1 | /* |
2 | * Copyright 2022 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included in |
12 | * all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * |
22 | */ |
23 | #ifndef _gc_11_0_3_SH_MASK_HEADER |
24 | #define |
25 | |
26 | |
27 | // addressBlock: gc_sdma0_sdma0dec |
28 | //SDMA0_DEC_START |
29 | #define SDMA0_DEC_START__START__SHIFT 0x0 |
30 | #define SDMA0_DEC_START__START_MASK 0xFFFFFFFFL |
31 | //SDMA0_F32_MISC_CNTL |
32 | #define SDMA0_F32_MISC_CNTL__F32_WAKEUP__SHIFT 0x0 |
33 | #define SDMA0_F32_MISC_CNTL__F32_WAKEUP_MASK 0x00000001L |
34 | //SDMA0_GLOBAL_TIMESTAMP_LO |
35 | #define SDMA0_GLOBAL_TIMESTAMP_LO__DATA__SHIFT 0x0 |
36 | #define SDMA0_GLOBAL_TIMESTAMP_LO__DATA_MASK 0xFFFFFFFFL |
37 | //SDMA0_GLOBAL_TIMESTAMP_HI |
38 | #define SDMA0_GLOBAL_TIMESTAMP_HI__DATA__SHIFT 0x0 |
39 | #define SDMA0_GLOBAL_TIMESTAMP_HI__DATA_MASK 0xFFFFFFFFL |
40 | //SDMA0_POWER_CNTL |
41 | #define SDMA0_POWER_CNTL__LS_ENABLE__SHIFT 0x8 |
42 | #define SDMA0_POWER_CNTL__LS_ENABLE_MASK 0x00000100L |
43 | //SDMA0_CNTL |
44 | #define SDMA0_CNTL__TRAP_ENABLE__SHIFT 0x0 |
45 | #define SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 |
46 | #define SDMA0_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 |
47 | #define SDMA0_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 |
48 | #define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5 |
49 | #define SDMA0_CNTL__PIO_DONE_ACK_ENABLE__SHIFT 0x6 |
50 | #define SDMA0_CNTL__TMZ_MIDCMD_PREEMPT_ENABLE__SHIFT 0x8 |
51 | #define SDMA0_CNTL__MIDCMD_EXPIRE_ENABLE__SHIFT 0x9 |
52 | #define SDMA0_CNTL__CP_MES_INT_ENABLE__SHIFT 0xa |
53 | #define SDMA0_CNTL__PAGE_RETRY_TIMEOUT_INT_ENABLE__SHIFT 0xb |
54 | #define SDMA0_CNTL__PAGE_NULL_INT_ENABLE__SHIFT 0xc |
55 | #define SDMA0_CNTL__PAGE_FAULT_INT_ENABLE__SHIFT 0xd |
56 | #define SDMA0_CNTL__CH_PERFCNT_ENABLE__SHIFT 0x10 |
57 | #define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 |
58 | #define SDMA0_CNTL__DRM_RESTORE_ENABLE__SHIFT 0x13 |
59 | #define SDMA0_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c |
60 | #define SDMA0_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d |
61 | #define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e |
62 | #define SDMA0_CNTL__RB_PREEMPT_INT_ENABLE__SHIFT 0x1f |
63 | #define SDMA0_CNTL__TRAP_ENABLE_MASK 0x00000001L |
64 | #define SDMA0_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L |
65 | #define SDMA0_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L |
66 | #define SDMA0_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L |
67 | #define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L |
68 | #define SDMA0_CNTL__PIO_DONE_ACK_ENABLE_MASK 0x00000040L |
69 | #define SDMA0_CNTL__TMZ_MIDCMD_PREEMPT_ENABLE_MASK 0x00000100L |
70 | #define SDMA0_CNTL__MIDCMD_EXPIRE_ENABLE_MASK 0x00000200L |
71 | #define SDMA0_CNTL__CP_MES_INT_ENABLE_MASK 0x00000400L |
72 | #define SDMA0_CNTL__PAGE_RETRY_TIMEOUT_INT_ENABLE_MASK 0x00000800L |
73 | #define SDMA0_CNTL__PAGE_NULL_INT_ENABLE_MASK 0x00001000L |
74 | #define SDMA0_CNTL__PAGE_FAULT_INT_ENABLE_MASK 0x00002000L |
75 | #define SDMA0_CNTL__CH_PERFCNT_ENABLE_MASK 0x00010000L |
76 | #define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L |
77 | #define SDMA0_CNTL__DRM_RESTORE_ENABLE_MASK 0x00080000L |
78 | #define SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L |
79 | #define SDMA0_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L |
80 | #define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L |
81 | #define SDMA0_CNTL__RB_PREEMPT_INT_ENABLE_MASK 0x80000000L |
82 | //SDMA0_CHICKEN_BITS |
83 | #define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1 |
84 | #define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2 |
85 | #define SDMA0_CHICKEN_BITS__BACK_COMPAT_ENABLE__SHIFT 0x3 |
86 | #define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x5 |
87 | #define SDMA0_CHICKEN_BITS__RD_BURST__SHIFT 0x6 |
88 | #define SDMA0_CHICKEN_BITS__WR_BURST__SHIFT 0x8 |
89 | #define SDMA0_CHICKEN_BITS__COMBINE_256B_WAIT_CYCLE__SHIFT 0xa |
90 | #define SDMA0_CHICKEN_BITS__WR_COMBINE_256B_ENABLE__SHIFT 0xe |
91 | #define SDMA0_CHICKEN_BITS__RD_COMBINE_256B_ENABLE__SHIFT 0xf |
92 | #define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10 |
93 | #define SDMA0_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x11 |
94 | #define SDMA0_CHICKEN_BITS__T2L_256B_ENABLE__SHIFT 0x12 |
95 | #define SDMA0_CHICKEN_BITS__SOFT_OVERRIDE_GCR_FGCG__SHIFT 0x13 |
96 | #define SDMA0_CHICKEN_BITS__SOFT_OVERRIDE_GRBM_FGCG__SHIFT 0x14 |
97 | #define SDMA0_CHICKEN_BITS__SOFT_OVERRIDE_CH_FGCG__SHIFT 0x15 |
98 | #define SDMA0_CHICKEN_BITS__SOFT_OVERRIDE_UTCL2_INVREQ_FGCG__SHIFT 0x16 |
99 | #define SDMA0_CHICKEN_BITS__SOFT_OVERRIDE_UTCL1_FGCG__SHIFT 0x17 |
100 | #define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x18 |
101 | #define SDMA0_CHICKEN_BITS__SW_FREEZE_ENABLE__SHIFT 0x19 |
102 | #define SDMA0_CHICKEN_BITS__DRAM_ECC_COPY_MODE_CNTL__SHIFT 0x1a |
103 | #define SDMA0_CHICKEN_BITS__RESERVED__SHIFT 0x1b |
104 | #define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L |
105 | #define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L |
106 | #define SDMA0_CHICKEN_BITS__BACK_COMPAT_ENABLE_MASK 0x00000008L |
107 | #define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00000020L |
108 | #define SDMA0_CHICKEN_BITS__RD_BURST_MASK 0x000000C0L |
109 | #define SDMA0_CHICKEN_BITS__WR_BURST_MASK 0x00000300L |
110 | #define SDMA0_CHICKEN_BITS__COMBINE_256B_WAIT_CYCLE_MASK 0x00003C00L |
111 | #define SDMA0_CHICKEN_BITS__WR_COMBINE_256B_ENABLE_MASK 0x00004000L |
112 | #define SDMA0_CHICKEN_BITS__RD_COMBINE_256B_ENABLE_MASK 0x00008000L |
113 | #define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L |
114 | #define SDMA0_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L |
115 | #define SDMA0_CHICKEN_BITS__T2L_256B_ENABLE_MASK 0x00040000L |
116 | #define SDMA0_CHICKEN_BITS__SOFT_OVERRIDE_GCR_FGCG_MASK 0x00080000L |
117 | #define SDMA0_CHICKEN_BITS__SOFT_OVERRIDE_GRBM_FGCG_MASK 0x00100000L |
118 | #define SDMA0_CHICKEN_BITS__SOFT_OVERRIDE_CH_FGCG_MASK 0x00200000L |
119 | #define SDMA0_CHICKEN_BITS__SOFT_OVERRIDE_UTCL2_INVREQ_FGCG_MASK 0x00400000L |
120 | #define SDMA0_CHICKEN_BITS__SOFT_OVERRIDE_UTCL1_FGCG_MASK 0x00800000L |
121 | #define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x01000000L |
122 | #define SDMA0_CHICKEN_BITS__SW_FREEZE_ENABLE_MASK 0x02000000L |
123 | #define SDMA0_CHICKEN_BITS__DRAM_ECC_COPY_MODE_CNTL_MASK 0x04000000L |
124 | #define SDMA0_CHICKEN_BITS__RESERVED_MASK 0xF8000000L |
125 | //SDMA0_GB_ADDR_CONFIG |
126 | #define SDMA0_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 |
127 | #define SDMA0_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 |
128 | #define SDMA0_GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0x6 |
129 | #define SDMA0_GB_ADDR_CONFIG__NUM_PKRS__SHIFT 0x8 |
130 | #define SDMA0_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 |
131 | #define SDMA0_GB_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT 0x1a |
132 | #define SDMA0_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L |
133 | #define SDMA0_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L |
134 | #define SDMA0_GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L |
135 | #define SDMA0_GB_ADDR_CONFIG__NUM_PKRS_MASK 0x00000700L |
136 | #define SDMA0_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L |
137 | #define SDMA0_GB_ADDR_CONFIG__NUM_RB_PER_SE_MASK 0x0C000000L |
138 | //SDMA0_GB_ADDR_CONFIG_READ |
139 | #define SDMA0_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0 |
140 | #define SDMA0_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 |
141 | #define SDMA0_GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS__SHIFT 0x6 |
142 | #define SDMA0_GB_ADDR_CONFIG_READ__NUM_PKRS__SHIFT 0x8 |
143 | #define SDMA0_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13 |
144 | #define SDMA0_GB_ADDR_CONFIG_READ__NUM_RB_PER_SE__SHIFT 0x1a |
145 | #define SDMA0_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L |
146 | #define SDMA0_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L |
147 | #define SDMA0_GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L |
148 | #define SDMA0_GB_ADDR_CONFIG_READ__NUM_PKRS_MASK 0x00000700L |
149 | #define SDMA0_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L |
150 | #define SDMA0_GB_ADDR_CONFIG_READ__NUM_RB_PER_SE_MASK 0x0C000000L |
151 | //SDMA0_RB_RPTR_FETCH |
152 | #define SDMA0_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 |
153 | #define SDMA0_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL |
154 | //SDMA0_RB_RPTR_FETCH_HI |
155 | #define SDMA0_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0 |
156 | #define SDMA0_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL |
157 | //SDMA0_SEM_WAIT_FAIL_TIMER_CNTL |
158 | #define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0 |
159 | #define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xFFFFFFFFL |
160 | //SDMA0_IB_OFFSET_FETCH |
161 | #define SDMA0_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 |
162 | #define SDMA0_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL |
163 | //SDMA0_PROGRAM |
164 | #define SDMA0_PROGRAM__STREAM__SHIFT 0x0 |
165 | #define SDMA0_PROGRAM__STREAM_MASK 0xFFFFFFFFL |
166 | //SDMA0_STATUS_REG |
167 | #define SDMA0_STATUS_REG__IDLE__SHIFT 0x0 |
168 | #define SDMA0_STATUS_REG__REG_IDLE__SHIFT 0x1 |
169 | #define SDMA0_STATUS_REG__RB_EMPTY__SHIFT 0x2 |
170 | #define SDMA0_STATUS_REG__RB_FULL__SHIFT 0x3 |
171 | #define SDMA0_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 |
172 | #define SDMA0_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 |
173 | #define SDMA0_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 |
174 | #define SDMA0_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 |
175 | #define SDMA0_STATUS_REG__BLOCK_IDLE__SHIFT 0x8 |
176 | #define SDMA0_STATUS_REG__INSIDE_IB__SHIFT 0x9 |
177 | #define SDMA0_STATUS_REG__EX_IDLE__SHIFT 0xa |
178 | #define SDMA0_STATUS_REG__CGCG_FENCE__SHIFT 0xb |
179 | #define SDMA0_STATUS_REG__PACKET_READY__SHIFT 0xc |
180 | #define SDMA0_STATUS_REG__MC_WR_IDLE__SHIFT 0xd |
181 | #define SDMA0_STATUS_REG__SRBM_IDLE__SHIFT 0xe |
182 | #define SDMA0_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf |
183 | #define SDMA0_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10 |
184 | #define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 |
185 | #define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 |
186 | #define SDMA0_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 |
187 | #define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14 |
188 | #define SDMA0_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15 |
189 | #define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 |
190 | #define SDMA0_STATUS_REG__DRM_IDLE__SHIFT 0x17 |
191 | #define SDMA0_STATUS_REG__DRM_MASK_FULL__SHIFT 0x18 |
192 | #define SDMA0_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19 |
193 | #define SDMA0_STATUS_REG__SEM_IDLE__SHIFT 0x1a |
194 | #define SDMA0_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b |
195 | #define SDMA0_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c |
196 | #define SDMA0_STATUS_REG__INT_IDLE__SHIFT 0x1e |
197 | #define SDMA0_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f |
198 | #define SDMA0_STATUS_REG__IDLE_MASK 0x00000001L |
199 | #define SDMA0_STATUS_REG__REG_IDLE_MASK 0x00000002L |
200 | #define SDMA0_STATUS_REG__RB_EMPTY_MASK 0x00000004L |
201 | #define SDMA0_STATUS_REG__RB_FULL_MASK 0x00000008L |
202 | #define SDMA0_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L |
203 | #define SDMA0_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L |
204 | #define SDMA0_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L |
205 | #define SDMA0_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L |
206 | #define SDMA0_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L |
207 | #define SDMA0_STATUS_REG__INSIDE_IB_MASK 0x00000200L |
208 | #define SDMA0_STATUS_REG__EX_IDLE_MASK 0x00000400L |
209 | #define SDMA0_STATUS_REG__CGCG_FENCE_MASK 0x00000800L |
210 | #define SDMA0_STATUS_REG__PACKET_READY_MASK 0x00001000L |
211 | #define SDMA0_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L |
212 | #define SDMA0_STATUS_REG__SRBM_IDLE_MASK 0x00004000L |
213 | #define SDMA0_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L |
214 | #define SDMA0_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L |
215 | #define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L |
216 | #define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L |
217 | #define SDMA0_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L |
218 | #define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L |
219 | #define SDMA0_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L |
220 | #define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L |
221 | #define SDMA0_STATUS_REG__DRM_IDLE_MASK 0x00800000L |
222 | #define SDMA0_STATUS_REG__DRM_MASK_FULL_MASK 0x01000000L |
223 | #define SDMA0_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L |
224 | #define SDMA0_STATUS_REG__SEM_IDLE_MASK 0x04000000L |
225 | #define SDMA0_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L |
226 | #define SDMA0_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L |
227 | #define SDMA0_STATUS_REG__INT_IDLE_MASK 0x40000000L |
228 | #define SDMA0_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L |
229 | //SDMA0_STATUS1_REG |
230 | #define SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 |
231 | #define SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 |
232 | #define SDMA0_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2 |
233 | #define SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 |
234 | #define SDMA0_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 |
235 | #define SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 |
236 | #define SDMA0_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 |
237 | #define SDMA0_STATUS1_REG__CE_DRM_IDLE__SHIFT 0x7 |
238 | #define SDMA0_STATUS1_REG__CE_DRM1_IDLE__SHIFT 0x8 |
239 | #define SDMA0_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9 |
240 | #define SDMA0_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa |
241 | #define SDMA0_STATUS1_REG__CE_INFO_FULL__SHIFT 0xb |
242 | #define SDMA0_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xc |
243 | #define SDMA0_STATUS1_REG__EX_START__SHIFT 0xd |
244 | #define SDMA0_STATUS1_REG__DRM_CTX_RESTORE__SHIFT 0xe |
245 | #define SDMA0_STATUS1_REG__CE_RD_STALL__SHIFT 0xf |
246 | #define SDMA0_STATUS1_REG__CE_WR_STALL__SHIFT 0x10 |
247 | #define SDMA0_STATUS1_REG__SEC_INTR_STATUS__SHIFT 0x11 |
248 | #define SDMA0_STATUS1_REG__WPTR_POLL_IDLE__SHIFT 0x12 |
249 | #define SDMA0_STATUS1_REG__SDMA_IDLE__SHIFT 0x13 |
250 | #define SDMA0_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L |
251 | #define SDMA0_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L |
252 | #define SDMA0_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L |
253 | #define SDMA0_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L |
254 | #define SDMA0_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L |
255 | #define SDMA0_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L |
256 | #define SDMA0_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L |
257 | #define SDMA0_STATUS1_REG__CE_DRM_IDLE_MASK 0x00000080L |
258 | #define SDMA0_STATUS1_REG__CE_DRM1_IDLE_MASK 0x00000100L |
259 | #define SDMA0_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L |
260 | #define SDMA0_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L |
261 | #define SDMA0_STATUS1_REG__CE_INFO_FULL_MASK 0x00000800L |
262 | #define SDMA0_STATUS1_REG__CE_INFO1_FULL_MASK 0x00001000L |
263 | #define SDMA0_STATUS1_REG__EX_START_MASK 0x00002000L |
264 | #define SDMA0_STATUS1_REG__DRM_CTX_RESTORE_MASK 0x00004000L |
265 | #define SDMA0_STATUS1_REG__CE_RD_STALL_MASK 0x00008000L |
266 | #define SDMA0_STATUS1_REG__CE_WR_STALL_MASK 0x00010000L |
267 | #define SDMA0_STATUS1_REG__SEC_INTR_STATUS_MASK 0x00020000L |
268 | #define SDMA0_STATUS1_REG__WPTR_POLL_IDLE_MASK 0x00040000L |
269 | #define SDMA0_STATUS1_REG__SDMA_IDLE_MASK 0x00080000L |
270 | //SDMA0_CNTL1 |
271 | #define SDMA0_CNTL1__WPTR_POLL_FREQUENCY__SHIFT 0x2 |
272 | #define SDMA0_CNTL1__WPTR_POLL_FREQUENCY_MASK 0x0000FFFCL |
273 | //SDMA0_HBM_PAGE_CONFIG |
274 | #define SDMA0_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0 |
275 | #define SDMA0_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000003L |
276 | //SDMA0_UCODE_CHECKSUM |
277 | #define SDMA0_UCODE_CHECKSUM__DATA__SHIFT 0x0 |
278 | #define SDMA0_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL |
279 | //SDMA0_FREEZE |
280 | #define SDMA0_FREEZE__PREEMPT__SHIFT 0x0 |
281 | #define SDMA0_FREEZE__FREEZE__SHIFT 0x4 |
282 | #define SDMA0_FREEZE__FROZEN__SHIFT 0x5 |
283 | #define SDMA0_FREEZE__F32_FREEZE__SHIFT 0x6 |
284 | #define SDMA0_FREEZE__PREEMPT_MASK 0x00000001L |
285 | #define SDMA0_FREEZE__FREEZE_MASK 0x00000010L |
286 | #define SDMA0_FREEZE__FROZEN_MASK 0x00000020L |
287 | #define SDMA0_FREEZE__F32_FREEZE_MASK 0x00000040L |
288 | //SDMA0_PROCESS_QUANTUM0 |
289 | #define SDMA0_PROCESS_QUANTUM0__PROCESS0_QUANTUM__SHIFT 0x0 |
290 | #define SDMA0_PROCESS_QUANTUM0__PROCESS1_QUANTUM__SHIFT 0x8 |
291 | #define SDMA0_PROCESS_QUANTUM0__PROCESS2_QUANTUM__SHIFT 0x10 |
292 | #define SDMA0_PROCESS_QUANTUM0__PROCESS3_QUANTUM__SHIFT 0x18 |
293 | #define SDMA0_PROCESS_QUANTUM0__PROCESS0_QUANTUM_MASK 0x000000FFL |
294 | #define SDMA0_PROCESS_QUANTUM0__PROCESS1_QUANTUM_MASK 0x0000FF00L |
295 | #define SDMA0_PROCESS_QUANTUM0__PROCESS2_QUANTUM_MASK 0x00FF0000L |
296 | #define SDMA0_PROCESS_QUANTUM0__PROCESS3_QUANTUM_MASK 0xFF000000L |
297 | //SDMA0_PROCESS_QUANTUM1 |
298 | #define SDMA0_PROCESS_QUANTUM1__PROCESS4_QUANTUM__SHIFT 0x0 |
299 | #define SDMA0_PROCESS_QUANTUM1__PROCESS5_QUANTUM__SHIFT 0x8 |
300 | #define SDMA0_PROCESS_QUANTUM1__PROCESS6_QUANTUM__SHIFT 0x10 |
301 | #define SDMA0_PROCESS_QUANTUM1__PROCESS7_QUANTUM__SHIFT 0x18 |
302 | #define SDMA0_PROCESS_QUANTUM1__PROCESS4_QUANTUM_MASK 0x000000FFL |
303 | #define SDMA0_PROCESS_QUANTUM1__PROCESS5_QUANTUM_MASK 0x0000FF00L |
304 | #define SDMA0_PROCESS_QUANTUM1__PROCESS6_QUANTUM_MASK 0x00FF0000L |
305 | #define SDMA0_PROCESS_QUANTUM1__PROCESS7_QUANTUM_MASK 0xFF000000L |
306 | //SDMA0_WATCHDOG_CNTL |
307 | #define SDMA0_WATCHDOG_CNTL__QUEUE_HANG_COUNT__SHIFT 0x0 |
308 | #define SDMA0_WATCHDOG_CNTL__CMD_TIMEOUT_COUNT__SHIFT 0x8 |
309 | #define SDMA0_WATCHDOG_CNTL__QUEUE_HANG_COUNT_MASK 0x000000FFL |
310 | #define SDMA0_WATCHDOG_CNTL__CMD_TIMEOUT_COUNT_MASK 0x0000FF00L |
311 | //SDMA0_QUEUE_STATUS0 |
312 | #define SDMA0_QUEUE_STATUS0__QUEUE0_STATUS__SHIFT 0x0 |
313 | #define SDMA0_QUEUE_STATUS0__QUEUE1_STATUS__SHIFT 0x4 |
314 | #define SDMA0_QUEUE_STATUS0__QUEUE2_STATUS__SHIFT 0x8 |
315 | #define SDMA0_QUEUE_STATUS0__QUEUE3_STATUS__SHIFT 0xc |
316 | #define SDMA0_QUEUE_STATUS0__QUEUE4_STATUS__SHIFT 0x10 |
317 | #define SDMA0_QUEUE_STATUS0__QUEUE5_STATUS__SHIFT 0x14 |
318 | #define SDMA0_QUEUE_STATUS0__QUEUE6_STATUS__SHIFT 0x18 |
319 | #define SDMA0_QUEUE_STATUS0__QUEUE7_STATUS__SHIFT 0x1c |
320 | #define SDMA0_QUEUE_STATUS0__QUEUE0_STATUS_MASK 0x0000000FL |
321 | #define SDMA0_QUEUE_STATUS0__QUEUE1_STATUS_MASK 0x000000F0L |
322 | #define SDMA0_QUEUE_STATUS0__QUEUE2_STATUS_MASK 0x00000F00L |
323 | #define SDMA0_QUEUE_STATUS0__QUEUE3_STATUS_MASK 0x0000F000L |
324 | #define SDMA0_QUEUE_STATUS0__QUEUE4_STATUS_MASK 0x000F0000L |
325 | #define SDMA0_QUEUE_STATUS0__QUEUE5_STATUS_MASK 0x00F00000L |
326 | #define SDMA0_QUEUE_STATUS0__QUEUE6_STATUS_MASK 0x0F000000L |
327 | #define SDMA0_QUEUE_STATUS0__QUEUE7_STATUS_MASK 0xF0000000L |
328 | //SDMA0_EDC_CONFIG |
329 | #define SDMA0_EDC_CONFIG__WRITE_DIS__SHIFT 0x0 |
330 | #define SDMA0_EDC_CONFIG__DIS_EDC__SHIFT 0x1 |
331 | #define SDMA0_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2 |
332 | #define SDMA0_EDC_CONFIG__WRITE_DIS_MASK 0x00000001L |
333 | #define SDMA0_EDC_CONFIG__DIS_EDC_MASK 0x00000002L |
334 | #define SDMA0_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x00000004L |
335 | //SDMA0_BA_THRESHOLD |
336 | #define SDMA0_BA_THRESHOLD__READ_THRES__SHIFT 0x0 |
337 | #define SDMA0_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10 |
338 | #define SDMA0_BA_THRESHOLD__READ_THRES_MASK 0x000003FFL |
339 | #define SDMA0_BA_THRESHOLD__WRITE_THRES_MASK 0x03FF0000L |
340 | //SDMA0_ID |
341 | #define SDMA0_ID__DEVICE_ID__SHIFT 0x0 |
342 | #define SDMA0_ID__DEVICE_ID_MASK 0x000000FFL |
343 | //SDMA0_VERSION |
344 | #define SDMA0_VERSION__MINVER__SHIFT 0x0 |
345 | #define SDMA0_VERSION__MAJVER__SHIFT 0x8 |
346 | #define SDMA0_VERSION__REV__SHIFT 0x10 |
347 | #define SDMA0_VERSION__MINVER_MASK 0x0000007FL |
348 | #define SDMA0_VERSION__MAJVER_MASK 0x00007F00L |
349 | #define SDMA0_VERSION__REV_MASK 0x003F0000L |
350 | //SDMA0_EDC_COUNTER |
351 | #define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_DED__SHIFT 0x0 |
352 | #define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_SEC__SHIFT 0x1 |
353 | #define SDMA0_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT 0x2 |
354 | #define SDMA0_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT 0x3 |
355 | #define SDMA0_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT 0x4 |
356 | #define SDMA0_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x5 |
357 | #define SDMA0_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT 0x6 |
358 | #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT 0x7 |
359 | #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT 0x8 |
360 | #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT 0x9 |
361 | #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0xa |
362 | #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT 0xb |
363 | #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xc |
364 | #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT 0xd |
365 | #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT 0xe |
366 | #define SDMA0_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT 0xf |
367 | #define SDMA0_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x10 |
368 | #define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_DED_MASK 0x00000001L |
369 | #define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_SEC_MASK 0x00000002L |
370 | #define SDMA0_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK 0x00000004L |
371 | #define SDMA0_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK 0x00000008L |
372 | #define SDMA0_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK 0x00000010L |
373 | #define SDMA0_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000020L |
374 | #define SDMA0_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK 0x00000040L |
375 | #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK 0x00000080L |
376 | #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK 0x00000100L |
377 | #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK 0x00000200L |
378 | #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK 0x00000400L |
379 | #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK 0x00000800L |
380 | #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK 0x00001000L |
381 | #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK 0x00002000L |
382 | #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK 0x00004000L |
383 | #define SDMA0_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK 0x00008000L |
384 | #define SDMA0_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK 0x00010000L |
385 | //SDMA0_EDC_COUNTER_CLEAR |
386 | #define SDMA0_EDC_COUNTER_CLEAR__DUMMY__SHIFT 0x0 |
387 | #define SDMA0_EDC_COUNTER_CLEAR__DUMMY_MASK 0x00000001L |
388 | //SDMA0_STATUS2_REG |
389 | #define SDMA0_STATUS2_REG__ID__SHIFT 0x0 |
390 | #define SDMA0_STATUS2_REG__TH0F32_INSTR_PTR__SHIFT 0x2 |
391 | #define SDMA0_STATUS2_REG__CMD_OP__SHIFT 0x10 |
392 | #define SDMA0_STATUS2_REG__ID_MASK 0x00000003L |
393 | #define SDMA0_STATUS2_REG__TH0F32_INSTR_PTR_MASK 0x0000FFFCL |
394 | #define SDMA0_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L |
395 | //SDMA0_ATOMIC_CNTL |
396 | #define SDMA0_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 |
397 | #define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f |
398 | #define SDMA0_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL |
399 | #define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L |
400 | //SDMA0_ATOMIC_PREOP_LO |
401 | #define SDMA0_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 |
402 | #define SDMA0_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL |
403 | //SDMA0_ATOMIC_PREOP_HI |
404 | #define SDMA0_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 |
405 | #define SDMA0_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL |
406 | //SDMA0_UTCL1_CNTL |
407 | #define SDMA0_UTCL1_CNTL__REDO_DELAY__SHIFT 0x0 |
408 | #define SDMA0_UTCL1_CNTL__PAGE_WAIT_DELAY__SHIFT 0x5 |
409 | #define SDMA0_UTCL1_CNTL__RESP_MODE__SHIFT 0x9 |
410 | #define SDMA0_UTCL1_CNTL__FORCE_INVALIDATION__SHIFT 0xe |
411 | #define SDMA0_UTCL1_CNTL__FORCE_INVREQ_HEAVY__SHIFT 0xf |
412 | #define SDMA0_UTCL1_CNTL__WR_EXE_PERMS_CTRL__SHIFT 0x10 |
413 | #define SDMA0_UTCL1_CNTL__RD_EXE_PERMS_CTRL__SHIFT 0x11 |
414 | #define SDMA0_UTCL1_CNTL__INVACK_DELAY__SHIFT 0x12 |
415 | #define SDMA0_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x18 |
416 | #define SDMA0_UTCL1_CNTL__REDO_DELAY_MASK 0x0000001FL |
417 | #define SDMA0_UTCL1_CNTL__PAGE_WAIT_DELAY_MASK 0x000001E0L |
418 | #define SDMA0_UTCL1_CNTL__RESP_MODE_MASK 0x00000600L |
419 | #define SDMA0_UTCL1_CNTL__FORCE_INVALIDATION_MASK 0x00004000L |
420 | #define SDMA0_UTCL1_CNTL__FORCE_INVREQ_HEAVY_MASK 0x00008000L |
421 | #define SDMA0_UTCL1_CNTL__WR_EXE_PERMS_CTRL_MASK 0x00010000L |
422 | #define SDMA0_UTCL1_CNTL__RD_EXE_PERMS_CTRL_MASK 0x00020000L |
423 | #define SDMA0_UTCL1_CNTL__INVACK_DELAY_MASK 0x003C0000L |
424 | #define SDMA0_UTCL1_CNTL__REQL2_CREDIT_MASK 0x3F000000L |
425 | //SDMA0_UTCL1_WATERMK |
426 | #define SDMA0_UTCL1_WATERMK__WR_REQ_FIFO_WATERMK__SHIFT 0x0 |
427 | #define SDMA0_UTCL1_WATERMK__WR_REQ_FIFO_DEPTH_STEP__SHIFT 0x4 |
428 | #define SDMA0_UTCL1_WATERMK__RD_REQ_FIFO_WATERMK__SHIFT 0x6 |
429 | #define SDMA0_UTCL1_WATERMK__RD_REQ_FIFO_DEPTH_STEP__SHIFT 0xa |
430 | #define SDMA0_UTCL1_WATERMK__WR_PAGE_FIFO_WATERMK__SHIFT 0xc |
431 | #define SDMA0_UTCL1_WATERMK__WR_PAGE_FIFO_DEPTH_STEP__SHIFT 0x10 |
432 | #define SDMA0_UTCL1_WATERMK__RD_PAGE_FIFO_WATERMK__SHIFT 0x12 |
433 | #define SDMA0_UTCL1_WATERMK__RD_PAGE_FIFO_DEPTH_STEP__SHIFT 0x16 |
434 | #define SDMA0_UTCL1_WATERMK__WR_REQ_FIFO_WATERMK_MASK 0x0000000FL |
435 | #define SDMA0_UTCL1_WATERMK__WR_REQ_FIFO_DEPTH_STEP_MASK 0x00000030L |
436 | #define SDMA0_UTCL1_WATERMK__RD_REQ_FIFO_WATERMK_MASK 0x000003C0L |
437 | #define SDMA0_UTCL1_WATERMK__RD_REQ_FIFO_DEPTH_STEP_MASK 0x00000C00L |
438 | #define SDMA0_UTCL1_WATERMK__WR_PAGE_FIFO_WATERMK_MASK 0x0000F000L |
439 | #define SDMA0_UTCL1_WATERMK__WR_PAGE_FIFO_DEPTH_STEP_MASK 0x00030000L |
440 | #define SDMA0_UTCL1_WATERMK__RD_PAGE_FIFO_WATERMK_MASK 0x003C0000L |
441 | #define SDMA0_UTCL1_WATERMK__RD_PAGE_FIFO_DEPTH_STEP_MASK 0x00C00000L |
442 | //SDMA0_UTCL1_TIMEOUT |
443 | #define SDMA0_UTCL1_TIMEOUT__XNACK_LIMIT__SHIFT 0x0 |
444 | #define SDMA0_UTCL1_TIMEOUT__XNACK_LIMIT_MASK 0x0000FFFFL |
445 | //SDMA0_UTCL1_PAGE |
446 | #define SDMA0_UTCL1_PAGE__VM_HOLE__SHIFT 0x0 |
447 | #define SDMA0_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1 |
448 | #define SDMA0_UTCL1_PAGE__TMZ_ENABLE__SHIFT 0x5 |
449 | #define SDMA0_UTCL1_PAGE__USE_MTYPE__SHIFT 0x6 |
450 | #define SDMA0_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0xa |
451 | #define SDMA0_UTCL1_PAGE__USE_IO__SHIFT 0xb |
452 | #define SDMA0_UTCL1_PAGE__RD_L2_POLICY__SHIFT 0xc |
453 | #define SDMA0_UTCL1_PAGE__WR_L2_POLICY__SHIFT 0xe |
454 | #define SDMA0_UTCL1_PAGE__DMA_PAGE_SIZE__SHIFT 0x10 |
455 | #define SDMA0_UTCL1_PAGE__USE_BC__SHIFT 0x16 |
456 | #define SDMA0_UTCL1_PAGE__ADDR_IS_PA__SHIFT 0x17 |
457 | #define SDMA0_UTCL1_PAGE__LLC_NOALLOC__SHIFT 0x18 |
458 | #define SDMA0_UTCL1_PAGE__VM_HOLE_MASK 0x00000001L |
459 | #define SDMA0_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001EL |
460 | #define SDMA0_UTCL1_PAGE__TMZ_ENABLE_MASK 0x00000020L |
461 | #define SDMA0_UTCL1_PAGE__USE_MTYPE_MASK 0x000003C0L |
462 | #define SDMA0_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000400L |
463 | #define SDMA0_UTCL1_PAGE__USE_IO_MASK 0x00000800L |
464 | #define SDMA0_UTCL1_PAGE__RD_L2_POLICY_MASK 0x00003000L |
465 | #define SDMA0_UTCL1_PAGE__WR_L2_POLICY_MASK 0x0000C000L |
466 | #define SDMA0_UTCL1_PAGE__DMA_PAGE_SIZE_MASK 0x003F0000L |
467 | #define SDMA0_UTCL1_PAGE__USE_BC_MASK 0x00400000L |
468 | #define SDMA0_UTCL1_PAGE__ADDR_IS_PA_MASK 0x00800000L |
469 | #define SDMA0_UTCL1_PAGE__LLC_NOALLOC_MASK 0x01000000L |
470 | //SDMA0_UTCL1_RD_STATUS |
471 | #define SDMA0_UTCL1_RD_STATUS__RD_VA_FIFO_EMPTY__SHIFT 0x0 |
472 | #define SDMA0_UTCL1_RD_STATUS__RD_REG_ENTRY_EMPTY__SHIFT 0x1 |
473 | #define SDMA0_UTCL1_RD_STATUS__RD_PAGE_FIFO_EMPTY__SHIFT 0x2 |
474 | #define SDMA0_UTCL1_RD_STATUS__RD_REQ_FIFO_EMPTY__SHIFT 0x3 |
475 | #define SDMA0_UTCL1_RD_STATUS__RD_VA_REQ_FIFO_EMPTY__SHIFT 0x4 |
476 | #define SDMA0_UTCL1_RD_STATUS__RESERVED0__SHIFT 0x5 |
477 | #define SDMA0_UTCL1_RD_STATUS__RESERVED1__SHIFT 0x6 |
478 | #define SDMA0_UTCL1_RD_STATUS__META_Q_EMPTY__SHIFT 0x7 |
479 | #define SDMA0_UTCL1_RD_STATUS__RD_VA_FIFO_FULL__SHIFT 0x8 |
480 | #define SDMA0_UTCL1_RD_STATUS__RD_REG_ENTRY_FULL__SHIFT 0x9 |
481 | #define SDMA0_UTCL1_RD_STATUS__RD_PAGE_FIFO_FULL__SHIFT 0xa |
482 | #define SDMA0_UTCL1_RD_STATUS__RD_REQ_FIFO_FULL__SHIFT 0xb |
483 | #define SDMA0_UTCL1_RD_STATUS__RD_VA_REQ_FIFO_FULL__SHIFT 0xc |
484 | #define SDMA0_UTCL1_RD_STATUS__RESERVED2__SHIFT 0xd |
485 | #define SDMA0_UTCL1_RD_STATUS__RESERVED3__SHIFT 0xe |
486 | #define SDMA0_UTCL1_RD_STATUS__META_Q_FULL__SHIFT 0xf |
487 | #define SDMA0_UTCL1_RD_STATUS__RD_L2_INTF_IDLE__SHIFT 0x10 |
488 | #define SDMA0_UTCL1_RD_STATUS__RD_REQRET_IDLE__SHIFT 0x11 |
489 | #define SDMA0_UTCL1_RD_STATUS__RD_REQ_IDLE__SHIFT 0x12 |
490 | #define SDMA0_UTCL1_RD_STATUS__RD_MERGE_TYPE__SHIFT 0x13 |
491 | #define SDMA0_UTCL1_RD_STATUS__RD_MERGE_DATA_PA_READY__SHIFT 0x15 |
492 | #define SDMA0_UTCL1_RD_STATUS__RD_MERGE_META_PA_READY__SHIFT 0x16 |
493 | #define SDMA0_UTCL1_RD_STATUS__RD_MERGE_REG_READY__SHIFT 0x17 |
494 | #define SDMA0_UTCL1_RD_STATUS__RD_MERGE_PAGE_FIFO_READY__SHIFT 0x18 |
495 | #define SDMA0_UTCL1_RD_STATUS__RD_MERGE_REQ_FIFO_READY__SHIFT 0x19 |
496 | #define SDMA0_UTCL1_RD_STATUS__RESERVED4__SHIFT 0x1a |
497 | #define SDMA0_UTCL1_RD_STATUS__RD_MERGE_OUT_RTR__SHIFT 0x1b |
498 | #define SDMA0_UTCL1_RD_STATUS__RDREQ_IN_RTR__SHIFT 0x1c |
499 | #define SDMA0_UTCL1_RD_STATUS__RDREQ_OUT_RTR__SHIFT 0x1d |
500 | #define SDMA0_UTCL1_RD_STATUS__INV_BUSY__SHIFT 0x1e |
501 | #define SDMA0_UTCL1_RD_STATUS__DBIT_REQ_IDLE__SHIFT 0x1f |
502 | #define SDMA0_UTCL1_RD_STATUS__RD_VA_FIFO_EMPTY_MASK 0x00000001L |
503 | #define SDMA0_UTCL1_RD_STATUS__RD_REG_ENTRY_EMPTY_MASK 0x00000002L |
504 | #define SDMA0_UTCL1_RD_STATUS__RD_PAGE_FIFO_EMPTY_MASK 0x00000004L |
505 | #define SDMA0_UTCL1_RD_STATUS__RD_REQ_FIFO_EMPTY_MASK 0x00000008L |
506 | #define SDMA0_UTCL1_RD_STATUS__RD_VA_REQ_FIFO_EMPTY_MASK 0x00000010L |
507 | #define SDMA0_UTCL1_RD_STATUS__RESERVED0_MASK 0x00000020L |
508 | #define SDMA0_UTCL1_RD_STATUS__RESERVED1_MASK 0x00000040L |
509 | #define SDMA0_UTCL1_RD_STATUS__META_Q_EMPTY_MASK 0x00000080L |
510 | #define SDMA0_UTCL1_RD_STATUS__RD_VA_FIFO_FULL_MASK 0x00000100L |
511 | #define SDMA0_UTCL1_RD_STATUS__RD_REG_ENTRY_FULL_MASK 0x00000200L |
512 | #define SDMA0_UTCL1_RD_STATUS__RD_PAGE_FIFO_FULL_MASK 0x00000400L |
513 | #define SDMA0_UTCL1_RD_STATUS__RD_REQ_FIFO_FULL_MASK 0x00000800L |
514 | #define SDMA0_UTCL1_RD_STATUS__RD_VA_REQ_FIFO_FULL_MASK 0x00001000L |
515 | #define SDMA0_UTCL1_RD_STATUS__RESERVED2_MASK 0x00002000L |
516 | #define SDMA0_UTCL1_RD_STATUS__RESERVED3_MASK 0x00004000L |
517 | #define SDMA0_UTCL1_RD_STATUS__META_Q_FULL_MASK 0x00008000L |
518 | #define SDMA0_UTCL1_RD_STATUS__RD_L2_INTF_IDLE_MASK 0x00010000L |
519 | #define SDMA0_UTCL1_RD_STATUS__RD_REQRET_IDLE_MASK 0x00020000L |
520 | #define SDMA0_UTCL1_RD_STATUS__RD_REQ_IDLE_MASK 0x00040000L |
521 | #define SDMA0_UTCL1_RD_STATUS__RD_MERGE_TYPE_MASK 0x00180000L |
522 | #define SDMA0_UTCL1_RD_STATUS__RD_MERGE_DATA_PA_READY_MASK 0x00200000L |
523 | #define SDMA0_UTCL1_RD_STATUS__RD_MERGE_META_PA_READY_MASK 0x00400000L |
524 | #define SDMA0_UTCL1_RD_STATUS__RD_MERGE_REG_READY_MASK 0x00800000L |
525 | #define SDMA0_UTCL1_RD_STATUS__RD_MERGE_PAGE_FIFO_READY_MASK 0x01000000L |
526 | #define SDMA0_UTCL1_RD_STATUS__RD_MERGE_REQ_FIFO_READY_MASK 0x02000000L |
527 | #define SDMA0_UTCL1_RD_STATUS__RESERVED4_MASK 0x04000000L |
528 | #define SDMA0_UTCL1_RD_STATUS__RD_MERGE_OUT_RTR_MASK 0x08000000L |
529 | #define SDMA0_UTCL1_RD_STATUS__RDREQ_IN_RTR_MASK 0x10000000L |
530 | #define SDMA0_UTCL1_RD_STATUS__RDREQ_OUT_RTR_MASK 0x20000000L |
531 | #define SDMA0_UTCL1_RD_STATUS__INV_BUSY_MASK 0x40000000L |
532 | #define SDMA0_UTCL1_RD_STATUS__DBIT_REQ_IDLE_MASK 0x80000000L |
533 | //SDMA0_UTCL1_WR_STATUS |
534 | #define SDMA0_UTCL1_WR_STATUS__WR_VA_FIFO_EMPTY__SHIFT 0x0 |
535 | #define SDMA0_UTCL1_WR_STATUS__WR_REG_ENTRY_EMPTY__SHIFT 0x1 |
536 | #define SDMA0_UTCL1_WR_STATUS__WR_PAGE_FIFO_EMPTY__SHIFT 0x2 |
537 | #define SDMA0_UTCL1_WR_STATUS__WR_REQ_FIFO_EMPTY__SHIFT 0x3 |
538 | #define SDMA0_UTCL1_WR_STATUS__WR_VA_REQ_FIFO_EMPTY__SHIFT 0x4 |
539 | #define SDMA0_UTCL1_WR_STATUS__WR_DATA2_EMPTY__SHIFT 0x5 |
540 | #define SDMA0_UTCL1_WR_STATUS__WR_DATA1_EMPTY__SHIFT 0x6 |
541 | #define SDMA0_UTCL1_WR_STATUS__RESERVED0__SHIFT 0x7 |
542 | #define SDMA0_UTCL1_WR_STATUS__WR_VA_FIFO_FULL__SHIFT 0x8 |
543 | #define SDMA0_UTCL1_WR_STATUS__WR_REG_ENTRY_FULL__SHIFT 0x9 |
544 | #define SDMA0_UTCL1_WR_STATUS__WR_PAGE_FIFO_FULL__SHIFT 0xa |
545 | #define SDMA0_UTCL1_WR_STATUS__WR_REQ_FIFO_FULL__SHIFT 0xb |
546 | #define SDMA0_UTCL1_WR_STATUS__WR_VA_REQ_FIFO_FULL__SHIFT 0xc |
547 | #define SDMA0_UTCL1_WR_STATUS__WR_DATA2_FULL__SHIFT 0xd |
548 | #define SDMA0_UTCL1_WR_STATUS__WR_DATA1_FULL__SHIFT 0xe |
549 | #define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0xf |
550 | #define SDMA0_UTCL1_WR_STATUS__WR_L2_INTF_IDLE__SHIFT 0x10 |
551 | #define SDMA0_UTCL1_WR_STATUS__WR_REQRET_IDLE__SHIFT 0x11 |
552 | #define SDMA0_UTCL1_WR_STATUS__WR_REQ_IDLE__SHIFT 0x12 |
553 | #define SDMA0_UTCL1_WR_STATUS__WR_MERGE_TYPE__SHIFT 0x13 |
554 | #define SDMA0_UTCL1_WR_STATUS__WR_MERGE_DATA_PA_READY__SHIFT 0x15 |
555 | #define SDMA0_UTCL1_WR_STATUS__WR_MERGE_META_PA_READY__SHIFT 0x16 |
556 | #define SDMA0_UTCL1_WR_STATUS__WR_MERGE_REG_READY__SHIFT 0x17 |
557 | #define SDMA0_UTCL1_WR_STATUS__WR_MERGE_PAGE_FIFO_READY__SHIFT 0x18 |
558 | #define SDMA0_UTCL1_WR_STATUS__WR_MERGE_REQ_FIFO_READY__SHIFT 0x19 |
559 | #define SDMA0_UTCL1_WR_STATUS__WR_MERGE_DATA_SEL__SHIFT 0x1a |
560 | #define SDMA0_UTCL1_WR_STATUS__WR_MERGE_OUT_RTR__SHIFT 0x1b |
561 | #define SDMA0_UTCL1_WR_STATUS__WRREQ_IN_RTR__SHIFT 0x1c |
562 | #define SDMA0_UTCL1_WR_STATUS__WRREQ_OUT_RTR__SHIFT 0x1d |
563 | #define SDMA0_UTCL1_WR_STATUS__WRREQ_IN_DATA1_RTR__SHIFT 0x1e |
564 | #define SDMA0_UTCL1_WR_STATUS__WRREQ_IN_DATA2_RTR__SHIFT 0x1f |
565 | #define SDMA0_UTCL1_WR_STATUS__WR_VA_FIFO_EMPTY_MASK 0x00000001L |
566 | #define SDMA0_UTCL1_WR_STATUS__WR_REG_ENTRY_EMPTY_MASK 0x00000002L |
567 | #define SDMA0_UTCL1_WR_STATUS__WR_PAGE_FIFO_EMPTY_MASK 0x00000004L |
568 | #define SDMA0_UTCL1_WR_STATUS__WR_REQ_FIFO_EMPTY_MASK 0x00000008L |
569 | #define SDMA0_UTCL1_WR_STATUS__WR_VA_REQ_FIFO_EMPTY_MASK 0x00000010L |
570 | #define SDMA0_UTCL1_WR_STATUS__WR_DATA2_EMPTY_MASK 0x00000020L |
571 | #define SDMA0_UTCL1_WR_STATUS__WR_DATA1_EMPTY_MASK 0x00000040L |
572 | #define SDMA0_UTCL1_WR_STATUS__RESERVED0_MASK 0x00000080L |
573 | #define SDMA0_UTCL1_WR_STATUS__WR_VA_FIFO_FULL_MASK 0x00000100L |
574 | #define SDMA0_UTCL1_WR_STATUS__WR_REG_ENTRY_FULL_MASK 0x00000200L |
575 | #define SDMA0_UTCL1_WR_STATUS__WR_PAGE_FIFO_FULL_MASK 0x00000400L |
576 | #define SDMA0_UTCL1_WR_STATUS__WR_REQ_FIFO_FULL_MASK 0x00000800L |
577 | #define SDMA0_UTCL1_WR_STATUS__WR_VA_REQ_FIFO_FULL_MASK 0x00001000L |
578 | #define SDMA0_UTCL1_WR_STATUS__WR_DATA2_FULL_MASK 0x00002000L |
579 | #define SDMA0_UTCL1_WR_STATUS__WR_DATA1_FULL_MASK 0x00004000L |
580 | #define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x00008000L |
581 | #define SDMA0_UTCL1_WR_STATUS__WR_L2_INTF_IDLE_MASK 0x00010000L |
582 | #define SDMA0_UTCL1_WR_STATUS__WR_REQRET_IDLE_MASK 0x00020000L |
583 | #define SDMA0_UTCL1_WR_STATUS__WR_REQ_IDLE_MASK 0x00040000L |
584 | #define SDMA0_UTCL1_WR_STATUS__WR_MERGE_TYPE_MASK 0x00180000L |
585 | #define SDMA0_UTCL1_WR_STATUS__WR_MERGE_DATA_PA_READY_MASK 0x00200000L |
586 | #define SDMA0_UTCL1_WR_STATUS__WR_MERGE_META_PA_READY_MASK 0x00400000L |
587 | #define SDMA0_UTCL1_WR_STATUS__WR_MERGE_REG_READY_MASK 0x00800000L |
588 | #define SDMA0_UTCL1_WR_STATUS__WR_MERGE_PAGE_FIFO_READY_MASK 0x01000000L |
589 | #define SDMA0_UTCL1_WR_STATUS__WR_MERGE_REQ_FIFO_READY_MASK 0x02000000L |
590 | #define SDMA0_UTCL1_WR_STATUS__WR_MERGE_DATA_SEL_MASK 0x04000000L |
591 | #define SDMA0_UTCL1_WR_STATUS__WR_MERGE_OUT_RTR_MASK 0x08000000L |
592 | #define SDMA0_UTCL1_WR_STATUS__WRREQ_IN_RTR_MASK 0x10000000L |
593 | #define SDMA0_UTCL1_WR_STATUS__WRREQ_OUT_RTR_MASK 0x20000000L |
594 | #define SDMA0_UTCL1_WR_STATUS__WRREQ_IN_DATA1_RTR_MASK 0x40000000L |
595 | #define SDMA0_UTCL1_WR_STATUS__WRREQ_IN_DATA2_RTR_MASK 0x80000000L |
596 | //SDMA0_UTCL1_INV0 |
597 | #define SDMA0_UTCL1_INV0__INV_PROC_BUSY__SHIFT 0x0 |
598 | #define SDMA0_UTCL1_INV0__GPUVM_FRAG_SIZE__SHIFT 0x1 |
599 | #define SDMA0_UTCL1_INV0__GPUVM_VMID__SHIFT 0x7 |
600 | #define SDMA0_UTCL1_INV0__GPUVM_MODE__SHIFT 0xb |
601 | #define SDMA0_UTCL1_INV0__GPUVM_HIGH__SHIFT 0xd |
602 | #define SDMA0_UTCL1_INV0__GPUVM_TAG__SHIFT 0xe |
603 | #define SDMA0_UTCL1_INV0__GPUVM_VMID_HIGH__SHIFT 0x12 |
604 | #define SDMA0_UTCL1_INV0__GPUVM_VMID_LOW__SHIFT 0x16 |
605 | #define SDMA0_UTCL1_INV0__INV_TYPE__SHIFT 0x1a |
606 | #define SDMA0_UTCL1_INV0__INV_PROC_BUSY_MASK 0x00000001L |
607 | #define SDMA0_UTCL1_INV0__GPUVM_FRAG_SIZE_MASK 0x0000007EL |
608 | #define SDMA0_UTCL1_INV0__GPUVM_VMID_MASK 0x00000780L |
609 | #define SDMA0_UTCL1_INV0__GPUVM_MODE_MASK 0x00001800L |
610 | #define SDMA0_UTCL1_INV0__GPUVM_HIGH_MASK 0x00002000L |
611 | #define SDMA0_UTCL1_INV0__GPUVM_TAG_MASK 0x0003C000L |
612 | #define SDMA0_UTCL1_INV0__GPUVM_VMID_HIGH_MASK 0x003C0000L |
613 | #define SDMA0_UTCL1_INV0__GPUVM_VMID_LOW_MASK 0x03C00000L |
614 | #define SDMA0_UTCL1_INV0__INV_TYPE_MASK 0x0C000000L |
615 | //SDMA0_UTCL1_INV1 |
616 | #define SDMA0_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0 |
617 | #define SDMA0_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL |
618 | //SDMA0_UTCL1_INV2 |
619 | #define SDMA0_UTCL1_INV2__CPF_VMID__SHIFT 0x0 |
620 | #define SDMA0_UTCL1_INV2__CPF_FLUSH_TYPE__SHIFT 0x10 |
621 | #define SDMA0_UTCL1_INV2__CPF_FRAG_SIZE__SHIFT 0x11 |
622 | #define SDMA0_UTCL1_INV2__CPF_VMID_MASK 0x0000FFFFL |
623 | #define SDMA0_UTCL1_INV2__CPF_FLUSH_TYPE_MASK 0x00010000L |
624 | #define SDMA0_UTCL1_INV2__CPF_FRAG_SIZE_MASK 0x007E0000L |
625 | //SDMA0_UTCL1_RD_XNACK0 |
626 | #define SDMA0_UTCL1_RD_XNACK0__XNACK_FAULT_ADDR_LO__SHIFT 0x0 |
627 | #define SDMA0_UTCL1_RD_XNACK0__XNACK_FAULT_ADDR_LO_MASK 0xFFFFFFFFL |
628 | //SDMA0_UTCL1_RD_XNACK1 |
629 | #define SDMA0_UTCL1_RD_XNACK1__XNACK_FAULT_ADDR_HI__SHIFT 0x0 |
630 | #define SDMA0_UTCL1_RD_XNACK1__XNACK_FAULT_VMID__SHIFT 0x4 |
631 | #define SDMA0_UTCL1_RD_XNACK1__XNACK_FAULT_VECTOR__SHIFT 0x8 |
632 | #define SDMA0_UTCL1_RD_XNACK1__XNACK_NULL_VECTOR__SHIFT 0xa |
633 | #define SDMA0_UTCL1_RD_XNACK1__XNACK_TIMEOUT_VECTOR__SHIFT 0xc |
634 | #define SDMA0_UTCL1_RD_XNACK1__XNACK_FAULT_FLAG__SHIFT 0xe |
635 | #define SDMA0_UTCL1_RD_XNACK1__XNACK_NULL_FLAG__SHIFT 0xf |
636 | #define SDMA0_UTCL1_RD_XNACK1__XNACK_TIMEOUT_FLAG__SHIFT 0x10 |
637 | #define SDMA0_UTCL1_RD_XNACK1__XNACK_FAULT_ADDR_HI_MASK 0x0000000FL |
638 | #define SDMA0_UTCL1_RD_XNACK1__XNACK_FAULT_VMID_MASK 0x000000F0L |
639 | #define SDMA0_UTCL1_RD_XNACK1__XNACK_FAULT_VECTOR_MASK 0x00000300L |
640 | #define SDMA0_UTCL1_RD_XNACK1__XNACK_NULL_VECTOR_MASK 0x00000C00L |
641 | #define SDMA0_UTCL1_RD_XNACK1__XNACK_TIMEOUT_VECTOR_MASK 0x00003000L |
642 | #define SDMA0_UTCL1_RD_XNACK1__XNACK_FAULT_FLAG_MASK 0x00004000L |
643 | #define SDMA0_UTCL1_RD_XNACK1__XNACK_NULL_FLAG_MASK 0x00008000L |
644 | #define SDMA0_UTCL1_RD_XNACK1__XNACK_TIMEOUT_FLAG_MASK 0x00010000L |
645 | //SDMA0_UTCL1_WR_XNACK0 |
646 | #define SDMA0_UTCL1_WR_XNACK0__XNACK_FAULT_ADDR_LO__SHIFT 0x0 |
647 | #define SDMA0_UTCL1_WR_XNACK0__XNACK_FAULT_ADDR_LO_MASK 0xFFFFFFFFL |
648 | //SDMA0_UTCL1_WR_XNACK1 |
649 | #define SDMA0_UTCL1_WR_XNACK1__XNACK_FAULT_ADDR_HI__SHIFT 0x0 |
650 | #define SDMA0_UTCL1_WR_XNACK1__XNACK_FAULT_VMID__SHIFT 0x4 |
651 | #define SDMA0_UTCL1_WR_XNACK1__XNACK_FAULT_VECTOR__SHIFT 0x8 |
652 | #define SDMA0_UTCL1_WR_XNACK1__XNACK_NULL_VECTOR__SHIFT 0xa |
653 | #define SDMA0_UTCL1_WR_XNACK1__XNACK_TIMEOUT_VECTOR__SHIFT 0xc |
654 | #define SDMA0_UTCL1_WR_XNACK1__XNACK_FAULT_FLAG__SHIFT 0xe |
655 | #define SDMA0_UTCL1_WR_XNACK1__XNACK_NULL_FLAG__SHIFT 0xf |
656 | #define SDMA0_UTCL1_WR_XNACK1__XNACK_TIMEOUT_FLAG__SHIFT 0x10 |
657 | #define SDMA0_UTCL1_WR_XNACK1__XNACK_FAULT_ADDR_HI_MASK 0x0000000FL |
658 | #define SDMA0_UTCL1_WR_XNACK1__XNACK_FAULT_VMID_MASK 0x000000F0L |
659 | #define SDMA0_UTCL1_WR_XNACK1__XNACK_FAULT_VECTOR_MASK 0x00000300L |
660 | #define SDMA0_UTCL1_WR_XNACK1__XNACK_NULL_VECTOR_MASK 0x00000C00L |
661 | #define SDMA0_UTCL1_WR_XNACK1__XNACK_TIMEOUT_VECTOR_MASK 0x00003000L |
662 | #define SDMA0_UTCL1_WR_XNACK1__XNACK_FAULT_FLAG_MASK 0x00004000L |
663 | #define SDMA0_UTCL1_WR_XNACK1__XNACK_NULL_FLAG_MASK 0x00008000L |
664 | #define SDMA0_UTCL1_WR_XNACK1__XNACK_TIMEOUT_FLAG_MASK 0x00010000L |
665 | //SDMA0_RELAX_ORDERING_LUT |
666 | #define SDMA0_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0 |
667 | #define SDMA0_RELAX_ORDERING_LUT__COPY__SHIFT 0x1 |
668 | #define SDMA0_RELAX_ORDERING_LUT__WRITE__SHIFT 0x2 |
669 | #define SDMA0_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3 |
670 | #define SDMA0_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4 |
671 | #define SDMA0_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5 |
672 | #define SDMA0_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6 |
673 | #define SDMA0_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8 |
674 | #define SDMA0_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9 |
675 | #define SDMA0_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa |
676 | #define SDMA0_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0xb |
677 | #define SDMA0_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0xc |
678 | #define SDMA0_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd |
679 | #define SDMA0_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe |
680 | #define SDMA0_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b |
681 | #define SDMA0_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c |
682 | #define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d |
683 | #define SDMA0_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e |
684 | #define SDMA0_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f |
685 | #define SDMA0_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L |
686 | #define SDMA0_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L |
687 | #define SDMA0_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L |
688 | #define SDMA0_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L |
689 | #define SDMA0_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L |
690 | #define SDMA0_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L |
691 | #define SDMA0_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L |
692 | #define SDMA0_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L |
693 | #define SDMA0_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L |
694 | #define SDMA0_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L |
695 | #define SDMA0_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L |
696 | #define SDMA0_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L |
697 | #define SDMA0_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L |
698 | #define SDMA0_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L |
699 | #define SDMA0_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L |
700 | #define SDMA0_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L |
701 | #define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L |
702 | #define SDMA0_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L |
703 | #define SDMA0_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L |
704 | //SDMA0_CHICKEN_BITS_2 |
705 | #define SDMA0_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x0 |
706 | #define SDMA0_CHICKEN_BITS_2__F32_SEND_POSTCODE_EN__SHIFT 0x4 |
707 | #define SDMA0_CHICKEN_BITS_2__UCODE_BUF_DS_EN__SHIFT 0x6 |
708 | #define SDMA0_CHICKEN_BITS_2__UCODE_SELFLOAD_THREAD_OVERLAP__SHIFT 0x7 |
709 | #define SDMA0_CHICKEN_BITS_2__WPTR_POLL_OUTSTANDING__SHIFT 0x8 |
710 | #define SDMA0_CHICKEN_BITS_2__RESERVED_14_12__SHIFT 0xc |
711 | #define SDMA0_CHICKEN_BITS_2__RESERVED_15__SHIFT 0xf |
712 | #define SDMA0_CHICKEN_BITS_2__RB_FIFO_WATERMARK__SHIFT 0x10 |
713 | #define SDMA0_CHICKEN_BITS_2__IB_FIFO_WATERMARK__SHIFT 0x12 |
714 | #define SDMA0_CHICKEN_BITS_2__RESERVED_22_20__SHIFT 0x14 |
715 | #define SDMA0_CHICKEN_BITS_2__CH_RD_WATERMARK__SHIFT 0x17 |
716 | #define SDMA0_CHICKEN_BITS_2__CH_WR_WATERMARK__SHIFT 0x19 |
717 | #define SDMA0_CHICKEN_BITS_2__CH_WR_WATERMARK_LSB__SHIFT 0x1e |
718 | #define SDMA0_CHICKEN_BITS_2__PIO_VFID_SOURCE__SHIFT 0x1f |
719 | #define SDMA0_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000FL |
720 | #define SDMA0_CHICKEN_BITS_2__F32_SEND_POSTCODE_EN_MASK 0x00000010L |
721 | #define SDMA0_CHICKEN_BITS_2__UCODE_BUF_DS_EN_MASK 0x00000040L |
722 | #define SDMA0_CHICKEN_BITS_2__UCODE_SELFLOAD_THREAD_OVERLAP_MASK 0x00000080L |
723 | #define SDMA0_CHICKEN_BITS_2__WPTR_POLL_OUTSTANDING_MASK 0x00000F00L |
724 | #define SDMA0_CHICKEN_BITS_2__RESERVED_14_12_MASK 0x00007000L |
725 | #define SDMA0_CHICKEN_BITS_2__RESERVED_15_MASK 0x00008000L |
726 | #define SDMA0_CHICKEN_BITS_2__RB_FIFO_WATERMARK_MASK 0x00030000L |
727 | #define SDMA0_CHICKEN_BITS_2__IB_FIFO_WATERMARK_MASK 0x000C0000L |
728 | #define SDMA0_CHICKEN_BITS_2__RESERVED_22_20_MASK 0x00700000L |
729 | #define SDMA0_CHICKEN_BITS_2__CH_RD_WATERMARK_MASK 0x01800000L |
730 | #define SDMA0_CHICKEN_BITS_2__CH_WR_WATERMARK_MASK 0x3E000000L |
731 | #define SDMA0_CHICKEN_BITS_2__CH_WR_WATERMARK_LSB_MASK 0x40000000L |
732 | #define SDMA0_CHICKEN_BITS_2__PIO_VFID_SOURCE_MASK 0x80000000L |
733 | //SDMA0_STATUS3_REG |
734 | #define SDMA0_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x0 |
735 | #define SDMA0_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10 |
736 | #define SDMA0_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14 |
737 | #define SDMA0_STATUS3_REG__AQL_PREV_CMD_IDLE__SHIFT 0x15 |
738 | #define SDMA0_STATUS3_REG__TLBI_IDLE__SHIFT 0x16 |
739 | #define SDMA0_STATUS3_REG__GCR_IDLE__SHIFT 0x17 |
740 | #define SDMA0_STATUS3_REG__INVREQ_IDLE__SHIFT 0x18 |
741 | #define SDMA0_STATUS3_REG__QUEUE_ID_MATCH__SHIFT 0x19 |
742 | #define SDMA0_STATUS3_REG__INT_QUEUE_ID__SHIFT 0x1a |
743 | #define SDMA0_STATUS3_REG__TMZ_MTYPE_STATUS__SHIFT 0x1e |
744 | #define SDMA0_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000FFFFL |
745 | #define SDMA0_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L |
746 | #define SDMA0_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L |
747 | #define SDMA0_STATUS3_REG__AQL_PREV_CMD_IDLE_MASK 0x00200000L |
748 | #define SDMA0_STATUS3_REG__TLBI_IDLE_MASK 0x00400000L |
749 | #define SDMA0_STATUS3_REG__GCR_IDLE_MASK 0x00800000L |
750 | #define SDMA0_STATUS3_REG__INVREQ_IDLE_MASK 0x01000000L |
751 | #define SDMA0_STATUS3_REG__QUEUE_ID_MATCH_MASK 0x02000000L |
752 | #define SDMA0_STATUS3_REG__INT_QUEUE_ID_MASK 0x3C000000L |
753 | #define SDMA0_STATUS3_REG__TMZ_MTYPE_STATUS_MASK 0xC0000000L |
754 | //SDMA0_PHYSICAL_ADDR_LO |
755 | #define SDMA0_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x0 |
756 | #define SDMA0_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x1 |
757 | #define SDMA0_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x2 |
758 | #define SDMA0_PHYSICAL_ADDR_LO__ADDR__SHIFT 0xc |
759 | #define SDMA0_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L |
760 | #define SDMA0_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L |
761 | #define SDMA0_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L |
762 | #define SDMA0_PHYSICAL_ADDR_LO__ADDR_MASK 0xFFFFF000L |
763 | //SDMA0_PHYSICAL_ADDR_HI |
764 | #define SDMA0_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x0 |
765 | #define SDMA0_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000FFFFL |
766 | //SDMA0_GLOBAL_QUANTUM |
767 | #define SDMA0_GLOBAL_QUANTUM__GLOBAL_FOCUS_QUANTUM__SHIFT 0x0 |
768 | #define SDMA0_GLOBAL_QUANTUM__GLOBAL_NORMAL_QUANTUM__SHIFT 0x8 |
769 | #define SDMA0_GLOBAL_QUANTUM__GLOBAL_FOCUS_QUANTUM_MASK 0x000000FFL |
770 | #define SDMA0_GLOBAL_QUANTUM__GLOBAL_NORMAL_QUANTUM_MASK 0x0000FF00L |
771 | //SDMA0_ERROR_LOG |
772 | #define SDMA0_ERROR_LOG__OVERRIDE__SHIFT 0x0 |
773 | #define SDMA0_ERROR_LOG__STATUS__SHIFT 0x10 |
774 | #define SDMA0_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL |
775 | #define SDMA0_ERROR_LOG__STATUS_MASK 0xFFFF0000L |
776 | //SDMA0_PUB_DUMMY_REG0 |
777 | #define SDMA0_PUB_DUMMY_REG0__VALUE__SHIFT 0x0 |
778 | #define SDMA0_PUB_DUMMY_REG0__VALUE_MASK 0xFFFFFFFFL |
779 | //SDMA0_PUB_DUMMY_REG1 |
780 | #define SDMA0_PUB_DUMMY_REG1__VALUE__SHIFT 0x0 |
781 | #define SDMA0_PUB_DUMMY_REG1__VALUE_MASK 0xFFFFFFFFL |
782 | //SDMA0_PUB_DUMMY_REG2 |
783 | #define SDMA0_PUB_DUMMY_REG2__VALUE__SHIFT 0x0 |
784 | #define SDMA0_PUB_DUMMY_REG2__VALUE_MASK 0xFFFFFFFFL |
785 | //SDMA0_PUB_DUMMY_REG3 |
786 | #define SDMA0_PUB_DUMMY_REG3__VALUE__SHIFT 0x0 |
787 | #define SDMA0_PUB_DUMMY_REG3__VALUE_MASK 0xFFFFFFFFL |
788 | //SDMA0_F32_COUNTER |
789 | #define SDMA0_F32_COUNTER__VALUE__SHIFT 0x0 |
790 | #define SDMA0_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL |
791 | //SDMA0_CRD_CNTL |
792 | #define SDMA0_CRD_CNTL__DRM_CREDIT__SHIFT 0x0 |
793 | #define SDMA0_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7 |
794 | #define SDMA0_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd |
795 | #define SDMA0_CRD_CNTL__CH_WRREQ_CREDIT__SHIFT 0x13 |
796 | #define SDMA0_CRD_CNTL__CH_RDREQ_CREDIT__SHIFT 0x19 |
797 | #define SDMA0_CRD_CNTL__DRM_CREDIT_MASK 0x0000007FL |
798 | #define SDMA0_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L |
799 | #define SDMA0_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L |
800 | #define SDMA0_CRD_CNTL__CH_WRREQ_CREDIT_MASK 0x01F80000L |
801 | #define SDMA0_CRD_CNTL__CH_RDREQ_CREDIT_MASK 0x7E000000L |
802 | //SDMA0_RLC_CGCG_CTRL |
803 | #define SDMA0_RLC_CGCG_CTRL__CGCG_INT_ENABLE__SHIFT 0x1 |
804 | #define SDMA0_RLC_CGCG_CTRL__CGCG_IDLE_HYSTERESIS__SHIFT 0x10 |
805 | #define SDMA0_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK 0x00000002L |
806 | #define SDMA0_RLC_CGCG_CTRL__CGCG_IDLE_HYSTERESIS_MASK 0xFFFF0000L |
807 | //SDMA0_GPU_IOV_VIOLATION_LOG |
808 | #define SDMA0_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0 |
809 | #define SDMA0_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1 |
810 | #define SDMA0_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2 |
811 | #define SDMA0_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION__SHIFT 0x14 |
812 | #define SDMA0_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x15 |
813 | #define SDMA0_GPU_IOV_VIOLATION_LOG__VFID__SHIFT 0x16 |
814 | #define SDMA0_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L |
815 | #define SDMA0_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L |
816 | #define SDMA0_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x000FFFFCL |
817 | #define SDMA0_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION_MASK 0x00100000L |
818 | #define SDMA0_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00200000L |
819 | #define SDMA0_GPU_IOV_VIOLATION_LOG__VFID_MASK 0x03C00000L |
820 | //SDMA0_AQL_STATUS |
821 | #define SDMA0_AQL_STATUS__COMPLETE_SIGNAL_EMPTY__SHIFT 0x0 |
822 | #define SDMA0_AQL_STATUS__INVALID_CMD_EMPTY__SHIFT 0x1 |
823 | #define SDMA0_AQL_STATUS__COMPLETE_SIGNAL_EMPTY_MASK 0x00000001L |
824 | #define SDMA0_AQL_STATUS__INVALID_CMD_EMPTY_MASK 0x00000002L |
825 | //SDMA0_EA_DBIT_ADDR_DATA |
826 | #define SDMA0_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x0 |
827 | #define SDMA0_EA_DBIT_ADDR_DATA__VALUE_MASK 0xFFFFFFFFL |
828 | //SDMA0_EA_DBIT_ADDR_INDEX |
829 | #define SDMA0_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x0 |
830 | #define SDMA0_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L |
831 | //SDMA0_TLBI_GCR_CNTL |
832 | #define SDMA0_TLBI_GCR_CNTL__TLBI_CMD_DW__SHIFT 0x0 |
833 | #define SDMA0_TLBI_GCR_CNTL__GCR_CMD_DW__SHIFT 0x4 |
834 | #define SDMA0_TLBI_GCR_CNTL__GCR_CLKEN_CYCLE__SHIFT 0x8 |
835 | #define SDMA0_TLBI_GCR_CNTL__TLBI_CREDIT__SHIFT 0x10 |
836 | #define SDMA0_TLBI_GCR_CNTL__GCR_CREDIT__SHIFT 0x18 |
837 | #define SDMA0_TLBI_GCR_CNTL__TLBI_CMD_DW_MASK 0x0000000FL |
838 | #define SDMA0_TLBI_GCR_CNTL__GCR_CMD_DW_MASK 0x000000F0L |
839 | #define SDMA0_TLBI_GCR_CNTL__GCR_CLKEN_CYCLE_MASK 0x00000F00L |
840 | #define SDMA0_TLBI_GCR_CNTL__TLBI_CREDIT_MASK 0x00FF0000L |
841 | #define SDMA0_TLBI_GCR_CNTL__GCR_CREDIT_MASK 0xFF000000L |
842 | //SDMA0_TILING_CONFIG |
843 | #define SDMA0_TILING_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 |
844 | #define SDMA0_TILING_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000070L |
845 | //SDMA0_HASH |
846 | #define SDMA0_HASH__CHANNEL_BITS__SHIFT 0x0 |
847 | #define SDMA0_HASH__BANK_BITS__SHIFT 0x4 |
848 | #define SDMA0_HASH__CHANNEL_XOR_COUNT__SHIFT 0x8 |
849 | #define SDMA0_HASH__BANK_XOR_COUNT__SHIFT 0xc |
850 | #define SDMA0_HASH__CHANNEL_BITS_MASK 0x00000007L |
851 | #define SDMA0_HASH__BANK_BITS_MASK 0x00000070L |
852 | #define SDMA0_HASH__CHANNEL_XOR_COUNT_MASK 0x00000700L |
853 | #define SDMA0_HASH__BANK_XOR_COUNT_MASK 0x00007000L |
854 | //SDMA0_INT_STATUS |
855 | #define SDMA0_INT_STATUS__DATA__SHIFT 0x0 |
856 | #define SDMA0_INT_STATUS__DATA_MASK 0xFFFFFFFFL |
857 | //SDMA0_GPU_IOV_VIOLATION_LOG2 |
858 | #define SDMA0_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID__SHIFT 0x0 |
859 | #define SDMA0_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID_MASK 0x000003FFL |
860 | //SDMA0_HOLE_ADDR_LO |
861 | #define SDMA0_HOLE_ADDR_LO__VALUE__SHIFT 0x0 |
862 | #define SDMA0_HOLE_ADDR_LO__VALUE_MASK 0xFFFFFFFFL |
863 | //SDMA0_HOLE_ADDR_HI |
864 | #define SDMA0_HOLE_ADDR_HI__VALUE__SHIFT 0x0 |
865 | #define SDMA0_HOLE_ADDR_HI__VALUE_MASK 0xFFFFFFFFL |
866 | //SDMA0_CLOCK_GATING_STATUS |
867 | #define SDMA0_CLOCK_GATING_STATUS__DYN_CLK_GATE_STATUS__SHIFT 0x0 |
868 | #define SDMA0_CLOCK_GATING_STATUS__CE_CLK_GATE_STATUS__SHIFT 0x2 |
869 | #define SDMA0_CLOCK_GATING_STATUS__CE_BC_CLK_GATE_STATUS__SHIFT 0x3 |
870 | #define SDMA0_CLOCK_GATING_STATUS__CE_NBC_CLK_GATE_STATUS__SHIFT 0x4 |
871 | #define SDMA0_CLOCK_GATING_STATUS__REG_CLK_GATE_STATUS__SHIFT 0x5 |
872 | #define SDMA0_CLOCK_GATING_STATUS__F32_CLK_GATE_STATUS__SHIFT 0x6 |
873 | #define SDMA0_CLOCK_GATING_STATUS__DYN_CLK_GATE_STATUS_MASK 0x00000001L |
874 | #define SDMA0_CLOCK_GATING_STATUS__CE_CLK_GATE_STATUS_MASK 0x00000004L |
875 | #define SDMA0_CLOCK_GATING_STATUS__CE_BC_CLK_GATE_STATUS_MASK 0x00000008L |
876 | #define SDMA0_CLOCK_GATING_STATUS__CE_NBC_CLK_GATE_STATUS_MASK 0x00000010L |
877 | #define SDMA0_CLOCK_GATING_STATUS__REG_CLK_GATE_STATUS_MASK 0x00000020L |
878 | #define SDMA0_CLOCK_GATING_STATUS__F32_CLK_GATE_STATUS_MASK 0x00000040L |
879 | //SDMA0_STATUS4_REG |
880 | #define SDMA0_STATUS4_REG__IDLE__SHIFT 0x0 |
881 | #define SDMA0_STATUS4_REG__IH_OUTSTANDING__SHIFT 0x2 |
882 | #define SDMA0_STATUS4_REG__SEM_OUTSTANDING__SHIFT 0x3 |
883 | #define SDMA0_STATUS4_REG__CH_RD_OUTSTANDING__SHIFT 0x4 |
884 | #define SDMA0_STATUS4_REG__CH_WR_OUTSTANDING__SHIFT 0x5 |
885 | #define SDMA0_STATUS4_REG__GCR_OUTSTANDING__SHIFT 0x6 |
886 | #define SDMA0_STATUS4_REG__TLBI_OUTSTANDING__SHIFT 0x7 |
887 | #define SDMA0_STATUS4_REG__UTCL2_RD_OUTSTANDING__SHIFT 0x8 |
888 | #define SDMA0_STATUS4_REG__UTCL2_WR_OUTSTANDING__SHIFT 0x9 |
889 | #define SDMA0_STATUS4_REG__REG_POLLING__SHIFT 0xa |
890 | #define SDMA0_STATUS4_REG__MEM_POLLING__SHIFT 0xb |
891 | #define SDMA0_STATUS4_REG__RESERVED_13_12__SHIFT 0xc |
892 | #define SDMA0_STATUS4_REG__RESERVED_15_14__SHIFT 0xe |
893 | #define SDMA0_STATUS4_REG__ACTIVE_QUEUE_ID__SHIFT 0x10 |
894 | #define SDMA0_STATUS4_REG__SRIOV_WATING_RLCV_CMD__SHIFT 0x14 |
895 | #define SDMA0_STATUS4_REG__SRIOV_SDMA_EXECUTING_CMD__SHIFT 0x15 |
896 | #define SDMA0_STATUS4_REG__UTCL2_RD_XNACK_FAULT__SHIFT 0x16 |
897 | #define SDMA0_STATUS4_REG__UTCL2_RD_XNACK_NULL__SHIFT 0x17 |
898 | #define SDMA0_STATUS4_REG__UTCL2_RD_XNACK_TIMEOUT__SHIFT 0x18 |
899 | #define SDMA0_STATUS4_REG__UTCL2_WR_XNACK_FAULT__SHIFT 0x19 |
900 | #define SDMA0_STATUS4_REG__UTCL2_WR_XNACK_NULL__SHIFT 0x1a |
901 | #define SDMA0_STATUS4_REG__UTCL2_WR_XNACK_TIMEOUT__SHIFT 0x1b |
902 | #define SDMA0_STATUS4_REG__IDLE_MASK 0x00000001L |
903 | #define SDMA0_STATUS4_REG__IH_OUTSTANDING_MASK 0x00000004L |
904 | #define SDMA0_STATUS4_REG__SEM_OUTSTANDING_MASK 0x00000008L |
905 | #define SDMA0_STATUS4_REG__CH_RD_OUTSTANDING_MASK 0x00000010L |
906 | #define SDMA0_STATUS4_REG__CH_WR_OUTSTANDING_MASK 0x00000020L |
907 | #define SDMA0_STATUS4_REG__GCR_OUTSTANDING_MASK 0x00000040L |
908 | #define SDMA0_STATUS4_REG__TLBI_OUTSTANDING_MASK 0x00000080L |
909 | #define SDMA0_STATUS4_REG__UTCL2_RD_OUTSTANDING_MASK 0x00000100L |
910 | #define SDMA0_STATUS4_REG__UTCL2_WR_OUTSTANDING_MASK 0x00000200L |
911 | #define SDMA0_STATUS4_REG__REG_POLLING_MASK 0x00000400L |
912 | #define SDMA0_STATUS4_REG__MEM_POLLING_MASK 0x00000800L |
913 | #define SDMA0_STATUS4_REG__RESERVED_13_12_MASK 0x00003000L |
914 | #define SDMA0_STATUS4_REG__RESERVED_15_14_MASK 0x0000C000L |
915 | #define SDMA0_STATUS4_REG__ACTIVE_QUEUE_ID_MASK 0x000F0000L |
916 | #define SDMA0_STATUS4_REG__SRIOV_WATING_RLCV_CMD_MASK 0x00100000L |
917 | #define SDMA0_STATUS4_REG__SRIOV_SDMA_EXECUTING_CMD_MASK 0x00200000L |
918 | #define SDMA0_STATUS4_REG__UTCL2_RD_XNACK_FAULT_MASK 0x00400000L |
919 | #define SDMA0_STATUS4_REG__UTCL2_RD_XNACK_NULL_MASK 0x00800000L |
920 | #define SDMA0_STATUS4_REG__UTCL2_RD_XNACK_TIMEOUT_MASK 0x01000000L |
921 | #define SDMA0_STATUS4_REG__UTCL2_WR_XNACK_FAULT_MASK 0x02000000L |
922 | #define SDMA0_STATUS4_REG__UTCL2_WR_XNACK_NULL_MASK 0x04000000L |
923 | #define SDMA0_STATUS4_REG__UTCL2_WR_XNACK_TIMEOUT_MASK 0x08000000L |
924 | //SDMA0_SCRATCH_RAM_DATA |
925 | #define SDMA0_SCRATCH_RAM_DATA__DATA__SHIFT 0x0 |
926 | #define SDMA0_SCRATCH_RAM_DATA__DATA_MASK 0xFFFFFFFFL |
927 | //SDMA0_SCRATCH_RAM_ADDR |
928 | #define SDMA0_SCRATCH_RAM_ADDR__ADDR__SHIFT 0x0 |
929 | #define SDMA0_SCRATCH_RAM_ADDR__ADDR_MASK 0x0000007FL |
930 | //SDMA0_TIMESTAMP_CNTL |
931 | #define SDMA0_TIMESTAMP_CNTL__CAPTURE__SHIFT 0x0 |
932 | #define SDMA0_TIMESTAMP_CNTL__CAPTURE_MASK 0x00000001L |
933 | //SDMA0_STATUS5_REG |
934 | #define SDMA0_STATUS5_REG__QUEUE0_RB_ENABLE_STATUS__SHIFT 0x0 |
935 | #define SDMA0_STATUS5_REG__QUEUE1_RB_ENABLE_STATUS__SHIFT 0x1 |
936 | #define SDMA0_STATUS5_REG__QUEUE2_RB_ENABLE_STATUS__SHIFT 0x2 |
937 | #define SDMA0_STATUS5_REG__QUEUE3_RB_ENABLE_STATUS__SHIFT 0x3 |
938 | #define SDMA0_STATUS5_REG__QUEUE4_RB_ENABLE_STATUS__SHIFT 0x4 |
939 | #define SDMA0_STATUS5_REG__QUEUE5_RB_ENABLE_STATUS__SHIFT 0x5 |
940 | #define SDMA0_STATUS5_REG__QUEUE6_RB_ENABLE_STATUS__SHIFT 0x6 |
941 | #define SDMA0_STATUS5_REG__QUEUE7_RB_ENABLE_STATUS__SHIFT 0x7 |
942 | #define SDMA0_STATUS5_REG__ACTIVE_QUEUE_ID__SHIFT 0x10 |
943 | #define SDMA0_STATUS5_REG__QUEUE0_WPTR_POLL_PAGE_EXCEPTION__SHIFT 0x14 |
944 | #define SDMA0_STATUS5_REG__QUEUE1_WPTR_POLL_PAGE_EXCEPTION__SHIFT 0x15 |
945 | #define SDMA0_STATUS5_REG__QUEUE2_WPTR_POLL_PAGE_EXCEPTION__SHIFT 0x16 |
946 | #define SDMA0_STATUS5_REG__QUEUE3_WPTR_POLL_PAGE_EXCEPTION__SHIFT 0x17 |
947 | #define SDMA0_STATUS5_REG__QUEUE4_WPTR_POLL_PAGE_EXCEPTION__SHIFT 0x18 |
948 | #define SDMA0_STATUS5_REG__QUEUE5_WPTR_POLL_PAGE_EXCEPTION__SHIFT 0x19 |
949 | #define SDMA0_STATUS5_REG__QUEUE6_WPTR_POLL_PAGE_EXCEPTION__SHIFT 0x1a |
950 | #define SDMA0_STATUS5_REG__QUEUE7_WPTR_POLL_PAGE_EXCEPTION__SHIFT 0x1b |
951 | #define SDMA0_STATUS5_REG__QUEUE0_RB_ENABLE_STATUS_MASK 0x00000001L |
952 | #define SDMA0_STATUS5_REG__QUEUE1_RB_ENABLE_STATUS_MASK 0x00000002L |
953 | #define SDMA0_STATUS5_REG__QUEUE2_RB_ENABLE_STATUS_MASK 0x00000004L |
954 | #define SDMA0_STATUS5_REG__QUEUE3_RB_ENABLE_STATUS_MASK 0x00000008L |
955 | #define SDMA0_STATUS5_REG__QUEUE4_RB_ENABLE_STATUS_MASK 0x00000010L |
956 | #define SDMA0_STATUS5_REG__QUEUE5_RB_ENABLE_STATUS_MASK 0x00000020L |
957 | #define SDMA0_STATUS5_REG__QUEUE6_RB_ENABLE_STATUS_MASK 0x00000040L |
958 | #define SDMA0_STATUS5_REG__QUEUE7_RB_ENABLE_STATUS_MASK 0x00000080L |
959 | #define SDMA0_STATUS5_REG__ACTIVE_QUEUE_ID_MASK 0x000F0000L |
960 | #define SDMA0_STATUS5_REG__QUEUE0_WPTR_POLL_PAGE_EXCEPTION_MASK 0x00100000L |
961 | #define SDMA0_STATUS5_REG__QUEUE1_WPTR_POLL_PAGE_EXCEPTION_MASK 0x00200000L |
962 | #define SDMA0_STATUS5_REG__QUEUE2_WPTR_POLL_PAGE_EXCEPTION_MASK 0x00400000L |
963 | #define SDMA0_STATUS5_REG__QUEUE3_WPTR_POLL_PAGE_EXCEPTION_MASK 0x00800000L |
964 | #define SDMA0_STATUS5_REG__QUEUE4_WPTR_POLL_PAGE_EXCEPTION_MASK 0x01000000L |
965 | #define SDMA0_STATUS5_REG__QUEUE5_WPTR_POLL_PAGE_EXCEPTION_MASK 0x02000000L |
966 | #define SDMA0_STATUS5_REG__QUEUE6_WPTR_POLL_PAGE_EXCEPTION_MASK 0x04000000L |
967 | #define SDMA0_STATUS5_REG__QUEUE7_WPTR_POLL_PAGE_EXCEPTION_MASK 0x08000000L |
968 | //SDMA0_QUEUE_RESET_REQ |
969 | #define SDMA0_QUEUE_RESET_REQ__QUEUE0_RESET__SHIFT 0x0 |
970 | #define SDMA0_QUEUE_RESET_REQ__QUEUE1_RESET__SHIFT 0x1 |
971 | #define SDMA0_QUEUE_RESET_REQ__QUEUE2_RESET__SHIFT 0x2 |
972 | #define SDMA0_QUEUE_RESET_REQ__QUEUE3_RESET__SHIFT 0x3 |
973 | #define SDMA0_QUEUE_RESET_REQ__QUEUE4_RESET__SHIFT 0x4 |
974 | #define SDMA0_QUEUE_RESET_REQ__QUEUE5_RESET__SHIFT 0x5 |
975 | #define SDMA0_QUEUE_RESET_REQ__QUEUE6_RESET__SHIFT 0x6 |
976 | #define SDMA0_QUEUE_RESET_REQ__QUEUE7_RESET__SHIFT 0x7 |
977 | #define SDMA0_QUEUE_RESET_REQ__RESERVED__SHIFT 0x8 |
978 | #define SDMA0_QUEUE_RESET_REQ__QUEUE0_RESET_MASK 0x00000001L |
979 | #define SDMA0_QUEUE_RESET_REQ__QUEUE1_RESET_MASK 0x00000002L |
980 | #define SDMA0_QUEUE_RESET_REQ__QUEUE2_RESET_MASK 0x00000004L |
981 | #define SDMA0_QUEUE_RESET_REQ__QUEUE3_RESET_MASK 0x00000008L |
982 | #define SDMA0_QUEUE_RESET_REQ__QUEUE4_RESET_MASK 0x00000010L |
983 | #define SDMA0_QUEUE_RESET_REQ__QUEUE5_RESET_MASK 0x00000020L |
984 | #define SDMA0_QUEUE_RESET_REQ__QUEUE6_RESET_MASK 0x00000040L |
985 | #define SDMA0_QUEUE_RESET_REQ__QUEUE7_RESET_MASK 0x00000080L |
986 | #define SDMA0_QUEUE_RESET_REQ__RESERVED_MASK 0xFFFFFF00L |
987 | //SDMA0_STATUS6_REG |
988 | #define SDMA0_STATUS6_REG__ID__SHIFT 0x0 |
989 | #define SDMA0_STATUS6_REG__TH1F32_INSTR_PTR__SHIFT 0x2 |
990 | #define SDMA0_STATUS6_REG__TH1_EXCEPTION__SHIFT 0x10 |
991 | #define SDMA0_STATUS6_REG__ID_MASK 0x00000003L |
992 | #define SDMA0_STATUS6_REG__TH1F32_INSTR_PTR_MASK 0x0000FFFCL |
993 | #define SDMA0_STATUS6_REG__TH1_EXCEPTION_MASK 0xFFFF0000L |
994 | //SDMA0_UCODE1_CHECKSUM |
995 | #define SDMA0_UCODE1_CHECKSUM__DATA__SHIFT 0x0 |
996 | #define SDMA0_UCODE1_CHECKSUM__DATA_MASK 0xFFFFFFFFL |
997 | //SDMA0_CE_CTRL |
998 | #define SDMA0_CE_CTRL__RD_LUT_WATERMARK__SHIFT 0x0 |
999 | #define SDMA0_CE_CTRL__RD_LUT_DEPTH__SHIFT 0x3 |
1000 | #define SDMA0_CE_CTRL__WR_AFIFO_WATERMARK__SHIFT 0x5 |
1001 | #define SDMA0_CE_CTRL__CE_DCC_READ_128B_ENABLE__SHIFT 0x8 |
1002 | #define SDMA0_CE_CTRL__RESERVED__SHIFT 0x9 |
1003 | #define SDMA0_CE_CTRL__RD_LUT_WATERMARK_MASK 0x00000007L |
1004 | #define SDMA0_CE_CTRL__RD_LUT_DEPTH_MASK 0x00000018L |
1005 | #define SDMA0_CE_CTRL__WR_AFIFO_WATERMARK_MASK 0x000000E0L |
1006 | #define SDMA0_CE_CTRL__CE_DCC_READ_128B_ENABLE_MASK 0x00000100L |
1007 | #define SDMA0_CE_CTRL__RESERVED_MASK 0xFFFFFE00L |
1008 | //SDMA0_FED_STATUS |
1009 | #define SDMA0_FED_STATUS__RB_FETCH_ECC__SHIFT 0x0 |
1010 | #define SDMA0_FED_STATUS__IB_FETCH_ECC__SHIFT 0x1 |
1011 | #define SDMA0_FED_STATUS__F32_DATA_ECC__SHIFT 0x2 |
1012 | #define SDMA0_FED_STATUS__WPTR_ATOMIC_ECC__SHIFT 0x3 |
1013 | #define SDMA0_FED_STATUS__COPY_DATA_ECC__SHIFT 0x4 |
1014 | #define SDMA0_FED_STATUS__COPY_METADATA_ECC__SHIFT 0x5 |
1015 | #define SDMA0_FED_STATUS__SELFLOAD_UCODE_ECC__SHIFT 0x6 |
1016 | #define SDMA0_FED_STATUS__RB_FETCH_ECC_MASK 0x00000001L |
1017 | #define SDMA0_FED_STATUS__IB_FETCH_ECC_MASK 0x00000002L |
1018 | #define SDMA0_FED_STATUS__F32_DATA_ECC_MASK 0x00000004L |
1019 | #define SDMA0_FED_STATUS__WPTR_ATOMIC_ECC_MASK 0x00000008L |
1020 | #define SDMA0_FED_STATUS__COPY_DATA_ECC_MASK 0x00000010L |
1021 | #define SDMA0_FED_STATUS__COPY_METADATA_ECC_MASK 0x00000020L |
1022 | #define SDMA0_FED_STATUS__SELFLOAD_UCODE_ECC_MASK 0x00000040L |
1023 | //SDMA0_QUEUE0_RB_CNTL |
1024 | #define SDMA0_QUEUE0_RB_CNTL__RB_ENABLE__SHIFT 0x0 |
1025 | #define SDMA0_QUEUE0_RB_CNTL__RB_SIZE__SHIFT 0x1 |
1026 | #define SDMA0_QUEUE0_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 |
1027 | #define SDMA0_QUEUE0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 |
1028 | #define SDMA0_QUEUE0_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa |
1029 | #define SDMA0_QUEUE0_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT 0xb |
1030 | #define SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc |
1031 | #define SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd |
1032 | #define SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 |
1033 | #define SDMA0_QUEUE0_RB_CNTL__RB_PRIV__SHIFT 0x17 |
1034 | #define SDMA0_QUEUE0_RB_CNTL__RB_VMID__SHIFT 0x18 |
1035 | #define SDMA0_QUEUE0_RB_CNTL__RB_ENABLE_MASK 0x00000001L |
1036 | #define SDMA0_QUEUE0_RB_CNTL__RB_SIZE_MASK 0x0000003EL |
1037 | #define SDMA0_QUEUE0_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L |
1038 | #define SDMA0_QUEUE0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L |
1039 | #define SDMA0_QUEUE0_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L |
1040 | #define SDMA0_QUEUE0_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK 0x00000800L |
1041 | #define SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L |
1042 | #define SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L |
1043 | #define SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L |
1044 | #define SDMA0_QUEUE0_RB_CNTL__RB_PRIV_MASK 0x00800000L |
1045 | #define SDMA0_QUEUE0_RB_CNTL__RB_VMID_MASK 0x0F000000L |
1046 | //SDMA0_QUEUE0_RB_BASE |
1047 | #define SDMA0_QUEUE0_RB_BASE__ADDR__SHIFT 0x0 |
1048 | #define SDMA0_QUEUE0_RB_BASE__ADDR_MASK 0xFFFFFFFFL |
1049 | //SDMA0_QUEUE0_RB_BASE_HI |
1050 | #define SDMA0_QUEUE0_RB_BASE_HI__ADDR__SHIFT 0x0 |
1051 | #define SDMA0_QUEUE0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL |
1052 | //SDMA0_QUEUE0_RB_RPTR |
1053 | #define SDMA0_QUEUE0_RB_RPTR__OFFSET__SHIFT 0x0 |
1054 | #define SDMA0_QUEUE0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL |
1055 | //SDMA0_QUEUE0_RB_RPTR_HI |
1056 | #define SDMA0_QUEUE0_RB_RPTR_HI__OFFSET__SHIFT 0x0 |
1057 | #define SDMA0_QUEUE0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
1058 | //SDMA0_QUEUE0_RB_WPTR |
1059 | #define SDMA0_QUEUE0_RB_WPTR__OFFSET__SHIFT 0x0 |
1060 | #define SDMA0_QUEUE0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL |
1061 | //SDMA0_QUEUE0_RB_WPTR_HI |
1062 | #define SDMA0_QUEUE0_RB_WPTR_HI__OFFSET__SHIFT 0x0 |
1063 | #define SDMA0_QUEUE0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
1064 | //SDMA0_QUEUE0_RB_RPTR_ADDR_HI |
1065 | #define SDMA0_QUEUE0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 |
1066 | #define SDMA0_QUEUE0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
1067 | //SDMA0_QUEUE0_RB_RPTR_ADDR_LO |
1068 | #define SDMA0_QUEUE0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 |
1069 | #define SDMA0_QUEUE0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
1070 | //SDMA0_QUEUE0_IB_CNTL |
1071 | #define SDMA0_QUEUE0_IB_CNTL__IB_ENABLE__SHIFT 0x0 |
1072 | #define SDMA0_QUEUE0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 |
1073 | #define SDMA0_QUEUE0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 |
1074 | #define SDMA0_QUEUE0_IB_CNTL__CMD_VMID__SHIFT 0x10 |
1075 | #define SDMA0_QUEUE0_IB_CNTL__IB_PRIV__SHIFT 0x1f |
1076 | #define SDMA0_QUEUE0_IB_CNTL__IB_ENABLE_MASK 0x00000001L |
1077 | #define SDMA0_QUEUE0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L |
1078 | #define SDMA0_QUEUE0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L |
1079 | #define SDMA0_QUEUE0_IB_CNTL__CMD_VMID_MASK 0x000F0000L |
1080 | #define SDMA0_QUEUE0_IB_CNTL__IB_PRIV_MASK 0x80000000L |
1081 | //SDMA0_QUEUE0_IB_RPTR |
1082 | #define SDMA0_QUEUE0_IB_RPTR__OFFSET__SHIFT 0x2 |
1083 | #define SDMA0_QUEUE0_IB_RPTR__OFFSET_MASK 0x003FFFFCL |
1084 | //SDMA0_QUEUE0_IB_OFFSET |
1085 | #define SDMA0_QUEUE0_IB_OFFSET__OFFSET__SHIFT 0x2 |
1086 | #define SDMA0_QUEUE0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL |
1087 | //SDMA0_QUEUE0_IB_BASE_LO |
1088 | #define SDMA0_QUEUE0_IB_BASE_LO__ADDR__SHIFT 0x5 |
1089 | #define SDMA0_QUEUE0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L |
1090 | //SDMA0_QUEUE0_IB_BASE_HI |
1091 | #define SDMA0_QUEUE0_IB_BASE_HI__ADDR__SHIFT 0x0 |
1092 | #define SDMA0_QUEUE0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL |
1093 | //SDMA0_QUEUE0_IB_SIZE |
1094 | #define SDMA0_QUEUE0_IB_SIZE__SIZE__SHIFT 0x0 |
1095 | #define SDMA0_QUEUE0_IB_SIZE__SIZE_MASK 0x000FFFFFL |
1096 | //SDMA0_QUEUE0_SKIP_CNTL |
1097 | #define SDMA0_QUEUE0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 |
1098 | #define SDMA0_QUEUE0_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL |
1099 | //SDMA0_QUEUE0_CONTEXT_STATUS |
1100 | #define SDMA0_QUEUE0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 |
1101 | #define SDMA0_QUEUE0_CONTEXT_STATUS__USE_IB__SHIFT 0x1 |
1102 | #define SDMA0_QUEUE0_CONTEXT_STATUS__IDLE__SHIFT 0x2 |
1103 | #define SDMA0_QUEUE0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 |
1104 | #define SDMA0_QUEUE0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 |
1105 | #define SDMA0_QUEUE0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 |
1106 | #define SDMA0_QUEUE0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa |
1107 | #define SDMA0_QUEUE0_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb |
1108 | #define SDMA0_QUEUE0_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc |
1109 | #define SDMA0_QUEUE0_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 |
1110 | #define SDMA0_QUEUE0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L |
1111 | #define SDMA0_QUEUE0_CONTEXT_STATUS__USE_IB_MASK 0x00000002L |
1112 | #define SDMA0_QUEUE0_CONTEXT_STATUS__IDLE_MASK 0x00000004L |
1113 | #define SDMA0_QUEUE0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L |
1114 | #define SDMA0_QUEUE0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L |
1115 | #define SDMA0_QUEUE0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L |
1116 | #define SDMA0_QUEUE0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L |
1117 | #define SDMA0_QUEUE0_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L |
1118 | #define SDMA0_QUEUE0_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L |
1119 | #define SDMA0_QUEUE0_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L |
1120 | //SDMA0_QUEUE0_DOORBELL |
1121 | #define SDMA0_QUEUE0_DOORBELL__ENABLE__SHIFT 0x1c |
1122 | #define SDMA0_QUEUE0_DOORBELL__CAPTURED__SHIFT 0x1e |
1123 | #define SDMA0_QUEUE0_DOORBELL__ENABLE_MASK 0x10000000L |
1124 | #define SDMA0_QUEUE0_DOORBELL__CAPTURED_MASK 0x40000000L |
1125 | //SDMA0_QUEUE0_DOORBELL_LOG |
1126 | #define SDMA0_QUEUE0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 |
1127 | #define SDMA0_QUEUE0_DOORBELL_LOG__DATA__SHIFT 0x2 |
1128 | #define SDMA0_QUEUE0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L |
1129 | #define SDMA0_QUEUE0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL |
1130 | //SDMA0_QUEUE0_DOORBELL_OFFSET |
1131 | #define SDMA0_QUEUE0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 |
1132 | #define SDMA0_QUEUE0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL |
1133 | //SDMA0_QUEUE0_CSA_ADDR_LO |
1134 | #define SDMA0_QUEUE0_CSA_ADDR_LO__ADDR__SHIFT 0x2 |
1135 | #define SDMA0_QUEUE0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
1136 | //SDMA0_QUEUE0_CSA_ADDR_HI |
1137 | #define SDMA0_QUEUE0_CSA_ADDR_HI__ADDR__SHIFT 0x0 |
1138 | #define SDMA0_QUEUE0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
1139 | //SDMA0_QUEUE0_SCHEDULE_CNTL |
1140 | #define SDMA0_QUEUE0_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 |
1141 | #define SDMA0_QUEUE0_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 |
1142 | #define SDMA0_QUEUE0_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 |
1143 | #define SDMA0_QUEUE0_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 |
1144 | #define SDMA0_QUEUE0_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L |
1145 | #define SDMA0_QUEUE0_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL |
1146 | #define SDMA0_QUEUE0_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L |
1147 | #define SDMA0_QUEUE0_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L |
1148 | //SDMA0_QUEUE0_IB_SUB_REMAIN |
1149 | #define SDMA0_QUEUE0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 |
1150 | #define SDMA0_QUEUE0_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL |
1151 | //SDMA0_QUEUE0_PREEMPT |
1152 | #define SDMA0_QUEUE0_PREEMPT__IB_PREEMPT__SHIFT 0x0 |
1153 | #define SDMA0_QUEUE0_PREEMPT__IB_PREEMPT_MASK 0x00000001L |
1154 | //SDMA0_QUEUE0_DUMMY_REG |
1155 | #define SDMA0_QUEUE0_DUMMY_REG__DUMMY__SHIFT 0x0 |
1156 | #define SDMA0_QUEUE0_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL |
1157 | //SDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI |
1158 | #define SDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 |
1159 | #define SDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
1160 | //SDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO |
1161 | #define SDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 |
1162 | #define SDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
1163 | //SDMA0_QUEUE0_RB_AQL_CNTL |
1164 | #define SDMA0_QUEUE0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 |
1165 | #define SDMA0_QUEUE0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 |
1166 | #define SDMA0_QUEUE0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 |
1167 | #define SDMA0_QUEUE0_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 |
1168 | #define SDMA0_QUEUE0_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 |
1169 | #define SDMA0_QUEUE0_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 |
1170 | #define SDMA0_QUEUE0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L |
1171 | #define SDMA0_QUEUE0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL |
1172 | #define SDMA0_QUEUE0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L |
1173 | #define SDMA0_QUEUE0_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L |
1174 | #define SDMA0_QUEUE0_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L |
1175 | #define SDMA0_QUEUE0_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L |
1176 | //SDMA0_QUEUE0_MINOR_PTR_UPDATE |
1177 | #define SDMA0_QUEUE0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 |
1178 | #define SDMA0_QUEUE0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L |
1179 | //SDMA0_QUEUE0_RB_PREEMPT |
1180 | #define SDMA0_QUEUE0_RB_PREEMPT__PREEMPT_REQ__SHIFT 0x0 |
1181 | #define SDMA0_QUEUE0_RB_PREEMPT__PREEMPT_REQ_MASK 0x00000001L |
1182 | //SDMA0_QUEUE0_MIDCMD_DATA0 |
1183 | #define SDMA0_QUEUE0_MIDCMD_DATA0__DATA0__SHIFT 0x0 |
1184 | #define SDMA0_QUEUE0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL |
1185 | //SDMA0_QUEUE0_MIDCMD_DATA1 |
1186 | #define SDMA0_QUEUE0_MIDCMD_DATA1__DATA1__SHIFT 0x0 |
1187 | #define SDMA0_QUEUE0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL |
1188 | //SDMA0_QUEUE0_MIDCMD_DATA2 |
1189 | #define SDMA0_QUEUE0_MIDCMD_DATA2__DATA2__SHIFT 0x0 |
1190 | #define SDMA0_QUEUE0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL |
1191 | //SDMA0_QUEUE0_MIDCMD_DATA3 |
1192 | #define SDMA0_QUEUE0_MIDCMD_DATA3__DATA3__SHIFT 0x0 |
1193 | #define SDMA0_QUEUE0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL |
1194 | //SDMA0_QUEUE0_MIDCMD_DATA4 |
1195 | #define SDMA0_QUEUE0_MIDCMD_DATA4__DATA4__SHIFT 0x0 |
1196 | #define SDMA0_QUEUE0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL |
1197 | //SDMA0_QUEUE0_MIDCMD_DATA5 |
1198 | #define SDMA0_QUEUE0_MIDCMD_DATA5__DATA5__SHIFT 0x0 |
1199 | #define SDMA0_QUEUE0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL |
1200 | //SDMA0_QUEUE0_MIDCMD_DATA6 |
1201 | #define SDMA0_QUEUE0_MIDCMD_DATA6__DATA6__SHIFT 0x0 |
1202 | #define SDMA0_QUEUE0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL |
1203 | //SDMA0_QUEUE0_MIDCMD_DATA7 |
1204 | #define SDMA0_QUEUE0_MIDCMD_DATA7__DATA7__SHIFT 0x0 |
1205 | #define SDMA0_QUEUE0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL |
1206 | //SDMA0_QUEUE0_MIDCMD_DATA8 |
1207 | #define SDMA0_QUEUE0_MIDCMD_DATA8__DATA8__SHIFT 0x0 |
1208 | #define SDMA0_QUEUE0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL |
1209 | //SDMA0_QUEUE0_MIDCMD_DATA9 |
1210 | #define SDMA0_QUEUE0_MIDCMD_DATA9__DATA9__SHIFT 0x0 |
1211 | #define SDMA0_QUEUE0_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL |
1212 | //SDMA0_QUEUE0_MIDCMD_DATA10 |
1213 | #define SDMA0_QUEUE0_MIDCMD_DATA10__DATA10__SHIFT 0x0 |
1214 | #define SDMA0_QUEUE0_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL |
1215 | //SDMA0_QUEUE0_MIDCMD_CNTL |
1216 | #define SDMA0_QUEUE0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 |
1217 | #define SDMA0_QUEUE0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 |
1218 | #define SDMA0_QUEUE0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 |
1219 | #define SDMA0_QUEUE0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 |
1220 | #define SDMA0_QUEUE0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L |
1221 | #define SDMA0_QUEUE0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L |
1222 | #define SDMA0_QUEUE0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L |
1223 | #define SDMA0_QUEUE0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L |
1224 | //SDMA0_QUEUE1_RB_CNTL |
1225 | #define SDMA0_QUEUE1_RB_CNTL__RB_ENABLE__SHIFT 0x0 |
1226 | #define SDMA0_QUEUE1_RB_CNTL__RB_SIZE__SHIFT 0x1 |
1227 | #define SDMA0_QUEUE1_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 |
1228 | #define SDMA0_QUEUE1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 |
1229 | #define SDMA0_QUEUE1_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa |
1230 | #define SDMA0_QUEUE1_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT 0xb |
1231 | #define SDMA0_QUEUE1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc |
1232 | #define SDMA0_QUEUE1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd |
1233 | #define SDMA0_QUEUE1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 |
1234 | #define SDMA0_QUEUE1_RB_CNTL__RB_PRIV__SHIFT 0x17 |
1235 | #define SDMA0_QUEUE1_RB_CNTL__RB_VMID__SHIFT 0x18 |
1236 | #define SDMA0_QUEUE1_RB_CNTL__RB_ENABLE_MASK 0x00000001L |
1237 | #define SDMA0_QUEUE1_RB_CNTL__RB_SIZE_MASK 0x0000003EL |
1238 | #define SDMA0_QUEUE1_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L |
1239 | #define SDMA0_QUEUE1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L |
1240 | #define SDMA0_QUEUE1_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L |
1241 | #define SDMA0_QUEUE1_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK 0x00000800L |
1242 | #define SDMA0_QUEUE1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L |
1243 | #define SDMA0_QUEUE1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L |
1244 | #define SDMA0_QUEUE1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L |
1245 | #define SDMA0_QUEUE1_RB_CNTL__RB_PRIV_MASK 0x00800000L |
1246 | #define SDMA0_QUEUE1_RB_CNTL__RB_VMID_MASK 0x0F000000L |
1247 | //SDMA0_QUEUE1_RB_BASE |
1248 | #define SDMA0_QUEUE1_RB_BASE__ADDR__SHIFT 0x0 |
1249 | #define SDMA0_QUEUE1_RB_BASE__ADDR_MASK 0xFFFFFFFFL |
1250 | //SDMA0_QUEUE1_RB_BASE_HI |
1251 | #define SDMA0_QUEUE1_RB_BASE_HI__ADDR__SHIFT 0x0 |
1252 | #define SDMA0_QUEUE1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL |
1253 | //SDMA0_QUEUE1_RB_RPTR |
1254 | #define SDMA0_QUEUE1_RB_RPTR__OFFSET__SHIFT 0x0 |
1255 | #define SDMA0_QUEUE1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL |
1256 | //SDMA0_QUEUE1_RB_RPTR_HI |
1257 | #define SDMA0_QUEUE1_RB_RPTR_HI__OFFSET__SHIFT 0x0 |
1258 | #define SDMA0_QUEUE1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
1259 | //SDMA0_QUEUE1_RB_WPTR |
1260 | #define SDMA0_QUEUE1_RB_WPTR__OFFSET__SHIFT 0x0 |
1261 | #define SDMA0_QUEUE1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL |
1262 | //SDMA0_QUEUE1_RB_WPTR_HI |
1263 | #define SDMA0_QUEUE1_RB_WPTR_HI__OFFSET__SHIFT 0x0 |
1264 | #define SDMA0_QUEUE1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
1265 | //SDMA0_QUEUE1_RB_RPTR_ADDR_HI |
1266 | #define SDMA0_QUEUE1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 |
1267 | #define SDMA0_QUEUE1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
1268 | //SDMA0_QUEUE1_RB_RPTR_ADDR_LO |
1269 | #define SDMA0_QUEUE1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 |
1270 | #define SDMA0_QUEUE1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
1271 | //SDMA0_QUEUE1_IB_CNTL |
1272 | #define SDMA0_QUEUE1_IB_CNTL__IB_ENABLE__SHIFT 0x0 |
1273 | #define SDMA0_QUEUE1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 |
1274 | #define SDMA0_QUEUE1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 |
1275 | #define SDMA0_QUEUE1_IB_CNTL__CMD_VMID__SHIFT 0x10 |
1276 | #define SDMA0_QUEUE1_IB_CNTL__IB_PRIV__SHIFT 0x1f |
1277 | #define SDMA0_QUEUE1_IB_CNTL__IB_ENABLE_MASK 0x00000001L |
1278 | #define SDMA0_QUEUE1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L |
1279 | #define SDMA0_QUEUE1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L |
1280 | #define SDMA0_QUEUE1_IB_CNTL__CMD_VMID_MASK 0x000F0000L |
1281 | #define SDMA0_QUEUE1_IB_CNTL__IB_PRIV_MASK 0x80000000L |
1282 | //SDMA0_QUEUE1_IB_RPTR |
1283 | #define SDMA0_QUEUE1_IB_RPTR__OFFSET__SHIFT 0x2 |
1284 | #define SDMA0_QUEUE1_IB_RPTR__OFFSET_MASK 0x003FFFFCL |
1285 | //SDMA0_QUEUE1_IB_OFFSET |
1286 | #define SDMA0_QUEUE1_IB_OFFSET__OFFSET__SHIFT 0x2 |
1287 | #define SDMA0_QUEUE1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL |
1288 | //SDMA0_QUEUE1_IB_BASE_LO |
1289 | #define SDMA0_QUEUE1_IB_BASE_LO__ADDR__SHIFT 0x5 |
1290 | #define SDMA0_QUEUE1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L |
1291 | //SDMA0_QUEUE1_IB_BASE_HI |
1292 | #define SDMA0_QUEUE1_IB_BASE_HI__ADDR__SHIFT 0x0 |
1293 | #define SDMA0_QUEUE1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL |
1294 | //SDMA0_QUEUE1_IB_SIZE |
1295 | #define SDMA0_QUEUE1_IB_SIZE__SIZE__SHIFT 0x0 |
1296 | #define SDMA0_QUEUE1_IB_SIZE__SIZE_MASK 0x000FFFFFL |
1297 | //SDMA0_QUEUE1_SKIP_CNTL |
1298 | #define SDMA0_QUEUE1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 |
1299 | #define SDMA0_QUEUE1_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL |
1300 | //SDMA0_QUEUE1_CONTEXT_STATUS |
1301 | #define SDMA0_QUEUE1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 |
1302 | #define SDMA0_QUEUE1_CONTEXT_STATUS__IDLE__SHIFT 0x2 |
1303 | #define SDMA0_QUEUE1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 |
1304 | #define SDMA0_QUEUE1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 |
1305 | #define SDMA0_QUEUE1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 |
1306 | #define SDMA0_QUEUE1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa |
1307 | #define SDMA0_QUEUE1_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb |
1308 | #define SDMA0_QUEUE1_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc |
1309 | #define SDMA0_QUEUE1_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 |
1310 | #define SDMA0_QUEUE1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L |
1311 | #define SDMA0_QUEUE1_CONTEXT_STATUS__IDLE_MASK 0x00000004L |
1312 | #define SDMA0_QUEUE1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L |
1313 | #define SDMA0_QUEUE1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L |
1314 | #define SDMA0_QUEUE1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L |
1315 | #define SDMA0_QUEUE1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L |
1316 | #define SDMA0_QUEUE1_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L |
1317 | #define SDMA0_QUEUE1_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L |
1318 | #define SDMA0_QUEUE1_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L |
1319 | //SDMA0_QUEUE1_DOORBELL |
1320 | #define SDMA0_QUEUE1_DOORBELL__ENABLE__SHIFT 0x1c |
1321 | #define SDMA0_QUEUE1_DOORBELL__CAPTURED__SHIFT 0x1e |
1322 | #define SDMA0_QUEUE1_DOORBELL__ENABLE_MASK 0x10000000L |
1323 | #define SDMA0_QUEUE1_DOORBELL__CAPTURED_MASK 0x40000000L |
1324 | //SDMA0_QUEUE1_DOORBELL_LOG |
1325 | #define SDMA0_QUEUE1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 |
1326 | #define SDMA0_QUEUE1_DOORBELL_LOG__DATA__SHIFT 0x2 |
1327 | #define SDMA0_QUEUE1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L |
1328 | #define SDMA0_QUEUE1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL |
1329 | //SDMA0_QUEUE1_DOORBELL_OFFSET |
1330 | #define SDMA0_QUEUE1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 |
1331 | #define SDMA0_QUEUE1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL |
1332 | //SDMA0_QUEUE1_CSA_ADDR_LO |
1333 | #define SDMA0_QUEUE1_CSA_ADDR_LO__ADDR__SHIFT 0x2 |
1334 | #define SDMA0_QUEUE1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
1335 | //SDMA0_QUEUE1_CSA_ADDR_HI |
1336 | #define SDMA0_QUEUE1_CSA_ADDR_HI__ADDR__SHIFT 0x0 |
1337 | #define SDMA0_QUEUE1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
1338 | //SDMA0_QUEUE1_SCHEDULE_CNTL |
1339 | #define SDMA0_QUEUE1_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 |
1340 | #define SDMA0_QUEUE1_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 |
1341 | #define SDMA0_QUEUE1_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 |
1342 | #define SDMA0_QUEUE1_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 |
1343 | #define SDMA0_QUEUE1_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L |
1344 | #define SDMA0_QUEUE1_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL |
1345 | #define SDMA0_QUEUE1_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L |
1346 | #define SDMA0_QUEUE1_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L |
1347 | //SDMA0_QUEUE1_IB_SUB_REMAIN |
1348 | #define SDMA0_QUEUE1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 |
1349 | #define SDMA0_QUEUE1_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL |
1350 | //SDMA0_QUEUE1_PREEMPT |
1351 | #define SDMA0_QUEUE1_PREEMPT__IB_PREEMPT__SHIFT 0x0 |
1352 | #define SDMA0_QUEUE1_PREEMPT__IB_PREEMPT_MASK 0x00000001L |
1353 | //SDMA0_QUEUE1_DUMMY_REG |
1354 | #define SDMA0_QUEUE1_DUMMY_REG__DUMMY__SHIFT 0x0 |
1355 | #define SDMA0_QUEUE1_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL |
1356 | //SDMA0_QUEUE1_RB_WPTR_POLL_ADDR_HI |
1357 | #define SDMA0_QUEUE1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 |
1358 | #define SDMA0_QUEUE1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
1359 | //SDMA0_QUEUE1_RB_WPTR_POLL_ADDR_LO |
1360 | #define SDMA0_QUEUE1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 |
1361 | #define SDMA0_QUEUE1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
1362 | //SDMA0_QUEUE1_RB_AQL_CNTL |
1363 | #define SDMA0_QUEUE1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 |
1364 | #define SDMA0_QUEUE1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 |
1365 | #define SDMA0_QUEUE1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 |
1366 | #define SDMA0_QUEUE1_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 |
1367 | #define SDMA0_QUEUE1_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 |
1368 | #define SDMA0_QUEUE1_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 |
1369 | #define SDMA0_QUEUE1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L |
1370 | #define SDMA0_QUEUE1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL |
1371 | #define SDMA0_QUEUE1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L |
1372 | #define SDMA0_QUEUE1_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L |
1373 | #define SDMA0_QUEUE1_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L |
1374 | #define SDMA0_QUEUE1_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L |
1375 | //SDMA0_QUEUE1_MINOR_PTR_UPDATE |
1376 | #define SDMA0_QUEUE1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 |
1377 | #define SDMA0_QUEUE1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L |
1378 | //SDMA0_QUEUE1_RB_PREEMPT |
1379 | #define SDMA0_QUEUE1_RB_PREEMPT__PREEMPT_REQ__SHIFT 0x0 |
1380 | #define SDMA0_QUEUE1_RB_PREEMPT__PREEMPT_REQ_MASK 0x00000001L |
1381 | //SDMA0_QUEUE1_MIDCMD_DATA0 |
1382 | #define SDMA0_QUEUE1_MIDCMD_DATA0__DATA0__SHIFT 0x0 |
1383 | #define SDMA0_QUEUE1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL |
1384 | //SDMA0_QUEUE1_MIDCMD_DATA1 |
1385 | #define SDMA0_QUEUE1_MIDCMD_DATA1__DATA1__SHIFT 0x0 |
1386 | #define SDMA0_QUEUE1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL |
1387 | //SDMA0_QUEUE1_MIDCMD_DATA2 |
1388 | #define SDMA0_QUEUE1_MIDCMD_DATA2__DATA2__SHIFT 0x0 |
1389 | #define SDMA0_QUEUE1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL |
1390 | //SDMA0_QUEUE1_MIDCMD_DATA3 |
1391 | #define SDMA0_QUEUE1_MIDCMD_DATA3__DATA3__SHIFT 0x0 |
1392 | #define SDMA0_QUEUE1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL |
1393 | //SDMA0_QUEUE1_MIDCMD_DATA4 |
1394 | #define SDMA0_QUEUE1_MIDCMD_DATA4__DATA4__SHIFT 0x0 |
1395 | #define SDMA0_QUEUE1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL |
1396 | //SDMA0_QUEUE1_MIDCMD_DATA5 |
1397 | #define SDMA0_QUEUE1_MIDCMD_DATA5__DATA5__SHIFT 0x0 |
1398 | #define SDMA0_QUEUE1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL |
1399 | //SDMA0_QUEUE1_MIDCMD_DATA6 |
1400 | #define SDMA0_QUEUE1_MIDCMD_DATA6__DATA6__SHIFT 0x0 |
1401 | #define SDMA0_QUEUE1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL |
1402 | //SDMA0_QUEUE1_MIDCMD_DATA7 |
1403 | #define SDMA0_QUEUE1_MIDCMD_DATA7__DATA7__SHIFT 0x0 |
1404 | #define SDMA0_QUEUE1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL |
1405 | //SDMA0_QUEUE1_MIDCMD_DATA8 |
1406 | #define SDMA0_QUEUE1_MIDCMD_DATA8__DATA8__SHIFT 0x0 |
1407 | #define SDMA0_QUEUE1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL |
1408 | //SDMA0_QUEUE1_MIDCMD_DATA9 |
1409 | #define SDMA0_QUEUE1_MIDCMD_DATA9__DATA9__SHIFT 0x0 |
1410 | #define SDMA0_QUEUE1_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL |
1411 | //SDMA0_QUEUE1_MIDCMD_DATA10 |
1412 | #define SDMA0_QUEUE1_MIDCMD_DATA10__DATA10__SHIFT 0x0 |
1413 | #define SDMA0_QUEUE1_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL |
1414 | //SDMA0_QUEUE1_MIDCMD_CNTL |
1415 | #define SDMA0_QUEUE1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 |
1416 | #define SDMA0_QUEUE1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 |
1417 | #define SDMA0_QUEUE1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 |
1418 | #define SDMA0_QUEUE1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 |
1419 | #define SDMA0_QUEUE1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L |
1420 | #define SDMA0_QUEUE1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L |
1421 | #define SDMA0_QUEUE1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L |
1422 | #define SDMA0_QUEUE1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L |
1423 | //SDMA0_QUEUE2_RB_CNTL |
1424 | #define SDMA0_QUEUE2_RB_CNTL__RB_ENABLE__SHIFT 0x0 |
1425 | #define SDMA0_QUEUE2_RB_CNTL__RB_SIZE__SHIFT 0x1 |
1426 | #define SDMA0_QUEUE2_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 |
1427 | #define SDMA0_QUEUE2_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 |
1428 | #define SDMA0_QUEUE2_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa |
1429 | #define SDMA0_QUEUE2_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT 0xb |
1430 | #define SDMA0_QUEUE2_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc |
1431 | #define SDMA0_QUEUE2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd |
1432 | #define SDMA0_QUEUE2_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 |
1433 | #define SDMA0_QUEUE2_RB_CNTL__RB_PRIV__SHIFT 0x17 |
1434 | #define SDMA0_QUEUE2_RB_CNTL__RB_VMID__SHIFT 0x18 |
1435 | #define SDMA0_QUEUE2_RB_CNTL__RB_ENABLE_MASK 0x00000001L |
1436 | #define SDMA0_QUEUE2_RB_CNTL__RB_SIZE_MASK 0x0000003EL |
1437 | #define SDMA0_QUEUE2_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L |
1438 | #define SDMA0_QUEUE2_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L |
1439 | #define SDMA0_QUEUE2_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L |
1440 | #define SDMA0_QUEUE2_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK 0x00000800L |
1441 | #define SDMA0_QUEUE2_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L |
1442 | #define SDMA0_QUEUE2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L |
1443 | #define SDMA0_QUEUE2_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L |
1444 | #define SDMA0_QUEUE2_RB_CNTL__RB_PRIV_MASK 0x00800000L |
1445 | #define SDMA0_QUEUE2_RB_CNTL__RB_VMID_MASK 0x0F000000L |
1446 | //SDMA0_QUEUE2_RB_BASE |
1447 | #define SDMA0_QUEUE2_RB_BASE__ADDR__SHIFT 0x0 |
1448 | #define SDMA0_QUEUE2_RB_BASE__ADDR_MASK 0xFFFFFFFFL |
1449 | //SDMA0_QUEUE2_RB_BASE_HI |
1450 | #define SDMA0_QUEUE2_RB_BASE_HI__ADDR__SHIFT 0x0 |
1451 | #define SDMA0_QUEUE2_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL |
1452 | //SDMA0_QUEUE2_RB_RPTR |
1453 | #define SDMA0_QUEUE2_RB_RPTR__OFFSET__SHIFT 0x0 |
1454 | #define SDMA0_QUEUE2_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL |
1455 | //SDMA0_QUEUE2_RB_RPTR_HI |
1456 | #define SDMA0_QUEUE2_RB_RPTR_HI__OFFSET__SHIFT 0x0 |
1457 | #define SDMA0_QUEUE2_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
1458 | //SDMA0_QUEUE2_RB_WPTR |
1459 | #define SDMA0_QUEUE2_RB_WPTR__OFFSET__SHIFT 0x0 |
1460 | #define SDMA0_QUEUE2_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL |
1461 | //SDMA0_QUEUE2_RB_WPTR_HI |
1462 | #define SDMA0_QUEUE2_RB_WPTR_HI__OFFSET__SHIFT 0x0 |
1463 | #define SDMA0_QUEUE2_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
1464 | //SDMA0_QUEUE2_RB_RPTR_ADDR_HI |
1465 | #define SDMA0_QUEUE2_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 |
1466 | #define SDMA0_QUEUE2_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
1467 | //SDMA0_QUEUE2_RB_RPTR_ADDR_LO |
1468 | #define SDMA0_QUEUE2_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 |
1469 | #define SDMA0_QUEUE2_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
1470 | //SDMA0_QUEUE2_IB_CNTL |
1471 | #define SDMA0_QUEUE2_IB_CNTL__IB_ENABLE__SHIFT 0x0 |
1472 | #define SDMA0_QUEUE2_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 |
1473 | #define SDMA0_QUEUE2_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 |
1474 | #define SDMA0_QUEUE2_IB_CNTL__CMD_VMID__SHIFT 0x10 |
1475 | #define SDMA0_QUEUE2_IB_CNTL__IB_PRIV__SHIFT 0x1f |
1476 | #define SDMA0_QUEUE2_IB_CNTL__IB_ENABLE_MASK 0x00000001L |
1477 | #define SDMA0_QUEUE2_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L |
1478 | #define SDMA0_QUEUE2_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L |
1479 | #define SDMA0_QUEUE2_IB_CNTL__CMD_VMID_MASK 0x000F0000L |
1480 | #define SDMA0_QUEUE2_IB_CNTL__IB_PRIV_MASK 0x80000000L |
1481 | //SDMA0_QUEUE2_IB_RPTR |
1482 | #define SDMA0_QUEUE2_IB_RPTR__OFFSET__SHIFT 0x2 |
1483 | #define SDMA0_QUEUE2_IB_RPTR__OFFSET_MASK 0x003FFFFCL |
1484 | //SDMA0_QUEUE2_IB_OFFSET |
1485 | #define SDMA0_QUEUE2_IB_OFFSET__OFFSET__SHIFT 0x2 |
1486 | #define SDMA0_QUEUE2_IB_OFFSET__OFFSET_MASK 0x003FFFFCL |
1487 | //SDMA0_QUEUE2_IB_BASE_LO |
1488 | #define SDMA0_QUEUE2_IB_BASE_LO__ADDR__SHIFT 0x5 |
1489 | #define SDMA0_QUEUE2_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L |
1490 | //SDMA0_QUEUE2_IB_BASE_HI |
1491 | #define SDMA0_QUEUE2_IB_BASE_HI__ADDR__SHIFT 0x0 |
1492 | #define SDMA0_QUEUE2_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL |
1493 | //SDMA0_QUEUE2_IB_SIZE |
1494 | #define SDMA0_QUEUE2_IB_SIZE__SIZE__SHIFT 0x0 |
1495 | #define SDMA0_QUEUE2_IB_SIZE__SIZE_MASK 0x000FFFFFL |
1496 | //SDMA0_QUEUE2_SKIP_CNTL |
1497 | #define SDMA0_QUEUE2_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 |
1498 | #define SDMA0_QUEUE2_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL |
1499 | //SDMA0_QUEUE2_CONTEXT_STATUS |
1500 | #define SDMA0_QUEUE2_CONTEXT_STATUS__SELECTED__SHIFT 0x0 |
1501 | #define SDMA0_QUEUE2_CONTEXT_STATUS__IDLE__SHIFT 0x2 |
1502 | #define SDMA0_QUEUE2_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 |
1503 | #define SDMA0_QUEUE2_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 |
1504 | #define SDMA0_QUEUE2_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 |
1505 | #define SDMA0_QUEUE2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa |
1506 | #define SDMA0_QUEUE2_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb |
1507 | #define SDMA0_QUEUE2_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc |
1508 | #define SDMA0_QUEUE2_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 |
1509 | #define SDMA0_QUEUE2_CONTEXT_STATUS__SELECTED_MASK 0x00000001L |
1510 | #define SDMA0_QUEUE2_CONTEXT_STATUS__IDLE_MASK 0x00000004L |
1511 | #define SDMA0_QUEUE2_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L |
1512 | #define SDMA0_QUEUE2_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L |
1513 | #define SDMA0_QUEUE2_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L |
1514 | #define SDMA0_QUEUE2_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L |
1515 | #define SDMA0_QUEUE2_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L |
1516 | #define SDMA0_QUEUE2_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L |
1517 | #define SDMA0_QUEUE2_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L |
1518 | //SDMA0_QUEUE2_DOORBELL |
1519 | #define SDMA0_QUEUE2_DOORBELL__ENABLE__SHIFT 0x1c |
1520 | #define SDMA0_QUEUE2_DOORBELL__CAPTURED__SHIFT 0x1e |
1521 | #define SDMA0_QUEUE2_DOORBELL__ENABLE_MASK 0x10000000L |
1522 | #define SDMA0_QUEUE2_DOORBELL__CAPTURED_MASK 0x40000000L |
1523 | //SDMA0_QUEUE2_DOORBELL_LOG |
1524 | #define SDMA0_QUEUE2_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 |
1525 | #define SDMA0_QUEUE2_DOORBELL_LOG__DATA__SHIFT 0x2 |
1526 | #define SDMA0_QUEUE2_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L |
1527 | #define SDMA0_QUEUE2_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL |
1528 | //SDMA0_QUEUE2_DOORBELL_OFFSET |
1529 | #define SDMA0_QUEUE2_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 |
1530 | #define SDMA0_QUEUE2_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL |
1531 | //SDMA0_QUEUE2_CSA_ADDR_LO |
1532 | #define SDMA0_QUEUE2_CSA_ADDR_LO__ADDR__SHIFT 0x2 |
1533 | #define SDMA0_QUEUE2_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
1534 | //SDMA0_QUEUE2_CSA_ADDR_HI |
1535 | #define SDMA0_QUEUE2_CSA_ADDR_HI__ADDR__SHIFT 0x0 |
1536 | #define SDMA0_QUEUE2_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
1537 | //SDMA0_QUEUE2_SCHEDULE_CNTL |
1538 | #define SDMA0_QUEUE2_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 |
1539 | #define SDMA0_QUEUE2_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 |
1540 | #define SDMA0_QUEUE2_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 |
1541 | #define SDMA0_QUEUE2_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 |
1542 | #define SDMA0_QUEUE2_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L |
1543 | #define SDMA0_QUEUE2_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL |
1544 | #define SDMA0_QUEUE2_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L |
1545 | #define SDMA0_QUEUE2_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L |
1546 | //SDMA0_QUEUE2_IB_SUB_REMAIN |
1547 | #define SDMA0_QUEUE2_IB_SUB_REMAIN__SIZE__SHIFT 0x0 |
1548 | #define SDMA0_QUEUE2_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL |
1549 | //SDMA0_QUEUE2_PREEMPT |
1550 | #define SDMA0_QUEUE2_PREEMPT__IB_PREEMPT__SHIFT 0x0 |
1551 | #define SDMA0_QUEUE2_PREEMPT__IB_PREEMPT_MASK 0x00000001L |
1552 | //SDMA0_QUEUE2_DUMMY_REG |
1553 | #define SDMA0_QUEUE2_DUMMY_REG__DUMMY__SHIFT 0x0 |
1554 | #define SDMA0_QUEUE2_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL |
1555 | //SDMA0_QUEUE2_RB_WPTR_POLL_ADDR_HI |
1556 | #define SDMA0_QUEUE2_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 |
1557 | #define SDMA0_QUEUE2_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
1558 | //SDMA0_QUEUE2_RB_WPTR_POLL_ADDR_LO |
1559 | #define SDMA0_QUEUE2_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 |
1560 | #define SDMA0_QUEUE2_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
1561 | //SDMA0_QUEUE2_RB_AQL_CNTL |
1562 | #define SDMA0_QUEUE2_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 |
1563 | #define SDMA0_QUEUE2_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 |
1564 | #define SDMA0_QUEUE2_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 |
1565 | #define SDMA0_QUEUE2_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 |
1566 | #define SDMA0_QUEUE2_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 |
1567 | #define SDMA0_QUEUE2_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 |
1568 | #define SDMA0_QUEUE2_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L |
1569 | #define SDMA0_QUEUE2_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL |
1570 | #define SDMA0_QUEUE2_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L |
1571 | #define SDMA0_QUEUE2_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L |
1572 | #define SDMA0_QUEUE2_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L |
1573 | #define SDMA0_QUEUE2_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L |
1574 | //SDMA0_QUEUE2_MINOR_PTR_UPDATE |
1575 | #define SDMA0_QUEUE2_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 |
1576 | #define SDMA0_QUEUE2_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L |
1577 | //SDMA0_QUEUE2_RB_PREEMPT |
1578 | #define SDMA0_QUEUE2_RB_PREEMPT__PREEMPT_REQ__SHIFT 0x0 |
1579 | #define SDMA0_QUEUE2_RB_PREEMPT__PREEMPT_REQ_MASK 0x00000001L |
1580 | //SDMA0_QUEUE2_MIDCMD_DATA0 |
1581 | #define SDMA0_QUEUE2_MIDCMD_DATA0__DATA0__SHIFT 0x0 |
1582 | #define SDMA0_QUEUE2_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL |
1583 | //SDMA0_QUEUE2_MIDCMD_DATA1 |
1584 | #define SDMA0_QUEUE2_MIDCMD_DATA1__DATA1__SHIFT 0x0 |
1585 | #define SDMA0_QUEUE2_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL |
1586 | //SDMA0_QUEUE2_MIDCMD_DATA2 |
1587 | #define SDMA0_QUEUE2_MIDCMD_DATA2__DATA2__SHIFT 0x0 |
1588 | #define SDMA0_QUEUE2_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL |
1589 | //SDMA0_QUEUE2_MIDCMD_DATA3 |
1590 | #define SDMA0_QUEUE2_MIDCMD_DATA3__DATA3__SHIFT 0x0 |
1591 | #define SDMA0_QUEUE2_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL |
1592 | //SDMA0_QUEUE2_MIDCMD_DATA4 |
1593 | #define SDMA0_QUEUE2_MIDCMD_DATA4__DATA4__SHIFT 0x0 |
1594 | #define SDMA0_QUEUE2_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL |
1595 | //SDMA0_QUEUE2_MIDCMD_DATA5 |
1596 | #define SDMA0_QUEUE2_MIDCMD_DATA5__DATA5__SHIFT 0x0 |
1597 | #define SDMA0_QUEUE2_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL |
1598 | //SDMA0_QUEUE2_MIDCMD_DATA6 |
1599 | #define SDMA0_QUEUE2_MIDCMD_DATA6__DATA6__SHIFT 0x0 |
1600 | #define SDMA0_QUEUE2_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL |
1601 | //SDMA0_QUEUE2_MIDCMD_DATA7 |
1602 | #define SDMA0_QUEUE2_MIDCMD_DATA7__DATA7__SHIFT 0x0 |
1603 | #define SDMA0_QUEUE2_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL |
1604 | //SDMA0_QUEUE2_MIDCMD_DATA8 |
1605 | #define SDMA0_QUEUE2_MIDCMD_DATA8__DATA8__SHIFT 0x0 |
1606 | #define SDMA0_QUEUE2_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL |
1607 | //SDMA0_QUEUE2_MIDCMD_DATA9 |
1608 | #define SDMA0_QUEUE2_MIDCMD_DATA9__DATA9__SHIFT 0x0 |
1609 | #define SDMA0_QUEUE2_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL |
1610 | //SDMA0_QUEUE2_MIDCMD_DATA10 |
1611 | #define SDMA0_QUEUE2_MIDCMD_DATA10__DATA10__SHIFT 0x0 |
1612 | #define SDMA0_QUEUE2_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL |
1613 | //SDMA0_QUEUE2_MIDCMD_CNTL |
1614 | #define SDMA0_QUEUE2_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 |
1615 | #define SDMA0_QUEUE2_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 |
1616 | #define SDMA0_QUEUE2_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 |
1617 | #define SDMA0_QUEUE2_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 |
1618 | #define SDMA0_QUEUE2_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L |
1619 | #define SDMA0_QUEUE2_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L |
1620 | #define SDMA0_QUEUE2_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L |
1621 | #define SDMA0_QUEUE2_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L |
1622 | //SDMA0_QUEUE3_RB_CNTL |
1623 | #define SDMA0_QUEUE3_RB_CNTL__RB_ENABLE__SHIFT 0x0 |
1624 | #define SDMA0_QUEUE3_RB_CNTL__RB_SIZE__SHIFT 0x1 |
1625 | #define SDMA0_QUEUE3_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 |
1626 | #define SDMA0_QUEUE3_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 |
1627 | #define SDMA0_QUEUE3_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa |
1628 | #define SDMA0_QUEUE3_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT 0xb |
1629 | #define SDMA0_QUEUE3_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc |
1630 | #define SDMA0_QUEUE3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd |
1631 | #define SDMA0_QUEUE3_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 |
1632 | #define SDMA0_QUEUE3_RB_CNTL__RB_PRIV__SHIFT 0x17 |
1633 | #define SDMA0_QUEUE3_RB_CNTL__RB_VMID__SHIFT 0x18 |
1634 | #define SDMA0_QUEUE3_RB_CNTL__RB_ENABLE_MASK 0x00000001L |
1635 | #define SDMA0_QUEUE3_RB_CNTL__RB_SIZE_MASK 0x0000003EL |
1636 | #define SDMA0_QUEUE3_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L |
1637 | #define SDMA0_QUEUE3_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L |
1638 | #define SDMA0_QUEUE3_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L |
1639 | #define SDMA0_QUEUE3_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK 0x00000800L |
1640 | #define SDMA0_QUEUE3_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L |
1641 | #define SDMA0_QUEUE3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L |
1642 | #define SDMA0_QUEUE3_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L |
1643 | #define SDMA0_QUEUE3_RB_CNTL__RB_PRIV_MASK 0x00800000L |
1644 | #define SDMA0_QUEUE3_RB_CNTL__RB_VMID_MASK 0x0F000000L |
1645 | //SDMA0_QUEUE3_RB_BASE |
1646 | #define SDMA0_QUEUE3_RB_BASE__ADDR__SHIFT 0x0 |
1647 | #define SDMA0_QUEUE3_RB_BASE__ADDR_MASK 0xFFFFFFFFL |
1648 | //SDMA0_QUEUE3_RB_BASE_HI |
1649 | #define SDMA0_QUEUE3_RB_BASE_HI__ADDR__SHIFT 0x0 |
1650 | #define SDMA0_QUEUE3_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL |
1651 | //SDMA0_QUEUE3_RB_RPTR |
1652 | #define SDMA0_QUEUE3_RB_RPTR__OFFSET__SHIFT 0x0 |
1653 | #define SDMA0_QUEUE3_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL |
1654 | //SDMA0_QUEUE3_RB_RPTR_HI |
1655 | #define SDMA0_QUEUE3_RB_RPTR_HI__OFFSET__SHIFT 0x0 |
1656 | #define SDMA0_QUEUE3_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
1657 | //SDMA0_QUEUE3_RB_WPTR |
1658 | #define SDMA0_QUEUE3_RB_WPTR__OFFSET__SHIFT 0x0 |
1659 | #define SDMA0_QUEUE3_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL |
1660 | //SDMA0_QUEUE3_RB_WPTR_HI |
1661 | #define SDMA0_QUEUE3_RB_WPTR_HI__OFFSET__SHIFT 0x0 |
1662 | #define SDMA0_QUEUE3_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
1663 | //SDMA0_QUEUE3_RB_RPTR_ADDR_HI |
1664 | #define SDMA0_QUEUE3_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 |
1665 | #define SDMA0_QUEUE3_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
1666 | //SDMA0_QUEUE3_RB_RPTR_ADDR_LO |
1667 | #define SDMA0_QUEUE3_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 |
1668 | #define SDMA0_QUEUE3_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
1669 | //SDMA0_QUEUE3_IB_CNTL |
1670 | #define SDMA0_QUEUE3_IB_CNTL__IB_ENABLE__SHIFT 0x0 |
1671 | #define SDMA0_QUEUE3_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 |
1672 | #define SDMA0_QUEUE3_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 |
1673 | #define SDMA0_QUEUE3_IB_CNTL__CMD_VMID__SHIFT 0x10 |
1674 | #define SDMA0_QUEUE3_IB_CNTL__IB_PRIV__SHIFT 0x1f |
1675 | #define SDMA0_QUEUE3_IB_CNTL__IB_ENABLE_MASK 0x00000001L |
1676 | #define SDMA0_QUEUE3_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L |
1677 | #define SDMA0_QUEUE3_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L |
1678 | #define SDMA0_QUEUE3_IB_CNTL__CMD_VMID_MASK 0x000F0000L |
1679 | #define SDMA0_QUEUE3_IB_CNTL__IB_PRIV_MASK 0x80000000L |
1680 | //SDMA0_QUEUE3_IB_RPTR |
1681 | #define SDMA0_QUEUE3_IB_RPTR__OFFSET__SHIFT 0x2 |
1682 | #define SDMA0_QUEUE3_IB_RPTR__OFFSET_MASK 0x003FFFFCL |
1683 | //SDMA0_QUEUE3_IB_OFFSET |
1684 | #define SDMA0_QUEUE3_IB_OFFSET__OFFSET__SHIFT 0x2 |
1685 | #define SDMA0_QUEUE3_IB_OFFSET__OFFSET_MASK 0x003FFFFCL |
1686 | //SDMA0_QUEUE3_IB_BASE_LO |
1687 | #define SDMA0_QUEUE3_IB_BASE_LO__ADDR__SHIFT 0x5 |
1688 | #define SDMA0_QUEUE3_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L |
1689 | //SDMA0_QUEUE3_IB_BASE_HI |
1690 | #define SDMA0_QUEUE3_IB_BASE_HI__ADDR__SHIFT 0x0 |
1691 | #define SDMA0_QUEUE3_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL |
1692 | //SDMA0_QUEUE3_IB_SIZE |
1693 | #define SDMA0_QUEUE3_IB_SIZE__SIZE__SHIFT 0x0 |
1694 | #define SDMA0_QUEUE3_IB_SIZE__SIZE_MASK 0x000FFFFFL |
1695 | //SDMA0_QUEUE3_SKIP_CNTL |
1696 | #define SDMA0_QUEUE3_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 |
1697 | #define SDMA0_QUEUE3_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL |
1698 | //SDMA0_QUEUE3_CONTEXT_STATUS |
1699 | #define SDMA0_QUEUE3_CONTEXT_STATUS__SELECTED__SHIFT 0x0 |
1700 | #define SDMA0_QUEUE3_CONTEXT_STATUS__IDLE__SHIFT 0x2 |
1701 | #define SDMA0_QUEUE3_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 |
1702 | #define SDMA0_QUEUE3_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 |
1703 | #define SDMA0_QUEUE3_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 |
1704 | #define SDMA0_QUEUE3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa |
1705 | #define SDMA0_QUEUE3_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb |
1706 | #define SDMA0_QUEUE3_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc |
1707 | #define SDMA0_QUEUE3_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 |
1708 | #define SDMA0_QUEUE3_CONTEXT_STATUS__SELECTED_MASK 0x00000001L |
1709 | #define SDMA0_QUEUE3_CONTEXT_STATUS__IDLE_MASK 0x00000004L |
1710 | #define SDMA0_QUEUE3_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L |
1711 | #define SDMA0_QUEUE3_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L |
1712 | #define SDMA0_QUEUE3_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L |
1713 | #define SDMA0_QUEUE3_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L |
1714 | #define SDMA0_QUEUE3_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L |
1715 | #define SDMA0_QUEUE3_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L |
1716 | #define SDMA0_QUEUE3_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L |
1717 | //SDMA0_QUEUE3_DOORBELL |
1718 | #define SDMA0_QUEUE3_DOORBELL__ENABLE__SHIFT 0x1c |
1719 | #define SDMA0_QUEUE3_DOORBELL__CAPTURED__SHIFT 0x1e |
1720 | #define SDMA0_QUEUE3_DOORBELL__ENABLE_MASK 0x10000000L |
1721 | #define SDMA0_QUEUE3_DOORBELL__CAPTURED_MASK 0x40000000L |
1722 | //SDMA0_QUEUE3_DOORBELL_LOG |
1723 | #define SDMA0_QUEUE3_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 |
1724 | #define SDMA0_QUEUE3_DOORBELL_LOG__DATA__SHIFT 0x2 |
1725 | #define SDMA0_QUEUE3_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L |
1726 | #define SDMA0_QUEUE3_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL |
1727 | //SDMA0_QUEUE3_DOORBELL_OFFSET |
1728 | #define SDMA0_QUEUE3_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 |
1729 | #define SDMA0_QUEUE3_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL |
1730 | //SDMA0_QUEUE3_CSA_ADDR_LO |
1731 | #define SDMA0_QUEUE3_CSA_ADDR_LO__ADDR__SHIFT 0x2 |
1732 | #define SDMA0_QUEUE3_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
1733 | //SDMA0_QUEUE3_CSA_ADDR_HI |
1734 | #define SDMA0_QUEUE3_CSA_ADDR_HI__ADDR__SHIFT 0x0 |
1735 | #define SDMA0_QUEUE3_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
1736 | //SDMA0_QUEUE3_SCHEDULE_CNTL |
1737 | #define SDMA0_QUEUE3_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 |
1738 | #define SDMA0_QUEUE3_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 |
1739 | #define SDMA0_QUEUE3_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 |
1740 | #define SDMA0_QUEUE3_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 |
1741 | #define SDMA0_QUEUE3_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L |
1742 | #define SDMA0_QUEUE3_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL |
1743 | #define SDMA0_QUEUE3_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L |
1744 | #define SDMA0_QUEUE3_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L |
1745 | //SDMA0_QUEUE3_IB_SUB_REMAIN |
1746 | #define SDMA0_QUEUE3_IB_SUB_REMAIN__SIZE__SHIFT 0x0 |
1747 | #define SDMA0_QUEUE3_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL |
1748 | //SDMA0_QUEUE3_PREEMPT |
1749 | #define SDMA0_QUEUE3_PREEMPT__IB_PREEMPT__SHIFT 0x0 |
1750 | #define SDMA0_QUEUE3_PREEMPT__IB_PREEMPT_MASK 0x00000001L |
1751 | //SDMA0_QUEUE3_DUMMY_REG |
1752 | #define SDMA0_QUEUE3_DUMMY_REG__DUMMY__SHIFT 0x0 |
1753 | #define SDMA0_QUEUE3_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL |
1754 | //SDMA0_QUEUE3_RB_WPTR_POLL_ADDR_HI |
1755 | #define SDMA0_QUEUE3_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 |
1756 | #define SDMA0_QUEUE3_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
1757 | //SDMA0_QUEUE3_RB_WPTR_POLL_ADDR_LO |
1758 | #define SDMA0_QUEUE3_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 |
1759 | #define SDMA0_QUEUE3_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
1760 | //SDMA0_QUEUE3_RB_AQL_CNTL |
1761 | #define SDMA0_QUEUE3_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 |
1762 | #define SDMA0_QUEUE3_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 |
1763 | #define SDMA0_QUEUE3_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 |
1764 | #define SDMA0_QUEUE3_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 |
1765 | #define SDMA0_QUEUE3_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 |
1766 | #define SDMA0_QUEUE3_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 |
1767 | #define SDMA0_QUEUE3_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L |
1768 | #define SDMA0_QUEUE3_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL |
1769 | #define SDMA0_QUEUE3_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L |
1770 | #define SDMA0_QUEUE3_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L |
1771 | #define SDMA0_QUEUE3_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L |
1772 | #define SDMA0_QUEUE3_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L |
1773 | //SDMA0_QUEUE3_MINOR_PTR_UPDATE |
1774 | #define SDMA0_QUEUE3_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 |
1775 | #define SDMA0_QUEUE3_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L |
1776 | //SDMA0_QUEUE3_RB_PREEMPT |
1777 | #define SDMA0_QUEUE3_RB_PREEMPT__PREEMPT_REQ__SHIFT 0x0 |
1778 | #define SDMA0_QUEUE3_RB_PREEMPT__PREEMPT_REQ_MASK 0x00000001L |
1779 | //SDMA0_QUEUE3_MIDCMD_DATA0 |
1780 | #define SDMA0_QUEUE3_MIDCMD_DATA0__DATA0__SHIFT 0x0 |
1781 | #define SDMA0_QUEUE3_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL |
1782 | //SDMA0_QUEUE3_MIDCMD_DATA1 |
1783 | #define SDMA0_QUEUE3_MIDCMD_DATA1__DATA1__SHIFT 0x0 |
1784 | #define SDMA0_QUEUE3_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL |
1785 | //SDMA0_QUEUE3_MIDCMD_DATA2 |
1786 | #define SDMA0_QUEUE3_MIDCMD_DATA2__DATA2__SHIFT 0x0 |
1787 | #define SDMA0_QUEUE3_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL |
1788 | //SDMA0_QUEUE3_MIDCMD_DATA3 |
1789 | #define SDMA0_QUEUE3_MIDCMD_DATA3__DATA3__SHIFT 0x0 |
1790 | #define SDMA0_QUEUE3_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL |
1791 | //SDMA0_QUEUE3_MIDCMD_DATA4 |
1792 | #define SDMA0_QUEUE3_MIDCMD_DATA4__DATA4__SHIFT 0x0 |
1793 | #define SDMA0_QUEUE3_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL |
1794 | //SDMA0_QUEUE3_MIDCMD_DATA5 |
1795 | #define SDMA0_QUEUE3_MIDCMD_DATA5__DATA5__SHIFT 0x0 |
1796 | #define SDMA0_QUEUE3_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL |
1797 | //SDMA0_QUEUE3_MIDCMD_DATA6 |
1798 | #define SDMA0_QUEUE3_MIDCMD_DATA6__DATA6__SHIFT 0x0 |
1799 | #define SDMA0_QUEUE3_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL |
1800 | //SDMA0_QUEUE3_MIDCMD_DATA7 |
1801 | #define SDMA0_QUEUE3_MIDCMD_DATA7__DATA7__SHIFT 0x0 |
1802 | #define SDMA0_QUEUE3_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL |
1803 | //SDMA0_QUEUE3_MIDCMD_DATA8 |
1804 | #define SDMA0_QUEUE3_MIDCMD_DATA8__DATA8__SHIFT 0x0 |
1805 | #define SDMA0_QUEUE3_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL |
1806 | //SDMA0_QUEUE3_MIDCMD_DATA9 |
1807 | #define SDMA0_QUEUE3_MIDCMD_DATA9__DATA9__SHIFT 0x0 |
1808 | #define SDMA0_QUEUE3_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL |
1809 | //SDMA0_QUEUE3_MIDCMD_DATA10 |
1810 | #define SDMA0_QUEUE3_MIDCMD_DATA10__DATA10__SHIFT 0x0 |
1811 | #define SDMA0_QUEUE3_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL |
1812 | //SDMA0_QUEUE3_MIDCMD_CNTL |
1813 | #define SDMA0_QUEUE3_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 |
1814 | #define SDMA0_QUEUE3_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 |
1815 | #define SDMA0_QUEUE3_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 |
1816 | #define SDMA0_QUEUE3_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 |
1817 | #define SDMA0_QUEUE3_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L |
1818 | #define SDMA0_QUEUE3_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L |
1819 | #define SDMA0_QUEUE3_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L |
1820 | #define SDMA0_QUEUE3_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L |
1821 | //SDMA0_QUEUE4_RB_CNTL |
1822 | #define SDMA0_QUEUE4_RB_CNTL__RB_ENABLE__SHIFT 0x0 |
1823 | #define SDMA0_QUEUE4_RB_CNTL__RB_SIZE__SHIFT 0x1 |
1824 | #define SDMA0_QUEUE4_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 |
1825 | #define SDMA0_QUEUE4_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 |
1826 | #define SDMA0_QUEUE4_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa |
1827 | #define SDMA0_QUEUE4_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT 0xb |
1828 | #define SDMA0_QUEUE4_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc |
1829 | #define SDMA0_QUEUE4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd |
1830 | #define SDMA0_QUEUE4_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 |
1831 | #define SDMA0_QUEUE4_RB_CNTL__RB_PRIV__SHIFT 0x17 |
1832 | #define SDMA0_QUEUE4_RB_CNTL__RB_VMID__SHIFT 0x18 |
1833 | #define SDMA0_QUEUE4_RB_CNTL__RB_ENABLE_MASK 0x00000001L |
1834 | #define SDMA0_QUEUE4_RB_CNTL__RB_SIZE_MASK 0x0000003EL |
1835 | #define SDMA0_QUEUE4_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L |
1836 | #define SDMA0_QUEUE4_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L |
1837 | #define SDMA0_QUEUE4_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L |
1838 | #define SDMA0_QUEUE4_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK 0x00000800L |
1839 | #define SDMA0_QUEUE4_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L |
1840 | #define SDMA0_QUEUE4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L |
1841 | #define SDMA0_QUEUE4_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L |
1842 | #define SDMA0_QUEUE4_RB_CNTL__RB_PRIV_MASK 0x00800000L |
1843 | #define SDMA0_QUEUE4_RB_CNTL__RB_VMID_MASK 0x0F000000L |
1844 | //SDMA0_QUEUE4_RB_BASE |
1845 | #define SDMA0_QUEUE4_RB_BASE__ADDR__SHIFT 0x0 |
1846 | #define SDMA0_QUEUE4_RB_BASE__ADDR_MASK 0xFFFFFFFFL |
1847 | //SDMA0_QUEUE4_RB_BASE_HI |
1848 | #define SDMA0_QUEUE4_RB_BASE_HI__ADDR__SHIFT 0x0 |
1849 | #define SDMA0_QUEUE4_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL |
1850 | //SDMA0_QUEUE4_RB_RPTR |
1851 | #define SDMA0_QUEUE4_RB_RPTR__OFFSET__SHIFT 0x0 |
1852 | #define SDMA0_QUEUE4_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL |
1853 | //SDMA0_QUEUE4_RB_RPTR_HI |
1854 | #define SDMA0_QUEUE4_RB_RPTR_HI__OFFSET__SHIFT 0x0 |
1855 | #define SDMA0_QUEUE4_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
1856 | //SDMA0_QUEUE4_RB_WPTR |
1857 | #define SDMA0_QUEUE4_RB_WPTR__OFFSET__SHIFT 0x0 |
1858 | #define SDMA0_QUEUE4_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL |
1859 | //SDMA0_QUEUE4_RB_WPTR_HI |
1860 | #define SDMA0_QUEUE4_RB_WPTR_HI__OFFSET__SHIFT 0x0 |
1861 | #define SDMA0_QUEUE4_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
1862 | //SDMA0_QUEUE4_RB_RPTR_ADDR_HI |
1863 | #define SDMA0_QUEUE4_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 |
1864 | #define SDMA0_QUEUE4_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
1865 | //SDMA0_QUEUE4_RB_RPTR_ADDR_LO |
1866 | #define SDMA0_QUEUE4_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 |
1867 | #define SDMA0_QUEUE4_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
1868 | //SDMA0_QUEUE4_IB_CNTL |
1869 | #define SDMA0_QUEUE4_IB_CNTL__IB_ENABLE__SHIFT 0x0 |
1870 | #define SDMA0_QUEUE4_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 |
1871 | #define SDMA0_QUEUE4_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 |
1872 | #define SDMA0_QUEUE4_IB_CNTL__CMD_VMID__SHIFT 0x10 |
1873 | #define SDMA0_QUEUE4_IB_CNTL__IB_PRIV__SHIFT 0x1f |
1874 | #define SDMA0_QUEUE4_IB_CNTL__IB_ENABLE_MASK 0x00000001L |
1875 | #define SDMA0_QUEUE4_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L |
1876 | #define SDMA0_QUEUE4_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L |
1877 | #define SDMA0_QUEUE4_IB_CNTL__CMD_VMID_MASK 0x000F0000L |
1878 | #define SDMA0_QUEUE4_IB_CNTL__IB_PRIV_MASK 0x80000000L |
1879 | //SDMA0_QUEUE4_IB_RPTR |
1880 | #define SDMA0_QUEUE4_IB_RPTR__OFFSET__SHIFT 0x2 |
1881 | #define SDMA0_QUEUE4_IB_RPTR__OFFSET_MASK 0x003FFFFCL |
1882 | //SDMA0_QUEUE4_IB_OFFSET |
1883 | #define SDMA0_QUEUE4_IB_OFFSET__OFFSET__SHIFT 0x2 |
1884 | #define SDMA0_QUEUE4_IB_OFFSET__OFFSET_MASK 0x003FFFFCL |
1885 | //SDMA0_QUEUE4_IB_BASE_LO |
1886 | #define SDMA0_QUEUE4_IB_BASE_LO__ADDR__SHIFT 0x5 |
1887 | #define SDMA0_QUEUE4_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L |
1888 | //SDMA0_QUEUE4_IB_BASE_HI |
1889 | #define SDMA0_QUEUE4_IB_BASE_HI__ADDR__SHIFT 0x0 |
1890 | #define SDMA0_QUEUE4_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL |
1891 | //SDMA0_QUEUE4_IB_SIZE |
1892 | #define SDMA0_QUEUE4_IB_SIZE__SIZE__SHIFT 0x0 |
1893 | #define SDMA0_QUEUE4_IB_SIZE__SIZE_MASK 0x000FFFFFL |
1894 | //SDMA0_QUEUE4_SKIP_CNTL |
1895 | #define SDMA0_QUEUE4_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 |
1896 | #define SDMA0_QUEUE4_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL |
1897 | //SDMA0_QUEUE4_CONTEXT_STATUS |
1898 | #define SDMA0_QUEUE4_CONTEXT_STATUS__SELECTED__SHIFT 0x0 |
1899 | #define SDMA0_QUEUE4_CONTEXT_STATUS__IDLE__SHIFT 0x2 |
1900 | #define SDMA0_QUEUE4_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 |
1901 | #define SDMA0_QUEUE4_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 |
1902 | #define SDMA0_QUEUE4_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 |
1903 | #define SDMA0_QUEUE4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa |
1904 | #define SDMA0_QUEUE4_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb |
1905 | #define SDMA0_QUEUE4_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc |
1906 | #define SDMA0_QUEUE4_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 |
1907 | #define SDMA0_QUEUE4_CONTEXT_STATUS__SELECTED_MASK 0x00000001L |
1908 | #define SDMA0_QUEUE4_CONTEXT_STATUS__IDLE_MASK 0x00000004L |
1909 | #define SDMA0_QUEUE4_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L |
1910 | #define SDMA0_QUEUE4_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L |
1911 | #define SDMA0_QUEUE4_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L |
1912 | #define SDMA0_QUEUE4_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L |
1913 | #define SDMA0_QUEUE4_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L |
1914 | #define SDMA0_QUEUE4_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L |
1915 | #define SDMA0_QUEUE4_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L |
1916 | //SDMA0_QUEUE4_DOORBELL |
1917 | #define SDMA0_QUEUE4_DOORBELL__ENABLE__SHIFT 0x1c |
1918 | #define SDMA0_QUEUE4_DOORBELL__CAPTURED__SHIFT 0x1e |
1919 | #define SDMA0_QUEUE4_DOORBELL__ENABLE_MASK 0x10000000L |
1920 | #define SDMA0_QUEUE4_DOORBELL__CAPTURED_MASK 0x40000000L |
1921 | //SDMA0_QUEUE4_DOORBELL_LOG |
1922 | #define SDMA0_QUEUE4_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 |
1923 | #define SDMA0_QUEUE4_DOORBELL_LOG__DATA__SHIFT 0x2 |
1924 | #define SDMA0_QUEUE4_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L |
1925 | #define SDMA0_QUEUE4_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL |
1926 | //SDMA0_QUEUE4_DOORBELL_OFFSET |
1927 | #define SDMA0_QUEUE4_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 |
1928 | #define SDMA0_QUEUE4_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL |
1929 | //SDMA0_QUEUE4_CSA_ADDR_LO |
1930 | #define SDMA0_QUEUE4_CSA_ADDR_LO__ADDR__SHIFT 0x2 |
1931 | #define SDMA0_QUEUE4_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
1932 | //SDMA0_QUEUE4_CSA_ADDR_HI |
1933 | #define SDMA0_QUEUE4_CSA_ADDR_HI__ADDR__SHIFT 0x0 |
1934 | #define SDMA0_QUEUE4_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
1935 | //SDMA0_QUEUE4_SCHEDULE_CNTL |
1936 | #define SDMA0_QUEUE4_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 |
1937 | #define SDMA0_QUEUE4_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 |
1938 | #define SDMA0_QUEUE4_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 |
1939 | #define SDMA0_QUEUE4_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 |
1940 | #define SDMA0_QUEUE4_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L |
1941 | #define SDMA0_QUEUE4_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL |
1942 | #define SDMA0_QUEUE4_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L |
1943 | #define SDMA0_QUEUE4_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L |
1944 | //SDMA0_QUEUE4_IB_SUB_REMAIN |
1945 | #define SDMA0_QUEUE4_IB_SUB_REMAIN__SIZE__SHIFT 0x0 |
1946 | #define SDMA0_QUEUE4_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL |
1947 | //SDMA0_QUEUE4_PREEMPT |
1948 | #define SDMA0_QUEUE4_PREEMPT__IB_PREEMPT__SHIFT 0x0 |
1949 | #define SDMA0_QUEUE4_PREEMPT__IB_PREEMPT_MASK 0x00000001L |
1950 | //SDMA0_QUEUE4_DUMMY_REG |
1951 | #define SDMA0_QUEUE4_DUMMY_REG__DUMMY__SHIFT 0x0 |
1952 | #define SDMA0_QUEUE4_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL |
1953 | //SDMA0_QUEUE4_RB_WPTR_POLL_ADDR_HI |
1954 | #define SDMA0_QUEUE4_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 |
1955 | #define SDMA0_QUEUE4_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
1956 | //SDMA0_QUEUE4_RB_WPTR_POLL_ADDR_LO |
1957 | #define SDMA0_QUEUE4_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 |
1958 | #define SDMA0_QUEUE4_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
1959 | //SDMA0_QUEUE4_RB_AQL_CNTL |
1960 | #define SDMA0_QUEUE4_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 |
1961 | #define SDMA0_QUEUE4_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 |
1962 | #define SDMA0_QUEUE4_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 |
1963 | #define SDMA0_QUEUE4_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 |
1964 | #define SDMA0_QUEUE4_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 |
1965 | #define SDMA0_QUEUE4_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 |
1966 | #define SDMA0_QUEUE4_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L |
1967 | #define SDMA0_QUEUE4_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL |
1968 | #define SDMA0_QUEUE4_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L |
1969 | #define SDMA0_QUEUE4_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L |
1970 | #define SDMA0_QUEUE4_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L |
1971 | #define SDMA0_QUEUE4_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L |
1972 | //SDMA0_QUEUE4_MINOR_PTR_UPDATE |
1973 | #define SDMA0_QUEUE4_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 |
1974 | #define SDMA0_QUEUE4_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L |
1975 | //SDMA0_QUEUE4_RB_PREEMPT |
1976 | #define SDMA0_QUEUE4_RB_PREEMPT__PREEMPT_REQ__SHIFT 0x0 |
1977 | #define SDMA0_QUEUE4_RB_PREEMPT__PREEMPT_REQ_MASK 0x00000001L |
1978 | //SDMA0_QUEUE4_MIDCMD_DATA0 |
1979 | #define SDMA0_QUEUE4_MIDCMD_DATA0__DATA0__SHIFT 0x0 |
1980 | #define SDMA0_QUEUE4_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL |
1981 | //SDMA0_QUEUE4_MIDCMD_DATA1 |
1982 | #define SDMA0_QUEUE4_MIDCMD_DATA1__DATA1__SHIFT 0x0 |
1983 | #define SDMA0_QUEUE4_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL |
1984 | //SDMA0_QUEUE4_MIDCMD_DATA2 |
1985 | #define SDMA0_QUEUE4_MIDCMD_DATA2__DATA2__SHIFT 0x0 |
1986 | #define SDMA0_QUEUE4_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL |
1987 | //SDMA0_QUEUE4_MIDCMD_DATA3 |
1988 | #define SDMA0_QUEUE4_MIDCMD_DATA3__DATA3__SHIFT 0x0 |
1989 | #define SDMA0_QUEUE4_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL |
1990 | //SDMA0_QUEUE4_MIDCMD_DATA4 |
1991 | #define SDMA0_QUEUE4_MIDCMD_DATA4__DATA4__SHIFT 0x0 |
1992 | #define SDMA0_QUEUE4_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL |
1993 | //SDMA0_QUEUE4_MIDCMD_DATA5 |
1994 | #define SDMA0_QUEUE4_MIDCMD_DATA5__DATA5__SHIFT 0x0 |
1995 | #define SDMA0_QUEUE4_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL |
1996 | //SDMA0_QUEUE4_MIDCMD_DATA6 |
1997 | #define SDMA0_QUEUE4_MIDCMD_DATA6__DATA6__SHIFT 0x0 |
1998 | #define SDMA0_QUEUE4_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL |
1999 | //SDMA0_QUEUE4_MIDCMD_DATA7 |
2000 | #define SDMA0_QUEUE4_MIDCMD_DATA7__DATA7__SHIFT 0x0 |
2001 | #define SDMA0_QUEUE4_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL |
2002 | //SDMA0_QUEUE4_MIDCMD_DATA8 |
2003 | #define SDMA0_QUEUE4_MIDCMD_DATA8__DATA8__SHIFT 0x0 |
2004 | #define SDMA0_QUEUE4_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL |
2005 | //SDMA0_QUEUE4_MIDCMD_DATA9 |
2006 | #define SDMA0_QUEUE4_MIDCMD_DATA9__DATA9__SHIFT 0x0 |
2007 | #define SDMA0_QUEUE4_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL |
2008 | //SDMA0_QUEUE4_MIDCMD_DATA10 |
2009 | #define SDMA0_QUEUE4_MIDCMD_DATA10__DATA10__SHIFT 0x0 |
2010 | #define SDMA0_QUEUE4_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL |
2011 | //SDMA0_QUEUE4_MIDCMD_CNTL |
2012 | #define SDMA0_QUEUE4_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 |
2013 | #define SDMA0_QUEUE4_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 |
2014 | #define SDMA0_QUEUE4_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 |
2015 | #define SDMA0_QUEUE4_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 |
2016 | #define SDMA0_QUEUE4_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L |
2017 | #define SDMA0_QUEUE4_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L |
2018 | #define SDMA0_QUEUE4_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L |
2019 | #define SDMA0_QUEUE4_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L |
2020 | //SDMA0_QUEUE5_RB_CNTL |
2021 | #define SDMA0_QUEUE5_RB_CNTL__RB_ENABLE__SHIFT 0x0 |
2022 | #define SDMA0_QUEUE5_RB_CNTL__RB_SIZE__SHIFT 0x1 |
2023 | #define SDMA0_QUEUE5_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 |
2024 | #define SDMA0_QUEUE5_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 |
2025 | #define SDMA0_QUEUE5_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa |
2026 | #define SDMA0_QUEUE5_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT 0xb |
2027 | #define SDMA0_QUEUE5_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc |
2028 | #define SDMA0_QUEUE5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd |
2029 | #define SDMA0_QUEUE5_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 |
2030 | #define SDMA0_QUEUE5_RB_CNTL__RB_PRIV__SHIFT 0x17 |
2031 | #define SDMA0_QUEUE5_RB_CNTL__RB_VMID__SHIFT 0x18 |
2032 | #define SDMA0_QUEUE5_RB_CNTL__RB_ENABLE_MASK 0x00000001L |
2033 | #define SDMA0_QUEUE5_RB_CNTL__RB_SIZE_MASK 0x0000003EL |
2034 | #define SDMA0_QUEUE5_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L |
2035 | #define SDMA0_QUEUE5_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L |
2036 | #define SDMA0_QUEUE5_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L |
2037 | #define SDMA0_QUEUE5_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK 0x00000800L |
2038 | #define SDMA0_QUEUE5_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L |
2039 | #define SDMA0_QUEUE5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L |
2040 | #define SDMA0_QUEUE5_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L |
2041 | #define SDMA0_QUEUE5_RB_CNTL__RB_PRIV_MASK 0x00800000L |
2042 | #define SDMA0_QUEUE5_RB_CNTL__RB_VMID_MASK 0x0F000000L |
2043 | //SDMA0_QUEUE5_RB_BASE |
2044 | #define SDMA0_QUEUE5_RB_BASE__ADDR__SHIFT 0x0 |
2045 | #define SDMA0_QUEUE5_RB_BASE__ADDR_MASK 0xFFFFFFFFL |
2046 | //SDMA0_QUEUE5_RB_BASE_HI |
2047 | #define SDMA0_QUEUE5_RB_BASE_HI__ADDR__SHIFT 0x0 |
2048 | #define SDMA0_QUEUE5_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL |
2049 | //SDMA0_QUEUE5_RB_RPTR |
2050 | #define SDMA0_QUEUE5_RB_RPTR__OFFSET__SHIFT 0x0 |
2051 | #define SDMA0_QUEUE5_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL |
2052 | //SDMA0_QUEUE5_RB_RPTR_HI |
2053 | #define SDMA0_QUEUE5_RB_RPTR_HI__OFFSET__SHIFT 0x0 |
2054 | #define SDMA0_QUEUE5_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
2055 | //SDMA0_QUEUE5_RB_WPTR |
2056 | #define SDMA0_QUEUE5_RB_WPTR__OFFSET__SHIFT 0x0 |
2057 | #define SDMA0_QUEUE5_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL |
2058 | //SDMA0_QUEUE5_RB_WPTR_HI |
2059 | #define SDMA0_QUEUE5_RB_WPTR_HI__OFFSET__SHIFT 0x0 |
2060 | #define SDMA0_QUEUE5_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
2061 | //SDMA0_QUEUE5_RB_RPTR_ADDR_HI |
2062 | #define SDMA0_QUEUE5_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 |
2063 | #define SDMA0_QUEUE5_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
2064 | //SDMA0_QUEUE5_RB_RPTR_ADDR_LO |
2065 | #define SDMA0_QUEUE5_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 |
2066 | #define SDMA0_QUEUE5_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
2067 | //SDMA0_QUEUE5_IB_CNTL |
2068 | #define SDMA0_QUEUE5_IB_CNTL__IB_ENABLE__SHIFT 0x0 |
2069 | #define SDMA0_QUEUE5_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 |
2070 | #define SDMA0_QUEUE5_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 |
2071 | #define SDMA0_QUEUE5_IB_CNTL__CMD_VMID__SHIFT 0x10 |
2072 | #define SDMA0_QUEUE5_IB_CNTL__IB_PRIV__SHIFT 0x1f |
2073 | #define SDMA0_QUEUE5_IB_CNTL__IB_ENABLE_MASK 0x00000001L |
2074 | #define SDMA0_QUEUE5_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L |
2075 | #define SDMA0_QUEUE5_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L |
2076 | #define SDMA0_QUEUE5_IB_CNTL__CMD_VMID_MASK 0x000F0000L |
2077 | #define SDMA0_QUEUE5_IB_CNTL__IB_PRIV_MASK 0x80000000L |
2078 | //SDMA0_QUEUE5_IB_RPTR |
2079 | #define SDMA0_QUEUE5_IB_RPTR__OFFSET__SHIFT 0x2 |
2080 | #define SDMA0_QUEUE5_IB_RPTR__OFFSET_MASK 0x003FFFFCL |
2081 | //SDMA0_QUEUE5_IB_OFFSET |
2082 | #define SDMA0_QUEUE5_IB_OFFSET__OFFSET__SHIFT 0x2 |
2083 | #define SDMA0_QUEUE5_IB_OFFSET__OFFSET_MASK 0x003FFFFCL |
2084 | //SDMA0_QUEUE5_IB_BASE_LO |
2085 | #define SDMA0_QUEUE5_IB_BASE_LO__ADDR__SHIFT 0x5 |
2086 | #define SDMA0_QUEUE5_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L |
2087 | //SDMA0_QUEUE5_IB_BASE_HI |
2088 | #define SDMA0_QUEUE5_IB_BASE_HI__ADDR__SHIFT 0x0 |
2089 | #define SDMA0_QUEUE5_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL |
2090 | //SDMA0_QUEUE5_IB_SIZE |
2091 | #define SDMA0_QUEUE5_IB_SIZE__SIZE__SHIFT 0x0 |
2092 | #define SDMA0_QUEUE5_IB_SIZE__SIZE_MASK 0x000FFFFFL |
2093 | //SDMA0_QUEUE5_SKIP_CNTL |
2094 | #define SDMA0_QUEUE5_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 |
2095 | #define SDMA0_QUEUE5_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL |
2096 | //SDMA0_QUEUE5_CONTEXT_STATUS |
2097 | #define SDMA0_QUEUE5_CONTEXT_STATUS__SELECTED__SHIFT 0x0 |
2098 | #define SDMA0_QUEUE5_CONTEXT_STATUS__IDLE__SHIFT 0x2 |
2099 | #define SDMA0_QUEUE5_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 |
2100 | #define SDMA0_QUEUE5_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 |
2101 | #define SDMA0_QUEUE5_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 |
2102 | #define SDMA0_QUEUE5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa |
2103 | #define SDMA0_QUEUE5_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb |
2104 | #define SDMA0_QUEUE5_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc |
2105 | #define SDMA0_QUEUE5_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 |
2106 | #define SDMA0_QUEUE5_CONTEXT_STATUS__SELECTED_MASK 0x00000001L |
2107 | #define SDMA0_QUEUE5_CONTEXT_STATUS__IDLE_MASK 0x00000004L |
2108 | #define SDMA0_QUEUE5_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L |
2109 | #define SDMA0_QUEUE5_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L |
2110 | #define SDMA0_QUEUE5_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L |
2111 | #define SDMA0_QUEUE5_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L |
2112 | #define SDMA0_QUEUE5_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L |
2113 | #define SDMA0_QUEUE5_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L |
2114 | #define SDMA0_QUEUE5_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L |
2115 | //SDMA0_QUEUE5_DOORBELL |
2116 | #define SDMA0_QUEUE5_DOORBELL__ENABLE__SHIFT 0x1c |
2117 | #define SDMA0_QUEUE5_DOORBELL__CAPTURED__SHIFT 0x1e |
2118 | #define SDMA0_QUEUE5_DOORBELL__ENABLE_MASK 0x10000000L |
2119 | #define SDMA0_QUEUE5_DOORBELL__CAPTURED_MASK 0x40000000L |
2120 | //SDMA0_QUEUE5_DOORBELL_LOG |
2121 | #define SDMA0_QUEUE5_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 |
2122 | #define SDMA0_QUEUE5_DOORBELL_LOG__DATA__SHIFT 0x2 |
2123 | #define SDMA0_QUEUE5_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L |
2124 | #define SDMA0_QUEUE5_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL |
2125 | //SDMA0_QUEUE5_DOORBELL_OFFSET |
2126 | #define SDMA0_QUEUE5_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 |
2127 | #define SDMA0_QUEUE5_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL |
2128 | //SDMA0_QUEUE5_CSA_ADDR_LO |
2129 | #define SDMA0_QUEUE5_CSA_ADDR_LO__ADDR__SHIFT 0x2 |
2130 | #define SDMA0_QUEUE5_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
2131 | //SDMA0_QUEUE5_CSA_ADDR_HI |
2132 | #define SDMA0_QUEUE5_CSA_ADDR_HI__ADDR__SHIFT 0x0 |
2133 | #define SDMA0_QUEUE5_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
2134 | //SDMA0_QUEUE5_SCHEDULE_CNTL |
2135 | #define SDMA0_QUEUE5_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 |
2136 | #define SDMA0_QUEUE5_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 |
2137 | #define SDMA0_QUEUE5_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 |
2138 | #define SDMA0_QUEUE5_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 |
2139 | #define SDMA0_QUEUE5_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L |
2140 | #define SDMA0_QUEUE5_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL |
2141 | #define SDMA0_QUEUE5_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L |
2142 | #define SDMA0_QUEUE5_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L |
2143 | //SDMA0_QUEUE5_IB_SUB_REMAIN |
2144 | #define SDMA0_QUEUE5_IB_SUB_REMAIN__SIZE__SHIFT 0x0 |
2145 | #define SDMA0_QUEUE5_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL |
2146 | //SDMA0_QUEUE5_PREEMPT |
2147 | #define SDMA0_QUEUE5_PREEMPT__IB_PREEMPT__SHIFT 0x0 |
2148 | #define SDMA0_QUEUE5_PREEMPT__IB_PREEMPT_MASK 0x00000001L |
2149 | //SDMA0_QUEUE5_DUMMY_REG |
2150 | #define SDMA0_QUEUE5_DUMMY_REG__DUMMY__SHIFT 0x0 |
2151 | #define SDMA0_QUEUE5_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL |
2152 | //SDMA0_QUEUE5_RB_WPTR_POLL_ADDR_HI |
2153 | #define SDMA0_QUEUE5_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 |
2154 | #define SDMA0_QUEUE5_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
2155 | //SDMA0_QUEUE5_RB_WPTR_POLL_ADDR_LO |
2156 | #define SDMA0_QUEUE5_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 |
2157 | #define SDMA0_QUEUE5_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
2158 | //SDMA0_QUEUE5_RB_AQL_CNTL |
2159 | #define SDMA0_QUEUE5_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 |
2160 | #define SDMA0_QUEUE5_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 |
2161 | #define SDMA0_QUEUE5_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 |
2162 | #define SDMA0_QUEUE5_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 |
2163 | #define SDMA0_QUEUE5_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 |
2164 | #define SDMA0_QUEUE5_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 |
2165 | #define SDMA0_QUEUE5_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L |
2166 | #define SDMA0_QUEUE5_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL |
2167 | #define SDMA0_QUEUE5_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L |
2168 | #define SDMA0_QUEUE5_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L |
2169 | #define SDMA0_QUEUE5_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L |
2170 | #define SDMA0_QUEUE5_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L |
2171 | //SDMA0_QUEUE5_MINOR_PTR_UPDATE |
2172 | #define SDMA0_QUEUE5_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 |
2173 | #define SDMA0_QUEUE5_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L |
2174 | //SDMA0_QUEUE5_RB_PREEMPT |
2175 | #define SDMA0_QUEUE5_RB_PREEMPT__PREEMPT_REQ__SHIFT 0x0 |
2176 | #define SDMA0_QUEUE5_RB_PREEMPT__PREEMPT_REQ_MASK 0x00000001L |
2177 | //SDMA0_QUEUE5_MIDCMD_DATA0 |
2178 | #define SDMA0_QUEUE5_MIDCMD_DATA0__DATA0__SHIFT 0x0 |
2179 | #define SDMA0_QUEUE5_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL |
2180 | //SDMA0_QUEUE5_MIDCMD_DATA1 |
2181 | #define SDMA0_QUEUE5_MIDCMD_DATA1__DATA1__SHIFT 0x0 |
2182 | #define SDMA0_QUEUE5_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL |
2183 | //SDMA0_QUEUE5_MIDCMD_DATA2 |
2184 | #define SDMA0_QUEUE5_MIDCMD_DATA2__DATA2__SHIFT 0x0 |
2185 | #define SDMA0_QUEUE5_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL |
2186 | //SDMA0_QUEUE5_MIDCMD_DATA3 |
2187 | #define SDMA0_QUEUE5_MIDCMD_DATA3__DATA3__SHIFT 0x0 |
2188 | #define SDMA0_QUEUE5_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL |
2189 | //SDMA0_QUEUE5_MIDCMD_DATA4 |
2190 | #define SDMA0_QUEUE5_MIDCMD_DATA4__DATA4__SHIFT 0x0 |
2191 | #define SDMA0_QUEUE5_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL |
2192 | //SDMA0_QUEUE5_MIDCMD_DATA5 |
2193 | #define SDMA0_QUEUE5_MIDCMD_DATA5__DATA5__SHIFT 0x0 |
2194 | #define SDMA0_QUEUE5_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL |
2195 | //SDMA0_QUEUE5_MIDCMD_DATA6 |
2196 | #define SDMA0_QUEUE5_MIDCMD_DATA6__DATA6__SHIFT 0x0 |
2197 | #define SDMA0_QUEUE5_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL |
2198 | //SDMA0_QUEUE5_MIDCMD_DATA7 |
2199 | #define SDMA0_QUEUE5_MIDCMD_DATA7__DATA7__SHIFT 0x0 |
2200 | #define SDMA0_QUEUE5_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL |
2201 | //SDMA0_QUEUE5_MIDCMD_DATA8 |
2202 | #define SDMA0_QUEUE5_MIDCMD_DATA8__DATA8__SHIFT 0x0 |
2203 | #define SDMA0_QUEUE5_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL |
2204 | //SDMA0_QUEUE5_MIDCMD_DATA9 |
2205 | #define SDMA0_QUEUE5_MIDCMD_DATA9__DATA9__SHIFT 0x0 |
2206 | #define SDMA0_QUEUE5_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL |
2207 | //SDMA0_QUEUE5_MIDCMD_DATA10 |
2208 | #define SDMA0_QUEUE5_MIDCMD_DATA10__DATA10__SHIFT 0x0 |
2209 | #define SDMA0_QUEUE5_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL |
2210 | //SDMA0_QUEUE5_MIDCMD_CNTL |
2211 | #define SDMA0_QUEUE5_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 |
2212 | #define SDMA0_QUEUE5_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 |
2213 | #define SDMA0_QUEUE5_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 |
2214 | #define SDMA0_QUEUE5_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 |
2215 | #define SDMA0_QUEUE5_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L |
2216 | #define SDMA0_QUEUE5_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L |
2217 | #define SDMA0_QUEUE5_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L |
2218 | #define SDMA0_QUEUE5_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L |
2219 | //SDMA0_QUEUE6_RB_CNTL |
2220 | #define SDMA0_QUEUE6_RB_CNTL__RB_ENABLE__SHIFT 0x0 |
2221 | #define SDMA0_QUEUE6_RB_CNTL__RB_SIZE__SHIFT 0x1 |
2222 | #define SDMA0_QUEUE6_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 |
2223 | #define SDMA0_QUEUE6_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 |
2224 | #define SDMA0_QUEUE6_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa |
2225 | #define SDMA0_QUEUE6_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT 0xb |
2226 | #define SDMA0_QUEUE6_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc |
2227 | #define SDMA0_QUEUE6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd |
2228 | #define SDMA0_QUEUE6_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 |
2229 | #define SDMA0_QUEUE6_RB_CNTL__RB_PRIV__SHIFT 0x17 |
2230 | #define SDMA0_QUEUE6_RB_CNTL__RB_VMID__SHIFT 0x18 |
2231 | #define SDMA0_QUEUE6_RB_CNTL__RB_ENABLE_MASK 0x00000001L |
2232 | #define SDMA0_QUEUE6_RB_CNTL__RB_SIZE_MASK 0x0000003EL |
2233 | #define SDMA0_QUEUE6_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L |
2234 | #define SDMA0_QUEUE6_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L |
2235 | #define SDMA0_QUEUE6_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L |
2236 | #define SDMA0_QUEUE6_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK 0x00000800L |
2237 | #define SDMA0_QUEUE6_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L |
2238 | #define SDMA0_QUEUE6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L |
2239 | #define SDMA0_QUEUE6_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L |
2240 | #define SDMA0_QUEUE6_RB_CNTL__RB_PRIV_MASK 0x00800000L |
2241 | #define SDMA0_QUEUE6_RB_CNTL__RB_VMID_MASK 0x0F000000L |
2242 | //SDMA0_QUEUE6_RB_BASE |
2243 | #define SDMA0_QUEUE6_RB_BASE__ADDR__SHIFT 0x0 |
2244 | #define SDMA0_QUEUE6_RB_BASE__ADDR_MASK 0xFFFFFFFFL |
2245 | //SDMA0_QUEUE6_RB_BASE_HI |
2246 | #define SDMA0_QUEUE6_RB_BASE_HI__ADDR__SHIFT 0x0 |
2247 | #define SDMA0_QUEUE6_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL |
2248 | //SDMA0_QUEUE6_RB_RPTR |
2249 | #define SDMA0_QUEUE6_RB_RPTR__OFFSET__SHIFT 0x0 |
2250 | #define SDMA0_QUEUE6_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL |
2251 | //SDMA0_QUEUE6_RB_RPTR_HI |
2252 | #define SDMA0_QUEUE6_RB_RPTR_HI__OFFSET__SHIFT 0x0 |
2253 | #define SDMA0_QUEUE6_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
2254 | //SDMA0_QUEUE6_RB_WPTR |
2255 | #define SDMA0_QUEUE6_RB_WPTR__OFFSET__SHIFT 0x0 |
2256 | #define SDMA0_QUEUE6_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL |
2257 | //SDMA0_QUEUE6_RB_WPTR_HI |
2258 | #define SDMA0_QUEUE6_RB_WPTR_HI__OFFSET__SHIFT 0x0 |
2259 | #define SDMA0_QUEUE6_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
2260 | //SDMA0_QUEUE6_RB_RPTR_ADDR_HI |
2261 | #define SDMA0_QUEUE6_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 |
2262 | #define SDMA0_QUEUE6_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
2263 | //SDMA0_QUEUE6_RB_RPTR_ADDR_LO |
2264 | #define SDMA0_QUEUE6_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 |
2265 | #define SDMA0_QUEUE6_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
2266 | //SDMA0_QUEUE6_IB_CNTL |
2267 | #define SDMA0_QUEUE6_IB_CNTL__IB_ENABLE__SHIFT 0x0 |
2268 | #define SDMA0_QUEUE6_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 |
2269 | #define SDMA0_QUEUE6_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 |
2270 | #define SDMA0_QUEUE6_IB_CNTL__CMD_VMID__SHIFT 0x10 |
2271 | #define SDMA0_QUEUE6_IB_CNTL__IB_PRIV__SHIFT 0x1f |
2272 | #define SDMA0_QUEUE6_IB_CNTL__IB_ENABLE_MASK 0x00000001L |
2273 | #define SDMA0_QUEUE6_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L |
2274 | #define SDMA0_QUEUE6_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L |
2275 | #define SDMA0_QUEUE6_IB_CNTL__CMD_VMID_MASK 0x000F0000L |
2276 | #define SDMA0_QUEUE6_IB_CNTL__IB_PRIV_MASK 0x80000000L |
2277 | //SDMA0_QUEUE6_IB_RPTR |
2278 | #define SDMA0_QUEUE6_IB_RPTR__OFFSET__SHIFT 0x2 |
2279 | #define SDMA0_QUEUE6_IB_RPTR__OFFSET_MASK 0x003FFFFCL |
2280 | //SDMA0_QUEUE6_IB_OFFSET |
2281 | #define SDMA0_QUEUE6_IB_OFFSET__OFFSET__SHIFT 0x2 |
2282 | #define SDMA0_QUEUE6_IB_OFFSET__OFFSET_MASK 0x003FFFFCL |
2283 | //SDMA0_QUEUE6_IB_BASE_LO |
2284 | #define SDMA0_QUEUE6_IB_BASE_LO__ADDR__SHIFT 0x5 |
2285 | #define SDMA0_QUEUE6_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L |
2286 | //SDMA0_QUEUE6_IB_BASE_HI |
2287 | #define SDMA0_QUEUE6_IB_BASE_HI__ADDR__SHIFT 0x0 |
2288 | #define SDMA0_QUEUE6_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL |
2289 | //SDMA0_QUEUE6_IB_SIZE |
2290 | #define SDMA0_QUEUE6_IB_SIZE__SIZE__SHIFT 0x0 |
2291 | #define SDMA0_QUEUE6_IB_SIZE__SIZE_MASK 0x000FFFFFL |
2292 | //SDMA0_QUEUE6_SKIP_CNTL |
2293 | #define SDMA0_QUEUE6_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 |
2294 | #define SDMA0_QUEUE6_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL |
2295 | //SDMA0_QUEUE6_CONTEXT_STATUS |
2296 | #define SDMA0_QUEUE6_CONTEXT_STATUS__SELECTED__SHIFT 0x0 |
2297 | #define SDMA0_QUEUE6_CONTEXT_STATUS__IDLE__SHIFT 0x2 |
2298 | #define SDMA0_QUEUE6_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 |
2299 | #define SDMA0_QUEUE6_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 |
2300 | #define SDMA0_QUEUE6_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 |
2301 | #define SDMA0_QUEUE6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa |
2302 | #define SDMA0_QUEUE6_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb |
2303 | #define SDMA0_QUEUE6_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc |
2304 | #define SDMA0_QUEUE6_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 |
2305 | #define SDMA0_QUEUE6_CONTEXT_STATUS__SELECTED_MASK 0x00000001L |
2306 | #define SDMA0_QUEUE6_CONTEXT_STATUS__IDLE_MASK 0x00000004L |
2307 | #define SDMA0_QUEUE6_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L |
2308 | #define SDMA0_QUEUE6_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L |
2309 | #define SDMA0_QUEUE6_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L |
2310 | #define SDMA0_QUEUE6_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L |
2311 | #define SDMA0_QUEUE6_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L |
2312 | #define SDMA0_QUEUE6_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L |
2313 | #define SDMA0_QUEUE6_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L |
2314 | //SDMA0_QUEUE6_DOORBELL |
2315 | #define SDMA0_QUEUE6_DOORBELL__ENABLE__SHIFT 0x1c |
2316 | #define SDMA0_QUEUE6_DOORBELL__CAPTURED__SHIFT 0x1e |
2317 | #define SDMA0_QUEUE6_DOORBELL__ENABLE_MASK 0x10000000L |
2318 | #define SDMA0_QUEUE6_DOORBELL__CAPTURED_MASK 0x40000000L |
2319 | //SDMA0_QUEUE6_DOORBELL_LOG |
2320 | #define SDMA0_QUEUE6_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 |
2321 | #define SDMA0_QUEUE6_DOORBELL_LOG__DATA__SHIFT 0x2 |
2322 | #define SDMA0_QUEUE6_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L |
2323 | #define SDMA0_QUEUE6_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL |
2324 | //SDMA0_QUEUE6_DOORBELL_OFFSET |
2325 | #define SDMA0_QUEUE6_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 |
2326 | #define SDMA0_QUEUE6_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL |
2327 | //SDMA0_QUEUE6_CSA_ADDR_LO |
2328 | #define SDMA0_QUEUE6_CSA_ADDR_LO__ADDR__SHIFT 0x2 |
2329 | #define SDMA0_QUEUE6_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
2330 | //SDMA0_QUEUE6_CSA_ADDR_HI |
2331 | #define SDMA0_QUEUE6_CSA_ADDR_HI__ADDR__SHIFT 0x0 |
2332 | #define SDMA0_QUEUE6_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
2333 | //SDMA0_QUEUE6_SCHEDULE_CNTL |
2334 | #define SDMA0_QUEUE6_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 |
2335 | #define SDMA0_QUEUE6_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 |
2336 | #define SDMA0_QUEUE6_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 |
2337 | #define SDMA0_QUEUE6_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 |
2338 | #define SDMA0_QUEUE6_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L |
2339 | #define SDMA0_QUEUE6_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL |
2340 | #define SDMA0_QUEUE6_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L |
2341 | #define SDMA0_QUEUE6_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L |
2342 | //SDMA0_QUEUE6_IB_SUB_REMAIN |
2343 | #define SDMA0_QUEUE6_IB_SUB_REMAIN__SIZE__SHIFT 0x0 |
2344 | #define SDMA0_QUEUE6_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL |
2345 | //SDMA0_QUEUE6_PREEMPT |
2346 | #define SDMA0_QUEUE6_PREEMPT__IB_PREEMPT__SHIFT 0x0 |
2347 | #define SDMA0_QUEUE6_PREEMPT__IB_PREEMPT_MASK 0x00000001L |
2348 | //SDMA0_QUEUE6_DUMMY_REG |
2349 | #define SDMA0_QUEUE6_DUMMY_REG__DUMMY__SHIFT 0x0 |
2350 | #define SDMA0_QUEUE6_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL |
2351 | //SDMA0_QUEUE6_RB_WPTR_POLL_ADDR_HI |
2352 | #define SDMA0_QUEUE6_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 |
2353 | #define SDMA0_QUEUE6_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
2354 | //SDMA0_QUEUE6_RB_WPTR_POLL_ADDR_LO |
2355 | #define SDMA0_QUEUE6_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 |
2356 | #define SDMA0_QUEUE6_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
2357 | //SDMA0_QUEUE6_RB_AQL_CNTL |
2358 | #define SDMA0_QUEUE6_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 |
2359 | #define SDMA0_QUEUE6_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 |
2360 | #define SDMA0_QUEUE6_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 |
2361 | #define SDMA0_QUEUE6_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 |
2362 | #define SDMA0_QUEUE6_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 |
2363 | #define SDMA0_QUEUE6_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 |
2364 | #define SDMA0_QUEUE6_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L |
2365 | #define SDMA0_QUEUE6_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL |
2366 | #define SDMA0_QUEUE6_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L |
2367 | #define SDMA0_QUEUE6_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L |
2368 | #define SDMA0_QUEUE6_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L |
2369 | #define SDMA0_QUEUE6_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L |
2370 | //SDMA0_QUEUE6_MINOR_PTR_UPDATE |
2371 | #define SDMA0_QUEUE6_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 |
2372 | #define SDMA0_QUEUE6_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L |
2373 | //SDMA0_QUEUE6_RB_PREEMPT |
2374 | #define SDMA0_QUEUE6_RB_PREEMPT__PREEMPT_REQ__SHIFT 0x0 |
2375 | #define SDMA0_QUEUE6_RB_PREEMPT__PREEMPT_REQ_MASK 0x00000001L |
2376 | //SDMA0_QUEUE6_MIDCMD_DATA0 |
2377 | #define SDMA0_QUEUE6_MIDCMD_DATA0__DATA0__SHIFT 0x0 |
2378 | #define SDMA0_QUEUE6_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL |
2379 | //SDMA0_QUEUE6_MIDCMD_DATA1 |
2380 | #define SDMA0_QUEUE6_MIDCMD_DATA1__DATA1__SHIFT 0x0 |
2381 | #define SDMA0_QUEUE6_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL |
2382 | //SDMA0_QUEUE6_MIDCMD_DATA2 |
2383 | #define SDMA0_QUEUE6_MIDCMD_DATA2__DATA2__SHIFT 0x0 |
2384 | #define SDMA0_QUEUE6_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL |
2385 | //SDMA0_QUEUE6_MIDCMD_DATA3 |
2386 | #define SDMA0_QUEUE6_MIDCMD_DATA3__DATA3__SHIFT 0x0 |
2387 | #define SDMA0_QUEUE6_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL |
2388 | //SDMA0_QUEUE6_MIDCMD_DATA4 |
2389 | #define SDMA0_QUEUE6_MIDCMD_DATA4__DATA4__SHIFT 0x0 |
2390 | #define SDMA0_QUEUE6_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL |
2391 | //SDMA0_QUEUE6_MIDCMD_DATA5 |
2392 | #define SDMA0_QUEUE6_MIDCMD_DATA5__DATA5__SHIFT 0x0 |
2393 | #define SDMA0_QUEUE6_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL |
2394 | //SDMA0_QUEUE6_MIDCMD_DATA6 |
2395 | #define SDMA0_QUEUE6_MIDCMD_DATA6__DATA6__SHIFT 0x0 |
2396 | #define SDMA0_QUEUE6_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL |
2397 | //SDMA0_QUEUE6_MIDCMD_DATA7 |
2398 | #define SDMA0_QUEUE6_MIDCMD_DATA7__DATA7__SHIFT 0x0 |
2399 | #define SDMA0_QUEUE6_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL |
2400 | //SDMA0_QUEUE6_MIDCMD_DATA8 |
2401 | #define SDMA0_QUEUE6_MIDCMD_DATA8__DATA8__SHIFT 0x0 |
2402 | #define SDMA0_QUEUE6_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL |
2403 | //SDMA0_QUEUE6_MIDCMD_DATA9 |
2404 | #define SDMA0_QUEUE6_MIDCMD_DATA9__DATA9__SHIFT 0x0 |
2405 | #define SDMA0_QUEUE6_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL |
2406 | //SDMA0_QUEUE6_MIDCMD_DATA10 |
2407 | #define SDMA0_QUEUE6_MIDCMD_DATA10__DATA10__SHIFT 0x0 |
2408 | #define SDMA0_QUEUE6_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL |
2409 | //SDMA0_QUEUE6_MIDCMD_CNTL |
2410 | #define SDMA0_QUEUE6_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 |
2411 | #define SDMA0_QUEUE6_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 |
2412 | #define SDMA0_QUEUE6_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 |
2413 | #define SDMA0_QUEUE6_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 |
2414 | #define SDMA0_QUEUE6_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L |
2415 | #define SDMA0_QUEUE6_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L |
2416 | #define SDMA0_QUEUE6_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L |
2417 | #define SDMA0_QUEUE6_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L |
2418 | //SDMA0_QUEUE7_RB_CNTL |
2419 | #define SDMA0_QUEUE7_RB_CNTL__RB_ENABLE__SHIFT 0x0 |
2420 | #define SDMA0_QUEUE7_RB_CNTL__RB_SIZE__SHIFT 0x1 |
2421 | #define SDMA0_QUEUE7_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 |
2422 | #define SDMA0_QUEUE7_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 |
2423 | #define SDMA0_QUEUE7_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa |
2424 | #define SDMA0_QUEUE7_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT 0xb |
2425 | #define SDMA0_QUEUE7_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc |
2426 | #define SDMA0_QUEUE7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd |
2427 | #define SDMA0_QUEUE7_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 |
2428 | #define SDMA0_QUEUE7_RB_CNTL__RB_PRIV__SHIFT 0x17 |
2429 | #define SDMA0_QUEUE7_RB_CNTL__RB_VMID__SHIFT 0x18 |
2430 | #define SDMA0_QUEUE7_RB_CNTL__RB_ENABLE_MASK 0x00000001L |
2431 | #define SDMA0_QUEUE7_RB_CNTL__RB_SIZE_MASK 0x0000003EL |
2432 | #define SDMA0_QUEUE7_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L |
2433 | #define SDMA0_QUEUE7_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L |
2434 | #define SDMA0_QUEUE7_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L |
2435 | #define SDMA0_QUEUE7_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK 0x00000800L |
2436 | #define SDMA0_QUEUE7_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L |
2437 | #define SDMA0_QUEUE7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L |
2438 | #define SDMA0_QUEUE7_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L |
2439 | #define SDMA0_QUEUE7_RB_CNTL__RB_PRIV_MASK 0x00800000L |
2440 | #define SDMA0_QUEUE7_RB_CNTL__RB_VMID_MASK 0x0F000000L |
2441 | //SDMA0_QUEUE7_RB_BASE |
2442 | #define SDMA0_QUEUE7_RB_BASE__ADDR__SHIFT 0x0 |
2443 | #define SDMA0_QUEUE7_RB_BASE__ADDR_MASK 0xFFFFFFFFL |
2444 | //SDMA0_QUEUE7_RB_BASE_HI |
2445 | #define SDMA0_QUEUE7_RB_BASE_HI__ADDR__SHIFT 0x0 |
2446 | #define SDMA0_QUEUE7_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL |
2447 | //SDMA0_QUEUE7_RB_RPTR |
2448 | #define SDMA0_QUEUE7_RB_RPTR__OFFSET__SHIFT 0x0 |
2449 | #define SDMA0_QUEUE7_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL |
2450 | //SDMA0_QUEUE7_RB_RPTR_HI |
2451 | #define SDMA0_QUEUE7_RB_RPTR_HI__OFFSET__SHIFT 0x0 |
2452 | #define SDMA0_QUEUE7_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
2453 | //SDMA0_QUEUE7_RB_WPTR |
2454 | #define SDMA0_QUEUE7_RB_WPTR__OFFSET__SHIFT 0x0 |
2455 | #define SDMA0_QUEUE7_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL |
2456 | //SDMA0_QUEUE7_RB_WPTR_HI |
2457 | #define SDMA0_QUEUE7_RB_WPTR_HI__OFFSET__SHIFT 0x0 |
2458 | #define SDMA0_QUEUE7_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
2459 | //SDMA0_QUEUE7_RB_RPTR_ADDR_HI |
2460 | #define SDMA0_QUEUE7_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 |
2461 | #define SDMA0_QUEUE7_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
2462 | //SDMA0_QUEUE7_RB_RPTR_ADDR_LO |
2463 | #define SDMA0_QUEUE7_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 |
2464 | #define SDMA0_QUEUE7_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
2465 | //SDMA0_QUEUE7_IB_CNTL |
2466 | #define SDMA0_QUEUE7_IB_CNTL__IB_ENABLE__SHIFT 0x0 |
2467 | #define SDMA0_QUEUE7_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 |
2468 | #define SDMA0_QUEUE7_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 |
2469 | #define SDMA0_QUEUE7_IB_CNTL__CMD_VMID__SHIFT 0x10 |
2470 | #define SDMA0_QUEUE7_IB_CNTL__IB_PRIV__SHIFT 0x1f |
2471 | #define SDMA0_QUEUE7_IB_CNTL__IB_ENABLE_MASK 0x00000001L |
2472 | #define SDMA0_QUEUE7_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L |
2473 | #define SDMA0_QUEUE7_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L |
2474 | #define SDMA0_QUEUE7_IB_CNTL__CMD_VMID_MASK 0x000F0000L |
2475 | #define SDMA0_QUEUE7_IB_CNTL__IB_PRIV_MASK 0x80000000L |
2476 | //SDMA0_QUEUE7_IB_RPTR |
2477 | #define SDMA0_QUEUE7_IB_RPTR__OFFSET__SHIFT 0x2 |
2478 | #define SDMA0_QUEUE7_IB_RPTR__OFFSET_MASK 0x003FFFFCL |
2479 | //SDMA0_QUEUE7_IB_OFFSET |
2480 | #define SDMA0_QUEUE7_IB_OFFSET__OFFSET__SHIFT 0x2 |
2481 | #define SDMA0_QUEUE7_IB_OFFSET__OFFSET_MASK 0x003FFFFCL |
2482 | //SDMA0_QUEUE7_IB_BASE_LO |
2483 | #define SDMA0_QUEUE7_IB_BASE_LO__ADDR__SHIFT 0x5 |
2484 | #define SDMA0_QUEUE7_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L |
2485 | //SDMA0_QUEUE7_IB_BASE_HI |
2486 | #define SDMA0_QUEUE7_IB_BASE_HI__ADDR__SHIFT 0x0 |
2487 | #define SDMA0_QUEUE7_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL |
2488 | //SDMA0_QUEUE7_IB_SIZE |
2489 | #define SDMA0_QUEUE7_IB_SIZE__SIZE__SHIFT 0x0 |
2490 | #define SDMA0_QUEUE7_IB_SIZE__SIZE_MASK 0x000FFFFFL |
2491 | //SDMA0_QUEUE7_SKIP_CNTL |
2492 | #define SDMA0_QUEUE7_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 |
2493 | #define SDMA0_QUEUE7_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL |
2494 | //SDMA0_QUEUE7_CONTEXT_STATUS |
2495 | #define SDMA0_QUEUE7_CONTEXT_STATUS__SELECTED__SHIFT 0x0 |
2496 | #define SDMA0_QUEUE7_CONTEXT_STATUS__IDLE__SHIFT 0x2 |
2497 | #define SDMA0_QUEUE7_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 |
2498 | #define SDMA0_QUEUE7_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 |
2499 | #define SDMA0_QUEUE7_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 |
2500 | #define SDMA0_QUEUE7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa |
2501 | #define SDMA0_QUEUE7_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb |
2502 | #define SDMA0_QUEUE7_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc |
2503 | #define SDMA0_QUEUE7_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 |
2504 | #define SDMA0_QUEUE7_CONTEXT_STATUS__SELECTED_MASK 0x00000001L |
2505 | #define SDMA0_QUEUE7_CONTEXT_STATUS__IDLE_MASK 0x00000004L |
2506 | #define SDMA0_QUEUE7_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L |
2507 | #define SDMA0_QUEUE7_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L |
2508 | #define SDMA0_QUEUE7_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L |
2509 | #define SDMA0_QUEUE7_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L |
2510 | #define SDMA0_QUEUE7_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L |
2511 | #define SDMA0_QUEUE7_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L |
2512 | #define SDMA0_QUEUE7_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L |
2513 | //SDMA0_QUEUE7_DOORBELL |
2514 | #define SDMA0_QUEUE7_DOORBELL__ENABLE__SHIFT 0x1c |
2515 | #define SDMA0_QUEUE7_DOORBELL__CAPTURED__SHIFT 0x1e |
2516 | #define SDMA0_QUEUE7_DOORBELL__ENABLE_MASK 0x10000000L |
2517 | #define SDMA0_QUEUE7_DOORBELL__CAPTURED_MASK 0x40000000L |
2518 | //SDMA0_QUEUE7_DOORBELL_LOG |
2519 | #define SDMA0_QUEUE7_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 |
2520 | #define SDMA0_QUEUE7_DOORBELL_LOG__DATA__SHIFT 0x2 |
2521 | #define SDMA0_QUEUE7_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L |
2522 | #define SDMA0_QUEUE7_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL |
2523 | //SDMA0_QUEUE7_DOORBELL_OFFSET |
2524 | #define SDMA0_QUEUE7_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 |
2525 | #define SDMA0_QUEUE7_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL |
2526 | //SDMA0_QUEUE7_CSA_ADDR_LO |
2527 | #define SDMA0_QUEUE7_CSA_ADDR_LO__ADDR__SHIFT 0x2 |
2528 | #define SDMA0_QUEUE7_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
2529 | //SDMA0_QUEUE7_CSA_ADDR_HI |
2530 | #define SDMA0_QUEUE7_CSA_ADDR_HI__ADDR__SHIFT 0x0 |
2531 | #define SDMA0_QUEUE7_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
2532 | //SDMA0_QUEUE7_SCHEDULE_CNTL |
2533 | #define SDMA0_QUEUE7_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 |
2534 | #define SDMA0_QUEUE7_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 |
2535 | #define SDMA0_QUEUE7_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 |
2536 | #define SDMA0_QUEUE7_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 |
2537 | #define SDMA0_QUEUE7_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L |
2538 | #define SDMA0_QUEUE7_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL |
2539 | #define SDMA0_QUEUE7_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L |
2540 | #define SDMA0_QUEUE7_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L |
2541 | //SDMA0_QUEUE7_IB_SUB_REMAIN |
2542 | #define SDMA0_QUEUE7_IB_SUB_REMAIN__SIZE__SHIFT 0x0 |
2543 | #define SDMA0_QUEUE7_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL |
2544 | //SDMA0_QUEUE7_PREEMPT |
2545 | #define SDMA0_QUEUE7_PREEMPT__IB_PREEMPT__SHIFT 0x0 |
2546 | #define SDMA0_QUEUE7_PREEMPT__IB_PREEMPT_MASK 0x00000001L |
2547 | //SDMA0_QUEUE7_DUMMY_REG |
2548 | #define SDMA0_QUEUE7_DUMMY_REG__DUMMY__SHIFT 0x0 |
2549 | #define SDMA0_QUEUE7_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL |
2550 | //SDMA0_QUEUE7_RB_WPTR_POLL_ADDR_HI |
2551 | #define SDMA0_QUEUE7_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 |
2552 | #define SDMA0_QUEUE7_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
2553 | //SDMA0_QUEUE7_RB_WPTR_POLL_ADDR_LO |
2554 | #define SDMA0_QUEUE7_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 |
2555 | #define SDMA0_QUEUE7_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
2556 | //SDMA0_QUEUE7_RB_AQL_CNTL |
2557 | #define SDMA0_QUEUE7_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 |
2558 | #define SDMA0_QUEUE7_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 |
2559 | #define SDMA0_QUEUE7_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 |
2560 | #define SDMA0_QUEUE7_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 |
2561 | #define SDMA0_QUEUE7_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 |
2562 | #define SDMA0_QUEUE7_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 |
2563 | #define SDMA0_QUEUE7_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L |
2564 | #define SDMA0_QUEUE7_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL |
2565 | #define SDMA0_QUEUE7_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L |
2566 | #define SDMA0_QUEUE7_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L |
2567 | #define SDMA0_QUEUE7_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L |
2568 | #define SDMA0_QUEUE7_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L |
2569 | //SDMA0_QUEUE7_MINOR_PTR_UPDATE |
2570 | #define SDMA0_QUEUE7_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 |
2571 | #define SDMA0_QUEUE7_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L |
2572 | //SDMA0_QUEUE7_RB_PREEMPT |
2573 | #define SDMA0_QUEUE7_RB_PREEMPT__PREEMPT_REQ__SHIFT 0x0 |
2574 | #define SDMA0_QUEUE7_RB_PREEMPT__PREEMPT_REQ_MASK 0x00000001L |
2575 | //SDMA0_QUEUE7_MIDCMD_DATA0 |
2576 | #define SDMA0_QUEUE7_MIDCMD_DATA0__DATA0__SHIFT 0x0 |
2577 | #define SDMA0_QUEUE7_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL |
2578 | //SDMA0_QUEUE7_MIDCMD_DATA1 |
2579 | #define SDMA0_QUEUE7_MIDCMD_DATA1__DATA1__SHIFT 0x0 |
2580 | #define SDMA0_QUEUE7_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL |
2581 | //SDMA0_QUEUE7_MIDCMD_DATA2 |
2582 | #define SDMA0_QUEUE7_MIDCMD_DATA2__DATA2__SHIFT 0x0 |
2583 | #define SDMA0_QUEUE7_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL |
2584 | //SDMA0_QUEUE7_MIDCMD_DATA3 |
2585 | #define SDMA0_QUEUE7_MIDCMD_DATA3__DATA3__SHIFT 0x0 |
2586 | #define SDMA0_QUEUE7_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL |
2587 | //SDMA0_QUEUE7_MIDCMD_DATA4 |
2588 | #define SDMA0_QUEUE7_MIDCMD_DATA4__DATA4__SHIFT 0x0 |
2589 | #define SDMA0_QUEUE7_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL |
2590 | //SDMA0_QUEUE7_MIDCMD_DATA5 |
2591 | #define SDMA0_QUEUE7_MIDCMD_DATA5__DATA5__SHIFT 0x0 |
2592 | #define SDMA0_QUEUE7_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL |
2593 | //SDMA0_QUEUE7_MIDCMD_DATA6 |
2594 | #define SDMA0_QUEUE7_MIDCMD_DATA6__DATA6__SHIFT 0x0 |
2595 | #define SDMA0_QUEUE7_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL |
2596 | //SDMA0_QUEUE7_MIDCMD_DATA7 |
2597 | #define SDMA0_QUEUE7_MIDCMD_DATA7__DATA7__SHIFT 0x0 |
2598 | #define SDMA0_QUEUE7_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL |
2599 | //SDMA0_QUEUE7_MIDCMD_DATA8 |
2600 | #define SDMA0_QUEUE7_MIDCMD_DATA8__DATA8__SHIFT 0x0 |
2601 | #define SDMA0_QUEUE7_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL |
2602 | //SDMA0_QUEUE7_MIDCMD_DATA9 |
2603 | #define SDMA0_QUEUE7_MIDCMD_DATA9__DATA9__SHIFT 0x0 |
2604 | #define SDMA0_QUEUE7_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL |
2605 | //SDMA0_QUEUE7_MIDCMD_DATA10 |
2606 | #define SDMA0_QUEUE7_MIDCMD_DATA10__DATA10__SHIFT 0x0 |
2607 | #define SDMA0_QUEUE7_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL |
2608 | //SDMA0_QUEUE7_MIDCMD_CNTL |
2609 | #define SDMA0_QUEUE7_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 |
2610 | #define SDMA0_QUEUE7_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 |
2611 | #define SDMA0_QUEUE7_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 |
2612 | #define SDMA0_QUEUE7_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 |
2613 | #define SDMA0_QUEUE7_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L |
2614 | #define SDMA0_QUEUE7_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L |
2615 | #define SDMA0_QUEUE7_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L |
2616 | #define SDMA0_QUEUE7_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L |
2617 | |
2618 | |
2619 | // addressBlock: gc_sdma0_sdma1dec |
2620 | //SDMA1_DEC_START |
2621 | #define SDMA1_DEC_START__START__SHIFT 0x0 |
2622 | #define SDMA1_DEC_START__START_MASK 0xFFFFFFFFL |
2623 | //SDMA1_F32_MISC_CNTL |
2624 | #define SDMA1_F32_MISC_CNTL__F32_WAKEUP__SHIFT 0x0 |
2625 | #define SDMA1_F32_MISC_CNTL__F32_WAKEUP_MASK 0x00000001L |
2626 | //SDMA1_GLOBAL_TIMESTAMP_LO |
2627 | #define SDMA1_GLOBAL_TIMESTAMP_LO__DATA__SHIFT 0x0 |
2628 | #define SDMA1_GLOBAL_TIMESTAMP_LO__DATA_MASK 0xFFFFFFFFL |
2629 | //SDMA1_GLOBAL_TIMESTAMP_HI |
2630 | #define SDMA1_GLOBAL_TIMESTAMP_HI__DATA__SHIFT 0x0 |
2631 | #define SDMA1_GLOBAL_TIMESTAMP_HI__DATA_MASK 0xFFFFFFFFL |
2632 | //SDMA1_POWER_CNTL |
2633 | #define SDMA1_POWER_CNTL__LS_ENABLE__SHIFT 0x8 |
2634 | #define SDMA1_POWER_CNTL__LS_ENABLE_MASK 0x00000100L |
2635 | //SDMA1_CNTL |
2636 | #define SDMA1_CNTL__TRAP_ENABLE__SHIFT 0x0 |
2637 | #define SDMA1_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 |
2638 | #define SDMA1_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 |
2639 | #define SDMA1_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 |
2640 | #define SDMA1_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5 |
2641 | #define SDMA1_CNTL__PIO_DONE_ACK_ENABLE__SHIFT 0x6 |
2642 | #define SDMA1_CNTL__TMZ_MIDCMD_PREEMPT_ENABLE__SHIFT 0x8 |
2643 | #define SDMA1_CNTL__MIDCMD_EXPIRE_ENABLE__SHIFT 0x9 |
2644 | #define SDMA1_CNTL__CP_MES_INT_ENABLE__SHIFT 0xa |
2645 | #define SDMA1_CNTL__PAGE_RETRY_TIMEOUT_INT_ENABLE__SHIFT 0xb |
2646 | #define SDMA1_CNTL__PAGE_NULL_INT_ENABLE__SHIFT 0xc |
2647 | #define SDMA1_CNTL__PAGE_FAULT_INT_ENABLE__SHIFT 0xd |
2648 | #define SDMA1_CNTL__CH_PERFCNT_ENABLE__SHIFT 0x10 |
2649 | #define SDMA1_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 |
2650 | #define SDMA1_CNTL__DRM_RESTORE_ENABLE__SHIFT 0x13 |
2651 | #define SDMA1_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c |
2652 | #define SDMA1_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d |
2653 | #define SDMA1_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e |
2654 | #define SDMA1_CNTL__RB_PREEMPT_INT_ENABLE__SHIFT 0x1f |
2655 | #define SDMA1_CNTL__TRAP_ENABLE_MASK 0x00000001L |
2656 | #define SDMA1_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L |
2657 | #define SDMA1_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L |
2658 | #define SDMA1_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L |
2659 | #define SDMA1_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L |
2660 | #define SDMA1_CNTL__PIO_DONE_ACK_ENABLE_MASK 0x00000040L |
2661 | #define SDMA1_CNTL__TMZ_MIDCMD_PREEMPT_ENABLE_MASK 0x00000100L |
2662 | #define SDMA1_CNTL__MIDCMD_EXPIRE_ENABLE_MASK 0x00000200L |
2663 | #define SDMA1_CNTL__CP_MES_INT_ENABLE_MASK 0x00000400L |
2664 | #define SDMA1_CNTL__PAGE_RETRY_TIMEOUT_INT_ENABLE_MASK 0x00000800L |
2665 | #define SDMA1_CNTL__PAGE_NULL_INT_ENABLE_MASK 0x00001000L |
2666 | #define SDMA1_CNTL__PAGE_FAULT_INT_ENABLE_MASK 0x00002000L |
2667 | #define SDMA1_CNTL__CH_PERFCNT_ENABLE_MASK 0x00010000L |
2668 | #define SDMA1_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L |
2669 | #define SDMA1_CNTL__DRM_RESTORE_ENABLE_MASK 0x00080000L |
2670 | #define SDMA1_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L |
2671 | #define SDMA1_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L |
2672 | #define SDMA1_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L |
2673 | #define SDMA1_CNTL__RB_PREEMPT_INT_ENABLE_MASK 0x80000000L |
2674 | //SDMA1_CHICKEN_BITS |
2675 | #define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1 |
2676 | #define SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2 |
2677 | #define SDMA1_CHICKEN_BITS__BACK_COMPAT_ENABLE__SHIFT 0x3 |
2678 | #define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x5 |
2679 | #define SDMA1_CHICKEN_BITS__RD_BURST__SHIFT 0x6 |
2680 | #define SDMA1_CHICKEN_BITS__WR_BURST__SHIFT 0x8 |
2681 | #define SDMA1_CHICKEN_BITS__COMBINE_256B_WAIT_CYCLE__SHIFT 0xa |
2682 | #define SDMA1_CHICKEN_BITS__WR_COMBINE_256B_ENABLE__SHIFT 0xe |
2683 | #define SDMA1_CHICKEN_BITS__RD_COMBINE_256B_ENABLE__SHIFT 0xf |
2684 | #define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10 |
2685 | #define SDMA1_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x11 |
2686 | #define SDMA1_CHICKEN_BITS__T2L_256B_ENABLE__SHIFT 0x12 |
2687 | #define SDMA1_CHICKEN_BITS__SOFT_OVERRIDE_GCR_FGCG__SHIFT 0x13 |
2688 | #define SDMA1_CHICKEN_BITS__SOFT_OVERRIDE_GRBM_FGCG__SHIFT 0x14 |
2689 | #define SDMA1_CHICKEN_BITS__SOFT_OVERRIDE_CH_FGCG__SHIFT 0x15 |
2690 | #define SDMA1_CHICKEN_BITS__SOFT_OVERRIDE_UTCL2_INVREQ_FGCG__SHIFT 0x16 |
2691 | #define SDMA1_CHICKEN_BITS__SOFT_OVERRIDE_UTCL1_FGCG__SHIFT 0x17 |
2692 | #define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x18 |
2693 | #define SDMA1_CHICKEN_BITS__SW_FREEZE_ENABLE__SHIFT 0x19 |
2694 | #define SDMA1_CHICKEN_BITS__DRAM_ECC_COPY_MODE_CNTL__SHIFT 0x1a |
2695 | #define SDMA1_CHICKEN_BITS__RESERVED__SHIFT 0x1b |
2696 | #define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L |
2697 | #define SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L |
2698 | #define SDMA1_CHICKEN_BITS__BACK_COMPAT_ENABLE_MASK 0x00000008L |
2699 | #define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00000020L |
2700 | #define SDMA1_CHICKEN_BITS__RD_BURST_MASK 0x000000C0L |
2701 | #define SDMA1_CHICKEN_BITS__WR_BURST_MASK 0x00000300L |
2702 | #define SDMA1_CHICKEN_BITS__COMBINE_256B_WAIT_CYCLE_MASK 0x00003C00L |
2703 | #define SDMA1_CHICKEN_BITS__WR_COMBINE_256B_ENABLE_MASK 0x00004000L |
2704 | #define SDMA1_CHICKEN_BITS__RD_COMBINE_256B_ENABLE_MASK 0x00008000L |
2705 | #define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L |
2706 | #define SDMA1_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L |
2707 | #define SDMA1_CHICKEN_BITS__T2L_256B_ENABLE_MASK 0x00040000L |
2708 | #define SDMA1_CHICKEN_BITS__SOFT_OVERRIDE_GCR_FGCG_MASK 0x00080000L |
2709 | #define SDMA1_CHICKEN_BITS__SOFT_OVERRIDE_GRBM_FGCG_MASK 0x00100000L |
2710 | #define SDMA1_CHICKEN_BITS__SOFT_OVERRIDE_CH_FGCG_MASK 0x00200000L |
2711 | #define SDMA1_CHICKEN_BITS__SOFT_OVERRIDE_UTCL2_INVREQ_FGCG_MASK 0x00400000L |
2712 | #define SDMA1_CHICKEN_BITS__SOFT_OVERRIDE_UTCL1_FGCG_MASK 0x00800000L |
2713 | #define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x01000000L |
2714 | #define SDMA1_CHICKEN_BITS__SW_FREEZE_ENABLE_MASK 0x02000000L |
2715 | #define SDMA1_CHICKEN_BITS__DRAM_ECC_COPY_MODE_CNTL_MASK 0x04000000L |
2716 | #define SDMA1_CHICKEN_BITS__RESERVED_MASK 0xF8000000L |
2717 | //SDMA1_GB_ADDR_CONFIG |
2718 | #define SDMA1_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 |
2719 | #define SDMA1_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 |
2720 | #define SDMA1_GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0x6 |
2721 | #define SDMA1_GB_ADDR_CONFIG__NUM_PKRS__SHIFT 0x8 |
2722 | #define SDMA1_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 |
2723 | #define SDMA1_GB_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT 0x1a |
2724 | #define SDMA1_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L |
2725 | #define SDMA1_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L |
2726 | #define SDMA1_GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L |
2727 | #define SDMA1_GB_ADDR_CONFIG__NUM_PKRS_MASK 0x00000700L |
2728 | #define SDMA1_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L |
2729 | #define SDMA1_GB_ADDR_CONFIG__NUM_RB_PER_SE_MASK 0x0C000000L |
2730 | //SDMA1_GB_ADDR_CONFIG_READ |
2731 | #define SDMA1_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0 |
2732 | #define SDMA1_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 |
2733 | #define SDMA1_GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS__SHIFT 0x6 |
2734 | #define SDMA1_GB_ADDR_CONFIG_READ__NUM_PKRS__SHIFT 0x8 |
2735 | #define SDMA1_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13 |
2736 | #define SDMA1_GB_ADDR_CONFIG_READ__NUM_RB_PER_SE__SHIFT 0x1a |
2737 | #define SDMA1_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L |
2738 | #define SDMA1_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L |
2739 | #define SDMA1_GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L |
2740 | #define SDMA1_GB_ADDR_CONFIG_READ__NUM_PKRS_MASK 0x00000700L |
2741 | #define SDMA1_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L |
2742 | #define SDMA1_GB_ADDR_CONFIG_READ__NUM_RB_PER_SE_MASK 0x0C000000L |
2743 | //SDMA1_RB_RPTR_FETCH |
2744 | #define SDMA1_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 |
2745 | #define SDMA1_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL |
2746 | //SDMA1_RB_RPTR_FETCH_HI |
2747 | #define SDMA1_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0 |
2748 | #define SDMA1_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL |
2749 | //SDMA1_SEM_WAIT_FAIL_TIMER_CNTL |
2750 | #define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0 |
2751 | #define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xFFFFFFFFL |
2752 | //SDMA1_IB_OFFSET_FETCH |
2753 | #define SDMA1_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 |
2754 | #define SDMA1_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL |
2755 | //SDMA1_PROGRAM |
2756 | #define SDMA1_PROGRAM__STREAM__SHIFT 0x0 |
2757 | #define SDMA1_PROGRAM__STREAM_MASK 0xFFFFFFFFL |
2758 | //SDMA1_STATUS_REG |
2759 | #define SDMA1_STATUS_REG__IDLE__SHIFT 0x0 |
2760 | #define SDMA1_STATUS_REG__REG_IDLE__SHIFT 0x1 |
2761 | #define SDMA1_STATUS_REG__RB_EMPTY__SHIFT 0x2 |
2762 | #define SDMA1_STATUS_REG__RB_FULL__SHIFT 0x3 |
2763 | #define SDMA1_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 |
2764 | #define SDMA1_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 |
2765 | #define SDMA1_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 |
2766 | #define SDMA1_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 |
2767 | #define SDMA1_STATUS_REG__BLOCK_IDLE__SHIFT 0x8 |
2768 | #define SDMA1_STATUS_REG__INSIDE_IB__SHIFT 0x9 |
2769 | #define SDMA1_STATUS_REG__EX_IDLE__SHIFT 0xa |
2770 | #define SDMA1_STATUS_REG__CGCG_FENCE__SHIFT 0xb |
2771 | #define SDMA1_STATUS_REG__PACKET_READY__SHIFT 0xc |
2772 | #define SDMA1_STATUS_REG__MC_WR_IDLE__SHIFT 0xd |
2773 | #define SDMA1_STATUS_REG__SRBM_IDLE__SHIFT 0xe |
2774 | #define SDMA1_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf |
2775 | #define SDMA1_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10 |
2776 | #define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 |
2777 | #define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 |
2778 | #define SDMA1_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 |
2779 | #define SDMA1_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14 |
2780 | #define SDMA1_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15 |
2781 | #define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 |
2782 | #define SDMA1_STATUS_REG__DRM_IDLE__SHIFT 0x17 |
2783 | #define SDMA1_STATUS_REG__DRM_MASK_FULL__SHIFT 0x18 |
2784 | #define SDMA1_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19 |
2785 | #define SDMA1_STATUS_REG__SEM_IDLE__SHIFT 0x1a |
2786 | #define SDMA1_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b |
2787 | #define SDMA1_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c |
2788 | #define SDMA1_STATUS_REG__INT_IDLE__SHIFT 0x1e |
2789 | #define SDMA1_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f |
2790 | #define SDMA1_STATUS_REG__IDLE_MASK 0x00000001L |
2791 | #define SDMA1_STATUS_REG__REG_IDLE_MASK 0x00000002L |
2792 | #define SDMA1_STATUS_REG__RB_EMPTY_MASK 0x00000004L |
2793 | #define SDMA1_STATUS_REG__RB_FULL_MASK 0x00000008L |
2794 | #define SDMA1_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L |
2795 | #define SDMA1_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L |
2796 | #define SDMA1_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L |
2797 | #define SDMA1_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L |
2798 | #define SDMA1_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L |
2799 | #define SDMA1_STATUS_REG__INSIDE_IB_MASK 0x00000200L |
2800 | #define SDMA1_STATUS_REG__EX_IDLE_MASK 0x00000400L |
2801 | #define SDMA1_STATUS_REG__CGCG_FENCE_MASK 0x00000800L |
2802 | #define SDMA1_STATUS_REG__PACKET_READY_MASK 0x00001000L |
2803 | #define SDMA1_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L |
2804 | #define SDMA1_STATUS_REG__SRBM_IDLE_MASK 0x00004000L |
2805 | #define SDMA1_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L |
2806 | #define SDMA1_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L |
2807 | #define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L |
2808 | #define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L |
2809 | #define SDMA1_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L |
2810 | #define SDMA1_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L |
2811 | #define SDMA1_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L |
2812 | #define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L |
2813 | #define SDMA1_STATUS_REG__DRM_IDLE_MASK 0x00800000L |
2814 | #define SDMA1_STATUS_REG__DRM_MASK_FULL_MASK 0x01000000L |
2815 | #define SDMA1_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L |
2816 | #define SDMA1_STATUS_REG__SEM_IDLE_MASK 0x04000000L |
2817 | #define SDMA1_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L |
2818 | #define SDMA1_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L |
2819 | #define SDMA1_STATUS_REG__INT_IDLE_MASK 0x40000000L |
2820 | #define SDMA1_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L |
2821 | //SDMA1_STATUS1_REG |
2822 | #define SDMA1_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 |
2823 | #define SDMA1_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 |
2824 | #define SDMA1_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2 |
2825 | #define SDMA1_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 |
2826 | #define SDMA1_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 |
2827 | #define SDMA1_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 |
2828 | #define SDMA1_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 |
2829 | #define SDMA1_STATUS1_REG__CE_DRM_IDLE__SHIFT 0x7 |
2830 | #define SDMA1_STATUS1_REG__CE_DRM1_IDLE__SHIFT 0x8 |
2831 | #define SDMA1_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9 |
2832 | #define SDMA1_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa |
2833 | #define SDMA1_STATUS1_REG__CE_INFO_FULL__SHIFT 0xb |
2834 | #define SDMA1_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xc |
2835 | #define SDMA1_STATUS1_REG__EX_START__SHIFT 0xd |
2836 | #define SDMA1_STATUS1_REG__DRM_CTX_RESTORE__SHIFT 0xe |
2837 | #define SDMA1_STATUS1_REG__CE_RD_STALL__SHIFT 0xf |
2838 | #define SDMA1_STATUS1_REG__CE_WR_STALL__SHIFT 0x10 |
2839 | #define SDMA1_STATUS1_REG__SEC_INTR_STATUS__SHIFT 0x11 |
2840 | #define SDMA1_STATUS1_REG__WPTR_POLL_IDLE__SHIFT 0x12 |
2841 | #define SDMA1_STATUS1_REG__SDMA_IDLE__SHIFT 0x13 |
2842 | #define SDMA1_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L |
2843 | #define SDMA1_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L |
2844 | #define SDMA1_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L |
2845 | #define SDMA1_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L |
2846 | #define SDMA1_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L |
2847 | #define SDMA1_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L |
2848 | #define SDMA1_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L |
2849 | #define SDMA1_STATUS1_REG__CE_DRM_IDLE_MASK 0x00000080L |
2850 | #define SDMA1_STATUS1_REG__CE_DRM1_IDLE_MASK 0x00000100L |
2851 | #define SDMA1_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L |
2852 | #define SDMA1_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L |
2853 | #define SDMA1_STATUS1_REG__CE_INFO_FULL_MASK 0x00000800L |
2854 | #define SDMA1_STATUS1_REG__CE_INFO1_FULL_MASK 0x00001000L |
2855 | #define SDMA1_STATUS1_REG__EX_START_MASK 0x00002000L |
2856 | #define SDMA1_STATUS1_REG__DRM_CTX_RESTORE_MASK 0x00004000L |
2857 | #define SDMA1_STATUS1_REG__CE_RD_STALL_MASK 0x00008000L |
2858 | #define SDMA1_STATUS1_REG__CE_WR_STALL_MASK 0x00010000L |
2859 | #define SDMA1_STATUS1_REG__SEC_INTR_STATUS_MASK 0x00020000L |
2860 | #define SDMA1_STATUS1_REG__WPTR_POLL_IDLE_MASK 0x00040000L |
2861 | #define SDMA1_STATUS1_REG__SDMA_IDLE_MASK 0x00080000L |
2862 | //SDMA1_CNTL1 |
2863 | #define SDMA1_CNTL1__WPTR_POLL_FREQUENCY__SHIFT 0x2 |
2864 | #define SDMA1_CNTL1__WPTR_POLL_FREQUENCY_MASK 0x0000FFFCL |
2865 | //SDMA1_HBM_PAGE_CONFIG |
2866 | #define SDMA1_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0 |
2867 | #define SDMA1_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000003L |
2868 | //SDMA1_UCODE_CHECKSUM |
2869 | #define SDMA1_UCODE_CHECKSUM__DATA__SHIFT 0x0 |
2870 | #define SDMA1_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL |
2871 | //SDMA1_FREEZE |
2872 | #define SDMA1_FREEZE__PREEMPT__SHIFT 0x0 |
2873 | #define SDMA1_FREEZE__FREEZE__SHIFT 0x4 |
2874 | #define SDMA1_FREEZE__FROZEN__SHIFT 0x5 |
2875 | #define SDMA1_FREEZE__F32_FREEZE__SHIFT 0x6 |
2876 | #define SDMA1_FREEZE__PREEMPT_MASK 0x00000001L |
2877 | #define SDMA1_FREEZE__FREEZE_MASK 0x00000010L |
2878 | #define SDMA1_FREEZE__FROZEN_MASK 0x00000020L |
2879 | #define SDMA1_FREEZE__F32_FREEZE_MASK 0x00000040L |
2880 | //SDMA1_PROCESS_QUANTUM0 |
2881 | #define SDMA1_PROCESS_QUANTUM0__PROCESS0_QUANTUM__SHIFT 0x0 |
2882 | #define SDMA1_PROCESS_QUANTUM0__PROCESS1_QUANTUM__SHIFT 0x8 |
2883 | #define SDMA1_PROCESS_QUANTUM0__PROCESS2_QUANTUM__SHIFT 0x10 |
2884 | #define SDMA1_PROCESS_QUANTUM0__PROCESS3_QUANTUM__SHIFT 0x18 |
2885 | #define SDMA1_PROCESS_QUANTUM0__PROCESS0_QUANTUM_MASK 0x000000FFL |
2886 | #define SDMA1_PROCESS_QUANTUM0__PROCESS1_QUANTUM_MASK 0x0000FF00L |
2887 | #define SDMA1_PROCESS_QUANTUM0__PROCESS2_QUANTUM_MASK 0x00FF0000L |
2888 | #define SDMA1_PROCESS_QUANTUM0__PROCESS3_QUANTUM_MASK 0xFF000000L |
2889 | //SDMA1_PROCESS_QUANTUM1 |
2890 | #define SDMA1_PROCESS_QUANTUM1__PROCESS4_QUANTUM__SHIFT 0x0 |
2891 | #define SDMA1_PROCESS_QUANTUM1__PROCESS5_QUANTUM__SHIFT 0x8 |
2892 | #define SDMA1_PROCESS_QUANTUM1__PROCESS6_QUANTUM__SHIFT 0x10 |
2893 | #define SDMA1_PROCESS_QUANTUM1__PROCESS7_QUANTUM__SHIFT 0x18 |
2894 | #define SDMA1_PROCESS_QUANTUM1__PROCESS4_QUANTUM_MASK 0x000000FFL |
2895 | #define SDMA1_PROCESS_QUANTUM1__PROCESS5_QUANTUM_MASK 0x0000FF00L |
2896 | #define SDMA1_PROCESS_QUANTUM1__PROCESS6_QUANTUM_MASK 0x00FF0000L |
2897 | #define SDMA1_PROCESS_QUANTUM1__PROCESS7_QUANTUM_MASK 0xFF000000L |
2898 | //SDMA1_WATCHDOG_CNTL |
2899 | #define SDMA1_WATCHDOG_CNTL__QUEUE_HANG_COUNT__SHIFT 0x0 |
2900 | #define SDMA1_WATCHDOG_CNTL__CMD_TIMEOUT_COUNT__SHIFT 0x8 |
2901 | #define SDMA1_WATCHDOG_CNTL__QUEUE_HANG_COUNT_MASK 0x000000FFL |
2902 | #define SDMA1_WATCHDOG_CNTL__CMD_TIMEOUT_COUNT_MASK 0x0000FF00L |
2903 | //SDMA1_QUEUE_STATUS0 |
2904 | #define SDMA1_QUEUE_STATUS0__QUEUE0_STATUS__SHIFT 0x0 |
2905 | #define SDMA1_QUEUE_STATUS0__QUEUE1_STATUS__SHIFT 0x4 |
2906 | #define SDMA1_QUEUE_STATUS0__QUEUE2_STATUS__SHIFT 0x8 |
2907 | #define SDMA1_QUEUE_STATUS0__QUEUE3_STATUS__SHIFT 0xc |
2908 | #define SDMA1_QUEUE_STATUS0__QUEUE4_STATUS__SHIFT 0x10 |
2909 | #define SDMA1_QUEUE_STATUS0__QUEUE5_STATUS__SHIFT 0x14 |
2910 | #define SDMA1_QUEUE_STATUS0__QUEUE6_STATUS__SHIFT 0x18 |
2911 | #define SDMA1_QUEUE_STATUS0__QUEUE7_STATUS__SHIFT 0x1c |
2912 | #define SDMA1_QUEUE_STATUS0__QUEUE0_STATUS_MASK 0x0000000FL |
2913 | #define SDMA1_QUEUE_STATUS0__QUEUE1_STATUS_MASK 0x000000F0L |
2914 | #define SDMA1_QUEUE_STATUS0__QUEUE2_STATUS_MASK 0x00000F00L |
2915 | #define SDMA1_QUEUE_STATUS0__QUEUE3_STATUS_MASK 0x0000F000L |
2916 | #define SDMA1_QUEUE_STATUS0__QUEUE4_STATUS_MASK 0x000F0000L |
2917 | #define SDMA1_QUEUE_STATUS0__QUEUE5_STATUS_MASK 0x00F00000L |
2918 | #define SDMA1_QUEUE_STATUS0__QUEUE6_STATUS_MASK 0x0F000000L |
2919 | #define SDMA1_QUEUE_STATUS0__QUEUE7_STATUS_MASK 0xF0000000L |
2920 | //SDMA1_EDC_CONFIG |
2921 | #define SDMA1_EDC_CONFIG__WRITE_DIS__SHIFT 0x0 |
2922 | #define SDMA1_EDC_CONFIG__DIS_EDC__SHIFT 0x1 |
2923 | #define SDMA1_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2 |
2924 | #define SDMA1_EDC_CONFIG__WRITE_DIS_MASK 0x00000001L |
2925 | #define SDMA1_EDC_CONFIG__DIS_EDC_MASK 0x00000002L |
2926 | #define SDMA1_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x00000004L |
2927 | //SDMA1_BA_THRESHOLD |
2928 | #define SDMA1_BA_THRESHOLD__READ_THRES__SHIFT 0x0 |
2929 | #define SDMA1_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10 |
2930 | #define SDMA1_BA_THRESHOLD__READ_THRES_MASK 0x000003FFL |
2931 | #define SDMA1_BA_THRESHOLD__WRITE_THRES_MASK 0x03FF0000L |
2932 | //SDMA1_ID |
2933 | #define SDMA1_ID__DEVICE_ID__SHIFT 0x0 |
2934 | #define SDMA1_ID__DEVICE_ID_MASK 0x000000FFL |
2935 | //SDMA1_VERSION |
2936 | #define SDMA1_VERSION__MINVER__SHIFT 0x0 |
2937 | #define SDMA1_VERSION__MAJVER__SHIFT 0x8 |
2938 | #define SDMA1_VERSION__REV__SHIFT 0x10 |
2939 | #define SDMA1_VERSION__MINVER_MASK 0x0000007FL |
2940 | #define SDMA1_VERSION__MAJVER_MASK 0x00007F00L |
2941 | #define SDMA1_VERSION__REV_MASK 0x003F0000L |
2942 | //SDMA1_EDC_COUNTER |
2943 | #define SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_DED__SHIFT 0x0 |
2944 | #define SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_SEC__SHIFT 0x1 |
2945 | #define SDMA1_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT 0x2 |
2946 | #define SDMA1_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT 0x3 |
2947 | #define SDMA1_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT 0x4 |
2948 | #define SDMA1_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x5 |
2949 | #define SDMA1_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT 0x6 |
2950 | #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT 0x7 |
2951 | #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT 0x8 |
2952 | #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT 0x9 |
2953 | #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0xa |
2954 | #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT 0xb |
2955 | #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xc |
2956 | #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT 0xd |
2957 | #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT 0xe |
2958 | #define SDMA1_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT 0xf |
2959 | #define SDMA1_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x10 |
2960 | #define SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_DED_MASK 0x00000001L |
2961 | #define SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_SEC_MASK 0x00000002L |
2962 | #define SDMA1_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK 0x00000004L |
2963 | #define SDMA1_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK 0x00000008L |
2964 | #define SDMA1_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK 0x00000010L |
2965 | #define SDMA1_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000020L |
2966 | #define SDMA1_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK 0x00000040L |
2967 | #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK 0x00000080L |
2968 | #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK 0x00000100L |
2969 | #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK 0x00000200L |
2970 | #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK 0x00000400L |
2971 | #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK 0x00000800L |
2972 | #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK 0x00001000L |
2973 | #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK 0x00002000L |
2974 | #define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK 0x00004000L |
2975 | #define SDMA1_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK 0x00008000L |
2976 | #define SDMA1_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK 0x00010000L |
2977 | //SDMA1_EDC_COUNTER_CLEAR |
2978 | #define SDMA1_EDC_COUNTER_CLEAR__DUMMY__SHIFT 0x0 |
2979 | #define SDMA1_EDC_COUNTER_CLEAR__DUMMY_MASK 0x00000001L |
2980 | //SDMA1_STATUS2_REG |
2981 | #define SDMA1_STATUS2_REG__ID__SHIFT 0x0 |
2982 | #define SDMA1_STATUS2_REG__TH0F32_INSTR_PTR__SHIFT 0x2 |
2983 | #define SDMA1_STATUS2_REG__CMD_OP__SHIFT 0x10 |
2984 | #define SDMA1_STATUS2_REG__ID_MASK 0x00000003L |
2985 | #define SDMA1_STATUS2_REG__TH0F32_INSTR_PTR_MASK 0x0000FFFCL |
2986 | #define SDMA1_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L |
2987 | //SDMA1_ATOMIC_CNTL |
2988 | #define SDMA1_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 |
2989 | #define SDMA1_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f |
2990 | #define SDMA1_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL |
2991 | #define SDMA1_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L |
2992 | //SDMA1_ATOMIC_PREOP_LO |
2993 | #define SDMA1_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 |
2994 | #define SDMA1_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL |
2995 | //SDMA1_ATOMIC_PREOP_HI |
2996 | #define SDMA1_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 |
2997 | #define SDMA1_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL |
2998 | //SDMA1_UTCL1_CNTL |
2999 | #define SDMA1_UTCL1_CNTL__REDO_DELAY__SHIFT 0x0 |
3000 | #define SDMA1_UTCL1_CNTL__PAGE_WAIT_DELAY__SHIFT 0x5 |
3001 | #define SDMA1_UTCL1_CNTL__RESP_MODE__SHIFT 0x9 |
3002 | #define SDMA1_UTCL1_CNTL__FORCE_INVALIDATION__SHIFT 0xe |
3003 | #define SDMA1_UTCL1_CNTL__FORCE_INVREQ_HEAVY__SHIFT 0xf |
3004 | #define SDMA1_UTCL1_CNTL__WR_EXE_PERMS_CTRL__SHIFT 0x10 |
3005 | #define SDMA1_UTCL1_CNTL__RD_EXE_PERMS_CTRL__SHIFT 0x11 |
3006 | #define SDMA1_UTCL1_CNTL__INVACK_DELAY__SHIFT 0x12 |
3007 | #define SDMA1_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x18 |
3008 | #define SDMA1_UTCL1_CNTL__REDO_DELAY_MASK 0x0000001FL |
3009 | #define SDMA1_UTCL1_CNTL__PAGE_WAIT_DELAY_MASK 0x000001E0L |
3010 | #define SDMA1_UTCL1_CNTL__RESP_MODE_MASK 0x00000600L |
3011 | #define SDMA1_UTCL1_CNTL__FORCE_INVALIDATION_MASK 0x00004000L |
3012 | #define SDMA1_UTCL1_CNTL__FORCE_INVREQ_HEAVY_MASK 0x00008000L |
3013 | #define SDMA1_UTCL1_CNTL__WR_EXE_PERMS_CTRL_MASK 0x00010000L |
3014 | #define SDMA1_UTCL1_CNTL__RD_EXE_PERMS_CTRL_MASK 0x00020000L |
3015 | #define SDMA1_UTCL1_CNTL__INVACK_DELAY_MASK 0x003C0000L |
3016 | #define SDMA1_UTCL1_CNTL__REQL2_CREDIT_MASK 0x3F000000L |
3017 | //SDMA1_UTCL1_WATERMK |
3018 | #define SDMA1_UTCL1_WATERMK__WR_REQ_FIFO_WATERMK__SHIFT 0x0 |
3019 | #define SDMA1_UTCL1_WATERMK__WR_REQ_FIFO_DEPTH_STEP__SHIFT 0x4 |
3020 | #define SDMA1_UTCL1_WATERMK__RD_REQ_FIFO_WATERMK__SHIFT 0x6 |
3021 | #define SDMA1_UTCL1_WATERMK__RD_REQ_FIFO_DEPTH_STEP__SHIFT 0xa |
3022 | #define SDMA1_UTCL1_WATERMK__WR_PAGE_FIFO_WATERMK__SHIFT 0xc |
3023 | #define SDMA1_UTCL1_WATERMK__WR_PAGE_FIFO_DEPTH_STEP__SHIFT 0x10 |
3024 | #define SDMA1_UTCL1_WATERMK__RD_PAGE_FIFO_WATERMK__SHIFT 0x12 |
3025 | #define SDMA1_UTCL1_WATERMK__RD_PAGE_FIFO_DEPTH_STEP__SHIFT 0x16 |
3026 | #define SDMA1_UTCL1_WATERMK__WR_REQ_FIFO_WATERMK_MASK 0x0000000FL |
3027 | #define SDMA1_UTCL1_WATERMK__WR_REQ_FIFO_DEPTH_STEP_MASK 0x00000030L |
3028 | #define SDMA1_UTCL1_WATERMK__RD_REQ_FIFO_WATERMK_MASK 0x000003C0L |
3029 | #define SDMA1_UTCL1_WATERMK__RD_REQ_FIFO_DEPTH_STEP_MASK 0x00000C00L |
3030 | #define SDMA1_UTCL1_WATERMK__WR_PAGE_FIFO_WATERMK_MASK 0x0000F000L |
3031 | #define SDMA1_UTCL1_WATERMK__WR_PAGE_FIFO_DEPTH_STEP_MASK 0x00030000L |
3032 | #define SDMA1_UTCL1_WATERMK__RD_PAGE_FIFO_WATERMK_MASK 0x003C0000L |
3033 | #define SDMA1_UTCL1_WATERMK__RD_PAGE_FIFO_DEPTH_STEP_MASK 0x00C00000L |
3034 | //SDMA1_UTCL1_TIMEOUT |
3035 | #define SDMA1_UTCL1_TIMEOUT__XNACK_LIMIT__SHIFT 0x0 |
3036 | #define SDMA1_UTCL1_TIMEOUT__XNACK_LIMIT_MASK 0x0000FFFFL |
3037 | //SDMA1_UTCL1_PAGE |
3038 | #define SDMA1_UTCL1_PAGE__VM_HOLE__SHIFT 0x0 |
3039 | #define SDMA1_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1 |
3040 | #define SDMA1_UTCL1_PAGE__TMZ_ENABLE__SHIFT 0x5 |
3041 | #define SDMA1_UTCL1_PAGE__USE_MTYPE__SHIFT 0x6 |
3042 | #define SDMA1_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0xa |
3043 | #define SDMA1_UTCL1_PAGE__USE_IO__SHIFT 0xb |
3044 | #define SDMA1_UTCL1_PAGE__RD_L2_POLICY__SHIFT 0xc |
3045 | #define SDMA1_UTCL1_PAGE__WR_L2_POLICY__SHIFT 0xe |
3046 | #define SDMA1_UTCL1_PAGE__DMA_PAGE_SIZE__SHIFT 0x10 |
3047 | #define SDMA1_UTCL1_PAGE__USE_BC__SHIFT 0x16 |
3048 | #define SDMA1_UTCL1_PAGE__ADDR_IS_PA__SHIFT 0x17 |
3049 | #define SDMA1_UTCL1_PAGE__LLC_NOALLOC__SHIFT 0x18 |
3050 | #define SDMA1_UTCL1_PAGE__VM_HOLE_MASK 0x00000001L |
3051 | #define SDMA1_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001EL |
3052 | #define SDMA1_UTCL1_PAGE__TMZ_ENABLE_MASK 0x00000020L |
3053 | #define SDMA1_UTCL1_PAGE__USE_MTYPE_MASK 0x000003C0L |
3054 | #define SDMA1_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000400L |
3055 | #define SDMA1_UTCL1_PAGE__USE_IO_MASK 0x00000800L |
3056 | #define SDMA1_UTCL1_PAGE__RD_L2_POLICY_MASK 0x00003000L |
3057 | #define SDMA1_UTCL1_PAGE__WR_L2_POLICY_MASK 0x0000C000L |
3058 | #define SDMA1_UTCL1_PAGE__DMA_PAGE_SIZE_MASK 0x003F0000L |
3059 | #define SDMA1_UTCL1_PAGE__USE_BC_MASK 0x00400000L |
3060 | #define SDMA1_UTCL1_PAGE__ADDR_IS_PA_MASK 0x00800000L |
3061 | #define SDMA1_UTCL1_PAGE__LLC_NOALLOC_MASK 0x01000000L |
3062 | //SDMA1_UTCL1_RD_STATUS |
3063 | #define SDMA1_UTCL1_RD_STATUS__RD_VA_FIFO_EMPTY__SHIFT 0x0 |
3064 | #define SDMA1_UTCL1_RD_STATUS__RD_REG_ENTRY_EMPTY__SHIFT 0x1 |
3065 | #define SDMA1_UTCL1_RD_STATUS__RD_PAGE_FIFO_EMPTY__SHIFT 0x2 |
3066 | #define SDMA1_UTCL1_RD_STATUS__RD_REQ_FIFO_EMPTY__SHIFT 0x3 |
3067 | #define SDMA1_UTCL1_RD_STATUS__RD_VA_REQ_FIFO_EMPTY__SHIFT 0x4 |
3068 | #define SDMA1_UTCL1_RD_STATUS__RESERVED0__SHIFT 0x5 |
3069 | #define SDMA1_UTCL1_RD_STATUS__RESERVED1__SHIFT 0x6 |
3070 | #define SDMA1_UTCL1_RD_STATUS__META_Q_EMPTY__SHIFT 0x7 |
3071 | #define SDMA1_UTCL1_RD_STATUS__RD_VA_FIFO_FULL__SHIFT 0x8 |
3072 | #define SDMA1_UTCL1_RD_STATUS__RD_REG_ENTRY_FULL__SHIFT 0x9 |
3073 | #define SDMA1_UTCL1_RD_STATUS__RD_PAGE_FIFO_FULL__SHIFT 0xa |
3074 | #define SDMA1_UTCL1_RD_STATUS__RD_REQ_FIFO_FULL__SHIFT 0xb |
3075 | #define SDMA1_UTCL1_RD_STATUS__RD_VA_REQ_FIFO_FULL__SHIFT 0xc |
3076 | #define SDMA1_UTCL1_RD_STATUS__RESERVED2__SHIFT 0xd |
3077 | #define SDMA1_UTCL1_RD_STATUS__RESERVED3__SHIFT 0xe |
3078 | #define SDMA1_UTCL1_RD_STATUS__META_Q_FULL__SHIFT 0xf |
3079 | #define SDMA1_UTCL1_RD_STATUS__RD_L2_INTF_IDLE__SHIFT 0x10 |
3080 | #define SDMA1_UTCL1_RD_STATUS__RD_REQRET_IDLE__SHIFT 0x11 |
3081 | #define SDMA1_UTCL1_RD_STATUS__RD_REQ_IDLE__SHIFT 0x12 |
3082 | #define SDMA1_UTCL1_RD_STATUS__RD_MERGE_TYPE__SHIFT 0x13 |
3083 | #define SDMA1_UTCL1_RD_STATUS__RD_MERGE_DATA_PA_READY__SHIFT 0x15 |
3084 | #define SDMA1_UTCL1_RD_STATUS__RD_MERGE_META_PA_READY__SHIFT 0x16 |
3085 | #define SDMA1_UTCL1_RD_STATUS__RD_MERGE_REG_READY__SHIFT 0x17 |
3086 | #define SDMA1_UTCL1_RD_STATUS__RD_MERGE_PAGE_FIFO_READY__SHIFT 0x18 |
3087 | #define SDMA1_UTCL1_RD_STATUS__RD_MERGE_REQ_FIFO_READY__SHIFT 0x19 |
3088 | #define SDMA1_UTCL1_RD_STATUS__RESERVED4__SHIFT 0x1a |
3089 | #define SDMA1_UTCL1_RD_STATUS__RD_MERGE_OUT_RTR__SHIFT 0x1b |
3090 | #define SDMA1_UTCL1_RD_STATUS__RDREQ_IN_RTR__SHIFT 0x1c |
3091 | #define SDMA1_UTCL1_RD_STATUS__RDREQ_OUT_RTR__SHIFT 0x1d |
3092 | #define SDMA1_UTCL1_RD_STATUS__INV_BUSY__SHIFT 0x1e |
3093 | #define SDMA1_UTCL1_RD_STATUS__DBIT_REQ_IDLE__SHIFT 0x1f |
3094 | #define SDMA1_UTCL1_RD_STATUS__RD_VA_FIFO_EMPTY_MASK 0x00000001L |
3095 | #define SDMA1_UTCL1_RD_STATUS__RD_REG_ENTRY_EMPTY_MASK 0x00000002L |
3096 | #define SDMA1_UTCL1_RD_STATUS__RD_PAGE_FIFO_EMPTY_MASK 0x00000004L |
3097 | #define SDMA1_UTCL1_RD_STATUS__RD_REQ_FIFO_EMPTY_MASK 0x00000008L |
3098 | #define SDMA1_UTCL1_RD_STATUS__RD_VA_REQ_FIFO_EMPTY_MASK 0x00000010L |
3099 | #define SDMA1_UTCL1_RD_STATUS__RESERVED0_MASK 0x00000020L |
3100 | #define SDMA1_UTCL1_RD_STATUS__RESERVED1_MASK 0x00000040L |
3101 | #define SDMA1_UTCL1_RD_STATUS__META_Q_EMPTY_MASK 0x00000080L |
3102 | #define SDMA1_UTCL1_RD_STATUS__RD_VA_FIFO_FULL_MASK 0x00000100L |
3103 | #define SDMA1_UTCL1_RD_STATUS__RD_REG_ENTRY_FULL_MASK 0x00000200L |
3104 | #define SDMA1_UTCL1_RD_STATUS__RD_PAGE_FIFO_FULL_MASK 0x00000400L |
3105 | #define SDMA1_UTCL1_RD_STATUS__RD_REQ_FIFO_FULL_MASK 0x00000800L |
3106 | #define SDMA1_UTCL1_RD_STATUS__RD_VA_REQ_FIFO_FULL_MASK 0x00001000L |
3107 | #define SDMA1_UTCL1_RD_STATUS__RESERVED2_MASK 0x00002000L |
3108 | #define SDMA1_UTCL1_RD_STATUS__RESERVED3_MASK 0x00004000L |
3109 | #define SDMA1_UTCL1_RD_STATUS__META_Q_FULL_MASK 0x00008000L |
3110 | #define SDMA1_UTCL1_RD_STATUS__RD_L2_INTF_IDLE_MASK 0x00010000L |
3111 | #define SDMA1_UTCL1_RD_STATUS__RD_REQRET_IDLE_MASK 0x00020000L |
3112 | #define SDMA1_UTCL1_RD_STATUS__RD_REQ_IDLE_MASK 0x00040000L |
3113 | #define SDMA1_UTCL1_RD_STATUS__RD_MERGE_TYPE_MASK 0x00180000L |
3114 | #define SDMA1_UTCL1_RD_STATUS__RD_MERGE_DATA_PA_READY_MASK 0x00200000L |
3115 | #define SDMA1_UTCL1_RD_STATUS__RD_MERGE_META_PA_READY_MASK 0x00400000L |
3116 | #define SDMA1_UTCL1_RD_STATUS__RD_MERGE_REG_READY_MASK 0x00800000L |
3117 | #define SDMA1_UTCL1_RD_STATUS__RD_MERGE_PAGE_FIFO_READY_MASK 0x01000000L |
3118 | #define SDMA1_UTCL1_RD_STATUS__RD_MERGE_REQ_FIFO_READY_MASK 0x02000000L |
3119 | #define SDMA1_UTCL1_RD_STATUS__RESERVED4_MASK 0x04000000L |
3120 | #define SDMA1_UTCL1_RD_STATUS__RD_MERGE_OUT_RTR_MASK 0x08000000L |
3121 | #define SDMA1_UTCL1_RD_STATUS__RDREQ_IN_RTR_MASK 0x10000000L |
3122 | #define SDMA1_UTCL1_RD_STATUS__RDREQ_OUT_RTR_MASK 0x20000000L |
3123 | #define SDMA1_UTCL1_RD_STATUS__INV_BUSY_MASK 0x40000000L |
3124 | #define SDMA1_UTCL1_RD_STATUS__DBIT_REQ_IDLE_MASK 0x80000000L |
3125 | //SDMA1_UTCL1_WR_STATUS |
3126 | #define SDMA1_UTCL1_WR_STATUS__WR_VA_FIFO_EMPTY__SHIFT 0x0 |
3127 | #define SDMA1_UTCL1_WR_STATUS__WR_REG_ENTRY_EMPTY__SHIFT 0x1 |
3128 | #define SDMA1_UTCL1_WR_STATUS__WR_PAGE_FIFO_EMPTY__SHIFT 0x2 |
3129 | #define SDMA1_UTCL1_WR_STATUS__WR_REQ_FIFO_EMPTY__SHIFT 0x3 |
3130 | #define SDMA1_UTCL1_WR_STATUS__WR_VA_REQ_FIFO_EMPTY__SHIFT 0x4 |
3131 | #define SDMA1_UTCL1_WR_STATUS__WR_DATA2_EMPTY__SHIFT 0x5 |
3132 | #define SDMA1_UTCL1_WR_STATUS__WR_DATA1_EMPTY__SHIFT 0x6 |
3133 | #define SDMA1_UTCL1_WR_STATUS__RESERVED0__SHIFT 0x7 |
3134 | #define SDMA1_UTCL1_WR_STATUS__WR_VA_FIFO_FULL__SHIFT 0x8 |
3135 | #define SDMA1_UTCL1_WR_STATUS__WR_REG_ENTRY_FULL__SHIFT 0x9 |
3136 | #define SDMA1_UTCL1_WR_STATUS__WR_PAGE_FIFO_FULL__SHIFT 0xa |
3137 | #define SDMA1_UTCL1_WR_STATUS__WR_REQ_FIFO_FULL__SHIFT 0xb |
3138 | #define SDMA1_UTCL1_WR_STATUS__WR_VA_REQ_FIFO_FULL__SHIFT 0xc |
3139 | #define SDMA1_UTCL1_WR_STATUS__WR_DATA2_FULL__SHIFT 0xd |
3140 | #define SDMA1_UTCL1_WR_STATUS__WR_DATA1_FULL__SHIFT 0xe |
3141 | #define SDMA1_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0xf |
3142 | #define SDMA1_UTCL1_WR_STATUS__WR_L2_INTF_IDLE__SHIFT 0x10 |
3143 | #define SDMA1_UTCL1_WR_STATUS__WR_REQRET_IDLE__SHIFT 0x11 |
3144 | #define SDMA1_UTCL1_WR_STATUS__WR_REQ_IDLE__SHIFT 0x12 |
3145 | #define SDMA1_UTCL1_WR_STATUS__WR_MERGE_TYPE__SHIFT 0x13 |
3146 | #define SDMA1_UTCL1_WR_STATUS__WR_MERGE_DATA_PA_READY__SHIFT 0x15 |
3147 | #define SDMA1_UTCL1_WR_STATUS__WR_MERGE_META_PA_READY__SHIFT 0x16 |
3148 | #define SDMA1_UTCL1_WR_STATUS__WR_MERGE_REG_READY__SHIFT 0x17 |
3149 | #define SDMA1_UTCL1_WR_STATUS__WR_MERGE_PAGE_FIFO_READY__SHIFT 0x18 |
3150 | #define SDMA1_UTCL1_WR_STATUS__WR_MERGE_REQ_FIFO_READY__SHIFT 0x19 |
3151 | #define SDMA1_UTCL1_WR_STATUS__WR_MERGE_DATA_SEL__SHIFT 0x1a |
3152 | #define SDMA1_UTCL1_WR_STATUS__WR_MERGE_OUT_RTR__SHIFT 0x1b |
3153 | #define SDMA1_UTCL1_WR_STATUS__WRREQ_IN_RTR__SHIFT 0x1c |
3154 | #define SDMA1_UTCL1_WR_STATUS__WRREQ_OUT_RTR__SHIFT 0x1d |
3155 | #define SDMA1_UTCL1_WR_STATUS__WRREQ_IN_DATA1_RTR__SHIFT 0x1e |
3156 | #define SDMA1_UTCL1_WR_STATUS__WRREQ_IN_DATA2_RTR__SHIFT 0x1f |
3157 | #define SDMA1_UTCL1_WR_STATUS__WR_VA_FIFO_EMPTY_MASK 0x00000001L |
3158 | #define SDMA1_UTCL1_WR_STATUS__WR_REG_ENTRY_EMPTY_MASK 0x00000002L |
3159 | #define SDMA1_UTCL1_WR_STATUS__WR_PAGE_FIFO_EMPTY_MASK 0x00000004L |
3160 | #define SDMA1_UTCL1_WR_STATUS__WR_REQ_FIFO_EMPTY_MASK 0x00000008L |
3161 | #define SDMA1_UTCL1_WR_STATUS__WR_VA_REQ_FIFO_EMPTY_MASK 0x00000010L |
3162 | #define SDMA1_UTCL1_WR_STATUS__WR_DATA2_EMPTY_MASK 0x00000020L |
3163 | #define SDMA1_UTCL1_WR_STATUS__WR_DATA1_EMPTY_MASK 0x00000040L |
3164 | #define SDMA1_UTCL1_WR_STATUS__RESERVED0_MASK 0x00000080L |
3165 | #define SDMA1_UTCL1_WR_STATUS__WR_VA_FIFO_FULL_MASK 0x00000100L |
3166 | #define SDMA1_UTCL1_WR_STATUS__WR_REG_ENTRY_FULL_MASK 0x00000200L |
3167 | #define SDMA1_UTCL1_WR_STATUS__WR_PAGE_FIFO_FULL_MASK 0x00000400L |
3168 | #define SDMA1_UTCL1_WR_STATUS__WR_REQ_FIFO_FULL_MASK 0x00000800L |
3169 | #define SDMA1_UTCL1_WR_STATUS__WR_VA_REQ_FIFO_FULL_MASK 0x00001000L |
3170 | #define SDMA1_UTCL1_WR_STATUS__WR_DATA2_FULL_MASK 0x00002000L |
3171 | #define SDMA1_UTCL1_WR_STATUS__WR_DATA1_FULL_MASK 0x00004000L |
3172 | #define SDMA1_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x00008000L |
3173 | #define SDMA1_UTCL1_WR_STATUS__WR_L2_INTF_IDLE_MASK 0x00010000L |
3174 | #define SDMA1_UTCL1_WR_STATUS__WR_REQRET_IDLE_MASK 0x00020000L |
3175 | #define SDMA1_UTCL1_WR_STATUS__WR_REQ_IDLE_MASK 0x00040000L |
3176 | #define SDMA1_UTCL1_WR_STATUS__WR_MERGE_TYPE_MASK 0x00180000L |
3177 | #define SDMA1_UTCL1_WR_STATUS__WR_MERGE_DATA_PA_READY_MASK 0x00200000L |
3178 | #define SDMA1_UTCL1_WR_STATUS__WR_MERGE_META_PA_READY_MASK 0x00400000L |
3179 | #define SDMA1_UTCL1_WR_STATUS__WR_MERGE_REG_READY_MASK 0x00800000L |
3180 | #define SDMA1_UTCL1_WR_STATUS__WR_MERGE_PAGE_FIFO_READY_MASK 0x01000000L |
3181 | #define SDMA1_UTCL1_WR_STATUS__WR_MERGE_REQ_FIFO_READY_MASK 0x02000000L |
3182 | #define SDMA1_UTCL1_WR_STATUS__WR_MERGE_DATA_SEL_MASK 0x04000000L |
3183 | #define SDMA1_UTCL1_WR_STATUS__WR_MERGE_OUT_RTR_MASK 0x08000000L |
3184 | #define SDMA1_UTCL1_WR_STATUS__WRREQ_IN_RTR_MASK 0x10000000L |
3185 | #define SDMA1_UTCL1_WR_STATUS__WRREQ_OUT_RTR_MASK 0x20000000L |
3186 | #define SDMA1_UTCL1_WR_STATUS__WRREQ_IN_DATA1_RTR_MASK 0x40000000L |
3187 | #define SDMA1_UTCL1_WR_STATUS__WRREQ_IN_DATA2_RTR_MASK 0x80000000L |
3188 | //SDMA1_UTCL1_INV0 |
3189 | #define SDMA1_UTCL1_INV0__INV_PROC_BUSY__SHIFT 0x0 |
3190 | #define SDMA1_UTCL1_INV0__GPUVM_FRAG_SIZE__SHIFT 0x1 |
3191 | #define SDMA1_UTCL1_INV0__GPUVM_VMID__SHIFT 0x7 |
3192 | #define SDMA1_UTCL1_INV0__GPUVM_MODE__SHIFT 0xb |
3193 | #define SDMA1_UTCL1_INV0__GPUVM_HIGH__SHIFT 0xd |
3194 | #define SDMA1_UTCL1_INV0__GPUVM_TAG__SHIFT 0xe |
3195 | #define SDMA1_UTCL1_INV0__GPUVM_VMID_HIGH__SHIFT 0x12 |
3196 | #define SDMA1_UTCL1_INV0__GPUVM_VMID_LOW__SHIFT 0x16 |
3197 | #define SDMA1_UTCL1_INV0__INV_TYPE__SHIFT 0x1a |
3198 | #define SDMA1_UTCL1_INV0__INV_PROC_BUSY_MASK 0x00000001L |
3199 | #define SDMA1_UTCL1_INV0__GPUVM_FRAG_SIZE_MASK 0x0000007EL |
3200 | #define SDMA1_UTCL1_INV0__GPUVM_VMID_MASK 0x00000780L |
3201 | #define SDMA1_UTCL1_INV0__GPUVM_MODE_MASK 0x00001800L |
3202 | #define SDMA1_UTCL1_INV0__GPUVM_HIGH_MASK 0x00002000L |
3203 | #define SDMA1_UTCL1_INV0__GPUVM_TAG_MASK 0x0003C000L |
3204 | #define SDMA1_UTCL1_INV0__GPUVM_VMID_HIGH_MASK 0x003C0000L |
3205 | #define SDMA1_UTCL1_INV0__GPUVM_VMID_LOW_MASK 0x03C00000L |
3206 | #define SDMA1_UTCL1_INV0__INV_TYPE_MASK 0x0C000000L |
3207 | //SDMA1_UTCL1_INV1 |
3208 | #define SDMA1_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0 |
3209 | #define SDMA1_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL |
3210 | //SDMA1_UTCL1_INV2 |
3211 | #define SDMA1_UTCL1_INV2__CPF_VMID__SHIFT 0x0 |
3212 | #define SDMA1_UTCL1_INV2__CPF_FLUSH_TYPE__SHIFT 0x10 |
3213 | #define SDMA1_UTCL1_INV2__CPF_FRAG_SIZE__SHIFT 0x11 |
3214 | #define SDMA1_UTCL1_INV2__CPF_VMID_MASK 0x0000FFFFL |
3215 | #define SDMA1_UTCL1_INV2__CPF_FLUSH_TYPE_MASK 0x00010000L |
3216 | #define SDMA1_UTCL1_INV2__CPF_FRAG_SIZE_MASK 0x007E0000L |
3217 | //SDMA1_UTCL1_RD_XNACK0 |
3218 | #define SDMA1_UTCL1_RD_XNACK0__XNACK_FAULT_ADDR_LO__SHIFT 0x0 |
3219 | #define SDMA1_UTCL1_RD_XNACK0__XNACK_FAULT_ADDR_LO_MASK 0xFFFFFFFFL |
3220 | //SDMA1_UTCL1_RD_XNACK1 |
3221 | #define SDMA1_UTCL1_RD_XNACK1__XNACK_FAULT_ADDR_HI__SHIFT 0x0 |
3222 | #define SDMA1_UTCL1_RD_XNACK1__XNACK_FAULT_VMID__SHIFT 0x4 |
3223 | #define SDMA1_UTCL1_RD_XNACK1__XNACK_FAULT_VECTOR__SHIFT 0x8 |
3224 | #define SDMA1_UTCL1_RD_XNACK1__XNACK_NULL_VECTOR__SHIFT 0xa |
3225 | #define SDMA1_UTCL1_RD_XNACK1__XNACK_TIMEOUT_VECTOR__SHIFT 0xc |
3226 | #define SDMA1_UTCL1_RD_XNACK1__XNACK_FAULT_FLAG__SHIFT 0xe |
3227 | #define SDMA1_UTCL1_RD_XNACK1__XNACK_NULL_FLAG__SHIFT 0xf |
3228 | #define SDMA1_UTCL1_RD_XNACK1__XNACK_TIMEOUT_FLAG__SHIFT 0x10 |
3229 | #define SDMA1_UTCL1_RD_XNACK1__XNACK_FAULT_ADDR_HI_MASK 0x0000000FL |
3230 | #define SDMA1_UTCL1_RD_XNACK1__XNACK_FAULT_VMID_MASK 0x000000F0L |
3231 | #define SDMA1_UTCL1_RD_XNACK1__XNACK_FAULT_VECTOR_MASK 0x00000300L |
3232 | #define SDMA1_UTCL1_RD_XNACK1__XNACK_NULL_VECTOR_MASK 0x00000C00L |
3233 | #define SDMA1_UTCL1_RD_XNACK1__XNACK_TIMEOUT_VECTOR_MASK 0x00003000L |
3234 | #define SDMA1_UTCL1_RD_XNACK1__XNACK_FAULT_FLAG_MASK 0x00004000L |
3235 | #define SDMA1_UTCL1_RD_XNACK1__XNACK_NULL_FLAG_MASK 0x00008000L |
3236 | #define SDMA1_UTCL1_RD_XNACK1__XNACK_TIMEOUT_FLAG_MASK 0x00010000L |
3237 | //SDMA1_UTCL1_WR_XNACK0 |
3238 | #define SDMA1_UTCL1_WR_XNACK0__XNACK_FAULT_ADDR_LO__SHIFT 0x0 |
3239 | #define SDMA1_UTCL1_WR_XNACK0__XNACK_FAULT_ADDR_LO_MASK 0xFFFFFFFFL |
3240 | //SDMA1_UTCL1_WR_XNACK1 |
3241 | #define SDMA1_UTCL1_WR_XNACK1__XNACK_FAULT_ADDR_HI__SHIFT 0x0 |
3242 | #define SDMA1_UTCL1_WR_XNACK1__XNACK_FAULT_VMID__SHIFT 0x4 |
3243 | #define SDMA1_UTCL1_WR_XNACK1__XNACK_FAULT_VECTOR__SHIFT 0x8 |
3244 | #define SDMA1_UTCL1_WR_XNACK1__XNACK_NULL_VECTOR__SHIFT 0xa |
3245 | #define SDMA1_UTCL1_WR_XNACK1__XNACK_TIMEOUT_VECTOR__SHIFT 0xc |
3246 | #define SDMA1_UTCL1_WR_XNACK1__XNACK_FAULT_FLAG__SHIFT 0xe |
3247 | #define SDMA1_UTCL1_WR_XNACK1__XNACK_NULL_FLAG__SHIFT 0xf |
3248 | #define SDMA1_UTCL1_WR_XNACK1__XNACK_TIMEOUT_FLAG__SHIFT 0x10 |
3249 | #define SDMA1_UTCL1_WR_XNACK1__XNACK_FAULT_ADDR_HI_MASK 0x0000000FL |
3250 | #define SDMA1_UTCL1_WR_XNACK1__XNACK_FAULT_VMID_MASK 0x000000F0L |
3251 | #define SDMA1_UTCL1_WR_XNACK1__XNACK_FAULT_VECTOR_MASK 0x00000300L |
3252 | #define SDMA1_UTCL1_WR_XNACK1__XNACK_NULL_VECTOR_MASK 0x00000C00L |
3253 | #define SDMA1_UTCL1_WR_XNACK1__XNACK_TIMEOUT_VECTOR_MASK 0x00003000L |
3254 | #define SDMA1_UTCL1_WR_XNACK1__XNACK_FAULT_FLAG_MASK 0x00004000L |
3255 | #define SDMA1_UTCL1_WR_XNACK1__XNACK_NULL_FLAG_MASK 0x00008000L |
3256 | #define SDMA1_UTCL1_WR_XNACK1__XNACK_TIMEOUT_FLAG_MASK 0x00010000L |
3257 | //SDMA1_RELAX_ORDERING_LUT |
3258 | #define SDMA1_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0 |
3259 | #define SDMA1_RELAX_ORDERING_LUT__COPY__SHIFT 0x1 |
3260 | #define SDMA1_RELAX_ORDERING_LUT__WRITE__SHIFT 0x2 |
3261 | #define SDMA1_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3 |
3262 | #define SDMA1_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4 |
3263 | #define SDMA1_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5 |
3264 | #define SDMA1_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6 |
3265 | #define SDMA1_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8 |
3266 | #define SDMA1_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9 |
3267 | #define SDMA1_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa |
3268 | #define SDMA1_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0xb |
3269 | #define SDMA1_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0xc |
3270 | #define SDMA1_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd |
3271 | #define SDMA1_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe |
3272 | #define SDMA1_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b |
3273 | #define SDMA1_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c |
3274 | #define SDMA1_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d |
3275 | #define SDMA1_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e |
3276 | #define SDMA1_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f |
3277 | #define SDMA1_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L |
3278 | #define SDMA1_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L |
3279 | #define SDMA1_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L |
3280 | #define SDMA1_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L |
3281 | #define SDMA1_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L |
3282 | #define SDMA1_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L |
3283 | #define SDMA1_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L |
3284 | #define SDMA1_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L |
3285 | #define SDMA1_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L |
3286 | #define SDMA1_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L |
3287 | #define SDMA1_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L |
3288 | #define SDMA1_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L |
3289 | #define SDMA1_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L |
3290 | #define SDMA1_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L |
3291 | #define SDMA1_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L |
3292 | #define SDMA1_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L |
3293 | #define SDMA1_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L |
3294 | #define SDMA1_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L |
3295 | #define SDMA1_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L |
3296 | //SDMA1_CHICKEN_BITS_2 |
3297 | #define SDMA1_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x0 |
3298 | #define SDMA1_CHICKEN_BITS_2__F32_SEND_POSTCODE_EN__SHIFT 0x4 |
3299 | #define SDMA1_CHICKEN_BITS_2__UCODE_BUF_DS_EN__SHIFT 0x6 |
3300 | #define SDMA1_CHICKEN_BITS_2__UCODE_SELFLOAD_THREAD_OVERLAP__SHIFT 0x7 |
3301 | #define SDMA1_CHICKEN_BITS_2__WPTR_POLL_OUTSTANDING__SHIFT 0x8 |
3302 | #define SDMA1_CHICKEN_BITS_2__RESERVED_14_12__SHIFT 0xc |
3303 | #define SDMA1_CHICKEN_BITS_2__RESERVED_15__SHIFT 0xf |
3304 | #define SDMA1_CHICKEN_BITS_2__RB_FIFO_WATERMARK__SHIFT 0x10 |
3305 | #define SDMA1_CHICKEN_BITS_2__IB_FIFO_WATERMARK__SHIFT 0x12 |
3306 | #define SDMA1_CHICKEN_BITS_2__RESERVED_22_20__SHIFT 0x14 |
3307 | #define SDMA1_CHICKEN_BITS_2__CH_RD_WATERMARK__SHIFT 0x17 |
3308 | #define SDMA1_CHICKEN_BITS_2__CH_WR_WATERMARK__SHIFT 0x19 |
3309 | #define SDMA1_CHICKEN_BITS_2__CH_WR_WATERMARK_LSB__SHIFT 0x1e |
3310 | #define SDMA1_CHICKEN_BITS_2__PIO_VFID_SOURCE__SHIFT 0x1f |
3311 | #define SDMA1_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000FL |
3312 | #define SDMA1_CHICKEN_BITS_2__F32_SEND_POSTCODE_EN_MASK 0x00000010L |
3313 | #define SDMA1_CHICKEN_BITS_2__UCODE_BUF_DS_EN_MASK 0x00000040L |
3314 | #define SDMA1_CHICKEN_BITS_2__UCODE_SELFLOAD_THREAD_OVERLAP_MASK 0x00000080L |
3315 | #define SDMA1_CHICKEN_BITS_2__WPTR_POLL_OUTSTANDING_MASK 0x00000F00L |
3316 | #define SDMA1_CHICKEN_BITS_2__RESERVED_14_12_MASK 0x00007000L |
3317 | #define SDMA1_CHICKEN_BITS_2__RESERVED_15_MASK 0x00008000L |
3318 | #define SDMA1_CHICKEN_BITS_2__RB_FIFO_WATERMARK_MASK 0x00030000L |
3319 | #define SDMA1_CHICKEN_BITS_2__IB_FIFO_WATERMARK_MASK 0x000C0000L |
3320 | #define SDMA1_CHICKEN_BITS_2__RESERVED_22_20_MASK 0x00700000L |
3321 | #define SDMA1_CHICKEN_BITS_2__CH_RD_WATERMARK_MASK 0x01800000L |
3322 | #define SDMA1_CHICKEN_BITS_2__CH_WR_WATERMARK_MASK 0x3E000000L |
3323 | #define SDMA1_CHICKEN_BITS_2__CH_WR_WATERMARK_LSB_MASK 0x40000000L |
3324 | #define SDMA1_CHICKEN_BITS_2__PIO_VFID_SOURCE_MASK 0x80000000L |
3325 | //SDMA1_STATUS3_REG |
3326 | #define SDMA1_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x0 |
3327 | #define SDMA1_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10 |
3328 | #define SDMA1_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14 |
3329 | #define SDMA1_STATUS3_REG__AQL_PREV_CMD_IDLE__SHIFT 0x15 |
3330 | #define SDMA1_STATUS3_REG__TLBI_IDLE__SHIFT 0x16 |
3331 | #define SDMA1_STATUS3_REG__GCR_IDLE__SHIFT 0x17 |
3332 | #define SDMA1_STATUS3_REG__INVREQ_IDLE__SHIFT 0x18 |
3333 | #define SDMA1_STATUS3_REG__QUEUE_ID_MATCH__SHIFT 0x19 |
3334 | #define SDMA1_STATUS3_REG__INT_QUEUE_ID__SHIFT 0x1a |
3335 | #define SDMA1_STATUS3_REG__TMZ_MTYPE_STATUS__SHIFT 0x1e |
3336 | #define SDMA1_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000FFFFL |
3337 | #define SDMA1_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L |
3338 | #define SDMA1_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L |
3339 | #define SDMA1_STATUS3_REG__AQL_PREV_CMD_IDLE_MASK 0x00200000L |
3340 | #define SDMA1_STATUS3_REG__TLBI_IDLE_MASK 0x00400000L |
3341 | #define SDMA1_STATUS3_REG__GCR_IDLE_MASK 0x00800000L |
3342 | #define SDMA1_STATUS3_REG__INVREQ_IDLE_MASK 0x01000000L |
3343 | #define SDMA1_STATUS3_REG__QUEUE_ID_MATCH_MASK 0x02000000L |
3344 | #define SDMA1_STATUS3_REG__INT_QUEUE_ID_MASK 0x3C000000L |
3345 | #define SDMA1_STATUS3_REG__TMZ_MTYPE_STATUS_MASK 0xC0000000L |
3346 | //SDMA1_PHYSICAL_ADDR_LO |
3347 | #define SDMA1_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x0 |
3348 | #define SDMA1_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x1 |
3349 | #define SDMA1_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x2 |
3350 | #define SDMA1_PHYSICAL_ADDR_LO__ADDR__SHIFT 0xc |
3351 | #define SDMA1_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L |
3352 | #define SDMA1_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L |
3353 | #define SDMA1_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L |
3354 | #define SDMA1_PHYSICAL_ADDR_LO__ADDR_MASK 0xFFFFF000L |
3355 | //SDMA1_PHYSICAL_ADDR_HI |
3356 | #define SDMA1_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x0 |
3357 | #define SDMA1_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000FFFFL |
3358 | //SDMA1_GLOBAL_QUANTUM |
3359 | #define SDMA1_GLOBAL_QUANTUM__GLOBAL_FOCUS_QUANTUM__SHIFT 0x0 |
3360 | #define SDMA1_GLOBAL_QUANTUM__GLOBAL_NORMAL_QUANTUM__SHIFT 0x8 |
3361 | #define SDMA1_GLOBAL_QUANTUM__GLOBAL_FOCUS_QUANTUM_MASK 0x000000FFL |
3362 | #define SDMA1_GLOBAL_QUANTUM__GLOBAL_NORMAL_QUANTUM_MASK 0x0000FF00L |
3363 | //SDMA1_ERROR_LOG |
3364 | #define SDMA1_ERROR_LOG__OVERRIDE__SHIFT 0x0 |
3365 | #define SDMA1_ERROR_LOG__STATUS__SHIFT 0x10 |
3366 | #define SDMA1_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL |
3367 | #define SDMA1_ERROR_LOG__STATUS_MASK 0xFFFF0000L |
3368 | //SDMA1_PUB_DUMMY_REG0 |
3369 | #define SDMA1_PUB_DUMMY_REG0__VALUE__SHIFT 0x0 |
3370 | #define SDMA1_PUB_DUMMY_REG0__VALUE_MASK 0xFFFFFFFFL |
3371 | //SDMA1_PUB_DUMMY_REG1 |
3372 | #define SDMA1_PUB_DUMMY_REG1__VALUE__SHIFT 0x0 |
3373 | #define SDMA1_PUB_DUMMY_REG1__VALUE_MASK 0xFFFFFFFFL |
3374 | //SDMA1_PUB_DUMMY_REG2 |
3375 | #define SDMA1_PUB_DUMMY_REG2__VALUE__SHIFT 0x0 |
3376 | #define SDMA1_PUB_DUMMY_REG2__VALUE_MASK 0xFFFFFFFFL |
3377 | //SDMA1_PUB_DUMMY_REG3 |
3378 | #define SDMA1_PUB_DUMMY_REG3__VALUE__SHIFT 0x0 |
3379 | #define SDMA1_PUB_DUMMY_REG3__VALUE_MASK 0xFFFFFFFFL |
3380 | //SDMA1_F32_COUNTER |
3381 | #define SDMA1_F32_COUNTER__VALUE__SHIFT 0x0 |
3382 | #define SDMA1_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL |
3383 | //SDMA1_CRD_CNTL |
3384 | #define SDMA1_CRD_CNTL__DRM_CREDIT__SHIFT 0x0 |
3385 | #define SDMA1_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7 |
3386 | #define SDMA1_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd |
3387 | #define SDMA1_CRD_CNTL__CH_WRREQ_CREDIT__SHIFT 0x13 |
3388 | #define SDMA1_CRD_CNTL__CH_RDREQ_CREDIT__SHIFT 0x19 |
3389 | #define SDMA1_CRD_CNTL__DRM_CREDIT_MASK 0x0000007FL |
3390 | #define SDMA1_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L |
3391 | #define SDMA1_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L |
3392 | #define SDMA1_CRD_CNTL__CH_WRREQ_CREDIT_MASK 0x01F80000L |
3393 | #define SDMA1_CRD_CNTL__CH_RDREQ_CREDIT_MASK 0x7E000000L |
3394 | //SDMA1_RLC_CGCG_CTRL |
3395 | #define SDMA1_RLC_CGCG_CTRL__CGCG_INT_ENABLE__SHIFT 0x1 |
3396 | #define SDMA1_RLC_CGCG_CTRL__CGCG_IDLE_HYSTERESIS__SHIFT 0x10 |
3397 | #define SDMA1_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK 0x00000002L |
3398 | #define SDMA1_RLC_CGCG_CTRL__CGCG_IDLE_HYSTERESIS_MASK 0xFFFF0000L |
3399 | //SDMA1_GPU_IOV_VIOLATION_LOG |
3400 | #define SDMA1_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0 |
3401 | #define SDMA1_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1 |
3402 | #define SDMA1_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2 |
3403 | #define SDMA1_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION__SHIFT 0x14 |
3404 | #define SDMA1_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x15 |
3405 | #define SDMA1_GPU_IOV_VIOLATION_LOG__VFID__SHIFT 0x16 |
3406 | #define SDMA1_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L |
3407 | #define SDMA1_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L |
3408 | #define SDMA1_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x000FFFFCL |
3409 | #define SDMA1_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION_MASK 0x00100000L |
3410 | #define SDMA1_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00200000L |
3411 | #define SDMA1_GPU_IOV_VIOLATION_LOG__VFID_MASK 0x03C00000L |
3412 | //SDMA1_AQL_STATUS |
3413 | #define SDMA1_AQL_STATUS__COMPLETE_SIGNAL_EMPTY__SHIFT 0x0 |
3414 | #define SDMA1_AQL_STATUS__INVALID_CMD_EMPTY__SHIFT 0x1 |
3415 | #define SDMA1_AQL_STATUS__COMPLETE_SIGNAL_EMPTY_MASK 0x00000001L |
3416 | #define SDMA1_AQL_STATUS__INVALID_CMD_EMPTY_MASK 0x00000002L |
3417 | //SDMA1_EA_DBIT_ADDR_DATA |
3418 | #define SDMA1_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x0 |
3419 | #define SDMA1_EA_DBIT_ADDR_DATA__VALUE_MASK 0xFFFFFFFFL |
3420 | //SDMA1_EA_DBIT_ADDR_INDEX |
3421 | #define SDMA1_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x0 |
3422 | #define SDMA1_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L |
3423 | //SDMA1_TLBI_GCR_CNTL |
3424 | #define SDMA1_TLBI_GCR_CNTL__TLBI_CMD_DW__SHIFT 0x0 |
3425 | #define SDMA1_TLBI_GCR_CNTL__GCR_CMD_DW__SHIFT 0x4 |
3426 | #define SDMA1_TLBI_GCR_CNTL__GCR_CLKEN_CYCLE__SHIFT 0x8 |
3427 | #define SDMA1_TLBI_GCR_CNTL__TLBI_CREDIT__SHIFT 0x10 |
3428 | #define SDMA1_TLBI_GCR_CNTL__GCR_CREDIT__SHIFT 0x18 |
3429 | #define SDMA1_TLBI_GCR_CNTL__TLBI_CMD_DW_MASK 0x0000000FL |
3430 | #define SDMA1_TLBI_GCR_CNTL__GCR_CMD_DW_MASK 0x000000F0L |
3431 | #define SDMA1_TLBI_GCR_CNTL__GCR_CLKEN_CYCLE_MASK 0x00000F00L |
3432 | #define SDMA1_TLBI_GCR_CNTL__TLBI_CREDIT_MASK 0x00FF0000L |
3433 | #define SDMA1_TLBI_GCR_CNTL__GCR_CREDIT_MASK 0xFF000000L |
3434 | //SDMA1_TILING_CONFIG |
3435 | #define SDMA1_TILING_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 |
3436 | #define SDMA1_TILING_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000070L |
3437 | //SDMA1_HASH |
3438 | #define SDMA1_HASH__CHANNEL_BITS__SHIFT 0x0 |
3439 | #define SDMA1_HASH__BANK_BITS__SHIFT 0x4 |
3440 | #define SDMA1_HASH__CHANNEL_XOR_COUNT__SHIFT 0x8 |
3441 | #define SDMA1_HASH__BANK_XOR_COUNT__SHIFT 0xc |
3442 | #define SDMA1_HASH__CHANNEL_BITS_MASK 0x00000007L |
3443 | #define SDMA1_HASH__BANK_BITS_MASK 0x00000070L |
3444 | #define SDMA1_HASH__CHANNEL_XOR_COUNT_MASK 0x00000700L |
3445 | #define SDMA1_HASH__BANK_XOR_COUNT_MASK 0x00007000L |
3446 | //SDMA1_INT_STATUS |
3447 | #define SDMA1_INT_STATUS__DATA__SHIFT 0x0 |
3448 | #define SDMA1_INT_STATUS__DATA_MASK 0xFFFFFFFFL |
3449 | //SDMA1_GPU_IOV_VIOLATION_LOG2 |
3450 | #define SDMA1_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID__SHIFT 0x0 |
3451 | #define SDMA1_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID_MASK 0x000003FFL |
3452 | //SDMA1_HOLE_ADDR_LO |
3453 | #define SDMA1_HOLE_ADDR_LO__VALUE__SHIFT 0x0 |
3454 | #define SDMA1_HOLE_ADDR_LO__VALUE_MASK 0xFFFFFFFFL |
3455 | //SDMA1_HOLE_ADDR_HI |
3456 | #define SDMA1_HOLE_ADDR_HI__VALUE__SHIFT 0x0 |
3457 | #define SDMA1_HOLE_ADDR_HI__VALUE_MASK 0xFFFFFFFFL |
3458 | //SDMA1_CLOCK_GATING_STATUS |
3459 | #define SDMA1_CLOCK_GATING_STATUS__DYN_CLK_GATE_STATUS__SHIFT 0x0 |
3460 | #define SDMA1_CLOCK_GATING_STATUS__CE_CLK_GATE_STATUS__SHIFT 0x2 |
3461 | #define SDMA1_CLOCK_GATING_STATUS__CE_BC_CLK_GATE_STATUS__SHIFT 0x3 |
3462 | #define SDMA1_CLOCK_GATING_STATUS__CE_NBC_CLK_GATE_STATUS__SHIFT 0x4 |
3463 | #define SDMA1_CLOCK_GATING_STATUS__REG_CLK_GATE_STATUS__SHIFT 0x5 |
3464 | #define SDMA1_CLOCK_GATING_STATUS__F32_CLK_GATE_STATUS__SHIFT 0x6 |
3465 | #define SDMA1_CLOCK_GATING_STATUS__DYN_CLK_GATE_STATUS_MASK 0x00000001L |
3466 | #define SDMA1_CLOCK_GATING_STATUS__CE_CLK_GATE_STATUS_MASK 0x00000004L |
3467 | #define SDMA1_CLOCK_GATING_STATUS__CE_BC_CLK_GATE_STATUS_MASK 0x00000008L |
3468 | #define SDMA1_CLOCK_GATING_STATUS__CE_NBC_CLK_GATE_STATUS_MASK 0x00000010L |
3469 | #define SDMA1_CLOCK_GATING_STATUS__REG_CLK_GATE_STATUS_MASK 0x00000020L |
3470 | #define SDMA1_CLOCK_GATING_STATUS__F32_CLK_GATE_STATUS_MASK 0x00000040L |
3471 | //SDMA1_STATUS4_REG |
3472 | #define SDMA1_STATUS4_REG__IDLE__SHIFT 0x0 |
3473 | #define SDMA1_STATUS4_REG__IH_OUTSTANDING__SHIFT 0x2 |
3474 | #define SDMA1_STATUS4_REG__SEM_OUTSTANDING__SHIFT 0x3 |
3475 | #define SDMA1_STATUS4_REG__CH_RD_OUTSTANDING__SHIFT 0x4 |
3476 | #define SDMA1_STATUS4_REG__CH_WR_OUTSTANDING__SHIFT 0x5 |
3477 | #define SDMA1_STATUS4_REG__GCR_OUTSTANDING__SHIFT 0x6 |
3478 | #define SDMA1_STATUS4_REG__TLBI_OUTSTANDING__SHIFT 0x7 |
3479 | #define SDMA1_STATUS4_REG__UTCL2_RD_OUTSTANDING__SHIFT 0x8 |
3480 | #define SDMA1_STATUS4_REG__UTCL2_WR_OUTSTANDING__SHIFT 0x9 |
3481 | #define SDMA1_STATUS4_REG__REG_POLLING__SHIFT 0xa |
3482 | #define SDMA1_STATUS4_REG__MEM_POLLING__SHIFT 0xb |
3483 | #define SDMA1_STATUS4_REG__RESERVED_13_12__SHIFT 0xc |
3484 | #define SDMA1_STATUS4_REG__RESERVED_15_14__SHIFT 0xe |
3485 | #define SDMA1_STATUS4_REG__ACTIVE_QUEUE_ID__SHIFT 0x10 |
3486 | #define SDMA1_STATUS4_REG__SRIOV_WATING_RLCV_CMD__SHIFT 0x14 |
3487 | #define SDMA1_STATUS4_REG__SRIOV_SDMA_EXECUTING_CMD__SHIFT 0x15 |
3488 | #define SDMA1_STATUS4_REG__UTCL2_RD_XNACK_FAULT__SHIFT 0x16 |
3489 | #define SDMA1_STATUS4_REG__UTCL2_RD_XNACK_NULL__SHIFT 0x17 |
3490 | #define SDMA1_STATUS4_REG__UTCL2_RD_XNACK_TIMEOUT__SHIFT 0x18 |
3491 | #define SDMA1_STATUS4_REG__UTCL2_WR_XNACK_FAULT__SHIFT 0x19 |
3492 | #define SDMA1_STATUS4_REG__UTCL2_WR_XNACK_NULL__SHIFT 0x1a |
3493 | #define SDMA1_STATUS4_REG__UTCL2_WR_XNACK_TIMEOUT__SHIFT 0x1b |
3494 | #define SDMA1_STATUS4_REG__IDLE_MASK 0x00000001L |
3495 | #define SDMA1_STATUS4_REG__IH_OUTSTANDING_MASK 0x00000004L |
3496 | #define SDMA1_STATUS4_REG__SEM_OUTSTANDING_MASK 0x00000008L |
3497 | #define SDMA1_STATUS4_REG__CH_RD_OUTSTANDING_MASK 0x00000010L |
3498 | #define SDMA1_STATUS4_REG__CH_WR_OUTSTANDING_MASK 0x00000020L |
3499 | #define SDMA1_STATUS4_REG__GCR_OUTSTANDING_MASK 0x00000040L |
3500 | #define SDMA1_STATUS4_REG__TLBI_OUTSTANDING_MASK 0x00000080L |
3501 | #define SDMA1_STATUS4_REG__UTCL2_RD_OUTSTANDING_MASK 0x00000100L |
3502 | #define SDMA1_STATUS4_REG__UTCL2_WR_OUTSTANDING_MASK 0x00000200L |
3503 | #define SDMA1_STATUS4_REG__REG_POLLING_MASK 0x00000400L |
3504 | #define SDMA1_STATUS4_REG__MEM_POLLING_MASK 0x00000800L |
3505 | #define SDMA1_STATUS4_REG__RESERVED_13_12_MASK 0x00003000L |
3506 | #define SDMA1_STATUS4_REG__RESERVED_15_14_MASK 0x0000C000L |
3507 | #define SDMA1_STATUS4_REG__ACTIVE_QUEUE_ID_MASK 0x000F0000L |
3508 | #define SDMA1_STATUS4_REG__SRIOV_WATING_RLCV_CMD_MASK 0x00100000L |
3509 | #define SDMA1_STATUS4_REG__SRIOV_SDMA_EXECUTING_CMD_MASK 0x00200000L |
3510 | #define SDMA1_STATUS4_REG__UTCL2_RD_XNACK_FAULT_MASK 0x00400000L |
3511 | #define SDMA1_STATUS4_REG__UTCL2_RD_XNACK_NULL_MASK 0x00800000L |
3512 | #define SDMA1_STATUS4_REG__UTCL2_RD_XNACK_TIMEOUT_MASK 0x01000000L |
3513 | #define SDMA1_STATUS4_REG__UTCL2_WR_XNACK_FAULT_MASK 0x02000000L |
3514 | #define SDMA1_STATUS4_REG__UTCL2_WR_XNACK_NULL_MASK 0x04000000L |
3515 | #define SDMA1_STATUS4_REG__UTCL2_WR_XNACK_TIMEOUT_MASK 0x08000000L |
3516 | //SDMA1_SCRATCH_RAM_DATA |
3517 | #define SDMA1_SCRATCH_RAM_DATA__DATA__SHIFT 0x0 |
3518 | #define SDMA1_SCRATCH_RAM_DATA__DATA_MASK 0xFFFFFFFFL |
3519 | //SDMA1_SCRATCH_RAM_ADDR |
3520 | #define SDMA1_SCRATCH_RAM_ADDR__ADDR__SHIFT 0x0 |
3521 | #define SDMA1_SCRATCH_RAM_ADDR__ADDR_MASK 0x0000007FL |
3522 | //SDMA1_TIMESTAMP_CNTL |
3523 | #define SDMA1_TIMESTAMP_CNTL__CAPTURE__SHIFT 0x0 |
3524 | #define SDMA1_TIMESTAMP_CNTL__CAPTURE_MASK 0x00000001L |
3525 | //SDMA1_STATUS5_REG |
3526 | #define SDMA1_STATUS5_REG__QUEUE0_RB_ENABLE_STATUS__SHIFT 0x0 |
3527 | #define SDMA1_STATUS5_REG__QUEUE1_RB_ENABLE_STATUS__SHIFT 0x1 |
3528 | #define SDMA1_STATUS5_REG__QUEUE2_RB_ENABLE_STATUS__SHIFT 0x2 |
3529 | #define SDMA1_STATUS5_REG__QUEUE3_RB_ENABLE_STATUS__SHIFT 0x3 |
3530 | #define SDMA1_STATUS5_REG__QUEUE4_RB_ENABLE_STATUS__SHIFT 0x4 |
3531 | #define SDMA1_STATUS5_REG__QUEUE5_RB_ENABLE_STATUS__SHIFT 0x5 |
3532 | #define SDMA1_STATUS5_REG__QUEUE6_RB_ENABLE_STATUS__SHIFT 0x6 |
3533 | #define SDMA1_STATUS5_REG__QUEUE7_RB_ENABLE_STATUS__SHIFT 0x7 |
3534 | #define SDMA1_STATUS5_REG__ACTIVE_QUEUE_ID__SHIFT 0x10 |
3535 | #define SDMA1_STATUS5_REG__QUEUE0_WPTR_POLL_PAGE_EXCEPTION__SHIFT 0x14 |
3536 | #define SDMA1_STATUS5_REG__QUEUE1_WPTR_POLL_PAGE_EXCEPTION__SHIFT 0x15 |
3537 | #define SDMA1_STATUS5_REG__QUEUE2_WPTR_POLL_PAGE_EXCEPTION__SHIFT 0x16 |
3538 | #define SDMA1_STATUS5_REG__QUEUE3_WPTR_POLL_PAGE_EXCEPTION__SHIFT 0x17 |
3539 | #define SDMA1_STATUS5_REG__QUEUE4_WPTR_POLL_PAGE_EXCEPTION__SHIFT 0x18 |
3540 | #define SDMA1_STATUS5_REG__QUEUE5_WPTR_POLL_PAGE_EXCEPTION__SHIFT 0x19 |
3541 | #define SDMA1_STATUS5_REG__QUEUE6_WPTR_POLL_PAGE_EXCEPTION__SHIFT 0x1a |
3542 | #define SDMA1_STATUS5_REG__QUEUE7_WPTR_POLL_PAGE_EXCEPTION__SHIFT 0x1b |
3543 | #define SDMA1_STATUS5_REG__QUEUE0_RB_ENABLE_STATUS_MASK 0x00000001L |
3544 | #define SDMA1_STATUS5_REG__QUEUE1_RB_ENABLE_STATUS_MASK 0x00000002L |
3545 | #define SDMA1_STATUS5_REG__QUEUE2_RB_ENABLE_STATUS_MASK 0x00000004L |
3546 | #define SDMA1_STATUS5_REG__QUEUE3_RB_ENABLE_STATUS_MASK 0x00000008L |
3547 | #define SDMA1_STATUS5_REG__QUEUE4_RB_ENABLE_STATUS_MASK 0x00000010L |
3548 | #define SDMA1_STATUS5_REG__QUEUE5_RB_ENABLE_STATUS_MASK 0x00000020L |
3549 | #define SDMA1_STATUS5_REG__QUEUE6_RB_ENABLE_STATUS_MASK 0x00000040L |
3550 | #define SDMA1_STATUS5_REG__QUEUE7_RB_ENABLE_STATUS_MASK 0x00000080L |
3551 | #define SDMA1_STATUS5_REG__ACTIVE_QUEUE_ID_MASK 0x000F0000L |
3552 | #define SDMA1_STATUS5_REG__QUEUE0_WPTR_POLL_PAGE_EXCEPTION_MASK 0x00100000L |
3553 | #define SDMA1_STATUS5_REG__QUEUE1_WPTR_POLL_PAGE_EXCEPTION_MASK 0x00200000L |
3554 | #define SDMA1_STATUS5_REG__QUEUE2_WPTR_POLL_PAGE_EXCEPTION_MASK 0x00400000L |
3555 | #define SDMA1_STATUS5_REG__QUEUE3_WPTR_POLL_PAGE_EXCEPTION_MASK 0x00800000L |
3556 | #define SDMA1_STATUS5_REG__QUEUE4_WPTR_POLL_PAGE_EXCEPTION_MASK 0x01000000L |
3557 | #define SDMA1_STATUS5_REG__QUEUE5_WPTR_POLL_PAGE_EXCEPTION_MASK 0x02000000L |
3558 | #define SDMA1_STATUS5_REG__QUEUE6_WPTR_POLL_PAGE_EXCEPTION_MASK 0x04000000L |
3559 | #define SDMA1_STATUS5_REG__QUEUE7_WPTR_POLL_PAGE_EXCEPTION_MASK 0x08000000L |
3560 | //SDMA1_QUEUE_RESET_REQ |
3561 | #define SDMA1_QUEUE_RESET_REQ__QUEUE0_RESET__SHIFT 0x0 |
3562 | #define SDMA1_QUEUE_RESET_REQ__QUEUE1_RESET__SHIFT 0x1 |
3563 | #define SDMA1_QUEUE_RESET_REQ__QUEUE2_RESET__SHIFT 0x2 |
3564 | #define SDMA1_QUEUE_RESET_REQ__QUEUE3_RESET__SHIFT 0x3 |
3565 | #define SDMA1_QUEUE_RESET_REQ__QUEUE4_RESET__SHIFT 0x4 |
3566 | #define SDMA1_QUEUE_RESET_REQ__QUEUE5_RESET__SHIFT 0x5 |
3567 | #define SDMA1_QUEUE_RESET_REQ__QUEUE6_RESET__SHIFT 0x6 |
3568 | #define SDMA1_QUEUE_RESET_REQ__QUEUE7_RESET__SHIFT 0x7 |
3569 | #define SDMA1_QUEUE_RESET_REQ__RESERVED__SHIFT 0x8 |
3570 | #define SDMA1_QUEUE_RESET_REQ__QUEUE0_RESET_MASK 0x00000001L |
3571 | #define SDMA1_QUEUE_RESET_REQ__QUEUE1_RESET_MASK 0x00000002L |
3572 | #define SDMA1_QUEUE_RESET_REQ__QUEUE2_RESET_MASK 0x00000004L |
3573 | #define SDMA1_QUEUE_RESET_REQ__QUEUE3_RESET_MASK 0x00000008L |
3574 | #define SDMA1_QUEUE_RESET_REQ__QUEUE4_RESET_MASK 0x00000010L |
3575 | #define SDMA1_QUEUE_RESET_REQ__QUEUE5_RESET_MASK 0x00000020L |
3576 | #define SDMA1_QUEUE_RESET_REQ__QUEUE6_RESET_MASK 0x00000040L |
3577 | #define SDMA1_QUEUE_RESET_REQ__QUEUE7_RESET_MASK 0x00000080L |
3578 | #define SDMA1_QUEUE_RESET_REQ__RESERVED_MASK 0xFFFFFF00L |
3579 | //SDMA1_STATUS6_REG |
3580 | #define SDMA1_STATUS6_REG__ID__SHIFT 0x0 |
3581 | #define SDMA1_STATUS6_REG__TH1F32_INSTR_PTR__SHIFT 0x2 |
3582 | #define SDMA1_STATUS6_REG__TH1_EXCEPTION__SHIFT 0x10 |
3583 | #define SDMA1_STATUS6_REG__ID_MASK 0x00000003L |
3584 | #define SDMA1_STATUS6_REG__TH1F32_INSTR_PTR_MASK 0x0000FFFCL |
3585 | #define SDMA1_STATUS6_REG__TH1_EXCEPTION_MASK 0xFFFF0000L |
3586 | //SDMA1_UCODE1_CHECKSUM |
3587 | #define SDMA1_UCODE1_CHECKSUM__DATA__SHIFT 0x0 |
3588 | #define SDMA1_UCODE1_CHECKSUM__DATA_MASK 0xFFFFFFFFL |
3589 | //SDMA1_CE_CTRL |
3590 | #define SDMA1_CE_CTRL__RD_LUT_WATERMARK__SHIFT 0x0 |
3591 | #define SDMA1_CE_CTRL__RD_LUT_DEPTH__SHIFT 0x3 |
3592 | #define SDMA1_CE_CTRL__WR_AFIFO_WATERMARK__SHIFT 0x5 |
3593 | #define SDMA1_CE_CTRL__CE_DCC_READ_128B_ENABLE__SHIFT 0x8 |
3594 | #define SDMA1_CE_CTRL__RESERVED__SHIFT 0x9 |
3595 | #define SDMA1_CE_CTRL__RD_LUT_WATERMARK_MASK 0x00000007L |
3596 | #define SDMA1_CE_CTRL__RD_LUT_DEPTH_MASK 0x00000018L |
3597 | #define SDMA1_CE_CTRL__WR_AFIFO_WATERMARK_MASK 0x000000E0L |
3598 | #define SDMA1_CE_CTRL__CE_DCC_READ_128B_ENABLE_MASK 0x00000100L |
3599 | #define SDMA1_CE_CTRL__RESERVED_MASK 0xFFFFFE00L |
3600 | //SDMA1_FED_STATUS |
3601 | #define SDMA1_FED_STATUS__RB_FETCH_ECC__SHIFT 0x0 |
3602 | #define SDMA1_FED_STATUS__IB_FETCH_ECC__SHIFT 0x1 |
3603 | #define SDMA1_FED_STATUS__F32_DATA_ECC__SHIFT 0x2 |
3604 | #define SDMA1_FED_STATUS__WPTR_ATOMIC_ECC__SHIFT 0x3 |
3605 | #define SDMA1_FED_STATUS__COPY_DATA_ECC__SHIFT 0x4 |
3606 | #define SDMA1_FED_STATUS__COPY_METADATA_ECC__SHIFT 0x5 |
3607 | #define SDMA1_FED_STATUS__SELFLOAD_UCODE_ECC__SHIFT 0x6 |
3608 | #define SDMA1_FED_STATUS__RB_FETCH_ECC_MASK 0x00000001L |
3609 | #define SDMA1_FED_STATUS__IB_FETCH_ECC_MASK 0x00000002L |
3610 | #define SDMA1_FED_STATUS__F32_DATA_ECC_MASK 0x00000004L |
3611 | #define SDMA1_FED_STATUS__WPTR_ATOMIC_ECC_MASK 0x00000008L |
3612 | #define SDMA1_FED_STATUS__COPY_DATA_ECC_MASK 0x00000010L |
3613 | #define SDMA1_FED_STATUS__COPY_METADATA_ECC_MASK 0x00000020L |
3614 | #define SDMA1_FED_STATUS__SELFLOAD_UCODE_ECC_MASK 0x00000040L |
3615 | //SDMA1_QUEUE0_RB_CNTL |
3616 | #define SDMA1_QUEUE0_RB_CNTL__RB_ENABLE__SHIFT 0x0 |
3617 | #define SDMA1_QUEUE0_RB_CNTL__RB_SIZE__SHIFT 0x1 |
3618 | #define SDMA1_QUEUE0_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 |
3619 | #define SDMA1_QUEUE0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 |
3620 | #define SDMA1_QUEUE0_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa |
3621 | #define SDMA1_QUEUE0_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT 0xb |
3622 | #define SDMA1_QUEUE0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc |
3623 | #define SDMA1_QUEUE0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd |
3624 | #define SDMA1_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 |
3625 | #define SDMA1_QUEUE0_RB_CNTL__RB_PRIV__SHIFT 0x17 |
3626 | #define SDMA1_QUEUE0_RB_CNTL__RB_VMID__SHIFT 0x18 |
3627 | #define SDMA1_QUEUE0_RB_CNTL__RB_ENABLE_MASK 0x00000001L |
3628 | #define SDMA1_QUEUE0_RB_CNTL__RB_SIZE_MASK 0x0000003EL |
3629 | #define SDMA1_QUEUE0_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L |
3630 | #define SDMA1_QUEUE0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L |
3631 | #define SDMA1_QUEUE0_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L |
3632 | #define SDMA1_QUEUE0_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK 0x00000800L |
3633 | #define SDMA1_QUEUE0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L |
3634 | #define SDMA1_QUEUE0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L |
3635 | #define SDMA1_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L |
3636 | #define SDMA1_QUEUE0_RB_CNTL__RB_PRIV_MASK 0x00800000L |
3637 | #define SDMA1_QUEUE0_RB_CNTL__RB_VMID_MASK 0x0F000000L |
3638 | //SDMA1_QUEUE0_RB_BASE |
3639 | #define SDMA1_QUEUE0_RB_BASE__ADDR__SHIFT 0x0 |
3640 | #define SDMA1_QUEUE0_RB_BASE__ADDR_MASK 0xFFFFFFFFL |
3641 | //SDMA1_QUEUE0_RB_BASE_HI |
3642 | #define SDMA1_QUEUE0_RB_BASE_HI__ADDR__SHIFT 0x0 |
3643 | #define SDMA1_QUEUE0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL |
3644 | //SDMA1_QUEUE0_RB_RPTR |
3645 | #define SDMA1_QUEUE0_RB_RPTR__OFFSET__SHIFT 0x0 |
3646 | #define SDMA1_QUEUE0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL |
3647 | //SDMA1_QUEUE0_RB_RPTR_HI |
3648 | #define SDMA1_QUEUE0_RB_RPTR_HI__OFFSET__SHIFT 0x0 |
3649 | #define SDMA1_QUEUE0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
3650 | //SDMA1_QUEUE0_RB_WPTR |
3651 | #define SDMA1_QUEUE0_RB_WPTR__OFFSET__SHIFT 0x0 |
3652 | #define SDMA1_QUEUE0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL |
3653 | //SDMA1_QUEUE0_RB_WPTR_HI |
3654 | #define SDMA1_QUEUE0_RB_WPTR_HI__OFFSET__SHIFT 0x0 |
3655 | #define SDMA1_QUEUE0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
3656 | //SDMA1_QUEUE0_RB_RPTR_ADDR_HI |
3657 | #define SDMA1_QUEUE0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 |
3658 | #define SDMA1_QUEUE0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
3659 | //SDMA1_QUEUE0_RB_RPTR_ADDR_LO |
3660 | #define SDMA1_QUEUE0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 |
3661 | #define SDMA1_QUEUE0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
3662 | //SDMA1_QUEUE0_IB_CNTL |
3663 | #define SDMA1_QUEUE0_IB_CNTL__IB_ENABLE__SHIFT 0x0 |
3664 | #define SDMA1_QUEUE0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 |
3665 | #define SDMA1_QUEUE0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 |
3666 | #define SDMA1_QUEUE0_IB_CNTL__CMD_VMID__SHIFT 0x10 |
3667 | #define SDMA1_QUEUE0_IB_CNTL__IB_PRIV__SHIFT 0x1f |
3668 | #define SDMA1_QUEUE0_IB_CNTL__IB_ENABLE_MASK 0x00000001L |
3669 | #define SDMA1_QUEUE0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L |
3670 | #define SDMA1_QUEUE0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L |
3671 | #define SDMA1_QUEUE0_IB_CNTL__CMD_VMID_MASK 0x000F0000L |
3672 | #define SDMA1_QUEUE0_IB_CNTL__IB_PRIV_MASK 0x80000000L |
3673 | //SDMA1_QUEUE0_IB_RPTR |
3674 | #define SDMA1_QUEUE0_IB_RPTR__OFFSET__SHIFT 0x2 |
3675 | #define SDMA1_QUEUE0_IB_RPTR__OFFSET_MASK 0x003FFFFCL |
3676 | //SDMA1_QUEUE0_IB_OFFSET |
3677 | #define SDMA1_QUEUE0_IB_OFFSET__OFFSET__SHIFT 0x2 |
3678 | #define SDMA1_QUEUE0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL |
3679 | //SDMA1_QUEUE0_IB_BASE_LO |
3680 | #define SDMA1_QUEUE0_IB_BASE_LO__ADDR__SHIFT 0x5 |
3681 | #define SDMA1_QUEUE0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L |
3682 | //SDMA1_QUEUE0_IB_BASE_HI |
3683 | #define SDMA1_QUEUE0_IB_BASE_HI__ADDR__SHIFT 0x0 |
3684 | #define SDMA1_QUEUE0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL |
3685 | //SDMA1_QUEUE0_IB_SIZE |
3686 | #define SDMA1_QUEUE0_IB_SIZE__SIZE__SHIFT 0x0 |
3687 | #define SDMA1_QUEUE0_IB_SIZE__SIZE_MASK 0x000FFFFFL |
3688 | //SDMA1_QUEUE0_SKIP_CNTL |
3689 | #define SDMA1_QUEUE0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 |
3690 | #define SDMA1_QUEUE0_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL |
3691 | //SDMA1_QUEUE0_CONTEXT_STATUS |
3692 | #define SDMA1_QUEUE0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 |
3693 | #define SDMA1_QUEUE0_CONTEXT_STATUS__USE_IB__SHIFT 0x1 |
3694 | #define SDMA1_QUEUE0_CONTEXT_STATUS__IDLE__SHIFT 0x2 |
3695 | #define SDMA1_QUEUE0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 |
3696 | #define SDMA1_QUEUE0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 |
3697 | #define SDMA1_QUEUE0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 |
3698 | #define SDMA1_QUEUE0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa |
3699 | #define SDMA1_QUEUE0_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb |
3700 | #define SDMA1_QUEUE0_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc |
3701 | #define SDMA1_QUEUE0_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 |
3702 | #define SDMA1_QUEUE0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L |
3703 | #define SDMA1_QUEUE0_CONTEXT_STATUS__USE_IB_MASK 0x00000002L |
3704 | #define SDMA1_QUEUE0_CONTEXT_STATUS__IDLE_MASK 0x00000004L |
3705 | #define SDMA1_QUEUE0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L |
3706 | #define SDMA1_QUEUE0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L |
3707 | #define SDMA1_QUEUE0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L |
3708 | #define SDMA1_QUEUE0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L |
3709 | #define SDMA1_QUEUE0_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L |
3710 | #define SDMA1_QUEUE0_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L |
3711 | #define SDMA1_QUEUE0_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L |
3712 | //SDMA1_QUEUE0_DOORBELL |
3713 | #define SDMA1_QUEUE0_DOORBELL__ENABLE__SHIFT 0x1c |
3714 | #define SDMA1_QUEUE0_DOORBELL__CAPTURED__SHIFT 0x1e |
3715 | #define SDMA1_QUEUE0_DOORBELL__ENABLE_MASK 0x10000000L |
3716 | #define SDMA1_QUEUE0_DOORBELL__CAPTURED_MASK 0x40000000L |
3717 | //SDMA1_QUEUE0_DOORBELL_LOG |
3718 | #define SDMA1_QUEUE0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 |
3719 | #define SDMA1_QUEUE0_DOORBELL_LOG__DATA__SHIFT 0x2 |
3720 | #define SDMA1_QUEUE0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L |
3721 | #define SDMA1_QUEUE0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL |
3722 | //SDMA1_QUEUE0_DOORBELL_OFFSET |
3723 | #define SDMA1_QUEUE0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 |
3724 | #define SDMA1_QUEUE0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL |
3725 | //SDMA1_QUEUE0_CSA_ADDR_LO |
3726 | #define SDMA1_QUEUE0_CSA_ADDR_LO__ADDR__SHIFT 0x2 |
3727 | #define SDMA1_QUEUE0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
3728 | //SDMA1_QUEUE0_CSA_ADDR_HI |
3729 | #define SDMA1_QUEUE0_CSA_ADDR_HI__ADDR__SHIFT 0x0 |
3730 | #define SDMA1_QUEUE0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
3731 | //SDMA1_QUEUE0_SCHEDULE_CNTL |
3732 | #define SDMA1_QUEUE0_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 |
3733 | #define SDMA1_QUEUE0_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 |
3734 | #define SDMA1_QUEUE0_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 |
3735 | #define SDMA1_QUEUE0_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 |
3736 | #define SDMA1_QUEUE0_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L |
3737 | #define SDMA1_QUEUE0_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL |
3738 | #define SDMA1_QUEUE0_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L |
3739 | #define SDMA1_QUEUE0_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L |
3740 | //SDMA1_QUEUE0_IB_SUB_REMAIN |
3741 | #define SDMA1_QUEUE0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 |
3742 | #define SDMA1_QUEUE0_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL |
3743 | //SDMA1_QUEUE0_PREEMPT |
3744 | #define SDMA1_QUEUE0_PREEMPT__IB_PREEMPT__SHIFT 0x0 |
3745 | #define SDMA1_QUEUE0_PREEMPT__IB_PREEMPT_MASK 0x00000001L |
3746 | //SDMA1_QUEUE0_DUMMY_REG |
3747 | #define SDMA1_QUEUE0_DUMMY_REG__DUMMY__SHIFT 0x0 |
3748 | #define SDMA1_QUEUE0_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL |
3749 | //SDMA1_QUEUE0_RB_WPTR_POLL_ADDR_HI |
3750 | #define SDMA1_QUEUE0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 |
3751 | #define SDMA1_QUEUE0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
3752 | //SDMA1_QUEUE0_RB_WPTR_POLL_ADDR_LO |
3753 | #define SDMA1_QUEUE0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 |
3754 | #define SDMA1_QUEUE0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
3755 | //SDMA1_QUEUE0_RB_AQL_CNTL |
3756 | #define SDMA1_QUEUE0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 |
3757 | #define SDMA1_QUEUE0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 |
3758 | #define SDMA1_QUEUE0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 |
3759 | #define SDMA1_QUEUE0_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 |
3760 | #define SDMA1_QUEUE0_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 |
3761 | #define SDMA1_QUEUE0_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 |
3762 | #define SDMA1_QUEUE0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L |
3763 | #define SDMA1_QUEUE0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL |
3764 | #define SDMA1_QUEUE0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L |
3765 | #define SDMA1_QUEUE0_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L |
3766 | #define SDMA1_QUEUE0_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L |
3767 | #define SDMA1_QUEUE0_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L |
3768 | //SDMA1_QUEUE0_MINOR_PTR_UPDATE |
3769 | #define SDMA1_QUEUE0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 |
3770 | #define SDMA1_QUEUE0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L |
3771 | //SDMA1_QUEUE0_RB_PREEMPT |
3772 | #define SDMA1_QUEUE0_RB_PREEMPT__PREEMPT_REQ__SHIFT 0x0 |
3773 | #define SDMA1_QUEUE0_RB_PREEMPT__PREEMPT_REQ_MASK 0x00000001L |
3774 | //SDMA1_QUEUE0_MIDCMD_DATA0 |
3775 | #define SDMA1_QUEUE0_MIDCMD_DATA0__DATA0__SHIFT 0x0 |
3776 | #define SDMA1_QUEUE0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL |
3777 | //SDMA1_QUEUE0_MIDCMD_DATA1 |
3778 | #define SDMA1_QUEUE0_MIDCMD_DATA1__DATA1__SHIFT 0x0 |
3779 | #define SDMA1_QUEUE0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL |
3780 | //SDMA1_QUEUE0_MIDCMD_DATA2 |
3781 | #define SDMA1_QUEUE0_MIDCMD_DATA2__DATA2__SHIFT 0x0 |
3782 | #define SDMA1_QUEUE0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL |
3783 | //SDMA1_QUEUE0_MIDCMD_DATA3 |
3784 | #define SDMA1_QUEUE0_MIDCMD_DATA3__DATA3__SHIFT 0x0 |
3785 | #define SDMA1_QUEUE0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL |
3786 | //SDMA1_QUEUE0_MIDCMD_DATA4 |
3787 | #define SDMA1_QUEUE0_MIDCMD_DATA4__DATA4__SHIFT 0x0 |
3788 | #define SDMA1_QUEUE0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL |
3789 | //SDMA1_QUEUE0_MIDCMD_DATA5 |
3790 | #define SDMA1_QUEUE0_MIDCMD_DATA5__DATA5__SHIFT 0x0 |
3791 | #define SDMA1_QUEUE0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL |
3792 | //SDMA1_QUEUE0_MIDCMD_DATA6 |
3793 | #define SDMA1_QUEUE0_MIDCMD_DATA6__DATA6__SHIFT 0x0 |
3794 | #define SDMA1_QUEUE0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL |
3795 | //SDMA1_QUEUE0_MIDCMD_DATA7 |
3796 | #define SDMA1_QUEUE0_MIDCMD_DATA7__DATA7__SHIFT 0x0 |
3797 | #define SDMA1_QUEUE0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL |
3798 | //SDMA1_QUEUE0_MIDCMD_DATA8 |
3799 | #define SDMA1_QUEUE0_MIDCMD_DATA8__DATA8__SHIFT 0x0 |
3800 | #define SDMA1_QUEUE0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL |
3801 | //SDMA1_QUEUE0_MIDCMD_DATA9 |
3802 | #define SDMA1_QUEUE0_MIDCMD_DATA9__DATA9__SHIFT 0x0 |
3803 | #define SDMA1_QUEUE0_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL |
3804 | //SDMA1_QUEUE0_MIDCMD_DATA10 |
3805 | #define SDMA1_QUEUE0_MIDCMD_DATA10__DATA10__SHIFT 0x0 |
3806 | #define SDMA1_QUEUE0_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL |
3807 | //SDMA1_QUEUE0_MIDCMD_CNTL |
3808 | #define SDMA1_QUEUE0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 |
3809 | #define SDMA1_QUEUE0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 |
3810 | #define SDMA1_QUEUE0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 |
3811 | #define SDMA1_QUEUE0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 |
3812 | #define SDMA1_QUEUE0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L |
3813 | #define SDMA1_QUEUE0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L |
3814 | #define SDMA1_QUEUE0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L |
3815 | #define SDMA1_QUEUE0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L |
3816 | //SDMA1_QUEUE1_RB_CNTL |
3817 | #define SDMA1_QUEUE1_RB_CNTL__RB_ENABLE__SHIFT 0x0 |
3818 | #define SDMA1_QUEUE1_RB_CNTL__RB_SIZE__SHIFT 0x1 |
3819 | #define SDMA1_QUEUE1_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 |
3820 | #define SDMA1_QUEUE1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 |
3821 | #define SDMA1_QUEUE1_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa |
3822 | #define SDMA1_QUEUE1_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT 0xb |
3823 | #define SDMA1_QUEUE1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc |
3824 | #define SDMA1_QUEUE1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd |
3825 | #define SDMA1_QUEUE1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 |
3826 | #define SDMA1_QUEUE1_RB_CNTL__RB_PRIV__SHIFT 0x17 |
3827 | #define SDMA1_QUEUE1_RB_CNTL__RB_VMID__SHIFT 0x18 |
3828 | #define SDMA1_QUEUE1_RB_CNTL__RB_ENABLE_MASK 0x00000001L |
3829 | #define SDMA1_QUEUE1_RB_CNTL__RB_SIZE_MASK 0x0000003EL |
3830 | #define SDMA1_QUEUE1_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L |
3831 | #define SDMA1_QUEUE1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L |
3832 | #define SDMA1_QUEUE1_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L |
3833 | #define SDMA1_QUEUE1_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK 0x00000800L |
3834 | #define SDMA1_QUEUE1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L |
3835 | #define SDMA1_QUEUE1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L |
3836 | #define SDMA1_QUEUE1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L |
3837 | #define SDMA1_QUEUE1_RB_CNTL__RB_PRIV_MASK 0x00800000L |
3838 | #define SDMA1_QUEUE1_RB_CNTL__RB_VMID_MASK 0x0F000000L |
3839 | //SDMA1_QUEUE1_RB_BASE |
3840 | #define SDMA1_QUEUE1_RB_BASE__ADDR__SHIFT 0x0 |
3841 | #define SDMA1_QUEUE1_RB_BASE__ADDR_MASK 0xFFFFFFFFL |
3842 | //SDMA1_QUEUE1_RB_BASE_HI |
3843 | #define SDMA1_QUEUE1_RB_BASE_HI__ADDR__SHIFT 0x0 |
3844 | #define SDMA1_QUEUE1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL |
3845 | //SDMA1_QUEUE1_RB_RPTR |
3846 | #define SDMA1_QUEUE1_RB_RPTR__OFFSET__SHIFT 0x0 |
3847 | #define SDMA1_QUEUE1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL |
3848 | //SDMA1_QUEUE1_RB_RPTR_HI |
3849 | #define SDMA1_QUEUE1_RB_RPTR_HI__OFFSET__SHIFT 0x0 |
3850 | #define SDMA1_QUEUE1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
3851 | //SDMA1_QUEUE1_RB_WPTR |
3852 | #define SDMA1_QUEUE1_RB_WPTR__OFFSET__SHIFT 0x0 |
3853 | #define SDMA1_QUEUE1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL |
3854 | //SDMA1_QUEUE1_RB_WPTR_HI |
3855 | #define SDMA1_QUEUE1_RB_WPTR_HI__OFFSET__SHIFT 0x0 |
3856 | #define SDMA1_QUEUE1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
3857 | //SDMA1_QUEUE1_RB_RPTR_ADDR_HI |
3858 | #define SDMA1_QUEUE1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 |
3859 | #define SDMA1_QUEUE1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
3860 | //SDMA1_QUEUE1_RB_RPTR_ADDR_LO |
3861 | #define SDMA1_QUEUE1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 |
3862 | #define SDMA1_QUEUE1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
3863 | //SDMA1_QUEUE1_IB_CNTL |
3864 | #define SDMA1_QUEUE1_IB_CNTL__IB_ENABLE__SHIFT 0x0 |
3865 | #define SDMA1_QUEUE1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 |
3866 | #define SDMA1_QUEUE1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 |
3867 | #define SDMA1_QUEUE1_IB_CNTL__CMD_VMID__SHIFT 0x10 |
3868 | #define SDMA1_QUEUE1_IB_CNTL__IB_PRIV__SHIFT 0x1f |
3869 | #define SDMA1_QUEUE1_IB_CNTL__IB_ENABLE_MASK 0x00000001L |
3870 | #define SDMA1_QUEUE1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L |
3871 | #define SDMA1_QUEUE1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L |
3872 | #define SDMA1_QUEUE1_IB_CNTL__CMD_VMID_MASK 0x000F0000L |
3873 | #define SDMA1_QUEUE1_IB_CNTL__IB_PRIV_MASK 0x80000000L |
3874 | //SDMA1_QUEUE1_IB_RPTR |
3875 | #define SDMA1_QUEUE1_IB_RPTR__OFFSET__SHIFT 0x2 |
3876 | #define SDMA1_QUEUE1_IB_RPTR__OFFSET_MASK 0x003FFFFCL |
3877 | //SDMA1_QUEUE1_IB_OFFSET |
3878 | #define SDMA1_QUEUE1_IB_OFFSET__OFFSET__SHIFT 0x2 |
3879 | #define SDMA1_QUEUE1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL |
3880 | //SDMA1_QUEUE1_IB_BASE_LO |
3881 | #define SDMA1_QUEUE1_IB_BASE_LO__ADDR__SHIFT 0x5 |
3882 | #define SDMA1_QUEUE1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L |
3883 | //SDMA1_QUEUE1_IB_BASE_HI |
3884 | #define SDMA1_QUEUE1_IB_BASE_HI__ADDR__SHIFT 0x0 |
3885 | #define SDMA1_QUEUE1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL |
3886 | //SDMA1_QUEUE1_IB_SIZE |
3887 | #define SDMA1_QUEUE1_IB_SIZE__SIZE__SHIFT 0x0 |
3888 | #define SDMA1_QUEUE1_IB_SIZE__SIZE_MASK 0x000FFFFFL |
3889 | //SDMA1_QUEUE1_SKIP_CNTL |
3890 | #define SDMA1_QUEUE1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 |
3891 | #define SDMA1_QUEUE1_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL |
3892 | //SDMA1_QUEUE1_CONTEXT_STATUS |
3893 | #define SDMA1_QUEUE1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 |
3894 | #define SDMA1_QUEUE1_CONTEXT_STATUS__IDLE__SHIFT 0x2 |
3895 | #define SDMA1_QUEUE1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 |
3896 | #define SDMA1_QUEUE1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 |
3897 | #define SDMA1_QUEUE1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 |
3898 | #define SDMA1_QUEUE1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa |
3899 | #define SDMA1_QUEUE1_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb |
3900 | #define SDMA1_QUEUE1_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc |
3901 | #define SDMA1_QUEUE1_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 |
3902 | #define SDMA1_QUEUE1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L |
3903 | #define SDMA1_QUEUE1_CONTEXT_STATUS__IDLE_MASK 0x00000004L |
3904 | #define SDMA1_QUEUE1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L |
3905 | #define SDMA1_QUEUE1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L |
3906 | #define SDMA1_QUEUE1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L |
3907 | #define SDMA1_QUEUE1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L |
3908 | #define SDMA1_QUEUE1_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L |
3909 | #define SDMA1_QUEUE1_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L |
3910 | #define SDMA1_QUEUE1_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L |
3911 | //SDMA1_QUEUE1_DOORBELL |
3912 | #define SDMA1_QUEUE1_DOORBELL__ENABLE__SHIFT 0x1c |
3913 | #define SDMA1_QUEUE1_DOORBELL__CAPTURED__SHIFT 0x1e |
3914 | #define SDMA1_QUEUE1_DOORBELL__ENABLE_MASK 0x10000000L |
3915 | #define SDMA1_QUEUE1_DOORBELL__CAPTURED_MASK 0x40000000L |
3916 | //SDMA1_QUEUE1_DOORBELL_LOG |
3917 | #define SDMA1_QUEUE1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 |
3918 | #define SDMA1_QUEUE1_DOORBELL_LOG__DATA__SHIFT 0x2 |
3919 | #define SDMA1_QUEUE1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L |
3920 | #define SDMA1_QUEUE1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL |
3921 | //SDMA1_QUEUE1_DOORBELL_OFFSET |
3922 | #define SDMA1_QUEUE1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 |
3923 | #define SDMA1_QUEUE1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL |
3924 | //SDMA1_QUEUE1_CSA_ADDR_LO |
3925 | #define SDMA1_QUEUE1_CSA_ADDR_LO__ADDR__SHIFT 0x2 |
3926 | #define SDMA1_QUEUE1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
3927 | //SDMA1_QUEUE1_CSA_ADDR_HI |
3928 | #define SDMA1_QUEUE1_CSA_ADDR_HI__ADDR__SHIFT 0x0 |
3929 | #define SDMA1_QUEUE1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
3930 | //SDMA1_QUEUE1_SCHEDULE_CNTL |
3931 | #define SDMA1_QUEUE1_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 |
3932 | #define SDMA1_QUEUE1_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 |
3933 | #define SDMA1_QUEUE1_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 |
3934 | #define SDMA1_QUEUE1_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 |
3935 | #define SDMA1_QUEUE1_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L |
3936 | #define SDMA1_QUEUE1_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL |
3937 | #define SDMA1_QUEUE1_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L |
3938 | #define SDMA1_QUEUE1_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L |
3939 | //SDMA1_QUEUE1_IB_SUB_REMAIN |
3940 | #define SDMA1_QUEUE1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 |
3941 | #define SDMA1_QUEUE1_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL |
3942 | //SDMA1_QUEUE1_PREEMPT |
3943 | #define SDMA1_QUEUE1_PREEMPT__IB_PREEMPT__SHIFT 0x0 |
3944 | #define SDMA1_QUEUE1_PREEMPT__IB_PREEMPT_MASK 0x00000001L |
3945 | //SDMA1_QUEUE1_DUMMY_REG |
3946 | #define SDMA1_QUEUE1_DUMMY_REG__DUMMY__SHIFT 0x0 |
3947 | #define SDMA1_QUEUE1_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL |
3948 | //SDMA1_QUEUE1_RB_WPTR_POLL_ADDR_HI |
3949 | #define SDMA1_QUEUE1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 |
3950 | #define SDMA1_QUEUE1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
3951 | //SDMA1_QUEUE1_RB_WPTR_POLL_ADDR_LO |
3952 | #define SDMA1_QUEUE1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 |
3953 | #define SDMA1_QUEUE1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
3954 | //SDMA1_QUEUE1_RB_AQL_CNTL |
3955 | #define SDMA1_QUEUE1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 |
3956 | #define SDMA1_QUEUE1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 |
3957 | #define SDMA1_QUEUE1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 |
3958 | #define SDMA1_QUEUE1_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 |
3959 | #define SDMA1_QUEUE1_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 |
3960 | #define SDMA1_QUEUE1_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 |
3961 | #define SDMA1_QUEUE1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L |
3962 | #define SDMA1_QUEUE1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL |
3963 | #define SDMA1_QUEUE1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L |
3964 | #define SDMA1_QUEUE1_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L |
3965 | #define SDMA1_QUEUE1_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L |
3966 | #define SDMA1_QUEUE1_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L |
3967 | //SDMA1_QUEUE1_MINOR_PTR_UPDATE |
3968 | #define SDMA1_QUEUE1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 |
3969 | #define SDMA1_QUEUE1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L |
3970 | //SDMA1_QUEUE1_RB_PREEMPT |
3971 | #define SDMA1_QUEUE1_RB_PREEMPT__PREEMPT_REQ__SHIFT 0x0 |
3972 | #define SDMA1_QUEUE1_RB_PREEMPT__PREEMPT_REQ_MASK 0x00000001L |
3973 | //SDMA1_QUEUE1_MIDCMD_DATA0 |
3974 | #define SDMA1_QUEUE1_MIDCMD_DATA0__DATA0__SHIFT 0x0 |
3975 | #define SDMA1_QUEUE1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL |
3976 | //SDMA1_QUEUE1_MIDCMD_DATA1 |
3977 | #define SDMA1_QUEUE1_MIDCMD_DATA1__DATA1__SHIFT 0x0 |
3978 | #define SDMA1_QUEUE1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL |
3979 | //SDMA1_QUEUE1_MIDCMD_DATA2 |
3980 | #define SDMA1_QUEUE1_MIDCMD_DATA2__DATA2__SHIFT 0x0 |
3981 | #define SDMA1_QUEUE1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL |
3982 | //SDMA1_QUEUE1_MIDCMD_DATA3 |
3983 | #define SDMA1_QUEUE1_MIDCMD_DATA3__DATA3__SHIFT 0x0 |
3984 | #define SDMA1_QUEUE1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL |
3985 | //SDMA1_QUEUE1_MIDCMD_DATA4 |
3986 | #define SDMA1_QUEUE1_MIDCMD_DATA4__DATA4__SHIFT 0x0 |
3987 | #define SDMA1_QUEUE1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL |
3988 | //SDMA1_QUEUE1_MIDCMD_DATA5 |
3989 | #define SDMA1_QUEUE1_MIDCMD_DATA5__DATA5__SHIFT 0x0 |
3990 | #define SDMA1_QUEUE1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL |
3991 | //SDMA1_QUEUE1_MIDCMD_DATA6 |
3992 | #define SDMA1_QUEUE1_MIDCMD_DATA6__DATA6__SHIFT 0x0 |
3993 | #define SDMA1_QUEUE1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL |
3994 | //SDMA1_QUEUE1_MIDCMD_DATA7 |
3995 | #define SDMA1_QUEUE1_MIDCMD_DATA7__DATA7__SHIFT 0x0 |
3996 | #define SDMA1_QUEUE1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL |
3997 | //SDMA1_QUEUE1_MIDCMD_DATA8 |
3998 | #define SDMA1_QUEUE1_MIDCMD_DATA8__DATA8__SHIFT 0x0 |
3999 | #define SDMA1_QUEUE1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL |
4000 | //SDMA1_QUEUE1_MIDCMD_DATA9 |
4001 | #define SDMA1_QUEUE1_MIDCMD_DATA9__DATA9__SHIFT 0x0 |
4002 | #define SDMA1_QUEUE1_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL |
4003 | //SDMA1_QUEUE1_MIDCMD_DATA10 |
4004 | #define SDMA1_QUEUE1_MIDCMD_DATA10__DATA10__SHIFT 0x0 |
4005 | #define SDMA1_QUEUE1_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL |
4006 | //SDMA1_QUEUE1_MIDCMD_CNTL |
4007 | #define SDMA1_QUEUE1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 |
4008 | #define SDMA1_QUEUE1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 |
4009 | #define SDMA1_QUEUE1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 |
4010 | #define SDMA1_QUEUE1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 |
4011 | #define SDMA1_QUEUE1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L |
4012 | #define SDMA1_QUEUE1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L |
4013 | #define SDMA1_QUEUE1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L |
4014 | #define SDMA1_QUEUE1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L |
4015 | //SDMA1_QUEUE2_RB_CNTL |
4016 | #define SDMA1_QUEUE2_RB_CNTL__RB_ENABLE__SHIFT 0x0 |
4017 | #define SDMA1_QUEUE2_RB_CNTL__RB_SIZE__SHIFT 0x1 |
4018 | #define SDMA1_QUEUE2_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 |
4019 | #define SDMA1_QUEUE2_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 |
4020 | #define SDMA1_QUEUE2_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa |
4021 | #define SDMA1_QUEUE2_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT 0xb |
4022 | #define SDMA1_QUEUE2_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc |
4023 | #define SDMA1_QUEUE2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd |
4024 | #define SDMA1_QUEUE2_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 |
4025 | #define SDMA1_QUEUE2_RB_CNTL__RB_PRIV__SHIFT 0x17 |
4026 | #define SDMA1_QUEUE2_RB_CNTL__RB_VMID__SHIFT 0x18 |
4027 | #define SDMA1_QUEUE2_RB_CNTL__RB_ENABLE_MASK 0x00000001L |
4028 | #define SDMA1_QUEUE2_RB_CNTL__RB_SIZE_MASK 0x0000003EL |
4029 | #define SDMA1_QUEUE2_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L |
4030 | #define SDMA1_QUEUE2_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L |
4031 | #define SDMA1_QUEUE2_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L |
4032 | #define SDMA1_QUEUE2_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK 0x00000800L |
4033 | #define SDMA1_QUEUE2_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L |
4034 | #define SDMA1_QUEUE2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L |
4035 | #define SDMA1_QUEUE2_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L |
4036 | #define SDMA1_QUEUE2_RB_CNTL__RB_PRIV_MASK 0x00800000L |
4037 | #define SDMA1_QUEUE2_RB_CNTL__RB_VMID_MASK 0x0F000000L |
4038 | //SDMA1_QUEUE2_RB_BASE |
4039 | #define SDMA1_QUEUE2_RB_BASE__ADDR__SHIFT 0x0 |
4040 | #define SDMA1_QUEUE2_RB_BASE__ADDR_MASK 0xFFFFFFFFL |
4041 | //SDMA1_QUEUE2_RB_BASE_HI |
4042 | #define SDMA1_QUEUE2_RB_BASE_HI__ADDR__SHIFT 0x0 |
4043 | #define SDMA1_QUEUE2_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL |
4044 | //SDMA1_QUEUE2_RB_RPTR |
4045 | #define SDMA1_QUEUE2_RB_RPTR__OFFSET__SHIFT 0x0 |
4046 | #define SDMA1_QUEUE2_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL |
4047 | //SDMA1_QUEUE2_RB_RPTR_HI |
4048 | #define SDMA1_QUEUE2_RB_RPTR_HI__OFFSET__SHIFT 0x0 |
4049 | #define SDMA1_QUEUE2_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
4050 | //SDMA1_QUEUE2_RB_WPTR |
4051 | #define SDMA1_QUEUE2_RB_WPTR__OFFSET__SHIFT 0x0 |
4052 | #define SDMA1_QUEUE2_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL |
4053 | //SDMA1_QUEUE2_RB_WPTR_HI |
4054 | #define SDMA1_QUEUE2_RB_WPTR_HI__OFFSET__SHIFT 0x0 |
4055 | #define SDMA1_QUEUE2_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
4056 | //SDMA1_QUEUE2_RB_RPTR_ADDR_HI |
4057 | #define SDMA1_QUEUE2_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 |
4058 | #define SDMA1_QUEUE2_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
4059 | //SDMA1_QUEUE2_RB_RPTR_ADDR_LO |
4060 | #define SDMA1_QUEUE2_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 |
4061 | #define SDMA1_QUEUE2_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
4062 | //SDMA1_QUEUE2_IB_CNTL |
4063 | #define SDMA1_QUEUE2_IB_CNTL__IB_ENABLE__SHIFT 0x0 |
4064 | #define SDMA1_QUEUE2_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 |
4065 | #define SDMA1_QUEUE2_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 |
4066 | #define SDMA1_QUEUE2_IB_CNTL__CMD_VMID__SHIFT 0x10 |
4067 | #define SDMA1_QUEUE2_IB_CNTL__IB_PRIV__SHIFT 0x1f |
4068 | #define SDMA1_QUEUE2_IB_CNTL__IB_ENABLE_MASK 0x00000001L |
4069 | #define SDMA1_QUEUE2_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L |
4070 | #define SDMA1_QUEUE2_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L |
4071 | #define SDMA1_QUEUE2_IB_CNTL__CMD_VMID_MASK 0x000F0000L |
4072 | #define SDMA1_QUEUE2_IB_CNTL__IB_PRIV_MASK 0x80000000L |
4073 | //SDMA1_QUEUE2_IB_RPTR |
4074 | #define SDMA1_QUEUE2_IB_RPTR__OFFSET__SHIFT 0x2 |
4075 | #define SDMA1_QUEUE2_IB_RPTR__OFFSET_MASK 0x003FFFFCL |
4076 | //SDMA1_QUEUE2_IB_OFFSET |
4077 | #define SDMA1_QUEUE2_IB_OFFSET__OFFSET__SHIFT 0x2 |
4078 | #define SDMA1_QUEUE2_IB_OFFSET__OFFSET_MASK 0x003FFFFCL |
4079 | //SDMA1_QUEUE2_IB_BASE_LO |
4080 | #define SDMA1_QUEUE2_IB_BASE_LO__ADDR__SHIFT 0x5 |
4081 | #define SDMA1_QUEUE2_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L |
4082 | //SDMA1_QUEUE2_IB_BASE_HI |
4083 | #define SDMA1_QUEUE2_IB_BASE_HI__ADDR__SHIFT 0x0 |
4084 | #define SDMA1_QUEUE2_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL |
4085 | //SDMA1_QUEUE2_IB_SIZE |
4086 | #define SDMA1_QUEUE2_IB_SIZE__SIZE__SHIFT 0x0 |
4087 | #define SDMA1_QUEUE2_IB_SIZE__SIZE_MASK 0x000FFFFFL |
4088 | //SDMA1_QUEUE2_SKIP_CNTL |
4089 | #define SDMA1_QUEUE2_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 |
4090 | #define SDMA1_QUEUE2_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL |
4091 | //SDMA1_QUEUE2_CONTEXT_STATUS |
4092 | #define SDMA1_QUEUE2_CONTEXT_STATUS__SELECTED__SHIFT 0x0 |
4093 | #define SDMA1_QUEUE2_CONTEXT_STATUS__IDLE__SHIFT 0x2 |
4094 | #define SDMA1_QUEUE2_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 |
4095 | #define SDMA1_QUEUE2_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 |
4096 | #define SDMA1_QUEUE2_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 |
4097 | #define SDMA1_QUEUE2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa |
4098 | #define SDMA1_QUEUE2_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb |
4099 | #define SDMA1_QUEUE2_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc |
4100 | #define SDMA1_QUEUE2_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 |
4101 | #define SDMA1_QUEUE2_CONTEXT_STATUS__SELECTED_MASK 0x00000001L |
4102 | #define SDMA1_QUEUE2_CONTEXT_STATUS__IDLE_MASK 0x00000004L |
4103 | #define SDMA1_QUEUE2_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L |
4104 | #define SDMA1_QUEUE2_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L |
4105 | #define SDMA1_QUEUE2_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L |
4106 | #define SDMA1_QUEUE2_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L |
4107 | #define SDMA1_QUEUE2_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L |
4108 | #define SDMA1_QUEUE2_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L |
4109 | #define SDMA1_QUEUE2_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L |
4110 | //SDMA1_QUEUE2_DOORBELL |
4111 | #define SDMA1_QUEUE2_DOORBELL__ENABLE__SHIFT 0x1c |
4112 | #define SDMA1_QUEUE2_DOORBELL__CAPTURED__SHIFT 0x1e |
4113 | #define SDMA1_QUEUE2_DOORBELL__ENABLE_MASK 0x10000000L |
4114 | #define SDMA1_QUEUE2_DOORBELL__CAPTURED_MASK 0x40000000L |
4115 | //SDMA1_QUEUE2_DOORBELL_LOG |
4116 | #define SDMA1_QUEUE2_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 |
4117 | #define SDMA1_QUEUE2_DOORBELL_LOG__DATA__SHIFT 0x2 |
4118 | #define SDMA1_QUEUE2_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L |
4119 | #define SDMA1_QUEUE2_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL |
4120 | //SDMA1_QUEUE2_DOORBELL_OFFSET |
4121 | #define SDMA1_QUEUE2_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 |
4122 | #define SDMA1_QUEUE2_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL |
4123 | //SDMA1_QUEUE2_CSA_ADDR_LO |
4124 | #define SDMA1_QUEUE2_CSA_ADDR_LO__ADDR__SHIFT 0x2 |
4125 | #define SDMA1_QUEUE2_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
4126 | //SDMA1_QUEUE2_CSA_ADDR_HI |
4127 | #define SDMA1_QUEUE2_CSA_ADDR_HI__ADDR__SHIFT 0x0 |
4128 | #define SDMA1_QUEUE2_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
4129 | //SDMA1_QUEUE2_SCHEDULE_CNTL |
4130 | #define SDMA1_QUEUE2_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 |
4131 | #define SDMA1_QUEUE2_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 |
4132 | #define SDMA1_QUEUE2_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 |
4133 | #define SDMA1_QUEUE2_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 |
4134 | #define SDMA1_QUEUE2_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L |
4135 | #define SDMA1_QUEUE2_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL |
4136 | #define SDMA1_QUEUE2_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L |
4137 | #define SDMA1_QUEUE2_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L |
4138 | //SDMA1_QUEUE2_IB_SUB_REMAIN |
4139 | #define SDMA1_QUEUE2_IB_SUB_REMAIN__SIZE__SHIFT 0x0 |
4140 | #define SDMA1_QUEUE2_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL |
4141 | //SDMA1_QUEUE2_PREEMPT |
4142 | #define SDMA1_QUEUE2_PREEMPT__IB_PREEMPT__SHIFT 0x0 |
4143 | #define SDMA1_QUEUE2_PREEMPT__IB_PREEMPT_MASK 0x00000001L |
4144 | //SDMA1_QUEUE2_DUMMY_REG |
4145 | #define SDMA1_QUEUE2_DUMMY_REG__DUMMY__SHIFT 0x0 |
4146 | #define SDMA1_QUEUE2_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL |
4147 | //SDMA1_QUEUE2_RB_WPTR_POLL_ADDR_HI |
4148 | #define SDMA1_QUEUE2_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 |
4149 | #define SDMA1_QUEUE2_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
4150 | //SDMA1_QUEUE2_RB_WPTR_POLL_ADDR_LO |
4151 | #define SDMA1_QUEUE2_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 |
4152 | #define SDMA1_QUEUE2_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
4153 | //SDMA1_QUEUE2_RB_AQL_CNTL |
4154 | #define SDMA1_QUEUE2_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 |
4155 | #define SDMA1_QUEUE2_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 |
4156 | #define SDMA1_QUEUE2_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 |
4157 | #define SDMA1_QUEUE2_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 |
4158 | #define SDMA1_QUEUE2_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 |
4159 | #define SDMA1_QUEUE2_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 |
4160 | #define SDMA1_QUEUE2_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L |
4161 | #define SDMA1_QUEUE2_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL |
4162 | #define SDMA1_QUEUE2_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L |
4163 | #define SDMA1_QUEUE2_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L |
4164 | #define SDMA1_QUEUE2_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L |
4165 | #define SDMA1_QUEUE2_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L |
4166 | //SDMA1_QUEUE2_MINOR_PTR_UPDATE |
4167 | #define SDMA1_QUEUE2_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 |
4168 | #define SDMA1_QUEUE2_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L |
4169 | //SDMA1_QUEUE2_RB_PREEMPT |
4170 | #define SDMA1_QUEUE2_RB_PREEMPT__PREEMPT_REQ__SHIFT 0x0 |
4171 | #define SDMA1_QUEUE2_RB_PREEMPT__PREEMPT_REQ_MASK 0x00000001L |
4172 | //SDMA1_QUEUE2_MIDCMD_DATA0 |
4173 | #define SDMA1_QUEUE2_MIDCMD_DATA0__DATA0__SHIFT 0x0 |
4174 | #define SDMA1_QUEUE2_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL |
4175 | //SDMA1_QUEUE2_MIDCMD_DATA1 |
4176 | #define SDMA1_QUEUE2_MIDCMD_DATA1__DATA1__SHIFT 0x0 |
4177 | #define SDMA1_QUEUE2_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL |
4178 | //SDMA1_QUEUE2_MIDCMD_DATA2 |
4179 | #define SDMA1_QUEUE2_MIDCMD_DATA2__DATA2__SHIFT 0x0 |
4180 | #define SDMA1_QUEUE2_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL |
4181 | //SDMA1_QUEUE2_MIDCMD_DATA3 |
4182 | #define SDMA1_QUEUE2_MIDCMD_DATA3__DATA3__SHIFT 0x0 |
4183 | #define SDMA1_QUEUE2_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL |
4184 | //SDMA1_QUEUE2_MIDCMD_DATA4 |
4185 | #define SDMA1_QUEUE2_MIDCMD_DATA4__DATA4__SHIFT 0x0 |
4186 | #define SDMA1_QUEUE2_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL |
4187 | //SDMA1_QUEUE2_MIDCMD_DATA5 |
4188 | #define SDMA1_QUEUE2_MIDCMD_DATA5__DATA5__SHIFT 0x0 |
4189 | #define SDMA1_QUEUE2_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL |
4190 | //SDMA1_QUEUE2_MIDCMD_DATA6 |
4191 | #define SDMA1_QUEUE2_MIDCMD_DATA6__DATA6__SHIFT 0x0 |
4192 | #define SDMA1_QUEUE2_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL |
4193 | //SDMA1_QUEUE2_MIDCMD_DATA7 |
4194 | #define SDMA1_QUEUE2_MIDCMD_DATA7__DATA7__SHIFT 0x0 |
4195 | #define SDMA1_QUEUE2_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL |
4196 | //SDMA1_QUEUE2_MIDCMD_DATA8 |
4197 | #define SDMA1_QUEUE2_MIDCMD_DATA8__DATA8__SHIFT 0x0 |
4198 | #define SDMA1_QUEUE2_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL |
4199 | //SDMA1_QUEUE2_MIDCMD_DATA9 |
4200 | #define SDMA1_QUEUE2_MIDCMD_DATA9__DATA9__SHIFT 0x0 |
4201 | #define SDMA1_QUEUE2_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL |
4202 | //SDMA1_QUEUE2_MIDCMD_DATA10 |
4203 | #define SDMA1_QUEUE2_MIDCMD_DATA10__DATA10__SHIFT 0x0 |
4204 | #define SDMA1_QUEUE2_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL |
4205 | //SDMA1_QUEUE2_MIDCMD_CNTL |
4206 | #define SDMA1_QUEUE2_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 |
4207 | #define SDMA1_QUEUE2_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 |
4208 | #define SDMA1_QUEUE2_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 |
4209 | #define SDMA1_QUEUE2_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 |
4210 | #define SDMA1_QUEUE2_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L |
4211 | #define SDMA1_QUEUE2_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L |
4212 | #define SDMA1_QUEUE2_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L |
4213 | #define SDMA1_QUEUE2_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L |
4214 | //SDMA1_QUEUE3_RB_CNTL |
4215 | #define SDMA1_QUEUE3_RB_CNTL__RB_ENABLE__SHIFT 0x0 |
4216 | #define SDMA1_QUEUE3_RB_CNTL__RB_SIZE__SHIFT 0x1 |
4217 | #define SDMA1_QUEUE3_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 |
4218 | #define SDMA1_QUEUE3_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 |
4219 | #define SDMA1_QUEUE3_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa |
4220 | #define SDMA1_QUEUE3_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT 0xb |
4221 | #define SDMA1_QUEUE3_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc |
4222 | #define SDMA1_QUEUE3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd |
4223 | #define SDMA1_QUEUE3_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 |
4224 | #define SDMA1_QUEUE3_RB_CNTL__RB_PRIV__SHIFT 0x17 |
4225 | #define SDMA1_QUEUE3_RB_CNTL__RB_VMID__SHIFT 0x18 |
4226 | #define SDMA1_QUEUE3_RB_CNTL__RB_ENABLE_MASK 0x00000001L |
4227 | #define SDMA1_QUEUE3_RB_CNTL__RB_SIZE_MASK 0x0000003EL |
4228 | #define SDMA1_QUEUE3_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L |
4229 | #define SDMA1_QUEUE3_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L |
4230 | #define SDMA1_QUEUE3_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L |
4231 | #define SDMA1_QUEUE3_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK 0x00000800L |
4232 | #define SDMA1_QUEUE3_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L |
4233 | #define SDMA1_QUEUE3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L |
4234 | #define SDMA1_QUEUE3_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L |
4235 | #define SDMA1_QUEUE3_RB_CNTL__RB_PRIV_MASK 0x00800000L |
4236 | #define SDMA1_QUEUE3_RB_CNTL__RB_VMID_MASK 0x0F000000L |
4237 | //SDMA1_QUEUE3_RB_BASE |
4238 | #define SDMA1_QUEUE3_RB_BASE__ADDR__SHIFT 0x0 |
4239 | #define SDMA1_QUEUE3_RB_BASE__ADDR_MASK 0xFFFFFFFFL |
4240 | //SDMA1_QUEUE3_RB_BASE_HI |
4241 | #define SDMA1_QUEUE3_RB_BASE_HI__ADDR__SHIFT 0x0 |
4242 | #define SDMA1_QUEUE3_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL |
4243 | //SDMA1_QUEUE3_RB_RPTR |
4244 | #define SDMA1_QUEUE3_RB_RPTR__OFFSET__SHIFT 0x0 |
4245 | #define SDMA1_QUEUE3_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL |
4246 | //SDMA1_QUEUE3_RB_RPTR_HI |
4247 | #define SDMA1_QUEUE3_RB_RPTR_HI__OFFSET__SHIFT 0x0 |
4248 | #define SDMA1_QUEUE3_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
4249 | //SDMA1_QUEUE3_RB_WPTR |
4250 | #define SDMA1_QUEUE3_RB_WPTR__OFFSET__SHIFT 0x0 |
4251 | #define SDMA1_QUEUE3_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL |
4252 | //SDMA1_QUEUE3_RB_WPTR_HI |
4253 | #define SDMA1_QUEUE3_RB_WPTR_HI__OFFSET__SHIFT 0x0 |
4254 | #define SDMA1_QUEUE3_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
4255 | //SDMA1_QUEUE3_RB_RPTR_ADDR_HI |
4256 | #define SDMA1_QUEUE3_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 |
4257 | #define SDMA1_QUEUE3_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
4258 | //SDMA1_QUEUE3_RB_RPTR_ADDR_LO |
4259 | #define SDMA1_QUEUE3_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 |
4260 | #define SDMA1_QUEUE3_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
4261 | //SDMA1_QUEUE3_IB_CNTL |
4262 | #define SDMA1_QUEUE3_IB_CNTL__IB_ENABLE__SHIFT 0x0 |
4263 | #define SDMA1_QUEUE3_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 |
4264 | #define SDMA1_QUEUE3_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 |
4265 | #define SDMA1_QUEUE3_IB_CNTL__CMD_VMID__SHIFT 0x10 |
4266 | #define SDMA1_QUEUE3_IB_CNTL__IB_PRIV__SHIFT 0x1f |
4267 | #define SDMA1_QUEUE3_IB_CNTL__IB_ENABLE_MASK 0x00000001L |
4268 | #define SDMA1_QUEUE3_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L |
4269 | #define SDMA1_QUEUE3_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L |
4270 | #define SDMA1_QUEUE3_IB_CNTL__CMD_VMID_MASK 0x000F0000L |
4271 | #define SDMA1_QUEUE3_IB_CNTL__IB_PRIV_MASK 0x80000000L |
4272 | //SDMA1_QUEUE3_IB_RPTR |
4273 | #define SDMA1_QUEUE3_IB_RPTR__OFFSET__SHIFT 0x2 |
4274 | #define SDMA1_QUEUE3_IB_RPTR__OFFSET_MASK 0x003FFFFCL |
4275 | //SDMA1_QUEUE3_IB_OFFSET |
4276 | #define SDMA1_QUEUE3_IB_OFFSET__OFFSET__SHIFT 0x2 |
4277 | #define SDMA1_QUEUE3_IB_OFFSET__OFFSET_MASK 0x003FFFFCL |
4278 | //SDMA1_QUEUE3_IB_BASE_LO |
4279 | #define SDMA1_QUEUE3_IB_BASE_LO__ADDR__SHIFT 0x5 |
4280 | #define SDMA1_QUEUE3_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L |
4281 | //SDMA1_QUEUE3_IB_BASE_HI |
4282 | #define SDMA1_QUEUE3_IB_BASE_HI__ADDR__SHIFT 0x0 |
4283 | #define SDMA1_QUEUE3_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL |
4284 | //SDMA1_QUEUE3_IB_SIZE |
4285 | #define SDMA1_QUEUE3_IB_SIZE__SIZE__SHIFT 0x0 |
4286 | #define SDMA1_QUEUE3_IB_SIZE__SIZE_MASK 0x000FFFFFL |
4287 | //SDMA1_QUEUE3_SKIP_CNTL |
4288 | #define SDMA1_QUEUE3_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 |
4289 | #define SDMA1_QUEUE3_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL |
4290 | //SDMA1_QUEUE3_CONTEXT_STATUS |
4291 | #define SDMA1_QUEUE3_CONTEXT_STATUS__SELECTED__SHIFT 0x0 |
4292 | #define SDMA1_QUEUE3_CONTEXT_STATUS__IDLE__SHIFT 0x2 |
4293 | #define SDMA1_QUEUE3_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 |
4294 | #define SDMA1_QUEUE3_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 |
4295 | #define SDMA1_QUEUE3_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 |
4296 | #define SDMA1_QUEUE3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa |
4297 | #define SDMA1_QUEUE3_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb |
4298 | #define SDMA1_QUEUE3_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc |
4299 | #define SDMA1_QUEUE3_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 |
4300 | #define SDMA1_QUEUE3_CONTEXT_STATUS__SELECTED_MASK 0x00000001L |
4301 | #define SDMA1_QUEUE3_CONTEXT_STATUS__IDLE_MASK 0x00000004L |
4302 | #define SDMA1_QUEUE3_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L |
4303 | #define SDMA1_QUEUE3_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L |
4304 | #define SDMA1_QUEUE3_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L |
4305 | #define SDMA1_QUEUE3_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L |
4306 | #define SDMA1_QUEUE3_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L |
4307 | #define SDMA1_QUEUE3_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L |
4308 | #define SDMA1_QUEUE3_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L |
4309 | //SDMA1_QUEUE3_DOORBELL |
4310 | #define SDMA1_QUEUE3_DOORBELL__ENABLE__SHIFT 0x1c |
4311 | #define SDMA1_QUEUE3_DOORBELL__CAPTURED__SHIFT 0x1e |
4312 | #define SDMA1_QUEUE3_DOORBELL__ENABLE_MASK 0x10000000L |
4313 | #define SDMA1_QUEUE3_DOORBELL__CAPTURED_MASK 0x40000000L |
4314 | //SDMA1_QUEUE3_DOORBELL_LOG |
4315 | #define SDMA1_QUEUE3_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 |
4316 | #define SDMA1_QUEUE3_DOORBELL_LOG__DATA__SHIFT 0x2 |
4317 | #define SDMA1_QUEUE3_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L |
4318 | #define SDMA1_QUEUE3_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL |
4319 | //SDMA1_QUEUE3_DOORBELL_OFFSET |
4320 | #define SDMA1_QUEUE3_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 |
4321 | #define SDMA1_QUEUE3_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL |
4322 | //SDMA1_QUEUE3_CSA_ADDR_LO |
4323 | #define SDMA1_QUEUE3_CSA_ADDR_LO__ADDR__SHIFT 0x2 |
4324 | #define SDMA1_QUEUE3_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
4325 | //SDMA1_QUEUE3_CSA_ADDR_HI |
4326 | #define SDMA1_QUEUE3_CSA_ADDR_HI__ADDR__SHIFT 0x0 |
4327 | #define SDMA1_QUEUE3_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
4328 | //SDMA1_QUEUE3_SCHEDULE_CNTL |
4329 | #define SDMA1_QUEUE3_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 |
4330 | #define SDMA1_QUEUE3_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 |
4331 | #define SDMA1_QUEUE3_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 |
4332 | #define SDMA1_QUEUE3_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 |
4333 | #define SDMA1_QUEUE3_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L |
4334 | #define SDMA1_QUEUE3_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL |
4335 | #define SDMA1_QUEUE3_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L |
4336 | #define SDMA1_QUEUE3_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L |
4337 | //SDMA1_QUEUE3_IB_SUB_REMAIN |
4338 | #define SDMA1_QUEUE3_IB_SUB_REMAIN__SIZE__SHIFT 0x0 |
4339 | #define SDMA1_QUEUE3_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL |
4340 | //SDMA1_QUEUE3_PREEMPT |
4341 | #define SDMA1_QUEUE3_PREEMPT__IB_PREEMPT__SHIFT 0x0 |
4342 | #define SDMA1_QUEUE3_PREEMPT__IB_PREEMPT_MASK 0x00000001L |
4343 | //SDMA1_QUEUE3_DUMMY_REG |
4344 | #define SDMA1_QUEUE3_DUMMY_REG__DUMMY__SHIFT 0x0 |
4345 | #define SDMA1_QUEUE3_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL |
4346 | //SDMA1_QUEUE3_RB_WPTR_POLL_ADDR_HI |
4347 | #define SDMA1_QUEUE3_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 |
4348 | #define SDMA1_QUEUE3_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
4349 | //SDMA1_QUEUE3_RB_WPTR_POLL_ADDR_LO |
4350 | #define SDMA1_QUEUE3_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 |
4351 | #define SDMA1_QUEUE3_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
4352 | //SDMA1_QUEUE3_RB_AQL_CNTL |
4353 | #define SDMA1_QUEUE3_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 |
4354 | #define SDMA1_QUEUE3_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 |
4355 | #define SDMA1_QUEUE3_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 |
4356 | #define SDMA1_QUEUE3_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 |
4357 | #define SDMA1_QUEUE3_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 |
4358 | #define SDMA1_QUEUE3_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 |
4359 | #define SDMA1_QUEUE3_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L |
4360 | #define SDMA1_QUEUE3_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL |
4361 | #define SDMA1_QUEUE3_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L |
4362 | #define SDMA1_QUEUE3_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L |
4363 | #define SDMA1_QUEUE3_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L |
4364 | #define SDMA1_QUEUE3_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L |
4365 | //SDMA1_QUEUE3_MINOR_PTR_UPDATE |
4366 | #define SDMA1_QUEUE3_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 |
4367 | #define SDMA1_QUEUE3_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L |
4368 | //SDMA1_QUEUE3_RB_PREEMPT |
4369 | #define SDMA1_QUEUE3_RB_PREEMPT__PREEMPT_REQ__SHIFT 0x0 |
4370 | #define SDMA1_QUEUE3_RB_PREEMPT__PREEMPT_REQ_MASK 0x00000001L |
4371 | //SDMA1_QUEUE3_MIDCMD_DATA0 |
4372 | #define SDMA1_QUEUE3_MIDCMD_DATA0__DATA0__SHIFT 0x0 |
4373 | #define SDMA1_QUEUE3_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL |
4374 | //SDMA1_QUEUE3_MIDCMD_DATA1 |
4375 | #define SDMA1_QUEUE3_MIDCMD_DATA1__DATA1__SHIFT 0x0 |
4376 | #define SDMA1_QUEUE3_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL |
4377 | //SDMA1_QUEUE3_MIDCMD_DATA2 |
4378 | #define SDMA1_QUEUE3_MIDCMD_DATA2__DATA2__SHIFT 0x0 |
4379 | #define SDMA1_QUEUE3_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL |
4380 | //SDMA1_QUEUE3_MIDCMD_DATA3 |
4381 | #define SDMA1_QUEUE3_MIDCMD_DATA3__DATA3__SHIFT 0x0 |
4382 | #define SDMA1_QUEUE3_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL |
4383 | //SDMA1_QUEUE3_MIDCMD_DATA4 |
4384 | #define SDMA1_QUEUE3_MIDCMD_DATA4__DATA4__SHIFT 0x0 |
4385 | #define SDMA1_QUEUE3_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL |
4386 | //SDMA1_QUEUE3_MIDCMD_DATA5 |
4387 | #define SDMA1_QUEUE3_MIDCMD_DATA5__DATA5__SHIFT 0x0 |
4388 | #define SDMA1_QUEUE3_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL |
4389 | //SDMA1_QUEUE3_MIDCMD_DATA6 |
4390 | #define SDMA1_QUEUE3_MIDCMD_DATA6__DATA6__SHIFT 0x0 |
4391 | #define SDMA1_QUEUE3_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL |
4392 | //SDMA1_QUEUE3_MIDCMD_DATA7 |
4393 | #define SDMA1_QUEUE3_MIDCMD_DATA7__DATA7__SHIFT 0x0 |
4394 | #define SDMA1_QUEUE3_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL |
4395 | //SDMA1_QUEUE3_MIDCMD_DATA8 |
4396 | #define SDMA1_QUEUE3_MIDCMD_DATA8__DATA8__SHIFT 0x0 |
4397 | #define SDMA1_QUEUE3_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL |
4398 | //SDMA1_QUEUE3_MIDCMD_DATA9 |
4399 | #define SDMA1_QUEUE3_MIDCMD_DATA9__DATA9__SHIFT 0x0 |
4400 | #define SDMA1_QUEUE3_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL |
4401 | //SDMA1_QUEUE3_MIDCMD_DATA10 |
4402 | #define SDMA1_QUEUE3_MIDCMD_DATA10__DATA10__SHIFT 0x0 |
4403 | #define SDMA1_QUEUE3_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL |
4404 | //SDMA1_QUEUE3_MIDCMD_CNTL |
4405 | #define SDMA1_QUEUE3_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 |
4406 | #define SDMA1_QUEUE3_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 |
4407 | #define SDMA1_QUEUE3_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 |
4408 | #define SDMA1_QUEUE3_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 |
4409 | #define SDMA1_QUEUE3_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L |
4410 | #define SDMA1_QUEUE3_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L |
4411 | #define SDMA1_QUEUE3_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L |
4412 | #define SDMA1_QUEUE3_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L |
4413 | //SDMA1_QUEUE4_RB_CNTL |
4414 | #define SDMA1_QUEUE4_RB_CNTL__RB_ENABLE__SHIFT 0x0 |
4415 | #define SDMA1_QUEUE4_RB_CNTL__RB_SIZE__SHIFT 0x1 |
4416 | #define SDMA1_QUEUE4_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 |
4417 | #define SDMA1_QUEUE4_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 |
4418 | #define SDMA1_QUEUE4_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa |
4419 | #define SDMA1_QUEUE4_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT 0xb |
4420 | #define SDMA1_QUEUE4_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc |
4421 | #define SDMA1_QUEUE4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd |
4422 | #define SDMA1_QUEUE4_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 |
4423 | #define SDMA1_QUEUE4_RB_CNTL__RB_PRIV__SHIFT 0x17 |
4424 | #define SDMA1_QUEUE4_RB_CNTL__RB_VMID__SHIFT 0x18 |
4425 | #define SDMA1_QUEUE4_RB_CNTL__RB_ENABLE_MASK 0x00000001L |
4426 | #define SDMA1_QUEUE4_RB_CNTL__RB_SIZE_MASK 0x0000003EL |
4427 | #define SDMA1_QUEUE4_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L |
4428 | #define SDMA1_QUEUE4_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L |
4429 | #define SDMA1_QUEUE4_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L |
4430 | #define SDMA1_QUEUE4_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK 0x00000800L |
4431 | #define SDMA1_QUEUE4_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L |
4432 | #define SDMA1_QUEUE4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L |
4433 | #define SDMA1_QUEUE4_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L |
4434 | #define SDMA1_QUEUE4_RB_CNTL__RB_PRIV_MASK 0x00800000L |
4435 | #define SDMA1_QUEUE4_RB_CNTL__RB_VMID_MASK 0x0F000000L |
4436 | //SDMA1_QUEUE4_RB_BASE |
4437 | #define SDMA1_QUEUE4_RB_BASE__ADDR__SHIFT 0x0 |
4438 | #define SDMA1_QUEUE4_RB_BASE__ADDR_MASK 0xFFFFFFFFL |
4439 | //SDMA1_QUEUE4_RB_BASE_HI |
4440 | #define SDMA1_QUEUE4_RB_BASE_HI__ADDR__SHIFT 0x0 |
4441 | #define SDMA1_QUEUE4_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL |
4442 | //SDMA1_QUEUE4_RB_RPTR |
4443 | #define SDMA1_QUEUE4_RB_RPTR__OFFSET__SHIFT 0x0 |
4444 | #define SDMA1_QUEUE4_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL |
4445 | //SDMA1_QUEUE4_RB_RPTR_HI |
4446 | #define SDMA1_QUEUE4_RB_RPTR_HI__OFFSET__SHIFT 0x0 |
4447 | #define SDMA1_QUEUE4_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
4448 | //SDMA1_QUEUE4_RB_WPTR |
4449 | #define SDMA1_QUEUE4_RB_WPTR__OFFSET__SHIFT 0x0 |
4450 | #define SDMA1_QUEUE4_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL |
4451 | //SDMA1_QUEUE4_RB_WPTR_HI |
4452 | #define SDMA1_QUEUE4_RB_WPTR_HI__OFFSET__SHIFT 0x0 |
4453 | #define SDMA1_QUEUE4_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
4454 | //SDMA1_QUEUE4_RB_RPTR_ADDR_HI |
4455 | #define SDMA1_QUEUE4_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 |
4456 | #define SDMA1_QUEUE4_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
4457 | //SDMA1_QUEUE4_RB_RPTR_ADDR_LO |
4458 | #define SDMA1_QUEUE4_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 |
4459 | #define SDMA1_QUEUE4_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
4460 | //SDMA1_QUEUE4_IB_CNTL |
4461 | #define SDMA1_QUEUE4_IB_CNTL__IB_ENABLE__SHIFT 0x0 |
4462 | #define SDMA1_QUEUE4_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 |
4463 | #define SDMA1_QUEUE4_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 |
4464 | #define SDMA1_QUEUE4_IB_CNTL__CMD_VMID__SHIFT 0x10 |
4465 | #define SDMA1_QUEUE4_IB_CNTL__IB_PRIV__SHIFT 0x1f |
4466 | #define SDMA1_QUEUE4_IB_CNTL__IB_ENABLE_MASK 0x00000001L |
4467 | #define SDMA1_QUEUE4_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L |
4468 | #define SDMA1_QUEUE4_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L |
4469 | #define SDMA1_QUEUE4_IB_CNTL__CMD_VMID_MASK 0x000F0000L |
4470 | #define SDMA1_QUEUE4_IB_CNTL__IB_PRIV_MASK 0x80000000L |
4471 | //SDMA1_QUEUE4_IB_RPTR |
4472 | #define SDMA1_QUEUE4_IB_RPTR__OFFSET__SHIFT 0x2 |
4473 | #define SDMA1_QUEUE4_IB_RPTR__OFFSET_MASK 0x003FFFFCL |
4474 | //SDMA1_QUEUE4_IB_OFFSET |
4475 | #define SDMA1_QUEUE4_IB_OFFSET__OFFSET__SHIFT 0x2 |
4476 | #define SDMA1_QUEUE4_IB_OFFSET__OFFSET_MASK 0x003FFFFCL |
4477 | //SDMA1_QUEUE4_IB_BASE_LO |
4478 | #define SDMA1_QUEUE4_IB_BASE_LO__ADDR__SHIFT 0x5 |
4479 | #define SDMA1_QUEUE4_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L |
4480 | //SDMA1_QUEUE4_IB_BASE_HI |
4481 | #define SDMA1_QUEUE4_IB_BASE_HI__ADDR__SHIFT 0x0 |
4482 | #define SDMA1_QUEUE4_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL |
4483 | //SDMA1_QUEUE4_IB_SIZE |
4484 | #define SDMA1_QUEUE4_IB_SIZE__SIZE__SHIFT 0x0 |
4485 | #define SDMA1_QUEUE4_IB_SIZE__SIZE_MASK 0x000FFFFFL |
4486 | //SDMA1_QUEUE4_SKIP_CNTL |
4487 | #define SDMA1_QUEUE4_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 |
4488 | #define SDMA1_QUEUE4_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL |
4489 | //SDMA1_QUEUE4_CONTEXT_STATUS |
4490 | #define SDMA1_QUEUE4_CONTEXT_STATUS__SELECTED__SHIFT 0x0 |
4491 | #define SDMA1_QUEUE4_CONTEXT_STATUS__IDLE__SHIFT 0x2 |
4492 | #define SDMA1_QUEUE4_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 |
4493 | #define SDMA1_QUEUE4_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 |
4494 | #define SDMA1_QUEUE4_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 |
4495 | #define SDMA1_QUEUE4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa |
4496 | #define SDMA1_QUEUE4_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb |
4497 | #define SDMA1_QUEUE4_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc |
4498 | #define SDMA1_QUEUE4_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 |
4499 | #define SDMA1_QUEUE4_CONTEXT_STATUS__SELECTED_MASK 0x00000001L |
4500 | #define SDMA1_QUEUE4_CONTEXT_STATUS__IDLE_MASK 0x00000004L |
4501 | #define SDMA1_QUEUE4_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L |
4502 | #define SDMA1_QUEUE4_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L |
4503 | #define SDMA1_QUEUE4_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L |
4504 | #define SDMA1_QUEUE4_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L |
4505 | #define SDMA1_QUEUE4_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L |
4506 | #define SDMA1_QUEUE4_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L |
4507 | #define SDMA1_QUEUE4_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L |
4508 | //SDMA1_QUEUE4_DOORBELL |
4509 | #define SDMA1_QUEUE4_DOORBELL__ENABLE__SHIFT 0x1c |
4510 | #define SDMA1_QUEUE4_DOORBELL__CAPTURED__SHIFT 0x1e |
4511 | #define SDMA1_QUEUE4_DOORBELL__ENABLE_MASK 0x10000000L |
4512 | #define SDMA1_QUEUE4_DOORBELL__CAPTURED_MASK 0x40000000L |
4513 | //SDMA1_QUEUE4_DOORBELL_LOG |
4514 | #define SDMA1_QUEUE4_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 |
4515 | #define SDMA1_QUEUE4_DOORBELL_LOG__DATA__SHIFT 0x2 |
4516 | #define SDMA1_QUEUE4_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L |
4517 | #define SDMA1_QUEUE4_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL |
4518 | //SDMA1_QUEUE4_DOORBELL_OFFSET |
4519 | #define SDMA1_QUEUE4_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 |
4520 | #define SDMA1_QUEUE4_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL |
4521 | //SDMA1_QUEUE4_CSA_ADDR_LO |
4522 | #define SDMA1_QUEUE4_CSA_ADDR_LO__ADDR__SHIFT 0x2 |
4523 | #define SDMA1_QUEUE4_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
4524 | //SDMA1_QUEUE4_CSA_ADDR_HI |
4525 | #define SDMA1_QUEUE4_CSA_ADDR_HI__ADDR__SHIFT 0x0 |
4526 | #define SDMA1_QUEUE4_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
4527 | //SDMA1_QUEUE4_SCHEDULE_CNTL |
4528 | #define SDMA1_QUEUE4_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 |
4529 | #define SDMA1_QUEUE4_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 |
4530 | #define SDMA1_QUEUE4_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 |
4531 | #define SDMA1_QUEUE4_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 |
4532 | #define SDMA1_QUEUE4_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L |
4533 | #define SDMA1_QUEUE4_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL |
4534 | #define SDMA1_QUEUE4_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L |
4535 | #define SDMA1_QUEUE4_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L |
4536 | //SDMA1_QUEUE4_IB_SUB_REMAIN |
4537 | #define SDMA1_QUEUE4_IB_SUB_REMAIN__SIZE__SHIFT 0x0 |
4538 | #define SDMA1_QUEUE4_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL |
4539 | //SDMA1_QUEUE4_PREEMPT |
4540 | #define SDMA1_QUEUE4_PREEMPT__IB_PREEMPT__SHIFT 0x0 |
4541 | #define SDMA1_QUEUE4_PREEMPT__IB_PREEMPT_MASK 0x00000001L |
4542 | //SDMA1_QUEUE4_DUMMY_REG |
4543 | #define SDMA1_QUEUE4_DUMMY_REG__DUMMY__SHIFT 0x0 |
4544 | #define SDMA1_QUEUE4_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL |
4545 | //SDMA1_QUEUE4_RB_WPTR_POLL_ADDR_HI |
4546 | #define SDMA1_QUEUE4_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 |
4547 | #define SDMA1_QUEUE4_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
4548 | //SDMA1_QUEUE4_RB_WPTR_POLL_ADDR_LO |
4549 | #define SDMA1_QUEUE4_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 |
4550 | #define SDMA1_QUEUE4_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
4551 | //SDMA1_QUEUE4_RB_AQL_CNTL |
4552 | #define SDMA1_QUEUE4_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 |
4553 | #define SDMA1_QUEUE4_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 |
4554 | #define SDMA1_QUEUE4_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 |
4555 | #define SDMA1_QUEUE4_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 |
4556 | #define SDMA1_QUEUE4_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 |
4557 | #define SDMA1_QUEUE4_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 |
4558 | #define SDMA1_QUEUE4_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L |
4559 | #define SDMA1_QUEUE4_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL |
4560 | #define SDMA1_QUEUE4_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L |
4561 | #define SDMA1_QUEUE4_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L |
4562 | #define SDMA1_QUEUE4_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L |
4563 | #define SDMA1_QUEUE4_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L |
4564 | //SDMA1_QUEUE4_MINOR_PTR_UPDATE |
4565 | #define SDMA1_QUEUE4_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 |
4566 | #define SDMA1_QUEUE4_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L |
4567 | //SDMA1_QUEUE4_RB_PREEMPT |
4568 | #define SDMA1_QUEUE4_RB_PREEMPT__PREEMPT_REQ__SHIFT 0x0 |
4569 | #define SDMA1_QUEUE4_RB_PREEMPT__PREEMPT_REQ_MASK 0x00000001L |
4570 | //SDMA1_QUEUE4_MIDCMD_DATA0 |
4571 | #define SDMA1_QUEUE4_MIDCMD_DATA0__DATA0__SHIFT 0x0 |
4572 | #define SDMA1_QUEUE4_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL |
4573 | //SDMA1_QUEUE4_MIDCMD_DATA1 |
4574 | #define SDMA1_QUEUE4_MIDCMD_DATA1__DATA1__SHIFT 0x0 |
4575 | #define SDMA1_QUEUE4_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL |
4576 | //SDMA1_QUEUE4_MIDCMD_DATA2 |
4577 | #define SDMA1_QUEUE4_MIDCMD_DATA2__DATA2__SHIFT 0x0 |
4578 | #define SDMA1_QUEUE4_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL |
4579 | //SDMA1_QUEUE4_MIDCMD_DATA3 |
4580 | #define SDMA1_QUEUE4_MIDCMD_DATA3__DATA3__SHIFT 0x0 |
4581 | #define SDMA1_QUEUE4_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL |
4582 | //SDMA1_QUEUE4_MIDCMD_DATA4 |
4583 | #define SDMA1_QUEUE4_MIDCMD_DATA4__DATA4__SHIFT 0x0 |
4584 | #define SDMA1_QUEUE4_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL |
4585 | //SDMA1_QUEUE4_MIDCMD_DATA5 |
4586 | #define SDMA1_QUEUE4_MIDCMD_DATA5__DATA5__SHIFT 0x0 |
4587 | #define SDMA1_QUEUE4_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL |
4588 | //SDMA1_QUEUE4_MIDCMD_DATA6 |
4589 | #define SDMA1_QUEUE4_MIDCMD_DATA6__DATA6__SHIFT 0x0 |
4590 | #define SDMA1_QUEUE4_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL |
4591 | //SDMA1_QUEUE4_MIDCMD_DATA7 |
4592 | #define SDMA1_QUEUE4_MIDCMD_DATA7__DATA7__SHIFT 0x0 |
4593 | #define SDMA1_QUEUE4_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL |
4594 | //SDMA1_QUEUE4_MIDCMD_DATA8 |
4595 | #define SDMA1_QUEUE4_MIDCMD_DATA8__DATA8__SHIFT 0x0 |
4596 | #define SDMA1_QUEUE4_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL |
4597 | //SDMA1_QUEUE4_MIDCMD_DATA9 |
4598 | #define SDMA1_QUEUE4_MIDCMD_DATA9__DATA9__SHIFT 0x0 |
4599 | #define SDMA1_QUEUE4_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL |
4600 | //SDMA1_QUEUE4_MIDCMD_DATA10 |
4601 | #define SDMA1_QUEUE4_MIDCMD_DATA10__DATA10__SHIFT 0x0 |
4602 | #define SDMA1_QUEUE4_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL |
4603 | //SDMA1_QUEUE4_MIDCMD_CNTL |
4604 | #define SDMA1_QUEUE4_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 |
4605 | #define SDMA1_QUEUE4_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 |
4606 | #define SDMA1_QUEUE4_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 |
4607 | #define SDMA1_QUEUE4_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 |
4608 | #define SDMA1_QUEUE4_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L |
4609 | #define SDMA1_QUEUE4_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L |
4610 | #define SDMA1_QUEUE4_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L |
4611 | #define SDMA1_QUEUE4_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L |
4612 | //SDMA1_QUEUE5_RB_CNTL |
4613 | #define SDMA1_QUEUE5_RB_CNTL__RB_ENABLE__SHIFT 0x0 |
4614 | #define SDMA1_QUEUE5_RB_CNTL__RB_SIZE__SHIFT 0x1 |
4615 | #define SDMA1_QUEUE5_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 |
4616 | #define SDMA1_QUEUE5_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 |
4617 | #define SDMA1_QUEUE5_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa |
4618 | #define SDMA1_QUEUE5_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT 0xb |
4619 | #define SDMA1_QUEUE5_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc |
4620 | #define SDMA1_QUEUE5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd |
4621 | #define SDMA1_QUEUE5_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 |
4622 | #define SDMA1_QUEUE5_RB_CNTL__RB_PRIV__SHIFT 0x17 |
4623 | #define SDMA1_QUEUE5_RB_CNTL__RB_VMID__SHIFT 0x18 |
4624 | #define SDMA1_QUEUE5_RB_CNTL__RB_ENABLE_MASK 0x00000001L |
4625 | #define SDMA1_QUEUE5_RB_CNTL__RB_SIZE_MASK 0x0000003EL |
4626 | #define SDMA1_QUEUE5_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L |
4627 | #define SDMA1_QUEUE5_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L |
4628 | #define SDMA1_QUEUE5_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L |
4629 | #define SDMA1_QUEUE5_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK 0x00000800L |
4630 | #define SDMA1_QUEUE5_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L |
4631 | #define SDMA1_QUEUE5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L |
4632 | #define SDMA1_QUEUE5_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L |
4633 | #define SDMA1_QUEUE5_RB_CNTL__RB_PRIV_MASK 0x00800000L |
4634 | #define SDMA1_QUEUE5_RB_CNTL__RB_VMID_MASK 0x0F000000L |
4635 | //SDMA1_QUEUE5_RB_BASE |
4636 | #define SDMA1_QUEUE5_RB_BASE__ADDR__SHIFT 0x0 |
4637 | #define SDMA1_QUEUE5_RB_BASE__ADDR_MASK 0xFFFFFFFFL |
4638 | //SDMA1_QUEUE5_RB_BASE_HI |
4639 | #define SDMA1_QUEUE5_RB_BASE_HI__ADDR__SHIFT 0x0 |
4640 | #define SDMA1_QUEUE5_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL |
4641 | //SDMA1_QUEUE5_RB_RPTR |
4642 | #define SDMA1_QUEUE5_RB_RPTR__OFFSET__SHIFT 0x0 |
4643 | #define SDMA1_QUEUE5_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL |
4644 | //SDMA1_QUEUE5_RB_RPTR_HI |
4645 | #define SDMA1_QUEUE5_RB_RPTR_HI__OFFSET__SHIFT 0x0 |
4646 | #define SDMA1_QUEUE5_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
4647 | //SDMA1_QUEUE5_RB_WPTR |
4648 | #define SDMA1_QUEUE5_RB_WPTR__OFFSET__SHIFT 0x0 |
4649 | #define SDMA1_QUEUE5_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL |
4650 | //SDMA1_QUEUE5_RB_WPTR_HI |
4651 | #define SDMA1_QUEUE5_RB_WPTR_HI__OFFSET__SHIFT 0x0 |
4652 | #define SDMA1_QUEUE5_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
4653 | //SDMA1_QUEUE5_RB_RPTR_ADDR_HI |
4654 | #define SDMA1_QUEUE5_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 |
4655 | #define SDMA1_QUEUE5_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
4656 | //SDMA1_QUEUE5_RB_RPTR_ADDR_LO |
4657 | #define SDMA1_QUEUE5_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 |
4658 | #define SDMA1_QUEUE5_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
4659 | //SDMA1_QUEUE5_IB_CNTL |
4660 | #define SDMA1_QUEUE5_IB_CNTL__IB_ENABLE__SHIFT 0x0 |
4661 | #define SDMA1_QUEUE5_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 |
4662 | #define SDMA1_QUEUE5_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 |
4663 | #define SDMA1_QUEUE5_IB_CNTL__CMD_VMID__SHIFT 0x10 |
4664 | #define SDMA1_QUEUE5_IB_CNTL__IB_PRIV__SHIFT 0x1f |
4665 | #define SDMA1_QUEUE5_IB_CNTL__IB_ENABLE_MASK 0x00000001L |
4666 | #define SDMA1_QUEUE5_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L |
4667 | #define SDMA1_QUEUE5_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L |
4668 | #define SDMA1_QUEUE5_IB_CNTL__CMD_VMID_MASK 0x000F0000L |
4669 | #define SDMA1_QUEUE5_IB_CNTL__IB_PRIV_MASK 0x80000000L |
4670 | //SDMA1_QUEUE5_IB_RPTR |
4671 | #define SDMA1_QUEUE5_IB_RPTR__OFFSET__SHIFT 0x2 |
4672 | #define SDMA1_QUEUE5_IB_RPTR__OFFSET_MASK 0x003FFFFCL |
4673 | //SDMA1_QUEUE5_IB_OFFSET |
4674 | #define SDMA1_QUEUE5_IB_OFFSET__OFFSET__SHIFT 0x2 |
4675 | #define SDMA1_QUEUE5_IB_OFFSET__OFFSET_MASK 0x003FFFFCL |
4676 | //SDMA1_QUEUE5_IB_BASE_LO |
4677 | #define SDMA1_QUEUE5_IB_BASE_LO__ADDR__SHIFT 0x5 |
4678 | #define SDMA1_QUEUE5_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L |
4679 | //SDMA1_QUEUE5_IB_BASE_HI |
4680 | #define SDMA1_QUEUE5_IB_BASE_HI__ADDR__SHIFT 0x0 |
4681 | #define SDMA1_QUEUE5_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL |
4682 | //SDMA1_QUEUE5_IB_SIZE |
4683 | #define SDMA1_QUEUE5_IB_SIZE__SIZE__SHIFT 0x0 |
4684 | #define SDMA1_QUEUE5_IB_SIZE__SIZE_MASK 0x000FFFFFL |
4685 | //SDMA1_QUEUE5_SKIP_CNTL |
4686 | #define SDMA1_QUEUE5_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 |
4687 | #define SDMA1_QUEUE5_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL |
4688 | //SDMA1_QUEUE5_CONTEXT_STATUS |
4689 | #define SDMA1_QUEUE5_CONTEXT_STATUS__SELECTED__SHIFT 0x0 |
4690 | #define SDMA1_QUEUE5_CONTEXT_STATUS__IDLE__SHIFT 0x2 |
4691 | #define SDMA1_QUEUE5_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 |
4692 | #define SDMA1_QUEUE5_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 |
4693 | #define SDMA1_QUEUE5_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 |
4694 | #define SDMA1_QUEUE5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa |
4695 | #define SDMA1_QUEUE5_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb |
4696 | #define SDMA1_QUEUE5_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc |
4697 | #define SDMA1_QUEUE5_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 |
4698 | #define SDMA1_QUEUE5_CONTEXT_STATUS__SELECTED_MASK 0x00000001L |
4699 | #define SDMA1_QUEUE5_CONTEXT_STATUS__IDLE_MASK 0x00000004L |
4700 | #define SDMA1_QUEUE5_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L |
4701 | #define SDMA1_QUEUE5_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L |
4702 | #define SDMA1_QUEUE5_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L |
4703 | #define SDMA1_QUEUE5_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L |
4704 | #define SDMA1_QUEUE5_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L |
4705 | #define SDMA1_QUEUE5_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L |
4706 | #define SDMA1_QUEUE5_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L |
4707 | //SDMA1_QUEUE5_DOORBELL |
4708 | #define SDMA1_QUEUE5_DOORBELL__ENABLE__SHIFT 0x1c |
4709 | #define SDMA1_QUEUE5_DOORBELL__CAPTURED__SHIFT 0x1e |
4710 | #define SDMA1_QUEUE5_DOORBELL__ENABLE_MASK 0x10000000L |
4711 | #define SDMA1_QUEUE5_DOORBELL__CAPTURED_MASK 0x40000000L |
4712 | //SDMA1_QUEUE5_DOORBELL_LOG |
4713 | #define SDMA1_QUEUE5_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 |
4714 | #define SDMA1_QUEUE5_DOORBELL_LOG__DATA__SHIFT 0x2 |
4715 | #define SDMA1_QUEUE5_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L |
4716 | #define SDMA1_QUEUE5_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL |
4717 | //SDMA1_QUEUE5_DOORBELL_OFFSET |
4718 | #define SDMA1_QUEUE5_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 |
4719 | #define SDMA1_QUEUE5_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL |
4720 | //SDMA1_QUEUE5_CSA_ADDR_LO |
4721 | #define SDMA1_QUEUE5_CSA_ADDR_LO__ADDR__SHIFT 0x2 |
4722 | #define SDMA1_QUEUE5_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
4723 | //SDMA1_QUEUE5_CSA_ADDR_HI |
4724 | #define SDMA1_QUEUE5_CSA_ADDR_HI__ADDR__SHIFT 0x0 |
4725 | #define SDMA1_QUEUE5_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
4726 | //SDMA1_QUEUE5_SCHEDULE_CNTL |
4727 | #define SDMA1_QUEUE5_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 |
4728 | #define SDMA1_QUEUE5_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 |
4729 | #define SDMA1_QUEUE5_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 |
4730 | #define SDMA1_QUEUE5_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 |
4731 | #define SDMA1_QUEUE5_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L |
4732 | #define SDMA1_QUEUE5_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL |
4733 | #define SDMA1_QUEUE5_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L |
4734 | #define SDMA1_QUEUE5_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L |
4735 | //SDMA1_QUEUE5_IB_SUB_REMAIN |
4736 | #define SDMA1_QUEUE5_IB_SUB_REMAIN__SIZE__SHIFT 0x0 |
4737 | #define SDMA1_QUEUE5_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL |
4738 | //SDMA1_QUEUE5_PREEMPT |
4739 | #define SDMA1_QUEUE5_PREEMPT__IB_PREEMPT__SHIFT 0x0 |
4740 | #define SDMA1_QUEUE5_PREEMPT__IB_PREEMPT_MASK 0x00000001L |
4741 | //SDMA1_QUEUE5_DUMMY_REG |
4742 | #define SDMA1_QUEUE5_DUMMY_REG__DUMMY__SHIFT 0x0 |
4743 | #define SDMA1_QUEUE5_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL |
4744 | //SDMA1_QUEUE5_RB_WPTR_POLL_ADDR_HI |
4745 | #define SDMA1_QUEUE5_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 |
4746 | #define SDMA1_QUEUE5_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
4747 | //SDMA1_QUEUE5_RB_WPTR_POLL_ADDR_LO |
4748 | #define SDMA1_QUEUE5_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 |
4749 | #define SDMA1_QUEUE5_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
4750 | //SDMA1_QUEUE5_RB_AQL_CNTL |
4751 | #define SDMA1_QUEUE5_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 |
4752 | #define SDMA1_QUEUE5_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 |
4753 | #define SDMA1_QUEUE5_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 |
4754 | #define SDMA1_QUEUE5_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 |
4755 | #define SDMA1_QUEUE5_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 |
4756 | #define SDMA1_QUEUE5_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 |
4757 | #define SDMA1_QUEUE5_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L |
4758 | #define SDMA1_QUEUE5_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL |
4759 | #define SDMA1_QUEUE5_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L |
4760 | #define SDMA1_QUEUE5_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L |
4761 | #define SDMA1_QUEUE5_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L |
4762 | #define SDMA1_QUEUE5_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L |
4763 | //SDMA1_QUEUE5_MINOR_PTR_UPDATE |
4764 | #define SDMA1_QUEUE5_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 |
4765 | #define SDMA1_QUEUE5_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L |
4766 | //SDMA1_QUEUE5_RB_PREEMPT |
4767 | #define SDMA1_QUEUE5_RB_PREEMPT__PREEMPT_REQ__SHIFT 0x0 |
4768 | #define SDMA1_QUEUE5_RB_PREEMPT__PREEMPT_REQ_MASK 0x00000001L |
4769 | //SDMA1_QUEUE5_MIDCMD_DATA0 |
4770 | #define SDMA1_QUEUE5_MIDCMD_DATA0__DATA0__SHIFT 0x0 |
4771 | #define SDMA1_QUEUE5_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL |
4772 | //SDMA1_QUEUE5_MIDCMD_DATA1 |
4773 | #define SDMA1_QUEUE5_MIDCMD_DATA1__DATA1__SHIFT 0x0 |
4774 | #define SDMA1_QUEUE5_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL |
4775 | //SDMA1_QUEUE5_MIDCMD_DATA2 |
4776 | #define SDMA1_QUEUE5_MIDCMD_DATA2__DATA2__SHIFT 0x0 |
4777 | #define SDMA1_QUEUE5_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL |
4778 | //SDMA1_QUEUE5_MIDCMD_DATA3 |
4779 | #define SDMA1_QUEUE5_MIDCMD_DATA3__DATA3__SHIFT 0x0 |
4780 | #define SDMA1_QUEUE5_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL |
4781 | //SDMA1_QUEUE5_MIDCMD_DATA4 |
4782 | #define SDMA1_QUEUE5_MIDCMD_DATA4__DATA4__SHIFT 0x0 |
4783 | #define SDMA1_QUEUE5_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL |
4784 | //SDMA1_QUEUE5_MIDCMD_DATA5 |
4785 | #define SDMA1_QUEUE5_MIDCMD_DATA5__DATA5__SHIFT 0x0 |
4786 | #define SDMA1_QUEUE5_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL |
4787 | //SDMA1_QUEUE5_MIDCMD_DATA6 |
4788 | #define SDMA1_QUEUE5_MIDCMD_DATA6__DATA6__SHIFT 0x0 |
4789 | #define SDMA1_QUEUE5_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL |
4790 | //SDMA1_QUEUE5_MIDCMD_DATA7 |
4791 | #define SDMA1_QUEUE5_MIDCMD_DATA7__DATA7__SHIFT 0x0 |
4792 | #define SDMA1_QUEUE5_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL |
4793 | //SDMA1_QUEUE5_MIDCMD_DATA8 |
4794 | #define SDMA1_QUEUE5_MIDCMD_DATA8__DATA8__SHIFT 0x0 |
4795 | #define SDMA1_QUEUE5_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL |
4796 | //SDMA1_QUEUE5_MIDCMD_DATA9 |
4797 | #define SDMA1_QUEUE5_MIDCMD_DATA9__DATA9__SHIFT 0x0 |
4798 | #define SDMA1_QUEUE5_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL |
4799 | //SDMA1_QUEUE5_MIDCMD_DATA10 |
4800 | #define SDMA1_QUEUE5_MIDCMD_DATA10__DATA10__SHIFT 0x0 |
4801 | #define SDMA1_QUEUE5_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL |
4802 | //SDMA1_QUEUE5_MIDCMD_CNTL |
4803 | #define SDMA1_QUEUE5_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 |
4804 | #define SDMA1_QUEUE5_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 |
4805 | #define SDMA1_QUEUE5_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 |
4806 | #define SDMA1_QUEUE5_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 |
4807 | #define SDMA1_QUEUE5_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L |
4808 | #define SDMA1_QUEUE5_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L |
4809 | #define SDMA1_QUEUE5_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L |
4810 | #define SDMA1_QUEUE5_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L |
4811 | //SDMA1_QUEUE6_RB_CNTL |
4812 | #define SDMA1_QUEUE6_RB_CNTL__RB_ENABLE__SHIFT 0x0 |
4813 | #define SDMA1_QUEUE6_RB_CNTL__RB_SIZE__SHIFT 0x1 |
4814 | #define SDMA1_QUEUE6_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 |
4815 | #define SDMA1_QUEUE6_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 |
4816 | #define SDMA1_QUEUE6_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa |
4817 | #define SDMA1_QUEUE6_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT 0xb |
4818 | #define SDMA1_QUEUE6_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc |
4819 | #define SDMA1_QUEUE6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd |
4820 | #define SDMA1_QUEUE6_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 |
4821 | #define SDMA1_QUEUE6_RB_CNTL__RB_PRIV__SHIFT 0x17 |
4822 | #define SDMA1_QUEUE6_RB_CNTL__RB_VMID__SHIFT 0x18 |
4823 | #define SDMA1_QUEUE6_RB_CNTL__RB_ENABLE_MASK 0x00000001L |
4824 | #define SDMA1_QUEUE6_RB_CNTL__RB_SIZE_MASK 0x0000003EL |
4825 | #define SDMA1_QUEUE6_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L |
4826 | #define SDMA1_QUEUE6_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L |
4827 | #define SDMA1_QUEUE6_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L |
4828 | #define SDMA1_QUEUE6_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK 0x00000800L |
4829 | #define SDMA1_QUEUE6_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L |
4830 | #define SDMA1_QUEUE6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L |
4831 | #define SDMA1_QUEUE6_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L |
4832 | #define SDMA1_QUEUE6_RB_CNTL__RB_PRIV_MASK 0x00800000L |
4833 | #define SDMA1_QUEUE6_RB_CNTL__RB_VMID_MASK 0x0F000000L |
4834 | //SDMA1_QUEUE6_RB_BASE |
4835 | #define SDMA1_QUEUE6_RB_BASE__ADDR__SHIFT 0x0 |
4836 | #define SDMA1_QUEUE6_RB_BASE__ADDR_MASK 0xFFFFFFFFL |
4837 | //SDMA1_QUEUE6_RB_BASE_HI |
4838 | #define SDMA1_QUEUE6_RB_BASE_HI__ADDR__SHIFT 0x0 |
4839 | #define SDMA1_QUEUE6_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL |
4840 | //SDMA1_QUEUE6_RB_RPTR |
4841 | #define SDMA1_QUEUE6_RB_RPTR__OFFSET__SHIFT 0x0 |
4842 | #define SDMA1_QUEUE6_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL |
4843 | //SDMA1_QUEUE6_RB_RPTR_HI |
4844 | #define SDMA1_QUEUE6_RB_RPTR_HI__OFFSET__SHIFT 0x0 |
4845 | #define SDMA1_QUEUE6_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
4846 | //SDMA1_QUEUE6_RB_WPTR |
4847 | #define SDMA1_QUEUE6_RB_WPTR__OFFSET__SHIFT 0x0 |
4848 | #define SDMA1_QUEUE6_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL |
4849 | //SDMA1_QUEUE6_RB_WPTR_HI |
4850 | #define SDMA1_QUEUE6_RB_WPTR_HI__OFFSET__SHIFT 0x0 |
4851 | #define SDMA1_QUEUE6_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
4852 | //SDMA1_QUEUE6_RB_RPTR_ADDR_HI |
4853 | #define SDMA1_QUEUE6_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 |
4854 | #define SDMA1_QUEUE6_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
4855 | //SDMA1_QUEUE6_RB_RPTR_ADDR_LO |
4856 | #define SDMA1_QUEUE6_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 |
4857 | #define SDMA1_QUEUE6_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
4858 | //SDMA1_QUEUE6_IB_CNTL |
4859 | #define SDMA1_QUEUE6_IB_CNTL__IB_ENABLE__SHIFT 0x0 |
4860 | #define SDMA1_QUEUE6_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 |
4861 | #define SDMA1_QUEUE6_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 |
4862 | #define SDMA1_QUEUE6_IB_CNTL__CMD_VMID__SHIFT 0x10 |
4863 | #define SDMA1_QUEUE6_IB_CNTL__IB_PRIV__SHIFT 0x1f |
4864 | #define SDMA1_QUEUE6_IB_CNTL__IB_ENABLE_MASK 0x00000001L |
4865 | #define SDMA1_QUEUE6_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L |
4866 | #define SDMA1_QUEUE6_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L |
4867 | #define SDMA1_QUEUE6_IB_CNTL__CMD_VMID_MASK 0x000F0000L |
4868 | #define SDMA1_QUEUE6_IB_CNTL__IB_PRIV_MASK 0x80000000L |
4869 | //SDMA1_QUEUE6_IB_RPTR |
4870 | #define SDMA1_QUEUE6_IB_RPTR__OFFSET__SHIFT 0x2 |
4871 | #define SDMA1_QUEUE6_IB_RPTR__OFFSET_MASK 0x003FFFFCL |
4872 | //SDMA1_QUEUE6_IB_OFFSET |
4873 | #define SDMA1_QUEUE6_IB_OFFSET__OFFSET__SHIFT 0x2 |
4874 | #define SDMA1_QUEUE6_IB_OFFSET__OFFSET_MASK 0x003FFFFCL |
4875 | //SDMA1_QUEUE6_IB_BASE_LO |
4876 | #define SDMA1_QUEUE6_IB_BASE_LO__ADDR__SHIFT 0x5 |
4877 | #define SDMA1_QUEUE6_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L |
4878 | //SDMA1_QUEUE6_IB_BASE_HI |
4879 | #define SDMA1_QUEUE6_IB_BASE_HI__ADDR__SHIFT 0x0 |
4880 | #define SDMA1_QUEUE6_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL |
4881 | //SDMA1_QUEUE6_IB_SIZE |
4882 | #define SDMA1_QUEUE6_IB_SIZE__SIZE__SHIFT 0x0 |
4883 | #define SDMA1_QUEUE6_IB_SIZE__SIZE_MASK 0x000FFFFFL |
4884 | //SDMA1_QUEUE6_SKIP_CNTL |
4885 | #define SDMA1_QUEUE6_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 |
4886 | #define SDMA1_QUEUE6_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL |
4887 | //SDMA1_QUEUE6_CONTEXT_STATUS |
4888 | #define SDMA1_QUEUE6_CONTEXT_STATUS__SELECTED__SHIFT 0x0 |
4889 | #define SDMA1_QUEUE6_CONTEXT_STATUS__IDLE__SHIFT 0x2 |
4890 | #define SDMA1_QUEUE6_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 |
4891 | #define SDMA1_QUEUE6_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 |
4892 | #define SDMA1_QUEUE6_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 |
4893 | #define SDMA1_QUEUE6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa |
4894 | #define SDMA1_QUEUE6_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb |
4895 | #define SDMA1_QUEUE6_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc |
4896 | #define SDMA1_QUEUE6_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 |
4897 | #define SDMA1_QUEUE6_CONTEXT_STATUS__SELECTED_MASK 0x00000001L |
4898 | #define SDMA1_QUEUE6_CONTEXT_STATUS__IDLE_MASK 0x00000004L |
4899 | #define SDMA1_QUEUE6_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L |
4900 | #define SDMA1_QUEUE6_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L |
4901 | #define SDMA1_QUEUE6_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L |
4902 | #define SDMA1_QUEUE6_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L |
4903 | #define SDMA1_QUEUE6_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L |
4904 | #define SDMA1_QUEUE6_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L |
4905 | #define SDMA1_QUEUE6_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L |
4906 | //SDMA1_QUEUE6_DOORBELL |
4907 | #define SDMA1_QUEUE6_DOORBELL__ENABLE__SHIFT 0x1c |
4908 | #define SDMA1_QUEUE6_DOORBELL__CAPTURED__SHIFT 0x1e |
4909 | #define SDMA1_QUEUE6_DOORBELL__ENABLE_MASK 0x10000000L |
4910 | #define SDMA1_QUEUE6_DOORBELL__CAPTURED_MASK 0x40000000L |
4911 | //SDMA1_QUEUE6_DOORBELL_LOG |
4912 | #define SDMA1_QUEUE6_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 |
4913 | #define SDMA1_QUEUE6_DOORBELL_LOG__DATA__SHIFT 0x2 |
4914 | #define SDMA1_QUEUE6_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L |
4915 | #define SDMA1_QUEUE6_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL |
4916 | //SDMA1_QUEUE6_DOORBELL_OFFSET |
4917 | #define SDMA1_QUEUE6_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 |
4918 | #define SDMA1_QUEUE6_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL |
4919 | //SDMA1_QUEUE6_CSA_ADDR_LO |
4920 | #define SDMA1_QUEUE6_CSA_ADDR_LO__ADDR__SHIFT 0x2 |
4921 | #define SDMA1_QUEUE6_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
4922 | //SDMA1_QUEUE6_CSA_ADDR_HI |
4923 | #define SDMA1_QUEUE6_CSA_ADDR_HI__ADDR__SHIFT 0x0 |
4924 | #define SDMA1_QUEUE6_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
4925 | //SDMA1_QUEUE6_SCHEDULE_CNTL |
4926 | #define SDMA1_QUEUE6_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 |
4927 | #define SDMA1_QUEUE6_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 |
4928 | #define SDMA1_QUEUE6_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 |
4929 | #define SDMA1_QUEUE6_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 |
4930 | #define SDMA1_QUEUE6_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L |
4931 | #define SDMA1_QUEUE6_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL |
4932 | #define SDMA1_QUEUE6_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L |
4933 | #define SDMA1_QUEUE6_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L |
4934 | //SDMA1_QUEUE6_IB_SUB_REMAIN |
4935 | #define SDMA1_QUEUE6_IB_SUB_REMAIN__SIZE__SHIFT 0x0 |
4936 | #define SDMA1_QUEUE6_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL |
4937 | //SDMA1_QUEUE6_PREEMPT |
4938 | #define SDMA1_QUEUE6_PREEMPT__IB_PREEMPT__SHIFT 0x0 |
4939 | #define SDMA1_QUEUE6_PREEMPT__IB_PREEMPT_MASK 0x00000001L |
4940 | //SDMA1_QUEUE6_DUMMY_REG |
4941 | #define SDMA1_QUEUE6_DUMMY_REG__DUMMY__SHIFT 0x0 |
4942 | #define SDMA1_QUEUE6_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL |
4943 | //SDMA1_QUEUE6_RB_WPTR_POLL_ADDR_HI |
4944 | #define SDMA1_QUEUE6_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 |
4945 | #define SDMA1_QUEUE6_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
4946 | //SDMA1_QUEUE6_RB_WPTR_POLL_ADDR_LO |
4947 | #define SDMA1_QUEUE6_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 |
4948 | #define SDMA1_QUEUE6_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
4949 | //SDMA1_QUEUE6_RB_AQL_CNTL |
4950 | #define SDMA1_QUEUE6_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 |
4951 | #define SDMA1_QUEUE6_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 |
4952 | #define SDMA1_QUEUE6_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 |
4953 | #define SDMA1_QUEUE6_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 |
4954 | #define SDMA1_QUEUE6_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 |
4955 | #define SDMA1_QUEUE6_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 |
4956 | #define SDMA1_QUEUE6_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L |
4957 | #define SDMA1_QUEUE6_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL |
4958 | #define SDMA1_QUEUE6_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L |
4959 | #define SDMA1_QUEUE6_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L |
4960 | #define SDMA1_QUEUE6_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L |
4961 | #define SDMA1_QUEUE6_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L |
4962 | //SDMA1_QUEUE6_MINOR_PTR_UPDATE |
4963 | #define SDMA1_QUEUE6_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 |
4964 | #define SDMA1_QUEUE6_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L |
4965 | //SDMA1_QUEUE6_RB_PREEMPT |
4966 | #define SDMA1_QUEUE6_RB_PREEMPT__PREEMPT_REQ__SHIFT 0x0 |
4967 | #define SDMA1_QUEUE6_RB_PREEMPT__PREEMPT_REQ_MASK 0x00000001L |
4968 | //SDMA1_QUEUE6_MIDCMD_DATA0 |
4969 | #define SDMA1_QUEUE6_MIDCMD_DATA0__DATA0__SHIFT 0x0 |
4970 | #define SDMA1_QUEUE6_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL |
4971 | //SDMA1_QUEUE6_MIDCMD_DATA1 |
4972 | #define SDMA1_QUEUE6_MIDCMD_DATA1__DATA1__SHIFT 0x0 |
4973 | #define SDMA1_QUEUE6_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL |
4974 | //SDMA1_QUEUE6_MIDCMD_DATA2 |
4975 | #define SDMA1_QUEUE6_MIDCMD_DATA2__DATA2__SHIFT 0x0 |
4976 | #define SDMA1_QUEUE6_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL |
4977 | //SDMA1_QUEUE6_MIDCMD_DATA3 |
4978 | #define SDMA1_QUEUE6_MIDCMD_DATA3__DATA3__SHIFT 0x0 |
4979 | #define SDMA1_QUEUE6_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL |
4980 | //SDMA1_QUEUE6_MIDCMD_DATA4 |
4981 | #define SDMA1_QUEUE6_MIDCMD_DATA4__DATA4__SHIFT 0x0 |
4982 | #define SDMA1_QUEUE6_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL |
4983 | //SDMA1_QUEUE6_MIDCMD_DATA5 |
4984 | #define SDMA1_QUEUE6_MIDCMD_DATA5__DATA5__SHIFT 0x0 |
4985 | #define SDMA1_QUEUE6_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL |
4986 | //SDMA1_QUEUE6_MIDCMD_DATA6 |
4987 | #define SDMA1_QUEUE6_MIDCMD_DATA6__DATA6__SHIFT 0x0 |
4988 | #define SDMA1_QUEUE6_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL |
4989 | //SDMA1_QUEUE6_MIDCMD_DATA7 |
4990 | #define SDMA1_QUEUE6_MIDCMD_DATA7__DATA7__SHIFT 0x0 |
4991 | #define SDMA1_QUEUE6_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL |
4992 | //SDMA1_QUEUE6_MIDCMD_DATA8 |
4993 | #define SDMA1_QUEUE6_MIDCMD_DATA8__DATA8__SHIFT 0x0 |
4994 | #define SDMA1_QUEUE6_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL |
4995 | //SDMA1_QUEUE6_MIDCMD_DATA9 |
4996 | #define SDMA1_QUEUE6_MIDCMD_DATA9__DATA9__SHIFT 0x0 |
4997 | #define SDMA1_QUEUE6_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL |
4998 | //SDMA1_QUEUE6_MIDCMD_DATA10 |
4999 | #define SDMA1_QUEUE6_MIDCMD_DATA10__DATA10__SHIFT 0x0 |
5000 | #define SDMA1_QUEUE6_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL |
5001 | //SDMA1_QUEUE6_MIDCMD_CNTL |
5002 | #define SDMA1_QUEUE6_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 |
5003 | #define SDMA1_QUEUE6_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 |
5004 | #define SDMA1_QUEUE6_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 |
5005 | #define SDMA1_QUEUE6_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 |
5006 | #define SDMA1_QUEUE6_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L |
5007 | #define SDMA1_QUEUE6_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L |
5008 | #define SDMA1_QUEUE6_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L |
5009 | #define SDMA1_QUEUE6_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L |
5010 | //SDMA1_QUEUE7_RB_CNTL |
5011 | #define SDMA1_QUEUE7_RB_CNTL__RB_ENABLE__SHIFT 0x0 |
5012 | #define SDMA1_QUEUE7_RB_CNTL__RB_SIZE__SHIFT 0x1 |
5013 | #define SDMA1_QUEUE7_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 |
5014 | #define SDMA1_QUEUE7_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 |
5015 | #define SDMA1_QUEUE7_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa |
5016 | #define SDMA1_QUEUE7_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT 0xb |
5017 | #define SDMA1_QUEUE7_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc |
5018 | #define SDMA1_QUEUE7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd |
5019 | #define SDMA1_QUEUE7_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 |
5020 | #define SDMA1_QUEUE7_RB_CNTL__RB_PRIV__SHIFT 0x17 |
5021 | #define SDMA1_QUEUE7_RB_CNTL__RB_VMID__SHIFT 0x18 |
5022 | #define SDMA1_QUEUE7_RB_CNTL__RB_ENABLE_MASK 0x00000001L |
5023 | #define SDMA1_QUEUE7_RB_CNTL__RB_SIZE_MASK 0x0000003EL |
5024 | #define SDMA1_QUEUE7_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L |
5025 | #define SDMA1_QUEUE7_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L |
5026 | #define SDMA1_QUEUE7_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L |
5027 | #define SDMA1_QUEUE7_RB_CNTL__F32_WPTR_POLL_ENABLE_MASK 0x00000800L |
5028 | #define SDMA1_QUEUE7_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L |
5029 | #define SDMA1_QUEUE7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L |
5030 | #define SDMA1_QUEUE7_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L |
5031 | #define SDMA1_QUEUE7_RB_CNTL__RB_PRIV_MASK 0x00800000L |
5032 | #define SDMA1_QUEUE7_RB_CNTL__RB_VMID_MASK 0x0F000000L |
5033 | //SDMA1_QUEUE7_RB_BASE |
5034 | #define SDMA1_QUEUE7_RB_BASE__ADDR__SHIFT 0x0 |
5035 | #define SDMA1_QUEUE7_RB_BASE__ADDR_MASK 0xFFFFFFFFL |
5036 | //SDMA1_QUEUE7_RB_BASE_HI |
5037 | #define SDMA1_QUEUE7_RB_BASE_HI__ADDR__SHIFT 0x0 |
5038 | #define SDMA1_QUEUE7_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL |
5039 | //SDMA1_QUEUE7_RB_RPTR |
5040 | #define SDMA1_QUEUE7_RB_RPTR__OFFSET__SHIFT 0x0 |
5041 | #define SDMA1_QUEUE7_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL |
5042 | //SDMA1_QUEUE7_RB_RPTR_HI |
5043 | #define SDMA1_QUEUE7_RB_RPTR_HI__OFFSET__SHIFT 0x0 |
5044 | #define SDMA1_QUEUE7_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
5045 | //SDMA1_QUEUE7_RB_WPTR |
5046 | #define SDMA1_QUEUE7_RB_WPTR__OFFSET__SHIFT 0x0 |
5047 | #define SDMA1_QUEUE7_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL |
5048 | //SDMA1_QUEUE7_RB_WPTR_HI |
5049 | #define SDMA1_QUEUE7_RB_WPTR_HI__OFFSET__SHIFT 0x0 |
5050 | #define SDMA1_QUEUE7_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL |
5051 | //SDMA1_QUEUE7_RB_RPTR_ADDR_HI |
5052 | #define SDMA1_QUEUE7_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 |
5053 | #define SDMA1_QUEUE7_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
5054 | //SDMA1_QUEUE7_RB_RPTR_ADDR_LO |
5055 | #define SDMA1_QUEUE7_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 |
5056 | #define SDMA1_QUEUE7_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
5057 | //SDMA1_QUEUE7_IB_CNTL |
5058 | #define SDMA1_QUEUE7_IB_CNTL__IB_ENABLE__SHIFT 0x0 |
5059 | #define SDMA1_QUEUE7_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 |
5060 | #define SDMA1_QUEUE7_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 |
5061 | #define SDMA1_QUEUE7_IB_CNTL__CMD_VMID__SHIFT 0x10 |
5062 | #define SDMA1_QUEUE7_IB_CNTL__IB_PRIV__SHIFT 0x1f |
5063 | #define SDMA1_QUEUE7_IB_CNTL__IB_ENABLE_MASK 0x00000001L |
5064 | #define SDMA1_QUEUE7_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L |
5065 | #define SDMA1_QUEUE7_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L |
5066 | #define SDMA1_QUEUE7_IB_CNTL__CMD_VMID_MASK 0x000F0000L |
5067 | #define SDMA1_QUEUE7_IB_CNTL__IB_PRIV_MASK 0x80000000L |
5068 | //SDMA1_QUEUE7_IB_RPTR |
5069 | #define SDMA1_QUEUE7_IB_RPTR__OFFSET__SHIFT 0x2 |
5070 | #define SDMA1_QUEUE7_IB_RPTR__OFFSET_MASK 0x003FFFFCL |
5071 | //SDMA1_QUEUE7_IB_OFFSET |
5072 | #define SDMA1_QUEUE7_IB_OFFSET__OFFSET__SHIFT 0x2 |
5073 | #define SDMA1_QUEUE7_IB_OFFSET__OFFSET_MASK 0x003FFFFCL |
5074 | //SDMA1_QUEUE7_IB_BASE_LO |
5075 | #define SDMA1_QUEUE7_IB_BASE_LO__ADDR__SHIFT 0x5 |
5076 | #define SDMA1_QUEUE7_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L |
5077 | //SDMA1_QUEUE7_IB_BASE_HI |
5078 | #define SDMA1_QUEUE7_IB_BASE_HI__ADDR__SHIFT 0x0 |
5079 | #define SDMA1_QUEUE7_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL |
5080 | //SDMA1_QUEUE7_IB_SIZE |
5081 | #define SDMA1_QUEUE7_IB_SIZE__SIZE__SHIFT 0x0 |
5082 | #define SDMA1_QUEUE7_IB_SIZE__SIZE_MASK 0x000FFFFFL |
5083 | //SDMA1_QUEUE7_SKIP_CNTL |
5084 | #define SDMA1_QUEUE7_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 |
5085 | #define SDMA1_QUEUE7_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL |
5086 | //SDMA1_QUEUE7_CONTEXT_STATUS |
5087 | #define SDMA1_QUEUE7_CONTEXT_STATUS__SELECTED__SHIFT 0x0 |
5088 | #define SDMA1_QUEUE7_CONTEXT_STATUS__IDLE__SHIFT 0x2 |
5089 | #define SDMA1_QUEUE7_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 |
5090 | #define SDMA1_QUEUE7_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 |
5091 | #define SDMA1_QUEUE7_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 |
5092 | #define SDMA1_QUEUE7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa |
5093 | #define SDMA1_QUEUE7_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb |
5094 | #define SDMA1_QUEUE7_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc |
5095 | #define SDMA1_QUEUE7_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 |
5096 | #define SDMA1_QUEUE7_CONTEXT_STATUS__SELECTED_MASK 0x00000001L |
5097 | #define SDMA1_QUEUE7_CONTEXT_STATUS__IDLE_MASK 0x00000004L |
5098 | #define SDMA1_QUEUE7_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L |
5099 | #define SDMA1_QUEUE7_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L |
5100 | #define SDMA1_QUEUE7_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L |
5101 | #define SDMA1_QUEUE7_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L |
5102 | #define SDMA1_QUEUE7_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L |
5103 | #define SDMA1_QUEUE7_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L |
5104 | #define SDMA1_QUEUE7_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L |
5105 | //SDMA1_QUEUE7_DOORBELL |
5106 | #define SDMA1_QUEUE7_DOORBELL__ENABLE__SHIFT 0x1c |
5107 | #define SDMA1_QUEUE7_DOORBELL__CAPTURED__SHIFT 0x1e |
5108 | #define SDMA1_QUEUE7_DOORBELL__ENABLE_MASK 0x10000000L |
5109 | #define SDMA1_QUEUE7_DOORBELL__CAPTURED_MASK 0x40000000L |
5110 | //SDMA1_QUEUE7_DOORBELL_LOG |
5111 | #define SDMA1_QUEUE7_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 |
5112 | #define SDMA1_QUEUE7_DOORBELL_LOG__DATA__SHIFT 0x2 |
5113 | #define SDMA1_QUEUE7_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L |
5114 | #define SDMA1_QUEUE7_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL |
5115 | //SDMA1_QUEUE7_DOORBELL_OFFSET |
5116 | #define SDMA1_QUEUE7_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 |
5117 | #define SDMA1_QUEUE7_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL |
5118 | //SDMA1_QUEUE7_CSA_ADDR_LO |
5119 | #define SDMA1_QUEUE7_CSA_ADDR_LO__ADDR__SHIFT 0x2 |
5120 | #define SDMA1_QUEUE7_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
5121 | //SDMA1_QUEUE7_CSA_ADDR_HI |
5122 | #define SDMA1_QUEUE7_CSA_ADDR_HI__ADDR__SHIFT 0x0 |
5123 | #define SDMA1_QUEUE7_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
5124 | //SDMA1_QUEUE7_SCHEDULE_CNTL |
5125 | #define SDMA1_QUEUE7_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 |
5126 | #define SDMA1_QUEUE7_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 |
5127 | #define SDMA1_QUEUE7_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 |
5128 | #define SDMA1_QUEUE7_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 |
5129 | #define SDMA1_QUEUE7_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L |
5130 | #define SDMA1_QUEUE7_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL |
5131 | #define SDMA1_QUEUE7_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L |
5132 | #define SDMA1_QUEUE7_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L |
5133 | //SDMA1_QUEUE7_IB_SUB_REMAIN |
5134 | #define SDMA1_QUEUE7_IB_SUB_REMAIN__SIZE__SHIFT 0x0 |
5135 | #define SDMA1_QUEUE7_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL |
5136 | //SDMA1_QUEUE7_PREEMPT |
5137 | #define SDMA1_QUEUE7_PREEMPT__IB_PREEMPT__SHIFT 0x0 |
5138 | #define SDMA1_QUEUE7_PREEMPT__IB_PREEMPT_MASK 0x00000001L |
5139 | //SDMA1_QUEUE7_DUMMY_REG |
5140 | #define SDMA1_QUEUE7_DUMMY_REG__DUMMY__SHIFT 0x0 |
5141 | #define SDMA1_QUEUE7_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL |
5142 | //SDMA1_QUEUE7_RB_WPTR_POLL_ADDR_HI |
5143 | #define SDMA1_QUEUE7_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 |
5144 | #define SDMA1_QUEUE7_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL |
5145 | //SDMA1_QUEUE7_RB_WPTR_POLL_ADDR_LO |
5146 | #define SDMA1_QUEUE7_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 |
5147 | #define SDMA1_QUEUE7_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL |
5148 | //SDMA1_QUEUE7_RB_AQL_CNTL |
5149 | #define SDMA1_QUEUE7_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 |
5150 | #define SDMA1_QUEUE7_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 |
5151 | #define SDMA1_QUEUE7_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 |
5152 | #define SDMA1_QUEUE7_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 |
5153 | #define SDMA1_QUEUE7_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 |
5154 | #define SDMA1_QUEUE7_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 |
5155 | #define SDMA1_QUEUE7_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L |
5156 | #define SDMA1_QUEUE7_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL |
5157 | #define SDMA1_QUEUE7_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L |
5158 | #define SDMA1_QUEUE7_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L |
5159 | #define SDMA1_QUEUE7_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L |
5160 | #define SDMA1_QUEUE7_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L |
5161 | //SDMA1_QUEUE7_MINOR_PTR_UPDATE |
5162 | #define SDMA1_QUEUE7_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 |
5163 | #define SDMA1_QUEUE7_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L |
5164 | //SDMA1_QUEUE7_RB_PREEMPT |
5165 | #define SDMA1_QUEUE7_RB_PREEMPT__PREEMPT_REQ__SHIFT 0x0 |
5166 | #define SDMA1_QUEUE7_RB_PREEMPT__PREEMPT_REQ_MASK 0x00000001L |
5167 | //SDMA1_QUEUE7_MIDCMD_DATA0 |
5168 | #define SDMA1_QUEUE7_MIDCMD_DATA0__DATA0__SHIFT 0x0 |
5169 | #define SDMA1_QUEUE7_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL |
5170 | //SDMA1_QUEUE7_MIDCMD_DATA1 |
5171 | #define SDMA1_QUEUE7_MIDCMD_DATA1__DATA1__SHIFT 0x0 |
5172 | #define SDMA1_QUEUE7_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL |
5173 | //SDMA1_QUEUE7_MIDCMD_DATA2 |
5174 | #define SDMA1_QUEUE7_MIDCMD_DATA2__DATA2__SHIFT 0x0 |
5175 | #define SDMA1_QUEUE7_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL |
5176 | //SDMA1_QUEUE7_MIDCMD_DATA3 |
5177 | #define SDMA1_QUEUE7_MIDCMD_DATA3__DATA3__SHIFT 0x0 |
5178 | #define SDMA1_QUEUE7_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL |
5179 | //SDMA1_QUEUE7_MIDCMD_DATA4 |
5180 | #define SDMA1_QUEUE7_MIDCMD_DATA4__DATA4__SHIFT 0x0 |
5181 | #define SDMA1_QUEUE7_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL |
5182 | //SDMA1_QUEUE7_MIDCMD_DATA5 |
5183 | #define SDMA1_QUEUE7_MIDCMD_DATA5__DATA5__SHIFT 0x0 |
5184 | #define SDMA1_QUEUE7_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL |
5185 | //SDMA1_QUEUE7_MIDCMD_DATA6 |
5186 | #define SDMA1_QUEUE7_MIDCMD_DATA6__DATA6__SHIFT 0x0 |
5187 | #define SDMA1_QUEUE7_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL |
5188 | //SDMA1_QUEUE7_MIDCMD_DATA7 |
5189 | #define SDMA1_QUEUE7_MIDCMD_DATA7__DATA7__SHIFT 0x0 |
5190 | #define SDMA1_QUEUE7_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL |
5191 | //SDMA1_QUEUE7_MIDCMD_DATA8 |
5192 | #define SDMA1_QUEUE7_MIDCMD_DATA8__DATA8__SHIFT 0x0 |
5193 | #define SDMA1_QUEUE7_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL |
5194 | //SDMA1_QUEUE7_MIDCMD_DATA9 |
5195 | #define SDMA1_QUEUE7_MIDCMD_DATA9__DATA9__SHIFT 0x0 |
5196 | #define SDMA1_QUEUE7_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL |
5197 | //SDMA1_QUEUE7_MIDCMD_DATA10 |
5198 | #define SDMA1_QUEUE7_MIDCMD_DATA10__DATA10__SHIFT 0x0 |
5199 | #define SDMA1_QUEUE7_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL |
5200 | //SDMA1_QUEUE7_MIDCMD_CNTL |
5201 | #define SDMA1_QUEUE7_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 |
5202 | #define SDMA1_QUEUE7_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 |
5203 | #define SDMA1_QUEUE7_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 |
5204 | #define SDMA1_QUEUE7_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 |
5205 | #define SDMA1_QUEUE7_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L |
5206 | #define SDMA1_QUEUE7_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L |
5207 | #define SDMA1_QUEUE7_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L |
5208 | #define SDMA1_QUEUE7_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L |
5209 | |
5210 | |
5211 | // addressBlock: gc_sdma0_sdma0hypdec |
5212 | //SDMA0_UCODE_ADDR |
5213 | #define SDMA0_UCODE_ADDR__VALUE__SHIFT 0x0 |
5214 | #define SDMA0_UCODE_ADDR__THID__SHIFT 0xf |
5215 | #define SDMA0_UCODE_ADDR__VALUE_MASK 0x00001FFFL |
5216 | #define SDMA0_UCODE_ADDR__THID_MASK 0x00008000L |
5217 | //SDMA0_UCODE_DATA |
5218 | #define SDMA0_UCODE_DATA__VALUE__SHIFT 0x0 |
5219 | #define SDMA0_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL |
5220 | //SDMA0_UCODE_SELFLOAD_CONTROL |
5221 | #define SDMA0_UCODE_SELFLOAD_CONTROL__GPA__SHIFT 0x0 |
5222 | #define SDMA0_UCODE_SELFLOAD_CONTROL__SYS__SHIFT 0x1 |
5223 | #define SDMA0_UCODE_SELFLOAD_CONTROL__CID__SHIFT 0x4 |
5224 | #define SDMA0_UCODE_SELFLOAD_CONTROL__CACHE_POLICY__SHIFT 0x8 |
5225 | #define SDMA0_UCODE_SELFLOAD_CONTROL__GPA_MASK 0x00000001L |
5226 | #define SDMA0_UCODE_SELFLOAD_CONTROL__SYS_MASK 0x00000002L |
5227 | #define SDMA0_UCODE_SELFLOAD_CONTROL__CID_MASK 0x000000F0L |
5228 | #define SDMA0_UCODE_SELFLOAD_CONTROL__CACHE_POLICY_MASK 0x00000300L |
5229 | //SDMA0_BROADCAST_UCODE_ADDR |
5230 | #define SDMA0_BROADCAST_UCODE_ADDR__VALUE__SHIFT 0x0 |
5231 | #define SDMA0_BROADCAST_UCODE_ADDR__THID__SHIFT 0xf |
5232 | #define SDMA0_BROADCAST_UCODE_ADDR__VALUE_MASK 0x00001FFFL |
5233 | #define SDMA0_BROADCAST_UCODE_ADDR__THID_MASK 0x00008000L |
5234 | //SDMA0_BROADCAST_UCODE_DATA |
5235 | #define SDMA0_BROADCAST_UCODE_DATA__VALUE__SHIFT 0x0 |
5236 | #define SDMA0_BROADCAST_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL |
5237 | //SDMA0_VM_CTX_LO |
5238 | #define SDMA0_VM_CTX_LO__ADDR__SHIFT 0x2 |
5239 | #define SDMA0_VM_CTX_LO__ADDR_MASK 0xFFFFFFFCL |
5240 | //SDMA0_VM_CTX_HI |
5241 | #define SDMA0_VM_CTX_HI__ADDR__SHIFT 0x0 |
5242 | #define SDMA0_VM_CTX_HI__ADDR_MASK 0xFFFFFFFFL |
5243 | //SDMA0_ACTIVE_FCN_ID |
5244 | #define SDMA0_ACTIVE_FCN_ID__VFID__SHIFT 0x0 |
5245 | #define SDMA0_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4 |
5246 | #define SDMA0_ACTIVE_FCN_ID__VF__SHIFT 0x1f |
5247 | #define SDMA0_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL |
5248 | #define SDMA0_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFF0L |
5249 | #define SDMA0_ACTIVE_FCN_ID__VF_MASK 0x80000000L |
5250 | //SDMA0_VM_CTX_CNTL |
5251 | #define SDMA0_VM_CTX_CNTL__PRIV__SHIFT 0x0 |
5252 | #define SDMA0_VM_CTX_CNTL__VMID__SHIFT 0x4 |
5253 | #define SDMA0_VM_CTX_CNTL__MEM_PHY__SHIFT 0x8 |
5254 | #define SDMA0_VM_CTX_CNTL__BUSY_STATUS_REPORT_ENABLE__SHIFT 0x10 |
5255 | #define SDMA0_VM_CTX_CNTL__PRIV_MASK 0x00000001L |
5256 | #define SDMA0_VM_CTX_CNTL__VMID_MASK 0x000000F0L |
5257 | #define SDMA0_VM_CTX_CNTL__MEM_PHY_MASK 0x00000300L |
5258 | #define SDMA0_VM_CTX_CNTL__BUSY_STATUS_REPORT_ENABLE_MASK 0x00010000L |
5259 | //SDMA0_VIRT_RESET_REQ |
5260 | #define SDMA0_VIRT_RESET_REQ__VF__SHIFT 0x0 |
5261 | #define SDMA0_VIRT_RESET_REQ__PF__SHIFT 0x1f |
5262 | #define SDMA0_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL |
5263 | #define SDMA0_VIRT_RESET_REQ__PF_MASK 0x80000000L |
5264 | //SDMA0_CONTEXT_REG_TYPE0 |
5265 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_QUEUE0_RB_CNTL__SHIFT 0x0 |
5266 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_QUEUE0_RB_BASE__SHIFT 0x1 |
5267 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_QUEUE0_RB_BASE_HI__SHIFT 0x2 |
5268 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_QUEUE0_RB_RPTR__SHIFT 0x3 |
5269 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_QUEUE0_RB_RPTR_HI__SHIFT 0x4 |
5270 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_QUEUE0_RB_WPTR__SHIFT 0x5 |
5271 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_QUEUE0_RB_WPTR_HI__SHIFT 0x6 |
5272 | #define SDMA0_CONTEXT_REG_TYPE0__RESERVED7__SHIFT 0x7 |
5273 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_QUEUE0_RB_RPTR_ADDR_HI__SHIFT 0x8 |
5274 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_QUEUE0_RB_RPTR_ADDR_LO__SHIFT 0x9 |
5275 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_QUEUE0_IB_CNTL__SHIFT 0xa |
5276 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_QUEUE0_IB_RPTR__SHIFT 0xb |
5277 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_QUEUE0_IB_OFFSET__SHIFT 0xc |
5278 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_QUEUE0_IB_BASE_LO__SHIFT 0xd |
5279 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_QUEUE0_IB_BASE_HI__SHIFT 0xe |
5280 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_QUEUE0_IB_SIZE__SHIFT 0xf |
5281 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_QUEUE0_SKIP_CNTL__SHIFT 0x10 |
5282 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_QUEUE0_CONTEXT_STATUS__SHIFT 0x11 |
5283 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_QUEUE0_DOORBELL__SHIFT 0x12 |
5284 | #define SDMA0_CONTEXT_REG_TYPE0__RESERVED31_19__SHIFT 0x13 |
5285 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_QUEUE0_RB_CNTL_MASK 0x00000001L |
5286 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_QUEUE0_RB_BASE_MASK 0x00000002L |
5287 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_QUEUE0_RB_BASE_HI_MASK 0x00000004L |
5288 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_QUEUE0_RB_RPTR_MASK 0x00000008L |
5289 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_QUEUE0_RB_RPTR_HI_MASK 0x00000010L |
5290 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_QUEUE0_RB_WPTR_MASK 0x00000020L |
5291 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_QUEUE0_RB_WPTR_HI_MASK 0x00000040L |
5292 | #define SDMA0_CONTEXT_REG_TYPE0__RESERVED7_MASK 0x00000080L |
5293 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_QUEUE0_RB_RPTR_ADDR_HI_MASK 0x00000100L |
5294 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_QUEUE0_RB_RPTR_ADDR_LO_MASK 0x00000200L |
5295 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_QUEUE0_IB_CNTL_MASK 0x00000400L |
5296 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_QUEUE0_IB_RPTR_MASK 0x00000800L |
5297 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_QUEUE0_IB_OFFSET_MASK 0x00001000L |
5298 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_QUEUE0_IB_BASE_LO_MASK 0x00002000L |
5299 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_QUEUE0_IB_BASE_HI_MASK 0x00004000L |
5300 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_QUEUE0_IB_SIZE_MASK 0x00008000L |
5301 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_QUEUE0_SKIP_CNTL_MASK 0x00010000L |
5302 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_QUEUE0_CONTEXT_STATUS_MASK 0x00020000L |
5303 | #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_QUEUE0_DOORBELL_MASK 0x00040000L |
5304 | #define SDMA0_CONTEXT_REG_TYPE0__RESERVED31_19_MASK 0xFFF80000L |
5305 | //SDMA0_CONTEXT_REG_TYPE1 |
5306 | #define SDMA0_CONTEXT_REG_TYPE1__RESERVED8_0__SHIFT 0x0 |
5307 | #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_QUEUE0_DOORBELL_LOG__SHIFT 0x9 |
5308 | #define SDMA0_CONTEXT_REG_TYPE1__RESERVED10__SHIFT 0xa |
5309 | #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_QUEUE0_DOORBELL_OFFSET__SHIFT 0xb |
5310 | #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_QUEUE0_CSA_ADDR_LO__SHIFT 0xc |
5311 | #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_QUEUE0_CSA_ADDR_HI__SHIFT 0xd |
5312 | #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_QUEUE0_SCHEDULE_CNTL__SHIFT 0xe |
5313 | #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_QUEUE0_IB_SUB_REMAIN__SHIFT 0xf |
5314 | #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_QUEUE0_PREEMPT__SHIFT 0x10 |
5315 | #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_QUEUE0_DUMMY_REG__SHIFT 0x11 |
5316 | #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI__SHIFT 0x12 |
5317 | #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO__SHIFT 0x13 |
5318 | #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_QUEUE0_RB_AQL_CNTL__SHIFT 0x14 |
5319 | #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_QUEUE0_MINOR_PTR_UPDATE__SHIFT 0x15 |
5320 | #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_QUEUE0_RB_PREEMPT__SHIFT 0x16 |
5321 | #define SDMA0_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x17 |
5322 | #define SDMA0_CONTEXT_REG_TYPE1__RESERVED8_0_MASK 0x000001FFL |
5323 | #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_QUEUE0_DOORBELL_LOG_MASK 0x00000200L |
5324 | #define SDMA0_CONTEXT_REG_TYPE1__RESERVED10_MASK 0x00000400L |
5325 | #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_QUEUE0_DOORBELL_OFFSET_MASK 0x00000800L |
5326 | #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_QUEUE0_CSA_ADDR_LO_MASK 0x00001000L |
5327 | #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_QUEUE0_CSA_ADDR_HI_MASK 0x00002000L |
5328 | #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_QUEUE0_SCHEDULE_CNTL_MASK 0x00004000L |
5329 | #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_QUEUE0_IB_SUB_REMAIN_MASK 0x00008000L |
5330 | #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_QUEUE0_PREEMPT_MASK 0x00010000L |
5331 | #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_QUEUE0_DUMMY_REG_MASK 0x00020000L |
5332 | #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI_MASK 0x00040000L |
5333 | #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO_MASK 0x00080000L |
5334 | #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_QUEUE0_RB_AQL_CNTL_MASK 0x00100000L |
5335 | #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_QUEUE0_MINOR_PTR_UPDATE_MASK 0x00200000L |
5336 | #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_QUEUE0_RB_PREEMPT_MASK 0x00400000L |
5337 | #define SDMA0_CONTEXT_REG_TYPE1__RESERVED_MASK 0xFF800000L |
5338 | //SDMA0_CONTEXT_REG_TYPE2 |
5339 | #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_QUEUE0_MIDCMD_DATA0__SHIFT 0x0 |
5340 | #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_QUEUE0_MIDCMD_DATA1__SHIFT 0x1 |
5341 | #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_QUEUE0_MIDCMD_DATA2__SHIFT 0x2 |
5342 | #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_QUEUE0_MIDCMD_DATA3__SHIFT 0x3 |
5343 | #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_QUEUE0_MIDCMD_DATA4__SHIFT 0x4 |
5344 | #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_QUEUE0_MIDCMD_DATA5__SHIFT 0x5 |
5345 | #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_QUEUE0_MIDCMD_DATA6__SHIFT 0x6 |
5346 | #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_QUEUE0_MIDCMD_DATA7__SHIFT 0x7 |
5347 | #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_QUEUE0_MIDCMD_DATA8__SHIFT 0x8 |
5348 | #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_QUEUE0_MIDCMD_DATA9__SHIFT 0x9 |
5349 | #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_QUEUE0_MIDCMD_DATA10__SHIFT 0xa |
5350 | #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_QUEUE0_MIDCMD_CNTL__SHIFT 0xb |
5351 | #define SDMA0_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xe |
5352 | #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_QUEUE0_MIDCMD_DATA0_MASK 0x00000001L |
5353 | #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_QUEUE0_MIDCMD_DATA1_MASK 0x00000002L |
5354 | #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_QUEUE0_MIDCMD_DATA2_MASK 0x00000004L |
5355 | #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_QUEUE0_MIDCMD_DATA3_MASK 0x00000008L |
5356 | #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_QUEUE0_MIDCMD_DATA4_MASK 0x00000010L |
5357 | #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_QUEUE0_MIDCMD_DATA5_MASK 0x00000020L |
5358 | #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_QUEUE0_MIDCMD_DATA6_MASK 0x00000040L |
5359 | #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_QUEUE0_MIDCMD_DATA7_MASK 0x00000080L |
5360 | #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_QUEUE0_MIDCMD_DATA8_MASK 0x00000100L |
5361 | #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_QUEUE0_MIDCMD_DATA9_MASK 0x00000200L |
5362 | #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_QUEUE0_MIDCMD_DATA10_MASK 0x00000400L |
5363 | #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_QUEUE0_MIDCMD_CNTL_MASK 0x00000800L |
5364 | #define SDMA0_CONTEXT_REG_TYPE2__RESERVED_MASK 0xFFFFC000L |
5365 | //SDMA0_PUB_REG_TYPE0 |
5366 | #define SDMA0_PUB_REG_TYPE0__SDMA0_DEC_START__SHIFT 0x0 |
5367 | #define SDMA0_PUB_REG_TYPE0__RESERVED_10_1__SHIFT 0x1 |
5368 | #define SDMA0_PUB_REG_TYPE0__SDMA0_F32_MISC_CNTL__SHIFT 0xb |
5369 | #define SDMA0_PUB_REG_TYPE0__SDMA0_GLOBAL_TIMESTAMP_LO__SHIFT 0xf |
5370 | #define SDMA0_PUB_REG_TYPE0__SDMA0_GLOBAL_TIMESTAMP_HI__SHIFT 0x10 |
5371 | #define SDMA0_PUB_REG_TYPE0__RESERVED22__SHIFT 0x16 |
5372 | #define SDMA0_PUB_REG_TYPE0__RESERVED23__SHIFT 0x17 |
5373 | #define SDMA0_PUB_REG_TYPE0__RESERVED24__SHIFT 0x18 |
5374 | #define SDMA0_PUB_REG_TYPE0__RESERVED25__SHIFT 0x19 |
5375 | #define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL__SHIFT 0x1a |
5376 | #define SDMA0_PUB_REG_TYPE0__RESERVED27__SHIFT 0x1b |
5377 | #define SDMA0_PUB_REG_TYPE0__SDMA0_CNTL__SHIFT 0x1c |
5378 | #define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS__SHIFT 0x1d |
5379 | #define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG__SHIFT 0x1e |
5380 | #define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_READ__SHIFT 0x1f |
5381 | #define SDMA0_PUB_REG_TYPE0__SDMA0_DEC_START_MASK 0x00000001L |
5382 | #define SDMA0_PUB_REG_TYPE0__RESERVED_10_1_MASK 0x000007FEL |
5383 | #define SDMA0_PUB_REG_TYPE0__SDMA0_F32_MISC_CNTL_MASK 0x00000800L |
5384 | #define SDMA0_PUB_REG_TYPE0__SDMA0_GLOBAL_TIMESTAMP_LO_MASK 0x00008000L |
5385 | #define SDMA0_PUB_REG_TYPE0__SDMA0_GLOBAL_TIMESTAMP_HI_MASK 0x00010000L |
5386 | #define SDMA0_PUB_REG_TYPE0__RESERVED22_MASK 0x00400000L |
5387 | #define SDMA0_PUB_REG_TYPE0__RESERVED23_MASK 0x00800000L |
5388 | #define SDMA0_PUB_REG_TYPE0__RESERVED24_MASK 0x01000000L |
5389 | #define SDMA0_PUB_REG_TYPE0__RESERVED25_MASK 0x02000000L |
5390 | #define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL_MASK 0x04000000L |
5391 | #define SDMA0_PUB_REG_TYPE0__RESERVED27_MASK 0x08000000L |
5392 | #define SDMA0_PUB_REG_TYPE0__SDMA0_CNTL_MASK 0x10000000L |
5393 | #define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS_MASK 0x20000000L |
5394 | #define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_MASK 0x40000000L |
5395 | #define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_READ_MASK 0x80000000L |
5396 | //SDMA0_PUB_REG_TYPE1 |
5397 | #define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH__SHIFT 0x0 |
5398 | #define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_HI__SHIFT 0x1 |
5399 | #define SDMA0_PUB_REG_TYPE1__SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT 0x2 |
5400 | #define SDMA0_PUB_REG_TYPE1__SDMA0_IB_OFFSET_FETCH__SHIFT 0x3 |
5401 | #define SDMA0_PUB_REG_TYPE1__SDMA0_PROGRAM__SHIFT 0x4 |
5402 | #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS_REG__SHIFT 0x5 |
5403 | #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS1_REG__SHIFT 0x6 |
5404 | #define SDMA0_PUB_REG_TYPE1__SDMA0_CNTL1__SHIFT 0x7 |
5405 | #define SDMA0_PUB_REG_TYPE1__SDMA0_HBM_PAGE_CONFIG__SHIFT 0x8 |
5406 | #define SDMA0_PUB_REG_TYPE1__SDMA0_UCODE_CHECKSUM__SHIFT 0x9 |
5407 | #define SDMA0_PUB_REG_TYPE1__RESERVED10__SHIFT 0xa |
5408 | #define SDMA0_PUB_REG_TYPE1__SDMA0_FREEZE__SHIFT 0xb |
5409 | #define SDMA0_PUB_REG_TYPE1__SDMA0_PROCESS_QUANTUM0__SHIFT 0xc |
5410 | #define SDMA0_PUB_REG_TYPE1__SDMA0_PROCESS_QUANTUM1__SHIFT 0xd |
5411 | #define SDMA0_PUB_REG_TYPE1__SDMA0_WATCHDOG_CNTL__SHIFT 0xe |
5412 | #define SDMA0_PUB_REG_TYPE1__RESERVED15__SHIFT 0xf |
5413 | #define SDMA0_PUB_REG_TYPE1__RESERVED16__SHIFT 0x10 |
5414 | #define SDMA0_PUB_REG_TYPE1__RESERVED17__SHIFT 0x11 |
5415 | #define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_CONFIG__SHIFT 0x12 |
5416 | #define SDMA0_PUB_REG_TYPE1__SDMA0_BA_THRESHOLD__SHIFT 0x13 |
5417 | #define SDMA0_PUB_REG_TYPE1__SDMA0_ID__SHIFT 0x14 |
5418 | #define SDMA0_PUB_REG_TYPE1__SDMA0_VERSION__SHIFT 0x15 |
5419 | #define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER__SHIFT 0x16 |
5420 | #define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_CLEAR__SHIFT 0x17 |
5421 | #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG__SHIFT 0x18 |
5422 | #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL__SHIFT 0x19 |
5423 | #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_LO__SHIFT 0x1a |
5424 | #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_HI__SHIFT 0x1b |
5425 | #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_CNTL__SHIFT 0x1c |
5426 | #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WATERMK__SHIFT 0x1d |
5427 | #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_TIMEOUT__SHIFT 0x1e |
5428 | #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_PAGE__SHIFT 0x1f |
5429 | #define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_MASK 0x00000001L |
5430 | #define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_HI_MASK 0x00000002L |
5431 | #define SDMA0_PUB_REG_TYPE1__SDMA0_SEM_WAIT_FAIL_TIMER_CNTL_MASK 0x00000004L |
5432 | #define SDMA0_PUB_REG_TYPE1__SDMA0_IB_OFFSET_FETCH_MASK 0x00000008L |
5433 | #define SDMA0_PUB_REG_TYPE1__SDMA0_PROGRAM_MASK 0x00000010L |
5434 | #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS_REG_MASK 0x00000020L |
5435 | #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS1_REG_MASK 0x00000040L |
5436 | #define SDMA0_PUB_REG_TYPE1__SDMA0_CNTL1_MASK 0x00000080L |
5437 | #define SDMA0_PUB_REG_TYPE1__SDMA0_HBM_PAGE_CONFIG_MASK 0x00000100L |
5438 | #define SDMA0_PUB_REG_TYPE1__SDMA0_UCODE_CHECKSUM_MASK 0x00000200L |
5439 | #define SDMA0_PUB_REG_TYPE1__RESERVED10_MASK 0x00000400L |
5440 | #define SDMA0_PUB_REG_TYPE1__SDMA0_FREEZE_MASK 0x00000800L |
5441 | #define SDMA0_PUB_REG_TYPE1__SDMA0_PROCESS_QUANTUM0_MASK 0x00001000L |
5442 | #define SDMA0_PUB_REG_TYPE1__SDMA0_PROCESS_QUANTUM1_MASK 0x00002000L |
5443 | #define SDMA0_PUB_REG_TYPE1__SDMA0_WATCHDOG_CNTL_MASK 0x00004000L |
5444 | #define SDMA0_PUB_REG_TYPE1__RESERVED15_MASK 0x00008000L |
5445 | #define SDMA0_PUB_REG_TYPE1__RESERVED16_MASK 0x00010000L |
5446 | #define SDMA0_PUB_REG_TYPE1__RESERVED17_MASK 0x00020000L |
5447 | #define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_CONFIG_MASK 0x00040000L |
5448 | #define SDMA0_PUB_REG_TYPE1__SDMA0_BA_THRESHOLD_MASK 0x00080000L |
5449 | #define SDMA0_PUB_REG_TYPE1__SDMA0_ID_MASK 0x00100000L |
5450 | #define SDMA0_PUB_REG_TYPE1__SDMA0_VERSION_MASK 0x00200000L |
5451 | #define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_MASK 0x00400000L |
5452 | #define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_CLEAR_MASK 0x00800000L |
5453 | #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG_MASK 0x01000000L |
5454 | #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL_MASK 0x02000000L |
5455 | #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_LO_MASK 0x04000000L |
5456 | #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_HI_MASK 0x08000000L |
5457 | #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_CNTL_MASK 0x10000000L |
5458 | #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WATERMK_MASK 0x20000000L |
5459 | #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_TIMEOUT_MASK 0x40000000L |
5460 | #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_PAGE_MASK 0x80000000L |
5461 | //SDMA0_PUB_REG_TYPE2 |
5462 | #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_STATUS__SHIFT 0x0 |
5463 | #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_STATUS__SHIFT 0x1 |
5464 | #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV0__SHIFT 0x2 |
5465 | #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV1__SHIFT 0x3 |
5466 | #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV2__SHIFT 0x4 |
5467 | #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK0__SHIFT 0x5 |
5468 | #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK1__SHIFT 0x6 |
5469 | #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK0__SHIFT 0x7 |
5470 | #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK1__SHIFT 0x8 |
5471 | #define SDMA0_PUB_REG_TYPE2__SDMA0_RELAX_ORDERING_LUT__SHIFT 0xa |
5472 | #define SDMA0_PUB_REG_TYPE2__SDMA0_CHICKEN_BITS_2__SHIFT 0xb |
5473 | #define SDMA0_PUB_REG_TYPE2__SDMA0_STATUS3_REG__SHIFT 0xc |
5474 | #define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_LO__SHIFT 0xd |
5475 | #define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_HI__SHIFT 0xe |
5476 | #define SDMA0_PUB_REG_TYPE2__SDMA0_GLOBAL_QUANTUM__SHIFT 0xf |
5477 | #define SDMA0_PUB_REG_TYPE2__SDMA0_ERROR_LOG__SHIFT 0x10 |
5478 | #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG0__SHIFT 0x11 |
5479 | #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG1__SHIFT 0x12 |
5480 | #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG2__SHIFT 0x13 |
5481 | #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG3__SHIFT 0x14 |
5482 | #define SDMA0_PUB_REG_TYPE2__SDMA0_F32_COUNTER__SHIFT 0x15 |
5483 | #define SDMA0_PUB_REG_TYPE2__RESERVE_22_22__SHIFT 0x16 |
5484 | #define SDMA0_PUB_REG_TYPE2__RESERVED23__SHIFT 0x17 |
5485 | #define SDMA0_PUB_REG_TYPE2__RESERVED24__SHIFT 0x18 |
5486 | #define SDMA0_PUB_REG_TYPE2__RESERVED25__SHIFT 0x19 |
5487 | #define SDMA0_PUB_REG_TYPE2__RESERVED26__SHIFT 0x1a |
5488 | #define SDMA0_PUB_REG_TYPE2__SDMA0_CRD_CNTL__SHIFT 0x1b |
5489 | #define SDMA0_PUB_REG_TYPE2__SDMA0_RLC_CGCG_CTRL__SHIFT 0x1c |
5490 | #define SDMA0_PUB_REG_TYPE2__SDMA0_GPU_IOV_VIOLATION_LOG__SHIFT 0x1d |
5491 | #define SDMA0_PUB_REG_TYPE2__SDMA0_AQL_STATUS__SHIFT 0x1f |
5492 | #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_STATUS_MASK 0x00000001L |
5493 | #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_STATUS_MASK 0x00000002L |
5494 | #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV0_MASK 0x00000004L |
5495 | #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV1_MASK 0x00000008L |
5496 | #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV2_MASK 0x00000010L |
5497 | #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK0_MASK 0x00000020L |
5498 | #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK1_MASK 0x00000040L |
5499 | #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK0_MASK 0x00000080L |
5500 | #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK1_MASK 0x00000100L |
5501 | #define SDMA0_PUB_REG_TYPE2__SDMA0_RELAX_ORDERING_LUT_MASK 0x00000400L |
5502 | #define SDMA0_PUB_REG_TYPE2__SDMA0_CHICKEN_BITS_2_MASK 0x00000800L |
5503 | #define SDMA0_PUB_REG_TYPE2__SDMA0_STATUS3_REG_MASK 0x00001000L |
5504 | #define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_LO_MASK 0x00002000L |
5505 | #define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_HI_MASK 0x00004000L |
5506 | #define SDMA0_PUB_REG_TYPE2__SDMA0_GLOBAL_QUANTUM_MASK 0x00008000L |
5507 | #define SDMA0_PUB_REG_TYPE2__SDMA0_ERROR_LOG_MASK 0x00010000L |
5508 | #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG0_MASK 0x00020000L |
5509 | #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG1_MASK 0x00040000L |
5510 | #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG2_MASK 0x00080000L |
5511 | #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG3_MASK 0x00100000L |
5512 | #define SDMA0_PUB_REG_TYPE2__SDMA0_F32_COUNTER_MASK 0x00200000L |
5513 | #define SDMA0_PUB_REG_TYPE2__RESERVE_22_22_MASK 0x00400000L |
5514 | #define SDMA0_PUB_REG_TYPE2__RESERVED23_MASK 0x00800000L |
5515 | #define SDMA0_PUB_REG_TYPE2__RESERVED24_MASK 0x01000000L |
5516 | #define SDMA0_PUB_REG_TYPE2__RESERVED25_MASK 0x02000000L |
5517 | #define SDMA0_PUB_REG_TYPE2__RESERVED26_MASK 0x04000000L |
5518 | #define SDMA0_PUB_REG_TYPE2__SDMA0_CRD_CNTL_MASK 0x08000000L |
5519 | #define SDMA0_PUB_REG_TYPE2__SDMA0_RLC_CGCG_CTRL_MASK 0x10000000L |
5520 | #define SDMA0_PUB_REG_TYPE2__SDMA0_GPU_IOV_VIOLATION_LOG_MASK 0x20000000L |
5521 | #define SDMA0_PUB_REG_TYPE2__SDMA0_AQL_STATUS_MASK 0x80000000L |
5522 | //SDMA0_PUB_REG_TYPE3 |
5523 | #define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_DATA__SHIFT 0x0 |
5524 | #define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_INDEX__SHIFT 0x1 |
5525 | #define SDMA0_PUB_REG_TYPE3__SDMA0_TLBI_GCR_CNTL__SHIFT 0x2 |
5526 | #define SDMA0_PUB_REG_TYPE3__SDMA0_TILING_CONFIG__SHIFT 0x3 |
5527 | #define SDMA0_PUB_REG_TYPE3__SDMA0_HASH__SHIFT 0x4 |
5528 | #define SDMA0_PUB_REG_TYPE3__RESERVED5__SHIFT 0x5 |
5529 | #define SDMA0_PUB_REG_TYPE3__RESERVED__SHIFT 0x6 |
5530 | #define SDMA0_PUB_REG_TYPE3__RESERVED7__SHIFT 0x7 |
5531 | #define SDMA0_PUB_REG_TYPE3__SDMA0_CE_CTRL__SHIFT 0x8 |
5532 | #define SDMA0_PUB_REG_TYPE3__SDMA0_FED_STATUS__SHIFT 0x9 |
5533 | #define SDMA0_PUB_REG_TYPE3__RESERVED10__SHIFT 0xa |
5534 | #define SDMA0_PUB_REG_TYPE3__RESERVED11__SHIFT 0xb |
5535 | #define SDMA0_PUB_REG_TYPE3__RESERVED12__SHIFT 0xc |
5536 | #define SDMA0_PUB_REG_TYPE3__RESERVED13__SHIFT 0xd |
5537 | #define SDMA0_PUB_REG_TYPE3__RESERVED14__SHIFT 0xe |
5538 | #define SDMA0_PUB_REG_TYPE3__RESERVED15__SHIFT 0xf |
5539 | #define SDMA0_PUB_REG_TYPE3__SDMA0_INT_STATUS__SHIFT 0x10 |
5540 | #define SDMA0_PUB_REG_TYPE3__SDMA0_GPU_IOV_VIOLATION_LOG2__SHIFT 0x11 |
5541 | #define SDMA0_PUB_REG_TYPE3__SDMA0_HOLE_ADDR_LO__SHIFT 0x12 |
5542 | #define SDMA0_PUB_REG_TYPE3__SDMA0_HOLE_ADDR_HI__SHIFT 0x13 |
5543 | #define SDMA0_PUB_REG_TYPE3__RESERVED20__SHIFT 0x14 |
5544 | #define SDMA0_PUB_REG_TYPE3__SDMA0_CLOCK_GATING_STATUS__SHIFT 0x15 |
5545 | #define SDMA0_PUB_REG_TYPE3__SDMA0_STATUS4_REG__SHIFT 0x16 |
5546 | #define SDMA0_PUB_REG_TYPE3__SDMA0_SCRATCH_RAM_DATA__SHIFT 0x17 |
5547 | #define SDMA0_PUB_REG_TYPE3__SDMA0_SCRATCH_RAM_ADDR__SHIFT 0x18 |
5548 | #define SDMA0_PUB_REG_TYPE3__SDMA0_TIMESTAMP_CNTL__SHIFT 0x19 |
5549 | #define SDMA0_PUB_REG_TYPE3__RESERVED26__SHIFT 0x1a |
5550 | #define SDMA0_PUB_REG_TYPE3__RESERVED27__SHIFT 0x1b |
5551 | #define SDMA0_PUB_REG_TYPE3__SDMA0_STATUS5_REG__SHIFT 0x1c |
5552 | #define SDMA0_PUB_REG_TYPE3__SDMA0_QUEUE_RESET_REQ__SHIFT 0x1d |
5553 | #define SDMA0_PUB_REG_TYPE3__SDMA0_STATUS6_REG__SHIFT 0x1e |
5554 | #define SDMA0_PUB_REG_TYPE3__SDMA0_UCODE1_CHECKSUM__SHIFT 0x1f |
5555 | #define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_DATA_MASK 0x00000001L |
5556 | #define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_INDEX_MASK 0x00000002L |
5557 | #define SDMA0_PUB_REG_TYPE3__SDMA0_TLBI_GCR_CNTL_MASK 0x00000004L |
5558 | #define SDMA0_PUB_REG_TYPE3__SDMA0_TILING_CONFIG_MASK 0x00000008L |
5559 | #define SDMA0_PUB_REG_TYPE3__SDMA0_HASH_MASK 0x00000010L |
5560 | #define SDMA0_PUB_REG_TYPE3__RESERVED5_MASK 0x00000020L |
5561 | #define SDMA0_PUB_REG_TYPE3__RESERVED_MASK 0x00000040L |
5562 | #define SDMA0_PUB_REG_TYPE3__RESERVED7_MASK 0x00000080L |
5563 | #define SDMA0_PUB_REG_TYPE3__SDMA0_CE_CTRL_MASK 0x00000100L |
5564 | #define SDMA0_PUB_REG_TYPE3__SDMA0_FED_STATUS_MASK 0x00000200L |
5565 | #define SDMA0_PUB_REG_TYPE3__RESERVED10_MASK 0x00000400L |
5566 | #define SDMA0_PUB_REG_TYPE3__RESERVED11_MASK 0x00000800L |
5567 | #define SDMA0_PUB_REG_TYPE3__RESERVED12_MASK 0x00001000L |
5568 | #define SDMA0_PUB_REG_TYPE3__RESERVED13_MASK 0x00002000L |
5569 | #define SDMA0_PUB_REG_TYPE3__RESERVED14_MASK 0x00004000L |
5570 | #define SDMA0_PUB_REG_TYPE3__RESERVED15_MASK 0x00008000L |
5571 | #define SDMA0_PUB_REG_TYPE3__SDMA0_INT_STATUS_MASK 0x00010000L |
5572 | #define SDMA0_PUB_REG_TYPE3__SDMA0_GPU_IOV_VIOLATION_LOG2_MASK 0x00020000L |
5573 | #define SDMA0_PUB_REG_TYPE3__SDMA0_HOLE_ADDR_LO_MASK 0x00040000L |
5574 | #define SDMA0_PUB_REG_TYPE3__SDMA0_HOLE_ADDR_HI_MASK 0x00080000L |
5575 | #define SDMA0_PUB_REG_TYPE3__RESERVED20_MASK 0x00100000L |
5576 | #define SDMA0_PUB_REG_TYPE3__SDMA0_CLOCK_GATING_STATUS_MASK 0x00200000L |
5577 | #define SDMA0_PUB_REG_TYPE3__SDMA0_STATUS4_REG_MASK 0x00400000L |
5578 | #define SDMA0_PUB_REG_TYPE3__SDMA0_SCRATCH_RAM_DATA_MASK 0x00800000L |
5579 | #define SDMA0_PUB_REG_TYPE3__SDMA0_SCRATCH_RAM_ADDR_MASK 0x01000000L |
5580 | #define SDMA0_PUB_REG_TYPE3__SDMA0_TIMESTAMP_CNTL_MASK 0x02000000L |
5581 | #define SDMA0_PUB_REG_TYPE3__RESERVED26_MASK 0x04000000L |
5582 | #define SDMA0_PUB_REG_TYPE3__RESERVED27_MASK 0x08000000L |
5583 | #define SDMA0_PUB_REG_TYPE3__SDMA0_STATUS5_REG_MASK 0x10000000L |
5584 | #define SDMA0_PUB_REG_TYPE3__SDMA0_QUEUE_RESET_REQ_MASK 0x20000000L |
5585 | #define SDMA0_PUB_REG_TYPE3__SDMA0_STATUS6_REG_MASK 0x40000000L |
5586 | #define SDMA0_PUB_REG_TYPE3__SDMA0_UCODE1_CHECKSUM_MASK 0x80000000L |
5587 | //SDMA0_VM_CNTL |
5588 | #define SDMA0_VM_CNTL__CMD__SHIFT 0x0 |
5589 | #define SDMA0_VM_CNTL__CMD_MASK 0x0000000FL |
5590 | //SDMA0_F32_CNTL |
5591 | #define SDMA0_F32_CNTL__HALT__SHIFT 0x0 |
5592 | #define SDMA0_F32_CNTL__DBG_SELECT_BITS__SHIFT 0x2 |
5593 | #define SDMA0_F32_CNTL__TH0_CHECKSUM_CLR__SHIFT 0x8 |
5594 | #define SDMA0_F32_CNTL__TH0_RESET__SHIFT 0x9 |
5595 | #define SDMA0_F32_CNTL__TH0_ENABLE__SHIFT 0xa |
5596 | #define SDMA0_F32_CNTL__TH1_CHECKSUM_CLR__SHIFT 0xc |
5597 | #define SDMA0_F32_CNTL__TH1_RESET__SHIFT 0xd |
5598 | #define SDMA0_F32_CNTL__TH1_ENABLE__SHIFT 0xe |
5599 | #define SDMA0_F32_CNTL__TH0_PRIORITY__SHIFT 0x10 |
5600 | #define SDMA0_F32_CNTL__TH1_PRIORITY__SHIFT 0x18 |
5601 | #define SDMA0_F32_CNTL__HALT_MASK 0x00000001L |
5602 | #define SDMA0_F32_CNTL__DBG_SELECT_BITS_MASK 0x000000FCL |
5603 | #define SDMA0_F32_CNTL__TH0_CHECKSUM_CLR_MASK 0x00000100L |
5604 | #define SDMA0_F32_CNTL__TH0_RESET_MASK 0x00000200L |
5605 | #define SDMA0_F32_CNTL__TH0_ENABLE_MASK 0x00000400L |
5606 | #define SDMA0_F32_CNTL__TH1_CHECKSUM_CLR_MASK 0x00001000L |
5607 | #define SDMA0_F32_CNTL__TH1_RESET_MASK 0x00002000L |
5608 | #define SDMA0_F32_CNTL__TH1_ENABLE_MASK 0x00004000L |
5609 | #define SDMA0_F32_CNTL__TH0_PRIORITY_MASK 0x00FF0000L |
5610 | #define SDMA0_F32_CNTL__TH1_PRIORITY_MASK 0xFF000000L |
5611 | |
5612 | |
5613 | // addressBlock: gc_sdma0_sdma1hypdec |
5614 | //SDMA1_UCODE_ADDR |
5615 | #define SDMA1_UCODE_ADDR__VALUE__SHIFT 0x0 |
5616 | #define SDMA1_UCODE_ADDR__THID__SHIFT 0xf |
5617 | #define SDMA1_UCODE_ADDR__VALUE_MASK 0x00001FFFL |
5618 | #define SDMA1_UCODE_ADDR__THID_MASK 0x00008000L |
5619 | //SDMA1_UCODE_DATA |
5620 | #define SDMA1_UCODE_DATA__VALUE__SHIFT 0x0 |
5621 | #define SDMA1_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL |
5622 | //SDMA1_UCODE_SELFLOAD_CONTROL |
5623 | #define SDMA1_UCODE_SELFLOAD_CONTROL__GPA__SHIFT 0x0 |
5624 | #define SDMA1_UCODE_SELFLOAD_CONTROL__SYS__SHIFT 0x1 |
5625 | #define SDMA1_UCODE_SELFLOAD_CONTROL__CID__SHIFT 0x4 |
5626 | #define SDMA1_UCODE_SELFLOAD_CONTROL__CACHE_POLICY__SHIFT 0x8 |
5627 | #define SDMA1_UCODE_SELFLOAD_CONTROL__GPA_MASK 0x00000001L |
5628 | #define SDMA1_UCODE_SELFLOAD_CONTROL__SYS_MASK 0x00000002L |
5629 | #define SDMA1_UCODE_SELFLOAD_CONTROL__CID_MASK 0x000000F0L |
5630 | #define SDMA1_UCODE_SELFLOAD_CONTROL__CACHE_POLICY_MASK 0x00000300L |
5631 | //SDMA1_BROADCAST_UCODE_ADDR |
5632 | #define SDMA1_BROADCAST_UCODE_ADDR__VALUE__SHIFT 0x0 |
5633 | #define SDMA1_BROADCAST_UCODE_ADDR__THID__SHIFT 0xf |
5634 | #define SDMA1_BROADCAST_UCODE_ADDR__VALUE_MASK 0x00001FFFL |
5635 | #define SDMA1_BROADCAST_UCODE_ADDR__THID_MASK 0x00008000L |
5636 | //SDMA1_BROADCAST_UCODE_DATA |
5637 | #define SDMA1_BROADCAST_UCODE_DATA__VALUE__SHIFT 0x0 |
5638 | #define SDMA1_BROADCAST_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL |
5639 | //SDMA1_VM_CTX_LO |
5640 | #define SDMA1_VM_CTX_LO__ADDR__SHIFT 0x2 |
5641 | #define SDMA1_VM_CTX_LO__ADDR_MASK 0xFFFFFFFCL |
5642 | //SDMA1_VM_CTX_HI |
5643 | #define SDMA1_VM_CTX_HI__ADDR__SHIFT 0x0 |
5644 | #define SDMA1_VM_CTX_HI__ADDR_MASK 0xFFFFFFFFL |
5645 | //SDMA1_ACTIVE_FCN_ID |
5646 | #define SDMA1_ACTIVE_FCN_ID__VFID__SHIFT 0x0 |
5647 | #define SDMA1_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4 |
5648 | #define SDMA1_ACTIVE_FCN_ID__VF__SHIFT 0x1f |
5649 | #define SDMA1_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL |
5650 | #define SDMA1_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFF0L |
5651 | #define SDMA1_ACTIVE_FCN_ID__VF_MASK 0x80000000L |
5652 | //SDMA1_VM_CTX_CNTL |
5653 | #define SDMA1_VM_CTX_CNTL__PRIV__SHIFT 0x0 |
5654 | #define SDMA1_VM_CTX_CNTL__VMID__SHIFT 0x4 |
5655 | #define SDMA1_VM_CTX_CNTL__MEM_PHY__SHIFT 0x8 |
5656 | #define SDMA1_VM_CTX_CNTL__BUSY_STATUS_REPORT_ENABLE__SHIFT 0x10 |
5657 | #define SDMA1_VM_CTX_CNTL__PRIV_MASK 0x00000001L |
5658 | #define SDMA1_VM_CTX_CNTL__VMID_MASK 0x000000F0L |
5659 | #define SDMA1_VM_CTX_CNTL__MEM_PHY_MASK 0x00000300L |
5660 | #define SDMA1_VM_CTX_CNTL__BUSY_STATUS_REPORT_ENABLE_MASK 0x00010000L |
5661 | //SDMA1_VIRT_RESET_REQ |
5662 | #define SDMA1_VIRT_RESET_REQ__VF__SHIFT 0x0 |
5663 | #define SDMA1_VIRT_RESET_REQ__PF__SHIFT 0x1f |
5664 | #define SDMA1_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL |
5665 | #define SDMA1_VIRT_RESET_REQ__PF_MASK 0x80000000L |
5666 | //SDMA1_CONTEXT_REG_TYPE0 |
5667 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_QUEUE0_RB_CNTL__SHIFT 0x0 |
5668 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_QUEUE0_RB_BASE__SHIFT 0x1 |
5669 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_QUEUE0_RB_BASE_HI__SHIFT 0x2 |
5670 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_QUEUE0_RB_RPTR__SHIFT 0x3 |
5671 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_QUEUE0_RB_RPTR_HI__SHIFT 0x4 |
5672 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_QUEUE0_RB_WPTR__SHIFT 0x5 |
5673 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_QUEUE0_RB_WPTR_HI__SHIFT 0x6 |
5674 | #define SDMA1_CONTEXT_REG_TYPE0__RESERVED7__SHIFT 0x7 |
5675 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_QUEUE0_RB_RPTR_ADDR_HI__SHIFT 0x8 |
5676 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_QUEUE0_RB_RPTR_ADDR_LO__SHIFT 0x9 |
5677 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_QUEUE0_IB_CNTL__SHIFT 0xa |
5678 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_QUEUE0_IB_RPTR__SHIFT 0xb |
5679 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_QUEUE0_IB_OFFSET__SHIFT 0xc |
5680 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_QUEUE0_IB_BASE_LO__SHIFT 0xd |
5681 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_QUEUE0_IB_BASE_HI__SHIFT 0xe |
5682 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_QUEUE0_IB_SIZE__SHIFT 0xf |
5683 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_QUEUE0_SKIP_CNTL__SHIFT 0x10 |
5684 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_QUEUE0_CONTEXT_STATUS__SHIFT 0x11 |
5685 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_QUEUE0_DOORBELL__SHIFT 0x12 |
5686 | #define SDMA1_CONTEXT_REG_TYPE0__RESERVED31_19__SHIFT 0x13 |
5687 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_QUEUE0_RB_CNTL_MASK 0x00000001L |
5688 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_QUEUE0_RB_BASE_MASK 0x00000002L |
5689 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_QUEUE0_RB_BASE_HI_MASK 0x00000004L |
5690 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_QUEUE0_RB_RPTR_MASK 0x00000008L |
5691 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_QUEUE0_RB_RPTR_HI_MASK 0x00000010L |
5692 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_QUEUE0_RB_WPTR_MASK 0x00000020L |
5693 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_QUEUE0_RB_WPTR_HI_MASK 0x00000040L |
5694 | #define SDMA1_CONTEXT_REG_TYPE0__RESERVED7_MASK 0x00000080L |
5695 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_QUEUE0_RB_RPTR_ADDR_HI_MASK 0x00000100L |
5696 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_QUEUE0_RB_RPTR_ADDR_LO_MASK 0x00000200L |
5697 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_QUEUE0_IB_CNTL_MASK 0x00000400L |
5698 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_QUEUE0_IB_RPTR_MASK 0x00000800L |
5699 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_QUEUE0_IB_OFFSET_MASK 0x00001000L |
5700 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_QUEUE0_IB_BASE_LO_MASK 0x00002000L |
5701 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_QUEUE0_IB_BASE_HI_MASK 0x00004000L |
5702 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_QUEUE0_IB_SIZE_MASK 0x00008000L |
5703 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_QUEUE0_SKIP_CNTL_MASK 0x00010000L |
5704 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_QUEUE0_CONTEXT_STATUS_MASK 0x00020000L |
5705 | #define SDMA1_CONTEXT_REG_TYPE0__SDMA1_QUEUE0_DOORBELL_MASK 0x00040000L |
5706 | #define SDMA1_CONTEXT_REG_TYPE0__RESERVED31_19_MASK 0xFFF80000L |
5707 | //SDMA1_CONTEXT_REG_TYPE1 |
5708 | #define SDMA1_CONTEXT_REG_TYPE1__RESERVED8_0__SHIFT 0x0 |
5709 | #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_QUEUE0_DOORBELL_LOG__SHIFT 0x9 |
5710 | #define SDMA1_CONTEXT_REG_TYPE1__RESERVED10__SHIFT 0xa |
5711 | #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_QUEUE0_DOORBELL_OFFSET__SHIFT 0xb |
5712 | #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_QUEUE0_CSA_ADDR_LO__SHIFT 0xc |
5713 | #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_QUEUE0_CSA_ADDR_HI__SHIFT 0xd |
5714 | #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_QUEUE0_SCHEDULE_CNTL__SHIFT 0xe |
5715 | #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_QUEUE0_IB_SUB_REMAIN__SHIFT 0xf |
5716 | #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_QUEUE0_PREEMPT__SHIFT 0x10 |
5717 | #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_QUEUE0_DUMMY_REG__SHIFT 0x11 |
5718 | #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_QUEUE0_RB_WPTR_POLL_ADDR_HI__SHIFT 0x12 |
5719 | #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_QUEUE0_RB_WPTR_POLL_ADDR_LO__SHIFT 0x13 |
5720 | #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_QUEUE0_RB_AQL_CNTL__SHIFT 0x14 |
5721 | #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_QUEUE0_MINOR_PTR_UPDATE__SHIFT 0x15 |
5722 | #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_QUEUE0_RB_PREEMPT__SHIFT 0x16 |
5723 | #define SDMA1_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x17 |
5724 | #define SDMA1_CONTEXT_REG_TYPE1__RESERVED8_0_MASK 0x000001FFL |
5725 | #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_QUEUE0_DOORBELL_LOG_MASK 0x00000200L |
5726 | #define SDMA1_CONTEXT_REG_TYPE1__RESERVED10_MASK 0x00000400L |
5727 | #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_QUEUE0_DOORBELL_OFFSET_MASK 0x00000800L |
5728 | #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_QUEUE0_CSA_ADDR_LO_MASK 0x00001000L |
5729 | #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_QUEUE0_CSA_ADDR_HI_MASK 0x00002000L |
5730 | #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_QUEUE0_SCHEDULE_CNTL_MASK 0x00004000L |
5731 | #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_QUEUE0_IB_SUB_REMAIN_MASK 0x00008000L |
5732 | #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_QUEUE0_PREEMPT_MASK 0x00010000L |
5733 | #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_QUEUE0_DUMMY_REG_MASK 0x00020000L |
5734 | #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_QUEUE0_RB_WPTR_POLL_ADDR_HI_MASK 0x00040000L |
5735 | #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_QUEUE0_RB_WPTR_POLL_ADDR_LO_MASK 0x00080000L |
5736 | #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_QUEUE0_RB_AQL_CNTL_MASK 0x00100000L |
5737 | #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_QUEUE0_MINOR_PTR_UPDATE_MASK 0x00200000L |
5738 | #define SDMA1_CONTEXT_REG_TYPE1__SDMA1_QUEUE0_RB_PREEMPT_MASK 0x00400000L |
5739 | #define SDMA1_CONTEXT_REG_TYPE1__RESERVED_MASK 0xFF800000L |
5740 | //SDMA1_CONTEXT_REG_TYPE2 |
5741 | #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_QUEUE0_MIDCMD_DATA0__SHIFT 0x0 |
5742 | #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_QUEUE0_MIDCMD_DATA1__SHIFT 0x1 |
5743 | #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_QUEUE0_MIDCMD_DATA2__SHIFT 0x2 |
5744 | #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_QUEUE0_MIDCMD_DATA3__SHIFT 0x3 |
5745 | #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_QUEUE0_MIDCMD_DATA4__SHIFT 0x4 |
5746 | #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_QUEUE0_MIDCMD_DATA5__SHIFT 0x5 |
5747 | #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_QUEUE0_MIDCMD_DATA6__SHIFT 0x6 |
5748 | #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_QUEUE0_MIDCMD_DATA7__SHIFT 0x7 |
5749 | #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_QUEUE0_MIDCMD_DATA8__SHIFT 0x8 |
5750 | #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_QUEUE0_MIDCMD_DATA9__SHIFT 0x9 |
5751 | #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_QUEUE0_MIDCMD_DATA10__SHIFT 0xa |
5752 | #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_QUEUE0_MIDCMD_CNTL__SHIFT 0xb |
5753 | #define SDMA1_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xe |
5754 | #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_QUEUE0_MIDCMD_DATA0_MASK 0x00000001L |
5755 | #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_QUEUE0_MIDCMD_DATA1_MASK 0x00000002L |
5756 | #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_QUEUE0_MIDCMD_DATA2_MASK 0x00000004L |
5757 | #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_QUEUE0_MIDCMD_DATA3_MASK 0x00000008L |
5758 | #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_QUEUE0_MIDCMD_DATA4_MASK 0x00000010L |
5759 | #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_QUEUE0_MIDCMD_DATA5_MASK 0x00000020L |
5760 | #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_QUEUE0_MIDCMD_DATA6_MASK 0x00000040L |
5761 | #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_QUEUE0_MIDCMD_DATA7_MASK 0x00000080L |
5762 | #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_QUEUE0_MIDCMD_DATA8_MASK 0x00000100L |
5763 | #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_QUEUE0_MIDCMD_DATA9_MASK 0x00000200L |
5764 | #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_QUEUE0_MIDCMD_DATA10_MASK 0x00000400L |
5765 | #define SDMA1_CONTEXT_REG_TYPE2__SDMA1_QUEUE0_MIDCMD_CNTL_MASK 0x00000800L |
5766 | #define SDMA1_CONTEXT_REG_TYPE2__RESERVED_MASK 0xFFFFC000L |
5767 | //SDMA1_PUB_REG_TYPE0 |
5768 | #define SDMA1_PUB_REG_TYPE0__SDMA1_DEC_START__SHIFT 0x0 |
5769 | #define SDMA1_PUB_REG_TYPE0__RESERVED_10_1__SHIFT 0x1 |
5770 | #define SDMA1_PUB_REG_TYPE0__SDMA1_F32_MISC_CNTL__SHIFT 0xb |
5771 | #define SDMA1_PUB_REG_TYPE0__SDMA1_GLOBAL_TIMESTAMP_LO__SHIFT 0xf |
5772 | #define SDMA1_PUB_REG_TYPE0__SDMA1_GLOBAL_TIMESTAMP_HI__SHIFT 0x10 |
5773 | #define SDMA1_PUB_REG_TYPE0__RESERVED22__SHIFT 0x16 |
5774 | #define SDMA1_PUB_REG_TYPE0__RESERVED23__SHIFT 0x17 |
5775 | #define SDMA1_PUB_REG_TYPE0__RESERVED24__SHIFT 0x18 |
5776 | #define SDMA1_PUB_REG_TYPE0__RESERVED25__SHIFT 0x19 |
5777 | #define SDMA1_PUB_REG_TYPE0__SDMA1_POWER_CNTL__SHIFT 0x1a |
5778 | #define SDMA1_PUB_REG_TYPE0__RESERVED27__SHIFT 0x1b |
5779 | #define SDMA1_PUB_REG_TYPE0__SDMA1_CNTL__SHIFT 0x1c |
5780 | #define SDMA1_PUB_REG_TYPE0__SDMA1_CHICKEN_BITS__SHIFT 0x1d |
5781 | #define SDMA1_PUB_REG_TYPE0__SDMA1_GB_ADDR_CONFIG__SHIFT 0x1e |
5782 | #define SDMA1_PUB_REG_TYPE0__SDMA1_GB_ADDR_CONFIG_READ__SHIFT 0x1f |
5783 | #define SDMA1_PUB_REG_TYPE0__SDMA1_DEC_START_MASK 0x00000001L |
5784 | #define SDMA1_PUB_REG_TYPE0__RESERVED_10_1_MASK 0x000007FEL |
5785 | #define SDMA1_PUB_REG_TYPE0__SDMA1_F32_MISC_CNTL_MASK 0x00000800L |
5786 | #define SDMA1_PUB_REG_TYPE0__SDMA1_GLOBAL_TIMESTAMP_LO_MASK 0x00008000L |
5787 | #define SDMA1_PUB_REG_TYPE0__SDMA1_GLOBAL_TIMESTAMP_HI_MASK 0x00010000L |
5788 | #define SDMA1_PUB_REG_TYPE0__RESERVED22_MASK 0x00400000L |
5789 | #define SDMA1_PUB_REG_TYPE0__RESERVED23_MASK 0x00800000L |
5790 | #define SDMA1_PUB_REG_TYPE0__RESERVED24_MASK 0x01000000L |
5791 | #define SDMA1_PUB_REG_TYPE0__RESERVED25_MASK 0x02000000L |
5792 | #define SDMA1_PUB_REG_TYPE0__SDMA1_POWER_CNTL_MASK 0x04000000L |
5793 | #define SDMA1_PUB_REG_TYPE0__RESERVED27_MASK 0x08000000L |
5794 | #define SDMA1_PUB_REG_TYPE0__SDMA1_CNTL_MASK 0x10000000L |
5795 | #define SDMA1_PUB_REG_TYPE0__SDMA1_CHICKEN_BITS_MASK 0x20000000L |
5796 | #define SDMA1_PUB_REG_TYPE0__SDMA1_GB_ADDR_CONFIG_MASK 0x40000000L |
5797 | #define SDMA1_PUB_REG_TYPE0__SDMA1_GB_ADDR_CONFIG_READ_MASK 0x80000000L |
5798 | //SDMA1_PUB_REG_TYPE1 |
5799 | #define SDMA1_PUB_REG_TYPE1__SDMA1_RB_RPTR_FETCH__SHIFT 0x0 |
5800 | #define SDMA1_PUB_REG_TYPE1__SDMA1_RB_RPTR_FETCH_HI__SHIFT 0x1 |
5801 | #define SDMA1_PUB_REG_TYPE1__SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT 0x2 |
5802 | #define SDMA1_PUB_REG_TYPE1__SDMA1_IB_OFFSET_FETCH__SHIFT 0x3 |
5803 | #define SDMA1_PUB_REG_TYPE1__SDMA1_PROGRAM__SHIFT 0x4 |
5804 | #define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS_REG__SHIFT 0x5 |
5805 | #define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS1_REG__SHIFT 0x6 |
5806 | #define SDMA1_PUB_REG_TYPE1__SDMA1_CNTL1__SHIFT 0x7 |
5807 | #define SDMA1_PUB_REG_TYPE1__SDMA1_HBM_PAGE_CONFIG__SHIFT 0x8 |
5808 | #define SDMA1_PUB_REG_TYPE1__SDMA1_UCODE_CHECKSUM__SHIFT 0x9 |
5809 | #define SDMA1_PUB_REG_TYPE1__RESERVED10__SHIFT 0xa |
5810 | #define SDMA1_PUB_REG_TYPE1__SDMA1_FREEZE__SHIFT 0xb |
5811 | #define SDMA1_PUB_REG_TYPE1__SDMA1_PROCESS_QUANTUM0__SHIFT 0xc |
5812 | #define SDMA1_PUB_REG_TYPE1__SDMA1_PROCESS_QUANTUM1__SHIFT 0xd |
5813 | #define SDMA1_PUB_REG_TYPE1__SDMA1_WATCHDOG_CNTL__SHIFT 0xe |
5814 | #define SDMA1_PUB_REG_TYPE1__RESERVED15__SHIFT 0xf |
5815 | #define SDMA1_PUB_REG_TYPE1__RESERVED16__SHIFT 0x10 |
5816 | #define SDMA1_PUB_REG_TYPE1__RESERVED17__SHIFT 0x11 |
5817 | #define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_CONFIG__SHIFT 0x12 |
5818 | #define SDMA1_PUB_REG_TYPE1__SDMA1_BA_THRESHOLD__SHIFT 0x13 |
5819 | #define SDMA1_PUB_REG_TYPE1__SDMA1_ID__SHIFT 0x14 |
5820 | #define SDMA1_PUB_REG_TYPE1__SDMA1_VERSION__SHIFT 0x15 |
5821 | #define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_COUNTER__SHIFT 0x16 |
5822 | #define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_COUNTER_CLEAR__SHIFT 0x17 |
5823 | #define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS2_REG__SHIFT 0x18 |
5824 | #define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_CNTL__SHIFT 0x19 |
5825 | #define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_LO__SHIFT 0x1a |
5826 | #define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_HI__SHIFT 0x1b |
5827 | #define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_CNTL__SHIFT 0x1c |
5828 | #define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_WATERMK__SHIFT 0x1d |
5829 | #define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_TIMEOUT__SHIFT 0x1e |
5830 | #define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_PAGE__SHIFT 0x1f |
5831 | #define SDMA1_PUB_REG_TYPE1__SDMA1_RB_RPTR_FETCH_MASK 0x00000001L |
5832 | #define SDMA1_PUB_REG_TYPE1__SDMA1_RB_RPTR_FETCH_HI_MASK 0x00000002L |
5833 | #define SDMA1_PUB_REG_TYPE1__SDMA1_SEM_WAIT_FAIL_TIMER_CNTL_MASK 0x00000004L |
5834 | #define SDMA1_PUB_REG_TYPE1__SDMA1_IB_OFFSET_FETCH_MASK 0x00000008L |
5835 | #define SDMA1_PUB_REG_TYPE1__SDMA1_PROGRAM_MASK 0x00000010L |
5836 | #define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS_REG_MASK 0x00000020L |
5837 | #define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS1_REG_MASK 0x00000040L |
5838 | #define SDMA1_PUB_REG_TYPE1__SDMA1_CNTL1_MASK 0x00000080L |
5839 | #define SDMA1_PUB_REG_TYPE1__SDMA1_HBM_PAGE_CONFIG_MASK 0x00000100L |
5840 | #define SDMA1_PUB_REG_TYPE1__SDMA1_UCODE_CHECKSUM_MASK 0x00000200L |
5841 | #define SDMA1_PUB_REG_TYPE1__RESERVED10_MASK 0x00000400L |
5842 | #define SDMA1_PUB_REG_TYPE1__SDMA1_FREEZE_MASK 0x00000800L |
5843 | #define SDMA1_PUB_REG_TYPE1__SDMA1_PROCESS_QUANTUM0_MASK 0x00001000L |
5844 | #define SDMA1_PUB_REG_TYPE1__SDMA1_PROCESS_QUANTUM1_MASK 0x00002000L |
5845 | #define SDMA1_PUB_REG_TYPE1__SDMA1_WATCHDOG_CNTL_MASK 0x00004000L |
5846 | #define SDMA1_PUB_REG_TYPE1__RESERVED15_MASK 0x00008000L |
5847 | #define SDMA1_PUB_REG_TYPE1__RESERVED16_MASK 0x00010000L |
5848 | #define SDMA1_PUB_REG_TYPE1__RESERVED17_MASK 0x00020000L |
5849 | #define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_CONFIG_MASK 0x00040000L |
5850 | #define SDMA1_PUB_REG_TYPE1__SDMA1_BA_THRESHOLD_MASK 0x00080000L |
5851 | #define SDMA1_PUB_REG_TYPE1__SDMA1_ID_MASK 0x00100000L |
5852 | #define SDMA1_PUB_REG_TYPE1__SDMA1_VERSION_MASK 0x00200000L |
5853 | #define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_COUNTER_MASK 0x00400000L |
5854 | #define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_COUNTER_CLEAR_MASK 0x00800000L |
5855 | #define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS2_REG_MASK 0x01000000L |
5856 | #define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_CNTL_MASK 0x02000000L |
5857 | #define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_LO_MASK 0x04000000L |
5858 | #define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_HI_MASK 0x08000000L |
5859 | #define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_CNTL_MASK 0x10000000L |
5860 | #define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_WATERMK_MASK 0x20000000L |
5861 | #define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_TIMEOUT_MASK 0x40000000L |
5862 | #define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_PAGE_MASK 0x80000000L |
5863 | //SDMA1_PUB_REG_TYPE2 |
5864 | #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_RD_STATUS__SHIFT 0x0 |
5865 | #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_WR_STATUS__SHIFT 0x1 |
5866 | #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV0__SHIFT 0x2 |
5867 | #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV1__SHIFT 0x3 |
5868 | #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV2__SHIFT 0x4 |
5869 | #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_RD_XNACK0__SHIFT 0x5 |
5870 | #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_RD_XNACK1__SHIFT 0x6 |
5871 | #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_WR_XNACK0__SHIFT 0x7 |
5872 | #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_WR_XNACK1__SHIFT 0x8 |
5873 | #define SDMA1_PUB_REG_TYPE2__SDMA1_RELAX_ORDERING_LUT__SHIFT 0xa |
5874 | #define SDMA1_PUB_REG_TYPE2__SDMA1_CHICKEN_BITS_2__SHIFT 0xb |
5875 | #define SDMA1_PUB_REG_TYPE2__SDMA1_STATUS3_REG__SHIFT 0xc |
5876 | #define SDMA1_PUB_REG_TYPE2__SDMA1_PHYSICAL_ADDR_LO__SHIFT 0xd |
5877 | #define SDMA1_PUB_REG_TYPE2__SDMA1_PHYSICAL_ADDR_HI__SHIFT 0xe |
5878 | #define SDMA1_PUB_REG_TYPE2__SDMA1_GLOBAL_QUANTUM__SHIFT 0xf |
5879 | #define SDMA1_PUB_REG_TYPE2__SDMA1_ERROR_LOG__SHIFT 0x10 |
5880 | #define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG0__SHIFT 0x11 |
5881 | #define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG1__SHIFT 0x12 |
5882 | #define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG2__SHIFT 0x13 |
5883 | #define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG3__SHIFT 0x14 |
5884 | #define SDMA1_PUB_REG_TYPE2__SDMA1_F32_COUNTER__SHIFT 0x15 |
5885 | #define SDMA1_PUB_REG_TYPE2__RESERVE_22_22__SHIFT 0x16 |
5886 | #define SDMA1_PUB_REG_TYPE2__RESERVED23__SHIFT 0x17 |
5887 | #define SDMA1_PUB_REG_TYPE2__RESERVED24__SHIFT 0x18 |
5888 | #define SDMA1_PUB_REG_TYPE2__RESERVED25__SHIFT 0x19 |
5889 | #define SDMA1_PUB_REG_TYPE2__RESERVED26__SHIFT 0x1a |
5890 | #define SDMA1_PUB_REG_TYPE2__SDMA1_CRD_CNTL__SHIFT 0x1b |
5891 | #define SDMA1_PUB_REG_TYPE2__SDMA1_RLC_CGCG_CTRL__SHIFT 0x1c |
5892 | #define SDMA1_PUB_REG_TYPE2__SDMA1_GPU_IOV_VIOLATION_LOG__SHIFT 0x1d |
5893 | #define SDMA1_PUB_REG_TYPE2__SDMA1_AQL_STATUS__SHIFT 0x1f |
5894 | #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_RD_STATUS_MASK 0x00000001L |
5895 | #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_WR_STATUS_MASK 0x00000002L |
5896 | #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV0_MASK 0x00000004L |
5897 | #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV1_MASK 0x00000008L |
5898 | #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV2_MASK 0x00000010L |
5899 | #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_RD_XNACK0_MASK 0x00000020L |
5900 | #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_RD_XNACK1_MASK 0x00000040L |
5901 | #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_WR_XNACK0_MASK 0x00000080L |
5902 | #define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_WR_XNACK1_MASK 0x00000100L |
5903 | #define SDMA1_PUB_REG_TYPE2__SDMA1_RELAX_ORDERING_LUT_MASK 0x00000400L |
5904 | #define SDMA1_PUB_REG_TYPE2__SDMA1_CHICKEN_BITS_2_MASK 0x00000800L |
5905 | #define SDMA1_PUB_REG_TYPE2__SDMA1_STATUS3_REG_MASK 0x00001000L |
5906 | #define SDMA1_PUB_REG_TYPE2__SDMA1_PHYSICAL_ADDR_LO_MASK 0x00002000L |
5907 | #define SDMA1_PUB_REG_TYPE2__SDMA1_PHYSICAL_ADDR_HI_MASK 0x00004000L |
5908 | #define SDMA1_PUB_REG_TYPE2__SDMA1_GLOBAL_QUANTUM_MASK 0x00008000L |
5909 | #define SDMA1_PUB_REG_TYPE2__SDMA1_ERROR_LOG_MASK 0x00010000L |
5910 | #define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG0_MASK 0x00020000L |
5911 | #define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG1_MASK 0x00040000L |
5912 | #define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG2_MASK 0x00080000L |
5913 | #define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG3_MASK 0x00100000L |
5914 | #define SDMA1_PUB_REG_TYPE2__SDMA1_F32_COUNTER_MASK 0x00200000L |
5915 | #define SDMA1_PUB_REG_TYPE2__RESERVE_22_22_MASK 0x00400000L |
5916 | #define SDMA1_PUB_REG_TYPE2__RESERVED23_MASK 0x00800000L |
5917 | #define SDMA1_PUB_REG_TYPE2__RESERVED24_MASK 0x01000000L |
5918 | #define SDMA1_PUB_REG_TYPE2__RESERVED25_MASK 0x02000000L |
5919 | #define SDMA1_PUB_REG_TYPE2__RESERVED26_MASK 0x04000000L |
5920 | #define SDMA1_PUB_REG_TYPE2__SDMA1_CRD_CNTL_MASK 0x08000000L |
5921 | #define SDMA1_PUB_REG_TYPE2__SDMA1_RLC_CGCG_CTRL_MASK 0x10000000L |
5922 | #define SDMA1_PUB_REG_TYPE2__SDMA1_GPU_IOV_VIOLATION_LOG_MASK 0x20000000L |
5923 | #define SDMA1_PUB_REG_TYPE2__SDMA1_AQL_STATUS_MASK 0x80000000L |
5924 | //SDMA1_PUB_REG_TYPE3 |
5925 | #define SDMA1_PUB_REG_TYPE3__SDMA1_EA_DBIT_ADDR_DATA__SHIFT 0x0 |
5926 | #define SDMA1_PUB_REG_TYPE3__SDMA1_EA_DBIT_ADDR_INDEX__SHIFT 0x1 |
5927 | #define SDMA1_PUB_REG_TYPE3__SDMA1_TLBI_GCR_CNTL__SHIFT 0x2 |
5928 | #define SDMA1_PUB_REG_TYPE3__SDMA1_TILING_CONFIG__SHIFT 0x3 |
5929 | #define SDMA1_PUB_REG_TYPE3__SDMA1_HASH__SHIFT 0x4 |
5930 | #define SDMA1_PUB_REG_TYPE3__RESERVED5__SHIFT 0x5 |
5931 | #define SDMA1_PUB_REG_TYPE3__RESERVED__SHIFT 0x6 |
5932 | #define SDMA1_PUB_REG_TYPE3__RESERVED7__SHIFT 0x7 |
5933 | #define SDMA1_PUB_REG_TYPE3__SDMA1_CE_CTRL__SHIFT 0x8 |
5934 | #define SDMA1_PUB_REG_TYPE3__SDMA1_FED_STATUS__SHIFT 0x9 |
5935 | #define SDMA1_PUB_REG_TYPE3__RESERVED10__SHIFT 0xa |
5936 | #define SDMA1_PUB_REG_TYPE3__RESERVED11__SHIFT 0xb |
5937 | #define SDMA1_PUB_REG_TYPE3__RESERVED12__SHIFT 0xc |
5938 | #define SDMA1_PUB_REG_TYPE3__RESERVED13__SHIFT 0xd |
5939 | #define SDMA1_PUB_REG_TYPE3__RESERVED14__SHIFT 0xe |
5940 | #define SDMA1_PUB_REG_TYPE3__RESERVED15__SHIFT 0xf |
5941 | #define SDMA1_PUB_REG_TYPE3__SDMA1_INT_STATUS__SHIFT 0x10 |
5942 | #define SDMA1_PUB_REG_TYPE3__SDMA1_GPU_IOV_VIOLATION_LOG2__SHIFT 0x11 |
5943 | #define SDMA1_PUB_REG_TYPE3__SDMA1_HOLE_ADDR_LO__SHIFT 0x12 |
5944 | #define SDMA1_PUB_REG_TYPE3__SDMA1_HOLE_ADDR_HI__SHIFT 0x13 |
5945 | #define SDMA1_PUB_REG_TYPE3__RESERVED20__SHIFT 0x14 |
5946 | #define SDMA1_PUB_REG_TYPE3__SDMA1_CLOCK_GATING_STATUS__SHIFT 0x15 |
5947 | #define SDMA1_PUB_REG_TYPE3__SDMA1_STATUS4_REG__SHIFT 0x16 |
5948 | #define SDMA1_PUB_REG_TYPE3__SDMA1_SCRATCH_RAM_DATA__SHIFT 0x17 |
5949 | #define SDMA1_PUB_REG_TYPE3__SDMA1_SCRATCH_RAM_ADDR__SHIFT 0x18 |
5950 | #define SDMA1_PUB_REG_TYPE3__SDMA1_TIMESTAMP_CNTL__SHIFT 0x19 |
5951 | #define SDMA1_PUB_REG_TYPE3__RESERVED26__SHIFT 0x1a |
5952 | #define SDMA1_PUB_REG_TYPE3__RESERVED27__SHIFT 0x1b |
5953 | #define SDMA1_PUB_REG_TYPE3__SDMA1_STATUS5_REG__SHIFT 0x1c |
5954 | #define SDMA1_PUB_REG_TYPE3__SDMA1_QUEUE_RESET_REQ__SHIFT 0x1d |
5955 | #define SDMA1_PUB_REG_TYPE3__SDMA1_STATUS6_REG__SHIFT 0x1e |
5956 | #define SDMA1_PUB_REG_TYPE3__SDMA1_UCODE1_CHECKSUM__SHIFT 0x1f |
5957 | #define SDMA1_PUB_REG_TYPE3__SDMA1_EA_DBIT_ADDR_DATA_MASK 0x00000001L |
5958 | #define SDMA1_PUB_REG_TYPE3__SDMA1_EA_DBIT_ADDR_INDEX_MASK 0x00000002L |
5959 | #define SDMA1_PUB_REG_TYPE3__SDMA1_TLBI_GCR_CNTL_MASK 0x00000004L |
5960 | #define SDMA1_PUB_REG_TYPE3__SDMA1_TILING_CONFIG_MASK 0x00000008L |
5961 | #define SDMA1_PUB_REG_TYPE3__SDMA1_HASH_MASK 0x00000010L |
5962 | #define SDMA1_PUB_REG_TYPE3__RESERVED5_MASK 0x00000020L |
5963 | #define SDMA1_PUB_REG_TYPE3__RESERVED_MASK 0x00000040L |
5964 | #define SDMA1_PUB_REG_TYPE3__RESERVED7_MASK 0x00000080L |
5965 | #define SDMA1_PUB_REG_TYPE3__SDMA1_CE_CTRL_MASK 0x00000100L |
5966 | #define SDMA1_PUB_REG_TYPE3__SDMA1_FED_STATUS_MASK 0x00000200L |
5967 | #define SDMA1_PUB_REG_TYPE3__RESERVED10_MASK 0x00000400L |
5968 | #define SDMA1_PUB_REG_TYPE3__RESERVED11_MASK 0x00000800L |
5969 | #define SDMA1_PUB_REG_TYPE3__RESERVED12_MASK 0x00001000L |
5970 | #define SDMA1_PUB_REG_TYPE3__RESERVED13_MASK 0x00002000L |
5971 | #define SDMA1_PUB_REG_TYPE3__RESERVED14_MASK 0x00004000L |
5972 | #define SDMA1_PUB_REG_TYPE3__RESERVED15_MASK 0x00008000L |
5973 | #define SDMA1_PUB_REG_TYPE3__SDMA1_INT_STATUS_MASK 0x00010000L |
5974 | #define SDMA1_PUB_REG_TYPE3__SDMA1_GPU_IOV_VIOLATION_LOG2_MASK 0x00020000L |
5975 | #define SDMA1_PUB_REG_TYPE3__SDMA1_HOLE_ADDR_LO_MASK 0x00040000L |
5976 | #define SDMA1_PUB_REG_TYPE3__SDMA1_HOLE_ADDR_HI_MASK 0x00080000L |
5977 | #define SDMA1_PUB_REG_TYPE3__RESERVED20_MASK 0x00100000L |
5978 | #define SDMA1_PUB_REG_TYPE3__SDMA1_CLOCK_GATING_STATUS_MASK 0x00200000L |
5979 | #define SDMA1_PUB_REG_TYPE3__SDMA1_STATUS4_REG_MASK 0x00400000L |
5980 | #define SDMA1_PUB_REG_TYPE3__SDMA1_SCRATCH_RAM_DATA_MASK 0x00800000L |
5981 | #define SDMA1_PUB_REG_TYPE3__SDMA1_SCRATCH_RAM_ADDR_MASK 0x01000000L |
5982 | #define SDMA1_PUB_REG_TYPE3__SDMA1_TIMESTAMP_CNTL_MASK 0x02000000L |
5983 | #define SDMA1_PUB_REG_TYPE3__RESERVED26_MASK 0x04000000L |
5984 | #define SDMA1_PUB_REG_TYPE3__RESERVED27_MASK 0x08000000L |
5985 | #define SDMA1_PUB_REG_TYPE3__SDMA1_STATUS5_REG_MASK 0x10000000L |
5986 | #define SDMA1_PUB_REG_TYPE3__SDMA1_QUEUE_RESET_REQ_MASK 0x20000000L |
5987 | #define SDMA1_PUB_REG_TYPE3__SDMA1_STATUS6_REG_MASK 0x40000000L |
5988 | #define SDMA1_PUB_REG_TYPE3__SDMA1_UCODE1_CHECKSUM_MASK 0x80000000L |
5989 | //SDMA1_VM_CNTL |
5990 | #define SDMA1_VM_CNTL__CMD__SHIFT 0x0 |
5991 | #define SDMA1_VM_CNTL__CMD_MASK 0x0000000FL |
5992 | //SDMA1_F32_CNTL |
5993 | #define SDMA1_F32_CNTL__HALT__SHIFT 0x0 |
5994 | #define SDMA1_F32_CNTL__DBG_SELECT_BITS__SHIFT 0x2 |
5995 | #define SDMA1_F32_CNTL__TH0_CHECKSUM_CLR__SHIFT 0x8 |
5996 | #define SDMA1_F32_CNTL__TH0_RESET__SHIFT 0x9 |
5997 | #define SDMA1_F32_CNTL__TH0_ENABLE__SHIFT 0xa |
5998 | #define SDMA1_F32_CNTL__TH1_CHECKSUM_CLR__SHIFT 0xc |
5999 | #define SDMA1_F32_CNTL__TH1_RESET__SHIFT 0xd |
6000 | #define SDMA1_F32_CNTL__TH1_ENABLE__SHIFT 0xe |
6001 | #define SDMA1_F32_CNTL__TH0_PRIORITY__SHIFT 0x10 |
6002 | #define SDMA1_F32_CNTL__TH1_PRIORITY__SHIFT 0x18 |
6003 | #define SDMA1_F32_CNTL__HALT_MASK 0x00000001L |
6004 | #define SDMA1_F32_CNTL__DBG_SELECT_BITS_MASK 0x000000FCL |
6005 | #define SDMA1_F32_CNTL__TH0_CHECKSUM_CLR_MASK 0x00000100L |
6006 | #define SDMA1_F32_CNTL__TH0_RESET_MASK 0x00000200L |
6007 | #define SDMA1_F32_CNTL__TH0_ENABLE_MASK 0x00000400L |
6008 | #define SDMA1_F32_CNTL__TH1_CHECKSUM_CLR_MASK 0x00001000L |
6009 | #define SDMA1_F32_CNTL__TH1_RESET_MASK 0x00002000L |
6010 | #define SDMA1_F32_CNTL__TH1_ENABLE_MASK 0x00004000L |
6011 | #define SDMA1_F32_CNTL__TH0_PRIORITY_MASK 0x00FF0000L |
6012 | #define SDMA1_F32_CNTL__TH1_PRIORITY_MASK 0xFF000000L |
6013 | |
6014 | |
6015 | // addressBlock: gc_sdma0_sdma0perfsdec |
6016 | //SDMA0_PERFCNT_PERFCOUNTER0_CFG |
6017 | #define SDMA0_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 |
6018 | #define SDMA0_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 |
6019 | #define SDMA0_PERFCNT_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 |
6020 | #define SDMA0_PERFCNT_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c |
6021 | #define SDMA0_PERFCNT_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d |
6022 | #define SDMA0_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL |
6023 | #define SDMA0_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L |
6024 | #define SDMA0_PERFCNT_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L |
6025 | #define SDMA0_PERFCNT_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L |
6026 | #define SDMA0_PERFCNT_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L |
6027 | //SDMA0_PERFCNT_PERFCOUNTER1_CFG |
6028 | #define SDMA0_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 |
6029 | #define SDMA0_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 |
6030 | #define SDMA0_PERFCNT_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 |
6031 | #define SDMA0_PERFCNT_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c |
6032 | #define SDMA0_PERFCNT_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d |
6033 | #define SDMA0_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL |
6034 | #define SDMA0_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L |
6035 | #define SDMA0_PERFCNT_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L |
6036 | #define SDMA0_PERFCNT_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L |
6037 | #define SDMA0_PERFCNT_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L |
6038 | //SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL |
6039 | #define SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 |
6040 | #define SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 |
6041 | #define SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 |
6042 | #define SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 |
6043 | #define SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 |
6044 | #define SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a |
6045 | #define SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL |
6046 | #define SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L |
6047 | #define SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L |
6048 | #define SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L |
6049 | #define SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L |
6050 | #define SDMA0_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L |
6051 | //SDMA0_PERFCNT_MISC_CNTL |
6052 | #define SDMA0_PERFCNT_MISC_CNTL__CMD_OP__SHIFT 0x0 |
6053 | #define SDMA0_PERFCNT_MISC_CNTL__CMD_OP_MASK 0x0000FFFFL |
6054 | //SDMA0_PERFCOUNTER0_SELECT |
6055 | #define SDMA0_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
6056 | #define SDMA0_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
6057 | #define SDMA0_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 |
6058 | #define SDMA0_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 |
6059 | #define SDMA0_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c |
6060 | #define SDMA0_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL |
6061 | #define SDMA0_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L |
6062 | #define SDMA0_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L |
6063 | #define SDMA0_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L |
6064 | #define SDMA0_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L |
6065 | //SDMA0_PERFCOUNTER0_SELECT1 |
6066 | #define SDMA0_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
6067 | #define SDMA0_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
6068 | #define SDMA0_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 |
6069 | #define SDMA0_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c |
6070 | #define SDMA0_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL |
6071 | #define SDMA0_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
6072 | #define SDMA0_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L |
6073 | #define SDMA0_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L |
6074 | //SDMA0_PERFCOUNTER1_SELECT |
6075 | #define SDMA0_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
6076 | #define SDMA0_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa |
6077 | #define SDMA0_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 |
6078 | #define SDMA0_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 |
6079 | #define SDMA0_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c |
6080 | #define SDMA0_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL |
6081 | #define SDMA0_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L |
6082 | #define SDMA0_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L |
6083 | #define SDMA0_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L |
6084 | #define SDMA0_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L |
6085 | //SDMA0_PERFCOUNTER1_SELECT1 |
6086 | #define SDMA0_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 |
6087 | #define SDMA0_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa |
6088 | #define SDMA0_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 |
6089 | #define SDMA0_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c |
6090 | #define SDMA0_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL |
6091 | #define SDMA0_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
6092 | #define SDMA0_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L |
6093 | #define SDMA0_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L |
6094 | |
6095 | |
6096 | // addressBlock: gc_sdma0_sdma1perfsdec |
6097 | //SDMA1_PERFCNT_PERFCOUNTER0_CFG |
6098 | #define SDMA1_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 |
6099 | #define SDMA1_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 |
6100 | #define SDMA1_PERFCNT_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 |
6101 | #define SDMA1_PERFCNT_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c |
6102 | #define SDMA1_PERFCNT_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d |
6103 | #define SDMA1_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL |
6104 | #define SDMA1_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L |
6105 | #define SDMA1_PERFCNT_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L |
6106 | #define SDMA1_PERFCNT_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L |
6107 | #define SDMA1_PERFCNT_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L |
6108 | //SDMA1_PERFCNT_PERFCOUNTER1_CFG |
6109 | #define SDMA1_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 |
6110 | #define SDMA1_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 |
6111 | #define SDMA1_PERFCNT_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 |
6112 | #define SDMA1_PERFCNT_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c |
6113 | #define SDMA1_PERFCNT_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d |
6114 | #define SDMA1_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL |
6115 | #define SDMA1_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L |
6116 | #define SDMA1_PERFCNT_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L |
6117 | #define SDMA1_PERFCNT_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L |
6118 | #define SDMA1_PERFCNT_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L |
6119 | //SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL |
6120 | #define SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 |
6121 | #define SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 |
6122 | #define SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 |
6123 | #define SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 |
6124 | #define SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 |
6125 | #define SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a |
6126 | #define SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL |
6127 | #define SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L |
6128 | #define SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L |
6129 | #define SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L |
6130 | #define SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L |
6131 | #define SDMA1_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L |
6132 | //SDMA1_PERFCNT_MISC_CNTL |
6133 | #define SDMA1_PERFCNT_MISC_CNTL__CMD_OP__SHIFT 0x0 |
6134 | #define SDMA1_PERFCNT_MISC_CNTL__CMD_OP_MASK 0x0000FFFFL |
6135 | //SDMA1_PERFCOUNTER0_SELECT |
6136 | #define SDMA1_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
6137 | #define SDMA1_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
6138 | #define SDMA1_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 |
6139 | #define SDMA1_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 |
6140 | #define SDMA1_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c |
6141 | #define SDMA1_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL |
6142 | #define SDMA1_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L |
6143 | #define SDMA1_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L |
6144 | #define SDMA1_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L |
6145 | #define SDMA1_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L |
6146 | //SDMA1_PERFCOUNTER0_SELECT1 |
6147 | #define SDMA1_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
6148 | #define SDMA1_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
6149 | #define SDMA1_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 |
6150 | #define SDMA1_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c |
6151 | #define SDMA1_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL |
6152 | #define SDMA1_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
6153 | #define SDMA1_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L |
6154 | #define SDMA1_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L |
6155 | //SDMA1_PERFCOUNTER1_SELECT |
6156 | #define SDMA1_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
6157 | #define SDMA1_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa |
6158 | #define SDMA1_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 |
6159 | #define SDMA1_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 |
6160 | #define SDMA1_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c |
6161 | #define SDMA1_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL |
6162 | #define SDMA1_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L |
6163 | #define SDMA1_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L |
6164 | #define SDMA1_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L |
6165 | #define SDMA1_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L |
6166 | //SDMA1_PERFCOUNTER1_SELECT1 |
6167 | #define SDMA1_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 |
6168 | #define SDMA1_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa |
6169 | #define SDMA1_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 |
6170 | #define SDMA1_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c |
6171 | #define SDMA1_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL |
6172 | #define SDMA1_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
6173 | #define SDMA1_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L |
6174 | #define SDMA1_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L |
6175 | |
6176 | |
6177 | // addressBlock: gc_sdma0_sdma0perfddec |
6178 | //SDMA0_PERFCNT_PERFCOUNTER_LO |
6179 | #define SDMA0_PERFCNT_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 |
6180 | #define SDMA0_PERFCNT_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL |
6181 | //SDMA0_PERFCNT_PERFCOUNTER_HI |
6182 | #define SDMA0_PERFCNT_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 |
6183 | #define SDMA0_PERFCNT_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 |
6184 | #define SDMA0_PERFCNT_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL |
6185 | #define SDMA0_PERFCNT_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L |
6186 | //SDMA0_PERFCOUNTER0_LO |
6187 | #define SDMA0_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
6188 | #define SDMA0_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
6189 | //SDMA0_PERFCOUNTER0_HI |
6190 | #define SDMA0_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
6191 | #define SDMA0_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
6192 | //SDMA0_PERFCOUNTER1_LO |
6193 | #define SDMA0_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
6194 | #define SDMA0_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
6195 | //SDMA0_PERFCOUNTER1_HI |
6196 | #define SDMA0_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
6197 | #define SDMA0_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
6198 | |
6199 | |
6200 | // addressBlock: gc_sdma0_sdma1perfddec |
6201 | //SDMA1_PERFCNT_PERFCOUNTER_LO |
6202 | #define SDMA1_PERFCNT_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 |
6203 | #define SDMA1_PERFCNT_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL |
6204 | //SDMA1_PERFCNT_PERFCOUNTER_HI |
6205 | #define SDMA1_PERFCNT_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 |
6206 | #define SDMA1_PERFCNT_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 |
6207 | #define SDMA1_PERFCNT_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL |
6208 | #define SDMA1_PERFCNT_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L |
6209 | //SDMA1_PERFCOUNTER0_LO |
6210 | #define SDMA1_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
6211 | #define SDMA1_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
6212 | //SDMA1_PERFCOUNTER0_HI |
6213 | #define SDMA1_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
6214 | #define SDMA1_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
6215 | //SDMA1_PERFCOUNTER1_LO |
6216 | #define SDMA1_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
6217 | #define SDMA1_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
6218 | //SDMA1_PERFCOUNTER1_HI |
6219 | #define SDMA1_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
6220 | #define SDMA1_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
6221 | |
6222 | |
6223 | // addressBlock: gc_grbmdec |
6224 | //GRBM_CNTL |
6225 | #define GRBM_CNTL__READ_TIMEOUT__SHIFT 0x0 |
6226 | #define GRBM_CNTL__REPORT_LAST_RDERR__SHIFT 0x1f |
6227 | #define GRBM_CNTL__READ_TIMEOUT_MASK 0x000000FFL |
6228 | #define GRBM_CNTL__REPORT_LAST_RDERR_MASK 0x80000000L |
6229 | //GRBM_SKEW_CNTL |
6230 | #define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD__SHIFT 0x0 |
6231 | #define GRBM_SKEW_CNTL__SKEW_COUNT__SHIFT 0x6 |
6232 | #define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD_MASK 0x0000003FL |
6233 | #define GRBM_SKEW_CNTL__SKEW_COUNT_MASK 0x00000FC0L |
6234 | //GRBM_STATUS2 |
6235 | #define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL__SHIFT 0x0 |
6236 | #define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING__SHIFT 0x4 |
6237 | #define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING__SHIFT 0x5 |
6238 | #define GRBM_STATUS2__ME1PIPE0_RQ_PENDING__SHIFT 0x6 |
6239 | #define GRBM_STATUS2__ME1PIPE1_RQ_PENDING__SHIFT 0x7 |
6240 | #define GRBM_STATUS2__ME1PIPE2_RQ_PENDING__SHIFT 0x8 |
6241 | #define GRBM_STATUS2__ME1PIPE3_RQ_PENDING__SHIFT 0x9 |
6242 | #define GRBM_STATUS2__RLC_RQ_PENDING__SHIFT 0xe |
6243 | #define GRBM_STATUS2__UTCL2_BUSY__SHIFT 0xf |
6244 | #define GRBM_STATUS2__EA_BUSY__SHIFT 0x10 |
6245 | #define GRBM_STATUS2__RMI_BUSY__SHIFT 0x11 |
6246 | #define GRBM_STATUS2__UTCL2_RQ_PENDING__SHIFT 0x12 |
6247 | #define GRBM_STATUS2__SDMA_SCH_RQ_PENDING__SHIFT 0x13 |
6248 | #define GRBM_STATUS2__EA_LINK_BUSY__SHIFT 0x14 |
6249 | #define GRBM_STATUS2__SDMA_BUSY__SHIFT 0x15 |
6250 | #define GRBM_STATUS2__SDMA0_RQ_PENDING__SHIFT 0x16 |
6251 | #define GRBM_STATUS2__SDMA1_RQ_PENDING__SHIFT 0x17 |
6252 | #define GRBM_STATUS2__RLC_BUSY__SHIFT 0x1a |
6253 | #define GRBM_STATUS2__TCP_BUSY__SHIFT 0x1b |
6254 | #define GRBM_STATUS2__CPF_BUSY__SHIFT 0x1c |
6255 | #define GRBM_STATUS2__CPC_BUSY__SHIFT 0x1d |
6256 | #define GRBM_STATUS2__CPG_BUSY__SHIFT 0x1e |
6257 | #define GRBM_STATUS2__CPAXI_BUSY__SHIFT 0x1f |
6258 | #define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL_MASK 0x0000000FL |
6259 | #define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING_MASK 0x00000010L |
6260 | #define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING_MASK 0x00000020L |
6261 | #define GRBM_STATUS2__ME1PIPE0_RQ_PENDING_MASK 0x00000040L |
6262 | #define GRBM_STATUS2__ME1PIPE1_RQ_PENDING_MASK 0x00000080L |
6263 | #define GRBM_STATUS2__ME1PIPE2_RQ_PENDING_MASK 0x00000100L |
6264 | #define GRBM_STATUS2__ME1PIPE3_RQ_PENDING_MASK 0x00000200L |
6265 | #define GRBM_STATUS2__RLC_RQ_PENDING_MASK 0x00004000L |
6266 | #define GRBM_STATUS2__UTCL2_BUSY_MASK 0x00008000L |
6267 | #define GRBM_STATUS2__EA_BUSY_MASK 0x00010000L |
6268 | #define GRBM_STATUS2__RMI_BUSY_MASK 0x00020000L |
6269 | #define GRBM_STATUS2__UTCL2_RQ_PENDING_MASK 0x00040000L |
6270 | #define GRBM_STATUS2__SDMA_SCH_RQ_PENDING_MASK 0x00080000L |
6271 | #define GRBM_STATUS2__EA_LINK_BUSY_MASK 0x00100000L |
6272 | #define GRBM_STATUS2__SDMA_BUSY_MASK 0x00200000L |
6273 | #define GRBM_STATUS2__SDMA0_RQ_PENDING_MASK 0x00400000L |
6274 | #define GRBM_STATUS2__SDMA1_RQ_PENDING_MASK 0x00800000L |
6275 | #define GRBM_STATUS2__RLC_BUSY_MASK 0x04000000L |
6276 | #define GRBM_STATUS2__TCP_BUSY_MASK 0x08000000L |
6277 | #define GRBM_STATUS2__CPF_BUSY_MASK 0x10000000L |
6278 | #define GRBM_STATUS2__CPC_BUSY_MASK 0x20000000L |
6279 | #define GRBM_STATUS2__CPG_BUSY_MASK 0x40000000L |
6280 | #define GRBM_STATUS2__CPAXI_BUSY_MASK 0x80000000L |
6281 | //GRBM_PWR_CNTL |
6282 | #define GRBM_PWR_CNTL__ALL_REQ_TYPE__SHIFT 0x0 |
6283 | #define GRBM_PWR_CNTL__GFX_REQ_TYPE__SHIFT 0x2 |
6284 | #define GRBM_PWR_CNTL__ALL_RSP_TYPE__SHIFT 0x4 |
6285 | #define GRBM_PWR_CNTL__GFX_RSP_TYPE__SHIFT 0x6 |
6286 | #define GRBM_PWR_CNTL__GFX_REQ_EN__SHIFT 0xe |
6287 | #define GRBM_PWR_CNTL__ALL_REQ_EN__SHIFT 0xf |
6288 | #define GRBM_PWR_CNTL__ALL_REQ_TYPE_MASK 0x00000003L |
6289 | #define GRBM_PWR_CNTL__GFX_REQ_TYPE_MASK 0x0000000CL |
6290 | #define GRBM_PWR_CNTL__ALL_RSP_TYPE_MASK 0x00000030L |
6291 | #define GRBM_PWR_CNTL__GFX_RSP_TYPE_MASK 0x000000C0L |
6292 | #define GRBM_PWR_CNTL__GFX_REQ_EN_MASK 0x00004000L |
6293 | #define GRBM_PWR_CNTL__ALL_REQ_EN_MASK 0x00008000L |
6294 | //GRBM_STATUS |
6295 | #define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL__SHIFT 0x0 |
6296 | #define GRBM_STATUS__RSMU_RQ_PENDING__SHIFT 0x5 |
6297 | #define GRBM_STATUS__SDMA_RQ_PENDING__SHIFT 0x6 |
6298 | #define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING__SHIFT 0x7 |
6299 | #define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING__SHIFT 0x8 |
6300 | #define GRBM_STATUS__GDS_DMA_RQ_PENDING__SHIFT 0x9 |
6301 | #define GRBM_STATUS__DB_CLEAN__SHIFT 0xc |
6302 | #define GRBM_STATUS__CB_CLEAN__SHIFT 0xd |
6303 | #define GRBM_STATUS__TA_BUSY__SHIFT 0xe |
6304 | #define GRBM_STATUS__GDS_BUSY__SHIFT 0xf |
6305 | #define GRBM_STATUS__GE_BUSY_NO_DMA__SHIFT 0x10 |
6306 | #define GRBM_STATUS__SX_BUSY__SHIFT 0x14 |
6307 | #define GRBM_STATUS__GE_BUSY__SHIFT 0x15 |
6308 | #define GRBM_STATUS__SPI_BUSY__SHIFT 0x16 |
6309 | #define GRBM_STATUS__BCI_BUSY__SHIFT 0x17 |
6310 | #define GRBM_STATUS__SC_BUSY__SHIFT 0x18 |
6311 | #define GRBM_STATUS__PA_BUSY__SHIFT 0x19 |
6312 | #define GRBM_STATUS__DB_BUSY__SHIFT 0x1a |
6313 | #define GRBM_STATUS__ANY_ACTIVE__SHIFT 0x1b |
6314 | #define GRBM_STATUS__CP_COHERENCY_BUSY__SHIFT 0x1c |
6315 | #define GRBM_STATUS__CP_BUSY__SHIFT 0x1d |
6316 | #define GRBM_STATUS__CB_BUSY__SHIFT 0x1e |
6317 | #define GRBM_STATUS__GUI_ACTIVE__SHIFT 0x1f |
6318 | #define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL_MASK 0x0000000FL |
6319 | #define GRBM_STATUS__RSMU_RQ_PENDING_MASK 0x00000020L |
6320 | #define GRBM_STATUS__SDMA_RQ_PENDING_MASK 0x00000040L |
6321 | #define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING_MASK 0x00000080L |
6322 | #define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING_MASK 0x00000100L |
6323 | #define GRBM_STATUS__GDS_DMA_RQ_PENDING_MASK 0x00000200L |
6324 | #define GRBM_STATUS__DB_CLEAN_MASK 0x00001000L |
6325 | #define GRBM_STATUS__CB_CLEAN_MASK 0x00002000L |
6326 | #define GRBM_STATUS__TA_BUSY_MASK 0x00004000L |
6327 | #define GRBM_STATUS__GDS_BUSY_MASK 0x00008000L |
6328 | #define GRBM_STATUS__GE_BUSY_NO_DMA_MASK 0x00010000L |
6329 | #define GRBM_STATUS__SX_BUSY_MASK 0x00100000L |
6330 | #define GRBM_STATUS__GE_BUSY_MASK 0x00200000L |
6331 | #define GRBM_STATUS__SPI_BUSY_MASK 0x00400000L |
6332 | #define GRBM_STATUS__BCI_BUSY_MASK 0x00800000L |
6333 | #define GRBM_STATUS__SC_BUSY_MASK 0x01000000L |
6334 | #define GRBM_STATUS__PA_BUSY_MASK 0x02000000L |
6335 | #define GRBM_STATUS__DB_BUSY_MASK 0x04000000L |
6336 | #define GRBM_STATUS__ANY_ACTIVE_MASK 0x08000000L |
6337 | #define GRBM_STATUS__CP_COHERENCY_BUSY_MASK 0x10000000L |
6338 | #define GRBM_STATUS__CP_BUSY_MASK 0x20000000L |
6339 | #define GRBM_STATUS__CB_BUSY_MASK 0x40000000L |
6340 | #define GRBM_STATUS__GUI_ACTIVE_MASK 0x80000000L |
6341 | //GRBM_STATUS_SE0 |
6342 | #define GRBM_STATUS_SE0__DB_CLEAN__SHIFT 0x1 |
6343 | #define GRBM_STATUS_SE0__CB_CLEAN__SHIFT 0x2 |
6344 | #define GRBM_STATUS_SE0__UTCL1_BUSY__SHIFT 0x3 |
6345 | #define GRBM_STATUS_SE0__TCP_BUSY__SHIFT 0x4 |
6346 | #define GRBM_STATUS_SE0__GL1CC_BUSY__SHIFT 0x5 |
6347 | #define GRBM_STATUS_SE0__GL1H_BUSY__SHIFT 0x6 |
6348 | #define GRBM_STATUS_SE0__PC_BUSY__SHIFT 0x7 |
6349 | #define GRBM_STATUS_SE0__SEDC_BUSY__SHIFT 0x8 |
6350 | #define GRBM_STATUS_SE0__RMI_BUSY__SHIFT 0x15 |
6351 | #define GRBM_STATUS_SE0__BCI_BUSY__SHIFT 0x16 |
6352 | #define GRBM_STATUS_SE0__PA_BUSY__SHIFT 0x18 |
6353 | #define GRBM_STATUS_SE0__TA_BUSY__SHIFT 0x19 |
6354 | #define GRBM_STATUS_SE0__SX_BUSY__SHIFT 0x1a |
6355 | #define GRBM_STATUS_SE0__SPI_BUSY__SHIFT 0x1b |
6356 | #define GRBM_STATUS_SE0__SC_BUSY__SHIFT 0x1d |
6357 | #define GRBM_STATUS_SE0__DB_BUSY__SHIFT 0x1e |
6358 | #define GRBM_STATUS_SE0__CB_BUSY__SHIFT 0x1f |
6359 | #define GRBM_STATUS_SE0__DB_CLEAN_MASK 0x00000002L |
6360 | #define GRBM_STATUS_SE0__CB_CLEAN_MASK 0x00000004L |
6361 | #define GRBM_STATUS_SE0__UTCL1_BUSY_MASK 0x00000008L |
6362 | #define GRBM_STATUS_SE0__TCP_BUSY_MASK 0x00000010L |
6363 | #define GRBM_STATUS_SE0__GL1CC_BUSY_MASK 0x00000020L |
6364 | #define GRBM_STATUS_SE0__GL1H_BUSY_MASK 0x00000040L |
6365 | #define GRBM_STATUS_SE0__PC_BUSY_MASK 0x00000080L |
6366 | #define GRBM_STATUS_SE0__SEDC_BUSY_MASK 0x00000100L |
6367 | #define GRBM_STATUS_SE0__RMI_BUSY_MASK 0x00200000L |
6368 | #define GRBM_STATUS_SE0__BCI_BUSY_MASK 0x00400000L |
6369 | #define GRBM_STATUS_SE0__PA_BUSY_MASK 0x01000000L |
6370 | #define GRBM_STATUS_SE0__TA_BUSY_MASK 0x02000000L |
6371 | #define GRBM_STATUS_SE0__SX_BUSY_MASK 0x04000000L |
6372 | #define GRBM_STATUS_SE0__SPI_BUSY_MASK 0x08000000L |
6373 | #define GRBM_STATUS_SE0__SC_BUSY_MASK 0x20000000L |
6374 | #define GRBM_STATUS_SE0__DB_BUSY_MASK 0x40000000L |
6375 | #define GRBM_STATUS_SE0__CB_BUSY_MASK 0x80000000L |
6376 | //GRBM_STATUS_SE1 |
6377 | #define GRBM_STATUS_SE1__DB_CLEAN__SHIFT 0x1 |
6378 | #define GRBM_STATUS_SE1__CB_CLEAN__SHIFT 0x2 |
6379 | #define GRBM_STATUS_SE1__UTCL1_BUSY__SHIFT 0x3 |
6380 | #define GRBM_STATUS_SE1__TCP_BUSY__SHIFT 0x4 |
6381 | #define GRBM_STATUS_SE1__GL1CC_BUSY__SHIFT 0x5 |
6382 | #define GRBM_STATUS_SE1__GL1H_BUSY__SHIFT 0x6 |
6383 | #define GRBM_STATUS_SE1__PC_BUSY__SHIFT 0x7 |
6384 | #define GRBM_STATUS_SE1__SEDC_BUSY__SHIFT 0x8 |
6385 | #define GRBM_STATUS_SE1__RMI_BUSY__SHIFT 0x15 |
6386 | #define GRBM_STATUS_SE1__BCI_BUSY__SHIFT 0x16 |
6387 | #define GRBM_STATUS_SE1__PA_BUSY__SHIFT 0x18 |
6388 | #define GRBM_STATUS_SE1__TA_BUSY__SHIFT 0x19 |
6389 | #define GRBM_STATUS_SE1__SX_BUSY__SHIFT 0x1a |
6390 | #define GRBM_STATUS_SE1__SPI_BUSY__SHIFT 0x1b |
6391 | #define GRBM_STATUS_SE1__SC_BUSY__SHIFT 0x1d |
6392 | #define GRBM_STATUS_SE1__DB_BUSY__SHIFT 0x1e |
6393 | #define GRBM_STATUS_SE1__CB_BUSY__SHIFT 0x1f |
6394 | #define GRBM_STATUS_SE1__DB_CLEAN_MASK 0x00000002L |
6395 | #define GRBM_STATUS_SE1__CB_CLEAN_MASK 0x00000004L |
6396 | #define GRBM_STATUS_SE1__UTCL1_BUSY_MASK 0x00000008L |
6397 | #define GRBM_STATUS_SE1__TCP_BUSY_MASK 0x00000010L |
6398 | #define GRBM_STATUS_SE1__GL1CC_BUSY_MASK 0x00000020L |
6399 | #define GRBM_STATUS_SE1__GL1H_BUSY_MASK 0x00000040L |
6400 | #define GRBM_STATUS_SE1__PC_BUSY_MASK 0x00000080L |
6401 | #define GRBM_STATUS_SE1__SEDC_BUSY_MASK 0x00000100L |
6402 | #define GRBM_STATUS_SE1__RMI_BUSY_MASK 0x00200000L |
6403 | #define GRBM_STATUS_SE1__BCI_BUSY_MASK 0x00400000L |
6404 | #define GRBM_STATUS_SE1__PA_BUSY_MASK 0x01000000L |
6405 | #define GRBM_STATUS_SE1__TA_BUSY_MASK 0x02000000L |
6406 | #define GRBM_STATUS_SE1__SX_BUSY_MASK 0x04000000L |
6407 | #define GRBM_STATUS_SE1__SPI_BUSY_MASK 0x08000000L |
6408 | #define GRBM_STATUS_SE1__SC_BUSY_MASK 0x20000000L |
6409 | #define GRBM_STATUS_SE1__DB_BUSY_MASK 0x40000000L |
6410 | #define GRBM_STATUS_SE1__CB_BUSY_MASK 0x80000000L |
6411 | //GRBM_STATUS3 |
6412 | #define GRBM_STATUS3__GRBM_RLC_INTR_CREDIT_PENDING__SHIFT 0x5 |
6413 | #define GRBM_STATUS3__GRBM_CPF_INTR_CREDIT_PENDING__SHIFT 0x7 |
6414 | #define GRBM_STATUS3__MESPIPE0_RQ_PENDING__SHIFT 0x8 |
6415 | #define GRBM_STATUS3__MESPIPE1_RQ_PENDING__SHIFT 0x9 |
6416 | #define GRBM_STATUS3__PH_BUSY__SHIFT 0xd |
6417 | #define GRBM_STATUS3__CH_BUSY__SHIFT 0xe |
6418 | #define GRBM_STATUS3__GL2CC_BUSY__SHIFT 0xf |
6419 | #define GRBM_STATUS3__GL1CC_BUSY__SHIFT 0x10 |
6420 | #define GRBM_STATUS3__SEDC_BUSY__SHIFT 0x19 |
6421 | #define GRBM_STATUS3__PC_BUSY__SHIFT 0x1a |
6422 | #define GRBM_STATUS3__GL1H_BUSY__SHIFT 0x1b |
6423 | #define GRBM_STATUS3__GUS_LINK_BUSY__SHIFT 0x1c |
6424 | #define GRBM_STATUS3__GUS_BUSY__SHIFT 0x1d |
6425 | #define GRBM_STATUS3__UTCL1_BUSY__SHIFT 0x1e |
6426 | #define GRBM_STATUS3__PMM_BUSY__SHIFT 0x1f |
6427 | #define GRBM_STATUS3__GRBM_RLC_INTR_CREDIT_PENDING_MASK 0x00000020L |
6428 | #define GRBM_STATUS3__GRBM_CPF_INTR_CREDIT_PENDING_MASK 0x00000080L |
6429 | #define GRBM_STATUS3__MESPIPE0_RQ_PENDING_MASK 0x00000100L |
6430 | #define GRBM_STATUS3__MESPIPE1_RQ_PENDING_MASK 0x00000200L |
6431 | #define GRBM_STATUS3__PH_BUSY_MASK 0x00002000L |
6432 | #define GRBM_STATUS3__CH_BUSY_MASK 0x00004000L |
6433 | #define GRBM_STATUS3__GL2CC_BUSY_MASK 0x00008000L |
6434 | #define GRBM_STATUS3__GL1CC_BUSY_MASK 0x00010000L |
6435 | #define GRBM_STATUS3__SEDC_BUSY_MASK 0x02000000L |
6436 | #define GRBM_STATUS3__PC_BUSY_MASK 0x04000000L |
6437 | #define GRBM_STATUS3__GL1H_BUSY_MASK 0x08000000L |
6438 | #define GRBM_STATUS3__GUS_LINK_BUSY_MASK 0x10000000L |
6439 | #define GRBM_STATUS3__GUS_BUSY_MASK 0x20000000L |
6440 | #define GRBM_STATUS3__UTCL1_BUSY_MASK 0x40000000L |
6441 | #define GRBM_STATUS3__PMM_BUSY_MASK 0x80000000L |
6442 | //GRBM_SOFT_RESET |
6443 | #define GRBM_SOFT_RESET__SOFT_RESET_CP__SHIFT 0x0 |
6444 | #define GRBM_SOFT_RESET__SOFT_RESET_RLC__SHIFT 0x2 |
6445 | #define GRBM_SOFT_RESET__SOFT_RESET_UTCL2__SHIFT 0xf |
6446 | #define GRBM_SOFT_RESET__SOFT_RESET_GFX__SHIFT 0x10 |
6447 | #define GRBM_SOFT_RESET__SOFT_RESET_CPF__SHIFT 0x11 |
6448 | #define GRBM_SOFT_RESET__SOFT_RESET_CPC__SHIFT 0x12 |
6449 | #define GRBM_SOFT_RESET__SOFT_RESET_CPG__SHIFT 0x13 |
6450 | #define GRBM_SOFT_RESET__SOFT_RESET_CAC__SHIFT 0x14 |
6451 | #define GRBM_SOFT_RESET__SOFT_RESET_CPAXI__SHIFT 0x15 |
6452 | #define GRBM_SOFT_RESET__SOFT_RESET_EA__SHIFT 0x16 |
6453 | #define GRBM_SOFT_RESET__SOFT_RESET_SDMA0__SHIFT 0x17 |
6454 | #define GRBM_SOFT_RESET__SOFT_RESET_SDMA1__SHIFT 0x18 |
6455 | #define GRBM_SOFT_RESET__SOFT_RESET_CP_MASK 0x00000001L |
6456 | #define GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK 0x00000004L |
6457 | #define GRBM_SOFT_RESET__SOFT_RESET_UTCL2_MASK 0x00008000L |
6458 | #define GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK 0x00010000L |
6459 | #define GRBM_SOFT_RESET__SOFT_RESET_CPF_MASK 0x00020000L |
6460 | #define GRBM_SOFT_RESET__SOFT_RESET_CPC_MASK 0x00040000L |
6461 | #define GRBM_SOFT_RESET__SOFT_RESET_CPG_MASK 0x00080000L |
6462 | #define GRBM_SOFT_RESET__SOFT_RESET_CAC_MASK 0x00100000L |
6463 | #define GRBM_SOFT_RESET__SOFT_RESET_CPAXI_MASK 0x00200000L |
6464 | #define GRBM_SOFT_RESET__SOFT_RESET_EA_MASK 0x00400000L |
6465 | #define GRBM_SOFT_RESET__SOFT_RESET_SDMA0_MASK 0x00800000L |
6466 | #define GRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK 0x01000000L |
6467 | //GRBM_GFX_CLKEN_CNTL |
6468 | #define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0 |
6469 | #define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8 |
6470 | #define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0x0000000FL |
6471 | #define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x00001F00L |
6472 | //GRBM_WAIT_IDLE_CLOCKS |
6473 | #define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS__SHIFT 0x0 |
6474 | #define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_MASK 0x000000FFL |
6475 | //GRBM_STATUS_SE2 |
6476 | #define GRBM_STATUS_SE2__DB_CLEAN__SHIFT 0x1 |
6477 | #define GRBM_STATUS_SE2__CB_CLEAN__SHIFT 0x2 |
6478 | #define GRBM_STATUS_SE2__UTCL1_BUSY__SHIFT 0x3 |
6479 | #define GRBM_STATUS_SE2__TCP_BUSY__SHIFT 0x4 |
6480 | #define GRBM_STATUS_SE2__GL1CC_BUSY__SHIFT 0x5 |
6481 | #define GRBM_STATUS_SE2__GL1H_BUSY__SHIFT 0x6 |
6482 | #define GRBM_STATUS_SE2__PC_BUSY__SHIFT 0x7 |
6483 | #define GRBM_STATUS_SE2__SEDC_BUSY__SHIFT 0x8 |
6484 | #define GRBM_STATUS_SE2__RMI_BUSY__SHIFT 0x15 |
6485 | #define GRBM_STATUS_SE2__BCI_BUSY__SHIFT 0x16 |
6486 | #define GRBM_STATUS_SE2__PA_BUSY__SHIFT 0x18 |
6487 | #define GRBM_STATUS_SE2__TA_BUSY__SHIFT 0x19 |
6488 | #define GRBM_STATUS_SE2__SX_BUSY__SHIFT 0x1a |
6489 | #define GRBM_STATUS_SE2__SPI_BUSY__SHIFT 0x1b |
6490 | #define GRBM_STATUS_SE2__SC_BUSY__SHIFT 0x1d |
6491 | #define GRBM_STATUS_SE2__DB_BUSY__SHIFT 0x1e |
6492 | #define GRBM_STATUS_SE2__CB_BUSY__SHIFT 0x1f |
6493 | #define GRBM_STATUS_SE2__DB_CLEAN_MASK 0x00000002L |
6494 | #define GRBM_STATUS_SE2__CB_CLEAN_MASK 0x00000004L |
6495 | #define GRBM_STATUS_SE2__UTCL1_BUSY_MASK 0x00000008L |
6496 | #define GRBM_STATUS_SE2__TCP_BUSY_MASK 0x00000010L |
6497 | #define GRBM_STATUS_SE2__GL1CC_BUSY_MASK 0x00000020L |
6498 | #define GRBM_STATUS_SE2__GL1H_BUSY_MASK 0x00000040L |
6499 | #define GRBM_STATUS_SE2__PC_BUSY_MASK 0x00000080L |
6500 | #define GRBM_STATUS_SE2__SEDC_BUSY_MASK 0x00000100L |
6501 | #define GRBM_STATUS_SE2__RMI_BUSY_MASK 0x00200000L |
6502 | #define GRBM_STATUS_SE2__BCI_BUSY_MASK 0x00400000L |
6503 | #define GRBM_STATUS_SE2__PA_BUSY_MASK 0x01000000L |
6504 | #define GRBM_STATUS_SE2__TA_BUSY_MASK 0x02000000L |
6505 | #define GRBM_STATUS_SE2__SX_BUSY_MASK 0x04000000L |
6506 | #define GRBM_STATUS_SE2__SPI_BUSY_MASK 0x08000000L |
6507 | #define GRBM_STATUS_SE2__SC_BUSY_MASK 0x20000000L |
6508 | #define GRBM_STATUS_SE2__DB_BUSY_MASK 0x40000000L |
6509 | #define GRBM_STATUS_SE2__CB_BUSY_MASK 0x80000000L |
6510 | //GRBM_READ_ERROR |
6511 | #define GRBM_READ_ERROR__READ_ADDRESS__SHIFT 0x2 |
6512 | #define GRBM_READ_ERROR__READ_PIPEID__SHIFT 0x14 |
6513 | #define GRBM_READ_ERROR__READ_MEID__SHIFT 0x16 |
6514 | #define GRBM_READ_ERROR__READ_ERROR__SHIFT 0x1f |
6515 | #define GRBM_READ_ERROR__READ_ADDRESS_MASK 0x000FFFFCL |
6516 | #define GRBM_READ_ERROR__READ_PIPEID_MASK 0x00300000L |
6517 | #define GRBM_READ_ERROR__READ_MEID_MASK 0x00C00000L |
6518 | #define GRBM_READ_ERROR__READ_ERROR_MASK 0x80000000L |
6519 | //GRBM_READ_ERROR2 |
6520 | #define GRBM_READ_ERROR2__READ_REQUESTER_MESPIPE0__SHIFT 0x9 |
6521 | #define GRBM_READ_ERROR2__READ_REQUESTER_MESPIPE1__SHIFT 0xa |
6522 | #define GRBM_READ_ERROR2__READ_REQUESTER_MESPIPE2__SHIFT 0xb |
6523 | #define GRBM_READ_ERROR2__READ_REQUESTER_MESPIPE3__SHIFT 0xc |
6524 | #define GRBM_READ_ERROR2__READ_REQUESTER_SDMA0__SHIFT 0xd |
6525 | #define GRBM_READ_ERROR2__READ_REQUESTER_SDMA1__SHIFT 0xe |
6526 | #define GRBM_READ_ERROR2__READ_REQUESTER_RSMU__SHIFT 0x11 |
6527 | #define GRBM_READ_ERROR2__READ_REQUESTER_RLC__SHIFT 0x12 |
6528 | #define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA__SHIFT 0x13 |
6529 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF__SHIFT 0x14 |
6530 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF__SHIFT 0x15 |
6531 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF__SHIFT 0x16 |
6532 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF__SHIFT 0x17 |
6533 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0__SHIFT 0x18 |
6534 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1__SHIFT 0x19 |
6535 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2__SHIFT 0x1a |
6536 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3__SHIFT 0x1b |
6537 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0__SHIFT 0x1c |
6538 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1__SHIFT 0x1d |
6539 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2__SHIFT 0x1e |
6540 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3__SHIFT 0x1f |
6541 | #define GRBM_READ_ERROR2__READ_REQUESTER_MESPIPE0_MASK 0x00000200L |
6542 | #define GRBM_READ_ERROR2__READ_REQUESTER_MESPIPE1_MASK 0x00000400L |
6543 | #define GRBM_READ_ERROR2__READ_REQUESTER_MESPIPE2_MASK 0x00000800L |
6544 | #define GRBM_READ_ERROR2__READ_REQUESTER_MESPIPE3_MASK 0x00001000L |
6545 | #define GRBM_READ_ERROR2__READ_REQUESTER_SDMA0_MASK 0x00002000L |
6546 | #define GRBM_READ_ERROR2__READ_REQUESTER_SDMA1_MASK 0x00004000L |
6547 | #define GRBM_READ_ERROR2__READ_REQUESTER_RSMU_MASK 0x00020000L |
6548 | #define GRBM_READ_ERROR2__READ_REQUESTER_RLC_MASK 0x00040000L |
6549 | #define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA_MASK 0x00080000L |
6550 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF_MASK 0x00100000L |
6551 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF_MASK 0x00200000L |
6552 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF_MASK 0x00400000L |
6553 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF_MASK 0x00800000L |
6554 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0_MASK 0x01000000L |
6555 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1_MASK 0x02000000L |
6556 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2_MASK 0x04000000L |
6557 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3_MASK 0x08000000L |
6558 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0_MASK 0x10000000L |
6559 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1_MASK 0x20000000L |
6560 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2_MASK 0x40000000L |
6561 | #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3_MASK 0x80000000L |
6562 | //GRBM_INT_CNTL |
6563 | #define GRBM_INT_CNTL__RDERR_INT_ENABLE__SHIFT 0x0 |
6564 | #define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE__SHIFT 0x13 |
6565 | #define GRBM_INT_CNTL__RDERR_INT_ENABLE_MASK 0x00000001L |
6566 | #define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE_MASK 0x00080000L |
6567 | //GRBM_TRAP_OP |
6568 | #define GRBM_TRAP_OP__RW__SHIFT 0x0 |
6569 | #define GRBM_TRAP_OP__RW_MASK 0x00000001L |
6570 | //GRBM_TRAP_ADDR |
6571 | #define GRBM_TRAP_ADDR__DATA__SHIFT 0x0 |
6572 | #define GRBM_TRAP_ADDR__DATA_MASK 0x0003FFFFL |
6573 | //GRBM_TRAP_ADDR_MSK |
6574 | #define GRBM_TRAP_ADDR_MSK__DATA__SHIFT 0x0 |
6575 | #define GRBM_TRAP_ADDR_MSK__DATA_MASK 0x0003FFFFL |
6576 | //GRBM_TRAP_WD |
6577 | #define GRBM_TRAP_WD__DATA__SHIFT 0x0 |
6578 | #define GRBM_TRAP_WD__DATA_MASK 0xFFFFFFFFL |
6579 | //GRBM_TRAP_WD_MSK |
6580 | #define GRBM_TRAP_WD_MSK__DATA__SHIFT 0x0 |
6581 | #define GRBM_TRAP_WD_MSK__DATA_MASK 0xFFFFFFFFL |
6582 | //GRBM_DSM_BYPASS |
6583 | #define GRBM_DSM_BYPASS__BYPASS_BITS__SHIFT 0x0 |
6584 | #define GRBM_DSM_BYPASS__BYPASS_EN__SHIFT 0x2 |
6585 | #define GRBM_DSM_BYPASS__BYPASS_BITS_MASK 0x00000003L |
6586 | #define GRBM_DSM_BYPASS__BYPASS_EN_MASK 0x00000004L |
6587 | //GRBM_WRITE_ERROR |
6588 | #define GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC__SHIFT 0x0 |
6589 | #define GRBM_WRITE_ERROR__WRITE_REQUESTER_RSMU__SHIFT 0x1 |
6590 | #define GRBM_WRITE_ERROR__WRITE_SSRCID__SHIFT 0x2 |
6591 | #define GRBM_WRITE_ERROR__WRITE_VFID__SHIFT 0x8 |
6592 | #define GRBM_WRITE_ERROR__WRITE_VF__SHIFT 0xc |
6593 | #define GRBM_WRITE_ERROR__WRITE_VMID__SHIFT 0xd |
6594 | #define GRBM_WRITE_ERROR__TMZ__SHIFT 0x11 |
6595 | #define GRBM_WRITE_ERROR__CP_SECURE_WR_ILLEGAL__SHIFT 0x12 |
6596 | #define GRBM_WRITE_ERROR__WRITE_PIPEID__SHIFT 0x14 |
6597 | #define GRBM_WRITE_ERROR__WRITE_MEID__SHIFT 0x16 |
6598 | #define GRBM_WRITE_ERROR__WRITE_ERROR__SHIFT 0x1f |
6599 | #define GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC_MASK 0x00000001L |
6600 | #define GRBM_WRITE_ERROR__WRITE_REQUESTER_RSMU_MASK 0x00000002L |
6601 | #define GRBM_WRITE_ERROR__WRITE_SSRCID_MASK 0x0000003CL |
6602 | #define GRBM_WRITE_ERROR__WRITE_VFID_MASK 0x00000F00L |
6603 | #define GRBM_WRITE_ERROR__WRITE_VF_MASK 0x00001000L |
6604 | #define GRBM_WRITE_ERROR__WRITE_VMID_MASK 0x0001E000L |
6605 | #define GRBM_WRITE_ERROR__TMZ_MASK 0x00020000L |
6606 | #define GRBM_WRITE_ERROR__CP_SECURE_WR_ILLEGAL_MASK 0x00040000L |
6607 | #define GRBM_WRITE_ERROR__WRITE_PIPEID_MASK 0x00300000L |
6608 | #define GRBM_WRITE_ERROR__WRITE_MEID_MASK 0x00C00000L |
6609 | #define GRBM_WRITE_ERROR__WRITE_ERROR_MASK 0x80000000L |
6610 | //GRBM_CHIP_REVISION |
6611 | #define GRBM_CHIP_REVISION__CHIP_REVISION__SHIFT 0x0 |
6612 | #define GRBM_CHIP_REVISION__CHIP_REVISION_MASK 0x000000FFL |
6613 | //GRBM_RSMU_CFG |
6614 | #define GRBM_RSMU_CFG__APERTURE_ID__SHIFT 0x0 |
6615 | #define GRBM_RSMU_CFG__QOS__SHIFT 0xc |
6616 | #define GRBM_RSMU_CFG__POSTED_WR__SHIFT 0x10 |
6617 | #define GRBM_RSMU_CFG__DEBUG_MASK__SHIFT 0x11 |
6618 | #define GRBM_RSMU_CFG__APERTURE_ID_MASK 0x00000FFFL |
6619 | #define GRBM_RSMU_CFG__QOS_MASK 0x0000F000L |
6620 | #define GRBM_RSMU_CFG__POSTED_WR_MASK 0x00010000L |
6621 | #define GRBM_RSMU_CFG__DEBUG_MASK_MASK 0x00020000L |
6622 | //GRBM_IH_CREDIT |
6623 | #define GRBM_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 |
6624 | #define GRBM_IH_CREDIT__IH_CLIENT_ID__SHIFT 0x10 |
6625 | #define GRBM_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L |
6626 | #define GRBM_IH_CREDIT__IH_CLIENT_ID_MASK 0x00FF0000L |
6627 | //GRBM_PWR_CNTL2 |
6628 | #define GRBM_PWR_CNTL2__PWR_REQUEST_HALT__SHIFT 0x10 |
6629 | #define GRBM_PWR_CNTL2__PWR_GFX3D_REQUEST_HALT__SHIFT 0x14 |
6630 | #define GRBM_PWR_CNTL2__PWR_REQUEST_HALT_MASK 0x00010000L |
6631 | #define GRBM_PWR_CNTL2__PWR_GFX3D_REQUEST_HALT_MASK 0x00100000L |
6632 | //GRBM_UTCL2_INVAL_RANGE_START |
6633 | #define GRBM_UTCL2_INVAL_RANGE_START__DATA__SHIFT 0x0 |
6634 | #define GRBM_UTCL2_INVAL_RANGE_START__DATA_MASK 0x0003FFFFL |
6635 | //GRBM_UTCL2_INVAL_RANGE_END |
6636 | #define GRBM_UTCL2_INVAL_RANGE_END__DATA__SHIFT 0x0 |
6637 | #define GRBM_UTCL2_INVAL_RANGE_END__DATA_MASK 0x0003FFFFL |
6638 | //GRBM_RSMU_READ_ERROR |
6639 | #define GRBM_RSMU_READ_ERROR__RSMU_READ_ADDRESS__SHIFT 0x2 |
6640 | #define GRBM_RSMU_READ_ERROR__RSMU_READ_VF__SHIFT 0x14 |
6641 | #define GRBM_RSMU_READ_ERROR__RSMU_READ_VFID__SHIFT 0x15 |
6642 | #define GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR_TYPE__SHIFT 0x1b |
6643 | #define GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR__SHIFT 0x1f |
6644 | #define GRBM_RSMU_READ_ERROR__RSMU_READ_ADDRESS_MASK 0x000FFFFCL |
6645 | #define GRBM_RSMU_READ_ERROR__RSMU_READ_VF_MASK 0x00100000L |
6646 | #define GRBM_RSMU_READ_ERROR__RSMU_READ_VFID_MASK 0x07E00000L |
6647 | #define GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR_TYPE_MASK 0x08000000L |
6648 | #define GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR_MASK 0x80000000L |
6649 | //GRBM_INVALID_PIPE |
6650 | #define GRBM_INVALID_PIPE__ADDR__SHIFT 0x2 |
6651 | #define GRBM_INVALID_PIPE__PIPEID__SHIFT 0x14 |
6652 | #define GRBM_INVALID_PIPE__MEID__SHIFT 0x16 |
6653 | #define GRBM_INVALID_PIPE__QUEUEID__SHIFT 0x18 |
6654 | #define GRBM_INVALID_PIPE__SSRCID__SHIFT 0x1b |
6655 | #define GRBM_INVALID_PIPE__INVALID_PIPE__SHIFT 0x1f |
6656 | #define GRBM_INVALID_PIPE__ADDR_MASK 0x000FFFFCL |
6657 | #define GRBM_INVALID_PIPE__PIPEID_MASK 0x00300000L |
6658 | #define GRBM_INVALID_PIPE__MEID_MASK 0x00C00000L |
6659 | #define GRBM_INVALID_PIPE__QUEUEID_MASK 0x07000000L |
6660 | #define GRBM_INVALID_PIPE__SSRCID_MASK 0x78000000L |
6661 | #define GRBM_INVALID_PIPE__INVALID_PIPE_MASK 0x80000000L |
6662 | //GRBM_FENCE_RANGE0 |
6663 | #define GRBM_FENCE_RANGE0__START__SHIFT 0x0 |
6664 | #define GRBM_FENCE_RANGE0__END__SHIFT 0x10 |
6665 | #define GRBM_FENCE_RANGE0__START_MASK 0x0000FFFFL |
6666 | #define GRBM_FENCE_RANGE0__END_MASK 0xFFFF0000L |
6667 | //GRBM_FENCE_RANGE1 |
6668 | #define GRBM_FENCE_RANGE1__START__SHIFT 0x0 |
6669 | #define GRBM_FENCE_RANGE1__END__SHIFT 0x10 |
6670 | #define GRBM_FENCE_RANGE1__START_MASK 0x0000FFFFL |
6671 | #define GRBM_FENCE_RANGE1__END_MASK 0xFFFF0000L |
6672 | //GRBM_SCRATCH_REG0 |
6673 | #define GRBM_SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x0 |
6674 | #define GRBM_SCRATCH_REG0__SCRATCH_REG0_MASK 0xFFFFFFFFL |
6675 | //GRBM_SCRATCH_REG1 |
6676 | #define GRBM_SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x0 |
6677 | #define GRBM_SCRATCH_REG1__SCRATCH_REG1_MASK 0xFFFFFFFFL |
6678 | //GRBM_SCRATCH_REG2 |
6679 | #define GRBM_SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x0 |
6680 | #define GRBM_SCRATCH_REG2__SCRATCH_REG2_MASK 0xFFFFFFFFL |
6681 | //GRBM_SCRATCH_REG3 |
6682 | #define GRBM_SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x0 |
6683 | #define GRBM_SCRATCH_REG3__SCRATCH_REG3_MASK 0xFFFFFFFFL |
6684 | //GRBM_SCRATCH_REG4 |
6685 | #define GRBM_SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x0 |
6686 | #define GRBM_SCRATCH_REG4__SCRATCH_REG4_MASK 0xFFFFFFFFL |
6687 | //GRBM_SCRATCH_REG5 |
6688 | #define GRBM_SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x0 |
6689 | #define GRBM_SCRATCH_REG5__SCRATCH_REG5_MASK 0xFFFFFFFFL |
6690 | //GRBM_SCRATCH_REG6 |
6691 | #define GRBM_SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x0 |
6692 | #define GRBM_SCRATCH_REG6__SCRATCH_REG6_MASK 0xFFFFFFFFL |
6693 | //GRBM_SCRATCH_REG7 |
6694 | #define GRBM_SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x0 |
6695 | #define GRBM_SCRATCH_REG7__SCRATCH_REG7_MASK 0xFFFFFFFFL |
6696 | //VIOLATION_DATA_ASYNC_VF_PROG |
6697 | #define VIOLATION_DATA_ASYNC_VF_PROG__SSRCID__SHIFT 0x0 |
6698 | #define VIOLATION_DATA_ASYNC_VF_PROG__VFID__SHIFT 0x4 |
6699 | #define VIOLATION_DATA_ASYNC_VF_PROG__VIOLATION_ERROR__SHIFT 0x1f |
6700 | #define VIOLATION_DATA_ASYNC_VF_PROG__SSRCID_MASK 0x0000000FL |
6701 | #define VIOLATION_DATA_ASYNC_VF_PROG__VFID_MASK 0x000003F0L |
6702 | #define VIOLATION_DATA_ASYNC_VF_PROG__VIOLATION_ERROR_MASK 0x80000000L |
6703 | |
6704 | |
6705 | // addressBlock: gc_cpdec |
6706 | //CP_CPC_DEBUG_CNTL |
6707 | #define CP_CPC_DEBUG_CNTL__DEBUG_INDX__SHIFT 0x0 |
6708 | #define CP_CPC_DEBUG_CNTL__DEBUG_INDX_MASK 0x0000007FL |
6709 | //CP_CPF_DEBUG_CNTL |
6710 | #define CP_CPF_DEBUG_CNTL__DEBUG_INDX__SHIFT 0x0 |
6711 | #define CP_CPF_DEBUG_CNTL__DEBUG_INDX_MASK 0x0000007FL |
6712 | //CP_CPC_STATUS |
6713 | #define CP_CPC_STATUS__MEC1_BUSY__SHIFT 0x0 |
6714 | #define CP_CPC_STATUS__MEC2_BUSY__SHIFT 0x1 |
6715 | #define CP_CPC_STATUS__DC0_BUSY__SHIFT 0x2 |
6716 | #define CP_CPC_STATUS__DC1_BUSY__SHIFT 0x3 |
6717 | #define CP_CPC_STATUS__RCIU1_BUSY__SHIFT 0x4 |
6718 | #define CP_CPC_STATUS__RCIU2_BUSY__SHIFT 0x5 |
6719 | #define CP_CPC_STATUS__ROQ1_BUSY__SHIFT 0x6 |
6720 | #define CP_CPC_STATUS__ROQ2_BUSY__SHIFT 0x7 |
6721 | #define CP_CPC_STATUS__TCIU_BUSY__SHIFT 0xa |
6722 | #define CP_CPC_STATUS__SCRATCH_RAM_BUSY__SHIFT 0xb |
6723 | #define CP_CPC_STATUS__QU_BUSY__SHIFT 0xc |
6724 | #define CP_CPC_STATUS__UTCL2IU_BUSY__SHIFT 0xd |
6725 | #define CP_CPC_STATUS__SAVE_RESTORE_BUSY__SHIFT 0xe |
6726 | #define CP_CPC_STATUS__GCRIU_BUSY__SHIFT 0xf |
6727 | #define CP_CPC_STATUS__MES_BUSY__SHIFT 0x10 |
6728 | #define CP_CPC_STATUS__MES_SCRATCH_RAM_BUSY__SHIFT 0x11 |
6729 | #define CP_CPC_STATUS__RCIU3_BUSY__SHIFT 0x12 |
6730 | #define CP_CPC_STATUS__MES_INSTRUCTION_CACHE_BUSY__SHIFT 0x13 |
6731 | #define CP_CPC_STATUS__MES_DATA_CACHE_BUSY__SHIFT 0x14 |
6732 | #define CP_CPC_STATUS__MEC_DATA_CACHE_BUSY__SHIFT 0x15 |
6733 | #define CP_CPC_STATUS__CPG_CPC_BUSY__SHIFT 0x1d |
6734 | #define CP_CPC_STATUS__CPF_CPC_BUSY__SHIFT 0x1e |
6735 | #define CP_CPC_STATUS__CPC_BUSY__SHIFT 0x1f |
6736 | #define CP_CPC_STATUS__MEC1_BUSY_MASK 0x00000001L |
6737 | #define CP_CPC_STATUS__MEC2_BUSY_MASK 0x00000002L |
6738 | #define CP_CPC_STATUS__DC0_BUSY_MASK 0x00000004L |
6739 | #define CP_CPC_STATUS__DC1_BUSY_MASK 0x00000008L |
6740 | #define CP_CPC_STATUS__RCIU1_BUSY_MASK 0x00000010L |
6741 | #define CP_CPC_STATUS__RCIU2_BUSY_MASK 0x00000020L |
6742 | #define CP_CPC_STATUS__ROQ1_BUSY_MASK 0x00000040L |
6743 | #define CP_CPC_STATUS__ROQ2_BUSY_MASK 0x00000080L |
6744 | #define CP_CPC_STATUS__TCIU_BUSY_MASK 0x00000400L |
6745 | #define CP_CPC_STATUS__SCRATCH_RAM_BUSY_MASK 0x00000800L |
6746 | #define CP_CPC_STATUS__QU_BUSY_MASK 0x00001000L |
6747 | #define CP_CPC_STATUS__UTCL2IU_BUSY_MASK 0x00002000L |
6748 | #define CP_CPC_STATUS__SAVE_RESTORE_BUSY_MASK 0x00004000L |
6749 | #define CP_CPC_STATUS__GCRIU_BUSY_MASK 0x00008000L |
6750 | #define CP_CPC_STATUS__MES_BUSY_MASK 0x00010000L |
6751 | #define CP_CPC_STATUS__MES_SCRATCH_RAM_BUSY_MASK 0x00020000L |
6752 | #define CP_CPC_STATUS__RCIU3_BUSY_MASK 0x00040000L |
6753 | #define CP_CPC_STATUS__MES_INSTRUCTION_CACHE_BUSY_MASK 0x00080000L |
6754 | #define CP_CPC_STATUS__MES_DATA_CACHE_BUSY_MASK 0x00100000L |
6755 | #define CP_CPC_STATUS__MEC_DATA_CACHE_BUSY_MASK 0x00200000L |
6756 | #define CP_CPC_STATUS__CPG_CPC_BUSY_MASK 0x20000000L |
6757 | #define CP_CPC_STATUS__CPF_CPC_BUSY_MASK 0x40000000L |
6758 | #define CP_CPC_STATUS__CPC_BUSY_MASK 0x80000000L |
6759 | //CP_CPC_BUSY_STAT |
6760 | #define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY__SHIFT 0x0 |
6761 | #define CP_CPC_BUSY_STAT__MEC1_SEMAPHORE_BUSY__SHIFT 0x1 |
6762 | #define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY__SHIFT 0x2 |
6763 | #define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY__SHIFT 0x3 |
6764 | #define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY__SHIFT 0x4 |
6765 | #define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY__SHIFT 0x5 |
6766 | #define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY__SHIFT 0x6 |
6767 | #define CP_CPC_BUSY_STAT__MEC1_TC_BUSY__SHIFT 0x7 |
6768 | #define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY__SHIFT 0x8 |
6769 | #define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY__SHIFT 0x9 |
6770 | #define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY__SHIFT 0xa |
6771 | #define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY__SHIFT 0xb |
6772 | #define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY__SHIFT 0xc |
6773 | #define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY__SHIFT 0xd |
6774 | #define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY__SHIFT 0x10 |
6775 | #define CP_CPC_BUSY_STAT__MEC2_SEMAPHORE_BUSY__SHIFT 0x11 |
6776 | #define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY__SHIFT 0x12 |
6777 | #define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY__SHIFT 0x13 |
6778 | #define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY__SHIFT 0x14 |
6779 | #define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY__SHIFT 0x15 |
6780 | #define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY__SHIFT 0x16 |
6781 | #define CP_CPC_BUSY_STAT__MEC2_TC_BUSY__SHIFT 0x17 |
6782 | #define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY__SHIFT 0x18 |
6783 | #define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY__SHIFT 0x19 |
6784 | #define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY__SHIFT 0x1a |
6785 | #define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY__SHIFT 0x1b |
6786 | #define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY__SHIFT 0x1c |
6787 | #define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY__SHIFT 0x1d |
6788 | #define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY_MASK 0x00000001L |
6789 | #define CP_CPC_BUSY_STAT__MEC1_SEMAPHORE_BUSY_MASK 0x00000002L |
6790 | #define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY_MASK 0x00000004L |
6791 | #define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY_MASK 0x00000008L |
6792 | #define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY_MASK 0x00000010L |
6793 | #define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY_MASK 0x00000020L |
6794 | #define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY_MASK 0x00000040L |
6795 | #define CP_CPC_BUSY_STAT__MEC1_TC_BUSY_MASK 0x00000080L |
6796 | #define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY_MASK 0x00000100L |
6797 | #define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY_MASK 0x00000200L |
6798 | #define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY_MASK 0x00000400L |
6799 | #define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY_MASK 0x00000800L |
6800 | #define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY_MASK 0x00001000L |
6801 | #define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY_MASK 0x00002000L |
6802 | #define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY_MASK 0x00010000L |
6803 | #define CP_CPC_BUSY_STAT__MEC2_SEMAPHORE_BUSY_MASK 0x00020000L |
6804 | #define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY_MASK 0x00040000L |
6805 | #define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY_MASK 0x00080000L |
6806 | #define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY_MASK 0x00100000L |
6807 | #define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY_MASK 0x00200000L |
6808 | #define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY_MASK 0x00400000L |
6809 | #define CP_CPC_BUSY_STAT__MEC2_TC_BUSY_MASK 0x00800000L |
6810 | #define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY_MASK 0x01000000L |
6811 | #define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY_MASK 0x02000000L |
6812 | #define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY_MASK 0x04000000L |
6813 | #define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY_MASK 0x08000000L |
6814 | #define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY_MASK 0x10000000L |
6815 | #define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY_MASK 0x20000000L |
6816 | //CP_CPC_STALLED_STAT1 |
6817 | #define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL__SHIFT 0x3 |
6818 | #define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION__SHIFT 0x4 |
6819 | #define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL__SHIFT 0x6 |
6820 | #define CP_CPC_STALLED_STAT1__TCIU_WAITING_ON_TAGS__SHIFT 0x7 |
6821 | #define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET__SHIFT 0x8 |
6822 | #define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU__SHIFT 0x9 |
6823 | #define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ__SHIFT 0xa |
6824 | #define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA__SHIFT 0xd |
6825 | #define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET__SHIFT 0x10 |
6826 | #define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU__SHIFT 0x11 |
6827 | #define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ__SHIFT 0x12 |
6828 | #define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA__SHIFT 0x15 |
6829 | #define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE__SHIFT 0x16 |
6830 | #define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS__SHIFT 0x17 |
6831 | #define CP_CPC_STALLED_STAT1__UTCL1_WAITING_ON_TRANS__SHIFT 0x18 |
6832 | #define CP_CPC_STALLED_STAT1__GCRIU_WAITING_ON_FREE__SHIFT 0x19 |
6833 | #define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL_MASK 0x00000008L |
6834 | #define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION_MASK 0x00000010L |
6835 | #define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL_MASK 0x00000040L |
6836 | #define CP_CPC_STALLED_STAT1__TCIU_WAITING_ON_TAGS_MASK 0x00000080L |
6837 | #define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET_MASK 0x00000100L |
6838 | #define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_MASK 0x00000200L |
6839 | #define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ_MASK 0x00000400L |
6840 | #define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA_MASK 0x00002000L |
6841 | #define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET_MASK 0x00010000L |
6842 | #define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_MASK 0x00020000L |
6843 | #define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ_MASK 0x00040000L |
6844 | #define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA_MASK 0x00200000L |
6845 | #define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE_MASK 0x00400000L |
6846 | #define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS_MASK 0x00800000L |
6847 | #define CP_CPC_STALLED_STAT1__UTCL1_WAITING_ON_TRANS_MASK 0x01000000L |
6848 | #define CP_CPC_STALLED_STAT1__GCRIU_WAITING_ON_FREE_MASK 0x02000000L |
6849 | //CP_CPF_STATUS |
6850 | #define CP_CPF_STATUS__POST_WPTR_GFX_BUSY__SHIFT 0x0 |
6851 | #define CP_CPF_STATUS__CSF_BUSY__SHIFT 0x1 |
6852 | #define CP_CPF_STATUS__ROQ_ALIGN_BUSY__SHIFT 0x4 |
6853 | #define CP_CPF_STATUS__ROQ_RING_BUSY__SHIFT 0x5 |
6854 | #define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY__SHIFT 0x6 |
6855 | #define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY__SHIFT 0x7 |
6856 | #define CP_CPF_STATUS__ROQ_STATE_BUSY__SHIFT 0x8 |
6857 | #define CP_CPF_STATUS__ROQ_CE_RING_BUSY__SHIFT 0x9 |
6858 | #define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY__SHIFT 0xa |
6859 | #define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY__SHIFT 0xb |
6860 | #define CP_CPF_STATUS__SEMAPHORE_BUSY__SHIFT 0xc |
6861 | #define CP_CPF_STATUS__INTERRUPT_BUSY__SHIFT 0xd |
6862 | #define CP_CPF_STATUS__TCIU_BUSY__SHIFT 0xe |
6863 | #define CP_CPF_STATUS__HQD_BUSY__SHIFT 0xf |
6864 | #define CP_CPF_STATUS__PRT_BUSY__SHIFT 0x10 |
6865 | #define CP_CPF_STATUS__UTCL2IU_BUSY__SHIFT 0x11 |
6866 | #define CP_CPF_STATUS__RCIU_BUSY__SHIFT 0x12 |
6867 | #define CP_CPF_STATUS__RCIU_GFX_BUSY__SHIFT 0x13 |
6868 | #define CP_CPF_STATUS__RCIU_CMP_BUSY__SHIFT 0x14 |
6869 | #define CP_CPF_STATUS__ROQ_DATA_BUSY__SHIFT 0x15 |
6870 | #define CP_CPF_STATUS__ROQ_CE_DATA_BUSY__SHIFT 0x16 |
6871 | #define CP_CPF_STATUS__GCRIU_BUSY__SHIFT 0x17 |
6872 | #define CP_CPF_STATUS__MES_HQD_BUSY__SHIFT 0x18 |
6873 | #define CP_CPF_STATUS__CPF_GFX_BUSY__SHIFT 0x1a |
6874 | #define CP_CPF_STATUS__CPF_CMP_BUSY__SHIFT 0x1b |
6875 | #define CP_CPF_STATUS__GRBM_CPF_STAT_BUSY__SHIFT 0x1c |
6876 | #define CP_CPF_STATUS__CPC_CPF_BUSY__SHIFT 0x1e |
6877 | #define CP_CPF_STATUS__CPF_BUSY__SHIFT 0x1f |
6878 | #define CP_CPF_STATUS__POST_WPTR_GFX_BUSY_MASK 0x00000001L |
6879 | #define CP_CPF_STATUS__CSF_BUSY_MASK 0x00000002L |
6880 | #define CP_CPF_STATUS__ROQ_ALIGN_BUSY_MASK 0x00000010L |
6881 | #define CP_CPF_STATUS__ROQ_RING_BUSY_MASK 0x00000020L |
6882 | #define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY_MASK 0x00000040L |
6883 | #define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY_MASK 0x00000080L |
6884 | #define CP_CPF_STATUS__ROQ_STATE_BUSY_MASK 0x00000100L |
6885 | #define CP_CPF_STATUS__ROQ_CE_RING_BUSY_MASK 0x00000200L |
6886 | #define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY_MASK 0x00000400L |
6887 | #define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY_MASK 0x00000800L |
6888 | #define CP_CPF_STATUS__SEMAPHORE_BUSY_MASK 0x00001000L |
6889 | #define CP_CPF_STATUS__INTERRUPT_BUSY_MASK 0x00002000L |
6890 | #define CP_CPF_STATUS__TCIU_BUSY_MASK 0x00004000L |
6891 | #define CP_CPF_STATUS__HQD_BUSY_MASK 0x00008000L |
6892 | #define CP_CPF_STATUS__PRT_BUSY_MASK 0x00010000L |
6893 | #define CP_CPF_STATUS__UTCL2IU_BUSY_MASK 0x00020000L |
6894 | #define CP_CPF_STATUS__RCIU_BUSY_MASK 0x00040000L |
6895 | #define CP_CPF_STATUS__RCIU_GFX_BUSY_MASK 0x00080000L |
6896 | #define CP_CPF_STATUS__RCIU_CMP_BUSY_MASK 0x00100000L |
6897 | #define CP_CPF_STATUS__ROQ_DATA_BUSY_MASK 0x00200000L |
6898 | #define CP_CPF_STATUS__ROQ_CE_DATA_BUSY_MASK 0x00400000L |
6899 | #define CP_CPF_STATUS__GCRIU_BUSY_MASK 0x00800000L |
6900 | #define CP_CPF_STATUS__MES_HQD_BUSY_MASK 0x01000000L |
6901 | #define CP_CPF_STATUS__CPF_GFX_BUSY_MASK 0x04000000L |
6902 | #define CP_CPF_STATUS__CPF_CMP_BUSY_MASK 0x08000000L |
6903 | #define CP_CPF_STATUS__GRBM_CPF_STAT_BUSY_MASK 0x30000000L |
6904 | #define CP_CPF_STATUS__CPC_CPF_BUSY_MASK 0x40000000L |
6905 | #define CP_CPF_STATUS__CPF_BUSY_MASK 0x80000000L |
6906 | //CP_CPF_BUSY_STAT |
6907 | #define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x0 |
6908 | #define CP_CPF_BUSY_STAT__CSF_RING_BUSY__SHIFT 0x1 |
6909 | #define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY__SHIFT 0x2 |
6910 | #define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY__SHIFT 0x3 |
6911 | #define CP_CPF_BUSY_STAT__CSF_STATE_BUSY__SHIFT 0x4 |
6912 | #define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY__SHIFT 0x5 |
6913 | #define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY__SHIFT 0x6 |
6914 | #define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY__SHIFT 0x7 |
6915 | #define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY__SHIFT 0x8 |
6916 | #define CP_CPF_BUSY_STAT__CSF_DATA_BUSY__SHIFT 0x9 |
6917 | #define CP_CPF_BUSY_STAT__CSF_CE_DATA_BUSY__SHIFT 0xa |
6918 | #define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY__SHIFT 0xb |
6919 | #define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY__SHIFT 0xc |
6920 | #define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY__SHIFT 0xd |
6921 | #define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY__SHIFT 0xe |
6922 | #define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY__SHIFT 0xf |
6923 | #define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY__SHIFT 0x10 |
6924 | #define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY__SHIFT 0x11 |
6925 | #define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY__SHIFT 0x12 |
6926 | #define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY__SHIFT 0x13 |
6927 | #define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY__SHIFT 0x14 |
6928 | #define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY__SHIFT 0x15 |
6929 | #define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY__SHIFT 0x16 |
6930 | #define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY__SHIFT 0x17 |
6931 | #define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY__SHIFT 0x18 |
6932 | #define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY__SHIFT 0x19 |
6933 | #define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY__SHIFT 0x1a |
6934 | #define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY__SHIFT 0x1b |
6935 | #define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY__SHIFT 0x1c |
6936 | #define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY__SHIFT 0x1d |
6937 | #define CP_CPF_BUSY_STAT__HQD_PQ_BUSY__SHIFT 0x1e |
6938 | #define CP_CPF_BUSY_STAT__HQD_IB_BUSY__SHIFT 0x1f |
6939 | #define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x00000001L |
6940 | #define CP_CPF_BUSY_STAT__CSF_RING_BUSY_MASK 0x00000002L |
6941 | #define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY_MASK 0x00000004L |
6942 | #define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY_MASK 0x00000008L |
6943 | #define CP_CPF_BUSY_STAT__CSF_STATE_BUSY_MASK 0x00000010L |
6944 | #define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY_MASK 0x00000020L |
6945 | #define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY_MASK 0x00000040L |
6946 | #define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY_MASK 0x00000080L |
6947 | #define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY_MASK 0x00000100L |
6948 | #define CP_CPF_BUSY_STAT__CSF_DATA_BUSY_MASK 0x00000200L |
6949 | #define CP_CPF_BUSY_STAT__CSF_CE_DATA_BUSY_MASK 0x00000400L |
6950 | #define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY_MASK 0x00000800L |
6951 | #define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY_MASK 0x00001000L |
6952 | #define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY_MASK 0x00002000L |
6953 | #define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY_MASK 0x00004000L |
6954 | #define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY_MASK 0x00008000L |
6955 | #define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY_MASK 0x00010000L |
6956 | #define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY_MASK 0x00020000L |
6957 | #define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY_MASK 0x00040000L |
6958 | #define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY_MASK 0x00080000L |
6959 | #define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY_MASK 0x00100000L |
6960 | #define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY_MASK 0x00200000L |
6961 | #define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY_MASK 0x00400000L |
6962 | #define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY_MASK 0x00800000L |
6963 | #define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY_MASK 0x01000000L |
6964 | #define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY_MASK 0x02000000L |
6965 | #define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY_MASK 0x04000000L |
6966 | #define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY_MASK 0x08000000L |
6967 | #define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY_MASK 0x10000000L |
6968 | #define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY_MASK 0x20000000L |
6969 | #define CP_CPF_BUSY_STAT__HQD_PQ_BUSY_MASK 0x40000000L |
6970 | #define CP_CPF_BUSY_STAT__HQD_IB_BUSY_MASK 0x80000000L |
6971 | //CP_CPF_STALLED_STAT1 |
6972 | #define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA__SHIFT 0x0 |
6973 | #define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA__SHIFT 0x1 |
6974 | #define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA__SHIFT 0x2 |
6975 | #define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA__SHIFT 0x3 |
6976 | #define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE__SHIFT 0x5 |
6977 | #define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS__SHIFT 0x6 |
6978 | #define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE__SHIFT 0x7 |
6979 | #define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS__SHIFT 0x8 |
6980 | #define CP_CPF_STALLED_STAT1__GFX_UTCL1_WAITING_ON_TRANS__SHIFT 0x9 |
6981 | #define CP_CPF_STALLED_STAT1__CMP_UTCL1_WAITING_ON_TRANS__SHIFT 0xa |
6982 | #define CP_CPF_STALLED_STAT1__RCIU_WAITING_ON_FREE__SHIFT 0xb |
6983 | #define CP_CPF_STALLED_STAT1__DATA_FETCHING_DATA__SHIFT 0xc |
6984 | #define CP_CPF_STALLED_STAT1__GCRIU_WAIT_ON_FREE__SHIFT 0xd |
6985 | #define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA_MASK 0x00000001L |
6986 | #define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA_MASK 0x00000002L |
6987 | #define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA_MASK 0x00000004L |
6988 | #define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA_MASK 0x00000008L |
6989 | #define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE_MASK 0x00000020L |
6990 | #define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS_MASK 0x00000040L |
6991 | #define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE_MASK 0x00000080L |
6992 | #define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS_MASK 0x00000100L |
6993 | #define CP_CPF_STALLED_STAT1__GFX_UTCL1_WAITING_ON_TRANS_MASK 0x00000200L |
6994 | #define CP_CPF_STALLED_STAT1__CMP_UTCL1_WAITING_ON_TRANS_MASK 0x00000400L |
6995 | #define CP_CPF_STALLED_STAT1__RCIU_WAITING_ON_FREE_MASK 0x00000800L |
6996 | #define CP_CPF_STALLED_STAT1__DATA_FETCHING_DATA_MASK 0x00001000L |
6997 | #define CP_CPF_STALLED_STAT1__GCRIU_WAIT_ON_FREE_MASK 0x00002000L |
6998 | //CP_CPC_BUSY_STAT2 |
6999 | #define CP_CPC_BUSY_STAT2__MES_LOAD_BUSY__SHIFT 0x0 |
7000 | #define CP_CPC_BUSY_STAT2__MES_MUTEX_BUSY__SHIFT 0x2 |
7001 | #define CP_CPC_BUSY_STAT2__MES_MESSAGE_BUSY__SHIFT 0x3 |
7002 | #define CP_CPC_BUSY_STAT2__MES_TC_BUSY__SHIFT 0x7 |
7003 | #define CP_CPC_BUSY_STAT2__MES_DMA_BUSY__SHIFT 0x8 |
7004 | #define CP_CPC_BUSY_STAT2__MES_PIPE0_BUSY__SHIFT 0xa |
7005 | #define CP_CPC_BUSY_STAT2__MES_PIPE1_BUSY__SHIFT 0xb |
7006 | #define CP_CPC_BUSY_STAT2__MES_PIPE2_BUSY__SHIFT 0xc |
7007 | #define CP_CPC_BUSY_STAT2__MES_PIPE3_BUSY__SHIFT 0xd |
7008 | #define CP_CPC_BUSY_STAT2__MES_LOAD_BUSY_MASK 0x00000001L |
7009 | #define CP_CPC_BUSY_STAT2__MES_MUTEX_BUSY_MASK 0x00000004L |
7010 | #define CP_CPC_BUSY_STAT2__MES_MESSAGE_BUSY_MASK 0x00000008L |
7011 | #define CP_CPC_BUSY_STAT2__MES_TC_BUSY_MASK 0x00000080L |
7012 | #define CP_CPC_BUSY_STAT2__MES_DMA_BUSY_MASK 0x00000100L |
7013 | #define CP_CPC_BUSY_STAT2__MES_PIPE0_BUSY_MASK 0x00000400L |
7014 | #define CP_CPC_BUSY_STAT2__MES_PIPE1_BUSY_MASK 0x00000800L |
7015 | #define CP_CPC_BUSY_STAT2__MES_PIPE2_BUSY_MASK 0x00001000L |
7016 | #define CP_CPC_BUSY_STAT2__MES_PIPE3_BUSY_MASK 0x00002000L |
7017 | //CP_CPC_GRBM_FREE_COUNT |
7018 | #define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0 |
7019 | #define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x0000003FL |
7020 | //CP_CPC_PRIV_VIOLATION_ADDR |
7021 | #define CP_CPC_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_ADDR__SHIFT 0x0 |
7022 | #define CP_CPC_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_ADDR_MASK 0x0003FFFFL |
7023 | //CP_MEC_ME1_HEADER_DUMP |
7024 | #define 0x0 |
7025 | #define 0xFFFFFFFFL |
7026 | //CP_MEC_ME2_HEADER_DUMP |
7027 | #define 0x0 |
7028 | #define 0xFFFFFFFFL |
7029 | //CP_CPC_SCRATCH_INDEX |
7030 | #define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0 |
7031 | #define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX_64BIT_MODE__SHIFT 0x1f |
7032 | #define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0x000001FFL |
7033 | #define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX_64BIT_MODE_MASK 0x80000000L |
7034 | //CP_CPC_SCRATCH_DATA |
7035 | #define CP_CPC_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0 |
7036 | #define CP_CPC_SCRATCH_DATA__SCRATCH_DATA_MASK 0xFFFFFFFFL |
7037 | //CP_CPF_GRBM_FREE_COUNT |
7038 | #define CP_CPF_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0 |
7039 | #define CP_CPF_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x00000007L |
7040 | //CP_CPF_BUSY_STAT2 |
7041 | #define CP_CPF_BUSY_STAT2__CP_SDMA_CPG_BUSY__SHIFT 0x0 |
7042 | #define CP_CPF_BUSY_STAT2__CP_SDMA_CPC_BUSY__SHIFT 0x1 |
7043 | #define CP_CPF_BUSY_STAT2__MES_HQD_DISPATCH_BUSY__SHIFT 0xc |
7044 | #define CP_CPF_BUSY_STAT2__MES_HQD_DMA_OFFLOAD_BUSY__SHIFT 0xe |
7045 | #define CP_CPF_BUSY_STAT2__MES_HQD_MESSAGE_BUSY__SHIFT 0x11 |
7046 | #define CP_CPF_BUSY_STAT2__MES_HQD_PQ_FETCHER_BUSY__SHIFT 0x12 |
7047 | #define CP_CPF_BUSY_STAT2__MES_HQD_CONSUMED_RPTR_BUSY__SHIFT 0x16 |
7048 | #define CP_CPF_BUSY_STAT2__MES_HQD_FETCHER_ARB_BUSY__SHIFT 0x17 |
7049 | #define CP_CPF_BUSY_STAT2__MES_HQD_ROQ_ALIGN_BUSY__SHIFT 0x18 |
7050 | #define CP_CPF_BUSY_STAT2__MES_HQD_ROQ_PQ_BUSY__SHIFT 0x1b |
7051 | #define CP_CPF_BUSY_STAT2__MES_HQD_PQ_BUSY__SHIFT 0x1e |
7052 | #define CP_CPF_BUSY_STAT2__CP_SDMA_CPG_BUSY_MASK 0x00000001L |
7053 | #define CP_CPF_BUSY_STAT2__CP_SDMA_CPC_BUSY_MASK 0x00000002L |
7054 | #define CP_CPF_BUSY_STAT2__MES_HQD_DISPATCH_BUSY_MASK 0x00001000L |
7055 | #define CP_CPF_BUSY_STAT2__MES_HQD_DMA_OFFLOAD_BUSY_MASK 0x00004000L |
7056 | #define CP_CPF_BUSY_STAT2__MES_HQD_MESSAGE_BUSY_MASK 0x00020000L |
7057 | #define CP_CPF_BUSY_STAT2__MES_HQD_PQ_FETCHER_BUSY_MASK 0x00040000L |
7058 | #define CP_CPF_BUSY_STAT2__MES_HQD_CONSUMED_RPTR_BUSY_MASK 0x00400000L |
7059 | #define CP_CPF_BUSY_STAT2__MES_HQD_FETCHER_ARB_BUSY_MASK 0x00800000L |
7060 | #define CP_CPF_BUSY_STAT2__MES_HQD_ROQ_ALIGN_BUSY_MASK 0x01000000L |
7061 | #define CP_CPF_BUSY_STAT2__MES_HQD_ROQ_PQ_BUSY_MASK 0x08000000L |
7062 | #define CP_CPF_BUSY_STAT2__MES_HQD_PQ_BUSY_MASK 0x40000000L |
7063 | //CP_CPC_HALT_HYST_COUNT |
7064 | #define CP_CPC_HALT_HYST_COUNT__COUNT__SHIFT 0x0 |
7065 | #define CP_CPC_HALT_HYST_COUNT__COUNT_MASK 0x0000000FL |
7066 | //CP_STALLED_STAT3 |
7067 | #define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0 |
7068 | #define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV__SHIFT 0x1 |
7069 | #define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER__SHIFT 0x2 |
7070 | #define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY__SHIFT 0x3 |
7071 | #define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY__SHIFT 0x4 |
7072 | #define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY__SHIFT 0x5 |
7073 | #define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV__SHIFT 0x6 |
7074 | #define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV__SHIFT 0x7 |
7075 | #define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA__SHIFT 0xa |
7076 | #define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG__SHIFT 0xb |
7077 | #define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER__SHIFT 0xc |
7078 | #define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW__SHIFT 0xd |
7079 | #define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE__SHIFT 0xe |
7080 | #define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS__SHIFT 0xf |
7081 | #define CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x10 |
7082 | #define CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x11 |
7083 | #define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_FREE__SHIFT 0x12 |
7084 | #define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_TAGS__SHIFT 0x13 |
7085 | #define CP_STALLED_STAT3__UTCL1_WAITING_ON_TRANS__SHIFT 0x14 |
7086 | #define CP_STALLED_STAT3__GCRIU_WAITING_ON_FREE__SHIFT 0x15 |
7087 | #define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV_MASK 0x00000001L |
7088 | #define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV_MASK 0x00000002L |
7089 | #define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER_MASK 0x00000004L |
7090 | #define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY_MASK 0x00000008L |
7091 | #define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY_MASK 0x00000010L |
7092 | #define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY_MASK 0x00000020L |
7093 | #define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV_MASK 0x00000040L |
7094 | #define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV_MASK 0x00000080L |
7095 | #define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA_MASK 0x00000400L |
7096 | #define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG_MASK 0x00000800L |
7097 | #define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_MASK 0x00001000L |
7098 | #define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW_MASK 0x00002000L |
7099 | #define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE_MASK 0x00004000L |
7100 | #define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS_MASK 0x00008000L |
7101 | #define CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM_MASK 0x00010000L |
7102 | #define CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x00020000L |
7103 | #define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_FREE_MASK 0x00040000L |
7104 | #define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_TAGS_MASK 0x00080000L |
7105 | #define CP_STALLED_STAT3__UTCL1_WAITING_ON_TRANS_MASK 0x00100000L |
7106 | #define CP_STALLED_STAT3__GCRIU_WAITING_ON_FREE_MASK 0x00200000L |
7107 | //CP_STALLED_STAT1 |
7108 | #define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV__SHIFT 0x0 |
7109 | #define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV_R0__SHIFT 0x2 |
7110 | #define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV_R1__SHIFT 0x3 |
7111 | #define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV_R0__SHIFT 0x4 |
7112 | #define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV_R1__SHIFT 0x5 |
7113 | #define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG__SHIFT 0xa |
7114 | #define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG__SHIFT 0xb |
7115 | #define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM__SHIFT 0xc |
7116 | #define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0xd |
7117 | #define CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA__SHIFT 0xe |
7118 | #define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA__SHIFT 0xf |
7119 | #define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE__SHIFT 0x17 |
7120 | #define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE__SHIFT 0x18 |
7121 | #define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE__SHIFT 0x19 |
7122 | #define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ__SHIFT 0x1a |
7123 | #define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ__SHIFT 0x1b |
7124 | #define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ__SHIFT 0x1c |
7125 | #define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION__SHIFT 0x1d |
7126 | #define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV_MASK 0x00000001L |
7127 | #define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV_R0_MASK 0x00000004L |
7128 | #define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV_R1_MASK 0x00000008L |
7129 | #define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV_R0_MASK 0x00000010L |
7130 | #define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV_R1_MASK 0x00000020L |
7131 | #define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG_MASK 0x00000400L |
7132 | #define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG_MASK 0x00000800L |
7133 | #define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM_MASK 0x00001000L |
7134 | #define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x00002000L |
7135 | #define CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA_MASK 0x00004000L |
7136 | #define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA_MASK 0x00008000L |
7137 | #define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE_MASK 0x00800000L |
7138 | #define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE_MASK 0x01000000L |
7139 | #define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE_MASK 0x02000000L |
7140 | #define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ_MASK 0x04000000L |
7141 | #define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ_MASK 0x08000000L |
7142 | #define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ_MASK 0x10000000L |
7143 | #define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION_MASK 0x20000000L |
7144 | //CP_STALLED_STAT2 |
7145 | #define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0 |
7146 | #define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV__SHIFT 0x1 |
7147 | #define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV__SHIFT 0x2 |
7148 | #define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING__SHIFT 0x4 |
7149 | #define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING__SHIFT 0x5 |
7150 | #define CP_STALLED_STAT2__PFP_TO_MEQ_DDID_NOT_RDY_TO_RCV__SHIFT 0x6 |
7151 | #define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA__SHIFT 0x8 |
7152 | #define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER__SHIFT 0x9 |
7153 | #define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER__SHIFT 0xa |
7154 | #define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME__SHIFT 0xb |
7155 | #define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV__SHIFT 0xc |
7156 | #define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV__SHIFT 0xd |
7157 | #define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP__SHIFT 0xe |
7158 | #define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH__SHIFT 0xf |
7159 | #define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x10 |
7160 | #define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x11 |
7161 | #define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ__SHIFT 0x12 |
7162 | #define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x13 |
7163 | #define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x14 |
7164 | #define CP_STALLED_STAT2__QU_STALLED_ON_EOP_DONE_PULSE__SHIFT 0x15 |
7165 | #define CP_STALLED_STAT2__QU_STALLED_ON_EOP_DONE_WR_CONFIRM__SHIFT 0x16 |
7166 | #define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING__SHIFT 0x17 |
7167 | #define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING__SHIFT 0x18 |
7168 | #define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE__SHIFT 0x19 |
7169 | #define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE__SHIFT 0x1a |
7170 | #define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM__SHIFT 0x1b |
7171 | #define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION__SHIFT 0x1c |
7172 | #define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE__SHIFT 0x1d |
7173 | #define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS__SHIFT 0x1e |
7174 | #define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN__SHIFT 0x1f |
7175 | #define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV_MASK 0x00000001L |
7176 | #define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV_MASK 0x00000002L |
7177 | #define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV_MASK 0x00000004L |
7178 | #define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING_MASK 0x00000010L |
7179 | #define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING_MASK 0x00000020L |
7180 | #define CP_STALLED_STAT2__PFP_TO_MEQ_DDID_NOT_RDY_TO_RCV_MASK 0x00000040L |
7181 | #define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA_MASK 0x00000100L |
7182 | #define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER_MASK 0x00000200L |
7183 | #define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER_MASK 0x00000400L |
7184 | #define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME_MASK 0x00000800L |
7185 | #define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV_MASK 0x00001000L |
7186 | #define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV_MASK 0x00002000L |
7187 | #define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP_MASK 0x00004000L |
7188 | #define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH_MASK 0x00008000L |
7189 | #define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x00010000L |
7190 | #define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x00020000L |
7191 | #define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ_MASK 0x00040000L |
7192 | #define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM_MASK 0x00080000L |
7193 | #define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x00100000L |
7194 | #define CP_STALLED_STAT2__QU_STALLED_ON_EOP_DONE_PULSE_MASK 0x00200000L |
7195 | #define CP_STALLED_STAT2__QU_STALLED_ON_EOP_DONE_WR_CONFIRM_MASK 0x00400000L |
7196 | #define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING_MASK 0x00800000L |
7197 | #define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING_MASK 0x01000000L |
7198 | #define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE_MASK 0x02000000L |
7199 | #define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE_MASK 0x04000000L |
7200 | #define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM_MASK 0x08000000L |
7201 | #define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION_MASK 0x10000000L |
7202 | #define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE_MASK 0x20000000L |
7203 | #define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS_MASK 0x40000000L |
7204 | #define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN_MASK 0x80000000L |
7205 | //CP_BUSY_STAT |
7206 | #define CP_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x0 |
7207 | #define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO__SHIFT 0x6 |
7208 | #define CP_BUSY_STAT__PFP_PARSING_PACKETS__SHIFT 0x7 |
7209 | #define CP_BUSY_STAT__ME_PARSING_PACKETS__SHIFT 0x8 |
7210 | #define CP_BUSY_STAT__RCIU_PFP_BUSY__SHIFT 0x9 |
7211 | #define CP_BUSY_STAT__RCIU_ME_BUSY__SHIFT 0xa |
7212 | #define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY__SHIFT 0xc |
7213 | #define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING__SHIFT 0xd |
7214 | #define CP_BUSY_STAT__SEM_POLLING_FOR_PASS__SHIFT 0xe |
7215 | #define CP_BUSY_STAT__GFX_CONTEXT_BUSY__SHIFT 0xf |
7216 | #define CP_BUSY_STAT__ME_PARSER_BUSY__SHIFT 0x11 |
7217 | #define CP_BUSY_STAT__EOP_DONE_BUSY__SHIFT 0x12 |
7218 | #define CP_BUSY_STAT__STRM_OUT_BUSY__SHIFT 0x13 |
7219 | #define CP_BUSY_STAT__PIPE_STATS_BUSY__SHIFT 0x14 |
7220 | #define CP_BUSY_STAT__RCIU_CE_BUSY__SHIFT 0x15 |
7221 | #define CP_BUSY_STAT__CE_PARSING_PACKETS__SHIFT 0x16 |
7222 | #define CP_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x00000001L |
7223 | #define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO_MASK 0x00000040L |
7224 | #define CP_BUSY_STAT__PFP_PARSING_PACKETS_MASK 0x00000080L |
7225 | #define CP_BUSY_STAT__ME_PARSING_PACKETS_MASK 0x00000100L |
7226 | #define CP_BUSY_STAT__RCIU_PFP_BUSY_MASK 0x00000200L |
7227 | #define CP_BUSY_STAT__RCIU_ME_BUSY_MASK 0x00000400L |
7228 | #define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY_MASK 0x00001000L |
7229 | #define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING_MASK 0x00002000L |
7230 | #define CP_BUSY_STAT__SEM_POLLING_FOR_PASS_MASK 0x00004000L |
7231 | #define CP_BUSY_STAT__GFX_CONTEXT_BUSY_MASK 0x00008000L |
7232 | #define CP_BUSY_STAT__ME_PARSER_BUSY_MASK 0x00020000L |
7233 | #define CP_BUSY_STAT__EOP_DONE_BUSY_MASK 0x00040000L |
7234 | #define CP_BUSY_STAT__STRM_OUT_BUSY_MASK 0x00080000L |
7235 | #define CP_BUSY_STAT__PIPE_STATS_BUSY_MASK 0x00100000L |
7236 | #define CP_BUSY_STAT__RCIU_CE_BUSY_MASK 0x00200000L |
7237 | #define CP_BUSY_STAT__CE_PARSING_PACKETS_MASK 0x00400000L |
7238 | //CP_STAT |
7239 | #define CP_STAT__ROQ_DB_BUSY__SHIFT 0x5 |
7240 | #define CP_STAT__ROQ_CE_DB_BUSY__SHIFT 0x6 |
7241 | #define CP_STAT__ROQ_RING_BUSY__SHIFT 0x9 |
7242 | #define CP_STAT__ROQ_INDIRECT1_BUSY__SHIFT 0xa |
7243 | #define CP_STAT__ROQ_INDIRECT2_BUSY__SHIFT 0xb |
7244 | #define CP_STAT__ROQ_STATE_BUSY__SHIFT 0xc |
7245 | #define CP_STAT__DC_BUSY__SHIFT 0xd |
7246 | #define CP_STAT__UTCL2IU_BUSY__SHIFT 0xe |
7247 | #define CP_STAT__PFP_BUSY__SHIFT 0xf |
7248 | #define CP_STAT__MEQ_BUSY__SHIFT 0x10 |
7249 | #define CP_STAT__ME_BUSY__SHIFT 0x11 |
7250 | #define CP_STAT__QUERY_BUSY__SHIFT 0x12 |
7251 | #define CP_STAT__SEMAPHORE_BUSY__SHIFT 0x13 |
7252 | #define CP_STAT__INTERRUPT_BUSY__SHIFT 0x14 |
7253 | #define CP_STAT__SURFACE_SYNC_BUSY__SHIFT 0x15 |
7254 | #define CP_STAT__DMA_BUSY__SHIFT 0x16 |
7255 | #define CP_STAT__RCIU_BUSY__SHIFT 0x17 |
7256 | #define CP_STAT__SCRATCH_RAM_BUSY__SHIFT 0x18 |
7257 | #define CP_STAT__GCRIU_BUSY__SHIFT 0x19 |
7258 | #define CP_STAT__CE_BUSY__SHIFT 0x1a |
7259 | #define CP_STAT__TCIU_BUSY__SHIFT 0x1b |
7260 | #define CP_STAT__ROQ_CE_RING_BUSY__SHIFT 0x1c |
7261 | #define CP_STAT__ROQ_CE_INDIRECT1_BUSY__SHIFT 0x1d |
7262 | #define CP_STAT__ROQ_CE_INDIRECT2_BUSY__SHIFT 0x1e |
7263 | #define CP_STAT__CP_BUSY__SHIFT 0x1f |
7264 | #define CP_STAT__ROQ_DB_BUSY_MASK 0x00000020L |
7265 | #define CP_STAT__ROQ_CE_DB_BUSY_MASK 0x00000040L |
7266 | #define CP_STAT__ROQ_RING_BUSY_MASK 0x00000200L |
7267 | #define CP_STAT__ROQ_INDIRECT1_BUSY_MASK 0x00000400L |
7268 | #define CP_STAT__ROQ_INDIRECT2_BUSY_MASK 0x00000800L |
7269 | #define CP_STAT__ROQ_STATE_BUSY_MASK 0x00001000L |
7270 | #define CP_STAT__DC_BUSY_MASK 0x00002000L |
7271 | #define CP_STAT__UTCL2IU_BUSY_MASK 0x00004000L |
7272 | #define CP_STAT__PFP_BUSY_MASK 0x00008000L |
7273 | #define CP_STAT__MEQ_BUSY_MASK 0x00010000L |
7274 | #define CP_STAT__ME_BUSY_MASK 0x00020000L |
7275 | #define CP_STAT__QUERY_BUSY_MASK 0x00040000L |
7276 | #define CP_STAT__SEMAPHORE_BUSY_MASK 0x00080000L |
7277 | #define CP_STAT__INTERRUPT_BUSY_MASK 0x00100000L |
7278 | #define CP_STAT__SURFACE_SYNC_BUSY_MASK 0x00200000L |
7279 | #define CP_STAT__DMA_BUSY_MASK 0x00400000L |
7280 | #define CP_STAT__RCIU_BUSY_MASK 0x00800000L |
7281 | #define CP_STAT__SCRATCH_RAM_BUSY_MASK 0x01000000L |
7282 | #define CP_STAT__GCRIU_BUSY_MASK 0x02000000L |
7283 | #define CP_STAT__CE_BUSY_MASK 0x04000000L |
7284 | #define CP_STAT__TCIU_BUSY_MASK 0x08000000L |
7285 | #define CP_STAT__ROQ_CE_RING_BUSY_MASK 0x10000000L |
7286 | #define CP_STAT__ROQ_CE_INDIRECT1_BUSY_MASK 0x20000000L |
7287 | #define CP_STAT__ROQ_CE_INDIRECT2_BUSY_MASK 0x40000000L |
7288 | #define CP_STAT__CP_BUSY_MASK 0x80000000L |
7289 | //CP_ME_HEADER_DUMP |
7290 | #define 0x0 |
7291 | #define 0xFFFFFFFFL |
7292 | //CP_PFP_HEADER_DUMP |
7293 | #define 0x0 |
7294 | #define 0xFFFFFFFFL |
7295 | //CP_GRBM_FREE_COUNT |
7296 | #define CP_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0 |
7297 | #define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS__SHIFT 0x8 |
7298 | #define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP__SHIFT 0x10 |
7299 | #define CP_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x0000003FL |
7300 | #define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS_MASK 0x00003F00L |
7301 | #define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP_MASK 0x003F0000L |
7302 | //CP_PFP_INSTR_PNTR |
7303 | #define CP_PFP_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0 |
7304 | #define CP_PFP_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL |
7305 | //CP_ME_INSTR_PNTR |
7306 | #define CP_ME_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0 |
7307 | #define CP_ME_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL |
7308 | //CP_MEC1_INSTR_PNTR |
7309 | #define CP_MEC1_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0 |
7310 | #define CP_MEC1_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL |
7311 | //CP_MEC2_INSTR_PNTR |
7312 | #define CP_MEC2_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0 |
7313 | #define CP_MEC2_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL |
7314 | //CP_CSF_STAT |
7315 | #define CP_CSF_STAT__BUFFER_REQUEST_COUNT__SHIFT 0x8 |
7316 | #define CP_CSF_STAT__BUFFER_REQUEST_COUNT_MASK 0x0001FF00L |
7317 | //CP_CNTX_STAT |
7318 | #define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS__SHIFT 0x0 |
7319 | #define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT__SHIFT 0x8 |
7320 | #define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS__SHIFT 0x14 |
7321 | #define CP_CNTX_STAT__CURRENT_GFX_CONTEXT__SHIFT 0x1c |
7322 | #define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS_MASK 0x000000FFL |
7323 | #define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT_MASK 0x00000700L |
7324 | #define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS_MASK 0x0FF00000L |
7325 | #define CP_CNTX_STAT__CURRENT_GFX_CONTEXT_MASK 0x70000000L |
7326 | //CP_ME_PREEMPTION |
7327 | #define CP_ME_PREEMPTION__OBSOLETE__SHIFT 0x0 |
7328 | #define CP_ME_PREEMPTION__OBSOLETE_MASK 0x00000001L |
7329 | //CP_RB1_RPTR |
7330 | #define CP_RB1_RPTR__RB_RPTR__SHIFT 0x0 |
7331 | #define CP_RB1_RPTR__RB_RPTR_MASK 0x000FFFFFL |
7332 | //CP_RB0_RPTR |
7333 | #define CP_RB0_RPTR__RB_RPTR__SHIFT 0x0 |
7334 | #define CP_RB0_RPTR__RB_RPTR_MASK 0x000FFFFFL |
7335 | //CP_RB_RPTR |
7336 | #define CP_RB_RPTR__RB_RPTR__SHIFT 0x0 |
7337 | #define CP_RB_RPTR__RB_RPTR_MASK 0x000FFFFFL |
7338 | //CP_RB_WPTR_DELAY |
7339 | #define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER__SHIFT 0x0 |
7340 | #define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT__SHIFT 0x1c |
7341 | #define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER_MASK 0x0FFFFFFFL |
7342 | #define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT_MASK 0xF0000000L |
7343 | //CP_RB_WPTR_POLL_CNTL |
7344 | #define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT 0x0 |
7345 | #define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 |
7346 | #define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK 0x0000FFFFL |
7347 | #define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L |
7348 | //CP_ROQ1_THRESHOLDS |
7349 | #define CP_ROQ1_THRESHOLDS__RB1_START__SHIFT 0x0 |
7350 | #define CP_ROQ1_THRESHOLDS__R0_IB1_START__SHIFT 0xa |
7351 | #define CP_ROQ1_THRESHOLDS__R1_IB1_START__SHIFT 0x14 |
7352 | #define CP_ROQ1_THRESHOLDS__RB1_START_MASK 0x000003FFL |
7353 | #define CP_ROQ1_THRESHOLDS__R0_IB1_START_MASK 0x000FFC00L |
7354 | #define CP_ROQ1_THRESHOLDS__R1_IB1_START_MASK 0x3FF00000L |
7355 | //CP_ROQ2_THRESHOLDS |
7356 | #define CP_ROQ2_THRESHOLDS__R0_IB2_START__SHIFT 0x0 |
7357 | #define CP_ROQ2_THRESHOLDS__R1_IB2_START__SHIFT 0xa |
7358 | #define CP_ROQ2_THRESHOLDS__R0_IB2_START_MASK 0x000003FFL |
7359 | #define CP_ROQ2_THRESHOLDS__R1_IB2_START_MASK 0x000FFC00L |
7360 | //CP_STQ_THRESHOLDS |
7361 | #define CP_STQ_THRESHOLDS__STQ0_START__SHIFT 0x0 |
7362 | #define CP_STQ_THRESHOLDS__STQ1_START__SHIFT 0x8 |
7363 | #define CP_STQ_THRESHOLDS__STQ2_START__SHIFT 0x10 |
7364 | #define CP_STQ_THRESHOLDS__STQ0_START_MASK 0x000000FFL |
7365 | #define CP_STQ_THRESHOLDS__STQ1_START_MASK 0x0000FF00L |
7366 | #define CP_STQ_THRESHOLDS__STQ2_START_MASK 0x00FF0000L |
7367 | //CP_MEQ_THRESHOLDS |
7368 | #define CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT 0x0 |
7369 | #define CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT 0x8 |
7370 | #define CP_MEQ_THRESHOLDS__MEQ1_START_MASK 0x000000FFL |
7371 | #define CP_MEQ_THRESHOLDS__MEQ2_START_MASK 0x0000FF00L |
7372 | //CP_ROQ_AVAIL |
7373 | #define CP_ROQ_AVAIL__ROQ_CNT_RING__SHIFT 0x0 |
7374 | #define CP_ROQ_AVAIL__ROQ_CNT_IB1__SHIFT 0x10 |
7375 | #define CP_ROQ_AVAIL__ROQ_CNT_RING_MASK 0x00000FFFL |
7376 | #define CP_ROQ_AVAIL__ROQ_CNT_IB1_MASK 0x0FFF0000L |
7377 | //CP_STQ_AVAIL |
7378 | #define CP_STQ_AVAIL__STQ_CNT__SHIFT 0x0 |
7379 | #define CP_STQ_AVAIL__STQ_CNT_MASK 0x000001FFL |
7380 | //CP_ROQ2_AVAIL |
7381 | #define CP_ROQ2_AVAIL__ROQ_CNT_IB2__SHIFT 0x0 |
7382 | #define CP_ROQ2_AVAIL__ROQ_CNT_DB__SHIFT 0x10 |
7383 | #define CP_ROQ2_AVAIL__ROQ_CNT_IB2_MASK 0x00000FFFL |
7384 | #define CP_ROQ2_AVAIL__ROQ_CNT_DB_MASK 0x0FFF0000L |
7385 | //CP_MEQ_AVAIL |
7386 | #define CP_MEQ_AVAIL__MEQ_CNT__SHIFT 0x0 |
7387 | #define CP_MEQ_AVAIL__MEQ_CNT_MASK 0x000003FFL |
7388 | //CP_CMD_INDEX |
7389 | #define CP_CMD_INDEX__CMD_INDEX__SHIFT 0x0 |
7390 | #define CP_CMD_INDEX__CMD_ME_SEL__SHIFT 0xc |
7391 | #define CP_CMD_INDEX__CMD_QUEUE_SEL__SHIFT 0x10 |
7392 | #define CP_CMD_INDEX__CMD_INDEX_MASK 0x000007FFL |
7393 | #define CP_CMD_INDEX__CMD_ME_SEL_MASK 0x00003000L |
7394 | #define CP_CMD_INDEX__CMD_QUEUE_SEL_MASK 0x00070000L |
7395 | //CP_CMD_DATA |
7396 | #define CP_CMD_DATA__CMD_DATA__SHIFT 0x0 |
7397 | #define CP_CMD_DATA__CMD_DATA_MASK 0xFFFFFFFFL |
7398 | //CP_ROQ_RB_STAT |
7399 | #define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY__SHIFT 0x0 |
7400 | #define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY__SHIFT 0x10 |
7401 | #define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY_MASK 0x00000FFFL |
7402 | #define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY_MASK 0x0FFF0000L |
7403 | //CP_ROQ_IB1_STAT |
7404 | #define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1__SHIFT 0x0 |
7405 | #define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1__SHIFT 0x10 |
7406 | #define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1_MASK 0x00000FFFL |
7407 | #define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1_MASK 0x0FFF0000L |
7408 | //CP_ROQ_IB2_STAT |
7409 | #define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2__SHIFT 0x0 |
7410 | #define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2__SHIFT 0x10 |
7411 | #define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2_MASK 0x00000FFFL |
7412 | #define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2_MASK 0x0FFF0000L |
7413 | //CP_STQ_STAT |
7414 | #define CP_STQ_STAT__STQ_RPTR__SHIFT 0x0 |
7415 | #define CP_STQ_STAT__STQ_RPTR_MASK 0x000003FFL |
7416 | //CP_STQ_WR_STAT |
7417 | #define CP_STQ_WR_STAT__STQ_WPTR__SHIFT 0x0 |
7418 | #define CP_STQ_WR_STAT__STQ_WPTR_MASK 0x000003FFL |
7419 | //CP_MEQ_STAT |
7420 | #define CP_MEQ_STAT__MEQ_RPTR__SHIFT 0x0 |
7421 | #define CP_MEQ_STAT__MEQ_WPTR__SHIFT 0x10 |
7422 | #define CP_MEQ_STAT__MEQ_RPTR_MASK 0x000003FFL |
7423 | #define CP_MEQ_STAT__MEQ_WPTR_MASK 0x03FF0000L |
7424 | //CP_ROQ3_THRESHOLDS |
7425 | #define CP_ROQ3_THRESHOLDS__R0_DB_START__SHIFT 0x0 |
7426 | #define CP_ROQ3_THRESHOLDS__R1_DB_START__SHIFT 0xa |
7427 | #define CP_ROQ3_THRESHOLDS__R0_DB_START_MASK 0x000003FFL |
7428 | #define CP_ROQ3_THRESHOLDS__R1_DB_START_MASK 0x000FFC00L |
7429 | //CP_ROQ_DB_STAT |
7430 | #define CP_ROQ_DB_STAT__ROQ_RPTR_DB__SHIFT 0x0 |
7431 | #define CP_ROQ_DB_STAT__ROQ_WPTR_DB__SHIFT 0x10 |
7432 | #define CP_ROQ_DB_STAT__ROQ_RPTR_DB_MASK 0x00000FFFL |
7433 | #define CP_ROQ_DB_STAT__ROQ_WPTR_DB_MASK 0x0FFF0000L |
7434 | //CP_INT_STAT_DEBUG |
7435 | #define CP_INT_STAT_DEBUG__RESUME_INT_ASSERTED__SHIFT 0x8 |
7436 | #define CP_INT_STAT_DEBUG__SUSPEND_INT_ASSERTED__SHIFT 0x9 |
7437 | #define CP_INT_STAT_DEBUG__DMA_WATCH_INT_ASSERTED__SHIFT 0xa |
7438 | #define CP_INT_STAT_DEBUG__CP_VM_DOORBELL_WR_INT_ASSERTED__SHIFT 0xb |
7439 | #define CP_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0xe |
7440 | #define CP_INT_STAT_DEBUG__FUE_INT_STATUS_DEBUG__SHIFT 0xf |
7441 | #define CP_INT_STAT_DEBUG__GPF_INT_ASSERTED__SHIFT 0x10 |
7442 | #define CP_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x11 |
7443 | #define CP_INT_STAT_DEBUG__CMP_BUSY_INT_ASSERTED__SHIFT 0x12 |
7444 | #define CP_INT_STAT_DEBUG__CNTX_BUSY_INT_ASSERTED__SHIFT 0x13 |
7445 | #define CP_INT_STAT_DEBUG__CNTX_EMPTY_INT_ASSERTED__SHIFT 0x14 |
7446 | #define CP_INT_STAT_DEBUG__GFX_IDLE_INT_ASSERTED__SHIFT 0x15 |
7447 | #define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED__SHIFT 0x16 |
7448 | #define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17 |
7449 | #define CP_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x18 |
7450 | #define CP_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x1a |
7451 | #define CP_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x1b |
7452 | #define CP_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d |
7453 | #define CP_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x1e |
7454 | #define CP_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x1f |
7455 | #define CP_INT_STAT_DEBUG__RESUME_INT_ASSERTED_MASK 0x00000100L |
7456 | #define CP_INT_STAT_DEBUG__SUSPEND_INT_ASSERTED_MASK 0x00000200L |
7457 | #define CP_INT_STAT_DEBUG__DMA_WATCH_INT_ASSERTED_MASK 0x00000400L |
7458 | #define CP_INT_STAT_DEBUG__CP_VM_DOORBELL_WR_INT_ASSERTED_MASK 0x00000800L |
7459 | #define CP_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x00004000L |
7460 | #define CP_INT_STAT_DEBUG__FUE_INT_STATUS_DEBUG_MASK 0x00008000L |
7461 | #define CP_INT_STAT_DEBUG__GPF_INT_ASSERTED_MASK 0x00010000L |
7462 | #define CP_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x00020000L |
7463 | #define CP_INT_STAT_DEBUG__CMP_BUSY_INT_ASSERTED_MASK 0x00040000L |
7464 | #define CP_INT_STAT_DEBUG__CNTX_BUSY_INT_ASSERTED_MASK 0x00080000L |
7465 | #define CP_INT_STAT_DEBUG__CNTX_EMPTY_INT_ASSERTED_MASK 0x00100000L |
7466 | #define CP_INT_STAT_DEBUG__GFX_IDLE_INT_ASSERTED_MASK 0x00200000L |
7467 | #define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED_MASK 0x00400000L |
7468 | #define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x00800000L |
7469 | #define CP_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x01000000L |
7470 | #define CP_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x04000000L |
7471 | #define CP_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x08000000L |
7472 | #define CP_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000L |
7473 | #define CP_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000L |
7474 | #define CP_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000L |
7475 | //CP_DEBUG_CNTL |
7476 | #define CP_DEBUG_CNTL__DEBUG_INDX__SHIFT 0x0 |
7477 | #define CP_DEBUG_CNTL__DEBUG_INDX_MASK 0x0000007FL |
7478 | //CP_PRIV_VIOLATION_ADDR |
7479 | #define CP_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_ADDR__SHIFT 0x0 |
7480 | #define CP_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_ADDR_MASK 0x0003FFFFL |
7481 | |
7482 | |
7483 | // addressBlock: gc_padec |
7484 | //VGT_DMA_DATA_FIFO_DEPTH |
7485 | #define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH__SHIFT 0x0 |
7486 | #define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH_MASK 0x000003FFL |
7487 | //VGT_DMA_REQ_FIFO_DEPTH |
7488 | #define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH__SHIFT 0x0 |
7489 | #define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH_MASK 0x0000003FL |
7490 | //VGT_DRAW_INIT_FIFO_DEPTH |
7491 | #define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH__SHIFT 0x0 |
7492 | #define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH_MASK 0x0000003FL |
7493 | //VGT_MC_LAT_CNTL |
7494 | #define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES__SHIFT 0x0 |
7495 | #define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES_MASK 0x0000000FL |
7496 | //IA_UTCL1_STATUS_2 |
7497 | #define IA_UTCL1_STATUS_2__IA_BUSY__SHIFT 0x0 |
7498 | #define IA_UTCL1_STATUS_2__IA_DMA_BUSY__SHIFT 0x1 |
7499 | #define IA_UTCL1_STATUS_2__IA_DMA_REQ_BUSY__SHIFT 0x2 |
7500 | #define IA_UTCL1_STATUS_2__IA_GRP_BUSY__SHIFT 0x3 |
7501 | #define IA_UTCL1_STATUS_2__IA_ADC_BUSY__SHIFT 0x4 |
7502 | #define IA_UTCL1_STATUS_2__FAULT_DETECTED__SHIFT 0x5 |
7503 | #define IA_UTCL1_STATUS_2__RETRY_DETECTED__SHIFT 0x6 |
7504 | #define IA_UTCL1_STATUS_2__PRT_DETECTED__SHIFT 0x7 |
7505 | #define IA_UTCL1_STATUS_2__FAULT_UTCL1ID__SHIFT 0x8 |
7506 | #define IA_UTCL1_STATUS_2__RETRY_UTCL1ID__SHIFT 0x10 |
7507 | #define IA_UTCL1_STATUS_2__PRT_UTCL1ID__SHIFT 0x18 |
7508 | #define IA_UTCL1_STATUS_2__IA_BUSY_MASK 0x00000001L |
7509 | #define IA_UTCL1_STATUS_2__IA_DMA_BUSY_MASK 0x00000002L |
7510 | #define IA_UTCL1_STATUS_2__IA_DMA_REQ_BUSY_MASK 0x00000004L |
7511 | #define IA_UTCL1_STATUS_2__IA_GRP_BUSY_MASK 0x00000008L |
7512 | #define IA_UTCL1_STATUS_2__IA_ADC_BUSY_MASK 0x00000010L |
7513 | #define IA_UTCL1_STATUS_2__FAULT_DETECTED_MASK 0x00000020L |
7514 | #define IA_UTCL1_STATUS_2__RETRY_DETECTED_MASK 0x00000040L |
7515 | #define IA_UTCL1_STATUS_2__PRT_DETECTED_MASK 0x00000080L |
7516 | #define IA_UTCL1_STATUS_2__FAULT_UTCL1ID_MASK 0x00003F00L |
7517 | #define IA_UTCL1_STATUS_2__RETRY_UTCL1ID_MASK 0x003F0000L |
7518 | #define IA_UTCL1_STATUS_2__PRT_UTCL1ID_MASK 0x3F000000L |
7519 | //WD_CNTL_STATUS |
7520 | #define WD_CNTL_STATUS__DIST_BUSY__SHIFT 0x0 |
7521 | #define WD_CNTL_STATUS__DIST_BE_BUSY__SHIFT 0x1 |
7522 | #define WD_CNTL_STATUS__GE_UTCL1_BUSY__SHIFT 0x2 |
7523 | #define WD_CNTL_STATUS__WD_TE11_BUSY__SHIFT 0x3 |
7524 | #define WD_CNTL_STATUS__PC_MANAGER_BUSY__SHIFT 0x4 |
7525 | #define WD_CNTL_STATUS__WLC_BUSY__SHIFT 0x5 |
7526 | #define WD_CNTL_STATUS__DIST_BUSY_MASK 0x00000001L |
7527 | #define WD_CNTL_STATUS__DIST_BE_BUSY_MASK 0x00000002L |
7528 | #define WD_CNTL_STATUS__GE_UTCL1_BUSY_MASK 0x00000004L |
7529 | #define WD_CNTL_STATUS__WD_TE11_BUSY_MASK 0x00000008L |
7530 | #define WD_CNTL_STATUS__PC_MANAGER_BUSY_MASK 0x00000010L |
7531 | #define WD_CNTL_STATUS__WLC_BUSY_MASK 0x00000020L |
7532 | //CC_GC_PRIM_CONFIG |
7533 | #define CC_GC_PRIM_CONFIG__WRITE_DIS__SHIFT 0x0 |
7534 | #define CC_GC_PRIM_CONFIG__INACTIVE_PA__SHIFT 0x4 |
7535 | #define CC_GC_PRIM_CONFIG__WRITE_DIS_MASK 0x00000001L |
7536 | #define CC_GC_PRIM_CONFIG__INACTIVE_PA_MASK 0x000FFFF0L |
7537 | //WD_QOS |
7538 | #define WD_QOS__DRAW_STALL__SHIFT 0x0 |
7539 | #define WD_QOS__DRAW_STALL_MASK 0x00000001L |
7540 | //WD_UTCL1_CNTL |
7541 | #define WD_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 |
7542 | #define WD_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x17 |
7543 | #define WD_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 |
7544 | #define WD_UTCL1_CNTL__BYPASS__SHIFT 0x19 |
7545 | #define WD_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a |
7546 | #define WD_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b |
7547 | #define WD_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c |
7548 | #define WD_UTCL1_CNTL__MTYPE_OVERRIDE__SHIFT 0x1d |
7549 | #define WD_UTCL1_CNTL__LLC_NOALLOC_OVERRIDE__SHIFT 0x1e |
7550 | #define WD_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL |
7551 | #define WD_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L |
7552 | #define WD_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L |
7553 | #define WD_UTCL1_CNTL__BYPASS_MASK 0x02000000L |
7554 | #define WD_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L |
7555 | #define WD_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L |
7556 | #define WD_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L |
7557 | #define WD_UTCL1_CNTL__MTYPE_OVERRIDE_MASK 0x20000000L |
7558 | #define WD_UTCL1_CNTL__LLC_NOALLOC_OVERRIDE_MASK 0x40000000L |
7559 | //WD_UTCL1_STATUS |
7560 | #define WD_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 |
7561 | #define WD_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 |
7562 | #define WD_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 |
7563 | #define WD_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8 |
7564 | #define WD_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10 |
7565 | #define WD_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18 |
7566 | #define WD_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L |
7567 | #define WD_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L |
7568 | #define WD_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L |
7569 | #define WD_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L |
7570 | #define WD_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L |
7571 | #define WD_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L |
7572 | //IA_UTCL1_CNTL |
7573 | #define IA_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 |
7574 | #define IA_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x17 |
7575 | #define IA_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 |
7576 | #define IA_UTCL1_CNTL__BYPASS__SHIFT 0x19 |
7577 | #define IA_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a |
7578 | #define IA_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b |
7579 | #define IA_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c |
7580 | #define IA_UTCL1_CNTL__MTYPE_OVERRIDE__SHIFT 0x1d |
7581 | #define IA_UTCL1_CNTL__LLC_NOALLOC_OVERRIDE__SHIFT 0x1e |
7582 | #define IA_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL |
7583 | #define IA_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L |
7584 | #define IA_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L |
7585 | #define IA_UTCL1_CNTL__BYPASS_MASK 0x02000000L |
7586 | #define IA_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L |
7587 | #define IA_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L |
7588 | #define IA_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L |
7589 | #define IA_UTCL1_CNTL__MTYPE_OVERRIDE_MASK 0x20000000L |
7590 | #define IA_UTCL1_CNTL__LLC_NOALLOC_OVERRIDE_MASK 0x40000000L |
7591 | //IA_UTCL1_STATUS |
7592 | #define IA_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 |
7593 | #define IA_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 |
7594 | #define IA_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 |
7595 | #define IA_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8 |
7596 | #define IA_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10 |
7597 | #define IA_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18 |
7598 | #define IA_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L |
7599 | #define IA_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L |
7600 | #define IA_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L |
7601 | #define IA_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L |
7602 | #define IA_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L |
7603 | #define IA_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L |
7604 | //CC_GC_SA_UNIT_DISABLE |
7605 | #define CC_GC_SA_UNIT_DISABLE__WRITE_DIS__SHIFT 0x0 |
7606 | #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT 0x8 |
7607 | #define CC_GC_SA_UNIT_DISABLE__WRITE_DIS_MASK 0x00000001L |
7608 | #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK 0x00FFFF00L |
7609 | //GE_RATE_CNTL_1 |
7610 | #define GE_RATE_CNTL_1__ADD_X_CLKS_LS_VERT__SHIFT 0x0 |
7611 | #define GE_RATE_CNTL_1__AFTER_Y_TRANS_LS_VERT__SHIFT 0x4 |
7612 | #define GE_RATE_CNTL_1__ADD_X_CLKS_HS_VERT__SHIFT 0x8 |
7613 | #define GE_RATE_CNTL_1__AFTER_Y_TRANS_HS_VERT__SHIFT 0xc |
7614 | #define GE_RATE_CNTL_1__ADD_X_CLKS_ES_VERT__SHIFT 0x10 |
7615 | #define GE_RATE_CNTL_1__AFTER_Y_TRANS_ES_VERT__SHIFT 0x14 |
7616 | #define GE_RATE_CNTL_1__ADD_X_CLKS_GS_PRIM__SHIFT 0x18 |
7617 | #define GE_RATE_CNTL_1__AFTER_Y_TRANS_GS_PRIM__SHIFT 0x1c |
7618 | #define GE_RATE_CNTL_1__ADD_X_CLKS_LS_VERT_MASK 0x0000000FL |
7619 | #define GE_RATE_CNTL_1__AFTER_Y_TRANS_LS_VERT_MASK 0x000000F0L |
7620 | #define GE_RATE_CNTL_1__ADD_X_CLKS_HS_VERT_MASK 0x00000F00L |
7621 | #define GE_RATE_CNTL_1__AFTER_Y_TRANS_HS_VERT_MASK 0x0000F000L |
7622 | #define GE_RATE_CNTL_1__ADD_X_CLKS_ES_VERT_MASK 0x000F0000L |
7623 | #define GE_RATE_CNTL_1__AFTER_Y_TRANS_ES_VERT_MASK 0x00F00000L |
7624 | #define GE_RATE_CNTL_1__ADD_X_CLKS_GS_PRIM_MASK 0x0F000000L |
7625 | #define GE_RATE_CNTL_1__AFTER_Y_TRANS_GS_PRIM_MASK 0xF0000000L |
7626 | //GE_RATE_CNTL_2 |
7627 | #define GE_RATE_CNTL_2__ADD_X_CLKS_VS_VERT__SHIFT 0x0 |
7628 | #define GE_RATE_CNTL_2__AFTER_Y_TRANS_VS_VERT__SHIFT 0x4 |
7629 | #define GE_RATE_CNTL_2__ADD_X_CLKS_PA_PRIM__SHIFT 0x8 |
7630 | #define GE_RATE_CNTL_2__AFTER_Y_TRANS_PA_PRIM__SHIFT 0xc |
7631 | #define GE_RATE_CNTL_2__ADD_X_CLKS_MERGED_HS_GS__SHIFT 0x10 |
7632 | #define GE_RATE_CNTL_2__ADD_X_CLKS_MERGED_LS_ES__SHIFT 0x14 |
7633 | #define GE_RATE_CNTL_2__MERGED_HS_GS_MODE__SHIFT 0x18 |
7634 | #define GE_RATE_CNTL_2__MERGED_LS_ES_MODE__SHIFT 0x19 |
7635 | #define GE_RATE_CNTL_2__ENABLE_RATE_CNTL__SHIFT 0x1a |
7636 | #define GE_RATE_CNTL_2__SWAP_PRIORITY__SHIFT 0x1b |
7637 | #define GE_RATE_CNTL_2__ADD_X_CLKS_VS_VERT_MASK 0x0000000FL |
7638 | #define GE_RATE_CNTL_2__AFTER_Y_TRANS_VS_VERT_MASK 0x000000F0L |
7639 | #define GE_RATE_CNTL_2__ADD_X_CLKS_PA_PRIM_MASK 0x00000F00L |
7640 | #define GE_RATE_CNTL_2__AFTER_Y_TRANS_PA_PRIM_MASK 0x0000F000L |
7641 | #define GE_RATE_CNTL_2__ADD_X_CLKS_MERGED_HS_GS_MASK 0x000F0000L |
7642 | #define GE_RATE_CNTL_2__ADD_X_CLKS_MERGED_LS_ES_MASK 0x00F00000L |
7643 | #define GE_RATE_CNTL_2__MERGED_HS_GS_MODE_MASK 0x01000000L |
7644 | #define GE_RATE_CNTL_2__MERGED_LS_ES_MODE_MASK 0x02000000L |
7645 | #define GE_RATE_CNTL_2__ENABLE_RATE_CNTL_MASK 0x04000000L |
7646 | #define GE_RATE_CNTL_2__SWAP_PRIORITY_MASK 0x08000000L |
7647 | //VGT_SYS_CONFIG |
7648 | #define VGT_SYS_CONFIG__DUAL_CORE_EN__SHIFT 0x0 |
7649 | #define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP__SHIFT 0x1 |
7650 | #define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE__SHIFT 0x7 |
7651 | #define VGT_SYS_CONFIG__NUM_SUBGROUPS_IN_FLIGHT__SHIFT 0x8 |
7652 | #define VGT_SYS_CONFIG__DUAL_CORE_EN_MASK 0x00000001L |
7653 | #define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP_MASK 0x0000007EL |
7654 | #define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE_MASK 0x00000080L |
7655 | #define VGT_SYS_CONFIG__NUM_SUBGROUPS_IN_FLIGHT_MASK 0x0007FF00L |
7656 | //GE_PRIV_CONTROL |
7657 | #define GE_PRIV_CONTROL__RESERVED__SHIFT 0x0 |
7658 | #define GE_PRIV_CONTROL__CLAMP_PRIMGRP_SIZE__SHIFT 0x1 |
7659 | #define GE_PRIV_CONTROL__RESET_ON_PIPELINE_CHANGE__SHIFT 0xa |
7660 | #define GE_PRIV_CONTROL__FGCG_OVERRIDE__SHIFT 0xf |
7661 | #define GE_PRIV_CONTROL__CLAMP_HS_OFFCHIP_PER_SE_OVERRIDE__SHIFT 0x10 |
7662 | #define GE_PRIV_CONTROL__DISABLE_ACCUM_AGM__SHIFT 0x11 |
7663 | #define GE_PRIV_CONTROL__RESERVED_MASK 0x00000001L |
7664 | #define GE_PRIV_CONTROL__CLAMP_PRIMGRP_SIZE_MASK 0x000003FEL |
7665 | #define GE_PRIV_CONTROL__RESET_ON_PIPELINE_CHANGE_MASK 0x00000400L |
7666 | #define GE_PRIV_CONTROL__FGCG_OVERRIDE_MASK 0x00008000L |
7667 | #define GE_PRIV_CONTROL__CLAMP_HS_OFFCHIP_PER_SE_OVERRIDE_MASK 0x00010000L |
7668 | #define GE_PRIV_CONTROL__DISABLE_ACCUM_AGM_MASK 0x00020000L |
7669 | //GE_STATUS |
7670 | #define GE_STATUS__PERFCOUNTER_STATUS__SHIFT 0x0 |
7671 | #define GE_STATUS__THREAD_TRACE_STATUS__SHIFT 0x1 |
7672 | #define GE_STATUS__PERFCOUNTER_STATUS_MASK 0x00000001L |
7673 | #define GE_STATUS__THREAD_TRACE_STATUS_MASK 0x00000002L |
7674 | //VGT_GS_MAX_WAVE_ID |
7675 | #define VGT_GS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0 |
7676 | #define VGT_GS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000FFFL |
7677 | //GFX_PIPE_CONTROL |
7678 | #define GFX_PIPE_CONTROL__HYSTERESIS_CNT__SHIFT 0x0 |
7679 | #define GFX_PIPE_CONTROL__RESERVED__SHIFT 0xd |
7680 | #define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN__SHIFT 0x10 |
7681 | #define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_STALL_EN__SHIFT 0x11 |
7682 | #define GFX_PIPE_CONTROL__HYSTERESIS_CNT_MASK 0x00001FFFL |
7683 | #define GFX_PIPE_CONTROL__RESERVED_MASK 0x0000E000L |
7684 | #define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN_MASK 0x00010000L |
7685 | #define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_STALL_EN_MASK 0x00020000L |
7686 | //CC_GC_SHADER_ARRAY_CONFIG |
7687 | #define CC_GC_SHADER_ARRAY_CONFIG__WRITE_DIS__SHIFT 0x0 |
7688 | #define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT 0x10 |
7689 | #define CC_GC_SHADER_ARRAY_CONFIG__WRITE_DIS_MASK 0x00000001L |
7690 | #define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK 0xFFFF0000L |
7691 | //GE2_SE_CNTL_STATUS |
7692 | #define GE2_SE_CNTL_STATUS__TE_BUSY__SHIFT 0x0 |
7693 | #define GE2_SE_CNTL_STATUS__NGG_BUSY__SHIFT 0x1 |
7694 | #define GE2_SE_CNTL_STATUS__HS_BUSY__SHIFT 0x2 |
7695 | #define GE2_SE_CNTL_STATUS__TE_BUSY_MASK 0x00000001L |
7696 | #define GE2_SE_CNTL_STATUS__NGG_BUSY_MASK 0x00000002L |
7697 | #define GE2_SE_CNTL_STATUS__HS_BUSY_MASK 0x00000004L |
7698 | //VGT_RESET_DEBUG |
7699 | #define VGT_RESET_DEBUG__GS_DISABLE__SHIFT 0x0 |
7700 | #define VGT_RESET_DEBUG__TESS_DISABLE__SHIFT 0x1 |
7701 | #define VGT_RESET_DEBUG__WD_DISABLE__SHIFT 0x2 |
7702 | #define VGT_RESET_DEBUG__DISABLE_TE11_DIST_PIPE0__SHIFT 0x3 |
7703 | #define VGT_RESET_DEBUG__DISABLE_TE11_DIST_PIPE1__SHIFT 0x4 |
7704 | #define VGT_RESET_DEBUG__ENABLE_VMID_RESET_UTCL1__SHIFT 0x5 |
7705 | #define VGT_RESET_DEBUG__DISABLE_PREFETCH__SHIFT 0x6 |
7706 | #define VGT_RESET_DEBUG__DISABLE_SWITCH_MODE_STALL_FIX__SHIFT 0x7 |
7707 | #define VGT_RESET_DEBUG__DISABLE_SENDING_MULTIPLE_SE_IN_PD__SHIFT 0x8 |
7708 | #define VGT_RESET_DEBUG__ENABLE_DIST_STALL_TESS_ON_OFF__SHIFT 0x9 |
7709 | #define VGT_RESET_DEBUG__DISABLE_PATCH_OPTIMIZATION__SHIFT 0xa |
7710 | #define VGT_RESET_DEBUG__ENABLE_DIST_STALL_TESS_OFF_ON__SHIFT 0xb |
7711 | #define VGT_RESET_DEBUG__DISABLE_MERGE_GRP_PERF_FIX__SHIFT 0xc |
7712 | #define VGT_RESET_DEBUG__DISABLE_MESH_SHADER_ATTR_PACKING__SHIFT 0xd |
7713 | #define VGT_RESET_DEBUG__ENABLE_SMALL_INST_PACK_ADJ_GS_OFF__SHIFT 0xe |
7714 | #define VGT_RESET_DEBUG__DISABLE_PATCH_DIST_LAST_DONUT_SE_SWITCH_LOGIC__SHIFT 0xf |
7715 | #define VGT_RESET_DEBUG__SPARE__SHIFT 0x10 |
7716 | #define VGT_RESET_DEBUG__GS_DISABLE_MASK 0x00000001L |
7717 | #define VGT_RESET_DEBUG__TESS_DISABLE_MASK 0x00000002L |
7718 | #define VGT_RESET_DEBUG__WD_DISABLE_MASK 0x00000004L |
7719 | #define VGT_RESET_DEBUG__DISABLE_TE11_DIST_PIPE0_MASK 0x00000008L |
7720 | #define VGT_RESET_DEBUG__DISABLE_TE11_DIST_PIPE1_MASK 0x00000010L |
7721 | #define VGT_RESET_DEBUG__ENABLE_VMID_RESET_UTCL1_MASK 0x00000020L |
7722 | #define VGT_RESET_DEBUG__DISABLE_PREFETCH_MASK 0x00000040L |
7723 | #define VGT_RESET_DEBUG__DISABLE_SWITCH_MODE_STALL_FIX_MASK 0x00000080L |
7724 | #define VGT_RESET_DEBUG__DISABLE_SENDING_MULTIPLE_SE_IN_PD_MASK 0x00000100L |
7725 | #define VGT_RESET_DEBUG__ENABLE_DIST_STALL_TESS_ON_OFF_MASK 0x00000200L |
7726 | #define VGT_RESET_DEBUG__DISABLE_PATCH_OPTIMIZATION_MASK 0x00000400L |
7727 | #define VGT_RESET_DEBUG__ENABLE_DIST_STALL_TESS_OFF_ON_MASK 0x00000800L |
7728 | #define VGT_RESET_DEBUG__DISABLE_MERGE_GRP_PERF_FIX_MASK 0x00001000L |
7729 | #define VGT_RESET_DEBUG__DISABLE_MESH_SHADER_ATTR_PACKING_MASK 0x00002000L |
7730 | #define VGT_RESET_DEBUG__ENABLE_SMALL_INST_PACK_ADJ_GS_OFF_MASK 0x00004000L |
7731 | #define VGT_RESET_DEBUG__DISABLE_PATCH_DIST_LAST_DONUT_SE_SWITCH_LOGIC_MASK 0x00008000L |
7732 | #define VGT_RESET_DEBUG__SPARE_MASK 0xFFFF0000L |
7733 | //GE_SPI_IF_SAFE_REG |
7734 | #define GE_SPI_IF_SAFE_REG__GE_SPI_LS_ES_DATA__SHIFT 0x0 |
7735 | #define GE_SPI_IF_SAFE_REG__GE_SPI_HS_GS_DATA__SHIFT 0x6 |
7736 | #define GE_SPI_IF_SAFE_REG__GE_SPI_GRP__SHIFT 0xc |
7737 | #define GE_SPI_IF_SAFE_REG__GE_SPI_LS_ES_DATA_MASK 0x0000003FL |
7738 | #define GE_SPI_IF_SAFE_REG__GE_SPI_HS_GS_DATA_MASK 0x00000FC0L |
7739 | #define GE_SPI_IF_SAFE_REG__GE_SPI_GRP_MASK 0x0003F000L |
7740 | //GE_PA_IF_SAFE_REG |
7741 | #define GE_PA_IF_SAFE_REG__GE_PA_CSB__SHIFT 0x0 |
7742 | #define GE_PA_IF_SAFE_REG__GE_PA_PAYLOAD__SHIFT 0xa |
7743 | #define GE_PA_IF_SAFE_REG__GE_PA_CSB_MASK 0x000003FFL |
7744 | #define GE_PA_IF_SAFE_REG__GE_PA_PAYLOAD_MASK 0x000FFC00L |
7745 | //PA_CL_CNTL_STATUS |
7746 | #define PA_CL_CNTL_STATUS__CL_BUSY__SHIFT 0x1f |
7747 | #define PA_CL_CNTL_STATUS__CL_BUSY_MASK 0x80000000L |
7748 | //PA_CL_ENHANCE |
7749 | #define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA__SHIFT 0x0 |
7750 | #define PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT 0x1 |
7751 | #define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL__SHIFT 0x3 |
7752 | #define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE__SHIFT 0x4 |
7753 | #define PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL__SHIFT 0x5 |
7754 | #define PA_CL_ENHANCE__IGNORE_PIPELINE_RESET__SHIFT 0x6 |
7755 | #define PA_CL_ENHANCE__KILL_INNER_EDGE_FLAGS__SHIFT 0x7 |
7756 | #define PA_CL_ENHANCE__NGG_PA_TO_ALL_SC__SHIFT 0x8 |
7757 | #define PA_CL_ENHANCE__TC_LATENCY_TIME_STAMP_RESOLUTION__SHIFT 0x9 |
7758 | #define PA_CL_ENHANCE__NGG_BYPASS_PRIM_FILTER__SHIFT 0xb |
7759 | #define PA_CL_ENHANCE__NGG_SIDEBAND_MEMORY_DEPTH__SHIFT 0xc |
7760 | #define PA_CL_ENHANCE__NGG_PRIM_INDICES_FIFO_DEPTH__SHIFT 0xe |
7761 | #define PA_CL_ENHANCE__PROG_NEAR_CLIP_PLANE_ENABLE__SHIFT 0x11 |
7762 | #define PA_CL_ENHANCE__POLY_INNER_EDGE_FLAG_DISABLE__SHIFT 0x12 |
7763 | #define PA_CL_ENHANCE__TC_REQUEST_PERF_CNTR_ENABLE__SHIFT 0x13 |
7764 | #define PA_CL_ENHANCE__DISABLE_PA_PH_INTF_FINE_CLOCK_GATE__SHIFT 0x14 |
7765 | #define PA_CL_ENHANCE__DISABLE_PA_SX_REQ_INTF_FINE_CLOCK_GATE__SHIFT 0x15 |
7766 | #define PA_CL_ENHANCE__ENABLE_PA_RATE_CNTL__SHIFT 0x16 |
7767 | #define PA_CL_ENHANCE__CLAMP_NEGATIVE_BB_TO_ZERO__SHIFT 0x17 |
7768 | #define PA_CL_ENHANCE__ECO_SPARE3__SHIFT 0x1c |
7769 | #define PA_CL_ENHANCE__ECO_SPARE2__SHIFT 0x1d |
7770 | #define PA_CL_ENHANCE__ECO_SPARE1__SHIFT 0x1e |
7771 | #define PA_CL_ENHANCE__ECO_SPARE0__SHIFT 0x1f |
7772 | #define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK 0x00000001L |
7773 | #define PA_CL_ENHANCE__NUM_CLIP_SEQ_MASK 0x00000006L |
7774 | #define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL_MASK 0x00000008L |
7775 | #define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE_MASK 0x00000010L |
7776 | #define PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL_MASK 0x00000020L |
7777 | #define PA_CL_ENHANCE__IGNORE_PIPELINE_RESET_MASK 0x00000040L |
7778 | #define PA_CL_ENHANCE__KILL_INNER_EDGE_FLAGS_MASK 0x00000080L |
7779 | #define PA_CL_ENHANCE__NGG_PA_TO_ALL_SC_MASK 0x00000100L |
7780 | #define PA_CL_ENHANCE__TC_LATENCY_TIME_STAMP_RESOLUTION_MASK 0x00000600L |
7781 | #define PA_CL_ENHANCE__NGG_BYPASS_PRIM_FILTER_MASK 0x00000800L |
7782 | #define PA_CL_ENHANCE__NGG_SIDEBAND_MEMORY_DEPTH_MASK 0x00003000L |
7783 | #define PA_CL_ENHANCE__NGG_PRIM_INDICES_FIFO_DEPTH_MASK 0x0001C000L |
7784 | #define PA_CL_ENHANCE__PROG_NEAR_CLIP_PLANE_ENABLE_MASK 0x00020000L |
7785 | #define PA_CL_ENHANCE__POLY_INNER_EDGE_FLAG_DISABLE_MASK 0x00040000L |
7786 | #define PA_CL_ENHANCE__TC_REQUEST_PERF_CNTR_ENABLE_MASK 0x00080000L |
7787 | #define PA_CL_ENHANCE__DISABLE_PA_PH_INTF_FINE_CLOCK_GATE_MASK 0x00100000L |
7788 | #define PA_CL_ENHANCE__DISABLE_PA_SX_REQ_INTF_FINE_CLOCK_GATE_MASK 0x00200000L |
7789 | #define PA_CL_ENHANCE__ENABLE_PA_RATE_CNTL_MASK 0x00400000L |
7790 | #define PA_CL_ENHANCE__CLAMP_NEGATIVE_BB_TO_ZERO_MASK 0x00800000L |
7791 | #define PA_CL_ENHANCE__ECO_SPARE3_MASK 0x10000000L |
7792 | #define PA_CL_ENHANCE__ECO_SPARE2_MASK 0x20000000L |
7793 | #define PA_CL_ENHANCE__ECO_SPARE1_MASK 0x40000000L |
7794 | #define PA_CL_ENHANCE__ECO_SPARE0_MASK 0x80000000L |
7795 | //PA_CL_RESET_DEBUG |
7796 | #define PA_CL_RESET_DEBUG__CL_TRIV_DISC_DISABLE__SHIFT 0x0 |
7797 | #define PA_CL_RESET_DEBUG__CL_TRIV_DISC_DISABLE_MASK 0x00000001L |
7798 | //PA_SU_CNTL_STATUS |
7799 | #define PA_SU_CNTL_STATUS__SU_BUSY__SHIFT 0x1f |
7800 | #define PA_SU_CNTL_STATUS__SU_BUSY_MASK 0x80000000L |
7801 | //PA_SC_FIFO_DEPTH_CNTL |
7802 | #define PA_SC_FIFO_DEPTH_CNTL__DEPTH__SHIFT 0x0 |
7803 | #define PA_SC_FIFO_DEPTH_CNTL__DEPTH_MASK 0x000003FFL |
7804 | |
7805 | |
7806 | // addressBlock: gc_sqdec |
7807 | //SQ_CONFIG |
7808 | #define SQ_CONFIG__ECO_SPARE__SHIFT 0x0 |
7809 | #define SQ_CONFIG__NEW_TRANS_ARB_SCHEME__SHIFT 0x8 |
7810 | #define SQ_CONFIG__DISABLE_VMEM_EXEC_ZERO_SKIP__SHIFT 0x9 |
7811 | #define SQ_CONFIG__DISABLE_SGPR_RD_KILL__SHIFT 0xa |
7812 | #define SQ_CONFIG__ENABLE_HIPRIO_ON_EXP_RDY_GS__SHIFT 0x12 |
7813 | #define SQ_CONFIG__PRIO_VAL_ON_EXP_RDY_GS__SHIFT 0x13 |
7814 | #define SQ_CONFIG__WCLK_HYSTERESIS_CNT__SHIFT 0x15 |
7815 | #define SQ_CONFIG__DISABLE_END_CLAUSE_TX__SHIFT 0x1b |
7816 | #define SQ_CONFIG__ECO_SPARE_MASK 0x000000FFL |
7817 | #define SQ_CONFIG__NEW_TRANS_ARB_SCHEME_MASK 0x00000100L |
7818 | #define SQ_CONFIG__DISABLE_VMEM_EXEC_ZERO_SKIP_MASK 0x00000200L |
7819 | #define SQ_CONFIG__DISABLE_SGPR_RD_KILL_MASK 0x00000400L |
7820 | #define SQ_CONFIG__ENABLE_HIPRIO_ON_EXP_RDY_GS_MASK 0x00040000L |
7821 | #define SQ_CONFIG__PRIO_VAL_ON_EXP_RDY_GS_MASK 0x00180000L |
7822 | #define SQ_CONFIG__WCLK_HYSTERESIS_CNT_MASK 0x00600000L |
7823 | #define SQ_CONFIG__DISABLE_END_CLAUSE_TX_MASK 0x08000000L |
7824 | //SQC_CONFIG |
7825 | #define SQC_CONFIG__INST_CACHE_SIZE__SHIFT 0x0 |
7826 | #define SQC_CONFIG__DATA_CACHE_SIZE__SHIFT 0x2 |
7827 | #define SQC_CONFIG__MISS_FIFO_DEPTH__SHIFT 0x4 |
7828 | #define SQC_CONFIG__HIT_FIFO_DEPTH__SHIFT 0x6 |
7829 | #define SQC_CONFIG__FORCE_ALWAYS_MISS__SHIFT 0x7 |
7830 | #define SQC_CONFIG__FORCE_IN_ORDER__SHIFT 0x8 |
7831 | #define SQC_CONFIG__PER_VMID_INV_DISABLE__SHIFT 0x9 |
7832 | #define SQC_CONFIG__EVICT_LRU__SHIFT 0xa |
7833 | #define SQC_CONFIG__FORCE_2_BANK__SHIFT 0xc |
7834 | #define SQC_CONFIG__FORCE_1_BANK__SHIFT 0xd |
7835 | #define SQC_CONFIG__LS_DISABLE_CLOCKS__SHIFT 0xe |
7836 | #define SQC_CONFIG__CACHE_CTRL_GCR_FIX_DISABLE__SHIFT 0x16 |
7837 | #define SQC_CONFIG__CACHE_CTRL_ALMOST_MAX_INFLIGHT_CONFIG__SHIFT 0x17 |
7838 | #define SQC_CONFIG__SPARE__SHIFT 0x1a |
7839 | #define SQC_CONFIG__INST_CACHE_SIZE_MASK 0x00000003L |
7840 | #define SQC_CONFIG__DATA_CACHE_SIZE_MASK 0x0000000CL |
7841 | #define SQC_CONFIG__MISS_FIFO_DEPTH_MASK 0x00000030L |
7842 | #define SQC_CONFIG__HIT_FIFO_DEPTH_MASK 0x00000040L |
7843 | #define SQC_CONFIG__FORCE_ALWAYS_MISS_MASK 0x00000080L |
7844 | #define SQC_CONFIG__FORCE_IN_ORDER_MASK 0x00000100L |
7845 | #define SQC_CONFIG__PER_VMID_INV_DISABLE_MASK 0x00000200L |
7846 | #define SQC_CONFIG__EVICT_LRU_MASK 0x00000C00L |
7847 | #define SQC_CONFIG__FORCE_2_BANK_MASK 0x00001000L |
7848 | #define SQC_CONFIG__FORCE_1_BANK_MASK 0x00002000L |
7849 | #define SQC_CONFIG__LS_DISABLE_CLOCKS_MASK 0x003FC000L |
7850 | #define SQC_CONFIG__CACHE_CTRL_GCR_FIX_DISABLE_MASK 0x00400000L |
7851 | #define SQC_CONFIG__CACHE_CTRL_ALMOST_MAX_INFLIGHT_CONFIG_MASK 0x03800000L |
7852 | #define SQC_CONFIG__SPARE_MASK 0xFC000000L |
7853 | //LDS_CONFIG |
7854 | #define LDS_CONFIG__ADDR_OUT_OF_RANGE_REPORTING__SHIFT 0x0 |
7855 | #define LDS_CONFIG__CONF_BIT_1__SHIFT 0x1 |
7856 | #define LDS_CONFIG__WAVE32_INTERP_DUAL_ISSUE_DISABLE__SHIFT 0x2 |
7857 | #define LDS_CONFIG__SP_TDDATA_FGCG_OVERRIDE__SHIFT 0x3 |
7858 | #define LDS_CONFIG__SQC_PERF_FGCG_OVERRIDE__SHIFT 0x4 |
7859 | #define LDS_CONFIG__CONF_BIT_5__SHIFT 0x5 |
7860 | #define LDS_CONFIG__CONF_BIT_6__SHIFT 0x6 |
7861 | #define LDS_CONFIG__CONF_BIT_7__SHIFT 0x7 |
7862 | #define LDS_CONFIG__CONF_BIT_8__SHIFT 0x8 |
7863 | #define LDS_CONFIG__ADDR_OUT_OF_RANGE_REPORTING_MASK 0x00000001L |
7864 | #define LDS_CONFIG__CONF_BIT_1_MASK 0x00000002L |
7865 | #define LDS_CONFIG__WAVE32_INTERP_DUAL_ISSUE_DISABLE_MASK 0x00000004L |
7866 | #define LDS_CONFIG__SP_TDDATA_FGCG_OVERRIDE_MASK 0x00000008L |
7867 | #define LDS_CONFIG__SQC_PERF_FGCG_OVERRIDE_MASK 0x00000010L |
7868 | #define LDS_CONFIG__CONF_BIT_5_MASK 0x00000020L |
7869 | #define LDS_CONFIG__CONF_BIT_6_MASK 0x00000040L |
7870 | #define LDS_CONFIG__CONF_BIT_7_MASK 0x00000080L |
7871 | #define LDS_CONFIG__CONF_BIT_8_MASK 0x00000100L |
7872 | //SQ_RANDOM_WAVE_PRI |
7873 | #define SQ_RANDOM_WAVE_PRI__RET__SHIFT 0x0 |
7874 | #define SQ_RANDOM_WAVE_PRI__RUI__SHIFT 0x7 |
7875 | #define SQ_RANDOM_WAVE_PRI__RNG__SHIFT 0xa |
7876 | #define SQ_RANDOM_WAVE_PRI__FORCE_IB_ARB_PRIO_MSK_VALID__SHIFT 0x1f |
7877 | #define SQ_RANDOM_WAVE_PRI__RET_MASK 0x0000007FL |
7878 | #define SQ_RANDOM_WAVE_PRI__RUI_MASK 0x00000380L |
7879 | #define SQ_RANDOM_WAVE_PRI__RNG_MASK 0x00FFFC00L |
7880 | #define SQ_RANDOM_WAVE_PRI__FORCE_IB_ARB_PRIO_MSK_VALID_MASK 0x80000000L |
7881 | //SQG_STATUS |
7882 | #define SQG_STATUS__REG_BUSY__SHIFT 0x0 |
7883 | #define SQG_STATUS__REG_BUSY_MASK 0x00000001L |
7884 | //SQ_FIFO_SIZES |
7885 | #define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE__SHIFT 0x0 |
7886 | #define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE__SHIFT 0x8 |
7887 | #define SQ_FIFO_SIZES__EXPORT_BUF_GS_RESERVED__SHIFT 0xc |
7888 | #define SQ_FIFO_SIZES__EXPORT_BUF_PS_RESERVED__SHIFT 0xe |
7889 | #define SQ_FIFO_SIZES__EXPORT_BUF_REDUCE__SHIFT 0x10 |
7890 | #define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE__SHIFT 0x12 |
7891 | #define SQ_FIFO_SIZES__EXPORT_BUF_PRIMPOS_LIMIT__SHIFT 0x14 |
7892 | #define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE_MASK 0x0000000FL |
7893 | #define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE_MASK 0x00000300L |
7894 | #define SQ_FIFO_SIZES__EXPORT_BUF_GS_RESERVED_MASK 0x00003000L |
7895 | #define SQ_FIFO_SIZES__EXPORT_BUF_PS_RESERVED_MASK 0x0000C000L |
7896 | #define SQ_FIFO_SIZES__EXPORT_BUF_REDUCE_MASK 0x00030000L |
7897 | #define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE_MASK 0x000C0000L |
7898 | #define SQ_FIFO_SIZES__EXPORT_BUF_PRIMPOS_LIMIT_MASK 0x00300000L |
7899 | //SQ_DSM_CNTL |
7900 | #define SQ_DSM_CNTL__WAVEFRONT_STALL_0__SHIFT 0x0 |
7901 | #define SQ_DSM_CNTL__WAVEFRONT_STALL_1__SHIFT 0x1 |
7902 | #define SQ_DSM_CNTL__SPI_BACKPRESSURE_0__SHIFT 0x2 |
7903 | #define SQ_DSM_CNTL__SPI_BACKPRESSURE_1__SHIFT 0x3 |
7904 | #define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA0__SHIFT 0x8 |
7905 | #define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA1__SHIFT 0x9 |
7906 | #define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE__SHIFT 0xa |
7907 | #define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA0__SHIFT 0x10 |
7908 | #define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA1__SHIFT 0x11 |
7909 | #define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE01__SHIFT 0x12 |
7910 | #define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA2__SHIFT 0x13 |
7911 | #define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA3__SHIFT 0x14 |
7912 | #define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE23__SHIFT 0x15 |
7913 | #define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA0__SHIFT 0x18 |
7914 | #define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA1__SHIFT 0x19 |
7915 | #define SQ_DSM_CNTL__SP_ENABLE_SINGLE_WRITE__SHIFT 0x1a |
7916 | #define SQ_DSM_CNTL__WAVEFRONT_STALL_0_MASK 0x00000001L |
7917 | #define SQ_DSM_CNTL__WAVEFRONT_STALL_1_MASK 0x00000002L |
7918 | #define SQ_DSM_CNTL__SPI_BACKPRESSURE_0_MASK 0x00000004L |
7919 | #define SQ_DSM_CNTL__SPI_BACKPRESSURE_1_MASK 0x00000008L |
7920 | #define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA0_MASK 0x00000100L |
7921 | #define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA1_MASK 0x00000200L |
7922 | #define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE_MASK 0x00000400L |
7923 | #define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA0_MASK 0x00010000L |
7924 | #define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA1_MASK 0x00020000L |
7925 | #define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE01_MASK 0x00040000L |
7926 | #define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA2_MASK 0x00080000L |
7927 | #define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA3_MASK 0x00100000L |
7928 | #define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE23_MASK 0x00200000L |
7929 | #define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA0_MASK 0x01000000L |
7930 | #define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA1_MASK 0x02000000L |
7931 | #define SQ_DSM_CNTL__SP_ENABLE_SINGLE_WRITE_MASK 0x04000000L |
7932 | //SQ_DSM_CNTL2 |
7933 | #define SQ_DSM_CNTL2__SGPR_ENABLE_ERROR_INJECT__SHIFT 0x0 |
7934 | #define SQ_DSM_CNTL2__SGPR_SELECT_INJECT_DELAY__SHIFT 0x2 |
7935 | #define SQ_DSM_CNTL2__LDS_D_ENABLE_ERROR_INJECT__SHIFT 0x3 |
7936 | #define SQ_DSM_CNTL2__LDS_D_SELECT_INJECT_DELAY__SHIFT 0x5 |
7937 | #define SQ_DSM_CNTL2__LDS_I_ENABLE_ERROR_INJECT__SHIFT 0x6 |
7938 | #define SQ_DSM_CNTL2__LDS_I_SELECT_INJECT_DELAY__SHIFT 0x8 |
7939 | #define SQ_DSM_CNTL2__SP_ENABLE_ERROR_INJECT__SHIFT 0x9 |
7940 | #define SQ_DSM_CNTL2__SP_SELECT_INJECT_DELAY__SHIFT 0xb |
7941 | #define SQ_DSM_CNTL2__LDS_INJECT_DELAY__SHIFT 0xe |
7942 | #define SQ_DSM_CNTL2__SP_INJECT_DELAY__SHIFT 0x14 |
7943 | #define SQ_DSM_CNTL2__SQ_INJECT_DELAY__SHIFT 0x1a |
7944 | #define SQ_DSM_CNTL2__SGPR_ENABLE_ERROR_INJECT_MASK 0x00000003L |
7945 | #define SQ_DSM_CNTL2__SGPR_SELECT_INJECT_DELAY_MASK 0x00000004L |
7946 | #define SQ_DSM_CNTL2__LDS_D_ENABLE_ERROR_INJECT_MASK 0x00000018L |
7947 | #define SQ_DSM_CNTL2__LDS_D_SELECT_INJECT_DELAY_MASK 0x00000020L |
7948 | #define SQ_DSM_CNTL2__LDS_I_ENABLE_ERROR_INJECT_MASK 0x000000C0L |
7949 | #define SQ_DSM_CNTL2__LDS_I_SELECT_INJECT_DELAY_MASK 0x00000100L |
7950 | #define SQ_DSM_CNTL2__SP_ENABLE_ERROR_INJECT_MASK 0x00000600L |
7951 | #define SQ_DSM_CNTL2__SP_SELECT_INJECT_DELAY_MASK 0x00000800L |
7952 | #define SQ_DSM_CNTL2__LDS_INJECT_DELAY_MASK 0x000FC000L |
7953 | #define SQ_DSM_CNTL2__SP_INJECT_DELAY_MASK 0x03F00000L |
7954 | #define SQ_DSM_CNTL2__SQ_INJECT_DELAY_MASK 0xFC000000L |
7955 | //SP_CONFIG |
7956 | #define SP_CONFIG__DEST_CACHE_EVICT_COUNTER__SHIFT 0x0 |
7957 | #define SP_CONFIG__ALU_BUSY_MGCG_OVERRIDE__SHIFT 0x2 |
7958 | #define SP_CONFIG__DISABLE_TRANS_COEXEC__SHIFT 0x3 |
7959 | #define SP_CONFIG__CAC_COUNTER_OVERRIDE__SHIFT 0x4 |
7960 | #define SP_CONFIG__SP_SX_EXPVDATA_FGCG_OVERRIDE__SHIFT 0x5 |
7961 | #define SP_CONFIG__DEST_CACHE_EVICT_COUNTER_MASK 0x00000003L |
7962 | #define SP_CONFIG__ALU_BUSY_MGCG_OVERRIDE_MASK 0x00000004L |
7963 | #define SP_CONFIG__DISABLE_TRANS_COEXEC_MASK 0x00000008L |
7964 | #define SP_CONFIG__CAC_COUNTER_OVERRIDE_MASK 0x00000010L |
7965 | #define SP_CONFIG__SP_SX_EXPVDATA_FGCG_OVERRIDE_MASK 0x00000020L |
7966 | //SQ_ARB_CONFIG |
7967 | #define SQ_ARB_CONFIG__WG_RR_INTERVAL__SHIFT 0x0 |
7968 | #define SQ_ARB_CONFIG__FWD_PROG_INTERVAL__SHIFT 0x4 |
7969 | #define SQ_ARB_CONFIG__WG_RR_INTERVAL_MASK 0x00000003L |
7970 | #define SQ_ARB_CONFIG__FWD_PROG_INTERVAL_MASK 0x00000030L |
7971 | //SQ_DEBUG_HOST_TRAP_STATUS |
7972 | #define SQ_DEBUG_HOST_TRAP_STATUS__PENDING_COUNT__SHIFT 0x0 |
7973 | #define SQ_DEBUG_HOST_TRAP_STATUS__PENDING_COUNT_MASK 0x0000007FL |
7974 | //SQG_GL1H_STATUS |
7975 | #define SQG_GL1H_STATUS__R0_ACK_ERR_DETECTED__SHIFT 0x0 |
7976 | #define SQG_GL1H_STATUS__R0_XNACK_ERR_DETECTED__SHIFT 0x1 |
7977 | #define SQG_GL1H_STATUS__R1_ACK_ERR_DETECTED__SHIFT 0x2 |
7978 | #define SQG_GL1H_STATUS__R1_XNACK_ERR_DETECTED__SHIFT 0x3 |
7979 | #define SQG_GL1H_STATUS__R0_ACK_ERR_DETECTED_MASK 0x00000001L |
7980 | #define SQG_GL1H_STATUS__R0_XNACK_ERR_DETECTED_MASK 0x00000002L |
7981 | #define SQG_GL1H_STATUS__R1_ACK_ERR_DETECTED_MASK 0x00000004L |
7982 | #define SQG_GL1H_STATUS__R1_XNACK_ERR_DETECTED_MASK 0x00000008L |
7983 | //SQG_CONFIG |
7984 | #define SQG_CONFIG__GL1H_PREFETCH_PAGE__SHIFT 0x0 |
7985 | #define SQG_CONFIG__SQG_ICPFT_EN__SHIFT 0xd |
7986 | #define SQG_CONFIG__SQG_ICPFT_CLR__SHIFT 0xe |
7987 | #define SQG_CONFIG__XNACK_INTR_MASK__SHIFT 0x10 |
7988 | #define SQG_CONFIG__GL1H_PREFETCH_PAGE_MASK 0x0000000FL |
7989 | #define SQG_CONFIG__SQG_ICPFT_EN_MASK 0x00002000L |
7990 | #define SQG_CONFIG__SQG_ICPFT_CLR_MASK 0x00004000L |
7991 | #define SQG_CONFIG__XNACK_INTR_MASK_MASK 0xFFFF0000L |
7992 | //SQ_PERF_SNAPSHOT_CTRL |
7993 | #define SQ_PERF_SNAPSHOT_CTRL__TIMER_ON_OFF__SHIFT 0x0 |
7994 | #define SQ_PERF_SNAPSHOT_CTRL__VMID_MASK__SHIFT 0x1 |
7995 | #define SQ_PERF_SNAPSHOT_CTRL__COUNT_SEL__SHIFT 0x11 |
7996 | #define SQ_PERF_SNAPSHOT_CTRL__COUNT_INTERVAL__SHIFT 0x12 |
7997 | #define SQ_PERF_SNAPSHOT_CTRL__TIMER_ON_OFF_MASK 0x00000001L |
7998 | #define SQ_PERF_SNAPSHOT_CTRL__VMID_MASK_MASK 0x0001FFFEL |
7999 | #define SQ_PERF_SNAPSHOT_CTRL__COUNT_SEL_MASK 0x00020000L |
8000 | #define SQ_PERF_SNAPSHOT_CTRL__COUNT_INTERVAL_MASK 0x003C0000L |
8001 | //CC_GC_SHADER_RATE_CONFIG |
8002 | #define CC_GC_SHADER_RATE_CONFIG__WRITE_DIS__SHIFT 0x0 |
8003 | #define CC_GC_SHADER_RATE_CONFIG__DPFP_RATE__SHIFT 0x1 |
8004 | #define CC_GC_SHADER_RATE_CONFIG__WRITE_DIS_MASK 0x00000001L |
8005 | #define CC_GC_SHADER_RATE_CONFIG__DPFP_RATE_MASK 0x00000006L |
8006 | //SQ_INTERRUPT_AUTO_MASK |
8007 | #define SQ_INTERRUPT_AUTO_MASK__MASK__SHIFT 0x0 |
8008 | #define SQ_INTERRUPT_AUTO_MASK__MASK_MASK 0x00FFFFFFL |
8009 | //SQ_INTERRUPT_MSG_CTRL |
8010 | #define SQ_INTERRUPT_MSG_CTRL__STALL__SHIFT 0x0 |
8011 | #define SQ_INTERRUPT_MSG_CTRL__STALL_MASK 0x00000001L |
8012 | //SQ_WATCH0_ADDR_H |
8013 | #define SQ_WATCH0_ADDR_H__ADDR__SHIFT 0x0 |
8014 | #define SQ_WATCH0_ADDR_H__ADDR_MASK 0x0000FFFFL |
8015 | //SQ_WATCH0_ADDR_L |
8016 | #define SQ_WATCH0_ADDR_L__ADDR__SHIFT 0x6 |
8017 | #define SQ_WATCH0_ADDR_L__ADDR_MASK 0xFFFFFFC0L |
8018 | //SQ_WATCH0_CNTL |
8019 | #define SQ_WATCH0_CNTL__MASK__SHIFT 0x0 |
8020 | #define SQ_WATCH0_CNTL__VMID__SHIFT 0x18 |
8021 | #define SQ_WATCH0_CNTL__VALID__SHIFT 0x1f |
8022 | #define SQ_WATCH0_CNTL__MASK_MASK 0x00FFFFFFL |
8023 | #define SQ_WATCH0_CNTL__VMID_MASK 0x0F000000L |
8024 | #define SQ_WATCH0_CNTL__VALID_MASK 0x80000000L |
8025 | //SQ_WATCH1_ADDR_H |
8026 | #define SQ_WATCH1_ADDR_H__ADDR__SHIFT 0x0 |
8027 | #define SQ_WATCH1_ADDR_H__ADDR_MASK 0x0000FFFFL |
8028 | //SQ_WATCH1_ADDR_L |
8029 | #define SQ_WATCH1_ADDR_L__ADDR__SHIFT 0x6 |
8030 | #define SQ_WATCH1_ADDR_L__ADDR_MASK 0xFFFFFFC0L |
8031 | //SQ_WATCH1_CNTL |
8032 | #define SQ_WATCH1_CNTL__MASK__SHIFT 0x0 |
8033 | #define SQ_WATCH1_CNTL__VMID__SHIFT 0x18 |
8034 | #define SQ_WATCH1_CNTL__VALID__SHIFT 0x1f |
8035 | #define SQ_WATCH1_CNTL__MASK_MASK 0x00FFFFFFL |
8036 | #define SQ_WATCH1_CNTL__VMID_MASK 0x0F000000L |
8037 | #define SQ_WATCH1_CNTL__VALID_MASK 0x80000000L |
8038 | //SQ_WATCH2_ADDR_H |
8039 | #define SQ_WATCH2_ADDR_H__ADDR__SHIFT 0x0 |
8040 | #define SQ_WATCH2_ADDR_H__ADDR_MASK 0x0000FFFFL |
8041 | //SQ_WATCH2_ADDR_L |
8042 | #define SQ_WATCH2_ADDR_L__ADDR__SHIFT 0x6 |
8043 | #define SQ_WATCH2_ADDR_L__ADDR_MASK 0xFFFFFFC0L |
8044 | //SQ_WATCH2_CNTL |
8045 | #define SQ_WATCH2_CNTL__MASK__SHIFT 0x0 |
8046 | #define SQ_WATCH2_CNTL__VMID__SHIFT 0x18 |
8047 | #define SQ_WATCH2_CNTL__VALID__SHIFT 0x1f |
8048 | #define SQ_WATCH2_CNTL__MASK_MASK 0x00FFFFFFL |
8049 | #define SQ_WATCH2_CNTL__VMID_MASK 0x0F000000L |
8050 | #define SQ_WATCH2_CNTL__VALID_MASK 0x80000000L |
8051 | //SQ_WATCH3_ADDR_H |
8052 | #define SQ_WATCH3_ADDR_H__ADDR__SHIFT 0x0 |
8053 | #define SQ_WATCH3_ADDR_H__ADDR_MASK 0x0000FFFFL |
8054 | //SQ_WATCH3_ADDR_L |
8055 | #define SQ_WATCH3_ADDR_L__ADDR__SHIFT 0x6 |
8056 | #define SQ_WATCH3_ADDR_L__ADDR_MASK 0xFFFFFFC0L |
8057 | //SQ_WATCH3_CNTL |
8058 | #define SQ_WATCH3_CNTL__MASK__SHIFT 0x0 |
8059 | #define SQ_WATCH3_CNTL__VMID__SHIFT 0x18 |
8060 | #define SQ_WATCH3_CNTL__VALID__SHIFT 0x1f |
8061 | #define SQ_WATCH3_CNTL__MASK_MASK 0x00FFFFFFL |
8062 | #define SQ_WATCH3_CNTL__VMID_MASK 0x0F000000L |
8063 | #define SQ_WATCH3_CNTL__VALID_MASK 0x80000000L |
8064 | //SQ_IND_INDEX |
8065 | #define SQ_IND_INDEX__WAVE_ID__SHIFT 0x0 |
8066 | #define SQ_IND_INDEX__WORKITEM_ID__SHIFT 0x5 |
8067 | #define SQ_IND_INDEX__AUTO_INCR__SHIFT 0xb |
8068 | #define SQ_IND_INDEX__INDEX__SHIFT 0x10 |
8069 | #define SQ_IND_INDEX__WAVE_ID_MASK 0x0000001FL |
8070 | #define SQ_IND_INDEX__WORKITEM_ID_MASK 0x000007E0L |
8071 | #define SQ_IND_INDEX__AUTO_INCR_MASK 0x00000800L |
8072 | #define SQ_IND_INDEX__INDEX_MASK 0xFFFF0000L |
8073 | //SQ_IND_DATA |
8074 | #define SQ_IND_DATA__DATA__SHIFT 0x0 |
8075 | #define SQ_IND_DATA__DATA_MASK 0xFFFFFFFFL |
8076 | //SQ_CMD |
8077 | #define SQ_CMD__CMD__SHIFT 0x0 |
8078 | #define SQ_CMD__MODE__SHIFT 0x4 |
8079 | #define SQ_CMD__CHECK_VMID__SHIFT 0x7 |
8080 | #define SQ_CMD__DATA__SHIFT 0x8 |
8081 | #define SQ_CMD__WAVE_ID__SHIFT 0x10 |
8082 | #define SQ_CMD__QUEUE_ID__SHIFT 0x18 |
8083 | #define SQ_CMD__VM_ID__SHIFT 0x1c |
8084 | #define SQ_CMD__CMD_MASK 0x0000000FL |
8085 | #define SQ_CMD__MODE_MASK 0x00000070L |
8086 | #define SQ_CMD__CHECK_VMID_MASK 0x00000080L |
8087 | #define SQ_CMD__DATA_MASK 0x00000F00L |
8088 | #define SQ_CMD__WAVE_ID_MASK 0x001F0000L |
8089 | #define SQ_CMD__QUEUE_ID_MASK 0x07000000L |
8090 | #define SQ_CMD__VM_ID_MASK 0xF0000000L |
8091 | //SQC_MISC_CONFIG |
8092 | #define SQC_MISC_CONFIG__UNUSED__SHIFT 0x0 |
8093 | #define SQC_MISC_CONFIG__SQC_SPI_TTRACE_FGCG_OVERRIDE__SHIFT 0x5 |
8094 | #define SQC_MISC_CONFIG__SQ_SPI_MSG_FGCG_OVERRIDE__SHIFT 0x6 |
8095 | #define SQC_MISC_CONFIG__SPI_SQ_EXPALLOC_FGCG_OVERRIDE__SHIFT 0x7 |
8096 | #define SQC_MISC_CONFIG__SQC_SQ_DATA_RET_FGCG_OVERRIDE__SHIFT 0x8 |
8097 | #define SQC_MISC_CONFIG__SQC_SQ_INST_RET_FGCG_OVERRIDE__SHIFT 0x9 |
8098 | #define SQC_MISC_CONFIG__SQC_GCR_RSP_FGCG_OVERRIDE__SHIFT 0xa |
8099 | #define SQC_MISC_CONFIG__ICLK_MGCG_DISABLE__SHIFT 0xb |
8100 | #define SQC_MISC_CONFIG__ICLK_BANK_MGCG_DISABLE__SHIFT 0xc |
8101 | #define SQC_MISC_CONFIG__DCLK_MGCG_DISABLE__SHIFT 0xd |
8102 | #define SQC_MISC_CONFIG__GCLK_MGCG_DISABLE__SHIFT 0xe |
8103 | #define SQC_MISC_CONFIG__MCLK_MGCG_DISABLE__SHIFT 0xf |
8104 | #define SQC_MISC_CONFIG__PCLK_MGCG_DISABLE__SHIFT 0x10 |
8105 | #define SQC_MISC_CONFIG__BCLK_MGCG_DISABLE__SHIFT 0x11 |
8106 | #define SQC_MISC_CONFIG__SQC_TA_RESET_FGCG_OVERRIDE__SHIFT 0x12 |
8107 | #define SQC_MISC_CONFIG__SQC_LDS_CONFIG_FGCG_OVERRIDE__SHIFT 0x13 |
8108 | #define SQC_MISC_CONFIG__DCLK_BANK_MGCG_DISABLE__SHIFT 0x14 |
8109 | #define SQC_MISC_CONFIG__SQC_SQ_BARRIER_DONE_FGCG_OVERRIDE__SHIFT 0x15 |
8110 | #define SQC_MISC_CONFIG__SQC_SQ_MSGDONE_FGCG_OVERRIDE__SHIFT 0x16 |
8111 | #define SQC_MISC_CONFIG__CMCLK_MGCG_DISABLE__SHIFT 0x17 |
8112 | #define SQC_MISC_CONFIG__SQC_GL1_CLKEN_OVERRIDE__SHIFT 0x18 |
8113 | #define SQC_MISC_CONFIG__SQC_CORE_OVERRIDE__SHIFT 0x19 |
8114 | #define SQC_MISC_CONFIG__ICLK_HMF_BS_MGCG_DISABLE__SHIFT 0x1a |
8115 | #define SQC_MISC_CONFIG__ICLK_CC_MGCG_DISABLE__SHIFT 0x1b |
8116 | #define SQC_MISC_CONFIG__DCLK_HMF_BS_MGCG_DISABLE__SHIFT 0x1c |
8117 | #define SQC_MISC_CONFIG__DCLK_CC_MGCG_DISABLE__SHIFT 0x1d |
8118 | #define SQC_MISC_CONFIG__UNUSED_MASK 0x0000001FL |
8119 | #define SQC_MISC_CONFIG__SQC_SPI_TTRACE_FGCG_OVERRIDE_MASK 0x00000020L |
8120 | #define SQC_MISC_CONFIG__SQ_SPI_MSG_FGCG_OVERRIDE_MASK 0x00000040L |
8121 | #define SQC_MISC_CONFIG__SPI_SQ_EXPALLOC_FGCG_OVERRIDE_MASK 0x00000080L |
8122 | #define SQC_MISC_CONFIG__SQC_SQ_DATA_RET_FGCG_OVERRIDE_MASK 0x00000100L |
8123 | #define SQC_MISC_CONFIG__SQC_SQ_INST_RET_FGCG_OVERRIDE_MASK 0x00000200L |
8124 | #define SQC_MISC_CONFIG__SQC_GCR_RSP_FGCG_OVERRIDE_MASK 0x00000400L |
8125 | #define SQC_MISC_CONFIG__ICLK_MGCG_DISABLE_MASK 0x00000800L |
8126 | #define SQC_MISC_CONFIG__ICLK_BANK_MGCG_DISABLE_MASK 0x00001000L |
8127 | #define SQC_MISC_CONFIG__DCLK_MGCG_DISABLE_MASK 0x00002000L |
8128 | #define SQC_MISC_CONFIG__GCLK_MGCG_DISABLE_MASK 0x00004000L |
8129 | #define SQC_MISC_CONFIG__MCLK_MGCG_DISABLE_MASK 0x00008000L |
8130 | #define SQC_MISC_CONFIG__PCLK_MGCG_DISABLE_MASK 0x00010000L |
8131 | #define SQC_MISC_CONFIG__BCLK_MGCG_DISABLE_MASK 0x00020000L |
8132 | #define SQC_MISC_CONFIG__SQC_TA_RESET_FGCG_OVERRIDE_MASK 0x00040000L |
8133 | #define SQC_MISC_CONFIG__SQC_LDS_CONFIG_FGCG_OVERRIDE_MASK 0x00080000L |
8134 | #define SQC_MISC_CONFIG__DCLK_BANK_MGCG_DISABLE_MASK 0x00100000L |
8135 | #define SQC_MISC_CONFIG__SQC_SQ_BARRIER_DONE_FGCG_OVERRIDE_MASK 0x00200000L |
8136 | #define SQC_MISC_CONFIG__SQC_SQ_MSGDONE_FGCG_OVERRIDE_MASK 0x00400000L |
8137 | #define SQC_MISC_CONFIG__CMCLK_MGCG_DISABLE_MASK 0x00800000L |
8138 | #define SQC_MISC_CONFIG__SQC_GL1_CLKEN_OVERRIDE_MASK 0x01000000L |
8139 | #define SQC_MISC_CONFIG__SQC_CORE_OVERRIDE_MASK 0x02000000L |
8140 | #define SQC_MISC_CONFIG__ICLK_HMF_BS_MGCG_DISABLE_MASK 0x04000000L |
8141 | #define SQC_MISC_CONFIG__ICLK_CC_MGCG_DISABLE_MASK 0x08000000L |
8142 | #define SQC_MISC_CONFIG__DCLK_HMF_BS_MGCG_DISABLE_MASK 0x10000000L |
8143 | #define SQC_MISC_CONFIG__DCLK_CC_MGCG_DISABLE_MASK 0x20000000L |
8144 | |
8145 | |
8146 | // addressBlock: gc_shsdec |
8147 | //SX_DEBUG_BUSY |
8148 | #define SX_DEBUG_BUSY__COL_WRCTRL1_VALIDQ3__SHIFT 0x0 |
8149 | #define SX_DEBUG_BUSY__COL_WRCTRL1_VALIDQ2__SHIFT 0x1 |
8150 | #define SX_DEBUG_BUSY__COL_WRCTRL1_VALIDQ1__SHIFT 0x2 |
8151 | #define SX_DEBUG_BUSY__COL_WRCTRL0_VALIDQ3__SHIFT 0x3 |
8152 | #define SX_DEBUG_BUSY__COL_WRCTRL0_VALIDQ2__SHIFT 0x4 |
8153 | #define SX_DEBUG_BUSY__COL_WRCTRL0_VALIDQ1__SHIFT 0x5 |
8154 | #define SX_DEBUG_BUSY__PCCMD_VALID__SHIFT 0x6 |
8155 | #define SX_DEBUG_BUSY__VDATA1_VALID__SHIFT 0x7 |
8156 | #define SX_DEBUG_BUSY__VDATA0_VALID__SHIFT 0x8 |
8157 | #define SX_DEBUG_BUSY__CMD_BUSYORVAL__SHIFT 0x9 |
8158 | #define SX_DEBUG_BUSY__ADDR_BUSYORVAL__SHIFT 0xa |
8159 | #define SX_DEBUG_BUSY__SX_SX_IN_VALID__SHIFT 0xb |
8160 | #define SX_DEBUG_BUSY__SX_SX_OUT_VALID__SHIFT 0xc |
8161 | #define SX_DEBUG_BUSY__RESERVED__SHIFT 0xd |
8162 | #define SX_DEBUG_BUSY__COL_WRCTRL1_VALIDQ3_MASK 0x00000001L |
8163 | #define SX_DEBUG_BUSY__COL_WRCTRL1_VALIDQ2_MASK 0x00000002L |
8164 | #define SX_DEBUG_BUSY__COL_WRCTRL1_VALIDQ1_MASK 0x00000004L |
8165 | #define SX_DEBUG_BUSY__COL_WRCTRL0_VALIDQ3_MASK 0x00000008L |
8166 | #define SX_DEBUG_BUSY__COL_WRCTRL0_VALIDQ2_MASK 0x00000010L |
8167 | #define SX_DEBUG_BUSY__COL_WRCTRL0_VALIDQ1_MASK 0x00000020L |
8168 | #define SX_DEBUG_BUSY__PCCMD_VALID_MASK 0x00000040L |
8169 | #define SX_DEBUG_BUSY__VDATA1_VALID_MASK 0x00000080L |
8170 | #define SX_DEBUG_BUSY__VDATA0_VALID_MASK 0x00000100L |
8171 | #define SX_DEBUG_BUSY__CMD_BUSYORVAL_MASK 0x00000200L |
8172 | #define SX_DEBUG_BUSY__ADDR_BUSYORVAL_MASK 0x00000400L |
8173 | #define SX_DEBUG_BUSY__SX_SX_IN_VALID_MASK 0x00000800L |
8174 | #define SX_DEBUG_BUSY__SX_SX_OUT_VALID_MASK 0x00001000L |
8175 | #define SX_DEBUG_BUSY__RESERVED_MASK 0xFFFFE000L |
8176 | //SX_DEBUG_BUSY_2 |
8177 | #define SX_DEBUG_BUSY_2__COL_SCBD0_BUSY__SHIFT 0x0 |
8178 | #define SX_DEBUG_BUSY_2__COL_REQ3_FREECNT_NE0__SHIFT 0x1 |
8179 | #define SX_DEBUG_BUSY_2__COL_REQ3_IDLE__SHIFT 0x2 |
8180 | #define SX_DEBUG_BUSY_2__COL_REQ3_BUSY__SHIFT 0x3 |
8181 | #define SX_DEBUG_BUSY_2__COL_REQ2_FREECNT_NE0__SHIFT 0x4 |
8182 | #define SX_DEBUG_BUSY_2__COL_REQ2_IDLE__SHIFT 0x5 |
8183 | #define SX_DEBUG_BUSY_2__COL_REQ2_BUSY__SHIFT 0x6 |
8184 | #define SX_DEBUG_BUSY_2__COL_REQ1_FREECNT_NE0__SHIFT 0x7 |
8185 | #define SX_DEBUG_BUSY_2__COL_REQ1_IDLE__SHIFT 0x8 |
8186 | #define SX_DEBUG_BUSY_2__COL_REQ1_BUSY__SHIFT 0x9 |
8187 | #define SX_DEBUG_BUSY_2__COL_REQ0_FREECNT_NE0__SHIFT 0xa |
8188 | #define SX_DEBUG_BUSY_2__COL_REQ0_IDLE__SHIFT 0xb |
8189 | #define SX_DEBUG_BUSY_2__COL_REQ0_BUSY__SHIFT 0xc |
8190 | #define SX_DEBUG_BUSY_2__COL_DBIF3_SENDFREE_BUSY__SHIFT 0xd |
8191 | #define SX_DEBUG_BUSY_2__COL_DBIF3_FIFO_BUSY__SHIFT 0xe |
8192 | #define SX_DEBUG_BUSY_2__COL_DBIF3_QUAD_FREE__SHIFT 0xf |
8193 | #define SX_DEBUG_BUSY_2__COL_DBIF2_SENDFREE_BUSY__SHIFT 0x10 |
8194 | #define SX_DEBUG_BUSY_2__COL_DBIF2_FIFO_BUSY__SHIFT 0x11 |
8195 | #define SX_DEBUG_BUSY_2__COL_DBIF2_QUAD_FREE__SHIFT 0x12 |
8196 | #define SX_DEBUG_BUSY_2__COL_DBIF1_SENDFREE_BUSY__SHIFT 0x13 |
8197 | #define SX_DEBUG_BUSY_2__COL_DBIF1_FIFO_BUSY__SHIFT 0x14 |
8198 | #define SX_DEBUG_BUSY_2__COL_DBIF1_QUAD_FREE__SHIFT 0x15 |
8199 | #define SX_DEBUG_BUSY_2__COL_DBIF0_SENDFREE_BUSY__SHIFT 0x16 |
8200 | #define SX_DEBUG_BUSY_2__COL_DBIF0_FIFO_BUSY__SHIFT 0x17 |
8201 | #define SX_DEBUG_BUSY_2__COL_DBIF0_QUAD_FREE__SHIFT 0x18 |
8202 | #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL3_BUSY__SHIFT 0x19 |
8203 | #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL2_BUSY__SHIFT 0x1a |
8204 | #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL1_BUSY__SHIFT 0x1b |
8205 | #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL0_BUSY__SHIFT 0x1c |
8206 | #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL3_BUSY__SHIFT 0x1d |
8207 | #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL2_BUSY__SHIFT 0x1e |
8208 | #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL1_BUSY__SHIFT 0x1f |
8209 | #define SX_DEBUG_BUSY_2__COL_SCBD0_BUSY_MASK 0x00000001L |
8210 | #define SX_DEBUG_BUSY_2__COL_REQ3_FREECNT_NE0_MASK 0x00000002L |
8211 | #define SX_DEBUG_BUSY_2__COL_REQ3_IDLE_MASK 0x00000004L |
8212 | #define SX_DEBUG_BUSY_2__COL_REQ3_BUSY_MASK 0x00000008L |
8213 | #define SX_DEBUG_BUSY_2__COL_REQ2_FREECNT_NE0_MASK 0x00000010L |
8214 | #define SX_DEBUG_BUSY_2__COL_REQ2_IDLE_MASK 0x00000020L |
8215 | #define SX_DEBUG_BUSY_2__COL_REQ2_BUSY_MASK 0x00000040L |
8216 | #define SX_DEBUG_BUSY_2__COL_REQ1_FREECNT_NE0_MASK 0x00000080L |
8217 | #define SX_DEBUG_BUSY_2__COL_REQ1_IDLE_MASK 0x00000100L |
8218 | #define SX_DEBUG_BUSY_2__COL_REQ1_BUSY_MASK 0x00000200L |
8219 | #define SX_DEBUG_BUSY_2__COL_REQ0_FREECNT_NE0_MASK 0x00000400L |
8220 | #define SX_DEBUG_BUSY_2__COL_REQ0_IDLE_MASK 0x00000800L |
8221 | #define SX_DEBUG_BUSY_2__COL_REQ0_BUSY_MASK 0x00001000L |
8222 | #define SX_DEBUG_BUSY_2__COL_DBIF3_SENDFREE_BUSY_MASK 0x00002000L |
8223 | #define SX_DEBUG_BUSY_2__COL_DBIF3_FIFO_BUSY_MASK 0x00004000L |
8224 | #define SX_DEBUG_BUSY_2__COL_DBIF3_QUAD_FREE_MASK 0x00008000L |
8225 | #define SX_DEBUG_BUSY_2__COL_DBIF2_SENDFREE_BUSY_MASK 0x00010000L |
8226 | #define SX_DEBUG_BUSY_2__COL_DBIF2_FIFO_BUSY_MASK 0x00020000L |
8227 | #define SX_DEBUG_BUSY_2__COL_DBIF2_QUAD_FREE_MASK 0x00040000L |
8228 | #define SX_DEBUG_BUSY_2__COL_DBIF1_SENDFREE_BUSY_MASK 0x00080000L |
8229 | #define SX_DEBUG_BUSY_2__COL_DBIF1_FIFO_BUSY_MASK 0x00100000L |
8230 | #define SX_DEBUG_BUSY_2__COL_DBIF1_QUAD_FREE_MASK 0x00200000L |
8231 | #define SX_DEBUG_BUSY_2__COL_DBIF0_SENDFREE_BUSY_MASK 0x00400000L |
8232 | #define SX_DEBUG_BUSY_2__COL_DBIF0_FIFO_BUSY_MASK 0x00800000L |
8233 | #define SX_DEBUG_BUSY_2__COL_DBIF0_QUAD_FREE_MASK 0x01000000L |
8234 | #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL3_BUSY_MASK 0x02000000L |
8235 | #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL2_BUSY_MASK 0x04000000L |
8236 | #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL1_BUSY_MASK 0x08000000L |
8237 | #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL0_BUSY_MASK 0x10000000L |
8238 | #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL3_BUSY_MASK 0x20000000L |
8239 | #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL2_BUSY_MASK 0x40000000L |
8240 | #define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL1_BUSY_MASK 0x80000000L |
8241 | //SX_DEBUG_BUSY_3 |
8242 | #define SX_DEBUG_BUSY_3__COL_BUFF3_BANK2_VAL0_BUSY__SHIFT 0x0 |
8243 | #define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL3_BUSY__SHIFT 0x1 |
8244 | #define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL2_BUSY__SHIFT 0x2 |
8245 | #define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL1_BUSY__SHIFT 0x3 |
8246 | #define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL0_BUSY__SHIFT 0x4 |
8247 | #define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL3_BUSY__SHIFT 0x5 |
8248 | #define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL2_BUSY__SHIFT 0x6 |
8249 | #define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL1_BUSY__SHIFT 0x7 |
8250 | #define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL0_BUSY__SHIFT 0x8 |
8251 | #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL3_BUSY__SHIFT 0x9 |
8252 | #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL2_BUSY__SHIFT 0xa |
8253 | #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL1_BUSY__SHIFT 0xb |
8254 | #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL0_BUSY__SHIFT 0xc |
8255 | #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL3_BUSY__SHIFT 0xd |
8256 | #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL2_BUSY__SHIFT 0xe |
8257 | #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL1_BUSY__SHIFT 0xf |
8258 | #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL0_BUSY__SHIFT 0x10 |
8259 | #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL3_BUSY__SHIFT 0x11 |
8260 | #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL2_BUSY__SHIFT 0x12 |
8261 | #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL1_BUSY__SHIFT 0x13 |
8262 | #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL0_BUSY__SHIFT 0x14 |
8263 | #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL3_BUSY__SHIFT 0x15 |
8264 | #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL2_BUSY__SHIFT 0x16 |
8265 | #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL1_BUSY__SHIFT 0x17 |
8266 | #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL0_BUSY__SHIFT 0x18 |
8267 | #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL3_BUSY__SHIFT 0x19 |
8268 | #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL2_BUSY__SHIFT 0x1a |
8269 | #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL1_BUSY__SHIFT 0x1b |
8270 | #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL0_BUSY__SHIFT 0x1c |
8271 | #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL3_BUSY__SHIFT 0x1d |
8272 | #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL2_BUSY__SHIFT 0x1e |
8273 | #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL1_BUSY__SHIFT 0x1f |
8274 | #define SX_DEBUG_BUSY_3__COL_BUFF3_BANK2_VAL0_BUSY_MASK 0x00000001L |
8275 | #define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL3_BUSY_MASK 0x00000002L |
8276 | #define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL2_BUSY_MASK 0x00000004L |
8277 | #define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL1_BUSY_MASK 0x00000008L |
8278 | #define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL0_BUSY_MASK 0x00000010L |
8279 | #define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL3_BUSY_MASK 0x00000020L |
8280 | #define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL2_BUSY_MASK 0x00000040L |
8281 | #define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL1_BUSY_MASK 0x00000080L |
8282 | #define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL0_BUSY_MASK 0x00000100L |
8283 | #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL3_BUSY_MASK 0x00000200L |
8284 | #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL2_BUSY_MASK 0x00000400L |
8285 | #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL1_BUSY_MASK 0x00000800L |
8286 | #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL0_BUSY_MASK 0x00001000L |
8287 | #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL3_BUSY_MASK 0x00002000L |
8288 | #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL2_BUSY_MASK 0x00004000L |
8289 | #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL1_BUSY_MASK 0x00008000L |
8290 | #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL0_BUSY_MASK 0x00010000L |
8291 | #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL3_BUSY_MASK 0x00020000L |
8292 | #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL2_BUSY_MASK 0x00040000L |
8293 | #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL1_BUSY_MASK 0x00080000L |
8294 | #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL0_BUSY_MASK 0x00100000L |
8295 | #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL3_BUSY_MASK 0x00200000L |
8296 | #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL2_BUSY_MASK 0x00400000L |
8297 | #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL1_BUSY_MASK 0x00800000L |
8298 | #define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL0_BUSY_MASK 0x01000000L |
8299 | #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL3_BUSY_MASK 0x02000000L |
8300 | #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL2_BUSY_MASK 0x04000000L |
8301 | #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL1_BUSY_MASK 0x08000000L |
8302 | #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL0_BUSY_MASK 0x10000000L |
8303 | #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL3_BUSY_MASK 0x20000000L |
8304 | #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL2_BUSY_MASK 0x40000000L |
8305 | #define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL1_BUSY_MASK 0x80000000L |
8306 | //SX_DEBUG_BUSY_4 |
8307 | #define SX_DEBUG_BUSY_4__COL_BUFF1_BANK2_VAL0_BUSY__SHIFT 0x0 |
8308 | #define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL3_BUSY__SHIFT 0x1 |
8309 | #define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL2_BUSY__SHIFT 0x2 |
8310 | #define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL1_BUSY__SHIFT 0x3 |
8311 | #define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL0_BUSY__SHIFT 0x4 |
8312 | #define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL3_BUSY__SHIFT 0x5 |
8313 | #define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL2_BUSY__SHIFT 0x6 |
8314 | #define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL1_BUSY__SHIFT 0x7 |
8315 | #define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL0_BUSY__SHIFT 0x8 |
8316 | #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL3_BUSY__SHIFT 0x9 |
8317 | #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL2_BUSY__SHIFT 0xa |
8318 | #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL1_BUSY__SHIFT 0xb |
8319 | #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL0_BUSY__SHIFT 0xc |
8320 | #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL3_BUSY__SHIFT 0xd |
8321 | #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL2_BUSY__SHIFT 0xe |
8322 | #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL1_BUSY__SHIFT 0xf |
8323 | #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL0_BUSY__SHIFT 0x10 |
8324 | #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL3_BUSY__SHIFT 0x11 |
8325 | #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL2_BUSY__SHIFT 0x12 |
8326 | #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL1_BUSY__SHIFT 0x13 |
8327 | #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL0_BUSY__SHIFT 0x14 |
8328 | #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL3_BUSY__SHIFT 0x15 |
8329 | #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL2_BUSY__SHIFT 0x16 |
8330 | #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL1_BUSY__SHIFT 0x17 |
8331 | #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL0_BUSY__SHIFT 0x18 |
8332 | #define SX_DEBUG_BUSY_4__COL_BUFF3_BANK7_VAL3_BUSY__SHIFT 0x19 |
8333 | #define SX_DEBUG_BUSY_4__COL_BUFF3_BANK7_VAL2_BUSY__SHIFT 0x1a |
8334 | #define SX_DEBUG_BUSY_4__COL_BUFF3_BANK7_VAL1_BUSY__SHIFT 0x1b |
8335 | #define SX_DEBUG_BUSY_4__COL_BUFF3_BANK7_VAL0_BUSY__SHIFT 0x1c |
8336 | #define SX_DEBUG_BUSY_4__COL_BUFF3_BANK6_VAL3_BUSY__SHIFT 0x1d |
8337 | #define SX_DEBUG_BUSY_4__COL_BUFF3_BANK6_VAL2_BUSY__SHIFT 0x1e |
8338 | #define SX_DEBUG_BUSY_4__COL_BUFF3_BANK6_VAL1_BUSY__SHIFT 0x1f |
8339 | #define SX_DEBUG_BUSY_4__COL_BUFF1_BANK2_VAL0_BUSY_MASK 0x00000001L |
8340 | #define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL3_BUSY_MASK 0x00000002L |
8341 | #define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL2_BUSY_MASK 0x00000004L |
8342 | #define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL1_BUSY_MASK 0x00000008L |
8343 | #define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL0_BUSY_MASK 0x00000010L |
8344 | #define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL3_BUSY_MASK 0x00000020L |
8345 | #define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL2_BUSY_MASK 0x00000040L |
8346 | #define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL1_BUSY_MASK 0x00000080L |
8347 | #define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL0_BUSY_MASK 0x00000100L |
8348 | #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL3_BUSY_MASK 0x00000200L |
8349 | #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL2_BUSY_MASK 0x00000400L |
8350 | #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL1_BUSY_MASK 0x00000800L |
8351 | #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL0_BUSY_MASK 0x00001000L |
8352 | #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL3_BUSY_MASK 0x00002000L |
8353 | #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL2_BUSY_MASK 0x00004000L |
8354 | #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL1_BUSY_MASK 0x00008000L |
8355 | #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL0_BUSY_MASK 0x00010000L |
8356 | #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL3_BUSY_MASK 0x00020000L |
8357 | #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL2_BUSY_MASK 0x00040000L |
8358 | #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL1_BUSY_MASK 0x00080000L |
8359 | #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL0_BUSY_MASK 0x00100000L |
8360 | #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL3_BUSY_MASK 0x00200000L |
8361 | #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL2_BUSY_MASK 0x00400000L |
8362 | #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL1_BUSY_MASK 0x00800000L |
8363 | #define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL0_BUSY_MASK 0x01000000L |
8364 | #define SX_DEBUG_BUSY_4__COL_BUFF3_BANK7_VAL3_BUSY_MASK 0x02000000L |
8365 | #define SX_DEBUG_BUSY_4__COL_BUFF3_BANK7_VAL2_BUSY_MASK 0x04000000L |
8366 | #define SX_DEBUG_BUSY_4__COL_BUFF3_BANK7_VAL1_BUSY_MASK 0x08000000L |
8367 | #define SX_DEBUG_BUSY_4__COL_BUFF3_BANK7_VAL0_BUSY_MASK 0x10000000L |
8368 | #define SX_DEBUG_BUSY_4__COL_BUFF3_BANK6_VAL3_BUSY_MASK 0x20000000L |
8369 | #define SX_DEBUG_BUSY_4__COL_BUFF3_BANK6_VAL2_BUSY_MASK 0x40000000L |
8370 | #define SX_DEBUG_BUSY_4__COL_BUFF3_BANK6_VAL1_BUSY_MASK 0x80000000L |
8371 | //SX_DEBUG_1 |
8372 | #define SX_DEBUG_1__SX_DB_QUAD_CREDIT__SHIFT 0x0 |
8373 | #define SX_DEBUG_1__ENABLE_FIFO_DEBUG_WRITE__SHIFT 0x7 |
8374 | #define SX_DEBUG_1__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT 0x8 |
8375 | #define SX_DEBUG_1__DISABLE_BLEND_OPT_BYPASS__SHIFT 0x9 |
8376 | #define SX_DEBUG_1__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT 0xa |
8377 | #define SX_DEBUG_1__DISABLE_QUAD_PAIR_OPT__SHIFT 0xb |
8378 | #define SX_DEBUG_1__DISABLE_PIX_EN_ZERO_OPT__SHIFT 0xc |
8379 | #define SX_DEBUG_1__DISABLE_REP_FGCG__SHIFT 0xd |
8380 | #define SX_DEBUG_1__ENABLE_SAME_PC_GDS_CGTS__SHIFT 0xe |
8381 | #define SX_DEBUG_1__DISABLE_RAM_FGCG__SHIFT 0xf |
8382 | #define SX_DEBUG_1__PC_DISABLE_SAME_ADDR_OPT__SHIFT 0x10 |
8383 | #define SX_DEBUG_1__DISABLE_COL_VAL_READ_OPT__SHIFT 0x11 |
8384 | #define SX_DEBUG_1__DISABLE_BC_RB_PLUS__SHIFT 0x12 |
8385 | #define SX_DEBUG_1__DISABLE_NATIVE_DOWNCVT_FMT_MAPPING__SHIFT 0x13 |
8386 | #define SX_DEBUG_1__DISABLE_SCBD_READ_PWR_OPT__SHIFT 0x14 |
8387 | #define SX_DEBUG_1__DISABLE_GDS_CGTS_OPT__SHIFT 0x15 |
8388 | #define SX_DEBUG_1__DISABLE_DOWNCVT_PWR_OPT__SHIFT 0x16 |
8389 | #define SX_DEBUG_1__DISABLE_POS_BUFF_REUSE_OPT__SHIFT 0x17 |
8390 | #define SX_DEBUG_1__SX_DB_QUAD_CREDIT_MASK 0x0000007FL |
8391 | #define SX_DEBUG_1__ENABLE_FIFO_DEBUG_WRITE_MASK 0x00000080L |
8392 | #define SX_DEBUG_1__DISABLE_BLEND_OPT_DONT_RD_DST_MASK 0x00000100L |
8393 | #define SX_DEBUG_1__DISABLE_BLEND_OPT_BYPASS_MASK 0x00000200L |
8394 | #define SX_DEBUG_1__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK 0x00000400L |
8395 | #define SX_DEBUG_1__DISABLE_QUAD_PAIR_OPT_MASK 0x00000800L |
8396 | #define SX_DEBUG_1__DISABLE_PIX_EN_ZERO_OPT_MASK 0x00001000L |
8397 | #define SX_DEBUG_1__DISABLE_REP_FGCG_MASK 0x00002000L |
8398 | #define SX_DEBUG_1__ENABLE_SAME_PC_GDS_CGTS_MASK 0x00004000L |
8399 | #define SX_DEBUG_1__DISABLE_RAM_FGCG_MASK 0x00008000L |
8400 | #define SX_DEBUG_1__PC_DISABLE_SAME_ADDR_OPT_MASK 0x00010000L |
8401 | #define SX_DEBUG_1__DISABLE_COL_VAL_READ_OPT_MASK 0x00020000L |
8402 | #define SX_DEBUG_1__DISABLE_BC_RB_PLUS_MASK 0x00040000L |
8403 | #define SX_DEBUG_1__DISABLE_NATIVE_DOWNCVT_FMT_MAPPING_MASK 0x00080000L |
8404 | #define SX_DEBUG_1__DISABLE_SCBD_READ_PWR_OPT_MASK 0x00100000L |
8405 | #define SX_DEBUG_1__DISABLE_GDS_CGTS_OPT_MASK 0x00200000L |
8406 | #define SX_DEBUG_1__DISABLE_DOWNCVT_PWR_OPT_MASK 0x00400000L |
8407 | #define SX_DEBUG_1__DISABLE_POS_BUFF_REUSE_OPT_MASK 0x00800000L |
8408 | //SX_DEBUG_BUSY_5 |
8409 | #define SX_DEBUG_BUSY_5__COL_BUFF3_BANK6_VAL0_BUSY__SHIFT 0x0 |
8410 | #define SX_DEBUG_BUSY_5__COL_BUFF3_BANK5_VAL3_BUSY__SHIFT 0x1 |
8411 | #define SX_DEBUG_BUSY_5__COL_BUFF3_BANK5_VAL2_BUSY__SHIFT 0x2 |
8412 | #define SX_DEBUG_BUSY_5__COL_BUFF3_BANK5_VAL1_BUSY__SHIFT 0x3 |
8413 | #define SX_DEBUG_BUSY_5__COL_BUFF3_BANK5_VAL0_BUSY__SHIFT 0x4 |
8414 | #define SX_DEBUG_BUSY_5__COL_BUFF3_BANK4_VAL3_BUSY__SHIFT 0x5 |
8415 | #define SX_DEBUG_BUSY_5__COL_BUFF3_BANK4_VAL2_BUSY__SHIFT 0x6 |
8416 | #define SX_DEBUG_BUSY_5__COL_BUFF3_BANK4_VAL1_BUSY__SHIFT 0x7 |
8417 | #define SX_DEBUG_BUSY_5__COL_BUFF3_BANK4_VAL0_BUSY__SHIFT 0x8 |
8418 | #define SX_DEBUG_BUSY_5__COL_BUFF2_BANK7_VAL3_BUSY__SHIFT 0x9 |
8419 | #define SX_DEBUG_BUSY_5__COL_BUFF2_BANK7_VAL2_BUSY__SHIFT 0xa |
8420 | #define SX_DEBUG_BUSY_5__COL_BUFF2_BANK7_VAL1_BUSY__SHIFT 0xb |
8421 | #define SX_DEBUG_BUSY_5__COL_BUFF2_BANK7_VAL0_BUSY__SHIFT 0xc |
8422 | #define SX_DEBUG_BUSY_5__COL_BUFF2_BANK6_VAL3_BUSY__SHIFT 0xd |
8423 | #define SX_DEBUG_BUSY_5__COL_BUFF2_BANK6_VAL2_BUSY__SHIFT 0xe |
8424 | #define SX_DEBUG_BUSY_5__COL_BUFF2_BANK6_VAL1_BUSY__SHIFT 0xf |
8425 | #define SX_DEBUG_BUSY_5__COL_BUFF2_BANK6_VAL0_BUSY__SHIFT 0x10 |
8426 | #define SX_DEBUG_BUSY_5__COL_BUFF2_BANK5_VAL3_BUSY__SHIFT 0x11 |
8427 | #define SX_DEBUG_BUSY_5__COL_BUFF2_BANK5_VAL2_BUSY__SHIFT 0x12 |
8428 | #define SX_DEBUG_BUSY_5__COL_BUFF2_BANK5_VAL1_BUSY__SHIFT 0x13 |
8429 | #define SX_DEBUG_BUSY_5__COL_BUFF2_BANK5_VAL0_BUSY__SHIFT 0x14 |
8430 | #define SX_DEBUG_BUSY_5__COL_BUFF2_BANK4_VAL3_BUSY__SHIFT 0x15 |
8431 | #define SX_DEBUG_BUSY_5__COL_BUFF2_BANK4_VAL2_BUSY__SHIFT 0x16 |
8432 | #define SX_DEBUG_BUSY_5__COL_BUFF2_BANK4_VAL1_BUSY__SHIFT 0x17 |
8433 | #define SX_DEBUG_BUSY_5__COL_BUFF2_BANK4_VAL0_BUSY__SHIFT 0x18 |
8434 | #define SX_DEBUG_BUSY_5__COL_BUFF1_BANK7_VAL3_BUSY__SHIFT 0x19 |
8435 | #define SX_DEBUG_BUSY_5__COL_BUFF1_BANK7_VAL2_BUSY__SHIFT 0x1a |
8436 | #define SX_DEBUG_BUSY_5__COL_BUFF1_BANK7_VAL1_BUSY__SHIFT 0x1b |
8437 | #define SX_DEBUG_BUSY_5__COL_BUFF1_BANK7_VAL0_BUSY__SHIFT 0x1c |
8438 | #define SX_DEBUG_BUSY_5__COL_BUFF1_BANK6_VAL3_BUSY__SHIFT 0x1d |
8439 | #define SX_DEBUG_BUSY_5__COL_BUFF1_BANK6_VAL2_BUSY__SHIFT 0x1e |
8440 | #define SX_DEBUG_BUSY_5__COL_BUFF1_BANK6_VAL1_BUSY__SHIFT 0x1f |
8441 | #define SX_DEBUG_BUSY_5__COL_BUFF3_BANK6_VAL0_BUSY_MASK 0x00000001L |
8442 | #define SX_DEBUG_BUSY_5__COL_BUFF3_BANK5_VAL3_BUSY_MASK 0x00000002L |
8443 | #define SX_DEBUG_BUSY_5__COL_BUFF3_BANK5_VAL2_BUSY_MASK 0x00000004L |
8444 | #define SX_DEBUG_BUSY_5__COL_BUFF3_BANK5_VAL1_BUSY_MASK 0x00000008L |
8445 | #define SX_DEBUG_BUSY_5__COL_BUFF3_BANK5_VAL0_BUSY_MASK 0x00000010L |
8446 | #define SX_DEBUG_BUSY_5__COL_BUFF3_BANK4_VAL3_BUSY_MASK 0x00000020L |
8447 | #define SX_DEBUG_BUSY_5__COL_BUFF3_BANK4_VAL2_BUSY_MASK 0x00000040L |
8448 | #define SX_DEBUG_BUSY_5__COL_BUFF3_BANK4_VAL1_BUSY_MASK 0x00000080L |
8449 | #define SX_DEBUG_BUSY_5__COL_BUFF3_BANK4_VAL0_BUSY_MASK 0x00000100L |
8450 | #define SX_DEBUG_BUSY_5__COL_BUFF2_BANK7_VAL3_BUSY_MASK 0x00000200L |
8451 | #define SX_DEBUG_BUSY_5__COL_BUFF2_BANK7_VAL2_BUSY_MASK 0x00000400L |
8452 | #define SX_DEBUG_BUSY_5__COL_BUFF2_BANK7_VAL1_BUSY_MASK 0x00000800L |
8453 | #define SX_DEBUG_BUSY_5__COL_BUFF2_BANK7_VAL0_BUSY_MASK 0x00001000L |
8454 | #define SX_DEBUG_BUSY_5__COL_BUFF2_BANK6_VAL3_BUSY_MASK 0x00002000L |
8455 | #define SX_DEBUG_BUSY_5__COL_BUFF2_BANK6_VAL2_BUSY_MASK 0x00004000L |
8456 | #define SX_DEBUG_BUSY_5__COL_BUFF2_BANK6_VAL1_BUSY_MASK 0x00008000L |
8457 | #define SX_DEBUG_BUSY_5__COL_BUFF2_BANK6_VAL0_BUSY_MASK 0x00010000L |
8458 | #define SX_DEBUG_BUSY_5__COL_BUFF2_BANK5_VAL3_BUSY_MASK 0x00020000L |
8459 | #define SX_DEBUG_BUSY_5__COL_BUFF2_BANK5_VAL2_BUSY_MASK 0x00040000L |
8460 | #define SX_DEBUG_BUSY_5__COL_BUFF2_BANK5_VAL1_BUSY_MASK 0x00080000L |
8461 | #define SX_DEBUG_BUSY_5__COL_BUFF2_BANK5_VAL0_BUSY_MASK 0x00100000L |
8462 | #define SX_DEBUG_BUSY_5__COL_BUFF2_BANK4_VAL3_BUSY_MASK 0x00200000L |
8463 | #define SX_DEBUG_BUSY_5__COL_BUFF2_BANK4_VAL2_BUSY_MASK 0x00400000L |
8464 | #define SX_DEBUG_BUSY_5__COL_BUFF2_BANK4_VAL1_BUSY_MASK 0x00800000L |
8465 | #define SX_DEBUG_BUSY_5__COL_BUFF2_BANK4_VAL0_BUSY_MASK 0x01000000L |
8466 | #define SX_DEBUG_BUSY_5__COL_BUFF1_BANK7_VAL3_BUSY_MASK 0x02000000L |
8467 | #define SX_DEBUG_BUSY_5__COL_BUFF1_BANK7_VAL2_BUSY_MASK 0x04000000L |
8468 | #define SX_DEBUG_BUSY_5__COL_BUFF1_BANK7_VAL1_BUSY_MASK 0x08000000L |
8469 | #define SX_DEBUG_BUSY_5__COL_BUFF1_BANK7_VAL0_BUSY_MASK 0x10000000L |
8470 | #define SX_DEBUG_BUSY_5__COL_BUFF1_BANK6_VAL3_BUSY_MASK 0x20000000L |
8471 | #define SX_DEBUG_BUSY_5__COL_BUFF1_BANK6_VAL2_BUSY_MASK 0x40000000L |
8472 | #define SX_DEBUG_BUSY_5__COL_BUFF1_BANK6_VAL1_BUSY_MASK 0x80000000L |
8473 | //SX_DEBUG_BUSY_6 |
8474 | #define SX_DEBUG_BUSY_6__COL_BUFF1_BANK6_VAL0_BUSY__SHIFT 0x0 |
8475 | #define SX_DEBUG_BUSY_6__COL_BUFF1_BANK5_VAL3_BUSY__SHIFT 0x1 |
8476 | #define SX_DEBUG_BUSY_6__COL_BUFF1_BANK5_VAL2_BUSY__SHIFT 0x2 |
8477 | #define SX_DEBUG_BUSY_6__COL_BUFF1_BANK5_VAL1_BUSY__SHIFT 0x3 |
8478 | #define SX_DEBUG_BUSY_6__COL_BUFF1_BANK5_VAL0_BUSY__SHIFT 0x4 |
8479 | #define SX_DEBUG_BUSY_6__COL_BUFF1_BANK4_VAL3_BUSY__SHIFT 0x5 |
8480 | #define SX_DEBUG_BUSY_6__COL_BUFF1_BANK4_VAL2_BUSY__SHIFT 0x6 |
8481 | #define SX_DEBUG_BUSY_6__COL_BUFF1_BANK4_VAL1_BUSY__SHIFT 0x7 |
8482 | #define SX_DEBUG_BUSY_6__COL_BUFF1_BANK4_VAL0_BUSY__SHIFT 0x8 |
8483 | #define SX_DEBUG_BUSY_6__COL_BUFF0_BANK7_VAL3_BUSY__SHIFT 0x9 |
8484 | #define SX_DEBUG_BUSY_6__COL_BUFF0_BANK7_VAL2_BUSY__SHIFT 0xa |
8485 | #define SX_DEBUG_BUSY_6__COL_BUFF0_BANK7_VAL1_BUSY__SHIFT 0xb |
8486 | #define SX_DEBUG_BUSY_6__COL_BUFF0_BANK7_VAL0_BUSY__SHIFT 0xc |
8487 | #define SX_DEBUG_BUSY_6__COL_BUFF0_BANK6_VAL3_BUSY__SHIFT 0xd |
8488 | #define SX_DEBUG_BUSY_6__COL_BUFF0_BANK6_VAL2_BUSY__SHIFT 0xe |
8489 | #define SX_DEBUG_BUSY_6__COL_BUFF0_BANK6_VAL1_BUSY__SHIFT 0xf |
8490 | #define SX_DEBUG_BUSY_6__COL_BUFF0_BANK6_VAL0_BUSY__SHIFT 0x10 |
8491 | #define SX_DEBUG_BUSY_6__COL_BUFF0_BANK5_VAL3_BUSY__SHIFT 0x11 |
8492 | #define SX_DEBUG_BUSY_6__COL_BUFF0_BANK5_VAL2_BUSY__SHIFT 0x12 |
8493 | #define SX_DEBUG_BUSY_6__COL_BUFF0_BANK5_VAL1_BUSY__SHIFT 0x13 |
8494 | #define SX_DEBUG_BUSY_6__COL_BUFF0_BANK5_VAL0_BUSY__SHIFT 0x14 |
8495 | #define SX_DEBUG_BUSY_6__COL_BUFF0_BANK4_VAL3_BUSY__SHIFT 0x15 |
8496 | #define SX_DEBUG_BUSY_6__COL_BUFF0_BANK4_VAL2_BUSY__SHIFT 0x16 |
8497 | #define SX_DEBUG_BUSY_6__COL_BUFF0_BANK4_VAL1_BUSY__SHIFT 0x17 |
8498 | #define SX_DEBUG_BUSY_6__COL_BUFF0_BANK4_VAL0_BUSY__SHIFT 0x18 |
8499 | #define SX_DEBUG_BUSY_6__COL_REQ3_CREDIT_BUSY__SHIFT 0x19 |
8500 | #define SX_DEBUG_BUSY_6__COL_REQ3_FLOP_BUSY__SHIFT 0x1a |
8501 | #define SX_DEBUG_BUSY_6__COL_REQ2_CREDIT_BUSY__SHIFT 0x1b |
8502 | #define SX_DEBUG_BUSY_6__COL_REQ2_FLOP_BUSY__SHIFT 0x1c |
8503 | #define SX_DEBUG_BUSY_6__COL_REQ1_CREDIT_BUSY__SHIFT 0x1d |
8504 | #define SX_DEBUG_BUSY_6__COL_REQ1_FLOP_BUSY__SHIFT 0x1e |
8505 | #define SX_DEBUG_BUSY_6__COL_REQ0_CREDIT_BUSY__SHIFT 0x1f |
8506 | #define SX_DEBUG_BUSY_6__COL_BUFF1_BANK6_VAL0_BUSY_MASK 0x00000001L |
8507 | #define SX_DEBUG_BUSY_6__COL_BUFF1_BANK5_VAL3_BUSY_MASK 0x00000002L |
8508 | #define SX_DEBUG_BUSY_6__COL_BUFF1_BANK5_VAL2_BUSY_MASK 0x00000004L |
8509 | #define SX_DEBUG_BUSY_6__COL_BUFF1_BANK5_VAL1_BUSY_MASK 0x00000008L |
8510 | #define SX_DEBUG_BUSY_6__COL_BUFF1_BANK5_VAL0_BUSY_MASK 0x00000010L |
8511 | #define SX_DEBUG_BUSY_6__COL_BUFF1_BANK4_VAL3_BUSY_MASK 0x00000020L |
8512 | #define SX_DEBUG_BUSY_6__COL_BUFF1_BANK4_VAL2_BUSY_MASK 0x00000040L |
8513 | #define SX_DEBUG_BUSY_6__COL_BUFF1_BANK4_VAL1_BUSY_MASK 0x00000080L |
8514 | #define SX_DEBUG_BUSY_6__COL_BUFF1_BANK4_VAL0_BUSY_MASK 0x00000100L |
8515 | #define SX_DEBUG_BUSY_6__COL_BUFF0_BANK7_VAL3_BUSY_MASK 0x00000200L |
8516 | #define SX_DEBUG_BUSY_6__COL_BUFF0_BANK7_VAL2_BUSY_MASK 0x00000400L |
8517 | #define SX_DEBUG_BUSY_6__COL_BUFF0_BANK7_VAL1_BUSY_MASK 0x00000800L |
8518 | #define SX_DEBUG_BUSY_6__COL_BUFF0_BANK7_VAL0_BUSY_MASK 0x00001000L |
8519 | #define SX_DEBUG_BUSY_6__COL_BUFF0_BANK6_VAL3_BUSY_MASK 0x00002000L |
8520 | #define SX_DEBUG_BUSY_6__COL_BUFF0_BANK6_VAL2_BUSY_MASK 0x00004000L |
8521 | #define SX_DEBUG_BUSY_6__COL_BUFF0_BANK6_VAL1_BUSY_MASK 0x00008000L |
8522 | #define SX_DEBUG_BUSY_6__COL_BUFF0_BANK6_VAL0_BUSY_MASK 0x00010000L |
8523 | #define SX_DEBUG_BUSY_6__COL_BUFF0_BANK5_VAL3_BUSY_MASK 0x00020000L |
8524 | #define SX_DEBUG_BUSY_6__COL_BUFF0_BANK5_VAL2_BUSY_MASK 0x00040000L |
8525 | #define SX_DEBUG_BUSY_6__COL_BUFF0_BANK5_VAL1_BUSY_MASK 0x00080000L |
8526 | #define SX_DEBUG_BUSY_6__COL_BUFF0_BANK5_VAL0_BUSY_MASK 0x00100000L |
8527 | #define SX_DEBUG_BUSY_6__COL_BUFF0_BANK4_VAL3_BUSY_MASK 0x00200000L |
8528 | #define SX_DEBUG_BUSY_6__COL_BUFF0_BANK4_VAL2_BUSY_MASK 0x00400000L |
8529 | #define SX_DEBUG_BUSY_6__COL_BUFF0_BANK4_VAL1_BUSY_MASK 0x00800000L |
8530 | #define SX_DEBUG_BUSY_6__COL_BUFF0_BANK4_VAL0_BUSY_MASK 0x01000000L |
8531 | #define SX_DEBUG_BUSY_6__COL_REQ3_CREDIT_BUSY_MASK 0x02000000L |
8532 | #define SX_DEBUG_BUSY_6__COL_REQ3_FLOP_BUSY_MASK 0x04000000L |
8533 | #define SX_DEBUG_BUSY_6__COL_REQ2_CREDIT_BUSY_MASK 0x08000000L |
8534 | #define SX_DEBUG_BUSY_6__COL_REQ2_FLOP_BUSY_MASK 0x10000000L |
8535 | #define SX_DEBUG_BUSY_6__COL_REQ1_CREDIT_BUSY_MASK 0x20000000L |
8536 | #define SX_DEBUG_BUSY_6__COL_REQ1_FLOP_BUSY_MASK 0x40000000L |
8537 | #define SX_DEBUG_BUSY_6__COL_REQ0_CREDIT_BUSY_MASK 0x80000000L |
8538 | //SX_DEBUG_BUSY_7 |
8539 | #define SX_DEBUG_BUSY_7__COL_REQ0_FLOP_BUSY__SHIFT 0x0 |
8540 | #define SX_DEBUG_BUSY_7__COL_SCBD1_BUSY__SHIFT 0x1 |
8541 | #define SX_DEBUG_BUSY_7__COL_BLEND3_DATA_VALIDQ1__SHIFT 0x2 |
8542 | #define SX_DEBUG_BUSY_7__COL_BLEND3_DATA_VALIDQ1_ADJ__SHIFT 0x3 |
8543 | #define SX_DEBUG_BUSY_7__COL_BLEND3_DATA_VALIDQ2__SHIFT 0x4 |
8544 | #define SX_DEBUG_BUSY_7__COL_BLEND3_DATA_VALIDQ3__SHIFT 0x5 |
8545 | #define SX_DEBUG_BUSY_7__COL_BLEND3_DATA_VALIDQ4__SHIFT 0x6 |
8546 | #define SX_DEBUG_BUSY_7__COL_BLEND3_DATA_VALIDQ5__SHIFT 0x7 |
8547 | #define SX_DEBUG_BUSY_7__COL_BLEND3_DATA_VALID_OUT__SHIFT 0x8 |
8548 | #define SX_DEBUG_BUSY_7__COL_BLEND2_DATA_VALIDQ1__SHIFT 0x9 |
8549 | #define SX_DEBUG_BUSY_7__COL_BLEND2_DATA_VALIDQ1_ADJ__SHIFT 0xa |
8550 | #define SX_DEBUG_BUSY_7__COL_BLEND2_DATA_VALIDQ2__SHIFT 0xb |
8551 | #define SX_DEBUG_BUSY_7__COL_BLEND2_DATA_VALIDQ3__SHIFT 0xc |
8552 | #define SX_DEBUG_BUSY_7__COL_BLEND2_DATA_VALIDQ4__SHIFT 0xd |
8553 | #define SX_DEBUG_BUSY_7__COL_BLEND2_DATA_VALIDQ5__SHIFT 0xe |
8554 | #define SX_DEBUG_BUSY_7__COL_BLEND2_DATA_VALID_OUT__SHIFT 0xf |
8555 | #define SX_DEBUG_BUSY_7__COL_BLEND1_DATA_VALIDQ1__SHIFT 0x10 |
8556 | #define SX_DEBUG_BUSY_7__COL_BLEND1_DATA_VALIDQ1_ADJ__SHIFT 0x11 |
8557 | #define SX_DEBUG_BUSY_7__COL_BLEND1_DATA_VALIDQ2__SHIFT 0x12 |
8558 | #define SX_DEBUG_BUSY_7__COL_BLEND1_DATA_VALIDQ3__SHIFT 0x13 |
8559 | #define SX_DEBUG_BUSY_7__COL_BLEND1_DATA_VALIDQ4__SHIFT 0x14 |
8560 | #define SX_DEBUG_BUSY_7__COL_BLEND1_DATA_VALIDQ5__SHIFT 0x15 |
8561 | #define SX_DEBUG_BUSY_7__COL_BLEND1_DATA_VALID_OUT__SHIFT 0x16 |
8562 | #define SX_DEBUG_BUSY_7__COL_BLEND0_DATA_VALIDQ1__SHIFT 0x17 |
8563 | #define SX_DEBUG_BUSY_7__COL_BLEND0_DATA_VALIDQ1_ADJ__SHIFT 0x18 |
8564 | #define SX_DEBUG_BUSY_7__COL_BLEND0_DATA_VALIDQ2__SHIFT 0x19 |
8565 | #define SX_DEBUG_BUSY_7__COL_BLEND0_DATA_VALIDQ3__SHIFT 0x1a |
8566 | #define SX_DEBUG_BUSY_7__COL_BLEND0_DATA_VALIDQ4__SHIFT 0x1b |
8567 | #define SX_DEBUG_BUSY_7__COL_BLEND0_DATA_VALIDQ5__SHIFT 0x1c |
8568 | #define SX_DEBUG_BUSY_7__COL_BLEND0_DATA_VALID_OUT__SHIFT 0x1d |
8569 | #define SX_DEBUG_BUSY_7__RESERVED__SHIFT 0x1e |
8570 | #define SX_DEBUG_BUSY_7__COL_REQ0_FLOP_BUSY_MASK 0x00000001L |
8571 | #define SX_DEBUG_BUSY_7__COL_SCBD1_BUSY_MASK 0x00000002L |
8572 | #define SX_DEBUG_BUSY_7__COL_BLEND3_DATA_VALIDQ1_MASK 0x00000004L |
8573 | #define SX_DEBUG_BUSY_7__COL_BLEND3_DATA_VALIDQ1_ADJ_MASK 0x00000008L |
8574 | #define SX_DEBUG_BUSY_7__COL_BLEND3_DATA_VALIDQ2_MASK 0x00000010L |
8575 | #define SX_DEBUG_BUSY_7__COL_BLEND3_DATA_VALIDQ3_MASK 0x00000020L |
8576 | #define SX_DEBUG_BUSY_7__COL_BLEND3_DATA_VALIDQ4_MASK 0x00000040L |
8577 | #define SX_DEBUG_BUSY_7__COL_BLEND3_DATA_VALIDQ5_MASK 0x00000080L |
8578 | #define SX_DEBUG_BUSY_7__COL_BLEND3_DATA_VALID_OUT_MASK 0x00000100L |
8579 | #define SX_DEBUG_BUSY_7__COL_BLEND2_DATA_VALIDQ1_MASK 0x00000200L |
8580 | #define SX_DEBUG_BUSY_7__COL_BLEND2_DATA_VALIDQ1_ADJ_MASK 0x00000400L |
8581 | #define SX_DEBUG_BUSY_7__COL_BLEND2_DATA_VALIDQ2_MASK 0x00000800L |
8582 | #define SX_DEBUG_BUSY_7__COL_BLEND2_DATA_VALIDQ3_MASK 0x00001000L |
8583 | #define SX_DEBUG_BUSY_7__COL_BLEND2_DATA_VALIDQ4_MASK 0x00002000L |
8584 | #define SX_DEBUG_BUSY_7__COL_BLEND2_DATA_VALIDQ5_MASK 0x00004000L |
8585 | #define SX_DEBUG_BUSY_7__COL_BLEND2_DATA_VALID_OUT_MASK 0x00008000L |
8586 | #define SX_DEBUG_BUSY_7__COL_BLEND1_DATA_VALIDQ1_MASK 0x00010000L |
8587 | #define SX_DEBUG_BUSY_7__COL_BLEND1_DATA_VALIDQ1_ADJ_MASK 0x00020000L |
8588 | #define SX_DEBUG_BUSY_7__COL_BLEND1_DATA_VALIDQ2_MASK 0x00040000L |
8589 | #define SX_DEBUG_BUSY_7__COL_BLEND1_DATA_VALIDQ3_MASK 0x00080000L |
8590 | #define SX_DEBUG_BUSY_7__COL_BLEND1_DATA_VALIDQ4_MASK 0x00100000L |
8591 | #define SX_DEBUG_BUSY_7__COL_BLEND1_DATA_VALIDQ5_MASK 0x00200000L |
8592 | #define SX_DEBUG_BUSY_7__COL_BLEND1_DATA_VALID_OUT_MASK 0x00400000L |
8593 | #define SX_DEBUG_BUSY_7__COL_BLEND0_DATA_VALIDQ1_MASK 0x00800000L |
8594 | #define SX_DEBUG_BUSY_7__COL_BLEND0_DATA_VALIDQ1_ADJ_MASK 0x01000000L |
8595 | #define SX_DEBUG_BUSY_7__COL_BLEND0_DATA_VALIDQ2_MASK 0x02000000L |
8596 | #define SX_DEBUG_BUSY_7__COL_BLEND0_DATA_VALIDQ3_MASK 0x04000000L |
8597 | #define SX_DEBUG_BUSY_7__COL_BLEND0_DATA_VALIDQ4_MASK 0x08000000L |
8598 | #define SX_DEBUG_BUSY_7__COL_BLEND0_DATA_VALIDQ5_MASK 0x10000000L |
8599 | #define SX_DEBUG_BUSY_7__COL_BLEND0_DATA_VALID_OUT_MASK 0x20000000L |
8600 | #define SX_DEBUG_BUSY_7__RESERVED_MASK 0xC0000000L |
8601 | //SX_DEBUG_BUSY_8 |
8602 | #define SX_DEBUG_BUSY_8__POS_BANK7VAL3_BUSY__SHIFT 0x0 |
8603 | #define SX_DEBUG_BUSY_8__POS_BANK7VAL2_BUSY__SHIFT 0x1 |
8604 | #define SX_DEBUG_BUSY_8__POS_BANK7VAL1_BUSY__SHIFT 0x2 |
8605 | #define SX_DEBUG_BUSY_8__POS_BANK7VAL0_BUSY__SHIFT 0x3 |
8606 | #define SX_DEBUG_BUSY_8__POS_BANK6VAL3_BUSY__SHIFT 0x4 |
8607 | #define SX_DEBUG_BUSY_8__POS_BANK6VAL2_BUSY__SHIFT 0x5 |
8608 | #define SX_DEBUG_BUSY_8__POS_BANK6VAL1_BUSY__SHIFT 0x6 |
8609 | #define SX_DEBUG_BUSY_8__POS_BANK6VAL0_BUSY__SHIFT 0x7 |
8610 | #define SX_DEBUG_BUSY_8__POS_BANK5VAL3_BUSY__SHIFT 0x8 |
8611 | #define SX_DEBUG_BUSY_8__POS_BANK5VAL2_BUSY__SHIFT 0x9 |
8612 | #define SX_DEBUG_BUSY_8__POS_BANK5VAL1_BUSY__SHIFT 0xa |
8613 | #define SX_DEBUG_BUSY_8__POS_BANK5VAL0_BUSY__SHIFT 0xb |
8614 | #define SX_DEBUG_BUSY_8__POS_BANK4VAL3_BUSY__SHIFT 0xc |
8615 | #define SX_DEBUG_BUSY_8__POS_BANK4VAL2_BUSY__SHIFT 0xd |
8616 | #define SX_DEBUG_BUSY_8__POS_BANK4VAL1_BUSY__SHIFT 0xe |
8617 | #define SX_DEBUG_BUSY_8__POS_BANK4VAL0_BUSY__SHIFT 0xf |
8618 | #define SX_DEBUG_BUSY_8__POS_BANK3VAL3_BUSY__SHIFT 0x10 |
8619 | #define SX_DEBUG_BUSY_8__POS_BANK3VAL2_BUSY__SHIFT 0x11 |
8620 | #define SX_DEBUG_BUSY_8__POS_BANK3VAL1_BUSY__SHIFT 0x12 |
8621 | #define SX_DEBUG_BUSY_8__POS_BANK3VAL0_BUSY__SHIFT 0x13 |
8622 | #define SX_DEBUG_BUSY_8__POS_BANK2VAL3_BUSY__SHIFT 0x14 |
8623 | #define SX_DEBUG_BUSY_8__POS_BANK2VAL2_BUSY__SHIFT 0x15 |
8624 | #define SX_DEBUG_BUSY_8__POS_BANK2VAL1_BUSY__SHIFT 0x16 |
8625 | #define SX_DEBUG_BUSY_8__POS_BANK2VAL0_BUSY__SHIFT 0x17 |
8626 | #define SX_DEBUG_BUSY_8__POS_BANK1VAL3_BUSY__SHIFT 0x18 |
8627 | #define SX_DEBUG_BUSY_8__POS_BANK1VAL2_BUSY__SHIFT 0x19 |
8628 | #define SX_DEBUG_BUSY_8__POS_BANK1VAL1_BUSY__SHIFT 0x1a |
8629 | #define SX_DEBUG_BUSY_8__POS_BANK1VAL0_BUSY__SHIFT 0x1b |
8630 | #define SX_DEBUG_BUSY_8__POS_BANK0VAL3_BUSY__SHIFT 0x1c |
8631 | #define SX_DEBUG_BUSY_8__POS_BANK0VAL2_BUSY__SHIFT 0x1d |
8632 | #define SX_DEBUG_BUSY_8__POS_BANK0VAL1_BUSY__SHIFT 0x1e |
8633 | #define SX_DEBUG_BUSY_8__POS_BANK0VAL0_BUSY__SHIFT 0x1f |
8634 | #define SX_DEBUG_BUSY_8__POS_BANK7VAL3_BUSY_MASK 0x00000001L |
8635 | #define SX_DEBUG_BUSY_8__POS_BANK7VAL2_BUSY_MASK 0x00000002L |
8636 | #define SX_DEBUG_BUSY_8__POS_BANK7VAL1_BUSY_MASK 0x00000004L |
8637 | #define SX_DEBUG_BUSY_8__POS_BANK7VAL0_BUSY_MASK 0x00000008L |
8638 | #define SX_DEBUG_BUSY_8__POS_BANK6VAL3_BUSY_MASK 0x00000010L |
8639 | #define SX_DEBUG_BUSY_8__POS_BANK6VAL2_BUSY_MASK 0x00000020L |
8640 | #define SX_DEBUG_BUSY_8__POS_BANK6VAL1_BUSY_MASK 0x00000040L |
8641 | #define SX_DEBUG_BUSY_8__POS_BANK6VAL0_BUSY_MASK 0x00000080L |
8642 | #define SX_DEBUG_BUSY_8__POS_BANK5VAL3_BUSY_MASK 0x00000100L |
8643 | #define SX_DEBUG_BUSY_8__POS_BANK5VAL2_BUSY_MASK 0x00000200L |
8644 | #define SX_DEBUG_BUSY_8__POS_BANK5VAL1_BUSY_MASK 0x00000400L |
8645 | #define SX_DEBUG_BUSY_8__POS_BANK5VAL0_BUSY_MASK 0x00000800L |
8646 | #define SX_DEBUG_BUSY_8__POS_BANK4VAL3_BUSY_MASK 0x00001000L |
8647 | #define SX_DEBUG_BUSY_8__POS_BANK4VAL2_BUSY_MASK 0x00002000L |
8648 | #define SX_DEBUG_BUSY_8__POS_BANK4VAL1_BUSY_MASK 0x00004000L |
8649 | #define SX_DEBUG_BUSY_8__POS_BANK4VAL0_BUSY_MASK 0x00008000L |
8650 | #define SX_DEBUG_BUSY_8__POS_BANK3VAL3_BUSY_MASK 0x00010000L |
8651 | #define SX_DEBUG_BUSY_8__POS_BANK3VAL2_BUSY_MASK 0x00020000L |
8652 | #define SX_DEBUG_BUSY_8__POS_BANK3VAL1_BUSY_MASK 0x00040000L |
8653 | #define SX_DEBUG_BUSY_8__POS_BANK3VAL0_BUSY_MASK 0x00080000L |
8654 | #define SX_DEBUG_BUSY_8__POS_BANK2VAL3_BUSY_MASK 0x00100000L |
8655 | #define SX_DEBUG_BUSY_8__POS_BANK2VAL2_BUSY_MASK 0x00200000L |
8656 | #define SX_DEBUG_BUSY_8__POS_BANK2VAL1_BUSY_MASK 0x00400000L |
8657 | #define SX_DEBUG_BUSY_8__POS_BANK2VAL0_BUSY_MASK 0x00800000L |
8658 | #define SX_DEBUG_BUSY_8__POS_BANK1VAL3_BUSY_MASK 0x01000000L |
8659 | #define SX_DEBUG_BUSY_8__POS_BANK1VAL2_BUSY_MASK 0x02000000L |
8660 | #define SX_DEBUG_BUSY_8__POS_BANK1VAL1_BUSY_MASK 0x04000000L |
8661 | #define SX_DEBUG_BUSY_8__POS_BANK1VAL0_BUSY_MASK 0x08000000L |
8662 | #define SX_DEBUG_BUSY_8__POS_BANK0VAL3_BUSY_MASK 0x10000000L |
8663 | #define SX_DEBUG_BUSY_8__POS_BANK0VAL2_BUSY_MASK 0x20000000L |
8664 | #define SX_DEBUG_BUSY_8__POS_BANK0VAL1_BUSY_MASK 0x40000000L |
8665 | #define SX_DEBUG_BUSY_8__POS_BANK0VAL0_BUSY_MASK 0x80000000L |
8666 | //SX_DEBUG_BUSY_9 |
8667 | #define SX_DEBUG_BUSY_9__IDX_BANK7VAL3_BUSY__SHIFT 0x0 |
8668 | #define SX_DEBUG_BUSY_9__IDX_BANK7VAL2_BUSY__SHIFT 0x1 |
8669 | #define SX_DEBUG_BUSY_9__IDX_BANK7VAL1_BUSY__SHIFT 0x2 |
8670 | #define SX_DEBUG_BUSY_9__IDX_BANK7VAL0_BUSY__SHIFT 0x3 |
8671 | #define SX_DEBUG_BUSY_9__IDX_BANK6VAL3_BUSY__SHIFT 0x4 |
8672 | #define SX_DEBUG_BUSY_9__IDX_BANK6VAL2_BUSY__SHIFT 0x5 |
8673 | #define SX_DEBUG_BUSY_9__IDX_BANK6VAL1_BUSY__SHIFT 0x6 |
8674 | #define SX_DEBUG_BUSY_9__IDX_BANK6VAL0_BUSY__SHIFT 0x7 |
8675 | #define SX_DEBUG_BUSY_9__IDX_BANK5VAL3_BUSY__SHIFT 0x8 |
8676 | #define SX_DEBUG_BUSY_9__IDX_BANK5VAL2_BUSY__SHIFT 0x9 |
8677 | #define SX_DEBUG_BUSY_9__IDX_BANK5VAL1_BUSY__SHIFT 0xa |
8678 | #define SX_DEBUG_BUSY_9__IDX_BANK5VAL0_BUSY__SHIFT 0xb |
8679 | #define SX_DEBUG_BUSY_9__IDX_BANK4VAL3_BUSY__SHIFT 0xc |
8680 | #define SX_DEBUG_BUSY_9__IDX_BANK4VAL2_BUSY__SHIFT 0xd |
8681 | #define SX_DEBUG_BUSY_9__IDX_BANK4VAL1_BUSY__SHIFT 0xe |
8682 | #define SX_DEBUG_BUSY_9__IDX_BANK4VAL0_BUSY__SHIFT 0xf |
8683 | #define SX_DEBUG_BUSY_9__IDX_BANK3VAL3_BUSY__SHIFT 0x10 |
8684 | #define SX_DEBUG_BUSY_9__IDX_BANK3VAL2_BUSY__SHIFT 0x11 |
8685 | #define SX_DEBUG_BUSY_9__IDX_BANK3VAL1_BUSY__SHIFT 0x12 |
8686 | #define SX_DEBUG_BUSY_9__IDX_BANK3VAL0_BUSY__SHIFT 0x13 |
8687 | #define SX_DEBUG_BUSY_9__IDX_BANK2VAL3_BUSY__SHIFT 0x14 |
8688 | #define SX_DEBUG_BUSY_9__IDX_BANK2VAL2_BUSY__SHIFT 0x15 |
8689 | #define SX_DEBUG_BUSY_9__IDX_BANK2VAL1_BUSY__SHIFT 0x16 |
8690 | #define SX_DEBUG_BUSY_9__IDX_BANK2VAL0_BUSY__SHIFT 0x17 |
8691 | #define SX_DEBUG_BUSY_9__IDX_BANK1VAL3_BUSY__SHIFT 0x18 |
8692 | #define SX_DEBUG_BUSY_9__IDX_BANK1VAL2_BUSY__SHIFT 0x19 |
8693 | #define SX_DEBUG_BUSY_9__IDX_BANK1VAL1_BUSY__SHIFT 0x1a |
8694 | #define SX_DEBUG_BUSY_9__IDX_BANK1VAL0_BUSY__SHIFT 0x1b |
8695 | #define SX_DEBUG_BUSY_9__IDX_BANK0VAL3_BUSY__SHIFT 0x1c |
8696 | #define SX_DEBUG_BUSY_9__IDX_BANK0VAL2_BUSY__SHIFT 0x1d |
8697 | #define SX_DEBUG_BUSY_9__IDX_BANK0VAL1_BUSY__SHIFT 0x1e |
8698 | #define SX_DEBUG_BUSY_9__IDX_BANK0VAL0_BUSY__SHIFT 0x1f |
8699 | #define SX_DEBUG_BUSY_9__IDX_BANK7VAL3_BUSY_MASK 0x00000001L |
8700 | #define SX_DEBUG_BUSY_9__IDX_BANK7VAL2_BUSY_MASK 0x00000002L |
8701 | #define SX_DEBUG_BUSY_9__IDX_BANK7VAL1_BUSY_MASK 0x00000004L |
8702 | #define SX_DEBUG_BUSY_9__IDX_BANK7VAL0_BUSY_MASK 0x00000008L |
8703 | #define SX_DEBUG_BUSY_9__IDX_BANK6VAL3_BUSY_MASK 0x00000010L |
8704 | #define SX_DEBUG_BUSY_9__IDX_BANK6VAL2_BUSY_MASK 0x00000020L |
8705 | #define SX_DEBUG_BUSY_9__IDX_BANK6VAL1_BUSY_MASK 0x00000040L |
8706 | #define SX_DEBUG_BUSY_9__IDX_BANK6VAL0_BUSY_MASK 0x00000080L |
8707 | #define SX_DEBUG_BUSY_9__IDX_BANK5VAL3_BUSY_MASK 0x00000100L |
8708 | #define SX_DEBUG_BUSY_9__IDX_BANK5VAL2_BUSY_MASK 0x00000200L |
8709 | #define SX_DEBUG_BUSY_9__IDX_BANK5VAL1_BUSY_MASK 0x00000400L |
8710 | #define SX_DEBUG_BUSY_9__IDX_BANK5VAL0_BUSY_MASK 0x00000800L |
8711 | #define SX_DEBUG_BUSY_9__IDX_BANK4VAL3_BUSY_MASK 0x00001000L |
8712 | #define SX_DEBUG_BUSY_9__IDX_BANK4VAL2_BUSY_MASK 0x00002000L |
8713 | #define SX_DEBUG_BUSY_9__IDX_BANK4VAL1_BUSY_MASK 0x00004000L |
8714 | #define SX_DEBUG_BUSY_9__IDX_BANK4VAL0_BUSY_MASK 0x00008000L |
8715 | #define SX_DEBUG_BUSY_9__IDX_BANK3VAL3_BUSY_MASK 0x00010000L |
8716 | #define SX_DEBUG_BUSY_9__IDX_BANK3VAL2_BUSY_MASK 0x00020000L |
8717 | #define SX_DEBUG_BUSY_9__IDX_BANK3VAL1_BUSY_MASK 0x00040000L |
8718 | #define SX_DEBUG_BUSY_9__IDX_BANK3VAL0_BUSY_MASK 0x00080000L |
8719 | #define SX_DEBUG_BUSY_9__IDX_BANK2VAL3_BUSY_MASK 0x00100000L |
8720 | #define SX_DEBUG_BUSY_9__IDX_BANK2VAL2_BUSY_MASK 0x00200000L |
8721 | #define SX_DEBUG_BUSY_9__IDX_BANK2VAL1_BUSY_MASK 0x00400000L |
8722 | #define SX_DEBUG_BUSY_9__IDX_BANK2VAL0_BUSY_MASK 0x00800000L |
8723 | #define SX_DEBUG_BUSY_9__IDX_BANK1VAL3_BUSY_MASK 0x01000000L |
8724 | #define SX_DEBUG_BUSY_9__IDX_BANK1VAL2_BUSY_MASK 0x02000000L |
8725 | #define SX_DEBUG_BUSY_9__IDX_BANK1VAL1_BUSY_MASK 0x04000000L |
8726 | #define SX_DEBUG_BUSY_9__IDX_BANK1VAL0_BUSY_MASK 0x08000000L |
8727 | #define SX_DEBUG_BUSY_9__IDX_BANK0VAL3_BUSY_MASK 0x10000000L |
8728 | #define SX_DEBUG_BUSY_9__IDX_BANK0VAL2_BUSY_MASK 0x20000000L |
8729 | #define SX_DEBUG_BUSY_9__IDX_BANK0VAL1_BUSY_MASK 0x40000000L |
8730 | #define SX_DEBUG_BUSY_9__IDX_BANK0VAL0_BUSY_MASK 0x80000000L |
8731 | //SX_DEBUG_BUSY_10 |
8732 | #define SX_DEBUG_BUSY_10__POS_SCBD_BUSY__SHIFT 0x0 |
8733 | #define SX_DEBUG_BUSY_10__POS_FREE_OR_VALIDS__SHIFT 0x1 |
8734 | #define SX_DEBUG_BUSY_10__POS_REQUESTER_BUSY__SHIFT 0x2 |
8735 | #define SX_DEBUG_BUSY_10__PA_SX_BUSY__SHIFT 0x3 |
8736 | #define SX_DEBUG_BUSY_10__POS_WRCTRL1_VALIDQ3__SHIFT 0x4 |
8737 | #define SX_DEBUG_BUSY_10__POS_WRCTRL1_VALIDQ2__SHIFT 0x5 |
8738 | #define SX_DEBUG_BUSY_10__POS_WRCTRL1_VALIDQ1__SHIFT 0x6 |
8739 | #define SX_DEBUG_BUSY_10__IDX_SCBD_BUSY__SHIFT 0x7 |
8740 | #define SX_DEBUG_BUSY_10__IDX_FREE_OR_VALIDS__SHIFT 0x8 |
8741 | #define SX_DEBUG_BUSY_10__IDX_REQUESTER_BUSY__SHIFT 0x9 |
8742 | #define SX_DEBUG_BUSY_10__PA_SX_IDX_BUSY__SHIFT 0xa |
8743 | #define SX_DEBUG_BUSY_10__IDX_WRCTRL1_VALIDQ3__SHIFT 0xb |
8744 | #define SX_DEBUG_BUSY_10__IDX_WRCTRL1_VALIDQ2__SHIFT 0xc |
8745 | #define SX_DEBUG_BUSY_10__IDX_WRCTRL1_VALIDQ1__SHIFT 0xd |
8746 | #define SX_DEBUG_BUSY_10__RESERVED__SHIFT 0xe |
8747 | #define SX_DEBUG_BUSY_10__POS_SCBD_BUSY_MASK 0x00000001L |
8748 | #define SX_DEBUG_BUSY_10__POS_FREE_OR_VALIDS_MASK 0x00000002L |
8749 | #define SX_DEBUG_BUSY_10__POS_REQUESTER_BUSY_MASK 0x00000004L |
8750 | #define SX_DEBUG_BUSY_10__PA_SX_BUSY_MASK 0x00000008L |
8751 | #define SX_DEBUG_BUSY_10__POS_WRCTRL1_VALIDQ3_MASK 0x00000010L |
8752 | #define SX_DEBUG_BUSY_10__POS_WRCTRL1_VALIDQ2_MASK 0x00000020L |
8753 | #define SX_DEBUG_BUSY_10__POS_WRCTRL1_VALIDQ1_MASK 0x00000040L |
8754 | #define SX_DEBUG_BUSY_10__IDX_SCBD_BUSY_MASK 0x00000080L |
8755 | #define SX_DEBUG_BUSY_10__IDX_FREE_OR_VALIDS_MASK 0x00000100L |
8756 | #define SX_DEBUG_BUSY_10__IDX_REQUESTER_BUSY_MASK 0x00000200L |
8757 | #define SX_DEBUG_BUSY_10__PA_SX_IDX_BUSY_MASK 0x00000400L |
8758 | #define SX_DEBUG_BUSY_10__IDX_WRCTRL1_VALIDQ3_MASK 0x00000800L |
8759 | #define SX_DEBUG_BUSY_10__IDX_WRCTRL1_VALIDQ2_MASK 0x00001000L |
8760 | #define SX_DEBUG_BUSY_10__IDX_WRCTRL1_VALIDQ1_MASK 0x00002000L |
8761 | #define SX_DEBUG_BUSY_10__RESERVED_MASK 0xFFFFC000L |
8762 | //SPI_PS_MAX_WAVE_ID |
8763 | #define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0 |
8764 | #define SPI_PS_MAX_WAVE_ID__MAX_COLLISION_WAVE_ID__SHIFT 0x10 |
8765 | #define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000FFFL |
8766 | #define SPI_PS_MAX_WAVE_ID__MAX_COLLISION_WAVE_ID_MASK 0x03FF0000L |
8767 | //SPI_GFX_CNTL |
8768 | #define SPI_GFX_CNTL__RESET_COUNTS__SHIFT 0x0 |
8769 | #define SPI_GFX_CNTL__RESET_COUNTS_MASK 0x00000001L |
8770 | //SPI_DEBUG_READ |
8771 | #define SPI_DEBUG_READ__DATA__SHIFT 0x0 |
8772 | #define SPI_DEBUG_READ__DATA_MASK 0xFFFFFFFFL |
8773 | //SPI_DSM_CNTL |
8774 | #define SPI_DSM_CNTL__SPI_SR_MEM_DSM_IRRITATOR_DATA__SHIFT 0x0 |
8775 | #define SPI_DSM_CNTL__SPI_SR_MEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 |
8776 | #define SPI_DSM_CNTL__SPI_SR_MEM_DSM_IRRITATOR_DATA_MASK 0x00000003L |
8777 | #define SPI_DSM_CNTL__SPI_SR_MEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L |
8778 | //SPI_DSM_CNTL2 |
8779 | #define SPI_DSM_CNTL2__SPI_SR_MEM_ENABLE_ERROR_INJECT__SHIFT 0x0 |
8780 | #define SPI_DSM_CNTL2__SPI_SR_MEM_SELECT_INJECT_DELAY__SHIFT 0x2 |
8781 | #define SPI_DSM_CNTL2__SPI_SR_MEM_INJECT_DELAY__SHIFT 0x3 |
8782 | #define SPI_DSM_CNTL2__SPI_SR_MEM_ENABLE_ERROR_INJECT_MASK 0x00000003L |
8783 | #define SPI_DSM_CNTL2__SPI_SR_MEM_SELECT_INJECT_DELAY_MASK 0x00000004L |
8784 | #define SPI_DSM_CNTL2__SPI_SR_MEM_INJECT_DELAY_MASK 0x000001F8L |
8785 | //SPI_EDC_CNT |
8786 | #define SPI_EDC_CNT__SPI_SR_MEM_SED_COUNT__SHIFT 0x0 |
8787 | #define SPI_EDC_CNT__SPI_SR_MEM_SED_COUNT_MASK 0x00000003L |
8788 | //SPI_DEBUG_BUSY |
8789 | #define SPI_DEBUG_BUSY__HS_BUSY__SHIFT 0x0 |
8790 | #define SPI_DEBUG_BUSY__GS_BUSY__SHIFT 0x1 |
8791 | #define SPI_DEBUG_BUSY__PS0_BUSY__SHIFT 0x2 |
8792 | #define SPI_DEBUG_BUSY__PS1_BUSY__SHIFT 0x3 |
8793 | #define SPI_DEBUG_BUSY__PS2_BUSY__SHIFT 0x4 |
8794 | #define SPI_DEBUG_BUSY__PS3_BUSY__SHIFT 0x5 |
8795 | #define SPI_DEBUG_BUSY__CSG0_BUSY__SHIFT 0x6 |
8796 | #define SPI_DEBUG_BUSY__CSG1_BUSY__SHIFT 0x7 |
8797 | #define SPI_DEBUG_BUSY__CS0_BUSY__SHIFT 0x8 |
8798 | #define SPI_DEBUG_BUSY__CS1_BUSY__SHIFT 0x9 |
8799 | #define SPI_DEBUG_BUSY__CS2_BUSY__SHIFT 0xa |
8800 | #define SPI_DEBUG_BUSY__CS3_BUSY__SHIFT 0xb |
8801 | #define SPI_DEBUG_BUSY__CS4_BUSY__SHIFT 0xc |
8802 | #define SPI_DEBUG_BUSY__CS5_BUSY__SHIFT 0xd |
8803 | #define SPI_DEBUG_BUSY__CS6_BUSY__SHIFT 0xe |
8804 | #define SPI_DEBUG_BUSY__CS7_BUSY__SHIFT 0xf |
8805 | #define SPI_DEBUG_BUSY__LDS_WR_CTL0_BUSY__SHIFT 0x10 |
8806 | #define SPI_DEBUG_BUSY__LDS_WR_CTL1_BUSY__SHIFT 0x11 |
8807 | #define SPI_DEBUG_BUSY__PC_DEALLOC_BUSY__SHIFT 0x12 |
8808 | #define SPI_DEBUG_BUSY__OFC_LDS_BUSY__SHIFT 0x13 |
8809 | #define SPI_DEBUG_BUSY__EVENT_CLCTR_BUSY__SHIFT 0x14 |
8810 | #define SPI_DEBUG_BUSY__GRBM_BUSY__SHIFT 0x15 |
8811 | #define SPI_DEBUG_BUSY__SPIS_BUSY__SHIFT 0x16 |
8812 | #define SPI_DEBUG_BUSY__RSRC_ALLOC_BUSY__SHIFT 0x17 |
8813 | #define SPI_DEBUG_BUSY__PWS_BUSY__SHIFT 0x18 |
8814 | #define SPI_DEBUG_BUSY__HS_BUSY_MASK 0x00000001L |
8815 | #define SPI_DEBUG_BUSY__GS_BUSY_MASK 0x00000002L |
8816 | #define SPI_DEBUG_BUSY__PS0_BUSY_MASK 0x00000004L |
8817 | #define SPI_DEBUG_BUSY__PS1_BUSY_MASK 0x00000008L |
8818 | #define SPI_DEBUG_BUSY__PS2_BUSY_MASK 0x00000010L |
8819 | #define SPI_DEBUG_BUSY__PS3_BUSY_MASK 0x00000020L |
8820 | #define SPI_DEBUG_BUSY__CSG0_BUSY_MASK 0x00000040L |
8821 | #define SPI_DEBUG_BUSY__CSG1_BUSY_MASK 0x00000080L |
8822 | #define SPI_DEBUG_BUSY__CS0_BUSY_MASK 0x00000100L |
8823 | #define SPI_DEBUG_BUSY__CS1_BUSY_MASK 0x00000200L |
8824 | #define SPI_DEBUG_BUSY__CS2_BUSY_MASK 0x00000400L |
8825 | #define SPI_DEBUG_BUSY__CS3_BUSY_MASK 0x00000800L |
8826 | #define SPI_DEBUG_BUSY__CS4_BUSY_MASK 0x00001000L |
8827 | #define SPI_DEBUG_BUSY__CS5_BUSY_MASK 0x00002000L |
8828 | #define SPI_DEBUG_BUSY__CS6_BUSY_MASK 0x00004000L |
8829 | #define SPI_DEBUG_BUSY__CS7_BUSY_MASK 0x00008000L |
8830 | #define SPI_DEBUG_BUSY__LDS_WR_CTL0_BUSY_MASK 0x00010000L |
8831 | #define SPI_DEBUG_BUSY__LDS_WR_CTL1_BUSY_MASK 0x00020000L |
8832 | #define SPI_DEBUG_BUSY__PC_DEALLOC_BUSY_MASK 0x00040000L |
8833 | #define SPI_DEBUG_BUSY__OFC_LDS_BUSY_MASK 0x00080000L |
8834 | #define SPI_DEBUG_BUSY__EVENT_CLCTR_BUSY_MASK 0x00100000L |
8835 | #define SPI_DEBUG_BUSY__GRBM_BUSY_MASK 0x00200000L |
8836 | #define SPI_DEBUG_BUSY__SPIS_BUSY_MASK 0x00400000L |
8837 | #define SPI_DEBUG_BUSY__RSRC_ALLOC_BUSY_MASK 0x00800000L |
8838 | #define SPI_DEBUG_BUSY__PWS_BUSY_MASK 0x01000000L |
8839 | //SPI_CONFIG_PS_CU_EN |
8840 | #define SPI_CONFIG_PS_CU_EN__PKR_OFFSET__SHIFT 0x0 |
8841 | #define SPI_CONFIG_PS_CU_EN__PKR2_OFFSET__SHIFT 0x4 |
8842 | #define SPI_CONFIG_PS_CU_EN__PKR3_OFFSET__SHIFT 0x8 |
8843 | #define SPI_CONFIG_PS_CU_EN__PKR_OFFSET_MASK 0x0000000FL |
8844 | #define SPI_CONFIG_PS_CU_EN__PKR2_OFFSET_MASK 0x000000F0L |
8845 | #define SPI_CONFIG_PS_CU_EN__PKR3_OFFSET_MASK 0x00000F00L |
8846 | //SPI_WF_LIFETIME_CNTL |
8847 | #define SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD__SHIFT 0x0 |
8848 | #define SPI_WF_LIFETIME_CNTL__EN__SHIFT 0x4 |
8849 | #define SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD_MASK 0x0000000FL |
8850 | #define SPI_WF_LIFETIME_CNTL__EN_MASK 0x00000010L |
8851 | //SPI_WF_LIFETIME_LIMIT_0 |
8852 | #define SPI_WF_LIFETIME_LIMIT_0__MAX_CNT__SHIFT 0x0 |
8853 | #define SPI_WF_LIFETIME_LIMIT_0__EN_WARN__SHIFT 0x1f |
8854 | #define SPI_WF_LIFETIME_LIMIT_0__MAX_CNT_MASK 0x7FFFFFFFL |
8855 | #define SPI_WF_LIFETIME_LIMIT_0__EN_WARN_MASK 0x80000000L |
8856 | //SPI_WF_LIFETIME_LIMIT_1 |
8857 | #define SPI_WF_LIFETIME_LIMIT_1__MAX_CNT__SHIFT 0x0 |
8858 | #define SPI_WF_LIFETIME_LIMIT_1__EN_WARN__SHIFT 0x1f |
8859 | #define SPI_WF_LIFETIME_LIMIT_1__MAX_CNT_MASK 0x7FFFFFFFL |
8860 | #define SPI_WF_LIFETIME_LIMIT_1__EN_WARN_MASK 0x80000000L |
8861 | //SPI_WF_LIFETIME_LIMIT_2 |
8862 | #define SPI_WF_LIFETIME_LIMIT_2__MAX_CNT__SHIFT 0x0 |
8863 | #define SPI_WF_LIFETIME_LIMIT_2__EN_WARN__SHIFT 0x1f |
8864 | #define SPI_WF_LIFETIME_LIMIT_2__MAX_CNT_MASK 0x7FFFFFFFL |
8865 | #define SPI_WF_LIFETIME_LIMIT_2__EN_WARN_MASK 0x80000000L |
8866 | //SPI_WF_LIFETIME_LIMIT_3 |
8867 | #define SPI_WF_LIFETIME_LIMIT_3__MAX_CNT__SHIFT 0x0 |
8868 | #define SPI_WF_LIFETIME_LIMIT_3__EN_WARN__SHIFT 0x1f |
8869 | #define SPI_WF_LIFETIME_LIMIT_3__MAX_CNT_MASK 0x7FFFFFFFL |
8870 | #define SPI_WF_LIFETIME_LIMIT_3__EN_WARN_MASK 0x80000000L |
8871 | //SPI_WF_LIFETIME_LIMIT_4 |
8872 | #define SPI_WF_LIFETIME_LIMIT_4__MAX_CNT__SHIFT 0x0 |
8873 | #define SPI_WF_LIFETIME_LIMIT_4__EN_WARN__SHIFT 0x1f |
8874 | #define SPI_WF_LIFETIME_LIMIT_4__MAX_CNT_MASK 0x7FFFFFFFL |
8875 | #define SPI_WF_LIFETIME_LIMIT_4__EN_WARN_MASK 0x80000000L |
8876 | //SPI_WF_LIFETIME_LIMIT_5 |
8877 | #define SPI_WF_LIFETIME_LIMIT_5__MAX_CNT__SHIFT 0x0 |
8878 | #define SPI_WF_LIFETIME_LIMIT_5__EN_WARN__SHIFT 0x1f |
8879 | #define SPI_WF_LIFETIME_LIMIT_5__MAX_CNT_MASK 0x7FFFFFFFL |
8880 | #define SPI_WF_LIFETIME_LIMIT_5__EN_WARN_MASK 0x80000000L |
8881 | //SPI_WF_LIFETIME_STATUS_0 |
8882 | #define SPI_WF_LIFETIME_STATUS_0__MAX_CNT__SHIFT 0x0 |
8883 | #define SPI_WF_LIFETIME_STATUS_0__INT_SENT__SHIFT 0x1f |
8884 | #define SPI_WF_LIFETIME_STATUS_0__MAX_CNT_MASK 0x7FFFFFFFL |
8885 | #define SPI_WF_LIFETIME_STATUS_0__INT_SENT_MASK 0x80000000L |
8886 | //SPI_WF_LIFETIME_STATUS_2 |
8887 | #define SPI_WF_LIFETIME_STATUS_2__MAX_CNT__SHIFT 0x0 |
8888 | #define SPI_WF_LIFETIME_STATUS_2__INT_SENT__SHIFT 0x1f |
8889 | #define SPI_WF_LIFETIME_STATUS_2__MAX_CNT_MASK 0x7FFFFFFFL |
8890 | #define SPI_WF_LIFETIME_STATUS_2__INT_SENT_MASK 0x80000000L |
8891 | //SPI_WF_LIFETIME_STATUS_4 |
8892 | #define SPI_WF_LIFETIME_STATUS_4__MAX_CNT__SHIFT 0x0 |
8893 | #define SPI_WF_LIFETIME_STATUS_4__INT_SENT__SHIFT 0x1f |
8894 | #define SPI_WF_LIFETIME_STATUS_4__MAX_CNT_MASK 0x7FFFFFFFL |
8895 | #define SPI_WF_LIFETIME_STATUS_4__INT_SENT_MASK 0x80000000L |
8896 | //SPI_WF_LIFETIME_STATUS_6 |
8897 | #define SPI_WF_LIFETIME_STATUS_6__MAX_CNT__SHIFT 0x0 |
8898 | #define SPI_WF_LIFETIME_STATUS_6__INT_SENT__SHIFT 0x1f |
8899 | #define SPI_WF_LIFETIME_STATUS_6__MAX_CNT_MASK 0x7FFFFFFFL |
8900 | #define SPI_WF_LIFETIME_STATUS_6__INT_SENT_MASK 0x80000000L |
8901 | //SPI_WF_LIFETIME_STATUS_7 |
8902 | #define SPI_WF_LIFETIME_STATUS_7__MAX_CNT__SHIFT 0x0 |
8903 | #define SPI_WF_LIFETIME_STATUS_7__INT_SENT__SHIFT 0x1f |
8904 | #define SPI_WF_LIFETIME_STATUS_7__MAX_CNT_MASK 0x7FFFFFFFL |
8905 | #define SPI_WF_LIFETIME_STATUS_7__INT_SENT_MASK 0x80000000L |
8906 | //SPI_WF_LIFETIME_STATUS_9 |
8907 | #define SPI_WF_LIFETIME_STATUS_9__MAX_CNT__SHIFT 0x0 |
8908 | #define SPI_WF_LIFETIME_STATUS_9__INT_SENT__SHIFT 0x1f |
8909 | #define SPI_WF_LIFETIME_STATUS_9__MAX_CNT_MASK 0x7FFFFFFFL |
8910 | #define SPI_WF_LIFETIME_STATUS_9__INT_SENT_MASK 0x80000000L |
8911 | //SPI_WF_LIFETIME_STATUS_11 |
8912 | #define SPI_WF_LIFETIME_STATUS_11__MAX_CNT__SHIFT 0x0 |
8913 | #define SPI_WF_LIFETIME_STATUS_11__INT_SENT__SHIFT 0x1f |
8914 | #define SPI_WF_LIFETIME_STATUS_11__MAX_CNT_MASK 0x7FFFFFFFL |
8915 | #define SPI_WF_LIFETIME_STATUS_11__INT_SENT_MASK 0x80000000L |
8916 | //SPI_WF_LIFETIME_STATUS_13 |
8917 | #define SPI_WF_LIFETIME_STATUS_13__MAX_CNT__SHIFT 0x0 |
8918 | #define SPI_WF_LIFETIME_STATUS_13__INT_SENT__SHIFT 0x1f |
8919 | #define SPI_WF_LIFETIME_STATUS_13__MAX_CNT_MASK 0x7FFFFFFFL |
8920 | #define SPI_WF_LIFETIME_STATUS_13__INT_SENT_MASK 0x80000000L |
8921 | //SPI_WF_LIFETIME_STATUS_14 |
8922 | #define SPI_WF_LIFETIME_STATUS_14__MAX_CNT__SHIFT 0x0 |
8923 | #define SPI_WF_LIFETIME_STATUS_14__INT_SENT__SHIFT 0x1f |
8924 | #define SPI_WF_LIFETIME_STATUS_14__MAX_CNT_MASK 0x7FFFFFFFL |
8925 | #define SPI_WF_LIFETIME_STATUS_14__INT_SENT_MASK 0x80000000L |
8926 | //SPI_WF_LIFETIME_STATUS_15 |
8927 | #define SPI_WF_LIFETIME_STATUS_15__MAX_CNT__SHIFT 0x0 |
8928 | #define SPI_WF_LIFETIME_STATUS_15__INT_SENT__SHIFT 0x1f |
8929 | #define SPI_WF_LIFETIME_STATUS_15__MAX_CNT_MASK 0x7FFFFFFFL |
8930 | #define SPI_WF_LIFETIME_STATUS_15__INT_SENT_MASK 0x80000000L |
8931 | //SPI_WF_LIFETIME_STATUS_16 |
8932 | #define SPI_WF_LIFETIME_STATUS_16__MAX_CNT__SHIFT 0x0 |
8933 | #define SPI_WF_LIFETIME_STATUS_16__INT_SENT__SHIFT 0x1f |
8934 | #define SPI_WF_LIFETIME_STATUS_16__MAX_CNT_MASK 0x7FFFFFFFL |
8935 | #define SPI_WF_LIFETIME_STATUS_16__INT_SENT_MASK 0x80000000L |
8936 | //SPI_WF_LIFETIME_STATUS_17 |
8937 | #define SPI_WF_LIFETIME_STATUS_17__MAX_CNT__SHIFT 0x0 |
8938 | #define SPI_WF_LIFETIME_STATUS_17__INT_SENT__SHIFT 0x1f |
8939 | #define SPI_WF_LIFETIME_STATUS_17__MAX_CNT_MASK 0x7FFFFFFFL |
8940 | #define SPI_WF_LIFETIME_STATUS_17__INT_SENT_MASK 0x80000000L |
8941 | //SPI_WF_LIFETIME_STATUS_18 |
8942 | #define SPI_WF_LIFETIME_STATUS_18__MAX_CNT__SHIFT 0x0 |
8943 | #define SPI_WF_LIFETIME_STATUS_18__INT_SENT__SHIFT 0x1f |
8944 | #define SPI_WF_LIFETIME_STATUS_18__MAX_CNT_MASK 0x7FFFFFFFL |
8945 | #define SPI_WF_LIFETIME_STATUS_18__INT_SENT_MASK 0x80000000L |
8946 | //SPI_WF_LIFETIME_STATUS_19 |
8947 | #define SPI_WF_LIFETIME_STATUS_19__MAX_CNT__SHIFT 0x0 |
8948 | #define SPI_WF_LIFETIME_STATUS_19__INT_SENT__SHIFT 0x1f |
8949 | #define SPI_WF_LIFETIME_STATUS_19__MAX_CNT_MASK 0x7FFFFFFFL |
8950 | #define SPI_WF_LIFETIME_STATUS_19__INT_SENT_MASK 0x80000000L |
8951 | //SPI_WF_LIFETIME_STATUS_20 |
8952 | #define SPI_WF_LIFETIME_STATUS_20__MAX_CNT__SHIFT 0x0 |
8953 | #define SPI_WF_LIFETIME_STATUS_20__INT_SENT__SHIFT 0x1f |
8954 | #define SPI_WF_LIFETIME_STATUS_20__MAX_CNT_MASK 0x7FFFFFFFL |
8955 | #define SPI_WF_LIFETIME_STATUS_20__INT_SENT_MASK 0x80000000L |
8956 | //SPI_WF_LIFETIME_DEBUG |
8957 | #define SPI_WF_LIFETIME_DEBUG__START_VALUE__SHIFT 0x0 |
8958 | #define SPI_WF_LIFETIME_DEBUG__OVERRIDE_EN__SHIFT 0x1f |
8959 | #define SPI_WF_LIFETIME_DEBUG__START_VALUE_MASK 0x7FFFFFFFL |
8960 | #define SPI_WF_LIFETIME_DEBUG__OVERRIDE_EN_MASK 0x80000000L |
8961 | //SPI_WF_LIFETIME_STATUS_21 |
8962 | #define SPI_WF_LIFETIME_STATUS_21__MAX_CNT__SHIFT 0x0 |
8963 | #define SPI_WF_LIFETIME_STATUS_21__INT_SENT__SHIFT 0x1f |
8964 | #define SPI_WF_LIFETIME_STATUS_21__MAX_CNT_MASK 0x7FFFFFFFL |
8965 | #define SPI_WF_LIFETIME_STATUS_21__INT_SENT_MASK 0x80000000L |
8966 | //SPI_LB_CTR_CTRL |
8967 | #define SPI_LB_CTR_CTRL__LOAD__SHIFT 0x0 |
8968 | #define SPI_LB_CTR_CTRL__WAVES_SELECT__SHIFT 0x1 |
8969 | #define SPI_LB_CTR_CTRL__CLEAR_ON_READ__SHIFT 0x3 |
8970 | #define SPI_LB_CTR_CTRL__RESET_COUNTS__SHIFT 0x4 |
8971 | #define SPI_LB_CTR_CTRL__LOAD_MASK 0x00000001L |
8972 | #define SPI_LB_CTR_CTRL__WAVES_SELECT_MASK 0x00000006L |
8973 | #define SPI_LB_CTR_CTRL__CLEAR_ON_READ_MASK 0x00000008L |
8974 | #define SPI_LB_CTR_CTRL__RESET_COUNTS_MASK 0x00000010L |
8975 | //SPI_LB_WGP_MASK |
8976 | #define SPI_LB_WGP_MASK__WGP_MASK__SHIFT 0x0 |
8977 | #define SPI_LB_WGP_MASK__WGP_MASK_MASK 0xFFFFL |
8978 | //SPI_LB_DATA_REG |
8979 | #define SPI_LB_DATA_REG__CNT_DATA__SHIFT 0x0 |
8980 | #define SPI_LB_DATA_REG__CNT_DATA_MASK 0xFFFFFFFFL |
8981 | //SPI_PG_ENABLE_STATIC_WGP_MASK |
8982 | #define SPI_PG_ENABLE_STATIC_WGP_MASK__WGP_MASK__SHIFT 0x0 |
8983 | #define SPI_PG_ENABLE_STATIC_WGP_MASK__WGP_MASK_MASK 0xFFFFL |
8984 | //SPI_GDS_CREDITS |
8985 | #define SPI_GDS_CREDITS__DS_DATA_CREDITS__SHIFT 0x0 |
8986 | #define SPI_GDS_CREDITS__DS_CMD_CREDITS__SHIFT 0x8 |
8987 | #define SPI_GDS_CREDITS__DS_DATA_CREDITS_MASK 0x000000FFL |
8988 | #define SPI_GDS_CREDITS__DS_CMD_CREDITS_MASK 0x0000FF00L |
8989 | //SPI_SX_EXPORT_BUFFER_SIZES |
8990 | #define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE__SHIFT 0x0 |
8991 | #define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE__SHIFT 0x10 |
8992 | #define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE_MASK 0x0000FFFFL |
8993 | #define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE_MASK 0xFFFF0000L |
8994 | //SPI_SX_SCOREBOARD_BUFFER_SIZES |
8995 | #define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE__SHIFT 0x0 |
8996 | #define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE__SHIFT 0x10 |
8997 | #define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE_MASK 0x0000FFFFL |
8998 | #define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE_MASK 0xFFFF0000L |
8999 | //SPI_CSQ_WF_ACTIVE_STATUS |
9000 | #define SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE__SHIFT 0x0 |
9001 | #define SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE_MASK 0xFFFFFFFFL |
9002 | //SPI_CSQ_WF_ACTIVE_COUNT_0 |
9003 | #define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT__SHIFT 0x0 |
9004 | #define SPI_CSQ_WF_ACTIVE_COUNT_0__EVENTS__SHIFT 0x10 |
9005 | #define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK 0x000007FFL |
9006 | #define SPI_CSQ_WF_ACTIVE_COUNT_0__EVENTS_MASK 0x07FF0000L |
9007 | //SPI_CSQ_WF_ACTIVE_COUNT_1 |
9008 | #define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT__SHIFT 0x0 |
9009 | #define SPI_CSQ_WF_ACTIVE_COUNT_1__EVENTS__SHIFT 0x10 |
9010 | #define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT_MASK 0x000007FFL |
9011 | #define SPI_CSQ_WF_ACTIVE_COUNT_1__EVENTS_MASK 0x07FF0000L |
9012 | //SPI_CSQ_WF_ACTIVE_COUNT_2 |
9013 | #define SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT__SHIFT 0x0 |
9014 | #define SPI_CSQ_WF_ACTIVE_COUNT_2__EVENTS__SHIFT 0x10 |
9015 | #define SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT_MASK 0x000007FFL |
9016 | #define SPI_CSQ_WF_ACTIVE_COUNT_2__EVENTS_MASK 0x07FF0000L |
9017 | //SPI_CSQ_WF_ACTIVE_COUNT_3 |
9018 | #define SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT__SHIFT 0x0 |
9019 | #define SPI_CSQ_WF_ACTIVE_COUNT_3__EVENTS__SHIFT 0x10 |
9020 | #define SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT_MASK 0x000007FFL |
9021 | #define SPI_CSQ_WF_ACTIVE_COUNT_3__EVENTS_MASK 0x07FF0000L |
9022 | //SPI_LB_DATA_WAVES |
9023 | #define SPI_LB_DATA_WAVES__COUNT0__SHIFT 0x0 |
9024 | #define SPI_LB_DATA_WAVES__COUNT1__SHIFT 0x10 |
9025 | #define SPI_LB_DATA_WAVES__COUNT0_MASK 0x0000FFFFL |
9026 | #define SPI_LB_DATA_WAVES__COUNT1_MASK 0xFFFF0000L |
9027 | //SPI_LB_DATA_PERWGP_WAVE_HSGS |
9028 | #define SPI_LB_DATA_PERWGP_WAVE_HSGS__WGP_USED_HS__SHIFT 0x0 |
9029 | #define SPI_LB_DATA_PERWGP_WAVE_HSGS__WGP_USED_GS__SHIFT 0x10 |
9030 | #define SPI_LB_DATA_PERWGP_WAVE_HSGS__WGP_USED_HS_MASK 0x0000FFFFL |
9031 | #define SPI_LB_DATA_PERWGP_WAVE_HSGS__WGP_USED_GS_MASK 0xFFFF0000L |
9032 | //SPI_LB_DATA_PERWGP_WAVE_CS |
9033 | #define SPI_LB_DATA_PERWGP_WAVE_CS__ACTIVE__SHIFT 0x0 |
9034 | #define SPI_LB_DATA_PERWGP_WAVE_CS__ACTIVE_MASK 0xFFFFL |
9035 | //SPIS_DEBUG_READ |
9036 | #define SPIS_DEBUG_READ__DATA__SHIFT 0x0 |
9037 | #define SPIS_DEBUG_READ__DATA_MASK 0xFFFFFFFFL |
9038 | //BCI_DEBUG_READ |
9039 | #define BCI_DEBUG_READ__DATA__SHIFT 0x0 |
9040 | #define BCI_DEBUG_READ__DATA_MASK 0xFFFFFFL |
9041 | //SPI_P0_TRAP_SCREEN_PSBA_LO |
9042 | #define SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT 0x0 |
9043 | #define SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK 0xFFFFFFFFL |
9044 | //SPI_P0_TRAP_SCREEN_PSBA_HI |
9045 | #define SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT 0x0 |
9046 | #define SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK 0xFFL |
9047 | //SPI_P0_TRAP_SCREEN_PSMA_LO |
9048 | #define SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT 0x0 |
9049 | #define SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK 0xFFFFFFFFL |
9050 | //SPI_P0_TRAP_SCREEN_PSMA_HI |
9051 | #define SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT 0x0 |
9052 | #define SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK 0xFFL |
9053 | //SPI_P0_TRAP_SCREEN_GPR_MIN |
9054 | #define SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT 0x0 |
9055 | #define SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT 0x6 |
9056 | #define SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK 0x003FL |
9057 | #define SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK 0x03C0L |
9058 | //SPI_P1_TRAP_SCREEN_PSBA_LO |
9059 | #define SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT 0x0 |
9060 | #define SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK 0xFFFFFFFFL |
9061 | //SPI_P1_TRAP_SCREEN_PSBA_HI |
9062 | #define SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT 0x0 |
9063 | #define SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK 0xFFL |
9064 | //SPI_P1_TRAP_SCREEN_PSMA_LO |
9065 | #define SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT 0x0 |
9066 | #define SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK 0xFFFFFFFFL |
9067 | //SPI_P1_TRAP_SCREEN_PSMA_HI |
9068 | #define SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT 0x0 |
9069 | #define SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK 0xFFL |
9070 | //SPI_P1_TRAP_SCREEN_GPR_MIN |
9071 | #define SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT 0x0 |
9072 | #define SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT 0x6 |
9073 | #define SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK 0x003FL |
9074 | #define SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK 0x03C0L |
9075 | |
9076 | |
9077 | // addressBlock: gc_tpdec |
9078 | //TD_CNTL |
9079 | #define TD_CNTL__DISABLE_MEDIAN_CALC_FOR_CUBECORNER_PHANTOM_TEXELS__SHIFT 0x0 |
9080 | #define TD_CNTL__FORCE_RESIDENCY_MAP_TO_BE_MAX_FILTER__SHIFT 0x2 |
9081 | #define TD_CNTL__FORCE_RESIDENCY_MAP_CC_MAX_OF_ALL_SAMPLES__SHIFT 0x7 |
9082 | #define TD_CNTL__PRESERVE_VGPR_ON_UTC_ERROR__SHIFT 0xd |
9083 | #define TD_CNTL__GATHER4_FLOAT_MODE__SHIFT 0x10 |
9084 | #define TD_CNTL__FORCE_RT_BVH4_ARBITER_TO_PING_PONG__SHIFT 0x11 |
9085 | #define TD_CNTL__GATHER4_DX9_MODE__SHIFT 0x13 |
9086 | #define TD_CNTL__DISABLE_POWER_THROTTLE__SHIFT 0x14 |
9087 | #define TD_CNTL__ENABLE_ROUND_TO_ZERO__SHIFT 0x15 |
9088 | #define TD_CNTL__DISABLE_ROUND_TO_ZERO_FOR_LARGE_FLOAT_TO_SMALL_FLOAT__SHIFT 0x16 |
9089 | #define TD_CNTL__DISABLE_2BIT_SIGNED_FORMAT__SHIFT 0x17 |
9090 | #define TD_CNTL__ARBITER_ROUND_ROBIN__SHIFT 0x18 |
9091 | #define TD_CNTL__ARBITER_OLDEST_PRIORITY__SHIFT 0x19 |
9092 | #define TD_CNTL__DONE_SCOREBOARD_DEPTH__SHIFT 0x1a |
9093 | #define TD_CNTL__DISABLE_MEDIAN_CALC_FOR_CUBECORNER_PHANTOM_TEXELS_MASK 0x00000001L |
9094 | #define TD_CNTL__FORCE_RESIDENCY_MAP_TO_BE_MAX_FILTER_MASK 0x00000004L |
9095 | #define TD_CNTL__FORCE_RESIDENCY_MAP_CC_MAX_OF_ALL_SAMPLES_MASK 0x00000080L |
9096 | #define TD_CNTL__PRESERVE_VGPR_ON_UTC_ERROR_MASK 0x00002000L |
9097 | #define TD_CNTL__GATHER4_FLOAT_MODE_MASK 0x00010000L |
9098 | #define TD_CNTL__FORCE_RT_BVH4_ARBITER_TO_PING_PONG_MASK 0x00020000L |
9099 | #define TD_CNTL__GATHER4_DX9_MODE_MASK 0x00080000L |
9100 | #define TD_CNTL__DISABLE_POWER_THROTTLE_MASK 0x00100000L |
9101 | #define TD_CNTL__ENABLE_ROUND_TO_ZERO_MASK 0x00200000L |
9102 | #define TD_CNTL__DISABLE_ROUND_TO_ZERO_FOR_LARGE_FLOAT_TO_SMALL_FLOAT_MASK 0x00400000L |
9103 | #define TD_CNTL__DISABLE_2BIT_SIGNED_FORMAT_MASK 0x00800000L |
9104 | #define TD_CNTL__ARBITER_ROUND_ROBIN_MASK 0x01000000L |
9105 | #define TD_CNTL__ARBITER_OLDEST_PRIORITY_MASK 0x02000000L |
9106 | #define TD_CNTL__DONE_SCOREBOARD_DEPTH_MASK 0xFC000000L |
9107 | //TD_STATUS |
9108 | #define TD_STATUS__BUSY__SHIFT 0x1f |
9109 | #define TD_STATUS__BUSY_MASK 0x80000000L |
9110 | //TD_POWER_CNTL |
9111 | #define TD_POWER_CNTL__DISABLE_NOFILTER_FORMATTER_POWER_OPT__SHIFT 0x6 |
9112 | #define TD_POWER_CNTL__FORCE_NOFILTER_D16_FORMATTERS_ON__SHIFT 0x7 |
9113 | #define TD_POWER_CNTL__ENABLE_DEBUG_REG__SHIFT 0x8 |
9114 | #define TD_POWER_CNTL__DISABLE_NOFILTER_FORMATTER_POWER_OPT_MASK 0x00000040L |
9115 | #define TD_POWER_CNTL__FORCE_NOFILTER_D16_FORMATTERS_ON_MASK 0x00000080L |
9116 | #define TD_POWER_CNTL__ENABLE_DEBUG_REG_MASK 0x00000100L |
9117 | //TD_CNTL2 |
9118 | #define TD_CNTL2__LDS_RETURN_FIFO_CREDIT__SHIFT 0x0 |
9119 | #define TD_CNTL2__MULTI_CYCLE_16FP__SHIFT 0x3 |
9120 | #define TD_CNTL2__LDS_RETURN_FIFO_CREDIT_MASK 0x00000007L |
9121 | #define TD_CNTL2__MULTI_CYCLE_16FP_MASK 0x00000008L |
9122 | //TD_DSM_CNTL |
9123 | //TD_DSM_CNTL2 |
9124 | //TD_SCRATCH |
9125 | #define TD_SCRATCH__SCRATCH__SHIFT 0x0 |
9126 | #define TD_SCRATCH__SCRATCH_MASK 0xFFFFFFFFL |
9127 | //TA_CNTL |
9128 | #define TA_CNTL__TA_SQ_XNACK_FGCG_DISABLE__SHIFT 0x0 |
9129 | #define TA_CNTL__ALIGNER_CREDIT__SHIFT 0x10 |
9130 | #define TA_CNTL__TD_FIFO_CREDIT__SHIFT 0x16 |
9131 | #define TA_CNTL__TA_SQ_XNACK_FGCG_DISABLE_MASK 0x00000001L |
9132 | #define TA_CNTL__ALIGNER_CREDIT_MASK 0x001F0000L |
9133 | #define TA_CNTL__TD_FIFO_CREDIT_MASK 0xFFC00000L |
9134 | //TA_CNTL_AUX |
9135 | #define TA_CNTL_AUX__SCOAL_DSWIZZLE_N__SHIFT 0x0 |
9136 | #define TA_CNTL_AUX__DEPTH_AS_PITCH_DIS__SHIFT 0x1 |
9137 | #define TA_CNTL_AUX__CORNER_SAMPLES_MIN_DIM__SHIFT 0x2 |
9138 | #define TA_CNTL_AUX__OVERRIDE_QUAD_MODE_DIS__SHIFT 0x3 |
9139 | #define TA_CNTL_AUX__DERIV_ADJUST_DIS__SHIFT 0x4 |
9140 | #define TA_CNTL_AUX__TFAULT_EN_OVERRIDE__SHIFT 0x5 |
9141 | #define TA_CNTL_AUX__GATHERH_DST_SEL__SHIFT 0x6 |
9142 | #define TA_CNTL_AUX__DISABLE_GATHER4_BC_SWIZZLE__SHIFT 0x7 |
9143 | #define TA_CNTL_AUX__ANISO_MAG_STEP_CLAMP__SHIFT 0x8 |
9144 | #define TA_CNTL_AUX__AUTO_ALIGN_FORMAT__SHIFT 0x9 |
9145 | #define TA_CNTL_AUX__ANISO_HALF_THRESH__SHIFT 0xa |
9146 | #define TA_CNTL_AUX__ANISO_ERROR_FP_VBIAS__SHIFT 0xc |
9147 | #define TA_CNTL_AUX__ANISO_STEP_ORDER__SHIFT 0xd |
9148 | #define TA_CNTL_AUX__ANISO_STEP__SHIFT 0xe |
9149 | #define TA_CNTL_AUX__MINMAG_UNNORM__SHIFT 0xf |
9150 | #define TA_CNTL_AUX__ANISO_WEIGHT_MODE__SHIFT 0x10 |
9151 | #define TA_CNTL_AUX__ANISO_RATIO_LUT__SHIFT 0x11 |
9152 | #define TA_CNTL_AUX__ANISO_TAP__SHIFT 0x12 |
9153 | #define TA_CNTL_AUX__DETERMINISM_RESERVED_DISABLE__SHIFT 0x14 |
9154 | #define TA_CNTL_AUX__DETERMINISM_OPCODE_STRICT_DISABLE__SHIFT 0x15 |
9155 | #define TA_CNTL_AUX__DETERMINISM_MISC_DISABLE__SHIFT 0x16 |
9156 | #define TA_CNTL_AUX__DETERMINISM_SAMPLE_C_DFMT_DISABLE__SHIFT 0x17 |
9157 | #define TA_CNTL_AUX__DETERMINISM_SAMPLER_MSAA_DISABLE__SHIFT 0x18 |
9158 | #define TA_CNTL_AUX__DETERMINISM_WRITEOP_READFMT_DISABLE__SHIFT 0x19 |
9159 | #define TA_CNTL_AUX__DETERMINISM_DFMT_NFMT_DISABLE__SHIFT 0x1a |
9160 | #define TA_CNTL_AUX__CUBEMAP_SLICE_CLAMP__SHIFT 0x1c |
9161 | #define TA_CNTL_AUX__TRUNC_SMALL_NEG__SHIFT 0x1d |
9162 | #define TA_CNTL_AUX__ARRAY_ROUND_MODE__SHIFT 0x1e |
9163 | #define TA_CNTL_AUX__SCOAL_DSWIZZLE_N_MASK 0x00000001L |
9164 | #define TA_CNTL_AUX__DEPTH_AS_PITCH_DIS_MASK 0x00000002L |
9165 | #define TA_CNTL_AUX__CORNER_SAMPLES_MIN_DIM_MASK 0x00000004L |
9166 | #define TA_CNTL_AUX__OVERRIDE_QUAD_MODE_DIS_MASK 0x00000008L |
9167 | #define TA_CNTL_AUX__DERIV_ADJUST_DIS_MASK 0x00000010L |
9168 | #define TA_CNTL_AUX__TFAULT_EN_OVERRIDE_MASK 0x00000020L |
9169 | #define TA_CNTL_AUX__GATHERH_DST_SEL_MASK 0x00000040L |
9170 | #define TA_CNTL_AUX__DISABLE_GATHER4_BC_SWIZZLE_MASK 0x00000080L |
9171 | #define TA_CNTL_AUX__ANISO_MAG_STEP_CLAMP_MASK 0x00000100L |
9172 | #define TA_CNTL_AUX__AUTO_ALIGN_FORMAT_MASK 0x00000200L |
9173 | #define TA_CNTL_AUX__ANISO_HALF_THRESH_MASK 0x00000C00L |
9174 | #define TA_CNTL_AUX__ANISO_ERROR_FP_VBIAS_MASK 0x00001000L |
9175 | #define TA_CNTL_AUX__ANISO_STEP_ORDER_MASK 0x00002000L |
9176 | #define TA_CNTL_AUX__ANISO_STEP_MASK 0x00004000L |
9177 | #define TA_CNTL_AUX__MINMAG_UNNORM_MASK 0x00008000L |
9178 | #define TA_CNTL_AUX__ANISO_WEIGHT_MODE_MASK 0x00010000L |
9179 | #define TA_CNTL_AUX__ANISO_RATIO_LUT_MASK 0x00020000L |
9180 | #define TA_CNTL_AUX__ANISO_TAP_MASK 0x00040000L |
9181 | #define TA_CNTL_AUX__DETERMINISM_RESERVED_DISABLE_MASK 0x00100000L |
9182 | #define TA_CNTL_AUX__DETERMINISM_OPCODE_STRICT_DISABLE_MASK 0x00200000L |
9183 | #define TA_CNTL_AUX__DETERMINISM_MISC_DISABLE_MASK 0x00400000L |
9184 | #define TA_CNTL_AUX__DETERMINISM_SAMPLE_C_DFMT_DISABLE_MASK 0x00800000L |
9185 | #define TA_CNTL_AUX__DETERMINISM_SAMPLER_MSAA_DISABLE_MASK 0x01000000L |
9186 | #define TA_CNTL_AUX__DETERMINISM_WRITEOP_READFMT_DISABLE_MASK 0x02000000L |
9187 | #define TA_CNTL_AUX__DETERMINISM_DFMT_NFMT_DISABLE_MASK 0x04000000L |
9188 | #define TA_CNTL_AUX__CUBEMAP_SLICE_CLAMP_MASK 0x10000000L |
9189 | #define TA_CNTL_AUX__TRUNC_SMALL_NEG_MASK 0x20000000L |
9190 | #define TA_CNTL_AUX__ARRAY_ROUND_MODE_MASK 0xC0000000L |
9191 | //TA_CNTL2 |
9192 | #define TA_CNTL2__POINT_SAMPLE_ACCEL_DIS__SHIFT 0x10 |
9193 | #define TA_CNTL2__ELEMSIZE_HASH_DIS__SHIFT 0x11 |
9194 | #define TA_CNTL2__TRUNCATE_COORD_MODE__SHIFT 0x12 |
9195 | #define TA_CNTL2__ELIMINATE_UNLIT_QUAD_DIS__SHIFT 0x13 |
9196 | #define TA_CNTL2__POINT_SAMPLE_ACCEL_DIS_MASK 0x00010000L |
9197 | #define TA_CNTL2__ELEMSIZE_HASH_DIS_MASK 0x00020000L |
9198 | #define TA_CNTL2__TRUNCATE_COORD_MODE_MASK 0x00040000L |
9199 | #define TA_CNTL2__ELIMINATE_UNLIT_QUAD_DIS_MASK 0x00080000L |
9200 | //TA_STATUS |
9201 | #define TA_STATUS__FG_PFIFO_EMPTYB__SHIFT 0xc |
9202 | #define TA_STATUS__FG_LFIFO_EMPTYB__SHIFT 0xd |
9203 | #define TA_STATUS__FG_SFIFO_EMPTYB__SHIFT 0xe |
9204 | #define TA_STATUS__FL_PFIFO_EMPTYB__SHIFT 0x10 |
9205 | #define TA_STATUS__FL_LFIFO_EMPTYB__SHIFT 0x11 |
9206 | #define TA_STATUS__FL_SFIFO_EMPTYB__SHIFT 0x12 |
9207 | #define TA_STATUS__FA_PFIFO_EMPTYB__SHIFT 0x14 |
9208 | #define TA_STATUS__FA_LFIFO_EMPTYB__SHIFT 0x15 |
9209 | #define TA_STATUS__FA_SFIFO_EMPTYB__SHIFT 0x16 |
9210 | #define TA_STATUS__IN_BUSY__SHIFT 0x18 |
9211 | #define TA_STATUS__FG_BUSY__SHIFT 0x19 |
9212 | #define TA_STATUS__LA_BUSY__SHIFT 0x1a |
9213 | #define TA_STATUS__FL_BUSY__SHIFT 0x1b |
9214 | #define TA_STATUS__TA_BUSY__SHIFT 0x1c |
9215 | #define TA_STATUS__FA_BUSY__SHIFT 0x1d |
9216 | #define TA_STATUS__AL_BUSY__SHIFT 0x1e |
9217 | #define TA_STATUS__BUSY__SHIFT 0x1f |
9218 | #define TA_STATUS__FG_PFIFO_EMPTYB_MASK 0x00001000L |
9219 | #define TA_STATUS__FG_LFIFO_EMPTYB_MASK 0x00002000L |
9220 | #define TA_STATUS__FG_SFIFO_EMPTYB_MASK 0x00004000L |
9221 | #define TA_STATUS__FL_PFIFO_EMPTYB_MASK 0x00010000L |
9222 | #define TA_STATUS__FL_LFIFO_EMPTYB_MASK 0x00020000L |
9223 | #define TA_STATUS__FL_SFIFO_EMPTYB_MASK 0x00040000L |
9224 | #define TA_STATUS__FA_PFIFO_EMPTYB_MASK 0x00100000L |
9225 | #define TA_STATUS__FA_LFIFO_EMPTYB_MASK 0x00200000L |
9226 | #define TA_STATUS__FA_SFIFO_EMPTYB_MASK 0x00400000L |
9227 | #define TA_STATUS__IN_BUSY_MASK 0x01000000L |
9228 | #define TA_STATUS__FG_BUSY_MASK 0x02000000L |
9229 | #define TA_STATUS__LA_BUSY_MASK 0x04000000L |
9230 | #define TA_STATUS__FL_BUSY_MASK 0x08000000L |
9231 | #define TA_STATUS__TA_BUSY_MASK 0x10000000L |
9232 | #define TA_STATUS__FA_BUSY_MASK 0x20000000L |
9233 | #define TA_STATUS__AL_BUSY_MASK 0x40000000L |
9234 | #define TA_STATUS__BUSY_MASK 0x80000000L |
9235 | //TA_SCRATCH |
9236 | #define TA_SCRATCH__SCRATCH__SHIFT 0x0 |
9237 | #define TA_SCRATCH__SCRATCH_MASK 0xFFFFFFFFL |
9238 | |
9239 | |
9240 | // addressBlock: gc_gdsdec |
9241 | //GDS_CONFIG |
9242 | #define GDS_CONFIG__WRITE_DIS__SHIFT 0x0 |
9243 | #define GDS_CONFIG__UNUSED__SHIFT 0x1 |
9244 | #define GDS_CONFIG__WRITE_DIS_MASK 0x00000001L |
9245 | #define GDS_CONFIG__UNUSED_MASK 0xFFFFFFFEL |
9246 | //GDS_CNTL_STATUS |
9247 | #define GDS_CNTL_STATUS__GDS_BUSY__SHIFT 0x0 |
9248 | #define GDS_CNTL_STATUS__GRBM_WBUF_BUSY__SHIFT 0x1 |
9249 | #define GDS_CNTL_STATUS__ORD_APP_BUSY__SHIFT 0x2 |
9250 | #define GDS_CNTL_STATUS__DS_WR_CLAMP__SHIFT 0x3 |
9251 | #define GDS_CNTL_STATUS__DS_RD_CLAMP__SHIFT 0x4 |
9252 | #define GDS_CNTL_STATUS__GRBM_RBUF_BUSY__SHIFT 0x5 |
9253 | #define GDS_CNTL_STATUS__DS_BUSY__SHIFT 0x6 |
9254 | #define GDS_CNTL_STATUS__GWS_BUSY__SHIFT 0x7 |
9255 | #define GDS_CNTL_STATUS__ORD_FIFO_BUSY__SHIFT 0x8 |
9256 | #define GDS_CNTL_STATUS__CREDIT_BUSY0__SHIFT 0x9 |
9257 | #define GDS_CNTL_STATUS__CREDIT_BUSY1__SHIFT 0xa |
9258 | #define GDS_CNTL_STATUS__CREDIT_BUSY2__SHIFT 0xb |
9259 | #define GDS_CNTL_STATUS__CREDIT_BUSY3__SHIFT 0xc |
9260 | #define GDS_CNTL_STATUS__CREDIT_BUSY4__SHIFT 0xd |
9261 | #define GDS_CNTL_STATUS__CREDIT_BUSY5__SHIFT 0xe |
9262 | #define GDS_CNTL_STATUS__CREDIT_BUSY6__SHIFT 0xf |
9263 | #define GDS_CNTL_STATUS__CREDIT_BUSY7__SHIFT 0x10 |
9264 | #define GDS_CNTL_STATUS__UNUSED__SHIFT 0x11 |
9265 | #define GDS_CNTL_STATUS__GDS_BUSY_MASK 0x00000001L |
9266 | #define GDS_CNTL_STATUS__GRBM_WBUF_BUSY_MASK 0x00000002L |
9267 | #define GDS_CNTL_STATUS__ORD_APP_BUSY_MASK 0x00000004L |
9268 | #define GDS_CNTL_STATUS__DS_WR_CLAMP_MASK 0x00000008L |
9269 | #define GDS_CNTL_STATUS__DS_RD_CLAMP_MASK 0x00000010L |
9270 | #define GDS_CNTL_STATUS__GRBM_RBUF_BUSY_MASK 0x00000020L |
9271 | #define GDS_CNTL_STATUS__DS_BUSY_MASK 0x00000040L |
9272 | #define GDS_CNTL_STATUS__GWS_BUSY_MASK 0x00000080L |
9273 | #define GDS_CNTL_STATUS__ORD_FIFO_BUSY_MASK 0x00000100L |
9274 | #define GDS_CNTL_STATUS__CREDIT_BUSY0_MASK 0x00000200L |
9275 | #define GDS_CNTL_STATUS__CREDIT_BUSY1_MASK 0x00000400L |
9276 | #define GDS_CNTL_STATUS__CREDIT_BUSY2_MASK 0x00000800L |
9277 | #define GDS_CNTL_STATUS__CREDIT_BUSY3_MASK 0x00001000L |
9278 | #define GDS_CNTL_STATUS__CREDIT_BUSY4_MASK 0x00002000L |
9279 | #define GDS_CNTL_STATUS__CREDIT_BUSY5_MASK 0x00004000L |
9280 | #define GDS_CNTL_STATUS__CREDIT_BUSY6_MASK 0x00008000L |
9281 | #define GDS_CNTL_STATUS__CREDIT_BUSY7_MASK 0x00010000L |
9282 | #define GDS_CNTL_STATUS__UNUSED_MASK 0xFFFE0000L |
9283 | //GDS_ENHANCE |
9284 | #define GDS_ENHANCE__MISC__SHIFT 0x0 |
9285 | #define GDS_ENHANCE__AUTO_INC_INDEX__SHIFT 0x10 |
9286 | #define GDS_ENHANCE__CGPG_RESTORE__SHIFT 0x11 |
9287 | #define GDS_ENHANCE__UNUSED__SHIFT 0x12 |
9288 | #define GDS_ENHANCE__MISC_MASK 0x0000FFFFL |
9289 | #define GDS_ENHANCE__AUTO_INC_INDEX_MASK 0x00010000L |
9290 | #define GDS_ENHANCE__CGPG_RESTORE_MASK 0x00020000L |
9291 | #define GDS_ENHANCE__UNUSED_MASK 0xFFFC0000L |
9292 | //GDS_PROTECTION_FAULT |
9293 | #define GDS_PROTECTION_FAULT__WRITE_DIS__SHIFT 0x0 |
9294 | #define GDS_PROTECTION_FAULT__FAULT_DETECTED__SHIFT 0x1 |
9295 | #define GDS_PROTECTION_FAULT__GRBM__SHIFT 0x2 |
9296 | #define GDS_PROTECTION_FAULT__SE_ID__SHIFT 0x3 |
9297 | #define GDS_PROTECTION_FAULT__SA_ID__SHIFT 0x6 |
9298 | #define GDS_PROTECTION_FAULT__WGP_ID__SHIFT 0x7 |
9299 | #define GDS_PROTECTION_FAULT__SIMD_ID__SHIFT 0xb |
9300 | #define GDS_PROTECTION_FAULT__WAVE_ID__SHIFT 0xd |
9301 | #define GDS_PROTECTION_FAULT__ADDRESS__SHIFT 0x12 |
9302 | #define GDS_PROTECTION_FAULT__WRITE_DIS_MASK 0x00000001L |
9303 | #define GDS_PROTECTION_FAULT__FAULT_DETECTED_MASK 0x00000002L |
9304 | #define GDS_PROTECTION_FAULT__GRBM_MASK 0x00000004L |
9305 | #define GDS_PROTECTION_FAULT__SE_ID_MASK 0x00000038L |
9306 | #define GDS_PROTECTION_FAULT__SA_ID_MASK 0x00000040L |
9307 | #define GDS_PROTECTION_FAULT__WGP_ID_MASK 0x00000780L |
9308 | #define GDS_PROTECTION_FAULT__SIMD_ID_MASK 0x00001800L |
9309 | #define GDS_PROTECTION_FAULT__WAVE_ID_MASK 0x0003E000L |
9310 | #define GDS_PROTECTION_FAULT__ADDRESS_MASK 0xFFFC0000L |
9311 | //GDS_VM_PROTECTION_FAULT |
9312 | #define GDS_VM_PROTECTION_FAULT__WRITE_DIS__SHIFT 0x0 |
9313 | #define GDS_VM_PROTECTION_FAULT__FAULT_DETECTED__SHIFT 0x1 |
9314 | #define GDS_VM_PROTECTION_FAULT__GWS__SHIFT 0x2 |
9315 | #define GDS_VM_PROTECTION_FAULT__OA__SHIFT 0x3 |
9316 | #define GDS_VM_PROTECTION_FAULT__GRBM__SHIFT 0x4 |
9317 | #define GDS_VM_PROTECTION_FAULT__TMZ__SHIFT 0x5 |
9318 | #define GDS_VM_PROTECTION_FAULT__UNUSED1__SHIFT 0x6 |
9319 | #define GDS_VM_PROTECTION_FAULT__VMID__SHIFT 0x8 |
9320 | #define GDS_VM_PROTECTION_FAULT__UNUSED2__SHIFT 0xc |
9321 | #define GDS_VM_PROTECTION_FAULT__ADDRESS__SHIFT 0x10 |
9322 | #define GDS_VM_PROTECTION_FAULT__WRITE_DIS_MASK 0x00000001L |
9323 | #define GDS_VM_PROTECTION_FAULT__FAULT_DETECTED_MASK 0x00000002L |
9324 | #define GDS_VM_PROTECTION_FAULT__GWS_MASK 0x00000004L |
9325 | #define GDS_VM_PROTECTION_FAULT__OA_MASK 0x00000008L |
9326 | #define GDS_VM_PROTECTION_FAULT__GRBM_MASK 0x00000010L |
9327 | #define GDS_VM_PROTECTION_FAULT__TMZ_MASK 0x00000020L |
9328 | #define GDS_VM_PROTECTION_FAULT__UNUSED1_MASK 0x000000C0L |
9329 | #define GDS_VM_PROTECTION_FAULT__VMID_MASK 0x00000F00L |
9330 | #define GDS_VM_PROTECTION_FAULT__UNUSED2_MASK 0x0000F000L |
9331 | #define GDS_VM_PROTECTION_FAULT__ADDRESS_MASK 0xFFFF0000L |
9332 | //GDS_EDC_CNT |
9333 | #define GDS_EDC_CNT__GDS_MEM_DED__SHIFT 0x0 |
9334 | #define GDS_EDC_CNT__GDS_INPUT_QUEUE_SED__SHIFT 0x2 |
9335 | #define GDS_EDC_CNT__GDS_MEM_SEC__SHIFT 0x4 |
9336 | #define GDS_EDC_CNT__UNUSED__SHIFT 0x6 |
9337 | #define GDS_EDC_CNT__GDS_MEM_DED_MASK 0x00000003L |
9338 | #define GDS_EDC_CNT__GDS_INPUT_QUEUE_SED_MASK 0x0000000CL |
9339 | #define GDS_EDC_CNT__GDS_MEM_SEC_MASK 0x00000030L |
9340 | #define GDS_EDC_CNT__UNUSED_MASK 0xFFFFFFC0L |
9341 | //GDS_EDC_GRBM_CNT |
9342 | #define GDS_EDC_GRBM_CNT__DED__SHIFT 0x0 |
9343 | #define GDS_EDC_GRBM_CNT__SEC__SHIFT 0x2 |
9344 | #define GDS_EDC_GRBM_CNT__UNUSED__SHIFT 0x4 |
9345 | #define GDS_EDC_GRBM_CNT__DED_MASK 0x00000003L |
9346 | #define GDS_EDC_GRBM_CNT__SEC_MASK 0x0000000CL |
9347 | #define GDS_EDC_GRBM_CNT__UNUSED_MASK 0xFFFFFFF0L |
9348 | //GDS_EDC_OA_DED |
9349 | #define GDS_EDC_OA_DED__ME0_GFXHP3D_PIX_DED__SHIFT 0x0 |
9350 | #define GDS_EDC_OA_DED__ME0_GFXHP3D_VTX_DED__SHIFT 0x1 |
9351 | #define GDS_EDC_OA_DED__ME0_CS_DED__SHIFT 0x2 |
9352 | #define GDS_EDC_OA_DED__ME0_GFXHP3D_GS_DED__SHIFT 0x3 |
9353 | #define GDS_EDC_OA_DED__ME1_PIPE0_DED__SHIFT 0x4 |
9354 | #define GDS_EDC_OA_DED__ME1_PIPE1_DED__SHIFT 0x5 |
9355 | #define GDS_EDC_OA_DED__ME1_PIPE2_DED__SHIFT 0x6 |
9356 | #define GDS_EDC_OA_DED__ME1_PIPE3_DED__SHIFT 0x7 |
9357 | #define GDS_EDC_OA_DED__ME2_PIPE0_DED__SHIFT 0x8 |
9358 | #define GDS_EDC_OA_DED__ME2_PIPE1_DED__SHIFT 0x9 |
9359 | #define GDS_EDC_OA_DED__ME2_PIPE2_DED__SHIFT 0xa |
9360 | #define GDS_EDC_OA_DED__ME2_PIPE3_DED__SHIFT 0xb |
9361 | #define GDS_EDC_OA_DED__ME0_PIPE1_CS_DED__SHIFT 0xc |
9362 | #define GDS_EDC_OA_DED__UNUSED1__SHIFT 0xd |
9363 | #define GDS_EDC_OA_DED__ME0_GFXHP3D_PIX_DED_MASK 0x00000001L |
9364 | #define GDS_EDC_OA_DED__ME0_GFXHP3D_VTX_DED_MASK 0x00000002L |
9365 | #define GDS_EDC_OA_DED__ME0_CS_DED_MASK 0x00000004L |
9366 | #define GDS_EDC_OA_DED__ME0_GFXHP3D_GS_DED_MASK 0x00000008L |
9367 | #define GDS_EDC_OA_DED__ME1_PIPE0_DED_MASK 0x00000010L |
9368 | #define GDS_EDC_OA_DED__ME1_PIPE1_DED_MASK 0x00000020L |
9369 | #define GDS_EDC_OA_DED__ME1_PIPE2_DED_MASK 0x00000040L |
9370 | #define GDS_EDC_OA_DED__ME1_PIPE3_DED_MASK 0x00000080L |
9371 | #define GDS_EDC_OA_DED__ME2_PIPE0_DED_MASK 0x00000100L |
9372 | #define GDS_EDC_OA_DED__ME2_PIPE1_DED_MASK 0x00000200L |
9373 | #define GDS_EDC_OA_DED__ME2_PIPE2_DED_MASK 0x00000400L |
9374 | #define GDS_EDC_OA_DED__ME2_PIPE3_DED_MASK 0x00000800L |
9375 | #define GDS_EDC_OA_DED__ME0_PIPE1_CS_DED_MASK 0x00001000L |
9376 | #define GDS_EDC_OA_DED__UNUSED1_MASK 0xFFFFE000L |
9377 | //GDS_DSM_CNTL |
9378 | #define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_0__SHIFT 0x0 |
9379 | #define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_1__SHIFT 0x1 |
9380 | #define GDS_DSM_CNTL__GDS_MEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 |
9381 | #define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_0__SHIFT 0x3 |
9382 | #define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_1__SHIFT 0x4 |
9383 | #define GDS_DSM_CNTL__GDS_INPUT_QUEUE_ENABLE_SINGLE_WRITE__SHIFT 0x5 |
9384 | #define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_0__SHIFT 0x6 |
9385 | #define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_1__SHIFT 0x7 |
9386 | #define GDS_DSM_CNTL__GDS_PHY_CMD_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x8 |
9387 | #define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_0__SHIFT 0x9 |
9388 | #define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_1__SHIFT 0xa |
9389 | #define GDS_DSM_CNTL__GDS_PHY_DATA_RAM_ENABLE_SINGLE_WRITE__SHIFT 0xb |
9390 | #define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_0__SHIFT 0xc |
9391 | #define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_1__SHIFT 0xd |
9392 | #define GDS_DSM_CNTL__GDS_PIPE_MEM_ENABLE_SINGLE_WRITE__SHIFT 0xe |
9393 | #define GDS_DSM_CNTL__UNUSED__SHIFT 0xf |
9394 | #define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_0_MASK 0x00000001L |
9395 | #define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_1_MASK 0x00000002L |
9396 | #define GDS_DSM_CNTL__GDS_MEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L |
9397 | #define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_0_MASK 0x00000008L |
9398 | #define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_1_MASK 0x00000010L |
9399 | #define GDS_DSM_CNTL__GDS_INPUT_QUEUE_ENABLE_SINGLE_WRITE_MASK 0x00000020L |
9400 | #define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_0_MASK 0x00000040L |
9401 | #define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_1_MASK 0x00000080L |
9402 | #define GDS_DSM_CNTL__GDS_PHY_CMD_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000100L |
9403 | #define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_0_MASK 0x00000200L |
9404 | #define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_1_MASK 0x00000400L |
9405 | #define GDS_DSM_CNTL__GDS_PHY_DATA_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000800L |
9406 | #define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_0_MASK 0x00001000L |
9407 | #define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_1_MASK 0x00002000L |
9408 | #define GDS_DSM_CNTL__GDS_PIPE_MEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L |
9409 | #define GDS_DSM_CNTL__UNUSED_MASK 0xFFFF8000L |
9410 | //GDS_EDC_OA_PHY_CNT |
9411 | #define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_SEC__SHIFT 0x0 |
9412 | #define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_DED__SHIFT 0x2 |
9413 | #define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_SEC__SHIFT 0x4 |
9414 | #define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_DED__SHIFT 0x6 |
9415 | #define GDS_EDC_OA_PHY_CNT__PHY_DATA_RAM_MEM_SED__SHIFT 0x8 |
9416 | #define GDS_EDC_OA_PHY_CNT__UNUSED1__SHIFT 0xa |
9417 | #define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_SEC_MASK 0x00000003L |
9418 | #define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_DED_MASK 0x0000000CL |
9419 | #define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_SEC_MASK 0x00000030L |
9420 | #define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_DED_MASK 0x000000C0L |
9421 | #define GDS_EDC_OA_PHY_CNT__PHY_DATA_RAM_MEM_SED_MASK 0x00000300L |
9422 | #define GDS_EDC_OA_PHY_CNT__UNUSED1_MASK 0xFFFFFC00L |
9423 | //GDS_EDC_OA_PIPE_CNT |
9424 | #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_SEC__SHIFT 0x0 |
9425 | #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_DED__SHIFT 0x2 |
9426 | #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_SEC__SHIFT 0x4 |
9427 | #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_DED__SHIFT 0x6 |
9428 | #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_SEC__SHIFT 0x8 |
9429 | #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_DED__SHIFT 0xa |
9430 | #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_SEC__SHIFT 0xc |
9431 | #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_DED__SHIFT 0xe |
9432 | #define GDS_EDC_OA_PIPE_CNT__UNUSED__SHIFT 0x10 |
9433 | #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_SEC_MASK 0x00000003L |
9434 | #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_DED_MASK 0x0000000CL |
9435 | #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_SEC_MASK 0x00000030L |
9436 | #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_DED_MASK 0x000000C0L |
9437 | #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_SEC_MASK 0x00000300L |
9438 | #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_DED_MASK 0x00000C00L |
9439 | #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_SEC_MASK 0x00003000L |
9440 | #define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_DED_MASK 0x0000C000L |
9441 | #define GDS_EDC_OA_PIPE_CNT__UNUSED_MASK 0xFFFF0000L |
9442 | //GDS_DSM_CNTL2 |
9443 | #define GDS_DSM_CNTL2__GDS_MEM_ENABLE_ERROR_INJECT__SHIFT 0x0 |
9444 | #define GDS_DSM_CNTL2__GDS_MEM_SELECT_INJECT_DELAY__SHIFT 0x2 |
9445 | #define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_ENABLE_ERROR_INJECT__SHIFT 0x3 |
9446 | #define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_SELECT_INJECT_DELAY__SHIFT 0x5 |
9447 | #define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_ENABLE_ERROR_INJECT__SHIFT 0x6 |
9448 | #define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_SELECT_INJECT_DELAY__SHIFT 0x8 |
9449 | #define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_ENABLE_ERROR_INJECT__SHIFT 0x9 |
9450 | #define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_SELECT_INJECT_DELAY__SHIFT 0xb |
9451 | #define GDS_DSM_CNTL2__GDS_PIPE_MEM_ENABLE_ERROR_INJECT__SHIFT 0xc |
9452 | #define GDS_DSM_CNTL2__GDS_PIPE_MEM_SELECT_INJECT_DELAY__SHIFT 0xe |
9453 | #define GDS_DSM_CNTL2__UNUSED__SHIFT 0xf |
9454 | #define GDS_DSM_CNTL2__GDS_INJECT_DELAY__SHIFT 0x1a |
9455 | #define GDS_DSM_CNTL2__GDS_MEM_ENABLE_ERROR_INJECT_MASK 0x00000003L |
9456 | #define GDS_DSM_CNTL2__GDS_MEM_SELECT_INJECT_DELAY_MASK 0x00000004L |
9457 | #define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_ENABLE_ERROR_INJECT_MASK 0x00000018L |
9458 | #define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_SELECT_INJECT_DELAY_MASK 0x00000020L |
9459 | #define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_ENABLE_ERROR_INJECT_MASK 0x000000C0L |
9460 | #define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_SELECT_INJECT_DELAY_MASK 0x00000100L |
9461 | #define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_ENABLE_ERROR_INJECT_MASK 0x00000600L |
9462 | #define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_SELECT_INJECT_DELAY_MASK 0x00000800L |
9463 | #define GDS_DSM_CNTL2__GDS_PIPE_MEM_ENABLE_ERROR_INJECT_MASK 0x00003000L |
9464 | #define GDS_DSM_CNTL2__GDS_PIPE_MEM_SELECT_INJECT_DELAY_MASK 0x00004000L |
9465 | #define GDS_DSM_CNTL2__UNUSED_MASK 0x03FF8000L |
9466 | #define GDS_DSM_CNTL2__GDS_INJECT_DELAY_MASK 0xFC000000L |
9467 | |
9468 | |
9469 | // addressBlock: gc_rbdec |
9470 | //DB_DEBUG |
9471 | #define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE__SHIFT 0x0 |
9472 | #define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE__SHIFT 0x1 |
9473 | #define DB_DEBUG__FETCH_FULL_Z_TILE__SHIFT 0x2 |
9474 | #define DB_DEBUG__FETCH_FULL_STENCIL_TILE__SHIFT 0x3 |
9475 | #define DB_DEBUG__FORCE_Z_MODE__SHIFT 0x4 |
9476 | #define DB_DEBUG__DEBUG_FORCE_DEPTH_READ__SHIFT 0x6 |
9477 | #define DB_DEBUG__DEBUG_FORCE_STENCIL_READ__SHIFT 0x7 |
9478 | #define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE__SHIFT 0x8 |
9479 | #define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0__SHIFT 0xa |
9480 | #define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1__SHIFT 0xc |
9481 | #define DB_DEBUG__DEBUG_FAST_Z_DISABLE__SHIFT 0xe |
9482 | #define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE__SHIFT 0xf |
9483 | #define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE__SHIFT 0x10 |
9484 | #define DB_DEBUG__DISABLE_SUMM_SQUADS__SHIFT 0x11 |
9485 | #define DB_DEBUG__DEPTH_CACHE_FORCE_MISS__SHIFT 0x12 |
9486 | #define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE__SHIFT 0x13 |
9487 | #define DB_DEBUG__NEVER_FREE_Z_ONLY__SHIFT 0x15 |
9488 | #define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS__SHIFT 0x16 |
9489 | #define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION__SHIFT 0x17 |
9490 | #define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES__SHIFT 0x18 |
9491 | #define DB_DEBUG__ONE_FREE_IN_FLIGHT__SHIFT 0x1c |
9492 | #define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT__SHIFT 0x1d |
9493 | #define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC__SHIFT 0x1e |
9494 | #define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC__SHIFT 0x1f |
9495 | #define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE_MASK 0x00000001L |
9496 | #define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE_MASK 0x00000002L |
9497 | #define DB_DEBUG__FETCH_FULL_Z_TILE_MASK 0x00000004L |
9498 | #define DB_DEBUG__FETCH_FULL_STENCIL_TILE_MASK 0x00000008L |
9499 | #define DB_DEBUG__FORCE_Z_MODE_MASK 0x00000030L |
9500 | #define DB_DEBUG__DEBUG_FORCE_DEPTH_READ_MASK 0x00000040L |
9501 | #define DB_DEBUG__DEBUG_FORCE_STENCIL_READ_MASK 0x00000080L |
9502 | #define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE_MASK 0x00000300L |
9503 | #define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0_MASK 0x00000C00L |
9504 | #define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1_MASK 0x00003000L |
9505 | #define DB_DEBUG__DEBUG_FAST_Z_DISABLE_MASK 0x00004000L |
9506 | #define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE_MASK 0x00008000L |
9507 | #define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE_MASK 0x00010000L |
9508 | #define DB_DEBUG__DISABLE_SUMM_SQUADS_MASK 0x00020000L |
9509 | #define DB_DEBUG__DEPTH_CACHE_FORCE_MISS_MASK 0x00040000L |
9510 | #define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE_MASK 0x00180000L |
9511 | #define DB_DEBUG__NEVER_FREE_Z_ONLY_MASK 0x00200000L |
9512 | #define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS_MASK 0x00400000L |
9513 | #define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION_MASK 0x00800000L |
9514 | #define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES_MASK 0x0F000000L |
9515 | #define DB_DEBUG__ONE_FREE_IN_FLIGHT_MASK 0x10000000L |
9516 | #define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT_MASK 0x20000000L |
9517 | #define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC_MASK 0x40000000L |
9518 | #define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC_MASK 0x80000000L |
9519 | //DB_DEBUG2 |
9520 | #define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING__SHIFT 0x0 |
9521 | #define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE__SHIFT 0x1 |
9522 | #define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE__SHIFT 0x2 |
9523 | #define DB_DEBUG2__DTR_ROUND_ROBIN_ARB__SHIFT 0x3 |
9524 | #define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM__SHIFT 0x4 |
9525 | #define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL__SHIFT 0x5 |
9526 | #define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_REZ__SHIFT 0x6 |
9527 | #define DB_DEBUG2__ENABLE_VIEWPORT_STALL_ON_ALL__SHIFT 0x7 |
9528 | #define DB_DEBUG2__OPTIMIZE_HIZ_MATCHES_FB_DISABLE__SHIFT 0x8 |
9529 | #define DB_DEBUG2__CLK_OFF_DELAY__SHIFT 0x9 |
9530 | #define DB_DEBUG2__FORCE_PERF_COUNTERS_ON__SHIFT 0xe |
9531 | #define DB_DEBUG2__FULL_TILE_CACHE_EVICT_ON_HALF_FULL__SHIFT 0xf |
9532 | #define DB_DEBUG2__DISABLE_HTILE_PAIRED_PIPES__SHIFT 0x10 |
9533 | #define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING__SHIFT 0x11 |
9534 | #define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING__SHIFT 0x12 |
9535 | #define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL__SHIFT 0x13 |
9536 | #define DB_DEBUG2__DISABLE_FULL_TILE_WAVE_BREAK__SHIFT 0x14 |
9537 | #define DB_DEBUG2__ENABLE_FULL_TILE_WAVE_BREAK_FOR_ALL_TILES__SHIFT 0x15 |
9538 | #define DB_DEBUG2__FORCE_ITERATE_256__SHIFT 0x18 |
9539 | #define DB_DEBUG2__RESERVED1__SHIFT 0x1a |
9540 | #define DB_DEBUG2__DEBUG_BUS_FLOP_EN__SHIFT 0x1b |
9541 | #define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM__SHIFT 0x1c |
9542 | #define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL__SHIFT 0x1d |
9543 | #define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM__SHIFT 0x1e |
9544 | #define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT__SHIFT 0x1f |
9545 | #define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING_MASK 0x00000001L |
9546 | #define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE_MASK 0x00000002L |
9547 | #define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE_MASK 0x00000004L |
9548 | #define DB_DEBUG2__DTR_ROUND_ROBIN_ARB_MASK 0x00000008L |
9549 | #define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM_MASK 0x00000010L |
9550 | #define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_MASK 0x00000020L |
9551 | #define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_REZ_MASK 0x00000040L |
9552 | #define DB_DEBUG2__ENABLE_VIEWPORT_STALL_ON_ALL_MASK 0x00000080L |
9553 | #define DB_DEBUG2__OPTIMIZE_HIZ_MATCHES_FB_DISABLE_MASK 0x00000100L |
9554 | #define DB_DEBUG2__CLK_OFF_DELAY_MASK 0x00003E00L |
9555 | #define DB_DEBUG2__FORCE_PERF_COUNTERS_ON_MASK 0x00004000L |
9556 | #define DB_DEBUG2__FULL_TILE_CACHE_EVICT_ON_HALF_FULL_MASK 0x00008000L |
9557 | #define DB_DEBUG2__DISABLE_HTILE_PAIRED_PIPES_MASK 0x00010000L |
9558 | #define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING_MASK 0x00020000L |
9559 | #define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING_MASK 0x00040000L |
9560 | #define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL_MASK 0x00080000L |
9561 | #define DB_DEBUG2__DISABLE_FULL_TILE_WAVE_BREAK_MASK 0x00100000L |
9562 | #define DB_DEBUG2__ENABLE_FULL_TILE_WAVE_BREAK_FOR_ALL_TILES_MASK 0x00200000L |
9563 | #define DB_DEBUG2__FORCE_ITERATE_256_MASK 0x03000000L |
9564 | #define DB_DEBUG2__RESERVED1_MASK 0x04000000L |
9565 | #define DB_DEBUG2__DEBUG_BUS_FLOP_EN_MASK 0x08000000L |
9566 | #define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM_MASK 0x10000000L |
9567 | #define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL_MASK 0x20000000L |
9568 | #define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM_MASK 0x40000000L |
9569 | #define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT_MASK 0x80000000L |
9570 | //DB_DEBUG3 |
9571 | #define DB_DEBUG3__DISABLE_CLEAR_ZRANGE_CORRECTION__SHIFT 0x0 |
9572 | #define DB_DEBUG3__DISABLE_RELOAD_CONTEXT_DRAW_DATA__SHIFT 0x1 |
9573 | #define DB_DEBUG3__FORCE_DB_IS_GOOD__SHIFT 0x2 |
9574 | #define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION__SHIFT 0x3 |
9575 | #define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP__SHIFT 0x4 |
9576 | #define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z__SHIFT 0x5 |
9577 | #define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z__SHIFT 0x6 |
9578 | #define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION__SHIFT 0x8 |
9579 | #define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP__SHIFT 0xa |
9580 | #define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS__SHIFT 0xb |
9581 | #define DB_DEBUG3__DISABLE_OP_DF_BYPASS__SHIFT 0xd |
9582 | #define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE__SHIFT 0xe |
9583 | #define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK__SHIFT 0xf |
9584 | #define DB_DEBUG3__DISABLE_SLOCS_PER_CTXT_MATCH__SHIFT 0x10 |
9585 | #define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE__SHIFT 0x11 |
9586 | #define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE__SHIFT 0x13 |
9587 | #define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE__SHIFT 0x14 |
9588 | #define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT__SHIFT 0x15 |
9589 | #define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB__SHIFT 0x16 |
9590 | #define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD__SHIFT 0x17 |
9591 | #define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT__SHIFT 0x18 |
9592 | #define DB_DEBUG3__DISABLE_DI_DT_STALL__SHIFT 0x19 |
9593 | #define DB_DEBUG3__ENABLE_DB_PROCESS_RESET__SHIFT 0x1a |
9594 | #define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX__SHIFT 0x1b |
9595 | #define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND__SHIFT 0x1c |
9596 | #define DB_DEBUG3__DELETE_CONTEXT_SUSPEND__SHIFT 0x1d |
9597 | #define DB_DEBUG3__DISABLE_TS_WRITE_L0__SHIFT 0x1e |
9598 | #define DB_DEBUG3__DISABLE_MULTIDTAG_FL_PANIC_REQUIREMENT__SHIFT 0x1f |
9599 | #define DB_DEBUG3__DISABLE_CLEAR_ZRANGE_CORRECTION_MASK 0x00000001L |
9600 | #define DB_DEBUG3__DISABLE_RELOAD_CONTEXT_DRAW_DATA_MASK 0x00000002L |
9601 | #define DB_DEBUG3__FORCE_DB_IS_GOOD_MASK 0x00000004L |
9602 | #define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION_MASK 0x00000008L |
9603 | #define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP_MASK 0x00000010L |
9604 | #define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z_MASK 0x00000020L |
9605 | #define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z_MASK 0x00000040L |
9606 | #define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION_MASK 0x00000100L |
9607 | #define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP_MASK 0x00000400L |
9608 | #define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS_MASK 0x00000800L |
9609 | #define DB_DEBUG3__DISABLE_OP_DF_BYPASS_MASK 0x00002000L |
9610 | #define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE_MASK 0x00004000L |
9611 | #define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK_MASK 0x00008000L |
9612 | #define DB_DEBUG3__DISABLE_SLOCS_PER_CTXT_MATCH_MASK 0x00010000L |
9613 | #define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE_MASK 0x00020000L |
9614 | #define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE_MASK 0x00080000L |
9615 | #define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE_MASK 0x00100000L |
9616 | #define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT_MASK 0x00200000L |
9617 | #define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB_MASK 0x00400000L |
9618 | #define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD_MASK 0x00800000L |
9619 | #define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT_MASK 0x01000000L |
9620 | #define DB_DEBUG3__DISABLE_DI_DT_STALL_MASK 0x02000000L |
9621 | #define DB_DEBUG3__ENABLE_DB_PROCESS_RESET_MASK 0x04000000L |
9622 | #define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX_MASK 0x08000000L |
9623 | #define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND_MASK 0x10000000L |
9624 | #define DB_DEBUG3__DELETE_CONTEXT_SUSPEND_MASK 0x20000000L |
9625 | #define DB_DEBUG3__DISABLE_TS_WRITE_L0_MASK 0x40000000L |
9626 | #define DB_DEBUG3__DISABLE_MULTIDTAG_FL_PANIC_REQUIREMENT_MASK 0x80000000L |
9627 | //DB_DEBUG4 |
9628 | #define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION__SHIFT 0x0 |
9629 | #define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION__SHIFT 0x1 |
9630 | #define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL__SHIFT 0x2 |
9631 | #define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL__SHIFT 0x3 |
9632 | #define DB_DEBUG4__DISABLE_SEPARATE_OP_PIPE_CLK__SHIFT 0x4 |
9633 | #define DB_DEBUG4__DISABLE_SEPARATE_SX_CLK__SHIFT 0x5 |
9634 | #define DB_DEBUG4__ALWAYS_ON_RMI_CLK_EN__SHIFT 0x6 |
9635 | #define DB_DEBUG4__ENABLE_DBCB_SLOW_FORMAT_COLLAPSE__SHIFT 0x7 |
9636 | #define DB_DEBUG4__DISABLE_SEPARATE_DBG_CLK__SHIFT 0x8 |
9637 | #define DB_DEBUG4__DISABLE_UNMAPPED_Z_INDICATOR__SHIFT 0x9 |
9638 | #define DB_DEBUG4__DISABLE_UNMAPPED_S_INDICATOR__SHIFT 0xa |
9639 | #define DB_DEBUG4__DISABLE_UNMAPPED_H_INDICATOR__SHIFT 0xb |
9640 | #define DB_DEBUG4__ENABLE_A2M_DQUAD_OPTIMIZATION__SHIFT 0xc |
9641 | #define DB_DEBUG4__DISABLE_DTT_FAST_HTILENACK_LOOKUP__SHIFT 0xd |
9642 | #define DB_DEBUG4__DISABLE_RESCHECK_MEMCOHER_OPTIMIZATION__SHIFT 0xe |
9643 | #define DB_DEBUG4__DISABLE_DYNAMIC_RAM_LIGHT_SLEEP_MODE__SHIFT 0xf |
9644 | #define DB_DEBUG4__DISABLE_HIZ_TS_COLLISION_DETECT__SHIFT 0x10 |
9645 | #define DB_DEBUG4__DISABLE_LAST_OF_BURST_ON_FLUSH_CHUNK0_ALL_DONE__SHIFT 0x12 |
9646 | #define DB_DEBUG4__ENABLE_CZ_OVERFLOW_TESTMODE__SHIFT 0x13 |
9647 | #define DB_DEBUG4__DISABLE_MCC_BURST_FIFO__SHIFT 0x15 |
9648 | #define DB_DEBUG4__DISABLE_MCC_BURST_FIFO_CONFLICT__SHIFT 0x16 |
9649 | #define DB_DEBUG4__WR_MEM_BURST_CTL__SHIFT 0x18 |
9650 | #define DB_DEBUG4__DISABLE_WR_MEM_BURST_POOLING__SHIFT 0x1b |
9651 | #define DB_DEBUG4__DISABLE_RD_MEM_BURST__SHIFT 0x1c |
9652 | #define DB_DEBUG4__LATE_ACK_SCOREBOARD_MULTIPLE_SLOT__SHIFT 0x1e |
9653 | #define DB_DEBUG4__LATE_ACK_PSD_EOP_OLD_METHOD__SHIFT 0x1f |
9654 | #define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION_MASK 0x00000001L |
9655 | #define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION_MASK 0x00000002L |
9656 | #define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL_MASK 0x00000004L |
9657 | #define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL_MASK 0x00000008L |
9658 | #define DB_DEBUG4__DISABLE_SEPARATE_OP_PIPE_CLK_MASK 0x00000010L |
9659 | #define DB_DEBUG4__DISABLE_SEPARATE_SX_CLK_MASK 0x00000020L |
9660 | #define DB_DEBUG4__ALWAYS_ON_RMI_CLK_EN_MASK 0x00000040L |
9661 | #define DB_DEBUG4__ENABLE_DBCB_SLOW_FORMAT_COLLAPSE_MASK 0x00000080L |
9662 | #define DB_DEBUG4__DISABLE_SEPARATE_DBG_CLK_MASK 0x00000100L |
9663 | #define DB_DEBUG4__DISABLE_UNMAPPED_Z_INDICATOR_MASK 0x00000200L |
9664 | #define DB_DEBUG4__DISABLE_UNMAPPED_S_INDICATOR_MASK 0x00000400L |
9665 | #define DB_DEBUG4__DISABLE_UNMAPPED_H_INDICATOR_MASK 0x00000800L |
9666 | #define DB_DEBUG4__ENABLE_A2M_DQUAD_OPTIMIZATION_MASK 0x00001000L |
9667 | #define DB_DEBUG4__DISABLE_DTT_FAST_HTILENACK_LOOKUP_MASK 0x00002000L |
9668 | #define DB_DEBUG4__DISABLE_RESCHECK_MEMCOHER_OPTIMIZATION_MASK 0x00004000L |
9669 | #define DB_DEBUG4__DISABLE_DYNAMIC_RAM_LIGHT_SLEEP_MODE_MASK 0x00008000L |
9670 | #define DB_DEBUG4__DISABLE_HIZ_TS_COLLISION_DETECT_MASK 0x00010000L |
9671 | #define DB_DEBUG4__DISABLE_LAST_OF_BURST_ON_FLUSH_CHUNK0_ALL_DONE_MASK 0x00040000L |
9672 | #define DB_DEBUG4__ENABLE_CZ_OVERFLOW_TESTMODE_MASK 0x00080000L |
9673 | #define DB_DEBUG4__DISABLE_MCC_BURST_FIFO_MASK 0x00200000L |
9674 | #define DB_DEBUG4__DISABLE_MCC_BURST_FIFO_CONFLICT_MASK 0x00400000L |
9675 | #define DB_DEBUG4__WR_MEM_BURST_CTL_MASK 0x07000000L |
9676 | #define DB_DEBUG4__DISABLE_WR_MEM_BURST_POOLING_MASK 0x08000000L |
9677 | #define DB_DEBUG4__DISABLE_RD_MEM_BURST_MASK 0x10000000L |
9678 | #define DB_DEBUG4__LATE_ACK_SCOREBOARD_MULTIPLE_SLOT_MASK 0x40000000L |
9679 | #define DB_DEBUG4__LATE_ACK_PSD_EOP_OLD_METHOD_MASK 0x80000000L |
9680 | //DB_ETILE_STUTTER_CONTROL |
9681 | #define DB_ETILE_STUTTER_CONTROL__THRESHOLD__SHIFT 0x0 |
9682 | #define DB_ETILE_STUTTER_CONTROL__TIMEOUT__SHIFT 0x10 |
9683 | #define DB_ETILE_STUTTER_CONTROL__THRESHOLD_MASK 0x000000FFL |
9684 | #define DB_ETILE_STUTTER_CONTROL__TIMEOUT_MASK 0x00FF0000L |
9685 | //DB_LTILE_STUTTER_CONTROL |
9686 | #define DB_LTILE_STUTTER_CONTROL__THRESHOLD__SHIFT 0x0 |
9687 | #define DB_LTILE_STUTTER_CONTROL__TIMEOUT__SHIFT 0x10 |
9688 | #define DB_LTILE_STUTTER_CONTROL__THRESHOLD_MASK 0x000000FFL |
9689 | #define DB_LTILE_STUTTER_CONTROL__TIMEOUT_MASK 0x00FF0000L |
9690 | //DB_EQUAD_STUTTER_CONTROL |
9691 | #define DB_EQUAD_STUTTER_CONTROL__THRESHOLD__SHIFT 0x0 |
9692 | #define DB_EQUAD_STUTTER_CONTROL__TIMEOUT__SHIFT 0x10 |
9693 | #define DB_EQUAD_STUTTER_CONTROL__THRESHOLD_MASK 0x000000FFL |
9694 | #define DB_EQUAD_STUTTER_CONTROL__TIMEOUT_MASK 0x00FF0000L |
9695 | //DB_LQUAD_STUTTER_CONTROL |
9696 | #define DB_LQUAD_STUTTER_CONTROL__THRESHOLD__SHIFT 0x0 |
9697 | #define DB_LQUAD_STUTTER_CONTROL__TIMEOUT__SHIFT 0x10 |
9698 | #define DB_LQUAD_STUTTER_CONTROL__THRESHOLD_MASK 0x000000FFL |
9699 | #define DB_LQUAD_STUTTER_CONTROL__TIMEOUT_MASK 0x00FF0000L |
9700 | //DB_CREDIT_LIMIT |
9701 | #define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS__SHIFT 0x0 |
9702 | #define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS__SHIFT 0x5 |
9703 | #define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS__SHIFT 0xa |
9704 | #define DB_CREDIT_LIMIT__DB_SC_WAVE_CREDITS__SHIFT 0xd |
9705 | #define DB_CREDIT_LIMIT__DB_SC_FREE_WAVE_CREDITS__SHIFT 0x12 |
9706 | #define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS_MASK 0x0000001FL |
9707 | #define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS_MASK 0x000003E0L |
9708 | #define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS_MASK 0x00001C00L |
9709 | #define DB_CREDIT_LIMIT__DB_SC_WAVE_CREDITS_MASK 0x0003E000L |
9710 | #define DB_CREDIT_LIMIT__DB_SC_FREE_WAVE_CREDITS_MASK 0x007C0000L |
9711 | //DB_WATERMARKS |
9712 | #define DB_WATERMARKS__DEPTH_FREE__SHIFT 0x0 |
9713 | #define DB_WATERMARKS__DEPTH_FLUSH__SHIFT 0x8 |
9714 | #define DB_WATERMARKS__DEPTH_PENDING_FREE__SHIFT 0x10 |
9715 | #define DB_WATERMARKS__DEPTH_CACHELINE_FREE__SHIFT 0x18 |
9716 | #define DB_WATERMARKS__DEPTH_FREE_MASK 0x000000FFL |
9717 | #define DB_WATERMARKS__DEPTH_FLUSH_MASK 0x0000FF00L |
9718 | #define DB_WATERMARKS__DEPTH_PENDING_FREE_MASK 0x00FF0000L |
9719 | #define DB_WATERMARKS__DEPTH_CACHELINE_FREE_MASK 0xFF000000L |
9720 | //DB_SUBTILE_CONTROL |
9721 | #define DB_SUBTILE_CONTROL__MSAA1_X__SHIFT 0x0 |
9722 | #define DB_SUBTILE_CONTROL__MSAA1_Y__SHIFT 0x2 |
9723 | #define DB_SUBTILE_CONTROL__MSAA2_X__SHIFT 0x4 |
9724 | #define DB_SUBTILE_CONTROL__MSAA2_Y__SHIFT 0x6 |
9725 | #define DB_SUBTILE_CONTROL__MSAA4_X__SHIFT 0x8 |
9726 | #define DB_SUBTILE_CONTROL__MSAA4_Y__SHIFT 0xa |
9727 | #define DB_SUBTILE_CONTROL__MSAA8_X__SHIFT 0xc |
9728 | #define DB_SUBTILE_CONTROL__MSAA8_Y__SHIFT 0xe |
9729 | #define DB_SUBTILE_CONTROL__MSAA16_X__SHIFT 0x10 |
9730 | #define DB_SUBTILE_CONTROL__MSAA16_Y__SHIFT 0x12 |
9731 | #define DB_SUBTILE_CONTROL__MSAA1_X_MASK 0x00000003L |
9732 | #define DB_SUBTILE_CONTROL__MSAA1_Y_MASK 0x0000000CL |
9733 | #define DB_SUBTILE_CONTROL__MSAA2_X_MASK 0x00000030L |
9734 | #define DB_SUBTILE_CONTROL__MSAA2_Y_MASK 0x000000C0L |
9735 | #define DB_SUBTILE_CONTROL__MSAA4_X_MASK 0x00000300L |
9736 | #define DB_SUBTILE_CONTROL__MSAA4_Y_MASK 0x00000C00L |
9737 | #define DB_SUBTILE_CONTROL__MSAA8_X_MASK 0x00003000L |
9738 | #define DB_SUBTILE_CONTROL__MSAA8_Y_MASK 0x0000C000L |
9739 | #define DB_SUBTILE_CONTROL__MSAA16_X_MASK 0x00030000L |
9740 | #define DB_SUBTILE_CONTROL__MSAA16_Y_MASK 0x000C0000L |
9741 | //DB_FREE_CACHELINES |
9742 | #define DB_FREE_CACHELINES__FREE_DTILE_DEPTH__SHIFT 0x0 |
9743 | #define DB_FREE_CACHELINES__FREE_PLANE_DEPTH__SHIFT 0x8 |
9744 | #define DB_FREE_CACHELINES__FREE_Z_DEPTH__SHIFT 0x10 |
9745 | #define DB_FREE_CACHELINES__FREE_HTILE_DEPTH__SHIFT 0x18 |
9746 | #define DB_FREE_CACHELINES__FREE_DTILE_DEPTH_MASK 0x000000FFL |
9747 | #define DB_FREE_CACHELINES__FREE_PLANE_DEPTH_MASK 0x0000FF00L |
9748 | #define DB_FREE_CACHELINES__FREE_Z_DEPTH_MASK 0x00FF0000L |
9749 | #define DB_FREE_CACHELINES__FREE_HTILE_DEPTH_MASK 0xFF000000L |
9750 | //DB_FIFO_DEPTH1 |
9751 | #define DB_FIFO_DEPTH1__MI_RDREQ_FIFO_DEPTH__SHIFT 0x0 |
9752 | #define DB_FIFO_DEPTH1__MI_WRREQ_FIFO_DEPTH__SHIFT 0x8 |
9753 | #define DB_FIFO_DEPTH1__MCC_DEPTH__SHIFT 0x10 |
9754 | #define DB_FIFO_DEPTH1__QC_DEPTH__SHIFT 0x18 |
9755 | #define DB_FIFO_DEPTH1__MI_RDREQ_FIFO_DEPTH_MASK 0x000000FFL |
9756 | #define DB_FIFO_DEPTH1__MI_WRREQ_FIFO_DEPTH_MASK 0x0000FF00L |
9757 | #define DB_FIFO_DEPTH1__MCC_DEPTH_MASK 0x00FF0000L |
9758 | #define DB_FIFO_DEPTH1__QC_DEPTH_MASK 0xFF000000L |
9759 | //DB_FIFO_DEPTH2 |
9760 | #define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH__SHIFT 0x0 |
9761 | #define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH__SHIFT 0x8 |
9762 | #define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH__SHIFT 0x10 |
9763 | #define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH__SHIFT 0x19 |
9764 | #define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH_MASK 0x000000FFL |
9765 | #define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH_MASK 0x0000FF00L |
9766 | #define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH_MASK 0x01FF0000L |
9767 | #define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH_MASK 0xFE000000L |
9768 | //DB_LAST_OF_BURST_CONFIG |
9769 | #define DB_LAST_OF_BURST_CONFIG__MAXBURST__SHIFT 0x0 |
9770 | #define DB_LAST_OF_BURST_CONFIG__TIMEOUT__SHIFT 0x8 |
9771 | #define DB_LAST_OF_BURST_CONFIG__DBCB_LOB_SWITCH_TIMEOUT__SHIFT 0xb |
9772 | #define DB_LAST_OF_BURST_CONFIG__ENABLE_FG_DEFAULT_TIMEOUT__SHIFT 0x11 |
9773 | #define DB_LAST_OF_BURST_CONFIG__DISABLE_MCC_BURST_COUNT_RESET_ON_LOB__SHIFT 0x12 |
9774 | #define DB_LAST_OF_BURST_CONFIG__DISABLE_FLQ_LOB_EVERY_256B__SHIFT 0x13 |
9775 | #define DB_LAST_OF_BURST_CONFIG__DISABLE_ZCACHE_FL_OP_EVEN_ARB__SHIFT 0x14 |
9776 | #define DB_LAST_OF_BURST_CONFIG__DISABLE_MCC_BURST_FORCE_FLUSH_BEFORE_FIFO__SHIFT 0x15 |
9777 | #define DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_DKG_LOB_GEN__SHIFT 0x16 |
9778 | #define DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_LPF_LOB_GEN__SHIFT 0x17 |
9779 | #define DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_FL_BURST__SHIFT 0x19 |
9780 | #define DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_FG_LOB_FWDR__SHIFT 0x1a |
9781 | #define DB_LAST_OF_BURST_CONFIG__BYPASS_SORT_RD_BA__SHIFT 0x1c |
9782 | #define DB_LAST_OF_BURST_CONFIG__DISABLE_256B_COALESCE__SHIFT 0x1d |
9783 | #define DB_LAST_OF_BURST_CONFIG__DISABLE_RD_BURST__SHIFT 0x1e |
9784 | #define DB_LAST_OF_BURST_CONFIG__LEGACY_LOB_INSERT_EN__SHIFT 0x1f |
9785 | #define DB_LAST_OF_BURST_CONFIG__MAXBURST_MASK 0x000000FFL |
9786 | #define DB_LAST_OF_BURST_CONFIG__TIMEOUT_MASK 0x00000700L |
9787 | #define DB_LAST_OF_BURST_CONFIG__DBCB_LOB_SWITCH_TIMEOUT_MASK 0x0000F800L |
9788 | #define DB_LAST_OF_BURST_CONFIG__ENABLE_FG_DEFAULT_TIMEOUT_MASK 0x00020000L |
9789 | #define DB_LAST_OF_BURST_CONFIG__DISABLE_MCC_BURST_COUNT_RESET_ON_LOB_MASK 0x00040000L |
9790 | #define DB_LAST_OF_BURST_CONFIG__DISABLE_FLQ_LOB_EVERY_256B_MASK 0x00080000L |
9791 | #define DB_LAST_OF_BURST_CONFIG__DISABLE_ZCACHE_FL_OP_EVEN_ARB_MASK 0x00100000L |
9792 | #define DB_LAST_OF_BURST_CONFIG__DISABLE_MCC_BURST_FORCE_FLUSH_BEFORE_FIFO_MASK 0x00200000L |
9793 | #define DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_DKG_LOB_GEN_MASK 0x00400000L |
9794 | #define DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_LPF_LOB_GEN_MASK 0x00800000L |
9795 | #define DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_FL_BURST_MASK 0x02000000L |
9796 | #define DB_LAST_OF_BURST_CONFIG__ENABLE_TIMEOUT_FG_LOB_FWDR_MASK 0x04000000L |
9797 | #define DB_LAST_OF_BURST_CONFIG__BYPASS_SORT_RD_BA_MASK 0x10000000L |
9798 | #define DB_LAST_OF_BURST_CONFIG__DISABLE_256B_COALESCE_MASK 0x20000000L |
9799 | #define DB_LAST_OF_BURST_CONFIG__DISABLE_RD_BURST_MASK 0x40000000L |
9800 | #define DB_LAST_OF_BURST_CONFIG__LEGACY_LOB_INSERT_EN_MASK 0x80000000L |
9801 | //DB_RING_CONTROL |
9802 | #define DB_RING_CONTROL__COUNTER_CONTROL__SHIFT 0x0 |
9803 | #define DB_RING_CONTROL__COUNTER_CONTROL_MASK 0x00000003L |
9804 | //DB_MEM_ARB_WATERMARKS |
9805 | #define DB_MEM_ARB_WATERMARKS__CLIENT0_WATERMARK__SHIFT 0x0 |
9806 | #define DB_MEM_ARB_WATERMARKS__CLIENT1_WATERMARK__SHIFT 0x8 |
9807 | #define DB_MEM_ARB_WATERMARKS__CLIENT2_WATERMARK__SHIFT 0x10 |
9808 | #define DB_MEM_ARB_WATERMARKS__CLIENT3_WATERMARK__SHIFT 0x18 |
9809 | #define DB_MEM_ARB_WATERMARKS__CLIENT0_WATERMARK_MASK 0x00000007L |
9810 | #define DB_MEM_ARB_WATERMARKS__CLIENT1_WATERMARK_MASK 0x00000700L |
9811 | #define DB_MEM_ARB_WATERMARKS__CLIENT2_WATERMARK_MASK 0x00070000L |
9812 | #define DB_MEM_ARB_WATERMARKS__CLIENT3_WATERMARK_MASK 0x07000000L |
9813 | //DB_FIFO_DEPTH3 |
9814 | #define DB_FIFO_DEPTH3__LTILE_PROBE_FIFO_DEPTH__SHIFT 0x0 |
9815 | #define DB_FIFO_DEPTH3__OSB_WAVE_TABLE_DEPTH__SHIFT 0x8 |
9816 | #define DB_FIFO_DEPTH3__OREO_WAVE_HIDE_DEPTH__SHIFT 0x10 |
9817 | #define DB_FIFO_DEPTH3__QUAD_READ_REQS__SHIFT 0x18 |
9818 | #define DB_FIFO_DEPTH3__LTILE_PROBE_FIFO_DEPTH_MASK 0x000000FFL |
9819 | #define DB_FIFO_DEPTH3__OSB_WAVE_TABLE_DEPTH_MASK 0x0000FF00L |
9820 | #define DB_FIFO_DEPTH3__OREO_WAVE_HIDE_DEPTH_MASK 0x00FF0000L |
9821 | #define DB_FIFO_DEPTH3__QUAD_READ_REQS_MASK 0xFF000000L |
9822 | //DB_DEBUG6 |
9823 | #define DB_DEBUG6__FORCE_DB_SC_WAVE_CONFLICT__SHIFT 0x0 |
9824 | #define DB_DEBUG6__FORCE_DB_SC_WAVE_HARD_CONFLICT__SHIFT 0x1 |
9825 | #define DB_DEBUG6__FORCE_DB_SC_QUAD_CONFLICT__SHIFT 0x2 |
9826 | #define DB_DEBUG6__OREO_TRANSITION_EVENT_ALL__SHIFT 0x3 |
9827 | #define DB_DEBUG6__OREO_TRANSITION_EVENT_ID__SHIFT 0x4 |
9828 | #define DB_DEBUG6__OREO_TRANSITION_EVENT_EN__SHIFT 0xa |
9829 | #define DB_DEBUG6__DISABLE_PWS_PLUS_TCP_CM_LIVENESS_STALL__SHIFT 0xb |
9830 | #define DB_DEBUG6__DISABLE_PWS_PLUS_DTT_TAG_LIVENESS_STALL__SHIFT 0xc |
9831 | #define DB_DEBUG6__SET_DB_PERFMON_PWS_PIPE_ID__SHIFT 0xd |
9832 | #define DB_DEBUG6__FTWB_MAX_TIMEOUT_VAL__SHIFT 0x10 |
9833 | #define DB_DEBUG6__DISABLE_LQO_SMT_RAM_OPT__SHIFT 0x18 |
9834 | #define DB_DEBUG6__FORCE_MAX_TILES_IN_WAVE_CHECK__SHIFT 0x19 |
9835 | #define DB_DEBUG6__DISABLE_OSB_DEADLOCK_FIX__SHIFT 0x1a |
9836 | #define DB_DEBUG6__DISABLE_OSB_DEADLOCK_WAIT_PANIC__SHIFT 0x1b |
9837 | #define DB_DEBUG6__FORCE_DB_SC_WAVE_CONFLICT_MASK 0x00000001L |
9838 | #define DB_DEBUG6__FORCE_DB_SC_WAVE_HARD_CONFLICT_MASK 0x00000002L |
9839 | #define DB_DEBUG6__FORCE_DB_SC_QUAD_CONFLICT_MASK 0x00000004L |
9840 | #define DB_DEBUG6__OREO_TRANSITION_EVENT_ALL_MASK 0x00000008L |
9841 | #define DB_DEBUG6__OREO_TRANSITION_EVENT_ID_MASK 0x000003F0L |
9842 | #define DB_DEBUG6__OREO_TRANSITION_EVENT_EN_MASK 0x00000400L |
9843 | #define DB_DEBUG6__DISABLE_PWS_PLUS_TCP_CM_LIVENESS_STALL_MASK 0x00000800L |
9844 | #define DB_DEBUG6__DISABLE_PWS_PLUS_DTT_TAG_LIVENESS_STALL_MASK 0x00001000L |
9845 | #define DB_DEBUG6__SET_DB_PERFMON_PWS_PIPE_ID_MASK 0x00006000L |
9846 | #define DB_DEBUG6__FTWB_MAX_TIMEOUT_VAL_MASK 0x00FF0000L |
9847 | #define DB_DEBUG6__DISABLE_LQO_SMT_RAM_OPT_MASK 0x01000000L |
9848 | #define DB_DEBUG6__FORCE_MAX_TILES_IN_WAVE_CHECK_MASK 0x02000000L |
9849 | #define DB_DEBUG6__DISABLE_OSB_DEADLOCK_FIX_MASK 0x04000000L |
9850 | #define DB_DEBUG6__DISABLE_OSB_DEADLOCK_WAIT_PANIC_MASK 0x08000000L |
9851 | //DB_EXCEPTION_CONTROL |
9852 | #define DB_EXCEPTION_CONTROL__EARLY_Z_PANIC_DISABLE__SHIFT 0x0 |
9853 | #define DB_EXCEPTION_CONTROL__LATE_Z_PANIC_DISABLE__SHIFT 0x1 |
9854 | #define DB_EXCEPTION_CONTROL__RE_Z_PANIC_DISABLE__SHIFT 0x2 |
9855 | #define DB_EXCEPTION_CONTROL__AUTO_FLUSH_HTILE__SHIFT 0x3 |
9856 | #define DB_EXCEPTION_CONTROL__AUTO_FLUSH_QUAD__SHIFT 0x4 |
9857 | #define DB_EXCEPTION_CONTROL__FORCE_SUMMARIZE__SHIFT 0x8 |
9858 | #define DB_EXCEPTION_CONTROL__DTAG_WATERMARK__SHIFT 0x18 |
9859 | #define DB_EXCEPTION_CONTROL__EARLY_Z_PANIC_DISABLE_MASK 0x00000001L |
9860 | #define DB_EXCEPTION_CONTROL__LATE_Z_PANIC_DISABLE_MASK 0x00000002L |
9861 | #define DB_EXCEPTION_CONTROL__RE_Z_PANIC_DISABLE_MASK 0x00000004L |
9862 | #define DB_EXCEPTION_CONTROL__AUTO_FLUSH_HTILE_MASK 0x00000008L |
9863 | #define DB_EXCEPTION_CONTROL__AUTO_FLUSH_QUAD_MASK 0x00000010L |
9864 | #define DB_EXCEPTION_CONTROL__FORCE_SUMMARIZE_MASK 0x00000F00L |
9865 | #define DB_EXCEPTION_CONTROL__DTAG_WATERMARK_MASK 0x7F000000L |
9866 | //DB_DEBUG7 |
9867 | #define DB_DEBUG7__SPARE_BITS__SHIFT 0x0 |
9868 | #define DB_DEBUG7__SPARE_BITS_MASK 0xFFFFFFFFL |
9869 | //DB_DEBUG5 |
9870 | #define DB_DEBUG5__DISABLE_TILE_CACHE_PRELOAD__SHIFT 0x0 |
9871 | #define DB_DEBUG5__ENABLE_SECONDARY_MIPS_TAILS_COMPRESSION__SHIFT 0x1 |
9872 | #define DB_DEBUG5__DISABLE_CLEAR_VALUE_UPDATE_ON_TILE_CACHE_HIT__SHIFT 0x2 |
9873 | #define DB_DEBUG5__DISABLE_2SRC_VRS_HARD_CONFLICT__SHIFT 0x3 |
9874 | #define DB_DEBUG5__DISABLE_FLQ_MCC_DTILEID_CHECK__SHIFT 0x4 |
9875 | #define DB_DEBUG5__DISABLE_NOZ_POWER_SAVINGS__SHIFT 0x5 |
9876 | #define DB_DEBUG5__DISABLE_TILE_INFLIGHT_DEC_POSTZ_FIX__SHIFT 0x6 |
9877 | #define DB_DEBUG5__DISABLE_MGCG_GATING_ON_SHADER_WAIT__SHIFT 0x7 |
9878 | #define DB_DEBUG5__DISABLE_VRS_1X2_2XAA__SHIFT 0x8 |
9879 | #define DB_DEBUG5__ENABLE_FULL_TILE_WAVE_BREAK_ON_COARSE__SHIFT 0x9 |
9880 | #define DB_DEBUG5__DISABLE_HTILE_HARVESTING__SHIFT 0xa |
9881 | #define DB_DEBUG5__DISABLE_SEPARATE_TILE_CLK__SHIFT 0xb |
9882 | #define DB_DEBUG5__DISABLE_TILE_CACHE_PREFETCH__SHIFT 0xc |
9883 | #define DB_DEBUG5__DISABLE_PSL_AUTO_MODE_FIX__SHIFT 0xd |
9884 | #define DB_DEBUG5__DISABLE_FORCE_ZMASK_EXPANDED__SHIFT 0xe |
9885 | #define DB_DEBUG5__DISABLE_SEPARATE_LQO_CLK__SHIFT 0xf |
9886 | #define DB_DEBUG5__DISABLE_Z_WITHOUT_PLANES_FLQ__SHIFT 0x10 |
9887 | #define DB_DEBUG5__PRESERVE_QMASK_FOR_POSTZ_OP_PIPE__SHIFT 0x11 |
9888 | #define DB_DEBUG5__Z_NACK_BEHAVIOR_ONLY_WHEN_Z_IS_PRT__SHIFT 0x12 |
9889 | #define DB_DEBUG5__S_NACK_BEHAVIOR_ONLY_WHEN_S_IS_PRT__SHIFT 0x13 |
9890 | #define DB_DEBUG5__DISABLE_RESIDENCY_CHECK_Z__SHIFT 0x14 |
9891 | #define DB_DEBUG5__DISABLE_RESIDENCY_CHECK_STENCIL__SHIFT 0x15 |
9892 | #define DB_DEBUG5__DISABLE_LQO_FTCQ_DUAL_QUAD_REGION_CHECK__SHIFT 0x16 |
9893 | #define DB_DEBUG5__DISABLE_EVENT_INSERTION_AFTER_ZPC_BEFORE_CONTEXT_DONE__SHIFT 0x17 |
9894 | #define DB_DEBUG5__SPARE_BITS__SHIFT 0x18 |
9895 | #define DB_DEBUG5__DISABLE_TILE_CACHE_PRELOAD_MASK 0x00000001L |
9896 | #define DB_DEBUG5__ENABLE_SECONDARY_MIPS_TAILS_COMPRESSION_MASK 0x00000002L |
9897 | #define DB_DEBUG5__DISABLE_CLEAR_VALUE_UPDATE_ON_TILE_CACHE_HIT_MASK 0x00000004L |
9898 | #define DB_DEBUG5__DISABLE_2SRC_VRS_HARD_CONFLICT_MASK 0x00000008L |
9899 | #define DB_DEBUG5__DISABLE_FLQ_MCC_DTILEID_CHECK_MASK 0x00000010L |
9900 | #define DB_DEBUG5__DISABLE_NOZ_POWER_SAVINGS_MASK 0x00000020L |
9901 | #define DB_DEBUG5__DISABLE_TILE_INFLIGHT_DEC_POSTZ_FIX_MASK 0x00000040L |
9902 | #define DB_DEBUG5__DISABLE_MGCG_GATING_ON_SHADER_WAIT_MASK 0x00000080L |
9903 | #define DB_DEBUG5__DISABLE_VRS_1X2_2XAA_MASK 0x00000100L |
9904 | #define DB_DEBUG5__ENABLE_FULL_TILE_WAVE_BREAK_ON_COARSE_MASK 0x00000200L |
9905 | #define DB_DEBUG5__DISABLE_HTILE_HARVESTING_MASK 0x00000400L |
9906 | #define DB_DEBUG5__DISABLE_SEPARATE_TILE_CLK_MASK 0x00000800L |
9907 | #define DB_DEBUG5__DISABLE_TILE_CACHE_PREFETCH_MASK 0x00001000L |
9908 | #define DB_DEBUG5__DISABLE_PSL_AUTO_MODE_FIX_MASK 0x00002000L |
9909 | #define DB_DEBUG5__DISABLE_FORCE_ZMASK_EXPANDED_MASK 0x00004000L |
9910 | #define DB_DEBUG5__DISABLE_SEPARATE_LQO_CLK_MASK 0x00008000L |
9911 | #define DB_DEBUG5__DISABLE_Z_WITHOUT_PLANES_FLQ_MASK 0x00010000L |
9912 | #define DB_DEBUG5__PRESERVE_QMASK_FOR_POSTZ_OP_PIPE_MASK 0x00020000L |
9913 | #define DB_DEBUG5__Z_NACK_BEHAVIOR_ONLY_WHEN_Z_IS_PRT_MASK 0x00040000L |
9914 | #define DB_DEBUG5__S_NACK_BEHAVIOR_ONLY_WHEN_S_IS_PRT_MASK 0x00080000L |
9915 | #define DB_DEBUG5__DISABLE_RESIDENCY_CHECK_Z_MASK 0x00100000L |
9916 | #define DB_DEBUG5__DISABLE_RESIDENCY_CHECK_STENCIL_MASK 0x00200000L |
9917 | #define DB_DEBUG5__DISABLE_LQO_FTCQ_DUAL_QUAD_REGION_CHECK_MASK 0x00400000L |
9918 | #define DB_DEBUG5__DISABLE_EVENT_INSERTION_AFTER_ZPC_BEFORE_CONTEXT_DONE_MASK 0x00800000L |
9919 | #define DB_DEBUG5__SPARE_BITS_MASK 0xFF000000L |
9920 | //DB_FGCG_SRAMS_CLK_CTRL |
9921 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE0__SHIFT 0x0 |
9922 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE1__SHIFT 0x1 |
9923 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE2__SHIFT 0x2 |
9924 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE3__SHIFT 0x3 |
9925 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE4__SHIFT 0x4 |
9926 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE5__SHIFT 0x5 |
9927 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE6__SHIFT 0x6 |
9928 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE7__SHIFT 0x7 |
9929 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE8__SHIFT 0x8 |
9930 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE9__SHIFT 0x9 |
9931 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE10__SHIFT 0xa |
9932 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE11__SHIFT 0xb |
9933 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE12__SHIFT 0xc |
9934 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE13__SHIFT 0xd |
9935 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE14__SHIFT 0xe |
9936 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE15__SHIFT 0xf |
9937 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE16__SHIFT 0x10 |
9938 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE17__SHIFT 0x11 |
9939 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE18__SHIFT 0x12 |
9940 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE19__SHIFT 0x13 |
9941 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE20__SHIFT 0x14 |
9942 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE21__SHIFT 0x15 |
9943 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE22__SHIFT 0x16 |
9944 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE23__SHIFT 0x17 |
9945 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE24__SHIFT 0x18 |
9946 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE25__SHIFT 0x19 |
9947 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE26__SHIFT 0x1a |
9948 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE27__SHIFT 0x1b |
9949 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE28__SHIFT 0x1c |
9950 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE29__SHIFT 0x1d |
9951 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE30__SHIFT 0x1e |
9952 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE31__SHIFT 0x1f |
9953 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE0_MASK 0x00000001L |
9954 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE1_MASK 0x00000002L |
9955 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE2_MASK 0x00000004L |
9956 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE3_MASK 0x00000008L |
9957 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE4_MASK 0x00000010L |
9958 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE5_MASK 0x00000020L |
9959 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE6_MASK 0x00000040L |
9960 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE7_MASK 0x00000080L |
9961 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE8_MASK 0x00000100L |
9962 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE9_MASK 0x00000200L |
9963 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE10_MASK 0x00000400L |
9964 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE11_MASK 0x00000800L |
9965 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE12_MASK 0x00001000L |
9966 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE13_MASK 0x00002000L |
9967 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE14_MASK 0x00004000L |
9968 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE15_MASK 0x00008000L |
9969 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE16_MASK 0x00010000L |
9970 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE17_MASK 0x00020000L |
9971 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE18_MASK 0x00040000L |
9972 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE19_MASK 0x00080000L |
9973 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE20_MASK 0x00100000L |
9974 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE21_MASK 0x00200000L |
9975 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE22_MASK 0x00400000L |
9976 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE23_MASK 0x00800000L |
9977 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE24_MASK 0x01000000L |
9978 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE25_MASK 0x02000000L |
9979 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE26_MASK 0x04000000L |
9980 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE27_MASK 0x08000000L |
9981 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE28_MASK 0x10000000L |
9982 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE29_MASK 0x20000000L |
9983 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE30_MASK 0x40000000L |
9984 | #define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE31_MASK 0x80000000L |
9985 | //DB_FGCG_INTERFACES_CLK_CTRL |
9986 | #define DB_FGCG_INTERFACES_CLK_CTRL__DB_SC_QUAD_OVERRIDE__SHIFT 0x0 |
9987 | #define DB_FGCG_INTERFACES_CLK_CTRL__DB_CB_EXPORT_OVERRIDE__SHIFT 0x2 |
9988 | #define DB_FGCG_INTERFACES_CLK_CTRL__DB_RMI_RDREQ_OVERRIDE__SHIFT 0x3 |
9989 | #define DB_FGCG_INTERFACES_CLK_CTRL__DB_RMI_WRREQ_OVERRIDE__SHIFT 0x4 |
9990 | #define DB_FGCG_INTERFACES_CLK_CTRL__DB_SC_TILE_OVERRIDE__SHIFT 0x5 |
9991 | #define DB_FGCG_INTERFACES_CLK_CTRL__DB_CB_RMIRET_OVERRIDE__SHIFT 0x6 |
9992 | #define DB_FGCG_INTERFACES_CLK_CTRL__DB_SC_WAVE_OVERRIDE__SHIFT 0x7 |
9993 | #define DB_FGCG_INTERFACES_CLK_CTRL__DB_SC_FREE_WAVE_OVERRIDE__SHIFT 0x8 |
9994 | #define DB_FGCG_INTERFACES_CLK_CTRL__DB_SC_QUAD_OVERRIDE_MASK 0x00000001L |
9995 | #define DB_FGCG_INTERFACES_CLK_CTRL__DB_CB_EXPORT_OVERRIDE_MASK 0x00000004L |
9996 | #define DB_FGCG_INTERFACES_CLK_CTRL__DB_RMI_RDREQ_OVERRIDE_MASK 0x00000008L |
9997 | #define DB_FGCG_INTERFACES_CLK_CTRL__DB_RMI_WRREQ_OVERRIDE_MASK 0x00000010L |
9998 | #define DB_FGCG_INTERFACES_CLK_CTRL__DB_SC_TILE_OVERRIDE_MASK 0x00000020L |
9999 | #define DB_FGCG_INTERFACES_CLK_CTRL__DB_CB_RMIRET_OVERRIDE_MASK 0x00000040L |
10000 | #define DB_FGCG_INTERFACES_CLK_CTRL__DB_SC_WAVE_OVERRIDE_MASK 0x00000080L |
10001 | #define DB_FGCG_INTERFACES_CLK_CTRL__DB_SC_FREE_WAVE_OVERRIDE_MASK 0x00000100L |
10002 | //DB_FIFO_DEPTH4 |
10003 | #define DB_FIFO_DEPTH4__OSB_SQUAD_TABLE_DEPTH__SHIFT 0x0 |
10004 | #define DB_FIFO_DEPTH4__OSB_TILE_TABLE_DEPTH__SHIFT 0x8 |
10005 | #define DB_FIFO_DEPTH4__OSB_SCORE_BOARD_DEPTH__SHIFT 0x10 |
10006 | #define DB_FIFO_DEPTH4__OSB_EVENT_FIFO_DEPTH__SHIFT 0x18 |
10007 | #define DB_FIFO_DEPTH4__OSB_SQUAD_TABLE_DEPTH_MASK 0x000000FFL |
10008 | #define DB_FIFO_DEPTH4__OSB_TILE_TABLE_DEPTH_MASK 0x0000FF00L |
10009 | #define DB_FIFO_DEPTH4__OSB_SCORE_BOARD_DEPTH_MASK 0x00FF0000L |
10010 | #define DB_FIFO_DEPTH4__OSB_EVENT_FIFO_DEPTH_MASK 0xFF000000L |
10011 | //CC_RB_REDUNDANCY |
10012 | #define CC_RB_REDUNDANCY__WRITE_DIS__SHIFT 0x0 |
10013 | #define CC_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8 |
10014 | #define CC_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc |
10015 | #define CC_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10 |
10016 | #define CC_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14 |
10017 | #define CC_RB_REDUNDANCY__WRITE_DIS_MASK 0x00000001L |
10018 | #define CC_RB_REDUNDANCY__FAILED_RB0_MASK 0x00000F00L |
10019 | #define CC_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x00001000L |
10020 | #define CC_RB_REDUNDANCY__FAILED_RB1_MASK 0x000F0000L |
10021 | #define CC_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x00100000L |
10022 | //CC_RB_BACKEND_DISABLE |
10023 | #define CC_RB_BACKEND_DISABLE__WRITE_DIS__SHIFT 0x0 |
10024 | #define CC_RB_BACKEND_DISABLE__RESERVED__SHIFT 0x2 |
10025 | #define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x4 |
10026 | #define CC_RB_BACKEND_DISABLE__WRITE_DIS_MASK 0x00000001L |
10027 | #define CC_RB_BACKEND_DISABLE__RESERVED_MASK 0x0000000CL |
10028 | #define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0xFFFFFFF0L |
10029 | //GB_ADDR_CONFIG |
10030 | #define GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 |
10031 | #define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 |
10032 | #define GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0x6 |
10033 | #define GB_ADDR_CONFIG__NUM_PKRS__SHIFT 0x8 |
10034 | #define GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 |
10035 | #define GB_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT 0x1a |
10036 | #define GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L |
10037 | #define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L |
10038 | #define GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L |
10039 | #define GB_ADDR_CONFIG__NUM_PKRS_MASK 0x00000700L |
10040 | #define GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L |
10041 | #define GB_ADDR_CONFIG__NUM_RB_PER_SE_MASK 0x0C000000L |
10042 | //GB_BACKEND_MAP |
10043 | #define GB_BACKEND_MAP__BACKEND_MAP__SHIFT 0x0 |
10044 | #define GB_BACKEND_MAP__BACKEND_MAP_MASK 0xFFFFFFFFL |
10045 | //GB_GPU_ID |
10046 | #define GB_GPU_ID__GPU_ID__SHIFT 0x0 |
10047 | #define GB_GPU_ID__GPU_ID_MASK 0x0000000FL |
10048 | //CC_RB_DAISY_CHAIN |
10049 | #define CC_RB_DAISY_CHAIN__RB_0__SHIFT 0x0 |
10050 | #define CC_RB_DAISY_CHAIN__RB_1__SHIFT 0x4 |
10051 | #define CC_RB_DAISY_CHAIN__RB_2__SHIFT 0x8 |
10052 | #define CC_RB_DAISY_CHAIN__RB_3__SHIFT 0xc |
10053 | #define CC_RB_DAISY_CHAIN__RB_4__SHIFT 0x10 |
10054 | #define CC_RB_DAISY_CHAIN__RB_5__SHIFT 0x14 |
10055 | #define CC_RB_DAISY_CHAIN__RB_6__SHIFT 0x18 |
10056 | #define CC_RB_DAISY_CHAIN__RB_7__SHIFT 0x1c |
10057 | #define CC_RB_DAISY_CHAIN__RB_0_MASK 0x0000000FL |
10058 | #define CC_RB_DAISY_CHAIN__RB_1_MASK 0x000000F0L |
10059 | #define CC_RB_DAISY_CHAIN__RB_2_MASK 0x00000F00L |
10060 | #define CC_RB_DAISY_CHAIN__RB_3_MASK 0x0000F000L |
10061 | #define CC_RB_DAISY_CHAIN__RB_4_MASK 0x000F0000L |
10062 | #define CC_RB_DAISY_CHAIN__RB_5_MASK 0x00F00000L |
10063 | #define CC_RB_DAISY_CHAIN__RB_6_MASK 0x0F000000L |
10064 | #define CC_RB_DAISY_CHAIN__RB_7_MASK 0xF0000000L |
10065 | //GB_ADDR_CONFIG_READ |
10066 | #define GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0 |
10067 | #define GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 |
10068 | #define GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS__SHIFT 0x6 |
10069 | #define GB_ADDR_CONFIG_READ__NUM_PKRS__SHIFT 0x8 |
10070 | #define GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13 |
10071 | #define GB_ADDR_CONFIG_READ__NUM_RB_PER_SE__SHIFT 0x1a |
10072 | #define GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L |
10073 | #define GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L |
10074 | #define GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L |
10075 | #define GB_ADDR_CONFIG_READ__NUM_PKRS_MASK 0x00000700L |
10076 | #define GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L |
10077 | #define GB_ADDR_CONFIG_READ__NUM_RB_PER_SE_MASK 0x0C000000L |
10078 | //CB_HW_CONTROL_4 |
10079 | #define CB_HW_CONTROL_4__COLOR_CACHE_FETCH_NUM_QB_LOG2__SHIFT 0x0 |
10080 | #define CB_HW_CONTROL_4__COLOR_CACHE_FETCH_ALGORITHM__SHIFT 0x3 |
10081 | #define CB_HW_CONTROL_4__DISABLE_USE_OF_SMT_SCORE__SHIFT 0x5 |
10082 | #define CB_HW_CONTROL_4__SPARE_10__SHIFT 0x6 |
10083 | #define CB_HW_CONTROL_4__SPARE_11__SHIFT 0x7 |
10084 | #define CB_HW_CONTROL_4__SPARE_12__SHIFT 0x8 |
10085 | #define CB_HW_CONTROL_4__DISABLE_MA_WAIT_FOR_LAST__SHIFT 0x9 |
10086 | #define CB_HW_CONTROL_4__SMT_TIMEOUT_THRESHOLD__SHIFT 0xa |
10087 | #define CB_HW_CONTROL_4__SMT_QPFIFO_THRESHOLD__SHIFT 0xd |
10088 | #define CB_HW_CONTROL_4__ENABLE_FRAGOP_STALLING_ON_RAW_HAZARD__SHIFT 0x10 |
10089 | #define CB_HW_CONTROL_4__ENABLE_FRAGOP_STALLING_ON_COARSE_RAW_HAZARD__SHIFT 0x11 |
10090 | #define CB_HW_CONTROL_4__ENABLE_FRAGOP_STALLING_ON_DS_RAW_HAZARD__SHIFT 0x12 |
10091 | #define CB_HW_CONTROL_4__COLOR_CACHE_FETCH_NUM_QB_LOG2_MASK 0x00000007L |
10092 | #define CB_HW_CONTROL_4__COLOR_CACHE_FETCH_ALGORITHM_MASK 0x00000018L |
10093 | #define CB_HW_CONTROL_4__DISABLE_USE_OF_SMT_SCORE_MASK 0x00000020L |
10094 | #define CB_HW_CONTROL_4__SPARE_10_MASK 0x00000040L |
10095 | #define CB_HW_CONTROL_4__SPARE_11_MASK 0x00000080L |
10096 | #define CB_HW_CONTROL_4__SPARE_12_MASK 0x00000100L |
10097 | #define CB_HW_CONTROL_4__DISABLE_MA_WAIT_FOR_LAST_MASK 0x00000200L |
10098 | #define CB_HW_CONTROL_4__SMT_TIMEOUT_THRESHOLD_MASK 0x00001C00L |
10099 | #define CB_HW_CONTROL_4__SMT_QPFIFO_THRESHOLD_MASK 0x0000E000L |
10100 | #define CB_HW_CONTROL_4__ENABLE_FRAGOP_STALLING_ON_RAW_HAZARD_MASK 0x00010000L |
10101 | #define CB_HW_CONTROL_4__ENABLE_FRAGOP_STALLING_ON_COARSE_RAW_HAZARD_MASK 0x00020000L |
10102 | #define CB_HW_CONTROL_4__ENABLE_FRAGOP_STALLING_ON_DS_RAW_HAZARD_MASK 0x00040000L |
10103 | //CB_HW_CONTROL_3 |
10104 | #define CB_HW_CONTROL_3__SPARE_5__SHIFT 0x0 |
10105 | #define CB_HW_CONTROL_3__RAM_ADDRESS_CONFLICTS_DISALLOWED__SHIFT 0x1 |
10106 | #define CB_HW_CONTROL_3__SPARE_6__SHIFT 0x2 |
10107 | #define CB_HW_CONTROL_3__SPARE_7__SHIFT 0x3 |
10108 | #define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_STATUS_ACCUM__SHIFT 0x4 |
10109 | #define CB_HW_CONTROL_3__DISABLE_CC_CACHE_PANIC_GATING__SHIFT 0x5 |
10110 | #define CB_HW_CONTROL_3__SPLIT_ALL_FAST_MODE_TRANSFERS__SHIFT 0x6 |
10111 | #define CB_HW_CONTROL_3__DISABLE_SHADER_BLEND_OPTS__SHIFT 0x7 |
10112 | #define CB_HW_CONTROL_3__FORCE_RMI_LAST_HIGH__SHIFT 0xb |
10113 | #define CB_HW_CONTROL_3__FORCE_RMI_CLKEN_HIGH__SHIFT 0xc |
10114 | #define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CC__SHIFT 0xd |
10115 | #define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_DC__SHIFT 0xe |
10116 | #define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CC__SHIFT 0xf |
10117 | #define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_DC__SHIFT 0x10 |
10118 | #define CB_HW_CONTROL_3__SPARE_8__SHIFT 0x11 |
10119 | #define CB_HW_CONTROL_3__SPARE_9__SHIFT 0x12 |
10120 | #define CB_HW_CONTROL_3__DISABLE_DCC_VRS_OPT__SHIFT 0x14 |
10121 | #define CB_HW_CONTROL_3__DISABLE_FMASK_NOALLOC_OPT__SHIFT 0x15 |
10122 | #define CB_HW_CONTROL_3__SPARE_5_MASK 0x00000001L |
10123 | #define CB_HW_CONTROL_3__RAM_ADDRESS_CONFLICTS_DISALLOWED_MASK 0x00000002L |
10124 | #define CB_HW_CONTROL_3__SPARE_6_MASK 0x00000004L |
10125 | #define CB_HW_CONTROL_3__SPARE_7_MASK 0x00000008L |
10126 | #define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_STATUS_ACCUM_MASK 0x00000010L |
10127 | #define CB_HW_CONTROL_3__DISABLE_CC_CACHE_PANIC_GATING_MASK 0x00000020L |
10128 | #define CB_HW_CONTROL_3__SPLIT_ALL_FAST_MODE_TRANSFERS_MASK 0x00000040L |
10129 | #define CB_HW_CONTROL_3__DISABLE_SHADER_BLEND_OPTS_MASK 0x00000080L |
10130 | #define CB_HW_CONTROL_3__FORCE_RMI_LAST_HIGH_MASK 0x00000800L |
10131 | #define CB_HW_CONTROL_3__FORCE_RMI_CLKEN_HIGH_MASK 0x00001000L |
10132 | #define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CC_MASK 0x00002000L |
10133 | #define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_DC_MASK 0x00004000L |
10134 | #define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CC_MASK 0x00008000L |
10135 | #define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_DC_MASK 0x00010000L |
10136 | #define CB_HW_CONTROL_3__SPARE_8_MASK 0x00020000L |
10137 | #define CB_HW_CONTROL_3__SPARE_9_MASK 0x00040000L |
10138 | #define CB_HW_CONTROL_3__DISABLE_DCC_VRS_OPT_MASK 0x00100000L |
10139 | #define CB_HW_CONTROL_3__DISABLE_FMASK_NOALLOC_OPT_MASK 0x00200000L |
10140 | //CB_HW_CONTROL |
10141 | #define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE__SHIFT 0x0 |
10142 | #define CB_HW_CONTROL__DISABLE_VRS_FILLRATE_OPTIMIZATION__SHIFT 0x1 |
10143 | #define CB_HW_CONTROL__DISABLE_SMT_WHEN_NO_FDCC_FIX__SHIFT 0x2 |
10144 | #define CB_HW_CONTROL__RMI_CREDITS__SHIFT 0x6 |
10145 | #define CB_HW_CONTROL__NUM_CCC_SKID_FIFO_ENTRIES__SHIFT 0xc |
10146 | #define CB_HW_CONTROL__FORCE_FEA_HIGH__SHIFT 0xf |
10147 | #define CB_HW_CONTROL__FORCE_EVICT_ALL_VALID__SHIFT 0x10 |
10148 | #define CB_HW_CONTROL__DISABLE_DCC_CACHE_BYTEMASKING__SHIFT 0x11 |
10149 | #define CB_HW_CONTROL__FORCE_NEEDS_DST__SHIFT 0x13 |
10150 | #define CB_HW_CONTROL__DISABLE_USE_OF_SET_HASH__SHIFT 0x14 |
10151 | #define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST__SHIFT 0x15 |
10152 | #define CB_HW_CONTROL__SPARE_2__SHIFT 0x16 |
10153 | #define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT 0x18 |
10154 | #define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS__SHIFT 0x19 |
10155 | #define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT 0x1a |
10156 | #define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED__SHIFT 0x1b |
10157 | #define CB_HW_CONTROL__SPARE_3__SHIFT 0x1d |
10158 | #define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT__SHIFT 0x1e |
10159 | #define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE__SHIFT 0x1f |
10160 | #define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE_MASK 0x00000001L |
10161 | #define CB_HW_CONTROL__DISABLE_VRS_FILLRATE_OPTIMIZATION_MASK 0x00000002L |
10162 | #define CB_HW_CONTROL__DISABLE_SMT_WHEN_NO_FDCC_FIX_MASK 0x00000004L |
10163 | #define CB_HW_CONTROL__RMI_CREDITS_MASK 0x00000FC0L |
10164 | #define CB_HW_CONTROL__NUM_CCC_SKID_FIFO_ENTRIES_MASK 0x00007000L |
10165 | #define CB_HW_CONTROL__FORCE_FEA_HIGH_MASK 0x00008000L |
10166 | #define CB_HW_CONTROL__FORCE_EVICT_ALL_VALID_MASK 0x00010000L |
10167 | #define CB_HW_CONTROL__DISABLE_DCC_CACHE_BYTEMASKING_MASK 0x00020000L |
10168 | #define CB_HW_CONTROL__FORCE_NEEDS_DST_MASK 0x00080000L |
10169 | #define CB_HW_CONTROL__DISABLE_USE_OF_SET_HASH_MASK 0x00100000L |
10170 | #define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST_MASK 0x00200000L |
10171 | #define CB_HW_CONTROL__SPARE_2_MASK 0x00400000L |
10172 | #define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST_MASK 0x01000000L |
10173 | #define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS_MASK 0x02000000L |
10174 | #define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK 0x04000000L |
10175 | #define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED_MASK 0x08000000L |
10176 | #define CB_HW_CONTROL__SPARE_3_MASK 0x20000000L |
10177 | #define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT_MASK 0x40000000L |
10178 | #define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE_MASK 0x80000000L |
10179 | //CB_HW_CONTROL_1 |
10180 | #define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS__SHIFT 0x0 |
10181 | #define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS_MASK 0x0000003FL |
10182 | //CB_HW_CONTROL_2 |
10183 | #define CB_HW_CONTROL_2__SPARE_4__SHIFT 0x0 |
10184 | #define CB_HW_CONTROL_2__DRR_ASSUMED_FIFO_DEPTH_DIV8__SHIFT 0x8 |
10185 | #define CB_HW_CONTROL_2__SPARE__SHIFT 0xe |
10186 | #define CB_HW_CONTROL_2__SPARE_4_MASK 0x000000FFL |
10187 | #define CB_HW_CONTROL_2__DRR_ASSUMED_FIFO_DEPTH_DIV8_MASK 0x00003F00L |
10188 | #define CB_HW_CONTROL_2__SPARE_MASK 0xFFFFC000L |
10189 | //CB_DCC_CONFIG |
10190 | #define CB_DCC_CONFIG__SAMPLE_MASK_TRACKER_DEPTH__SHIFT 0x0 |
10191 | #define CB_DCC_CONFIG__SAMPLE_MASK_TRACKER_DISABLE__SHIFT 0x5 |
10192 | #define CB_DCC_CONFIG__SPARE_13__SHIFT 0x6 |
10193 | #define CB_DCC_CONFIG__DISABLE_CONSTANT_ENCODE__SHIFT 0x7 |
10194 | #define CB_DCC_CONFIG__SPARE_14__SHIFT 0x8 |
10195 | #define CB_DCC_CONFIG__READ_RETURN_SKID_FIFO_DEPTH__SHIFT 0x10 |
10196 | #define CB_DCC_CONFIG__DCC_CACHE_NUM_TAGS__SHIFT 0x19 |
10197 | #define CB_DCC_CONFIG__SAMPLE_MASK_TRACKER_DEPTH_MASK 0x0000001FL |
10198 | #define CB_DCC_CONFIG__SAMPLE_MASK_TRACKER_DISABLE_MASK 0x00000020L |
10199 | #define CB_DCC_CONFIG__SPARE_13_MASK 0x00000040L |
10200 | #define CB_DCC_CONFIG__DISABLE_CONSTANT_ENCODE_MASK 0x00000080L |
10201 | #define CB_DCC_CONFIG__SPARE_14_MASK 0x0000FF00L |
10202 | #define CB_DCC_CONFIG__READ_RETURN_SKID_FIFO_DEPTH_MASK 0x01FF0000L |
10203 | #define CB_DCC_CONFIG__DCC_CACHE_NUM_TAGS_MASK 0xFE000000L |
10204 | //CB_HW_MEM_ARBITER_RD |
10205 | #define CB_HW_MEM_ARBITER_RD__MODE__SHIFT 0x0 |
10206 | #define CB_HW_MEM_ARBITER_RD__IGNORE_URGENT_AGE__SHIFT 0x2 |
10207 | #define CB_HW_MEM_ARBITER_RD__BREAK_GROUP_AGE__SHIFT 0x6 |
10208 | #define CB_HW_MEM_ARBITER_RD__WEIGHT_CC__SHIFT 0xa |
10209 | #define CB_HW_MEM_ARBITER_RD__WEIGHT_DC__SHIFT 0xc |
10210 | #define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_REQS__SHIFT 0xe |
10211 | #define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_NOREQS__SHIFT 0x10 |
10212 | #define CB_HW_MEM_ARBITER_RD__WEIGHT_IGNORE_NUM_TIDS__SHIFT 0x12 |
10213 | #define CB_HW_MEM_ARBITER_RD__SCALE_AGE__SHIFT 0x13 |
10214 | #define CB_HW_MEM_ARBITER_RD__SCALE_WEIGHT__SHIFT 0x16 |
10215 | #define CB_HW_MEM_ARBITER_RD__SEND_LASTS_WITHIN_GROUPS__SHIFT 0x19 |
10216 | #define CB_HW_MEM_ARBITER_RD__MODE_MASK 0x00000003L |
10217 | #define CB_HW_MEM_ARBITER_RD__IGNORE_URGENT_AGE_MASK 0x0000003CL |
10218 | #define CB_HW_MEM_ARBITER_RD__BREAK_GROUP_AGE_MASK 0x000003C0L |
10219 | #define CB_HW_MEM_ARBITER_RD__WEIGHT_CC_MASK 0x00000C00L |
10220 | #define CB_HW_MEM_ARBITER_RD__WEIGHT_DC_MASK 0x00003000L |
10221 | #define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_REQS_MASK 0x0000C000L |
10222 | #define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_NOREQS_MASK 0x00030000L |
10223 | #define CB_HW_MEM_ARBITER_RD__WEIGHT_IGNORE_NUM_TIDS_MASK 0x00040000L |
10224 | #define CB_HW_MEM_ARBITER_RD__SCALE_AGE_MASK 0x00380000L |
10225 | #define CB_HW_MEM_ARBITER_RD__SCALE_WEIGHT_MASK 0x01C00000L |
10226 | #define CB_HW_MEM_ARBITER_RD__SEND_LASTS_WITHIN_GROUPS_MASK 0x02000000L |
10227 | //CB_HW_MEM_ARBITER_WR |
10228 | #define CB_HW_MEM_ARBITER_WR__MODE__SHIFT 0x0 |
10229 | #define CB_HW_MEM_ARBITER_WR__IGNORE_URGENT_AGE__SHIFT 0x2 |
10230 | #define CB_HW_MEM_ARBITER_WR__BREAK_GROUP_AGE__SHIFT 0x6 |
10231 | #define CB_HW_MEM_ARBITER_WR__WEIGHT_CC__SHIFT 0xa |
10232 | #define CB_HW_MEM_ARBITER_WR__WEIGHT_DC__SHIFT 0xc |
10233 | #define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_REQS__SHIFT 0xe |
10234 | #define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_NOREQS__SHIFT 0x10 |
10235 | #define CB_HW_MEM_ARBITER_WR__WEIGHT_IGNORE_BYTE_MASK__SHIFT 0x12 |
10236 | #define CB_HW_MEM_ARBITER_WR__SCALE_AGE__SHIFT 0x13 |
10237 | #define CB_HW_MEM_ARBITER_WR__SCALE_WEIGHT__SHIFT 0x16 |
10238 | #define CB_HW_MEM_ARBITER_WR__SEND_LASTS_WITHIN_GROUPS__SHIFT 0x19 |
10239 | #define CB_HW_MEM_ARBITER_WR__MODE_MASK 0x00000003L |
10240 | #define CB_HW_MEM_ARBITER_WR__IGNORE_URGENT_AGE_MASK 0x0000003CL |
10241 | #define CB_HW_MEM_ARBITER_WR__BREAK_GROUP_AGE_MASK 0x000003C0L |
10242 | #define CB_HW_MEM_ARBITER_WR__WEIGHT_CC_MASK 0x00000C00L |
10243 | #define CB_HW_MEM_ARBITER_WR__WEIGHT_DC_MASK 0x00003000L |
10244 | #define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_REQS_MASK 0x0000C000L |
10245 | #define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_NOREQS_MASK 0x00030000L |
10246 | #define CB_HW_MEM_ARBITER_WR__WEIGHT_IGNORE_BYTE_MASK_MASK 0x00040000L |
10247 | #define CB_HW_MEM_ARBITER_WR__SCALE_AGE_MASK 0x00380000L |
10248 | #define CB_HW_MEM_ARBITER_WR__SCALE_WEIGHT_MASK 0x01C00000L |
10249 | #define CB_HW_MEM_ARBITER_WR__SEND_LASTS_WITHIN_GROUPS_MASK 0x02000000L |
10250 | //CB_FGCG_SRAM_OVERRIDE |
10251 | #define CB_FGCG_SRAM_OVERRIDE__DISABLE_FGCG__SHIFT 0x0 |
10252 | #define CB_FGCG_SRAM_OVERRIDE__DISABLE_FGCG_MASK 0x000FFFFFL |
10253 | //CB_DCC_CONFIG2 |
10254 | #define CB_DCC_CONFIG2__INVALID_KEY_ERROR_CODE__SHIFT 0x0 |
10255 | #define CB_DCC_CONFIG2__CLEAR_FRAG2DCC_KEY_ERROR_CODE__SHIFT 0x8 |
10256 | #define CB_DCC_CONFIG2__ENABLE_COMP_KEY_ERROR_DETECTION__SHIFT 0x9 |
10257 | #define CB_DCC_CONFIG2__INVALID_KEY_ERROR_CODE_MASK 0x000000FFL |
10258 | #define CB_DCC_CONFIG2__CLEAR_FRAG2DCC_KEY_ERROR_CODE_MASK 0x00000100L |
10259 | #define CB_DCC_CONFIG2__ENABLE_COMP_KEY_ERROR_DETECTION_MASK 0x00000200L |
10260 | //CHICKEN_BITS |
10261 | #define CHICKEN_BITS__SPARE__SHIFT 0x0 |
10262 | #define CHICKEN_BITS__SPARE_MASK 0xFFFFFFFFL |
10263 | //CB_CACHE_EVICT_POINTS |
10264 | #define CB_CACHE_EVICT_POINTS__CC_COLOR_EVICT_POINT__SHIFT 0x0 |
10265 | #define CB_CACHE_EVICT_POINTS__CC_FMASK_EVICT_POINT__SHIFT 0x8 |
10266 | #define CB_CACHE_EVICT_POINTS__DCC_CACHE_EVICT_POINT__SHIFT 0x10 |
10267 | #define CB_CACHE_EVICT_POINTS__CC_CACHE_EVICT_POINT__SHIFT 0x18 |
10268 | #define CB_CACHE_EVICT_POINTS__CC_COLOR_EVICT_POINT_MASK 0x000000FFL |
10269 | #define CB_CACHE_EVICT_POINTS__CC_FMASK_EVICT_POINT_MASK 0x0000FF00L |
10270 | #define CB_CACHE_EVICT_POINTS__DCC_CACHE_EVICT_POINT_MASK 0x00FF0000L |
10271 | #define CB_CACHE_EVICT_POINTS__CC_CACHE_EVICT_POINT_MASK 0xFF000000L |
10272 | |
10273 | |
10274 | // addressBlock: gc_gceadec |
10275 | //GCEA_DRAM_RD_CLI2GRP_MAP0 |
10276 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 |
10277 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 |
10278 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 |
10279 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 |
10280 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 |
10281 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa |
10282 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc |
10283 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe |
10284 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 |
10285 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 |
10286 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 |
10287 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 |
10288 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 |
10289 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a |
10290 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c |
10291 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e |
10292 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L |
10293 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL |
10294 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L |
10295 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L |
10296 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L |
10297 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L |
10298 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L |
10299 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L |
10300 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L |
10301 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L |
10302 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L |
10303 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L |
10304 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L |
10305 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L |
10306 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L |
10307 | #define GCEA_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L |
10308 | //GCEA_DRAM_RD_CLI2GRP_MAP1 |
10309 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 |
10310 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 |
10311 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 |
10312 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 |
10313 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 |
10314 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa |
10315 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc |
10316 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe |
10317 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 |
10318 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 |
10319 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 |
10320 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 |
10321 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 |
10322 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a |
10323 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c |
10324 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e |
10325 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L |
10326 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL |
10327 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L |
10328 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L |
10329 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L |
10330 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L |
10331 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L |
10332 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L |
10333 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L |
10334 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L |
10335 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L |
10336 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L |
10337 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L |
10338 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L |
10339 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L |
10340 | #define GCEA_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L |
10341 | //GCEA_DRAM_WR_CLI2GRP_MAP0 |
10342 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 |
10343 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 |
10344 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 |
10345 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 |
10346 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 |
10347 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa |
10348 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc |
10349 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe |
10350 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 |
10351 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 |
10352 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 |
10353 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 |
10354 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 |
10355 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a |
10356 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c |
10357 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e |
10358 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L |
10359 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL |
10360 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L |
10361 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L |
10362 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L |
10363 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L |
10364 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L |
10365 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L |
10366 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L |
10367 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L |
10368 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L |
10369 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L |
10370 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L |
10371 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L |
10372 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L |
10373 | #define GCEA_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L |
10374 | //GCEA_DRAM_WR_CLI2GRP_MAP1 |
10375 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 |
10376 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 |
10377 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 |
10378 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 |
10379 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 |
10380 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa |
10381 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc |
10382 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe |
10383 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 |
10384 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 |
10385 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 |
10386 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 |
10387 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 |
10388 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a |
10389 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c |
10390 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e |
10391 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L |
10392 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL |
10393 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L |
10394 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L |
10395 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L |
10396 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L |
10397 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L |
10398 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L |
10399 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L |
10400 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L |
10401 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L |
10402 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L |
10403 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L |
10404 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L |
10405 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L |
10406 | #define GCEA_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L |
10407 | //GCEA_DRAM_RD_GRP2VC_MAP |
10408 | #define GCEA_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 |
10409 | #define GCEA_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 |
10410 | #define GCEA_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 |
10411 | #define GCEA_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 |
10412 | #define GCEA_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L |
10413 | #define GCEA_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L |
10414 | #define GCEA_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L |
10415 | #define GCEA_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L |
10416 | //GCEA_DRAM_WR_GRP2VC_MAP |
10417 | #define GCEA_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 |
10418 | #define GCEA_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 |
10419 | #define GCEA_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 |
10420 | #define GCEA_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 |
10421 | #define GCEA_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L |
10422 | #define GCEA_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L |
10423 | #define GCEA_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L |
10424 | #define GCEA_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L |
10425 | //GCEA_DRAM_RD_LAZY |
10426 | #define GCEA_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 |
10427 | #define GCEA_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 |
10428 | #define GCEA_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 |
10429 | #define GCEA_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 |
10430 | #define GCEA_DRAM_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc |
10431 | #define GCEA_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 |
10432 | #define GCEA_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b |
10433 | #define GCEA_DRAM_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L |
10434 | #define GCEA_DRAM_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L |
10435 | #define GCEA_DRAM_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L |
10436 | #define GCEA_DRAM_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L |
10437 | #define GCEA_DRAM_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L |
10438 | #define GCEA_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L |
10439 | #define GCEA_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L |
10440 | //GCEA_DRAM_WR_LAZY |
10441 | #define GCEA_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 |
10442 | #define GCEA_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 |
10443 | #define GCEA_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 |
10444 | #define GCEA_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 |
10445 | #define GCEA_DRAM_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc |
10446 | #define GCEA_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 |
10447 | #define GCEA_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b |
10448 | #define GCEA_DRAM_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L |
10449 | #define GCEA_DRAM_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L |
10450 | #define GCEA_DRAM_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L |
10451 | #define GCEA_DRAM_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L |
10452 | #define GCEA_DRAM_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L |
10453 | #define GCEA_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L |
10454 | #define GCEA_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L |
10455 | //GCEA_DRAM_RD_CAM_CNTL |
10456 | #define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 |
10457 | #define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 |
10458 | #define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 |
10459 | #define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc |
10460 | #define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 |
10461 | #define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 |
10462 | #define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 |
10463 | #define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 |
10464 | #define GCEA_DRAM_RD_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c |
10465 | #define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL |
10466 | #define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L |
10467 | #define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L |
10468 | #define GCEA_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L |
10469 | #define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L |
10470 | #define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L |
10471 | #define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L |
10472 | #define GCEA_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L |
10473 | #define GCEA_DRAM_RD_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L |
10474 | //GCEA_DRAM_WR_CAM_CNTL |
10475 | #define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 |
10476 | #define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 |
10477 | #define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 |
10478 | #define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc |
10479 | #define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 |
10480 | #define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 |
10481 | #define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 |
10482 | #define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 |
10483 | #define GCEA_DRAM_WR_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c |
10484 | #define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL |
10485 | #define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L |
10486 | #define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L |
10487 | #define GCEA_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L |
10488 | #define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L |
10489 | #define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L |
10490 | #define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L |
10491 | #define GCEA_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L |
10492 | #define GCEA_DRAM_WR_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L |
10493 | //GCEA_DRAM_PAGE_BURST |
10494 | #define GCEA_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 |
10495 | #define GCEA_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 |
10496 | #define GCEA_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 |
10497 | #define GCEA_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 |
10498 | #define GCEA_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL |
10499 | #define GCEA_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L |
10500 | #define GCEA_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L |
10501 | #define GCEA_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L |
10502 | //GCEA_DRAM_RD_PRI_AGE |
10503 | #define GCEA_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 |
10504 | #define GCEA_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 |
10505 | #define GCEA_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 |
10506 | #define GCEA_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 |
10507 | #define GCEA_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc |
10508 | #define GCEA_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf |
10509 | #define GCEA_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 |
10510 | #define GCEA_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 |
10511 | #define GCEA_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L |
10512 | #define GCEA_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L |
10513 | #define GCEA_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L |
10514 | #define GCEA_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L |
10515 | #define GCEA_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L |
10516 | #define GCEA_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L |
10517 | #define GCEA_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L |
10518 | #define GCEA_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L |
10519 | //GCEA_DRAM_WR_PRI_AGE |
10520 | #define GCEA_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 |
10521 | #define GCEA_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 |
10522 | #define GCEA_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 |
10523 | #define GCEA_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 |
10524 | #define GCEA_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc |
10525 | #define GCEA_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf |
10526 | #define GCEA_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 |
10527 | #define GCEA_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 |
10528 | #define GCEA_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L |
10529 | #define GCEA_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L |
10530 | #define GCEA_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L |
10531 | #define GCEA_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L |
10532 | #define GCEA_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L |
10533 | #define GCEA_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L |
10534 | #define GCEA_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L |
10535 | #define GCEA_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L |
10536 | //GCEA_DRAM_RD_PRI_QUEUING |
10537 | #define GCEA_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 |
10538 | #define GCEA_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 |
10539 | #define GCEA_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 |
10540 | #define GCEA_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 |
10541 | #define GCEA_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L |
10542 | #define GCEA_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L |
10543 | #define GCEA_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L |
10544 | #define GCEA_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L |
10545 | //GCEA_DRAM_WR_PRI_QUEUING |
10546 | #define GCEA_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 |
10547 | #define GCEA_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 |
10548 | #define GCEA_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 |
10549 | #define GCEA_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 |
10550 | #define GCEA_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L |
10551 | #define GCEA_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L |
10552 | #define GCEA_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L |
10553 | #define GCEA_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L |
10554 | //GCEA_DRAM_RD_PRI_FIXED |
10555 | #define GCEA_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 |
10556 | #define GCEA_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 |
10557 | #define GCEA_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 |
10558 | #define GCEA_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 |
10559 | #define GCEA_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L |
10560 | #define GCEA_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L |
10561 | #define GCEA_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L |
10562 | #define GCEA_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L |
10563 | //GCEA_DRAM_WR_PRI_FIXED |
10564 | #define GCEA_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 |
10565 | #define GCEA_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 |
10566 | #define GCEA_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 |
10567 | #define GCEA_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 |
10568 | #define GCEA_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L |
10569 | #define GCEA_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L |
10570 | #define GCEA_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L |
10571 | #define GCEA_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L |
10572 | //GCEA_DRAM_RD_PRI_URGENCY |
10573 | #define GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 |
10574 | #define GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 |
10575 | #define GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 |
10576 | #define GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 |
10577 | #define GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc |
10578 | #define GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd |
10579 | #define GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe |
10580 | #define GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf |
10581 | #define GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L |
10582 | #define GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L |
10583 | #define GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L |
10584 | #define GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L |
10585 | #define GCEA_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L |
10586 | #define GCEA_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L |
10587 | #define GCEA_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L |
10588 | #define GCEA_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L |
10589 | //GCEA_DRAM_WR_PRI_URGENCY |
10590 | #define GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 |
10591 | #define GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 |
10592 | #define GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 |
10593 | #define GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 |
10594 | #define GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc |
10595 | #define GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd |
10596 | #define GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe |
10597 | #define GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf |
10598 | #define GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L |
10599 | #define GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L |
10600 | #define GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L |
10601 | #define GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L |
10602 | #define GCEA_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L |
10603 | #define GCEA_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L |
10604 | #define GCEA_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L |
10605 | #define GCEA_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L |
10606 | //GCEA_DRAM_RD_PRI_QUANT_PRI1 |
10607 | #define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 |
10608 | #define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 |
10609 | #define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 |
10610 | #define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 |
10611 | #define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL |
10612 | #define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L |
10613 | #define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L |
10614 | #define GCEA_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L |
10615 | //GCEA_DRAM_RD_PRI_QUANT_PRI2 |
10616 | #define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 |
10617 | #define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 |
10618 | #define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 |
10619 | #define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 |
10620 | #define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL |
10621 | #define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L |
10622 | #define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L |
10623 | #define GCEA_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L |
10624 | //GCEA_DRAM_RD_PRI_QUANT_PRI3 |
10625 | #define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 |
10626 | #define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 |
10627 | #define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 |
10628 | #define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 |
10629 | #define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL |
10630 | #define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L |
10631 | #define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L |
10632 | #define GCEA_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L |
10633 | //GCEA_DRAM_WR_PRI_QUANT_PRI1 |
10634 | #define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 |
10635 | #define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 |
10636 | #define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 |
10637 | #define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 |
10638 | #define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL |
10639 | #define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L |
10640 | #define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L |
10641 | #define GCEA_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L |
10642 | //GCEA_DRAM_WR_PRI_QUANT_PRI2 |
10643 | #define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 |
10644 | #define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 |
10645 | #define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 |
10646 | #define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 |
10647 | #define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL |
10648 | #define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L |
10649 | #define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L |
10650 | #define GCEA_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L |
10651 | //GCEA_DRAM_WR_PRI_QUANT_PRI3 |
10652 | #define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 |
10653 | #define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 |
10654 | #define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 |
10655 | #define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 |
10656 | #define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL |
10657 | #define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L |
10658 | #define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L |
10659 | #define GCEA_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L |
10660 | //GCEA_IO_RD_CLI2GRP_MAP0 |
10661 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 |
10662 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 |
10663 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 |
10664 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 |
10665 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 |
10666 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa |
10667 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc |
10668 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe |
10669 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 |
10670 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 |
10671 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 |
10672 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 |
10673 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 |
10674 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a |
10675 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c |
10676 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e |
10677 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L |
10678 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL |
10679 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L |
10680 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L |
10681 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L |
10682 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L |
10683 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L |
10684 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L |
10685 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L |
10686 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L |
10687 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L |
10688 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L |
10689 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L |
10690 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L |
10691 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L |
10692 | #define GCEA_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L |
10693 | //GCEA_IO_RD_CLI2GRP_MAP1 |
10694 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 |
10695 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 |
10696 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 |
10697 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 |
10698 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 |
10699 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa |
10700 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc |
10701 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe |
10702 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 |
10703 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 |
10704 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 |
10705 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 |
10706 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 |
10707 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a |
10708 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c |
10709 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e |
10710 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L |
10711 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL |
10712 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L |
10713 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L |
10714 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L |
10715 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L |
10716 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L |
10717 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L |
10718 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L |
10719 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L |
10720 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L |
10721 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L |
10722 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L |
10723 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L |
10724 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L |
10725 | #define GCEA_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L |
10726 | //GCEA_IO_WR_CLI2GRP_MAP0 |
10727 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 |
10728 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 |
10729 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 |
10730 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 |
10731 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 |
10732 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa |
10733 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc |
10734 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe |
10735 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 |
10736 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 |
10737 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 |
10738 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 |
10739 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 |
10740 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a |
10741 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c |
10742 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e |
10743 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L |
10744 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL |
10745 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L |
10746 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L |
10747 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L |
10748 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L |
10749 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L |
10750 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L |
10751 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L |
10752 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L |
10753 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L |
10754 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L |
10755 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L |
10756 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L |
10757 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L |
10758 | #define GCEA_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L |
10759 | //GCEA_IO_WR_CLI2GRP_MAP1 |
10760 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 |
10761 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 |
10762 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 |
10763 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 |
10764 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 |
10765 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa |
10766 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc |
10767 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe |
10768 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 |
10769 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 |
10770 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 |
10771 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 |
10772 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 |
10773 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a |
10774 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c |
10775 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e |
10776 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L |
10777 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL |
10778 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L |
10779 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L |
10780 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L |
10781 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L |
10782 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L |
10783 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L |
10784 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L |
10785 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L |
10786 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L |
10787 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L |
10788 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L |
10789 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L |
10790 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L |
10791 | #define GCEA_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L |
10792 | //GCEA_IO_RD_COMBINE_FLUSH |
10793 | #define GCEA_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 |
10794 | #define GCEA_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 |
10795 | #define GCEA_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 |
10796 | #define GCEA_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc |
10797 | #define GCEA_IO_RD_COMBINE_FLUSH__COMB_MODE__SHIFT 0x10 |
10798 | #define GCEA_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL |
10799 | #define GCEA_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L |
10800 | #define GCEA_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L |
10801 | #define GCEA_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L |
10802 | #define GCEA_IO_RD_COMBINE_FLUSH__COMB_MODE_MASK 0x00030000L |
10803 | //GCEA_IO_WR_COMBINE_FLUSH |
10804 | #define GCEA_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 |
10805 | #define GCEA_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 |
10806 | #define GCEA_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 |
10807 | #define GCEA_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc |
10808 | #define GCEA_IO_WR_COMBINE_FLUSH__COMB_MODE__SHIFT 0x10 |
10809 | #define GCEA_IO_WR_COMBINE_FLUSH__DISABLE_MAM_CHAINING__SHIFT 0x12 |
10810 | #define GCEA_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL |
10811 | #define GCEA_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L |
10812 | #define GCEA_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L |
10813 | #define GCEA_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L |
10814 | #define GCEA_IO_WR_COMBINE_FLUSH__COMB_MODE_MASK 0x00030000L |
10815 | #define GCEA_IO_WR_COMBINE_FLUSH__DISABLE_MAM_CHAINING_MASK 0x00040000L |
10816 | //GCEA_IO_GROUP_BURST |
10817 | #define GCEA_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT 0x0 |
10818 | #define GCEA_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT 0x8 |
10819 | #define GCEA_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT 0x10 |
10820 | #define GCEA_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT 0x18 |
10821 | #define GCEA_IO_GROUP_BURST__RD_LIMIT_LO_MASK 0x000000FFL |
10822 | #define GCEA_IO_GROUP_BURST__RD_LIMIT_HI_MASK 0x0000FF00L |
10823 | #define GCEA_IO_GROUP_BURST__WR_LIMIT_LO_MASK 0x00FF0000L |
10824 | #define GCEA_IO_GROUP_BURST__WR_LIMIT_HI_MASK 0xFF000000L |
10825 | //GCEA_IO_RD_PRI_AGE |
10826 | #define GCEA_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 |
10827 | #define GCEA_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 |
10828 | #define GCEA_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 |
10829 | #define GCEA_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 |
10830 | #define GCEA_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc |
10831 | #define GCEA_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf |
10832 | #define GCEA_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 |
10833 | #define GCEA_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 |
10834 | #define GCEA_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L |
10835 | #define GCEA_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L |
10836 | #define GCEA_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L |
10837 | #define GCEA_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L |
10838 | #define GCEA_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L |
10839 | #define GCEA_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L |
10840 | #define GCEA_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L |
10841 | #define GCEA_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L |
10842 | //GCEA_IO_WR_PRI_AGE |
10843 | #define GCEA_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 |
10844 | #define GCEA_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 |
10845 | #define GCEA_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 |
10846 | #define GCEA_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 |
10847 | #define GCEA_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc |
10848 | #define GCEA_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf |
10849 | #define GCEA_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 |
10850 | #define GCEA_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 |
10851 | #define GCEA_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L |
10852 | #define GCEA_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L |
10853 | #define GCEA_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L |
10854 | #define GCEA_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L |
10855 | #define GCEA_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L |
10856 | #define GCEA_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L |
10857 | #define GCEA_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L |
10858 | #define GCEA_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L |
10859 | //GCEA_IO_RD_PRI_QUEUING |
10860 | #define GCEA_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 |
10861 | #define GCEA_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 |
10862 | #define GCEA_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 |
10863 | #define GCEA_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 |
10864 | #define GCEA_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L |
10865 | #define GCEA_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L |
10866 | #define GCEA_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L |
10867 | #define GCEA_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L |
10868 | //GCEA_IO_WR_PRI_QUEUING |
10869 | #define GCEA_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 |
10870 | #define GCEA_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 |
10871 | #define GCEA_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 |
10872 | #define GCEA_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 |
10873 | #define GCEA_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L |
10874 | #define GCEA_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L |
10875 | #define GCEA_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L |
10876 | #define GCEA_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L |
10877 | //GCEA_IO_RD_PRI_FIXED |
10878 | #define GCEA_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 |
10879 | #define GCEA_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 |
10880 | #define GCEA_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 |
10881 | #define GCEA_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 |
10882 | #define GCEA_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L |
10883 | #define GCEA_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L |
10884 | #define GCEA_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L |
10885 | #define GCEA_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L |
10886 | //GCEA_IO_WR_PRI_FIXED |
10887 | #define GCEA_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 |
10888 | #define GCEA_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 |
10889 | #define GCEA_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 |
10890 | #define GCEA_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 |
10891 | #define GCEA_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L |
10892 | #define GCEA_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L |
10893 | #define GCEA_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L |
10894 | #define GCEA_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L |
10895 | //GCEA_IO_RD_PRI_URGENCY |
10896 | #define GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 |
10897 | #define GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 |
10898 | #define GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 |
10899 | #define GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 |
10900 | #define GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc |
10901 | #define GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd |
10902 | #define GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe |
10903 | #define GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf |
10904 | #define GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L |
10905 | #define GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L |
10906 | #define GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L |
10907 | #define GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L |
10908 | #define GCEA_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L |
10909 | #define GCEA_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L |
10910 | #define GCEA_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L |
10911 | #define GCEA_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L |
10912 | //GCEA_IO_WR_PRI_URGENCY |
10913 | #define GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 |
10914 | #define GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 |
10915 | #define GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 |
10916 | #define GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 |
10917 | #define GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc |
10918 | #define GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd |
10919 | #define GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe |
10920 | #define GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf |
10921 | #define GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L |
10922 | #define GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L |
10923 | #define GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L |
10924 | #define GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L |
10925 | #define GCEA_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L |
10926 | #define GCEA_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L |
10927 | #define GCEA_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L |
10928 | #define GCEA_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L |
10929 | //GCEA_IO_RD_PRI_URGENCY_MASKING |
10930 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 |
10931 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 |
10932 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 |
10933 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 |
10934 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 |
10935 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 |
10936 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 |
10937 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 |
10938 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 |
10939 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 |
10940 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa |
10941 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb |
10942 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc |
10943 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd |
10944 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe |
10945 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf |
10946 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 |
10947 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 |
10948 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 |
10949 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 |
10950 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 |
10951 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 |
10952 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 |
10953 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 |
10954 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 |
10955 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 |
10956 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a |
10957 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b |
10958 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c |
10959 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d |
10960 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e |
10961 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f |
10962 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L |
10963 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L |
10964 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L |
10965 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L |
10966 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L |
10967 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L |
10968 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L |
10969 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L |
10970 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L |
10971 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L |
10972 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L |
10973 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L |
10974 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L |
10975 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L |
10976 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L |
10977 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L |
10978 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L |
10979 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L |
10980 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L |
10981 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L |
10982 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L |
10983 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L |
10984 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L |
10985 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L |
10986 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L |
10987 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L |
10988 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L |
10989 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L |
10990 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L |
10991 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L |
10992 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L |
10993 | #define GCEA_IO_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L |
10994 | //GCEA_IO_WR_PRI_URGENCY_MASKING |
10995 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 |
10996 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 |
10997 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 |
10998 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 |
10999 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 |
11000 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 |
11001 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 |
11002 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 |
11003 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 |
11004 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 |
11005 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa |
11006 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb |
11007 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc |
11008 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd |
11009 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe |
11010 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf |
11011 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 |
11012 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 |
11013 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 |
11014 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 |
11015 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 |
11016 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 |
11017 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 |
11018 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 |
11019 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 |
11020 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 |
11021 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a |
11022 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b |
11023 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c |
11024 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d |
11025 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e |
11026 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f |
11027 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L |
11028 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L |
11029 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L |
11030 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L |
11031 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L |
11032 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L |
11033 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L |
11034 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L |
11035 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L |
11036 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L |
11037 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L |
11038 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L |
11039 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L |
11040 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L |
11041 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L |
11042 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L |
11043 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L |
11044 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L |
11045 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L |
11046 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L |
11047 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L |
11048 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L |
11049 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L |
11050 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L |
11051 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L |
11052 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L |
11053 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L |
11054 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L |
11055 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L |
11056 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L |
11057 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L |
11058 | #define GCEA_IO_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L |
11059 | //GCEA_IO_RD_PRI_QUANT_PRI1 |
11060 | #define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 |
11061 | #define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 |
11062 | #define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 |
11063 | #define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 |
11064 | #define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL |
11065 | #define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L |
11066 | #define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L |
11067 | #define GCEA_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L |
11068 | //GCEA_IO_RD_PRI_QUANT_PRI2 |
11069 | #define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 |
11070 | #define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 |
11071 | #define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 |
11072 | #define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 |
11073 | #define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL |
11074 | #define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L |
11075 | #define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L |
11076 | #define GCEA_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L |
11077 | //GCEA_IO_RD_PRI_QUANT_PRI3 |
11078 | #define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 |
11079 | #define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 |
11080 | #define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 |
11081 | #define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 |
11082 | #define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL |
11083 | #define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L |
11084 | #define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L |
11085 | #define GCEA_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L |
11086 | //GCEA_IO_WR_PRI_QUANT_PRI1 |
11087 | #define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 |
11088 | #define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 |
11089 | #define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 |
11090 | #define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 |
11091 | #define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL |
11092 | #define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L |
11093 | #define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L |
11094 | #define GCEA_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L |
11095 | //GCEA_IO_WR_PRI_QUANT_PRI2 |
11096 | #define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 |
11097 | #define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 |
11098 | #define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 |
11099 | #define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 |
11100 | #define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL |
11101 | #define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L |
11102 | #define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L |
11103 | #define GCEA_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L |
11104 | //GCEA_IO_WR_PRI_QUANT_PRI3 |
11105 | #define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 |
11106 | #define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 |
11107 | #define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 |
11108 | #define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 |
11109 | #define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL |
11110 | #define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L |
11111 | #define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L |
11112 | #define GCEA_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L |
11113 | //GCEA_SDP_ARB_DRAM |
11114 | #define GCEA_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0 |
11115 | #define GCEA_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT 0x8 |
11116 | #define GCEA_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT 0x10 |
11117 | #define GCEA_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT 0x11 |
11118 | #define GCEA_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT 0x12 |
11119 | #define GCEA_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT 0x13 |
11120 | #define GCEA_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT 0x14 |
11121 | #define GCEA_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE__SHIFT 0x15 |
11122 | #define GCEA_SDP_ARB_DRAM__ALLOW_CHAIN_BREAKING__SHIFT 0x16 |
11123 | #define GCEA_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL |
11124 | #define GCEA_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L |
11125 | #define GCEA_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK 0x00010000L |
11126 | #define GCEA_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK 0x00020000L |
11127 | #define GCEA_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK 0x00040000L |
11128 | #define GCEA_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK 0x00080000L |
11129 | #define GCEA_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK 0x00100000L |
11130 | #define GCEA_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE_MASK 0x00200000L |
11131 | #define GCEA_SDP_ARB_DRAM__ALLOW_CHAIN_BREAKING_MASK 0x00400000L |
11132 | //GCEA_SDP_ARB_FINAL |
11133 | #define GCEA_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x0 |
11134 | #define GCEA_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 0x5 |
11135 | #define GCEA_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa |
11136 | #define GCEA_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf |
11137 | #define GCEA_SDP_ARB_FINAL__RDONLY_VC0__SHIFT 0x11 |
11138 | #define GCEA_SDP_ARB_FINAL__RDONLY_VC1__SHIFT 0x12 |
11139 | #define GCEA_SDP_ARB_FINAL__RDONLY_VC2__SHIFT 0x13 |
11140 | #define GCEA_SDP_ARB_FINAL__RDONLY_VC3__SHIFT 0x14 |
11141 | #define GCEA_SDP_ARB_FINAL__RDONLY_VC4__SHIFT 0x15 |
11142 | #define GCEA_SDP_ARB_FINAL__RDONLY_VC5__SHIFT 0x16 |
11143 | #define GCEA_SDP_ARB_FINAL__RDONLY_VC6__SHIFT 0x17 |
11144 | #define GCEA_SDP_ARB_FINAL__RDONLY_VC7__SHIFT 0x18 |
11145 | #define GCEA_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x19 |
11146 | #define GCEA_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x1a |
11147 | #define GCEA_SDP_ARB_FINAL__GMI_BURST_STRETCH__SHIFT 0x1b |
11148 | #define GCEA_SDP_ARB_FINAL__DRAM_RD_THROTTLE__SHIFT 0x1c |
11149 | #define GCEA_SDP_ARB_FINAL__DRAM_WR_THROTTLE__SHIFT 0x1d |
11150 | #define GCEA_SDP_ARB_FINAL__GMI_RD_THROTTLE__SHIFT 0x1e |
11151 | #define GCEA_SDP_ARB_FINAL__GMI_WR_THROTTLE__SHIFT 0x1f |
11152 | #define GCEA_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x0000001FL |
11153 | #define GCEA_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK 0x000003E0L |
11154 | #define GCEA_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L |
11155 | #define GCEA_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L |
11156 | #define GCEA_SDP_ARB_FINAL__RDONLY_VC0_MASK 0x00020000L |
11157 | #define GCEA_SDP_ARB_FINAL__RDONLY_VC1_MASK 0x00040000L |
11158 | #define GCEA_SDP_ARB_FINAL__RDONLY_VC2_MASK 0x00080000L |
11159 | #define GCEA_SDP_ARB_FINAL__RDONLY_VC3_MASK 0x00100000L |
11160 | #define GCEA_SDP_ARB_FINAL__RDONLY_VC4_MASK 0x00200000L |
11161 | #define GCEA_SDP_ARB_FINAL__RDONLY_VC5_MASK 0x00400000L |
11162 | #define GCEA_SDP_ARB_FINAL__RDONLY_VC6_MASK 0x00800000L |
11163 | #define GCEA_SDP_ARB_FINAL__RDONLY_VC7_MASK 0x01000000L |
11164 | #define GCEA_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x02000000L |
11165 | #define GCEA_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x04000000L |
11166 | #define GCEA_SDP_ARB_FINAL__GMI_BURST_STRETCH_MASK 0x08000000L |
11167 | #define GCEA_SDP_ARB_FINAL__DRAM_RD_THROTTLE_MASK 0x10000000L |
11168 | #define GCEA_SDP_ARB_FINAL__DRAM_WR_THROTTLE_MASK 0x20000000L |
11169 | #define GCEA_SDP_ARB_FINAL__GMI_RD_THROTTLE_MASK 0x40000000L |
11170 | #define GCEA_SDP_ARB_FINAL__GMI_WR_THROTTLE_MASK 0x80000000L |
11171 | //GCEA_SDP_DRAM_PRIORITY |
11172 | #define GCEA_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 |
11173 | #define GCEA_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 |
11174 | #define GCEA_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 |
11175 | #define GCEA_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc |
11176 | #define GCEA_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 |
11177 | #define GCEA_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 |
11178 | #define GCEA_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 |
11179 | #define GCEA_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c |
11180 | #define GCEA_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL |
11181 | #define GCEA_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L |
11182 | #define GCEA_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L |
11183 | #define GCEA_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L |
11184 | #define GCEA_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L |
11185 | #define GCEA_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L |
11186 | #define GCEA_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L |
11187 | #define GCEA_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L |
11188 | //GCEA_SDP_IO_PRIORITY |
11189 | #define GCEA_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 |
11190 | #define GCEA_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 |
11191 | #define GCEA_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 |
11192 | #define GCEA_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc |
11193 | #define GCEA_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 |
11194 | #define GCEA_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 |
11195 | #define GCEA_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 |
11196 | #define GCEA_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c |
11197 | #define GCEA_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL |
11198 | #define GCEA_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L |
11199 | #define GCEA_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L |
11200 | #define GCEA_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L |
11201 | #define GCEA_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L |
11202 | #define GCEA_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L |
11203 | #define GCEA_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L |
11204 | #define GCEA_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L |
11205 | //GCEA_SDP_CREDITS |
11206 | #define GCEA_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0 |
11207 | #define GCEA_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8 |
11208 | #define GCEA_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10 |
11209 | #define GCEA_SDP_CREDITS__PRB_REQ_CREDITS__SHIFT 0x18 |
11210 | #define GCEA_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL |
11211 | #define GCEA_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L |
11212 | #define GCEA_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x007F0000L |
11213 | #define GCEA_SDP_CREDITS__PRB_REQ_CREDITS_MASK 0x3F000000L |
11214 | //GCEA_SDP_TAG_RESERVE0 |
11215 | #define GCEA_SDP_TAG_RESERVE0__VC0__SHIFT 0x0 |
11216 | #define GCEA_SDP_TAG_RESERVE0__VC1__SHIFT 0x8 |
11217 | #define GCEA_SDP_TAG_RESERVE0__VC2__SHIFT 0x10 |
11218 | #define GCEA_SDP_TAG_RESERVE0__VC3__SHIFT 0x18 |
11219 | #define GCEA_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL |
11220 | #define GCEA_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L |
11221 | #define GCEA_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L |
11222 | #define GCEA_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L |
11223 | //GCEA_SDP_TAG_RESERVE1 |
11224 | #define GCEA_SDP_TAG_RESERVE1__VC4__SHIFT 0x0 |
11225 | #define GCEA_SDP_TAG_RESERVE1__VC5__SHIFT 0x8 |
11226 | #define GCEA_SDP_TAG_RESERVE1__VC6__SHIFT 0x10 |
11227 | #define GCEA_SDP_TAG_RESERVE1__VC7__SHIFT 0x18 |
11228 | #define GCEA_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL |
11229 | #define GCEA_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L |
11230 | #define GCEA_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L |
11231 | #define GCEA_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L |
11232 | //GCEA_SDP_VCC_RESERVE0 |
11233 | #define GCEA_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0 |
11234 | #define GCEA_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6 |
11235 | #define GCEA_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc |
11236 | #define GCEA_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12 |
11237 | #define GCEA_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18 |
11238 | #define GCEA_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL |
11239 | #define GCEA_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L |
11240 | #define GCEA_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L |
11241 | #define GCEA_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L |
11242 | #define GCEA_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L |
11243 | //GCEA_SDP_VCC_RESERVE1 |
11244 | #define GCEA_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0 |
11245 | #define GCEA_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6 |
11246 | #define GCEA_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc |
11247 | #define GCEA_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f |
11248 | #define GCEA_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL |
11249 | #define GCEA_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L |
11250 | #define GCEA_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L |
11251 | #define GCEA_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L |
11252 | //GCEA_SDP_VCD_RESERVE0 |
11253 | #define GCEA_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT 0x0 |
11254 | #define GCEA_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT 0x6 |
11255 | #define GCEA_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT 0xc |
11256 | #define GCEA_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT 0x12 |
11257 | #define GCEA_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT 0x18 |
11258 | #define GCEA_SDP_VCD_RESERVE0__VC0_CREDITS_MASK 0x0000003FL |
11259 | #define GCEA_SDP_VCD_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L |
11260 | #define GCEA_SDP_VCD_RESERVE0__VC2_CREDITS_MASK 0x0003F000L |
11261 | #define GCEA_SDP_VCD_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L |
11262 | #define GCEA_SDP_VCD_RESERVE0__VC4_CREDITS_MASK 0x3F000000L |
11263 | |
11264 | |
11265 | // addressBlock: gc_gceadec2 |
11266 | //GCEA_SDP_VCD_RESERVE1 |
11267 | #define GCEA_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT 0x0 |
11268 | #define GCEA_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT 0x6 |
11269 | #define GCEA_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT 0xc |
11270 | #define GCEA_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f |
11271 | #define GCEA_SDP_VCD_RESERVE1__VC5_CREDITS_MASK 0x0000003FL |
11272 | #define GCEA_SDP_VCD_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L |
11273 | #define GCEA_SDP_VCD_RESERVE1__VC7_CREDITS_MASK 0x0003F000L |
11274 | #define GCEA_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L |
11275 | //GCEA_SDP_REQ_CNTL |
11276 | #define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0 |
11277 | #define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1 |
11278 | #define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2 |
11279 | #define GCEA_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3 |
11280 | #define GCEA_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT 0x4 |
11281 | #define GCEA_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x5 |
11282 | #define GCEA_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ__SHIFT 0x6 |
11283 | #define GCEA_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE__SHIFT 0x8 |
11284 | #define GCEA_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC__SHIFT 0xa |
11285 | #define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L |
11286 | #define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L |
11287 | #define GCEA_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L |
11288 | #define GCEA_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L |
11289 | #define GCEA_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK 0x00000010L |
11290 | #define GCEA_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000020L |
11291 | #define GCEA_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ_MASK 0x000000C0L |
11292 | #define GCEA_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE_MASK 0x00000300L |
11293 | #define GCEA_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC_MASK 0x00000C00L |
11294 | //GCEA_MISC |
11295 | #define GCEA_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT 0x0 |
11296 | #define GCEA_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT 0x1 |
11297 | #define GCEA_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT 0x2 |
11298 | #define GCEA_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT 0x3 |
11299 | #define GCEA_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT 0x4 |
11300 | #define GCEA_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT 0x5 |
11301 | #define GCEA_MISC__EARLYWRRET_ENABLE_VC0__SHIFT 0x6 |
11302 | #define GCEA_MISC__EARLYWRRET_ENABLE_VC1__SHIFT 0x7 |
11303 | #define GCEA_MISC__EARLYWRRET_ENABLE_VC2__SHIFT 0x8 |
11304 | #define GCEA_MISC__EARLYWRRET_ENABLE_VC3__SHIFT 0x9 |
11305 | #define GCEA_MISC__EARLYWRRET_ENABLE_VC4__SHIFT 0xa |
11306 | #define GCEA_MISC__EARLYWRRET_ENABLE_VC5__SHIFT 0xb |
11307 | #define GCEA_MISC__EARLYWRRET_ENABLE_VC6__SHIFT 0xc |
11308 | #define GCEA_MISC__EARLYWRRET_ENABLE_VC7__SHIFT 0xd |
11309 | #define GCEA_MISC__EARLY_SDP_ORIGDATA__SHIFT 0xe |
11310 | #define GCEA_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0xf |
11311 | #define GCEA_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0x11 |
11312 | #define GCEA_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0x13 |
11313 | #define GCEA_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0x15 |
11314 | #define GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT 0x1a |
11315 | #define GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT 0x1b |
11316 | #define GCEA_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT 0x1c |
11317 | #define GCEA_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT 0x1d |
11318 | #define GCEA_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT 0x1e |
11319 | #define GCEA_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT 0x1f |
11320 | #define GCEA_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK 0x00000001L |
11321 | #define GCEA_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK 0x00000002L |
11322 | #define GCEA_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK 0x00000004L |
11323 | #define GCEA_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK 0x00000008L |
11324 | #define GCEA_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK 0x00000010L |
11325 | #define GCEA_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK 0x00000020L |
11326 | #define GCEA_MISC__EARLYWRRET_ENABLE_VC0_MASK 0x00000040L |
11327 | #define GCEA_MISC__EARLYWRRET_ENABLE_VC1_MASK 0x00000080L |
11328 | #define GCEA_MISC__EARLYWRRET_ENABLE_VC2_MASK 0x00000100L |
11329 | #define GCEA_MISC__EARLYWRRET_ENABLE_VC3_MASK 0x00000200L |
11330 | #define GCEA_MISC__EARLYWRRET_ENABLE_VC4_MASK 0x00000400L |
11331 | #define GCEA_MISC__EARLYWRRET_ENABLE_VC5_MASK 0x00000800L |
11332 | #define GCEA_MISC__EARLYWRRET_ENABLE_VC6_MASK 0x00001000L |
11333 | #define GCEA_MISC__EARLYWRRET_ENABLE_VC7_MASK 0x00002000L |
11334 | #define GCEA_MISC__EARLY_SDP_ORIGDATA_MASK 0x00004000L |
11335 | #define GCEA_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00018000L |
11336 | #define GCEA_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00060000L |
11337 | #define GCEA_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00180000L |
11338 | #define GCEA_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x03E00000L |
11339 | #define GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK 0x04000000L |
11340 | #define GCEA_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK 0x08000000L |
11341 | #define GCEA_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK 0x10000000L |
11342 | #define GCEA_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK 0x20000000L |
11343 | #define GCEA_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK 0x40000000L |
11344 | #define GCEA_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK 0x80000000L |
11345 | //GCEA_LATENCY_SAMPLING |
11346 | #define GCEA_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0 |
11347 | #define GCEA_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1 |
11348 | #define GCEA_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2 |
11349 | #define GCEA_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3 |
11350 | #define GCEA_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4 |
11351 | #define GCEA_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5 |
11352 | #define GCEA_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6 |
11353 | #define GCEA_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7 |
11354 | #define GCEA_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8 |
11355 | #define GCEA_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9 |
11356 | #define GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa |
11357 | #define GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb |
11358 | #define GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc |
11359 | #define GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd |
11360 | #define GCEA_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe |
11361 | #define GCEA_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16 |
11362 | #define GCEA_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L |
11363 | #define GCEA_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L |
11364 | #define GCEA_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L |
11365 | #define GCEA_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L |
11366 | #define GCEA_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L |
11367 | #define GCEA_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L |
11368 | #define GCEA_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L |
11369 | #define GCEA_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L |
11370 | #define GCEA_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L |
11371 | #define GCEA_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L |
11372 | #define GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L |
11373 | #define GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L |
11374 | #define GCEA_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L |
11375 | #define GCEA_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L |
11376 | #define GCEA_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L |
11377 | #define GCEA_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L |
11378 | //GCEA_MAM_CTRL2 |
11379 | #define GCEA_MAM_CTRL2__ARAM_FLUSH_DISABLE__SHIFT 0x0 |
11380 | #define GCEA_MAM_CTRL2__DBIT_PF_CLR_ONLY__SHIFT 0x1 |
11381 | #define GCEA_MAM_CTRL2__DBIT_PF_RD_ONLY__SHIFT 0x2 |
11382 | #define GCEA_MAM_CTRL2__DBIT_TRACK_SEGMENT__SHIFT 0x3 |
11383 | #define GCEA_MAM_CTRL2__ARAM_TRACK_SEGMENT__SHIFT 0x6 |
11384 | #define GCEA_MAM_CTRL2__ARAM_FB_TRACK_SIZE__SHIFT 0x9 |
11385 | #define GCEA_MAM_CTRL2__ARAM_RB_ENTRY_SIZE__SHIFT 0xf |
11386 | #define GCEA_MAM_CTRL2__ARAM_OVERRIDE_EA_STRAP__SHIFT 0x12 |
11387 | #define GCEA_MAM_CTRL2__ABIT_FLUSH_SPACE_OVERRIDE_ENABLE__SHIFT 0x13 |
11388 | #define GCEA_MAM_CTRL2__ABIT_FLUSH_SPACE_OVERRIDE_VALUE__SHIFT 0x14 |
11389 | #define GCEA_MAM_CTRL2__ARAM_REMOVE_TRACKER__SHIFT 0x15 |
11390 | #define GCEA_MAM_CTRL2__FORCE_DBIT_QUERY_DIRTY_ENABLE__SHIFT 0x16 |
11391 | #define GCEA_MAM_CTRL2__FORCE_DBIT_QUERY_DIRTY_VALUE__SHIFT 0x17 |
11392 | #define GCEA_MAM_CTRL2__RESERVED_FIELD__SHIFT 0x18 |
11393 | #define GCEA_MAM_CTRL2__ARAM_FLUSH_DISABLE_MASK 0x00000001L |
11394 | #define GCEA_MAM_CTRL2__DBIT_PF_CLR_ONLY_MASK 0x00000002L |
11395 | #define GCEA_MAM_CTRL2__DBIT_PF_RD_ONLY_MASK 0x00000004L |
11396 | #define GCEA_MAM_CTRL2__DBIT_TRACK_SEGMENT_MASK 0x00000038L |
11397 | #define GCEA_MAM_CTRL2__ARAM_TRACK_SEGMENT_MASK 0x000001C0L |
11398 | #define GCEA_MAM_CTRL2__ARAM_FB_TRACK_SIZE_MASK 0x00007E00L |
11399 | #define GCEA_MAM_CTRL2__ARAM_RB_ENTRY_SIZE_MASK 0x00038000L |
11400 | #define GCEA_MAM_CTRL2__ARAM_OVERRIDE_EA_STRAP_MASK 0x00040000L |
11401 | #define GCEA_MAM_CTRL2__ABIT_FLUSH_SPACE_OVERRIDE_ENABLE_MASK 0x00080000L |
11402 | #define GCEA_MAM_CTRL2__ABIT_FLUSH_SPACE_OVERRIDE_VALUE_MASK 0x00100000L |
11403 | #define GCEA_MAM_CTRL2__ARAM_REMOVE_TRACKER_MASK 0x00200000L |
11404 | #define GCEA_MAM_CTRL2__FORCE_DBIT_QUERY_DIRTY_ENABLE_MASK 0x00400000L |
11405 | #define GCEA_MAM_CTRL2__FORCE_DBIT_QUERY_DIRTY_VALUE_MASK 0x00800000L |
11406 | #define GCEA_MAM_CTRL2__RESERVED_FIELD_MASK 0xFF000000L |
11407 | //GCEA_MAM_CTRL |
11408 | #define GCEA_MAM_CTRL__MAM_DISABLE__SHIFT 0x0 |
11409 | #define GCEA_MAM_CTRL__DBIT_COALESCE_DISABLE__SHIFT 0x1 |
11410 | #define GCEA_MAM_CTRL__ARAM_COALESCE_DISABLE__SHIFT 0x2 |
11411 | #define GCEA_MAM_CTRL__ARAM_FLUSH_SNOOP_EN__SHIFT 0x3 |
11412 | #define GCEA_MAM_CTRL__SDMA_UPDT_ARAM__SHIFT 0x4 |
11413 | #define GCEA_MAM_CTRL__ARAM_FLUSH_NOALLOC__SHIFT 0x5 |
11414 | #define GCEA_MAM_CTRL__FLUSH_TRACKER__SHIFT 0x6 |
11415 | #define GCEA_MAM_CTRL__CLEAR_TRACKER__SHIFT 0x7 |
11416 | #define GCEA_MAM_CTRL__SDP_PRIORITY__SHIFT 0x8 |
11417 | #define GCEA_MAM_CTRL__FORCE_FLUSH_UPDT_TRACKER__SHIFT 0xc |
11418 | #define GCEA_MAM_CTRL__FORCE_FLUSH_GEN_INTERRUPT__SHIFT 0xd |
11419 | #define GCEA_MAM_CTRL__TIMER_FLUSH_UPDT_TRACKER__SHIFT 0xe |
11420 | #define GCEA_MAM_CTRL__TIMER_FLUSH_GEN_INTERRUPT__SHIFT 0xf |
11421 | #define GCEA_MAM_CTRL__RESERVED_FIELD__SHIFT 0x10 |
11422 | #define GCEA_MAM_CTRL__ARAM_NUM_RB_ENTRIES__SHIFT 0x17 |
11423 | #define GCEA_MAM_CTRL__ARAM_RB_ADDR_HI__SHIFT 0x1c |
11424 | #define GCEA_MAM_CTRL__MAM_DISABLE_MASK 0x00000001L |
11425 | #define GCEA_MAM_CTRL__DBIT_COALESCE_DISABLE_MASK 0x00000002L |
11426 | #define GCEA_MAM_CTRL__ARAM_COALESCE_DISABLE_MASK 0x00000004L |
11427 | #define GCEA_MAM_CTRL__ARAM_FLUSH_SNOOP_EN_MASK 0x00000008L |
11428 | #define GCEA_MAM_CTRL__SDMA_UPDT_ARAM_MASK 0x00000010L |
11429 | #define GCEA_MAM_CTRL__ARAM_FLUSH_NOALLOC_MASK 0x00000020L |
11430 | #define GCEA_MAM_CTRL__FLUSH_TRACKER_MASK 0x00000040L |
11431 | #define GCEA_MAM_CTRL__CLEAR_TRACKER_MASK 0x00000080L |
11432 | #define GCEA_MAM_CTRL__SDP_PRIORITY_MASK 0x00000F00L |
11433 | #define GCEA_MAM_CTRL__FORCE_FLUSH_UPDT_TRACKER_MASK 0x00001000L |
11434 | #define GCEA_MAM_CTRL__FORCE_FLUSH_GEN_INTERRUPT_MASK 0x00002000L |
11435 | #define GCEA_MAM_CTRL__TIMER_FLUSH_UPDT_TRACKER_MASK 0x00004000L |
11436 | #define GCEA_MAM_CTRL__TIMER_FLUSH_GEN_INTERRUPT_MASK 0x00008000L |
11437 | #define GCEA_MAM_CTRL__RESERVED_FIELD_MASK 0x007F0000L |
11438 | #define GCEA_MAM_CTRL__ARAM_NUM_RB_ENTRIES_MASK 0x0F800000L |
11439 | #define GCEA_MAM_CTRL__ARAM_RB_ADDR_HI_MASK 0xF0000000L |
11440 | //GCEA_EDC_CNT |
11441 | #define GCEA_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0 |
11442 | #define GCEA_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2 |
11443 | #define GCEA_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4 |
11444 | #define GCEA_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6 |
11445 | #define GCEA_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8 |
11446 | #define GCEA_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa |
11447 | #define GCEA_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc |
11448 | #define GCEA_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0xe |
11449 | #define GCEA_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10 |
11450 | #define GCEA_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x12 |
11451 | #define GCEA_EDC_CNT__IOWR_DATAMEM_SEC_COUNT__SHIFT 0x14 |
11452 | #define GCEA_EDC_CNT__IOWR_DATAMEM_DED_COUNT__SHIFT 0x16 |
11453 | #define GCEA_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x18 |
11454 | #define GCEA_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x1a |
11455 | #define GCEA_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT 0x1c |
11456 | #define GCEA_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1e |
11457 | #define GCEA_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L |
11458 | #define GCEA_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL |
11459 | #define GCEA_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L |
11460 | #define GCEA_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L |
11461 | #define GCEA_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L |
11462 | #define GCEA_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L |
11463 | #define GCEA_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L |
11464 | #define GCEA_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L |
11465 | #define GCEA_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L |
11466 | #define GCEA_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L |
11467 | #define GCEA_EDC_CNT__IOWR_DATAMEM_SEC_COUNT_MASK 0x00300000L |
11468 | #define GCEA_EDC_CNT__IOWR_DATAMEM_DED_COUNT_MASK 0x00C00000L |
11469 | #define GCEA_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x03000000L |
11470 | #define GCEA_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x0C000000L |
11471 | #define GCEA_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK 0x30000000L |
11472 | #define GCEA_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK 0xC0000000L |
11473 | //GCEA_EDC_CNT2 |
11474 | #define GCEA_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0 |
11475 | #define GCEA_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2 |
11476 | #define GCEA_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4 |
11477 | #define GCEA_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6 |
11478 | #define GCEA_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8 |
11479 | #define GCEA_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa |
11480 | #define GCEA_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc |
11481 | #define GCEA_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe |
11482 | #define GCEA_EDC_CNT2__MAM_D0MEM_SED_COUNT__SHIFT 0x10 |
11483 | #define GCEA_EDC_CNT2__MAM_D1MEM_SED_COUNT__SHIFT 0x12 |
11484 | #define GCEA_EDC_CNT2__MAM_D2MEM_SED_COUNT__SHIFT 0x14 |
11485 | #define GCEA_EDC_CNT2__MAM_D3MEM_SED_COUNT__SHIFT 0x16 |
11486 | #define GCEA_EDC_CNT2__MAM_D0MEM_DED_COUNT__SHIFT 0x18 |
11487 | #define GCEA_EDC_CNT2__MAM_D1MEM_DED_COUNT__SHIFT 0x1a |
11488 | #define GCEA_EDC_CNT2__MAM_D2MEM_DED_COUNT__SHIFT 0x1c |
11489 | #define GCEA_EDC_CNT2__MAM_D3MEM_DED_COUNT__SHIFT 0x1e |
11490 | #define GCEA_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L |
11491 | #define GCEA_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL |
11492 | #define GCEA_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L |
11493 | #define GCEA_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L |
11494 | #define GCEA_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L |
11495 | #define GCEA_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L |
11496 | #define GCEA_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L |
11497 | #define GCEA_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L |
11498 | #define GCEA_EDC_CNT2__MAM_D0MEM_SED_COUNT_MASK 0x00030000L |
11499 | #define GCEA_EDC_CNT2__MAM_D1MEM_SED_COUNT_MASK 0x000C0000L |
11500 | #define GCEA_EDC_CNT2__MAM_D2MEM_SED_COUNT_MASK 0x00300000L |
11501 | #define GCEA_EDC_CNT2__MAM_D3MEM_SED_COUNT_MASK 0x00C00000L |
11502 | #define GCEA_EDC_CNT2__MAM_D0MEM_DED_COUNT_MASK 0x03000000L |
11503 | #define GCEA_EDC_CNT2__MAM_D1MEM_DED_COUNT_MASK 0x0C000000L |
11504 | #define GCEA_EDC_CNT2__MAM_D2MEM_DED_COUNT_MASK 0x30000000L |
11505 | #define GCEA_EDC_CNT2__MAM_D3MEM_DED_COUNT_MASK 0xC0000000L |
11506 | //GCEA_DSM_CNTL |
11507 | #define GCEA_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 |
11508 | #define GCEA_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 |
11509 | #define GCEA_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 |
11510 | #define GCEA_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 |
11511 | #define GCEA_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 |
11512 | #define GCEA_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 |
11513 | #define GCEA_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 |
11514 | #define GCEA_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb |
11515 | #define GCEA_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0xc |
11516 | #define GCEA_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe |
11517 | #define GCEA_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0xf |
11518 | #define GCEA_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 |
11519 | #define GCEA_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 |
11520 | #define GCEA_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 |
11521 | #define GCEA_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x15 |
11522 | #define GCEA_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x17 |
11523 | #define GCEA_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L |
11524 | #define GCEA_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L |
11525 | #define GCEA_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L |
11526 | #define GCEA_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L |
11527 | #define GCEA_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L |
11528 | #define GCEA_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L |
11529 | #define GCEA_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L |
11530 | #define GCEA_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L |
11531 | #define GCEA_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L |
11532 | #define GCEA_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L |
11533 | #define GCEA_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L |
11534 | #define GCEA_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L |
11535 | #define GCEA_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L |
11536 | #define GCEA_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L |
11537 | #define GCEA_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00600000L |
11538 | #define GCEA_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00800000L |
11539 | //GCEA_DSM_CNTLA |
11540 | #define GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 |
11541 | #define GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 |
11542 | #define GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 |
11543 | #define GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 |
11544 | #define GCEA_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 |
11545 | #define GCEA_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 |
11546 | #define GCEA_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 |
11547 | #define GCEA_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb |
11548 | #define GCEA_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0xc |
11549 | #define GCEA_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe |
11550 | #define GCEA_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0xf |
11551 | #define GCEA_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 |
11552 | #define GCEA_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 |
11553 | #define GCEA_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 |
11554 | #define GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L |
11555 | #define GCEA_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L |
11556 | #define GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L |
11557 | #define GCEA_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L |
11558 | #define GCEA_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L |
11559 | #define GCEA_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L |
11560 | #define GCEA_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L |
11561 | #define GCEA_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L |
11562 | #define GCEA_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L |
11563 | #define GCEA_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L |
11564 | #define GCEA_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L |
11565 | #define GCEA_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L |
11566 | #define GCEA_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L |
11567 | #define GCEA_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L |
11568 | //GCEA_DSM_CNTLB |
11569 | #define GCEA_DSM_CNTLB__MAM_D0MEM_DSM_IRRITATOR_DATA__SHIFT 0x0 |
11570 | #define GCEA_DSM_CNTLB__MAM_D0MEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 |
11571 | #define GCEA_DSM_CNTLB__MAM_D1MEM_DSM_IRRITATOR_DATA__SHIFT 0x3 |
11572 | #define GCEA_DSM_CNTLB__MAM_D1MEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 |
11573 | #define GCEA_DSM_CNTLB__MAM_D2MEM_DSM_IRRITATOR_DATA__SHIFT 0x6 |
11574 | #define GCEA_DSM_CNTLB__MAM_D2MEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 |
11575 | #define GCEA_DSM_CNTLB__MAM_D3MEM_DSM_IRRITATOR_DATA__SHIFT 0x9 |
11576 | #define GCEA_DSM_CNTLB__MAM_D3MEM_ENABLE_SINGLE_WRITE__SHIFT 0xb |
11577 | #define GCEA_DSM_CNTLB__MAM_A0MEM_DSM_IRRITATOR_DATA__SHIFT 0xc |
11578 | #define GCEA_DSM_CNTLB__MAM_A0MEM_ENABLE_SINGLE_WRITE__SHIFT 0xe |
11579 | #define GCEA_DSM_CNTLB__MAM_A1MEM_DSM_IRRITATOR_DATA__SHIFT 0xf |
11580 | #define GCEA_DSM_CNTLB__MAM_A1MEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 |
11581 | #define GCEA_DSM_CNTLB__MAM_A2MEM_DSM_IRRITATOR_DATA__SHIFT 0x12 |
11582 | #define GCEA_DSM_CNTLB__MAM_A2MEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 |
11583 | #define GCEA_DSM_CNTLB__MAM_A3MEM_DSM_IRRITATOR_DATA__SHIFT 0x15 |
11584 | #define GCEA_DSM_CNTLB__MAM_A3MEM_ENABLE_SINGLE_WRITE__SHIFT 0x17 |
11585 | #define GCEA_DSM_CNTLB__MAM_AFMEM_DSM_IRRITATOR_DATA__SHIFT 0x18 |
11586 | #define GCEA_DSM_CNTLB__MAM_AFMEM_ENABLE_SINGLE_WRITE__SHIFT 0x1a |
11587 | #define GCEA_DSM_CNTLB__MAM_D0MEM_DSM_IRRITATOR_DATA_MASK 0x00000003L |
11588 | #define GCEA_DSM_CNTLB__MAM_D0MEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L |
11589 | #define GCEA_DSM_CNTLB__MAM_D1MEM_DSM_IRRITATOR_DATA_MASK 0x00000018L |
11590 | #define GCEA_DSM_CNTLB__MAM_D1MEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L |
11591 | #define GCEA_DSM_CNTLB__MAM_D2MEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L |
11592 | #define GCEA_DSM_CNTLB__MAM_D2MEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L |
11593 | #define GCEA_DSM_CNTLB__MAM_D3MEM_DSM_IRRITATOR_DATA_MASK 0x00000600L |
11594 | #define GCEA_DSM_CNTLB__MAM_D3MEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L |
11595 | #define GCEA_DSM_CNTLB__MAM_A0MEM_DSM_IRRITATOR_DATA_MASK 0x00003000L |
11596 | #define GCEA_DSM_CNTLB__MAM_A0MEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L |
11597 | #define GCEA_DSM_CNTLB__MAM_A1MEM_DSM_IRRITATOR_DATA_MASK 0x00018000L |
11598 | #define GCEA_DSM_CNTLB__MAM_A1MEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L |
11599 | #define GCEA_DSM_CNTLB__MAM_A2MEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L |
11600 | #define GCEA_DSM_CNTLB__MAM_A2MEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L |
11601 | #define GCEA_DSM_CNTLB__MAM_A3MEM_DSM_IRRITATOR_DATA_MASK 0x00600000L |
11602 | #define GCEA_DSM_CNTLB__MAM_A3MEM_ENABLE_SINGLE_WRITE_MASK 0x00800000L |
11603 | #define GCEA_DSM_CNTLB__MAM_AFMEM_DSM_IRRITATOR_DATA_MASK 0x03000000L |
11604 | #define GCEA_DSM_CNTLB__MAM_AFMEM_ENABLE_SINGLE_WRITE_MASK 0x04000000L |
11605 | //GCEA_DSM_CNTL2 |
11606 | #define GCEA_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 |
11607 | #define GCEA_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x2 |
11608 | #define GCEA_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 |
11609 | #define GCEA_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x5 |
11610 | #define GCEA_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 |
11611 | #define GCEA_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x8 |
11612 | #define GCEA_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 |
11613 | #define GCEA_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xb |
11614 | #define GCEA_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0xc |
11615 | #define GCEA_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xe |
11616 | #define GCEA_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0xf |
11617 | #define GCEA_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x11 |
11618 | #define GCEA_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 |
11619 | #define GCEA_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x14 |
11620 | #define GCEA_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x15 |
11621 | #define GCEA_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x17 |
11622 | #define GCEA_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a |
11623 | #define GCEA_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L |
11624 | #define GCEA_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000004L |
11625 | #define GCEA_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L |
11626 | #define GCEA_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000020L |
11627 | #define GCEA_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L |
11628 | #define GCEA_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00000100L |
11629 | #define GCEA_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L |
11630 | #define GCEA_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00000800L |
11631 | #define GCEA_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L |
11632 | #define GCEA_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00004000L |
11633 | #define GCEA_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L |
11634 | #define GCEA_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00020000L |
11635 | #define GCEA_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L |
11636 | #define GCEA_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00100000L |
11637 | #define GCEA_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00600000L |
11638 | #define GCEA_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00800000L |
11639 | #define GCEA_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L |
11640 | //GCEA_DSM_CNTL2A |
11641 | #define GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 |
11642 | #define GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x2 |
11643 | #define GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 |
11644 | #define GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x5 |
11645 | #define GCEA_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 |
11646 | #define GCEA_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x8 |
11647 | #define GCEA_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 |
11648 | #define GCEA_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0xb |
11649 | #define GCEA_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0xc |
11650 | #define GCEA_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0xe |
11651 | #define GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0xf |
11652 | #define GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x11 |
11653 | #define GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 |
11654 | #define GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x14 |
11655 | #define GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L |
11656 | #define GCEA_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000004L |
11657 | #define GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L |
11658 | #define GCEA_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000020L |
11659 | #define GCEA_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L |
11660 | #define GCEA_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000100L |
11661 | #define GCEA_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L |
11662 | #define GCEA_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000800L |
11663 | #define GCEA_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L |
11664 | #define GCEA_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00004000L |
11665 | #define GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L |
11666 | #define GCEA_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00020000L |
11667 | #define GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L |
11668 | #define GCEA_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00100000L |
11669 | //GCEA_DSM_CNTL2B |
11670 | #define GCEA_DSM_CNTL2B__MAM_D0MEM_ENABLE_ERROR_INJECT__SHIFT 0x0 |
11671 | #define GCEA_DSM_CNTL2B__MAM_D0MEM_SELECT_INJECT_DELAY__SHIFT 0x2 |
11672 | #define GCEA_DSM_CNTL2B__MAM_D1MEM_ENABLE_ERROR_INJECT__SHIFT 0x3 |
11673 | #define GCEA_DSM_CNTL2B__MAM_D1MEM_SELECT_INJECT_DELAY__SHIFT 0x5 |
11674 | #define GCEA_DSM_CNTL2B__MAM_D2MEM_ENABLE_ERROR_INJECT__SHIFT 0x6 |
11675 | #define GCEA_DSM_CNTL2B__MAM_D2MEM_SELECT_INJECT_DELAY__SHIFT 0x8 |
11676 | #define GCEA_DSM_CNTL2B__MAM_D3MEM_ENABLE_ERROR_INJECT__SHIFT 0x9 |
11677 | #define GCEA_DSM_CNTL2B__MAM_D3MEM_SELECT_INJECT_DELAY__SHIFT 0xb |
11678 | #define GCEA_DSM_CNTL2B__MAM_A0MEM_ENABLE_ERROR_INJECT__SHIFT 0xc |
11679 | #define GCEA_DSM_CNTL2B__MAM_A0MEM_SELECT_INJECT_DELAY__SHIFT 0xe |
11680 | #define GCEA_DSM_CNTL2B__MAM_A1MEM_ENABLE_ERROR_INJECT__SHIFT 0xf |
11681 | #define GCEA_DSM_CNTL2B__MAM_A1MEM_SELECT_INJECT_DELAY__SHIFT 0x11 |
11682 | #define GCEA_DSM_CNTL2B__MAM_A2MEM_ENABLE_ERROR_INJECT__SHIFT 0x12 |
11683 | #define GCEA_DSM_CNTL2B__MAM_A2MEM_SELECT_INJECT_DELAY__SHIFT 0x14 |
11684 | #define GCEA_DSM_CNTL2B__MAM_A3MEM_ENABLE_ERROR_INJECT__SHIFT 0x15 |
11685 | #define GCEA_DSM_CNTL2B__MAM_A3MEM_SELECT_INJECT_DELAY__SHIFT 0x17 |
11686 | #define GCEA_DSM_CNTL2B__MAM_AFMEM_ENABLE_ERROR_INJECT__SHIFT 0x18 |
11687 | #define GCEA_DSM_CNTL2B__MAM_AFMEM_SELECT_INJECT_DELAY__SHIFT 0x1a |
11688 | #define GCEA_DSM_CNTL2B__MAM_D0MEM_ENABLE_ERROR_INJECT_MASK 0x00000003L |
11689 | #define GCEA_DSM_CNTL2B__MAM_D0MEM_SELECT_INJECT_DELAY_MASK 0x00000004L |
11690 | #define GCEA_DSM_CNTL2B__MAM_D1MEM_ENABLE_ERROR_INJECT_MASK 0x00000018L |
11691 | #define GCEA_DSM_CNTL2B__MAM_D1MEM_SELECT_INJECT_DELAY_MASK 0x00000020L |
11692 | #define GCEA_DSM_CNTL2B__MAM_D2MEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L |
11693 | #define GCEA_DSM_CNTL2B__MAM_D2MEM_SELECT_INJECT_DELAY_MASK 0x00000100L |
11694 | #define GCEA_DSM_CNTL2B__MAM_D3MEM_ENABLE_ERROR_INJECT_MASK 0x00000600L |
11695 | #define GCEA_DSM_CNTL2B__MAM_D3MEM_SELECT_INJECT_DELAY_MASK 0x00000800L |
11696 | #define GCEA_DSM_CNTL2B__MAM_A0MEM_ENABLE_ERROR_INJECT_MASK 0x00003000L |
11697 | #define GCEA_DSM_CNTL2B__MAM_A0MEM_SELECT_INJECT_DELAY_MASK 0x00004000L |
11698 | #define GCEA_DSM_CNTL2B__MAM_A1MEM_ENABLE_ERROR_INJECT_MASK 0x00018000L |
11699 | #define GCEA_DSM_CNTL2B__MAM_A1MEM_SELECT_INJECT_DELAY_MASK 0x00020000L |
11700 | #define GCEA_DSM_CNTL2B__MAM_A2MEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L |
11701 | #define GCEA_DSM_CNTL2B__MAM_A2MEM_SELECT_INJECT_DELAY_MASK 0x00100000L |
11702 | #define GCEA_DSM_CNTL2B__MAM_A3MEM_ENABLE_ERROR_INJECT_MASK 0x00600000L |
11703 | #define GCEA_DSM_CNTL2B__MAM_A3MEM_SELECT_INJECT_DELAY_MASK 0x00800000L |
11704 | #define GCEA_DSM_CNTL2B__MAM_AFMEM_ENABLE_ERROR_INJECT_MASK 0x03000000L |
11705 | #define GCEA_DSM_CNTL2B__MAM_AFMEM_SELECT_INJECT_DELAY_MASK 0x04000000L |
11706 | //GCEA_GL2C_XBR_CREDITS |
11707 | #define GCEA_GL2C_XBR_CREDITS__DRAM_RD_LIMIT__SHIFT 0x0 |
11708 | #define GCEA_GL2C_XBR_CREDITS__DRAM_RD_RESERVE__SHIFT 0x6 |
11709 | #define GCEA_GL2C_XBR_CREDITS__IO_RD_LIMIT__SHIFT 0x8 |
11710 | #define GCEA_GL2C_XBR_CREDITS__IO_RD_RESERVE__SHIFT 0xe |
11711 | #define GCEA_GL2C_XBR_CREDITS__DRAM_WR_LIMIT__SHIFT 0x10 |
11712 | #define GCEA_GL2C_XBR_CREDITS__DRAM_WR_RESERVE__SHIFT 0x16 |
11713 | #define GCEA_GL2C_XBR_CREDITS__IO_WR_LIMIT__SHIFT 0x18 |
11714 | #define GCEA_GL2C_XBR_CREDITS__IO_WR_RESERVE__SHIFT 0x1e |
11715 | #define GCEA_GL2C_XBR_CREDITS__DRAM_RD_LIMIT_MASK 0x0000003FL |
11716 | #define GCEA_GL2C_XBR_CREDITS__DRAM_RD_RESERVE_MASK 0x000000C0L |
11717 | #define GCEA_GL2C_XBR_CREDITS__IO_RD_LIMIT_MASK 0x00003F00L |
11718 | #define GCEA_GL2C_XBR_CREDITS__IO_RD_RESERVE_MASK 0x0000C000L |
11719 | #define GCEA_GL2C_XBR_CREDITS__DRAM_WR_LIMIT_MASK 0x003F0000L |
11720 | #define GCEA_GL2C_XBR_CREDITS__DRAM_WR_RESERVE_MASK 0x00C00000L |
11721 | #define GCEA_GL2C_XBR_CREDITS__IO_WR_LIMIT_MASK 0x3F000000L |
11722 | #define GCEA_GL2C_XBR_CREDITS__IO_WR_RESERVE_MASK 0xC0000000L |
11723 | //GCEA_GL2C_XBR_MAXBURST |
11724 | #define GCEA_GL2C_XBR_MAXBURST__DRAM_RD__SHIFT 0x0 |
11725 | #define GCEA_GL2C_XBR_MAXBURST__IO_RD__SHIFT 0x4 |
11726 | #define GCEA_GL2C_XBR_MAXBURST__DRAM_WR__SHIFT 0x8 |
11727 | #define GCEA_GL2C_XBR_MAXBURST__IO_WR__SHIFT 0xc |
11728 | #define GCEA_GL2C_XBR_MAXBURST__DRAM_RD_COMB_FLUSH_TIMER__SHIFT 0x10 |
11729 | #define GCEA_GL2C_XBR_MAXBURST__DRAM_RD_COMB_SAME64B_ONLY__SHIFT 0x13 |
11730 | #define GCEA_GL2C_XBR_MAXBURST__DRAM_WR_COMB_FLUSH_TIMER__SHIFT 0x14 |
11731 | #define GCEA_GL2C_XBR_MAXBURST__DRAM_WR_COMB_SAME64B_ONLY__SHIFT 0x17 |
11732 | #define GCEA_GL2C_XBR_MAXBURST__DRAM_RD_MASK 0x0000000FL |
11733 | #define GCEA_GL2C_XBR_MAXBURST__IO_RD_MASK 0x000000F0L |
11734 | #define GCEA_GL2C_XBR_MAXBURST__DRAM_WR_MASK 0x00000F00L |
11735 | #define GCEA_GL2C_XBR_MAXBURST__IO_WR_MASK 0x0000F000L |
11736 | #define GCEA_GL2C_XBR_MAXBURST__DRAM_RD_COMB_FLUSH_TIMER_MASK 0x00070000L |
11737 | #define GCEA_GL2C_XBR_MAXBURST__DRAM_RD_COMB_SAME64B_ONLY_MASK 0x00080000L |
11738 | #define GCEA_GL2C_XBR_MAXBURST__DRAM_WR_COMB_FLUSH_TIMER_MASK 0x00700000L |
11739 | #define GCEA_GL2C_XBR_MAXBURST__DRAM_WR_COMB_SAME64B_ONLY_MASK 0x00800000L |
11740 | //GCEA_PROBE_CNTL |
11741 | #define GCEA_PROBE_CNTL__REQ2RSP_DELAY__SHIFT 0x0 |
11742 | #define GCEA_PROBE_CNTL__PRB_FILTER_DISABLE__SHIFT 0x5 |
11743 | #define GCEA_PROBE_CNTL__REQ2RSP_DELAY_MASK 0x0000001FL |
11744 | #define GCEA_PROBE_CNTL__PRB_FILTER_DISABLE_MASK 0x00000020L |
11745 | //GCEA_PROBE_MAP |
11746 | #define GCEA_PROBE_MAP__CHADDR0_TO_RIGHTGL2C__SHIFT 0x0 |
11747 | #define GCEA_PROBE_MAP__CHADDR1_TO_RIGHTGL2C__SHIFT 0x1 |
11748 | #define GCEA_PROBE_MAP__CHADDR2_TO_RIGHTGL2C__SHIFT 0x2 |
11749 | #define GCEA_PROBE_MAP__CHADDR3_TO_RIGHTGL2C__SHIFT 0x3 |
11750 | #define GCEA_PROBE_MAP__CHADDR4_TO_RIGHTGL2C__SHIFT 0x4 |
11751 | #define GCEA_PROBE_MAP__CHADDR5_TO_RIGHTGL2C__SHIFT 0x5 |
11752 | #define GCEA_PROBE_MAP__CHADDR6_TO_RIGHTGL2C__SHIFT 0x6 |
11753 | #define GCEA_PROBE_MAP__CHADDR7_TO_RIGHTGL2C__SHIFT 0x7 |
11754 | #define GCEA_PROBE_MAP__CHADDR8_TO_RIGHTGL2C__SHIFT 0x8 |
11755 | #define GCEA_PROBE_MAP__CHADDR9_TO_RIGHTGL2C__SHIFT 0x9 |
11756 | #define GCEA_PROBE_MAP__CHADDR10_TO_RIGHTGL2C__SHIFT 0xa |
11757 | #define GCEA_PROBE_MAP__CHADDR11_TO_RIGHTGL2C__SHIFT 0xb |
11758 | #define GCEA_PROBE_MAP__CHADDR12_TO_RIGHTGL2C__SHIFT 0xc |
11759 | #define GCEA_PROBE_MAP__CHADDR13_TO_RIGHTGL2C__SHIFT 0xd |
11760 | #define GCEA_PROBE_MAP__CHADDR14_TO_RIGHTGL2C__SHIFT 0xe |
11761 | #define GCEA_PROBE_MAP__CHADDR15_TO_RIGHTGL2C__SHIFT 0xf |
11762 | #define GCEA_PROBE_MAP__INTLV_SIZE__SHIFT 0x10 |
11763 | #define GCEA_PROBE_MAP__CHADDR0_TO_RIGHTGL2C_MASK 0x00000001L |
11764 | #define GCEA_PROBE_MAP__CHADDR1_TO_RIGHTGL2C_MASK 0x00000002L |
11765 | #define GCEA_PROBE_MAP__CHADDR2_TO_RIGHTGL2C_MASK 0x00000004L |
11766 | #define GCEA_PROBE_MAP__CHADDR3_TO_RIGHTGL2C_MASK 0x00000008L |
11767 | #define GCEA_PROBE_MAP__CHADDR4_TO_RIGHTGL2C_MASK 0x00000010L |
11768 | #define GCEA_PROBE_MAP__CHADDR5_TO_RIGHTGL2C_MASK 0x00000020L |
11769 | #define GCEA_PROBE_MAP__CHADDR6_TO_RIGHTGL2C_MASK 0x00000040L |
11770 | #define GCEA_PROBE_MAP__CHADDR7_TO_RIGHTGL2C_MASK 0x00000080L |
11771 | #define GCEA_PROBE_MAP__CHADDR8_TO_RIGHTGL2C_MASK 0x00000100L |
11772 | #define GCEA_PROBE_MAP__CHADDR9_TO_RIGHTGL2C_MASK 0x00000200L |
11773 | #define GCEA_PROBE_MAP__CHADDR10_TO_RIGHTGL2C_MASK 0x00000400L |
11774 | #define GCEA_PROBE_MAP__CHADDR11_TO_RIGHTGL2C_MASK 0x00000800L |
11775 | #define GCEA_PROBE_MAP__CHADDR12_TO_RIGHTGL2C_MASK 0x00001000L |
11776 | #define GCEA_PROBE_MAP__CHADDR13_TO_RIGHTGL2C_MASK 0x00002000L |
11777 | #define GCEA_PROBE_MAP__CHADDR14_TO_RIGHTGL2C_MASK 0x00004000L |
11778 | #define GCEA_PROBE_MAP__CHADDR15_TO_RIGHTGL2C_MASK 0x00008000L |
11779 | #define GCEA_PROBE_MAP__INTLV_SIZE_MASK 0x00030000L |
11780 | //GCEA_ERR_STATUS |
11781 | #define GCEA_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0 |
11782 | #define GCEA_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4 |
11783 | #define GCEA_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8 |
11784 | #define GCEA_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa |
11785 | #define GCEA_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xb |
11786 | #define GCEA_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xc |
11787 | #define GCEA_ERR_STATUS__FUE_FLAG__SHIFT 0xd |
11788 | #define GCEA_ERR_STATUS__IGNORE_RDRSP_FED__SHIFT 0xe |
11789 | #define GCEA_ERR_STATUS__INTERRUPT_ON_FATAL__SHIFT 0xf |
11790 | #define GCEA_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL__SHIFT 0x10 |
11791 | #define GCEA_ERR_STATUS__LEVEL_INTERRUPT__SHIFT 0x11 |
11792 | #define GCEA_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL |
11793 | #define GCEA_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L |
11794 | #define GCEA_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L |
11795 | #define GCEA_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L |
11796 | #define GCEA_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000800L |
11797 | #define GCEA_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00001000L |
11798 | #define GCEA_ERR_STATUS__FUE_FLAG_MASK 0x00002000L |
11799 | #define GCEA_ERR_STATUS__IGNORE_RDRSP_FED_MASK 0x00004000L |
11800 | #define GCEA_ERR_STATUS__INTERRUPT_ON_FATAL_MASK 0x00008000L |
11801 | #define GCEA_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL_MASK 0x00010000L |
11802 | #define GCEA_ERR_STATUS__LEVEL_INTERRUPT_MASK 0x00020000L |
11803 | //GCEA_MISC2 |
11804 | #define GCEA_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT 0x0 |
11805 | #define GCEA_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT 0x1 |
11806 | #define GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT 0x2 |
11807 | #define GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT 0x7 |
11808 | #define GCEA_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT 0xc |
11809 | #define GCEA_MISC2__BLOCK_REQUESTS__SHIFT 0xd |
11810 | #define GCEA_MISC2__REQUESTS_BLOCKED__SHIFT 0xe |
11811 | #define GCEA_MISC2__FGCLKEN_OVERRIDE__SHIFT 0xf |
11812 | #define GCEA_MISC2__LINKMGR_CRBUSY_MASK__SHIFT 0x10 |
11813 | #define GCEA_MISC2__RDRET_FED_MASK__SHIFT 0x11 |
11814 | #define GCEA_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK 0x00000001L |
11815 | #define GCEA_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK 0x00000002L |
11816 | #define GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK 0x0000007CL |
11817 | #define GCEA_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK 0x00000F80L |
11818 | #define GCEA_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK 0x00001000L |
11819 | #define GCEA_MISC2__BLOCK_REQUESTS_MASK 0x00002000L |
11820 | #define GCEA_MISC2__REQUESTS_BLOCKED_MASK 0x00004000L |
11821 | #define GCEA_MISC2__FGCLKEN_OVERRIDE_MASK 0x00008000L |
11822 | #define GCEA_MISC2__LINKMGR_CRBUSY_MASK_MASK 0x00010000L |
11823 | #define GCEA_MISC2__RDRET_FED_MASK_MASK 0x00020000L |
11824 | |
11825 | |
11826 | // addressBlock: gc_gceadec3 |
11827 | //GCEA_SDP_BACKDOOR_CMDCREDITS0 |
11828 | #define GCEA_SDP_BACKDOOR_CMDCREDITS0__VC0_CREDITS_RECEIVED__SHIFT 0x0 |
11829 | #define GCEA_SDP_BACKDOOR_CMDCREDITS0__VC1_CREDITS_RECEIVED__SHIFT 0x7 |
11830 | #define GCEA_SDP_BACKDOOR_CMDCREDITS0__VC2_CREDITS_RECEIVED__SHIFT 0xe |
11831 | #define GCEA_SDP_BACKDOOR_CMDCREDITS0__VC3_CREDITS_RECEIVED__SHIFT 0x15 |
11832 | #define GCEA_SDP_BACKDOOR_CMDCREDITS0__VC4_CREDITS_RECEIVED__SHIFT 0x1c |
11833 | #define GCEA_SDP_BACKDOOR_CMDCREDITS0__VC0_CREDITS_RECEIVED_MASK 0x0000007FL |
11834 | #define GCEA_SDP_BACKDOOR_CMDCREDITS0__VC1_CREDITS_RECEIVED_MASK 0x00003F80L |
11835 | #define GCEA_SDP_BACKDOOR_CMDCREDITS0__VC2_CREDITS_RECEIVED_MASK 0x001FC000L |
11836 | #define GCEA_SDP_BACKDOOR_CMDCREDITS0__VC3_CREDITS_RECEIVED_MASK 0x0FE00000L |
11837 | #define GCEA_SDP_BACKDOOR_CMDCREDITS0__VC4_CREDITS_RECEIVED_MASK 0xF0000000L |
11838 | //GCEA_SDP_BACKDOOR_CMDCREDITS1 |
11839 | #define GCEA_SDP_BACKDOOR_CMDCREDITS1__VC4_CREDITS_RECEIVED__SHIFT 0x0 |
11840 | #define GCEA_SDP_BACKDOOR_CMDCREDITS1__VC5_CREDITS_RECEIVED__SHIFT 0x3 |
11841 | #define GCEA_SDP_BACKDOOR_CMDCREDITS1__VC6_CREDITS_RECEIVED__SHIFT 0xa |
11842 | #define GCEA_SDP_BACKDOOR_CMDCREDITS1__VC7_CREDITS_RECEIVED__SHIFT 0x11 |
11843 | #define GCEA_SDP_BACKDOOR_CMDCREDITS1__POOL_CREDITS_RECEIVED__SHIFT 0x18 |
11844 | #define GCEA_SDP_BACKDOOR_CMDCREDITS1__VC4_CREDITS_RECEIVED_MASK 0x00000007L |
11845 | #define GCEA_SDP_BACKDOOR_CMDCREDITS1__VC5_CREDITS_RECEIVED_MASK 0x000003F8L |
11846 | #define GCEA_SDP_BACKDOOR_CMDCREDITS1__VC6_CREDITS_RECEIVED_MASK 0x0001FC00L |
11847 | #define GCEA_SDP_BACKDOOR_CMDCREDITS1__VC7_CREDITS_RECEIVED_MASK 0x00FE0000L |
11848 | #define GCEA_SDP_BACKDOOR_CMDCREDITS1__POOL_CREDITS_RECEIVED_MASK 0x7F000000L |
11849 | //GCEA_SDP_BACKDOOR_DATACREDITS0 |
11850 | #define GCEA_SDP_BACKDOOR_DATACREDITS0__VC0_CREDITS_RECEIVED__SHIFT 0x0 |
11851 | #define GCEA_SDP_BACKDOOR_DATACREDITS0__VC1_CREDITS_RECEIVED__SHIFT 0x7 |
11852 | #define GCEA_SDP_BACKDOOR_DATACREDITS0__VC2_CREDITS_RECEIVED__SHIFT 0xe |
11853 | #define GCEA_SDP_BACKDOOR_DATACREDITS0__VC3_CREDITS_RECEIVED__SHIFT 0x15 |
11854 | #define GCEA_SDP_BACKDOOR_DATACREDITS0__VC4_CREDITS_RECEIVED__SHIFT 0x1c |
11855 | #define GCEA_SDP_BACKDOOR_DATACREDITS0__VC0_CREDITS_RECEIVED_MASK 0x0000007FL |
11856 | #define GCEA_SDP_BACKDOOR_DATACREDITS0__VC1_CREDITS_RECEIVED_MASK 0x00003F80L |
11857 | #define GCEA_SDP_BACKDOOR_DATACREDITS0__VC2_CREDITS_RECEIVED_MASK 0x001FC000L |
11858 | #define GCEA_SDP_BACKDOOR_DATACREDITS0__VC3_CREDITS_RECEIVED_MASK 0x0FE00000L |
11859 | #define GCEA_SDP_BACKDOOR_DATACREDITS0__VC4_CREDITS_RECEIVED_MASK 0xF0000000L |
11860 | //GCEA_SDP_BACKDOOR_DATACREDITS1 |
11861 | #define GCEA_SDP_BACKDOOR_DATACREDITS1__VC4_CREDITS_RECEIVED__SHIFT 0x0 |
11862 | #define GCEA_SDP_BACKDOOR_DATACREDITS1__VC5_CREDITS_RECEIVED__SHIFT 0x3 |
11863 | #define GCEA_SDP_BACKDOOR_DATACREDITS1__VC6_CREDITS_RECEIVED__SHIFT 0xa |
11864 | #define GCEA_SDP_BACKDOOR_DATACREDITS1__VC7_CREDITS_RECEIVED__SHIFT 0x11 |
11865 | #define GCEA_SDP_BACKDOOR_DATACREDITS1__POOL_CREDITS_RECEIVED__SHIFT 0x18 |
11866 | #define GCEA_SDP_BACKDOOR_DATACREDITS1__VC4_CREDITS_RECEIVED_MASK 0x00000007L |
11867 | #define GCEA_SDP_BACKDOOR_DATACREDITS1__VC5_CREDITS_RECEIVED_MASK 0x000003F8L |
11868 | #define GCEA_SDP_BACKDOOR_DATACREDITS1__VC6_CREDITS_RECEIVED_MASK 0x0001FC00L |
11869 | #define GCEA_SDP_BACKDOOR_DATACREDITS1__VC7_CREDITS_RECEIVED_MASK 0x00FE0000L |
11870 | #define GCEA_SDP_BACKDOOR_DATACREDITS1__POOL_CREDITS_RECEIVED_MASK 0x7F000000L |
11871 | //GCEA_SDP_BACKDOOR_MISCCREDITS |
11872 | #define GCEA_SDP_BACKDOOR_MISCCREDITS__PRB_RSP_CREDITS_RECEIVED__SHIFT 0x0 |
11873 | #define GCEA_SDP_BACKDOOR_MISCCREDITS__PRB_RSP_CREDITS_RECEIVED_MASK 0x0000007FL |
11874 | //GCEA_RRET_MEM_RESERVE |
11875 | #define GCEA_RRET_MEM_RESERVE__VC0__SHIFT 0x0 |
11876 | #define GCEA_RRET_MEM_RESERVE__VC1__SHIFT 0x4 |
11877 | #define GCEA_RRET_MEM_RESERVE__VC2__SHIFT 0x8 |
11878 | #define GCEA_RRET_MEM_RESERVE__VC3__SHIFT 0xc |
11879 | #define GCEA_RRET_MEM_RESERVE__VC4__SHIFT 0x10 |
11880 | #define GCEA_RRET_MEM_RESERVE__VC5__SHIFT 0x14 |
11881 | #define GCEA_RRET_MEM_RESERVE__VC6__SHIFT 0x18 |
11882 | #define GCEA_RRET_MEM_RESERVE__VC7__SHIFT 0x1c |
11883 | #define GCEA_RRET_MEM_RESERVE__VC0_MASK 0x0000000FL |
11884 | #define GCEA_RRET_MEM_RESERVE__VC1_MASK 0x000000F0L |
11885 | #define GCEA_RRET_MEM_RESERVE__VC2_MASK 0x00000F00L |
11886 | #define GCEA_RRET_MEM_RESERVE__VC3_MASK 0x0000F000L |
11887 | #define GCEA_RRET_MEM_RESERVE__VC4_MASK 0x000F0000L |
11888 | #define GCEA_RRET_MEM_RESERVE__VC5_MASK 0x00F00000L |
11889 | #define GCEA_RRET_MEM_RESERVE__VC6_MASK 0x0F000000L |
11890 | #define GCEA_RRET_MEM_RESERVE__VC7_MASK 0xF0000000L |
11891 | //GCEA_EDC_CNT3 |
11892 | #define GCEA_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT__SHIFT 0x0 |
11893 | #define GCEA_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT__SHIFT 0x2 |
11894 | #define GCEA_EDC_CNT3__IORD_CMDMEM_DED_COUNT__SHIFT 0x4 |
11895 | #define GCEA_EDC_CNT3__IOWR_CMDMEM_DED_COUNT__SHIFT 0x6 |
11896 | #define GCEA_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT__SHIFT 0x8 |
11897 | #define GCEA_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT__SHIFT 0xa |
11898 | #define GCEA_EDC_CNT3__MAM_A0MEM_SEC_COUNT__SHIFT 0xc |
11899 | #define GCEA_EDC_CNT3__MAM_A0MEM_DED_COUNT__SHIFT 0xe |
11900 | #define GCEA_EDC_CNT3__MAM_A1MEM_SEC_COUNT__SHIFT 0x10 |
11901 | #define GCEA_EDC_CNT3__MAM_A1MEM_DED_COUNT__SHIFT 0x12 |
11902 | #define GCEA_EDC_CNT3__MAM_A2MEM_SEC_COUNT__SHIFT 0x14 |
11903 | #define GCEA_EDC_CNT3__MAM_A2MEM_DED_COUNT__SHIFT 0x16 |
11904 | #define GCEA_EDC_CNT3__MAM_A3MEM_SEC_COUNT__SHIFT 0x18 |
11905 | #define GCEA_EDC_CNT3__MAM_A3MEM_DED_COUNT__SHIFT 0x1a |
11906 | #define GCEA_EDC_CNT3__MAM_AFMEM_SEC_COUNT__SHIFT 0x1c |
11907 | #define GCEA_EDC_CNT3__MAM_AFMEM_DED_COUNT__SHIFT 0x1e |
11908 | #define GCEA_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT_MASK 0x00000003L |
11909 | #define GCEA_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT_MASK 0x0000000CL |
11910 | #define GCEA_EDC_CNT3__IORD_CMDMEM_DED_COUNT_MASK 0x00000030L |
11911 | #define GCEA_EDC_CNT3__IOWR_CMDMEM_DED_COUNT_MASK 0x000000C0L |
11912 | #define GCEA_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT_MASK 0x00000300L |
11913 | #define GCEA_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT_MASK 0x00000C00L |
11914 | #define GCEA_EDC_CNT3__MAM_A0MEM_SEC_COUNT_MASK 0x00003000L |
11915 | #define GCEA_EDC_CNT3__MAM_A0MEM_DED_COUNT_MASK 0x0000C000L |
11916 | #define GCEA_EDC_CNT3__MAM_A1MEM_SEC_COUNT_MASK 0x00030000L |
11917 | #define GCEA_EDC_CNT3__MAM_A1MEM_DED_COUNT_MASK 0x000C0000L |
11918 | #define GCEA_EDC_CNT3__MAM_A2MEM_SEC_COUNT_MASK 0x00300000L |
11919 | #define GCEA_EDC_CNT3__MAM_A2MEM_DED_COUNT_MASK 0x00C00000L |
11920 | #define GCEA_EDC_CNT3__MAM_A3MEM_SEC_COUNT_MASK 0x03000000L |
11921 | #define GCEA_EDC_CNT3__MAM_A3MEM_DED_COUNT_MASK 0x0C000000L |
11922 | #define GCEA_EDC_CNT3__MAM_AFMEM_SEC_COUNT_MASK 0x30000000L |
11923 | #define GCEA_EDC_CNT3__MAM_AFMEM_DED_COUNT_MASK 0xC0000000L |
11924 | //GCEA_SDP_ENABLE |
11925 | #define GCEA_SDP_ENABLE__ENABLE__SHIFT 0x0 |
11926 | #define GCEA_SDP_ENABLE__EARLY_CREDIT_REQUEST__SHIFT 0x1 |
11927 | #define GCEA_SDP_ENABLE__ENABLE_MASK 0x00000001L |
11928 | #define GCEA_SDP_ENABLE__EARLY_CREDIT_REQUEST_MASK 0x00000002L |
11929 | |
11930 | |
11931 | // addressBlock: gc_spipdec2 |
11932 | //SPI_PQEV_CTRL |
11933 | #define SPI_PQEV_CTRL__SCAN_PERIOD__SHIFT 0x0 |
11934 | #define SPI_PQEV_CTRL__QUEUE_DURATION__SHIFT 0xa |
11935 | #define SPI_PQEV_CTRL__COMPUTE_PIPE_EN__SHIFT 0x10 |
11936 | #define SPI_PQEV_CTRL__SCAN_PERIOD_MASK 0x000003FFL |
11937 | #define SPI_PQEV_CTRL__QUEUE_DURATION_MASK 0x0000FC00L |
11938 | #define SPI_PQEV_CTRL__COMPUTE_PIPE_EN_MASK 0x00FF0000L |
11939 | //SPI_EXP_THROTTLE_CTRL |
11940 | #define SPI_EXP_THROTTLE_CTRL__ENABLE__SHIFT 0x0 |
11941 | #define SPI_EXP_THROTTLE_CTRL__PERIOD__SHIFT 0x1 |
11942 | #define SPI_EXP_THROTTLE_CTRL__UPSTEP__SHIFT 0x5 |
11943 | #define SPI_EXP_THROTTLE_CTRL__DOWNSTEP__SHIFT 0x9 |
11944 | #define SPI_EXP_THROTTLE_CTRL__LOW_STALL_MON_HIST_COUNT__SHIFT 0xd |
11945 | #define SPI_EXP_THROTTLE_CTRL__HIGH_STALL_MON_HIST_COUNT__SHIFT 0x10 |
11946 | #define SPI_EXP_THROTTLE_CTRL__EXP_STALL_THRESHOLD__SHIFT 0x13 |
11947 | #define SPI_EXP_THROTTLE_CTRL__SKEW_COUNT__SHIFT 0x1a |
11948 | #define SPI_EXP_THROTTLE_CTRL__THROTTLE_RESET__SHIFT 0x1d |
11949 | #define SPI_EXP_THROTTLE_CTRL__ENABLE_MASK 0x00000001L |
11950 | #define SPI_EXP_THROTTLE_CTRL__PERIOD_MASK 0x0000001EL |
11951 | #define SPI_EXP_THROTTLE_CTRL__UPSTEP_MASK 0x000001E0L |
11952 | #define SPI_EXP_THROTTLE_CTRL__DOWNSTEP_MASK 0x00001E00L |
11953 | #define SPI_EXP_THROTTLE_CTRL__LOW_STALL_MON_HIST_COUNT_MASK 0x0000E000L |
11954 | #define SPI_EXP_THROTTLE_CTRL__HIGH_STALL_MON_HIST_COUNT_MASK 0x00070000L |
11955 | #define SPI_EXP_THROTTLE_CTRL__EXP_STALL_THRESHOLD_MASK 0x03F80000L |
11956 | #define SPI_EXP_THROTTLE_CTRL__SKEW_COUNT_MASK 0x1C000000L |
11957 | #define SPI_EXP_THROTTLE_CTRL__THROTTLE_RESET_MASK 0x20000000L |
11958 | |
11959 | |
11960 | // addressBlock: gc_rmi_rmidec |
11961 | //RMI_GENERAL_CNTL |
11962 | #define RMI_GENERAL_CNTL__BURST_DISABLE__SHIFT 0x0 |
11963 | #define RMI_GENERAL_CNTL__VMID_BYPASS_ENABLE__SHIFT 0x1 |
11964 | #define RMI_GENERAL_CNTL__RB0_HARVEST_EN__SHIFT 0x13 |
11965 | #define RMI_GENERAL_CNTL__LOOPBACK_DIS_BY_REQ_TYPE__SHIFT 0x15 |
11966 | #define RMI_GENERAL_CNTL__BURST_DISABLE_MASK 0x00000001L |
11967 | #define RMI_GENERAL_CNTL__VMID_BYPASS_ENABLE_MASK 0x0001FFFEL |
11968 | #define RMI_GENERAL_CNTL__RB0_HARVEST_EN_MASK 0x00080000L |
11969 | #define RMI_GENERAL_CNTL__LOOPBACK_DIS_BY_REQ_TYPE_MASK 0x01E00000L |
11970 | //RMI_GENERAL_CNTL1 |
11971 | #define RMI_GENERAL_CNTL1__EARLY_WRACK_ENABLE_PER_MTYPE__SHIFT 0x0 |
11972 | #define RMI_GENERAL_CNTL1__TCIW0_64B_RD_STALL_MODE__SHIFT 0x4 |
11973 | #define RMI_GENERAL_CNTL1__TCIW1_64B_RD_STALL_MODE__SHIFT 0x6 |
11974 | #define RMI_GENERAL_CNTL1__EARLY_WRACK_DISABLE_FOR_LOOPBACK__SHIFT 0x8 |
11975 | #define RMI_GENERAL_CNTL1__POLICY_OVERRIDE_VALUE__SHIFT 0x9 |
11976 | #define RMI_GENERAL_CNTL1__POLICY_OVERRIDE__SHIFT 0xb |
11977 | #define RMI_GENERAL_CNTL1__ARBITER_ADDRESS_CHANGE_ENABLE__SHIFT 0xe |
11978 | #define RMI_GENERAL_CNTL1__LAST_OF_BURST_INSERTION_DISABLE__SHIFT 0xf |
11979 | #define RMI_GENERAL_CNTL1__TCIW0_PRODUCER_CREDITS__SHIFT 0x10 |
11980 | #define RMI_GENERAL_CNTL1__TCIW1_PRODUCER_CREDITS__SHIFT 0x16 |
11981 | #define RMI_GENERAL_CNTL1__EARLY_WRACK_ENABLE_PER_MTYPE_MASK 0x0000000FL |
11982 | #define RMI_GENERAL_CNTL1__TCIW0_64B_RD_STALL_MODE_MASK 0x00000030L |
11983 | #define RMI_GENERAL_CNTL1__TCIW1_64B_RD_STALL_MODE_MASK 0x000000C0L |
11984 | #define RMI_GENERAL_CNTL1__EARLY_WRACK_DISABLE_FOR_LOOPBACK_MASK 0x00000100L |
11985 | #define RMI_GENERAL_CNTL1__POLICY_OVERRIDE_VALUE_MASK 0x00000600L |
11986 | #define RMI_GENERAL_CNTL1__POLICY_OVERRIDE_MASK 0x00000800L |
11987 | #define RMI_GENERAL_CNTL1__ARBITER_ADDRESS_CHANGE_ENABLE_MASK 0x00004000L |
11988 | #define RMI_GENERAL_CNTL1__LAST_OF_BURST_INSERTION_DISABLE_MASK 0x00008000L |
11989 | #define RMI_GENERAL_CNTL1__TCIW0_PRODUCER_CREDITS_MASK 0x003F0000L |
11990 | #define RMI_GENERAL_CNTL1__TCIW1_PRODUCER_CREDITS_MASK 0x0FC00000L |
11991 | //RMI_GENERAL_STATUS |
11992 | #define RMI_GENERAL_STATUS__GENERAL_RMI_ERRORS_COMBINED__SHIFT 0x0 |
11993 | #define RMI_GENERAL_STATUS__SKID_FIFO_0_OVERFLOW_ERROR__SHIFT 0x1 |
11994 | #define RMI_GENERAL_STATUS__SKID_FIFO_0_UNDERFLOW_ERROR__SHIFT 0x2 |
11995 | #define RMI_GENERAL_STATUS__SKID_FIFO_1_OVERFLOW_ERROR__SHIFT 0x3 |
11996 | #define RMI_GENERAL_STATUS__SKID_FIFO_1_UNDERFLOW_ERROR__SHIFT 0x4 |
11997 | #define RMI_GENERAL_STATUS__RMI_XBAR_BUSY__SHIFT 0x5 |
11998 | #define RMI_GENERAL_STATUS__RESERVED_BIT_6__SHIFT 0x6 |
11999 | #define RMI_GENERAL_STATUS__RMI_SCOREBOARD_BUSY__SHIFT 0x7 |
12000 | #define RMI_GENERAL_STATUS__TCIW0_PRT_FIFO_BUSY__SHIFT 0x8 |
12001 | #define RMI_GENERAL_STATUS__TCIW_FRMTR0_BUSY__SHIFT 0x9 |
12002 | #define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR0_BUSY__SHIFT 0xa |
12003 | #define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_0_BUSY__SHIFT 0xb |
12004 | #define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_0_BUSY__SHIFT 0xc |
12005 | #define RMI_GENERAL_STATUS__TCIW1_PRT_FIFO_BUSY__SHIFT 0xd |
12006 | #define RMI_GENERAL_STATUS__TCIW_FRMTR1_BUSY__SHIFT 0xe |
12007 | #define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR1_BUSY__SHIFT 0xf |
12008 | #define RMI_GENERAL_STATUS__RESERVED_BIT_18__SHIFT 0x12 |
12009 | #define RMI_GENERAL_STATUS__RESERVED_BIT_19__SHIFT 0x13 |
12010 | #define RMI_GENERAL_STATUS__RESERVED_BIT_20__SHIFT 0x14 |
12011 | #define RMI_GENERAL_STATUS__RESERVED_BITS_28_21__SHIFT 0x15 |
12012 | #define RMI_GENERAL_STATUS__RESERVED_BIT_29__SHIFT 0x1d |
12013 | #define RMI_GENERAL_STATUS__RESERVED_BIT_30__SHIFT 0x1e |
12014 | #define RMI_GENERAL_STATUS__SKID_FIFO_FREESPACE_IS_ZERO_ERROR__SHIFT 0x1f |
12015 | #define RMI_GENERAL_STATUS__GENERAL_RMI_ERRORS_COMBINED_MASK 0x00000001L |
12016 | #define RMI_GENERAL_STATUS__SKID_FIFO_0_OVERFLOW_ERROR_MASK 0x00000002L |
12017 | #define RMI_GENERAL_STATUS__SKID_FIFO_0_UNDERFLOW_ERROR_MASK 0x00000004L |
12018 | #define RMI_GENERAL_STATUS__SKID_FIFO_1_OVERFLOW_ERROR_MASK 0x00000008L |
12019 | #define RMI_GENERAL_STATUS__SKID_FIFO_1_UNDERFLOW_ERROR_MASK 0x00000010L |
12020 | #define RMI_GENERAL_STATUS__RMI_XBAR_BUSY_MASK 0x00000020L |
12021 | #define RMI_GENERAL_STATUS__RESERVED_BIT_6_MASK 0x00000040L |
12022 | #define RMI_GENERAL_STATUS__RMI_SCOREBOARD_BUSY_MASK 0x00000080L |
12023 | #define RMI_GENERAL_STATUS__TCIW0_PRT_FIFO_BUSY_MASK 0x00000100L |
12024 | #define RMI_GENERAL_STATUS__TCIW_FRMTR0_BUSY_MASK 0x00000200L |
12025 | #define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR0_BUSY_MASK 0x00000400L |
12026 | #define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_0_BUSY_MASK 0x00000800L |
12027 | #define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_0_BUSY_MASK 0x00001000L |
12028 | #define RMI_GENERAL_STATUS__TCIW1_PRT_FIFO_BUSY_MASK 0x00002000L |
12029 | #define RMI_GENERAL_STATUS__TCIW_FRMTR1_BUSY_MASK 0x00004000L |
12030 | #define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR1_BUSY_MASK 0x00008000L |
12031 | #define RMI_GENERAL_STATUS__RESERVED_BIT_18_MASK 0x00040000L |
12032 | #define RMI_GENERAL_STATUS__RESERVED_BIT_19_MASK 0x00080000L |
12033 | #define RMI_GENERAL_STATUS__RESERVED_BIT_20_MASK 0x00100000L |
12034 | #define RMI_GENERAL_STATUS__RESERVED_BITS_28_21_MASK 0x1FE00000L |
12035 | #define RMI_GENERAL_STATUS__RESERVED_BIT_29_MASK 0x20000000L |
12036 | #define RMI_GENERAL_STATUS__RESERVED_BIT_30_MASK 0x40000000L |
12037 | #define RMI_GENERAL_STATUS__SKID_FIFO_FREESPACE_IS_ZERO_ERROR_MASK 0x80000000L |
12038 | //RMI_SUBBLOCK_STATUS0 |
12039 | #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE0__SHIFT 0x0 |
12040 | #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE0__SHIFT 0x7 |
12041 | #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE0__SHIFT 0x8 |
12042 | #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE1__SHIFT 0x9 |
12043 | #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE1__SHIFT 0x10 |
12044 | #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE1__SHIFT 0x11 |
12045 | #define RMI_SUBBLOCK_STATUS0__TCIW0_INFLIGHT_CNT__SHIFT 0x12 |
12046 | #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE0_MASK 0x0000007FL |
12047 | #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE0_MASK 0x00000080L |
12048 | #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE0_MASK 0x00000100L |
12049 | #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE1_MASK 0x0000FE00L |
12050 | #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE1_MASK 0x00010000L |
12051 | #define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE1_MASK 0x00020000L |
12052 | #define RMI_SUBBLOCK_STATUS0__TCIW0_INFLIGHT_CNT_MASK 0x0FFC0000L |
12053 | //RMI_SUBBLOCK_STATUS1 |
12054 | #define RMI_SUBBLOCK_STATUS1__SKID_FIFO_0_FREE_SPACE__SHIFT 0x0 |
12055 | #define RMI_SUBBLOCK_STATUS1__SKID_FIFO_1_FREE_SPACE__SHIFT 0xa |
12056 | #define RMI_SUBBLOCK_STATUS1__TCIW1_INFLIGHT_CNT__SHIFT 0x14 |
12057 | #define RMI_SUBBLOCK_STATUS1__SKID_FIFO_0_FREE_SPACE_MASK 0x000003FFL |
12058 | #define RMI_SUBBLOCK_STATUS1__SKID_FIFO_1_FREE_SPACE_MASK 0x000FFC00L |
12059 | #define RMI_SUBBLOCK_STATUS1__TCIW1_INFLIGHT_CNT_MASK 0x3FF00000L |
12060 | //RMI_SUBBLOCK_STATUS2 |
12061 | #define RMI_SUBBLOCK_STATUS2__PRT_FIFO_0_NUM_USED__SHIFT 0x0 |
12062 | #define RMI_SUBBLOCK_STATUS2__PRT_FIFO_1_NUM_USED__SHIFT 0x9 |
12063 | #define RMI_SUBBLOCK_STATUS2__PRT_FIFO_0_NUM_USED_MASK 0x000001FFL |
12064 | #define RMI_SUBBLOCK_STATUS2__PRT_FIFO_1_NUM_USED_MASK 0x0003FE00L |
12065 | //RMI_SUBBLOCK_STATUS3 |
12066 | #define RMI_SUBBLOCK_STATUS3__SKID_FIFO_0_FREE_SPACE_TOTAL__SHIFT 0x0 |
12067 | #define RMI_SUBBLOCK_STATUS3__SKID_FIFO_1_FREE_SPACE_TOTAL__SHIFT 0xa |
12068 | #define RMI_SUBBLOCK_STATUS3__SKID_FIFO_0_FREE_SPACE_TOTAL_MASK 0x000003FFL |
12069 | #define RMI_SUBBLOCK_STATUS3__SKID_FIFO_1_FREE_SPACE_TOTAL_MASK 0x000FFC00L |
12070 | //RMI_XBAR_CONFIG |
12071 | #define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_OVERRIDE__SHIFT 0x0 |
12072 | #define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_REQ_TYPE_OVERRIDE__SHIFT 0x2 |
12073 | #define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_CB_DB_OVERRIDE__SHIFT 0x6 |
12074 | #define RMI_XBAR_CONFIG__ARBITER_DIS__SHIFT 0x7 |
12075 | #define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ__SHIFT 0x8 |
12076 | #define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_OVERRIDE__SHIFT 0xc |
12077 | #define RMI_XBAR_CONFIG__XBAR_EN_IN_RB0__SHIFT 0xd |
12078 | #define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_OVERRIDE_MASK 0x00000003L |
12079 | #define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_REQ_TYPE_OVERRIDE_MASK 0x0000003CL |
12080 | #define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_CB_DB_OVERRIDE_MASK 0x00000040L |
12081 | #define RMI_XBAR_CONFIG__ARBITER_DIS_MASK 0x00000080L |
12082 | #define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_MASK 0x00000F00L |
12083 | #define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_OVERRIDE_MASK 0x00001000L |
12084 | #define RMI_XBAR_CONFIG__XBAR_EN_IN_RB0_MASK 0x00002000L |
12085 | //RMI_PROBE_POP_LOGIC_CNTL |
12086 | #define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_0_MAX_DEPTH__SHIFT 0x0 |
12087 | #define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE0_DIS__SHIFT 0x7 |
12088 | #define RMI_PROBE_POP_LOGIC_CNTL__REDUCE_MAX_XLAT_CHAIN_SIZE_BY_2__SHIFT 0x8 |
12089 | #define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_1_MAX_DEPTH__SHIFT 0xa |
12090 | #define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE1_DIS__SHIFT 0x11 |
12091 | #define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_0_MAX_DEPTH_MASK 0x0000007FL |
12092 | #define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE0_DIS_MASK 0x00000080L |
12093 | #define RMI_PROBE_POP_LOGIC_CNTL__REDUCE_MAX_XLAT_CHAIN_SIZE_BY_2_MASK 0x00000300L |
12094 | #define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_1_MAX_DEPTH_MASK 0x0001FC00L |
12095 | #define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE1_DIS_MASK 0x00020000L |
12096 | //RMI_UTC_XNACK_N_MISC_CNTL |
12097 | #define RMI_UTC_XNACK_N_MISC_CNTL__MASTER_XNACK_TIMER_INC__SHIFT 0x0 |
12098 | #define RMI_UTC_XNACK_N_MISC_CNTL__IND_XNACK_TIMER_START_VALUE__SHIFT 0x8 |
12099 | #define RMI_UTC_XNACK_N_MISC_CNTL__UTCL1_PERM_MODE__SHIFT 0xc |
12100 | #define RMI_UTC_XNACK_N_MISC_CNTL__CP_VMID_RESET_REQUEST_DISABLE__SHIFT 0xd |
12101 | #define RMI_UTC_XNACK_N_MISC_CNTL__MASTER_XNACK_TIMER_INC_MASK 0x000000FFL |
12102 | #define RMI_UTC_XNACK_N_MISC_CNTL__IND_XNACK_TIMER_START_VALUE_MASK 0x00000F00L |
12103 | #define RMI_UTC_XNACK_N_MISC_CNTL__UTCL1_PERM_MODE_MASK 0x00001000L |
12104 | #define RMI_UTC_XNACK_N_MISC_CNTL__CP_VMID_RESET_REQUEST_DISABLE_MASK 0x00002000L |
12105 | //RMI_DEMUX_CNTL |
12106 | #define RMI_DEMUX_CNTL__DEMUX_ARB0_MODE_OVERRIDE_EN__SHIFT 0x2 |
12107 | #define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_START_VALUE__SHIFT 0x6 |
12108 | #define RMI_DEMUX_CNTL__DEMUX_ARB0_MODE__SHIFT 0xe |
12109 | #define RMI_DEMUX_CNTL__DEMUX_ARB1_MODE_OVERRIDE_EN__SHIFT 0x12 |
12110 | #define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_START_VALUE__SHIFT 0x16 |
12111 | #define RMI_DEMUX_CNTL__DEMUX_ARB1_MODE__SHIFT 0x1e |
12112 | #define RMI_DEMUX_CNTL__DEMUX_ARB0_MODE_OVERRIDE_EN_MASK 0x00000004L |
12113 | #define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_START_VALUE_MASK 0x00003FC0L |
12114 | #define RMI_DEMUX_CNTL__DEMUX_ARB0_MODE_MASK 0x0000C000L |
12115 | #define RMI_DEMUX_CNTL__DEMUX_ARB1_MODE_OVERRIDE_EN_MASK 0x00040000L |
12116 | #define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_START_VALUE_MASK 0x3FC00000L |
12117 | #define RMI_DEMUX_CNTL__DEMUX_ARB1_MODE_MASK 0xC0000000L |
12118 | //RMI_UTCL1_CNTL1 |
12119 | #define RMI_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0 |
12120 | #define RMI_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT 0x1 |
12121 | #define RMI_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2 |
12122 | #define RMI_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3 |
12123 | #define RMI_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5 |
12124 | #define RMI_UTCL1_CNTL1__CLIENTID__SHIFT 0x7 |
12125 | #define RMI_UTCL1_CNTL1__USERVM_DIS__SHIFT 0x10 |
12126 | #define RMI_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11 |
12127 | #define RMI_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12 |
12128 | #define RMI_UTCL1_CNTL1__REG_INV_VMID__SHIFT 0x13 |
12129 | #define RMI_UTCL1_CNTL1__REG_INV_ALL_VMID__SHIFT 0x17 |
12130 | #define RMI_UTCL1_CNTL1__REG_INV_TOGGLE__SHIFT 0x18 |
12131 | #define RMI_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT 0x19 |
12132 | #define RMI_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a |
12133 | #define RMI_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b |
12134 | #define RMI_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c |
12135 | #define RMI_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e |
12136 | #define RMI_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L |
12137 | #define RMI_UTCL1_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L |
12138 | #define RMI_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L |
12139 | #define RMI_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L |
12140 | #define RMI_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L |
12141 | #define RMI_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L |
12142 | #define RMI_UTCL1_CNTL1__USERVM_DIS_MASK 0x00010000L |
12143 | #define RMI_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L |
12144 | #define RMI_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L |
12145 | #define RMI_UTCL1_CNTL1__REG_INV_VMID_MASK 0x00780000L |
12146 | #define RMI_UTCL1_CNTL1__REG_INV_ALL_VMID_MASK 0x00800000L |
12147 | #define RMI_UTCL1_CNTL1__REG_INV_TOGGLE_MASK 0x01000000L |
12148 | #define RMI_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK 0x02000000L |
12149 | #define RMI_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L |
12150 | #define RMI_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L |
12151 | #define RMI_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L |
12152 | #define RMI_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L |
12153 | //RMI_UTCL1_CNTL2 |
12154 | #define RMI_UTCL1_CNTL2__UTC_SPARE__SHIFT 0x0 |
12155 | #define RMI_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9 |
12156 | #define RMI_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa |
12157 | #define RMI_UTCL1_CNTL2__DIS_EDC__SHIFT 0xb |
12158 | #define RMI_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc |
12159 | #define RMI_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT 0xd |
12160 | #define RMI_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe |
12161 | #define RMI_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf |
12162 | #define RMI_UTCL1_CNTL2__UTCL1_ARB_BURST_MODE__SHIFT 0x10 |
12163 | #define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_RD_WR__SHIFT 0x12 |
12164 | #define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_RD_WR__SHIFT 0x13 |
12165 | #define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_VMID__SHIFT 0x14 |
12166 | #define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_VMID__SHIFT 0x15 |
12167 | #define RMI_UTCL1_CNTL2__UTCL1_DIS_DUAL_L2_REQ__SHIFT 0x19 |
12168 | #define RMI_UTCL1_CNTL2__UTCL1_FORCE_FRAG_2M_TO_64K__SHIFT 0x1a |
12169 | #define RMI_UTCL1_CNTL2__PERM_MODE_OVRD__SHIFT 0x1b |
12170 | #define RMI_UTCL1_CNTL2__LINE_INVALIDATE_OPT__SHIFT 0x1c |
12171 | #define RMI_UTCL1_CNTL2__GPUVM_16K_DEFAULT__SHIFT 0x1d |
12172 | #define RMI_UTCL1_CNTL2__FGCG_DISABLE__SHIFT 0x1e |
12173 | #define RMI_UTCL1_CNTL2__RESERVED__SHIFT 0x1f |
12174 | #define RMI_UTCL1_CNTL2__UTC_SPARE_MASK 0x000000FFL |
12175 | #define RMI_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L |
12176 | #define RMI_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L |
12177 | #define RMI_UTCL1_CNTL2__DIS_EDC_MASK 0x00000800L |
12178 | #define RMI_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L |
12179 | #define RMI_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK 0x00002000L |
12180 | #define RMI_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L |
12181 | #define RMI_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L |
12182 | #define RMI_UTCL1_CNTL2__UTCL1_ARB_BURST_MODE_MASK 0x00030000L |
12183 | #define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L |
12184 | #define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_RD_WR_MASK 0x00080000L |
12185 | #define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_VMID_MASK 0x00100000L |
12186 | #define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_VMID_MASK 0x01E00000L |
12187 | #define RMI_UTCL1_CNTL2__UTCL1_DIS_DUAL_L2_REQ_MASK 0x02000000L |
12188 | #define RMI_UTCL1_CNTL2__UTCL1_FORCE_FRAG_2M_TO_64K_MASK 0x04000000L |
12189 | #define RMI_UTCL1_CNTL2__PERM_MODE_OVRD_MASK 0x08000000L |
12190 | #define RMI_UTCL1_CNTL2__LINE_INVALIDATE_OPT_MASK 0x10000000L |
12191 | #define RMI_UTCL1_CNTL2__GPUVM_16K_DEFAULT_MASK 0x20000000L |
12192 | #define RMI_UTCL1_CNTL2__FGCG_DISABLE_MASK 0x40000000L |
12193 | #define RMI_UTCL1_CNTL2__RESERVED_MASK 0x80000000L |
12194 | //RMI_UTC_UNIT_CONFIG |
12195 | #define RMI_UTC_UNIT_CONFIG__TMZ_REQ_EN__SHIFT 0x0 |
12196 | #define RMI_UTC_UNIT_CONFIG__TMZ_REQ_EN_MASK 0x0000FFFFL |
12197 | //RMI_TCIW_FORMATTER0_CNTL |
12198 | #define RMI_TCIW_FORMATTER0_CNTL__TCIW0_MAX_ALLOWED_INFLIGHT_REQ__SHIFT 0x9 |
12199 | #define RMI_TCIW_FORMATTER0_CNTL__RMI_IN0_REORDER_DIS__SHIFT 0x1d |
12200 | #define RMI_TCIW_FORMATTER0_CNTL__ALL_FAULT_RET0_DATA__SHIFT 0x1f |
12201 | #define RMI_TCIW_FORMATTER0_CNTL__TCIW0_MAX_ALLOWED_INFLIGHT_REQ_MASK 0x0007FE00L |
12202 | #define RMI_TCIW_FORMATTER0_CNTL__RMI_IN0_REORDER_DIS_MASK 0x20000000L |
12203 | #define RMI_TCIW_FORMATTER0_CNTL__ALL_FAULT_RET0_DATA_MASK 0x80000000L |
12204 | //RMI_TCIW_FORMATTER1_CNTL |
12205 | #define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_OVERRIDE__SHIFT 0x0 |
12206 | #define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_TIME_OUT_WINDOW__SHIFT 0x1 |
12207 | #define RMI_TCIW_FORMATTER1_CNTL__TCIW1_MAX_ALLOWED_INFLIGHT_REQ__SHIFT 0x9 |
12208 | #define RMI_TCIW_FORMATTER1_CNTL__RMI_IN1_REORDER_DIS__SHIFT 0x1d |
12209 | #define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_AT_LAST_OF_BURST__SHIFT 0x1e |
12210 | #define RMI_TCIW_FORMATTER1_CNTL__ALL_FAULT_RET1_DATA__SHIFT 0x1f |
12211 | #define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_OVERRIDE_MASK 0x00000001L |
12212 | #define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_TIME_OUT_WINDOW_MASK 0x000001FEL |
12213 | #define RMI_TCIW_FORMATTER1_CNTL__TCIW1_MAX_ALLOWED_INFLIGHT_REQ_MASK 0x0007FE00L |
12214 | #define RMI_TCIW_FORMATTER1_CNTL__RMI_IN1_REORDER_DIS_MASK 0x20000000L |
12215 | #define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_AT_LAST_OF_BURST_MASK 0x40000000L |
12216 | #define RMI_TCIW_FORMATTER1_CNTL__ALL_FAULT_RET1_DATA_MASK 0x80000000L |
12217 | //RMI_SCOREBOARD_CNTL |
12218 | #define RMI_SCOREBOARD_CNTL__COMPLETE_RB0_FLUSH__SHIFT 0x0 |
12219 | #define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB0__SHIFT 0x1 |
12220 | #define RMI_SCOREBOARD_CNTL__COMPLETE_RB1_FLUSH__SHIFT 0x2 |
12221 | #define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB1__SHIFT 0x3 |
12222 | #define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_EN__SHIFT 0x5 |
12223 | #define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_VALUE__SHIFT 0x6 |
12224 | #define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_TIMER_START_VALUE__SHIFT 0x9 |
12225 | #define RMI_SCOREBOARD_CNTL__COMPLETE_RB0_FLUSH_MASK 0x00000001L |
12226 | #define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB0_MASK 0x00000002L |
12227 | #define RMI_SCOREBOARD_CNTL__COMPLETE_RB1_FLUSH_MASK 0x00000004L |
12228 | #define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB1_MASK 0x00000008L |
12229 | #define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_EN_MASK 0x00000020L |
12230 | #define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_VALUE_MASK 0x00000040L |
12231 | #define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_TIMER_START_VALUE_MASK 0x001FFE00L |
12232 | //RMI_SCOREBOARD_STATUS0 |
12233 | #define RMI_SCOREBOARD_STATUS0__CURRENT_SESSION_ID__SHIFT 0x0 |
12234 | #define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_IN_PROG__SHIFT 0x1 |
12235 | #define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_REQ_VMID__SHIFT 0x2 |
12236 | #define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_UTC_DONE__SHIFT 0x12 |
12237 | #define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_DONE__SHIFT 0x13 |
12238 | #define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_FLUSH_TYPE__SHIFT 0x14 |
12239 | #define RMI_SCOREBOARD_STATUS0__FORCE_VMID_INV_DONE__SHIFT 0x15 |
12240 | #define RMI_SCOREBOARD_STATUS0__COUNTER_SELECT__SHIFT 0x16 |
12241 | #define RMI_SCOREBOARD_STATUS0__CURRENT_SESSION_ID_MASK 0x00000001L |
12242 | #define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_IN_PROG_MASK 0x00000002L |
12243 | #define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_REQ_VMID_MASK 0x0003FFFCL |
12244 | #define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_UTC_DONE_MASK 0x00040000L |
12245 | #define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_DONE_MASK 0x00080000L |
12246 | #define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_FLUSH_TYPE_MASK 0x00100000L |
12247 | #define RMI_SCOREBOARD_STATUS0__FORCE_VMID_INV_DONE_MASK 0x00200000L |
12248 | #define RMI_SCOREBOARD_STATUS0__COUNTER_SELECT_MASK 0x07C00000L |
12249 | //RMI_SCOREBOARD_STATUS1 |
12250 | #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB0__SHIFT 0x0 |
12251 | #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB0__SHIFT 0xc |
12252 | #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB0__SHIFT 0xd |
12253 | #define RMI_SCOREBOARD_STATUS1__MULTI_VMID_INVAL_FROM_CP_DETECTED__SHIFT 0xe |
12254 | #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB1__SHIFT 0xf |
12255 | #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB1__SHIFT 0x1b |
12256 | #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB1__SHIFT 0x1c |
12257 | #define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB1__SHIFT 0x1d |
12258 | #define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB0__SHIFT 0x1e |
12259 | #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB0_MASK 0x00000FFFL |
12260 | #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB0_MASK 0x00001000L |
12261 | #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB0_MASK 0x00002000L |
12262 | #define RMI_SCOREBOARD_STATUS1__MULTI_VMID_INVAL_FROM_CP_DETECTED_MASK 0x00004000L |
12263 | #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB1_MASK 0x07FF8000L |
12264 | #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB1_MASK 0x08000000L |
12265 | #define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB1_MASK 0x10000000L |
12266 | #define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB1_MASK 0x20000000L |
12267 | #define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB0_MASK 0x40000000L |
12268 | //RMI_SCOREBOARD_STATUS2 |
12269 | #define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB0__SHIFT 0x0 |
12270 | #define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB0__SHIFT 0xc |
12271 | #define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB1__SHIFT 0xd |
12272 | #define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB1__SHIFT 0x19 |
12273 | #define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB1__SHIFT 0x1a |
12274 | #define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB0__SHIFT 0x1b |
12275 | #define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB0__SHIFT 0x1c |
12276 | #define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB1__SHIFT 0x1d |
12277 | #define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB0__SHIFT 0x1e |
12278 | #define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB1__SHIFT 0x1f |
12279 | #define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB0_MASK 0x00000FFFL |
12280 | #define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB0_MASK 0x00001000L |
12281 | #define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB1_MASK 0x01FFE000L |
12282 | #define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB1_MASK 0x02000000L |
12283 | #define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB1_MASK 0x04000000L |
12284 | #define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB0_MASK 0x08000000L |
12285 | #define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB0_MASK 0x10000000L |
12286 | #define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB1_MASK 0x20000000L |
12287 | #define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB0_MASK 0x40000000L |
12288 | #define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB1_MASK 0x80000000L |
12289 | //RMI_XBAR_ARBITER_CONFIG |
12290 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_MODE__SHIFT 0x0 |
12291 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_WEIGHTEDRR__SHIFT 0x2 |
12292 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL__SHIFT 0x3 |
12293 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_IDLEIN__SHIFT 0x4 |
12294 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_MODE_OVERRIDE_EN__SHIFT 0x5 |
12295 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_OVERRIDE__SHIFT 0x6 |
12296 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_START_VALUE__SHIFT 0x8 |
12297 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_MODE__SHIFT 0x10 |
12298 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_WEIGHTEDRR__SHIFT 0x12 |
12299 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL__SHIFT 0x13 |
12300 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_IDLEIN__SHIFT 0x14 |
12301 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_MODE_OVERRIDE_EN__SHIFT 0x15 |
12302 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_OVERRIDE__SHIFT 0x16 |
12303 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_START_VALUE__SHIFT 0x18 |
12304 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_MODE_MASK 0x00000003L |
12305 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_WEIGHTEDRR_MASK 0x00000004L |
12306 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_MASK 0x00000008L |
12307 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_IDLEIN_MASK 0x00000010L |
12308 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_MODE_OVERRIDE_EN_MASK 0x00000020L |
12309 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_OVERRIDE_MASK 0x000000C0L |
12310 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_START_VALUE_MASK 0x0000FF00L |
12311 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_MODE_MASK 0x00030000L |
12312 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_WEIGHTEDRR_MASK 0x00040000L |
12313 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_MASK 0x00080000L |
12314 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_IDLEIN_MASK 0x00100000L |
12315 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_MODE_OVERRIDE_EN_MASK 0x00200000L |
12316 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_OVERRIDE_MASK 0x00C00000L |
12317 | #define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_START_VALUE_MASK 0xFF000000L |
12318 | //RMI_XBAR_ARBITER_CONFIG_1 |
12319 | #define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_RD__SHIFT 0x0 |
12320 | #define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_WR__SHIFT 0x8 |
12321 | #define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_RD_MASK 0x000000FFL |
12322 | #define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_WR_MASK 0x0000FF00L |
12323 | //RMI_CLOCK_CNTRL |
12324 | #define RMI_CLOCK_CNTRL__DYN_CLK_RB0_BUSY_MASK__SHIFT 0x0 |
12325 | #define RMI_CLOCK_CNTRL__DYN_CLK_CMN_BUSY_MASK__SHIFT 0x5 |
12326 | #define RMI_CLOCK_CNTRL__DYN_CLK_RB0_WAKEUP_MASK__SHIFT 0xa |
12327 | #define RMI_CLOCK_CNTRL__DYN_CLK_CMN_WAKEUP_MASK__SHIFT 0xf |
12328 | #define RMI_CLOCK_CNTRL__DYN_CLK_RB0_BUSY_MASK_MASK 0x0000001FL |
12329 | #define RMI_CLOCK_CNTRL__DYN_CLK_CMN_BUSY_MASK_MASK 0x000003E0L |
12330 | #define RMI_CLOCK_CNTRL__DYN_CLK_RB0_WAKEUP_MASK_MASK 0x00007C00L |
12331 | #define RMI_CLOCK_CNTRL__DYN_CLK_CMN_WAKEUP_MASK_MASK 0x000F8000L |
12332 | //RMI_UTCL1_STATUS |
12333 | #define RMI_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 |
12334 | #define RMI_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 |
12335 | #define RMI_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 |
12336 | #define RMI_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L |
12337 | #define RMI_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L |
12338 | #define RMI_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L |
12339 | //RMI_RB_GLX_CID_MAP |
12340 | #define RMI_RB_GLX_CID_MAP__CB_COLOR_MAP__SHIFT 0x0 |
12341 | #define RMI_RB_GLX_CID_MAP__CB_FMASK_MAP__SHIFT 0x4 |
12342 | #define RMI_RB_GLX_CID_MAP__CB_CMASK_MAP__SHIFT 0x8 |
12343 | #define RMI_RB_GLX_CID_MAP__CB_DCC_MAP__SHIFT 0xc |
12344 | #define RMI_RB_GLX_CID_MAP__DB_Z_MAP__SHIFT 0x10 |
12345 | #define RMI_RB_GLX_CID_MAP__DB_S_MAP__SHIFT 0x14 |
12346 | #define RMI_RB_GLX_CID_MAP__DB_TILE_MAP__SHIFT 0x18 |
12347 | #define RMI_RB_GLX_CID_MAP__DB_ZPCPSD_MAP__SHIFT 0x1c |
12348 | #define RMI_RB_GLX_CID_MAP__CB_COLOR_MAP_MASK 0x0000000FL |
12349 | #define RMI_RB_GLX_CID_MAP__CB_FMASK_MAP_MASK 0x000000F0L |
12350 | #define RMI_RB_GLX_CID_MAP__CB_CMASK_MAP_MASK 0x00000F00L |
12351 | #define RMI_RB_GLX_CID_MAP__CB_DCC_MAP_MASK 0x0000F000L |
12352 | #define RMI_RB_GLX_CID_MAP__DB_Z_MAP_MASK 0x000F0000L |
12353 | #define RMI_RB_GLX_CID_MAP__DB_S_MAP_MASK 0x00F00000L |
12354 | #define RMI_RB_GLX_CID_MAP__DB_TILE_MAP_MASK 0x0F000000L |
12355 | #define RMI_RB_GLX_CID_MAP__DB_ZPCPSD_MAP_MASK 0xF0000000L |
12356 | //RMI_XNACK_DEBUG |
12357 | #define RMI_XNACK_DEBUG__XNACK_PER_VMID__SHIFT 0x0 |
12358 | #define RMI_XNACK_DEBUG__XNACK_PER_VMID_MASK 0x0000FFFFL |
12359 | //RMI_SPARE |
12360 | #define RMI_SPARE__RMI_2_GL1_128B_READ_DISABLE__SHIFT 0x1 |
12361 | #define RMI_SPARE__RMI_2_GL1_REPEATER_FGCG_DISABLE__SHIFT 0x2 |
12362 | #define RMI_SPARE__RMI_2_RB_REPEATER_FGCG_DISABLE__SHIFT 0x3 |
12363 | #define RMI_SPARE__EARLY_WRITE_ACK_ENABLE_C_RW_NOA_RESOLVE_DIS__SHIFT 0x4 |
12364 | #define RMI_SPARE__RMI_REORDER_BYPASS_CHANNEL_DIS__SHIFT 0x5 |
12365 | #define RMI_SPARE__XNACK_RETURN_DATA_OVERRIDE__SHIFT 0x6 |
12366 | #define RMI_SPARE__SPARE_BIT_7__SHIFT 0x7 |
12367 | #define RMI_SPARE__NOFILL_RMI_CID_CC__SHIFT 0x8 |
12368 | #define RMI_SPARE__NOFILL_RMI_CID_FC__SHIFT 0x9 |
12369 | #define RMI_SPARE__NOFILL_RMI_CID_CM__SHIFT 0xa |
12370 | #define RMI_SPARE__NOFILL_RMI_CID_DC__SHIFT 0xb |
12371 | #define RMI_SPARE__NOFILL_RMI_CID_Z__SHIFT 0xc |
12372 | #define RMI_SPARE__NOFILL_RMI_CID_S__SHIFT 0xd |
12373 | #define RMI_SPARE__NOFILL_RMI_CID_TILE__SHIFT 0xe |
12374 | #define RMI_SPARE__SPARE_BIT_15_0__SHIFT 0xf |
12375 | #define RMI_SPARE__ARBITER_ADDRESS_MASK__SHIFT 0x10 |
12376 | #define RMI_SPARE__RMI_2_GL1_128B_READ_DISABLE_MASK 0x00000002L |
12377 | #define RMI_SPARE__RMI_2_GL1_REPEATER_FGCG_DISABLE_MASK 0x00000004L |
12378 | #define RMI_SPARE__RMI_2_RB_REPEATER_FGCG_DISABLE_MASK 0x00000008L |
12379 | #define RMI_SPARE__EARLY_WRITE_ACK_ENABLE_C_RW_NOA_RESOLVE_DIS_MASK 0x00000010L |
12380 | #define RMI_SPARE__RMI_REORDER_BYPASS_CHANNEL_DIS_MASK 0x00000020L |
12381 | #define RMI_SPARE__XNACK_RETURN_DATA_OVERRIDE_MASK 0x00000040L |
12382 | #define RMI_SPARE__SPARE_BIT_7_MASK 0x00000080L |
12383 | #define RMI_SPARE__NOFILL_RMI_CID_CC_MASK 0x00000100L |
12384 | #define RMI_SPARE__NOFILL_RMI_CID_FC_MASK 0x00000200L |
12385 | #define RMI_SPARE__NOFILL_RMI_CID_CM_MASK 0x00000400L |
12386 | #define RMI_SPARE__NOFILL_RMI_CID_DC_MASK 0x00000800L |
12387 | #define RMI_SPARE__NOFILL_RMI_CID_Z_MASK 0x00001000L |
12388 | #define RMI_SPARE__NOFILL_RMI_CID_S_MASK 0x00002000L |
12389 | #define RMI_SPARE__NOFILL_RMI_CID_TILE_MASK 0x00004000L |
12390 | #define RMI_SPARE__SPARE_BIT_15_0_MASK 0x00008000L |
12391 | #define RMI_SPARE__ARBITER_ADDRESS_MASK_MASK 0xFFFF0000L |
12392 | //RMI_SPARE_1 |
12393 | #define RMI_SPARE_1__EARLY_WRACK_FIFO_DISABLE__SHIFT 0x0 |
12394 | #define RMI_SPARE_1__SPARE_BIT_9__SHIFT 0x1 |
12395 | #define RMI_SPARE_1__SPARE_BIT_10__SHIFT 0x2 |
12396 | #define RMI_SPARE_1__SPARE_BIT_11__SHIFT 0x3 |
12397 | #define RMI_SPARE_1__SPARE_BIT_12__SHIFT 0x4 |
12398 | #define RMI_SPARE_1__SPARE_BIT_13__SHIFT 0x5 |
12399 | #define RMI_SPARE_1__SPARE_BIT_14__SHIFT 0x6 |
12400 | #define RMI_SPARE_1__SPARE_BIT_15__SHIFT 0x7 |
12401 | #define RMI_SPARE_1__RMI_REORDER_DIS_BY_CID__SHIFT 0x8 |
12402 | #define RMI_SPARE_1__SPARE_BIT_16_1__SHIFT 0x10 |
12403 | #define RMI_SPARE_1__EARLY_WRACK_FIFO_DISABLE_MASK 0x00000001L |
12404 | #define RMI_SPARE_1__SPARE_BIT_9_MASK 0x00000002L |
12405 | #define RMI_SPARE_1__SPARE_BIT_10_MASK 0x00000004L |
12406 | #define RMI_SPARE_1__SPARE_BIT_11_MASK 0x00000008L |
12407 | #define RMI_SPARE_1__SPARE_BIT_12_MASK 0x00000010L |
12408 | #define RMI_SPARE_1__SPARE_BIT_13_MASK 0x00000020L |
12409 | #define RMI_SPARE_1__SPARE_BIT_14_MASK 0x00000040L |
12410 | #define RMI_SPARE_1__SPARE_BIT_15_MASK 0x00000080L |
12411 | #define RMI_SPARE_1__RMI_REORDER_DIS_BY_CID_MASK 0x0000FF00L |
12412 | #define RMI_SPARE_1__SPARE_BIT_16_1_MASK 0xFFFF0000L |
12413 | //RMI_SPARE_2 |
12414 | #define RMI_SPARE_2__ERROR_ZERO_BYTE_MASK_CID__SHIFT 0x0 |
12415 | #define RMI_SPARE_2__SPARE_BIT_8_2__SHIFT 0x10 |
12416 | #define RMI_SPARE_2__SPARE_BIT_8_3__SHIFT 0x18 |
12417 | #define RMI_SPARE_2__ERROR_ZERO_BYTE_MASK_CID_MASK 0x0000FFFFL |
12418 | #define RMI_SPARE_2__SPARE_BIT_8_2_MASK 0x00FF0000L |
12419 | #define RMI_SPARE_2__SPARE_BIT_8_3_MASK 0xFF000000L |
12420 | //CC_RMI_REDUNDANCY |
12421 | #define CC_RMI_REDUNDANCY__WRITE_DIS__SHIFT 0x0 |
12422 | #define CC_RMI_REDUNDANCY__REPAIR_EN_IN_0__SHIFT 0x1 |
12423 | #define CC_RMI_REDUNDANCY__REPAIR_EN_IN_1__SHIFT 0x2 |
12424 | #define CC_RMI_REDUNDANCY__REPAIR_RMI_OVERRIDE__SHIFT 0x3 |
12425 | #define CC_RMI_REDUNDANCY__REPAIR_ID_SWAP__SHIFT 0x4 |
12426 | #define CC_RMI_REDUNDANCY__WRITE_DIS_MASK 0x00000001L |
12427 | #define CC_RMI_REDUNDANCY__REPAIR_EN_IN_0_MASK 0x00000002L |
12428 | #define CC_RMI_REDUNDANCY__REPAIR_EN_IN_1_MASK 0x00000004L |
12429 | #define CC_RMI_REDUNDANCY__REPAIR_RMI_OVERRIDE_MASK 0x00000008L |
12430 | #define CC_RMI_REDUNDANCY__REPAIR_ID_SWAP_MASK 0x00000010L |
12431 | |
12432 | |
12433 | // addressBlock: gc_pmmdec |
12434 | //GCR_PIO_CNTL |
12435 | #define GCR_PIO_CNTL__GCR_DATA_INDEX__SHIFT 0x0 |
12436 | #define GCR_PIO_CNTL__GCR_REG_DONE__SHIFT 0x2 |
12437 | #define GCR_PIO_CNTL__GCR_REG_RESET__SHIFT 0x3 |
12438 | #define GCR_PIO_CNTL__GCR_PIO_RSP_TAG__SHIFT 0x10 |
12439 | #define GCR_PIO_CNTL__GCR_PIO_RSP_DONE__SHIFT 0x1e |
12440 | #define GCR_PIO_CNTL__GCR_READY__SHIFT 0x1f |
12441 | #define GCR_PIO_CNTL__GCR_DATA_INDEX_MASK 0x00000003L |
12442 | #define GCR_PIO_CNTL__GCR_REG_DONE_MASK 0x00000004L |
12443 | #define GCR_PIO_CNTL__GCR_REG_RESET_MASK 0x00000008L |
12444 | #define GCR_PIO_CNTL__GCR_PIO_RSP_TAG_MASK 0x00FF0000L |
12445 | #define GCR_PIO_CNTL__GCR_PIO_RSP_DONE_MASK 0x40000000L |
12446 | #define GCR_PIO_CNTL__GCR_READY_MASK 0x80000000L |
12447 | //GCR_PIO_DATA |
12448 | #define GCR_PIO_DATA__GCR_DATA__SHIFT 0x0 |
12449 | #define GCR_PIO_DATA__GCR_DATA_MASK 0xFFFFFFFFL |
12450 | //PMM_CNTL |
12451 | #define PMM_CNTL__PMM_DISABLE__SHIFT 0x0 |
12452 | #define PMM_CNTL__ABIT_FORCE_FLUSH__SHIFT 0x1 |
12453 | #define PMM_CNTL__ABIT_TIMER_THRESHOLD__SHIFT 0x2 |
12454 | #define PMM_CNTL__ABIT_TIMER_DISABLE__SHIFT 0x6 |
12455 | #define PMM_CNTL__ABIT_TIMER_RESET__SHIFT 0x7 |
12456 | #define PMM_CNTL__INTERRUPT_PRIORITY__SHIFT 0x8 |
12457 | #define PMM_CNTL__PMM_INTERRUPTS_DISABLE__SHIFT 0xa |
12458 | #define PMM_CNTL__RESERVED__SHIFT 0xb |
12459 | #define PMM_CNTL__PMM_DISABLE_MASK 0x00000001L |
12460 | #define PMM_CNTL__ABIT_FORCE_FLUSH_MASK 0x00000002L |
12461 | #define PMM_CNTL__ABIT_TIMER_THRESHOLD_MASK 0x0000003CL |
12462 | #define PMM_CNTL__ABIT_TIMER_DISABLE_MASK 0x00000040L |
12463 | #define PMM_CNTL__ABIT_TIMER_RESET_MASK 0x00000080L |
12464 | #define PMM_CNTL__INTERRUPT_PRIORITY_MASK 0x00000300L |
12465 | #define PMM_CNTL__PMM_INTERRUPTS_DISABLE_MASK 0x00000400L |
12466 | #define PMM_CNTL__RESERVED_MASK 0xFFFFF800L |
12467 | //PMM_STATUS |
12468 | #define PMM_STATUS__PMM_IDLE__SHIFT 0x0 |
12469 | #define PMM_STATUS__ABIT_FORCE_FLUSH_IN_PROGRESS__SHIFT 0x1 |
12470 | #define PMM_STATUS__ABIT_FORCE_FLUSH_DONE__SHIFT 0x2 |
12471 | #define PMM_STATUS__ABIT_TIMER_FLUSH_IN_PROGRESS__SHIFT 0x3 |
12472 | #define PMM_STATUS__ABIT_TIMER_FLUSH_DONE__SHIFT 0x4 |
12473 | #define PMM_STATUS__ABIT_TIMER_RUNNING__SHIFT 0x5 |
12474 | #define PMM_STATUS__PMM_INTERRUPTS_PENDING__SHIFT 0x6 |
12475 | #define PMM_STATUS__ABIT_FLUSH_ERROR__SHIFT 0x7 |
12476 | #define PMM_STATUS__ABIT_TIMER_RESET_CDC_IN_PROGRESS__SHIFT 0x8 |
12477 | #define PMM_STATUS__ABIT_TIMER_ENABLE_CDC_IN_PROGRESS__SHIFT 0x9 |
12478 | #define PMM_STATUS__ABIT_TIMER_THRESHOLD_CDC_IN_PROGRESS__SHIFT 0xa |
12479 | #define PMM_STATUS__RESERVED__SHIFT 0xb |
12480 | #define PMM_STATUS__PMM_IDLE_MASK 0x00000001L |
12481 | #define PMM_STATUS__ABIT_FORCE_FLUSH_IN_PROGRESS_MASK 0x00000002L |
12482 | #define PMM_STATUS__ABIT_FORCE_FLUSH_DONE_MASK 0x00000004L |
12483 | #define PMM_STATUS__ABIT_TIMER_FLUSH_IN_PROGRESS_MASK 0x00000008L |
12484 | #define PMM_STATUS__ABIT_TIMER_FLUSH_DONE_MASK 0x00000010L |
12485 | #define PMM_STATUS__ABIT_TIMER_RUNNING_MASK 0x00000020L |
12486 | #define PMM_STATUS__PMM_INTERRUPTS_PENDING_MASK 0x00000040L |
12487 | #define PMM_STATUS__ABIT_FLUSH_ERROR_MASK 0x00000080L |
12488 | #define PMM_STATUS__ABIT_TIMER_RESET_CDC_IN_PROGRESS_MASK 0x00000100L |
12489 | #define PMM_STATUS__ABIT_TIMER_ENABLE_CDC_IN_PROGRESS_MASK 0x00000200L |
12490 | #define PMM_STATUS__ABIT_TIMER_THRESHOLD_CDC_IN_PROGRESS_MASK 0x00000400L |
12491 | #define PMM_STATUS__RESERVED_MASK 0xFFFFF800L |
12492 | |
12493 | |
12494 | // addressBlock: gc_utcl1dec |
12495 | //UTCL1_CTRL_1 |
12496 | #define UTCL1_CTRL_1__UTCL1_CACHE_CORE_BYPASS__SHIFT 0x0 |
12497 | #define UTCL1_CTRL_1__UTCL1_TCP_BYPASS__SHIFT 0x1 |
12498 | #define UTCL1_CTRL_1__UTCL1_SQCI_BYPASS__SHIFT 0x2 |
12499 | #define UTCL1_CTRL_1__UTCL1_SQCD_BYPASS__SHIFT 0x3 |
12500 | #define UTCL1_CTRL_1__UTCL1_RMI_BYPASS__SHIFT 0x4 |
12501 | #define UTCL1_CTRL_1__UTCL1_SQG_BYPASS__SHIFT 0x5 |
12502 | #define UTCL1_CTRL_1__UTCL1_FORCE_RANGE_INV_TO_VMID__SHIFT 0x6 |
12503 | #define UTCL1_CTRL_1__UTCL1_FORCE_INV_ALL__SHIFT 0x7 |
12504 | #define UTCL1_CTRL_1__UTCL1_FORCE_INV_ALL_DONE__SHIFT 0x8 |
12505 | #define UTCL1_CTRL_1__UTCL1_PAGE_SIZE_1__SHIFT 0x9 |
12506 | #define UTCL1_CTRL_1__UTCL1_PAGE_SIZE_2__SHIFT 0xb |
12507 | #define UTCL1_CTRL_1__UTCL1_PAGE_SIZE_3__SHIFT 0xd |
12508 | #define UTCL1_CTRL_1__UTCL1_PAGE_SIZE_4__SHIFT 0xf |
12509 | #define UTCL1_CTRL_1__RESERVED__SHIFT 0x11 |
12510 | #define UTCL1_CTRL_1__UTCL1_CACHE_CORE_BYPASS_MASK 0x00000001L |
12511 | #define UTCL1_CTRL_1__UTCL1_TCP_BYPASS_MASK 0x00000002L |
12512 | #define UTCL1_CTRL_1__UTCL1_SQCI_BYPASS_MASK 0x00000004L |
12513 | #define UTCL1_CTRL_1__UTCL1_SQCD_BYPASS_MASK 0x00000008L |
12514 | #define UTCL1_CTRL_1__UTCL1_RMI_BYPASS_MASK 0x00000010L |
12515 | #define UTCL1_CTRL_1__UTCL1_SQG_BYPASS_MASK 0x00000020L |
12516 | #define UTCL1_CTRL_1__UTCL1_FORCE_RANGE_INV_TO_VMID_MASK 0x00000040L |
12517 | #define UTCL1_CTRL_1__UTCL1_FORCE_INV_ALL_MASK 0x00000080L |
12518 | #define UTCL1_CTRL_1__UTCL1_FORCE_INV_ALL_DONE_MASK 0x00000100L |
12519 | #define UTCL1_CTRL_1__UTCL1_PAGE_SIZE_1_MASK 0x00000600L |
12520 | #define UTCL1_CTRL_1__UTCL1_PAGE_SIZE_2_MASK 0x00001800L |
12521 | #define UTCL1_CTRL_1__UTCL1_PAGE_SIZE_3_MASK 0x00006000L |
12522 | #define UTCL1_CTRL_1__UTCL1_PAGE_SIZE_4_MASK 0x00018000L |
12523 | #define UTCL1_CTRL_1__RESERVED_MASK 0xFFFE0000L |
12524 | //UTCL1_ALOG |
12525 | #define UTCL1_ALOG__UTCL1_ALOG_MODE1_FILTER1_THRESHOLD__SHIFT 0x0 |
12526 | #define UTCL1_ALOG__UTCL1_ALOG_MODE1_FILTER2_BYPASS__SHIFT 0x3 |
12527 | #define UTCL1_ALOG__UTCL1_ALOG_ACTIVE__SHIFT 0x4 |
12528 | #define UTCL1_ALOG__UTCL1_ALOG_MODE__SHIFT 0x5 |
12529 | #define UTCL1_ALOG__UTCL1_ALOG_MODE2_LOCK_WINDOW__SHIFT 0x6 |
12530 | #define UTCL1_ALOG__UTCL1_ALOG_ONLY_MISS__SHIFT 0x9 |
12531 | #define UTCL1_ALOG__UTCL1_ALOG_MODE2_INTR_THRESHOLD__SHIFT 0xa |
12532 | #define UTCL1_ALOG__UTCL1_ALOG_SPACE_EN__SHIFT 0xc |
12533 | #define UTCL1_ALOG__UTCL1_ALOG_CLEAN__SHIFT 0xf |
12534 | #define UTCL1_ALOG__UTCL1_ALOG_IDLE__SHIFT 0x10 |
12535 | #define UTCL1_ALOG__UTCL1_ALOG_TRACK_SEGMENT_SIZE__SHIFT 0x11 |
12536 | #define UTCL1_ALOG__UTCL1_ALOG_MODE1_FILTER1_BYPASS__SHIFT 0x17 |
12537 | #define UTCL1_ALOG__UTCL1_ALOG_MODE1_INTR_ON_ALLOC__SHIFT 0x18 |
12538 | #define UTCL1_ALOG__UTCL1_ALOG_MODE1_FILTER1_THRESHOLD_MASK 0x00000007L |
12539 | #define UTCL1_ALOG__UTCL1_ALOG_MODE1_FILTER2_BYPASS_MASK 0x00000008L |
12540 | #define UTCL1_ALOG__UTCL1_ALOG_ACTIVE_MASK 0x00000010L |
12541 | #define UTCL1_ALOG__UTCL1_ALOG_MODE_MASK 0x00000020L |
12542 | #define UTCL1_ALOG__UTCL1_ALOG_MODE2_LOCK_WINDOW_MASK 0x000001C0L |
12543 | #define UTCL1_ALOG__UTCL1_ALOG_ONLY_MISS_MASK 0x00000200L |
12544 | #define UTCL1_ALOG__UTCL1_ALOG_MODE2_INTR_THRESHOLD_MASK 0x00000C00L |
12545 | #define UTCL1_ALOG__UTCL1_ALOG_SPACE_EN_MASK 0x00007000L |
12546 | #define UTCL1_ALOG__UTCL1_ALOG_CLEAN_MASK 0x00008000L |
12547 | #define UTCL1_ALOG__UTCL1_ALOG_IDLE_MASK 0x00010000L |
12548 | #define UTCL1_ALOG__UTCL1_ALOG_TRACK_SEGMENT_SIZE_MASK 0x007E0000L |
12549 | #define UTCL1_ALOG__UTCL1_ALOG_MODE1_FILTER1_BYPASS_MASK 0x00800000L |
12550 | #define UTCL1_ALOG__UTCL1_ALOG_MODE1_INTR_ON_ALLOC_MASK 0x01000000L |
12551 | //UTCL1_STATUS |
12552 | #define UTCL1_STATUS__UTCL1_HIT_PATH_BUSY__SHIFT 0x0 |
12553 | #define UTCL1_STATUS__UTCL1_MH_BUSY__SHIFT 0x1 |
12554 | #define UTCL1_STATUS__UTCL1_INV_BUSY__SHIFT 0x2 |
12555 | #define UTCL1_STATUS__UTCL1_PENDING_UTCL2_REQ__SHIFT 0x3 |
12556 | #define UTCL1_STATUS__UTCL1_PENDING_UTCL2_RET__SHIFT 0x4 |
12557 | #define UTCL1_STATUS__UTCL1_LAST_UTCL2_RET_XNACK__SHIFT 0x5 |
12558 | #define UTCL1_STATUS__UTCL1_RANGE_INV_IN_PROGRESS__SHIFT 0x7 |
12559 | #define UTCL1_STATUS__RESERVED__SHIFT 0x8 |
12560 | #define UTCL1_STATUS__UTCL1_HIT_PATH_BUSY_MASK 0x00000001L |
12561 | #define UTCL1_STATUS__UTCL1_MH_BUSY_MASK 0x00000002L |
12562 | #define UTCL1_STATUS__UTCL1_INV_BUSY_MASK 0x00000004L |
12563 | #define UTCL1_STATUS__UTCL1_PENDING_UTCL2_REQ_MASK 0x00000008L |
12564 | #define UTCL1_STATUS__UTCL1_PENDING_UTCL2_RET_MASK 0x00000010L |
12565 | #define UTCL1_STATUS__UTCL1_LAST_UTCL2_RET_XNACK_MASK 0x00000060L |
12566 | #define UTCL1_STATUS__UTCL1_RANGE_INV_IN_PROGRESS_MASK 0x00000080L |
12567 | #define UTCL1_STATUS__RESERVED_MASK 0x00000100L |
12568 | |
12569 | |
12570 | // addressBlock: gc_gcvmsharedpfdec |
12571 | //GCMC_VM_NB_MMIOBASE |
12572 | #define GCMC_VM_NB_MMIOBASE__MMIOBASE__SHIFT 0x0 |
12573 | #define GCMC_VM_NB_MMIOBASE__MMIOBASE_MASK 0xFFFFFFFFL |
12574 | //GCMC_VM_NB_MMIOLIMIT |
12575 | #define GCMC_VM_NB_MMIOLIMIT__MMIOLIMIT__SHIFT 0x0 |
12576 | #define GCMC_VM_NB_MMIOLIMIT__MMIOLIMIT_MASK 0xFFFFFFFFL |
12577 | //GCMC_VM_NB_PCI_CTRL |
12578 | #define GCMC_VM_NB_PCI_CTRL__MMIOENABLE__SHIFT 0x17 |
12579 | #define GCMC_VM_NB_PCI_CTRL__MMIOENABLE_MASK 0x00800000L |
12580 | //GCMC_VM_NB_PCI_ARB |
12581 | #define GCMC_VM_NB_PCI_ARB__VGA_HOLE__SHIFT 0x3 |
12582 | #define GCMC_VM_NB_PCI_ARB__VGA_HOLE_MASK 0x00000008L |
12583 | //GCMC_VM_NB_TOP_OF_DRAM_SLOT1 |
12584 | #define GCMC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM__SHIFT 0x17 |
12585 | #define GCMC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_MASK 0xFF800000L |
12586 | //GCMC_VM_NB_LOWER_TOP_OF_DRAM2 |
12587 | #define GCMC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE__SHIFT 0x0 |
12588 | #define GCMC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2__SHIFT 0x17 |
12589 | #define GCMC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE_MASK 0x00000001L |
12590 | #define GCMC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2_MASK 0xFF800000L |
12591 | //GCMC_VM_NB_UPPER_TOP_OF_DRAM2 |
12592 | #define GCMC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2__SHIFT 0x0 |
12593 | #define GCMC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2_MASK 0x00000FFFL |
12594 | //GCMC_VM_FB_OFFSET |
12595 | #define GCMC_VM_FB_OFFSET__FB_OFFSET__SHIFT 0x0 |
12596 | #define GCMC_VM_FB_OFFSET__FB_OFFSET_MASK 0x00FFFFFFL |
12597 | //GCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB |
12598 | #define GCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB__SHIFT 0x0 |
12599 | #define GCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB_MASK 0xFFFFFFFFL |
12600 | //GCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB |
12601 | #define GCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB__SHIFT 0x0 |
12602 | #define GCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB_MASK 0x0000000FL |
12603 | //GCMC_VM_STEERING |
12604 | #define GCMC_VM_STEERING__DEFAULT_STEERING__SHIFT 0x0 |
12605 | #define GCMC_VM_STEERING__DEFAULT_STEERING_MASK 0x00000003L |
12606 | //GCMC_SHARED_VIRT_RESET_REQ |
12607 | #define GCMC_SHARED_VIRT_RESET_REQ__VF__SHIFT 0x0 |
12608 | #define GCMC_SHARED_VIRT_RESET_REQ__PF__SHIFT 0x1f |
12609 | #define GCMC_SHARED_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL |
12610 | #define GCMC_SHARED_VIRT_RESET_REQ__PF_MASK 0x80000000L |
12611 | //GCMC_MEM_POWER_LS |
12612 | #define GCMC_MEM_POWER_LS__LS_SETUP__SHIFT 0x0 |
12613 | #define GCMC_MEM_POWER_LS__LS_HOLD__SHIFT 0x6 |
12614 | #define GCMC_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL |
12615 | #define GCMC_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L |
12616 | //GCMC_VM_CACHEABLE_DRAM_ADDRESS_START |
12617 | #define GCMC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS__SHIFT 0x0 |
12618 | #define GCMC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL |
12619 | //GCMC_VM_CACHEABLE_DRAM_ADDRESS_END |
12620 | #define GCMC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS__SHIFT 0x0 |
12621 | #define GCMC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL |
12622 | //GCMC_VM_LOCAL_SYSMEM_ADDRESS_START |
12623 | #define GCMC_VM_LOCAL_SYSMEM_ADDRESS_START__ADDRESS__SHIFT 0x0 |
12624 | #define GCMC_VM_LOCAL_SYSMEM_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL |
12625 | //GCMC_VM_LOCAL_SYSMEM_ADDRESS_END |
12626 | #define GCMC_VM_LOCAL_SYSMEM_ADDRESS_END__ADDRESS__SHIFT 0x0 |
12627 | #define GCMC_VM_LOCAL_SYSMEM_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL |
12628 | //GCMC_VM_APT_CNTL |
12629 | #define GCMC_VM_APT_CNTL__FORCE_MTYPE_UC__SHIFT 0x0 |
12630 | #define GCMC_VM_APT_CNTL__DIRECT_SYSTEM_EN__SHIFT 0x1 |
12631 | #define GCMC_VM_APT_CNTL__FRAG_APT_INTXN_MODE__SHIFT 0x2 |
12632 | #define GCMC_VM_APT_CNTL__CHECK_IS_LOCAL__SHIFT 0x4 |
12633 | #define GCMC_VM_APT_CNTL__CAP_FRAG_SIZE_2M__SHIFT 0x5 |
12634 | #define GCMC_VM_APT_CNTL__LOCAL_SYSMEM_APERTURE_CNTL__SHIFT 0x6 |
12635 | #define GCMC_VM_APT_CNTL__FORCE_MTYPE_UC_MASK 0x00000001L |
12636 | #define GCMC_VM_APT_CNTL__DIRECT_SYSTEM_EN_MASK 0x00000002L |
12637 | #define GCMC_VM_APT_CNTL__FRAG_APT_INTXN_MODE_MASK 0x0000000CL |
12638 | #define GCMC_VM_APT_CNTL__CHECK_IS_LOCAL_MASK 0x00000010L |
12639 | #define GCMC_VM_APT_CNTL__CAP_FRAG_SIZE_2M_MASK 0x00000020L |
12640 | #define GCMC_VM_APT_CNTL__LOCAL_SYSMEM_APERTURE_CNTL_MASK 0x000000C0L |
12641 | //GCMC_VM_LOCAL_FB_ADDRESS_START |
12642 | #define GCMC_VM_LOCAL_FB_ADDRESS_START__ADDRESS__SHIFT 0x0 |
12643 | #define GCMC_VM_LOCAL_FB_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL |
12644 | //GCMC_VM_LOCAL_FB_ADDRESS_END |
12645 | #define GCMC_VM_LOCAL_FB_ADDRESS_END__ADDRESS__SHIFT 0x0 |
12646 | #define GCMC_VM_LOCAL_FB_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL |
12647 | //GCMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL |
12648 | #define GCMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL__LOCK__SHIFT 0x0 |
12649 | #define GCMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL__LOCK_MASK 0x00000001L |
12650 | //GCUTCL2_ICG_CTRL |
12651 | #define GCUTCL2_ICG_CTRL__OFF_HYSTERESIS__SHIFT 0x0 |
12652 | #define GCUTCL2_ICG_CTRL__DYNAMIC_CLOCK_OVERRIDE__SHIFT 0x4 |
12653 | #define GCUTCL2_ICG_CTRL__STATIC_CLOCK_OVERRIDE__SHIFT 0x5 |
12654 | #define GCUTCL2_ICG_CTRL__AON_CLOCK_OVERRIDE__SHIFT 0x6 |
12655 | #define GCUTCL2_ICG_CTRL__PERFMON_CLOCK_OVERRIDE__SHIFT 0x7 |
12656 | #define GCUTCL2_ICG_CTRL__OFF_HYSTERESIS_MASK 0x0000000FL |
12657 | #define GCUTCL2_ICG_CTRL__DYNAMIC_CLOCK_OVERRIDE_MASK 0x00000010L |
12658 | #define GCUTCL2_ICG_CTRL__STATIC_CLOCK_OVERRIDE_MASK 0x00000020L |
12659 | #define GCUTCL2_ICG_CTRL__AON_CLOCK_OVERRIDE_MASK 0x00000040L |
12660 | #define GCUTCL2_ICG_CTRL__PERFMON_CLOCK_OVERRIDE_MASK 0x00000080L |
12661 | //GCMC_SHARED_ACTIVE_FCN_ID |
12662 | #define GCMC_SHARED_ACTIVE_FCN_ID__VFID__SHIFT 0x0 |
12663 | #define GCMC_SHARED_ACTIVE_FCN_ID__VF__SHIFT 0x1e |
12664 | #define GCMC_SHARED_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL |
12665 | #define GCMC_SHARED_ACTIVE_FCN_ID__VF_MASK 0x40000000L |
12666 | //GCUTCL2_CGTT_BUSY_CTRL |
12667 | #define GCUTCL2_CGTT_BUSY_CTRL__READ_DELAY__SHIFT 0x0 |
12668 | #define GCUTCL2_CGTT_BUSY_CTRL__ALWAYS_BUSY__SHIFT 0x5 |
12669 | #define GCUTCL2_CGTT_BUSY_CTRL__READ_DELAY_MASK 0x0000001FL |
12670 | #define GCUTCL2_CGTT_BUSY_CTRL__ALWAYS_BUSY_MASK 0x00000020L |
12671 | //GCMC_VM_FB_NOALLOC_CNTL |
12672 | #define GCMC_VM_FB_NOALLOC_CNTL__LOCAL_FB_NOALLOC_NOPTE__SHIFT 0x0 |
12673 | #define GCMC_VM_FB_NOALLOC_CNTL__REMOTE_FB_NOALLOC_NOPTE__SHIFT 0x1 |
12674 | #define GCMC_VM_FB_NOALLOC_CNTL__FB_NOALLOC_WALKER_FETCH__SHIFT 0x2 |
12675 | #define GCMC_VM_FB_NOALLOC_CNTL__ROUTER_ATCL2_NOALLOC__SHIFT 0x3 |
12676 | #define GCMC_VM_FB_NOALLOC_CNTL__ROUTER_GPA_MODE2_NOALLOC__SHIFT 0x4 |
12677 | #define GCMC_VM_FB_NOALLOC_CNTL__ROUTER_GPA_MODE3_NOALLOC__SHIFT 0x5 |
12678 | #define GCMC_VM_FB_NOALLOC_CNTL__LOCAL_FB_NOALLOC_NOPTE_MASK 0x00000001L |
12679 | #define GCMC_VM_FB_NOALLOC_CNTL__REMOTE_FB_NOALLOC_NOPTE_MASK 0x00000002L |
12680 | #define GCMC_VM_FB_NOALLOC_CNTL__FB_NOALLOC_WALKER_FETCH_MASK 0x00000004L |
12681 | #define GCMC_VM_FB_NOALLOC_CNTL__ROUTER_ATCL2_NOALLOC_MASK 0x00000008L |
12682 | #define GCMC_VM_FB_NOALLOC_CNTL__ROUTER_GPA_MODE2_NOALLOC_MASK 0x00000010L |
12683 | #define GCMC_VM_FB_NOALLOC_CNTL__ROUTER_GPA_MODE3_NOALLOC_MASK 0x00000020L |
12684 | //GCUTCL2_HARVEST_BYPASS_GROUPS |
12685 | #define GCUTCL2_HARVEST_BYPASS_GROUPS__BYPASS_GROUPS__SHIFT 0x0 |
12686 | #define GCUTCL2_HARVEST_BYPASS_GROUPS__BYPASS_GROUPS_MASK 0xFFFFFFFFL |
12687 | //GCUTCL2_GROUP_RET_FAULT_STATUS |
12688 | #define GCUTCL2_GROUP_RET_FAULT_STATUS__FAULT_GROUPS__SHIFT 0x0 |
12689 | #define GCUTCL2_GROUP_RET_FAULT_STATUS__FAULT_GROUPS_MASK 0xFFFFFFFFL |
12690 | |
12691 | |
12692 | // addressBlock: gc_gcvml2pfdec |
12693 | //GCVM_L2_CNTL |
12694 | #define GCVM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x0 |
12695 | #define GCVM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT 0x1 |
12696 | #define GCVM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT 0x2 |
12697 | #define GCVM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT 0x4 |
12698 | #define GCVM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT 0x8 |
12699 | #define GCVM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x9 |
12700 | #define GCVM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa |
12701 | #define GCVM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb |
12702 | #define GCVM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT 0xc |
12703 | #define GCVM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf |
12704 | #define GCVM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT 0x12 |
12705 | #define GCVM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT 0x13 |
12706 | #define GCVM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT 0x15 |
12707 | #define GCVM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE__SHIFT 0x1a |
12708 | #define GCVM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x00000001L |
12709 | #define GCVM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK 0x00000002L |
12710 | #define GCVM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK 0x0000000CL |
12711 | #define GCVM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK 0x00000030L |
12712 | #define GCVM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK 0x00000100L |
12713 | #define GCVM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000200L |
12714 | #define GCVM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000400L |
12715 | #define GCVM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L |
12716 | #define GCVM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK 0x00007000L |
12717 | #define GCVM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x00038000L |
12718 | #define GCVM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK 0x00040000L |
12719 | #define GCVM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK 0x00180000L |
12720 | #define GCVM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK 0x03E00000L |
12721 | #define GCVM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE_MASK 0x0C000000L |
12722 | //GCVM_L2_CNTL2 |
12723 | #define GCVM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT 0x0 |
12724 | #define GCVM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT 0x1 |
12725 | #define GCVM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x15 |
12726 | #define GCVM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT 0x16 |
12727 | #define GCVM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE__SHIFT 0x17 |
12728 | #define GCVM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT 0x1a |
12729 | #define GCVM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 0x1c |
12730 | #define GCVM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK 0x00000001L |
12731 | #define GCVM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK 0x00000002L |
12732 | #define GCVM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x00200000L |
12733 | #define GCVM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK 0x00400000L |
12734 | #define GCVM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE_MASK 0x03800000L |
12735 | #define GCVM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK 0x0C000000L |
12736 | #define GCVM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK 0x70000000L |
12737 | //GCVM_L2_CNTL3 |
12738 | #define GCVM_L2_CNTL3__BANK_SELECT__SHIFT 0x0 |
12739 | #define GCVM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT 0x6 |
12740 | #define GCVM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x8 |
12741 | #define GCVM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0xf |
12742 | #define GCVM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT 0x14 |
12743 | #define GCVM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 0x15 |
12744 | #define GCVM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT 0x18 |
12745 | #define GCVM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT 0x1c |
12746 | #define GCVM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT 0x1d |
12747 | #define GCVM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT 0x1e |
12748 | #define GCVM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT 0x1f |
12749 | #define GCVM_L2_CNTL3__BANK_SELECT_MASK 0x0000003FL |
12750 | #define GCVM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L |
12751 | #define GCVM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x00001F00L |
12752 | #define GCVM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000F8000L |
12753 | #define GCVM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK 0x00100000L |
12754 | #define GCVM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 0x00E00000L |
12755 | #define GCVM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 0x0F000000L |
12756 | #define GCVM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK 0x10000000L |
12757 | #define GCVM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK 0x20000000L |
12758 | #define GCVM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK 0x40000000L |
12759 | #define GCVM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK 0x80000000L |
12760 | //GCVM_L2_STATUS |
12761 | #define GCVM_L2_STATUS__L2_BUSY__SHIFT 0x0 |
12762 | #define GCVM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT 0x1 |
12763 | #define GCVM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS__SHIFT 0x11 |
12764 | #define GCVM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS__SHIFT 0x12 |
12765 | #define GCVM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS__SHIFT 0x13 |
12766 | #define GCVM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS__SHIFT 0x14 |
12767 | #define GCVM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS__SHIFT 0x15 |
12768 | #define GCVM_L2_STATUS__L2_BUSY_MASK 0x00000001L |
12769 | #define GCVM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK 0x0001FFFEL |
12770 | #define GCVM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS_MASK 0x00020000L |
12771 | #define GCVM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS_MASK 0x00040000L |
12772 | #define GCVM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS_MASK 0x00080000L |
12773 | #define GCVM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS_MASK 0x00100000L |
12774 | #define GCVM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS_MASK 0x00200000L |
12775 | //GCVM_DUMMY_PAGE_FAULT_CNTL |
12776 | #define GCVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT 0x0 |
12777 | #define GCVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT 0x1 |
12778 | #define GCVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS__SHIFT 0x2 |
12779 | #define GCVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK 0x00000001L |
12780 | #define GCVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK 0x00000002L |
12781 | #define GCVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS_MASK 0x000000FCL |
12782 | //GCVM_DUMMY_PAGE_FAULT_ADDR_LO32 |
12783 | #define GCVM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32__SHIFT 0x0 |
12784 | #define GCVM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL |
12785 | //GCVM_DUMMY_PAGE_FAULT_ADDR_HI32 |
12786 | #define GCVM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4__SHIFT 0x0 |
12787 | #define GCVM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4_MASK 0x0000000FL |
12788 | //GCVM_INVALIDATE_CNTL |
12789 | #define GCVM_INVALIDATE_CNTL__PRI_REG_ALTERNATING__SHIFT 0x0 |
12790 | #define GCVM_INVALIDATE_CNTL__MAX_REG_OUTSTANDING__SHIFT 0x8 |
12791 | #define GCVM_INVALIDATE_CNTL__PRI_REG_ALTERNATING_MASK 0x000000FFL |
12792 | #define GCVM_INVALIDATE_CNTL__MAX_REG_OUTSTANDING_MASK 0x0000FF00L |
12793 | //GCVM_L2_PROTECTION_FAULT_CNTL |
12794 | #define GCVM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0 |
12795 | #define GCVM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x1 |
12796 | #define GCVM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x2 |
12797 | #define GCVM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x3 |
12798 | #define GCVM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4 |
12799 | #define GCVM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x5 |
12800 | #define GCVM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x6 |
12801 | #define GCVM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7 |
12802 | #define GCVM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x8 |
12803 | #define GCVM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x9 |
12804 | #define GCVM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
12805 | #define GCVM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb |
12806 | #define GCVM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
12807 | #define GCVM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0xd |
12808 | #define GCVM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x1d |
12809 | #define GCVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT__SHIFT 0x1e |
12810 | #define GCVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT__SHIFT 0x1f |
12811 | #define GCVM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00000001L |
12812 | #define GCVM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x00000002L |
12813 | #define GCVM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000004L |
12814 | #define GCVM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000008L |
12815 | #define GCVM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000010L |
12816 | #define GCVM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000020L |
12817 | #define GCVM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000040L |
12818 | #define GCVM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000080L |
12819 | #define GCVM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000100L |
12820 | #define GCVM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000200L |
12821 | #define GCVM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
12822 | #define GCVM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L |
12823 | #define GCVM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
12824 | #define GCVM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x1FFFE000L |
12825 | #define GCVM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x20000000L |
12826 | #define GCVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT_MASK 0x40000000L |
12827 | #define GCVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT_MASK 0x80000000L |
12828 | //GCVM_L2_PROTECTION_FAULT_CNTL2 |
12829 | #define GCVM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x0 |
12830 | #define GCVM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x10 |
12831 | #define GCVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE__SHIFT 0x11 |
12832 | #define GCVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY__SHIFT 0x12 |
12833 | #define GCVM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT__SHIFT 0x13 |
12834 | #define GCVM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x0000FFFFL |
12835 | #define GCVM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x00010000L |
12836 | #define GCVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_MASK 0x00020000L |
12837 | #define GCVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY_MASK 0x00040000L |
12838 | #define GCVM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT_MASK 0x00080000L |
12839 | //GCVM_L2_PROTECTION_FAULT_MM_CNTL3 |
12840 | #define GCVM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0 |
12841 | #define GCVM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL |
12842 | //GCVM_L2_PROTECTION_FAULT_MM_CNTL4 |
12843 | #define GCVM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0 |
12844 | #define GCVM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL |
12845 | //GCVM_L2_PROTECTION_FAULT_STATUS |
12846 | #define GCVM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS__SHIFT 0x0 |
12847 | #define GCVM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR__SHIFT 0x1 |
12848 | #define GCVM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS__SHIFT 0x4 |
12849 | #define GCVM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR__SHIFT 0x8 |
12850 | #define GCVM_L2_PROTECTION_FAULT_STATUS__CID__SHIFT 0x9 |
12851 | #define GCVM_L2_PROTECTION_FAULT_STATUS__RW__SHIFT 0x12 |
12852 | #define GCVM_L2_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT 0x13 |
12853 | #define GCVM_L2_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x14 |
12854 | #define GCVM_L2_PROTECTION_FAULT_STATUS__VF__SHIFT 0x18 |
12855 | #define GCVM_L2_PROTECTION_FAULT_STATUS__VFID__SHIFT 0x19 |
12856 | #define GCVM_L2_PROTECTION_FAULT_STATUS__PRT__SHIFT 0x1d |
12857 | #define GCVM_L2_PROTECTION_FAULT_STATUS__FED__SHIFT 0x1e |
12858 | #define GCVM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS_MASK 0x00000001L |
12859 | #define GCVM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR_MASK 0x0000000EL |
12860 | #define GCVM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS_MASK 0x000000F0L |
12861 | #define GCVM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR_MASK 0x00000100L |
12862 | #define GCVM_L2_PROTECTION_FAULT_STATUS__CID_MASK 0x0003FE00L |
12863 | #define GCVM_L2_PROTECTION_FAULT_STATUS__RW_MASK 0x00040000L |
12864 | #define GCVM_L2_PROTECTION_FAULT_STATUS__ATOMIC_MASK 0x00080000L |
12865 | #define GCVM_L2_PROTECTION_FAULT_STATUS__VMID_MASK 0x00F00000L |
12866 | #define GCVM_L2_PROTECTION_FAULT_STATUS__VF_MASK 0x01000000L |
12867 | #define GCVM_L2_PROTECTION_FAULT_STATUS__VFID_MASK 0x1E000000L |
12868 | #define GCVM_L2_PROTECTION_FAULT_STATUS__PRT_MASK 0x20000000L |
12869 | #define GCVM_L2_PROTECTION_FAULT_STATUS__FED_MASK 0x40000000L |
12870 | //GCVM_L2_PROTECTION_FAULT_ADDR_LO32 |
12871 | #define GCVM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT 0x0 |
12872 | #define GCVM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL |
12873 | //GCVM_L2_PROTECTION_FAULT_ADDR_HI32 |
12874 | #define GCVM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT 0x0 |
12875 | #define GCVM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK 0x0000000FL |
12876 | //GCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 |
12877 | #define GCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32__SHIFT 0x0 |
12878 | #define GCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL |
12879 | //GCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 |
12880 | #define GCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4__SHIFT 0x0 |
12881 | #define GCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4_MASK 0x0000000FL |
12882 | //GCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 |
12883 | #define GCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
12884 | #define GCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
12885 | //GCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 |
12886 | #define GCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
12887 | #define GCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
12888 | //GCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 |
12889 | #define GCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
12890 | #define GCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
12891 | //GCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 |
12892 | #define GCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
12893 | #define GCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
12894 | //GCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 |
12895 | #define GCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32__SHIFT 0x0 |
12896 | #define GCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32_MASK 0xFFFFFFFFL |
12897 | //GCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 |
12898 | #define GCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4__SHIFT 0x0 |
12899 | #define GCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4_MASK 0x0000000FL |
12900 | //GCVM_L2_CNTL4 |
12901 | #define GCVM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT 0x0 |
12902 | #define GCVM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL__SHIFT 0x6 |
12903 | #define GCVM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL__SHIFT 0x7 |
12904 | #define GCVM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x8 |
12905 | #define GCVM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x12 |
12906 | #define GCVM_L2_CNTL4__BPM_CGCGLS_OVERRIDE__SHIFT 0x1c |
12907 | #define GCVM_L2_CNTL4__GC_CH_FGCG_OFF__SHIFT 0x1d |
12908 | #define GCVM_L2_CNTL4__VFIFO_HEAD_OF_QUEUE__SHIFT 0x1e |
12909 | #define GCVM_L2_CNTL4__VFIFO_VISIBLE_BANK_SILOS__SHIFT 0x1f |
12910 | #define GCVM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK 0x0000003FL |
12911 | #define GCVM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL_MASK 0x00000040L |
12912 | #define GCVM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL_MASK 0x00000080L |
12913 | #define GCVM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0003FF00L |
12914 | #define GCVM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0FFC0000L |
12915 | #define GCVM_L2_CNTL4__BPM_CGCGLS_OVERRIDE_MASK 0x10000000L |
12916 | #define GCVM_L2_CNTL4__GC_CH_FGCG_OFF_MASK 0x20000000L |
12917 | #define GCVM_L2_CNTL4__VFIFO_HEAD_OF_QUEUE_MASK 0x40000000L |
12918 | #define GCVM_L2_CNTL4__VFIFO_VISIBLE_BANK_SILOS_MASK 0x80000000L |
12919 | //GCVM_L2_MM_GROUP_RT_CLASSES |
12920 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS__SHIFT 0x0 |
12921 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS__SHIFT 0x1 |
12922 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS__SHIFT 0x2 |
12923 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS__SHIFT 0x3 |
12924 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS__SHIFT 0x4 |
12925 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS__SHIFT 0x5 |
12926 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS__SHIFT 0x6 |
12927 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS__SHIFT 0x7 |
12928 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS__SHIFT 0x8 |
12929 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS__SHIFT 0x9 |
12930 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS__SHIFT 0xa |
12931 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS__SHIFT 0xb |
12932 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS__SHIFT 0xc |
12933 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS__SHIFT 0xd |
12934 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS__SHIFT 0xe |
12935 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS__SHIFT 0xf |
12936 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS__SHIFT 0x10 |
12937 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS__SHIFT 0x11 |
12938 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS__SHIFT 0x12 |
12939 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS__SHIFT 0x13 |
12940 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS__SHIFT 0x14 |
12941 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS__SHIFT 0x15 |
12942 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS__SHIFT 0x16 |
12943 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS__SHIFT 0x17 |
12944 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS__SHIFT 0x18 |
12945 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS__SHIFT 0x19 |
12946 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS__SHIFT 0x1a |
12947 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS__SHIFT 0x1b |
12948 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS__SHIFT 0x1c |
12949 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS__SHIFT 0x1d |
12950 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS__SHIFT 0x1e |
12951 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS__SHIFT 0x1f |
12952 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS_MASK 0x00000001L |
12953 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS_MASK 0x00000002L |
12954 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS_MASK 0x00000004L |
12955 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS_MASK 0x00000008L |
12956 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS_MASK 0x00000010L |
12957 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS_MASK 0x00000020L |
12958 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS_MASK 0x00000040L |
12959 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS_MASK 0x00000080L |
12960 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS_MASK 0x00000100L |
12961 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS_MASK 0x00000200L |
12962 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS_MASK 0x00000400L |
12963 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS_MASK 0x00000800L |
12964 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS_MASK 0x00001000L |
12965 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS_MASK 0x00002000L |
12966 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS_MASK 0x00004000L |
12967 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS_MASK 0x00008000L |
12968 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS_MASK 0x00010000L |
12969 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS_MASK 0x00020000L |
12970 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS_MASK 0x00040000L |
12971 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS_MASK 0x00080000L |
12972 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS_MASK 0x00100000L |
12973 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS_MASK 0x00200000L |
12974 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS_MASK 0x00400000L |
12975 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS_MASK 0x00800000L |
12976 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS_MASK 0x01000000L |
12977 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS_MASK 0x02000000L |
12978 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS_MASK 0x04000000L |
12979 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS_MASK 0x08000000L |
12980 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS_MASK 0x10000000L |
12981 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS_MASK 0x20000000L |
12982 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS_MASK 0x40000000L |
12983 | #define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS_MASK 0x80000000L |
12984 | //GCVM_L2_BANK_SELECT_RESERVED_CID |
12985 | #define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID__SHIFT 0x0 |
12986 | #define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa |
12987 | #define GCVM_L2_BANK_SELECT_RESERVED_CID__ENABLE__SHIFT 0x14 |
12988 | #define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18 |
12989 | #define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19 |
12990 | #define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_FRAGMENT_SIZE__SHIFT 0x1a |
12991 | #define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL |
12992 | #define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L |
12993 | #define GCVM_L2_BANK_SELECT_RESERVED_CID__ENABLE_MASK 0x00100000L |
12994 | #define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L |
12995 | #define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L |
12996 | #define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_FRAGMENT_SIZE_MASK 0x7C000000L |
12997 | //GCVM_L2_BANK_SELECT_RESERVED_CID2 |
12998 | #define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID__SHIFT 0x0 |
12999 | #define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa |
13000 | #define GCVM_L2_BANK_SELECT_RESERVED_CID2__ENABLE__SHIFT 0x14 |
13001 | #define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18 |
13002 | #define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19 |
13003 | #define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_FRAGMENT_SIZE__SHIFT 0x1a |
13004 | #define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL |
13005 | #define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L |
13006 | #define GCVM_L2_BANK_SELECT_RESERVED_CID2__ENABLE_MASK 0x00100000L |
13007 | #define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L |
13008 | #define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L |
13009 | #define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_FRAGMENT_SIZE_MASK 0x7C000000L |
13010 | //GCVM_L2_CACHE_PARITY_CNTL |
13011 | #define GCVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES__SHIFT 0x0 |
13012 | #define GCVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES__SHIFT 0x1 |
13013 | #define GCVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES__SHIFT 0x2 |
13014 | #define GCVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE__SHIFT 0x3 |
13015 | #define GCVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE__SHIFT 0x4 |
13016 | #define GCVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE__SHIFT 0x5 |
13017 | #define GCVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK__SHIFT 0x6 |
13018 | #define GCVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER__SHIFT 0x9 |
13019 | #define GCVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC__SHIFT 0xc |
13020 | #define GCVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES_MASK 0x00000001L |
13021 | #define GCVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES_MASK 0x00000002L |
13022 | #define GCVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES_MASK 0x00000004L |
13023 | #define GCVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE_MASK 0x00000008L |
13024 | #define GCVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE_MASK 0x00000010L |
13025 | #define GCVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE_MASK 0x00000020L |
13026 | #define GCVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK_MASK 0x000001C0L |
13027 | #define GCVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER_MASK 0x00000E00L |
13028 | #define GCVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC_MASK 0x0000F000L |
13029 | //GCVM_L2_ICG_CTRL |
13030 | #define GCVM_L2_ICG_CTRL__OFF_HYSTERESIS__SHIFT 0x0 |
13031 | #define GCVM_L2_ICG_CTRL__DYNAMIC_CLOCK_OVERRIDE__SHIFT 0x4 |
13032 | #define GCVM_L2_ICG_CTRL__STATIC_CLOCK_OVERRIDE__SHIFT 0x5 |
13033 | #define GCVM_L2_ICG_CTRL__AON_CLOCK_OVERRIDE__SHIFT 0x6 |
13034 | #define GCVM_L2_ICG_CTRL__PERFMON_CLOCK_OVERRIDE__SHIFT 0x7 |
13035 | #define GCVM_L2_ICG_CTRL__OFF_HYSTERESIS_MASK 0x0000000FL |
13036 | #define GCVM_L2_ICG_CTRL__DYNAMIC_CLOCK_OVERRIDE_MASK 0x00000010L |
13037 | #define GCVM_L2_ICG_CTRL__STATIC_CLOCK_OVERRIDE_MASK 0x00000020L |
13038 | #define GCVM_L2_ICG_CTRL__AON_CLOCK_OVERRIDE_MASK 0x00000040L |
13039 | #define GCVM_L2_ICG_CTRL__PERFMON_CLOCK_OVERRIDE_MASK 0x00000080L |
13040 | //GCVM_L2_CNTL5 |
13041 | #define GCVM_L2_CNTL5__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 |
13042 | #define GCVM_L2_CNTL5__WALKER_PRIORITY_CLIENT_ID__SHIFT 0x5 |
13043 | #define GCVM_L2_CNTL5__WALKER_FETCH_PDE_NOALLOC_ENABLE__SHIFT 0xe |
13044 | #define GCVM_L2_CNTL5__WALKER_FETCH_PDE_MTYPE_ENABLE__SHIFT 0xf |
13045 | #define GCVM_L2_CNTL5__UTCL2_ATC_REQ_FGCG_OFF__SHIFT 0x10 |
13046 | #define GCVM_L2_CNTL5__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL |
13047 | #define GCVM_L2_CNTL5__WALKER_PRIORITY_CLIENT_ID_MASK 0x00003FE0L |
13048 | #define GCVM_L2_CNTL5__WALKER_FETCH_PDE_NOALLOC_ENABLE_MASK 0x00004000L |
13049 | #define GCVM_L2_CNTL5__WALKER_FETCH_PDE_MTYPE_ENABLE_MASK 0x00008000L |
13050 | #define GCVM_L2_CNTL5__UTCL2_ATC_REQ_FGCG_OFF_MASK 0x00010000L |
13051 | //GCVM_L2_GCR_CNTL |
13052 | #define GCVM_L2_GCR_CNTL__GCR_ENABLE__SHIFT 0x0 |
13053 | #define GCVM_L2_GCR_CNTL__GCR_CLIENT_ID__SHIFT 0x1 |
13054 | #define GCVM_L2_GCR_CNTL__GCR_ENABLE_MASK 0x00000001L |
13055 | #define GCVM_L2_GCR_CNTL__GCR_CLIENT_ID_MASK 0x000003FEL |
13056 | //GCVML2_WALKER_MACRO_THROTTLE_TIME |
13057 | #define GCVML2_WALKER_MACRO_THROTTLE_TIME__TIME__SHIFT 0x0 |
13058 | #define GCVML2_WALKER_MACRO_THROTTLE_TIME__TIME_MASK 0x00FFFFFFL |
13059 | //GCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT |
13060 | #define GCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT__LIMIT__SHIFT 0x1 |
13061 | #define GCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT__LIMIT_MASK 0x0000FFFEL |
13062 | //GCVML2_WALKER_MICRO_THROTTLE_TIME |
13063 | #define GCVML2_WALKER_MICRO_THROTTLE_TIME__TIME__SHIFT 0x0 |
13064 | #define GCVML2_WALKER_MICRO_THROTTLE_TIME__TIME_MASK 0x00FFFFFFL |
13065 | //GCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT |
13066 | #define GCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT__LIMIT__SHIFT 0x1 |
13067 | #define GCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT__LIMIT_MASK 0x0000FFFEL |
13068 | //GCVM_L2_CGTT_BUSY_CTRL |
13069 | #define GCVM_L2_CGTT_BUSY_CTRL__READ_DELAY__SHIFT 0x0 |
13070 | #define GCVM_L2_CGTT_BUSY_CTRL__ALWAYS_BUSY__SHIFT 0x5 |
13071 | #define GCVM_L2_CGTT_BUSY_CTRL__READ_DELAY_MASK 0x0000001FL |
13072 | #define GCVM_L2_CGTT_BUSY_CTRL__ALWAYS_BUSY_MASK 0x00000020L |
13073 | //GCVM_L2_PTE_CACHE_DUMP_CNTL |
13074 | #define GCVM_L2_PTE_CACHE_DUMP_CNTL__ENABLE__SHIFT 0x0 |
13075 | #define GCVM_L2_PTE_CACHE_DUMP_CNTL__READY__SHIFT 0x1 |
13076 | #define GCVM_L2_PTE_CACHE_DUMP_CNTL__BANK__SHIFT 0x4 |
13077 | #define GCVM_L2_PTE_CACHE_DUMP_CNTL__CACHE__SHIFT 0x8 |
13078 | #define GCVM_L2_PTE_CACHE_DUMP_CNTL__ASSOC__SHIFT 0xc |
13079 | #define GCVM_L2_PTE_CACHE_DUMP_CNTL__INDEX__SHIFT 0x10 |
13080 | #define GCVM_L2_PTE_CACHE_DUMP_CNTL__ENABLE_MASK 0x00000001L |
13081 | #define GCVM_L2_PTE_CACHE_DUMP_CNTL__READY_MASK 0x00000002L |
13082 | #define GCVM_L2_PTE_CACHE_DUMP_CNTL__BANK_MASK 0x000000F0L |
13083 | #define GCVM_L2_PTE_CACHE_DUMP_CNTL__CACHE_MASK 0x00000F00L |
13084 | #define GCVM_L2_PTE_CACHE_DUMP_CNTL__ASSOC_MASK 0x0000F000L |
13085 | #define GCVM_L2_PTE_CACHE_DUMP_CNTL__INDEX_MASK 0xFFFF0000L |
13086 | //GCVM_L2_PTE_CACHE_DUMP_READ |
13087 | #define GCVM_L2_PTE_CACHE_DUMP_READ__DATA__SHIFT 0x0 |
13088 | #define GCVM_L2_PTE_CACHE_DUMP_READ__DATA_MASK 0xFFFFFFFFL |
13089 | //GCVM_L2_BANK_SELECT_MASKS |
13090 | #define GCVM_L2_BANK_SELECT_MASKS__MASK0__SHIFT 0x0 |
13091 | #define GCVM_L2_BANK_SELECT_MASKS__MASK1__SHIFT 0x4 |
13092 | #define GCVM_L2_BANK_SELECT_MASKS__MASK2__SHIFT 0x8 |
13093 | #define GCVM_L2_BANK_SELECT_MASKS__MASK3__SHIFT 0xc |
13094 | #define GCVM_L2_BANK_SELECT_MASKS__MASK0_MASK 0x0000000FL |
13095 | #define GCVM_L2_BANK_SELECT_MASKS__MASK1_MASK 0x000000F0L |
13096 | #define GCVM_L2_BANK_SELECT_MASKS__MASK2_MASK 0x00000F00L |
13097 | #define GCVM_L2_BANK_SELECT_MASKS__MASK3_MASK 0x0000F000L |
13098 | //GCUTCL2_CREDIT_SAFETY_GROUP_RET_CDC |
13099 | #define GCUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__CREDITS__SHIFT 0x0 |
13100 | #define GCUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__UPDATE__SHIFT 0xa |
13101 | #define GCUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__CREDITS_MASK 0x000003FFL |
13102 | #define GCUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__UPDATE_MASK 0x00000400L |
13103 | //GCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC |
13104 | #define GCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__CREDITS__SHIFT 0x0 |
13105 | #define GCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__UPDATE__SHIFT 0xa |
13106 | #define GCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__CREDITS_MASK 0x000003FFL |
13107 | #define GCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__UPDATE_MASK 0x00000400L |
13108 | //GCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC |
13109 | #define GCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__CREDITS__SHIFT 0x0 |
13110 | #define GCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__UPDATE__SHIFT 0xa |
13111 | #define GCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__CREDITS_MASK 0x000003FFL |
13112 | #define GCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__UPDATE_MASK 0x00000400L |
13113 | //GCVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT |
13114 | #define GCVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__CREDITS__SHIFT 0x0 |
13115 | #define GCVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__UPDATE__SHIFT 0xa |
13116 | #define GCVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__CREDITS_MASK 0x000003FFL |
13117 | #define GCVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__UPDATE_MASK 0x00000400L |
13118 | //GCVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ |
13119 | #define GCVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__CREDITS__SHIFT 0x0 |
13120 | #define GCVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__UPDATE__SHIFT 0xa |
13121 | #define GCVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__CREDITS_MASK 0x000003FFL |
13122 | #define GCVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__UPDATE_MASK 0x00000400L |
13123 | |
13124 | |
13125 | // addressBlock: gc_gcatcl2dec |
13126 | //GC_ATC_L2_CNTL |
13127 | #define GC_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT 0x0 |
13128 | #define GC_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT 0x3 |
13129 | #define GC_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0x6 |
13130 | #define GC_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0x7 |
13131 | #define GC_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READ_REQUESTS__SHIFT 0x8 |
13132 | #define GC_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITE_REQUESTS__SHIFT 0xb |
13133 | #define GC_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0xe |
13134 | #define GC_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0xf |
13135 | #define GC_ATC_L2_CNTL__CACHE_INVALIDATE_MODE__SHIFT 0x10 |
13136 | #define GC_ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0x13 |
13137 | #define GC_ATC_L2_CNTL__FRAG_APT_INTXN_MODE__SHIFT 0x14 |
13138 | #define GC_ATC_L2_CNTL__CLI_GPA_REQ_FRAG_SIZE__SHIFT 0x16 |
13139 | #define GC_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK 0x00000003L |
13140 | #define GC_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK 0x00000018L |
13141 | #define GC_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x00000040L |
13142 | #define GC_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x00000080L |
13143 | #define GC_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READ_REQUESTS_MASK 0x00000300L |
13144 | #define GC_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITE_REQUESTS_MASK 0x00001800L |
13145 | #define GC_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x00004000L |
13146 | #define GC_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x00008000L |
13147 | #define GC_ATC_L2_CNTL__CACHE_INVALIDATE_MODE_MASK 0x00070000L |
13148 | #define GC_ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00080000L |
13149 | #define GC_ATC_L2_CNTL__FRAG_APT_INTXN_MODE_MASK 0x00300000L |
13150 | #define GC_ATC_L2_CNTL__CLI_GPA_REQ_FRAG_SIZE_MASK 0x0FC00000L |
13151 | //GC_ATC_L2_CNTL2 |
13152 | #define GC_ATC_L2_CNTL2__BANK_SELECT__SHIFT 0x0 |
13153 | #define GC_ATC_L2_CNTL2__NUM_BANKS_LOG2__SHIFT 0x6 |
13154 | #define GC_ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE__SHIFT 0x9 |
13155 | #define GC_ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xb |
13156 | #define GC_ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS__SHIFT 0xc |
13157 | #define GC_ATC_L2_CNTL2__L2_CACHE_VMID_MODE__SHIFT 0xf |
13158 | #define GC_ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x12 |
13159 | #define GC_ATC_L2_CNTL2__BANK_SELECT_MASK 0x0000003FL |
13160 | #define GC_ATC_L2_CNTL2__NUM_BANKS_LOG2_MASK 0x000001C0L |
13161 | #define GC_ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE_MASK 0x00000600L |
13162 | #define GC_ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000800L |
13163 | #define GC_ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS_MASK 0x00007000L |
13164 | #define GC_ATC_L2_CNTL2__L2_CACHE_VMID_MODE_MASK 0x00038000L |
13165 | #define GC_ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x00FC0000L |
13166 | //GC_ATC_L2_CACHE_DATA0 |
13167 | #define GC_ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID__SHIFT 0x0 |
13168 | #define GC_ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID__SHIFT 0x1 |
13169 | #define GC_ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES__SHIFT 0x2 |
13170 | #define GC_ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH__SHIFT 0x18 |
13171 | #define GC_ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID_MASK 0x00000001L |
13172 | #define GC_ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID_MASK 0x00000002L |
13173 | #define GC_ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES_MASK 0x00FFFFFCL |
13174 | #define GC_ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH_MASK 0x0F000000L |
13175 | //GC_ATC_L2_CACHE_DATA1 |
13176 | #define GC_ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW__SHIFT 0x0 |
13177 | #define GC_ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW_MASK 0xFFFFFFFFL |
13178 | //GC_ATC_L2_CACHE_DATA2 |
13179 | #define GC_ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS__SHIFT 0x0 |
13180 | #define GC_ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_MASK 0xFFFFFFFFL |
13181 | //GC_ATC_L2_CNTL3 |
13182 | #define GC_ATC_L2_CNTL3__L2_SMALLK_CACHE_FRAGMENT_SIZE__SHIFT 0x0 |
13183 | #define GC_ATC_L2_CNTL3__L2_MIDK_CACHE_FRAGMENT_SIZE__SHIFT 0x6 |
13184 | #define GC_ATC_L2_CNTL3__L2_BIGK_CACHE_FRAGMENT_SIZE__SHIFT 0xc |
13185 | #define GC_ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST__SHIFT 0x12 |
13186 | #define GC_ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1__SHIFT 0x15 |
13187 | #define GC_ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS__SHIFT 0x1b |
13188 | #define GC_ATC_L2_CNTL3__REPEATER_FGCG_OFF__SHIFT 0x1e |
13189 | #define GC_ATC_L2_CNTL3__L2_SMALLK_CACHE_FRAGMENT_SIZE_MASK 0x0000003FL |
13190 | #define GC_ATC_L2_CNTL3__L2_MIDK_CACHE_FRAGMENT_SIZE_MASK 0x00000FC0L |
13191 | #define GC_ATC_L2_CNTL3__L2_BIGK_CACHE_FRAGMENT_SIZE_MASK 0x0003F000L |
13192 | #define GC_ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST_MASK 0x001C0000L |
13193 | #define GC_ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1_MASK 0x07E00000L |
13194 | #define GC_ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS_MASK 0x38000000L |
13195 | #define GC_ATC_L2_CNTL3__REPEATER_FGCG_OFF_MASK 0x40000000L |
13196 | //GC_ATC_L2_STATUS |
13197 | #define GC_ATC_L2_STATUS__BUSY__SHIFT 0x0 |
13198 | #define GC_ATC_L2_STATUS__NO_OUTSTANDING_AT_REQUESTS__SHIFT 0x1 |
13199 | #define GC_ATC_L2_STATUS__BUSY_MASK 0x00000001L |
13200 | #define GC_ATC_L2_STATUS__NO_OUTSTANDING_AT_REQUESTS_MASK 0x00000002L |
13201 | //GC_ATC_L2_STATUS2 |
13202 | #define GC_ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO__SHIFT 0x0 |
13203 | #define GC_ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO__SHIFT 0x8 |
13204 | #define GC_ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO_MASK 0x000000FFL |
13205 | #define GC_ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO_MASK 0x0000FF00L |
13206 | //GC_ATC_L2_MISC_CG |
13207 | #define GC_ATC_L2_MISC_CG__OFFDLY__SHIFT 0x6 |
13208 | #define GC_ATC_L2_MISC_CG__ENABLE__SHIFT 0x12 |
13209 | #define GC_ATC_L2_MISC_CG__MEM_LS_ENABLE__SHIFT 0x13 |
13210 | #define GC_ATC_L2_MISC_CG__OFFDLY_MASK 0x00000FC0L |
13211 | #define GC_ATC_L2_MISC_CG__ENABLE_MASK 0x00040000L |
13212 | #define GC_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK 0x00080000L |
13213 | //GC_ATC_L2_MEM_POWER_LS |
13214 | #define GC_ATC_L2_MEM_POWER_LS__LS_SETUP__SHIFT 0x0 |
13215 | #define GC_ATC_L2_MEM_POWER_LS__LS_HOLD__SHIFT 0x6 |
13216 | #define GC_ATC_L2_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL |
13217 | #define GC_ATC_L2_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L |
13218 | //GC_ATC_L2_SDPPORT_CTRL |
13219 | #define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKEN__SHIFT 0x0 |
13220 | #define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKENRCV__SHIFT 0x1 |
13221 | #define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKEN__SHIFT 0x2 |
13222 | #define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKENRCV__SHIFT 0x3 |
13223 | #define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKEN__SHIFT 0x4 |
13224 | #define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKENRCV__SHIFT 0x5 |
13225 | #define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKEN__SHIFT 0x6 |
13226 | #define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKENRCV__SHIFT 0x7 |
13227 | #define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKEN__SHIFT 0x8 |
13228 | #define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKENRCV__SHIFT 0x9 |
13229 | #define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKEN_MASK 0x00000001L |
13230 | #define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKENRCV_MASK 0x00000002L |
13231 | #define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKEN_MASK 0x00000004L |
13232 | #define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKENRCV_MASK 0x00000008L |
13233 | #define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKEN_MASK 0x00000010L |
13234 | #define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKENRCV_MASK 0x00000020L |
13235 | #define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKEN_MASK 0x00000040L |
13236 | #define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKENRCV_MASK 0x00000080L |
13237 | #define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKEN_MASK 0x00000100L |
13238 | #define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKENRCV_MASK 0x00000200L |
13239 | |
13240 | |
13241 | // addressBlock: gc_gcl2tlbpfdec |
13242 | //GCL2TLB_TLB0_STATUS |
13243 | #define GCL2TLB_TLB0_STATUS__BUSY__SHIFT 0x0 |
13244 | #define GCL2TLB_TLB0_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 |
13245 | #define GCL2TLB_TLB0_STATUS__FOUND_APERTURE_FAULTS__SHIFT 0x2 |
13246 | #define GCL2TLB_TLB0_STATUS__BUSY_MASK 0x00000001L |
13247 | #define GCL2TLB_TLB0_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L |
13248 | #define GCL2TLB_TLB0_STATUS__FOUND_APERTURE_FAULTS_MASK 0x00000004L |
13249 | //GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO |
13250 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO__ADDR__SHIFT 0x0 |
13251 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO__ADDR_MASK 0xFFFFFFFFL |
13252 | //GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI |
13253 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__ADDR__SHIFT 0x0 |
13254 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VMID__SHIFT 0x4 |
13255 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VFID__SHIFT 0x8 |
13256 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VF__SHIFT 0xc |
13257 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__GPA__SHIFT 0xd |
13258 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__RD_PERM__SHIFT 0xf |
13259 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__WR_PERM__SHIFT 0x10 |
13260 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__EX_PERM__SHIFT 0x11 |
13261 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__CLIENT_ID__SHIFT 0x12 |
13262 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__REQ__SHIFT 0x1e |
13263 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__ADDR_MASK 0x0000000FL |
13264 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VMID_MASK 0x000000F0L |
13265 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VFID_MASK 0x00000F00L |
13266 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VF_MASK 0x00001000L |
13267 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__GPA_MASK 0x00006000L |
13268 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__RD_PERM_MASK 0x00008000L |
13269 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__WR_PERM_MASK 0x00010000L |
13270 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__EX_PERM_MASK 0x00020000L |
13271 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__CLIENT_ID_MASK 0x07FC0000L |
13272 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__REQ_MASK 0x40000000L |
13273 | //GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO |
13274 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO__ADDR__SHIFT 0x0 |
13275 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO__ADDR_MASK 0xFFFFFFFFL |
13276 | //GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI |
13277 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ADDR__SHIFT 0x0 |
13278 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PERMS__SHIFT 0x4 |
13279 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__FRAGMENT_SIZE__SHIFT 0x7 |
13280 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SNOOP__SHIFT 0xd |
13281 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SPA__SHIFT 0xe |
13282 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__IO__SHIFT 0xf |
13283 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PTE_TMZ__SHIFT 0x10 |
13284 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NO_PTE__SHIFT 0x11 |
13285 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MTYPE__SHIFT 0x12 |
13286 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MEMLOG__SHIFT 0x15 |
13287 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NACK__SHIFT 0x16 |
13288 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__LLC_NOALLOC__SHIFT 0x18 |
13289 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ACK__SHIFT 0x1f |
13290 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ADDR_MASK 0x0000000FL |
13291 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PERMS_MASK 0x00000070L |
13292 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__FRAGMENT_SIZE_MASK 0x00001F80L |
13293 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SNOOP_MASK 0x00002000L |
13294 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SPA_MASK 0x00004000L |
13295 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__IO_MASK 0x00008000L |
13296 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PTE_TMZ_MASK 0x00010000L |
13297 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NO_PTE_MASK 0x00020000L |
13298 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MTYPE_MASK 0x001C0000L |
13299 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MEMLOG_MASK 0x00200000L |
13300 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NACK_MASK 0x00C00000L |
13301 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__LLC_NOALLOC_MASK 0x01000000L |
13302 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ACK_MASK 0x80000000L |
13303 | |
13304 | |
13305 | // addressBlock: gc_gcvmsharedvcdec |
13306 | //GCMC_VM_FB_LOCATION_BASE |
13307 | #define GCMC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT 0x0 |
13308 | #define GCMC_VM_FB_LOCATION_BASE__FB_BASE_MASK 0x00FFFFFFL |
13309 | //GCMC_VM_FB_LOCATION_TOP |
13310 | #define GCMC_VM_FB_LOCATION_TOP__FB_TOP__SHIFT 0x0 |
13311 | #define GCMC_VM_FB_LOCATION_TOP__FB_TOP_MASK 0x00FFFFFFL |
13312 | //GCMC_VM_AGP_TOP |
13313 | #define GCMC_VM_AGP_TOP__AGP_TOP__SHIFT 0x0 |
13314 | #define GCMC_VM_AGP_TOP__AGP_TOP_MASK 0x00FFFFFFL |
13315 | //GCMC_VM_AGP_BOT |
13316 | #define GCMC_VM_AGP_BOT__AGP_BOT__SHIFT 0x0 |
13317 | #define GCMC_VM_AGP_BOT__AGP_BOT_MASK 0x00FFFFFFL |
13318 | //GCMC_VM_AGP_BASE |
13319 | #define GCMC_VM_AGP_BASE__AGP_BASE__SHIFT 0x0 |
13320 | #define GCMC_VM_AGP_BASE__AGP_BASE_MASK 0x00FFFFFFL |
13321 | //GCMC_VM_SYSTEM_APERTURE_LOW_ADDR |
13322 | #define GCMC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR__SHIFT 0x0 |
13323 | #define GCMC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL |
13324 | //GCMC_VM_SYSTEM_APERTURE_HIGH_ADDR |
13325 | #define GCMC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR__SHIFT 0x0 |
13326 | #define GCMC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL |
13327 | //GCMC_VM_MX_L1_TLB_CNTL |
13328 | #define GCMC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0 |
13329 | #define GCMC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3 |
13330 | #define GCMC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5 |
13331 | #define GCMC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6 |
13332 | #define GCMC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT 0x7 |
13333 | #define GCMC_VM_MX_L1_TLB_CNTL__MTYPE__SHIFT 0xb |
13334 | #define GCMC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L |
13335 | #define GCMC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L |
13336 | #define GCMC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L |
13337 | #define GCMC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L |
13338 | #define GCMC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK 0x00000780L |
13339 | #define GCMC_VM_MX_L1_TLB_CNTL__MTYPE_MASK 0x00003800L |
13340 | |
13341 | |
13342 | // addressBlock: gc_gcvml2vcdec |
13343 | //GCVM_CONTEXT0_CNTL |
13344 | #define GCVM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
13345 | #define GCVM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
13346 | #define GCVM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
13347 | #define GCVM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
13348 | #define GCVM_CONTEXT0_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
13349 | #define GCVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
13350 | #define GCVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
13351 | #define GCVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
13352 | #define GCVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
13353 | #define GCVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
13354 | #define GCVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
13355 | #define GCVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
13356 | #define GCVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
13357 | #define GCVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
13358 | #define GCVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
13359 | #define GCVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
13360 | #define GCVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
13361 | #define GCVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
13362 | #define GCVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
13363 | #define GCVM_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 |
13364 | #define GCVM_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 |
13365 | #define GCVM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
13366 | #define GCVM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
13367 | #define GCVM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
13368 | #define GCVM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
13369 | #define GCVM_CONTEXT0_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
13370 | #define GCVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
13371 | #define GCVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
13372 | #define GCVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
13373 | #define GCVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
13374 | #define GCVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
13375 | #define GCVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
13376 | #define GCVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
13377 | #define GCVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
13378 | #define GCVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
13379 | #define GCVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
13380 | #define GCVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
13381 | #define GCVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
13382 | #define GCVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
13383 | #define GCVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
13384 | #define GCVM_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L |
13385 | #define GCVM_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L |
13386 | //GCVM_CONTEXT1_CNTL |
13387 | #define GCVM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
13388 | #define GCVM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
13389 | #define GCVM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
13390 | #define GCVM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
13391 | #define GCVM_CONTEXT1_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
13392 | #define GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
13393 | #define GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
13394 | #define GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
13395 | #define GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
13396 | #define GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
13397 | #define GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
13398 | #define GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
13399 | #define GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
13400 | #define GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
13401 | #define GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
13402 | #define GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
13403 | #define GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
13404 | #define GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
13405 | #define GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
13406 | #define GCVM_CONTEXT1_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 |
13407 | #define GCVM_CONTEXT1_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 |
13408 | #define GCVM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
13409 | #define GCVM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
13410 | #define GCVM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
13411 | #define GCVM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
13412 | #define GCVM_CONTEXT1_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
13413 | #define GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
13414 | #define GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
13415 | #define GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
13416 | #define GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
13417 | #define GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
13418 | #define GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
13419 | #define GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
13420 | #define GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
13421 | #define GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
13422 | #define GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
13423 | #define GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
13424 | #define GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
13425 | #define GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
13426 | #define GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
13427 | #define GCVM_CONTEXT1_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L |
13428 | #define GCVM_CONTEXT1_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L |
13429 | //GCVM_CONTEXT2_CNTL |
13430 | #define GCVM_CONTEXT2_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
13431 | #define GCVM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
13432 | #define GCVM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
13433 | #define GCVM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
13434 | #define GCVM_CONTEXT2_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
13435 | #define GCVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
13436 | #define GCVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
13437 | #define GCVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
13438 | #define GCVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
13439 | #define GCVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
13440 | #define GCVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
13441 | #define GCVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
13442 | #define GCVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
13443 | #define GCVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
13444 | #define GCVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
13445 | #define GCVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
13446 | #define GCVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
13447 | #define GCVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
13448 | #define GCVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
13449 | #define GCVM_CONTEXT2_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 |
13450 | #define GCVM_CONTEXT2_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 |
13451 | #define GCVM_CONTEXT2_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
13452 | #define GCVM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
13453 | #define GCVM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
13454 | #define GCVM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
13455 | #define GCVM_CONTEXT2_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
13456 | #define GCVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
13457 | #define GCVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
13458 | #define GCVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
13459 | #define GCVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
13460 | #define GCVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
13461 | #define GCVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
13462 | #define GCVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
13463 | #define GCVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
13464 | #define GCVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
13465 | #define GCVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
13466 | #define GCVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
13467 | #define GCVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
13468 | #define GCVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
13469 | #define GCVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
13470 | #define GCVM_CONTEXT2_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L |
13471 | #define GCVM_CONTEXT2_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L |
13472 | //GCVM_CONTEXT3_CNTL |
13473 | #define GCVM_CONTEXT3_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
13474 | #define GCVM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
13475 | #define GCVM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
13476 | #define GCVM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
13477 | #define GCVM_CONTEXT3_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
13478 | #define GCVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
13479 | #define GCVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
13480 | #define GCVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
13481 | #define GCVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
13482 | #define GCVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
13483 | #define GCVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
13484 | #define GCVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
13485 | #define GCVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
13486 | #define GCVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
13487 | #define GCVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
13488 | #define GCVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
13489 | #define GCVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
13490 | #define GCVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
13491 | #define GCVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
13492 | #define GCVM_CONTEXT3_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 |
13493 | #define GCVM_CONTEXT3_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 |
13494 | #define GCVM_CONTEXT3_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
13495 | #define GCVM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
13496 | #define GCVM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
13497 | #define GCVM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
13498 | #define GCVM_CONTEXT3_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
13499 | #define GCVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
13500 | #define GCVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
13501 | #define GCVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
13502 | #define GCVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
13503 | #define GCVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
13504 | #define GCVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
13505 | #define GCVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
13506 | #define GCVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
13507 | #define GCVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
13508 | #define GCVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
13509 | #define GCVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
13510 | #define GCVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
13511 | #define GCVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
13512 | #define GCVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
13513 | #define GCVM_CONTEXT3_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L |
13514 | #define GCVM_CONTEXT3_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L |
13515 | //GCVM_CONTEXT4_CNTL |
13516 | #define GCVM_CONTEXT4_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
13517 | #define GCVM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
13518 | #define GCVM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
13519 | #define GCVM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
13520 | #define GCVM_CONTEXT4_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
13521 | #define GCVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
13522 | #define GCVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
13523 | #define GCVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
13524 | #define GCVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
13525 | #define GCVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
13526 | #define GCVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
13527 | #define GCVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
13528 | #define GCVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
13529 | #define GCVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
13530 | #define GCVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
13531 | #define GCVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
13532 | #define GCVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
13533 | #define GCVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
13534 | #define GCVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
13535 | #define GCVM_CONTEXT4_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 |
13536 | #define GCVM_CONTEXT4_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 |
13537 | #define GCVM_CONTEXT4_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
13538 | #define GCVM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
13539 | #define GCVM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
13540 | #define GCVM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
13541 | #define GCVM_CONTEXT4_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
13542 | #define GCVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
13543 | #define GCVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
13544 | #define GCVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
13545 | #define GCVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
13546 | #define GCVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
13547 | #define GCVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
13548 | #define GCVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
13549 | #define GCVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
13550 | #define GCVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
13551 | #define GCVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
13552 | #define GCVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
13553 | #define GCVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
13554 | #define GCVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
13555 | #define GCVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
13556 | #define GCVM_CONTEXT4_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L |
13557 | #define GCVM_CONTEXT4_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L |
13558 | //GCVM_CONTEXT5_CNTL |
13559 | #define GCVM_CONTEXT5_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
13560 | #define GCVM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
13561 | #define GCVM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
13562 | #define GCVM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
13563 | #define GCVM_CONTEXT5_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
13564 | #define GCVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
13565 | #define GCVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
13566 | #define GCVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
13567 | #define GCVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
13568 | #define GCVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
13569 | #define GCVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
13570 | #define GCVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
13571 | #define GCVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
13572 | #define GCVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
13573 | #define GCVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
13574 | #define GCVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
13575 | #define GCVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
13576 | #define GCVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
13577 | #define GCVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
13578 | #define GCVM_CONTEXT5_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 |
13579 | #define GCVM_CONTEXT5_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 |
13580 | #define GCVM_CONTEXT5_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
13581 | #define GCVM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
13582 | #define GCVM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
13583 | #define GCVM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
13584 | #define GCVM_CONTEXT5_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
13585 | #define GCVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
13586 | #define GCVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
13587 | #define GCVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
13588 | #define GCVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
13589 | #define GCVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
13590 | #define GCVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
13591 | #define GCVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
13592 | #define GCVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
13593 | #define GCVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
13594 | #define GCVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
13595 | #define GCVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
13596 | #define GCVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
13597 | #define GCVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
13598 | #define GCVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
13599 | #define GCVM_CONTEXT5_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L |
13600 | #define GCVM_CONTEXT5_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L |
13601 | //GCVM_CONTEXT6_CNTL |
13602 | #define GCVM_CONTEXT6_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
13603 | #define GCVM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
13604 | #define GCVM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
13605 | #define GCVM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
13606 | #define GCVM_CONTEXT6_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
13607 | #define GCVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
13608 | #define GCVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
13609 | #define GCVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
13610 | #define GCVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
13611 | #define GCVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
13612 | #define GCVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
13613 | #define GCVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
13614 | #define GCVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
13615 | #define GCVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
13616 | #define GCVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
13617 | #define GCVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
13618 | #define GCVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
13619 | #define GCVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
13620 | #define GCVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
13621 | #define GCVM_CONTEXT6_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 |
13622 | #define GCVM_CONTEXT6_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 |
13623 | #define GCVM_CONTEXT6_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
13624 | #define GCVM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
13625 | #define GCVM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
13626 | #define GCVM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
13627 | #define GCVM_CONTEXT6_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
13628 | #define GCVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
13629 | #define GCVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
13630 | #define GCVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
13631 | #define GCVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
13632 | #define GCVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
13633 | #define GCVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
13634 | #define GCVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
13635 | #define GCVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
13636 | #define GCVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
13637 | #define GCVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
13638 | #define GCVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
13639 | #define GCVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
13640 | #define GCVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
13641 | #define GCVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
13642 | #define GCVM_CONTEXT6_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L |
13643 | #define GCVM_CONTEXT6_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L |
13644 | //GCVM_CONTEXT7_CNTL |
13645 | #define GCVM_CONTEXT7_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
13646 | #define GCVM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
13647 | #define GCVM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
13648 | #define GCVM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
13649 | #define GCVM_CONTEXT7_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
13650 | #define GCVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
13651 | #define GCVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
13652 | #define GCVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
13653 | #define GCVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
13654 | #define GCVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
13655 | #define GCVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
13656 | #define GCVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
13657 | #define GCVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
13658 | #define GCVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
13659 | #define GCVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
13660 | #define GCVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
13661 | #define GCVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
13662 | #define GCVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
13663 | #define GCVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
13664 | #define GCVM_CONTEXT7_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 |
13665 | #define GCVM_CONTEXT7_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 |
13666 | #define GCVM_CONTEXT7_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
13667 | #define GCVM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
13668 | #define GCVM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
13669 | #define GCVM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
13670 | #define GCVM_CONTEXT7_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
13671 | #define GCVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
13672 | #define GCVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
13673 | #define GCVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
13674 | #define GCVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
13675 | #define GCVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
13676 | #define GCVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
13677 | #define GCVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
13678 | #define GCVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
13679 | #define GCVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
13680 | #define GCVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
13681 | #define GCVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
13682 | #define GCVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
13683 | #define GCVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
13684 | #define GCVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
13685 | #define GCVM_CONTEXT7_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L |
13686 | #define GCVM_CONTEXT7_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L |
13687 | //GCVM_CONTEXT8_CNTL |
13688 | #define GCVM_CONTEXT8_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
13689 | #define GCVM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
13690 | #define GCVM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
13691 | #define GCVM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
13692 | #define GCVM_CONTEXT8_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
13693 | #define GCVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
13694 | #define GCVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
13695 | #define GCVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
13696 | #define GCVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
13697 | #define GCVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
13698 | #define GCVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
13699 | #define GCVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
13700 | #define GCVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
13701 | #define GCVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
13702 | #define GCVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
13703 | #define GCVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
13704 | #define GCVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
13705 | #define GCVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
13706 | #define GCVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
13707 | #define GCVM_CONTEXT8_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 |
13708 | #define GCVM_CONTEXT8_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 |
13709 | #define GCVM_CONTEXT8_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
13710 | #define GCVM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
13711 | #define GCVM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
13712 | #define GCVM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
13713 | #define GCVM_CONTEXT8_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
13714 | #define GCVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
13715 | #define GCVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
13716 | #define GCVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
13717 | #define GCVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
13718 | #define GCVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
13719 | #define GCVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
13720 | #define GCVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
13721 | #define GCVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
13722 | #define GCVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
13723 | #define GCVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
13724 | #define GCVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
13725 | #define GCVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
13726 | #define GCVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
13727 | #define GCVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
13728 | #define GCVM_CONTEXT8_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L |
13729 | #define GCVM_CONTEXT8_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L |
13730 | //GCVM_CONTEXT9_CNTL |
13731 | #define GCVM_CONTEXT9_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
13732 | #define GCVM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
13733 | #define GCVM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
13734 | #define GCVM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
13735 | #define GCVM_CONTEXT9_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
13736 | #define GCVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
13737 | #define GCVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
13738 | #define GCVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
13739 | #define GCVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
13740 | #define GCVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
13741 | #define GCVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
13742 | #define GCVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
13743 | #define GCVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
13744 | #define GCVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
13745 | #define GCVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
13746 | #define GCVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
13747 | #define GCVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
13748 | #define GCVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
13749 | #define GCVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
13750 | #define GCVM_CONTEXT9_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 |
13751 | #define GCVM_CONTEXT9_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 |
13752 | #define GCVM_CONTEXT9_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
13753 | #define GCVM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
13754 | #define GCVM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
13755 | #define GCVM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
13756 | #define GCVM_CONTEXT9_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
13757 | #define GCVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
13758 | #define GCVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
13759 | #define GCVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
13760 | #define GCVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
13761 | #define GCVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
13762 | #define GCVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
13763 | #define GCVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
13764 | #define GCVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
13765 | #define GCVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
13766 | #define GCVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
13767 | #define GCVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
13768 | #define GCVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
13769 | #define GCVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
13770 | #define GCVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
13771 | #define GCVM_CONTEXT9_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L |
13772 | #define GCVM_CONTEXT9_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L |
13773 | //GCVM_CONTEXT10_CNTL |
13774 | #define GCVM_CONTEXT10_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
13775 | #define GCVM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
13776 | #define GCVM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
13777 | #define GCVM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
13778 | #define GCVM_CONTEXT10_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
13779 | #define GCVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
13780 | #define GCVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
13781 | #define GCVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
13782 | #define GCVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
13783 | #define GCVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
13784 | #define GCVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
13785 | #define GCVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
13786 | #define GCVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
13787 | #define GCVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
13788 | #define GCVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
13789 | #define GCVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
13790 | #define GCVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
13791 | #define GCVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
13792 | #define GCVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
13793 | #define GCVM_CONTEXT10_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 |
13794 | #define GCVM_CONTEXT10_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 |
13795 | #define GCVM_CONTEXT10_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
13796 | #define GCVM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
13797 | #define GCVM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
13798 | #define GCVM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
13799 | #define GCVM_CONTEXT10_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
13800 | #define GCVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
13801 | #define GCVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
13802 | #define GCVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
13803 | #define GCVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
13804 | #define GCVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
13805 | #define GCVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
13806 | #define GCVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
13807 | #define GCVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
13808 | #define GCVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
13809 | #define GCVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
13810 | #define GCVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
13811 | #define GCVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
13812 | #define GCVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
13813 | #define GCVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
13814 | #define GCVM_CONTEXT10_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L |
13815 | #define GCVM_CONTEXT10_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L |
13816 | //GCVM_CONTEXT11_CNTL |
13817 | #define GCVM_CONTEXT11_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
13818 | #define GCVM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
13819 | #define GCVM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
13820 | #define GCVM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
13821 | #define GCVM_CONTEXT11_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
13822 | #define GCVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
13823 | #define GCVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
13824 | #define GCVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
13825 | #define GCVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
13826 | #define GCVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
13827 | #define GCVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
13828 | #define GCVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
13829 | #define GCVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
13830 | #define GCVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
13831 | #define GCVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
13832 | #define GCVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
13833 | #define GCVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
13834 | #define GCVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
13835 | #define GCVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
13836 | #define GCVM_CONTEXT11_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 |
13837 | #define GCVM_CONTEXT11_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 |
13838 | #define GCVM_CONTEXT11_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
13839 | #define GCVM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
13840 | #define GCVM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
13841 | #define GCVM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
13842 | #define GCVM_CONTEXT11_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
13843 | #define GCVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
13844 | #define GCVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
13845 | #define GCVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
13846 | #define GCVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
13847 | #define GCVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
13848 | #define GCVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
13849 | #define GCVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
13850 | #define GCVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
13851 | #define GCVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
13852 | #define GCVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
13853 | #define GCVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
13854 | #define GCVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
13855 | #define GCVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
13856 | #define GCVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
13857 | #define GCVM_CONTEXT11_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L |
13858 | #define GCVM_CONTEXT11_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L |
13859 | //GCVM_CONTEXT12_CNTL |
13860 | #define GCVM_CONTEXT12_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
13861 | #define GCVM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
13862 | #define GCVM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
13863 | #define GCVM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
13864 | #define GCVM_CONTEXT12_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
13865 | #define GCVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
13866 | #define GCVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
13867 | #define GCVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
13868 | #define GCVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
13869 | #define GCVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
13870 | #define GCVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
13871 | #define GCVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
13872 | #define GCVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
13873 | #define GCVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
13874 | #define GCVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
13875 | #define GCVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
13876 | #define GCVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
13877 | #define GCVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
13878 | #define GCVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
13879 | #define GCVM_CONTEXT12_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 |
13880 | #define GCVM_CONTEXT12_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 |
13881 | #define GCVM_CONTEXT12_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
13882 | #define GCVM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
13883 | #define GCVM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
13884 | #define GCVM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
13885 | #define GCVM_CONTEXT12_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
13886 | #define GCVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
13887 | #define GCVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
13888 | #define GCVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
13889 | #define GCVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
13890 | #define GCVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
13891 | #define GCVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
13892 | #define GCVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
13893 | #define GCVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
13894 | #define GCVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
13895 | #define GCVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
13896 | #define GCVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
13897 | #define GCVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
13898 | #define GCVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
13899 | #define GCVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
13900 | #define GCVM_CONTEXT12_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L |
13901 | #define GCVM_CONTEXT12_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L |
13902 | //GCVM_CONTEXT13_CNTL |
13903 | #define GCVM_CONTEXT13_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
13904 | #define GCVM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
13905 | #define GCVM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
13906 | #define GCVM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
13907 | #define GCVM_CONTEXT13_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
13908 | #define GCVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
13909 | #define GCVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
13910 | #define GCVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
13911 | #define GCVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
13912 | #define GCVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
13913 | #define GCVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
13914 | #define GCVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
13915 | #define GCVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
13916 | #define GCVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
13917 | #define GCVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
13918 | #define GCVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
13919 | #define GCVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
13920 | #define GCVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
13921 | #define GCVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
13922 | #define GCVM_CONTEXT13_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 |
13923 | #define GCVM_CONTEXT13_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 |
13924 | #define GCVM_CONTEXT13_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
13925 | #define GCVM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
13926 | #define GCVM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
13927 | #define GCVM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
13928 | #define GCVM_CONTEXT13_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
13929 | #define GCVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
13930 | #define GCVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
13931 | #define GCVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
13932 | #define GCVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
13933 | #define GCVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
13934 | #define GCVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
13935 | #define GCVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
13936 | #define GCVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
13937 | #define GCVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
13938 | #define GCVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
13939 | #define GCVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
13940 | #define GCVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
13941 | #define GCVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
13942 | #define GCVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
13943 | #define GCVM_CONTEXT13_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L |
13944 | #define GCVM_CONTEXT13_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L |
13945 | //GCVM_CONTEXT14_CNTL |
13946 | #define GCVM_CONTEXT14_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
13947 | #define GCVM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
13948 | #define GCVM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
13949 | #define GCVM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
13950 | #define GCVM_CONTEXT14_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
13951 | #define GCVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
13952 | #define GCVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
13953 | #define GCVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
13954 | #define GCVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
13955 | #define GCVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
13956 | #define GCVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
13957 | #define GCVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
13958 | #define GCVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
13959 | #define GCVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
13960 | #define GCVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
13961 | #define GCVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
13962 | #define GCVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
13963 | #define GCVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
13964 | #define GCVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
13965 | #define GCVM_CONTEXT14_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 |
13966 | #define GCVM_CONTEXT14_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 |
13967 | #define GCVM_CONTEXT14_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
13968 | #define GCVM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
13969 | #define GCVM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
13970 | #define GCVM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
13971 | #define GCVM_CONTEXT14_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
13972 | #define GCVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
13973 | #define GCVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
13974 | #define GCVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
13975 | #define GCVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
13976 | #define GCVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
13977 | #define GCVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
13978 | #define GCVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
13979 | #define GCVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
13980 | #define GCVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
13981 | #define GCVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
13982 | #define GCVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
13983 | #define GCVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
13984 | #define GCVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
13985 | #define GCVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
13986 | #define GCVM_CONTEXT14_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L |
13987 | #define GCVM_CONTEXT14_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L |
13988 | //GCVM_CONTEXT15_CNTL |
13989 | #define GCVM_CONTEXT15_CNTL__ENABLE_CONTEXT__SHIFT 0x0 |
13990 | #define GCVM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 |
13991 | #define GCVM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 |
13992 | #define GCVM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 |
13993 | #define GCVM_CONTEXT15_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 |
13994 | #define GCVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 |
13995 | #define GCVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa |
13996 | #define GCVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb |
13997 | #define GCVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc |
13998 | #define GCVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd |
13999 | #define GCVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe |
14000 | #define GCVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf |
14001 | #define GCVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 |
14002 | #define GCVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 |
14003 | #define GCVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 |
14004 | #define GCVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 |
14005 | #define GCVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 |
14006 | #define GCVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 |
14007 | #define GCVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 |
14008 | #define GCVM_CONTEXT15_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x17 |
14009 | #define GCVM_CONTEXT15_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x18 |
14010 | #define GCVM_CONTEXT15_CNTL__ENABLE_CONTEXT_MASK 0x00000001L |
14011 | #define GCVM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L |
14012 | #define GCVM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L |
14013 | #define GCVM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L |
14014 | #define GCVM_CONTEXT15_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L |
14015 | #define GCVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L |
14016 | #define GCVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L |
14017 | #define GCVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L |
14018 | #define GCVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L |
14019 | #define GCVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L |
14020 | #define GCVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L |
14021 | #define GCVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L |
14022 | #define GCVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L |
14023 | #define GCVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L |
14024 | #define GCVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L |
14025 | #define GCVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L |
14026 | #define GCVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L |
14027 | #define GCVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L |
14028 | #define GCVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L |
14029 | #define GCVM_CONTEXT15_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00800000L |
14030 | #define GCVM_CONTEXT15_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x01000000L |
14031 | //GCVM_CONTEXTS_DISABLE |
14032 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT 0x0 |
14033 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT 0x1 |
14034 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT 0x2 |
14035 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT 0x3 |
14036 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT 0x4 |
14037 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT 0x5 |
14038 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT 0x6 |
14039 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT 0x7 |
14040 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT 0x8 |
14041 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT 0x9 |
14042 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT 0xa |
14043 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT 0xb |
14044 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT 0xc |
14045 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT 0xd |
14046 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT 0xe |
14047 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT 0xf |
14048 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK 0x00000001L |
14049 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK 0x00000002L |
14050 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK 0x00000004L |
14051 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK 0x00000008L |
14052 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK 0x00000010L |
14053 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK 0x00000020L |
14054 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK 0x00000040L |
14055 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK 0x00000080L |
14056 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK 0x00000100L |
14057 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK 0x00000200L |
14058 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK 0x00000400L |
14059 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK 0x00000800L |
14060 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK 0x00001000L |
14061 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK 0x00002000L |
14062 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK 0x00004000L |
14063 | #define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK 0x00008000L |
14064 | //GCVM_INVALIDATE_ENG0_SEM |
14065 | #define GCVM_INVALIDATE_ENG0_SEM__SEMAPHORE__SHIFT 0x0 |
14066 | #define GCVM_INVALIDATE_ENG0_SEM__SEMAPHORE_MASK 0x00000001L |
14067 | //GCVM_INVALIDATE_ENG1_SEM |
14068 | #define GCVM_INVALIDATE_ENG1_SEM__SEMAPHORE__SHIFT 0x0 |
14069 | #define GCVM_INVALIDATE_ENG1_SEM__SEMAPHORE_MASK 0x00000001L |
14070 | //GCVM_INVALIDATE_ENG2_SEM |
14071 | #define GCVM_INVALIDATE_ENG2_SEM__SEMAPHORE__SHIFT 0x0 |
14072 | #define GCVM_INVALIDATE_ENG2_SEM__SEMAPHORE_MASK 0x00000001L |
14073 | //GCVM_INVALIDATE_ENG3_SEM |
14074 | #define GCVM_INVALIDATE_ENG3_SEM__SEMAPHORE__SHIFT 0x0 |
14075 | #define GCVM_INVALIDATE_ENG3_SEM__SEMAPHORE_MASK 0x00000001L |
14076 | //GCVM_INVALIDATE_ENG4_SEM |
14077 | #define GCVM_INVALIDATE_ENG4_SEM__SEMAPHORE__SHIFT 0x0 |
14078 | #define GCVM_INVALIDATE_ENG4_SEM__SEMAPHORE_MASK 0x00000001L |
14079 | //GCVM_INVALIDATE_ENG5_SEM |
14080 | #define GCVM_INVALIDATE_ENG5_SEM__SEMAPHORE__SHIFT 0x0 |
14081 | #define GCVM_INVALIDATE_ENG5_SEM__SEMAPHORE_MASK 0x00000001L |
14082 | //GCVM_INVALIDATE_ENG6_SEM |
14083 | #define GCVM_INVALIDATE_ENG6_SEM__SEMAPHORE__SHIFT 0x0 |
14084 | #define GCVM_INVALIDATE_ENG6_SEM__SEMAPHORE_MASK 0x00000001L |
14085 | //GCVM_INVALIDATE_ENG7_SEM |
14086 | #define GCVM_INVALIDATE_ENG7_SEM__SEMAPHORE__SHIFT 0x0 |
14087 | #define GCVM_INVALIDATE_ENG7_SEM__SEMAPHORE_MASK 0x00000001L |
14088 | //GCVM_INVALIDATE_ENG8_SEM |
14089 | #define GCVM_INVALIDATE_ENG8_SEM__SEMAPHORE__SHIFT 0x0 |
14090 | #define GCVM_INVALIDATE_ENG8_SEM__SEMAPHORE_MASK 0x00000001L |
14091 | //GCVM_INVALIDATE_ENG9_SEM |
14092 | #define GCVM_INVALIDATE_ENG9_SEM__SEMAPHORE__SHIFT 0x0 |
14093 | #define GCVM_INVALIDATE_ENG9_SEM__SEMAPHORE_MASK 0x00000001L |
14094 | //GCVM_INVALIDATE_ENG10_SEM |
14095 | #define GCVM_INVALIDATE_ENG10_SEM__SEMAPHORE__SHIFT 0x0 |
14096 | #define GCVM_INVALIDATE_ENG10_SEM__SEMAPHORE_MASK 0x00000001L |
14097 | //GCVM_INVALIDATE_ENG11_SEM |
14098 | #define GCVM_INVALIDATE_ENG11_SEM__SEMAPHORE__SHIFT 0x0 |
14099 | #define GCVM_INVALIDATE_ENG11_SEM__SEMAPHORE_MASK 0x00000001L |
14100 | //GCVM_INVALIDATE_ENG12_SEM |
14101 | #define GCVM_INVALIDATE_ENG12_SEM__SEMAPHORE__SHIFT 0x0 |
14102 | #define GCVM_INVALIDATE_ENG12_SEM__SEMAPHORE_MASK 0x00000001L |
14103 | //GCVM_INVALIDATE_ENG13_SEM |
14104 | #define GCVM_INVALIDATE_ENG13_SEM__SEMAPHORE__SHIFT 0x0 |
14105 | #define GCVM_INVALIDATE_ENG13_SEM__SEMAPHORE_MASK 0x00000001L |
14106 | //GCVM_INVALIDATE_ENG14_SEM |
14107 | #define GCVM_INVALIDATE_ENG14_SEM__SEMAPHORE__SHIFT 0x0 |
14108 | #define GCVM_INVALIDATE_ENG14_SEM__SEMAPHORE_MASK 0x00000001L |
14109 | //GCVM_INVALIDATE_ENG15_SEM |
14110 | #define GCVM_INVALIDATE_ENG15_SEM__SEMAPHORE__SHIFT 0x0 |
14111 | #define GCVM_INVALIDATE_ENG15_SEM__SEMAPHORE_MASK 0x00000001L |
14112 | //GCVM_INVALIDATE_ENG16_SEM |
14113 | #define GCVM_INVALIDATE_ENG16_SEM__SEMAPHORE__SHIFT 0x0 |
14114 | #define GCVM_INVALIDATE_ENG16_SEM__SEMAPHORE_MASK 0x00000001L |
14115 | //GCVM_INVALIDATE_ENG17_SEM |
14116 | #define GCVM_INVALIDATE_ENG17_SEM__SEMAPHORE__SHIFT 0x0 |
14117 | #define GCVM_INVALIDATE_ENG17_SEM__SEMAPHORE_MASK 0x00000001L |
14118 | //GCVM_INVALIDATE_ENG0_REQ |
14119 | #define GCVM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
14120 | #define GCVM_INVALIDATE_ENG0_REQ__FLUSH_TYPE__SHIFT 0x10 |
14121 | #define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 |
14122 | #define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 |
14123 | #define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 |
14124 | #define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 |
14125 | #define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 |
14126 | #define GCVM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 |
14127 | #define GCVM_INVALIDATE_ENG0_REQ__LOG_REQUEST__SHIFT 0x19 |
14128 | #define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a |
14129 | #define GCVM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
14130 | #define GCVM_INVALIDATE_ENG0_REQ__FLUSH_TYPE_MASK 0x00070000L |
14131 | #define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L |
14132 | #define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L |
14133 | #define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L |
14134 | #define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L |
14135 | #define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L |
14136 | #define GCVM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L |
14137 | #define GCVM_INVALIDATE_ENG0_REQ__LOG_REQUEST_MASK 0x02000000L |
14138 | #define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L |
14139 | //GCVM_INVALIDATE_ENG1_REQ |
14140 | #define GCVM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
14141 | #define GCVM_INVALIDATE_ENG1_REQ__FLUSH_TYPE__SHIFT 0x10 |
14142 | #define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 |
14143 | #define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 |
14144 | #define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 |
14145 | #define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 |
14146 | #define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 |
14147 | #define GCVM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 |
14148 | #define GCVM_INVALIDATE_ENG1_REQ__LOG_REQUEST__SHIFT 0x19 |
14149 | #define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a |
14150 | #define GCVM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
14151 | #define GCVM_INVALIDATE_ENG1_REQ__FLUSH_TYPE_MASK 0x00070000L |
14152 | #define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L |
14153 | #define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L |
14154 | #define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L |
14155 | #define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L |
14156 | #define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L |
14157 | #define GCVM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L |
14158 | #define GCVM_INVALIDATE_ENG1_REQ__LOG_REQUEST_MASK 0x02000000L |
14159 | #define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L |
14160 | //GCVM_INVALIDATE_ENG2_REQ |
14161 | #define GCVM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
14162 | #define GCVM_INVALIDATE_ENG2_REQ__FLUSH_TYPE__SHIFT 0x10 |
14163 | #define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 |
14164 | #define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 |
14165 | #define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 |
14166 | #define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 |
14167 | #define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 |
14168 | #define GCVM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 |
14169 | #define GCVM_INVALIDATE_ENG2_REQ__LOG_REQUEST__SHIFT 0x19 |
14170 | #define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a |
14171 | #define GCVM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
14172 | #define GCVM_INVALIDATE_ENG2_REQ__FLUSH_TYPE_MASK 0x00070000L |
14173 | #define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L |
14174 | #define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L |
14175 | #define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L |
14176 | #define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L |
14177 | #define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L |
14178 | #define GCVM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L |
14179 | #define GCVM_INVALIDATE_ENG2_REQ__LOG_REQUEST_MASK 0x02000000L |
14180 | #define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L |
14181 | //GCVM_INVALIDATE_ENG3_REQ |
14182 | #define GCVM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
14183 | #define GCVM_INVALIDATE_ENG3_REQ__FLUSH_TYPE__SHIFT 0x10 |
14184 | #define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 |
14185 | #define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 |
14186 | #define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 |
14187 | #define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 |
14188 | #define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 |
14189 | #define GCVM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 |
14190 | #define GCVM_INVALIDATE_ENG3_REQ__LOG_REQUEST__SHIFT 0x19 |
14191 | #define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a |
14192 | #define GCVM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
14193 | #define GCVM_INVALIDATE_ENG3_REQ__FLUSH_TYPE_MASK 0x00070000L |
14194 | #define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L |
14195 | #define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L |
14196 | #define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L |
14197 | #define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L |
14198 | #define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L |
14199 | #define GCVM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L |
14200 | #define GCVM_INVALIDATE_ENG3_REQ__LOG_REQUEST_MASK 0x02000000L |
14201 | #define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L |
14202 | //GCVM_INVALIDATE_ENG4_REQ |
14203 | #define GCVM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
14204 | #define GCVM_INVALIDATE_ENG4_REQ__FLUSH_TYPE__SHIFT 0x10 |
14205 | #define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 |
14206 | #define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 |
14207 | #define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 |
14208 | #define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 |
14209 | #define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 |
14210 | #define GCVM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 |
14211 | #define GCVM_INVALIDATE_ENG4_REQ__LOG_REQUEST__SHIFT 0x19 |
14212 | #define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a |
14213 | #define GCVM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
14214 | #define GCVM_INVALIDATE_ENG4_REQ__FLUSH_TYPE_MASK 0x00070000L |
14215 | #define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L |
14216 | #define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L |
14217 | #define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L |
14218 | #define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L |
14219 | #define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L |
14220 | #define GCVM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L |
14221 | #define GCVM_INVALIDATE_ENG4_REQ__LOG_REQUEST_MASK 0x02000000L |
14222 | #define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L |
14223 | //GCVM_INVALIDATE_ENG5_REQ |
14224 | #define GCVM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
14225 | #define GCVM_INVALIDATE_ENG5_REQ__FLUSH_TYPE__SHIFT 0x10 |
14226 | #define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 |
14227 | #define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 |
14228 | #define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 |
14229 | #define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 |
14230 | #define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 |
14231 | #define GCVM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 |
14232 | #define GCVM_INVALIDATE_ENG5_REQ__LOG_REQUEST__SHIFT 0x19 |
14233 | #define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a |
14234 | #define GCVM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
14235 | #define GCVM_INVALIDATE_ENG5_REQ__FLUSH_TYPE_MASK 0x00070000L |
14236 | #define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L |
14237 | #define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L |
14238 | #define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L |
14239 | #define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L |
14240 | #define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L |
14241 | #define GCVM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L |
14242 | #define GCVM_INVALIDATE_ENG5_REQ__LOG_REQUEST_MASK 0x02000000L |
14243 | #define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L |
14244 | //GCVM_INVALIDATE_ENG6_REQ |
14245 | #define GCVM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
14246 | #define GCVM_INVALIDATE_ENG6_REQ__FLUSH_TYPE__SHIFT 0x10 |
14247 | #define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 |
14248 | #define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 |
14249 | #define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 |
14250 | #define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 |
14251 | #define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 |
14252 | #define GCVM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 |
14253 | #define GCVM_INVALIDATE_ENG6_REQ__LOG_REQUEST__SHIFT 0x19 |
14254 | #define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a |
14255 | #define GCVM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
14256 | #define GCVM_INVALIDATE_ENG6_REQ__FLUSH_TYPE_MASK 0x00070000L |
14257 | #define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L |
14258 | #define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L |
14259 | #define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L |
14260 | #define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L |
14261 | #define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L |
14262 | #define GCVM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L |
14263 | #define GCVM_INVALIDATE_ENG6_REQ__LOG_REQUEST_MASK 0x02000000L |
14264 | #define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L |
14265 | //GCVM_INVALIDATE_ENG7_REQ |
14266 | #define GCVM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
14267 | #define GCVM_INVALIDATE_ENG7_REQ__FLUSH_TYPE__SHIFT 0x10 |
14268 | #define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 |
14269 | #define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 |
14270 | #define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 |
14271 | #define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 |
14272 | #define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 |
14273 | #define GCVM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 |
14274 | #define GCVM_INVALIDATE_ENG7_REQ__LOG_REQUEST__SHIFT 0x19 |
14275 | #define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a |
14276 | #define GCVM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
14277 | #define GCVM_INVALIDATE_ENG7_REQ__FLUSH_TYPE_MASK 0x00070000L |
14278 | #define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L |
14279 | #define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L |
14280 | #define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L |
14281 | #define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L |
14282 | #define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L |
14283 | #define GCVM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L |
14284 | #define GCVM_INVALIDATE_ENG7_REQ__LOG_REQUEST_MASK 0x02000000L |
14285 | #define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L |
14286 | //GCVM_INVALIDATE_ENG8_REQ |
14287 | #define GCVM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
14288 | #define GCVM_INVALIDATE_ENG8_REQ__FLUSH_TYPE__SHIFT 0x10 |
14289 | #define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 |
14290 | #define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 |
14291 | #define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 |
14292 | #define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 |
14293 | #define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 |
14294 | #define GCVM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 |
14295 | #define GCVM_INVALIDATE_ENG8_REQ__LOG_REQUEST__SHIFT 0x19 |
14296 | #define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a |
14297 | #define GCVM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
14298 | #define GCVM_INVALIDATE_ENG8_REQ__FLUSH_TYPE_MASK 0x00070000L |
14299 | #define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L |
14300 | #define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L |
14301 | #define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L |
14302 | #define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L |
14303 | #define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L |
14304 | #define GCVM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L |
14305 | #define GCVM_INVALIDATE_ENG8_REQ__LOG_REQUEST_MASK 0x02000000L |
14306 | #define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L |
14307 | //GCVM_INVALIDATE_ENG9_REQ |
14308 | #define GCVM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
14309 | #define GCVM_INVALIDATE_ENG9_REQ__FLUSH_TYPE__SHIFT 0x10 |
14310 | #define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 |
14311 | #define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 |
14312 | #define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 |
14313 | #define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 |
14314 | #define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 |
14315 | #define GCVM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 |
14316 | #define GCVM_INVALIDATE_ENG9_REQ__LOG_REQUEST__SHIFT 0x19 |
14317 | #define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a |
14318 | #define GCVM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
14319 | #define GCVM_INVALIDATE_ENG9_REQ__FLUSH_TYPE_MASK 0x00070000L |
14320 | #define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L |
14321 | #define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L |
14322 | #define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L |
14323 | #define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L |
14324 | #define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L |
14325 | #define GCVM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L |
14326 | #define GCVM_INVALIDATE_ENG9_REQ__LOG_REQUEST_MASK 0x02000000L |
14327 | #define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L |
14328 | //GCVM_INVALIDATE_ENG10_REQ |
14329 | #define GCVM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
14330 | #define GCVM_INVALIDATE_ENG10_REQ__FLUSH_TYPE__SHIFT 0x10 |
14331 | #define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 |
14332 | #define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 |
14333 | #define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 |
14334 | #define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 |
14335 | #define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 |
14336 | #define GCVM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 |
14337 | #define GCVM_INVALIDATE_ENG10_REQ__LOG_REQUEST__SHIFT 0x19 |
14338 | #define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a |
14339 | #define GCVM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
14340 | #define GCVM_INVALIDATE_ENG10_REQ__FLUSH_TYPE_MASK 0x00070000L |
14341 | #define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L |
14342 | #define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L |
14343 | #define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L |
14344 | #define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L |
14345 | #define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L |
14346 | #define GCVM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L |
14347 | #define GCVM_INVALIDATE_ENG10_REQ__LOG_REQUEST_MASK 0x02000000L |
14348 | #define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L |
14349 | //GCVM_INVALIDATE_ENG11_REQ |
14350 | #define GCVM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
14351 | #define GCVM_INVALIDATE_ENG11_REQ__FLUSH_TYPE__SHIFT 0x10 |
14352 | #define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 |
14353 | #define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 |
14354 | #define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 |
14355 | #define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 |
14356 | #define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 |
14357 | #define GCVM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 |
14358 | #define GCVM_INVALIDATE_ENG11_REQ__LOG_REQUEST__SHIFT 0x19 |
14359 | #define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a |
14360 | #define GCVM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
14361 | #define GCVM_INVALIDATE_ENG11_REQ__FLUSH_TYPE_MASK 0x00070000L |
14362 | #define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L |
14363 | #define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L |
14364 | #define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L |
14365 | #define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L |
14366 | #define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L |
14367 | #define GCVM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L |
14368 | #define GCVM_INVALIDATE_ENG11_REQ__LOG_REQUEST_MASK 0x02000000L |
14369 | #define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L |
14370 | //GCVM_INVALIDATE_ENG12_REQ |
14371 | #define GCVM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
14372 | #define GCVM_INVALIDATE_ENG12_REQ__FLUSH_TYPE__SHIFT 0x10 |
14373 | #define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 |
14374 | #define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 |
14375 | #define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 |
14376 | #define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 |
14377 | #define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 |
14378 | #define GCVM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 |
14379 | #define GCVM_INVALIDATE_ENG12_REQ__LOG_REQUEST__SHIFT 0x19 |
14380 | #define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a |
14381 | #define GCVM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
14382 | #define GCVM_INVALIDATE_ENG12_REQ__FLUSH_TYPE_MASK 0x00070000L |
14383 | #define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L |
14384 | #define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L |
14385 | #define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L |
14386 | #define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L |
14387 | #define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L |
14388 | #define GCVM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L |
14389 | #define GCVM_INVALIDATE_ENG12_REQ__LOG_REQUEST_MASK 0x02000000L |
14390 | #define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L |
14391 | //GCVM_INVALIDATE_ENG13_REQ |
14392 | #define GCVM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
14393 | #define GCVM_INVALIDATE_ENG13_REQ__FLUSH_TYPE__SHIFT 0x10 |
14394 | #define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 |
14395 | #define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 |
14396 | #define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 |
14397 | #define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 |
14398 | #define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 |
14399 | #define GCVM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 |
14400 | #define GCVM_INVALIDATE_ENG13_REQ__LOG_REQUEST__SHIFT 0x19 |
14401 | #define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a |
14402 | #define GCVM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
14403 | #define GCVM_INVALIDATE_ENG13_REQ__FLUSH_TYPE_MASK 0x00070000L |
14404 | #define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L |
14405 | #define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L |
14406 | #define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L |
14407 | #define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L |
14408 | #define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L |
14409 | #define GCVM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L |
14410 | #define GCVM_INVALIDATE_ENG13_REQ__LOG_REQUEST_MASK 0x02000000L |
14411 | #define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L |
14412 | //GCVM_INVALIDATE_ENG14_REQ |
14413 | #define GCVM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
14414 | #define GCVM_INVALIDATE_ENG14_REQ__FLUSH_TYPE__SHIFT 0x10 |
14415 | #define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 |
14416 | #define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 |
14417 | #define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 |
14418 | #define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 |
14419 | #define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 |
14420 | #define GCVM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 |
14421 | #define GCVM_INVALIDATE_ENG14_REQ__LOG_REQUEST__SHIFT 0x19 |
14422 | #define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a |
14423 | #define GCVM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
14424 | #define GCVM_INVALIDATE_ENG14_REQ__FLUSH_TYPE_MASK 0x00070000L |
14425 | #define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L |
14426 | #define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L |
14427 | #define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L |
14428 | #define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L |
14429 | #define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L |
14430 | #define GCVM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L |
14431 | #define GCVM_INVALIDATE_ENG14_REQ__LOG_REQUEST_MASK 0x02000000L |
14432 | #define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L |
14433 | //GCVM_INVALIDATE_ENG15_REQ |
14434 | #define GCVM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
14435 | #define GCVM_INVALIDATE_ENG15_REQ__FLUSH_TYPE__SHIFT 0x10 |
14436 | #define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 |
14437 | #define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 |
14438 | #define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 |
14439 | #define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 |
14440 | #define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 |
14441 | #define GCVM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 |
14442 | #define GCVM_INVALIDATE_ENG15_REQ__LOG_REQUEST__SHIFT 0x19 |
14443 | #define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a |
14444 | #define GCVM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
14445 | #define GCVM_INVALIDATE_ENG15_REQ__FLUSH_TYPE_MASK 0x00070000L |
14446 | #define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L |
14447 | #define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L |
14448 | #define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L |
14449 | #define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L |
14450 | #define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L |
14451 | #define GCVM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L |
14452 | #define GCVM_INVALIDATE_ENG15_REQ__LOG_REQUEST_MASK 0x02000000L |
14453 | #define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L |
14454 | //GCVM_INVALIDATE_ENG16_REQ |
14455 | #define GCVM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
14456 | #define GCVM_INVALIDATE_ENG16_REQ__FLUSH_TYPE__SHIFT 0x10 |
14457 | #define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 |
14458 | #define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 |
14459 | #define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 |
14460 | #define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 |
14461 | #define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 |
14462 | #define GCVM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 |
14463 | #define GCVM_INVALIDATE_ENG16_REQ__LOG_REQUEST__SHIFT 0x19 |
14464 | #define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a |
14465 | #define GCVM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
14466 | #define GCVM_INVALIDATE_ENG16_REQ__FLUSH_TYPE_MASK 0x00070000L |
14467 | #define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L |
14468 | #define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L |
14469 | #define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L |
14470 | #define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L |
14471 | #define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L |
14472 | #define GCVM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L |
14473 | #define GCVM_INVALIDATE_ENG16_REQ__LOG_REQUEST_MASK 0x02000000L |
14474 | #define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L |
14475 | //GCVM_INVALIDATE_ENG17_REQ |
14476 | #define GCVM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 |
14477 | #define GCVM_INVALIDATE_ENG17_REQ__FLUSH_TYPE__SHIFT 0x10 |
14478 | #define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 |
14479 | #define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 |
14480 | #define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 |
14481 | #define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 |
14482 | #define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 |
14483 | #define GCVM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 |
14484 | #define GCVM_INVALIDATE_ENG17_REQ__LOG_REQUEST__SHIFT 0x19 |
14485 | #define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a |
14486 | #define GCVM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL |
14487 | #define GCVM_INVALIDATE_ENG17_REQ__FLUSH_TYPE_MASK 0x00070000L |
14488 | #define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L |
14489 | #define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L |
14490 | #define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L |
14491 | #define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L |
14492 | #define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L |
14493 | #define GCVM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L |
14494 | #define GCVM_INVALIDATE_ENG17_REQ__LOG_REQUEST_MASK 0x02000000L |
14495 | #define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L |
14496 | //GCVM_INVALIDATE_ENG0_ACK |
14497 | #define GCVM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
14498 | #define GCVM_INVALIDATE_ENG0_ACK__SEMAPHORE__SHIFT 0x10 |
14499 | #define GCVM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
14500 | #define GCVM_INVALIDATE_ENG0_ACK__SEMAPHORE_MASK 0x00010000L |
14501 | //GCVM_INVALIDATE_ENG1_ACK |
14502 | #define GCVM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
14503 | #define GCVM_INVALIDATE_ENG1_ACK__SEMAPHORE__SHIFT 0x10 |
14504 | #define GCVM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
14505 | #define GCVM_INVALIDATE_ENG1_ACK__SEMAPHORE_MASK 0x00010000L |
14506 | //GCVM_INVALIDATE_ENG2_ACK |
14507 | #define GCVM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
14508 | #define GCVM_INVALIDATE_ENG2_ACK__SEMAPHORE__SHIFT 0x10 |
14509 | #define GCVM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
14510 | #define GCVM_INVALIDATE_ENG2_ACK__SEMAPHORE_MASK 0x00010000L |
14511 | //GCVM_INVALIDATE_ENG3_ACK |
14512 | #define GCVM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
14513 | #define GCVM_INVALIDATE_ENG3_ACK__SEMAPHORE__SHIFT 0x10 |
14514 | #define GCVM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
14515 | #define GCVM_INVALIDATE_ENG3_ACK__SEMAPHORE_MASK 0x00010000L |
14516 | //GCVM_INVALIDATE_ENG4_ACK |
14517 | #define GCVM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
14518 | #define GCVM_INVALIDATE_ENG4_ACK__SEMAPHORE__SHIFT 0x10 |
14519 | #define GCVM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
14520 | #define GCVM_INVALIDATE_ENG4_ACK__SEMAPHORE_MASK 0x00010000L |
14521 | //GCVM_INVALIDATE_ENG5_ACK |
14522 | #define GCVM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
14523 | #define GCVM_INVALIDATE_ENG5_ACK__SEMAPHORE__SHIFT 0x10 |
14524 | #define GCVM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
14525 | #define GCVM_INVALIDATE_ENG5_ACK__SEMAPHORE_MASK 0x00010000L |
14526 | //GCVM_INVALIDATE_ENG6_ACK |
14527 | #define GCVM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
14528 | #define GCVM_INVALIDATE_ENG6_ACK__SEMAPHORE__SHIFT 0x10 |
14529 | #define GCVM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
14530 | #define GCVM_INVALIDATE_ENG6_ACK__SEMAPHORE_MASK 0x00010000L |
14531 | //GCVM_INVALIDATE_ENG7_ACK |
14532 | #define GCVM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
14533 | #define GCVM_INVALIDATE_ENG7_ACK__SEMAPHORE__SHIFT 0x10 |
14534 | #define GCVM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
14535 | #define GCVM_INVALIDATE_ENG7_ACK__SEMAPHORE_MASK 0x00010000L |
14536 | //GCVM_INVALIDATE_ENG8_ACK |
14537 | #define GCVM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
14538 | #define GCVM_INVALIDATE_ENG8_ACK__SEMAPHORE__SHIFT 0x10 |
14539 | #define GCVM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
14540 | #define GCVM_INVALIDATE_ENG8_ACK__SEMAPHORE_MASK 0x00010000L |
14541 | //GCVM_INVALIDATE_ENG9_ACK |
14542 | #define GCVM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
14543 | #define GCVM_INVALIDATE_ENG9_ACK__SEMAPHORE__SHIFT 0x10 |
14544 | #define GCVM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
14545 | #define GCVM_INVALIDATE_ENG9_ACK__SEMAPHORE_MASK 0x00010000L |
14546 | //GCVM_INVALIDATE_ENG10_ACK |
14547 | #define GCVM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
14548 | #define GCVM_INVALIDATE_ENG10_ACK__SEMAPHORE__SHIFT 0x10 |
14549 | #define GCVM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
14550 | #define GCVM_INVALIDATE_ENG10_ACK__SEMAPHORE_MASK 0x00010000L |
14551 | //GCVM_INVALIDATE_ENG11_ACK |
14552 | #define GCVM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
14553 | #define GCVM_INVALIDATE_ENG11_ACK__SEMAPHORE__SHIFT 0x10 |
14554 | #define GCVM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
14555 | #define GCVM_INVALIDATE_ENG11_ACK__SEMAPHORE_MASK 0x00010000L |
14556 | //GCVM_INVALIDATE_ENG12_ACK |
14557 | #define GCVM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
14558 | #define GCVM_INVALIDATE_ENG12_ACK__SEMAPHORE__SHIFT 0x10 |
14559 | #define GCVM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
14560 | #define GCVM_INVALIDATE_ENG12_ACK__SEMAPHORE_MASK 0x00010000L |
14561 | //GCVM_INVALIDATE_ENG13_ACK |
14562 | #define GCVM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
14563 | #define GCVM_INVALIDATE_ENG13_ACK__SEMAPHORE__SHIFT 0x10 |
14564 | #define GCVM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
14565 | #define GCVM_INVALIDATE_ENG13_ACK__SEMAPHORE_MASK 0x00010000L |
14566 | //GCVM_INVALIDATE_ENG14_ACK |
14567 | #define GCVM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
14568 | #define GCVM_INVALIDATE_ENG14_ACK__SEMAPHORE__SHIFT 0x10 |
14569 | #define GCVM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
14570 | #define GCVM_INVALIDATE_ENG14_ACK__SEMAPHORE_MASK 0x00010000L |
14571 | //GCVM_INVALIDATE_ENG15_ACK |
14572 | #define GCVM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
14573 | #define GCVM_INVALIDATE_ENG15_ACK__SEMAPHORE__SHIFT 0x10 |
14574 | #define GCVM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
14575 | #define GCVM_INVALIDATE_ENG15_ACK__SEMAPHORE_MASK 0x00010000L |
14576 | //GCVM_INVALIDATE_ENG16_ACK |
14577 | #define GCVM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
14578 | #define GCVM_INVALIDATE_ENG16_ACK__SEMAPHORE__SHIFT 0x10 |
14579 | #define GCVM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
14580 | #define GCVM_INVALIDATE_ENG16_ACK__SEMAPHORE_MASK 0x00010000L |
14581 | //GCVM_INVALIDATE_ENG17_ACK |
14582 | #define GCVM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 |
14583 | #define GCVM_INVALIDATE_ENG17_ACK__SEMAPHORE__SHIFT 0x10 |
14584 | #define GCVM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL |
14585 | #define GCVM_INVALIDATE_ENG17_ACK__SEMAPHORE_MASK 0x00010000L |
14586 | //GCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 |
14587 | #define GCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
14588 | #define GCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
14589 | #define GCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
14590 | #define GCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
14591 | //GCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 |
14592 | #define GCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
14593 | #define GCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
14594 | //GCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 |
14595 | #define GCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
14596 | #define GCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
14597 | #define GCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
14598 | #define GCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
14599 | //GCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 |
14600 | #define GCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
14601 | #define GCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
14602 | //GCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 |
14603 | #define GCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
14604 | #define GCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
14605 | #define GCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
14606 | #define GCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
14607 | //GCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 |
14608 | #define GCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
14609 | #define GCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
14610 | //GCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 |
14611 | #define GCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
14612 | #define GCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
14613 | #define GCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
14614 | #define GCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
14615 | //GCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 |
14616 | #define GCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
14617 | #define GCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
14618 | //GCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 |
14619 | #define GCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
14620 | #define GCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
14621 | #define GCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
14622 | #define GCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
14623 | //GCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 |
14624 | #define GCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
14625 | #define GCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
14626 | //GCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 |
14627 | #define GCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
14628 | #define GCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
14629 | #define GCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
14630 | #define GCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
14631 | //GCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 |
14632 | #define GCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
14633 | #define GCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
14634 | //GCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 |
14635 | #define GCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
14636 | #define GCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
14637 | #define GCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
14638 | #define GCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
14639 | //GCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 |
14640 | #define GCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
14641 | #define GCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
14642 | //GCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 |
14643 | #define GCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
14644 | #define GCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
14645 | #define GCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
14646 | #define GCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
14647 | //GCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 |
14648 | #define GCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
14649 | #define GCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
14650 | //GCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 |
14651 | #define GCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
14652 | #define GCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
14653 | #define GCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
14654 | #define GCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
14655 | //GCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 |
14656 | #define GCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
14657 | #define GCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
14658 | //GCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 |
14659 | #define GCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
14660 | #define GCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
14661 | #define GCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
14662 | #define GCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
14663 | //GCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 |
14664 | #define GCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
14665 | #define GCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
14666 | //GCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 |
14667 | #define GCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
14668 | #define GCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
14669 | #define GCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
14670 | #define GCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
14671 | //GCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 |
14672 | #define GCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
14673 | #define GCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
14674 | //GCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 |
14675 | #define GCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
14676 | #define GCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
14677 | #define GCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
14678 | #define GCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
14679 | //GCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 |
14680 | #define GCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
14681 | #define GCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
14682 | //GCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 |
14683 | #define GCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
14684 | #define GCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
14685 | #define GCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
14686 | #define GCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
14687 | //GCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 |
14688 | #define GCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
14689 | #define GCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
14690 | //GCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 |
14691 | #define GCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
14692 | #define GCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
14693 | #define GCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
14694 | #define GCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
14695 | //GCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 |
14696 | #define GCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
14697 | #define GCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
14698 | //GCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 |
14699 | #define GCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
14700 | #define GCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
14701 | #define GCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
14702 | #define GCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
14703 | //GCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 |
14704 | #define GCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
14705 | #define GCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
14706 | //GCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 |
14707 | #define GCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
14708 | #define GCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
14709 | #define GCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
14710 | #define GCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
14711 | //GCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 |
14712 | #define GCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
14713 | #define GCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
14714 | //GCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 |
14715 | #define GCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
14716 | #define GCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
14717 | #define GCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
14718 | #define GCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
14719 | //GCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 |
14720 | #define GCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
14721 | #define GCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
14722 | //GCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 |
14723 | #define GCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 |
14724 | #define GCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 |
14725 | #define GCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L |
14726 | #define GCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL |
14727 | //GCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 |
14728 | #define GCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 |
14729 | #define GCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL |
14730 | //GCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 |
14731 | #define GCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
14732 | #define GCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
14733 | //GCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 |
14734 | #define GCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
14735 | #define GCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
14736 | //GCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 |
14737 | #define GCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
14738 | #define GCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
14739 | //GCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 |
14740 | #define GCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
14741 | #define GCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
14742 | //GCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 |
14743 | #define GCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
14744 | #define GCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
14745 | //GCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 |
14746 | #define GCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
14747 | #define GCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
14748 | //GCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 |
14749 | #define GCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
14750 | #define GCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
14751 | //GCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 |
14752 | #define GCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
14753 | #define GCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
14754 | //GCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 |
14755 | #define GCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
14756 | #define GCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
14757 | //GCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 |
14758 | #define GCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
14759 | #define GCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
14760 | //GCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 |
14761 | #define GCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
14762 | #define GCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
14763 | //GCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 |
14764 | #define GCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
14765 | #define GCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
14766 | //GCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 |
14767 | #define GCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
14768 | #define GCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
14769 | //GCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 |
14770 | #define GCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
14771 | #define GCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
14772 | //GCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 |
14773 | #define GCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
14774 | #define GCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
14775 | //GCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 |
14776 | #define GCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
14777 | #define GCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
14778 | //GCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 |
14779 | #define GCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
14780 | #define GCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
14781 | //GCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 |
14782 | #define GCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
14783 | #define GCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
14784 | //GCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 |
14785 | #define GCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
14786 | #define GCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
14787 | //GCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 |
14788 | #define GCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
14789 | #define GCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
14790 | //GCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 |
14791 | #define GCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
14792 | #define GCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
14793 | //GCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 |
14794 | #define GCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
14795 | #define GCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
14796 | //GCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 |
14797 | #define GCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
14798 | #define GCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
14799 | //GCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 |
14800 | #define GCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
14801 | #define GCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
14802 | //GCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 |
14803 | #define GCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
14804 | #define GCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
14805 | //GCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 |
14806 | #define GCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
14807 | #define GCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
14808 | //GCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 |
14809 | #define GCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
14810 | #define GCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
14811 | //GCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 |
14812 | #define GCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
14813 | #define GCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
14814 | //GCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 |
14815 | #define GCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
14816 | #define GCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
14817 | //GCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 |
14818 | #define GCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
14819 | #define GCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
14820 | //GCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 |
14821 | #define GCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 |
14822 | #define GCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL |
14823 | //GCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 |
14824 | #define GCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 |
14825 | #define GCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL |
14826 | //GCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 |
14827 | #define GCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
14828 | #define GCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
14829 | //GCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 |
14830 | #define GCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
14831 | #define GCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
14832 | //GCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 |
14833 | #define GCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
14834 | #define GCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
14835 | //GCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 |
14836 | #define GCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
14837 | #define GCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
14838 | //GCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 |
14839 | #define GCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
14840 | #define GCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
14841 | //GCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 |
14842 | #define GCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
14843 | #define GCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
14844 | //GCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 |
14845 | #define GCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
14846 | #define GCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
14847 | //GCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 |
14848 | #define GCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
14849 | #define GCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
14850 | //GCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 |
14851 | #define GCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
14852 | #define GCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
14853 | //GCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 |
14854 | #define GCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
14855 | #define GCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
14856 | //GCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 |
14857 | #define GCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
14858 | #define GCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
14859 | //GCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 |
14860 | #define GCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
14861 | #define GCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
14862 | //GCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 |
14863 | #define GCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
14864 | #define GCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
14865 | //GCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 |
14866 | #define GCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
14867 | #define GCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
14868 | //GCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 |
14869 | #define GCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
14870 | #define GCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
14871 | //GCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 |
14872 | #define GCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
14873 | #define GCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
14874 | //GCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 |
14875 | #define GCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
14876 | #define GCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
14877 | //GCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 |
14878 | #define GCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
14879 | #define GCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
14880 | //GCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 |
14881 | #define GCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
14882 | #define GCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
14883 | //GCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 |
14884 | #define GCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
14885 | #define GCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
14886 | //GCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 |
14887 | #define GCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
14888 | #define GCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
14889 | //GCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 |
14890 | #define GCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
14891 | #define GCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
14892 | //GCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 |
14893 | #define GCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
14894 | #define GCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
14895 | //GCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 |
14896 | #define GCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
14897 | #define GCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
14898 | //GCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 |
14899 | #define GCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
14900 | #define GCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
14901 | //GCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 |
14902 | #define GCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
14903 | #define GCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
14904 | //GCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 |
14905 | #define GCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
14906 | #define GCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
14907 | //GCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 |
14908 | #define GCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
14909 | #define GCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
14910 | //GCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 |
14911 | #define GCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
14912 | #define GCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
14913 | //GCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 |
14914 | #define GCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
14915 | #define GCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
14916 | //GCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 |
14917 | #define GCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
14918 | #define GCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
14919 | //GCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 |
14920 | #define GCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
14921 | #define GCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
14922 | //GCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 |
14923 | #define GCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
14924 | #define GCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
14925 | //GCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 |
14926 | #define GCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
14927 | #define GCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
14928 | //GCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 |
14929 | #define GCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
14930 | #define GCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
14931 | //GCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 |
14932 | #define GCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
14933 | #define GCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
14934 | //GCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 |
14935 | #define GCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
14936 | #define GCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
14937 | //GCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 |
14938 | #define GCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
14939 | #define GCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
14940 | //GCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 |
14941 | #define GCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
14942 | #define GCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
14943 | //GCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 |
14944 | #define GCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
14945 | #define GCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
14946 | //GCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 |
14947 | #define GCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
14948 | #define GCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
14949 | //GCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 |
14950 | #define GCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
14951 | #define GCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
14952 | //GCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 |
14953 | #define GCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
14954 | #define GCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
14955 | //GCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 |
14956 | #define GCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
14957 | #define GCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
14958 | //GCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 |
14959 | #define GCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
14960 | #define GCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
14961 | //GCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 |
14962 | #define GCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
14963 | #define GCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
14964 | //GCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 |
14965 | #define GCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
14966 | #define GCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
14967 | //GCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 |
14968 | #define GCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
14969 | #define GCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
14970 | //GCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 |
14971 | #define GCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
14972 | #define GCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
14973 | //GCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 |
14974 | #define GCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
14975 | #define GCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
14976 | //GCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 |
14977 | #define GCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
14978 | #define GCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
14979 | //GCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 |
14980 | #define GCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
14981 | #define GCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
14982 | //GCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 |
14983 | #define GCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
14984 | #define GCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
14985 | //GCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 |
14986 | #define GCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
14987 | #define GCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
14988 | //GCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 |
14989 | #define GCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
14990 | #define GCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
14991 | //GCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 |
14992 | #define GCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
14993 | #define GCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
14994 | //GCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 |
14995 | #define GCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
14996 | #define GCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
14997 | //GCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 |
14998 | #define GCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
14999 | #define GCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
15000 | //GCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 |
15001 | #define GCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
15002 | #define GCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
15003 | //GCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 |
15004 | #define GCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
15005 | #define GCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
15006 | //GCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 |
15007 | #define GCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
15008 | #define GCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
15009 | //GCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 |
15010 | #define GCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
15011 | #define GCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
15012 | //GCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 |
15013 | #define GCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 |
15014 | #define GCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL |
15015 | //GCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 |
15016 | #define GCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 |
15017 | #define GCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL |
15018 | //GCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES |
15019 | #define GCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 |
15020 | #define GCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 |
15021 | #define GCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa |
15022 | #define GCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL |
15023 | #define GCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L |
15024 | #define GCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L |
15025 | //GCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES |
15026 | #define GCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 |
15027 | #define GCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 |
15028 | #define GCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa |
15029 | #define GCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL |
15030 | #define GCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L |
15031 | #define GCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L |
15032 | //GCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES |
15033 | #define GCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 |
15034 | #define GCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 |
15035 | #define GCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa |
15036 | #define GCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL |
15037 | #define GCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L |
15038 | #define GCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L |
15039 | //GCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES |
15040 | #define GCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 |
15041 | #define GCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 |
15042 | #define GCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa |
15043 | #define GCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL |
15044 | #define GCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L |
15045 | #define GCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L |
15046 | //GCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES |
15047 | #define GCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 |
15048 | #define GCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 |
15049 | #define GCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa |
15050 | #define GCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL |
15051 | #define GCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L |
15052 | #define GCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L |
15053 | //GCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES |
15054 | #define GCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 |
15055 | #define GCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 |
15056 | #define GCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa |
15057 | #define GCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL |
15058 | #define GCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L |
15059 | #define GCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L |
15060 | //GCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES |
15061 | #define GCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 |
15062 | #define GCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 |
15063 | #define GCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa |
15064 | #define GCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL |
15065 | #define GCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L |
15066 | #define GCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L |
15067 | //GCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES |
15068 | #define GCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 |
15069 | #define GCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 |
15070 | #define GCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa |
15071 | #define GCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL |
15072 | #define GCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L |
15073 | #define GCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L |
15074 | //GCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES |
15075 | #define GCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 |
15076 | #define GCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 |
15077 | #define GCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa |
15078 | #define GCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL |
15079 | #define GCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L |
15080 | #define GCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L |
15081 | //GCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES |
15082 | #define GCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 |
15083 | #define GCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 |
15084 | #define GCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa |
15085 | #define GCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL |
15086 | #define GCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L |
15087 | #define GCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L |
15088 | //GCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES |
15089 | #define GCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 |
15090 | #define GCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 |
15091 | #define GCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa |
15092 | #define GCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL |
15093 | #define GCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L |
15094 | #define GCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L |
15095 | //GCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES |
15096 | #define GCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 |
15097 | #define GCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 |
15098 | #define GCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa |
15099 | #define GCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL |
15100 | #define GCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L |
15101 | #define GCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L |
15102 | //GCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES |
15103 | #define GCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 |
15104 | #define GCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 |
15105 | #define GCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa |
15106 | #define GCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL |
15107 | #define GCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L |
15108 | #define GCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L |
15109 | //GCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES |
15110 | #define GCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 |
15111 | #define GCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 |
15112 | #define GCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa |
15113 | #define GCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL |
15114 | #define GCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L |
15115 | #define GCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L |
15116 | //GCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES |
15117 | #define GCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 |
15118 | #define GCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 |
15119 | #define GCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa |
15120 | #define GCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL |
15121 | #define GCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L |
15122 | #define GCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L |
15123 | //GCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES |
15124 | #define GCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 |
15125 | #define GCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 |
15126 | #define GCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa |
15127 | #define GCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL |
15128 | #define GCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L |
15129 | #define GCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L |
15130 | //GCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES |
15131 | #define GCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 |
15132 | #define GCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 |
15133 | #define GCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa |
15134 | #define GCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL |
15135 | #define GCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L |
15136 | #define GCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L |
15137 | |
15138 | |
15139 | // addressBlock: gc_gcvml2perfddec |
15140 | //GCVML2_PERFCOUNTER2_0_LO |
15141 | #define GCVML2_PERFCOUNTER2_0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
15142 | #define GCVML2_PERFCOUNTER2_0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
15143 | //GCVML2_PERFCOUNTER2_1_LO |
15144 | #define GCVML2_PERFCOUNTER2_1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
15145 | #define GCVML2_PERFCOUNTER2_1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
15146 | //GCVML2_PERFCOUNTER2_0_HI |
15147 | #define GCVML2_PERFCOUNTER2_0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
15148 | #define GCVML2_PERFCOUNTER2_0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
15149 | //GCVML2_PERFCOUNTER2_1_HI |
15150 | #define GCVML2_PERFCOUNTER2_1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
15151 | #define GCVML2_PERFCOUNTER2_1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
15152 | |
15153 | |
15154 | // addressBlock: gc_gcvml2prdec |
15155 | //GCMC_VM_L2_PERFCOUNTER_LO |
15156 | #define GCMC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 |
15157 | #define GCMC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL |
15158 | //GCMC_VM_L2_PERFCOUNTER_HI |
15159 | #define GCMC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 |
15160 | #define GCMC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 |
15161 | #define GCMC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL |
15162 | #define GCMC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L |
15163 | //GCUTCL2_PERFCOUNTER_LO |
15164 | #define GCUTCL2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 |
15165 | #define GCUTCL2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL |
15166 | //GCUTCL2_PERFCOUNTER_HI |
15167 | #define GCUTCL2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 |
15168 | #define GCUTCL2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 |
15169 | #define GCUTCL2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL |
15170 | #define GCUTCL2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L |
15171 | |
15172 | |
15173 | // addressBlock: gc_gcatcl2perfddec |
15174 | //GC_ATC_L2_PERFCOUNTER2_LO |
15175 | #define GC_ATC_L2_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 |
15176 | #define GC_ATC_L2_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
15177 | //GC_ATC_L2_PERFCOUNTER2_HI |
15178 | #define GC_ATC_L2_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 |
15179 | #define GC_ATC_L2_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
15180 | |
15181 | |
15182 | // addressBlock: gc_gcatcl2pfcntrdec |
15183 | //GC_ATC_L2_PERFCOUNTER_LO |
15184 | #define GC_ATC_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 |
15185 | #define GC_ATC_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL |
15186 | //GC_ATC_L2_PERFCOUNTER_HI |
15187 | #define GC_ATC_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 |
15188 | #define GC_ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 |
15189 | #define GC_ATC_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL |
15190 | #define GC_ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L |
15191 | |
15192 | |
15193 | // addressBlock: gc_gcl2tlbprdec |
15194 | //GCL2TLB_PERFCOUNTER_LO |
15195 | #define GCL2TLB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 |
15196 | #define GCL2TLB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL |
15197 | //GCL2TLB_PERFCOUNTER_HI |
15198 | #define GCL2TLB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 |
15199 | #define GCL2TLB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 |
15200 | #define GCL2TLB_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL |
15201 | #define GCL2TLB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L |
15202 | |
15203 | |
15204 | // addressBlock: gc_gcvml2perfsdec |
15205 | //GCVML2_PERFCOUNTER2_0_SELECT |
15206 | #define GCVML2_PERFCOUNTER2_0_SELECT__PERF_SEL__SHIFT 0x0 |
15207 | #define GCVML2_PERFCOUNTER2_0_SELECT__PERF_SEL1__SHIFT 0xa |
15208 | #define GCVML2_PERFCOUNTER2_0_SELECT__CNTR_MODE__SHIFT 0x14 |
15209 | #define GCVML2_PERFCOUNTER2_0_SELECT__PERF_MODE1__SHIFT 0x18 |
15210 | #define GCVML2_PERFCOUNTER2_0_SELECT__PERF_MODE__SHIFT 0x1c |
15211 | #define GCVML2_PERFCOUNTER2_0_SELECT__PERF_SEL_MASK 0x000003FFL |
15212 | #define GCVML2_PERFCOUNTER2_0_SELECT__PERF_SEL1_MASK 0x000FFC00L |
15213 | #define GCVML2_PERFCOUNTER2_0_SELECT__CNTR_MODE_MASK 0x00F00000L |
15214 | #define GCVML2_PERFCOUNTER2_0_SELECT__PERF_MODE1_MASK 0x0F000000L |
15215 | #define GCVML2_PERFCOUNTER2_0_SELECT__PERF_MODE_MASK 0xF0000000L |
15216 | //GCVML2_PERFCOUNTER2_1_SELECT |
15217 | #define GCVML2_PERFCOUNTER2_1_SELECT__PERF_SEL__SHIFT 0x0 |
15218 | #define GCVML2_PERFCOUNTER2_1_SELECT__PERF_SEL1__SHIFT 0xa |
15219 | #define GCVML2_PERFCOUNTER2_1_SELECT__CNTR_MODE__SHIFT 0x14 |
15220 | #define GCVML2_PERFCOUNTER2_1_SELECT__PERF_MODE1__SHIFT 0x18 |
15221 | #define GCVML2_PERFCOUNTER2_1_SELECT__PERF_MODE__SHIFT 0x1c |
15222 | #define GCVML2_PERFCOUNTER2_1_SELECT__PERF_SEL_MASK 0x000003FFL |
15223 | #define GCVML2_PERFCOUNTER2_1_SELECT__PERF_SEL1_MASK 0x000FFC00L |
15224 | #define GCVML2_PERFCOUNTER2_1_SELECT__CNTR_MODE_MASK 0x00F00000L |
15225 | #define GCVML2_PERFCOUNTER2_1_SELECT__PERF_MODE1_MASK 0x0F000000L |
15226 | #define GCVML2_PERFCOUNTER2_1_SELECT__PERF_MODE_MASK 0xF0000000L |
15227 | //GCVML2_PERFCOUNTER2_0_SELECT1 |
15228 | #define GCVML2_PERFCOUNTER2_0_SELECT1__PERF_SEL2__SHIFT 0x0 |
15229 | #define GCVML2_PERFCOUNTER2_0_SELECT1__PERF_SEL3__SHIFT 0xa |
15230 | #define GCVML2_PERFCOUNTER2_0_SELECT1__PERF_MODE3__SHIFT 0x18 |
15231 | #define GCVML2_PERFCOUNTER2_0_SELECT1__PERF_MODE2__SHIFT 0x1c |
15232 | #define GCVML2_PERFCOUNTER2_0_SELECT1__PERF_SEL2_MASK 0x000003FFL |
15233 | #define GCVML2_PERFCOUNTER2_0_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
15234 | #define GCVML2_PERFCOUNTER2_0_SELECT1__PERF_MODE3_MASK 0x0F000000L |
15235 | #define GCVML2_PERFCOUNTER2_0_SELECT1__PERF_MODE2_MASK 0xF0000000L |
15236 | //GCVML2_PERFCOUNTER2_1_SELECT1 |
15237 | #define GCVML2_PERFCOUNTER2_1_SELECT1__PERF_SEL2__SHIFT 0x0 |
15238 | #define GCVML2_PERFCOUNTER2_1_SELECT1__PERF_SEL3__SHIFT 0xa |
15239 | #define GCVML2_PERFCOUNTER2_1_SELECT1__PERF_MODE3__SHIFT 0x18 |
15240 | #define GCVML2_PERFCOUNTER2_1_SELECT1__PERF_MODE2__SHIFT 0x1c |
15241 | #define GCVML2_PERFCOUNTER2_1_SELECT1__PERF_SEL2_MASK 0x000003FFL |
15242 | #define GCVML2_PERFCOUNTER2_1_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
15243 | #define GCVML2_PERFCOUNTER2_1_SELECT1__PERF_MODE3_MASK 0x0F000000L |
15244 | #define GCVML2_PERFCOUNTER2_1_SELECT1__PERF_MODE2_MASK 0xF0000000L |
15245 | //GCVML2_PERFCOUNTER2_0_MODE |
15246 | #define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_MODE0__SHIFT 0x0 |
15247 | #define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_MODE1__SHIFT 0x2 |
15248 | #define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_MODE2__SHIFT 0x4 |
15249 | #define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_MODE3__SHIFT 0x6 |
15250 | #define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_VALUE0__SHIFT 0x8 |
15251 | #define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_VALUE1__SHIFT 0xc |
15252 | #define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_VALUE2__SHIFT 0x10 |
15253 | #define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_VALUE3__SHIFT 0x14 |
15254 | #define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_MODE0_MASK 0x00000003L |
15255 | #define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_MODE1_MASK 0x0000000CL |
15256 | #define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_MODE2_MASK 0x00000030L |
15257 | #define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_MODE3_MASK 0x000000C0L |
15258 | #define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_VALUE0_MASK 0x00000F00L |
15259 | #define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_VALUE1_MASK 0x0000F000L |
15260 | #define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_VALUE2_MASK 0x000F0000L |
15261 | #define GCVML2_PERFCOUNTER2_0_MODE__COMPARE_VALUE3_MASK 0x00F00000L |
15262 | //GCVML2_PERFCOUNTER2_1_MODE |
15263 | #define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_MODE0__SHIFT 0x0 |
15264 | #define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_MODE1__SHIFT 0x2 |
15265 | #define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_MODE2__SHIFT 0x4 |
15266 | #define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_MODE3__SHIFT 0x6 |
15267 | #define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_VALUE0__SHIFT 0x8 |
15268 | #define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_VALUE1__SHIFT 0xc |
15269 | #define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_VALUE2__SHIFT 0x10 |
15270 | #define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_VALUE3__SHIFT 0x14 |
15271 | #define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_MODE0_MASK 0x00000003L |
15272 | #define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_MODE1_MASK 0x0000000CL |
15273 | #define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_MODE2_MASK 0x00000030L |
15274 | #define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_MODE3_MASK 0x000000C0L |
15275 | #define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_VALUE0_MASK 0x00000F00L |
15276 | #define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_VALUE1_MASK 0x0000F000L |
15277 | #define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_VALUE2_MASK 0x000F0000L |
15278 | #define GCVML2_PERFCOUNTER2_1_MODE__COMPARE_VALUE3_MASK 0x00F00000L |
15279 | |
15280 | |
15281 | // addressBlock: gc_gcvml2pldec |
15282 | //GCMC_VM_L2_PERFCOUNTER0_CFG |
15283 | #define GCMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 |
15284 | #define GCMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 |
15285 | #define GCMC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 |
15286 | #define GCMC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c |
15287 | #define GCMC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d |
15288 | #define GCMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL |
15289 | #define GCMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L |
15290 | #define GCMC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L |
15291 | #define GCMC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L |
15292 | #define GCMC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L |
15293 | //GCMC_VM_L2_PERFCOUNTER1_CFG |
15294 | #define GCMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 |
15295 | #define GCMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 |
15296 | #define GCMC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 |
15297 | #define GCMC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c |
15298 | #define GCMC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d |
15299 | #define GCMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL |
15300 | #define GCMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L |
15301 | #define GCMC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L |
15302 | #define GCMC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L |
15303 | #define GCMC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L |
15304 | //GCMC_VM_L2_PERFCOUNTER2_CFG |
15305 | #define GCMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 |
15306 | #define GCMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 |
15307 | #define GCMC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 |
15308 | #define GCMC_VM_L2_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c |
15309 | #define GCMC_VM_L2_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d |
15310 | #define GCMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL |
15311 | #define GCMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L |
15312 | #define GCMC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L |
15313 | #define GCMC_VM_L2_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L |
15314 | #define GCMC_VM_L2_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L |
15315 | //GCMC_VM_L2_PERFCOUNTER3_CFG |
15316 | #define GCMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 |
15317 | #define GCMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 |
15318 | #define GCMC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 |
15319 | #define GCMC_VM_L2_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c |
15320 | #define GCMC_VM_L2_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d |
15321 | #define GCMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL |
15322 | #define GCMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L |
15323 | #define GCMC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L |
15324 | #define GCMC_VM_L2_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L |
15325 | #define GCMC_VM_L2_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L |
15326 | //GCMC_VM_L2_PERFCOUNTER4_CFG |
15327 | #define GCMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL__SHIFT 0x0 |
15328 | #define GCMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END__SHIFT 0x8 |
15329 | #define GCMC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE__SHIFT 0x18 |
15330 | #define GCMC_VM_L2_PERFCOUNTER4_CFG__ENABLE__SHIFT 0x1c |
15331 | #define GCMC_VM_L2_PERFCOUNTER4_CFG__CLEAR__SHIFT 0x1d |
15332 | #define GCMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_MASK 0x000000FFL |
15333 | #define GCMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END_MASK 0x0000FF00L |
15334 | #define GCMC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE_MASK 0x0F000000L |
15335 | #define GCMC_VM_L2_PERFCOUNTER4_CFG__ENABLE_MASK 0x10000000L |
15336 | #define GCMC_VM_L2_PERFCOUNTER4_CFG__CLEAR_MASK 0x20000000L |
15337 | //GCMC_VM_L2_PERFCOUNTER5_CFG |
15338 | #define GCMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL__SHIFT 0x0 |
15339 | #define GCMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END__SHIFT 0x8 |
15340 | #define GCMC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE__SHIFT 0x18 |
15341 | #define GCMC_VM_L2_PERFCOUNTER5_CFG__ENABLE__SHIFT 0x1c |
15342 | #define GCMC_VM_L2_PERFCOUNTER5_CFG__CLEAR__SHIFT 0x1d |
15343 | #define GCMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_MASK 0x000000FFL |
15344 | #define GCMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END_MASK 0x0000FF00L |
15345 | #define GCMC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE_MASK 0x0F000000L |
15346 | #define GCMC_VM_L2_PERFCOUNTER5_CFG__ENABLE_MASK 0x10000000L |
15347 | #define GCMC_VM_L2_PERFCOUNTER5_CFG__CLEAR_MASK 0x20000000L |
15348 | //GCMC_VM_L2_PERFCOUNTER6_CFG |
15349 | #define GCMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL__SHIFT 0x0 |
15350 | #define GCMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END__SHIFT 0x8 |
15351 | #define GCMC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE__SHIFT 0x18 |
15352 | #define GCMC_VM_L2_PERFCOUNTER6_CFG__ENABLE__SHIFT 0x1c |
15353 | #define GCMC_VM_L2_PERFCOUNTER6_CFG__CLEAR__SHIFT 0x1d |
15354 | #define GCMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_MASK 0x000000FFL |
15355 | #define GCMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END_MASK 0x0000FF00L |
15356 | #define GCMC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE_MASK 0x0F000000L |
15357 | #define GCMC_VM_L2_PERFCOUNTER6_CFG__ENABLE_MASK 0x10000000L |
15358 | #define GCMC_VM_L2_PERFCOUNTER6_CFG__CLEAR_MASK 0x20000000L |
15359 | //GCMC_VM_L2_PERFCOUNTER7_CFG |
15360 | #define GCMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL__SHIFT 0x0 |
15361 | #define GCMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END__SHIFT 0x8 |
15362 | #define GCMC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE__SHIFT 0x18 |
15363 | #define GCMC_VM_L2_PERFCOUNTER7_CFG__ENABLE__SHIFT 0x1c |
15364 | #define GCMC_VM_L2_PERFCOUNTER7_CFG__CLEAR__SHIFT 0x1d |
15365 | #define GCMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_MASK 0x000000FFL |
15366 | #define GCMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END_MASK 0x0000FF00L |
15367 | #define GCMC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE_MASK 0x0F000000L |
15368 | #define GCMC_VM_L2_PERFCOUNTER7_CFG__ENABLE_MASK 0x10000000L |
15369 | #define GCMC_VM_L2_PERFCOUNTER7_CFG__CLEAR_MASK 0x20000000L |
15370 | //GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL |
15371 | #define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 |
15372 | #define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 |
15373 | #define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 |
15374 | #define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 |
15375 | #define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 |
15376 | #define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a |
15377 | #define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL |
15378 | #define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L |
15379 | #define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L |
15380 | #define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L |
15381 | #define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L |
15382 | #define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L |
15383 | //GCUTCL2_PERFCOUNTER0_CFG |
15384 | #define GCUTCL2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 |
15385 | #define GCUTCL2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 |
15386 | #define GCUTCL2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 |
15387 | #define GCUTCL2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c |
15388 | #define GCUTCL2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d |
15389 | #define GCUTCL2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL |
15390 | #define GCUTCL2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L |
15391 | #define GCUTCL2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L |
15392 | #define GCUTCL2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L |
15393 | #define GCUTCL2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L |
15394 | //GCUTCL2_PERFCOUNTER1_CFG |
15395 | #define GCUTCL2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 |
15396 | #define GCUTCL2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 |
15397 | #define GCUTCL2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 |
15398 | #define GCUTCL2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c |
15399 | #define GCUTCL2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d |
15400 | #define GCUTCL2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL |
15401 | #define GCUTCL2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L |
15402 | #define GCUTCL2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L |
15403 | #define GCUTCL2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L |
15404 | #define GCUTCL2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L |
15405 | //GCUTCL2_PERFCOUNTER2_CFG |
15406 | #define GCUTCL2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 |
15407 | #define GCUTCL2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 |
15408 | #define GCUTCL2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 |
15409 | #define GCUTCL2_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c |
15410 | #define GCUTCL2_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d |
15411 | #define GCUTCL2_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL |
15412 | #define GCUTCL2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L |
15413 | #define GCUTCL2_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L |
15414 | #define GCUTCL2_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L |
15415 | #define GCUTCL2_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L |
15416 | //GCUTCL2_PERFCOUNTER3_CFG |
15417 | #define GCUTCL2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 |
15418 | #define GCUTCL2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 |
15419 | #define GCUTCL2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 |
15420 | #define GCUTCL2_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c |
15421 | #define GCUTCL2_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d |
15422 | #define GCUTCL2_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL |
15423 | #define GCUTCL2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L |
15424 | #define GCUTCL2_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L |
15425 | #define GCUTCL2_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L |
15426 | #define GCUTCL2_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L |
15427 | //GCUTCL2_PERFCOUNTER_RSLT_CNTL |
15428 | #define GCUTCL2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 |
15429 | #define GCUTCL2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 |
15430 | #define GCUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 |
15431 | #define GCUTCL2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 |
15432 | #define GCUTCL2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 |
15433 | #define GCUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a |
15434 | #define GCUTCL2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL |
15435 | #define GCUTCL2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L |
15436 | #define GCUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L |
15437 | #define GCUTCL2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L |
15438 | #define GCUTCL2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L |
15439 | #define GCUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L |
15440 | |
15441 | |
15442 | // addressBlock: gc_gcatcl2perfsdec |
15443 | //GC_ATC_L2_PERFCOUNTER2_SELECT |
15444 | #define GC_ATC_L2_PERFCOUNTER2_SELECT__PERF_SEL0__SHIFT 0x0 |
15445 | #define GC_ATC_L2_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa |
15446 | #define GC_ATC_L2_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 |
15447 | #define GC_ATC_L2_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 |
15448 | #define GC_ATC_L2_PERFCOUNTER2_SELECT__PERF_MODE0__SHIFT 0x1c |
15449 | #define GC_ATC_L2_PERFCOUNTER2_SELECT__PERF_SEL0_MASK 0x000003FFL |
15450 | #define GC_ATC_L2_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L |
15451 | #define GC_ATC_L2_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L |
15452 | #define GC_ATC_L2_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L |
15453 | #define GC_ATC_L2_PERFCOUNTER2_SELECT__PERF_MODE0_MASK 0xF0000000L |
15454 | //GC_ATC_L2_PERFCOUNTER2_SELECT1 |
15455 | #define GC_ATC_L2_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 |
15456 | #define GC_ATC_L2_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa |
15457 | #define GC_ATC_L2_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18 |
15458 | #define GC_ATC_L2_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c |
15459 | #define GC_ATC_L2_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL |
15460 | #define GC_ATC_L2_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
15461 | #define GC_ATC_L2_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L |
15462 | #define GC_ATC_L2_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L |
15463 | //GC_ATC_L2_PERFCOUNTER2_MODE |
15464 | #define GC_ATC_L2_PERFCOUNTER2_MODE__COMPARE_MODE0__SHIFT 0x0 |
15465 | #define GC_ATC_L2_PERFCOUNTER2_MODE__COMPARE_MODE1__SHIFT 0x2 |
15466 | #define GC_ATC_L2_PERFCOUNTER2_MODE__COMPARE_MODE2__SHIFT 0x4 |
15467 | #define GC_ATC_L2_PERFCOUNTER2_MODE__COMPARE_MODE3__SHIFT 0x6 |
15468 | #define GC_ATC_L2_PERFCOUNTER2_MODE__COMPARE_VALUE0__SHIFT 0x8 |
15469 | #define GC_ATC_L2_PERFCOUNTER2_MODE__COMPARE_VALUE1__SHIFT 0xc |
15470 | #define GC_ATC_L2_PERFCOUNTER2_MODE__COMPARE_VALUE2__SHIFT 0x10 |
15471 | #define GC_ATC_L2_PERFCOUNTER2_MODE__COMPARE_VALUE3__SHIFT 0x14 |
15472 | #define GC_ATC_L2_PERFCOUNTER2_MODE__COMPARE_MODE0_MASK 0x00000003L |
15473 | #define GC_ATC_L2_PERFCOUNTER2_MODE__COMPARE_MODE1_MASK 0x0000000CL |
15474 | #define GC_ATC_L2_PERFCOUNTER2_MODE__COMPARE_MODE2_MASK 0x00000030L |
15475 | #define GC_ATC_L2_PERFCOUNTER2_MODE__COMPARE_MODE3_MASK 0x000000C0L |
15476 | #define GC_ATC_L2_PERFCOUNTER2_MODE__COMPARE_VALUE0_MASK 0x00000F00L |
15477 | #define GC_ATC_L2_PERFCOUNTER2_MODE__COMPARE_VALUE1_MASK 0x0000F000L |
15478 | #define GC_ATC_L2_PERFCOUNTER2_MODE__COMPARE_VALUE2_MASK 0x000F0000L |
15479 | #define GC_ATC_L2_PERFCOUNTER2_MODE__COMPARE_VALUE3_MASK 0x00F00000L |
15480 | |
15481 | |
15482 | // addressBlock: gc_gcatcl2pfcntldec |
15483 | //GC_ATC_L2_PERFCOUNTER0_CFG |
15484 | #define GC_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 |
15485 | #define GC_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 |
15486 | #define GC_ATC_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 |
15487 | #define GC_ATC_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c |
15488 | #define GC_ATC_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d |
15489 | #define GC_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL |
15490 | #define GC_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L |
15491 | #define GC_ATC_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L |
15492 | #define GC_ATC_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L |
15493 | #define GC_ATC_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L |
15494 | //GC_ATC_L2_PERFCOUNTER1_CFG |
15495 | #define GC_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 |
15496 | #define GC_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 |
15497 | #define GC_ATC_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 |
15498 | #define GC_ATC_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c |
15499 | #define GC_ATC_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d |
15500 | #define GC_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL |
15501 | #define GC_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L |
15502 | #define GC_ATC_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L |
15503 | #define GC_ATC_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L |
15504 | #define GC_ATC_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L |
15505 | //GC_ATC_L2_PERFCOUNTER_RSLT_CNTL |
15506 | #define GC_ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 |
15507 | #define GC_ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 |
15508 | #define GC_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 |
15509 | #define GC_ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 |
15510 | #define GC_ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 |
15511 | #define GC_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a |
15512 | #define GC_ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL |
15513 | #define GC_ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L |
15514 | #define GC_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L |
15515 | #define GC_ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L |
15516 | #define GC_ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L |
15517 | #define GC_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L |
15518 | |
15519 | |
15520 | // addressBlock: gc_gcl2tlbpldec |
15521 | //GCL2TLB_PERFCOUNTER0_CFG |
15522 | #define GCL2TLB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 |
15523 | #define GCL2TLB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 |
15524 | #define GCL2TLB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 |
15525 | #define GCL2TLB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c |
15526 | #define GCL2TLB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d |
15527 | #define GCL2TLB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL |
15528 | #define GCL2TLB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L |
15529 | #define GCL2TLB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L |
15530 | #define GCL2TLB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L |
15531 | #define GCL2TLB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L |
15532 | //GCL2TLB_PERFCOUNTER1_CFG |
15533 | #define GCL2TLB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 |
15534 | #define GCL2TLB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 |
15535 | #define GCL2TLB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 |
15536 | #define GCL2TLB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c |
15537 | #define GCL2TLB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d |
15538 | #define GCL2TLB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL |
15539 | #define GCL2TLB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L |
15540 | #define GCL2TLB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L |
15541 | #define GCL2TLB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L |
15542 | #define GCL2TLB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L |
15543 | //GCL2TLB_PERFCOUNTER2_CFG |
15544 | #define GCL2TLB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 |
15545 | #define GCL2TLB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 |
15546 | #define GCL2TLB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 |
15547 | #define GCL2TLB_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c |
15548 | #define GCL2TLB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d |
15549 | #define GCL2TLB_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL |
15550 | #define GCL2TLB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L |
15551 | #define GCL2TLB_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L |
15552 | #define GCL2TLB_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L |
15553 | #define GCL2TLB_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L |
15554 | //GCL2TLB_PERFCOUNTER3_CFG |
15555 | #define GCL2TLB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 |
15556 | #define GCL2TLB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 |
15557 | #define GCL2TLB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 |
15558 | #define GCL2TLB_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c |
15559 | #define GCL2TLB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d |
15560 | #define GCL2TLB_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL |
15561 | #define GCL2TLB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L |
15562 | #define GCL2TLB_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L |
15563 | #define GCL2TLB_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L |
15564 | #define GCL2TLB_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L |
15565 | //GCL2TLB_PERFCOUNTER_RSLT_CNTL |
15566 | #define GCL2TLB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 |
15567 | #define GCL2TLB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 |
15568 | #define GCL2TLB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 |
15569 | #define GCL2TLB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 |
15570 | #define GCL2TLB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 |
15571 | #define GCL2TLB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a |
15572 | #define GCL2TLB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL |
15573 | #define GCL2TLB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L |
15574 | #define GCL2TLB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L |
15575 | #define GCL2TLB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L |
15576 | #define GCL2TLB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L |
15577 | #define GCL2TLB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L |
15578 | |
15579 | |
15580 | // addressBlock: gc_gcvml2pspdec |
15581 | //GCUTCL2_TRANSLATION_BYPASS_BY_VMID |
15582 | #define GCUTCL2_TRANSLATION_BYPASS_BY_VMID__TRANS_BYPASS_VMIDS__SHIFT 0x0 |
15583 | #define GCUTCL2_TRANSLATION_BYPASS_BY_VMID__GPA_MODE_VMIDS__SHIFT 0x10 |
15584 | #define GCUTCL2_TRANSLATION_BYPASS_BY_VMID__TRANS_BYPASS_VMIDS_MASK 0x0000FFFFL |
15585 | #define GCUTCL2_TRANSLATION_BYPASS_BY_VMID__GPA_MODE_VMIDS_MASK 0xFFFF0000L |
15586 | //GCVM_IOMMU_GPU_HOST_TRANSLATION_ENABLE |
15587 | #define GCVM_IOMMU_GPU_HOST_TRANSLATION_ENABLE__GPU_HOST_TRANSLATION_ENABLE__SHIFT 0x0 |
15588 | #define GCVM_IOMMU_GPU_HOST_TRANSLATION_ENABLE__GPU_HOST_TRANSLATION_ENABLE_MASK 0x00000001L |
15589 | //GCVM_IOMMU_CONTROL_REGISTER |
15590 | #define GCVM_IOMMU_CONTROL_REGISTER__IOMMUEN__SHIFT 0x0 |
15591 | #define GCVM_IOMMU_CONTROL_REGISTER__IOMMUEN_MASK 0x00000001L |
15592 | //GCVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER |
15593 | #define GCVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN__SHIFT 0xd |
15594 | #define GCVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN_MASK 0x00002000L |
15595 | //GCVM_IOMMU_MMIO_CNTRL_1 |
15596 | #define GCVM_IOMMU_MMIO_CNTRL_1__MARC_EN__SHIFT 0x8 |
15597 | #define GCVM_IOMMU_MMIO_CNTRL_1__MARC_EN_MASK 0x00000100L |
15598 | //GCMC_VM_MARC_BASE_LO_0 |
15599 | #define GCMC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0__SHIFT 0xc |
15600 | #define GCMC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0_MASK 0xFFFFF000L |
15601 | //GCMC_VM_MARC_BASE_LO_1 |
15602 | #define GCMC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1__SHIFT 0xc |
15603 | #define GCMC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1_MASK 0xFFFFF000L |
15604 | //GCMC_VM_MARC_BASE_LO_2 |
15605 | #define GCMC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2__SHIFT 0xc |
15606 | #define GCMC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2_MASK 0xFFFFF000L |
15607 | //GCMC_VM_MARC_BASE_LO_3 |
15608 | #define GCMC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3__SHIFT 0xc |
15609 | #define GCMC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3_MASK 0xFFFFF000L |
15610 | //GCMC_VM_MARC_BASE_LO_4 |
15611 | #define GCMC_VM_MARC_BASE_LO_4__MARC_BASE_LO_4__SHIFT 0xc |
15612 | #define GCMC_VM_MARC_BASE_LO_4__MARC_BASE_LO_4_MASK 0xFFFFF000L |
15613 | //GCMC_VM_MARC_BASE_LO_5 |
15614 | #define GCMC_VM_MARC_BASE_LO_5__MARC_BASE_LO_5__SHIFT 0xc |
15615 | #define GCMC_VM_MARC_BASE_LO_5__MARC_BASE_LO_5_MASK 0xFFFFF000L |
15616 | //GCMC_VM_MARC_BASE_LO_6 |
15617 | #define GCMC_VM_MARC_BASE_LO_6__MARC_BASE_LO_6__SHIFT 0xc |
15618 | #define GCMC_VM_MARC_BASE_LO_6__MARC_BASE_LO_6_MASK 0xFFFFF000L |
15619 | //GCMC_VM_MARC_BASE_LO_7 |
15620 | #define GCMC_VM_MARC_BASE_LO_7__MARC_BASE_LO_7__SHIFT 0xc |
15621 | #define GCMC_VM_MARC_BASE_LO_7__MARC_BASE_LO_7_MASK 0xFFFFF000L |
15622 | //GCMC_VM_MARC_BASE_LO_8 |
15623 | #define GCMC_VM_MARC_BASE_LO_8__MARC_BASE_LO_8__SHIFT 0xc |
15624 | #define GCMC_VM_MARC_BASE_LO_8__MARC_BASE_LO_8_MASK 0xFFFFF000L |
15625 | //GCMC_VM_MARC_BASE_LO_9 |
15626 | #define GCMC_VM_MARC_BASE_LO_9__MARC_BASE_LO_9__SHIFT 0xc |
15627 | #define GCMC_VM_MARC_BASE_LO_9__MARC_BASE_LO_9_MASK 0xFFFFF000L |
15628 | //GCMC_VM_MARC_BASE_LO_10 |
15629 | #define GCMC_VM_MARC_BASE_LO_10__MARC_BASE_LO_10__SHIFT 0xc |
15630 | #define GCMC_VM_MARC_BASE_LO_10__MARC_BASE_LO_10_MASK 0xFFFFF000L |
15631 | //GCMC_VM_MARC_BASE_LO_11 |
15632 | #define GCMC_VM_MARC_BASE_LO_11__MARC_BASE_LO_11__SHIFT 0xc |
15633 | #define GCMC_VM_MARC_BASE_LO_11__MARC_BASE_LO_11_MASK 0xFFFFF000L |
15634 | //GCMC_VM_MARC_BASE_LO_12 |
15635 | #define GCMC_VM_MARC_BASE_LO_12__MARC_BASE_LO_12__SHIFT 0xc |
15636 | #define GCMC_VM_MARC_BASE_LO_12__MARC_BASE_LO_12_MASK 0xFFFFF000L |
15637 | //GCMC_VM_MARC_BASE_LO_13 |
15638 | #define GCMC_VM_MARC_BASE_LO_13__MARC_BASE_LO_13__SHIFT 0xc |
15639 | #define GCMC_VM_MARC_BASE_LO_13__MARC_BASE_LO_13_MASK 0xFFFFF000L |
15640 | //GCMC_VM_MARC_BASE_LO_14 |
15641 | #define GCMC_VM_MARC_BASE_LO_14__MARC_BASE_LO_14__SHIFT 0xc |
15642 | #define GCMC_VM_MARC_BASE_LO_14__MARC_BASE_LO_14_MASK 0xFFFFF000L |
15643 | //GCMC_VM_MARC_BASE_LO_15 |
15644 | #define GCMC_VM_MARC_BASE_LO_15__MARC_BASE_LO_15__SHIFT 0xc |
15645 | #define GCMC_VM_MARC_BASE_LO_15__MARC_BASE_LO_15_MASK 0xFFFFF000L |
15646 | //GCMC_VM_MARC_BASE_HI_0 |
15647 | #define GCMC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0__SHIFT 0x0 |
15648 | #define GCMC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0_MASK 0x000FFFFFL |
15649 | //GCMC_VM_MARC_BASE_HI_1 |
15650 | #define GCMC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1__SHIFT 0x0 |
15651 | #define GCMC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1_MASK 0x000FFFFFL |
15652 | //GCMC_VM_MARC_BASE_HI_2 |
15653 | #define GCMC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2__SHIFT 0x0 |
15654 | #define GCMC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2_MASK 0x000FFFFFL |
15655 | //GCMC_VM_MARC_BASE_HI_3 |
15656 | #define GCMC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3__SHIFT 0x0 |
15657 | #define GCMC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3_MASK 0x000FFFFFL |
15658 | //GCMC_VM_MARC_BASE_HI_4 |
15659 | #define GCMC_VM_MARC_BASE_HI_4__MARC_BASE_HI_4__SHIFT 0x0 |
15660 | #define GCMC_VM_MARC_BASE_HI_4__MARC_BASE_HI_4_MASK 0x000FFFFFL |
15661 | //GCMC_VM_MARC_BASE_HI_5 |
15662 | #define GCMC_VM_MARC_BASE_HI_5__MARC_BASE_HI_5__SHIFT 0x0 |
15663 | #define GCMC_VM_MARC_BASE_HI_5__MARC_BASE_HI_5_MASK 0x000FFFFFL |
15664 | //GCMC_VM_MARC_BASE_HI_6 |
15665 | #define GCMC_VM_MARC_BASE_HI_6__MARC_BASE_HI_6__SHIFT 0x0 |
15666 | #define GCMC_VM_MARC_BASE_HI_6__MARC_BASE_HI_6_MASK 0x000FFFFFL |
15667 | //GCMC_VM_MARC_BASE_HI_7 |
15668 | #define GCMC_VM_MARC_BASE_HI_7__MARC_BASE_HI_7__SHIFT 0x0 |
15669 | #define GCMC_VM_MARC_BASE_HI_7__MARC_BASE_HI_7_MASK 0x000FFFFFL |
15670 | //GCMC_VM_MARC_BASE_HI_8 |
15671 | #define GCMC_VM_MARC_BASE_HI_8__MARC_BASE_HI_8__SHIFT 0x0 |
15672 | #define GCMC_VM_MARC_BASE_HI_8__MARC_BASE_HI_8_MASK 0x000FFFFFL |
15673 | //GCMC_VM_MARC_BASE_HI_9 |
15674 | #define GCMC_VM_MARC_BASE_HI_9__MARC_BASE_HI_9__SHIFT 0x0 |
15675 | #define GCMC_VM_MARC_BASE_HI_9__MARC_BASE_HI_9_MASK 0x000FFFFFL |
15676 | //GCMC_VM_MARC_BASE_HI_10 |
15677 | #define GCMC_VM_MARC_BASE_HI_10__MARC_BASE_HI_10__SHIFT 0x0 |
15678 | #define GCMC_VM_MARC_BASE_HI_10__MARC_BASE_HI_10_MASK 0x000FFFFFL |
15679 | //GCMC_VM_MARC_BASE_HI_11 |
15680 | #define GCMC_VM_MARC_BASE_HI_11__MARC_BASE_HI_11__SHIFT 0x0 |
15681 | #define GCMC_VM_MARC_BASE_HI_11__MARC_BASE_HI_11_MASK 0x000FFFFFL |
15682 | //GCMC_VM_MARC_BASE_HI_12 |
15683 | #define GCMC_VM_MARC_BASE_HI_12__MARC_BASE_HI_12__SHIFT 0x0 |
15684 | #define GCMC_VM_MARC_BASE_HI_12__MARC_BASE_HI_12_MASK 0x000FFFFFL |
15685 | //GCMC_VM_MARC_BASE_HI_13 |
15686 | #define GCMC_VM_MARC_BASE_HI_13__MARC_BASE_HI_13__SHIFT 0x0 |
15687 | #define GCMC_VM_MARC_BASE_HI_13__MARC_BASE_HI_13_MASK 0x000FFFFFL |
15688 | //GCMC_VM_MARC_BASE_HI_14 |
15689 | #define GCMC_VM_MARC_BASE_HI_14__MARC_BASE_HI_14__SHIFT 0x0 |
15690 | #define GCMC_VM_MARC_BASE_HI_14__MARC_BASE_HI_14_MASK 0x000FFFFFL |
15691 | //GCMC_VM_MARC_BASE_HI_15 |
15692 | #define GCMC_VM_MARC_BASE_HI_15__MARC_BASE_HI_15__SHIFT 0x0 |
15693 | #define GCMC_VM_MARC_BASE_HI_15__MARC_BASE_HI_15_MASK 0x000FFFFFL |
15694 | //GCMC_VM_MARC_RELOC_LO_0 |
15695 | #define GCMC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0__SHIFT 0x0 |
15696 | #define GCMC_VM_MARC_RELOC_LO_0__MARC_READONLY_0__SHIFT 0x1 |
15697 | #define GCMC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0__SHIFT 0xc |
15698 | #define GCMC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0_MASK 0x00000001L |
15699 | #define GCMC_VM_MARC_RELOC_LO_0__MARC_READONLY_0_MASK 0x00000002L |
15700 | #define GCMC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0_MASK 0xFFFFF000L |
15701 | //GCMC_VM_MARC_RELOC_LO_1 |
15702 | #define GCMC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1__SHIFT 0x0 |
15703 | #define GCMC_VM_MARC_RELOC_LO_1__MARC_READONLY_1__SHIFT 0x1 |
15704 | #define GCMC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1__SHIFT 0xc |
15705 | #define GCMC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1_MASK 0x00000001L |
15706 | #define GCMC_VM_MARC_RELOC_LO_1__MARC_READONLY_1_MASK 0x00000002L |
15707 | #define GCMC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1_MASK 0xFFFFF000L |
15708 | //GCMC_VM_MARC_RELOC_LO_2 |
15709 | #define GCMC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2__SHIFT 0x0 |
15710 | #define GCMC_VM_MARC_RELOC_LO_2__MARC_READONLY_2__SHIFT 0x1 |
15711 | #define GCMC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2__SHIFT 0xc |
15712 | #define GCMC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2_MASK 0x00000001L |
15713 | #define GCMC_VM_MARC_RELOC_LO_2__MARC_READONLY_2_MASK 0x00000002L |
15714 | #define GCMC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2_MASK 0xFFFFF000L |
15715 | //GCMC_VM_MARC_RELOC_LO_3 |
15716 | #define GCMC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3__SHIFT 0x0 |
15717 | #define GCMC_VM_MARC_RELOC_LO_3__MARC_READONLY_3__SHIFT 0x1 |
15718 | #define GCMC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3__SHIFT 0xc |
15719 | #define GCMC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3_MASK 0x00000001L |
15720 | #define GCMC_VM_MARC_RELOC_LO_3__MARC_READONLY_3_MASK 0x00000002L |
15721 | #define GCMC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3_MASK 0xFFFFF000L |
15722 | //GCMC_VM_MARC_RELOC_LO_4 |
15723 | #define GCMC_VM_MARC_RELOC_LO_4__MARC_ENABLE_4__SHIFT 0x0 |
15724 | #define GCMC_VM_MARC_RELOC_LO_4__MARC_READONLY_4__SHIFT 0x1 |
15725 | #define GCMC_VM_MARC_RELOC_LO_4__MARC_RELOC_LO_4__SHIFT 0xc |
15726 | #define GCMC_VM_MARC_RELOC_LO_4__MARC_ENABLE_4_MASK 0x00000001L |
15727 | #define GCMC_VM_MARC_RELOC_LO_4__MARC_READONLY_4_MASK 0x00000002L |
15728 | #define GCMC_VM_MARC_RELOC_LO_4__MARC_RELOC_LO_4_MASK 0xFFFFF000L |
15729 | //GCMC_VM_MARC_RELOC_LO_5 |
15730 | #define GCMC_VM_MARC_RELOC_LO_5__MARC_ENABLE_5__SHIFT 0x0 |
15731 | #define GCMC_VM_MARC_RELOC_LO_5__MARC_READONLY_5__SHIFT 0x1 |
15732 | #define GCMC_VM_MARC_RELOC_LO_5__MARC_RELOC_LO_5__SHIFT 0xc |
15733 | #define GCMC_VM_MARC_RELOC_LO_5__MARC_ENABLE_5_MASK 0x00000001L |
15734 | #define GCMC_VM_MARC_RELOC_LO_5__MARC_READONLY_5_MASK 0x00000002L |
15735 | #define GCMC_VM_MARC_RELOC_LO_5__MARC_RELOC_LO_5_MASK 0xFFFFF000L |
15736 | //GCMC_VM_MARC_RELOC_LO_6 |
15737 | #define GCMC_VM_MARC_RELOC_LO_6__MARC_ENABLE_6__SHIFT 0x0 |
15738 | #define GCMC_VM_MARC_RELOC_LO_6__MARC_READONLY_6__SHIFT 0x1 |
15739 | #define GCMC_VM_MARC_RELOC_LO_6__MARC_RELOC_LO_6__SHIFT 0xc |
15740 | #define GCMC_VM_MARC_RELOC_LO_6__MARC_ENABLE_6_MASK 0x00000001L |
15741 | #define GCMC_VM_MARC_RELOC_LO_6__MARC_READONLY_6_MASK 0x00000002L |
15742 | #define GCMC_VM_MARC_RELOC_LO_6__MARC_RELOC_LO_6_MASK 0xFFFFF000L |
15743 | //GCMC_VM_MARC_RELOC_LO_7 |
15744 | #define GCMC_VM_MARC_RELOC_LO_7__MARC_ENABLE_7__SHIFT 0x0 |
15745 | #define GCMC_VM_MARC_RELOC_LO_7__MARC_READONLY_7__SHIFT 0x1 |
15746 | #define GCMC_VM_MARC_RELOC_LO_7__MARC_RELOC_LO_7__SHIFT 0xc |
15747 | #define GCMC_VM_MARC_RELOC_LO_7__MARC_ENABLE_7_MASK 0x00000001L |
15748 | #define GCMC_VM_MARC_RELOC_LO_7__MARC_READONLY_7_MASK 0x00000002L |
15749 | #define GCMC_VM_MARC_RELOC_LO_7__MARC_RELOC_LO_7_MASK 0xFFFFF000L |
15750 | //GCMC_VM_MARC_RELOC_LO_8 |
15751 | #define GCMC_VM_MARC_RELOC_LO_8__MARC_ENABLE_8__SHIFT 0x0 |
15752 | #define GCMC_VM_MARC_RELOC_LO_8__MARC_READONLY_8__SHIFT 0x1 |
15753 | #define GCMC_VM_MARC_RELOC_LO_8__MARC_RELOC_LO_8__SHIFT 0xc |
15754 | #define GCMC_VM_MARC_RELOC_LO_8__MARC_ENABLE_8_MASK 0x00000001L |
15755 | #define GCMC_VM_MARC_RELOC_LO_8__MARC_READONLY_8_MASK 0x00000002L |
15756 | #define GCMC_VM_MARC_RELOC_LO_8__MARC_RELOC_LO_8_MASK 0xFFFFF000L |
15757 | //GCMC_VM_MARC_RELOC_LO_9 |
15758 | #define GCMC_VM_MARC_RELOC_LO_9__MARC_ENABLE_9__SHIFT 0x0 |
15759 | #define GCMC_VM_MARC_RELOC_LO_9__MARC_READONLY_9__SHIFT 0x1 |
15760 | #define GCMC_VM_MARC_RELOC_LO_9__MARC_RELOC_LO_9__SHIFT 0xc |
15761 | #define GCMC_VM_MARC_RELOC_LO_9__MARC_ENABLE_9_MASK 0x00000001L |
15762 | #define GCMC_VM_MARC_RELOC_LO_9__MARC_READONLY_9_MASK 0x00000002L |
15763 | #define GCMC_VM_MARC_RELOC_LO_9__MARC_RELOC_LO_9_MASK 0xFFFFF000L |
15764 | //GCMC_VM_MARC_RELOC_LO_10 |
15765 | #define GCMC_VM_MARC_RELOC_LO_10__MARC_ENABLE_10__SHIFT 0x0 |
15766 | #define GCMC_VM_MARC_RELOC_LO_10__MARC_READONLY_10__SHIFT 0x1 |
15767 | #define GCMC_VM_MARC_RELOC_LO_10__MARC_RELOC_LO_10__SHIFT 0xc |
15768 | #define GCMC_VM_MARC_RELOC_LO_10__MARC_ENABLE_10_MASK 0x00000001L |
15769 | #define GCMC_VM_MARC_RELOC_LO_10__MARC_READONLY_10_MASK 0x00000002L |
15770 | #define GCMC_VM_MARC_RELOC_LO_10__MARC_RELOC_LO_10_MASK 0xFFFFF000L |
15771 | //GCMC_VM_MARC_RELOC_LO_11 |
15772 | #define GCMC_VM_MARC_RELOC_LO_11__MARC_ENABLE_11__SHIFT 0x0 |
15773 | #define GCMC_VM_MARC_RELOC_LO_11__MARC_READONLY_11__SHIFT 0x1 |
15774 | #define GCMC_VM_MARC_RELOC_LO_11__MARC_RELOC_LO_11__SHIFT 0xc |
15775 | #define GCMC_VM_MARC_RELOC_LO_11__MARC_ENABLE_11_MASK 0x00000001L |
15776 | #define GCMC_VM_MARC_RELOC_LO_11__MARC_READONLY_11_MASK 0x00000002L |
15777 | #define GCMC_VM_MARC_RELOC_LO_11__MARC_RELOC_LO_11_MASK 0xFFFFF000L |
15778 | //GCMC_VM_MARC_RELOC_LO_12 |
15779 | #define GCMC_VM_MARC_RELOC_LO_12__MARC_ENABLE_12__SHIFT 0x0 |
15780 | #define GCMC_VM_MARC_RELOC_LO_12__MARC_READONLY_12__SHIFT 0x1 |
15781 | #define GCMC_VM_MARC_RELOC_LO_12__MARC_RELOC_LO_12__SHIFT 0xc |
15782 | #define GCMC_VM_MARC_RELOC_LO_12__MARC_ENABLE_12_MASK 0x00000001L |
15783 | #define GCMC_VM_MARC_RELOC_LO_12__MARC_READONLY_12_MASK 0x00000002L |
15784 | #define GCMC_VM_MARC_RELOC_LO_12__MARC_RELOC_LO_12_MASK 0xFFFFF000L |
15785 | //GCMC_VM_MARC_RELOC_LO_13 |
15786 | #define GCMC_VM_MARC_RELOC_LO_13__MARC_ENABLE_13__SHIFT 0x0 |
15787 | #define GCMC_VM_MARC_RELOC_LO_13__MARC_READONLY_13__SHIFT 0x1 |
15788 | #define GCMC_VM_MARC_RELOC_LO_13__MARC_RELOC_LO_13__SHIFT 0xc |
15789 | #define GCMC_VM_MARC_RELOC_LO_13__MARC_ENABLE_13_MASK 0x00000001L |
15790 | #define GCMC_VM_MARC_RELOC_LO_13__MARC_READONLY_13_MASK 0x00000002L |
15791 | #define GCMC_VM_MARC_RELOC_LO_13__MARC_RELOC_LO_13_MASK 0xFFFFF000L |
15792 | //GCMC_VM_MARC_RELOC_LO_14 |
15793 | #define GCMC_VM_MARC_RELOC_LO_14__MARC_ENABLE_14__SHIFT 0x0 |
15794 | #define GCMC_VM_MARC_RELOC_LO_14__MARC_READONLY_14__SHIFT 0x1 |
15795 | #define GCMC_VM_MARC_RELOC_LO_14__MARC_RELOC_LO_14__SHIFT 0xc |
15796 | #define GCMC_VM_MARC_RELOC_LO_14__MARC_ENABLE_14_MASK 0x00000001L |
15797 | #define GCMC_VM_MARC_RELOC_LO_14__MARC_READONLY_14_MASK 0x00000002L |
15798 | #define GCMC_VM_MARC_RELOC_LO_14__MARC_RELOC_LO_14_MASK 0xFFFFF000L |
15799 | //GCMC_VM_MARC_RELOC_LO_15 |
15800 | #define GCMC_VM_MARC_RELOC_LO_15__MARC_ENABLE_15__SHIFT 0x0 |
15801 | #define GCMC_VM_MARC_RELOC_LO_15__MARC_READONLY_15__SHIFT 0x1 |
15802 | #define GCMC_VM_MARC_RELOC_LO_15__MARC_RELOC_LO_15__SHIFT 0xc |
15803 | #define GCMC_VM_MARC_RELOC_LO_15__MARC_ENABLE_15_MASK 0x00000001L |
15804 | #define GCMC_VM_MARC_RELOC_LO_15__MARC_READONLY_15_MASK 0x00000002L |
15805 | #define GCMC_VM_MARC_RELOC_LO_15__MARC_RELOC_LO_15_MASK 0xFFFFF000L |
15806 | //GCMC_VM_MARC_RELOC_HI_0 |
15807 | #define GCMC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0__SHIFT 0x0 |
15808 | #define GCMC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0_MASK 0x000FFFFFL |
15809 | //GCMC_VM_MARC_RELOC_HI_1 |
15810 | #define GCMC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1__SHIFT 0x0 |
15811 | #define GCMC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1_MASK 0x000FFFFFL |
15812 | //GCMC_VM_MARC_RELOC_HI_2 |
15813 | #define GCMC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2__SHIFT 0x0 |
15814 | #define GCMC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2_MASK 0x000FFFFFL |
15815 | //GCMC_VM_MARC_RELOC_HI_3 |
15816 | #define GCMC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3__SHIFT 0x0 |
15817 | #define GCMC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3_MASK 0x000FFFFFL |
15818 | //GCMC_VM_MARC_RELOC_HI_4 |
15819 | #define GCMC_VM_MARC_RELOC_HI_4__MARC_RELOC_HI_4__SHIFT 0x0 |
15820 | #define GCMC_VM_MARC_RELOC_HI_4__MARC_RELOC_HI_4_MASK 0x000FFFFFL |
15821 | //GCMC_VM_MARC_RELOC_HI_5 |
15822 | #define GCMC_VM_MARC_RELOC_HI_5__MARC_RELOC_HI_5__SHIFT 0x0 |
15823 | #define GCMC_VM_MARC_RELOC_HI_5__MARC_RELOC_HI_5_MASK 0x000FFFFFL |
15824 | //GCMC_VM_MARC_RELOC_HI_6 |
15825 | #define GCMC_VM_MARC_RELOC_HI_6__MARC_RELOC_HI_6__SHIFT 0x0 |
15826 | #define GCMC_VM_MARC_RELOC_HI_6__MARC_RELOC_HI_6_MASK 0x000FFFFFL |
15827 | //GCMC_VM_MARC_RELOC_HI_7 |
15828 | #define GCMC_VM_MARC_RELOC_HI_7__MARC_RELOC_HI_7__SHIFT 0x0 |
15829 | #define GCMC_VM_MARC_RELOC_HI_7__MARC_RELOC_HI_7_MASK 0x000FFFFFL |
15830 | //GCMC_VM_MARC_RELOC_HI_8 |
15831 | #define GCMC_VM_MARC_RELOC_HI_8__MARC_RELOC_HI_8__SHIFT 0x0 |
15832 | #define GCMC_VM_MARC_RELOC_HI_8__MARC_RELOC_HI_8_MASK 0x000FFFFFL |
15833 | //GCMC_VM_MARC_RELOC_HI_9 |
15834 | #define GCMC_VM_MARC_RELOC_HI_9__MARC_RELOC_HI_9__SHIFT 0x0 |
15835 | #define GCMC_VM_MARC_RELOC_HI_9__MARC_RELOC_HI_9_MASK 0x000FFFFFL |
15836 | //GCMC_VM_MARC_RELOC_HI_10 |
15837 | #define GCMC_VM_MARC_RELOC_HI_10__MARC_RELOC_HI_10__SHIFT 0x0 |
15838 | #define GCMC_VM_MARC_RELOC_HI_10__MARC_RELOC_HI_10_MASK 0x000FFFFFL |
15839 | //GCMC_VM_MARC_RELOC_HI_11 |
15840 | #define GCMC_VM_MARC_RELOC_HI_11__MARC_RELOC_HI_11__SHIFT 0x0 |
15841 | #define GCMC_VM_MARC_RELOC_HI_11__MARC_RELOC_HI_11_MASK 0x000FFFFFL |
15842 | //GCMC_VM_MARC_RELOC_HI_12 |
15843 | #define GCMC_VM_MARC_RELOC_HI_12__MARC_RELOC_HI_12__SHIFT 0x0 |
15844 | #define GCMC_VM_MARC_RELOC_HI_12__MARC_RELOC_HI_12_MASK 0x000FFFFFL |
15845 | //GCMC_VM_MARC_RELOC_HI_13 |
15846 | #define GCMC_VM_MARC_RELOC_HI_13__MARC_RELOC_HI_13__SHIFT 0x0 |
15847 | #define GCMC_VM_MARC_RELOC_HI_13__MARC_RELOC_HI_13_MASK 0x000FFFFFL |
15848 | //GCMC_VM_MARC_RELOC_HI_14 |
15849 | #define GCMC_VM_MARC_RELOC_HI_14__MARC_RELOC_HI_14__SHIFT 0x0 |
15850 | #define GCMC_VM_MARC_RELOC_HI_14__MARC_RELOC_HI_14_MASK 0x000FFFFFL |
15851 | //GCMC_VM_MARC_RELOC_HI_15 |
15852 | #define GCMC_VM_MARC_RELOC_HI_15__MARC_RELOC_HI_15__SHIFT 0x0 |
15853 | #define GCMC_VM_MARC_RELOC_HI_15__MARC_RELOC_HI_15_MASK 0x000FFFFFL |
15854 | //GCMC_VM_MARC_LEN_LO_0 |
15855 | #define GCMC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0__SHIFT 0xc |
15856 | #define GCMC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0_MASK 0xFFFFF000L |
15857 | //GCMC_VM_MARC_LEN_LO_1 |
15858 | #define GCMC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1__SHIFT 0xc |
15859 | #define GCMC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1_MASK 0xFFFFF000L |
15860 | //GCMC_VM_MARC_LEN_LO_2 |
15861 | #define GCMC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2__SHIFT 0xc |
15862 | #define GCMC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2_MASK 0xFFFFF000L |
15863 | //GCMC_VM_MARC_LEN_LO_3 |
15864 | #define GCMC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3__SHIFT 0xc |
15865 | #define GCMC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3_MASK 0xFFFFF000L |
15866 | //GCMC_VM_MARC_LEN_LO_4 |
15867 | #define GCMC_VM_MARC_LEN_LO_4__MARC_LEN_LO_4__SHIFT 0xc |
15868 | #define GCMC_VM_MARC_LEN_LO_4__MARC_LEN_LO_4_MASK 0xFFFFF000L |
15869 | //GCMC_VM_MARC_LEN_LO_5 |
15870 | #define GCMC_VM_MARC_LEN_LO_5__MARC_LEN_LO_5__SHIFT 0xc |
15871 | #define GCMC_VM_MARC_LEN_LO_5__MARC_LEN_LO_5_MASK 0xFFFFF000L |
15872 | //GCMC_VM_MARC_LEN_LO_6 |
15873 | #define GCMC_VM_MARC_LEN_LO_6__MARC_LEN_LO_6__SHIFT 0xc |
15874 | #define GCMC_VM_MARC_LEN_LO_6__MARC_LEN_LO_6_MASK 0xFFFFF000L |
15875 | //GCMC_VM_MARC_LEN_LO_7 |
15876 | #define GCMC_VM_MARC_LEN_LO_7__MARC_LEN_LO_7__SHIFT 0xc |
15877 | #define GCMC_VM_MARC_LEN_LO_7__MARC_LEN_LO_7_MASK 0xFFFFF000L |
15878 | //GCMC_VM_MARC_LEN_LO_8 |
15879 | #define GCMC_VM_MARC_LEN_LO_8__MARC_LEN_LO_8__SHIFT 0xc |
15880 | #define GCMC_VM_MARC_LEN_LO_8__MARC_LEN_LO_8_MASK 0xFFFFF000L |
15881 | //GCMC_VM_MARC_LEN_LO_9 |
15882 | #define GCMC_VM_MARC_LEN_LO_9__MARC_LEN_LO_9__SHIFT 0xc |
15883 | #define GCMC_VM_MARC_LEN_LO_9__MARC_LEN_LO_9_MASK 0xFFFFF000L |
15884 | //GCMC_VM_MARC_LEN_LO_10 |
15885 | #define GCMC_VM_MARC_LEN_LO_10__MARC_LEN_LO_10__SHIFT 0xc |
15886 | #define GCMC_VM_MARC_LEN_LO_10__MARC_LEN_LO_10_MASK 0xFFFFF000L |
15887 | //GCMC_VM_MARC_LEN_LO_11 |
15888 | #define GCMC_VM_MARC_LEN_LO_11__MARC_LEN_LO_11__SHIFT 0xc |
15889 | #define GCMC_VM_MARC_LEN_LO_11__MARC_LEN_LO_11_MASK 0xFFFFF000L |
15890 | //GCMC_VM_MARC_LEN_LO_12 |
15891 | #define GCMC_VM_MARC_LEN_LO_12__MARC_LEN_LO_12__SHIFT 0xc |
15892 | #define GCMC_VM_MARC_LEN_LO_12__MARC_LEN_LO_12_MASK 0xFFFFF000L |
15893 | //GCMC_VM_MARC_LEN_LO_13 |
15894 | #define GCMC_VM_MARC_LEN_LO_13__MARC_LEN_LO_13__SHIFT 0xc |
15895 | #define GCMC_VM_MARC_LEN_LO_13__MARC_LEN_LO_13_MASK 0xFFFFF000L |
15896 | //GCMC_VM_MARC_LEN_LO_14 |
15897 | #define GCMC_VM_MARC_LEN_LO_14__MARC_LEN_LO_14__SHIFT 0xc |
15898 | #define GCMC_VM_MARC_LEN_LO_14__MARC_LEN_LO_14_MASK 0xFFFFF000L |
15899 | //GCMC_VM_MARC_LEN_LO_15 |
15900 | #define GCMC_VM_MARC_LEN_LO_15__MARC_LEN_LO_15__SHIFT 0xc |
15901 | #define GCMC_VM_MARC_LEN_LO_15__MARC_LEN_LO_15_MASK 0xFFFFF000L |
15902 | //GCMC_VM_MARC_LEN_HI_0 |
15903 | #define GCMC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0__SHIFT 0x0 |
15904 | #define GCMC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0_MASK 0x000FFFFFL |
15905 | //GCMC_VM_MARC_LEN_HI_1 |
15906 | #define GCMC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1__SHIFT 0x0 |
15907 | #define GCMC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1_MASK 0x000FFFFFL |
15908 | //GCMC_VM_MARC_LEN_HI_2 |
15909 | #define GCMC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2__SHIFT 0x0 |
15910 | #define GCMC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2_MASK 0x000FFFFFL |
15911 | //GCMC_VM_MARC_LEN_HI_3 |
15912 | #define GCMC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3__SHIFT 0x0 |
15913 | #define GCMC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3_MASK 0x000FFFFFL |
15914 | //GCMC_VM_MARC_LEN_HI_4 |
15915 | #define GCMC_VM_MARC_LEN_HI_4__MARC_LEN_HI_4__SHIFT 0x0 |
15916 | #define GCMC_VM_MARC_LEN_HI_4__MARC_LEN_HI_4_MASK 0x000FFFFFL |
15917 | //GCMC_VM_MARC_LEN_HI_5 |
15918 | #define GCMC_VM_MARC_LEN_HI_5__MARC_LEN_HI_5__SHIFT 0x0 |
15919 | #define GCMC_VM_MARC_LEN_HI_5__MARC_LEN_HI_5_MASK 0x000FFFFFL |
15920 | //GCMC_VM_MARC_LEN_HI_6 |
15921 | #define GCMC_VM_MARC_LEN_HI_6__MARC_LEN_HI_6__SHIFT 0x0 |
15922 | #define GCMC_VM_MARC_LEN_HI_6__MARC_LEN_HI_6_MASK 0x000FFFFFL |
15923 | //GCMC_VM_MARC_LEN_HI_7 |
15924 | #define GCMC_VM_MARC_LEN_HI_7__MARC_LEN_HI_7__SHIFT 0x0 |
15925 | #define GCMC_VM_MARC_LEN_HI_7__MARC_LEN_HI_7_MASK 0x000FFFFFL |
15926 | //GCMC_VM_MARC_LEN_HI_8 |
15927 | #define GCMC_VM_MARC_LEN_HI_8__MARC_LEN_HI_8__SHIFT 0x0 |
15928 | #define GCMC_VM_MARC_LEN_HI_8__MARC_LEN_HI_8_MASK 0x000FFFFFL |
15929 | //GCMC_VM_MARC_LEN_HI_9 |
15930 | #define GCMC_VM_MARC_LEN_HI_9__MARC_LEN_HI_9__SHIFT 0x0 |
15931 | #define GCMC_VM_MARC_LEN_HI_9__MARC_LEN_HI_9_MASK 0x000FFFFFL |
15932 | //GCMC_VM_MARC_LEN_HI_10 |
15933 | #define GCMC_VM_MARC_LEN_HI_10__MARC_LEN_HI_10__SHIFT 0x0 |
15934 | #define GCMC_VM_MARC_LEN_HI_10__MARC_LEN_HI_10_MASK 0x000FFFFFL |
15935 | //GCMC_VM_MARC_LEN_HI_11 |
15936 | #define GCMC_VM_MARC_LEN_HI_11__MARC_LEN_HI_11__SHIFT 0x0 |
15937 | #define GCMC_VM_MARC_LEN_HI_11__MARC_LEN_HI_11_MASK 0x000FFFFFL |
15938 | //GCMC_VM_MARC_LEN_HI_12 |
15939 | #define GCMC_VM_MARC_LEN_HI_12__MARC_LEN_HI_12__SHIFT 0x0 |
15940 | #define GCMC_VM_MARC_LEN_HI_12__MARC_LEN_HI_12_MASK 0x000FFFFFL |
15941 | //GCMC_VM_MARC_LEN_HI_13 |
15942 | #define GCMC_VM_MARC_LEN_HI_13__MARC_LEN_HI_13__SHIFT 0x0 |
15943 | #define GCMC_VM_MARC_LEN_HI_13__MARC_LEN_HI_13_MASK 0x000FFFFFL |
15944 | //GCMC_VM_MARC_LEN_HI_14 |
15945 | #define GCMC_VM_MARC_LEN_HI_14__MARC_LEN_HI_14__SHIFT 0x0 |
15946 | #define GCMC_VM_MARC_LEN_HI_14__MARC_LEN_HI_14_MASK 0x000FFFFFL |
15947 | //GCMC_VM_MARC_LEN_HI_15 |
15948 | #define GCMC_VM_MARC_LEN_HI_15__MARC_LEN_HI_15__SHIFT 0x0 |
15949 | #define GCMC_VM_MARC_LEN_HI_15__MARC_LEN_HI_15_MASK 0x000FFFFFL |
15950 | //GCMC_VM_MARC_PFVF_MAPPING_0 |
15951 | #define GCMC_VM_MARC_PFVF_MAPPING_0__ENABLE_VFS__SHIFT 0x0 |
15952 | #define GCMC_VM_MARC_PFVF_MAPPING_0__ENABLE_PF__SHIFT 0x10 |
15953 | #define GCMC_VM_MARC_PFVF_MAPPING_0__ENABLE_VFS_MASK 0x0000FFFFL |
15954 | #define GCMC_VM_MARC_PFVF_MAPPING_0__ENABLE_PF_MASK 0x00010000L |
15955 | //GCMC_VM_MARC_PFVF_MAPPING_1 |
15956 | #define GCMC_VM_MARC_PFVF_MAPPING_1__ENABLE_VFS__SHIFT 0x0 |
15957 | #define GCMC_VM_MARC_PFVF_MAPPING_1__ENABLE_PF__SHIFT 0x10 |
15958 | #define GCMC_VM_MARC_PFVF_MAPPING_1__ENABLE_VFS_MASK 0x0000FFFFL |
15959 | #define GCMC_VM_MARC_PFVF_MAPPING_1__ENABLE_PF_MASK 0x00010000L |
15960 | //GCMC_VM_MARC_PFVF_MAPPING_2 |
15961 | #define GCMC_VM_MARC_PFVF_MAPPING_2__ENABLE_VFS__SHIFT 0x0 |
15962 | #define GCMC_VM_MARC_PFVF_MAPPING_2__ENABLE_PF__SHIFT 0x10 |
15963 | #define GCMC_VM_MARC_PFVF_MAPPING_2__ENABLE_VFS_MASK 0x0000FFFFL |
15964 | #define GCMC_VM_MARC_PFVF_MAPPING_2__ENABLE_PF_MASK 0x00010000L |
15965 | //GCMC_VM_MARC_PFVF_MAPPING_3 |
15966 | #define GCMC_VM_MARC_PFVF_MAPPING_3__ENABLE_VFS__SHIFT 0x0 |
15967 | #define GCMC_VM_MARC_PFVF_MAPPING_3__ENABLE_PF__SHIFT 0x10 |
15968 | #define GCMC_VM_MARC_PFVF_MAPPING_3__ENABLE_VFS_MASK 0x0000FFFFL |
15969 | #define GCMC_VM_MARC_PFVF_MAPPING_3__ENABLE_PF_MASK 0x00010000L |
15970 | //GCMC_VM_MARC_PFVF_MAPPING_4 |
15971 | #define GCMC_VM_MARC_PFVF_MAPPING_4__ENABLE_VFS__SHIFT 0x0 |
15972 | #define GCMC_VM_MARC_PFVF_MAPPING_4__ENABLE_PF__SHIFT 0x10 |
15973 | #define GCMC_VM_MARC_PFVF_MAPPING_4__ENABLE_VFS_MASK 0x0000FFFFL |
15974 | #define GCMC_VM_MARC_PFVF_MAPPING_4__ENABLE_PF_MASK 0x00010000L |
15975 | //GCMC_VM_MARC_PFVF_MAPPING_5 |
15976 | #define GCMC_VM_MARC_PFVF_MAPPING_5__ENABLE_VFS__SHIFT 0x0 |
15977 | #define GCMC_VM_MARC_PFVF_MAPPING_5__ENABLE_PF__SHIFT 0x10 |
15978 | #define GCMC_VM_MARC_PFVF_MAPPING_5__ENABLE_VFS_MASK 0x0000FFFFL |
15979 | #define GCMC_VM_MARC_PFVF_MAPPING_5__ENABLE_PF_MASK 0x00010000L |
15980 | //GCMC_VM_MARC_PFVF_MAPPING_6 |
15981 | #define GCMC_VM_MARC_PFVF_MAPPING_6__ENABLE_VFS__SHIFT 0x0 |
15982 | #define GCMC_VM_MARC_PFVF_MAPPING_6__ENABLE_PF__SHIFT 0x10 |
15983 | #define GCMC_VM_MARC_PFVF_MAPPING_6__ENABLE_VFS_MASK 0x0000FFFFL |
15984 | #define GCMC_VM_MARC_PFVF_MAPPING_6__ENABLE_PF_MASK 0x00010000L |
15985 | //GCMC_VM_MARC_PFVF_MAPPING_7 |
15986 | #define GCMC_VM_MARC_PFVF_MAPPING_7__ENABLE_VFS__SHIFT 0x0 |
15987 | #define GCMC_VM_MARC_PFVF_MAPPING_7__ENABLE_PF__SHIFT 0x10 |
15988 | #define GCMC_VM_MARC_PFVF_MAPPING_7__ENABLE_VFS_MASK 0x0000FFFFL |
15989 | #define GCMC_VM_MARC_PFVF_MAPPING_7__ENABLE_PF_MASK 0x00010000L |
15990 | //GCMC_VM_MARC_PFVF_MAPPING_8 |
15991 | #define GCMC_VM_MARC_PFVF_MAPPING_8__ENABLE_VFS__SHIFT 0x0 |
15992 | #define GCMC_VM_MARC_PFVF_MAPPING_8__ENABLE_PF__SHIFT 0x10 |
15993 | #define GCMC_VM_MARC_PFVF_MAPPING_8__ENABLE_VFS_MASK 0x0000FFFFL |
15994 | #define GCMC_VM_MARC_PFVF_MAPPING_8__ENABLE_PF_MASK 0x00010000L |
15995 | //GCMC_VM_MARC_PFVF_MAPPING_9 |
15996 | #define GCMC_VM_MARC_PFVF_MAPPING_9__ENABLE_VFS__SHIFT 0x0 |
15997 | #define GCMC_VM_MARC_PFVF_MAPPING_9__ENABLE_PF__SHIFT 0x10 |
15998 | #define GCMC_VM_MARC_PFVF_MAPPING_9__ENABLE_VFS_MASK 0x0000FFFFL |
15999 | #define GCMC_VM_MARC_PFVF_MAPPING_9__ENABLE_PF_MASK 0x00010000L |
16000 | //GCMC_VM_MARC_PFVF_MAPPING_10 |
16001 | #define GCMC_VM_MARC_PFVF_MAPPING_10__ENABLE_VFS__SHIFT 0x0 |
16002 | #define GCMC_VM_MARC_PFVF_MAPPING_10__ENABLE_PF__SHIFT 0x10 |
16003 | #define GCMC_VM_MARC_PFVF_MAPPING_10__ENABLE_VFS_MASK 0x0000FFFFL |
16004 | #define GCMC_VM_MARC_PFVF_MAPPING_10__ENABLE_PF_MASK 0x00010000L |
16005 | //GCMC_VM_MARC_PFVF_MAPPING_11 |
16006 | #define GCMC_VM_MARC_PFVF_MAPPING_11__ENABLE_VFS__SHIFT 0x0 |
16007 | #define GCMC_VM_MARC_PFVF_MAPPING_11__ENABLE_PF__SHIFT 0x10 |
16008 | #define GCMC_VM_MARC_PFVF_MAPPING_11__ENABLE_VFS_MASK 0x0000FFFFL |
16009 | #define GCMC_VM_MARC_PFVF_MAPPING_11__ENABLE_PF_MASK 0x00010000L |
16010 | //GCMC_VM_MARC_PFVF_MAPPING_12 |
16011 | #define GCMC_VM_MARC_PFVF_MAPPING_12__ENABLE_VFS__SHIFT 0x0 |
16012 | #define GCMC_VM_MARC_PFVF_MAPPING_12__ENABLE_PF__SHIFT 0x10 |
16013 | #define GCMC_VM_MARC_PFVF_MAPPING_12__ENABLE_VFS_MASK 0x0000FFFFL |
16014 | #define GCMC_VM_MARC_PFVF_MAPPING_12__ENABLE_PF_MASK 0x00010000L |
16015 | //GCMC_VM_MARC_PFVF_MAPPING_13 |
16016 | #define GCMC_VM_MARC_PFVF_MAPPING_13__ENABLE_VFS__SHIFT 0x0 |
16017 | #define GCMC_VM_MARC_PFVF_MAPPING_13__ENABLE_PF__SHIFT 0x10 |
16018 | #define GCMC_VM_MARC_PFVF_MAPPING_13__ENABLE_VFS_MASK 0x0000FFFFL |
16019 | #define GCMC_VM_MARC_PFVF_MAPPING_13__ENABLE_PF_MASK 0x00010000L |
16020 | //GCMC_VM_MARC_PFVF_MAPPING_14 |
16021 | #define GCMC_VM_MARC_PFVF_MAPPING_14__ENABLE_VFS__SHIFT 0x0 |
16022 | #define GCMC_VM_MARC_PFVF_MAPPING_14__ENABLE_PF__SHIFT 0x10 |
16023 | #define GCMC_VM_MARC_PFVF_MAPPING_14__ENABLE_VFS_MASK 0x0000FFFFL |
16024 | #define GCMC_VM_MARC_PFVF_MAPPING_14__ENABLE_PF_MASK 0x00010000L |
16025 | //GCMC_VM_MARC_PFVF_MAPPING_15 |
16026 | #define GCMC_VM_MARC_PFVF_MAPPING_15__ENABLE_VFS__SHIFT 0x0 |
16027 | #define GCMC_VM_MARC_PFVF_MAPPING_15__ENABLE_PF__SHIFT 0x10 |
16028 | #define GCMC_VM_MARC_PFVF_MAPPING_15__ENABLE_VFS_MASK 0x0000FFFFL |
16029 | #define GCMC_VM_MARC_PFVF_MAPPING_15__ENABLE_PF_MASK 0x00010000L |
16030 | //GCUTC_TRANSLATION_FAULT_CNTL0 |
16031 | #define GCUTC_TRANSLATION_FAULT_CNTL0__DEFAULT_PHYSICAL_PAGE_ADDRESS_LSB__SHIFT 0x0 |
16032 | #define GCUTC_TRANSLATION_FAULT_CNTL0__DEFAULT_PHYSICAL_PAGE_ADDRESS_LSB_MASK 0xFFFFFFFFL |
16033 | //GCUTC_TRANSLATION_FAULT_CNTL1 |
16034 | #define GCUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_PHYSICAL_PAGE_ADDRESS_MSB__SHIFT 0x0 |
16035 | #define GCUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_IO__SHIFT 0x4 |
16036 | #define GCUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_SPA__SHIFT 0x5 |
16037 | #define GCUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_SNOOP__SHIFT 0x6 |
16038 | #define GCUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_PHYSICAL_PAGE_ADDRESS_MSB_MASK 0x0000000FL |
16039 | #define GCUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_IO_MASK 0x00000010L |
16040 | #define GCUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_SPA_MASK 0x00000020L |
16041 | #define GCUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_SNOOP_MASK 0x00000040L |
16042 | |
16043 | |
16044 | // addressBlock: gc_gcl2tlbpspdec |
16045 | //GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL |
16046 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL__ENABLE__SHIFT 0x0 |
16047 | #define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL__ENABLE_MASK 0x00000001L |
16048 | |
16049 | |
16050 | // addressBlock: gc_shdec |
16051 | //SPI_SHADER_PGM_RSRC4_PS |
16052 | #define SPI_SHADER_PGM_RSRC4_PS__CU_EN__SHIFT 0x0 |
16053 | #define SPI_SHADER_PGM_RSRC4_PS__INST_PREF_SIZE__SHIFT 0x10 |
16054 | #define SPI_SHADER_PGM_RSRC4_PS__TRAP_ON_START__SHIFT 0x1d |
16055 | #define SPI_SHADER_PGM_RSRC4_PS__TRAP_ON_END__SHIFT 0x1e |
16056 | #define SPI_SHADER_PGM_RSRC4_PS__IMAGE_OP__SHIFT 0x1f |
16057 | #define SPI_SHADER_PGM_RSRC4_PS__CU_EN_MASK 0x0000FFFFL |
16058 | #define SPI_SHADER_PGM_RSRC4_PS__INST_PREF_SIZE_MASK 0x003F0000L |
16059 | #define SPI_SHADER_PGM_RSRC4_PS__TRAP_ON_START_MASK 0x20000000L |
16060 | #define SPI_SHADER_PGM_RSRC4_PS__TRAP_ON_END_MASK 0x40000000L |
16061 | #define SPI_SHADER_PGM_RSRC4_PS__IMAGE_OP_MASK 0x80000000L |
16062 | //SPI_SHADER_PGM_CHKSUM_PS |
16063 | #define SPI_SHADER_PGM_CHKSUM_PS__CHECKSUM__SHIFT 0x0 |
16064 | #define SPI_SHADER_PGM_CHKSUM_PS__CHECKSUM_MASK 0xFFFFFFFFL |
16065 | //SPI_SHADER_PGM_RSRC3_PS |
16066 | #define SPI_SHADER_PGM_RSRC3_PS__CU_EN__SHIFT 0x0 |
16067 | #define SPI_SHADER_PGM_RSRC3_PS__WAVE_LIMIT__SHIFT 0x10 |
16068 | #define SPI_SHADER_PGM_RSRC3_PS__LDS_GROUP_SIZE__SHIFT 0x16 |
16069 | #define SPI_SHADER_PGM_RSRC3_PS__CU_EN_MASK 0x0000FFFFL |
16070 | #define SPI_SHADER_PGM_RSRC3_PS__WAVE_LIMIT_MASK 0x003F0000L |
16071 | #define SPI_SHADER_PGM_RSRC3_PS__LDS_GROUP_SIZE_MASK 0x00C00000L |
16072 | //SPI_SHADER_PGM_LO_PS |
16073 | #define SPI_SHADER_PGM_LO_PS__MEM_BASE__SHIFT 0x0 |
16074 | #define SPI_SHADER_PGM_LO_PS__MEM_BASE_MASK 0xFFFFFFFFL |
16075 | //SPI_SHADER_PGM_HI_PS |
16076 | #define SPI_SHADER_PGM_HI_PS__MEM_BASE__SHIFT 0x0 |
16077 | #define SPI_SHADER_PGM_HI_PS__MEM_BASE_MASK 0xFFL |
16078 | //SPI_SHADER_PGM_RSRC1_PS |
16079 | #define SPI_SHADER_PGM_RSRC1_PS__VGPRS__SHIFT 0x0 |
16080 | #define SPI_SHADER_PGM_RSRC1_PS__SGPRS__SHIFT 0x6 |
16081 | #define SPI_SHADER_PGM_RSRC1_PS__PRIORITY__SHIFT 0xa |
16082 | #define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE__SHIFT 0xc |
16083 | #define SPI_SHADER_PGM_RSRC1_PS__PRIV__SHIFT 0x14 |
16084 | #define SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP__SHIFT 0x15 |
16085 | #define SPI_SHADER_PGM_RSRC1_PS__DEBUG_MODE__SHIFT 0x16 |
16086 | #define SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE__SHIFT 0x17 |
16087 | #define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE__SHIFT 0x18 |
16088 | #define SPI_SHADER_PGM_RSRC1_PS__MEM_ORDERED__SHIFT 0x19 |
16089 | #define SPI_SHADER_PGM_RSRC1_PS__FWD_PROGRESS__SHIFT 0x1a |
16090 | #define SPI_SHADER_PGM_RSRC1_PS__LOAD_PROVOKING_VTX__SHIFT 0x1b |
16091 | #define SPI_SHADER_PGM_RSRC1_PS__CDBG_USER__SHIFT 0x1c |
16092 | #define SPI_SHADER_PGM_RSRC1_PS__FP16_OVFL__SHIFT 0x1d |
16093 | #define SPI_SHADER_PGM_RSRC1_PS__VGPRS_MASK 0x0000003FL |
16094 | #define SPI_SHADER_PGM_RSRC1_PS__SGPRS_MASK 0x000003C0L |
16095 | #define SPI_SHADER_PGM_RSRC1_PS__PRIORITY_MASK 0x00000C00L |
16096 | #define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE_MASK 0x000FF000L |
16097 | #define SPI_SHADER_PGM_RSRC1_PS__PRIV_MASK 0x00100000L |
16098 | #define SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP_MASK 0x00200000L |
16099 | #define SPI_SHADER_PGM_RSRC1_PS__DEBUG_MODE_MASK 0x00400000L |
16100 | #define SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE_MASK 0x00800000L |
16101 | #define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE_MASK 0x01000000L |
16102 | #define SPI_SHADER_PGM_RSRC1_PS__MEM_ORDERED_MASK 0x02000000L |
16103 | #define SPI_SHADER_PGM_RSRC1_PS__FWD_PROGRESS_MASK 0x04000000L |
16104 | #define SPI_SHADER_PGM_RSRC1_PS__LOAD_PROVOKING_VTX_MASK 0x08000000L |
16105 | #define SPI_SHADER_PGM_RSRC1_PS__CDBG_USER_MASK 0x10000000L |
16106 | #define SPI_SHADER_PGM_RSRC1_PS__FP16_OVFL_MASK 0x20000000L |
16107 | //SPI_SHADER_PGM_RSRC2_PS |
16108 | #define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN__SHIFT 0x0 |
16109 | #define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR__SHIFT 0x1 |
16110 | #define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT__SHIFT 0x6 |
16111 | #define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN__SHIFT 0x7 |
16112 | #define 0x8 |
16113 | #define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN__SHIFT 0x10 |
16114 | #define SPI_SHADER_PGM_RSRC2_PS__LOAD_COLLISION_WAVEID__SHIFT 0x19 |
16115 | #define SPI_SHADER_PGM_RSRC2_PS__LOAD_INTRAWAVE_COLLISION__SHIFT 0x1a |
16116 | #define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MSB__SHIFT 0x1b |
16117 | #define SPI_SHADER_PGM_RSRC2_PS__SHARED_VGPR_CNT__SHIFT 0x1c |
16118 | #define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN_MASK 0x00000001L |
16119 | #define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MASK 0x0000003EL |
16120 | #define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT_MASK 0x00000040L |
16121 | #define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN_MASK 0x00000080L |
16122 | #define 0x0000FF00L |
16123 | #define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN_MASK 0x01FF0000L |
16124 | #define SPI_SHADER_PGM_RSRC2_PS__LOAD_COLLISION_WAVEID_MASK 0x02000000L |
16125 | #define SPI_SHADER_PGM_RSRC2_PS__LOAD_INTRAWAVE_COLLISION_MASK 0x04000000L |
16126 | #define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MSB_MASK 0x08000000L |
16127 | #define SPI_SHADER_PGM_RSRC2_PS__SHARED_VGPR_CNT_MASK 0xF0000000L |
16128 | //SPI_SHADER_USER_DATA_PS_0 |
16129 | #define SPI_SHADER_USER_DATA_PS_0__DATA__SHIFT 0x0 |
16130 | #define SPI_SHADER_USER_DATA_PS_0__DATA_MASK 0xFFFFFFFFL |
16131 | //SPI_SHADER_USER_DATA_PS_1 |
16132 | #define SPI_SHADER_USER_DATA_PS_1__DATA__SHIFT 0x0 |
16133 | #define SPI_SHADER_USER_DATA_PS_1__DATA_MASK 0xFFFFFFFFL |
16134 | //SPI_SHADER_USER_DATA_PS_2 |
16135 | #define SPI_SHADER_USER_DATA_PS_2__DATA__SHIFT 0x0 |
16136 | #define SPI_SHADER_USER_DATA_PS_2__DATA_MASK 0xFFFFFFFFL |
16137 | //SPI_SHADER_USER_DATA_PS_3 |
16138 | #define SPI_SHADER_USER_DATA_PS_3__DATA__SHIFT 0x0 |
16139 | #define SPI_SHADER_USER_DATA_PS_3__DATA_MASK 0xFFFFFFFFL |
16140 | //SPI_SHADER_USER_DATA_PS_4 |
16141 | #define SPI_SHADER_USER_DATA_PS_4__DATA__SHIFT 0x0 |
16142 | #define SPI_SHADER_USER_DATA_PS_4__DATA_MASK 0xFFFFFFFFL |
16143 | //SPI_SHADER_USER_DATA_PS_5 |
16144 | #define SPI_SHADER_USER_DATA_PS_5__DATA__SHIFT 0x0 |
16145 | #define SPI_SHADER_USER_DATA_PS_5__DATA_MASK 0xFFFFFFFFL |
16146 | //SPI_SHADER_USER_DATA_PS_6 |
16147 | #define SPI_SHADER_USER_DATA_PS_6__DATA__SHIFT 0x0 |
16148 | #define SPI_SHADER_USER_DATA_PS_6__DATA_MASK 0xFFFFFFFFL |
16149 | //SPI_SHADER_USER_DATA_PS_7 |
16150 | #define SPI_SHADER_USER_DATA_PS_7__DATA__SHIFT 0x0 |
16151 | #define SPI_SHADER_USER_DATA_PS_7__DATA_MASK 0xFFFFFFFFL |
16152 | //SPI_SHADER_USER_DATA_PS_8 |
16153 | #define SPI_SHADER_USER_DATA_PS_8__DATA__SHIFT 0x0 |
16154 | #define SPI_SHADER_USER_DATA_PS_8__DATA_MASK 0xFFFFFFFFL |
16155 | //SPI_SHADER_USER_DATA_PS_9 |
16156 | #define SPI_SHADER_USER_DATA_PS_9__DATA__SHIFT 0x0 |
16157 | #define SPI_SHADER_USER_DATA_PS_9__DATA_MASK 0xFFFFFFFFL |
16158 | //SPI_SHADER_USER_DATA_PS_10 |
16159 | #define SPI_SHADER_USER_DATA_PS_10__DATA__SHIFT 0x0 |
16160 | #define SPI_SHADER_USER_DATA_PS_10__DATA_MASK 0xFFFFFFFFL |
16161 | //SPI_SHADER_USER_DATA_PS_11 |
16162 | #define SPI_SHADER_USER_DATA_PS_11__DATA__SHIFT 0x0 |
16163 | #define SPI_SHADER_USER_DATA_PS_11__DATA_MASK 0xFFFFFFFFL |
16164 | //SPI_SHADER_USER_DATA_PS_12 |
16165 | #define SPI_SHADER_USER_DATA_PS_12__DATA__SHIFT 0x0 |
16166 | #define SPI_SHADER_USER_DATA_PS_12__DATA_MASK 0xFFFFFFFFL |
16167 | //SPI_SHADER_USER_DATA_PS_13 |
16168 | #define SPI_SHADER_USER_DATA_PS_13__DATA__SHIFT 0x0 |
16169 | #define SPI_SHADER_USER_DATA_PS_13__DATA_MASK 0xFFFFFFFFL |
16170 | //SPI_SHADER_USER_DATA_PS_14 |
16171 | #define SPI_SHADER_USER_DATA_PS_14__DATA__SHIFT 0x0 |
16172 | #define SPI_SHADER_USER_DATA_PS_14__DATA_MASK 0xFFFFFFFFL |
16173 | //SPI_SHADER_USER_DATA_PS_15 |
16174 | #define SPI_SHADER_USER_DATA_PS_15__DATA__SHIFT 0x0 |
16175 | #define SPI_SHADER_USER_DATA_PS_15__DATA_MASK 0xFFFFFFFFL |
16176 | //SPI_SHADER_USER_DATA_PS_16 |
16177 | #define SPI_SHADER_USER_DATA_PS_16__DATA__SHIFT 0x0 |
16178 | #define SPI_SHADER_USER_DATA_PS_16__DATA_MASK 0xFFFFFFFFL |
16179 | //SPI_SHADER_USER_DATA_PS_17 |
16180 | #define SPI_SHADER_USER_DATA_PS_17__DATA__SHIFT 0x0 |
16181 | #define SPI_SHADER_USER_DATA_PS_17__DATA_MASK 0xFFFFFFFFL |
16182 | //SPI_SHADER_USER_DATA_PS_18 |
16183 | #define SPI_SHADER_USER_DATA_PS_18__DATA__SHIFT 0x0 |
16184 | #define SPI_SHADER_USER_DATA_PS_18__DATA_MASK 0xFFFFFFFFL |
16185 | //SPI_SHADER_USER_DATA_PS_19 |
16186 | #define SPI_SHADER_USER_DATA_PS_19__DATA__SHIFT 0x0 |
16187 | #define SPI_SHADER_USER_DATA_PS_19__DATA_MASK 0xFFFFFFFFL |
16188 | //SPI_SHADER_USER_DATA_PS_20 |
16189 | #define SPI_SHADER_USER_DATA_PS_20__DATA__SHIFT 0x0 |
16190 | #define SPI_SHADER_USER_DATA_PS_20__DATA_MASK 0xFFFFFFFFL |
16191 | //SPI_SHADER_USER_DATA_PS_21 |
16192 | #define SPI_SHADER_USER_DATA_PS_21__DATA__SHIFT 0x0 |
16193 | #define SPI_SHADER_USER_DATA_PS_21__DATA_MASK 0xFFFFFFFFL |
16194 | //SPI_SHADER_USER_DATA_PS_22 |
16195 | #define SPI_SHADER_USER_DATA_PS_22__DATA__SHIFT 0x0 |
16196 | #define SPI_SHADER_USER_DATA_PS_22__DATA_MASK 0xFFFFFFFFL |
16197 | //SPI_SHADER_USER_DATA_PS_23 |
16198 | #define SPI_SHADER_USER_DATA_PS_23__DATA__SHIFT 0x0 |
16199 | #define SPI_SHADER_USER_DATA_PS_23__DATA_MASK 0xFFFFFFFFL |
16200 | //SPI_SHADER_USER_DATA_PS_24 |
16201 | #define SPI_SHADER_USER_DATA_PS_24__DATA__SHIFT 0x0 |
16202 | #define SPI_SHADER_USER_DATA_PS_24__DATA_MASK 0xFFFFFFFFL |
16203 | //SPI_SHADER_USER_DATA_PS_25 |
16204 | #define SPI_SHADER_USER_DATA_PS_25__DATA__SHIFT 0x0 |
16205 | #define SPI_SHADER_USER_DATA_PS_25__DATA_MASK 0xFFFFFFFFL |
16206 | //SPI_SHADER_USER_DATA_PS_26 |
16207 | #define SPI_SHADER_USER_DATA_PS_26__DATA__SHIFT 0x0 |
16208 | #define SPI_SHADER_USER_DATA_PS_26__DATA_MASK 0xFFFFFFFFL |
16209 | //SPI_SHADER_USER_DATA_PS_27 |
16210 | #define SPI_SHADER_USER_DATA_PS_27__DATA__SHIFT 0x0 |
16211 | #define SPI_SHADER_USER_DATA_PS_27__DATA_MASK 0xFFFFFFFFL |
16212 | //SPI_SHADER_USER_DATA_PS_28 |
16213 | #define SPI_SHADER_USER_DATA_PS_28__DATA__SHIFT 0x0 |
16214 | #define SPI_SHADER_USER_DATA_PS_28__DATA_MASK 0xFFFFFFFFL |
16215 | //SPI_SHADER_USER_DATA_PS_29 |
16216 | #define SPI_SHADER_USER_DATA_PS_29__DATA__SHIFT 0x0 |
16217 | #define SPI_SHADER_USER_DATA_PS_29__DATA_MASK 0xFFFFFFFFL |
16218 | //SPI_SHADER_USER_DATA_PS_30 |
16219 | #define SPI_SHADER_USER_DATA_PS_30__DATA__SHIFT 0x0 |
16220 | #define SPI_SHADER_USER_DATA_PS_30__DATA_MASK 0xFFFFFFFFL |
16221 | //SPI_SHADER_USER_DATA_PS_31 |
16222 | #define SPI_SHADER_USER_DATA_PS_31__DATA__SHIFT 0x0 |
16223 | #define SPI_SHADER_USER_DATA_PS_31__DATA_MASK 0xFFFFFFFFL |
16224 | //SPI_SHADER_REQ_CTRL_PS |
16225 | #define SPI_SHADER_REQ_CTRL_PS__SOFT_GROUPING_EN__SHIFT 0x0 |
16226 | #define SPI_SHADER_REQ_CTRL_PS__NUMBER_OF_REQUESTS_PER_CU__SHIFT 0x1 |
16227 | #define SPI_SHADER_REQ_CTRL_PS__SOFT_GROUPING_ALLOCATION_TIMEOUT__SHIFT 0x5 |
16228 | #define SPI_SHADER_REQ_CTRL_PS__HARD_LOCK_HYSTERESIS__SHIFT 0x9 |
16229 | #define SPI_SHADER_REQ_CTRL_PS__HARD_LOCK_LOW_THRESHOLD__SHIFT 0xa |
16230 | #define SPI_SHADER_REQ_CTRL_PS__PRODUCER_REQUEST_LOCKOUT__SHIFT 0xf |
16231 | #define SPI_SHADER_REQ_CTRL_PS__GLOBAL_SCANNING_EN__SHIFT 0x10 |
16232 | #define SPI_SHADER_REQ_CTRL_PS__ALLOCATION_RATE_THROTTLING_THRESHOLD__SHIFT 0x11 |
16233 | #define SPI_SHADER_REQ_CTRL_PS__SOFT_GROUPING_EN_MASK 0x00000001L |
16234 | #define SPI_SHADER_REQ_CTRL_PS__NUMBER_OF_REQUESTS_PER_CU_MASK 0x0000001EL |
16235 | #define SPI_SHADER_REQ_CTRL_PS__SOFT_GROUPING_ALLOCATION_TIMEOUT_MASK 0x000001E0L |
16236 | #define SPI_SHADER_REQ_CTRL_PS__HARD_LOCK_HYSTERESIS_MASK 0x00000200L |
16237 | #define SPI_SHADER_REQ_CTRL_PS__HARD_LOCK_LOW_THRESHOLD_MASK 0x00007C00L |
16238 | #define SPI_SHADER_REQ_CTRL_PS__PRODUCER_REQUEST_LOCKOUT_MASK 0x00008000L |
16239 | #define SPI_SHADER_REQ_CTRL_PS__GLOBAL_SCANNING_EN_MASK 0x00010000L |
16240 | #define SPI_SHADER_REQ_CTRL_PS__ALLOCATION_RATE_THROTTLING_THRESHOLD_MASK 0x000E0000L |
16241 | //SPI_SHADER_USER_ACCUM_PS_0 |
16242 | #define SPI_SHADER_USER_ACCUM_PS_0__CONTRIBUTION__SHIFT 0x0 |
16243 | #define SPI_SHADER_USER_ACCUM_PS_0__CONTRIBUTION_MASK 0x0000007FL |
16244 | //SPI_SHADER_USER_ACCUM_PS_1 |
16245 | #define SPI_SHADER_USER_ACCUM_PS_1__CONTRIBUTION__SHIFT 0x0 |
16246 | #define SPI_SHADER_USER_ACCUM_PS_1__CONTRIBUTION_MASK 0x0000007FL |
16247 | //SPI_SHADER_USER_ACCUM_PS_2 |
16248 | #define SPI_SHADER_USER_ACCUM_PS_2__CONTRIBUTION__SHIFT 0x0 |
16249 | #define SPI_SHADER_USER_ACCUM_PS_2__CONTRIBUTION_MASK 0x0000007FL |
16250 | //SPI_SHADER_USER_ACCUM_PS_3 |
16251 | #define SPI_SHADER_USER_ACCUM_PS_3__CONTRIBUTION__SHIFT 0x0 |
16252 | #define SPI_SHADER_USER_ACCUM_PS_3__CONTRIBUTION_MASK 0x0000007FL |
16253 | //SPI_SHADER_PGM_CHKSUM_GS |
16254 | #define SPI_SHADER_PGM_CHKSUM_GS__CHECKSUM__SHIFT 0x0 |
16255 | #define SPI_SHADER_PGM_CHKSUM_GS__CHECKSUM_MASK 0xFFFFFFFFL |
16256 | //SPI_SHADER_PGM_RSRC4_GS |
16257 | #define SPI_SHADER_PGM_RSRC4_GS__CU_EN__SHIFT 0x0 |
16258 | #define SPI_SHADER_PGM_RSRC4_GS__RESERVED__SHIFT 0x1 |
16259 | #define SPI_SHADER_PGM_RSRC4_GS__PH_THROTTLE_EN__SHIFT 0xe |
16260 | #define SPI_SHADER_PGM_RSRC4_GS__SPI_THROTTLE_EN__SHIFT 0xf |
16261 | #define SPI_SHADER_PGM_RSRC4_GS__SPI_SHADER_LATE_ALLOC_GS__SHIFT 0x10 |
16262 | #define SPI_SHADER_PGM_RSRC4_GS__INST_PREF_SIZE__SHIFT 0x17 |
16263 | #define SPI_SHADER_PGM_RSRC4_GS__TRAP_ON_START__SHIFT 0x1d |
16264 | #define SPI_SHADER_PGM_RSRC4_GS__TRAP_ON_END__SHIFT 0x1e |
16265 | #define SPI_SHADER_PGM_RSRC4_GS__IMAGE_OP__SHIFT 0x1f |
16266 | #define SPI_SHADER_PGM_RSRC4_GS__CU_EN_MASK 0x00000001L |
16267 | #define SPI_SHADER_PGM_RSRC4_GS__RESERVED_MASK 0x00003FFEL |
16268 | #define SPI_SHADER_PGM_RSRC4_GS__PH_THROTTLE_EN_MASK 0x00004000L |
16269 | #define SPI_SHADER_PGM_RSRC4_GS__SPI_THROTTLE_EN_MASK 0x00008000L |
16270 | #define SPI_SHADER_PGM_RSRC4_GS__SPI_SHADER_LATE_ALLOC_GS_MASK 0x007F0000L |
16271 | #define SPI_SHADER_PGM_RSRC4_GS__INST_PREF_SIZE_MASK 0x1F800000L |
16272 | #define SPI_SHADER_PGM_RSRC4_GS__TRAP_ON_START_MASK 0x20000000L |
16273 | #define SPI_SHADER_PGM_RSRC4_GS__TRAP_ON_END_MASK 0x40000000L |
16274 | #define SPI_SHADER_PGM_RSRC4_GS__IMAGE_OP_MASK 0x80000000L |
16275 | //SPI_SHADER_USER_DATA_ADDR_LO_GS |
16276 | #define SPI_SHADER_USER_DATA_ADDR_LO_GS__MEM_BASE__SHIFT 0x0 |
16277 | #define SPI_SHADER_USER_DATA_ADDR_LO_GS__MEM_BASE_MASK 0xFFFFFFFFL |
16278 | //SPI_SHADER_USER_DATA_ADDR_HI_GS |
16279 | #define SPI_SHADER_USER_DATA_ADDR_HI_GS__MEM_BASE__SHIFT 0x0 |
16280 | #define SPI_SHADER_USER_DATA_ADDR_HI_GS__MEM_BASE_MASK 0xFFFFFFFFL |
16281 | //SPI_SHADER_PGM_LO_ES_GS |
16282 | #define SPI_SHADER_PGM_LO_ES_GS__MEM_BASE__SHIFT 0x0 |
16283 | #define SPI_SHADER_PGM_LO_ES_GS__MEM_BASE_MASK 0xFFFFFFFFL |
16284 | //SPI_SHADER_PGM_HI_ES_GS |
16285 | #define SPI_SHADER_PGM_HI_ES_GS__MEM_BASE__SHIFT 0x0 |
16286 | #define SPI_SHADER_PGM_HI_ES_GS__MEM_BASE_MASK 0xFFL |
16287 | //SPI_SHADER_PGM_RSRC3_GS |
16288 | #define SPI_SHADER_PGM_RSRC3_GS__CU_EN__SHIFT 0x0 |
16289 | #define SPI_SHADER_PGM_RSRC3_GS__WAVE_LIMIT__SHIFT 0x10 |
16290 | #define SPI_SHADER_PGM_RSRC3_GS__LOCK_LOW_THRESHOLD__SHIFT 0x16 |
16291 | #define SPI_SHADER_PGM_RSRC3_GS__GROUP_FIFO_DEPTH__SHIFT 0x1a |
16292 | #define SPI_SHADER_PGM_RSRC3_GS__CU_EN_MASK 0x0000FFFFL |
16293 | #define SPI_SHADER_PGM_RSRC3_GS__WAVE_LIMIT_MASK 0x003F0000L |
16294 | #define SPI_SHADER_PGM_RSRC3_GS__LOCK_LOW_THRESHOLD_MASK 0x03C00000L |
16295 | #define SPI_SHADER_PGM_RSRC3_GS__GROUP_FIFO_DEPTH_MASK 0xFC000000L |
16296 | //SPI_SHADER_PGM_LO_GS |
16297 | #define SPI_SHADER_PGM_LO_GS__MEM_BASE__SHIFT 0x0 |
16298 | #define SPI_SHADER_PGM_LO_GS__MEM_BASE_MASK 0xFFFFFFFFL |
16299 | //SPI_SHADER_PGM_HI_GS |
16300 | #define SPI_SHADER_PGM_HI_GS__MEM_BASE__SHIFT 0x0 |
16301 | #define SPI_SHADER_PGM_HI_GS__MEM_BASE_MASK 0xFFFFFFFFL |
16302 | //SPI_SHADER_PGM_RSRC1_GS |
16303 | #define SPI_SHADER_PGM_RSRC1_GS__VGPRS__SHIFT 0x0 |
16304 | #define SPI_SHADER_PGM_RSRC1_GS__SGPRS__SHIFT 0x6 |
16305 | #define SPI_SHADER_PGM_RSRC1_GS__PRIORITY__SHIFT 0xa |
16306 | #define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE__SHIFT 0xc |
16307 | #define SPI_SHADER_PGM_RSRC1_GS__PRIV__SHIFT 0x14 |
16308 | #define SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP__SHIFT 0x15 |
16309 | #define SPI_SHADER_PGM_RSRC1_GS__DEBUG_MODE__SHIFT 0x16 |
16310 | #define SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE__SHIFT 0x17 |
16311 | #define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE__SHIFT 0x18 |
16312 | #define SPI_SHADER_PGM_RSRC1_GS__MEM_ORDERED__SHIFT 0x19 |
16313 | #define SPI_SHADER_PGM_RSRC1_GS__FWD_PROGRESS__SHIFT 0x1a |
16314 | #define SPI_SHADER_PGM_RSRC1_GS__WGP_MODE__SHIFT 0x1b |
16315 | #define SPI_SHADER_PGM_RSRC1_GS__CDBG_USER__SHIFT 0x1c |
16316 | #define SPI_SHADER_PGM_RSRC1_GS__GS_VGPR_COMP_CNT__SHIFT 0x1d |
16317 | #define SPI_SHADER_PGM_RSRC1_GS__FP16_OVFL__SHIFT 0x1f |
16318 | #define SPI_SHADER_PGM_RSRC1_GS__VGPRS_MASK 0x0000003FL |
16319 | #define SPI_SHADER_PGM_RSRC1_GS__SGPRS_MASK 0x000003C0L |
16320 | #define SPI_SHADER_PGM_RSRC1_GS__PRIORITY_MASK 0x00000C00L |
16321 | #define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE_MASK 0x000FF000L |
16322 | #define SPI_SHADER_PGM_RSRC1_GS__PRIV_MASK 0x00100000L |
16323 | #define SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP_MASK 0x00200000L |
16324 | #define SPI_SHADER_PGM_RSRC1_GS__DEBUG_MODE_MASK 0x00400000L |
16325 | #define SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE_MASK 0x00800000L |
16326 | #define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE_MASK 0x01000000L |
16327 | #define SPI_SHADER_PGM_RSRC1_GS__MEM_ORDERED_MASK 0x02000000L |
16328 | #define SPI_SHADER_PGM_RSRC1_GS__FWD_PROGRESS_MASK 0x04000000L |
16329 | #define SPI_SHADER_PGM_RSRC1_GS__WGP_MODE_MASK 0x08000000L |
16330 | #define SPI_SHADER_PGM_RSRC1_GS__CDBG_USER_MASK 0x10000000L |
16331 | #define SPI_SHADER_PGM_RSRC1_GS__GS_VGPR_COMP_CNT_MASK 0x60000000L |
16332 | #define SPI_SHADER_PGM_RSRC1_GS__FP16_OVFL_MASK 0x80000000L |
16333 | //SPI_SHADER_PGM_RSRC2_GS |
16334 | #define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN__SHIFT 0x0 |
16335 | #define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR__SHIFT 0x1 |
16336 | #define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT__SHIFT 0x6 |
16337 | #define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN__SHIFT 0x7 |
16338 | #define SPI_SHADER_PGM_RSRC2_GS__ES_VGPR_COMP_CNT__SHIFT 0x10 |
16339 | #define SPI_SHADER_PGM_RSRC2_GS__OC_LDS_EN__SHIFT 0x12 |
16340 | #define SPI_SHADER_PGM_RSRC2_GS__LDS_SIZE__SHIFT 0x13 |
16341 | #define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MSB__SHIFT 0x1b |
16342 | #define SPI_SHADER_PGM_RSRC2_GS__SHARED_VGPR_CNT__SHIFT 0x1c |
16343 | #define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN_MASK 0x00000001L |
16344 | #define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MASK 0x0000003EL |
16345 | #define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT_MASK 0x00000040L |
16346 | #define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN_MASK 0x0000FF80L |
16347 | #define SPI_SHADER_PGM_RSRC2_GS__ES_VGPR_COMP_CNT_MASK 0x00030000L |
16348 | #define SPI_SHADER_PGM_RSRC2_GS__OC_LDS_EN_MASK 0x00040000L |
16349 | #define SPI_SHADER_PGM_RSRC2_GS__LDS_SIZE_MASK 0x07F80000L |
16350 | #define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MSB_MASK 0x08000000L |
16351 | #define SPI_SHADER_PGM_RSRC2_GS__SHARED_VGPR_CNT_MASK 0xF0000000L |
16352 | //SPI_SHADER_USER_DATA_GS_0 |
16353 | #define SPI_SHADER_USER_DATA_GS_0__DATA__SHIFT 0x0 |
16354 | #define SPI_SHADER_USER_DATA_GS_0__DATA_MASK 0xFFFFFFFFL |
16355 | //SPI_SHADER_USER_DATA_GS_1 |
16356 | #define SPI_SHADER_USER_DATA_GS_1__DATA__SHIFT 0x0 |
16357 | #define SPI_SHADER_USER_DATA_GS_1__DATA_MASK 0xFFFFFFFFL |
16358 | //SPI_SHADER_USER_DATA_GS_2 |
16359 | #define SPI_SHADER_USER_DATA_GS_2__DATA__SHIFT 0x0 |
16360 | #define SPI_SHADER_USER_DATA_GS_2__DATA_MASK 0xFFFFFFFFL |
16361 | //SPI_SHADER_USER_DATA_GS_3 |
16362 | #define SPI_SHADER_USER_DATA_GS_3__DATA__SHIFT 0x0 |
16363 | #define SPI_SHADER_USER_DATA_GS_3__DATA_MASK 0xFFFFFFFFL |
16364 | //SPI_SHADER_USER_DATA_GS_4 |
16365 | #define SPI_SHADER_USER_DATA_GS_4__DATA__SHIFT 0x0 |
16366 | #define SPI_SHADER_USER_DATA_GS_4__DATA_MASK 0xFFFFFFFFL |
16367 | //SPI_SHADER_USER_DATA_GS_5 |
16368 | #define SPI_SHADER_USER_DATA_GS_5__DATA__SHIFT 0x0 |
16369 | #define SPI_SHADER_USER_DATA_GS_5__DATA_MASK 0xFFFFFFFFL |
16370 | //SPI_SHADER_USER_DATA_GS_6 |
16371 | #define SPI_SHADER_USER_DATA_GS_6__DATA__SHIFT 0x0 |
16372 | #define SPI_SHADER_USER_DATA_GS_6__DATA_MASK 0xFFFFFFFFL |
16373 | //SPI_SHADER_USER_DATA_GS_7 |
16374 | #define SPI_SHADER_USER_DATA_GS_7__DATA__SHIFT 0x0 |
16375 | #define SPI_SHADER_USER_DATA_GS_7__DATA_MASK 0xFFFFFFFFL |
16376 | //SPI_SHADER_USER_DATA_GS_8 |
16377 | #define SPI_SHADER_USER_DATA_GS_8__DATA__SHIFT 0x0 |
16378 | #define SPI_SHADER_USER_DATA_GS_8__DATA_MASK 0xFFFFFFFFL |
16379 | //SPI_SHADER_USER_DATA_GS_9 |
16380 | #define SPI_SHADER_USER_DATA_GS_9__DATA__SHIFT 0x0 |
16381 | #define SPI_SHADER_USER_DATA_GS_9__DATA_MASK 0xFFFFFFFFL |
16382 | //SPI_SHADER_USER_DATA_GS_10 |
16383 | #define SPI_SHADER_USER_DATA_GS_10__DATA__SHIFT 0x0 |
16384 | #define SPI_SHADER_USER_DATA_GS_10__DATA_MASK 0xFFFFFFFFL |
16385 | //SPI_SHADER_USER_DATA_GS_11 |
16386 | #define SPI_SHADER_USER_DATA_GS_11__DATA__SHIFT 0x0 |
16387 | #define SPI_SHADER_USER_DATA_GS_11__DATA_MASK 0xFFFFFFFFL |
16388 | //SPI_SHADER_USER_DATA_GS_12 |
16389 | #define SPI_SHADER_USER_DATA_GS_12__DATA__SHIFT 0x0 |
16390 | #define SPI_SHADER_USER_DATA_GS_12__DATA_MASK 0xFFFFFFFFL |
16391 | //SPI_SHADER_USER_DATA_GS_13 |
16392 | #define SPI_SHADER_USER_DATA_GS_13__DATA__SHIFT 0x0 |
16393 | #define SPI_SHADER_USER_DATA_GS_13__DATA_MASK 0xFFFFFFFFL |
16394 | //SPI_SHADER_USER_DATA_GS_14 |
16395 | #define SPI_SHADER_USER_DATA_GS_14__DATA__SHIFT 0x0 |
16396 | #define SPI_SHADER_USER_DATA_GS_14__DATA_MASK 0xFFFFFFFFL |
16397 | //SPI_SHADER_USER_DATA_GS_15 |
16398 | #define SPI_SHADER_USER_DATA_GS_15__DATA__SHIFT 0x0 |
16399 | #define SPI_SHADER_USER_DATA_GS_15__DATA_MASK 0xFFFFFFFFL |
16400 | //SPI_SHADER_USER_DATA_GS_16 |
16401 | #define SPI_SHADER_USER_DATA_GS_16__DATA__SHIFT 0x0 |
16402 | #define SPI_SHADER_USER_DATA_GS_16__DATA_MASK 0xFFFFFFFFL |
16403 | //SPI_SHADER_USER_DATA_GS_17 |
16404 | #define SPI_SHADER_USER_DATA_GS_17__DATA__SHIFT 0x0 |
16405 | #define SPI_SHADER_USER_DATA_GS_17__DATA_MASK 0xFFFFFFFFL |
16406 | //SPI_SHADER_USER_DATA_GS_18 |
16407 | #define SPI_SHADER_USER_DATA_GS_18__DATA__SHIFT 0x0 |
16408 | #define SPI_SHADER_USER_DATA_GS_18__DATA_MASK 0xFFFFFFFFL |
16409 | //SPI_SHADER_USER_DATA_GS_19 |
16410 | #define SPI_SHADER_USER_DATA_GS_19__DATA__SHIFT 0x0 |
16411 | #define SPI_SHADER_USER_DATA_GS_19__DATA_MASK 0xFFFFFFFFL |
16412 | //SPI_SHADER_USER_DATA_GS_20 |
16413 | #define SPI_SHADER_USER_DATA_GS_20__DATA__SHIFT 0x0 |
16414 | #define SPI_SHADER_USER_DATA_GS_20__DATA_MASK 0xFFFFFFFFL |
16415 | //SPI_SHADER_USER_DATA_GS_21 |
16416 | #define SPI_SHADER_USER_DATA_GS_21__DATA__SHIFT 0x0 |
16417 | #define SPI_SHADER_USER_DATA_GS_21__DATA_MASK 0xFFFFFFFFL |
16418 | //SPI_SHADER_USER_DATA_GS_22 |
16419 | #define SPI_SHADER_USER_DATA_GS_22__DATA__SHIFT 0x0 |
16420 | #define SPI_SHADER_USER_DATA_GS_22__DATA_MASK 0xFFFFFFFFL |
16421 | //SPI_SHADER_USER_DATA_GS_23 |
16422 | #define SPI_SHADER_USER_DATA_GS_23__DATA__SHIFT 0x0 |
16423 | #define SPI_SHADER_USER_DATA_GS_23__DATA_MASK 0xFFFFFFFFL |
16424 | //SPI_SHADER_USER_DATA_GS_24 |
16425 | #define SPI_SHADER_USER_DATA_GS_24__DATA__SHIFT 0x0 |
16426 | #define SPI_SHADER_USER_DATA_GS_24__DATA_MASK 0xFFFFFFFFL |
16427 | //SPI_SHADER_USER_DATA_GS_25 |
16428 | #define SPI_SHADER_USER_DATA_GS_25__DATA__SHIFT 0x0 |
16429 | #define SPI_SHADER_USER_DATA_GS_25__DATA_MASK 0xFFFFFFFFL |
16430 | //SPI_SHADER_USER_DATA_GS_26 |
16431 | #define SPI_SHADER_USER_DATA_GS_26__DATA__SHIFT 0x0 |
16432 | #define SPI_SHADER_USER_DATA_GS_26__DATA_MASK 0xFFFFFFFFL |
16433 | //SPI_SHADER_USER_DATA_GS_27 |
16434 | #define SPI_SHADER_USER_DATA_GS_27__DATA__SHIFT 0x0 |
16435 | #define SPI_SHADER_USER_DATA_GS_27__DATA_MASK 0xFFFFFFFFL |
16436 | //SPI_SHADER_USER_DATA_GS_28 |
16437 | #define SPI_SHADER_USER_DATA_GS_28__DATA__SHIFT 0x0 |
16438 | #define SPI_SHADER_USER_DATA_GS_28__DATA_MASK 0xFFFFFFFFL |
16439 | //SPI_SHADER_USER_DATA_GS_29 |
16440 | #define SPI_SHADER_USER_DATA_GS_29__DATA__SHIFT 0x0 |
16441 | #define SPI_SHADER_USER_DATA_GS_29__DATA_MASK 0xFFFFFFFFL |
16442 | //SPI_SHADER_USER_DATA_GS_30 |
16443 | #define SPI_SHADER_USER_DATA_GS_30__DATA__SHIFT 0x0 |
16444 | #define SPI_SHADER_USER_DATA_GS_30__DATA_MASK 0xFFFFFFFFL |
16445 | //SPI_SHADER_USER_DATA_GS_31 |
16446 | #define SPI_SHADER_USER_DATA_GS_31__DATA__SHIFT 0x0 |
16447 | #define SPI_SHADER_USER_DATA_GS_31__DATA_MASK 0xFFFFFFFFL |
16448 | //SPI_SHADER_GS_MESHLET_DIM |
16449 | #define SPI_SHADER_GS_MESHLET_DIM__MESHLET_NUM_THREAD_X__SHIFT 0x0 |
16450 | #define SPI_SHADER_GS_MESHLET_DIM__MESHLET_NUM_THREAD_Y__SHIFT 0x8 |
16451 | #define SPI_SHADER_GS_MESHLET_DIM__MESHLET_NUM_THREAD_Z__SHIFT 0x10 |
16452 | #define SPI_SHADER_GS_MESHLET_DIM__MESHLET_THREADGROUP_SIZE__SHIFT 0x18 |
16453 | #define SPI_SHADER_GS_MESHLET_DIM__MESHLET_NUM_THREAD_X_MASK 0x000000FFL |
16454 | #define SPI_SHADER_GS_MESHLET_DIM__MESHLET_NUM_THREAD_Y_MASK 0x0000FF00L |
16455 | #define SPI_SHADER_GS_MESHLET_DIM__MESHLET_NUM_THREAD_Z_MASK 0x00FF0000L |
16456 | #define SPI_SHADER_GS_MESHLET_DIM__MESHLET_THREADGROUP_SIZE_MASK 0xFF000000L |
16457 | //SPI_SHADER_GS_MESHLET_EXP_ALLOC |
16458 | #define SPI_SHADER_GS_MESHLET_EXP_ALLOC__MAX_EXP_VERTS__SHIFT 0x0 |
16459 | #define SPI_SHADER_GS_MESHLET_EXP_ALLOC__MAX_EXP_PRIMS__SHIFT 0x9 |
16460 | #define SPI_SHADER_GS_MESHLET_EXP_ALLOC__MAX_EXP_VERTS_MASK 0x000001FFL |
16461 | #define SPI_SHADER_GS_MESHLET_EXP_ALLOC__MAX_EXP_PRIMS_MASK 0x0003FE00L |
16462 | //SPI_SHADER_REQ_CTRL_ESGS |
16463 | #define SPI_SHADER_REQ_CTRL_ESGS__SOFT_GROUPING_EN__SHIFT 0x0 |
16464 | #define SPI_SHADER_REQ_CTRL_ESGS__NUMBER_OF_REQUESTS_PER_CU__SHIFT 0x1 |
16465 | #define SPI_SHADER_REQ_CTRL_ESGS__SOFT_GROUPING_ALLOCATION_TIMEOUT__SHIFT 0x5 |
16466 | #define SPI_SHADER_REQ_CTRL_ESGS__HARD_LOCK_HYSTERESIS__SHIFT 0x9 |
16467 | #define SPI_SHADER_REQ_CTRL_ESGS__HARD_LOCK_LOW_THRESHOLD__SHIFT 0xa |
16468 | #define SPI_SHADER_REQ_CTRL_ESGS__PRODUCER_REQUEST_LOCKOUT__SHIFT 0xf |
16469 | #define SPI_SHADER_REQ_CTRL_ESGS__GLOBAL_SCANNING_EN__SHIFT 0x10 |
16470 | #define SPI_SHADER_REQ_CTRL_ESGS__ALLOCATION_RATE_THROTTLING_THRESHOLD__SHIFT 0x11 |
16471 | #define SPI_SHADER_REQ_CTRL_ESGS__SOFT_GROUPING_EN_MASK 0x00000001L |
16472 | #define SPI_SHADER_REQ_CTRL_ESGS__NUMBER_OF_REQUESTS_PER_CU_MASK 0x0000001EL |
16473 | #define SPI_SHADER_REQ_CTRL_ESGS__SOFT_GROUPING_ALLOCATION_TIMEOUT_MASK 0x000001E0L |
16474 | #define SPI_SHADER_REQ_CTRL_ESGS__HARD_LOCK_HYSTERESIS_MASK 0x00000200L |
16475 | #define SPI_SHADER_REQ_CTRL_ESGS__HARD_LOCK_LOW_THRESHOLD_MASK 0x00007C00L |
16476 | #define SPI_SHADER_REQ_CTRL_ESGS__PRODUCER_REQUEST_LOCKOUT_MASK 0x00008000L |
16477 | #define SPI_SHADER_REQ_CTRL_ESGS__GLOBAL_SCANNING_EN_MASK 0x00010000L |
16478 | #define SPI_SHADER_REQ_CTRL_ESGS__ALLOCATION_RATE_THROTTLING_THRESHOLD_MASK 0x000E0000L |
16479 | //SPI_SHADER_USER_ACCUM_ESGS_0 |
16480 | #define SPI_SHADER_USER_ACCUM_ESGS_0__CONTRIBUTION__SHIFT 0x0 |
16481 | #define SPI_SHADER_USER_ACCUM_ESGS_0__CONTRIBUTION_MASK 0x0000007FL |
16482 | //SPI_SHADER_USER_ACCUM_ESGS_1 |
16483 | #define SPI_SHADER_USER_ACCUM_ESGS_1__CONTRIBUTION__SHIFT 0x0 |
16484 | #define SPI_SHADER_USER_ACCUM_ESGS_1__CONTRIBUTION_MASK 0x0000007FL |
16485 | //SPI_SHADER_USER_ACCUM_ESGS_2 |
16486 | #define SPI_SHADER_USER_ACCUM_ESGS_2__CONTRIBUTION__SHIFT 0x0 |
16487 | #define SPI_SHADER_USER_ACCUM_ESGS_2__CONTRIBUTION_MASK 0x0000007FL |
16488 | //SPI_SHADER_USER_ACCUM_ESGS_3 |
16489 | #define SPI_SHADER_USER_ACCUM_ESGS_3__CONTRIBUTION__SHIFT 0x0 |
16490 | #define SPI_SHADER_USER_ACCUM_ESGS_3__CONTRIBUTION_MASK 0x0000007FL |
16491 | //SPI_SHADER_PGM_LO_ES |
16492 | #define SPI_SHADER_PGM_LO_ES__MEM_BASE__SHIFT 0x0 |
16493 | #define SPI_SHADER_PGM_LO_ES__MEM_BASE_MASK 0xFFFFFFFFL |
16494 | //SPI_SHADER_PGM_HI_ES |
16495 | #define SPI_SHADER_PGM_HI_ES__MEM_BASE__SHIFT 0x0 |
16496 | #define SPI_SHADER_PGM_HI_ES__MEM_BASE_MASK 0xFFL |
16497 | //SPI_SHADER_PGM_CHKSUM_HS |
16498 | #define SPI_SHADER_PGM_CHKSUM_HS__CHECKSUM__SHIFT 0x0 |
16499 | #define SPI_SHADER_PGM_CHKSUM_HS__CHECKSUM_MASK 0xFFFFFFFFL |
16500 | //SPI_SHADER_PGM_RSRC4_HS |
16501 | #define SPI_SHADER_PGM_RSRC4_HS__CU_EN__SHIFT 0x0 |
16502 | #define SPI_SHADER_PGM_RSRC4_HS__INST_PREF_SIZE__SHIFT 0x10 |
16503 | #define SPI_SHADER_PGM_RSRC4_HS__TRAP_ON_START__SHIFT 0x1d |
16504 | #define SPI_SHADER_PGM_RSRC4_HS__TRAP_ON_END__SHIFT 0x1e |
16505 | #define SPI_SHADER_PGM_RSRC4_HS__IMAGE_OP__SHIFT 0x1f |
16506 | #define SPI_SHADER_PGM_RSRC4_HS__CU_EN_MASK 0x0000FFFFL |
16507 | #define SPI_SHADER_PGM_RSRC4_HS__INST_PREF_SIZE_MASK 0x003F0000L |
16508 | #define SPI_SHADER_PGM_RSRC4_HS__TRAP_ON_START_MASK 0x20000000L |
16509 | #define SPI_SHADER_PGM_RSRC4_HS__TRAP_ON_END_MASK 0x40000000L |
16510 | #define SPI_SHADER_PGM_RSRC4_HS__IMAGE_OP_MASK 0x80000000L |
16511 | //SPI_SHADER_USER_DATA_ADDR_LO_HS |
16512 | #define SPI_SHADER_USER_DATA_ADDR_LO_HS__MEM_BASE__SHIFT 0x0 |
16513 | #define SPI_SHADER_USER_DATA_ADDR_LO_HS__MEM_BASE_MASK 0xFFFFFFFFL |
16514 | //SPI_SHADER_USER_DATA_ADDR_HI_HS |
16515 | #define SPI_SHADER_USER_DATA_ADDR_HI_HS__MEM_BASE__SHIFT 0x0 |
16516 | #define SPI_SHADER_USER_DATA_ADDR_HI_HS__MEM_BASE_MASK 0xFFFFFFFFL |
16517 | //SPI_SHADER_PGM_LO_LS_HS |
16518 | #define SPI_SHADER_PGM_LO_LS_HS__MEM_BASE__SHIFT 0x0 |
16519 | #define SPI_SHADER_PGM_LO_LS_HS__MEM_BASE_MASK 0xFFFFFFFFL |
16520 | //SPI_SHADER_PGM_HI_LS_HS |
16521 | #define SPI_SHADER_PGM_HI_LS_HS__MEM_BASE__SHIFT 0x0 |
16522 | #define SPI_SHADER_PGM_HI_LS_HS__MEM_BASE_MASK 0xFFL |
16523 | //SPI_SHADER_PGM_RSRC3_HS |
16524 | #define SPI_SHADER_PGM_RSRC3_HS__WAVE_LIMIT__SHIFT 0x0 |
16525 | #define SPI_SHADER_PGM_RSRC3_HS__LOCK_LOW_THRESHOLD__SHIFT 0x6 |
16526 | #define SPI_SHADER_PGM_RSRC3_HS__GROUP_FIFO_DEPTH__SHIFT 0xa |
16527 | #define SPI_SHADER_PGM_RSRC3_HS__CU_EN__SHIFT 0x10 |
16528 | #define SPI_SHADER_PGM_RSRC3_HS__WAVE_LIMIT_MASK 0x0000003FL |
16529 | #define SPI_SHADER_PGM_RSRC3_HS__LOCK_LOW_THRESHOLD_MASK 0x000003C0L |
16530 | #define SPI_SHADER_PGM_RSRC3_HS__GROUP_FIFO_DEPTH_MASK 0x0000FC00L |
16531 | #define SPI_SHADER_PGM_RSRC3_HS__CU_EN_MASK 0xFFFF0000L |
16532 | //SPI_SHADER_PGM_LO_HS |
16533 | #define SPI_SHADER_PGM_LO_HS__MEM_BASE__SHIFT 0x0 |
16534 | #define SPI_SHADER_PGM_LO_HS__MEM_BASE_MASK 0xFFFFFFFFL |
16535 | //SPI_SHADER_PGM_HI_HS |
16536 | #define SPI_SHADER_PGM_HI_HS__MEM_BASE__SHIFT 0x0 |
16537 | #define SPI_SHADER_PGM_HI_HS__MEM_BASE_MASK 0xFFFFFFFFL |
16538 | //SPI_SHADER_PGM_RSRC1_HS |
16539 | #define SPI_SHADER_PGM_RSRC1_HS__VGPRS__SHIFT 0x0 |
16540 | #define SPI_SHADER_PGM_RSRC1_HS__SGPRS__SHIFT 0x6 |
16541 | #define SPI_SHADER_PGM_RSRC1_HS__PRIORITY__SHIFT 0xa |
16542 | #define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE__SHIFT 0xc |
16543 | #define SPI_SHADER_PGM_RSRC1_HS__PRIV__SHIFT 0x14 |
16544 | #define SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP__SHIFT 0x15 |
16545 | #define SPI_SHADER_PGM_RSRC1_HS__DEBUG_MODE__SHIFT 0x16 |
16546 | #define SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE__SHIFT 0x17 |
16547 | #define SPI_SHADER_PGM_RSRC1_HS__MEM_ORDERED__SHIFT 0x18 |
16548 | #define SPI_SHADER_PGM_RSRC1_HS__FWD_PROGRESS__SHIFT 0x19 |
16549 | #define SPI_SHADER_PGM_RSRC1_HS__WGP_MODE__SHIFT 0x1a |
16550 | #define SPI_SHADER_PGM_RSRC1_HS__CDBG_USER__SHIFT 0x1b |
16551 | #define SPI_SHADER_PGM_RSRC1_HS__LS_VGPR_COMP_CNT__SHIFT 0x1c |
16552 | #define SPI_SHADER_PGM_RSRC1_HS__FP16_OVFL__SHIFT 0x1e |
16553 | #define SPI_SHADER_PGM_RSRC1_HS__VGPRS_MASK 0x0000003FL |
16554 | #define SPI_SHADER_PGM_RSRC1_HS__SGPRS_MASK 0x000003C0L |
16555 | #define SPI_SHADER_PGM_RSRC1_HS__PRIORITY_MASK 0x00000C00L |
16556 | #define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE_MASK 0x000FF000L |
16557 | #define SPI_SHADER_PGM_RSRC1_HS__PRIV_MASK 0x00100000L |
16558 | #define SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP_MASK 0x00200000L |
16559 | #define SPI_SHADER_PGM_RSRC1_HS__DEBUG_MODE_MASK 0x00400000L |
16560 | #define SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE_MASK 0x00800000L |
16561 | #define SPI_SHADER_PGM_RSRC1_HS__MEM_ORDERED_MASK 0x01000000L |
16562 | #define SPI_SHADER_PGM_RSRC1_HS__FWD_PROGRESS_MASK 0x02000000L |
16563 | #define SPI_SHADER_PGM_RSRC1_HS__WGP_MODE_MASK 0x04000000L |
16564 | #define SPI_SHADER_PGM_RSRC1_HS__CDBG_USER_MASK 0x08000000L |
16565 | #define SPI_SHADER_PGM_RSRC1_HS__LS_VGPR_COMP_CNT_MASK 0x30000000L |
16566 | #define SPI_SHADER_PGM_RSRC1_HS__FP16_OVFL_MASK 0x40000000L |
16567 | //SPI_SHADER_PGM_RSRC2_HS |
16568 | #define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN__SHIFT 0x0 |
16569 | #define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR__SHIFT 0x1 |
16570 | #define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT__SHIFT 0x6 |
16571 | #define SPI_SHADER_PGM_RSRC2_HS__OC_LDS_EN__SHIFT 0x7 |
16572 | #define SPI_SHADER_PGM_RSRC2_HS__TG_SIZE_EN__SHIFT 0x8 |
16573 | #define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN__SHIFT 0x9 |
16574 | #define SPI_SHADER_PGM_RSRC2_HS__LDS_SIZE__SHIFT 0x12 |
16575 | #define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MSB__SHIFT 0x1b |
16576 | #define SPI_SHADER_PGM_RSRC2_HS__SHARED_VGPR_CNT__SHIFT 0x1c |
16577 | #define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN_MASK 0x00000001L |
16578 | #define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MASK 0x0000003EL |
16579 | #define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT_MASK 0x00000040L |
16580 | #define SPI_SHADER_PGM_RSRC2_HS__OC_LDS_EN_MASK 0x00000080L |
16581 | #define SPI_SHADER_PGM_RSRC2_HS__TG_SIZE_EN_MASK 0x00000100L |
16582 | #define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN_MASK 0x0003FE00L |
16583 | #define SPI_SHADER_PGM_RSRC2_HS__LDS_SIZE_MASK 0x07FC0000L |
16584 | #define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MSB_MASK 0x08000000L |
16585 | #define SPI_SHADER_PGM_RSRC2_HS__SHARED_VGPR_CNT_MASK 0xF0000000L |
16586 | //SPI_SHADER_USER_DATA_HS_0 |
16587 | #define SPI_SHADER_USER_DATA_HS_0__DATA__SHIFT 0x0 |
16588 | #define SPI_SHADER_USER_DATA_HS_0__DATA_MASK 0xFFFFFFFFL |
16589 | //SPI_SHADER_USER_DATA_HS_1 |
16590 | #define SPI_SHADER_USER_DATA_HS_1__DATA__SHIFT 0x0 |
16591 | #define SPI_SHADER_USER_DATA_HS_1__DATA_MASK 0xFFFFFFFFL |
16592 | //SPI_SHADER_USER_DATA_HS_2 |
16593 | #define SPI_SHADER_USER_DATA_HS_2__DATA__SHIFT 0x0 |
16594 | #define SPI_SHADER_USER_DATA_HS_2__DATA_MASK 0xFFFFFFFFL |
16595 | //SPI_SHADER_USER_DATA_HS_3 |
16596 | #define SPI_SHADER_USER_DATA_HS_3__DATA__SHIFT 0x0 |
16597 | #define SPI_SHADER_USER_DATA_HS_3__DATA_MASK 0xFFFFFFFFL |
16598 | //SPI_SHADER_USER_DATA_HS_4 |
16599 | #define SPI_SHADER_USER_DATA_HS_4__DATA__SHIFT 0x0 |
16600 | #define SPI_SHADER_USER_DATA_HS_4__DATA_MASK 0xFFFFFFFFL |
16601 | //SPI_SHADER_USER_DATA_HS_5 |
16602 | #define SPI_SHADER_USER_DATA_HS_5__DATA__SHIFT 0x0 |
16603 | #define SPI_SHADER_USER_DATA_HS_5__DATA_MASK 0xFFFFFFFFL |
16604 | //SPI_SHADER_USER_DATA_HS_6 |
16605 | #define SPI_SHADER_USER_DATA_HS_6__DATA__SHIFT 0x0 |
16606 | #define SPI_SHADER_USER_DATA_HS_6__DATA_MASK 0xFFFFFFFFL |
16607 | //SPI_SHADER_USER_DATA_HS_7 |
16608 | #define SPI_SHADER_USER_DATA_HS_7__DATA__SHIFT 0x0 |
16609 | #define SPI_SHADER_USER_DATA_HS_7__DATA_MASK 0xFFFFFFFFL |
16610 | //SPI_SHADER_USER_DATA_HS_8 |
16611 | #define SPI_SHADER_USER_DATA_HS_8__DATA__SHIFT 0x0 |
16612 | #define SPI_SHADER_USER_DATA_HS_8__DATA_MASK 0xFFFFFFFFL |
16613 | //SPI_SHADER_USER_DATA_HS_9 |
16614 | #define SPI_SHADER_USER_DATA_HS_9__DATA__SHIFT 0x0 |
16615 | #define SPI_SHADER_USER_DATA_HS_9__DATA_MASK 0xFFFFFFFFL |
16616 | //SPI_SHADER_USER_DATA_HS_10 |
16617 | #define SPI_SHADER_USER_DATA_HS_10__DATA__SHIFT 0x0 |
16618 | #define SPI_SHADER_USER_DATA_HS_10__DATA_MASK 0xFFFFFFFFL |
16619 | //SPI_SHADER_USER_DATA_HS_11 |
16620 | #define SPI_SHADER_USER_DATA_HS_11__DATA__SHIFT 0x0 |
16621 | #define SPI_SHADER_USER_DATA_HS_11__DATA_MASK 0xFFFFFFFFL |
16622 | //SPI_SHADER_USER_DATA_HS_12 |
16623 | #define SPI_SHADER_USER_DATA_HS_12__DATA__SHIFT 0x0 |
16624 | #define SPI_SHADER_USER_DATA_HS_12__DATA_MASK 0xFFFFFFFFL |
16625 | //SPI_SHADER_USER_DATA_HS_13 |
16626 | #define SPI_SHADER_USER_DATA_HS_13__DATA__SHIFT 0x0 |
16627 | #define SPI_SHADER_USER_DATA_HS_13__DATA_MASK 0xFFFFFFFFL |
16628 | //SPI_SHADER_USER_DATA_HS_14 |
16629 | #define SPI_SHADER_USER_DATA_HS_14__DATA__SHIFT 0x0 |
16630 | #define SPI_SHADER_USER_DATA_HS_14__DATA_MASK 0xFFFFFFFFL |
16631 | //SPI_SHADER_USER_DATA_HS_15 |
16632 | #define SPI_SHADER_USER_DATA_HS_15__DATA__SHIFT 0x0 |
16633 | #define SPI_SHADER_USER_DATA_HS_15__DATA_MASK 0xFFFFFFFFL |
16634 | //SPI_SHADER_USER_DATA_HS_16 |
16635 | #define SPI_SHADER_USER_DATA_HS_16__DATA__SHIFT 0x0 |
16636 | #define SPI_SHADER_USER_DATA_HS_16__DATA_MASK 0xFFFFFFFFL |
16637 | //SPI_SHADER_USER_DATA_HS_17 |
16638 | #define SPI_SHADER_USER_DATA_HS_17__DATA__SHIFT 0x0 |
16639 | #define SPI_SHADER_USER_DATA_HS_17__DATA_MASK 0xFFFFFFFFL |
16640 | //SPI_SHADER_USER_DATA_HS_18 |
16641 | #define SPI_SHADER_USER_DATA_HS_18__DATA__SHIFT 0x0 |
16642 | #define SPI_SHADER_USER_DATA_HS_18__DATA_MASK 0xFFFFFFFFL |
16643 | //SPI_SHADER_USER_DATA_HS_19 |
16644 | #define SPI_SHADER_USER_DATA_HS_19__DATA__SHIFT 0x0 |
16645 | #define SPI_SHADER_USER_DATA_HS_19__DATA_MASK 0xFFFFFFFFL |
16646 | //SPI_SHADER_USER_DATA_HS_20 |
16647 | #define SPI_SHADER_USER_DATA_HS_20__DATA__SHIFT 0x0 |
16648 | #define SPI_SHADER_USER_DATA_HS_20__DATA_MASK 0xFFFFFFFFL |
16649 | //SPI_SHADER_USER_DATA_HS_21 |
16650 | #define SPI_SHADER_USER_DATA_HS_21__DATA__SHIFT 0x0 |
16651 | #define SPI_SHADER_USER_DATA_HS_21__DATA_MASK 0xFFFFFFFFL |
16652 | //SPI_SHADER_USER_DATA_HS_22 |
16653 | #define SPI_SHADER_USER_DATA_HS_22__DATA__SHIFT 0x0 |
16654 | #define SPI_SHADER_USER_DATA_HS_22__DATA_MASK 0xFFFFFFFFL |
16655 | //SPI_SHADER_USER_DATA_HS_23 |
16656 | #define SPI_SHADER_USER_DATA_HS_23__DATA__SHIFT 0x0 |
16657 | #define SPI_SHADER_USER_DATA_HS_23__DATA_MASK 0xFFFFFFFFL |
16658 | //SPI_SHADER_USER_DATA_HS_24 |
16659 | #define SPI_SHADER_USER_DATA_HS_24__DATA__SHIFT 0x0 |
16660 | #define SPI_SHADER_USER_DATA_HS_24__DATA_MASK 0xFFFFFFFFL |
16661 | //SPI_SHADER_USER_DATA_HS_25 |
16662 | #define SPI_SHADER_USER_DATA_HS_25__DATA__SHIFT 0x0 |
16663 | #define SPI_SHADER_USER_DATA_HS_25__DATA_MASK 0xFFFFFFFFL |
16664 | //SPI_SHADER_USER_DATA_HS_26 |
16665 | #define SPI_SHADER_USER_DATA_HS_26__DATA__SHIFT 0x0 |
16666 | #define SPI_SHADER_USER_DATA_HS_26__DATA_MASK 0xFFFFFFFFL |
16667 | //SPI_SHADER_USER_DATA_HS_27 |
16668 | #define SPI_SHADER_USER_DATA_HS_27__DATA__SHIFT 0x0 |
16669 | #define SPI_SHADER_USER_DATA_HS_27__DATA_MASK 0xFFFFFFFFL |
16670 | //SPI_SHADER_USER_DATA_HS_28 |
16671 | #define SPI_SHADER_USER_DATA_HS_28__DATA__SHIFT 0x0 |
16672 | #define SPI_SHADER_USER_DATA_HS_28__DATA_MASK 0xFFFFFFFFL |
16673 | //SPI_SHADER_USER_DATA_HS_29 |
16674 | #define SPI_SHADER_USER_DATA_HS_29__DATA__SHIFT 0x0 |
16675 | #define SPI_SHADER_USER_DATA_HS_29__DATA_MASK 0xFFFFFFFFL |
16676 | //SPI_SHADER_USER_DATA_HS_30 |
16677 | #define SPI_SHADER_USER_DATA_HS_30__DATA__SHIFT 0x0 |
16678 | #define SPI_SHADER_USER_DATA_HS_30__DATA_MASK 0xFFFFFFFFL |
16679 | //SPI_SHADER_USER_DATA_HS_31 |
16680 | #define SPI_SHADER_USER_DATA_HS_31__DATA__SHIFT 0x0 |
16681 | #define SPI_SHADER_USER_DATA_HS_31__DATA_MASK 0xFFFFFFFFL |
16682 | //SPI_SHADER_REQ_CTRL_LSHS |
16683 | #define SPI_SHADER_REQ_CTRL_LSHS__SOFT_GROUPING_EN__SHIFT 0x0 |
16684 | #define SPI_SHADER_REQ_CTRL_LSHS__NUMBER_OF_REQUESTS_PER_CU__SHIFT 0x1 |
16685 | #define SPI_SHADER_REQ_CTRL_LSHS__SOFT_GROUPING_ALLOCATION_TIMEOUT__SHIFT 0x5 |
16686 | #define SPI_SHADER_REQ_CTRL_LSHS__HARD_LOCK_HYSTERESIS__SHIFT 0x9 |
16687 | #define SPI_SHADER_REQ_CTRL_LSHS__HARD_LOCK_LOW_THRESHOLD__SHIFT 0xa |
16688 | #define SPI_SHADER_REQ_CTRL_LSHS__PRODUCER_REQUEST_LOCKOUT__SHIFT 0xf |
16689 | #define SPI_SHADER_REQ_CTRL_LSHS__GLOBAL_SCANNING_EN__SHIFT 0x10 |
16690 | #define SPI_SHADER_REQ_CTRL_LSHS__ALLOCATION_RATE_THROTTLING_THRESHOLD__SHIFT 0x11 |
16691 | #define SPI_SHADER_REQ_CTRL_LSHS__SOFT_GROUPING_EN_MASK 0x00000001L |
16692 | #define SPI_SHADER_REQ_CTRL_LSHS__NUMBER_OF_REQUESTS_PER_CU_MASK 0x0000001EL |
16693 | #define SPI_SHADER_REQ_CTRL_LSHS__SOFT_GROUPING_ALLOCATION_TIMEOUT_MASK 0x000001E0L |
16694 | #define SPI_SHADER_REQ_CTRL_LSHS__HARD_LOCK_HYSTERESIS_MASK 0x00000200L |
16695 | #define SPI_SHADER_REQ_CTRL_LSHS__HARD_LOCK_LOW_THRESHOLD_MASK 0x00007C00L |
16696 | #define SPI_SHADER_REQ_CTRL_LSHS__PRODUCER_REQUEST_LOCKOUT_MASK 0x00008000L |
16697 | #define SPI_SHADER_REQ_CTRL_LSHS__GLOBAL_SCANNING_EN_MASK 0x00010000L |
16698 | #define SPI_SHADER_REQ_CTRL_LSHS__ALLOCATION_RATE_THROTTLING_THRESHOLD_MASK 0x000E0000L |
16699 | //SPI_SHADER_USER_ACCUM_LSHS_0 |
16700 | #define SPI_SHADER_USER_ACCUM_LSHS_0__CONTRIBUTION__SHIFT 0x0 |
16701 | #define SPI_SHADER_USER_ACCUM_LSHS_0__CONTRIBUTION_MASK 0x0000007FL |
16702 | //SPI_SHADER_USER_ACCUM_LSHS_1 |
16703 | #define SPI_SHADER_USER_ACCUM_LSHS_1__CONTRIBUTION__SHIFT 0x0 |
16704 | #define SPI_SHADER_USER_ACCUM_LSHS_1__CONTRIBUTION_MASK 0x0000007FL |
16705 | //SPI_SHADER_USER_ACCUM_LSHS_2 |
16706 | #define SPI_SHADER_USER_ACCUM_LSHS_2__CONTRIBUTION__SHIFT 0x0 |
16707 | #define SPI_SHADER_USER_ACCUM_LSHS_2__CONTRIBUTION_MASK 0x0000007FL |
16708 | //SPI_SHADER_USER_ACCUM_LSHS_3 |
16709 | #define SPI_SHADER_USER_ACCUM_LSHS_3__CONTRIBUTION__SHIFT 0x0 |
16710 | #define SPI_SHADER_USER_ACCUM_LSHS_3__CONTRIBUTION_MASK 0x0000007FL |
16711 | //SPI_SHADER_PGM_LO_LS |
16712 | #define SPI_SHADER_PGM_LO_LS__MEM_BASE__SHIFT 0x0 |
16713 | #define SPI_SHADER_PGM_LO_LS__MEM_BASE_MASK 0xFFFFFFFFL |
16714 | //SPI_SHADER_PGM_HI_LS |
16715 | #define SPI_SHADER_PGM_HI_LS__MEM_BASE__SHIFT 0x0 |
16716 | #define SPI_SHADER_PGM_HI_LS__MEM_BASE_MASK 0xFFL |
16717 | //COMPUTE_DISPATCH_INITIATOR |
16718 | #define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN__SHIFT 0x0 |
16719 | #define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN__SHIFT 0x1 |
16720 | #define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000__SHIFT 0x2 |
16721 | #define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL__SHIFT 0x3 |
16722 | #define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE__SHIFT 0x4 |
16723 | #define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS__SHIFT 0x5 |
16724 | #define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE__SHIFT 0x6 |
16725 | #define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL__SHIFT 0xa |
16726 | #define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL__SHIFT 0xb |
16727 | #define COMPUTE_DISPATCH_INITIATOR__RESERVED__SHIFT 0xc |
16728 | #define COMPUTE_DISPATCH_INITIATOR__TUNNEL_ENABLE__SHIFT 0xd |
16729 | #define COMPUTE_DISPATCH_INITIATOR__RESTORE__SHIFT 0xe |
16730 | #define COMPUTE_DISPATCH_INITIATOR__CS_W32_EN__SHIFT 0xf |
16731 | #define COMPUTE_DISPATCH_INITIATOR__AMP_SHADER_EN__SHIFT 0x10 |
16732 | #define COMPUTE_DISPATCH_INITIATOR__DISABLE_DISP_PREMPT_EN__SHIFT 0x11 |
16733 | #define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN_MASK 0x00000001L |
16734 | #define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN_MASK 0x00000002L |
16735 | #define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000_MASK 0x00000004L |
16736 | #define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL_MASK 0x00000008L |
16737 | #define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE_MASK 0x00000010L |
16738 | #define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS_MASK 0x00000020L |
16739 | #define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE_MASK 0x00000040L |
16740 | #define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL_MASK 0x00000400L |
16741 | #define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL_MASK 0x00000800L |
16742 | #define COMPUTE_DISPATCH_INITIATOR__RESERVED_MASK 0x00001000L |
16743 | #define COMPUTE_DISPATCH_INITIATOR__TUNNEL_ENABLE_MASK 0x00002000L |
16744 | #define COMPUTE_DISPATCH_INITIATOR__RESTORE_MASK 0x00004000L |
16745 | #define COMPUTE_DISPATCH_INITIATOR__CS_W32_EN_MASK 0x00008000L |
16746 | #define COMPUTE_DISPATCH_INITIATOR__AMP_SHADER_EN_MASK 0x00010000L |
16747 | #define COMPUTE_DISPATCH_INITIATOR__DISABLE_DISP_PREMPT_EN_MASK 0x00020000L |
16748 | //COMPUTE_DIM_X |
16749 | #define COMPUTE_DIM_X__SIZE__SHIFT 0x0 |
16750 | #define COMPUTE_DIM_X__SIZE_MASK 0xFFFFFFFFL |
16751 | //COMPUTE_DIM_Y |
16752 | #define COMPUTE_DIM_Y__SIZE__SHIFT 0x0 |
16753 | #define COMPUTE_DIM_Y__SIZE_MASK 0xFFFFFFFFL |
16754 | //COMPUTE_DIM_Z |
16755 | #define COMPUTE_DIM_Z__SIZE__SHIFT 0x0 |
16756 | #define COMPUTE_DIM_Z__SIZE_MASK 0xFFFFFFFFL |
16757 | //COMPUTE_START_X |
16758 | #define COMPUTE_START_X__START__SHIFT 0x0 |
16759 | #define COMPUTE_START_X__START_MASK 0xFFFFFFFFL |
16760 | //COMPUTE_START_Y |
16761 | #define COMPUTE_START_Y__START__SHIFT 0x0 |
16762 | #define COMPUTE_START_Y__START_MASK 0xFFFFFFFFL |
16763 | //COMPUTE_START_Z |
16764 | #define COMPUTE_START_Z__START__SHIFT 0x0 |
16765 | #define COMPUTE_START_Z__START_MASK 0xFFFFFFFFL |
16766 | //COMPUTE_NUM_THREAD_X |
16767 | #define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL__SHIFT 0x0 |
16768 | #define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL__SHIFT 0x10 |
16769 | #define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL_MASK 0x0000FFFFL |
16770 | #define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL_MASK 0xFFFF0000L |
16771 | //COMPUTE_NUM_THREAD_Y |
16772 | #define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL__SHIFT 0x0 |
16773 | #define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL__SHIFT 0x10 |
16774 | #define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL_MASK 0x0000FFFFL |
16775 | #define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL_MASK 0xFFFF0000L |
16776 | //COMPUTE_NUM_THREAD_Z |
16777 | #define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL__SHIFT 0x0 |
16778 | #define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL__SHIFT 0x10 |
16779 | #define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL_MASK 0x0000FFFFL |
16780 | #define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL_MASK 0xFFFF0000L |
16781 | //COMPUTE_PIPELINESTAT_ENABLE |
16782 | #define COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE__SHIFT 0x0 |
16783 | #define COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE_MASK 0x00000001L |
16784 | //COMPUTE_PERFCOUNT_ENABLE |
16785 | #define COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE__SHIFT 0x0 |
16786 | #define COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE_MASK 0x00000001L |
16787 | //COMPUTE_PGM_LO |
16788 | #define COMPUTE_PGM_LO__DATA__SHIFT 0x0 |
16789 | #define COMPUTE_PGM_LO__DATA_MASK 0xFFFFFFFFL |
16790 | //COMPUTE_PGM_HI |
16791 | #define COMPUTE_PGM_HI__DATA__SHIFT 0x0 |
16792 | #define COMPUTE_PGM_HI__DATA_MASK 0x000000FFL |
16793 | //COMPUTE_DISPATCH_PKT_ADDR_LO |
16794 | #define COMPUTE_DISPATCH_PKT_ADDR_LO__DATA__SHIFT 0x0 |
16795 | #define COMPUTE_DISPATCH_PKT_ADDR_LO__DATA_MASK 0xFFFFFFFFL |
16796 | //COMPUTE_DISPATCH_PKT_ADDR_HI |
16797 | #define COMPUTE_DISPATCH_PKT_ADDR_HI__DATA__SHIFT 0x0 |
16798 | #define COMPUTE_DISPATCH_PKT_ADDR_HI__DATA_MASK 0x000000FFL |
16799 | //COMPUTE_DISPATCH_SCRATCH_BASE_LO |
16800 | #define COMPUTE_DISPATCH_SCRATCH_BASE_LO__DATA__SHIFT 0x0 |
16801 | #define COMPUTE_DISPATCH_SCRATCH_BASE_LO__DATA_MASK 0xFFFFFFFFL |
16802 | //COMPUTE_DISPATCH_SCRATCH_BASE_HI |
16803 | #define COMPUTE_DISPATCH_SCRATCH_BASE_HI__DATA__SHIFT 0x0 |
16804 | #define COMPUTE_DISPATCH_SCRATCH_BASE_HI__DATA_MASK 0x000000FFL |
16805 | //COMPUTE_PGM_RSRC1 |
16806 | #define COMPUTE_PGM_RSRC1__VGPRS__SHIFT 0x0 |
16807 | #define COMPUTE_PGM_RSRC1__SGPRS__SHIFT 0x6 |
16808 | #define COMPUTE_PGM_RSRC1__PRIORITY__SHIFT 0xa |
16809 | #define COMPUTE_PGM_RSRC1__FLOAT_MODE__SHIFT 0xc |
16810 | #define COMPUTE_PGM_RSRC1__PRIV__SHIFT 0x14 |
16811 | #define COMPUTE_PGM_RSRC1__DX10_CLAMP__SHIFT 0x15 |
16812 | #define COMPUTE_PGM_RSRC1__DEBUG_MODE__SHIFT 0x16 |
16813 | #define COMPUTE_PGM_RSRC1__IEEE_MODE__SHIFT 0x17 |
16814 | #define COMPUTE_PGM_RSRC1__BULKY__SHIFT 0x18 |
16815 | #define COMPUTE_PGM_RSRC1__CDBG_USER__SHIFT 0x19 |
16816 | #define COMPUTE_PGM_RSRC1__FP16_OVFL__SHIFT 0x1a |
16817 | #define COMPUTE_PGM_RSRC1__WGP_MODE__SHIFT 0x1d |
16818 | #define COMPUTE_PGM_RSRC1__MEM_ORDERED__SHIFT 0x1e |
16819 | #define COMPUTE_PGM_RSRC1__FWD_PROGRESS__SHIFT 0x1f |
16820 | #define COMPUTE_PGM_RSRC1__VGPRS_MASK 0x0000003FL |
16821 | #define COMPUTE_PGM_RSRC1__SGPRS_MASK 0x000003C0L |
16822 | #define COMPUTE_PGM_RSRC1__PRIORITY_MASK 0x00000C00L |
16823 | #define COMPUTE_PGM_RSRC1__FLOAT_MODE_MASK 0x000FF000L |
16824 | #define COMPUTE_PGM_RSRC1__PRIV_MASK 0x00100000L |
16825 | #define COMPUTE_PGM_RSRC1__DX10_CLAMP_MASK 0x00200000L |
16826 | #define COMPUTE_PGM_RSRC1__DEBUG_MODE_MASK 0x00400000L |
16827 | #define COMPUTE_PGM_RSRC1__IEEE_MODE_MASK 0x00800000L |
16828 | #define COMPUTE_PGM_RSRC1__BULKY_MASK 0x01000000L |
16829 | #define COMPUTE_PGM_RSRC1__CDBG_USER_MASK 0x02000000L |
16830 | #define COMPUTE_PGM_RSRC1__FP16_OVFL_MASK 0x04000000L |
16831 | #define COMPUTE_PGM_RSRC1__WGP_MODE_MASK 0x20000000L |
16832 | #define COMPUTE_PGM_RSRC1__MEM_ORDERED_MASK 0x40000000L |
16833 | #define COMPUTE_PGM_RSRC1__FWD_PROGRESS_MASK 0x80000000L |
16834 | //COMPUTE_PGM_RSRC2 |
16835 | #define COMPUTE_PGM_RSRC2__SCRATCH_EN__SHIFT 0x0 |
16836 | #define COMPUTE_PGM_RSRC2__USER_SGPR__SHIFT 0x1 |
16837 | #define COMPUTE_PGM_RSRC2__TRAP_PRESENT__SHIFT 0x6 |
16838 | #define COMPUTE_PGM_RSRC2__TGID_X_EN__SHIFT 0x7 |
16839 | #define COMPUTE_PGM_RSRC2__TGID_Y_EN__SHIFT 0x8 |
16840 | #define COMPUTE_PGM_RSRC2__TGID_Z_EN__SHIFT 0x9 |
16841 | #define COMPUTE_PGM_RSRC2__TG_SIZE_EN__SHIFT 0xa |
16842 | #define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT__SHIFT 0xb |
16843 | #define COMPUTE_PGM_RSRC2__EXCP_EN_MSB__SHIFT 0xd |
16844 | #define COMPUTE_PGM_RSRC2__LDS_SIZE__SHIFT 0xf |
16845 | #define COMPUTE_PGM_RSRC2__EXCP_EN__SHIFT 0x18 |
16846 | #define COMPUTE_PGM_RSRC2__SCRATCH_EN_MASK 0x00000001L |
16847 | #define COMPUTE_PGM_RSRC2__USER_SGPR_MASK 0x0000003EL |
16848 | #define COMPUTE_PGM_RSRC2__TRAP_PRESENT_MASK 0x00000040L |
16849 | #define COMPUTE_PGM_RSRC2__TGID_X_EN_MASK 0x00000080L |
16850 | #define COMPUTE_PGM_RSRC2__TGID_Y_EN_MASK 0x00000100L |
16851 | #define COMPUTE_PGM_RSRC2__TGID_Z_EN_MASK 0x00000200L |
16852 | #define COMPUTE_PGM_RSRC2__TG_SIZE_EN_MASK 0x00000400L |
16853 | #define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT_MASK 0x00001800L |
16854 | #define COMPUTE_PGM_RSRC2__EXCP_EN_MSB_MASK 0x00006000L |
16855 | #define COMPUTE_PGM_RSRC2__LDS_SIZE_MASK 0x00FF8000L |
16856 | #define COMPUTE_PGM_RSRC2__EXCP_EN_MASK 0x7F000000L |
16857 | //COMPUTE_VMID |
16858 | #define COMPUTE_VMID__DATA__SHIFT 0x0 |
16859 | #define COMPUTE_VMID__DATA_MASK 0x0000000FL |
16860 | //COMPUTE_RESOURCE_LIMITS |
16861 | #define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH__SHIFT 0x0 |
16862 | #define COMPUTE_RESOURCE_LIMITS__TG_PER_CU__SHIFT 0xc |
16863 | #define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD__SHIFT 0x10 |
16864 | #define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL__SHIFT 0x16 |
16865 | #define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST__SHIFT 0x17 |
16866 | #define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT__SHIFT 0x18 |
16867 | #define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH_MASK 0x000003FFL |
16868 | #define COMPUTE_RESOURCE_LIMITS__TG_PER_CU_MASK 0x0000F000L |
16869 | #define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD_MASK 0x003F0000L |
16870 | #define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL_MASK 0x00400000L |
16871 | #define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST_MASK 0x00800000L |
16872 | #define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT_MASK 0x07000000L |
16873 | //COMPUTE_DESTINATION_EN_SE0 |
16874 | #define COMPUTE_DESTINATION_EN_SE0__CU_EN__SHIFT 0x0 |
16875 | #define COMPUTE_DESTINATION_EN_SE0__CU_EN_MASK 0xFFFFFFFFL |
16876 | //COMPUTE_STATIC_THREAD_MGMT_SE0 |
16877 | #define COMPUTE_STATIC_THREAD_MGMT_SE0__SA0_CU_EN__SHIFT 0x0 |
16878 | #define COMPUTE_STATIC_THREAD_MGMT_SE0__SA1_CU_EN__SHIFT 0x10 |
16879 | #define COMPUTE_STATIC_THREAD_MGMT_SE0__SA0_CU_EN_MASK 0x0000FFFFL |
16880 | #define COMPUTE_STATIC_THREAD_MGMT_SE0__SA1_CU_EN_MASK 0xFFFF0000L |
16881 | //COMPUTE_DESTINATION_EN_SE1 |
16882 | #define COMPUTE_DESTINATION_EN_SE1__CU_EN__SHIFT 0x0 |
16883 | #define COMPUTE_DESTINATION_EN_SE1__CU_EN_MASK 0xFFFFFFFFL |
16884 | //COMPUTE_STATIC_THREAD_MGMT_SE1 |
16885 | #define COMPUTE_STATIC_THREAD_MGMT_SE1__SA0_CU_EN__SHIFT 0x0 |
16886 | #define COMPUTE_STATIC_THREAD_MGMT_SE1__SA1_CU_EN__SHIFT 0x10 |
16887 | #define COMPUTE_STATIC_THREAD_MGMT_SE1__SA0_CU_EN_MASK 0x0000FFFFL |
16888 | #define COMPUTE_STATIC_THREAD_MGMT_SE1__SA1_CU_EN_MASK 0xFFFF0000L |
16889 | //COMPUTE_TMPRING_SIZE |
16890 | #define COMPUTE_TMPRING_SIZE__WAVES__SHIFT 0x0 |
16891 | #define COMPUTE_TMPRING_SIZE__WAVESIZE__SHIFT 0xc |
16892 | #define COMPUTE_TMPRING_SIZE__WAVES_MASK 0x00000FFFL |
16893 | #define COMPUTE_TMPRING_SIZE__WAVESIZE_MASK 0x07FFF000L |
16894 | //COMPUTE_DESTINATION_EN_SE2 |
16895 | #define COMPUTE_DESTINATION_EN_SE2__CU_EN__SHIFT 0x0 |
16896 | #define COMPUTE_DESTINATION_EN_SE2__CU_EN_MASK 0xFFFFFFFFL |
16897 | //COMPUTE_STATIC_THREAD_MGMT_SE2 |
16898 | #define COMPUTE_STATIC_THREAD_MGMT_SE2__SA0_CU_EN__SHIFT 0x0 |
16899 | #define COMPUTE_STATIC_THREAD_MGMT_SE2__SA1_CU_EN__SHIFT 0x10 |
16900 | #define COMPUTE_STATIC_THREAD_MGMT_SE2__SA0_CU_EN_MASK 0x0000FFFFL |
16901 | #define COMPUTE_STATIC_THREAD_MGMT_SE2__SA1_CU_EN_MASK 0xFFFF0000L |
16902 | //COMPUTE_DESTINATION_EN_SE3 |
16903 | #define COMPUTE_DESTINATION_EN_SE3__CU_EN__SHIFT 0x0 |
16904 | #define COMPUTE_DESTINATION_EN_SE3__CU_EN_MASK 0xFFFFFFFFL |
16905 | //COMPUTE_STATIC_THREAD_MGMT_SE3 |
16906 | #define COMPUTE_STATIC_THREAD_MGMT_SE3__SA0_CU_EN__SHIFT 0x0 |
16907 | #define COMPUTE_STATIC_THREAD_MGMT_SE3__SA1_CU_EN__SHIFT 0x10 |
16908 | #define COMPUTE_STATIC_THREAD_MGMT_SE3__SA0_CU_EN_MASK 0x0000FFFFL |
16909 | #define COMPUTE_STATIC_THREAD_MGMT_SE3__SA1_CU_EN_MASK 0xFFFF0000L |
16910 | //COMPUTE_RESTART_X |
16911 | #define COMPUTE_RESTART_X__RESTART__SHIFT 0x0 |
16912 | #define COMPUTE_RESTART_X__RESTART_MASK 0xFFFFFFFFL |
16913 | //COMPUTE_RESTART_Y |
16914 | #define COMPUTE_RESTART_Y__RESTART__SHIFT 0x0 |
16915 | #define COMPUTE_RESTART_Y__RESTART_MASK 0xFFFFFFFFL |
16916 | //COMPUTE_RESTART_Z |
16917 | #define COMPUTE_RESTART_Z__RESTART__SHIFT 0x0 |
16918 | #define COMPUTE_RESTART_Z__RESTART_MASK 0xFFFFFFFFL |
16919 | //COMPUTE_THREAD_TRACE_ENABLE |
16920 | #define COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE__SHIFT 0x0 |
16921 | #define COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE_MASK 0x00000001L |
16922 | //COMPUTE_MISC_RESERVED |
16923 | #define COMPUTE_MISC_RESERVED__SEND_SEID__SHIFT 0x0 |
16924 | #define COMPUTE_MISC_RESERVED__RESERVED3__SHIFT 0x3 |
16925 | #define COMPUTE_MISC_RESERVED__RESERVED4__SHIFT 0x4 |
16926 | #define COMPUTE_MISC_RESERVED__WAVE_ID_BASE__SHIFT 0x5 |
16927 | #define COMPUTE_MISC_RESERVED__SEND_SEID_MASK 0x00000007L |
16928 | #define COMPUTE_MISC_RESERVED__RESERVED3_MASK 0x00000008L |
16929 | #define COMPUTE_MISC_RESERVED__RESERVED4_MASK 0x00000010L |
16930 | #define COMPUTE_MISC_RESERVED__WAVE_ID_BASE_MASK 0x0001FFE0L |
16931 | //COMPUTE_DISPATCH_ID |
16932 | #define COMPUTE_DISPATCH_ID__DISPATCH_ID__SHIFT 0x0 |
16933 | #define COMPUTE_DISPATCH_ID__DISPATCH_ID_MASK 0xFFFFFFFFL |
16934 | //COMPUTE_THREADGROUP_ID |
16935 | #define COMPUTE_THREADGROUP_ID__THREADGROUP_ID__SHIFT 0x0 |
16936 | #define COMPUTE_THREADGROUP_ID__THREADGROUP_ID_MASK 0xFFFFFFFFL |
16937 | //COMPUTE_REQ_CTRL |
16938 | #define COMPUTE_REQ_CTRL__SOFT_GROUPING_EN__SHIFT 0x0 |
16939 | #define COMPUTE_REQ_CTRL__NUMBER_OF_REQUESTS_PER_CU__SHIFT 0x1 |
16940 | #define COMPUTE_REQ_CTRL__SOFT_GROUPING_ALLOCATION_TIMEOUT__SHIFT 0x5 |
16941 | #define COMPUTE_REQ_CTRL__HARD_LOCK_HYSTERESIS__SHIFT 0x9 |
16942 | #define COMPUTE_REQ_CTRL__HARD_LOCK_LOW_THRESHOLD__SHIFT 0xa |
16943 | #define COMPUTE_REQ_CTRL__PRODUCER_REQUEST_LOCKOUT__SHIFT 0xf |
16944 | #define COMPUTE_REQ_CTRL__GLOBAL_SCANNING_EN__SHIFT 0x10 |
16945 | #define COMPUTE_REQ_CTRL__ALLOCATION_RATE_THROTTLING_THRESHOLD__SHIFT 0x11 |
16946 | #define COMPUTE_REQ_CTRL__DEDICATED_PREALLOCATION_BUFFER_LIMIT__SHIFT 0x14 |
16947 | #define COMPUTE_REQ_CTRL__SOFT_GROUPING_EN_MASK 0x00000001L |
16948 | #define COMPUTE_REQ_CTRL__NUMBER_OF_REQUESTS_PER_CU_MASK 0x0000001EL |
16949 | #define COMPUTE_REQ_CTRL__SOFT_GROUPING_ALLOCATION_TIMEOUT_MASK 0x000001E0L |
16950 | #define COMPUTE_REQ_CTRL__HARD_LOCK_HYSTERESIS_MASK 0x00000200L |
16951 | #define COMPUTE_REQ_CTRL__HARD_LOCK_LOW_THRESHOLD_MASK 0x00007C00L |
16952 | #define COMPUTE_REQ_CTRL__PRODUCER_REQUEST_LOCKOUT_MASK 0x00008000L |
16953 | #define COMPUTE_REQ_CTRL__GLOBAL_SCANNING_EN_MASK 0x00010000L |
16954 | #define COMPUTE_REQ_CTRL__ALLOCATION_RATE_THROTTLING_THRESHOLD_MASK 0x000E0000L |
16955 | #define COMPUTE_REQ_CTRL__DEDICATED_PREALLOCATION_BUFFER_LIMIT_MASK 0x07F00000L |
16956 | //COMPUTE_USER_ACCUM_0 |
16957 | #define COMPUTE_USER_ACCUM_0__CONTRIBUTION__SHIFT 0x0 |
16958 | #define COMPUTE_USER_ACCUM_0__CONTRIBUTION_MASK 0x0000007FL |
16959 | //COMPUTE_USER_ACCUM_1 |
16960 | #define COMPUTE_USER_ACCUM_1__CONTRIBUTION__SHIFT 0x0 |
16961 | #define COMPUTE_USER_ACCUM_1__CONTRIBUTION_MASK 0x0000007FL |
16962 | //COMPUTE_USER_ACCUM_2 |
16963 | #define COMPUTE_USER_ACCUM_2__CONTRIBUTION__SHIFT 0x0 |
16964 | #define COMPUTE_USER_ACCUM_2__CONTRIBUTION_MASK 0x0000007FL |
16965 | //COMPUTE_USER_ACCUM_3 |
16966 | #define COMPUTE_USER_ACCUM_3__CONTRIBUTION__SHIFT 0x0 |
16967 | #define COMPUTE_USER_ACCUM_3__CONTRIBUTION_MASK 0x0000007FL |
16968 | //COMPUTE_PGM_RSRC3 |
16969 | #define COMPUTE_PGM_RSRC3__SHARED_VGPR_CNT__SHIFT 0x0 |
16970 | #define COMPUTE_PGM_RSRC3__INST_PREF_SIZE__SHIFT 0x4 |
16971 | #define COMPUTE_PGM_RSRC3__TRAP_ON_START__SHIFT 0xa |
16972 | #define COMPUTE_PGM_RSRC3__TRAP_ON_END__SHIFT 0xb |
16973 | #define COMPUTE_PGM_RSRC3__IMAGE_OP__SHIFT 0x1f |
16974 | #define COMPUTE_PGM_RSRC3__SHARED_VGPR_CNT_MASK 0x0000000FL |
16975 | #define COMPUTE_PGM_RSRC3__INST_PREF_SIZE_MASK 0x000003F0L |
16976 | #define COMPUTE_PGM_RSRC3__TRAP_ON_START_MASK 0x00000400L |
16977 | #define COMPUTE_PGM_RSRC3__TRAP_ON_END_MASK 0x00000800L |
16978 | #define COMPUTE_PGM_RSRC3__IMAGE_OP_MASK 0x80000000L |
16979 | //COMPUTE_DDID_INDEX |
16980 | #define COMPUTE_DDID_INDEX__INDEX__SHIFT 0x0 |
16981 | #define COMPUTE_DDID_INDEX__INDEX_MASK 0x000007FFL |
16982 | //COMPUTE_SHADER_CHKSUM |
16983 | #define COMPUTE_SHADER_CHKSUM__CHECKSUM__SHIFT 0x0 |
16984 | #define COMPUTE_SHADER_CHKSUM__CHECKSUM_MASK 0xFFFFFFFFL |
16985 | //COMPUTE_STATIC_THREAD_MGMT_SE4 |
16986 | #define COMPUTE_STATIC_THREAD_MGMT_SE4__SA0_CU_EN__SHIFT 0x0 |
16987 | #define COMPUTE_STATIC_THREAD_MGMT_SE4__SA1_CU_EN__SHIFT 0x10 |
16988 | #define COMPUTE_STATIC_THREAD_MGMT_SE4__SA0_CU_EN_MASK 0x0000FFFFL |
16989 | #define COMPUTE_STATIC_THREAD_MGMT_SE4__SA1_CU_EN_MASK 0xFFFF0000L |
16990 | //COMPUTE_STATIC_THREAD_MGMT_SE5 |
16991 | #define COMPUTE_STATIC_THREAD_MGMT_SE5__SA0_CU_EN__SHIFT 0x0 |
16992 | #define COMPUTE_STATIC_THREAD_MGMT_SE5__SA1_CU_EN__SHIFT 0x10 |
16993 | #define COMPUTE_STATIC_THREAD_MGMT_SE5__SA0_CU_EN_MASK 0x0000FFFFL |
16994 | #define COMPUTE_STATIC_THREAD_MGMT_SE5__SA1_CU_EN_MASK 0xFFFF0000L |
16995 | //COMPUTE_STATIC_THREAD_MGMT_SE6 |
16996 | #define COMPUTE_STATIC_THREAD_MGMT_SE6__SA0_CU_EN__SHIFT 0x0 |
16997 | #define COMPUTE_STATIC_THREAD_MGMT_SE6__SA1_CU_EN__SHIFT 0x10 |
16998 | #define COMPUTE_STATIC_THREAD_MGMT_SE6__SA0_CU_EN_MASK 0x0000FFFFL |
16999 | #define COMPUTE_STATIC_THREAD_MGMT_SE6__SA1_CU_EN_MASK 0xFFFF0000L |
17000 | //COMPUTE_STATIC_THREAD_MGMT_SE7 |
17001 | #define COMPUTE_STATIC_THREAD_MGMT_SE7__SA0_CU_EN__SHIFT 0x0 |
17002 | #define COMPUTE_STATIC_THREAD_MGMT_SE7__SA1_CU_EN__SHIFT 0x10 |
17003 | #define COMPUTE_STATIC_THREAD_MGMT_SE7__SA0_CU_EN_MASK 0x0000FFFFL |
17004 | #define COMPUTE_STATIC_THREAD_MGMT_SE7__SA1_CU_EN_MASK 0xFFFF0000L |
17005 | //COMPUTE_DISPATCH_INTERLEAVE |
17006 | #define COMPUTE_DISPATCH_INTERLEAVE__INTERLEAVE__SHIFT 0x0 |
17007 | #define COMPUTE_DISPATCH_INTERLEAVE__INTERLEAVE_MASK 0x000003FFL |
17008 | //COMPUTE_RELAUNCH |
17009 | #define COMPUTE_RELAUNCH__PAYLOAD__SHIFT 0x0 |
17010 | #define COMPUTE_RELAUNCH__IS_EVENT__SHIFT 0x1e |
17011 | #define COMPUTE_RELAUNCH__IS_STATE__SHIFT 0x1f |
17012 | #define COMPUTE_RELAUNCH__PAYLOAD_MASK 0x3FFFFFFFL |
17013 | #define COMPUTE_RELAUNCH__IS_EVENT_MASK 0x40000000L |
17014 | #define COMPUTE_RELAUNCH__IS_STATE_MASK 0x80000000L |
17015 | //COMPUTE_WAVE_RESTORE_ADDR_LO |
17016 | #define COMPUTE_WAVE_RESTORE_ADDR_LO__ADDR__SHIFT 0x0 |
17017 | #define COMPUTE_WAVE_RESTORE_ADDR_LO__ADDR_MASK 0xFFFFFFFFL |
17018 | //COMPUTE_WAVE_RESTORE_ADDR_HI |
17019 | #define COMPUTE_WAVE_RESTORE_ADDR_HI__ADDR__SHIFT 0x0 |
17020 | #define COMPUTE_WAVE_RESTORE_ADDR_HI__ADDR_MASK 0xFFFFL |
17021 | //COMPUTE_RELAUNCH2 |
17022 | #define COMPUTE_RELAUNCH2__PAYLOAD__SHIFT 0x0 |
17023 | #define COMPUTE_RELAUNCH2__IS_EVENT__SHIFT 0x1e |
17024 | #define COMPUTE_RELAUNCH2__IS_STATE__SHIFT 0x1f |
17025 | #define COMPUTE_RELAUNCH2__PAYLOAD_MASK 0x3FFFFFFFL |
17026 | #define COMPUTE_RELAUNCH2__IS_EVENT_MASK 0x40000000L |
17027 | #define COMPUTE_RELAUNCH2__IS_STATE_MASK 0x80000000L |
17028 | //COMPUTE_USER_DATA_0 |
17029 | #define COMPUTE_USER_DATA_0__DATA__SHIFT 0x0 |
17030 | #define COMPUTE_USER_DATA_0__DATA_MASK 0xFFFFFFFFL |
17031 | //COMPUTE_USER_DATA_1 |
17032 | #define COMPUTE_USER_DATA_1__DATA__SHIFT 0x0 |
17033 | #define COMPUTE_USER_DATA_1__DATA_MASK 0xFFFFFFFFL |
17034 | //COMPUTE_USER_DATA_2 |
17035 | #define COMPUTE_USER_DATA_2__DATA__SHIFT 0x0 |
17036 | #define COMPUTE_USER_DATA_2__DATA_MASK 0xFFFFFFFFL |
17037 | //COMPUTE_USER_DATA_3 |
17038 | #define COMPUTE_USER_DATA_3__DATA__SHIFT 0x0 |
17039 | #define COMPUTE_USER_DATA_3__DATA_MASK 0xFFFFFFFFL |
17040 | //COMPUTE_USER_DATA_4 |
17041 | #define COMPUTE_USER_DATA_4__DATA__SHIFT 0x0 |
17042 | #define COMPUTE_USER_DATA_4__DATA_MASK 0xFFFFFFFFL |
17043 | //COMPUTE_USER_DATA_5 |
17044 | #define COMPUTE_USER_DATA_5__DATA__SHIFT 0x0 |
17045 | #define COMPUTE_USER_DATA_5__DATA_MASK 0xFFFFFFFFL |
17046 | //COMPUTE_USER_DATA_6 |
17047 | #define COMPUTE_USER_DATA_6__DATA__SHIFT 0x0 |
17048 | #define COMPUTE_USER_DATA_6__DATA_MASK 0xFFFFFFFFL |
17049 | //COMPUTE_USER_DATA_7 |
17050 | #define COMPUTE_USER_DATA_7__DATA__SHIFT 0x0 |
17051 | #define COMPUTE_USER_DATA_7__DATA_MASK 0xFFFFFFFFL |
17052 | //COMPUTE_USER_DATA_8 |
17053 | #define COMPUTE_USER_DATA_8__DATA__SHIFT 0x0 |
17054 | #define COMPUTE_USER_DATA_8__DATA_MASK 0xFFFFFFFFL |
17055 | //COMPUTE_USER_DATA_9 |
17056 | #define COMPUTE_USER_DATA_9__DATA__SHIFT 0x0 |
17057 | #define COMPUTE_USER_DATA_9__DATA_MASK 0xFFFFFFFFL |
17058 | //COMPUTE_USER_DATA_10 |
17059 | #define COMPUTE_USER_DATA_10__DATA__SHIFT 0x0 |
17060 | #define COMPUTE_USER_DATA_10__DATA_MASK 0xFFFFFFFFL |
17061 | //COMPUTE_USER_DATA_11 |
17062 | #define COMPUTE_USER_DATA_11__DATA__SHIFT 0x0 |
17063 | #define COMPUTE_USER_DATA_11__DATA_MASK 0xFFFFFFFFL |
17064 | //COMPUTE_USER_DATA_12 |
17065 | #define COMPUTE_USER_DATA_12__DATA__SHIFT 0x0 |
17066 | #define COMPUTE_USER_DATA_12__DATA_MASK 0xFFFFFFFFL |
17067 | //COMPUTE_USER_DATA_13 |
17068 | #define COMPUTE_USER_DATA_13__DATA__SHIFT 0x0 |
17069 | #define COMPUTE_USER_DATA_13__DATA_MASK 0xFFFFFFFFL |
17070 | //COMPUTE_USER_DATA_14 |
17071 | #define COMPUTE_USER_DATA_14__DATA__SHIFT 0x0 |
17072 | #define COMPUTE_USER_DATA_14__DATA_MASK 0xFFFFFFFFL |
17073 | //COMPUTE_USER_DATA_15 |
17074 | #define COMPUTE_USER_DATA_15__DATA__SHIFT 0x0 |
17075 | #define COMPUTE_USER_DATA_15__DATA_MASK 0xFFFFFFFFL |
17076 | //COMPUTE_DISPATCH_TUNNEL |
17077 | #define COMPUTE_DISPATCH_TUNNEL__OFF_DELAY__SHIFT 0x0 |
17078 | #define COMPUTE_DISPATCH_TUNNEL__IMMEDIATE__SHIFT 0xa |
17079 | #define COMPUTE_DISPATCH_TUNNEL__OFF_DELAY_MASK 0x000003FFL |
17080 | #define COMPUTE_DISPATCH_TUNNEL__IMMEDIATE_MASK 0x00000400L |
17081 | //COMPUTE_DISPATCH_END |
17082 | #define COMPUTE_DISPATCH_END__DATA__SHIFT 0x0 |
17083 | #define COMPUTE_DISPATCH_END__DATA_MASK 0xFFFFFFFFL |
17084 | //COMPUTE_NOWHERE |
17085 | #define COMPUTE_NOWHERE__DATA__SHIFT 0x0 |
17086 | #define COMPUTE_NOWHERE__DATA_MASK 0xFFFFFFFFL |
17087 | //SH_RESERVED_REG0 |
17088 | #define SH_RESERVED_REG0__DATA__SHIFT 0x0 |
17089 | #define SH_RESERVED_REG0__DATA_MASK 0xFFFFFFFFL |
17090 | //SH_RESERVED_REG1 |
17091 | #define SH_RESERVED_REG1__DATA__SHIFT 0x0 |
17092 | #define SH_RESERVED_REG1__DATA_MASK 0xFFFFFFFFL |
17093 | |
17094 | |
17095 | // addressBlock: gc_cppdec |
17096 | //CP_CU_MASK_ADDR_LO |
17097 | #define CP_CU_MASK_ADDR_LO__ADDR_LO__SHIFT 0x2 |
17098 | #define CP_CU_MASK_ADDR_LO__ADDR_LO_MASK 0xFFFFFFFCL |
17099 | //CP_CU_MASK_ADDR_HI |
17100 | #define CP_CU_MASK_ADDR_HI__ADDR_HI__SHIFT 0x0 |
17101 | #define CP_CU_MASK_ADDR_HI__ADDR_HI_MASK 0xFFFFFFFFL |
17102 | //CP_CU_MASK_CNTL |
17103 | #define CP_CU_MASK_CNTL__POLICY__SHIFT 0x0 |
17104 | #define CP_CU_MASK_CNTL__POLICY_MASK 0x00000001L |
17105 | //CP_EOPQ_WAIT_TIME |
17106 | #define CP_EOPQ_WAIT_TIME__WAIT_TIME__SHIFT 0x0 |
17107 | #define CP_EOPQ_WAIT_TIME__SCALE_COUNT__SHIFT 0xa |
17108 | #define CP_EOPQ_WAIT_TIME__WAIT_TIME_MASK 0x000003FFL |
17109 | #define CP_EOPQ_WAIT_TIME__SCALE_COUNT_MASK 0x0003FC00L |
17110 | //CP_CPC_MGCG_SYNC_CNTL |
17111 | #define CP_CPC_MGCG_SYNC_CNTL__COOLDOWN_PERIOD__SHIFT 0x0 |
17112 | #define CP_CPC_MGCG_SYNC_CNTL__WARMUP_PERIOD__SHIFT 0x8 |
17113 | #define CP_CPC_MGCG_SYNC_CNTL__COOLDOWN_PERIOD_MASK 0x000000FFL |
17114 | #define CP_CPC_MGCG_SYNC_CNTL__WARMUP_PERIOD_MASK 0x0000FF00L |
17115 | //CPC_INT_INFO |
17116 | #define CPC_INT_INFO__ADDR_HI__SHIFT 0x0 |
17117 | #define CPC_INT_INFO__TYPE__SHIFT 0x10 |
17118 | #define CPC_INT_INFO__VMID__SHIFT 0x14 |
17119 | #define CPC_INT_INFO__QUEUE_ID__SHIFT 0x1c |
17120 | #define CPC_INT_INFO__ADDR_HI_MASK 0x0000FFFFL |
17121 | #define CPC_INT_INFO__TYPE_MASK 0x00010000L |
17122 | #define CPC_INT_INFO__VMID_MASK 0x00F00000L |
17123 | #define CPC_INT_INFO__QUEUE_ID_MASK 0x70000000L |
17124 | //CP_VIRT_STATUS |
17125 | #define CP_VIRT_STATUS__VIRT_STATUS__SHIFT 0x0 |
17126 | #define CP_VIRT_STATUS__VIRT_STATUS_MASK 0xFFFFFFFFL |
17127 | //CPC_INT_ADDR |
17128 | #define CPC_INT_ADDR__ADDR__SHIFT 0x0 |
17129 | #define CPC_INT_ADDR__ADDR_MASK 0xFFFFFFFFL |
17130 | //CPC_INT_PASID |
17131 | #define CPC_INT_PASID__PASID__SHIFT 0x0 |
17132 | #define CPC_INT_PASID__BYPASS_PASID__SHIFT 0x10 |
17133 | #define CPC_INT_PASID__PASID_MASK 0x0000FFFFL |
17134 | #define CPC_INT_PASID__BYPASS_PASID_MASK 0x00010000L |
17135 | //CP_GFX_ERROR |
17136 | #define CP_GFX_ERROR__ME_INSTR_CACHE_UTCL1_ERROR__SHIFT 0x0 |
17137 | #define CP_GFX_ERROR__PFP_INSTR_CACHE_UTCL1_ERROR__SHIFT 0x1 |
17138 | #define CP_GFX_ERROR__DDID_DRAW_UTCL1_ERROR__SHIFT 0x2 |
17139 | #define CP_GFX_ERROR__DDID_DISPATCH_UTCL1_ERROR__SHIFT 0x3 |
17140 | #define CP_GFX_ERROR__SUA_ERROR__SHIFT 0x4 |
17141 | #define CP_GFX_ERROR__DATA_FETCHER_UTCL1_ERROR__SHIFT 0x6 |
17142 | #define CP_GFX_ERROR__SEM_UTCL1_ERROR__SHIFT 0x7 |
17143 | #define CP_GFX_ERROR__QU_EOP_UTCL1_ERROR__SHIFT 0x9 |
17144 | #define CP_GFX_ERROR__QU_PIPE_UTCL1_ERROR__SHIFT 0xa |
17145 | #define CP_GFX_ERROR__QU_READ_UTCL1_ERROR__SHIFT 0xb |
17146 | #define CP_GFX_ERROR__SYNC_MEMRD_UTCL1_ERROR__SHIFT 0xc |
17147 | #define CP_GFX_ERROR__SYNC_MEMWR_UTCL1_ERROR__SHIFT 0xd |
17148 | #define CP_GFX_ERROR__SHADOW_UTCL1_ERROR__SHIFT 0xe |
17149 | #define CP_GFX_ERROR__APPEND_UTCL1_ERROR__SHIFT 0xf |
17150 | #define CP_GFX_ERROR__DMA_SRC_UTCL1_ERROR__SHIFT 0x12 |
17151 | #define CP_GFX_ERROR__DMA_DST_UTCL1_ERROR__SHIFT 0x13 |
17152 | #define CP_GFX_ERROR__PFP_TC_UTCL1_ERROR__SHIFT 0x14 |
17153 | #define CP_GFX_ERROR__ME_TC_UTCL1_ERROR__SHIFT 0x15 |
17154 | #define CP_GFX_ERROR__PRT_LOD_UTCL1_ERROR__SHIFT 0x17 |
17155 | #define CP_GFX_ERROR__RDPTR_RPT_UTCL1_ERROR__SHIFT 0x18 |
17156 | #define CP_GFX_ERROR__RB_FETCHER_UTCL1_ERROR__SHIFT 0x19 |
17157 | #define CP_GFX_ERROR__I1_FETCHER_UTCL1_ERROR__SHIFT 0x1a |
17158 | #define CP_GFX_ERROR__I2_FETCHER_UTCL1_ERROR__SHIFT 0x1b |
17159 | #define CP_GFX_ERROR__ST_FETCHER_UTCL1_ERROR__SHIFT 0x1e |
17160 | #define CP_GFX_ERROR__RESERVED__SHIFT 0x1f |
17161 | #define CP_GFX_ERROR__ME_INSTR_CACHE_UTCL1_ERROR_MASK 0x00000001L |
17162 | #define CP_GFX_ERROR__PFP_INSTR_CACHE_UTCL1_ERROR_MASK 0x00000002L |
17163 | #define CP_GFX_ERROR__DDID_DRAW_UTCL1_ERROR_MASK 0x00000004L |
17164 | #define CP_GFX_ERROR__DDID_DISPATCH_UTCL1_ERROR_MASK 0x00000008L |
17165 | #define CP_GFX_ERROR__SUA_ERROR_MASK 0x00000010L |
17166 | #define CP_GFX_ERROR__DATA_FETCHER_UTCL1_ERROR_MASK 0x00000040L |
17167 | #define CP_GFX_ERROR__SEM_UTCL1_ERROR_MASK 0x00000080L |
17168 | #define CP_GFX_ERROR__QU_EOP_UTCL1_ERROR_MASK 0x00000200L |
17169 | #define CP_GFX_ERROR__QU_PIPE_UTCL1_ERROR_MASK 0x00000400L |
17170 | #define CP_GFX_ERROR__QU_READ_UTCL1_ERROR_MASK 0x00000800L |
17171 | #define CP_GFX_ERROR__SYNC_MEMRD_UTCL1_ERROR_MASK 0x00001000L |
17172 | #define CP_GFX_ERROR__SYNC_MEMWR_UTCL1_ERROR_MASK 0x00002000L |
17173 | #define CP_GFX_ERROR__SHADOW_UTCL1_ERROR_MASK 0x00004000L |
17174 | #define CP_GFX_ERROR__APPEND_UTCL1_ERROR_MASK 0x00008000L |
17175 | #define CP_GFX_ERROR__DMA_SRC_UTCL1_ERROR_MASK 0x00040000L |
17176 | #define CP_GFX_ERROR__DMA_DST_UTCL1_ERROR_MASK 0x00080000L |
17177 | #define CP_GFX_ERROR__PFP_TC_UTCL1_ERROR_MASK 0x00100000L |
17178 | #define CP_GFX_ERROR__ME_TC_UTCL1_ERROR_MASK 0x00200000L |
17179 | #define CP_GFX_ERROR__PRT_LOD_UTCL1_ERROR_MASK 0x00800000L |
17180 | #define CP_GFX_ERROR__RDPTR_RPT_UTCL1_ERROR_MASK 0x01000000L |
17181 | #define CP_GFX_ERROR__RB_FETCHER_UTCL1_ERROR_MASK 0x02000000L |
17182 | #define CP_GFX_ERROR__I1_FETCHER_UTCL1_ERROR_MASK 0x04000000L |
17183 | #define CP_GFX_ERROR__I2_FETCHER_UTCL1_ERROR_MASK 0x08000000L |
17184 | #define CP_GFX_ERROR__ST_FETCHER_UTCL1_ERROR_MASK 0x40000000L |
17185 | #define CP_GFX_ERROR__RESERVED_MASK 0x80000000L |
17186 | //CPG_UTCL1_CNTL |
17187 | #define CPG_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 |
17188 | #define CPG_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x17 |
17189 | #define CPG_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 |
17190 | #define CPG_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a |
17191 | #define CPG_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b |
17192 | #define CPG_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c |
17193 | #define CPG_UTCL1_CNTL__IGNORE_PTE_PERMISSION__SHIFT 0x1d |
17194 | #define CPG_UTCL1_CNTL__MTYPE_NO_PTE_MODE__SHIFT 0x1e |
17195 | #define CPG_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL |
17196 | #define CPG_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L |
17197 | #define CPG_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L |
17198 | #define CPG_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L |
17199 | #define CPG_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L |
17200 | #define CPG_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L |
17201 | #define CPG_UTCL1_CNTL__IGNORE_PTE_PERMISSION_MASK 0x20000000L |
17202 | #define CPG_UTCL1_CNTL__MTYPE_NO_PTE_MODE_MASK 0x40000000L |
17203 | //CPC_UTCL1_CNTL |
17204 | #define CPC_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 |
17205 | #define CPC_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 |
17206 | #define CPC_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a |
17207 | #define CPC_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b |
17208 | #define CPC_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c |
17209 | #define CPC_UTCL1_CNTL__IGNORE_PTE_PERMISSION__SHIFT 0x1d |
17210 | #define CPC_UTCL1_CNTL__MTYPE_NO_PTE_MODE__SHIFT 0x1e |
17211 | #define CPC_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL |
17212 | #define CPC_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L |
17213 | #define CPC_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L |
17214 | #define CPC_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L |
17215 | #define CPC_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L |
17216 | #define CPC_UTCL1_CNTL__IGNORE_PTE_PERMISSION_MASK 0x20000000L |
17217 | #define CPC_UTCL1_CNTL__MTYPE_NO_PTE_MODE_MASK 0x40000000L |
17218 | //CPF_UTCL1_CNTL |
17219 | #define CPF_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 |
17220 | #define CPF_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x17 |
17221 | #define CPF_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 |
17222 | #define CPF_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a |
17223 | #define CPF_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b |
17224 | #define CPF_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c |
17225 | #define CPF_UTCL1_CNTL__IGNORE_PTE_PERMISSION__SHIFT 0x1d |
17226 | #define CPF_UTCL1_CNTL__MTYPE_NO_PTE_MODE__SHIFT 0x1e |
17227 | #define CPF_UTCL1_CNTL__FORCE_NO_EXE__SHIFT 0x1f |
17228 | #define CPF_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL |
17229 | #define CPF_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L |
17230 | #define CPF_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L |
17231 | #define CPF_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L |
17232 | #define CPF_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L |
17233 | #define CPF_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L |
17234 | #define CPF_UTCL1_CNTL__IGNORE_PTE_PERMISSION_MASK 0x20000000L |
17235 | #define CPF_UTCL1_CNTL__MTYPE_NO_PTE_MODE_MASK 0x40000000L |
17236 | #define CPF_UTCL1_CNTL__FORCE_NO_EXE_MASK 0x80000000L |
17237 | //CP_AQL_SMM_STATUS |
17238 | #define CP_AQL_SMM_STATUS__AQL_QUEUE_SMM__SHIFT 0x0 |
17239 | #define CP_AQL_SMM_STATUS__AQL_QUEUE_SMM_MASK 0xFFFFFFFFL |
17240 | //CP_RB0_BASE |
17241 | #define CP_RB0_BASE__RB_BASE__SHIFT 0x0 |
17242 | #define CP_RB0_BASE__RB_BASE_MASK 0xFFFFFFFFL |
17243 | //CP_RB_BASE |
17244 | #define CP_RB_BASE__RB_BASE__SHIFT 0x0 |
17245 | #define CP_RB_BASE__RB_BASE_MASK 0xFFFFFFFFL |
17246 | //CP_RB0_CNTL |
17247 | #define CP_RB0_CNTL__RB_BUFSZ__SHIFT 0x0 |
17248 | #define CP_RB0_CNTL__TMZ_STATE__SHIFT 0x6 |
17249 | #define CP_RB0_CNTL__TMZ_MATCH__SHIFT 0x7 |
17250 | #define CP_RB0_CNTL__RB_BLKSZ__SHIFT 0x8 |
17251 | #define CP_RB0_CNTL__RB_NON_PRIV__SHIFT 0xf |
17252 | #define CP_RB0_CNTL__MIN_AVAILSZ__SHIFT 0x14 |
17253 | #define CP_RB0_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16 |
17254 | #define CP_RB0_CNTL__CACHE_POLICY__SHIFT 0x18 |
17255 | #define CP_RB0_CNTL__RB_VOLATILE__SHIFT 0x1a |
17256 | #define CP_RB0_CNTL__RB_NO_UPDATE__SHIFT 0x1b |
17257 | #define CP_RB0_CNTL__RB_EXE__SHIFT 0x1c |
17258 | #define CP_RB0_CNTL__KMD_QUEUE__SHIFT 0x1d |
17259 | #define CP_RB0_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f |
17260 | #define CP_RB0_CNTL__RB_BUFSZ_MASK 0x0000003FL |
17261 | #define CP_RB0_CNTL__TMZ_STATE_MASK 0x00000040L |
17262 | #define CP_RB0_CNTL__TMZ_MATCH_MASK 0x00000080L |
17263 | #define CP_RB0_CNTL__RB_BLKSZ_MASK 0x00003F00L |
17264 | #define CP_RB0_CNTL__RB_NON_PRIV_MASK 0x00008000L |
17265 | #define CP_RB0_CNTL__MIN_AVAILSZ_MASK 0x00300000L |
17266 | #define CP_RB0_CNTL__MIN_IB_AVAILSZ_MASK 0x00C00000L |
17267 | #define CP_RB0_CNTL__CACHE_POLICY_MASK 0x03000000L |
17268 | #define CP_RB0_CNTL__RB_VOLATILE_MASK 0x04000000L |
17269 | #define CP_RB0_CNTL__RB_NO_UPDATE_MASK 0x08000000L |
17270 | #define CP_RB0_CNTL__RB_EXE_MASK 0x10000000L |
17271 | #define CP_RB0_CNTL__KMD_QUEUE_MASK 0x20000000L |
17272 | #define CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L |
17273 | //CP_RB_CNTL |
17274 | #define CP_RB_CNTL__RB_BUFSZ__SHIFT 0x0 |
17275 | #define CP_RB_CNTL__TMZ_STATE__SHIFT 0x6 |
17276 | #define CP_RB_CNTL__TMZ_MATCH__SHIFT 0x7 |
17277 | #define CP_RB_CNTL__RB_BLKSZ__SHIFT 0x8 |
17278 | #define CP_RB_CNTL__RB_NON_PRIV__SHIFT 0xf |
17279 | #define CP_RB_CNTL__MIN_AVAILSZ__SHIFT 0x14 |
17280 | #define CP_RB_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16 |
17281 | #define CP_RB_CNTL__CACHE_POLICY__SHIFT 0x18 |
17282 | #define CP_RB_CNTL__RB_VOLATILE__SHIFT 0x1a |
17283 | #define CP_RB_CNTL__RB_NO_UPDATE__SHIFT 0x1b |
17284 | #define CP_RB_CNTL__RB_EXE__SHIFT 0x1c |
17285 | #define CP_RB_CNTL__KMD_QUEUE__SHIFT 0x1d |
17286 | #define CP_RB_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f |
17287 | #define CP_RB_CNTL__RB_BUFSZ_MASK 0x0000003FL |
17288 | #define CP_RB_CNTL__TMZ_STATE_MASK 0x00000040L |
17289 | #define CP_RB_CNTL__TMZ_MATCH_MASK 0x00000080L |
17290 | #define CP_RB_CNTL__RB_BLKSZ_MASK 0x00003F00L |
17291 | #define CP_RB_CNTL__RB_NON_PRIV_MASK 0x00008000L |
17292 | #define CP_RB_CNTL__MIN_AVAILSZ_MASK 0x00300000L |
17293 | #define CP_RB_CNTL__MIN_IB_AVAILSZ_MASK 0x00C00000L |
17294 | #define CP_RB_CNTL__CACHE_POLICY_MASK 0x03000000L |
17295 | #define CP_RB_CNTL__RB_VOLATILE_MASK 0x04000000L |
17296 | #define CP_RB_CNTL__RB_NO_UPDATE_MASK 0x08000000L |
17297 | #define CP_RB_CNTL__RB_EXE_MASK 0x10000000L |
17298 | #define CP_RB_CNTL__KMD_QUEUE_MASK 0x20000000L |
17299 | #define CP_RB_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L |
17300 | //CP_RB_RPTR_WR |
17301 | #define CP_RB_RPTR_WR__RB_RPTR_WR__SHIFT 0x0 |
17302 | #define CP_RB_RPTR_WR__RB_RPTR_WR_MASK 0x000FFFFFL |
17303 | //CP_RB0_RPTR_ADDR |
17304 | #define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2 |
17305 | #define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFCL |
17306 | //CP_RB_RPTR_ADDR |
17307 | #define CP_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2 |
17308 | #define CP_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFCL |
17309 | //CP_RB0_RPTR_ADDR_HI |
17310 | #define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0 |
17311 | #define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL |
17312 | //CP_RB_RPTR_ADDR_HI |
17313 | #define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0 |
17314 | #define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL |
17315 | //CP_RB0_BUFSZ_MASK |
17316 | #define CP_RB0_BUFSZ_MASK__DATA__SHIFT 0x0 |
17317 | #define CP_RB0_BUFSZ_MASK__DATA_MASK 0x000FFFFFL |
17318 | //CP_RB_BUFSZ_MASK |
17319 | #define CP_RB_BUFSZ_MASK__DATA__SHIFT 0x0 |
17320 | #define CP_RB_BUFSZ_MASK__DATA_MASK 0x000FFFFFL |
17321 | //GC_PRIV_MODE |
17322 | #define GC_PRIV_MODE__MC_PRIV_MODE__SHIFT 0x0 |
17323 | #define GC_PRIV_MODE__MC_PRIV_MODE_MASK 0x00000001L |
17324 | //CP_INT_CNTL |
17325 | #define CP_INT_CNTL__RESUME_INT_ENABLE__SHIFT 0x8 |
17326 | #define CP_INT_CNTL__SUSPEND_INT_ENABLE__SHIFT 0x9 |
17327 | #define CP_INT_CNTL__DMA_WATCH_INT_ENABLE__SHIFT 0xa |
17328 | #define CP_INT_CNTL__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb |
17329 | #define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe |
17330 | #define CP_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 |
17331 | #define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 |
17332 | #define CP_INT_CNTL__CMP_BUSY_INT_ENABLE__SHIFT 0x12 |
17333 | #define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE__SHIFT 0x13 |
17334 | #define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14 |
17335 | #define CP_INT_CNTL__GFX_IDLE_INT_ENABLE__SHIFT 0x15 |
17336 | #define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE__SHIFT 0x16 |
17337 | #define CP_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 |
17338 | #define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 |
17339 | #define CP_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a |
17340 | #define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b |
17341 | #define CP_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d |
17342 | #define CP_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e |
17343 | #define CP_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f |
17344 | #define CP_INT_CNTL__RESUME_INT_ENABLE_MASK 0x00000100L |
17345 | #define CP_INT_CNTL__SUSPEND_INT_ENABLE_MASK 0x00000200L |
17346 | #define CP_INT_CNTL__DMA_WATCH_INT_ENABLE_MASK 0x00000400L |
17347 | #define CP_INT_CNTL__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x00000800L |
17348 | #define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L |
17349 | #define CP_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L |
17350 | #define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L |
17351 | #define CP_INT_CNTL__CMP_BUSY_INT_ENABLE_MASK 0x00040000L |
17352 | #define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L |
17353 | #define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L |
17354 | #define CP_INT_CNTL__GFX_IDLE_INT_ENABLE_MASK 0x00200000L |
17355 | #define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L |
17356 | #define CP_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L |
17357 | #define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L |
17358 | #define CP_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L |
17359 | #define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L |
17360 | #define CP_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L |
17361 | #define CP_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L |
17362 | #define CP_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L |
17363 | //CP_INT_STATUS |
17364 | #define CP_INT_STATUS__RESUME_INT_STAT__SHIFT 0x8 |
17365 | #define CP_INT_STATUS__SUSPEND_INT_STAT__SHIFT 0x9 |
17366 | #define CP_INT_STATUS__DMA_WATCH_INT_STAT__SHIFT 0xa |
17367 | #define CP_INT_STATUS__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb |
17368 | #define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT__SHIFT 0xe |
17369 | #define CP_INT_STATUS__GPF_INT_STAT__SHIFT 0x10 |
17370 | #define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11 |
17371 | #define CP_INT_STATUS__CMP_BUSY_INT_STAT__SHIFT 0x12 |
17372 | #define CP_INT_STATUS__CNTX_BUSY_INT_STAT__SHIFT 0x13 |
17373 | #define CP_INT_STATUS__CNTX_EMPTY_INT_STAT__SHIFT 0x14 |
17374 | #define CP_INT_STATUS__GFX_IDLE_INT_STAT__SHIFT 0x15 |
17375 | #define CP_INT_STATUS__PRIV_INSTR_INT_STAT__SHIFT 0x16 |
17376 | #define CP_INT_STATUS__PRIV_REG_INT_STAT__SHIFT 0x17 |
17377 | #define CP_INT_STATUS__OPCODE_ERROR_INT_STAT__SHIFT 0x18 |
17378 | #define CP_INT_STATUS__TIME_STAMP_INT_STAT__SHIFT 0x1a |
17379 | #define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b |
17380 | #define CP_INT_STATUS__GENERIC2_INT_STAT__SHIFT 0x1d |
17381 | #define CP_INT_STATUS__GENERIC1_INT_STAT__SHIFT 0x1e |
17382 | #define CP_INT_STATUS__GENERIC0_INT_STAT__SHIFT 0x1f |
17383 | #define CP_INT_STATUS__RESUME_INT_STAT_MASK 0x00000100L |
17384 | #define CP_INT_STATUS__SUSPEND_INT_STAT_MASK 0x00000200L |
17385 | #define CP_INT_STATUS__DMA_WATCH_INT_STAT_MASK 0x00000400L |
17386 | #define CP_INT_STATUS__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x00000800L |
17387 | #define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L |
17388 | #define CP_INT_STATUS__GPF_INT_STAT_MASK 0x00010000L |
17389 | #define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L |
17390 | #define CP_INT_STATUS__CMP_BUSY_INT_STAT_MASK 0x00040000L |
17391 | #define CP_INT_STATUS__CNTX_BUSY_INT_STAT_MASK 0x00080000L |
17392 | #define CP_INT_STATUS__CNTX_EMPTY_INT_STAT_MASK 0x00100000L |
17393 | #define CP_INT_STATUS__GFX_IDLE_INT_STAT_MASK 0x00200000L |
17394 | #define CP_INT_STATUS__PRIV_INSTR_INT_STAT_MASK 0x00400000L |
17395 | #define CP_INT_STATUS__PRIV_REG_INT_STAT_MASK 0x00800000L |
17396 | #define CP_INT_STATUS__OPCODE_ERROR_INT_STAT_MASK 0x01000000L |
17397 | #define CP_INT_STATUS__TIME_STAMP_INT_STAT_MASK 0x04000000L |
17398 | #define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L |
17399 | #define CP_INT_STATUS__GENERIC2_INT_STAT_MASK 0x20000000L |
17400 | #define CP_INT_STATUS__GENERIC1_INT_STAT_MASK 0x40000000L |
17401 | #define CP_INT_STATUS__GENERIC0_INT_STAT_MASK 0x80000000L |
17402 | //CP_DEVICE_ID |
17403 | #define CP_DEVICE_ID__DEVICE_ID__SHIFT 0x0 |
17404 | #define CP_DEVICE_ID__DEVICE_ID_MASK 0x000000FFL |
17405 | //CP_ME0_PIPE_PRIORITY_CNTS |
17406 | #define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0 |
17407 | #define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8 |
17408 | #define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10 |
17409 | #define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18 |
17410 | #define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL |
17411 | #define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L |
17412 | #define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L |
17413 | #define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L |
17414 | //CP_RING_PRIORITY_CNTS |
17415 | #define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0 |
17416 | #define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8 |
17417 | #define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10 |
17418 | #define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18 |
17419 | #define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL |
17420 | #define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L |
17421 | #define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L |
17422 | #define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L |
17423 | //CP_ME0_PIPE0_PRIORITY |
17424 | #define CP_ME0_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0 |
17425 | #define CP_ME0_PIPE0_PRIORITY__PRIORITY_MASK 0x00000003L |
17426 | //CP_RING0_PRIORITY |
17427 | #define CP_RING0_PRIORITY__PRIORITY__SHIFT 0x0 |
17428 | #define CP_RING0_PRIORITY__PRIORITY_MASK 0x00000003L |
17429 | //CP_ME0_PIPE1_PRIORITY |
17430 | #define CP_ME0_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0 |
17431 | #define CP_ME0_PIPE1_PRIORITY__PRIORITY_MASK 0x00000003L |
17432 | //CP_RING1_PRIORITY |
17433 | #define CP_RING1_PRIORITY__PRIORITY__SHIFT 0x0 |
17434 | #define CP_RING1_PRIORITY__PRIORITY_MASK 0x00000003L |
17435 | //CP_FATAL_ERROR |
17436 | #define CP_FATAL_ERROR__CPF_FATAL_ERROR__SHIFT 0x0 |
17437 | #define CP_FATAL_ERROR__CPG_FATAL_ERROR__SHIFT 0x1 |
17438 | #define CP_FATAL_ERROR__GFX_HALT_PROC__SHIFT 0x2 |
17439 | #define CP_FATAL_ERROR__DIS_CPG_FATAL_ERROR__SHIFT 0x3 |
17440 | #define CP_FATAL_ERROR__CPG_TAG_FATAL_ERROR_EN__SHIFT 0x4 |
17441 | #define CP_FATAL_ERROR__CPF_FATAL_ERROR_MASK 0x00000001L |
17442 | #define CP_FATAL_ERROR__CPG_FATAL_ERROR_MASK 0x00000002L |
17443 | #define CP_FATAL_ERROR__GFX_HALT_PROC_MASK 0x00000004L |
17444 | #define CP_FATAL_ERROR__DIS_CPG_FATAL_ERROR_MASK 0x00000008L |
17445 | #define CP_FATAL_ERROR__CPG_TAG_FATAL_ERROR_EN_MASK 0x00000010L |
17446 | //CP_RB_VMID |
17447 | #define CP_RB_VMID__RB0_VMID__SHIFT 0x0 |
17448 | #define CP_RB_VMID__RB1_VMID__SHIFT 0x8 |
17449 | #define CP_RB_VMID__RB2_VMID__SHIFT 0x10 |
17450 | #define CP_RB_VMID__RB0_VMID_MASK 0x0000000FL |
17451 | #define CP_RB_VMID__RB1_VMID_MASK 0x00000F00L |
17452 | #define CP_RB_VMID__RB2_VMID_MASK 0x000F0000L |
17453 | //CP_ME0_PIPE0_VMID |
17454 | #define CP_ME0_PIPE0_VMID__VMID__SHIFT 0x0 |
17455 | #define CP_ME0_PIPE0_VMID__VMID_MASK 0x0000000FL |
17456 | //CP_ME0_PIPE1_VMID |
17457 | #define CP_ME0_PIPE1_VMID__VMID__SHIFT 0x0 |
17458 | #define CP_ME0_PIPE1_VMID__VMID_MASK 0x0000000FL |
17459 | //CP_RB0_WPTR |
17460 | #define CP_RB0_WPTR__RB_WPTR__SHIFT 0x0 |
17461 | #define CP_RB0_WPTR__RB_WPTR_MASK 0xFFFFFFFFL |
17462 | //CP_RB_WPTR |
17463 | #define CP_RB_WPTR__RB_WPTR__SHIFT 0x0 |
17464 | #define CP_RB_WPTR__RB_WPTR_MASK 0xFFFFFFFFL |
17465 | //CP_RB0_WPTR_HI |
17466 | #define CP_RB0_WPTR_HI__RB_WPTR__SHIFT 0x0 |
17467 | #define CP_RB0_WPTR_HI__RB_WPTR_MASK 0xFFFFFFFFL |
17468 | //CP_RB_WPTR_HI |
17469 | #define CP_RB_WPTR_HI__RB_WPTR__SHIFT 0x0 |
17470 | #define CP_RB_WPTR_HI__RB_WPTR_MASK 0xFFFFFFFFL |
17471 | //CP_RB1_WPTR |
17472 | #define CP_RB1_WPTR__RB_WPTR__SHIFT 0x0 |
17473 | #define CP_RB1_WPTR__RB_WPTR_MASK 0xFFFFFFFFL |
17474 | //CP_RB1_WPTR_HI |
17475 | #define CP_RB1_WPTR_HI__RB_WPTR__SHIFT 0x0 |
17476 | #define CP_RB1_WPTR_HI__RB_WPTR_MASK 0xFFFFFFFFL |
17477 | //CP_PROCESS_QUANTUM |
17478 | #define CP_PROCESS_QUANTUM__QUANTUM_DURATION__SHIFT 0x0 |
17479 | #define CP_PROCESS_QUANTUM__TIMER_EXPIRED__SHIFT 0x1c |
17480 | #define CP_PROCESS_QUANTUM__QUANTUM_SCALE__SHIFT 0x1d |
17481 | #define CP_PROCESS_QUANTUM__QUANTUM_EN__SHIFT 0x1f |
17482 | #define CP_PROCESS_QUANTUM__QUANTUM_DURATION_MASK 0x0FFFFFFFL |
17483 | #define CP_PROCESS_QUANTUM__TIMER_EXPIRED_MASK 0x10000000L |
17484 | #define CP_PROCESS_QUANTUM__QUANTUM_SCALE_MASK 0x60000000L |
17485 | #define CP_PROCESS_QUANTUM__QUANTUM_EN_MASK 0x80000000L |
17486 | //CP_RB_DOORBELL_RANGE_LOWER |
17487 | #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER__SHIFT 0x2 |
17488 | #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_MASK 0x00000FFCL |
17489 | //CP_RB_DOORBELL_RANGE_UPPER |
17490 | #define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER__SHIFT 0x2 |
17491 | #define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK 0x00000FFCL |
17492 | //CP_MEC_DOORBELL_RANGE_LOWER |
17493 | #define CP_MEC_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER__SHIFT 0x2 |
17494 | #define CP_MEC_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_MASK 0x00000FFCL |
17495 | //CP_MEC_DOORBELL_RANGE_UPPER |
17496 | #define CP_MEC_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER__SHIFT 0x2 |
17497 | #define CP_MEC_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK 0x00000FFCL |
17498 | //CPG_UTCL1_ERROR |
17499 | #define CPG_UTCL1_ERROR__ERROR_DETECTED_HALT__SHIFT 0x0 |
17500 | #define CPG_UTCL1_ERROR__ERROR_DETECTED_HALT_MASK 0x00000001L |
17501 | //CPC_UTCL1_ERROR |
17502 | #define CPC_UTCL1_ERROR__ERROR_DETECTED_HALT__SHIFT 0x0 |
17503 | #define CPC_UTCL1_ERROR__ERROR_DETECTED_HALT_MASK 0x00000001L |
17504 | //CP_RB1_BASE |
17505 | #define CP_RB1_BASE__RB_BASE__SHIFT 0x0 |
17506 | #define CP_RB1_BASE__RB_BASE_MASK 0xFFFFFFFFL |
17507 | //CP_RB1_CNTL |
17508 | #define CP_RB1_CNTL__RB_BUFSZ__SHIFT 0x0 |
17509 | #define CP_RB1_CNTL__TMZ_STATE__SHIFT 0x6 |
17510 | #define CP_RB1_CNTL__TMZ_MATCH__SHIFT 0x7 |
17511 | #define CP_RB1_CNTL__RB_BLKSZ__SHIFT 0x8 |
17512 | #define CP_RB1_CNTL__RB_NON_PRIV__SHIFT 0xf |
17513 | #define CP_RB1_CNTL__MIN_AVAILSZ__SHIFT 0x14 |
17514 | #define CP_RB1_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16 |
17515 | #define CP_RB1_CNTL__CACHE_POLICY__SHIFT 0x18 |
17516 | #define CP_RB1_CNTL__RB_VOLATILE__SHIFT 0x1a |
17517 | #define CP_RB1_CNTL__RB_NO_UPDATE__SHIFT 0x1b |
17518 | #define CP_RB1_CNTL__RB_EXE__SHIFT 0x1c |
17519 | #define CP_RB1_CNTL__KMD_QUEUE__SHIFT 0x1d |
17520 | #define CP_RB1_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f |
17521 | #define CP_RB1_CNTL__RB_BUFSZ_MASK 0x0000003FL |
17522 | #define CP_RB1_CNTL__TMZ_STATE_MASK 0x00000040L |
17523 | #define CP_RB1_CNTL__TMZ_MATCH_MASK 0x00000080L |
17524 | #define CP_RB1_CNTL__RB_BLKSZ_MASK 0x00003F00L |
17525 | #define CP_RB1_CNTL__RB_NON_PRIV_MASK 0x00008000L |
17526 | #define CP_RB1_CNTL__MIN_AVAILSZ_MASK 0x00300000L |
17527 | #define CP_RB1_CNTL__MIN_IB_AVAILSZ_MASK 0x00C00000L |
17528 | #define CP_RB1_CNTL__CACHE_POLICY_MASK 0x03000000L |
17529 | #define CP_RB1_CNTL__RB_VOLATILE_MASK 0x04000000L |
17530 | #define CP_RB1_CNTL__RB_NO_UPDATE_MASK 0x08000000L |
17531 | #define CP_RB1_CNTL__RB_EXE_MASK 0x10000000L |
17532 | #define CP_RB1_CNTL__KMD_QUEUE_MASK 0x20000000L |
17533 | #define CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L |
17534 | //CP_RB1_RPTR_ADDR |
17535 | #define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2 |
17536 | #define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFCL |
17537 | //CP_RB1_RPTR_ADDR_HI |
17538 | #define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0 |
17539 | #define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL |
17540 | //CP_RB1_BUFSZ_MASK |
17541 | #define CP_RB1_BUFSZ_MASK__DATA__SHIFT 0x0 |
17542 | #define CP_RB1_BUFSZ_MASK__DATA_MASK 0x000FFFFFL |
17543 | //CP_INT_CNTL_RING0 |
17544 | #define CP_INT_CNTL_RING0__RESUME_INT_ENABLE__SHIFT 0x8 |
17545 | #define CP_INT_CNTL_RING0__SUSPEND_INT_ENABLE__SHIFT 0x9 |
17546 | #define CP_INT_CNTL_RING0__DMA_WATCH_INT_ENABLE__SHIFT 0xa |
17547 | #define CP_INT_CNTL_RING0__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb |
17548 | #define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe |
17549 | #define CP_INT_CNTL_RING0__GPF_INT_ENABLE__SHIFT 0x10 |
17550 | #define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 |
17551 | #define CP_INT_CNTL_RING0__CMP_BUSY_INT_ENABLE__SHIFT 0x12 |
17552 | #define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE__SHIFT 0x13 |
17553 | #define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14 |
17554 | #define CP_INT_CNTL_RING0__GFX_IDLE_INT_ENABLE__SHIFT 0x15 |
17555 | #define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE__SHIFT 0x16 |
17556 | #define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE__SHIFT 0x17 |
17557 | #define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 |
17558 | #define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE__SHIFT 0x1a |
17559 | #define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b |
17560 | #define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE__SHIFT 0x1d |
17561 | #define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE__SHIFT 0x1e |
17562 | #define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE__SHIFT 0x1f |
17563 | #define CP_INT_CNTL_RING0__RESUME_INT_ENABLE_MASK 0x00000100L |
17564 | #define CP_INT_CNTL_RING0__SUSPEND_INT_ENABLE_MASK 0x00000200L |
17565 | #define CP_INT_CNTL_RING0__DMA_WATCH_INT_ENABLE_MASK 0x00000400L |
17566 | #define CP_INT_CNTL_RING0__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x00000800L |
17567 | #define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L |
17568 | #define CP_INT_CNTL_RING0__GPF_INT_ENABLE_MASK 0x00010000L |
17569 | #define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L |
17570 | #define CP_INT_CNTL_RING0__CMP_BUSY_INT_ENABLE_MASK 0x00040000L |
17571 | #define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L |
17572 | #define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L |
17573 | #define CP_INT_CNTL_RING0__GFX_IDLE_INT_ENABLE_MASK 0x00200000L |
17574 | #define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L |
17575 | #define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK 0x00800000L |
17576 | #define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L |
17577 | #define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK 0x04000000L |
17578 | #define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L |
17579 | #define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE_MASK 0x20000000L |
17580 | #define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE_MASK 0x40000000L |
17581 | #define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE_MASK 0x80000000L |
17582 | //CP_INT_CNTL_RING1 |
17583 | #define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe |
17584 | #define CP_INT_CNTL_RING1__GPF_INT_ENABLE__SHIFT 0x10 |
17585 | #define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 |
17586 | #define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE__SHIFT 0x16 |
17587 | #define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE__SHIFT 0x17 |
17588 | #define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 |
17589 | #define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE__SHIFT 0x1a |
17590 | #define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b |
17591 | #define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE__SHIFT 0x1d |
17592 | #define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE__SHIFT 0x1e |
17593 | #define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE__SHIFT 0x1f |
17594 | #define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L |
17595 | #define CP_INT_CNTL_RING1__GPF_INT_ENABLE_MASK 0x00010000L |
17596 | #define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L |
17597 | #define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L |
17598 | #define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE_MASK 0x00800000L |
17599 | #define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L |
17600 | #define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK 0x04000000L |
17601 | #define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L |
17602 | #define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE_MASK 0x20000000L |
17603 | #define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE_MASK 0x40000000L |
17604 | #define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE_MASK 0x80000000L |
17605 | //CP_INT_STATUS_RING0 |
17606 | #define CP_INT_STATUS_RING0__RESUME_INT_STAT__SHIFT 0x8 |
17607 | #define CP_INT_STATUS_RING0__SUSPEND_INT_STAT__SHIFT 0x9 |
17608 | #define CP_INT_STATUS_RING0__DMA_WATCH_INT_STAT__SHIFT 0xa |
17609 | #define CP_INT_STATUS_RING0__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb |
17610 | #define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT__SHIFT 0xe |
17611 | #define CP_INT_STATUS_RING0__GPF_INT_STAT__SHIFT 0x10 |
17612 | #define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11 |
17613 | #define CP_INT_STATUS_RING0__CMP_BUSY_INT_STAT__SHIFT 0x12 |
17614 | #define CP_INT_STATUS_RING0__GCNTX_BUSY_INT_STAT__SHIFT 0x13 |
17615 | #define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT__SHIFT 0x14 |
17616 | #define CP_INT_STATUS_RING0__GFX_IDLE_INT_STAT__SHIFT 0x15 |
17617 | #define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT__SHIFT 0x16 |
17618 | #define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT__SHIFT 0x17 |
17619 | #define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT__SHIFT 0x18 |
17620 | #define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT__SHIFT 0x1a |
17621 | #define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b |
17622 | #define CP_INT_STATUS_RING0__GENERIC2_INT_STAT__SHIFT 0x1d |
17623 | #define CP_INT_STATUS_RING0__GENERIC1_INT_STAT__SHIFT 0x1e |
17624 | #define CP_INT_STATUS_RING0__GENERIC0_INT_STAT__SHIFT 0x1f |
17625 | #define CP_INT_STATUS_RING0__RESUME_INT_STAT_MASK 0x00000100L |
17626 | #define CP_INT_STATUS_RING0__SUSPEND_INT_STAT_MASK 0x00000200L |
17627 | #define CP_INT_STATUS_RING0__DMA_WATCH_INT_STAT_MASK 0x00000400L |
17628 | #define CP_INT_STATUS_RING0__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x00000800L |
17629 | #define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L |
17630 | #define CP_INT_STATUS_RING0__GPF_INT_STAT_MASK 0x00010000L |
17631 | #define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L |
17632 | #define CP_INT_STATUS_RING0__CMP_BUSY_INT_STAT_MASK 0x00040000L |
17633 | #define CP_INT_STATUS_RING0__GCNTX_BUSY_INT_STAT_MASK 0x00080000L |
17634 | #define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT_MASK 0x00100000L |
17635 | #define CP_INT_STATUS_RING0__GFX_IDLE_INT_STAT_MASK 0x00200000L |
17636 | #define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT_MASK 0x00400000L |
17637 | #define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT_MASK 0x00800000L |
17638 | #define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT_MASK 0x01000000L |
17639 | #define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT_MASK 0x04000000L |
17640 | #define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L |
17641 | #define CP_INT_STATUS_RING0__GENERIC2_INT_STAT_MASK 0x20000000L |
17642 | #define CP_INT_STATUS_RING0__GENERIC1_INT_STAT_MASK 0x40000000L |
17643 | #define CP_INT_STATUS_RING0__GENERIC0_INT_STAT_MASK 0x80000000L |
17644 | //CP_INT_STATUS_RING1 |
17645 | #define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT__SHIFT 0xe |
17646 | #define CP_INT_STATUS_RING1__GPF_INT_STAT__SHIFT 0x10 |
17647 | #define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11 |
17648 | #define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT__SHIFT 0x16 |
17649 | #define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT__SHIFT 0x17 |
17650 | #define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT__SHIFT 0x18 |
17651 | #define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT__SHIFT 0x1a |
17652 | #define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b |
17653 | #define CP_INT_STATUS_RING1__GENERIC2_INT_STAT__SHIFT 0x1d |
17654 | #define CP_INT_STATUS_RING1__GENERIC1_INT_STAT__SHIFT 0x1e |
17655 | #define CP_INT_STATUS_RING1__GENERIC0_INT_STAT__SHIFT 0x1f |
17656 | #define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L |
17657 | #define CP_INT_STATUS_RING1__GPF_INT_STAT_MASK 0x00010000L |
17658 | #define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L |
17659 | #define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT_MASK 0x00400000L |
17660 | #define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT_MASK 0x00800000L |
17661 | #define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT_MASK 0x01000000L |
17662 | #define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT_MASK 0x04000000L |
17663 | #define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L |
17664 | #define CP_INT_STATUS_RING1__GENERIC2_INT_STAT_MASK 0x20000000L |
17665 | #define CP_INT_STATUS_RING1__GENERIC1_INT_STAT_MASK 0x40000000L |
17666 | #define CP_INT_STATUS_RING1__GENERIC0_INT_STAT_MASK 0x80000000L |
17667 | //CP_ME_F32_INTERRUPT |
17668 | #define CP_ME_F32_INTERRUPT__ECC_ERROR_INT__SHIFT 0x0 |
17669 | #define CP_ME_F32_INTERRUPT__TIME_STAMP_INT__SHIFT 0x1 |
17670 | #define CP_ME_F32_INTERRUPT__ME_F32_INT_2__SHIFT 0x2 |
17671 | #define CP_ME_F32_INTERRUPT__ME_F32_INT_3__SHIFT 0x3 |
17672 | #define CP_ME_F32_INTERRUPT__ECC_ERROR_INT_MASK 0x00000001L |
17673 | #define CP_ME_F32_INTERRUPT__TIME_STAMP_INT_MASK 0x00000002L |
17674 | #define CP_ME_F32_INTERRUPT__ME_F32_INT_2_MASK 0x00000004L |
17675 | #define CP_ME_F32_INTERRUPT__ME_F32_INT_3_MASK 0x00000008L |
17676 | //CP_PFP_F32_INTERRUPT |
17677 | #define CP_PFP_F32_INTERRUPT__ECC_ERROR_INT__SHIFT 0x0 |
17678 | #define CP_PFP_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1 |
17679 | #define CP_PFP_F32_INTERRUPT__RESERVED_BIT_ERR_INT__SHIFT 0x2 |
17680 | #define CP_PFP_F32_INTERRUPT__PFP_F32_INT_3__SHIFT 0x3 |
17681 | #define CP_PFP_F32_INTERRUPT__ECC_ERROR_INT_MASK 0x00000001L |
17682 | #define CP_PFP_F32_INTERRUPT__PRIV_REG_INT_MASK 0x00000002L |
17683 | #define CP_PFP_F32_INTERRUPT__RESERVED_BIT_ERR_INT_MASK 0x00000004L |
17684 | #define CP_PFP_F32_INTERRUPT__PFP_F32_INT_3_MASK 0x00000008L |
17685 | //CP_MEC1_F32_INTERRUPT |
17686 | #define CP_MEC1_F32_INTERRUPT__EDC_ROQ_FED_INT__SHIFT 0x0 |
17687 | #define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1 |
17688 | #define CP_MEC1_F32_INTERRUPT__RESERVED_BIT_ERR_INT__SHIFT 0x2 |
17689 | #define CP_MEC1_F32_INTERRUPT__EDC_TC_FED_INT__SHIFT 0x3 |
17690 | #define CP_MEC1_F32_INTERRUPT__EDC_GDS_FED_INT__SHIFT 0x4 |
17691 | #define CP_MEC1_F32_INTERRUPT__EDC_SCRATCH_FED_INT__SHIFT 0x5 |
17692 | #define CP_MEC1_F32_INTERRUPT__WAVE_RESTORE_INT__SHIFT 0x6 |
17693 | #define CP_MEC1_F32_INTERRUPT__SUA_VIOLATION_INT__SHIFT 0x7 |
17694 | #define CP_MEC1_F32_INTERRUPT__EDC_DMA_FED_INT__SHIFT 0x8 |
17695 | #define CP_MEC1_F32_INTERRUPT__IQ_TIMER_INT__SHIFT 0x9 |
17696 | #define CP_MEC1_F32_INTERRUPT__GPF_INT_CPF__SHIFT 0xa |
17697 | #define CP_MEC1_F32_INTERRUPT__GPF_INT_DMA__SHIFT 0xb |
17698 | #define CP_MEC1_F32_INTERRUPT__GPF_INT_CPC__SHIFT 0xc |
17699 | #define CP_MEC1_F32_INTERRUPT__EDC_SR_MEM_FED_INT__SHIFT 0xd |
17700 | #define CP_MEC1_F32_INTERRUPT__QUEUE_MESSAGE_INT__SHIFT 0xe |
17701 | #define CP_MEC1_F32_INTERRUPT__FATAL_EDC_ERROR_INT__SHIFT 0xf |
17702 | #define CP_MEC1_F32_INTERRUPT__EDC_ROQ_FED_INT_MASK 0x00000001L |
17703 | #define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT_MASK 0x00000002L |
17704 | #define CP_MEC1_F32_INTERRUPT__RESERVED_BIT_ERR_INT_MASK 0x00000004L |
17705 | #define CP_MEC1_F32_INTERRUPT__EDC_TC_FED_INT_MASK 0x00000008L |
17706 | #define CP_MEC1_F32_INTERRUPT__EDC_GDS_FED_INT_MASK 0x00000010L |
17707 | #define CP_MEC1_F32_INTERRUPT__EDC_SCRATCH_FED_INT_MASK 0x00000020L |
17708 | #define CP_MEC1_F32_INTERRUPT__WAVE_RESTORE_INT_MASK 0x00000040L |
17709 | #define CP_MEC1_F32_INTERRUPT__SUA_VIOLATION_INT_MASK 0x00000080L |
17710 | #define CP_MEC1_F32_INTERRUPT__EDC_DMA_FED_INT_MASK 0x00000100L |
17711 | #define CP_MEC1_F32_INTERRUPT__IQ_TIMER_INT_MASK 0x00000200L |
17712 | #define CP_MEC1_F32_INTERRUPT__GPF_INT_CPF_MASK 0x00000400L |
17713 | #define CP_MEC1_F32_INTERRUPT__GPF_INT_DMA_MASK 0x00000800L |
17714 | #define CP_MEC1_F32_INTERRUPT__GPF_INT_CPC_MASK 0x00001000L |
17715 | #define CP_MEC1_F32_INTERRUPT__EDC_SR_MEM_FED_INT_MASK 0x00002000L |
17716 | #define CP_MEC1_F32_INTERRUPT__QUEUE_MESSAGE_INT_MASK 0x00004000L |
17717 | #define CP_MEC1_F32_INTERRUPT__FATAL_EDC_ERROR_INT_MASK 0x00008000L |
17718 | //CP_MEC2_F32_INTERRUPT |
17719 | #define CP_MEC2_F32_INTERRUPT__EDC_ROQ_FED_INT__SHIFT 0x0 |
17720 | #define CP_MEC2_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1 |
17721 | #define CP_MEC2_F32_INTERRUPT__RESERVED_BIT_ERR_INT__SHIFT 0x2 |
17722 | #define CP_MEC2_F32_INTERRUPT__EDC_TC_FED_INT__SHIFT 0x3 |
17723 | #define CP_MEC2_F32_INTERRUPT__EDC_GDS_FED_INT__SHIFT 0x4 |
17724 | #define CP_MEC2_F32_INTERRUPT__EDC_SCRATCH_FED_INT__SHIFT 0x5 |
17725 | #define CP_MEC2_F32_INTERRUPT__WAVE_RESTORE_INT__SHIFT 0x6 |
17726 | #define CP_MEC2_F32_INTERRUPT__SUA_VIOLATION_INT__SHIFT 0x7 |
17727 | #define CP_MEC2_F32_INTERRUPT__EDC_DMA_FED_INT__SHIFT 0x8 |
17728 | #define CP_MEC2_F32_INTERRUPT__IQ_TIMER_INT__SHIFT 0x9 |
17729 | #define CP_MEC2_F32_INTERRUPT__GPF_INT_CPF__SHIFT 0xa |
17730 | #define CP_MEC2_F32_INTERRUPT__GPF_INT_DMA__SHIFT 0xb |
17731 | #define CP_MEC2_F32_INTERRUPT__GPF_INT_CPC__SHIFT 0xc |
17732 | #define CP_MEC2_F32_INTERRUPT__EDC_SR_MEM_FED_INT__SHIFT 0xd |
17733 | #define CP_MEC2_F32_INTERRUPT__QUEUE_MESSAGE_INT__SHIFT 0xe |
17734 | #define CP_MEC2_F32_INTERRUPT__FATAL_EDC_ERROR_INT__SHIFT 0xf |
17735 | #define CP_MEC2_F32_INTERRUPT__EDC_ROQ_FED_INT_MASK 0x00000001L |
17736 | #define CP_MEC2_F32_INTERRUPT__PRIV_REG_INT_MASK 0x00000002L |
17737 | #define CP_MEC2_F32_INTERRUPT__RESERVED_BIT_ERR_INT_MASK 0x00000004L |
17738 | #define CP_MEC2_F32_INTERRUPT__EDC_TC_FED_INT_MASK 0x00000008L |
17739 | #define CP_MEC2_F32_INTERRUPT__EDC_GDS_FED_INT_MASK 0x00000010L |
17740 | #define CP_MEC2_F32_INTERRUPT__EDC_SCRATCH_FED_INT_MASK 0x00000020L |
17741 | #define CP_MEC2_F32_INTERRUPT__WAVE_RESTORE_INT_MASK 0x00000040L |
17742 | #define CP_MEC2_F32_INTERRUPT__SUA_VIOLATION_INT_MASK 0x00000080L |
17743 | #define CP_MEC2_F32_INTERRUPT__EDC_DMA_FED_INT_MASK 0x00000100L |
17744 | #define CP_MEC2_F32_INTERRUPT__IQ_TIMER_INT_MASK 0x00000200L |
17745 | #define CP_MEC2_F32_INTERRUPT__GPF_INT_CPF_MASK 0x00000400L |
17746 | #define CP_MEC2_F32_INTERRUPT__GPF_INT_DMA_MASK 0x00000800L |
17747 | #define CP_MEC2_F32_INTERRUPT__GPF_INT_CPC_MASK 0x00001000L |
17748 | #define CP_MEC2_F32_INTERRUPT__EDC_SR_MEM_FED_INT_MASK 0x00002000L |
17749 | #define CP_MEC2_F32_INTERRUPT__QUEUE_MESSAGE_INT_MASK 0x00004000L |
17750 | #define CP_MEC2_F32_INTERRUPT__FATAL_EDC_ERROR_INT_MASK 0x00008000L |
17751 | //CP_PWR_CNTL |
17752 | #define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0__SHIFT 0x0 |
17753 | #define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1__SHIFT 0x1 |
17754 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0__SHIFT 0x8 |
17755 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1__SHIFT 0x9 |
17756 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2__SHIFT 0xa |
17757 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE3__SHIFT 0xb |
17758 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0__SHIFT 0x10 |
17759 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE1__SHIFT 0x11 |
17760 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2__SHIFT 0x12 |
17761 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3__SHIFT 0x13 |
17762 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME3_PIPE0__SHIFT 0x14 |
17763 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME3_PIPE1__SHIFT 0x15 |
17764 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME3_PIPE2__SHIFT 0x16 |
17765 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME3_PIPE3__SHIFT 0x17 |
17766 | #define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0_MASK 0x00000001L |
17767 | #define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1_MASK 0x00000002L |
17768 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0_MASK 0x00000100L |
17769 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1_MASK 0x00000200L |
17770 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2_MASK 0x00000400L |
17771 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE3_MASK 0x00000800L |
17772 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0_MASK 0x00010000L |
17773 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE1_MASK 0x00020000L |
17774 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2_MASK 0x00040000L |
17775 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3_MASK 0x00080000L |
17776 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME3_PIPE0_MASK 0x00100000L |
17777 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME3_PIPE1_MASK 0x00200000L |
17778 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME3_PIPE2_MASK 0x00400000L |
17779 | #define CP_PWR_CNTL__CMP_CLK_HALT_ME3_PIPE3_MASK 0x00800000L |
17780 | //CP_ECC_FIRSTOCCURRENCE |
17781 | #define CP_ECC_FIRSTOCCURRENCE__INTERFACE__SHIFT 0x0 |
17782 | #define CP_ECC_FIRSTOCCURRENCE__CLIENT__SHIFT 0x4 |
17783 | #define CP_ECC_FIRSTOCCURRENCE__ME__SHIFT 0x8 |
17784 | #define CP_ECC_FIRSTOCCURRENCE__PIPE__SHIFT 0xa |
17785 | #define CP_ECC_FIRSTOCCURRENCE__VMID__SHIFT 0x10 |
17786 | #define CP_ECC_FIRSTOCCURRENCE__INTERFACE_MASK 0x00000003L |
17787 | #define CP_ECC_FIRSTOCCURRENCE__CLIENT_MASK 0x000000F0L |
17788 | #define CP_ECC_FIRSTOCCURRENCE__ME_MASK 0x00000300L |
17789 | #define CP_ECC_FIRSTOCCURRENCE__PIPE_MASK 0x00000C00L |
17790 | #define CP_ECC_FIRSTOCCURRENCE__VMID_MASK 0x000F0000L |
17791 | //CP_ECC_FIRSTOCCURRENCE_RING0 |
17792 | #define CP_ECC_FIRSTOCCURRENCE_RING0__OBSOLETE__SHIFT 0x0 |
17793 | #define CP_ECC_FIRSTOCCURRENCE_RING0__OBSOLETE_MASK 0xFFFFFFFFL |
17794 | //CP_ECC_FIRSTOCCURRENCE_RING1 |
17795 | #define CP_ECC_FIRSTOCCURRENCE_RING1__OBSOLETE__SHIFT 0x0 |
17796 | #define CP_ECC_FIRSTOCCURRENCE_RING1__OBSOLETE_MASK 0xFFFFFFFFL |
17797 | //GB_EDC_MODE |
17798 | #define GB_EDC_MODE__FORCE_SEC_ON_DED__SHIFT 0xf |
17799 | #define GB_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10 |
17800 | #define GB_EDC_MODE__GATE_FUE__SHIFT 0x11 |
17801 | #define GB_EDC_MODE__DED_MODE__SHIFT 0x14 |
17802 | #define GB_EDC_MODE__PROP_FED__SHIFT 0x1d |
17803 | #define GB_EDC_MODE__BYPASS__SHIFT 0x1f |
17804 | #define GB_EDC_MODE__FORCE_SEC_ON_DED_MASK 0x00008000L |
17805 | #define GB_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L |
17806 | #define GB_EDC_MODE__GATE_FUE_MASK 0x00020000L |
17807 | #define GB_EDC_MODE__DED_MODE_MASK 0x00300000L |
17808 | #define GB_EDC_MODE__PROP_FED_MASK 0x20000000L |
17809 | #define GB_EDC_MODE__BYPASS_MASK 0x80000000L |
17810 | //CP_DEBUG |
17811 | #define CP_DEBUG__PERFMON_RING_SEL__SHIFT 0x0 |
17812 | #define CP_DEBUG__DEBUG_BUS_SELECT_BITS__SHIFT 0x2 |
17813 | #define CP_DEBUG__DEBUG_BUS_FLOP_EN__SHIFT 0x8 |
17814 | #define CP_DEBUG__CPG_REPEATER_FGCG_OVERRIDE__SHIFT 0x9 |
17815 | #define CP_DEBUG__PACKET_FILTER_DISABLE__SHIFT 0xa |
17816 | #define CP_DEBUG__NOT_EOP_PREEMPT_DISABLE__SHIFT 0xb |
17817 | #define CP_DEBUG__CPG_CHIU_RO_DISABLE__SHIFT 0xc |
17818 | #define CP_DEBUG__CPG_GCR_CNTL_BYPASS__SHIFT 0xd |
17819 | #define CP_DEBUG__CPG_RAM_CLK_GATING_DISABLE__SHIFT 0xe |
17820 | #define CP_DEBUG__CPG_UTCL1_ERROR_HALT_DISABLE__SHIFT 0xf |
17821 | #define CP_DEBUG__SURFSYNC_CNTX_RDADDR__SHIFT 0x10 |
17822 | #define CP_DEBUG__CPG_DATA_POISONING_INT_DISABLE__SHIFT 0x13 |
17823 | #define CP_DEBUG__PRIV_VIOLATION_WRITE_DISABLE__SHIFT 0x14 |
17824 | #define CP_DEBUG__CPG_CHIU_GUS_DISABLE__SHIFT 0x15 |
17825 | #define CP_DEBUG__INTERRUPT_DISABLE__SHIFT 0x16 |
17826 | #define CP_DEBUG__PREDICATE_DISABLE__SHIFT 0x17 |
17827 | #define CP_DEBUG__UNDERFLOW_BUSY_DISABLE__SHIFT 0x18 |
17828 | #define CP_DEBUG__OVERFLOW_BUSY_DISABLE__SHIFT 0x19 |
17829 | #define CP_DEBUG__EVENT_FILT_DISABLE__SHIFT 0x1a |
17830 | #define CP_DEBUG__CPG_CHIU_MTYPE_OVERRIDE__SHIFT 0x1b |
17831 | #define CP_DEBUG__CPG_TC_ONE_CYCLE_WRITE_DISABLE__SHIFT 0x1c |
17832 | #define CP_DEBUG__CS_STATE_FILT_DISABLE__SHIFT 0x1d |
17833 | #define CP_DEBUG__CS_PIPELINE_RESET_DISABLE__SHIFT 0x1e |
17834 | #define CP_DEBUG__IB_PACKET_INJECTOR_DISABLE__SHIFT 0x1f |
17835 | #define CP_DEBUG__PERFMON_RING_SEL_MASK 0x00000003L |
17836 | #define CP_DEBUG__DEBUG_BUS_SELECT_BITS_MASK 0x000000FCL |
17837 | #define CP_DEBUG__DEBUG_BUS_FLOP_EN_MASK 0x00000100L |
17838 | #define CP_DEBUG__CPG_REPEATER_FGCG_OVERRIDE_MASK 0x00000200L |
17839 | #define CP_DEBUG__PACKET_FILTER_DISABLE_MASK 0x00000400L |
17840 | #define CP_DEBUG__NOT_EOP_PREEMPT_DISABLE_MASK 0x00000800L |
17841 | #define CP_DEBUG__CPG_CHIU_RO_DISABLE_MASK 0x00001000L |
17842 | #define CP_DEBUG__CPG_GCR_CNTL_BYPASS_MASK 0x00002000L |
17843 | #define CP_DEBUG__CPG_RAM_CLK_GATING_DISABLE_MASK 0x00004000L |
17844 | #define CP_DEBUG__CPG_UTCL1_ERROR_HALT_DISABLE_MASK 0x00008000L |
17845 | #define CP_DEBUG__SURFSYNC_CNTX_RDADDR_MASK 0x00070000L |
17846 | #define CP_DEBUG__CPG_DATA_POISONING_INT_DISABLE_MASK 0x00080000L |
17847 | #define CP_DEBUG__PRIV_VIOLATION_WRITE_DISABLE_MASK 0x00100000L |
17848 | #define CP_DEBUG__CPG_CHIU_GUS_DISABLE_MASK 0x00200000L |
17849 | #define CP_DEBUG__INTERRUPT_DISABLE_MASK 0x00400000L |
17850 | #define CP_DEBUG__PREDICATE_DISABLE_MASK 0x00800000L |
17851 | #define CP_DEBUG__UNDERFLOW_BUSY_DISABLE_MASK 0x01000000L |
17852 | #define CP_DEBUG__OVERFLOW_BUSY_DISABLE_MASK 0x02000000L |
17853 | #define CP_DEBUG__EVENT_FILT_DISABLE_MASK 0x04000000L |
17854 | #define CP_DEBUG__CPG_CHIU_MTYPE_OVERRIDE_MASK 0x08000000L |
17855 | #define CP_DEBUG__CPG_TC_ONE_CYCLE_WRITE_DISABLE_MASK 0x10000000L |
17856 | #define CP_DEBUG__CS_STATE_FILT_DISABLE_MASK 0x20000000L |
17857 | #define CP_DEBUG__CS_PIPELINE_RESET_DISABLE_MASK 0x40000000L |
17858 | #define CP_DEBUG__IB_PACKET_INJECTOR_DISABLE_MASK 0x80000000L |
17859 | //CP_CPF_DEBUG |
17860 | #define CP_CPF_DEBUG__DEBUG_BUS_FLOP_EN__SHIFT 0xe |
17861 | #define CP_CPF_DEBUG__CPF_REPEATER_FGCG_OVERRIDE__SHIFT 0x10 |
17862 | #define CP_CPF_DEBUG__CPF_GCR_CNTL_BYPASS__SHIFT 0x11 |
17863 | #define CP_CPF_DEBUG__CPF_RAM_CLK_GATING_DISABLE__SHIFT 0x12 |
17864 | #define CP_CPF_DEBUG__CPF_DATA_POISONING_INT_DISABLE__SHIFT 0x13 |
17865 | #define CP_CPF_DEBUG__CLOCK_ACTIVE_DELAY_OVERRIDE__SHIFT 0x16 |
17866 | #define CP_CPF_DEBUG__CLOCK_ACTIVE_OVERRIDE__SHIFT 0x17 |
17867 | #define CP_CPF_DEBUG__UNDERFLOW_BUSY_DISABLE__SHIFT 0x18 |
17868 | #define CP_CPF_DEBUG__OVERFLOW_BUSY_DISABLE__SHIFT 0x19 |
17869 | #define CP_CPF_DEBUG__CPF_CHIU_NOALLOC_OVERRIDE__SHIFT 0x1a |
17870 | #define CP_CPF_DEBUG__CE_FETCHER_DISABLE__SHIFT 0x1b |
17871 | #define CP_CPF_DEBUG__CPF_CHIU_GUS_DISABLE__SHIFT 0x1c |
17872 | #define CP_CPF_DEBUG__CPF_PRIORITY_YIELD_ACTIVE_DIS__SHIFT 0x1d |
17873 | #define CP_CPF_DEBUG__CPF_CHIU_MTYPE_OVERRIDE__SHIFT 0x1e |
17874 | #define CP_CPF_DEBUG__DBGU_TRIGGER__SHIFT 0x1f |
17875 | #define CP_CPF_DEBUG__DEBUG_BUS_FLOP_EN_MASK 0x00004000L |
17876 | #define CP_CPF_DEBUG__CPF_REPEATER_FGCG_OVERRIDE_MASK 0x00010000L |
17877 | #define CP_CPF_DEBUG__CPF_GCR_CNTL_BYPASS_MASK 0x00020000L |
17878 | #define CP_CPF_DEBUG__CPF_RAM_CLK_GATING_DISABLE_MASK 0x00040000L |
17879 | #define CP_CPF_DEBUG__CPF_DATA_POISONING_INT_DISABLE_MASK 0x00080000L |
17880 | #define CP_CPF_DEBUG__CLOCK_ACTIVE_DELAY_OVERRIDE_MASK 0x00400000L |
17881 | #define CP_CPF_DEBUG__CLOCK_ACTIVE_OVERRIDE_MASK 0x00800000L |
17882 | #define CP_CPF_DEBUG__UNDERFLOW_BUSY_DISABLE_MASK 0x01000000L |
17883 | #define CP_CPF_DEBUG__OVERFLOW_BUSY_DISABLE_MASK 0x02000000L |
17884 | #define CP_CPF_DEBUG__CPF_CHIU_NOALLOC_OVERRIDE_MASK 0x04000000L |
17885 | #define CP_CPF_DEBUG__CE_FETCHER_DISABLE_MASK 0x08000000L |
17886 | #define CP_CPF_DEBUG__CPF_CHIU_GUS_DISABLE_MASK 0x10000000L |
17887 | #define CP_CPF_DEBUG__CPF_PRIORITY_YIELD_ACTIVE_DIS_MASK 0x20000000L |
17888 | #define CP_CPF_DEBUG__CPF_CHIU_MTYPE_OVERRIDE_MASK 0x40000000L |
17889 | #define CP_CPF_DEBUG__DBGU_TRIGGER_MASK 0x80000000L |
17890 | //CP_CPC_DEBUG |
17891 | #define CP_CPC_DEBUG__PIPE_SELECT__SHIFT 0x0 |
17892 | #define CP_CPC_DEBUG__ME_SELECT__SHIFT 0x2 |
17893 | #define CP_CPC_DEBUG__ADC_INTERLEAVE_DISABLE__SHIFT 0x4 |
17894 | #define CP_CPC_DEBUG__DEBUG_BUS_FLOP_EN__SHIFT 0xe |
17895 | #define CP_CPC_DEBUG__CPC_REPEATER_FGCG_OVERRIDE__SHIFT 0xf |
17896 | #define CP_CPC_DEBUG__CPC_CHIU_NOALLOC_OVERRIDE__SHIFT 0x10 |
17897 | #define CP_CPC_DEBUG__CPC_GCR_CNTL_BYPASS__SHIFT 0x11 |
17898 | #define CP_CPC_DEBUG__CPC_RAM_CLK_GATING_DISABLE__SHIFT 0x12 |
17899 | #define CP_CPC_DEBUG__CPC_DATA_POISONING_INT_DISABLE__SHIFT 0x13 |
17900 | #define CP_CPC_DEBUG__PRIV_VIOLATION_WRITE_DISABLE__SHIFT 0x14 |
17901 | #define CP_CPC_DEBUG__UCODE_ECC_ERROR_DISABLE__SHIFT 0x15 |
17902 | #define CP_CPC_DEBUG__INTERRUPT_DISABLE__SHIFT 0x16 |
17903 | #define CP_CPC_DEBUG__CPC_CHIU_RO_DISABLE__SHIFT 0x17 |
17904 | #define CP_CPC_DEBUG__UNDERFLOW_BUSY_DISABLE__SHIFT 0x18 |
17905 | #define CP_CPC_DEBUG__OVERFLOW_BUSY_DISABLE__SHIFT 0x19 |
17906 | #define CP_CPC_DEBUG__EVENT_FILT_DISABLE__SHIFT 0x1a |
17907 | #define CP_CPC_DEBUG__CPC_CHIU_GUS_DISABLE__SHIFT 0x1b |
17908 | #define CP_CPC_DEBUG__CPC_TC_ONE_CYCLE_WRITE_DISABLE__SHIFT 0x1c |
17909 | #define CP_CPC_DEBUG__CS_STATE_FILT_DISABLE__SHIFT 0x1d |
17910 | #define CP_CPC_DEBUG__CPC_CHIU_MTYPE_OVERRIDE__SHIFT 0x1e |
17911 | #define CP_CPC_DEBUG__ME2_UCODE_RAM_ENABLE__SHIFT 0x1f |
17912 | #define CP_CPC_DEBUG__PIPE_SELECT_MASK 0x00000003L |
17913 | #define CP_CPC_DEBUG__ME_SELECT_MASK 0x00000004L |
17914 | #define CP_CPC_DEBUG__ADC_INTERLEAVE_DISABLE_MASK 0x00000010L |
17915 | #define CP_CPC_DEBUG__DEBUG_BUS_FLOP_EN_MASK 0x00004000L |
17916 | #define CP_CPC_DEBUG__CPC_REPEATER_FGCG_OVERRIDE_MASK 0x00008000L |
17917 | #define CP_CPC_DEBUG__CPC_CHIU_NOALLOC_OVERRIDE_MASK 0x00010000L |
17918 | #define CP_CPC_DEBUG__CPC_GCR_CNTL_BYPASS_MASK 0x00020000L |
17919 | #define CP_CPC_DEBUG__CPC_RAM_CLK_GATING_DISABLE_MASK 0x00040000L |
17920 | #define CP_CPC_DEBUG__CPC_DATA_POISONING_INT_DISABLE_MASK 0x00080000L |
17921 | #define CP_CPC_DEBUG__PRIV_VIOLATION_WRITE_DISABLE_MASK 0x00100000L |
17922 | #define CP_CPC_DEBUG__UCODE_ECC_ERROR_DISABLE_MASK 0x00200000L |
17923 | #define CP_CPC_DEBUG__INTERRUPT_DISABLE_MASK 0x00400000L |
17924 | #define CP_CPC_DEBUG__CPC_CHIU_RO_DISABLE_MASK 0x00800000L |
17925 | #define CP_CPC_DEBUG__UNDERFLOW_BUSY_DISABLE_MASK 0x01000000L |
17926 | #define CP_CPC_DEBUG__OVERFLOW_BUSY_DISABLE_MASK 0x02000000L |
17927 | #define CP_CPC_DEBUG__EVENT_FILT_DISABLE_MASK 0x04000000L |
17928 | #define CP_CPC_DEBUG__CPC_CHIU_GUS_DISABLE_MASK 0x08000000L |
17929 | #define CP_CPC_DEBUG__CPC_TC_ONE_CYCLE_WRITE_DISABLE_MASK 0x10000000L |
17930 | #define CP_CPC_DEBUG__CS_STATE_FILT_DISABLE_MASK 0x20000000L |
17931 | #define CP_CPC_DEBUG__CPC_CHIU_MTYPE_OVERRIDE_MASK 0x40000000L |
17932 | #define CP_CPC_DEBUG__ME2_UCODE_RAM_ENABLE_MASK 0x80000000L |
17933 | //CP_PQ_WPTR_POLL_CNTL |
17934 | #define CP_PQ_WPTR_POLL_CNTL__PERIOD__SHIFT 0x0 |
17935 | #define CP_PQ_WPTR_POLL_CNTL__DISABLE_PEND_REQ_ONE_SHOT__SHIFT 0x1d |
17936 | #define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE__SHIFT 0x1e |
17937 | #define CP_PQ_WPTR_POLL_CNTL__EN__SHIFT 0x1f |
17938 | #define CP_PQ_WPTR_POLL_CNTL__PERIOD_MASK 0x000000FFL |
17939 | #define CP_PQ_WPTR_POLL_CNTL__DISABLE_PEND_REQ_ONE_SHOT_MASK 0x20000000L |
17940 | #define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE_MASK 0x40000000L |
17941 | #define CP_PQ_WPTR_POLL_CNTL__EN_MASK 0x80000000L |
17942 | //CP_PQ_WPTR_POLL_CNTL1 |
17943 | #define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK__SHIFT 0x0 |
17944 | #define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK_MASK 0xFFFFFFFFL |
17945 | //CP_ME1_PIPE0_INT_CNTL |
17946 | #define CP_ME1_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc |
17947 | #define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd |
17948 | #define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe |
17949 | #define CP_ME1_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf |
17950 | #define CP_ME1_PIPE0_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 |
17951 | #define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 |
17952 | #define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 |
17953 | #define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 |
17954 | #define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a |
17955 | #define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b |
17956 | #define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d |
17957 | #define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e |
17958 | #define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f |
17959 | #define CP_ME1_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L |
17960 | #define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L |
17961 | #define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L |
17962 | #define CP_ME1_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L |
17963 | #define CP_ME1_PIPE0_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L |
17964 | #define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L |
17965 | #define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L |
17966 | #define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L |
17967 | #define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L |
17968 | #define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L |
17969 | #define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L |
17970 | #define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L |
17971 | #define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L |
17972 | //CP_ME1_PIPE1_INT_CNTL |
17973 | #define CP_ME1_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc |
17974 | #define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd |
17975 | #define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe |
17976 | #define CP_ME1_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf |
17977 | #define CP_ME1_PIPE1_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 |
17978 | #define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 |
17979 | #define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 |
17980 | #define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 |
17981 | #define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a |
17982 | #define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b |
17983 | #define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d |
17984 | #define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e |
17985 | #define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f |
17986 | #define CP_ME1_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L |
17987 | #define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L |
17988 | #define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L |
17989 | #define CP_ME1_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L |
17990 | #define CP_ME1_PIPE1_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L |
17991 | #define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L |
17992 | #define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L |
17993 | #define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L |
17994 | #define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L |
17995 | #define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L |
17996 | #define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L |
17997 | #define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L |
17998 | #define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L |
17999 | //CP_ME1_PIPE2_INT_CNTL |
18000 | #define CP_ME1_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc |
18001 | #define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd |
18002 | #define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe |
18003 | #define CP_ME1_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf |
18004 | #define CP_ME1_PIPE2_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 |
18005 | #define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 |
18006 | #define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 |
18007 | #define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 |
18008 | #define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a |
18009 | #define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b |
18010 | #define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d |
18011 | #define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e |
18012 | #define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f |
18013 | #define CP_ME1_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L |
18014 | #define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L |
18015 | #define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L |
18016 | #define CP_ME1_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L |
18017 | #define CP_ME1_PIPE2_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L |
18018 | #define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L |
18019 | #define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L |
18020 | #define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L |
18021 | #define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L |
18022 | #define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L |
18023 | #define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L |
18024 | #define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L |
18025 | #define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L |
18026 | //CP_ME1_PIPE3_INT_CNTL |
18027 | #define CP_ME1_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc |
18028 | #define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd |
18029 | #define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe |
18030 | #define CP_ME1_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf |
18031 | #define CP_ME1_PIPE3_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 |
18032 | #define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 |
18033 | #define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 |
18034 | #define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 |
18035 | #define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a |
18036 | #define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b |
18037 | #define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d |
18038 | #define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e |
18039 | #define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f |
18040 | #define CP_ME1_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L |
18041 | #define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L |
18042 | #define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L |
18043 | #define CP_ME1_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L |
18044 | #define CP_ME1_PIPE3_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L |
18045 | #define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L |
18046 | #define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L |
18047 | #define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L |
18048 | #define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L |
18049 | #define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L |
18050 | #define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L |
18051 | #define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L |
18052 | #define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L |
18053 | //CP_ME2_PIPE0_INT_CNTL |
18054 | #define CP_ME2_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc |
18055 | #define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd |
18056 | #define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe |
18057 | #define CP_ME2_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf |
18058 | #define CP_ME2_PIPE0_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 |
18059 | #define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 |
18060 | #define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 |
18061 | #define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 |
18062 | #define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a |
18063 | #define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b |
18064 | #define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d |
18065 | #define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e |
18066 | #define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f |
18067 | #define CP_ME2_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L |
18068 | #define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L |
18069 | #define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L |
18070 | #define CP_ME2_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L |
18071 | #define CP_ME2_PIPE0_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L |
18072 | #define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L |
18073 | #define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L |
18074 | #define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L |
18075 | #define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L |
18076 | #define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L |
18077 | #define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L |
18078 | #define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L |
18079 | #define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L |
18080 | //CP_ME2_PIPE1_INT_CNTL |
18081 | #define CP_ME2_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc |
18082 | #define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd |
18083 | #define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe |
18084 | #define CP_ME2_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf |
18085 | #define CP_ME2_PIPE1_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 |
18086 | #define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 |
18087 | #define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 |
18088 | #define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 |
18089 | #define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a |
18090 | #define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b |
18091 | #define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d |
18092 | #define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e |
18093 | #define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f |
18094 | #define CP_ME2_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L |
18095 | #define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L |
18096 | #define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L |
18097 | #define CP_ME2_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L |
18098 | #define CP_ME2_PIPE1_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L |
18099 | #define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L |
18100 | #define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L |
18101 | #define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L |
18102 | #define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L |
18103 | #define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L |
18104 | #define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L |
18105 | #define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L |
18106 | #define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L |
18107 | //CP_ME2_PIPE2_INT_CNTL |
18108 | #define CP_ME2_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc |
18109 | #define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd |
18110 | #define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe |
18111 | #define CP_ME2_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf |
18112 | #define CP_ME2_PIPE2_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 |
18113 | #define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 |
18114 | #define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 |
18115 | #define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 |
18116 | #define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a |
18117 | #define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b |
18118 | #define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d |
18119 | #define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e |
18120 | #define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f |
18121 | #define CP_ME2_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L |
18122 | #define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L |
18123 | #define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L |
18124 | #define CP_ME2_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L |
18125 | #define CP_ME2_PIPE2_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L |
18126 | #define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L |
18127 | #define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L |
18128 | #define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L |
18129 | #define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L |
18130 | #define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L |
18131 | #define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L |
18132 | #define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L |
18133 | #define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L |
18134 | //CP_ME2_PIPE3_INT_CNTL |
18135 | #define CP_ME2_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc |
18136 | #define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd |
18137 | #define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe |
18138 | #define CP_ME2_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf |
18139 | #define CP_ME2_PIPE3_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 |
18140 | #define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 |
18141 | #define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 |
18142 | #define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 |
18143 | #define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a |
18144 | #define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b |
18145 | #define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d |
18146 | #define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e |
18147 | #define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f |
18148 | #define CP_ME2_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L |
18149 | #define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L |
18150 | #define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L |
18151 | #define CP_ME2_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L |
18152 | #define CP_ME2_PIPE3_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L |
18153 | #define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L |
18154 | #define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L |
18155 | #define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L |
18156 | #define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L |
18157 | #define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L |
18158 | #define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L |
18159 | #define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L |
18160 | #define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L |
18161 | //CP_ME1_PIPE0_INT_STATUS |
18162 | #define CP_ME1_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc |
18163 | #define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd |
18164 | #define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe |
18165 | #define CP_ME1_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf |
18166 | #define CP_ME1_PIPE0_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 |
18167 | #define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 |
18168 | #define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 |
18169 | #define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 |
18170 | #define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a |
18171 | #define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b |
18172 | #define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d |
18173 | #define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e |
18174 | #define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f |
18175 | #define CP_ME1_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L |
18176 | #define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L |
18177 | #define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L |
18178 | #define CP_ME1_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L |
18179 | #define CP_ME1_PIPE0_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L |
18180 | #define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L |
18181 | #define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L |
18182 | #define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L |
18183 | #define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L |
18184 | #define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L |
18185 | #define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L |
18186 | #define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L |
18187 | #define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L |
18188 | //CP_ME1_PIPE1_INT_STATUS |
18189 | #define CP_ME1_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc |
18190 | #define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd |
18191 | #define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe |
18192 | #define CP_ME1_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf |
18193 | #define CP_ME1_PIPE1_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 |
18194 | #define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 |
18195 | #define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 |
18196 | #define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 |
18197 | #define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a |
18198 | #define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b |
18199 | #define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d |
18200 | #define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e |
18201 | #define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f |
18202 | #define CP_ME1_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L |
18203 | #define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L |
18204 | #define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L |
18205 | #define CP_ME1_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L |
18206 | #define CP_ME1_PIPE1_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L |
18207 | #define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L |
18208 | #define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L |
18209 | #define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L |
18210 | #define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L |
18211 | #define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L |
18212 | #define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L |
18213 | #define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L |
18214 | #define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L |
18215 | //CP_ME1_PIPE2_INT_STATUS |
18216 | #define CP_ME1_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc |
18217 | #define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd |
18218 | #define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe |
18219 | #define CP_ME1_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf |
18220 | #define CP_ME1_PIPE2_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 |
18221 | #define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 |
18222 | #define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 |
18223 | #define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 |
18224 | #define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a |
18225 | #define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b |
18226 | #define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d |
18227 | #define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e |
18228 | #define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f |
18229 | #define CP_ME1_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L |
18230 | #define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L |
18231 | #define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L |
18232 | #define CP_ME1_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L |
18233 | #define CP_ME1_PIPE2_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L |
18234 | #define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L |
18235 | #define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L |
18236 | #define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L |
18237 | #define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L |
18238 | #define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L |
18239 | #define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L |
18240 | #define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L |
18241 | #define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L |
18242 | //CP_ME1_PIPE3_INT_STATUS |
18243 | #define CP_ME1_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc |
18244 | #define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd |
18245 | #define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe |
18246 | #define CP_ME1_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf |
18247 | #define CP_ME1_PIPE3_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 |
18248 | #define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 |
18249 | #define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 |
18250 | #define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 |
18251 | #define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a |
18252 | #define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b |
18253 | #define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d |
18254 | #define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e |
18255 | #define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f |
18256 | #define CP_ME1_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L |
18257 | #define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L |
18258 | #define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L |
18259 | #define CP_ME1_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L |
18260 | #define CP_ME1_PIPE3_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L |
18261 | #define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L |
18262 | #define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L |
18263 | #define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L |
18264 | #define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L |
18265 | #define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L |
18266 | #define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L |
18267 | #define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L |
18268 | #define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L |
18269 | //CP_ME2_PIPE0_INT_STATUS |
18270 | #define CP_ME2_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc |
18271 | #define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd |
18272 | #define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe |
18273 | #define CP_ME2_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf |
18274 | #define CP_ME2_PIPE0_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 |
18275 | #define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 |
18276 | #define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 |
18277 | #define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 |
18278 | #define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a |
18279 | #define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b |
18280 | #define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d |
18281 | #define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e |
18282 | #define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f |
18283 | #define CP_ME2_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L |
18284 | #define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L |
18285 | #define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L |
18286 | #define CP_ME2_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L |
18287 | #define CP_ME2_PIPE0_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L |
18288 | #define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L |
18289 | #define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L |
18290 | #define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L |
18291 | #define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L |
18292 | #define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L |
18293 | #define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L |
18294 | #define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L |
18295 | #define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L |
18296 | //CP_ME2_PIPE1_INT_STATUS |
18297 | #define CP_ME2_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc |
18298 | #define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd |
18299 | #define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe |
18300 | #define CP_ME2_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf |
18301 | #define CP_ME2_PIPE1_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 |
18302 | #define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 |
18303 | #define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 |
18304 | #define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 |
18305 | #define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a |
18306 | #define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b |
18307 | #define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d |
18308 | #define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e |
18309 | #define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f |
18310 | #define CP_ME2_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L |
18311 | #define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L |
18312 | #define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L |
18313 | #define CP_ME2_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L |
18314 | #define CP_ME2_PIPE1_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L |
18315 | #define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L |
18316 | #define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L |
18317 | #define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L |
18318 | #define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L |
18319 | #define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L |
18320 | #define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L |
18321 | #define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L |
18322 | #define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L |
18323 | //CP_ME2_PIPE2_INT_STATUS |
18324 | #define CP_ME2_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc |
18325 | #define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd |
18326 | #define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe |
18327 | #define CP_ME2_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf |
18328 | #define CP_ME2_PIPE2_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 |
18329 | #define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 |
18330 | #define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 |
18331 | #define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 |
18332 | #define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a |
18333 | #define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b |
18334 | #define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d |
18335 | #define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e |
18336 | #define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f |
18337 | #define CP_ME2_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L |
18338 | #define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L |
18339 | #define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L |
18340 | #define CP_ME2_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L |
18341 | #define CP_ME2_PIPE2_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L |
18342 | #define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L |
18343 | #define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L |
18344 | #define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L |
18345 | #define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L |
18346 | #define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L |
18347 | #define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L |
18348 | #define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L |
18349 | #define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L |
18350 | //CP_ME2_PIPE3_INT_STATUS |
18351 | #define CP_ME2_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc |
18352 | #define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd |
18353 | #define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe |
18354 | #define CP_ME2_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf |
18355 | #define CP_ME2_PIPE3_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 |
18356 | #define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 |
18357 | #define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 |
18358 | #define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 |
18359 | #define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a |
18360 | #define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b |
18361 | #define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d |
18362 | #define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e |
18363 | #define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f |
18364 | #define CP_ME2_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L |
18365 | #define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L |
18366 | #define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L |
18367 | #define CP_ME2_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L |
18368 | #define CP_ME2_PIPE3_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L |
18369 | #define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L |
18370 | #define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L |
18371 | #define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L |
18372 | #define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L |
18373 | #define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L |
18374 | #define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L |
18375 | #define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L |
18376 | #define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L |
18377 | //CP_ME1_INT_STAT_DEBUG |
18378 | #define CP_ME1_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED__SHIFT 0xc |
18379 | #define CP_ME1_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED__SHIFT 0xd |
18380 | #define CP_ME1_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0xe |
18381 | #define CP_ME1_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS__SHIFT 0xf |
18382 | #define CP_ME1_INT_STAT_DEBUG__GPF_INT_ASSERTED__SHIFT 0x10 |
18383 | #define CP_ME1_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x11 |
18384 | #define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17 |
18385 | #define CP_ME1_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x18 |
18386 | #define CP_ME1_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x1a |
18387 | #define CP_ME1_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x1b |
18388 | #define CP_ME1_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d |
18389 | #define CP_ME1_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x1e |
18390 | #define CP_ME1_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x1f |
18391 | #define CP_ME1_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED_MASK 0x00001000L |
18392 | #define CP_ME1_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED_MASK 0x00002000L |
18393 | #define CP_ME1_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x00004000L |
18394 | #define CP_ME1_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L |
18395 | #define CP_ME1_INT_STAT_DEBUG__GPF_INT_ASSERTED_MASK 0x00010000L |
18396 | #define CP_ME1_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x00020000L |
18397 | #define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x00800000L |
18398 | #define CP_ME1_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x01000000L |
18399 | #define CP_ME1_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x04000000L |
18400 | #define CP_ME1_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x08000000L |
18401 | #define CP_ME1_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000L |
18402 | #define CP_ME1_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000L |
18403 | #define CP_ME1_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000L |
18404 | //CP_ME2_INT_STAT_DEBUG |
18405 | #define CP_ME2_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED__SHIFT 0xc |
18406 | #define CP_ME2_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED__SHIFT 0xd |
18407 | #define CP_ME2_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0xe |
18408 | #define CP_ME2_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS__SHIFT 0xf |
18409 | #define CP_ME2_INT_STAT_DEBUG__GPF_INT_ASSERTED__SHIFT 0x10 |
18410 | #define CP_ME2_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x11 |
18411 | #define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17 |
18412 | #define CP_ME2_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x18 |
18413 | #define CP_ME2_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x1a |
18414 | #define CP_ME2_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x1b |
18415 | #define CP_ME2_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d |
18416 | #define CP_ME2_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x1e |
18417 | #define CP_ME2_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x1f |
18418 | #define CP_ME2_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED_MASK 0x00001000L |
18419 | #define CP_ME2_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED_MASK 0x00002000L |
18420 | #define CP_ME2_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x00004000L |
18421 | #define CP_ME2_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L |
18422 | #define CP_ME2_INT_STAT_DEBUG__GPF_INT_ASSERTED_MASK 0x00010000L |
18423 | #define CP_ME2_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x00020000L |
18424 | #define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x00800000L |
18425 | #define CP_ME2_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x01000000L |
18426 | #define CP_ME2_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x04000000L |
18427 | #define CP_ME2_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x08000000L |
18428 | #define CP_ME2_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000L |
18429 | #define CP_ME2_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000L |
18430 | #define CP_ME2_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000L |
18431 | //CP_GFX_QUEUE_INDEX |
18432 | #define CP_GFX_QUEUE_INDEX__QUEUE_ACCESS__SHIFT 0x0 |
18433 | #define CP_GFX_QUEUE_INDEX__PIPE_ID__SHIFT 0x4 |
18434 | #define CP_GFX_QUEUE_INDEX__QUEUE_ID__SHIFT 0x8 |
18435 | #define CP_GFX_QUEUE_INDEX__QUEUE_ACCESS_MASK 0x00000001L |
18436 | #define CP_GFX_QUEUE_INDEX__PIPE_ID_MASK 0x00000030L |
18437 | #define CP_GFX_QUEUE_INDEX__QUEUE_ID_MASK 0x00000700L |
18438 | //CC_GC_EDC_CONFIG |
18439 | #define CC_GC_EDC_CONFIG__WRITE_DIS__SHIFT 0x0 |
18440 | #define CC_GC_EDC_CONFIG__DIS_EDC__SHIFT 0x1 |
18441 | #define CC_GC_EDC_CONFIG__WRITE_DIS_MASK 0x00000001L |
18442 | #define CC_GC_EDC_CONFIG__DIS_EDC_MASK 0x00000002L |
18443 | //CP_ME1_PIPE_PRIORITY_CNTS |
18444 | #define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0 |
18445 | #define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8 |
18446 | #define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10 |
18447 | #define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18 |
18448 | #define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL |
18449 | #define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L |
18450 | #define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L |
18451 | #define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L |
18452 | //CP_ME1_PIPE0_PRIORITY |
18453 | #define CP_ME1_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0 |
18454 | #define CP_ME1_PIPE0_PRIORITY__PRIORITY_MASK 0x00000003L |
18455 | //CP_ME1_PIPE1_PRIORITY |
18456 | #define CP_ME1_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0 |
18457 | #define CP_ME1_PIPE1_PRIORITY__PRIORITY_MASK 0x00000003L |
18458 | //CP_ME1_PIPE2_PRIORITY |
18459 | #define CP_ME1_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0 |
18460 | #define CP_ME1_PIPE2_PRIORITY__PRIORITY_MASK 0x00000003L |
18461 | //CP_ME1_PIPE3_PRIORITY |
18462 | #define CP_ME1_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0 |
18463 | #define CP_ME1_PIPE3_PRIORITY__PRIORITY_MASK 0x00000003L |
18464 | //CP_ME2_PIPE_PRIORITY_CNTS |
18465 | #define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0 |
18466 | #define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8 |
18467 | #define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10 |
18468 | #define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18 |
18469 | #define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL |
18470 | #define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L |
18471 | #define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L |
18472 | #define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L |
18473 | //CP_ME2_PIPE0_PRIORITY |
18474 | #define CP_ME2_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0 |
18475 | #define CP_ME2_PIPE0_PRIORITY__PRIORITY_MASK 0x00000003L |
18476 | //CP_ME2_PIPE1_PRIORITY |
18477 | #define CP_ME2_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0 |
18478 | #define CP_ME2_PIPE1_PRIORITY__PRIORITY_MASK 0x00000003L |
18479 | //CP_ME2_PIPE2_PRIORITY |
18480 | #define CP_ME2_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0 |
18481 | #define CP_ME2_PIPE2_PRIORITY__PRIORITY_MASK 0x00000003L |
18482 | //CP_ME2_PIPE3_PRIORITY |
18483 | #define CP_ME2_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0 |
18484 | #define CP_ME2_PIPE3_PRIORITY__PRIORITY_MASK 0x00000003L |
18485 | //CP_PFP_PRGRM_CNTR_START |
18486 | #define CP_PFP_PRGRM_CNTR_START__IP_START__SHIFT 0x0 |
18487 | #define CP_PFP_PRGRM_CNTR_START__IP_START_MASK 0xFFFFFFFFL |
18488 | //CP_ME_PRGRM_CNTR_START |
18489 | #define CP_ME_PRGRM_CNTR_START__IP_START__SHIFT 0x0 |
18490 | #define CP_ME_PRGRM_CNTR_START__IP_START_MASK 0xFFFFFFFFL |
18491 | //CP_MEC1_PRGRM_CNTR_START |
18492 | #define CP_MEC1_PRGRM_CNTR_START__IP_START__SHIFT 0x0 |
18493 | #define CP_MEC1_PRGRM_CNTR_START__IP_START_MASK 0x000FFFFFL |
18494 | //CP_MEC2_PRGRM_CNTR_START |
18495 | #define CP_MEC2_PRGRM_CNTR_START__IP_START__SHIFT 0x0 |
18496 | #define CP_MEC2_PRGRM_CNTR_START__IP_START_MASK 0x000FFFFFL |
18497 | //CP_PFP_INTR_ROUTINE_START |
18498 | #define CP_PFP_INTR_ROUTINE_START__IR_START__SHIFT 0x0 |
18499 | #define CP_PFP_INTR_ROUTINE_START__IR_START_MASK 0xFFFFFFFFL |
18500 | //CP_ME_INTR_ROUTINE_START |
18501 | #define CP_ME_INTR_ROUTINE_START__IR_START__SHIFT 0x0 |
18502 | #define CP_ME_INTR_ROUTINE_START__IR_START_MASK 0xFFFFFFFFL |
18503 | //CP_MEC1_INTR_ROUTINE_START |
18504 | #define CP_MEC1_INTR_ROUTINE_START__IR_START__SHIFT 0x0 |
18505 | #define CP_MEC1_INTR_ROUTINE_START__IR_START_MASK 0x000FFFFFL |
18506 | //CP_MEC2_INTR_ROUTINE_START |
18507 | #define CP_MEC2_INTR_ROUTINE_START__IR_START__SHIFT 0x0 |
18508 | #define CP_MEC2_INTR_ROUTINE_START__IR_START_MASK 0x000FFFFFL |
18509 | //CP_CONTEXT_CNTL |
18510 | #define CP_CONTEXT_CNTL__ME0PIPE0_MAX_GE_CNTX__SHIFT 0x0 |
18511 | #define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX__SHIFT 0x4 |
18512 | #define CP_CONTEXT_CNTL__ME0PIPE1_MAX_GE_CNTX__SHIFT 0x10 |
18513 | #define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX__SHIFT 0x14 |
18514 | #define CP_CONTEXT_CNTL__ME0PIPE0_MAX_GE_CNTX_MASK 0x00000007L |
18515 | #define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX_MASK 0x00000070L |
18516 | #define CP_CONTEXT_CNTL__ME0PIPE1_MAX_GE_CNTX_MASK 0x00070000L |
18517 | #define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX_MASK 0x00700000L |
18518 | //CP_MAX_CONTEXT |
18519 | #define CP_MAX_CONTEXT__MAX_CONTEXT__SHIFT 0x0 |
18520 | #define CP_MAX_CONTEXT__MAX_CONTEXT_MASK 0x00000007L |
18521 | //CP_IQ_WAIT_TIME1 |
18522 | #define CP_IQ_WAIT_TIME1__IB_OFFLOAD__SHIFT 0x0 |
18523 | #define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD__SHIFT 0x8 |
18524 | #define CP_IQ_WAIT_TIME1__WRM_OFFLOAD__SHIFT 0x10 |
18525 | #define CP_IQ_WAIT_TIME1__GWS__SHIFT 0x18 |
18526 | #define CP_IQ_WAIT_TIME1__IB_OFFLOAD_MASK 0x000000FFL |
18527 | #define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD_MASK 0x0000FF00L |
18528 | #define CP_IQ_WAIT_TIME1__WRM_OFFLOAD_MASK 0x00FF0000L |
18529 | #define CP_IQ_WAIT_TIME1__GWS_MASK 0xFF000000L |
18530 | //CP_IQ_WAIT_TIME2 |
18531 | #define CP_IQ_WAIT_TIME2__QUE_SLEEP__SHIFT 0x0 |
18532 | #define CP_IQ_WAIT_TIME2__SCH_WAVE__SHIFT 0x8 |
18533 | #define CP_IQ_WAIT_TIME2__SEM_REARM__SHIFT 0x10 |
18534 | #define CP_IQ_WAIT_TIME2__DEQ_RETRY__SHIFT 0x18 |
18535 | #define CP_IQ_WAIT_TIME2__QUE_SLEEP_MASK 0x000000FFL |
18536 | #define CP_IQ_WAIT_TIME2__SCH_WAVE_MASK 0x0000FF00L |
18537 | #define CP_IQ_WAIT_TIME2__SEM_REARM_MASK 0x00FF0000L |
18538 | #define CP_IQ_WAIT_TIME2__DEQ_RETRY_MASK 0xFF000000L |
18539 | //CP_RB0_BASE_HI |
18540 | #define CP_RB0_BASE_HI__RB_BASE_HI__SHIFT 0x0 |
18541 | #define CP_RB0_BASE_HI__RB_BASE_HI_MASK 0x000000FFL |
18542 | //CP_RB1_BASE_HI |
18543 | #define CP_RB1_BASE_HI__RB_BASE_HI__SHIFT 0x0 |
18544 | #define CP_RB1_BASE_HI__RB_BASE_HI_MASK 0x000000FFL |
18545 | //CP_VMID_RESET |
18546 | #define CP_VMID_RESET__RESET_REQUEST__SHIFT 0x0 |
18547 | #define CP_VMID_RESET__PIPE0_QUEUES__SHIFT 0x10 |
18548 | #define CP_VMID_RESET__PIPE1_QUEUES__SHIFT 0x18 |
18549 | #define CP_VMID_RESET__RESET_REQUEST_MASK 0x0000FFFFL |
18550 | #define CP_VMID_RESET__PIPE0_QUEUES_MASK 0x00FF0000L |
18551 | #define CP_VMID_RESET__PIPE1_QUEUES_MASK 0xFF000000L |
18552 | //CPC_INT_CNTL |
18553 | #define CPC_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc |
18554 | #define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd |
18555 | #define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe |
18556 | #define CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf |
18557 | #define CPC_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 |
18558 | #define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 |
18559 | #define CPC_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 |
18560 | #define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 |
18561 | #define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a |
18562 | #define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b |
18563 | #define CPC_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d |
18564 | #define CPC_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e |
18565 | #define CPC_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f |
18566 | #define CPC_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L |
18567 | #define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L |
18568 | #define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L |
18569 | #define CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L |
18570 | #define CPC_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L |
18571 | #define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L |
18572 | #define CPC_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L |
18573 | #define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L |
18574 | #define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L |
18575 | #define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L |
18576 | #define CPC_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L |
18577 | #define CPC_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L |
18578 | #define CPC_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L |
18579 | //CPC_INT_STATUS |
18580 | #define CPC_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc |
18581 | #define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd |
18582 | #define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe |
18583 | #define CPC_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf |
18584 | #define CPC_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 |
18585 | #define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 |
18586 | #define CPC_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 |
18587 | #define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 |
18588 | #define CPC_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a |
18589 | #define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b |
18590 | #define CPC_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d |
18591 | #define CPC_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e |
18592 | #define CPC_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f |
18593 | #define CPC_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L |
18594 | #define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L |
18595 | #define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L |
18596 | #define CPC_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L |
18597 | #define CPC_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L |
18598 | #define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L |
18599 | #define CPC_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L |
18600 | #define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L |
18601 | #define CPC_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L |
18602 | #define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L |
18603 | #define CPC_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L |
18604 | #define CPC_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L |
18605 | #define CPC_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L |
18606 | //CP_VMID_PREEMPT |
18607 | #define CP_VMID_PREEMPT__PREEMPT_REQUEST__SHIFT 0x0 |
18608 | #define CP_VMID_PREEMPT__VIRT_COMMAND__SHIFT 0x10 |
18609 | #define CP_VMID_PREEMPT__PREEMPT_REQUEST_MASK 0x0000FFFFL |
18610 | #define CP_VMID_PREEMPT__VIRT_COMMAND_MASK 0x000F0000L |
18611 | //CPC_INT_CNTX_ID |
18612 | #define CPC_INT_CNTX_ID__CNTX_ID__SHIFT 0x0 |
18613 | #define CPC_INT_CNTX_ID__CNTX_ID_MASK 0xFFFFFFFFL |
18614 | //CP_PQ_STATUS |
18615 | #define CP_PQ_STATUS__DOORBELL_UPDATED__SHIFT 0x0 |
18616 | #define CP_PQ_STATUS__DOORBELL_ENABLE__SHIFT 0x1 |
18617 | #define CP_PQ_STATUS__DOORBELL_UPDATED_EN__SHIFT 0x2 |
18618 | #define CP_PQ_STATUS__DOORBELL_UPDATED_MODE__SHIFT 0x3 |
18619 | #define CP_PQ_STATUS__DOORBELL_UPDATED_MASK 0x00000001L |
18620 | #define CP_PQ_STATUS__DOORBELL_ENABLE_MASK 0x00000002L |
18621 | #define CP_PQ_STATUS__DOORBELL_UPDATED_EN_MASK 0x00000004L |
18622 | #define CP_PQ_STATUS__DOORBELL_UPDATED_MODE_MASK 0x00000008L |
18623 | //CP_PFP_PRGRM_CNTR_START_HI |
18624 | #define CP_PFP_PRGRM_CNTR_START_HI__IP_START__SHIFT 0x0 |
18625 | #define CP_PFP_PRGRM_CNTR_START_HI__IP_START_MASK 0x3FFFFFFFL |
18626 | //CP_MAX_DRAW_COUNT |
18627 | #define CP_MAX_DRAW_COUNT__MAX_DRAW_COUNT__SHIFT 0x0 |
18628 | #define CP_MAX_DRAW_COUNT__MAX_DRAW_COUNT_MASK 0xFFFFFFFFL |
18629 | //CP_MEC1_F32_INT_DIS |
18630 | #define CP_MEC1_F32_INT_DIS__EDC_ROQ_FED_INT__SHIFT 0x0 |
18631 | #define CP_MEC1_F32_INT_DIS__PRIV_REG_INT__SHIFT 0x1 |
18632 | #define CP_MEC1_F32_INT_DIS__RESERVED_BIT_ERR_INT__SHIFT 0x2 |
18633 | #define CP_MEC1_F32_INT_DIS__EDC_TC_FED_INT__SHIFT 0x3 |
18634 | #define CP_MEC1_F32_INT_DIS__EDC_GDS_FED_INT__SHIFT 0x4 |
18635 | #define CP_MEC1_F32_INT_DIS__EDC_SCRATCH_FED_INT__SHIFT 0x5 |
18636 | #define CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT 0x6 |
18637 | #define CP_MEC1_F32_INT_DIS__SUA_VIOLATION_INT__SHIFT 0x7 |
18638 | #define CP_MEC1_F32_INT_DIS__EDC_DMA_FED_INT__SHIFT 0x8 |
18639 | #define CP_MEC1_F32_INT_DIS__IQ_TIMER_INT__SHIFT 0x9 |
18640 | #define CP_MEC1_F32_INT_DIS__GPF_INT_CPF__SHIFT 0xa |
18641 | #define CP_MEC1_F32_INT_DIS__GPF_INT_DMA__SHIFT 0xb |
18642 | #define CP_MEC1_F32_INT_DIS__GPF_INT_CPC__SHIFT 0xc |
18643 | #define CP_MEC1_F32_INT_DIS__EDC_SR_MEM_FED_INT__SHIFT 0xd |
18644 | #define CP_MEC1_F32_INT_DIS__QUEUE_MESSAGE_INT__SHIFT 0xe |
18645 | #define CP_MEC1_F32_INT_DIS__FATAL_EDC_ERROR_INT__SHIFT 0xf |
18646 | #define CP_MEC1_F32_INT_DIS__EDC_ROQ_FED_INT_MASK 0x00000001L |
18647 | #define CP_MEC1_F32_INT_DIS__PRIV_REG_INT_MASK 0x00000002L |
18648 | #define CP_MEC1_F32_INT_DIS__RESERVED_BIT_ERR_INT_MASK 0x00000004L |
18649 | #define CP_MEC1_F32_INT_DIS__EDC_TC_FED_INT_MASK 0x00000008L |
18650 | #define CP_MEC1_F32_INT_DIS__EDC_GDS_FED_INT_MASK 0x00000010L |
18651 | #define CP_MEC1_F32_INT_DIS__EDC_SCRATCH_FED_INT_MASK 0x00000020L |
18652 | #define CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT_MASK 0x00000040L |
18653 | #define CP_MEC1_F32_INT_DIS__SUA_VIOLATION_INT_MASK 0x00000080L |
18654 | #define CP_MEC1_F32_INT_DIS__EDC_DMA_FED_INT_MASK 0x00000100L |
18655 | #define CP_MEC1_F32_INT_DIS__IQ_TIMER_INT_MASK 0x00000200L |
18656 | #define CP_MEC1_F32_INT_DIS__GPF_INT_CPF_MASK 0x00000400L |
18657 | #define CP_MEC1_F32_INT_DIS__GPF_INT_DMA_MASK 0x00000800L |
18658 | #define CP_MEC1_F32_INT_DIS__GPF_INT_CPC_MASK 0x00001000L |
18659 | #define CP_MEC1_F32_INT_DIS__EDC_SR_MEM_FED_INT_MASK 0x00002000L |
18660 | #define CP_MEC1_F32_INT_DIS__QUEUE_MESSAGE_INT_MASK 0x00004000L |
18661 | #define CP_MEC1_F32_INT_DIS__FATAL_EDC_ERROR_INT_MASK 0x00008000L |
18662 | //CP_MEC2_F32_INT_DIS |
18663 | #define CP_MEC2_F32_INT_DIS__EDC_ROQ_FED_INT__SHIFT 0x0 |
18664 | #define CP_MEC2_F32_INT_DIS__PRIV_REG_INT__SHIFT 0x1 |
18665 | #define CP_MEC2_F32_INT_DIS__RESERVED_BIT_ERR_INT__SHIFT 0x2 |
18666 | #define CP_MEC2_F32_INT_DIS__EDC_TC_FED_INT__SHIFT 0x3 |
18667 | #define CP_MEC2_F32_INT_DIS__EDC_GDS_FED_INT__SHIFT 0x4 |
18668 | #define CP_MEC2_F32_INT_DIS__EDC_SCRATCH_FED_INT__SHIFT 0x5 |
18669 | #define CP_MEC2_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT 0x6 |
18670 | #define CP_MEC2_F32_INT_DIS__SUA_VIOLATION_INT__SHIFT 0x7 |
18671 | #define CP_MEC2_F32_INT_DIS__EDC_DMA_FED_INT__SHIFT 0x8 |
18672 | #define CP_MEC2_F32_INT_DIS__IQ_TIMER_INT__SHIFT 0x9 |
18673 | #define CP_MEC2_F32_INT_DIS__GPF_INT_CPF__SHIFT 0xa |
18674 | #define CP_MEC2_F32_INT_DIS__GPF_INT_DMA__SHIFT 0xb |
18675 | #define CP_MEC2_F32_INT_DIS__GPF_INT_CPC__SHIFT 0xc |
18676 | #define CP_MEC2_F32_INT_DIS__EDC_SR_MEM_FED_INT__SHIFT 0xd |
18677 | #define CP_MEC2_F32_INT_DIS__QUEUE_MESSAGE_INT__SHIFT 0xe |
18678 | #define CP_MEC2_F32_INT_DIS__FATAL_EDC_ERROR_INT__SHIFT 0xf |
18679 | #define CP_MEC2_F32_INT_DIS__EDC_ROQ_FED_INT_MASK 0x00000001L |
18680 | #define CP_MEC2_F32_INT_DIS__PRIV_REG_INT_MASK 0x00000002L |
18681 | #define CP_MEC2_F32_INT_DIS__RESERVED_BIT_ERR_INT_MASK 0x00000004L |
18682 | #define CP_MEC2_F32_INT_DIS__EDC_TC_FED_INT_MASK 0x00000008L |
18683 | #define CP_MEC2_F32_INT_DIS__EDC_GDS_FED_INT_MASK 0x00000010L |
18684 | #define CP_MEC2_F32_INT_DIS__EDC_SCRATCH_FED_INT_MASK 0x00000020L |
18685 | #define CP_MEC2_F32_INT_DIS__WAVE_RESTORE_INT_MASK 0x00000040L |
18686 | #define CP_MEC2_F32_INT_DIS__SUA_VIOLATION_INT_MASK 0x00000080L |
18687 | #define CP_MEC2_F32_INT_DIS__EDC_DMA_FED_INT_MASK 0x00000100L |
18688 | #define CP_MEC2_F32_INT_DIS__IQ_TIMER_INT_MASK 0x00000200L |
18689 | #define CP_MEC2_F32_INT_DIS__GPF_INT_CPF_MASK 0x00000400L |
18690 | #define CP_MEC2_F32_INT_DIS__GPF_INT_DMA_MASK 0x00000800L |
18691 | #define CP_MEC2_F32_INT_DIS__GPF_INT_CPC_MASK 0x00001000L |
18692 | #define CP_MEC2_F32_INT_DIS__EDC_SR_MEM_FED_INT_MASK 0x00002000L |
18693 | #define CP_MEC2_F32_INT_DIS__QUEUE_MESSAGE_INT_MASK 0x00004000L |
18694 | #define CP_MEC2_F32_INT_DIS__FATAL_EDC_ERROR_INT_MASK 0x00008000L |
18695 | //CP_VMID_STATUS |
18696 | #define CP_VMID_STATUS__PREEMPT_DE_STATUS__SHIFT 0x0 |
18697 | #define CP_VMID_STATUS__PREEMPT_CE_STATUS__SHIFT 0x10 |
18698 | #define CP_VMID_STATUS__PREEMPT_DE_STATUS_MASK 0x0000FFFFL |
18699 | #define CP_VMID_STATUS__PREEMPT_CE_STATUS_MASK 0xFFFF0000L |
18700 | //CPC_SUSPEND_CTX_SAVE_BASE_ADDR_LO |
18701 | #define CPC_SUSPEND_CTX_SAVE_BASE_ADDR_LO__ADDR__SHIFT 0xc |
18702 | #define CPC_SUSPEND_CTX_SAVE_BASE_ADDR_LO__ADDR_MASK 0xFFFFF000L |
18703 | //CPC_SUSPEND_CTX_SAVE_BASE_ADDR_HI |
18704 | #define CPC_SUSPEND_CTX_SAVE_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0 |
18705 | #define CPC_SUSPEND_CTX_SAVE_BASE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL |
18706 | //CPC_SUSPEND_CTX_SAVE_CONTROL |
18707 | #define CPC_SUSPEND_CTX_SAVE_CONTROL__POLICY__SHIFT 0x3 |
18708 | #define CPC_SUSPEND_CTX_SAVE_CONTROL__EXE_DISABLE__SHIFT 0x17 |
18709 | #define CPC_SUSPEND_CTX_SAVE_CONTROL__POLICY_MASK 0x00000018L |
18710 | #define CPC_SUSPEND_CTX_SAVE_CONTROL__EXE_DISABLE_MASK 0x00800000L |
18711 | //CPC_SUSPEND_CNTL_STACK_OFFSET |
18712 | #define CPC_SUSPEND_CNTL_STACK_OFFSET__OFFSET__SHIFT 0x2 |
18713 | #define CPC_SUSPEND_CNTL_STACK_OFFSET__OFFSET_MASK 0x0000FFFCL |
18714 | //CPC_SUSPEND_CNTL_STACK_SIZE |
18715 | #define CPC_SUSPEND_CNTL_STACK_SIZE__SIZE__SHIFT 0xc |
18716 | #define CPC_SUSPEND_CNTL_STACK_SIZE__SIZE_MASK 0x0000F000L |
18717 | //CPC_SUSPEND_WG_STATE_OFFSET |
18718 | #define CPC_SUSPEND_WG_STATE_OFFSET__OFFSET__SHIFT 0x2 |
18719 | #define CPC_SUSPEND_WG_STATE_OFFSET__OFFSET_MASK 0x03FFFFFCL |
18720 | //CPC_SUSPEND_CTX_SAVE_SIZE |
18721 | #define CPC_SUSPEND_CTX_SAVE_SIZE__SIZE__SHIFT 0xc |
18722 | #define CPC_SUSPEND_CTX_SAVE_SIZE__SIZE_MASK 0x03FFF000L |
18723 | //CPC_OS_PIPES |
18724 | #define CPC_OS_PIPES__OS_PIPES__SHIFT 0x0 |
18725 | #define CPC_OS_PIPES__OS_PIPES_MASK 0x000000FFL |
18726 | //CP_SUSPEND_RESUME_REQ |
18727 | #define CP_SUSPEND_RESUME_REQ__SUSPEND_REQ__SHIFT 0x0 |
18728 | #define CP_SUSPEND_RESUME_REQ__RESUME_REQ__SHIFT 0x1 |
18729 | #define CP_SUSPEND_RESUME_REQ__SUSPEND_REQ_MASK 0x00000001L |
18730 | #define CP_SUSPEND_RESUME_REQ__RESUME_REQ_MASK 0x00000002L |
18731 | //CP_SUSPEND_CNTL |
18732 | #define CP_SUSPEND_CNTL__SUSPEND_MODE__SHIFT 0x0 |
18733 | #define CP_SUSPEND_CNTL__SUSPEND_ENABLE__SHIFT 0x1 |
18734 | #define CP_SUSPEND_CNTL__RESUME_LOCK__SHIFT 0x2 |
18735 | #define CP_SUSPEND_CNTL__ACE_SUSPEND_ACTIVE__SHIFT 0x3 |
18736 | #define CP_SUSPEND_CNTL__SUSPEND_MODE_MASK 0x00000001L |
18737 | #define CP_SUSPEND_CNTL__SUSPEND_ENABLE_MASK 0x00000002L |
18738 | #define CP_SUSPEND_CNTL__RESUME_LOCK_MASK 0x00000004L |
18739 | #define CP_SUSPEND_CNTL__ACE_SUSPEND_ACTIVE_MASK 0x00000008L |
18740 | //CP_IQ_WAIT_TIME3 |
18741 | #define CP_IQ_WAIT_TIME3__SUSPEND_QUE__SHIFT 0x0 |
18742 | #define CP_IQ_WAIT_TIME3__SUSPEND_QUE_MASK 0x000000FFL |
18743 | //CPC_DDID_BASE_ADDR_LO |
18744 | #define CPC_DDID_BASE_ADDR_LO__BASE_ADDR_LO__SHIFT 0x6 |
18745 | #define CPC_DDID_BASE_ADDR_LO__BASE_ADDR_LO_MASK 0xFFFFFFC0L |
18746 | //CP_DDID_BASE_ADDR_LO |
18747 | #define CP_DDID_BASE_ADDR_LO__BASE_ADDR_LO__SHIFT 0x6 |
18748 | #define CP_DDID_BASE_ADDR_LO__BASE_ADDR_LO_MASK 0xFFFFFFC0L |
18749 | //CPC_DDID_BASE_ADDR_HI |
18750 | #define CPC_DDID_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 |
18751 | #define CPC_DDID_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0x0000FFFFL |
18752 | //CP_DDID_BASE_ADDR_HI |
18753 | #define CP_DDID_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 |
18754 | #define CP_DDID_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0x0000FFFFL |
18755 | //CPC_DDID_CNTL |
18756 | #define CPC_DDID_CNTL__THRESHOLD__SHIFT 0x0 |
18757 | #define CPC_DDID_CNTL__SIZE__SHIFT 0x10 |
18758 | #define CPC_DDID_CNTL__NO_RING_MEMORY__SHIFT 0x13 |
18759 | #define CPC_DDID_CNTL__POLICY__SHIFT 0x1c |
18760 | #define CPC_DDID_CNTL__MODE__SHIFT 0x1e |
18761 | #define CPC_DDID_CNTL__ENABLE__SHIFT 0x1f |
18762 | #define CPC_DDID_CNTL__THRESHOLD_MASK 0x000000FFL |
18763 | #define CPC_DDID_CNTL__SIZE_MASK 0x00010000L |
18764 | #define CPC_DDID_CNTL__NO_RING_MEMORY_MASK 0x00080000L |
18765 | #define CPC_DDID_CNTL__POLICY_MASK 0x30000000L |
18766 | #define CPC_DDID_CNTL__MODE_MASK 0x40000000L |
18767 | #define CPC_DDID_CNTL__ENABLE_MASK 0x80000000L |
18768 | //CP_DDID_CNTL |
18769 | #define CP_DDID_CNTL__THRESHOLD__SHIFT 0x0 |
18770 | #define CP_DDID_CNTL__SIZE__SHIFT 0x10 |
18771 | #define CP_DDID_CNTL__NO_RING_MEMORY__SHIFT 0x13 |
18772 | #define CP_DDID_CNTL__VMID__SHIFT 0x14 |
18773 | #define CP_DDID_CNTL__VMID_SEL__SHIFT 0x18 |
18774 | #define CP_DDID_CNTL__POLICY__SHIFT 0x1c |
18775 | #define CP_DDID_CNTL__MODE__SHIFT 0x1e |
18776 | #define CP_DDID_CNTL__ENABLE__SHIFT 0x1f |
18777 | #define CP_DDID_CNTL__THRESHOLD_MASK 0x000000FFL |
18778 | #define CP_DDID_CNTL__SIZE_MASK 0x00010000L |
18779 | #define CP_DDID_CNTL__NO_RING_MEMORY_MASK 0x00080000L |
18780 | #define CP_DDID_CNTL__VMID_MASK 0x00F00000L |
18781 | #define CP_DDID_CNTL__VMID_SEL_MASK 0x01000000L |
18782 | #define CP_DDID_CNTL__POLICY_MASK 0x30000000L |
18783 | #define CP_DDID_CNTL__MODE_MASK 0x40000000L |
18784 | #define CP_DDID_CNTL__ENABLE_MASK 0x80000000L |
18785 | //CP_GFX_DDID_INFLIGHT_COUNT |
18786 | #define CP_GFX_DDID_INFLIGHT_COUNT__COUNT__SHIFT 0x0 |
18787 | #define CP_GFX_DDID_INFLIGHT_COUNT__COUNT_MASK 0x0000FFFFL |
18788 | //CP_GFX_DDID_WPTR |
18789 | #define CP_GFX_DDID_WPTR__COUNT__SHIFT 0x0 |
18790 | #define CP_GFX_DDID_WPTR__COUNT_MASK 0x0000FFFFL |
18791 | //CP_GFX_DDID_RPTR |
18792 | #define CP_GFX_DDID_RPTR__COUNT__SHIFT 0x0 |
18793 | #define CP_GFX_DDID_RPTR__COUNT_MASK 0x0000FFFFL |
18794 | //CP_GFX_DDID_DELTA_RPT_COUNT |
18795 | #define CP_GFX_DDID_DELTA_RPT_COUNT__COUNT__SHIFT 0x0 |
18796 | #define CP_GFX_DDID_DELTA_RPT_COUNT__COUNT_MASK 0x000000FFL |
18797 | //CP_GFX_HPD_STATUS0 |
18798 | #define CP_GFX_HPD_STATUS0__QUEUE_STATE__SHIFT 0x0 |
18799 | #define CP_GFX_HPD_STATUS0__MAPPED_QUEUE__SHIFT 0x5 |
18800 | #define CP_GFX_HPD_STATUS0__QUEUE_AVAILABLE__SHIFT 0x8 |
18801 | #define CP_GFX_HPD_STATUS0__FORCE_MAPPED_QUEUE__SHIFT 0x10 |
18802 | #define CP_GFX_HPD_STATUS0__FORCE_QUEUE_STATE__SHIFT 0x14 |
18803 | #define CP_GFX_HPD_STATUS0__SUSPEND_REQ__SHIFT 0x1c |
18804 | #define CP_GFX_HPD_STATUS0__ENABLE_OVERIDE_QUEUEID__SHIFT 0x1d |
18805 | #define CP_GFX_HPD_STATUS0__OVERIDE_QUEUEID__SHIFT 0x1e |
18806 | #define CP_GFX_HPD_STATUS0__FORCE_QUEUE__SHIFT 0x1f |
18807 | #define CP_GFX_HPD_STATUS0__QUEUE_STATE_MASK 0x0000001FL |
18808 | #define CP_GFX_HPD_STATUS0__MAPPED_QUEUE_MASK 0x000000E0L |
18809 | #define CP_GFX_HPD_STATUS0__QUEUE_AVAILABLE_MASK 0x0000FF00L |
18810 | #define CP_GFX_HPD_STATUS0__FORCE_MAPPED_QUEUE_MASK 0x00070000L |
18811 | #define CP_GFX_HPD_STATUS0__FORCE_QUEUE_STATE_MASK 0x01F00000L |
18812 | #define CP_GFX_HPD_STATUS0__SUSPEND_REQ_MASK 0x10000000L |
18813 | #define CP_GFX_HPD_STATUS0__ENABLE_OVERIDE_QUEUEID_MASK 0x20000000L |
18814 | #define CP_GFX_HPD_STATUS0__OVERIDE_QUEUEID_MASK 0x40000000L |
18815 | #define CP_GFX_HPD_STATUS0__FORCE_QUEUE_MASK 0x80000000L |
18816 | //CP_GFX_HPD_CONTROL0 |
18817 | #define CP_GFX_HPD_CONTROL0__SUSPEND_ENABLE__SHIFT 0x0 |
18818 | #define CP_GFX_HPD_CONTROL0__PIPE_HOLDING__SHIFT 0x4 |
18819 | #define CP_GFX_HPD_CONTROL0__RB_CE_ROQ_CNTL__SHIFT 0x8 |
18820 | #define CP_GFX_HPD_CONTROL0__SUSPEND_ENABLE_MASK 0x00000001L |
18821 | #define CP_GFX_HPD_CONTROL0__PIPE_HOLDING_MASK 0x00000010L |
18822 | #define CP_GFX_HPD_CONTROL0__RB_CE_ROQ_CNTL_MASK 0x00000100L |
18823 | //CP_GFX_HPD_OSPRE_FENCE_ADDR_LO |
18824 | #define CP_GFX_HPD_OSPRE_FENCE_ADDR_LO__ADDR_LO__SHIFT 0x2 |
18825 | #define CP_GFX_HPD_OSPRE_FENCE_ADDR_LO__ADDR_LO_MASK 0xFFFFFFFCL |
18826 | //CP_GFX_HPD_OSPRE_FENCE_ADDR_HI |
18827 | #define CP_GFX_HPD_OSPRE_FENCE_ADDR_HI__ADDR_HI__SHIFT 0x0 |
18828 | #define CP_GFX_HPD_OSPRE_FENCE_ADDR_HI__RSVD__SHIFT 0x10 |
18829 | #define CP_GFX_HPD_OSPRE_FENCE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL |
18830 | #define CP_GFX_HPD_OSPRE_FENCE_ADDR_HI__RSVD_MASK 0xFFFF0000L |
18831 | //CP_GFX_HPD_OSPRE_FENCE_DATA_LO |
18832 | #define CP_GFX_HPD_OSPRE_FENCE_DATA_LO__DATA_LO__SHIFT 0x0 |
18833 | #define CP_GFX_HPD_OSPRE_FENCE_DATA_LO__DATA_LO_MASK 0xFFFFFFFFL |
18834 | //CP_GFX_HPD_OSPRE_FENCE_DATA_HI |
18835 | #define CP_GFX_HPD_OSPRE_FENCE_DATA_HI__DATA_HI__SHIFT 0x0 |
18836 | #define CP_GFX_HPD_OSPRE_FENCE_DATA_HI__DATA_HI_MASK 0xFFFFFFFFL |
18837 | //CP_GFX_INDEX_MUTEX |
18838 | #define CP_GFX_INDEX_MUTEX__REQUEST__SHIFT 0x0 |
18839 | #define CP_GFX_INDEX_MUTEX__CLIENTID__SHIFT 0x1 |
18840 | #define CP_GFX_INDEX_MUTEX__REQUEST_MASK 0x00000001L |
18841 | #define CP_GFX_INDEX_MUTEX__CLIENTID_MASK 0x0000000EL |
18842 | //CP_ME_PRGRM_CNTR_START_HI |
18843 | #define CP_ME_PRGRM_CNTR_START_HI__IP_START__SHIFT 0x0 |
18844 | #define CP_ME_PRGRM_CNTR_START_HI__IP_START_MASK 0x3FFFFFFFL |
18845 | //CP_PFP_INTR_ROUTINE_START_HI |
18846 | #define CP_PFP_INTR_ROUTINE_START_HI__IR_START__SHIFT 0x0 |
18847 | #define CP_PFP_INTR_ROUTINE_START_HI__IR_START_MASK 0x3FFFFFFFL |
18848 | //CP_ME_INTR_ROUTINE_START_HI |
18849 | #define CP_ME_INTR_ROUTINE_START_HI__IR_START__SHIFT 0x0 |
18850 | #define CP_ME_INTR_ROUTINE_START_HI__IR_START_MASK 0x3FFFFFFFL |
18851 | //CP_GFX_MQD_BASE_ADDR |
18852 | #define CP_GFX_MQD_BASE_ADDR__BASE_ADDR__SHIFT 0x2 |
18853 | #define CP_GFX_MQD_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFCL |
18854 | //CP_GFX_MQD_BASE_ADDR_HI |
18855 | #define CP_GFX_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 |
18856 | #define CP_GFX_MQD_BASE_ADDR_HI__APP_VMID__SHIFT 0x1c |
18857 | #define CP_GFX_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0x0000FFFFL |
18858 | #define CP_GFX_MQD_BASE_ADDR_HI__APP_VMID_MASK 0xF0000000L |
18859 | //CP_GFX_HQD_ACTIVE |
18860 | #define CP_GFX_HQD_ACTIVE__ACTIVE__SHIFT 0x0 |
18861 | #define CP_GFX_HQD_ACTIVE__ACTIVE_MASK 0x00000001L |
18862 | //CP_GFX_HQD_VMID |
18863 | #define CP_GFX_HQD_VMID__VMID__SHIFT 0x0 |
18864 | #define CP_GFX_HQD_VMID__VMID_MASK 0x0000000FL |
18865 | //CP_GFX_HQD_QUEUE_PRIORITY |
18866 | #define CP_GFX_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL__SHIFT 0x0 |
18867 | #define CP_GFX_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL_MASK 0x0000000FL |
18868 | //CP_GFX_HQD_QUANTUM |
18869 | #define CP_GFX_HQD_QUANTUM__QUANTUM_EN__SHIFT 0x0 |
18870 | #define CP_GFX_HQD_QUANTUM__QUANTUM_SCALE__SHIFT 0x3 |
18871 | #define CP_GFX_HQD_QUANTUM__QUANTUM_DURATION__SHIFT 0x8 |
18872 | #define CP_GFX_HQD_QUANTUM__QUANTUM_ACTIVE__SHIFT 0x1f |
18873 | #define CP_GFX_HQD_QUANTUM__QUANTUM_EN_MASK 0x00000001L |
18874 | #define CP_GFX_HQD_QUANTUM__QUANTUM_SCALE_MASK 0x00000018L |
18875 | #define CP_GFX_HQD_QUANTUM__QUANTUM_DURATION_MASK 0x0000FF00L |
18876 | #define CP_GFX_HQD_QUANTUM__QUANTUM_ACTIVE_MASK 0x80000000L |
18877 | //CP_GFX_HQD_BASE |
18878 | #define CP_GFX_HQD_BASE__RB_BASE__SHIFT 0x0 |
18879 | #define CP_GFX_HQD_BASE__RB_BASE_MASK 0xFFFFFFFFL |
18880 | //CP_GFX_HQD_BASE_HI |
18881 | #define CP_GFX_HQD_BASE_HI__RB_BASE_HI__SHIFT 0x0 |
18882 | #define CP_GFX_HQD_BASE_HI__RB_BASE_HI_MASK 0x000000FFL |
18883 | //CP_GFX_HQD_RPTR |
18884 | #define CP_GFX_HQD_RPTR__RB_RPTR__SHIFT 0x0 |
18885 | #define CP_GFX_HQD_RPTR__RB_RPTR_MASK 0x000FFFFFL |
18886 | //CP_GFX_HQD_RPTR_ADDR |
18887 | #define CP_GFX_HQD_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2 |
18888 | #define CP_GFX_HQD_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFCL |
18889 | //CP_GFX_HQD_RPTR_ADDR_HI |
18890 | #define CP_GFX_HQD_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0 |
18891 | #define CP_GFX_HQD_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL |
18892 | //CP_RB_WPTR_POLL_ADDR_LO |
18893 | #define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO__SHIFT 0x2 |
18894 | #define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO_MASK 0xFFFFFFFCL |
18895 | //CP_RB_WPTR_POLL_ADDR_HI |
18896 | #define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI__SHIFT 0x0 |
18897 | #define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI_MASK 0x0000FFFFL |
18898 | //CP_RB_DOORBELL_CONTROL |
18899 | #define CP_RB_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT 0x1 |
18900 | #define CP_RB_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x2 |
18901 | #define CP_RB_DOORBELL_CONTROL__DOORBELL_EN__SHIFT 0x1e |
18902 | #define CP_RB_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT 0x1f |
18903 | #define CP_RB_DOORBELL_CONTROL__DOORBELL_BIF_DROP_MASK 0x00000002L |
18904 | #define CP_RB_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x0FFFFFFCL |
18905 | #define CP_RB_DOORBELL_CONTROL__DOORBELL_EN_MASK 0x40000000L |
18906 | #define CP_RB_DOORBELL_CONTROL__DOORBELL_HIT_MASK 0x80000000L |
18907 | //CP_GFX_HQD_OFFSET |
18908 | #define CP_GFX_HQD_OFFSET__RB_OFFSET__SHIFT 0x0 |
18909 | #define CP_GFX_HQD_OFFSET__DISABLE_RB_OFFSET__SHIFT 0x1f |
18910 | #define CP_GFX_HQD_OFFSET__RB_OFFSET_MASK 0x000FFFFFL |
18911 | #define CP_GFX_HQD_OFFSET__DISABLE_RB_OFFSET_MASK 0x80000000L |
18912 | //CP_GFX_HQD_CNTL |
18913 | #define CP_GFX_HQD_CNTL__RB_BUFSZ__SHIFT 0x0 |
18914 | #define CP_GFX_HQD_CNTL__TMZ_STATE__SHIFT 0x6 |
18915 | #define CP_GFX_HQD_CNTL__TMZ_MATCH__SHIFT 0x7 |
18916 | #define CP_GFX_HQD_CNTL__RB_BLKSZ__SHIFT 0x8 |
18917 | #define CP_GFX_HQD_CNTL__RB_NON_PRIV__SHIFT 0xf |
18918 | #define CP_GFX_HQD_CNTL__BUF_SWAP__SHIFT 0x10 |
18919 | #define CP_GFX_HQD_CNTL__MIN_AVAILSZ__SHIFT 0x14 |
18920 | #define CP_GFX_HQD_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16 |
18921 | #define CP_GFX_HQD_CNTL__CACHE_POLICY__SHIFT 0x18 |
18922 | #define CP_GFX_HQD_CNTL__RB_VOLATILE__SHIFT 0x1a |
18923 | #define CP_GFX_HQD_CNTL__RB_NO_UPDATE__SHIFT 0x1b |
18924 | #define CP_GFX_HQD_CNTL__RB_EXE__SHIFT 0x1c |
18925 | #define CP_GFX_HQD_CNTL__KMD_QUEUE__SHIFT 0x1d |
18926 | #define CP_GFX_HQD_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f |
18927 | #define CP_GFX_HQD_CNTL__RB_BUFSZ_MASK 0x0000003FL |
18928 | #define CP_GFX_HQD_CNTL__TMZ_STATE_MASK 0x00000040L |
18929 | #define CP_GFX_HQD_CNTL__TMZ_MATCH_MASK 0x00000080L |
18930 | #define CP_GFX_HQD_CNTL__RB_BLKSZ_MASK 0x00003F00L |
18931 | #define CP_GFX_HQD_CNTL__RB_NON_PRIV_MASK 0x00008000L |
18932 | #define CP_GFX_HQD_CNTL__BUF_SWAP_MASK 0x00030000L |
18933 | #define CP_GFX_HQD_CNTL__MIN_AVAILSZ_MASK 0x00300000L |
18934 | #define CP_GFX_HQD_CNTL__MIN_IB_AVAILSZ_MASK 0x00C00000L |
18935 | #define CP_GFX_HQD_CNTL__CACHE_POLICY_MASK 0x03000000L |
18936 | #define CP_GFX_HQD_CNTL__RB_VOLATILE_MASK 0x04000000L |
18937 | #define CP_GFX_HQD_CNTL__RB_NO_UPDATE_MASK 0x08000000L |
18938 | #define CP_GFX_HQD_CNTL__RB_EXE_MASK 0x10000000L |
18939 | #define CP_GFX_HQD_CNTL__KMD_QUEUE_MASK 0x20000000L |
18940 | #define CP_GFX_HQD_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L |
18941 | //CP_GFX_HQD_CSMD_RPTR |
18942 | #define CP_GFX_HQD_CSMD_RPTR__RB_RPTR__SHIFT 0x0 |
18943 | #define CP_GFX_HQD_CSMD_RPTR__RB_RPTR_MASK 0x000FFFFFL |
18944 | //CP_GFX_HQD_WPTR |
18945 | #define CP_GFX_HQD_WPTR__RB_WPTR__SHIFT 0x0 |
18946 | #define CP_GFX_HQD_WPTR__RB_WPTR_MASK 0xFFFFFFFFL |
18947 | //CP_GFX_HQD_WPTR_HI |
18948 | #define CP_GFX_HQD_WPTR_HI__RB_WPTR__SHIFT 0x0 |
18949 | #define CP_GFX_HQD_WPTR_HI__RB_WPTR_MASK 0xFFFFFFFFL |
18950 | //CP_GFX_HQD_DEQUEUE_REQUEST |
18951 | #define CP_GFX_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ__SHIFT 0x0 |
18952 | #define CP_GFX_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND__SHIFT 0x4 |
18953 | #define CP_GFX_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN__SHIFT 0x9 |
18954 | #define CP_GFX_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN__SHIFT 0xa |
18955 | #define CP_GFX_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_MASK 0x00000001L |
18956 | #define CP_GFX_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK 0x00000010L |
18957 | #define CP_GFX_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN_MASK 0x00000200L |
18958 | #define CP_GFX_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN_MASK 0x00000400L |
18959 | //CP_GFX_HQD_MAPPED |
18960 | #define CP_GFX_HQD_MAPPED__MAPPED__SHIFT 0x0 |
18961 | #define CP_GFX_HQD_MAPPED__MAPPED_MASK 0x00000001L |
18962 | //CP_GFX_HQD_QUE_MGR_CONTROL |
18963 | #define CP_GFX_HQD_QUE_MGR_CONTROL__DISABLE_IDLE_QUEUE_DISCONNECT__SHIFT 0x0 |
18964 | #define CP_GFX_HQD_QUE_MGR_CONTROL__DISABLE_CONNECT_HANDSHAKE__SHIFT 0x4 |
18965 | #define CP_GFX_HQD_QUE_MGR_CONTROL__DISABLE_FETCHER_DISCONNECT__SHIFT 0x5 |
18966 | #define CP_GFX_HQD_QUE_MGR_CONTROL__FORCE_QUEUE_ACTIVE_EN__SHIFT 0x6 |
18967 | #define CP_GFX_HQD_QUE_MGR_CONTROL__FORCE_ALLOW_DB_UPDATE_EN__SHIFT 0x7 |
18968 | #define CP_GFX_HQD_QUE_MGR_CONTROL__FORCE_QUEUE__SHIFT 0x8 |
18969 | #define CP_GFX_HQD_QUE_MGR_CONTROL__DISABLE_OFFSET_UPDATE__SHIFT 0xb |
18970 | #define CP_GFX_HQD_QUE_MGR_CONTROL__PRIORITY_PREEMPT_DISABLE__SHIFT 0xd |
18971 | #define CP_GFX_HQD_QUE_MGR_CONTROL__DISABLE_QUEUE_MGR__SHIFT 0xf |
18972 | #define CP_GFX_HQD_QUE_MGR_CONTROL__ENABLE_IDLE_MESSAGE__SHIFT 0x10 |
18973 | #define CP_GFX_HQD_QUE_MGR_CONTROL__DISABLE_SWITCH_MESSAGE_IDLE__SHIFT 0x11 |
18974 | #define CP_GFX_HQD_QUE_MGR_CONTROL__ENABLE_SWITCH_MSG_PREEMPT__SHIFT 0x12 |
18975 | #define CP_GFX_HQD_QUE_MGR_CONTROL__DISABLE_MAPPED_QUEUE_IDLE_MSG__SHIFT 0x17 |
18976 | #define CP_GFX_HQD_QUE_MGR_CONTROL__DISABLE_IDLE_QUEUE_DISCONNECT_MASK 0x00000001L |
18977 | #define CP_GFX_HQD_QUE_MGR_CONTROL__DISABLE_CONNECT_HANDSHAKE_MASK 0x00000010L |
18978 | #define CP_GFX_HQD_QUE_MGR_CONTROL__DISABLE_FETCHER_DISCONNECT_MASK 0x00000020L |
18979 | #define CP_GFX_HQD_QUE_MGR_CONTROL__FORCE_QUEUE_ACTIVE_EN_MASK 0x00000040L |
18980 | #define CP_GFX_HQD_QUE_MGR_CONTROL__FORCE_ALLOW_DB_UPDATE_EN_MASK 0x00000080L |
18981 | #define CP_GFX_HQD_QUE_MGR_CONTROL__FORCE_QUEUE_MASK 0x00000700L |
18982 | #define CP_GFX_HQD_QUE_MGR_CONTROL__DISABLE_OFFSET_UPDATE_MASK 0x00000800L |
18983 | #define CP_GFX_HQD_QUE_MGR_CONTROL__PRIORITY_PREEMPT_DISABLE_MASK 0x00002000L |
18984 | #define CP_GFX_HQD_QUE_MGR_CONTROL__DISABLE_QUEUE_MGR_MASK 0x00008000L |
18985 | #define CP_GFX_HQD_QUE_MGR_CONTROL__ENABLE_IDLE_MESSAGE_MASK 0x00010000L |
18986 | #define CP_GFX_HQD_QUE_MGR_CONTROL__DISABLE_SWITCH_MESSAGE_IDLE_MASK 0x00020000L |
18987 | #define CP_GFX_HQD_QUE_MGR_CONTROL__ENABLE_SWITCH_MSG_PREEMPT_MASK 0x00040000L |
18988 | #define CP_GFX_HQD_QUE_MGR_CONTROL__DISABLE_MAPPED_QUEUE_IDLE_MSG_MASK 0x00800000L |
18989 | //CP_GFX_HQD_IQ_TIMER |
18990 | #define CP_GFX_HQD_IQ_TIMER__WAIT_TIME__SHIFT 0x0 |
18991 | #define CP_GFX_HQD_IQ_TIMER__RETRY_TYPE__SHIFT 0x8 |
18992 | #define CP_GFX_HQD_IQ_TIMER__IMMEDIATE_EXPIRE__SHIFT 0xb |
18993 | #define CP_GFX_HQD_IQ_TIMER__INTERRUPT_TYPE__SHIFT 0xc |
18994 | #define CP_GFX_HQD_IQ_TIMER__CLOCK_COUNT__SHIFT 0xe |
18995 | #define CP_GFX_HQD_IQ_TIMER__QUANTUM_TIMER__SHIFT 0x16 |
18996 | #define CP_GFX_HQD_IQ_TIMER__QUEUE_TYPE__SHIFT 0x1b |
18997 | #define CP_GFX_HQD_IQ_TIMER__REARM_TIMER__SHIFT 0x1c |
18998 | #define CP_GFX_HQD_IQ_TIMER__ACTIVE__SHIFT 0x1f |
18999 | #define CP_GFX_HQD_IQ_TIMER__WAIT_TIME_MASK 0x000000FFL |
19000 | #define CP_GFX_HQD_IQ_TIMER__RETRY_TYPE_MASK 0x00000700L |
19001 | #define CP_GFX_HQD_IQ_TIMER__IMMEDIATE_EXPIRE_MASK 0x00000800L |
19002 | #define CP_GFX_HQD_IQ_TIMER__INTERRUPT_TYPE_MASK 0x00003000L |
19003 | #define CP_GFX_HQD_IQ_TIMER__CLOCK_COUNT_MASK 0x0000C000L |
19004 | #define CP_GFX_HQD_IQ_TIMER__QUANTUM_TIMER_MASK 0x00400000L |
19005 | #define CP_GFX_HQD_IQ_TIMER__QUEUE_TYPE_MASK 0x08000000L |
19006 | #define CP_GFX_HQD_IQ_TIMER__REARM_TIMER_MASK 0x10000000L |
19007 | #define CP_GFX_HQD_IQ_TIMER__ACTIVE_MASK 0x80000000L |
19008 | //CP_GFX_HQD_HQ_STATUS0 |
19009 | #define CP_GFX_HQD_HQ_STATUS0__DEQUEUE_STATUS__SHIFT 0x0 |
19010 | #define CP_GFX_HQD_HQ_STATUS0__OS_PREEMPT_STATUS__SHIFT 0x4 |
19011 | #define CP_GFX_HQD_HQ_STATUS0__PREEMPT_ACK__SHIFT 0x6 |
19012 | #define CP_GFX_HQD_HQ_STATUS0__QUEUE_IDLE__SHIFT 0x1e |
19013 | #define CP_GFX_HQD_HQ_STATUS0__DEQUEUE_STATUS_MASK 0x00000001L |
19014 | #define CP_GFX_HQD_HQ_STATUS0__OS_PREEMPT_STATUS_MASK 0x00000030L |
19015 | #define CP_GFX_HQD_HQ_STATUS0__PREEMPT_ACK_MASK 0x00000040L |
19016 | #define CP_GFX_HQD_HQ_STATUS0__QUEUE_IDLE_MASK 0x40000000L |
19017 | //CP_GFX_HQD_HQ_CONTROL0 |
19018 | #define CP_GFX_HQD_HQ_CONTROL0__COMMAND__SHIFT 0x0 |
19019 | #define CP_GFX_HQD_HQ_CONTROL0__SPARES__SHIFT 0x4 |
19020 | #define CP_GFX_HQD_HQ_CONTROL0__COMMAND_MASK 0x0000000FL |
19021 | #define CP_GFX_HQD_HQ_CONTROL0__SPARES_MASK 0x000000F0L |
19022 | //CP_GFX_MQD_CONTROL |
19023 | #define CP_GFX_MQD_CONTROL__VMID__SHIFT 0x0 |
19024 | #define CP_GFX_MQD_CONTROL__PRIV_STATE__SHIFT 0x8 |
19025 | #define CP_GFX_MQD_CONTROL__PROCESSING_MQD__SHIFT 0xc |
19026 | #define CP_GFX_MQD_CONTROL__PROCESSING_MQD_EN__SHIFT 0xd |
19027 | #define CP_GFX_MQD_CONTROL__EXE_DISABLE__SHIFT 0x17 |
19028 | #define CP_GFX_MQD_CONTROL__CACHE_POLICY__SHIFT 0x18 |
19029 | #define CP_GFX_MQD_CONTROL__VMID_MASK 0x0000000FL |
19030 | #define CP_GFX_MQD_CONTROL__PRIV_STATE_MASK 0x00000100L |
19031 | #define CP_GFX_MQD_CONTROL__PROCESSING_MQD_MASK 0x00001000L |
19032 | #define CP_GFX_MQD_CONTROL__PROCESSING_MQD_EN_MASK 0x00002000L |
19033 | #define CP_GFX_MQD_CONTROL__EXE_DISABLE_MASK 0x00800000L |
19034 | #define CP_GFX_MQD_CONTROL__CACHE_POLICY_MASK 0x03000000L |
19035 | //CP_HQD_GFX_CONTROL |
19036 | #define CP_HQD_GFX_CONTROL__MESSAGE__SHIFT 0x0 |
19037 | #define CP_HQD_GFX_CONTROL__MISC__SHIFT 0x4 |
19038 | #define CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN__SHIFT 0xf |
19039 | #define CP_HQD_GFX_CONTROL__MESSAGE_MASK 0x0000000FL |
19040 | #define CP_HQD_GFX_CONTROL__MISC_MASK 0x00007FF0L |
19041 | #define CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN_MASK 0x00008000L |
19042 | //CP_HQD_GFX_STATUS |
19043 | #define CP_HQD_GFX_STATUS__STATUS__SHIFT 0x0 |
19044 | #define CP_HQD_GFX_STATUS__STATUS_MASK 0x0000FFFFL |
19045 | //CP_DMA_WATCH0_ADDR_LO |
19046 | #define CP_DMA_WATCH0_ADDR_LO__RSVD__SHIFT 0x0 |
19047 | #define CP_DMA_WATCH0_ADDR_LO__ADDR_LO__SHIFT 0x7 |
19048 | #define CP_DMA_WATCH0_ADDR_LO__RSVD_MASK 0x0000007FL |
19049 | #define CP_DMA_WATCH0_ADDR_LO__ADDR_LO_MASK 0xFFFFFF80L |
19050 | //CP_DMA_WATCH0_ADDR_HI |
19051 | #define CP_DMA_WATCH0_ADDR_HI__ADDR_HI__SHIFT 0x0 |
19052 | #define CP_DMA_WATCH0_ADDR_HI__RSVD__SHIFT 0x10 |
19053 | #define CP_DMA_WATCH0_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL |
19054 | #define CP_DMA_WATCH0_ADDR_HI__RSVD_MASK 0xFFFF0000L |
19055 | //CP_DMA_WATCH0_MASK |
19056 | #define CP_DMA_WATCH0_MASK__RSVD__SHIFT 0x0 |
19057 | #define CP_DMA_WATCH0_MASK__MASK__SHIFT 0x7 |
19058 | #define CP_DMA_WATCH0_MASK__RSVD_MASK 0x0000007FL |
19059 | #define CP_DMA_WATCH0_MASK__MASK_MASK 0xFFFFFF80L |
19060 | //CP_DMA_WATCH0_CNTL |
19061 | #define CP_DMA_WATCH0_CNTL__VMID__SHIFT 0x0 |
19062 | #define CP_DMA_WATCH0_CNTL__RSVD1__SHIFT 0x4 |
19063 | #define CP_DMA_WATCH0_CNTL__WATCH_READS__SHIFT 0x8 |
19064 | #define CP_DMA_WATCH0_CNTL__WATCH_WRITES__SHIFT 0x9 |
19065 | #define CP_DMA_WATCH0_CNTL__ANY_VMID__SHIFT 0xa |
19066 | #define CP_DMA_WATCH0_CNTL__RSVD2__SHIFT 0xb |
19067 | #define CP_DMA_WATCH0_CNTL__VMID_MASK 0x0000000FL |
19068 | #define CP_DMA_WATCH0_CNTL__RSVD1_MASK 0x000000F0L |
19069 | #define CP_DMA_WATCH0_CNTL__WATCH_READS_MASK 0x00000100L |
19070 | #define CP_DMA_WATCH0_CNTL__WATCH_WRITES_MASK 0x00000200L |
19071 | #define CP_DMA_WATCH0_CNTL__ANY_VMID_MASK 0x00000400L |
19072 | #define CP_DMA_WATCH0_CNTL__RSVD2_MASK 0xFFFFF800L |
19073 | //CP_DMA_WATCH1_ADDR_LO |
19074 | #define CP_DMA_WATCH1_ADDR_LO__RSVD__SHIFT 0x0 |
19075 | #define CP_DMA_WATCH1_ADDR_LO__ADDR_LO__SHIFT 0x7 |
19076 | #define CP_DMA_WATCH1_ADDR_LO__RSVD_MASK 0x0000007FL |
19077 | #define CP_DMA_WATCH1_ADDR_LO__ADDR_LO_MASK 0xFFFFFF80L |
19078 | //CP_DMA_WATCH1_ADDR_HI |
19079 | #define CP_DMA_WATCH1_ADDR_HI__ADDR_HI__SHIFT 0x0 |
19080 | #define CP_DMA_WATCH1_ADDR_HI__RSVD__SHIFT 0x10 |
19081 | #define CP_DMA_WATCH1_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL |
19082 | #define CP_DMA_WATCH1_ADDR_HI__RSVD_MASK 0xFFFF0000L |
19083 | //CP_DMA_WATCH1_MASK |
19084 | #define CP_DMA_WATCH1_MASK__RSVD__SHIFT 0x0 |
19085 | #define CP_DMA_WATCH1_MASK__MASK__SHIFT 0x7 |
19086 | #define CP_DMA_WATCH1_MASK__RSVD_MASK 0x0000007FL |
19087 | #define CP_DMA_WATCH1_MASK__MASK_MASK 0xFFFFFF80L |
19088 | //CP_DMA_WATCH1_CNTL |
19089 | #define CP_DMA_WATCH1_CNTL__VMID__SHIFT 0x0 |
19090 | #define CP_DMA_WATCH1_CNTL__RSVD1__SHIFT 0x4 |
19091 | #define CP_DMA_WATCH1_CNTL__WATCH_READS__SHIFT 0x8 |
19092 | #define CP_DMA_WATCH1_CNTL__WATCH_WRITES__SHIFT 0x9 |
19093 | #define CP_DMA_WATCH1_CNTL__ANY_VMID__SHIFT 0xa |
19094 | #define CP_DMA_WATCH1_CNTL__RSVD2__SHIFT 0xb |
19095 | #define CP_DMA_WATCH1_CNTL__VMID_MASK 0x0000000FL |
19096 | #define CP_DMA_WATCH1_CNTL__RSVD1_MASK 0x000000F0L |
19097 | #define CP_DMA_WATCH1_CNTL__WATCH_READS_MASK 0x00000100L |
19098 | #define CP_DMA_WATCH1_CNTL__WATCH_WRITES_MASK 0x00000200L |
19099 | #define CP_DMA_WATCH1_CNTL__ANY_VMID_MASK 0x00000400L |
19100 | #define CP_DMA_WATCH1_CNTL__RSVD2_MASK 0xFFFFF800L |
19101 | //CP_DMA_WATCH2_ADDR_LO |
19102 | #define CP_DMA_WATCH2_ADDR_LO__RSVD__SHIFT 0x0 |
19103 | #define CP_DMA_WATCH2_ADDR_LO__ADDR_LO__SHIFT 0x7 |
19104 | #define CP_DMA_WATCH2_ADDR_LO__RSVD_MASK 0x0000007FL |
19105 | #define CP_DMA_WATCH2_ADDR_LO__ADDR_LO_MASK 0xFFFFFF80L |
19106 | //CP_DMA_WATCH2_ADDR_HI |
19107 | #define CP_DMA_WATCH2_ADDR_HI__ADDR_HI__SHIFT 0x0 |
19108 | #define CP_DMA_WATCH2_ADDR_HI__RSVD__SHIFT 0x10 |
19109 | #define CP_DMA_WATCH2_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL |
19110 | #define CP_DMA_WATCH2_ADDR_HI__RSVD_MASK 0xFFFF0000L |
19111 | //CP_DMA_WATCH2_MASK |
19112 | #define CP_DMA_WATCH2_MASK__RSVD__SHIFT 0x0 |
19113 | #define CP_DMA_WATCH2_MASK__MASK__SHIFT 0x7 |
19114 | #define CP_DMA_WATCH2_MASK__RSVD_MASK 0x0000007FL |
19115 | #define CP_DMA_WATCH2_MASK__MASK_MASK 0xFFFFFF80L |
19116 | //CP_DMA_WATCH2_CNTL |
19117 | #define CP_DMA_WATCH2_CNTL__VMID__SHIFT 0x0 |
19118 | #define CP_DMA_WATCH2_CNTL__RSVD1__SHIFT 0x4 |
19119 | #define CP_DMA_WATCH2_CNTL__WATCH_READS__SHIFT 0x8 |
19120 | #define CP_DMA_WATCH2_CNTL__WATCH_WRITES__SHIFT 0x9 |
19121 | #define CP_DMA_WATCH2_CNTL__ANY_VMID__SHIFT 0xa |
19122 | #define CP_DMA_WATCH2_CNTL__RSVD2__SHIFT 0xb |
19123 | #define CP_DMA_WATCH2_CNTL__VMID_MASK 0x0000000FL |
19124 | #define CP_DMA_WATCH2_CNTL__RSVD1_MASK 0x000000F0L |
19125 | #define CP_DMA_WATCH2_CNTL__WATCH_READS_MASK 0x00000100L |
19126 | #define CP_DMA_WATCH2_CNTL__WATCH_WRITES_MASK 0x00000200L |
19127 | #define CP_DMA_WATCH2_CNTL__ANY_VMID_MASK 0x00000400L |
19128 | #define CP_DMA_WATCH2_CNTL__RSVD2_MASK 0xFFFFF800L |
19129 | //CP_DMA_WATCH3_ADDR_LO |
19130 | #define CP_DMA_WATCH3_ADDR_LO__RSVD__SHIFT 0x0 |
19131 | #define CP_DMA_WATCH3_ADDR_LO__ADDR_LO__SHIFT 0x7 |
19132 | #define CP_DMA_WATCH3_ADDR_LO__RSVD_MASK 0x0000007FL |
19133 | #define CP_DMA_WATCH3_ADDR_LO__ADDR_LO_MASK 0xFFFFFF80L |
19134 | //CP_DMA_WATCH3_ADDR_HI |
19135 | #define CP_DMA_WATCH3_ADDR_HI__ADDR_HI__SHIFT 0x0 |
19136 | #define CP_DMA_WATCH3_ADDR_HI__RSVD__SHIFT 0x10 |
19137 | #define CP_DMA_WATCH3_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL |
19138 | #define CP_DMA_WATCH3_ADDR_HI__RSVD_MASK 0xFFFF0000L |
19139 | //CP_DMA_WATCH3_MASK |
19140 | #define CP_DMA_WATCH3_MASK__RSVD__SHIFT 0x0 |
19141 | #define CP_DMA_WATCH3_MASK__MASK__SHIFT 0x7 |
19142 | #define CP_DMA_WATCH3_MASK__RSVD_MASK 0x0000007FL |
19143 | #define CP_DMA_WATCH3_MASK__MASK_MASK 0xFFFFFF80L |
19144 | //CP_DMA_WATCH3_CNTL |
19145 | #define CP_DMA_WATCH3_CNTL__VMID__SHIFT 0x0 |
19146 | #define CP_DMA_WATCH3_CNTL__RSVD1__SHIFT 0x4 |
19147 | #define CP_DMA_WATCH3_CNTL__WATCH_READS__SHIFT 0x8 |
19148 | #define CP_DMA_WATCH3_CNTL__WATCH_WRITES__SHIFT 0x9 |
19149 | #define CP_DMA_WATCH3_CNTL__ANY_VMID__SHIFT 0xa |
19150 | #define CP_DMA_WATCH3_CNTL__RSVD2__SHIFT 0xb |
19151 | #define CP_DMA_WATCH3_CNTL__VMID_MASK 0x0000000FL |
19152 | #define CP_DMA_WATCH3_CNTL__RSVD1_MASK 0x000000F0L |
19153 | #define CP_DMA_WATCH3_CNTL__WATCH_READS_MASK 0x00000100L |
19154 | #define CP_DMA_WATCH3_CNTL__WATCH_WRITES_MASK 0x00000200L |
19155 | #define CP_DMA_WATCH3_CNTL__ANY_VMID_MASK 0x00000400L |
19156 | #define CP_DMA_WATCH3_CNTL__RSVD2_MASK 0xFFFFF800L |
19157 | //CP_DMA_WATCH_STAT_ADDR_LO |
19158 | #define CP_DMA_WATCH_STAT_ADDR_LO__ADDR_LO__SHIFT 0x2 |
19159 | #define CP_DMA_WATCH_STAT_ADDR_LO__ADDR_LO_MASK 0xFFFFFFFCL |
19160 | //CP_DMA_WATCH_STAT_ADDR_HI |
19161 | #define CP_DMA_WATCH_STAT_ADDR_HI__ADDR_HI__SHIFT 0x0 |
19162 | #define CP_DMA_WATCH_STAT_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL |
19163 | //CP_DMA_WATCH_STAT |
19164 | #define CP_DMA_WATCH_STAT__VMID__SHIFT 0x0 |
19165 | #define CP_DMA_WATCH_STAT__QUEUE_ID__SHIFT 0x4 |
19166 | #define CP_DMA_WATCH_STAT__CLIENT_ID__SHIFT 0x8 |
19167 | #define CP_DMA_WATCH_STAT__PIPE__SHIFT 0xc |
19168 | #define CP_DMA_WATCH_STAT__WATCH_ID__SHIFT 0x10 |
19169 | #define CP_DMA_WATCH_STAT__RD_WR__SHIFT 0x14 |
19170 | #define CP_DMA_WATCH_STAT__TRAP_FLAG__SHIFT 0x1f |
19171 | #define CP_DMA_WATCH_STAT__VMID_MASK 0x0000000FL |
19172 | #define CP_DMA_WATCH_STAT__QUEUE_ID_MASK 0x00000070L |
19173 | #define CP_DMA_WATCH_STAT__CLIENT_ID_MASK 0x00000700L |
19174 | #define CP_DMA_WATCH_STAT__PIPE_MASK 0x00003000L |
19175 | #define CP_DMA_WATCH_STAT__WATCH_ID_MASK 0x00030000L |
19176 | #define CP_DMA_WATCH_STAT__RD_WR_MASK 0x00100000L |
19177 | #define CP_DMA_WATCH_STAT__TRAP_FLAG_MASK 0x80000000L |
19178 | //CP_PFP_JT_STAT |
19179 | #define CP_PFP_JT_STAT__JT_LOADED__SHIFT 0x0 |
19180 | #define CP_PFP_JT_STAT__WR_MASK__SHIFT 0x10 |
19181 | #define CP_PFP_JT_STAT__JT_LOADED_MASK 0x00000003L |
19182 | #define CP_PFP_JT_STAT__WR_MASK_MASK 0x00030000L |
19183 | //CP_MEC_JT_STAT |
19184 | #define CP_MEC_JT_STAT__JT_LOADED__SHIFT 0x0 |
19185 | #define CP_MEC_JT_STAT__WR_MASK__SHIFT 0x10 |
19186 | #define CP_MEC_JT_STAT__JT_LOADED_MASK 0x000000FFL |
19187 | #define CP_MEC_JT_STAT__WR_MASK_MASK 0x00FF0000L |
19188 | //CP_CPC_BUSY_HYSTERESIS |
19189 | #define CP_CPC_BUSY_HYSTERESIS__CAC_ACTIVE__SHIFT 0x0 |
19190 | #define CP_CPC_BUSY_HYSTERESIS__CPC_BUSY__SHIFT 0x8 |
19191 | #define CP_CPC_BUSY_HYSTERESIS__CAC_ACTIVE_MASK 0x000000FFL |
19192 | #define CP_CPC_BUSY_HYSTERESIS__CPC_BUSY_MASK 0x0000FF00L |
19193 | //CP_CPF_BUSY_HYSTERESIS1 |
19194 | #define CP_CPF_BUSY_HYSTERESIS1__CAC_ACTIVE__SHIFT 0x0 |
19195 | #define CP_CPF_BUSY_HYSTERESIS1__CPF_BUSY__SHIFT 0x8 |
19196 | #define CP_CPF_BUSY_HYSTERESIS1__CORE_BUSY__SHIFT 0x10 |
19197 | #define CP_CPF_BUSY_HYSTERESIS1__GFX_BUSY__SHIFT 0x18 |
19198 | #define CP_CPF_BUSY_HYSTERESIS1__CAC_ACTIVE_MASK 0x000000FFL |
19199 | #define CP_CPF_BUSY_HYSTERESIS1__CPF_BUSY_MASK 0x0000FF00L |
19200 | #define CP_CPF_BUSY_HYSTERESIS1__CORE_BUSY_MASK 0x00FF0000L |
19201 | #define CP_CPF_BUSY_HYSTERESIS1__GFX_BUSY_MASK 0xFF000000L |
19202 | //CP_CPF_BUSY_HYSTERESIS2 |
19203 | #define CP_CPF_BUSY_HYSTERESIS2__CMP_BUSY__SHIFT 0x0 |
19204 | #define CP_CPF_BUSY_HYSTERESIS2__CMP_BUSY_MASK 0x000000FFL |
19205 | //CP_CPG_BUSY_HYSTERESIS1 |
19206 | #define CP_CPG_BUSY_HYSTERESIS1__CAC_ACTIVE__SHIFT 0x0 |
19207 | #define CP_CPG_BUSY_HYSTERESIS1__CP_BUSY__SHIFT 0x8 |
19208 | #define CP_CPG_BUSY_HYSTERESIS1__DMA_BUSY__SHIFT 0x10 |
19209 | #define CP_CPG_BUSY_HYSTERESIS1__GFX_BUSY__SHIFT 0x18 |
19210 | #define CP_CPG_BUSY_HYSTERESIS1__CAC_ACTIVE_MASK 0x000000FFL |
19211 | #define CP_CPG_BUSY_HYSTERESIS1__CP_BUSY_MASK 0x0000FF00L |
19212 | #define CP_CPG_BUSY_HYSTERESIS1__DMA_BUSY_MASK 0x00FF0000L |
19213 | #define CP_CPG_BUSY_HYSTERESIS1__GFX_BUSY_MASK 0xFF000000L |
19214 | //CP_CPG_BUSY_HYSTERESIS2 |
19215 | #define CP_CPG_BUSY_HYSTERESIS2__CMP_BUSY__SHIFT 0x0 |
19216 | #define CP_CPG_BUSY_HYSTERESIS2__SPI_CLOCK_0__SHIFT 0x8 |
19217 | #define CP_CPG_BUSY_HYSTERESIS2__SPI_CLOCK_1__SHIFT 0x10 |
19218 | #define CP_CPG_BUSY_HYSTERESIS2__CMP_BUSY_MASK 0x000000FFL |
19219 | #define CP_CPG_BUSY_HYSTERESIS2__SPI_CLOCK_0_MASK 0x0000FF00L |
19220 | #define CP_CPG_BUSY_HYSTERESIS2__SPI_CLOCK_1_MASK 0x00FF0000L |
19221 | //CP_RB_DOORBELL_CLEAR |
19222 | #define CP_RB_DOORBELL_CLEAR__MAPPED_QUEUE__SHIFT 0x0 |
19223 | #define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_EN_CLEAR__SHIFT 0x8 |
19224 | #define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_HIT_CLEAR__SHIFT 0x9 |
19225 | #define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_EN_CLEAR__SHIFT 0xa |
19226 | #define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_HIT_CLEAR__SHIFT 0xb |
19227 | #define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_EN_CLEAR__SHIFT 0xc |
19228 | #define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_HIT_CLEAR__SHIFT 0xd |
19229 | #define CP_RB_DOORBELL_CLEAR__MAPPED_QUEUE_MASK 0x00000007L |
19230 | #define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_EN_CLEAR_MASK 0x00000100L |
19231 | #define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_HIT_CLEAR_MASK 0x00000200L |
19232 | #define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_EN_CLEAR_MASK 0x00000400L |
19233 | #define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_HIT_CLEAR_MASK 0x00000800L |
19234 | #define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_EN_CLEAR_MASK 0x00001000L |
19235 | #define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_HIT_CLEAR_MASK 0x00002000L |
19236 | //CP_RB0_ACTIVE |
19237 | #define CP_RB0_ACTIVE__ACTIVE__SHIFT 0x0 |
19238 | #define CP_RB0_ACTIVE__ACTIVE_MASK 0x00000001L |
19239 | //CP_RB_ACTIVE |
19240 | #define CP_RB_ACTIVE__ACTIVE__SHIFT 0x0 |
19241 | #define CP_RB_ACTIVE__ACTIVE_MASK 0x00000001L |
19242 | //CP_RB1_ACTIVE |
19243 | #define CP_RB1_ACTIVE__ACTIVE__SHIFT 0x0 |
19244 | #define CP_RB1_ACTIVE__ACTIVE_MASK 0x00000001L |
19245 | //CP_RB_STATUS |
19246 | #define CP_RB_STATUS__DOORBELL_UPDATED__SHIFT 0x0 |
19247 | #define CP_RB_STATUS__DOORBELL_ENABLE__SHIFT 0x1 |
19248 | #define CP_RB_STATUS__DOORBELL_UPDATED_MASK 0x00000001L |
19249 | #define CP_RB_STATUS__DOORBELL_ENABLE_MASK 0x00000002L |
19250 | //CPG_RCIU_CAM_INDEX |
19251 | #define CPG_RCIU_CAM_INDEX__INDEX__SHIFT 0x0 |
19252 | #define CPG_RCIU_CAM_INDEX__INDEX_MASK 0x0000001FL |
19253 | //CPG_RCIU_CAM_DATA |
19254 | #define CPG_RCIU_CAM_DATA__DATA__SHIFT 0x0 |
19255 | #define CPG_RCIU_CAM_DATA__DATA_MASK 0xFFFFFFFFL |
19256 | //CPG_RCIU_CAM_DATA_PHASE0 |
19257 | #define CPG_RCIU_CAM_DATA_PHASE0__ADDR__SHIFT 0x0 |
19258 | #define CPG_RCIU_CAM_DATA_PHASE0__PIPE0_EN__SHIFT 0x18 |
19259 | #define CPG_RCIU_CAM_DATA_PHASE0__PIPE1_EN__SHIFT 0x19 |
19260 | #define CPG_RCIU_CAM_DATA_PHASE0__SKIP_WR__SHIFT 0x1f |
19261 | #define CPG_RCIU_CAM_DATA_PHASE0__ADDR_MASK 0x0003FFFFL |
19262 | #define CPG_RCIU_CAM_DATA_PHASE0__PIPE0_EN_MASK 0x01000000L |
19263 | #define CPG_RCIU_CAM_DATA_PHASE0__PIPE1_EN_MASK 0x02000000L |
19264 | #define CPG_RCIU_CAM_DATA_PHASE0__SKIP_WR_MASK 0x80000000L |
19265 | //CPG_RCIU_CAM_DATA_PHASE1 |
19266 | #define CPG_RCIU_CAM_DATA_PHASE1__MASK__SHIFT 0x0 |
19267 | #define CPG_RCIU_CAM_DATA_PHASE1__MASK_MASK 0xFFFFFFFFL |
19268 | //CPG_RCIU_CAM_DATA_PHASE2 |
19269 | #define CPG_RCIU_CAM_DATA_PHASE2__VALUE__SHIFT 0x0 |
19270 | #define CPG_RCIU_CAM_DATA_PHASE2__VALUE_MASK 0xFFFFFFFFL |
19271 | //CP_GPU_TIMESTAMP_OFFSET_LO |
19272 | #define CP_GPU_TIMESTAMP_OFFSET_LO__OFFSET_LO__SHIFT 0x0 |
19273 | #define CP_GPU_TIMESTAMP_OFFSET_LO__OFFSET_LO_MASK 0xFFFFFFFFL |
19274 | //CP_GPU_TIMESTAMP_OFFSET_HI |
19275 | #define CP_GPU_TIMESTAMP_OFFSET_HI__OFFSET_HI__SHIFT 0x0 |
19276 | #define CP_GPU_TIMESTAMP_OFFSET_HI__OFFSET_HI_MASK 0xFFFFFFFFL |
19277 | //CP_SDMA_DMA_DONE |
19278 | #define CP_SDMA_DMA_DONE__SDMA_ID__SHIFT 0x0 |
19279 | #define CP_SDMA_DMA_DONE__SDMA_ID_MASK 0x0000000FL |
19280 | //CP_PFP_SDMA_CS |
19281 | #define CP_PFP_SDMA_CS__REQUEST_GRANT__SHIFT 0x0 |
19282 | #define CP_PFP_SDMA_CS__SDMA_ID__SHIFT 0x4 |
19283 | #define CP_PFP_SDMA_CS__REQUEST_POSITION__SHIFT 0x8 |
19284 | #define CP_PFP_SDMA_CS__SDMA_COUNT__SHIFT 0xc |
19285 | #define CP_PFP_SDMA_CS__REQUEST_GRANT_MASK 0x00000001L |
19286 | #define CP_PFP_SDMA_CS__SDMA_ID_MASK 0x000000F0L |
19287 | #define CP_PFP_SDMA_CS__REQUEST_POSITION_MASK 0x00000F00L |
19288 | #define CP_PFP_SDMA_CS__SDMA_COUNT_MASK 0x00003000L |
19289 | //CP_ME_SDMA_CS |
19290 | #define CP_ME_SDMA_CS__REQUEST_GRANT__SHIFT 0x0 |
19291 | #define CP_ME_SDMA_CS__SDMA_ID__SHIFT 0x4 |
19292 | #define CP_ME_SDMA_CS__REQUEST_POSITION__SHIFT 0x8 |
19293 | #define CP_ME_SDMA_CS__SDMA_COUNT__SHIFT 0xc |
19294 | #define CP_ME_SDMA_CS__REQUEST_GRANT_MASK 0x00000001L |
19295 | #define CP_ME_SDMA_CS__SDMA_ID_MASK 0x000000F0L |
19296 | #define CP_ME_SDMA_CS__REQUEST_POSITION_MASK 0x00000F00L |
19297 | #define CP_ME_SDMA_CS__SDMA_COUNT_MASK 0x00003000L |
19298 | //CPF_GCR_CNTL |
19299 | #define CPF_GCR_CNTL__GCR_GL_CMD__SHIFT 0x0 |
19300 | #define CPF_GCR_CNTL__GCR_GL_CMD_MASK 0x0007FFFFL |
19301 | //CPG_UTCL1_STATUS |
19302 | #define CPG_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 |
19303 | #define CPG_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 |
19304 | #define CPG_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 |
19305 | #define CPG_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8 |
19306 | #define CPG_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10 |
19307 | #define CPG_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18 |
19308 | #define CPG_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L |
19309 | #define CPG_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L |
19310 | #define CPG_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L |
19311 | #define CPG_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L |
19312 | #define CPG_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L |
19313 | #define CPG_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L |
19314 | //CPC_UTCL1_STATUS |
19315 | #define CPC_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 |
19316 | #define CPC_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 |
19317 | #define CPC_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 |
19318 | #define CPC_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8 |
19319 | #define CPC_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10 |
19320 | #define CPC_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18 |
19321 | #define CPC_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L |
19322 | #define CPC_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L |
19323 | #define CPC_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L |
19324 | #define CPC_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L |
19325 | #define CPC_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L |
19326 | #define CPC_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L |
19327 | //CPF_UTCL1_STATUS |
19328 | #define CPF_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 |
19329 | #define CPF_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 |
19330 | #define CPF_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 |
19331 | #define CPF_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8 |
19332 | #define CPF_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10 |
19333 | #define CPF_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18 |
19334 | #define CPF_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L |
19335 | #define CPF_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L |
19336 | #define CPF_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L |
19337 | #define CPF_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L |
19338 | #define CPF_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L |
19339 | #define CPF_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L |
19340 | //CP_SD_CNTL |
19341 | #define CP_SD_CNTL__CPF_EN__SHIFT 0x0 |
19342 | #define CP_SD_CNTL__CPG_EN__SHIFT 0x1 |
19343 | #define CP_SD_CNTL__CPC_EN__SHIFT 0x2 |
19344 | #define CP_SD_CNTL__RLC_EN__SHIFT 0x3 |
19345 | #define CP_SD_CNTL__GE_EN__SHIFT 0x5 |
19346 | #define CP_SD_CNTL__UTCL1_EN__SHIFT 0x6 |
19347 | #define CP_SD_CNTL__EA_EN__SHIFT 0x9 |
19348 | #define CP_SD_CNTL__SDMA_EN__SHIFT 0xa |
19349 | #define CP_SD_CNTL__SD_VMIDVEC_OVERRIDE__SHIFT 0x1f |
19350 | #define CP_SD_CNTL__CPF_EN_MASK 0x00000001L |
19351 | #define CP_SD_CNTL__CPG_EN_MASK 0x00000002L |
19352 | #define CP_SD_CNTL__CPC_EN_MASK 0x00000004L |
19353 | #define CP_SD_CNTL__RLC_EN_MASK 0x00000008L |
19354 | #define CP_SD_CNTL__GE_EN_MASK 0x00000020L |
19355 | #define CP_SD_CNTL__UTCL1_EN_MASK 0x00000040L |
19356 | #define CP_SD_CNTL__EA_EN_MASK 0x00000200L |
19357 | #define CP_SD_CNTL__SDMA_EN_MASK 0x00000400L |
19358 | #define CP_SD_CNTL__SD_VMIDVEC_OVERRIDE_MASK 0x80000000L |
19359 | //CP_SOFT_RESET_CNTL |
19360 | #define CP_SOFT_RESET_CNTL__CMP_ONLY_SOFT_RESET__SHIFT 0x0 |
19361 | #define CP_SOFT_RESET_CNTL__GFX_ONLY_SOFT_RESET__SHIFT 0x1 |
19362 | #define CP_SOFT_RESET_CNTL__CMP_HQD_REG_RESET__SHIFT 0x2 |
19363 | #define CP_SOFT_RESET_CNTL__CMP_INTR_REG_RESET__SHIFT 0x3 |
19364 | #define CP_SOFT_RESET_CNTL__CMP_HQD_QUEUE_DOORBELL_RESET__SHIFT 0x4 |
19365 | #define CP_SOFT_RESET_CNTL__GFX_RB_DOORBELL_RESET__SHIFT 0x5 |
19366 | #define CP_SOFT_RESET_CNTL__GFX_INTR_REG_RESET__SHIFT 0x6 |
19367 | #define CP_SOFT_RESET_CNTL__GFX_HQD_REG_RESET__SHIFT 0x7 |
19368 | #define CP_SOFT_RESET_CNTL__CMP_ONLY_SOFT_RESET_MASK 0x00000001L |
19369 | #define CP_SOFT_RESET_CNTL__GFX_ONLY_SOFT_RESET_MASK 0x00000002L |
19370 | #define CP_SOFT_RESET_CNTL__CMP_HQD_REG_RESET_MASK 0x00000004L |
19371 | #define CP_SOFT_RESET_CNTL__CMP_INTR_REG_RESET_MASK 0x00000008L |
19372 | #define CP_SOFT_RESET_CNTL__CMP_HQD_QUEUE_DOORBELL_RESET_MASK 0x00000010L |
19373 | #define CP_SOFT_RESET_CNTL__GFX_RB_DOORBELL_RESET_MASK 0x00000020L |
19374 | #define CP_SOFT_RESET_CNTL__GFX_INTR_REG_RESET_MASK 0x00000040L |
19375 | #define CP_SOFT_RESET_CNTL__GFX_HQD_REG_RESET_MASK 0x00000080L |
19376 | //CP_CPC_GFX_CNTL |
19377 | #define CP_CPC_GFX_CNTL__QUEUEID__SHIFT 0x0 |
19378 | #define CP_CPC_GFX_CNTL__PIPEID__SHIFT 0x3 |
19379 | #define CP_CPC_GFX_CNTL__MEID__SHIFT 0x5 |
19380 | #define CP_CPC_GFX_CNTL__VALID__SHIFT 0x7 |
19381 | #define CP_CPC_GFX_CNTL__QUEUEID_MASK 0x00000007L |
19382 | #define CP_CPC_GFX_CNTL__PIPEID_MASK 0x00000018L |
19383 | #define CP_CPC_GFX_CNTL__MEID_MASK 0x00000060L |
19384 | #define CP_CPC_GFX_CNTL__VALID_MASK 0x00000080L |
19385 | |
19386 | |
19387 | // addressBlock: gc_spipdec |
19388 | //SPI_ARB_PRIORITY |
19389 | #define SPI_ARB_PRIORITY__PIPE_ORDER_TS0__SHIFT 0x0 |
19390 | #define SPI_ARB_PRIORITY__PIPE_ORDER_TS1__SHIFT 0x3 |
19391 | #define SPI_ARB_PRIORITY__PIPE_ORDER_TS2__SHIFT 0x6 |
19392 | #define SPI_ARB_PRIORITY__PIPE_ORDER_TS3__SHIFT 0x9 |
19393 | #define SPI_ARB_PRIORITY__TS0_DUR_MULT__SHIFT 0xc |
19394 | #define SPI_ARB_PRIORITY__TS1_DUR_MULT__SHIFT 0xe |
19395 | #define SPI_ARB_PRIORITY__TS2_DUR_MULT__SHIFT 0x10 |
19396 | #define SPI_ARB_PRIORITY__TS3_DUR_MULT__SHIFT 0x12 |
19397 | #define SPI_ARB_PRIORITY__PIPE_ORDER_TS0_MASK 0x00000007L |
19398 | #define SPI_ARB_PRIORITY__PIPE_ORDER_TS1_MASK 0x00000038L |
19399 | #define SPI_ARB_PRIORITY__PIPE_ORDER_TS2_MASK 0x000001C0L |
19400 | #define SPI_ARB_PRIORITY__PIPE_ORDER_TS3_MASK 0x00000E00L |
19401 | #define SPI_ARB_PRIORITY__TS0_DUR_MULT_MASK 0x00003000L |
19402 | #define SPI_ARB_PRIORITY__TS1_DUR_MULT_MASK 0x0000C000L |
19403 | #define SPI_ARB_PRIORITY__TS2_DUR_MULT_MASK 0x00030000L |
19404 | #define SPI_ARB_PRIORITY__TS3_DUR_MULT_MASK 0x000C0000L |
19405 | //SPI_ARB_CYCLES_0 |
19406 | #define SPI_ARB_CYCLES_0__TS0_DURATION__SHIFT 0x0 |
19407 | #define SPI_ARB_CYCLES_0__TS1_DURATION__SHIFT 0x10 |
19408 | #define SPI_ARB_CYCLES_0__TS0_DURATION_MASK 0x0000FFFFL |
19409 | #define SPI_ARB_CYCLES_0__TS1_DURATION_MASK 0xFFFF0000L |
19410 | //SPI_ARB_CYCLES_1 |
19411 | #define SPI_ARB_CYCLES_1__TS2_DURATION__SHIFT 0x0 |
19412 | #define SPI_ARB_CYCLES_1__TS3_DURATION__SHIFT 0x10 |
19413 | #define SPI_ARB_CYCLES_1__TS2_DURATION_MASK 0x0000FFFFL |
19414 | #define SPI_ARB_CYCLES_1__TS3_DURATION_MASK 0xFFFF0000L |
19415 | //SPI_WCL_PIPE_PERCENT_GFX |
19416 | #define SPI_WCL_PIPE_PERCENT_GFX__VALUE__SHIFT 0x0 |
19417 | #define SPI_WCL_PIPE_PERCENT_GFX__HS_GRP_VALUE__SHIFT 0xc |
19418 | #define SPI_WCL_PIPE_PERCENT_GFX__GS_GRP_VALUE__SHIFT 0x16 |
19419 | #define SPI_WCL_PIPE_PERCENT_GFX__VALUE_MASK 0x0000007FL |
19420 | #define SPI_WCL_PIPE_PERCENT_GFX__HS_GRP_VALUE_MASK 0x0001F000L |
19421 | #define SPI_WCL_PIPE_PERCENT_GFX__GS_GRP_VALUE_MASK 0x07C00000L |
19422 | //SPI_WCL_PIPE_PERCENT_HP3D |
19423 | #define SPI_WCL_PIPE_PERCENT_HP3D__VALUE__SHIFT 0x0 |
19424 | #define SPI_WCL_PIPE_PERCENT_HP3D__HS_GRP_VALUE__SHIFT 0xc |
19425 | #define SPI_WCL_PIPE_PERCENT_HP3D__GS_GRP_VALUE__SHIFT 0x16 |
19426 | #define SPI_WCL_PIPE_PERCENT_HP3D__VALUE_MASK 0x0000007FL |
19427 | #define SPI_WCL_PIPE_PERCENT_HP3D__HS_GRP_VALUE_MASK 0x0001F000L |
19428 | #define SPI_WCL_PIPE_PERCENT_HP3D__GS_GRP_VALUE_MASK 0x07C00000L |
19429 | //SPI_WCL_PIPE_PERCENT_CS0 |
19430 | #define SPI_WCL_PIPE_PERCENT_CS0__VALUE__SHIFT 0x0 |
19431 | #define SPI_WCL_PIPE_PERCENT_CS0__VALUE_MASK 0x7FL |
19432 | //SPI_WCL_PIPE_PERCENT_CS1 |
19433 | #define SPI_WCL_PIPE_PERCENT_CS1__VALUE__SHIFT 0x0 |
19434 | #define SPI_WCL_PIPE_PERCENT_CS1__VALUE_MASK 0x7FL |
19435 | //SPI_WCL_PIPE_PERCENT_CS2 |
19436 | #define SPI_WCL_PIPE_PERCENT_CS2__VALUE__SHIFT 0x0 |
19437 | #define SPI_WCL_PIPE_PERCENT_CS2__VALUE_MASK 0x7FL |
19438 | //SPI_WCL_PIPE_PERCENT_CS3 |
19439 | #define SPI_WCL_PIPE_PERCENT_CS3__VALUE__SHIFT 0x0 |
19440 | #define SPI_WCL_PIPE_PERCENT_CS3__VALUE_MASK 0x7FL |
19441 | //SPI_WCL_PIPE_PERCENT_CS4 |
19442 | #define SPI_WCL_PIPE_PERCENT_CS4__VALUE__SHIFT 0x0 |
19443 | #define SPI_WCL_PIPE_PERCENT_CS4__VALUE_MASK 0x7FL |
19444 | //SPI_WCL_PIPE_PERCENT_CS5 |
19445 | #define SPI_WCL_PIPE_PERCENT_CS5__VALUE__SHIFT 0x0 |
19446 | #define SPI_WCL_PIPE_PERCENT_CS5__VALUE_MASK 0x7FL |
19447 | //SPI_WCL_PIPE_PERCENT_CS6 |
19448 | #define SPI_WCL_PIPE_PERCENT_CS6__VALUE__SHIFT 0x0 |
19449 | #define SPI_WCL_PIPE_PERCENT_CS6__VALUE_MASK 0x7FL |
19450 | //SPI_WCL_PIPE_PERCENT_CS7 |
19451 | #define SPI_WCL_PIPE_PERCENT_CS7__VALUE__SHIFT 0x0 |
19452 | #define SPI_WCL_PIPE_PERCENT_CS7__VALUE_MASK 0x7FL |
19453 | //SPI_USER_ACCUM_VMID_CNTL |
19454 | #define SPI_USER_ACCUM_VMID_CNTL__EN_USER_ACCUM__SHIFT 0x0 |
19455 | #define SPI_USER_ACCUM_VMID_CNTL__EN_USER_ACCUM_MASK 0x0000000FL |
19456 | //SPI_GDBG_PER_VMID_CNTL |
19457 | #define SPI_GDBG_PER_VMID_CNTL__STALL_VMID__SHIFT 0x0 |
19458 | #define SPI_GDBG_PER_VMID_CNTL__LAUNCH_MODE__SHIFT 0x1 |
19459 | #define SPI_GDBG_PER_VMID_CNTL__TRAP_EN__SHIFT 0x3 |
19460 | #define SPI_GDBG_PER_VMID_CNTL__EXCP_EN__SHIFT 0x4 |
19461 | #define SPI_GDBG_PER_VMID_CNTL__EXCP_REPLACE__SHIFT 0xd |
19462 | #define SPI_GDBG_PER_VMID_CNTL__STALL_VMID_MASK 0x00000001L |
19463 | #define SPI_GDBG_PER_VMID_CNTL__LAUNCH_MODE_MASK 0x00000006L |
19464 | #define SPI_GDBG_PER_VMID_CNTL__TRAP_EN_MASK 0x00000008L |
19465 | #define SPI_GDBG_PER_VMID_CNTL__EXCP_EN_MASK 0x00001FF0L |
19466 | #define SPI_GDBG_PER_VMID_CNTL__EXCP_REPLACE_MASK 0x00002000L |
19467 | //SPI_COMPUTE_QUEUE_RESET |
19468 | #define SPI_COMPUTE_QUEUE_RESET__RESET__SHIFT 0x0 |
19469 | #define SPI_COMPUTE_QUEUE_RESET__RESET_MASK 0x01L |
19470 | //SPI_COMPUTE_WF_CTX_SAVE |
19471 | #define SPI_COMPUTE_WF_CTX_SAVE__INITIATE__SHIFT 0x0 |
19472 | #define SPI_COMPUTE_WF_CTX_SAVE__GDS_INTERRUPT_EN__SHIFT 0x1 |
19473 | #define SPI_COMPUTE_WF_CTX_SAVE__DONE_INTERRUPT_EN__SHIFT 0x2 |
19474 | #define SPI_COMPUTE_WF_CTX_SAVE__GDS_REQ_BUSY__SHIFT 0x1e |
19475 | #define SPI_COMPUTE_WF_CTX_SAVE__SAVE_BUSY__SHIFT 0x1f |
19476 | #define SPI_COMPUTE_WF_CTX_SAVE__INITIATE_MASK 0x00000001L |
19477 | #define SPI_COMPUTE_WF_CTX_SAVE__GDS_INTERRUPT_EN_MASK 0x00000002L |
19478 | #define SPI_COMPUTE_WF_CTX_SAVE__DONE_INTERRUPT_EN_MASK 0x00000004L |
19479 | #define SPI_COMPUTE_WF_CTX_SAVE__GDS_REQ_BUSY_MASK 0x40000000L |
19480 | #define SPI_COMPUTE_WF_CTX_SAVE__SAVE_BUSY_MASK 0x80000000L |
19481 | |
19482 | |
19483 | // addressBlock: gc_cpphqddec |
19484 | //CP_HPD_UTCL1_CNTL |
19485 | #define CP_HPD_UTCL1_CNTL__SELECT__SHIFT 0x0 |
19486 | #define CP_HPD_UTCL1_CNTL__DISABLE_ERROR_REPORT__SHIFT 0xa |
19487 | #define CP_HPD_UTCL1_CNTL__SELECT_MASK 0x0000000FL |
19488 | #define CP_HPD_UTCL1_CNTL__DISABLE_ERROR_REPORT_MASK 0x00000400L |
19489 | //CP_HPD_UTCL1_ERROR |
19490 | #define CP_HPD_UTCL1_ERROR__ADDR_HI__SHIFT 0x0 |
19491 | #define CP_HPD_UTCL1_ERROR__TYPE__SHIFT 0x10 |
19492 | #define CP_HPD_UTCL1_ERROR__VMID__SHIFT 0x14 |
19493 | #define CP_HPD_UTCL1_ERROR__ADDR_HI_MASK 0x0000FFFFL |
19494 | #define CP_HPD_UTCL1_ERROR__TYPE_MASK 0x00010000L |
19495 | #define CP_HPD_UTCL1_ERROR__VMID_MASK 0x00F00000L |
19496 | //CP_HPD_UTCL1_ERROR_ADDR |
19497 | #define CP_HPD_UTCL1_ERROR_ADDR__ADDR__SHIFT 0xc |
19498 | #define CP_HPD_UTCL1_ERROR_ADDR__ADDR_MASK 0xFFFFF000L |
19499 | //CP_MQD_BASE_ADDR |
19500 | #define CP_MQD_BASE_ADDR__BASE_ADDR__SHIFT 0x2 |
19501 | #define CP_MQD_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFCL |
19502 | //CP_MQD_BASE_ADDR_HI |
19503 | #define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 |
19504 | #define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0x0000FFFFL |
19505 | //CP_HQD_ACTIVE |
19506 | #define CP_HQD_ACTIVE__ACTIVE__SHIFT 0x0 |
19507 | #define CP_HQD_ACTIVE__BUSY_GATE__SHIFT 0x1 |
19508 | #define CP_HQD_ACTIVE__ACTIVE_MASK 0x00000001L |
19509 | #define CP_HQD_ACTIVE__BUSY_GATE_MASK 0x00000002L |
19510 | //CP_HQD_VMID |
19511 | #define CP_HQD_VMID__VMID__SHIFT 0x0 |
19512 | #define CP_HQD_VMID__IB_VMID__SHIFT 0x8 |
19513 | #define CP_HQD_VMID__VQID__SHIFT 0x10 |
19514 | #define CP_HQD_VMID__VMID_MASK 0x0000000FL |
19515 | #define CP_HQD_VMID__IB_VMID_MASK 0x00000F00L |
19516 | #define CP_HQD_VMID__VQID_MASK 0x03FF0000L |
19517 | //CP_HQD_PERSISTENT_STATE |
19518 | #define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ__SHIFT 0x0 |
19519 | #define CP_HQD_PERSISTENT_STATE__TMZ_CONNECT_OVERRIDE__SHIFT 0x1 |
19520 | #define CP_HQD_PERSISTENT_STATE__SUSPEND_STATUS__SHIFT 0x7 |
19521 | #define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT 0x8 |
19522 | #define CP_HQD_PERSISTENT_STATE__TMZ_SWITCH_EXEMPT__SHIFT 0x12 |
19523 | #define CP_HQD_PERSISTENT_STATE__TMZ_MATCH_DIS__SHIFT 0x13 |
19524 | #define CP_HQD_PERSISTENT_STATE__WPP_CLAMP_EN__SHIFT 0x14 |
19525 | #define CP_HQD_PERSISTENT_STATE__WPP_SWITCH_QOS_EN__SHIFT 0x15 |
19526 | #define CP_HQD_PERSISTENT_STATE__IQ_SWITCH_QOS_EN__SHIFT 0x16 |
19527 | #define CP_HQD_PERSISTENT_STATE__IB_SWITCH_QOS_EN__SHIFT 0x17 |
19528 | #define CP_HQD_PERSISTENT_STATE__EOP_SWITCH_QOS_EN__SHIFT 0x18 |
19529 | #define CP_HQD_PERSISTENT_STATE__PQ_SWITCH_QOS_EN__SHIFT 0x19 |
19530 | #define CP_HQD_PERSISTENT_STATE__TC_OFFLOAD_QOS_EN__SHIFT 0x1a |
19531 | #define CP_HQD_PERSISTENT_STATE__CACHE_FULL_PACKET_EN__SHIFT 0x1b |
19532 | #define CP_HQD_PERSISTENT_STATE__RESTORE_ACTIVE__SHIFT 0x1c |
19533 | #define CP_HQD_PERSISTENT_STATE__RELAUNCH_WAVES__SHIFT 0x1d |
19534 | #define CP_HQD_PERSISTENT_STATE__QSWITCH_MODE__SHIFT 0x1e |
19535 | #define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE__SHIFT 0x1f |
19536 | #define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK 0x00000001L |
19537 | #define CP_HQD_PERSISTENT_STATE__TMZ_CONNECT_OVERRIDE_MASK 0x00000002L |
19538 | #define CP_HQD_PERSISTENT_STATE__SUSPEND_STATUS_MASK 0x00000080L |
19539 | #define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE_MASK 0x0003FF00L |
19540 | #define CP_HQD_PERSISTENT_STATE__TMZ_SWITCH_EXEMPT_MASK 0x00040000L |
19541 | #define CP_HQD_PERSISTENT_STATE__TMZ_MATCH_DIS_MASK 0x00080000L |
19542 | #define CP_HQD_PERSISTENT_STATE__WPP_CLAMP_EN_MASK 0x00100000L |
19543 | #define CP_HQD_PERSISTENT_STATE__WPP_SWITCH_QOS_EN_MASK 0x00200000L |
19544 | #define CP_HQD_PERSISTENT_STATE__IQ_SWITCH_QOS_EN_MASK 0x00400000L |
19545 | #define CP_HQD_PERSISTENT_STATE__IB_SWITCH_QOS_EN_MASK 0x00800000L |
19546 | #define CP_HQD_PERSISTENT_STATE__EOP_SWITCH_QOS_EN_MASK 0x01000000L |
19547 | #define CP_HQD_PERSISTENT_STATE__PQ_SWITCH_QOS_EN_MASK 0x02000000L |
19548 | #define CP_HQD_PERSISTENT_STATE__TC_OFFLOAD_QOS_EN_MASK 0x04000000L |
19549 | #define CP_HQD_PERSISTENT_STATE__CACHE_FULL_PACKET_EN_MASK 0x08000000L |
19550 | #define CP_HQD_PERSISTENT_STATE__RESTORE_ACTIVE_MASK 0x10000000L |
19551 | #define CP_HQD_PERSISTENT_STATE__RELAUNCH_WAVES_MASK 0x20000000L |
19552 | #define CP_HQD_PERSISTENT_STATE__QSWITCH_MODE_MASK 0x40000000L |
19553 | #define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE_MASK 0x80000000L |
19554 | //CP_HQD_PIPE_PRIORITY |
19555 | #define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY__SHIFT 0x0 |
19556 | #define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY_MASK 0x00000003L |
19557 | //CP_HQD_QUEUE_PRIORITY |
19558 | #define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL__SHIFT 0x0 |
19559 | #define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL_MASK 0x0000000FL |
19560 | //CP_HQD_QUANTUM |
19561 | #define CP_HQD_QUANTUM__QUANTUM_EN__SHIFT 0x0 |
19562 | #define CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT 0x4 |
19563 | #define CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT 0x8 |
19564 | #define CP_HQD_QUANTUM__QUANTUM_ACTIVE__SHIFT 0x1f |
19565 | #define CP_HQD_QUANTUM__QUANTUM_EN_MASK 0x00000001L |
19566 | #define CP_HQD_QUANTUM__QUANTUM_SCALE_MASK 0x00000010L |
19567 | #define CP_HQD_QUANTUM__QUANTUM_DURATION_MASK 0x00003F00L |
19568 | #define CP_HQD_QUANTUM__QUANTUM_ACTIVE_MASK 0x80000000L |
19569 | //CP_HQD_PQ_BASE |
19570 | #define CP_HQD_PQ_BASE__ADDR__SHIFT 0x0 |
19571 | #define CP_HQD_PQ_BASE__ADDR_MASK 0xFFFFFFFFL |
19572 | //CP_HQD_PQ_BASE_HI |
19573 | #define CP_HQD_PQ_BASE_HI__ADDR_HI__SHIFT 0x0 |
19574 | #define CP_HQD_PQ_BASE_HI__ADDR_HI_MASK 0x000000FFL |
19575 | //CP_HQD_PQ_RPTR |
19576 | #define CP_HQD_PQ_RPTR__CONSUMED_OFFSET__SHIFT 0x0 |
19577 | #define CP_HQD_PQ_RPTR__CONSUMED_OFFSET_MASK 0xFFFFFFFFL |
19578 | //CP_HQD_PQ_RPTR_REPORT_ADDR |
19579 | #define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR__SHIFT 0x2 |
19580 | #define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR_MASK 0xFFFFFFFCL |
19581 | //CP_HQD_PQ_RPTR_REPORT_ADDR_HI |
19582 | #define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI__SHIFT 0x0 |
19583 | #define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI_MASK 0x0000FFFFL |
19584 | //CP_HQD_PQ_WPTR_POLL_ADDR |
19585 | #define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR__SHIFT 0x3 |
19586 | #define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR_MASK 0xFFFFFFF8L |
19587 | //CP_HQD_PQ_WPTR_POLL_ADDR_HI |
19588 | #define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI__SHIFT 0x0 |
19589 | #define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI_MASK 0x0000FFFFL |
19590 | //CP_HQD_PQ_DOORBELL_CONTROL |
19591 | #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE__SHIFT 0x0 |
19592 | #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT 0x1 |
19593 | #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x2 |
19594 | #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE__SHIFT 0x1c |
19595 | #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT__SHIFT 0x1d |
19596 | #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN__SHIFT 0x1e |
19597 | #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT 0x1f |
19598 | #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE_MASK 0x00000001L |
19599 | #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP_MASK 0x00000002L |
19600 | #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x0FFFFFFCL |
19601 | #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE_MASK 0x10000000L |
19602 | #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT_MASK 0x20000000L |
19603 | #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK 0x40000000L |
19604 | #define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT_MASK 0x80000000L |
19605 | //CP_HQD_PQ_CONTROL |
19606 | #define CP_HQD_PQ_CONTROL__QUEUE_SIZE__SHIFT 0x0 |
19607 | #define CP_HQD_PQ_CONTROL__WPTR_CARRY__SHIFT 0x6 |
19608 | #define CP_HQD_PQ_CONTROL__RPTR_CARRY__SHIFT 0x7 |
19609 | #define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT 0x8 |
19610 | #define CP_HQD_PQ_CONTROL__QUEUE_FULL_EN__SHIFT 0xe |
19611 | #define CP_HQD_PQ_CONTROL__PQ_EMPTY__SHIFT 0xf |
19612 | #define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT 0x12 |
19613 | #define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE__SHIFT 0x14 |
19614 | #define CP_HQD_PQ_CONTROL__TMZ__SHIFT 0x16 |
19615 | #define CP_HQD_PQ_CONTROL__EXE_DISABLE__SHIFT 0x17 |
19616 | #define CP_HQD_PQ_CONTROL__CACHE_POLICY__SHIFT 0x18 |
19617 | #define CP_HQD_PQ_CONTROL__PQ_VOLATILE__SHIFT 0x1a |
19618 | #define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR__SHIFT 0x1b |
19619 | #define CP_HQD_PQ_CONTROL__UNORD_DISPATCH__SHIFT 0x1c |
19620 | #define CP_HQD_PQ_CONTROL__TUNNEL_DISPATCH__SHIFT 0x1d |
19621 | #define CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT 0x1e |
19622 | #define CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT 0x1f |
19623 | #define CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK 0x0000003FL |
19624 | #define CP_HQD_PQ_CONTROL__WPTR_CARRY_MASK 0x00000040L |
19625 | #define CP_HQD_PQ_CONTROL__RPTR_CARRY_MASK 0x00000080L |
19626 | #define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK 0x00003F00L |
19627 | #define CP_HQD_PQ_CONTROL__QUEUE_FULL_EN_MASK 0x00004000L |
19628 | #define CP_HQD_PQ_CONTROL__PQ_EMPTY_MASK 0x00008000L |
19629 | #define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR_MASK 0x000C0000L |
19630 | #define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE_MASK 0x00300000L |
19631 | #define CP_HQD_PQ_CONTROL__TMZ_MASK 0x00400000L |
19632 | #define CP_HQD_PQ_CONTROL__EXE_DISABLE_MASK 0x00800000L |
19633 | #define CP_HQD_PQ_CONTROL__CACHE_POLICY_MASK 0x03000000L |
19634 | #define CP_HQD_PQ_CONTROL__PQ_VOLATILE_MASK 0x04000000L |
19635 | #define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK 0x08000000L |
19636 | #define CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK 0x10000000L |
19637 | #define CP_HQD_PQ_CONTROL__TUNNEL_DISPATCH_MASK 0x20000000L |
19638 | #define CP_HQD_PQ_CONTROL__PRIV_STATE_MASK 0x40000000L |
19639 | #define CP_HQD_PQ_CONTROL__KMD_QUEUE_MASK 0x80000000L |
19640 | //CP_HQD_IB_BASE_ADDR |
19641 | #define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR__SHIFT 0x2 |
19642 | #define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR_MASK 0xFFFFFFFCL |
19643 | //CP_HQD_IB_BASE_ADDR_HI |
19644 | #define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI__SHIFT 0x0 |
19645 | #define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI_MASK 0x0000FFFFL |
19646 | //CP_HQD_IB_RPTR |
19647 | #define CP_HQD_IB_RPTR__CONSUMED_OFFSET__SHIFT 0x0 |
19648 | #define CP_HQD_IB_RPTR__CONSUMED_OFFSET_MASK 0x000FFFFFL |
19649 | //CP_HQD_IB_CONTROL |
19650 | #define CP_HQD_IB_CONTROL__IB_SIZE__SHIFT 0x0 |
19651 | #define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT 0x14 |
19652 | #define CP_HQD_IB_CONTROL__IB_EXE_DISABLE__SHIFT 0x17 |
19653 | #define CP_HQD_IB_CONTROL__IB_CACHE_POLICY__SHIFT 0x18 |
19654 | #define CP_HQD_IB_CONTROL__IB_VOLATILE__SHIFT 0x1a |
19655 | #define CP_HQD_IB_CONTROL__IB_PRIV_STATE__SHIFT 0x1e |
19656 | #define CP_HQD_IB_CONTROL__PROCESSING_IB__SHIFT 0x1f |
19657 | #define CP_HQD_IB_CONTROL__IB_SIZE_MASK 0x000FFFFFL |
19658 | #define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE_MASK 0x00300000L |
19659 | #define CP_HQD_IB_CONTROL__IB_EXE_DISABLE_MASK 0x00800000L |
19660 | #define CP_HQD_IB_CONTROL__IB_CACHE_POLICY_MASK 0x03000000L |
19661 | #define CP_HQD_IB_CONTROL__IB_VOLATILE_MASK 0x04000000L |
19662 | #define CP_HQD_IB_CONTROL__IB_PRIV_STATE_MASK 0x40000000L |
19663 | #define CP_HQD_IB_CONTROL__PROCESSING_IB_MASK 0x80000000L |
19664 | //CP_HQD_IQ_TIMER |
19665 | #define CP_HQD_IQ_TIMER__WAIT_TIME__SHIFT 0x0 |
19666 | #define CP_HQD_IQ_TIMER__RETRY_TYPE__SHIFT 0x8 |
19667 | #define CP_HQD_IQ_TIMER__IMMEDIATE_EXPIRE__SHIFT 0xb |
19668 | #define CP_HQD_IQ_TIMER__INTERRUPT_TYPE__SHIFT 0xc |
19669 | #define CP_HQD_IQ_TIMER__CLOCK_COUNT__SHIFT 0xe |
19670 | #define CP_HQD_IQ_TIMER__INTERRUPT_SIZE__SHIFT 0x10 |
19671 | #define CP_HQD_IQ_TIMER__QUANTUM_TIMER__SHIFT 0x16 |
19672 | #define CP_HQD_IQ_TIMER__EXE_DISABLE__SHIFT 0x17 |
19673 | #define CP_HQD_IQ_TIMER__CACHE_POLICY__SHIFT 0x18 |
19674 | #define CP_HQD_IQ_TIMER__IQ_VOLATILE__SHIFT 0x1a |
19675 | #define CP_HQD_IQ_TIMER__QUEUE_TYPE__SHIFT 0x1b |
19676 | #define CP_HQD_IQ_TIMER__REARM_TIMER__SHIFT 0x1c |
19677 | #define CP_HQD_IQ_TIMER__PROCESS_IQ_EN__SHIFT 0x1d |
19678 | #define CP_HQD_IQ_TIMER__PROCESSING_IQ__SHIFT 0x1e |
19679 | #define CP_HQD_IQ_TIMER__ACTIVE__SHIFT 0x1f |
19680 | #define CP_HQD_IQ_TIMER__WAIT_TIME_MASK 0x000000FFL |
19681 | #define CP_HQD_IQ_TIMER__RETRY_TYPE_MASK 0x00000700L |
19682 | #define CP_HQD_IQ_TIMER__IMMEDIATE_EXPIRE_MASK 0x00000800L |
19683 | #define CP_HQD_IQ_TIMER__INTERRUPT_TYPE_MASK 0x00003000L |
19684 | #define CP_HQD_IQ_TIMER__CLOCK_COUNT_MASK 0x0000C000L |
19685 | #define CP_HQD_IQ_TIMER__INTERRUPT_SIZE_MASK 0x003F0000L |
19686 | #define CP_HQD_IQ_TIMER__QUANTUM_TIMER_MASK 0x00400000L |
19687 | #define CP_HQD_IQ_TIMER__EXE_DISABLE_MASK 0x00800000L |
19688 | #define CP_HQD_IQ_TIMER__CACHE_POLICY_MASK 0x03000000L |
19689 | #define CP_HQD_IQ_TIMER__IQ_VOLATILE_MASK 0x04000000L |
19690 | #define CP_HQD_IQ_TIMER__QUEUE_TYPE_MASK 0x08000000L |
19691 | #define CP_HQD_IQ_TIMER__REARM_TIMER_MASK 0x10000000L |
19692 | #define CP_HQD_IQ_TIMER__PROCESS_IQ_EN_MASK 0x20000000L |
19693 | #define CP_HQD_IQ_TIMER__PROCESSING_IQ_MASK 0x40000000L |
19694 | #define CP_HQD_IQ_TIMER__ACTIVE_MASK 0x80000000L |
19695 | //CP_HQD_IQ_RPTR |
19696 | #define CP_HQD_IQ_RPTR__OFFSET__SHIFT 0x0 |
19697 | #define CP_HQD_IQ_RPTR__OFFSET_MASK 0x0000003FL |
19698 | //CP_HQD_DEQUEUE_REQUEST |
19699 | #define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ__SHIFT 0x0 |
19700 | #define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND__SHIFT 0x4 |
19701 | #define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT__SHIFT 0x8 |
19702 | #define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN__SHIFT 0x9 |
19703 | #define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN__SHIFT 0xa |
19704 | #define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_MASK 0x0000000FL |
19705 | #define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK 0x00000010L |
19706 | #define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT_MASK 0x00000100L |
19707 | #define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN_MASK 0x00000200L |
19708 | #define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN_MASK 0x00000400L |
19709 | //CP_HQD_DMA_OFFLOAD |
19710 | #define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD__SHIFT 0x0 |
19711 | #define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD_EN__SHIFT 0x1 |
19712 | #define CP_HQD_DMA_OFFLOAD__AQL_OFFLOAD__SHIFT 0x2 |
19713 | #define CP_HQD_DMA_OFFLOAD__AQL_OFFLOAD_EN__SHIFT 0x3 |
19714 | #define CP_HQD_DMA_OFFLOAD__EOP_OFFLOAD__SHIFT 0x4 |
19715 | #define CP_HQD_DMA_OFFLOAD__EOP_OFFLOAD_EN__SHIFT 0x5 |
19716 | #define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD_MASK 0x00000001L |
19717 | #define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD_EN_MASK 0x00000002L |
19718 | #define CP_HQD_DMA_OFFLOAD__AQL_OFFLOAD_MASK 0x00000004L |
19719 | #define CP_HQD_DMA_OFFLOAD__AQL_OFFLOAD_EN_MASK 0x00000008L |
19720 | #define CP_HQD_DMA_OFFLOAD__EOP_OFFLOAD_MASK 0x00000010L |
19721 | #define CP_HQD_DMA_OFFLOAD__EOP_OFFLOAD_EN_MASK 0x00000020L |
19722 | //CP_HQD_OFFLOAD |
19723 | #define CP_HQD_OFFLOAD__DMA_OFFLOAD__SHIFT 0x0 |
19724 | #define CP_HQD_OFFLOAD__DMA_OFFLOAD_EN__SHIFT 0x1 |
19725 | #define CP_HQD_OFFLOAD__AQL_OFFLOAD__SHIFT 0x2 |
19726 | #define CP_HQD_OFFLOAD__AQL_OFFLOAD_EN__SHIFT 0x3 |
19727 | #define CP_HQD_OFFLOAD__EOP_OFFLOAD__SHIFT 0x4 |
19728 | #define CP_HQD_OFFLOAD__EOP_OFFLOAD_EN__SHIFT 0x5 |
19729 | #define CP_HQD_OFFLOAD__DMA_OFFLOAD_MASK 0x00000001L |
19730 | #define CP_HQD_OFFLOAD__DMA_OFFLOAD_EN_MASK 0x00000002L |
19731 | #define CP_HQD_OFFLOAD__AQL_OFFLOAD_MASK 0x00000004L |
19732 | #define CP_HQD_OFFLOAD__AQL_OFFLOAD_EN_MASK 0x00000008L |
19733 | #define CP_HQD_OFFLOAD__EOP_OFFLOAD_MASK 0x00000010L |
19734 | #define CP_HQD_OFFLOAD__EOP_OFFLOAD_EN_MASK 0x00000020L |
19735 | //CP_HQD_SEMA_CMD |
19736 | #define CP_HQD_SEMA_CMD__RETRY__SHIFT 0x0 |
19737 | #define CP_HQD_SEMA_CMD__RESULT__SHIFT 0x1 |
19738 | #define CP_HQD_SEMA_CMD__POLLING_DIS__SHIFT 0x8 |
19739 | #define CP_HQD_SEMA_CMD__MESSAGE_EN__SHIFT 0x9 |
19740 | #define CP_HQD_SEMA_CMD__RETRY_MASK 0x00000001L |
19741 | #define CP_HQD_SEMA_CMD__RESULT_MASK 0x00000006L |
19742 | #define CP_HQD_SEMA_CMD__POLLING_DIS_MASK 0x00000100L |
19743 | #define CP_HQD_SEMA_CMD__MESSAGE_EN_MASK 0x00000200L |
19744 | //CP_HQD_MSG_TYPE |
19745 | #define CP_HQD_MSG_TYPE__ACTION__SHIFT 0x0 |
19746 | #define CP_HQD_MSG_TYPE__SAVE_STATE__SHIFT 0x4 |
19747 | #define CP_HQD_MSG_TYPE__ACTION_MASK 0x00000007L |
19748 | #define CP_HQD_MSG_TYPE__SAVE_STATE_MASK 0x00000070L |
19749 | //CP_HQD_ATOMIC0_PREOP_LO |
19750 | #define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO__SHIFT 0x0 |
19751 | #define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO_MASK 0xFFFFFFFFL |
19752 | //CP_HQD_ATOMIC0_PREOP_HI |
19753 | #define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI__SHIFT 0x0 |
19754 | #define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI_MASK 0xFFFFFFFFL |
19755 | //CP_HQD_ATOMIC1_PREOP_LO |
19756 | #define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO__SHIFT 0x0 |
19757 | #define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO_MASK 0xFFFFFFFFL |
19758 | //CP_HQD_ATOMIC1_PREOP_HI |
19759 | #define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI__SHIFT 0x0 |
19760 | #define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI_MASK 0xFFFFFFFFL |
19761 | //CP_HQD_HQ_SCHEDULER0 |
19762 | #define CP_HQD_HQ_SCHEDULER0__CWSR__SHIFT 0x0 |
19763 | #define CP_HQD_HQ_SCHEDULER0__SAVE_STATUS__SHIFT 0x1 |
19764 | #define CP_HQD_HQ_SCHEDULER0__RSRV__SHIFT 0x2 |
19765 | #define CP_HQD_HQ_SCHEDULER0__STATIC_QUEUE__SHIFT 0x3 |
19766 | #define CP_HQD_HQ_SCHEDULER0__QUEUE_RUN_ONCE__SHIFT 0x6 |
19767 | #define CP_HQD_HQ_SCHEDULER0__SCRATCH_RAM_INIT__SHIFT 0x7 |
19768 | #define CP_HQD_HQ_SCHEDULER0__TCL2_DIRTY__SHIFT 0x8 |
19769 | #define CP_HQD_HQ_SCHEDULER0__C_INHERIT_VMID__SHIFT 0x9 |
19770 | #define CP_HQD_HQ_SCHEDULER0__QUEUE_SCHEDULER_TYPE__SHIFT 0xa |
19771 | #define CP_HQD_HQ_SCHEDULER0__C_QUEUE_USE_GWS__SHIFT 0xd |
19772 | #define CP_HQD_HQ_SCHEDULER0__C_QUEUE_DEBUG_EN__SHIFT 0xe |
19773 | #define CP_HQD_HQ_SCHEDULER0__QUEUE_SLOT_CONNECTED__SHIFT 0xf |
19774 | #define CP_HQD_HQ_SCHEDULER0__MES_INTERRUPT_ENABLED__SHIFT 0x14 |
19775 | #define CP_HQD_HQ_SCHEDULER0__MES_INTERRUPT_PIPE__SHIFT 0x15 |
19776 | #define CP_HQD_HQ_SCHEDULER0__CONCURRENT_PROCESS_COUNT__SHIFT 0x18 |
19777 | #define CP_HQD_HQ_SCHEDULER0__QUEUE_IDLE__SHIFT 0x1e |
19778 | #define CP_HQD_HQ_SCHEDULER0__DB_UPDATED_MSG_EN__SHIFT 0x1f |
19779 | #define CP_HQD_HQ_SCHEDULER0__CWSR_MASK 0x00000001L |
19780 | #define CP_HQD_HQ_SCHEDULER0__SAVE_STATUS_MASK 0x00000002L |
19781 | #define CP_HQD_HQ_SCHEDULER0__RSRV_MASK 0x00000004L |
19782 | #define CP_HQD_HQ_SCHEDULER0__STATIC_QUEUE_MASK 0x00000038L |
19783 | #define CP_HQD_HQ_SCHEDULER0__QUEUE_RUN_ONCE_MASK 0x00000040L |
19784 | #define CP_HQD_HQ_SCHEDULER0__SCRATCH_RAM_INIT_MASK 0x00000080L |
19785 | #define CP_HQD_HQ_SCHEDULER0__TCL2_DIRTY_MASK 0x00000100L |
19786 | #define CP_HQD_HQ_SCHEDULER0__C_INHERIT_VMID_MASK 0x00000200L |
19787 | #define CP_HQD_HQ_SCHEDULER0__QUEUE_SCHEDULER_TYPE_MASK 0x00001C00L |
19788 | #define CP_HQD_HQ_SCHEDULER0__C_QUEUE_USE_GWS_MASK 0x00002000L |
19789 | #define CP_HQD_HQ_SCHEDULER0__C_QUEUE_DEBUG_EN_MASK 0x00004000L |
19790 | #define CP_HQD_HQ_SCHEDULER0__QUEUE_SLOT_CONNECTED_MASK 0x00008000L |
19791 | #define CP_HQD_HQ_SCHEDULER0__MES_INTERRUPT_ENABLED_MASK 0x00100000L |
19792 | #define CP_HQD_HQ_SCHEDULER0__MES_INTERRUPT_PIPE_MASK 0x00600000L |
19793 | #define CP_HQD_HQ_SCHEDULER0__CONCURRENT_PROCESS_COUNT_MASK 0x0F000000L |
19794 | #define CP_HQD_HQ_SCHEDULER0__QUEUE_IDLE_MASK 0x40000000L |
19795 | #define CP_HQD_HQ_SCHEDULER0__DB_UPDATED_MSG_EN_MASK 0x80000000L |
19796 | //CP_HQD_HQ_STATUS0 |
19797 | #define CP_HQD_HQ_STATUS0__CWSR__SHIFT 0x0 |
19798 | #define CP_HQD_HQ_STATUS0__SAVE_STATUS__SHIFT 0x1 |
19799 | #define CP_HQD_HQ_STATUS0__RSRV__SHIFT 0x2 |
19800 | #define CP_HQD_HQ_STATUS0__STATIC_QUEUE__SHIFT 0x3 |
19801 | #define CP_HQD_HQ_STATUS0__QUEUE_RUN_ONCE__SHIFT 0x6 |
19802 | #define CP_HQD_HQ_STATUS0__SCRATCH_RAM_INIT__SHIFT 0x7 |
19803 | #define CP_HQD_HQ_STATUS0__TCL2_DIRTY__SHIFT 0x8 |
19804 | #define CP_HQD_HQ_STATUS0__C_INHERIT_VMID__SHIFT 0x9 |
19805 | #define CP_HQD_HQ_STATUS0__QUEUE_SCHEDULER_TYPE__SHIFT 0xa |
19806 | #define CP_HQD_HQ_STATUS0__C_QUEUE_USE_GWS__SHIFT 0xd |
19807 | #define CP_HQD_HQ_STATUS0__C_QUEUE_DEBUG_EN__SHIFT 0xe |
19808 | #define CP_HQD_HQ_STATUS0__QUEUE_SLOT_CONNECTED__SHIFT 0xf |
19809 | #define CP_HQD_HQ_STATUS0__MES_INTERRUPT_ENABLED__SHIFT 0x14 |
19810 | #define CP_HQD_HQ_STATUS0__MES_INTERRUPT_PIPE__SHIFT 0x15 |
19811 | #define CP_HQD_HQ_STATUS0__CONCURRENT_PROCESS_COUNT__SHIFT 0x18 |
19812 | #define CP_HQD_HQ_STATUS0__QUEUE_IDLE__SHIFT 0x1e |
19813 | #define CP_HQD_HQ_STATUS0__DB_UPDATED_MSG_EN__SHIFT 0x1f |
19814 | #define CP_HQD_HQ_STATUS0__CWSR_MASK 0x00000001L |
19815 | #define CP_HQD_HQ_STATUS0__SAVE_STATUS_MASK 0x00000002L |
19816 | #define CP_HQD_HQ_STATUS0__RSRV_MASK 0x00000004L |
19817 | #define CP_HQD_HQ_STATUS0__STATIC_QUEUE_MASK 0x00000038L |
19818 | #define CP_HQD_HQ_STATUS0__QUEUE_RUN_ONCE_MASK 0x00000040L |
19819 | #define CP_HQD_HQ_STATUS0__SCRATCH_RAM_INIT_MASK 0x00000080L |
19820 | #define CP_HQD_HQ_STATUS0__TCL2_DIRTY_MASK 0x00000100L |
19821 | #define CP_HQD_HQ_STATUS0__C_INHERIT_VMID_MASK 0x00000200L |
19822 | #define CP_HQD_HQ_STATUS0__QUEUE_SCHEDULER_TYPE_MASK 0x00001C00L |
19823 | #define CP_HQD_HQ_STATUS0__C_QUEUE_USE_GWS_MASK 0x00002000L |
19824 | #define CP_HQD_HQ_STATUS0__C_QUEUE_DEBUG_EN_MASK 0x00004000L |
19825 | #define CP_HQD_HQ_STATUS0__QUEUE_SLOT_CONNECTED_MASK 0x00008000L |
19826 | #define CP_HQD_HQ_STATUS0__MES_INTERRUPT_ENABLED_MASK 0x00100000L |
19827 | #define CP_HQD_HQ_STATUS0__MES_INTERRUPT_PIPE_MASK 0x00600000L |
19828 | #define CP_HQD_HQ_STATUS0__CONCURRENT_PROCESS_COUNT_MASK 0x0F000000L |
19829 | #define CP_HQD_HQ_STATUS0__QUEUE_IDLE_MASK 0x40000000L |
19830 | #define CP_HQD_HQ_STATUS0__DB_UPDATED_MSG_EN_MASK 0x80000000L |
19831 | //CP_HQD_HQ_CONTROL0 |
19832 | #define CP_HQD_HQ_CONTROL0__CONTROL__SHIFT 0x0 |
19833 | #define CP_HQD_HQ_CONTROL0__CONTROL_MASK 0xFFFFFFFFL |
19834 | //CP_HQD_HQ_SCHEDULER1 |
19835 | #define CP_HQD_HQ_SCHEDULER1__SCHEDULER__SHIFT 0x0 |
19836 | #define CP_HQD_HQ_SCHEDULER1__SCHEDULER_MASK 0xFFFFFFFFL |
19837 | //CP_MQD_CONTROL |
19838 | #define CP_MQD_CONTROL__VMID__SHIFT 0x0 |
19839 | #define CP_MQD_CONTROL__PRIV_STATE__SHIFT 0x8 |
19840 | #define CP_MQD_CONTROL__PROCESSING_MQD__SHIFT 0xc |
19841 | #define CP_MQD_CONTROL__PROCESSING_MQD_EN__SHIFT 0xd |
19842 | #define CP_MQD_CONTROL__EXE_DISABLE__SHIFT 0x17 |
19843 | #define CP_MQD_CONTROL__CACHE_POLICY__SHIFT 0x18 |
19844 | #define CP_MQD_CONTROL__MQD_VOLATILE__SHIFT 0x1a |
19845 | #define CP_MQD_CONTROL__VMID_MASK 0x0000000FL |
19846 | #define CP_MQD_CONTROL__PRIV_STATE_MASK 0x00000100L |
19847 | #define CP_MQD_CONTROL__PROCESSING_MQD_MASK 0x00001000L |
19848 | #define CP_MQD_CONTROL__PROCESSING_MQD_EN_MASK 0x00002000L |
19849 | #define CP_MQD_CONTROL__EXE_DISABLE_MASK 0x00800000L |
19850 | #define CP_MQD_CONTROL__CACHE_POLICY_MASK 0x03000000L |
19851 | #define CP_MQD_CONTROL__MQD_VOLATILE_MASK 0x04000000L |
19852 | //CP_HQD_HQ_STATUS1 |
19853 | #define CP_HQD_HQ_STATUS1__STATUS__SHIFT 0x0 |
19854 | #define CP_HQD_HQ_STATUS1__STATUS_MASK 0xFFFFFFFFL |
19855 | //CP_HQD_HQ_CONTROL1 |
19856 | #define CP_HQD_HQ_CONTROL1__CONTROL__SHIFT 0x0 |
19857 | #define CP_HQD_HQ_CONTROL1__CONTROL_MASK 0xFFFFFFFFL |
19858 | //CP_HQD_EOP_BASE_ADDR |
19859 | #define CP_HQD_EOP_BASE_ADDR__BASE_ADDR__SHIFT 0x0 |
19860 | #define CP_HQD_EOP_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL |
19861 | //CP_HQD_EOP_BASE_ADDR_HI |
19862 | #define CP_HQD_EOP_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 |
19863 | #define CP_HQD_EOP_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0x000000FFL |
19864 | //CP_HQD_EOP_CONTROL |
19865 | #define CP_HQD_EOP_CONTROL__EOP_SIZE__SHIFT 0x0 |
19866 | #define CP_HQD_EOP_CONTROL__PROCESSING_EOP__SHIFT 0x8 |
19867 | #define CP_HQD_EOP_CONTROL__PROCESS_EOP_EN__SHIFT 0xc |
19868 | #define CP_HQD_EOP_CONTROL__PROCESSING_EOPIB__SHIFT 0xd |
19869 | #define CP_HQD_EOP_CONTROL__PROCESS_EOPIB_EN__SHIFT 0xe |
19870 | #define CP_HQD_EOP_CONTROL__HALT_FETCHER__SHIFT 0x15 |
19871 | #define CP_HQD_EOP_CONTROL__HALT_FETCHER_EN__SHIFT 0x16 |
19872 | #define CP_HQD_EOP_CONTROL__EXE_DISABLE__SHIFT 0x17 |
19873 | #define CP_HQD_EOP_CONTROL__CACHE_POLICY__SHIFT 0x18 |
19874 | #define CP_HQD_EOP_CONTROL__EOP_VOLATILE__SHIFT 0x1a |
19875 | #define CP_HQD_EOP_CONTROL__SIG_SEM_RESULT__SHIFT 0x1d |
19876 | #define CP_HQD_EOP_CONTROL__PEND_SIG_SEM__SHIFT 0x1f |
19877 | #define CP_HQD_EOP_CONTROL__EOP_SIZE_MASK 0x0000003FL |
19878 | #define CP_HQD_EOP_CONTROL__PROCESSING_EOP_MASK 0x00000100L |
19879 | #define CP_HQD_EOP_CONTROL__PROCESS_EOP_EN_MASK 0x00001000L |
19880 | #define CP_HQD_EOP_CONTROL__PROCESSING_EOPIB_MASK 0x00002000L |
19881 | #define CP_HQD_EOP_CONTROL__PROCESS_EOPIB_EN_MASK 0x00004000L |
19882 | #define CP_HQD_EOP_CONTROL__HALT_FETCHER_MASK 0x00200000L |
19883 | #define CP_HQD_EOP_CONTROL__HALT_FETCHER_EN_MASK 0x00400000L |
19884 | #define CP_HQD_EOP_CONTROL__EXE_DISABLE_MASK 0x00800000L |
19885 | #define CP_HQD_EOP_CONTROL__CACHE_POLICY_MASK 0x03000000L |
19886 | #define CP_HQD_EOP_CONTROL__EOP_VOLATILE_MASK 0x04000000L |
19887 | #define CP_HQD_EOP_CONTROL__SIG_SEM_RESULT_MASK 0x60000000L |
19888 | #define CP_HQD_EOP_CONTROL__PEND_SIG_SEM_MASK 0x80000000L |
19889 | //CP_HQD_EOP_RPTR |
19890 | #define CP_HQD_EOP_RPTR__RPTR__SHIFT 0x0 |
19891 | #define CP_HQD_EOP_RPTR__RESET_FETCHER__SHIFT 0x1c |
19892 | #define CP_HQD_EOP_RPTR__DEQUEUE_PEND__SHIFT 0x1d |
19893 | #define CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR__SHIFT 0x1e |
19894 | #define CP_HQD_EOP_RPTR__INIT_FETCHER__SHIFT 0x1f |
19895 | #define CP_HQD_EOP_RPTR__RPTR_MASK 0x00001FFFL |
19896 | #define CP_HQD_EOP_RPTR__RESET_FETCHER_MASK 0x10000000L |
19897 | #define CP_HQD_EOP_RPTR__DEQUEUE_PEND_MASK 0x20000000L |
19898 | #define CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR_MASK 0x40000000L |
19899 | #define CP_HQD_EOP_RPTR__INIT_FETCHER_MASK 0x80000000L |
19900 | //CP_HQD_EOP_WPTR |
19901 | #define CP_HQD_EOP_WPTR__WPTR__SHIFT 0x0 |
19902 | #define CP_HQD_EOP_WPTR__EOP_EMPTY__SHIFT 0xf |
19903 | #define CP_HQD_EOP_WPTR__EOP_AVAIL__SHIFT 0x10 |
19904 | #define CP_HQD_EOP_WPTR__WPTR_MASK 0x00001FFFL |
19905 | #define CP_HQD_EOP_WPTR__EOP_EMPTY_MASK 0x00008000L |
19906 | #define CP_HQD_EOP_WPTR__EOP_AVAIL_MASK 0x1FFF0000L |
19907 | //CP_HQD_EOP_EVENTS |
19908 | #define CP_HQD_EOP_EVENTS__EVENT_COUNT__SHIFT 0x0 |
19909 | #define CP_HQD_EOP_EVENTS__CS_PARTIAL_FLUSH_PEND__SHIFT 0x10 |
19910 | #define CP_HQD_EOP_EVENTS__EVENT_COUNT_MASK 0x00000FFFL |
19911 | #define CP_HQD_EOP_EVENTS__CS_PARTIAL_FLUSH_PEND_MASK 0x00010000L |
19912 | //CP_HQD_CTX_SAVE_BASE_ADDR_LO |
19913 | #define CP_HQD_CTX_SAVE_BASE_ADDR_LO__ADDR__SHIFT 0xc |
19914 | #define CP_HQD_CTX_SAVE_BASE_ADDR_LO__ADDR_MASK 0xFFFFF000L |
19915 | //CP_HQD_CTX_SAVE_BASE_ADDR_HI |
19916 | #define CP_HQD_CTX_SAVE_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0 |
19917 | #define CP_HQD_CTX_SAVE_BASE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL |
19918 | //CP_HQD_CTX_SAVE_CONTROL |
19919 | #define CP_HQD_CTX_SAVE_CONTROL__POLICY__SHIFT 0x3 |
19920 | #define CP_HQD_CTX_SAVE_CONTROL__EXE_DISABLE__SHIFT 0x17 |
19921 | #define CP_HQD_CTX_SAVE_CONTROL__POLICY_MASK 0x00000018L |
19922 | #define CP_HQD_CTX_SAVE_CONTROL__EXE_DISABLE_MASK 0x00800000L |
19923 | //CP_HQD_CNTL_STACK_OFFSET |
19924 | #define CP_HQD_CNTL_STACK_OFFSET__OFFSET__SHIFT 0x2 |
19925 | #define CP_HQD_CNTL_STACK_OFFSET__OFFSET_MASK 0x0000FFFCL |
19926 | //CP_HQD_CNTL_STACK_SIZE |
19927 | #define CP_HQD_CNTL_STACK_SIZE__SIZE__SHIFT 0xc |
19928 | #define CP_HQD_CNTL_STACK_SIZE__SIZE_MASK 0x0000F000L |
19929 | //CP_HQD_WG_STATE_OFFSET |
19930 | #define CP_HQD_WG_STATE_OFFSET__OFFSET__SHIFT 0x2 |
19931 | #define CP_HQD_WG_STATE_OFFSET__OFFSET_MASK 0x03FFFFFCL |
19932 | //CP_HQD_CTX_SAVE_SIZE |
19933 | #define CP_HQD_CTX_SAVE_SIZE__SIZE__SHIFT 0xc |
19934 | #define CP_HQD_CTX_SAVE_SIZE__SIZE_MASK 0x03FFF000L |
19935 | //CP_HQD_GDS_RESOURCE_STATE |
19936 | #define CP_HQD_GDS_RESOURCE_STATE__OA_REQUIRED__SHIFT 0x0 |
19937 | #define CP_HQD_GDS_RESOURCE_STATE__OA_ACQUIRED__SHIFT 0x1 |
19938 | #define CP_HQD_GDS_RESOURCE_STATE__GWS_SIZE__SHIFT 0x4 |
19939 | #define CP_HQD_GDS_RESOURCE_STATE__GWS_PNTR__SHIFT 0xc |
19940 | #define CP_HQD_GDS_RESOURCE_STATE__OA_REQUIRED_MASK 0x00000001L |
19941 | #define CP_HQD_GDS_RESOURCE_STATE__OA_ACQUIRED_MASK 0x00000002L |
19942 | #define CP_HQD_GDS_RESOURCE_STATE__GWS_SIZE_MASK 0x000003F0L |
19943 | #define CP_HQD_GDS_RESOURCE_STATE__GWS_PNTR_MASK 0x0003F000L |
19944 | //CP_HQD_ERROR |
19945 | #define CP_HQD_ERROR__EDC_ERROR_ID__SHIFT 0x0 |
19946 | #define CP_HQD_ERROR__SUA_ERROR__SHIFT 0x4 |
19947 | #define CP_HQD_ERROR__AQL_ERROR__SHIFT 0x5 |
19948 | #define CP_HQD_ERROR__PQ_UTCL1_ERROR__SHIFT 0x8 |
19949 | #define CP_HQD_ERROR__IB_UTCL1_ERROR__SHIFT 0x9 |
19950 | #define CP_HQD_ERROR__EOP_UTCL1_ERROR__SHIFT 0xa |
19951 | #define CP_HQD_ERROR__IQ_UTCL1_ERROR__SHIFT 0xb |
19952 | #define CP_HQD_ERROR__RRPT_UTCL1_ERROR__SHIFT 0xc |
19953 | #define CP_HQD_ERROR__WPP_UTCL1_ERROR__SHIFT 0xd |
19954 | #define CP_HQD_ERROR__SEM_UTCL1_ERROR__SHIFT 0xe |
19955 | #define CP_HQD_ERROR__DMA_SRC_UTCL1_ERROR__SHIFT 0xf |
19956 | #define CP_HQD_ERROR__DMA_DST_UTCL1_ERROR__SHIFT 0x10 |
19957 | #define CP_HQD_ERROR__SR_UTCL1_ERROR__SHIFT 0x11 |
19958 | #define CP_HQD_ERROR__QU_UTCL1_ERROR__SHIFT 0x12 |
19959 | #define CP_HQD_ERROR__TC_UTCL1_ERROR__SHIFT 0x13 |
19960 | #define CP_HQD_ERROR__EDC_ERROR_ID_MASK 0x0000000FL |
19961 | #define CP_HQD_ERROR__SUA_ERROR_MASK 0x00000010L |
19962 | #define CP_HQD_ERROR__AQL_ERROR_MASK 0x00000020L |
19963 | #define CP_HQD_ERROR__PQ_UTCL1_ERROR_MASK 0x00000100L |
19964 | #define CP_HQD_ERROR__IB_UTCL1_ERROR_MASK 0x00000200L |
19965 | #define CP_HQD_ERROR__EOP_UTCL1_ERROR_MASK 0x00000400L |
19966 | #define CP_HQD_ERROR__IQ_UTCL1_ERROR_MASK 0x00000800L |
19967 | #define CP_HQD_ERROR__RRPT_UTCL1_ERROR_MASK 0x00001000L |
19968 | #define CP_HQD_ERROR__WPP_UTCL1_ERROR_MASK 0x00002000L |
19969 | #define CP_HQD_ERROR__SEM_UTCL1_ERROR_MASK 0x00004000L |
19970 | #define CP_HQD_ERROR__DMA_SRC_UTCL1_ERROR_MASK 0x00008000L |
19971 | #define CP_HQD_ERROR__DMA_DST_UTCL1_ERROR_MASK 0x00010000L |
19972 | #define CP_HQD_ERROR__SR_UTCL1_ERROR_MASK 0x00020000L |
19973 | #define CP_HQD_ERROR__QU_UTCL1_ERROR_MASK 0x00040000L |
19974 | #define CP_HQD_ERROR__TC_UTCL1_ERROR_MASK 0x00080000L |
19975 | //CP_HQD_EOP_WPTR_MEM |
19976 | #define CP_HQD_EOP_WPTR_MEM__WPTR__SHIFT 0x0 |
19977 | #define CP_HQD_EOP_WPTR_MEM__WPTR_MASK 0x00001FFFL |
19978 | //CP_HQD_AQL_CONTROL |
19979 | #define CP_HQD_AQL_CONTROL__CONTROL0__SHIFT 0x0 |
19980 | #define CP_HQD_AQL_CONTROL__CONTROL0_EN__SHIFT 0xf |
19981 | #define CP_HQD_AQL_CONTROL__CONTROL1__SHIFT 0x10 |
19982 | #define CP_HQD_AQL_CONTROL__CONTROL1_EN__SHIFT 0x1f |
19983 | #define CP_HQD_AQL_CONTROL__CONTROL0_MASK 0x00007FFFL |
19984 | #define CP_HQD_AQL_CONTROL__CONTROL0_EN_MASK 0x00008000L |
19985 | #define CP_HQD_AQL_CONTROL__CONTROL1_MASK 0x7FFF0000L |
19986 | #define CP_HQD_AQL_CONTROL__CONTROL1_EN_MASK 0x80000000L |
19987 | //CP_HQD_PQ_WPTR_LO |
19988 | #define CP_HQD_PQ_WPTR_LO__OFFSET__SHIFT 0x0 |
19989 | #define CP_HQD_PQ_WPTR_LO__OFFSET_MASK 0xFFFFFFFFL |
19990 | //CP_HQD_PQ_WPTR_HI |
19991 | #define CP_HQD_PQ_WPTR_HI__DATA__SHIFT 0x0 |
19992 | #define CP_HQD_PQ_WPTR_HI__DATA_MASK 0xFFFFFFFFL |
19993 | //CP_HQD_SUSPEND_CNTL_STACK_OFFSET |
19994 | #define CP_HQD_SUSPEND_CNTL_STACK_OFFSET__OFFSET__SHIFT 0x2 |
19995 | #define CP_HQD_SUSPEND_CNTL_STACK_OFFSET__OFFSET_MASK 0x0000FFFCL |
19996 | //CP_HQD_SUSPEND_CNTL_STACK_DW_CNT |
19997 | #define CP_HQD_SUSPEND_CNTL_STACK_DW_CNT__CNT__SHIFT 0x0 |
19998 | #define CP_HQD_SUSPEND_CNTL_STACK_DW_CNT__CNT_MASK 0x00003FFFL |
19999 | //CP_HQD_SUSPEND_WG_STATE_OFFSET |
20000 | #define CP_HQD_SUSPEND_WG_STATE_OFFSET__OFFSET__SHIFT 0x2 |
20001 | #define CP_HQD_SUSPEND_WG_STATE_OFFSET__OFFSET_MASK 0x03FFFFFCL |
20002 | //CP_HQD_DDID_RPTR |
20003 | #define CP_HQD_DDID_RPTR__RPTR__SHIFT 0x0 |
20004 | #define CP_HQD_DDID_RPTR__RPTR_MASK 0x000007FFL |
20005 | //CP_HQD_DDID_WPTR |
20006 | #define CP_HQD_DDID_WPTR__WPTR__SHIFT 0x0 |
20007 | #define CP_HQD_DDID_WPTR__WPTR_MASK 0x000007FFL |
20008 | //CP_HQD_DDID_INFLIGHT_COUNT |
20009 | #define CP_HQD_DDID_INFLIGHT_COUNT__COUNT__SHIFT 0x0 |
20010 | #define CP_HQD_DDID_INFLIGHT_COUNT__COUNT_MASK 0x0000FFFFL |
20011 | //CP_HQD_DDID_DELTA_RPT_COUNT |
20012 | #define CP_HQD_DDID_DELTA_RPT_COUNT__COUNT__SHIFT 0x0 |
20013 | #define CP_HQD_DDID_DELTA_RPT_COUNT__COUNT_MASK 0x000000FFL |
20014 | //CP_HQD_DEQUEUE_STATUS |
20015 | #define CP_HQD_DEQUEUE_STATUS__DEQUEUE_STAT__SHIFT 0x0 |
20016 | #define CP_HQD_DEQUEUE_STATUS__SUSPEND_REQ_PEND__SHIFT 0x4 |
20017 | #define CP_HQD_DEQUEUE_STATUS__SUSPEND_REQ_PEND_EN__SHIFT 0x9 |
20018 | #define CP_HQD_DEQUEUE_STATUS__DEQUEUE_STAT_EN__SHIFT 0xa |
20019 | #define CP_HQD_DEQUEUE_STATUS__DEQUEUE_STAT_MASK 0x0000000FL |
20020 | #define CP_HQD_DEQUEUE_STATUS__SUSPEND_REQ_PEND_MASK 0x00000010L |
20021 | #define CP_HQD_DEQUEUE_STATUS__SUSPEND_REQ_PEND_EN_MASK 0x00000200L |
20022 | #define CP_HQD_DEQUEUE_STATUS__DEQUEUE_STAT_EN_MASK 0x00000400L |
20023 | |
20024 | |
20025 | // addressBlock: gc_tcpdec |
20026 | //TCP_WATCH0_ADDR_H |
20027 | #define TCP_WATCH0_ADDR_H__ADDR__SHIFT 0x0 |
20028 | #define TCP_WATCH0_ADDR_H__ADDR_MASK 0x0000FFFFL |
20029 | //TCP_WATCH0_ADDR_L |
20030 | #define TCP_WATCH0_ADDR_L__ADDR__SHIFT 0x7 |
20031 | #define TCP_WATCH0_ADDR_L__ADDR_MASK 0xFFFFFF80L |
20032 | //TCP_WATCH0_CNTL |
20033 | #define TCP_WATCH0_CNTL__MASK__SHIFT 0x0 |
20034 | #define TCP_WATCH0_CNTL__VMID__SHIFT 0x18 |
20035 | #define TCP_WATCH0_CNTL__MODE__SHIFT 0x1d |
20036 | #define TCP_WATCH0_CNTL__VALID__SHIFT 0x1f |
20037 | #define TCP_WATCH0_CNTL__MASK_MASK 0x007FFFFFL |
20038 | #define TCP_WATCH0_CNTL__VMID_MASK 0x0F000000L |
20039 | #define TCP_WATCH0_CNTL__MODE_MASK 0x60000000L |
20040 | #define TCP_WATCH0_CNTL__VALID_MASK 0x80000000L |
20041 | //TCP_WATCH1_ADDR_H |
20042 | #define TCP_WATCH1_ADDR_H__ADDR__SHIFT 0x0 |
20043 | #define TCP_WATCH1_ADDR_H__ADDR_MASK 0x0000FFFFL |
20044 | //TCP_WATCH1_ADDR_L |
20045 | #define TCP_WATCH1_ADDR_L__ADDR__SHIFT 0x7 |
20046 | #define TCP_WATCH1_ADDR_L__ADDR_MASK 0xFFFFFF80L |
20047 | //TCP_WATCH1_CNTL |
20048 | #define TCP_WATCH1_CNTL__MASK__SHIFT 0x0 |
20049 | #define TCP_WATCH1_CNTL__VMID__SHIFT 0x18 |
20050 | #define TCP_WATCH1_CNTL__MODE__SHIFT 0x1d |
20051 | #define TCP_WATCH1_CNTL__VALID__SHIFT 0x1f |
20052 | #define TCP_WATCH1_CNTL__MASK_MASK 0x007FFFFFL |
20053 | #define TCP_WATCH1_CNTL__VMID_MASK 0x0F000000L |
20054 | #define TCP_WATCH1_CNTL__MODE_MASK 0x60000000L |
20055 | #define TCP_WATCH1_CNTL__VALID_MASK 0x80000000L |
20056 | //TCP_WATCH2_ADDR_H |
20057 | #define TCP_WATCH2_ADDR_H__ADDR__SHIFT 0x0 |
20058 | #define TCP_WATCH2_ADDR_H__ADDR_MASK 0x0000FFFFL |
20059 | //TCP_WATCH2_ADDR_L |
20060 | #define TCP_WATCH2_ADDR_L__ADDR__SHIFT 0x7 |
20061 | #define TCP_WATCH2_ADDR_L__ADDR_MASK 0xFFFFFF80L |
20062 | //TCP_WATCH2_CNTL |
20063 | #define TCP_WATCH2_CNTL__MASK__SHIFT 0x0 |
20064 | #define TCP_WATCH2_CNTL__VMID__SHIFT 0x18 |
20065 | #define TCP_WATCH2_CNTL__MODE__SHIFT 0x1d |
20066 | #define TCP_WATCH2_CNTL__VALID__SHIFT 0x1f |
20067 | #define TCP_WATCH2_CNTL__MASK_MASK 0x007FFFFFL |
20068 | #define TCP_WATCH2_CNTL__VMID_MASK 0x0F000000L |
20069 | #define TCP_WATCH2_CNTL__MODE_MASK 0x60000000L |
20070 | #define TCP_WATCH2_CNTL__VALID_MASK 0x80000000L |
20071 | //TCP_WATCH3_ADDR_H |
20072 | #define TCP_WATCH3_ADDR_H__ADDR__SHIFT 0x0 |
20073 | #define TCP_WATCH3_ADDR_H__ADDR_MASK 0x0000FFFFL |
20074 | //TCP_WATCH3_ADDR_L |
20075 | #define TCP_WATCH3_ADDR_L__ADDR__SHIFT 0x7 |
20076 | #define TCP_WATCH3_ADDR_L__ADDR_MASK 0xFFFFFF80L |
20077 | //TCP_WATCH3_CNTL |
20078 | #define TCP_WATCH3_CNTL__MASK__SHIFT 0x0 |
20079 | #define TCP_WATCH3_CNTL__VMID__SHIFT 0x18 |
20080 | #define TCP_WATCH3_CNTL__MODE__SHIFT 0x1d |
20081 | #define TCP_WATCH3_CNTL__VALID__SHIFT 0x1f |
20082 | #define TCP_WATCH3_CNTL__MASK_MASK 0x007FFFFFL |
20083 | #define TCP_WATCH3_CNTL__VMID_MASK 0x0F000000L |
20084 | #define TCP_WATCH3_CNTL__MODE_MASK 0x60000000L |
20085 | #define TCP_WATCH3_CNTL__VALID_MASK 0x80000000L |
20086 | |
20087 | |
20088 | // addressBlock: gc_gdspdec |
20089 | //GDS_VMID0_BASE |
20090 | #define GDS_VMID0_BASE__BASE__SHIFT 0x0 |
20091 | #define GDS_VMID0_BASE__UNUSED__SHIFT 0x10 |
20092 | #define GDS_VMID0_BASE__BASE_MASK 0x0000FFFFL |
20093 | #define GDS_VMID0_BASE__UNUSED_MASK 0xFFFF0000L |
20094 | //GDS_VMID0_SIZE |
20095 | #define GDS_VMID0_SIZE__SIZE__SHIFT 0x0 |
20096 | #define GDS_VMID0_SIZE__UNUSED__SHIFT 0x11 |
20097 | #define GDS_VMID0_SIZE__SIZE_MASK 0x0001FFFFL |
20098 | #define GDS_VMID0_SIZE__UNUSED_MASK 0xFFFE0000L |
20099 | //GDS_VMID1_BASE |
20100 | #define GDS_VMID1_BASE__BASE__SHIFT 0x0 |
20101 | #define GDS_VMID1_BASE__UNUSED__SHIFT 0x10 |
20102 | #define GDS_VMID1_BASE__BASE_MASK 0x0000FFFFL |
20103 | #define GDS_VMID1_BASE__UNUSED_MASK 0xFFFF0000L |
20104 | //GDS_VMID1_SIZE |
20105 | #define GDS_VMID1_SIZE__SIZE__SHIFT 0x0 |
20106 | #define GDS_VMID1_SIZE__UNUSED__SHIFT 0x11 |
20107 | #define GDS_VMID1_SIZE__SIZE_MASK 0x0001FFFFL |
20108 | #define GDS_VMID1_SIZE__UNUSED_MASK 0xFFFE0000L |
20109 | //GDS_VMID2_BASE |
20110 | #define GDS_VMID2_BASE__BASE__SHIFT 0x0 |
20111 | #define GDS_VMID2_BASE__UNUSED__SHIFT 0x10 |
20112 | #define GDS_VMID2_BASE__BASE_MASK 0x0000FFFFL |
20113 | #define GDS_VMID2_BASE__UNUSED_MASK 0xFFFF0000L |
20114 | //GDS_VMID2_SIZE |
20115 | #define GDS_VMID2_SIZE__SIZE__SHIFT 0x0 |
20116 | #define GDS_VMID2_SIZE__UNUSED__SHIFT 0x11 |
20117 | #define GDS_VMID2_SIZE__SIZE_MASK 0x0001FFFFL |
20118 | #define GDS_VMID2_SIZE__UNUSED_MASK 0xFFFE0000L |
20119 | //GDS_VMID3_BASE |
20120 | #define GDS_VMID3_BASE__BASE__SHIFT 0x0 |
20121 | #define GDS_VMID3_BASE__UNUSED__SHIFT 0x10 |
20122 | #define GDS_VMID3_BASE__BASE_MASK 0x0000FFFFL |
20123 | #define GDS_VMID3_BASE__UNUSED_MASK 0xFFFF0000L |
20124 | //GDS_VMID3_SIZE |
20125 | #define GDS_VMID3_SIZE__SIZE__SHIFT 0x0 |
20126 | #define GDS_VMID3_SIZE__UNUSED__SHIFT 0x11 |
20127 | #define GDS_VMID3_SIZE__SIZE_MASK 0x0001FFFFL |
20128 | #define GDS_VMID3_SIZE__UNUSED_MASK 0xFFFE0000L |
20129 | //GDS_VMID4_BASE |
20130 | #define GDS_VMID4_BASE__BASE__SHIFT 0x0 |
20131 | #define GDS_VMID4_BASE__UNUSED__SHIFT 0x10 |
20132 | #define GDS_VMID4_BASE__BASE_MASK 0x0000FFFFL |
20133 | #define GDS_VMID4_BASE__UNUSED_MASK 0xFFFF0000L |
20134 | //GDS_VMID4_SIZE |
20135 | #define GDS_VMID4_SIZE__SIZE__SHIFT 0x0 |
20136 | #define GDS_VMID4_SIZE__UNUSED__SHIFT 0x11 |
20137 | #define GDS_VMID4_SIZE__SIZE_MASK 0x0001FFFFL |
20138 | #define GDS_VMID4_SIZE__UNUSED_MASK 0xFFFE0000L |
20139 | //GDS_VMID5_BASE |
20140 | #define GDS_VMID5_BASE__BASE__SHIFT 0x0 |
20141 | #define GDS_VMID5_BASE__UNUSED__SHIFT 0x10 |
20142 | #define GDS_VMID5_BASE__BASE_MASK 0x0000FFFFL |
20143 | #define GDS_VMID5_BASE__UNUSED_MASK 0xFFFF0000L |
20144 | //GDS_VMID5_SIZE |
20145 | #define GDS_VMID5_SIZE__SIZE__SHIFT 0x0 |
20146 | #define GDS_VMID5_SIZE__UNUSED__SHIFT 0x11 |
20147 | #define GDS_VMID5_SIZE__SIZE_MASK 0x0001FFFFL |
20148 | #define GDS_VMID5_SIZE__UNUSED_MASK 0xFFFE0000L |
20149 | //GDS_VMID6_BASE |
20150 | #define GDS_VMID6_BASE__BASE__SHIFT 0x0 |
20151 | #define GDS_VMID6_BASE__UNUSED__SHIFT 0x10 |
20152 | #define GDS_VMID6_BASE__BASE_MASK 0x0000FFFFL |
20153 | #define GDS_VMID6_BASE__UNUSED_MASK 0xFFFF0000L |
20154 | //GDS_VMID6_SIZE |
20155 | #define GDS_VMID6_SIZE__SIZE__SHIFT 0x0 |
20156 | #define GDS_VMID6_SIZE__UNUSED__SHIFT 0x11 |
20157 | #define GDS_VMID6_SIZE__SIZE_MASK 0x0001FFFFL |
20158 | #define GDS_VMID6_SIZE__UNUSED_MASK 0xFFFE0000L |
20159 | //GDS_VMID7_BASE |
20160 | #define GDS_VMID7_BASE__BASE__SHIFT 0x0 |
20161 | #define GDS_VMID7_BASE__UNUSED__SHIFT 0x10 |
20162 | #define GDS_VMID7_BASE__BASE_MASK 0x0000FFFFL |
20163 | #define GDS_VMID7_BASE__UNUSED_MASK 0xFFFF0000L |
20164 | //GDS_VMID7_SIZE |
20165 | #define GDS_VMID7_SIZE__SIZE__SHIFT 0x0 |
20166 | #define GDS_VMID7_SIZE__UNUSED__SHIFT 0x11 |
20167 | #define GDS_VMID7_SIZE__SIZE_MASK 0x0001FFFFL |
20168 | #define GDS_VMID7_SIZE__UNUSED_MASK 0xFFFE0000L |
20169 | //GDS_VMID8_BASE |
20170 | #define GDS_VMID8_BASE__BASE__SHIFT 0x0 |
20171 | #define GDS_VMID8_BASE__UNUSED__SHIFT 0x10 |
20172 | #define GDS_VMID8_BASE__BASE_MASK 0x0000FFFFL |
20173 | #define GDS_VMID8_BASE__UNUSED_MASK 0xFFFF0000L |
20174 | //GDS_VMID8_SIZE |
20175 | #define GDS_VMID8_SIZE__SIZE__SHIFT 0x0 |
20176 | #define GDS_VMID8_SIZE__UNUSED__SHIFT 0x11 |
20177 | #define GDS_VMID8_SIZE__SIZE_MASK 0x0001FFFFL |
20178 | #define GDS_VMID8_SIZE__UNUSED_MASK 0xFFFE0000L |
20179 | //GDS_VMID9_BASE |
20180 | #define GDS_VMID9_BASE__BASE__SHIFT 0x0 |
20181 | #define GDS_VMID9_BASE__UNUSED__SHIFT 0x10 |
20182 | #define GDS_VMID9_BASE__BASE_MASK 0x0000FFFFL |
20183 | #define GDS_VMID9_BASE__UNUSED_MASK 0xFFFF0000L |
20184 | //GDS_VMID9_SIZE |
20185 | #define GDS_VMID9_SIZE__SIZE__SHIFT 0x0 |
20186 | #define GDS_VMID9_SIZE__UNUSED__SHIFT 0x11 |
20187 | #define GDS_VMID9_SIZE__SIZE_MASK 0x0001FFFFL |
20188 | #define GDS_VMID9_SIZE__UNUSED_MASK 0xFFFE0000L |
20189 | //GDS_VMID10_BASE |
20190 | #define GDS_VMID10_BASE__BASE__SHIFT 0x0 |
20191 | #define GDS_VMID10_BASE__UNUSED__SHIFT 0x10 |
20192 | #define GDS_VMID10_BASE__BASE_MASK 0x0000FFFFL |
20193 | #define GDS_VMID10_BASE__UNUSED_MASK 0xFFFF0000L |
20194 | //GDS_VMID10_SIZE |
20195 | #define GDS_VMID10_SIZE__SIZE__SHIFT 0x0 |
20196 | #define GDS_VMID10_SIZE__UNUSED__SHIFT 0x11 |
20197 | #define GDS_VMID10_SIZE__SIZE_MASK 0x0001FFFFL |
20198 | #define GDS_VMID10_SIZE__UNUSED_MASK 0xFFFE0000L |
20199 | //GDS_VMID11_BASE |
20200 | #define GDS_VMID11_BASE__BASE__SHIFT 0x0 |
20201 | #define GDS_VMID11_BASE__UNUSED__SHIFT 0x10 |
20202 | #define GDS_VMID11_BASE__BASE_MASK 0x0000FFFFL |
20203 | #define GDS_VMID11_BASE__UNUSED_MASK 0xFFFF0000L |
20204 | //GDS_VMID11_SIZE |
20205 | #define GDS_VMID11_SIZE__SIZE__SHIFT 0x0 |
20206 | #define GDS_VMID11_SIZE__UNUSED__SHIFT 0x11 |
20207 | #define GDS_VMID11_SIZE__SIZE_MASK 0x0001FFFFL |
20208 | #define GDS_VMID11_SIZE__UNUSED_MASK 0xFFFE0000L |
20209 | //GDS_VMID12_BASE |
20210 | #define GDS_VMID12_BASE__BASE__SHIFT 0x0 |
20211 | #define GDS_VMID12_BASE__UNUSED__SHIFT 0x10 |
20212 | #define GDS_VMID12_BASE__BASE_MASK 0x0000FFFFL |
20213 | #define GDS_VMID12_BASE__UNUSED_MASK 0xFFFF0000L |
20214 | //GDS_VMID12_SIZE |
20215 | #define GDS_VMID12_SIZE__SIZE__SHIFT 0x0 |
20216 | #define GDS_VMID12_SIZE__UNUSED__SHIFT 0x11 |
20217 | #define GDS_VMID12_SIZE__SIZE_MASK 0x0001FFFFL |
20218 | #define GDS_VMID12_SIZE__UNUSED_MASK 0xFFFE0000L |
20219 | //GDS_VMID13_BASE |
20220 | #define GDS_VMID13_BASE__BASE__SHIFT 0x0 |
20221 | #define GDS_VMID13_BASE__UNUSED__SHIFT 0x10 |
20222 | #define GDS_VMID13_BASE__BASE_MASK 0x0000FFFFL |
20223 | #define GDS_VMID13_BASE__UNUSED_MASK 0xFFFF0000L |
20224 | //GDS_VMID13_SIZE |
20225 | #define GDS_VMID13_SIZE__SIZE__SHIFT 0x0 |
20226 | #define GDS_VMID13_SIZE__UNUSED__SHIFT 0x11 |
20227 | #define GDS_VMID13_SIZE__SIZE_MASK 0x0001FFFFL |
20228 | #define GDS_VMID13_SIZE__UNUSED_MASK 0xFFFE0000L |
20229 | //GDS_VMID14_BASE |
20230 | #define GDS_VMID14_BASE__BASE__SHIFT 0x0 |
20231 | #define GDS_VMID14_BASE__UNUSED__SHIFT 0x10 |
20232 | #define GDS_VMID14_BASE__BASE_MASK 0x0000FFFFL |
20233 | #define GDS_VMID14_BASE__UNUSED_MASK 0xFFFF0000L |
20234 | //GDS_VMID14_SIZE |
20235 | #define GDS_VMID14_SIZE__SIZE__SHIFT 0x0 |
20236 | #define GDS_VMID14_SIZE__UNUSED__SHIFT 0x11 |
20237 | #define GDS_VMID14_SIZE__SIZE_MASK 0x0001FFFFL |
20238 | #define GDS_VMID14_SIZE__UNUSED_MASK 0xFFFE0000L |
20239 | //GDS_VMID15_BASE |
20240 | #define GDS_VMID15_BASE__BASE__SHIFT 0x0 |
20241 | #define GDS_VMID15_BASE__UNUSED__SHIFT 0x10 |
20242 | #define GDS_VMID15_BASE__BASE_MASK 0x0000FFFFL |
20243 | #define GDS_VMID15_BASE__UNUSED_MASK 0xFFFF0000L |
20244 | //GDS_VMID15_SIZE |
20245 | #define GDS_VMID15_SIZE__SIZE__SHIFT 0x0 |
20246 | #define GDS_VMID15_SIZE__UNUSED__SHIFT 0x11 |
20247 | #define GDS_VMID15_SIZE__SIZE_MASK 0x0001FFFFL |
20248 | #define GDS_VMID15_SIZE__UNUSED_MASK 0xFFFE0000L |
20249 | //GDS_GWS_VMID0 |
20250 | #define GDS_GWS_VMID0__BASE__SHIFT 0x0 |
20251 | #define GDS_GWS_VMID0__UNUSED1__SHIFT 0x6 |
20252 | #define GDS_GWS_VMID0__SIZE__SHIFT 0x10 |
20253 | #define GDS_GWS_VMID0__UNUSED2__SHIFT 0x17 |
20254 | #define GDS_GWS_VMID0__BASE_MASK 0x0000003FL |
20255 | #define GDS_GWS_VMID0__UNUSED1_MASK 0x0000FFC0L |
20256 | #define GDS_GWS_VMID0__SIZE_MASK 0x007F0000L |
20257 | #define GDS_GWS_VMID0__UNUSED2_MASK 0xFF800000L |
20258 | //GDS_GWS_VMID1 |
20259 | #define GDS_GWS_VMID1__BASE__SHIFT 0x0 |
20260 | #define GDS_GWS_VMID1__UNUSED1__SHIFT 0x6 |
20261 | #define GDS_GWS_VMID1__SIZE__SHIFT 0x10 |
20262 | #define GDS_GWS_VMID1__UNUSED2__SHIFT 0x17 |
20263 | #define GDS_GWS_VMID1__BASE_MASK 0x0000003FL |
20264 | #define GDS_GWS_VMID1__UNUSED1_MASK 0x0000FFC0L |
20265 | #define GDS_GWS_VMID1__SIZE_MASK 0x007F0000L |
20266 | #define GDS_GWS_VMID1__UNUSED2_MASK 0xFF800000L |
20267 | //GDS_GWS_VMID2 |
20268 | #define GDS_GWS_VMID2__BASE__SHIFT 0x0 |
20269 | #define GDS_GWS_VMID2__UNUSED1__SHIFT 0x6 |
20270 | #define GDS_GWS_VMID2__SIZE__SHIFT 0x10 |
20271 | #define GDS_GWS_VMID2__UNUSED2__SHIFT 0x17 |
20272 | #define GDS_GWS_VMID2__BASE_MASK 0x0000003FL |
20273 | #define GDS_GWS_VMID2__UNUSED1_MASK 0x0000FFC0L |
20274 | #define GDS_GWS_VMID2__SIZE_MASK 0x007F0000L |
20275 | #define GDS_GWS_VMID2__UNUSED2_MASK 0xFF800000L |
20276 | //GDS_GWS_VMID3 |
20277 | #define GDS_GWS_VMID3__BASE__SHIFT 0x0 |
20278 | #define GDS_GWS_VMID3__UNUSED1__SHIFT 0x6 |
20279 | #define GDS_GWS_VMID3__SIZE__SHIFT 0x10 |
20280 | #define GDS_GWS_VMID3__UNUSED2__SHIFT 0x17 |
20281 | #define GDS_GWS_VMID3__BASE_MASK 0x0000003FL |
20282 | #define GDS_GWS_VMID3__UNUSED1_MASK 0x0000FFC0L |
20283 | #define GDS_GWS_VMID3__SIZE_MASK 0x007F0000L |
20284 | #define GDS_GWS_VMID3__UNUSED2_MASK 0xFF800000L |
20285 | //GDS_GWS_VMID4 |
20286 | #define GDS_GWS_VMID4__BASE__SHIFT 0x0 |
20287 | #define GDS_GWS_VMID4__UNUSED1__SHIFT 0x6 |
20288 | #define GDS_GWS_VMID4__SIZE__SHIFT 0x10 |
20289 | #define GDS_GWS_VMID4__UNUSED2__SHIFT 0x17 |
20290 | #define GDS_GWS_VMID4__BASE_MASK 0x0000003FL |
20291 | #define GDS_GWS_VMID4__UNUSED1_MASK 0x0000FFC0L |
20292 | #define GDS_GWS_VMID4__SIZE_MASK 0x007F0000L |
20293 | #define GDS_GWS_VMID4__UNUSED2_MASK 0xFF800000L |
20294 | //GDS_GWS_VMID5 |
20295 | #define GDS_GWS_VMID5__BASE__SHIFT 0x0 |
20296 | #define GDS_GWS_VMID5__UNUSED1__SHIFT 0x6 |
20297 | #define GDS_GWS_VMID5__SIZE__SHIFT 0x10 |
20298 | #define GDS_GWS_VMID5__UNUSED2__SHIFT 0x17 |
20299 | #define GDS_GWS_VMID5__BASE_MASK 0x0000003FL |
20300 | #define GDS_GWS_VMID5__UNUSED1_MASK 0x0000FFC0L |
20301 | #define GDS_GWS_VMID5__SIZE_MASK 0x007F0000L |
20302 | #define GDS_GWS_VMID5__UNUSED2_MASK 0xFF800000L |
20303 | //GDS_GWS_VMID6 |
20304 | #define GDS_GWS_VMID6__BASE__SHIFT 0x0 |
20305 | #define GDS_GWS_VMID6__UNUSED1__SHIFT 0x6 |
20306 | #define GDS_GWS_VMID6__SIZE__SHIFT 0x10 |
20307 | #define GDS_GWS_VMID6__UNUSED2__SHIFT 0x17 |
20308 | #define GDS_GWS_VMID6__BASE_MASK 0x0000003FL |
20309 | #define GDS_GWS_VMID6__UNUSED1_MASK 0x0000FFC0L |
20310 | #define GDS_GWS_VMID6__SIZE_MASK 0x007F0000L |
20311 | #define GDS_GWS_VMID6__UNUSED2_MASK 0xFF800000L |
20312 | //GDS_GWS_VMID7 |
20313 | #define GDS_GWS_VMID7__BASE__SHIFT 0x0 |
20314 | #define GDS_GWS_VMID7__UNUSED1__SHIFT 0x6 |
20315 | #define GDS_GWS_VMID7__SIZE__SHIFT 0x10 |
20316 | #define GDS_GWS_VMID7__UNUSED2__SHIFT 0x17 |
20317 | #define GDS_GWS_VMID7__BASE_MASK 0x0000003FL |
20318 | #define GDS_GWS_VMID7__UNUSED1_MASK 0x0000FFC0L |
20319 | #define GDS_GWS_VMID7__SIZE_MASK 0x007F0000L |
20320 | #define GDS_GWS_VMID7__UNUSED2_MASK 0xFF800000L |
20321 | //GDS_GWS_VMID8 |
20322 | #define GDS_GWS_VMID8__BASE__SHIFT 0x0 |
20323 | #define GDS_GWS_VMID8__UNUSED1__SHIFT 0x6 |
20324 | #define GDS_GWS_VMID8__SIZE__SHIFT 0x10 |
20325 | #define GDS_GWS_VMID8__UNUSED2__SHIFT 0x17 |
20326 | #define GDS_GWS_VMID8__BASE_MASK 0x0000003FL |
20327 | #define GDS_GWS_VMID8__UNUSED1_MASK 0x0000FFC0L |
20328 | #define GDS_GWS_VMID8__SIZE_MASK 0x007F0000L |
20329 | #define GDS_GWS_VMID8__UNUSED2_MASK 0xFF800000L |
20330 | //GDS_GWS_VMID9 |
20331 | #define GDS_GWS_VMID9__BASE__SHIFT 0x0 |
20332 | #define GDS_GWS_VMID9__UNUSED1__SHIFT 0x6 |
20333 | #define GDS_GWS_VMID9__SIZE__SHIFT 0x10 |
20334 | #define GDS_GWS_VMID9__UNUSED2__SHIFT 0x17 |
20335 | #define GDS_GWS_VMID9__BASE_MASK 0x0000003FL |
20336 | #define GDS_GWS_VMID9__UNUSED1_MASK 0x0000FFC0L |
20337 | #define GDS_GWS_VMID9__SIZE_MASK 0x007F0000L |
20338 | #define GDS_GWS_VMID9__UNUSED2_MASK 0xFF800000L |
20339 | //GDS_GWS_VMID10 |
20340 | #define GDS_GWS_VMID10__BASE__SHIFT 0x0 |
20341 | #define GDS_GWS_VMID10__UNUSED1__SHIFT 0x6 |
20342 | #define GDS_GWS_VMID10__SIZE__SHIFT 0x10 |
20343 | #define GDS_GWS_VMID10__UNUSED2__SHIFT 0x17 |
20344 | #define GDS_GWS_VMID10__BASE_MASK 0x0000003FL |
20345 | #define GDS_GWS_VMID10__UNUSED1_MASK 0x0000FFC0L |
20346 | #define GDS_GWS_VMID10__SIZE_MASK 0x007F0000L |
20347 | #define GDS_GWS_VMID10__UNUSED2_MASK 0xFF800000L |
20348 | //GDS_GWS_VMID11 |
20349 | #define GDS_GWS_VMID11__BASE__SHIFT 0x0 |
20350 | #define GDS_GWS_VMID11__UNUSED1__SHIFT 0x6 |
20351 | #define GDS_GWS_VMID11__SIZE__SHIFT 0x10 |
20352 | #define GDS_GWS_VMID11__UNUSED2__SHIFT 0x17 |
20353 | #define GDS_GWS_VMID11__BASE_MASK 0x0000003FL |
20354 | #define GDS_GWS_VMID11__UNUSED1_MASK 0x0000FFC0L |
20355 | #define GDS_GWS_VMID11__SIZE_MASK 0x007F0000L |
20356 | #define GDS_GWS_VMID11__UNUSED2_MASK 0xFF800000L |
20357 | //GDS_GWS_VMID12 |
20358 | #define GDS_GWS_VMID12__BASE__SHIFT 0x0 |
20359 | #define GDS_GWS_VMID12__UNUSED1__SHIFT 0x6 |
20360 | #define GDS_GWS_VMID12__SIZE__SHIFT 0x10 |
20361 | #define GDS_GWS_VMID12__UNUSED2__SHIFT 0x17 |
20362 | #define GDS_GWS_VMID12__BASE_MASK 0x0000003FL |
20363 | #define GDS_GWS_VMID12__UNUSED1_MASK 0x0000FFC0L |
20364 | #define GDS_GWS_VMID12__SIZE_MASK 0x007F0000L |
20365 | #define GDS_GWS_VMID12__UNUSED2_MASK 0xFF800000L |
20366 | //GDS_GWS_VMID13 |
20367 | #define GDS_GWS_VMID13__BASE__SHIFT 0x0 |
20368 | #define GDS_GWS_VMID13__UNUSED1__SHIFT 0x6 |
20369 | #define GDS_GWS_VMID13__SIZE__SHIFT 0x10 |
20370 | #define GDS_GWS_VMID13__UNUSED2__SHIFT 0x17 |
20371 | #define GDS_GWS_VMID13__BASE_MASK 0x0000003FL |
20372 | #define GDS_GWS_VMID13__UNUSED1_MASK 0x0000FFC0L |
20373 | #define GDS_GWS_VMID13__SIZE_MASK 0x007F0000L |
20374 | #define GDS_GWS_VMID13__UNUSED2_MASK 0xFF800000L |
20375 | //GDS_GWS_VMID14 |
20376 | #define GDS_GWS_VMID14__BASE__SHIFT 0x0 |
20377 | #define GDS_GWS_VMID14__UNUSED1__SHIFT 0x6 |
20378 | #define GDS_GWS_VMID14__SIZE__SHIFT 0x10 |
20379 | #define GDS_GWS_VMID14__UNUSED2__SHIFT 0x17 |
20380 | #define GDS_GWS_VMID14__BASE_MASK 0x0000003FL |
20381 | #define GDS_GWS_VMID14__UNUSED1_MASK 0x0000FFC0L |
20382 | #define GDS_GWS_VMID14__SIZE_MASK 0x007F0000L |
20383 | #define GDS_GWS_VMID14__UNUSED2_MASK 0xFF800000L |
20384 | //GDS_GWS_VMID15 |
20385 | #define GDS_GWS_VMID15__BASE__SHIFT 0x0 |
20386 | #define GDS_GWS_VMID15__UNUSED1__SHIFT 0x6 |
20387 | #define GDS_GWS_VMID15__SIZE__SHIFT 0x10 |
20388 | #define GDS_GWS_VMID15__UNUSED2__SHIFT 0x17 |
20389 | #define GDS_GWS_VMID15__BASE_MASK 0x0000003FL |
20390 | #define GDS_GWS_VMID15__UNUSED1_MASK 0x0000FFC0L |
20391 | #define GDS_GWS_VMID15__SIZE_MASK 0x007F0000L |
20392 | #define GDS_GWS_VMID15__UNUSED2_MASK 0xFF800000L |
20393 | //GDS_OA_VMID0 |
20394 | #define GDS_OA_VMID0__MASK__SHIFT 0x0 |
20395 | #define GDS_OA_VMID0__UNUSED__SHIFT 0x10 |
20396 | #define GDS_OA_VMID0__MASK_MASK 0x0000FFFFL |
20397 | #define GDS_OA_VMID0__UNUSED_MASK 0xFFFF0000L |
20398 | //GDS_OA_VMID1 |
20399 | #define GDS_OA_VMID1__MASK__SHIFT 0x0 |
20400 | #define GDS_OA_VMID1__UNUSED__SHIFT 0x10 |
20401 | #define GDS_OA_VMID1__MASK_MASK 0x0000FFFFL |
20402 | #define GDS_OA_VMID1__UNUSED_MASK 0xFFFF0000L |
20403 | //GDS_OA_VMID2 |
20404 | #define GDS_OA_VMID2__MASK__SHIFT 0x0 |
20405 | #define GDS_OA_VMID2__UNUSED__SHIFT 0x10 |
20406 | #define GDS_OA_VMID2__MASK_MASK 0x0000FFFFL |
20407 | #define GDS_OA_VMID2__UNUSED_MASK 0xFFFF0000L |
20408 | //GDS_OA_VMID3 |
20409 | #define GDS_OA_VMID3__MASK__SHIFT 0x0 |
20410 | #define GDS_OA_VMID3__UNUSED__SHIFT 0x10 |
20411 | #define GDS_OA_VMID3__MASK_MASK 0x0000FFFFL |
20412 | #define GDS_OA_VMID3__UNUSED_MASK 0xFFFF0000L |
20413 | //GDS_OA_VMID4 |
20414 | #define GDS_OA_VMID4__MASK__SHIFT 0x0 |
20415 | #define GDS_OA_VMID4__UNUSED__SHIFT 0x10 |
20416 | #define GDS_OA_VMID4__MASK_MASK 0x0000FFFFL |
20417 | #define GDS_OA_VMID4__UNUSED_MASK 0xFFFF0000L |
20418 | //GDS_OA_VMID5 |
20419 | #define GDS_OA_VMID5__MASK__SHIFT 0x0 |
20420 | #define GDS_OA_VMID5__UNUSED__SHIFT 0x10 |
20421 | #define GDS_OA_VMID5__MASK_MASK 0x0000FFFFL |
20422 | #define GDS_OA_VMID5__UNUSED_MASK 0xFFFF0000L |
20423 | //GDS_OA_VMID6 |
20424 | #define GDS_OA_VMID6__MASK__SHIFT 0x0 |
20425 | #define GDS_OA_VMID6__UNUSED__SHIFT 0x10 |
20426 | #define GDS_OA_VMID6__MASK_MASK 0x0000FFFFL |
20427 | #define GDS_OA_VMID6__UNUSED_MASK 0xFFFF0000L |
20428 | //GDS_OA_VMID7 |
20429 | #define GDS_OA_VMID7__MASK__SHIFT 0x0 |
20430 | #define GDS_OA_VMID7__UNUSED__SHIFT 0x10 |
20431 | #define GDS_OA_VMID7__MASK_MASK 0x0000FFFFL |
20432 | #define GDS_OA_VMID7__UNUSED_MASK 0xFFFF0000L |
20433 | //GDS_OA_VMID8 |
20434 | #define GDS_OA_VMID8__MASK__SHIFT 0x0 |
20435 | #define GDS_OA_VMID8__UNUSED__SHIFT 0x10 |
20436 | #define GDS_OA_VMID8__MASK_MASK 0x0000FFFFL |
20437 | #define GDS_OA_VMID8__UNUSED_MASK 0xFFFF0000L |
20438 | //GDS_OA_VMID9 |
20439 | #define GDS_OA_VMID9__MASK__SHIFT 0x0 |
20440 | #define GDS_OA_VMID9__UNUSED__SHIFT 0x10 |
20441 | #define GDS_OA_VMID9__MASK_MASK 0x0000FFFFL |
20442 | #define GDS_OA_VMID9__UNUSED_MASK 0xFFFF0000L |
20443 | //GDS_OA_VMID10 |
20444 | #define GDS_OA_VMID10__MASK__SHIFT 0x0 |
20445 | #define GDS_OA_VMID10__UNUSED__SHIFT 0x10 |
20446 | #define GDS_OA_VMID10__MASK_MASK 0x0000FFFFL |
20447 | #define GDS_OA_VMID10__UNUSED_MASK 0xFFFF0000L |
20448 | //GDS_OA_VMID11 |
20449 | #define GDS_OA_VMID11__MASK__SHIFT 0x0 |
20450 | #define GDS_OA_VMID11__UNUSED__SHIFT 0x10 |
20451 | #define GDS_OA_VMID11__MASK_MASK 0x0000FFFFL |
20452 | #define GDS_OA_VMID11__UNUSED_MASK 0xFFFF0000L |
20453 | //GDS_OA_VMID12 |
20454 | #define GDS_OA_VMID12__MASK__SHIFT 0x0 |
20455 | #define GDS_OA_VMID12__UNUSED__SHIFT 0x10 |
20456 | #define GDS_OA_VMID12__MASK_MASK 0x0000FFFFL |
20457 | #define GDS_OA_VMID12__UNUSED_MASK 0xFFFF0000L |
20458 | //GDS_OA_VMID13 |
20459 | #define GDS_OA_VMID13__MASK__SHIFT 0x0 |
20460 | #define GDS_OA_VMID13__UNUSED__SHIFT 0x10 |
20461 | #define GDS_OA_VMID13__MASK_MASK 0x0000FFFFL |
20462 | #define GDS_OA_VMID13__UNUSED_MASK 0xFFFF0000L |
20463 | //GDS_OA_VMID14 |
20464 | #define GDS_OA_VMID14__MASK__SHIFT 0x0 |
20465 | #define GDS_OA_VMID14__UNUSED__SHIFT 0x10 |
20466 | #define GDS_OA_VMID14__MASK_MASK 0x0000FFFFL |
20467 | #define GDS_OA_VMID14__UNUSED_MASK 0xFFFF0000L |
20468 | //GDS_OA_VMID15 |
20469 | #define GDS_OA_VMID15__MASK__SHIFT 0x0 |
20470 | #define GDS_OA_VMID15__UNUSED__SHIFT 0x10 |
20471 | #define GDS_OA_VMID15__MASK_MASK 0x0000FFFFL |
20472 | #define GDS_OA_VMID15__UNUSED_MASK 0xFFFF0000L |
20473 | //GDS_GWS_RESET0 |
20474 | #define GDS_GWS_RESET0__RESOURCE0_RESET__SHIFT 0x0 |
20475 | #define GDS_GWS_RESET0__RESOURCE1_RESET__SHIFT 0x1 |
20476 | #define GDS_GWS_RESET0__RESOURCE2_RESET__SHIFT 0x2 |
20477 | #define GDS_GWS_RESET0__RESOURCE3_RESET__SHIFT 0x3 |
20478 | #define GDS_GWS_RESET0__RESOURCE4_RESET__SHIFT 0x4 |
20479 | #define GDS_GWS_RESET0__RESOURCE5_RESET__SHIFT 0x5 |
20480 | #define GDS_GWS_RESET0__RESOURCE6_RESET__SHIFT 0x6 |
20481 | #define GDS_GWS_RESET0__RESOURCE7_RESET__SHIFT 0x7 |
20482 | #define GDS_GWS_RESET0__RESOURCE8_RESET__SHIFT 0x8 |
20483 | #define GDS_GWS_RESET0__RESOURCE9_RESET__SHIFT 0x9 |
20484 | #define GDS_GWS_RESET0__RESOURCE10_RESET__SHIFT 0xa |
20485 | #define GDS_GWS_RESET0__RESOURCE11_RESET__SHIFT 0xb |
20486 | #define GDS_GWS_RESET0__RESOURCE12_RESET__SHIFT 0xc |
20487 | #define GDS_GWS_RESET0__RESOURCE13_RESET__SHIFT 0xd |
20488 | #define GDS_GWS_RESET0__RESOURCE14_RESET__SHIFT 0xe |
20489 | #define GDS_GWS_RESET0__RESOURCE15_RESET__SHIFT 0xf |
20490 | #define GDS_GWS_RESET0__RESOURCE16_RESET__SHIFT 0x10 |
20491 | #define GDS_GWS_RESET0__RESOURCE17_RESET__SHIFT 0x11 |
20492 | #define GDS_GWS_RESET0__RESOURCE18_RESET__SHIFT 0x12 |
20493 | #define GDS_GWS_RESET0__RESOURCE19_RESET__SHIFT 0x13 |
20494 | #define GDS_GWS_RESET0__RESOURCE20_RESET__SHIFT 0x14 |
20495 | #define GDS_GWS_RESET0__RESOURCE21_RESET__SHIFT 0x15 |
20496 | #define GDS_GWS_RESET0__RESOURCE22_RESET__SHIFT 0x16 |
20497 | #define GDS_GWS_RESET0__RESOURCE23_RESET__SHIFT 0x17 |
20498 | #define GDS_GWS_RESET0__RESOURCE24_RESET__SHIFT 0x18 |
20499 | #define GDS_GWS_RESET0__RESOURCE25_RESET__SHIFT 0x19 |
20500 | #define GDS_GWS_RESET0__RESOURCE26_RESET__SHIFT 0x1a |
20501 | #define GDS_GWS_RESET0__RESOURCE27_RESET__SHIFT 0x1b |
20502 | #define GDS_GWS_RESET0__RESOURCE28_RESET__SHIFT 0x1c |
20503 | #define GDS_GWS_RESET0__RESOURCE29_RESET__SHIFT 0x1d |
20504 | #define GDS_GWS_RESET0__RESOURCE30_RESET__SHIFT 0x1e |
20505 | #define GDS_GWS_RESET0__RESOURCE31_RESET__SHIFT 0x1f |
20506 | #define GDS_GWS_RESET0__RESOURCE0_RESET_MASK 0x00000001L |
20507 | #define GDS_GWS_RESET0__RESOURCE1_RESET_MASK 0x00000002L |
20508 | #define GDS_GWS_RESET0__RESOURCE2_RESET_MASK 0x00000004L |
20509 | #define GDS_GWS_RESET0__RESOURCE3_RESET_MASK 0x00000008L |
20510 | #define GDS_GWS_RESET0__RESOURCE4_RESET_MASK 0x00000010L |
20511 | #define GDS_GWS_RESET0__RESOURCE5_RESET_MASK 0x00000020L |
20512 | #define GDS_GWS_RESET0__RESOURCE6_RESET_MASK 0x00000040L |
20513 | #define GDS_GWS_RESET0__RESOURCE7_RESET_MASK 0x00000080L |
20514 | #define GDS_GWS_RESET0__RESOURCE8_RESET_MASK 0x00000100L |
20515 | #define GDS_GWS_RESET0__RESOURCE9_RESET_MASK 0x00000200L |
20516 | #define GDS_GWS_RESET0__RESOURCE10_RESET_MASK 0x00000400L |
20517 | #define GDS_GWS_RESET0__RESOURCE11_RESET_MASK 0x00000800L |
20518 | #define GDS_GWS_RESET0__RESOURCE12_RESET_MASK 0x00001000L |
20519 | #define GDS_GWS_RESET0__RESOURCE13_RESET_MASK 0x00002000L |
20520 | #define GDS_GWS_RESET0__RESOURCE14_RESET_MASK 0x00004000L |
20521 | #define GDS_GWS_RESET0__RESOURCE15_RESET_MASK 0x00008000L |
20522 | #define GDS_GWS_RESET0__RESOURCE16_RESET_MASK 0x00010000L |
20523 | #define GDS_GWS_RESET0__RESOURCE17_RESET_MASK 0x00020000L |
20524 | #define GDS_GWS_RESET0__RESOURCE18_RESET_MASK 0x00040000L |
20525 | #define GDS_GWS_RESET0__RESOURCE19_RESET_MASK 0x00080000L |
20526 | #define GDS_GWS_RESET0__RESOURCE20_RESET_MASK 0x00100000L |
20527 | #define GDS_GWS_RESET0__RESOURCE21_RESET_MASK 0x00200000L |
20528 | #define GDS_GWS_RESET0__RESOURCE22_RESET_MASK 0x00400000L |
20529 | #define GDS_GWS_RESET0__RESOURCE23_RESET_MASK 0x00800000L |
20530 | #define GDS_GWS_RESET0__RESOURCE24_RESET_MASK 0x01000000L |
20531 | #define GDS_GWS_RESET0__RESOURCE25_RESET_MASK 0x02000000L |
20532 | #define GDS_GWS_RESET0__RESOURCE26_RESET_MASK 0x04000000L |
20533 | #define GDS_GWS_RESET0__RESOURCE27_RESET_MASK 0x08000000L |
20534 | #define GDS_GWS_RESET0__RESOURCE28_RESET_MASK 0x10000000L |
20535 | #define GDS_GWS_RESET0__RESOURCE29_RESET_MASK 0x20000000L |
20536 | #define GDS_GWS_RESET0__RESOURCE30_RESET_MASK 0x40000000L |
20537 | #define GDS_GWS_RESET0__RESOURCE31_RESET_MASK 0x80000000L |
20538 | //GDS_GWS_RESET1 |
20539 | #define GDS_GWS_RESET1__RESOURCE32_RESET__SHIFT 0x0 |
20540 | #define GDS_GWS_RESET1__RESOURCE33_RESET__SHIFT 0x1 |
20541 | #define GDS_GWS_RESET1__RESOURCE34_RESET__SHIFT 0x2 |
20542 | #define GDS_GWS_RESET1__RESOURCE35_RESET__SHIFT 0x3 |
20543 | #define GDS_GWS_RESET1__RESOURCE36_RESET__SHIFT 0x4 |
20544 | #define GDS_GWS_RESET1__RESOURCE37_RESET__SHIFT 0x5 |
20545 | #define GDS_GWS_RESET1__RESOURCE38_RESET__SHIFT 0x6 |
20546 | #define GDS_GWS_RESET1__RESOURCE39_RESET__SHIFT 0x7 |
20547 | #define GDS_GWS_RESET1__RESOURCE40_RESET__SHIFT 0x8 |
20548 | #define GDS_GWS_RESET1__RESOURCE41_RESET__SHIFT 0x9 |
20549 | #define GDS_GWS_RESET1__RESOURCE42_RESET__SHIFT 0xa |
20550 | #define GDS_GWS_RESET1__RESOURCE43_RESET__SHIFT 0xb |
20551 | #define GDS_GWS_RESET1__RESOURCE44_RESET__SHIFT 0xc |
20552 | #define GDS_GWS_RESET1__RESOURCE45_RESET__SHIFT 0xd |
20553 | #define GDS_GWS_RESET1__RESOURCE46_RESET__SHIFT 0xe |
20554 | #define GDS_GWS_RESET1__RESOURCE47_RESET__SHIFT 0xf |
20555 | #define GDS_GWS_RESET1__RESOURCE48_RESET__SHIFT 0x10 |
20556 | #define GDS_GWS_RESET1__RESOURCE49_RESET__SHIFT 0x11 |
20557 | #define GDS_GWS_RESET1__RESOURCE50_RESET__SHIFT 0x12 |
20558 | #define GDS_GWS_RESET1__RESOURCE51_RESET__SHIFT 0x13 |
20559 | #define GDS_GWS_RESET1__RESOURCE52_RESET__SHIFT 0x14 |
20560 | #define GDS_GWS_RESET1__RESOURCE53_RESET__SHIFT 0x15 |
20561 | #define GDS_GWS_RESET1__RESOURCE54_RESET__SHIFT 0x16 |
20562 | #define GDS_GWS_RESET1__RESOURCE55_RESET__SHIFT 0x17 |
20563 | #define GDS_GWS_RESET1__RESOURCE56_RESET__SHIFT 0x18 |
20564 | #define GDS_GWS_RESET1__RESOURCE57_RESET__SHIFT 0x19 |
20565 | #define GDS_GWS_RESET1__RESOURCE58_RESET__SHIFT 0x1a |
20566 | #define GDS_GWS_RESET1__RESOURCE59_RESET__SHIFT 0x1b |
20567 | #define GDS_GWS_RESET1__RESOURCE60_RESET__SHIFT 0x1c |
20568 | #define GDS_GWS_RESET1__RESOURCE61_RESET__SHIFT 0x1d |
20569 | #define GDS_GWS_RESET1__RESOURCE62_RESET__SHIFT 0x1e |
20570 | #define GDS_GWS_RESET1__RESOURCE63_RESET__SHIFT 0x1f |
20571 | #define GDS_GWS_RESET1__RESOURCE32_RESET_MASK 0x00000001L |
20572 | #define GDS_GWS_RESET1__RESOURCE33_RESET_MASK 0x00000002L |
20573 | #define GDS_GWS_RESET1__RESOURCE34_RESET_MASK 0x00000004L |
20574 | #define GDS_GWS_RESET1__RESOURCE35_RESET_MASK 0x00000008L |
20575 | #define GDS_GWS_RESET1__RESOURCE36_RESET_MASK 0x00000010L |
20576 | #define GDS_GWS_RESET1__RESOURCE37_RESET_MASK 0x00000020L |
20577 | #define GDS_GWS_RESET1__RESOURCE38_RESET_MASK 0x00000040L |
20578 | #define GDS_GWS_RESET1__RESOURCE39_RESET_MASK 0x00000080L |
20579 | #define GDS_GWS_RESET1__RESOURCE40_RESET_MASK 0x00000100L |
20580 | #define GDS_GWS_RESET1__RESOURCE41_RESET_MASK 0x00000200L |
20581 | #define GDS_GWS_RESET1__RESOURCE42_RESET_MASK 0x00000400L |
20582 | #define GDS_GWS_RESET1__RESOURCE43_RESET_MASK 0x00000800L |
20583 | #define GDS_GWS_RESET1__RESOURCE44_RESET_MASK 0x00001000L |
20584 | #define GDS_GWS_RESET1__RESOURCE45_RESET_MASK 0x00002000L |
20585 | #define GDS_GWS_RESET1__RESOURCE46_RESET_MASK 0x00004000L |
20586 | #define GDS_GWS_RESET1__RESOURCE47_RESET_MASK 0x00008000L |
20587 | #define GDS_GWS_RESET1__RESOURCE48_RESET_MASK 0x00010000L |
20588 | #define GDS_GWS_RESET1__RESOURCE49_RESET_MASK 0x00020000L |
20589 | #define GDS_GWS_RESET1__RESOURCE50_RESET_MASK 0x00040000L |
20590 | #define GDS_GWS_RESET1__RESOURCE51_RESET_MASK 0x00080000L |
20591 | #define GDS_GWS_RESET1__RESOURCE52_RESET_MASK 0x00100000L |
20592 | #define GDS_GWS_RESET1__RESOURCE53_RESET_MASK 0x00200000L |
20593 | #define GDS_GWS_RESET1__RESOURCE54_RESET_MASK 0x00400000L |
20594 | #define GDS_GWS_RESET1__RESOURCE55_RESET_MASK 0x00800000L |
20595 | #define GDS_GWS_RESET1__RESOURCE56_RESET_MASK 0x01000000L |
20596 | #define GDS_GWS_RESET1__RESOURCE57_RESET_MASK 0x02000000L |
20597 | #define GDS_GWS_RESET1__RESOURCE58_RESET_MASK 0x04000000L |
20598 | #define GDS_GWS_RESET1__RESOURCE59_RESET_MASK 0x08000000L |
20599 | #define GDS_GWS_RESET1__RESOURCE60_RESET_MASK 0x10000000L |
20600 | #define GDS_GWS_RESET1__RESOURCE61_RESET_MASK 0x20000000L |
20601 | #define GDS_GWS_RESET1__RESOURCE62_RESET_MASK 0x40000000L |
20602 | #define GDS_GWS_RESET1__RESOURCE63_RESET_MASK 0x80000000L |
20603 | //GDS_GWS_RESOURCE_RESET |
20604 | #define GDS_GWS_RESOURCE_RESET__RESET__SHIFT 0x0 |
20605 | #define GDS_GWS_RESOURCE_RESET__RESOURCE_ID__SHIFT 0x8 |
20606 | #define GDS_GWS_RESOURCE_RESET__UNUSED__SHIFT 0x10 |
20607 | #define GDS_GWS_RESOURCE_RESET__RESET_MASK 0x00000001L |
20608 | #define GDS_GWS_RESOURCE_RESET__RESOURCE_ID_MASK 0x0000FF00L |
20609 | #define GDS_GWS_RESOURCE_RESET__UNUSED_MASK 0xFFFF0000L |
20610 | //GDS_COMPUTE_MAX_WAVE_ID |
20611 | #define GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0 |
20612 | #define GDS_COMPUTE_MAX_WAVE_ID__UNUSED__SHIFT 0xc |
20613 | #define GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000FFFL |
20614 | #define GDS_COMPUTE_MAX_WAVE_ID__UNUSED_MASK 0xFFFFF000L |
20615 | //GDS_OA_RESET_MASK |
20616 | #define GDS_OA_RESET_MASK__ME0_GFXHP3D_PIX_RESET__SHIFT 0x0 |
20617 | #define GDS_OA_RESET_MASK__ME0_GFXHP3D_VTX_RESET__SHIFT 0x1 |
20618 | #define GDS_OA_RESET_MASK__ME0_CS_RESET__SHIFT 0x2 |
20619 | #define GDS_OA_RESET_MASK__ME0_GFXHP3D_GS_RESET__SHIFT 0x3 |
20620 | #define GDS_OA_RESET_MASK__ME1_PIPE0_RESET__SHIFT 0x4 |
20621 | #define GDS_OA_RESET_MASK__ME1_PIPE1_RESET__SHIFT 0x5 |
20622 | #define GDS_OA_RESET_MASK__ME1_PIPE2_RESET__SHIFT 0x6 |
20623 | #define GDS_OA_RESET_MASK__ME1_PIPE3_RESET__SHIFT 0x7 |
20624 | #define GDS_OA_RESET_MASK__ME2_PIPE0_RESET__SHIFT 0x8 |
20625 | #define GDS_OA_RESET_MASK__ME2_PIPE1_RESET__SHIFT 0x9 |
20626 | #define GDS_OA_RESET_MASK__ME2_PIPE2_RESET__SHIFT 0xa |
20627 | #define GDS_OA_RESET_MASK__ME2_PIPE3_RESET__SHIFT 0xb |
20628 | #define GDS_OA_RESET_MASK__ME0_PIPE1_CS_RESET__SHIFT 0xc |
20629 | #define GDS_OA_RESET_MASK__UNUSED1__SHIFT 0xd |
20630 | #define GDS_OA_RESET_MASK__ME0_GFXHP3D_PIX_RESET_MASK 0x00000001L |
20631 | #define GDS_OA_RESET_MASK__ME0_GFXHP3D_VTX_RESET_MASK 0x00000002L |
20632 | #define GDS_OA_RESET_MASK__ME0_CS_RESET_MASK 0x00000004L |
20633 | #define GDS_OA_RESET_MASK__ME0_GFXHP3D_GS_RESET_MASK 0x00000008L |
20634 | #define GDS_OA_RESET_MASK__ME1_PIPE0_RESET_MASK 0x00000010L |
20635 | #define GDS_OA_RESET_MASK__ME1_PIPE1_RESET_MASK 0x00000020L |
20636 | #define GDS_OA_RESET_MASK__ME1_PIPE2_RESET_MASK 0x00000040L |
20637 | #define GDS_OA_RESET_MASK__ME1_PIPE3_RESET_MASK 0x00000080L |
20638 | #define GDS_OA_RESET_MASK__ME2_PIPE0_RESET_MASK 0x00000100L |
20639 | #define GDS_OA_RESET_MASK__ME2_PIPE1_RESET_MASK 0x00000200L |
20640 | #define GDS_OA_RESET_MASK__ME2_PIPE2_RESET_MASK 0x00000400L |
20641 | #define GDS_OA_RESET_MASK__ME2_PIPE3_RESET_MASK 0x00000800L |
20642 | #define GDS_OA_RESET_MASK__ME0_PIPE1_CS_RESET_MASK 0x00001000L |
20643 | #define GDS_OA_RESET_MASK__UNUSED1_MASK 0xFFFFE000L |
20644 | //GDS_OA_RESET |
20645 | #define GDS_OA_RESET__RESET__SHIFT 0x0 |
20646 | #define GDS_OA_RESET__PIPE_ID__SHIFT 0x8 |
20647 | #define GDS_OA_RESET__UNUSED__SHIFT 0x10 |
20648 | #define GDS_OA_RESET__RESET_MASK 0x00000001L |
20649 | #define GDS_OA_RESET__PIPE_ID_MASK 0x0000FF00L |
20650 | #define GDS_OA_RESET__UNUSED_MASK 0xFFFF0000L |
20651 | //GDS_CS_CTXSW_STATUS |
20652 | #define GDS_CS_CTXSW_STATUS__R__SHIFT 0x0 |
20653 | #define GDS_CS_CTXSW_STATUS__W__SHIFT 0x1 |
20654 | #define GDS_CS_CTXSW_STATUS__UNUSED__SHIFT 0x2 |
20655 | #define GDS_CS_CTXSW_STATUS__R_MASK 0x00000001L |
20656 | #define GDS_CS_CTXSW_STATUS__W_MASK 0x00000002L |
20657 | #define GDS_CS_CTXSW_STATUS__UNUSED_MASK 0xFFFFFFFCL |
20658 | //GDS_CS_CTXSW_CNT0 |
20659 | #define GDS_CS_CTXSW_CNT0__UPDN__SHIFT 0x0 |
20660 | #define GDS_CS_CTXSW_CNT0__PTR__SHIFT 0x10 |
20661 | #define GDS_CS_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL |
20662 | #define GDS_CS_CTXSW_CNT0__PTR_MASK 0xFFFF0000L |
20663 | //GDS_CS_CTXSW_CNT1 |
20664 | #define GDS_CS_CTXSW_CNT1__UPDN__SHIFT 0x0 |
20665 | #define GDS_CS_CTXSW_CNT1__PTR__SHIFT 0x10 |
20666 | #define GDS_CS_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL |
20667 | #define GDS_CS_CTXSW_CNT1__PTR_MASK 0xFFFF0000L |
20668 | //GDS_CS_CTXSW_CNT2 |
20669 | #define GDS_CS_CTXSW_CNT2__UPDN__SHIFT 0x0 |
20670 | #define GDS_CS_CTXSW_CNT2__PTR__SHIFT 0x10 |
20671 | #define GDS_CS_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL |
20672 | #define GDS_CS_CTXSW_CNT2__PTR_MASK 0xFFFF0000L |
20673 | //GDS_CS_CTXSW_CNT3 |
20674 | #define GDS_CS_CTXSW_CNT3__UPDN__SHIFT 0x0 |
20675 | #define GDS_CS_CTXSW_CNT3__PTR__SHIFT 0x10 |
20676 | #define GDS_CS_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL |
20677 | #define GDS_CS_CTXSW_CNT3__PTR_MASK 0xFFFF0000L |
20678 | //GDS_GFX_CTXSW_STATUS |
20679 | #define GDS_GFX_CTXSW_STATUS__R__SHIFT 0x0 |
20680 | #define GDS_GFX_CTXSW_STATUS__W__SHIFT 0x1 |
20681 | #define GDS_GFX_CTXSW_STATUS__UNUSED__SHIFT 0x2 |
20682 | #define GDS_GFX_CTXSW_STATUS__R_MASK 0x00000001L |
20683 | #define GDS_GFX_CTXSW_STATUS__W_MASK 0x00000002L |
20684 | #define GDS_GFX_CTXSW_STATUS__UNUSED_MASK 0xFFFFFFFCL |
20685 | //GDS_PS_CTXSW_CNT0 |
20686 | #define GDS_PS_CTXSW_CNT0__UPDN__SHIFT 0x0 |
20687 | #define GDS_PS_CTXSW_CNT0__PTR__SHIFT 0x10 |
20688 | #define GDS_PS_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL |
20689 | #define GDS_PS_CTXSW_CNT0__PTR_MASK 0xFFFF0000L |
20690 | //GDS_PS_CTXSW_CNT1 |
20691 | #define GDS_PS_CTXSW_CNT1__UPDN__SHIFT 0x0 |
20692 | #define GDS_PS_CTXSW_CNT1__PTR__SHIFT 0x10 |
20693 | #define GDS_PS_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL |
20694 | #define GDS_PS_CTXSW_CNT1__PTR_MASK 0xFFFF0000L |
20695 | //GDS_PS_CTXSW_CNT2 |
20696 | #define GDS_PS_CTXSW_CNT2__UPDN__SHIFT 0x0 |
20697 | #define GDS_PS_CTXSW_CNT2__PTR__SHIFT 0x10 |
20698 | #define GDS_PS_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL |
20699 | #define GDS_PS_CTXSW_CNT2__PTR_MASK 0xFFFF0000L |
20700 | //GDS_PS_CTXSW_CNT3 |
20701 | #define GDS_PS_CTXSW_CNT3__UPDN__SHIFT 0x0 |
20702 | #define GDS_PS_CTXSW_CNT3__PTR__SHIFT 0x10 |
20703 | #define GDS_PS_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL |
20704 | #define GDS_PS_CTXSW_CNT3__PTR_MASK 0xFFFF0000L |
20705 | //GDS_PS_CTXSW_IDX |
20706 | #define GDS_PS_CTXSW_IDX__PACKER_ID__SHIFT 0x0 |
20707 | #define GDS_PS_CTXSW_IDX__UNUSED__SHIFT 0x6 |
20708 | #define GDS_PS_CTXSW_IDX__PACKER_ID_MASK 0x0000003FL |
20709 | #define GDS_PS_CTXSW_IDX__UNUSED_MASK 0xFFFFFFC0L |
20710 | //GDS_GS_CTXSW_CNT0 |
20711 | #define GDS_GS_CTXSW_CNT0__UPDN__SHIFT 0x0 |
20712 | #define GDS_GS_CTXSW_CNT0__PTR__SHIFT 0x10 |
20713 | #define GDS_GS_CTXSW_CNT0__UPDN_MASK 0x0000FFFFL |
20714 | #define GDS_GS_CTXSW_CNT0__PTR_MASK 0xFFFF0000L |
20715 | //GDS_GS_CTXSW_CNT1 |
20716 | #define GDS_GS_CTXSW_CNT1__UPDN__SHIFT 0x0 |
20717 | #define GDS_GS_CTXSW_CNT1__PTR__SHIFT 0x10 |
20718 | #define GDS_GS_CTXSW_CNT1__UPDN_MASK 0x0000FFFFL |
20719 | #define GDS_GS_CTXSW_CNT1__PTR_MASK 0xFFFF0000L |
20720 | //GDS_GS_CTXSW_CNT2 |
20721 | #define GDS_GS_CTXSW_CNT2__UPDN__SHIFT 0x0 |
20722 | #define GDS_GS_CTXSW_CNT2__PTR__SHIFT 0x10 |
20723 | #define GDS_GS_CTXSW_CNT2__UPDN_MASK 0x0000FFFFL |
20724 | #define GDS_GS_CTXSW_CNT2__PTR_MASK 0xFFFF0000L |
20725 | //GDS_GS_CTXSW_CNT3 |
20726 | #define GDS_GS_CTXSW_CNT3__UPDN__SHIFT 0x0 |
20727 | #define GDS_GS_CTXSW_CNT3__PTR__SHIFT 0x10 |
20728 | #define GDS_GS_CTXSW_CNT3__UPDN_MASK 0x0000FFFFL |
20729 | #define GDS_GS_CTXSW_CNT3__PTR_MASK 0xFFFF0000L |
20730 | //GDS_MEMORY_CLEAN |
20731 | #define GDS_MEMORY_CLEAN__START__SHIFT 0x0 |
20732 | #define GDS_MEMORY_CLEAN__FINISH__SHIFT 0x1 |
20733 | #define GDS_MEMORY_CLEAN__UNUSED__SHIFT 0x2 |
20734 | #define GDS_MEMORY_CLEAN__START_MASK 0x00000001L |
20735 | #define GDS_MEMORY_CLEAN__FINISH_MASK 0x00000002L |
20736 | #define GDS_MEMORY_CLEAN__UNUSED_MASK 0xFFFFFFFCL |
20737 | |
20738 | |
20739 | // addressBlock: gc_rasdec |
20740 | //RAS_SIGNATURE_CONTROL |
20741 | #define RAS_SIGNATURE_CONTROL__ENABLE__SHIFT 0x0 |
20742 | #define RAS_SIGNATURE_CONTROL__ENABLE_MASK 0x00000001L |
20743 | //RAS_SIGNATURE_MASK |
20744 | #define RAS_SIGNATURE_MASK__INPUT_BUS_MASK__SHIFT 0x0 |
20745 | #define RAS_SIGNATURE_MASK__INPUT_BUS_MASK_MASK 0xFFFFFFFFL |
20746 | //RAS_SX_SIGNATURE0 |
20747 | #define RAS_SX_SIGNATURE0__SIGNATURE__SHIFT 0x0 |
20748 | #define RAS_SX_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL |
20749 | //RAS_SX_SIGNATURE1 |
20750 | #define RAS_SX_SIGNATURE1__SIGNATURE__SHIFT 0x0 |
20751 | #define RAS_SX_SIGNATURE1__SIGNATURE_MASK 0xFFFFFFFFL |
20752 | //RAS_SX_SIGNATURE2 |
20753 | #define RAS_SX_SIGNATURE2__SIGNATURE__SHIFT 0x0 |
20754 | #define RAS_SX_SIGNATURE2__SIGNATURE_MASK 0xFFFFFFFFL |
20755 | //RAS_SX_SIGNATURE3 |
20756 | #define RAS_SX_SIGNATURE3__SIGNATURE__SHIFT 0x0 |
20757 | #define RAS_SX_SIGNATURE3__SIGNATURE_MASK 0xFFFFFFFFL |
20758 | //RAS_DB_SIGNATURE0 |
20759 | #define RAS_DB_SIGNATURE0__SIGNATURE__SHIFT 0x0 |
20760 | #define RAS_DB_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL |
20761 | //RAS_PA_SIGNATURE0 |
20762 | #define RAS_PA_SIGNATURE0__SIGNATURE__SHIFT 0x0 |
20763 | #define RAS_PA_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL |
20764 | //RAS_SC_SIGNATURE0 |
20765 | #define RAS_SC_SIGNATURE0__SIGNATURE__SHIFT 0x0 |
20766 | #define RAS_SC_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL |
20767 | //RAS_SC_SIGNATURE1 |
20768 | #define RAS_SC_SIGNATURE1__SIGNATURE__SHIFT 0x0 |
20769 | #define RAS_SC_SIGNATURE1__SIGNATURE_MASK 0xFFFFFFFFL |
20770 | //RAS_SC_SIGNATURE2 |
20771 | #define RAS_SC_SIGNATURE2__SIGNATURE__SHIFT 0x0 |
20772 | #define RAS_SC_SIGNATURE2__SIGNATURE_MASK 0xFFFFFFFFL |
20773 | //RAS_SC_SIGNATURE3 |
20774 | #define RAS_SC_SIGNATURE3__SIGNATURE__SHIFT 0x0 |
20775 | #define RAS_SC_SIGNATURE3__SIGNATURE_MASK 0xFFFFFFFFL |
20776 | //RAS_SC_SIGNATURE4 |
20777 | #define RAS_SC_SIGNATURE4__SIGNATURE__SHIFT 0x0 |
20778 | #define RAS_SC_SIGNATURE4__SIGNATURE_MASK 0xFFFFFFFFL |
20779 | //RAS_SC_SIGNATURE5 |
20780 | #define RAS_SC_SIGNATURE5__SIGNATURE__SHIFT 0x0 |
20781 | #define RAS_SC_SIGNATURE5__SIGNATURE_MASK 0xFFFFFFFFL |
20782 | //RAS_SC_SIGNATURE6 |
20783 | #define RAS_SC_SIGNATURE6__SIGNATURE__SHIFT 0x0 |
20784 | #define RAS_SC_SIGNATURE6__SIGNATURE_MASK 0xFFFFFFFFL |
20785 | //RAS_SC_SIGNATURE7 |
20786 | #define RAS_SC_SIGNATURE7__SIGNATURE__SHIFT 0x0 |
20787 | #define RAS_SC_SIGNATURE7__SIGNATURE_MASK 0xFFFFFFFFL |
20788 | //RAS_SPI_SIGNATURE0 |
20789 | #define RAS_SPI_SIGNATURE0__SIGNATURE__SHIFT 0x0 |
20790 | #define RAS_SPI_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL |
20791 | //RAS_SPI_SIGNATURE1 |
20792 | #define RAS_SPI_SIGNATURE1__SIGNATURE__SHIFT 0x0 |
20793 | #define RAS_SPI_SIGNATURE1__SIGNATURE_MASK 0xFFFFFFFFL |
20794 | //RAS_CB_SIGNATURE0 |
20795 | #define RAS_CB_SIGNATURE0__SIGNATURE__SHIFT 0x0 |
20796 | #define RAS_CB_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL |
20797 | //RAS_BCI_SIGNATURE0 |
20798 | #define RAS_BCI_SIGNATURE0__SIGNATURE__SHIFT 0x0 |
20799 | #define RAS_BCI_SIGNATURE0__SIGNATURE_MASK 0xFFFFFFFFL |
20800 | //RAS_BCI_SIGNATURE1 |
20801 | #define RAS_BCI_SIGNATURE1__SIGNATURE__SHIFT 0x0 |
20802 | #define RAS_BCI_SIGNATURE1__SIGNATURE_MASK 0xFFFFFFFFL |
20803 | |
20804 | |
20805 | // addressBlock: gc_gusdec |
20806 | //GUS_IO_RD_COMBINE_FLUSH |
20807 | #define GUS_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 |
20808 | #define GUS_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 |
20809 | #define GUS_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 |
20810 | #define GUS_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc |
20811 | #define GUS_IO_RD_COMBINE_FLUSH__GROUP4_TIMER__SHIFT 0x10 |
20812 | #define GUS_IO_RD_COMBINE_FLUSH__GROUP5_TIMER__SHIFT 0x14 |
20813 | #define GUS_IO_RD_COMBINE_FLUSH__COMB_MODE__SHIFT 0x18 |
20814 | #define GUS_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL |
20815 | #define GUS_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L |
20816 | #define GUS_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L |
20817 | #define GUS_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L |
20818 | #define GUS_IO_RD_COMBINE_FLUSH__GROUP4_TIMER_MASK 0x000F0000L |
20819 | #define GUS_IO_RD_COMBINE_FLUSH__GROUP5_TIMER_MASK 0x00F00000L |
20820 | #define GUS_IO_RD_COMBINE_FLUSH__COMB_MODE_MASK 0x03000000L |
20821 | //GUS_IO_WR_COMBINE_FLUSH |
20822 | #define GUS_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 |
20823 | #define GUS_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 |
20824 | #define GUS_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 |
20825 | #define GUS_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc |
20826 | #define GUS_IO_WR_COMBINE_FLUSH__GROUP4_TIMER__SHIFT 0x10 |
20827 | #define GUS_IO_WR_COMBINE_FLUSH__GROUP5_TIMER__SHIFT 0x14 |
20828 | #define GUS_IO_WR_COMBINE_FLUSH__COMB_MODE__SHIFT 0x18 |
20829 | #define GUS_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL |
20830 | #define GUS_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L |
20831 | #define GUS_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L |
20832 | #define GUS_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L |
20833 | #define GUS_IO_WR_COMBINE_FLUSH__GROUP4_TIMER_MASK 0x000F0000L |
20834 | #define GUS_IO_WR_COMBINE_FLUSH__GROUP5_TIMER_MASK 0x00F00000L |
20835 | #define GUS_IO_WR_COMBINE_FLUSH__COMB_MODE_MASK 0x03000000L |
20836 | //GUS_IO_RD_PRI_AGE_RATE |
20837 | #define GUS_IO_RD_PRI_AGE_RATE__GROUP0_AGING_RATE__SHIFT 0x0 |
20838 | #define GUS_IO_RD_PRI_AGE_RATE__GROUP1_AGING_RATE__SHIFT 0x3 |
20839 | #define GUS_IO_RD_PRI_AGE_RATE__GROUP2_AGING_RATE__SHIFT 0x6 |
20840 | #define GUS_IO_RD_PRI_AGE_RATE__GROUP3_AGING_RATE__SHIFT 0x9 |
20841 | #define GUS_IO_RD_PRI_AGE_RATE__GROUP4_AGING_RATE__SHIFT 0xc |
20842 | #define GUS_IO_RD_PRI_AGE_RATE__GROUP5_AGING_RATE__SHIFT 0xf |
20843 | #define GUS_IO_RD_PRI_AGE_RATE__GROUP0_AGING_RATE_MASK 0x00000007L |
20844 | #define GUS_IO_RD_PRI_AGE_RATE__GROUP1_AGING_RATE_MASK 0x00000038L |
20845 | #define GUS_IO_RD_PRI_AGE_RATE__GROUP2_AGING_RATE_MASK 0x000001C0L |
20846 | #define GUS_IO_RD_PRI_AGE_RATE__GROUP3_AGING_RATE_MASK 0x00000E00L |
20847 | #define GUS_IO_RD_PRI_AGE_RATE__GROUP4_AGING_RATE_MASK 0x00007000L |
20848 | #define GUS_IO_RD_PRI_AGE_RATE__GROUP5_AGING_RATE_MASK 0x00038000L |
20849 | //GUS_IO_WR_PRI_AGE_RATE |
20850 | #define GUS_IO_WR_PRI_AGE_RATE__GROUP0_AGING_RATE__SHIFT 0x0 |
20851 | #define GUS_IO_WR_PRI_AGE_RATE__GROUP1_AGING_RATE__SHIFT 0x3 |
20852 | #define GUS_IO_WR_PRI_AGE_RATE__GROUP2_AGING_RATE__SHIFT 0x6 |
20853 | #define GUS_IO_WR_PRI_AGE_RATE__GROUP3_AGING_RATE__SHIFT 0x9 |
20854 | #define GUS_IO_WR_PRI_AGE_RATE__GROUP4_AGING_RATE__SHIFT 0xc |
20855 | #define GUS_IO_WR_PRI_AGE_RATE__GROUP5_AGING_RATE__SHIFT 0xf |
20856 | #define GUS_IO_WR_PRI_AGE_RATE__GROUP0_AGING_RATE_MASK 0x00000007L |
20857 | #define GUS_IO_WR_PRI_AGE_RATE__GROUP1_AGING_RATE_MASK 0x00000038L |
20858 | #define GUS_IO_WR_PRI_AGE_RATE__GROUP2_AGING_RATE_MASK 0x000001C0L |
20859 | #define GUS_IO_WR_PRI_AGE_RATE__GROUP3_AGING_RATE_MASK 0x00000E00L |
20860 | #define GUS_IO_WR_PRI_AGE_RATE__GROUP4_AGING_RATE_MASK 0x00007000L |
20861 | #define GUS_IO_WR_PRI_AGE_RATE__GROUP5_AGING_RATE_MASK 0x00038000L |
20862 | //GUS_IO_RD_PRI_AGE_COEFF |
20863 | #define GUS_IO_RD_PRI_AGE_COEFF__GROUP0_AGE_COEFFICIENT__SHIFT 0x0 |
20864 | #define GUS_IO_RD_PRI_AGE_COEFF__GROUP1_AGE_COEFFICIENT__SHIFT 0x3 |
20865 | #define GUS_IO_RD_PRI_AGE_COEFF__GROUP2_AGE_COEFFICIENT__SHIFT 0x6 |
20866 | #define GUS_IO_RD_PRI_AGE_COEFF__GROUP3_AGE_COEFFICIENT__SHIFT 0x9 |
20867 | #define GUS_IO_RD_PRI_AGE_COEFF__GROUP4_AGE_COEFFICIENT__SHIFT 0xc |
20868 | #define GUS_IO_RD_PRI_AGE_COEFF__GROUP5_AGE_COEFFICIENT__SHIFT 0xf |
20869 | #define GUS_IO_RD_PRI_AGE_COEFF__GROUP0_AGE_COEFFICIENT_MASK 0x00000007L |
20870 | #define GUS_IO_RD_PRI_AGE_COEFF__GROUP1_AGE_COEFFICIENT_MASK 0x00000038L |
20871 | #define GUS_IO_RD_PRI_AGE_COEFF__GROUP2_AGE_COEFFICIENT_MASK 0x000001C0L |
20872 | #define GUS_IO_RD_PRI_AGE_COEFF__GROUP3_AGE_COEFFICIENT_MASK 0x00000E00L |
20873 | #define GUS_IO_RD_PRI_AGE_COEFF__GROUP4_AGE_COEFFICIENT_MASK 0x00007000L |
20874 | #define GUS_IO_RD_PRI_AGE_COEFF__GROUP5_AGE_COEFFICIENT_MASK 0x00038000L |
20875 | //GUS_IO_WR_PRI_AGE_COEFF |
20876 | #define GUS_IO_WR_PRI_AGE_COEFF__GROUP0_AGE_COEFFICIENT__SHIFT 0x0 |
20877 | #define GUS_IO_WR_PRI_AGE_COEFF__GROUP1_AGE_COEFFICIENT__SHIFT 0x3 |
20878 | #define GUS_IO_WR_PRI_AGE_COEFF__GROUP2_AGE_COEFFICIENT__SHIFT 0x6 |
20879 | #define GUS_IO_WR_PRI_AGE_COEFF__GROUP3_AGE_COEFFICIENT__SHIFT 0x9 |
20880 | #define GUS_IO_WR_PRI_AGE_COEFF__GROUP4_AGE_COEFFICIENT__SHIFT 0xc |
20881 | #define GUS_IO_WR_PRI_AGE_COEFF__GROUP5_AGE_COEFFICIENT__SHIFT 0xf |
20882 | #define GUS_IO_WR_PRI_AGE_COEFF__GROUP0_AGE_COEFFICIENT_MASK 0x00000007L |
20883 | #define GUS_IO_WR_PRI_AGE_COEFF__GROUP1_AGE_COEFFICIENT_MASK 0x00000038L |
20884 | #define GUS_IO_WR_PRI_AGE_COEFF__GROUP2_AGE_COEFFICIENT_MASK 0x000001C0L |
20885 | #define GUS_IO_WR_PRI_AGE_COEFF__GROUP3_AGE_COEFFICIENT_MASK 0x00000E00L |
20886 | #define GUS_IO_WR_PRI_AGE_COEFF__GROUP4_AGE_COEFFICIENT_MASK 0x00007000L |
20887 | #define GUS_IO_WR_PRI_AGE_COEFF__GROUP5_AGE_COEFFICIENT_MASK 0x00038000L |
20888 | //GUS_IO_RD_PRI_QUEUING |
20889 | #define GUS_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 |
20890 | #define GUS_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 |
20891 | #define GUS_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 |
20892 | #define GUS_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 |
20893 | #define GUS_IO_RD_PRI_QUEUING__GROUP4_QUEUING_COEFFICIENT__SHIFT 0xc |
20894 | #define GUS_IO_RD_PRI_QUEUING__GROUP5_QUEUING_COEFFICIENT__SHIFT 0xf |
20895 | #define GUS_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L |
20896 | #define GUS_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L |
20897 | #define GUS_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L |
20898 | #define GUS_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L |
20899 | #define GUS_IO_RD_PRI_QUEUING__GROUP4_QUEUING_COEFFICIENT_MASK 0x00007000L |
20900 | #define GUS_IO_RD_PRI_QUEUING__GROUP5_QUEUING_COEFFICIENT_MASK 0x00038000L |
20901 | //GUS_IO_WR_PRI_QUEUING |
20902 | #define GUS_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 |
20903 | #define GUS_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 |
20904 | #define GUS_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 |
20905 | #define GUS_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 |
20906 | #define GUS_IO_WR_PRI_QUEUING__GROUP4_QUEUING_COEFFICIENT__SHIFT 0xc |
20907 | #define GUS_IO_WR_PRI_QUEUING__GROUP5_QUEUING_COEFFICIENT__SHIFT 0xf |
20908 | #define GUS_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L |
20909 | #define GUS_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L |
20910 | #define GUS_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L |
20911 | #define GUS_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L |
20912 | #define GUS_IO_WR_PRI_QUEUING__GROUP4_QUEUING_COEFFICIENT_MASK 0x00007000L |
20913 | #define GUS_IO_WR_PRI_QUEUING__GROUP5_QUEUING_COEFFICIENT_MASK 0x00038000L |
20914 | //GUS_IO_RD_PRI_FIXED |
20915 | #define GUS_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 |
20916 | #define GUS_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 |
20917 | #define GUS_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 |
20918 | #define GUS_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 |
20919 | #define GUS_IO_RD_PRI_FIXED__GROUP4_FIXED_COEFFICIENT__SHIFT 0xc |
20920 | #define GUS_IO_RD_PRI_FIXED__GROUP5_FIXED_COEFFICIENT__SHIFT 0xf |
20921 | #define GUS_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L |
20922 | #define GUS_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L |
20923 | #define GUS_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L |
20924 | #define GUS_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L |
20925 | #define GUS_IO_RD_PRI_FIXED__GROUP4_FIXED_COEFFICIENT_MASK 0x00007000L |
20926 | #define GUS_IO_RD_PRI_FIXED__GROUP5_FIXED_COEFFICIENT_MASK 0x00038000L |
20927 | //GUS_IO_WR_PRI_FIXED |
20928 | #define GUS_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 |
20929 | #define GUS_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 |
20930 | #define GUS_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 |
20931 | #define GUS_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 |
20932 | #define GUS_IO_WR_PRI_FIXED__GROUP4_FIXED_COEFFICIENT__SHIFT 0xc |
20933 | #define GUS_IO_WR_PRI_FIXED__GROUP5_FIXED_COEFFICIENT__SHIFT 0xf |
20934 | #define GUS_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L |
20935 | #define GUS_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L |
20936 | #define GUS_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L |
20937 | #define GUS_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L |
20938 | #define GUS_IO_WR_PRI_FIXED__GROUP4_FIXED_COEFFICIENT_MASK 0x00007000L |
20939 | #define GUS_IO_WR_PRI_FIXED__GROUP5_FIXED_COEFFICIENT_MASK 0x00038000L |
20940 | //GUS_IO_RD_PRI_URGENCY_COEFF |
20941 | #define GUS_IO_RD_PRI_URGENCY_COEFF__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 |
20942 | #define GUS_IO_RD_PRI_URGENCY_COEFF__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 |
20943 | #define GUS_IO_RD_PRI_URGENCY_COEFF__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 |
20944 | #define GUS_IO_RD_PRI_URGENCY_COEFF__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 |
20945 | #define GUS_IO_RD_PRI_URGENCY_COEFF__GROUP4_URGENCY_COEFFICIENT__SHIFT 0xc |
20946 | #define GUS_IO_RD_PRI_URGENCY_COEFF__GROUP5_URGENCY_COEFFICIENT__SHIFT 0xf |
20947 | #define GUS_IO_RD_PRI_URGENCY_COEFF__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L |
20948 | #define GUS_IO_RD_PRI_URGENCY_COEFF__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L |
20949 | #define GUS_IO_RD_PRI_URGENCY_COEFF__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L |
20950 | #define GUS_IO_RD_PRI_URGENCY_COEFF__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L |
20951 | #define GUS_IO_RD_PRI_URGENCY_COEFF__GROUP4_URGENCY_COEFFICIENT_MASK 0x00007000L |
20952 | #define GUS_IO_RD_PRI_URGENCY_COEFF__GROUP5_URGENCY_COEFFICIENT_MASK 0x00038000L |
20953 | //GUS_IO_WR_PRI_URGENCY_COEFF |
20954 | #define GUS_IO_WR_PRI_URGENCY_COEFF__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 |
20955 | #define GUS_IO_WR_PRI_URGENCY_COEFF__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 |
20956 | #define GUS_IO_WR_PRI_URGENCY_COEFF__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 |
20957 | #define GUS_IO_WR_PRI_URGENCY_COEFF__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 |
20958 | #define GUS_IO_WR_PRI_URGENCY_COEFF__GROUP4_URGENCY_COEFFICIENT__SHIFT 0xc |
20959 | #define GUS_IO_WR_PRI_URGENCY_COEFF__GROUP5_URGENCY_COEFFICIENT__SHIFT 0xf |
20960 | #define GUS_IO_WR_PRI_URGENCY_COEFF__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L |
20961 | #define GUS_IO_WR_PRI_URGENCY_COEFF__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L |
20962 | #define GUS_IO_WR_PRI_URGENCY_COEFF__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L |
20963 | #define GUS_IO_WR_PRI_URGENCY_COEFF__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L |
20964 | #define GUS_IO_WR_PRI_URGENCY_COEFF__GROUP4_URGENCY_COEFFICIENT_MASK 0x00007000L |
20965 | #define GUS_IO_WR_PRI_URGENCY_COEFF__GROUP5_URGENCY_COEFFICIENT_MASK 0x00038000L |
20966 | //GUS_IO_RD_PRI_URGENCY_MODE |
20967 | #define GUS_IO_RD_PRI_URGENCY_MODE__GROUP0_URGENCY_MODE__SHIFT 0x0 |
20968 | #define GUS_IO_RD_PRI_URGENCY_MODE__GROUP1_URGENCY_MODE__SHIFT 0x1 |
20969 | #define GUS_IO_RD_PRI_URGENCY_MODE__GROUP2_URGENCY_MODE__SHIFT 0x2 |
20970 | #define GUS_IO_RD_PRI_URGENCY_MODE__GROUP3_URGENCY_MODE__SHIFT 0x3 |
20971 | #define GUS_IO_RD_PRI_URGENCY_MODE__GROUP4_URGENCY_MODE__SHIFT 0x4 |
20972 | #define GUS_IO_RD_PRI_URGENCY_MODE__GROUP5_URGENCY_MODE__SHIFT 0x5 |
20973 | #define GUS_IO_RD_PRI_URGENCY_MODE__GROUP0_URGENCY_MODE_MASK 0x00000001L |
20974 | #define GUS_IO_RD_PRI_URGENCY_MODE__GROUP1_URGENCY_MODE_MASK 0x00000002L |
20975 | #define GUS_IO_RD_PRI_URGENCY_MODE__GROUP2_URGENCY_MODE_MASK 0x00000004L |
20976 | #define GUS_IO_RD_PRI_URGENCY_MODE__GROUP3_URGENCY_MODE_MASK 0x00000008L |
20977 | #define GUS_IO_RD_PRI_URGENCY_MODE__GROUP4_URGENCY_MODE_MASK 0x00000010L |
20978 | #define GUS_IO_RD_PRI_URGENCY_MODE__GROUP5_URGENCY_MODE_MASK 0x00000020L |
20979 | //GUS_IO_WR_PRI_URGENCY_MODE |
20980 | #define GUS_IO_WR_PRI_URGENCY_MODE__GROUP0_URGENCY_MODE__SHIFT 0x0 |
20981 | #define GUS_IO_WR_PRI_URGENCY_MODE__GROUP1_URGENCY_MODE__SHIFT 0x1 |
20982 | #define GUS_IO_WR_PRI_URGENCY_MODE__GROUP2_URGENCY_MODE__SHIFT 0x2 |
20983 | #define GUS_IO_WR_PRI_URGENCY_MODE__GROUP3_URGENCY_MODE__SHIFT 0x3 |
20984 | #define GUS_IO_WR_PRI_URGENCY_MODE__GROUP4_URGENCY_MODE__SHIFT 0x4 |
20985 | #define GUS_IO_WR_PRI_URGENCY_MODE__GROUP5_URGENCY_MODE__SHIFT 0x5 |
20986 | #define GUS_IO_WR_PRI_URGENCY_MODE__GROUP0_URGENCY_MODE_MASK 0x00000001L |
20987 | #define GUS_IO_WR_PRI_URGENCY_MODE__GROUP1_URGENCY_MODE_MASK 0x00000002L |
20988 | #define GUS_IO_WR_PRI_URGENCY_MODE__GROUP2_URGENCY_MODE_MASK 0x00000004L |
20989 | #define GUS_IO_WR_PRI_URGENCY_MODE__GROUP3_URGENCY_MODE_MASK 0x00000008L |
20990 | #define GUS_IO_WR_PRI_URGENCY_MODE__GROUP4_URGENCY_MODE_MASK 0x00000010L |
20991 | #define GUS_IO_WR_PRI_URGENCY_MODE__GROUP5_URGENCY_MODE_MASK 0x00000020L |
20992 | //GUS_IO_RD_PRI_QUANT_PRI1 |
20993 | #define GUS_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 |
20994 | #define GUS_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 |
20995 | #define GUS_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 |
20996 | #define GUS_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 |
20997 | #define GUS_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL |
20998 | #define GUS_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L |
20999 | #define GUS_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L |
21000 | #define GUS_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L |
21001 | //GUS_IO_RD_PRI_QUANT_PRI2 |
21002 | #define GUS_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 |
21003 | #define GUS_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 |
21004 | #define GUS_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 |
21005 | #define GUS_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 |
21006 | #define GUS_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL |
21007 | #define GUS_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L |
21008 | #define GUS_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L |
21009 | #define GUS_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L |
21010 | //GUS_IO_RD_PRI_QUANT_PRI3 |
21011 | #define GUS_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 |
21012 | #define GUS_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 |
21013 | #define GUS_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 |
21014 | #define GUS_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 |
21015 | #define GUS_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL |
21016 | #define GUS_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L |
21017 | #define GUS_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L |
21018 | #define GUS_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L |
21019 | //GUS_IO_RD_PRI_QUANT_PRI4 |
21020 | #define GUS_IO_RD_PRI_QUANT_PRI4__GROUP0_THRESHOLD__SHIFT 0x0 |
21021 | #define GUS_IO_RD_PRI_QUANT_PRI4__GROUP1_THRESHOLD__SHIFT 0x8 |
21022 | #define GUS_IO_RD_PRI_QUANT_PRI4__GROUP2_THRESHOLD__SHIFT 0x10 |
21023 | #define GUS_IO_RD_PRI_QUANT_PRI4__GROUP3_THRESHOLD__SHIFT 0x18 |
21024 | #define GUS_IO_RD_PRI_QUANT_PRI4__GROUP0_THRESHOLD_MASK 0x000000FFL |
21025 | #define GUS_IO_RD_PRI_QUANT_PRI4__GROUP1_THRESHOLD_MASK 0x0000FF00L |
21026 | #define GUS_IO_RD_PRI_QUANT_PRI4__GROUP2_THRESHOLD_MASK 0x00FF0000L |
21027 | #define GUS_IO_RD_PRI_QUANT_PRI4__GROUP3_THRESHOLD_MASK 0xFF000000L |
21028 | //GUS_IO_WR_PRI_QUANT_PRI1 |
21029 | #define GUS_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 |
21030 | #define GUS_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 |
21031 | #define GUS_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 |
21032 | #define GUS_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 |
21033 | #define GUS_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL |
21034 | #define GUS_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L |
21035 | #define GUS_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L |
21036 | #define GUS_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L |
21037 | //GUS_IO_WR_PRI_QUANT_PRI2 |
21038 | #define GUS_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 |
21039 | #define GUS_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 |
21040 | #define GUS_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 |
21041 | #define GUS_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 |
21042 | #define GUS_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL |
21043 | #define GUS_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L |
21044 | #define GUS_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L |
21045 | #define GUS_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L |
21046 | //GUS_IO_WR_PRI_QUANT_PRI3 |
21047 | #define GUS_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 |
21048 | #define GUS_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 |
21049 | #define GUS_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 |
21050 | #define GUS_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 |
21051 | #define GUS_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL |
21052 | #define GUS_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L |
21053 | #define GUS_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L |
21054 | #define GUS_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L |
21055 | //GUS_IO_WR_PRI_QUANT_PRI4 |
21056 | #define GUS_IO_WR_PRI_QUANT_PRI4__GROUP0_THRESHOLD__SHIFT 0x0 |
21057 | #define GUS_IO_WR_PRI_QUANT_PRI4__GROUP1_THRESHOLD__SHIFT 0x8 |
21058 | #define GUS_IO_WR_PRI_QUANT_PRI4__GROUP2_THRESHOLD__SHIFT 0x10 |
21059 | #define GUS_IO_WR_PRI_QUANT_PRI4__GROUP3_THRESHOLD__SHIFT 0x18 |
21060 | #define GUS_IO_WR_PRI_QUANT_PRI4__GROUP0_THRESHOLD_MASK 0x000000FFL |
21061 | #define GUS_IO_WR_PRI_QUANT_PRI4__GROUP1_THRESHOLD_MASK 0x0000FF00L |
21062 | #define GUS_IO_WR_PRI_QUANT_PRI4__GROUP2_THRESHOLD_MASK 0x00FF0000L |
21063 | #define GUS_IO_WR_PRI_QUANT_PRI4__GROUP3_THRESHOLD_MASK 0xFF000000L |
21064 | //GUS_IO_RD_PRI_QUANT1_PRI1 |
21065 | #define GUS_IO_RD_PRI_QUANT1_PRI1__GROUP4_THRESHOLD__SHIFT 0x0 |
21066 | #define GUS_IO_RD_PRI_QUANT1_PRI1__GROUP5_THRESHOLD__SHIFT 0x8 |
21067 | #define GUS_IO_RD_PRI_QUANT1_PRI1__GROUP4_THRESHOLD_MASK 0x000000FFL |
21068 | #define GUS_IO_RD_PRI_QUANT1_PRI1__GROUP5_THRESHOLD_MASK 0x0000FF00L |
21069 | //GUS_IO_RD_PRI_QUANT1_PRI2 |
21070 | #define GUS_IO_RD_PRI_QUANT1_PRI2__GROUP4_THRESHOLD__SHIFT 0x0 |
21071 | #define GUS_IO_RD_PRI_QUANT1_PRI2__GROUP5_THRESHOLD__SHIFT 0x8 |
21072 | #define GUS_IO_RD_PRI_QUANT1_PRI2__GROUP4_THRESHOLD_MASK 0x000000FFL |
21073 | #define GUS_IO_RD_PRI_QUANT1_PRI2__GROUP5_THRESHOLD_MASK 0x0000FF00L |
21074 | //GUS_IO_RD_PRI_QUANT1_PRI3 |
21075 | #define GUS_IO_RD_PRI_QUANT1_PRI3__GROUP4_THRESHOLD__SHIFT 0x0 |
21076 | #define GUS_IO_RD_PRI_QUANT1_PRI3__GROUP5_THRESHOLD__SHIFT 0x8 |
21077 | #define GUS_IO_RD_PRI_QUANT1_PRI3__GROUP4_THRESHOLD_MASK 0x000000FFL |
21078 | #define GUS_IO_RD_PRI_QUANT1_PRI3__GROUP5_THRESHOLD_MASK 0x0000FF00L |
21079 | //GUS_IO_RD_PRI_QUANT1_PRI4 |
21080 | #define GUS_IO_RD_PRI_QUANT1_PRI4__GROUP4_THRESHOLD__SHIFT 0x0 |
21081 | #define GUS_IO_RD_PRI_QUANT1_PRI4__GROUP5_THRESHOLD__SHIFT 0x8 |
21082 | #define GUS_IO_RD_PRI_QUANT1_PRI4__GROUP4_THRESHOLD_MASK 0x000000FFL |
21083 | #define GUS_IO_RD_PRI_QUANT1_PRI4__GROUP5_THRESHOLD_MASK 0x0000FF00L |
21084 | //GUS_IO_WR_PRI_QUANT1_PRI1 |
21085 | #define GUS_IO_WR_PRI_QUANT1_PRI1__GROUP4_THRESHOLD__SHIFT 0x0 |
21086 | #define GUS_IO_WR_PRI_QUANT1_PRI1__GROUP5_THRESHOLD__SHIFT 0x8 |
21087 | #define GUS_IO_WR_PRI_QUANT1_PRI1__GROUP4_THRESHOLD_MASK 0x000000FFL |
21088 | #define GUS_IO_WR_PRI_QUANT1_PRI1__GROUP5_THRESHOLD_MASK 0x0000FF00L |
21089 | //GUS_IO_WR_PRI_QUANT1_PRI2 |
21090 | #define GUS_IO_WR_PRI_QUANT1_PRI2__GROUP4_THRESHOLD__SHIFT 0x0 |
21091 | #define GUS_IO_WR_PRI_QUANT1_PRI2__GROUP5_THRESHOLD__SHIFT 0x8 |
21092 | #define GUS_IO_WR_PRI_QUANT1_PRI2__GROUP4_THRESHOLD_MASK 0x000000FFL |
21093 | #define GUS_IO_WR_PRI_QUANT1_PRI2__GROUP5_THRESHOLD_MASK 0x0000FF00L |
21094 | //GUS_IO_WR_PRI_QUANT1_PRI3 |
21095 | #define GUS_IO_WR_PRI_QUANT1_PRI3__GROUP4_THRESHOLD__SHIFT 0x0 |
21096 | #define GUS_IO_WR_PRI_QUANT1_PRI3__GROUP5_THRESHOLD__SHIFT 0x8 |
21097 | #define GUS_IO_WR_PRI_QUANT1_PRI3__GROUP4_THRESHOLD_MASK 0x000000FFL |
21098 | #define GUS_IO_WR_PRI_QUANT1_PRI3__GROUP5_THRESHOLD_MASK 0x0000FF00L |
21099 | //GUS_IO_WR_PRI_QUANT1_PRI4 |
21100 | #define GUS_IO_WR_PRI_QUANT1_PRI4__GROUP4_THRESHOLD__SHIFT 0x0 |
21101 | #define GUS_IO_WR_PRI_QUANT1_PRI4__GROUP5_THRESHOLD__SHIFT 0x8 |
21102 | #define GUS_IO_WR_PRI_QUANT1_PRI4__GROUP4_THRESHOLD_MASK 0x000000FFL |
21103 | #define GUS_IO_WR_PRI_QUANT1_PRI4__GROUP5_THRESHOLD_MASK 0x0000FF00L |
21104 | //GUS_DRAM_COMBINE_FLUSH |
21105 | #define GUS_DRAM_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 |
21106 | #define GUS_DRAM_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 |
21107 | #define GUS_DRAM_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 |
21108 | #define GUS_DRAM_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc |
21109 | #define GUS_DRAM_COMBINE_FLUSH__GROUP4_TIMER__SHIFT 0x10 |
21110 | #define GUS_DRAM_COMBINE_FLUSH__GROUP5_TIMER__SHIFT 0x14 |
21111 | #define GUS_DRAM_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL |
21112 | #define GUS_DRAM_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L |
21113 | #define GUS_DRAM_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L |
21114 | #define GUS_DRAM_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L |
21115 | #define GUS_DRAM_COMBINE_FLUSH__GROUP4_TIMER_MASK 0x000F0000L |
21116 | #define GUS_DRAM_COMBINE_FLUSH__GROUP5_TIMER_MASK 0x00F00000L |
21117 | //GUS_DRAM_COMBINE_RD_WR_EN |
21118 | #define GUS_DRAM_COMBINE_RD_WR_EN__GROUP0_TIMER__SHIFT 0x0 |
21119 | #define GUS_DRAM_COMBINE_RD_WR_EN__GROUP1_TIMER__SHIFT 0x2 |
21120 | #define GUS_DRAM_COMBINE_RD_WR_EN__GROUP2_TIMER__SHIFT 0x4 |
21121 | #define GUS_DRAM_COMBINE_RD_WR_EN__GROUP3_TIMER__SHIFT 0x6 |
21122 | #define GUS_DRAM_COMBINE_RD_WR_EN__GROUP4_TIMER__SHIFT 0x8 |
21123 | #define GUS_DRAM_COMBINE_RD_WR_EN__GROUP5_TIMER__SHIFT 0xa |
21124 | #define GUS_DRAM_COMBINE_RD_WR_EN__GROUP0_TIMER_MASK 0x00000003L |
21125 | #define GUS_DRAM_COMBINE_RD_WR_EN__GROUP1_TIMER_MASK 0x0000000CL |
21126 | #define GUS_DRAM_COMBINE_RD_WR_EN__GROUP2_TIMER_MASK 0x00000030L |
21127 | #define GUS_DRAM_COMBINE_RD_WR_EN__GROUP3_TIMER_MASK 0x000000C0L |
21128 | #define GUS_DRAM_COMBINE_RD_WR_EN__GROUP4_TIMER_MASK 0x00000300L |
21129 | #define GUS_DRAM_COMBINE_RD_WR_EN__GROUP5_TIMER_MASK 0x00000C00L |
21130 | //GUS_DRAM_PRI_AGE_RATE |
21131 | #define GUS_DRAM_PRI_AGE_RATE__GROUP0_AGING_RATE__SHIFT 0x0 |
21132 | #define GUS_DRAM_PRI_AGE_RATE__GROUP1_AGING_RATE__SHIFT 0x3 |
21133 | #define GUS_DRAM_PRI_AGE_RATE__GROUP2_AGING_RATE__SHIFT 0x6 |
21134 | #define GUS_DRAM_PRI_AGE_RATE__GROUP3_AGING_RATE__SHIFT 0x9 |
21135 | #define GUS_DRAM_PRI_AGE_RATE__GROUP4_AGING_RATE__SHIFT 0xc |
21136 | #define GUS_DRAM_PRI_AGE_RATE__GROUP5_AGING_RATE__SHIFT 0xf |
21137 | #define GUS_DRAM_PRI_AGE_RATE__GROUP0_AGING_RATE_MASK 0x00000007L |
21138 | #define GUS_DRAM_PRI_AGE_RATE__GROUP1_AGING_RATE_MASK 0x00000038L |
21139 | #define GUS_DRAM_PRI_AGE_RATE__GROUP2_AGING_RATE_MASK 0x000001C0L |
21140 | #define GUS_DRAM_PRI_AGE_RATE__GROUP3_AGING_RATE_MASK 0x00000E00L |
21141 | #define GUS_DRAM_PRI_AGE_RATE__GROUP4_AGING_RATE_MASK 0x00007000L |
21142 | #define GUS_DRAM_PRI_AGE_RATE__GROUP5_AGING_RATE_MASK 0x00038000L |
21143 | //GUS_DRAM_PRI_AGE_COEFF |
21144 | #define GUS_DRAM_PRI_AGE_COEFF__GROUP0_AGE_COEFFICIENT__SHIFT 0x0 |
21145 | #define GUS_DRAM_PRI_AGE_COEFF__GROUP1_AGE_COEFFICIENT__SHIFT 0x3 |
21146 | #define GUS_DRAM_PRI_AGE_COEFF__GROUP2_AGE_COEFFICIENT__SHIFT 0x6 |
21147 | #define GUS_DRAM_PRI_AGE_COEFF__GROUP3_AGE_COEFFICIENT__SHIFT 0x9 |
21148 | #define GUS_DRAM_PRI_AGE_COEFF__GROUP4_AGE_COEFFICIENT__SHIFT 0xc |
21149 | #define GUS_DRAM_PRI_AGE_COEFF__GROUP5_AGE_COEFFICIENT__SHIFT 0xf |
21150 | #define GUS_DRAM_PRI_AGE_COEFF__GROUP0_AGE_COEFFICIENT_MASK 0x00000007L |
21151 | #define GUS_DRAM_PRI_AGE_COEFF__GROUP1_AGE_COEFFICIENT_MASK 0x00000038L |
21152 | #define GUS_DRAM_PRI_AGE_COEFF__GROUP2_AGE_COEFFICIENT_MASK 0x000001C0L |
21153 | #define GUS_DRAM_PRI_AGE_COEFF__GROUP3_AGE_COEFFICIENT_MASK 0x00000E00L |
21154 | #define GUS_DRAM_PRI_AGE_COEFF__GROUP4_AGE_COEFFICIENT_MASK 0x00007000L |
21155 | #define GUS_DRAM_PRI_AGE_COEFF__GROUP5_AGE_COEFFICIENT_MASK 0x00038000L |
21156 | //GUS_DRAM_PRI_QUEUING |
21157 | #define GUS_DRAM_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 |
21158 | #define GUS_DRAM_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 |
21159 | #define GUS_DRAM_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 |
21160 | #define GUS_DRAM_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 |
21161 | #define GUS_DRAM_PRI_QUEUING__GROUP4_QUEUING_COEFFICIENT__SHIFT 0xc |
21162 | #define GUS_DRAM_PRI_QUEUING__GROUP5_QUEUING_COEFFICIENT__SHIFT 0xf |
21163 | #define GUS_DRAM_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L |
21164 | #define GUS_DRAM_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L |
21165 | #define GUS_DRAM_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L |
21166 | #define GUS_DRAM_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L |
21167 | #define GUS_DRAM_PRI_QUEUING__GROUP4_QUEUING_COEFFICIENT_MASK 0x00007000L |
21168 | #define GUS_DRAM_PRI_QUEUING__GROUP5_QUEUING_COEFFICIENT_MASK 0x00038000L |
21169 | //GUS_DRAM_PRI_FIXED |
21170 | #define GUS_DRAM_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 |
21171 | #define GUS_DRAM_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 |
21172 | #define GUS_DRAM_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 |
21173 | #define GUS_DRAM_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 |
21174 | #define GUS_DRAM_PRI_FIXED__GROUP4_FIXED_COEFFICIENT__SHIFT 0xc |
21175 | #define GUS_DRAM_PRI_FIXED__GROUP5_FIXED_COEFFICIENT__SHIFT 0xf |
21176 | #define GUS_DRAM_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L |
21177 | #define GUS_DRAM_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L |
21178 | #define GUS_DRAM_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L |
21179 | #define GUS_DRAM_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L |
21180 | #define GUS_DRAM_PRI_FIXED__GROUP4_FIXED_COEFFICIENT_MASK 0x00007000L |
21181 | #define GUS_DRAM_PRI_FIXED__GROUP5_FIXED_COEFFICIENT_MASK 0x00038000L |
21182 | //GUS_DRAM_PRI_URGENCY_COEFF |
21183 | #define GUS_DRAM_PRI_URGENCY_COEFF__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 |
21184 | #define GUS_DRAM_PRI_URGENCY_COEFF__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 |
21185 | #define GUS_DRAM_PRI_URGENCY_COEFF__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 |
21186 | #define GUS_DRAM_PRI_URGENCY_COEFF__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 |
21187 | #define GUS_DRAM_PRI_URGENCY_COEFF__GROUP4_URGENCY_COEFFICIENT__SHIFT 0xc |
21188 | #define GUS_DRAM_PRI_URGENCY_COEFF__GROUP5_URGENCY_COEFFICIENT__SHIFT 0xf |
21189 | #define GUS_DRAM_PRI_URGENCY_COEFF__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L |
21190 | #define GUS_DRAM_PRI_URGENCY_COEFF__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L |
21191 | #define GUS_DRAM_PRI_URGENCY_COEFF__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L |
21192 | #define GUS_DRAM_PRI_URGENCY_COEFF__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L |
21193 | #define GUS_DRAM_PRI_URGENCY_COEFF__GROUP4_URGENCY_COEFFICIENT_MASK 0x00007000L |
21194 | #define GUS_DRAM_PRI_URGENCY_COEFF__GROUP5_URGENCY_COEFFICIENT_MASK 0x00038000L |
21195 | //GUS_DRAM_PRI_URGENCY_MODE |
21196 | #define GUS_DRAM_PRI_URGENCY_MODE__GROUP0_URGENCY_MODE__SHIFT 0x0 |
21197 | #define GUS_DRAM_PRI_URGENCY_MODE__GROUP1_URGENCY_MODE__SHIFT 0x1 |
21198 | #define GUS_DRAM_PRI_URGENCY_MODE__GROUP2_URGENCY_MODE__SHIFT 0x2 |
21199 | #define GUS_DRAM_PRI_URGENCY_MODE__GROUP3_URGENCY_MODE__SHIFT 0x3 |
21200 | #define GUS_DRAM_PRI_URGENCY_MODE__GROUP4_URGENCY_MODE__SHIFT 0x4 |
21201 | #define GUS_DRAM_PRI_URGENCY_MODE__GROUP5_URGENCY_MODE__SHIFT 0x5 |
21202 | #define GUS_DRAM_PRI_URGENCY_MODE__GROUP0_URGENCY_MODE_MASK 0x00000001L |
21203 | #define GUS_DRAM_PRI_URGENCY_MODE__GROUP1_URGENCY_MODE_MASK 0x00000002L |
21204 | #define GUS_DRAM_PRI_URGENCY_MODE__GROUP2_URGENCY_MODE_MASK 0x00000004L |
21205 | #define GUS_DRAM_PRI_URGENCY_MODE__GROUP3_URGENCY_MODE_MASK 0x00000008L |
21206 | #define GUS_DRAM_PRI_URGENCY_MODE__GROUP4_URGENCY_MODE_MASK 0x00000010L |
21207 | #define GUS_DRAM_PRI_URGENCY_MODE__GROUP5_URGENCY_MODE_MASK 0x00000020L |
21208 | //GUS_DRAM_PRI_QUANT_PRI1 |
21209 | #define GUS_DRAM_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 |
21210 | #define GUS_DRAM_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 |
21211 | #define GUS_DRAM_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 |
21212 | #define GUS_DRAM_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 |
21213 | #define GUS_DRAM_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL |
21214 | #define GUS_DRAM_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L |
21215 | #define GUS_DRAM_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L |
21216 | #define GUS_DRAM_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L |
21217 | //GUS_DRAM_PRI_QUANT_PRI2 |
21218 | #define GUS_DRAM_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 |
21219 | #define GUS_DRAM_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 |
21220 | #define GUS_DRAM_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 |
21221 | #define GUS_DRAM_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 |
21222 | #define GUS_DRAM_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL |
21223 | #define GUS_DRAM_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L |
21224 | #define GUS_DRAM_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L |
21225 | #define GUS_DRAM_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L |
21226 | //GUS_DRAM_PRI_QUANT_PRI3 |
21227 | #define GUS_DRAM_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 |
21228 | #define GUS_DRAM_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 |
21229 | #define GUS_DRAM_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 |
21230 | #define GUS_DRAM_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 |
21231 | #define GUS_DRAM_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL |
21232 | #define GUS_DRAM_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L |
21233 | #define GUS_DRAM_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L |
21234 | #define GUS_DRAM_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L |
21235 | //GUS_DRAM_PRI_QUANT_PRI4 |
21236 | #define GUS_DRAM_PRI_QUANT_PRI4__GROUP0_THRESHOLD__SHIFT 0x0 |
21237 | #define GUS_DRAM_PRI_QUANT_PRI4__GROUP1_THRESHOLD__SHIFT 0x8 |
21238 | #define GUS_DRAM_PRI_QUANT_PRI4__GROUP2_THRESHOLD__SHIFT 0x10 |
21239 | #define GUS_DRAM_PRI_QUANT_PRI4__GROUP3_THRESHOLD__SHIFT 0x18 |
21240 | #define GUS_DRAM_PRI_QUANT_PRI4__GROUP0_THRESHOLD_MASK 0x000000FFL |
21241 | #define GUS_DRAM_PRI_QUANT_PRI4__GROUP1_THRESHOLD_MASK 0x0000FF00L |
21242 | #define GUS_DRAM_PRI_QUANT_PRI4__GROUP2_THRESHOLD_MASK 0x00FF0000L |
21243 | #define GUS_DRAM_PRI_QUANT_PRI4__GROUP3_THRESHOLD_MASK 0xFF000000L |
21244 | //GUS_DRAM_PRI_QUANT_PRI5 |
21245 | #define GUS_DRAM_PRI_QUANT_PRI5__GROUP0_THRESHOLD__SHIFT 0x0 |
21246 | #define GUS_DRAM_PRI_QUANT_PRI5__GROUP1_THRESHOLD__SHIFT 0x8 |
21247 | #define GUS_DRAM_PRI_QUANT_PRI5__GROUP2_THRESHOLD__SHIFT 0x10 |
21248 | #define GUS_DRAM_PRI_QUANT_PRI5__GROUP3_THRESHOLD__SHIFT 0x18 |
21249 | #define GUS_DRAM_PRI_QUANT_PRI5__GROUP0_THRESHOLD_MASK 0x000000FFL |
21250 | #define GUS_DRAM_PRI_QUANT_PRI5__GROUP1_THRESHOLD_MASK 0x0000FF00L |
21251 | #define GUS_DRAM_PRI_QUANT_PRI5__GROUP2_THRESHOLD_MASK 0x00FF0000L |
21252 | #define GUS_DRAM_PRI_QUANT_PRI5__GROUP3_THRESHOLD_MASK 0xFF000000L |
21253 | //GUS_DRAM_PRI_QUANT1_PRI1 |
21254 | #define GUS_DRAM_PRI_QUANT1_PRI1__GROUP4_THRESHOLD__SHIFT 0x0 |
21255 | #define GUS_DRAM_PRI_QUANT1_PRI1__GROUP5_THRESHOLD__SHIFT 0x8 |
21256 | #define GUS_DRAM_PRI_QUANT1_PRI1__GROUP4_THRESHOLD_MASK 0x000000FFL |
21257 | #define GUS_DRAM_PRI_QUANT1_PRI1__GROUP5_THRESHOLD_MASK 0x0000FF00L |
21258 | //GUS_DRAM_PRI_QUANT1_PRI2 |
21259 | #define GUS_DRAM_PRI_QUANT1_PRI2__GROUP4_THRESHOLD__SHIFT 0x0 |
21260 | #define GUS_DRAM_PRI_QUANT1_PRI2__GROUP5_THRESHOLD__SHIFT 0x8 |
21261 | #define GUS_DRAM_PRI_QUANT1_PRI2__GROUP4_THRESHOLD_MASK 0x000000FFL |
21262 | #define GUS_DRAM_PRI_QUANT1_PRI2__GROUP5_THRESHOLD_MASK 0x0000FF00L |
21263 | //GUS_DRAM_PRI_QUANT1_PRI3 |
21264 | #define GUS_DRAM_PRI_QUANT1_PRI3__GROUP4_THRESHOLD__SHIFT 0x0 |
21265 | #define GUS_DRAM_PRI_QUANT1_PRI3__GROUP5_THRESHOLD__SHIFT 0x8 |
21266 | #define GUS_DRAM_PRI_QUANT1_PRI3__GROUP4_THRESHOLD_MASK 0x000000FFL |
21267 | #define GUS_DRAM_PRI_QUANT1_PRI3__GROUP5_THRESHOLD_MASK 0x0000FF00L |
21268 | //GUS_DRAM_PRI_QUANT1_PRI4 |
21269 | #define GUS_DRAM_PRI_QUANT1_PRI4__GROUP4_THRESHOLD__SHIFT 0x0 |
21270 | #define GUS_DRAM_PRI_QUANT1_PRI4__GROUP5_THRESHOLD__SHIFT 0x8 |
21271 | #define GUS_DRAM_PRI_QUANT1_PRI4__GROUP4_THRESHOLD_MASK 0x000000FFL |
21272 | #define GUS_DRAM_PRI_QUANT1_PRI4__GROUP5_THRESHOLD_MASK 0x0000FF00L |
21273 | //GUS_DRAM_PRI_QUANT1_PRI5 |
21274 | #define GUS_DRAM_PRI_QUANT1_PRI5__GROUP4_THRESHOLD__SHIFT 0x0 |
21275 | #define GUS_DRAM_PRI_QUANT1_PRI5__GROUP5_THRESHOLD__SHIFT 0x8 |
21276 | #define GUS_DRAM_PRI_QUANT1_PRI5__GROUP4_THRESHOLD_MASK 0x000000FFL |
21277 | #define GUS_DRAM_PRI_QUANT1_PRI5__GROUP5_THRESHOLD_MASK 0x0000FF00L |
21278 | //GUS_IO_GROUP_BURST |
21279 | #define GUS_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT 0x0 |
21280 | #define GUS_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT 0x8 |
21281 | #define GUS_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT 0x10 |
21282 | #define GUS_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT 0x18 |
21283 | #define GUS_IO_GROUP_BURST__RD_LIMIT_LO_MASK 0x000000FFL |
21284 | #define GUS_IO_GROUP_BURST__RD_LIMIT_HI_MASK 0x0000FF00L |
21285 | #define GUS_IO_GROUP_BURST__WR_LIMIT_LO_MASK 0x00FF0000L |
21286 | #define GUS_IO_GROUP_BURST__WR_LIMIT_HI_MASK 0xFF000000L |
21287 | //GUS_DRAM_GROUP_BURST |
21288 | #define GUS_DRAM_GROUP_BURST__DRAM_LIMIT_LO__SHIFT 0x0 |
21289 | #define GUS_DRAM_GROUP_BURST__DRAM_LIMIT_HI__SHIFT 0x8 |
21290 | #define GUS_DRAM_GROUP_BURST__DRAM_LIMIT_LO_MASK 0x000000FFL |
21291 | #define GUS_DRAM_GROUP_BURST__DRAM_LIMIT_HI_MASK 0x0000FF00L |
21292 | //GUS_SDP_ARB_FINAL |
21293 | #define GUS_SDP_ARB_FINAL__HI_DRAM_BURST_LIMIT__SHIFT 0x0 |
21294 | #define GUS_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x5 |
21295 | #define GUS_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa |
21296 | #define GUS_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf |
21297 | #define GUS_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x11 |
21298 | #define GUS_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x12 |
21299 | #define GUS_SDP_ARB_FINAL__HI_DRAM_BURST_LIMIT_MASK 0x0000001FL |
21300 | #define GUS_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x000003E0L |
21301 | #define GUS_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L |
21302 | #define GUS_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L |
21303 | #define GUS_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x00020000L |
21304 | #define GUS_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x00040000L |
21305 | //GUS_SDP_QOS_VC_PRIORITY |
21306 | #define GUS_SDP_QOS_VC_PRIORITY__VC2_IORD__SHIFT 0x0 |
21307 | #define GUS_SDP_QOS_VC_PRIORITY__VC3_IOWR__SHIFT 0x4 |
21308 | #define GUS_SDP_QOS_VC_PRIORITY__VC4_DRAM__SHIFT 0x8 |
21309 | #define GUS_SDP_QOS_VC_PRIORITY__VC4_HI_DRAM__SHIFT 0xc |
21310 | #define GUS_SDP_QOS_VC_PRIORITY__VC2_IORD_MASK 0x0000000FL |
21311 | #define GUS_SDP_QOS_VC_PRIORITY__VC3_IOWR_MASK 0x000000F0L |
21312 | #define GUS_SDP_QOS_VC_PRIORITY__VC4_DRAM_MASK 0x00000F00L |
21313 | #define GUS_SDP_QOS_VC_PRIORITY__VC4_HI_DRAM_MASK 0x0000F000L |
21314 | //GUS_SDP_CREDITS |
21315 | #define GUS_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0 |
21316 | #define GUS_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8 |
21317 | #define GUS_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10 |
21318 | #define GUS_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL |
21319 | #define GUS_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L |
21320 | #define GUS_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x007F0000L |
21321 | //GUS_SDP_TAG_RESERVE0 |
21322 | #define GUS_SDP_TAG_RESERVE0__VC0__SHIFT 0x0 |
21323 | #define GUS_SDP_TAG_RESERVE0__VC1__SHIFT 0x8 |
21324 | #define GUS_SDP_TAG_RESERVE0__VC2__SHIFT 0x10 |
21325 | #define GUS_SDP_TAG_RESERVE0__VC3__SHIFT 0x18 |
21326 | #define GUS_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL |
21327 | #define GUS_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L |
21328 | #define GUS_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L |
21329 | #define GUS_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L |
21330 | //GUS_SDP_TAG_RESERVE1 |
21331 | #define GUS_SDP_TAG_RESERVE1__VC4__SHIFT 0x0 |
21332 | #define GUS_SDP_TAG_RESERVE1__VC5__SHIFT 0x8 |
21333 | #define GUS_SDP_TAG_RESERVE1__VC6__SHIFT 0x10 |
21334 | #define GUS_SDP_TAG_RESERVE1__VC7__SHIFT 0x18 |
21335 | #define GUS_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL |
21336 | #define GUS_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L |
21337 | #define GUS_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L |
21338 | #define GUS_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L |
21339 | //GUS_SDP_VCC_RESERVE0 |
21340 | #define GUS_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0 |
21341 | #define GUS_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6 |
21342 | #define GUS_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc |
21343 | #define GUS_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12 |
21344 | #define GUS_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18 |
21345 | #define GUS_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL |
21346 | #define GUS_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L |
21347 | #define GUS_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L |
21348 | #define GUS_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L |
21349 | #define GUS_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L |
21350 | //GUS_SDP_VCC_RESERVE1 |
21351 | #define GUS_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0 |
21352 | #define GUS_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6 |
21353 | #define GUS_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc |
21354 | #define GUS_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f |
21355 | #define GUS_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL |
21356 | #define GUS_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L |
21357 | #define GUS_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L |
21358 | #define GUS_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L |
21359 | //GUS_SDP_VCD_RESERVE0 |
21360 | #define GUS_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT 0x0 |
21361 | #define GUS_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT 0x6 |
21362 | #define GUS_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT 0xc |
21363 | #define GUS_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT 0x12 |
21364 | #define GUS_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT 0x18 |
21365 | #define GUS_SDP_VCD_RESERVE0__VC0_CREDITS_MASK 0x0000003FL |
21366 | #define GUS_SDP_VCD_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L |
21367 | #define GUS_SDP_VCD_RESERVE0__VC2_CREDITS_MASK 0x0003F000L |
21368 | #define GUS_SDP_VCD_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L |
21369 | #define GUS_SDP_VCD_RESERVE0__VC4_CREDITS_MASK 0x3F000000L |
21370 | //GUS_SDP_VCD_RESERVE1 |
21371 | #define GUS_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT 0x0 |
21372 | #define GUS_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT 0x6 |
21373 | #define GUS_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT 0xc |
21374 | #define GUS_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f |
21375 | #define GUS_SDP_VCD_RESERVE1__VC5_CREDITS_MASK 0x0000003FL |
21376 | #define GUS_SDP_VCD_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L |
21377 | #define GUS_SDP_VCD_RESERVE1__VC7_CREDITS_MASK 0x0003F000L |
21378 | #define GUS_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L |
21379 | //GUS_SDP_REQ_CNTL |
21380 | #define GUS_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0 |
21381 | #define GUS_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1 |
21382 | #define GUS_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2 |
21383 | #define GUS_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3 |
21384 | #define GUS_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x4 |
21385 | #define GUS_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L |
21386 | #define GUS_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L |
21387 | #define GUS_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L |
21388 | #define GUS_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L |
21389 | #define GUS_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000010L |
21390 | //GUS_MISC |
21391 | #define GUS_MISC__RELATIVE_PRI_IN_DRAM_ARB__SHIFT 0x0 |
21392 | #define GUS_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT 0x1 |
21393 | #define GUS_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT 0x2 |
21394 | #define GUS_MISC__EARLY_SDP_ORIGDATA__SHIFT 0x3 |
21395 | #define GUS_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0x4 |
21396 | #define GUS_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0x6 |
21397 | #define GUS_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0x8 |
21398 | #define GUS_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0xa |
21399 | #define GUS_MISC__SEND0_IOWR_ONLY__SHIFT 0xf |
21400 | #define GUS_MISC__RELATIVE_PRI_IN_DRAM_ARB_MASK 0x00000001L |
21401 | #define GUS_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK 0x00000002L |
21402 | #define GUS_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK 0x00000004L |
21403 | #define GUS_MISC__EARLY_SDP_ORIGDATA_MASK 0x00000008L |
21404 | #define GUS_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00000030L |
21405 | #define GUS_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x000000C0L |
21406 | #define GUS_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00000300L |
21407 | #define GUS_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x00007C00L |
21408 | #define GUS_MISC__SEND0_IOWR_ONLY_MASK 0x00008000L |
21409 | //GUS_LATENCY_SAMPLING |
21410 | #define GUS_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0 |
21411 | #define GUS_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1 |
21412 | #define GUS_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x2 |
21413 | #define GUS_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x3 |
21414 | #define GUS_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x4 |
21415 | #define GUS_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x5 |
21416 | #define GUS_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x6 |
21417 | #define GUS_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x7 |
21418 | #define GUS_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0x8 |
21419 | #define GUS_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0x9 |
21420 | #define GUS_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xa |
21421 | #define GUS_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xb |
21422 | #define GUS_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xc |
21423 | #define GUS_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x14 |
21424 | #define GUS_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L |
21425 | #define GUS_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L |
21426 | #define GUS_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000004L |
21427 | #define GUS_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000008L |
21428 | #define GUS_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000010L |
21429 | #define GUS_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000020L |
21430 | #define GUS_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000040L |
21431 | #define GUS_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000080L |
21432 | #define GUS_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000100L |
21433 | #define GUS_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000200L |
21434 | #define GUS_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00000400L |
21435 | #define GUS_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00000800L |
21436 | #define GUS_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x000FF000L |
21437 | #define GUS_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x0FF00000L |
21438 | //GUS_ERR_STATUS |
21439 | #define GUS_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0 |
21440 | #define GUS_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4 |
21441 | #define GUS_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8 |
21442 | #define GUS_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa |
21443 | #define GUS_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xb |
21444 | #define GUS_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xc |
21445 | #define GUS_ERR_STATUS__FUE_FLAG__SHIFT 0xd |
21446 | #define GUS_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL |
21447 | #define GUS_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L |
21448 | #define GUS_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L |
21449 | #define GUS_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L |
21450 | #define GUS_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000800L |
21451 | #define GUS_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00001000L |
21452 | #define GUS_ERR_STATUS__FUE_FLAG_MASK 0x00002000L |
21453 | //GUS_MISC2 |
21454 | #define GUS_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT 0x0 |
21455 | #define GUS_MISC2__CH_L1_RO_MASK__SHIFT 0x1 |
21456 | #define GUS_MISC2__SA0_L1_RO_MASK__SHIFT 0x2 |
21457 | #define GUS_MISC2__SA1_L1_RO_MASK__SHIFT 0x3 |
21458 | #define GUS_MISC2__SA2_L1_RO_MASK__SHIFT 0x4 |
21459 | #define GUS_MISC2__SA3_L1_RO_MASK__SHIFT 0x5 |
21460 | #define GUS_MISC2__CH_L1_PERF_MASK__SHIFT 0x6 |
21461 | #define GUS_MISC2__SA0_L1_PERF_MASK__SHIFT 0x7 |
21462 | #define GUS_MISC2__SA1_L1_PERF_MASK__SHIFT 0x8 |
21463 | #define GUS_MISC2__SA2_L1_PERF_MASK__SHIFT 0x9 |
21464 | #define GUS_MISC2__SA3_L1_PERF_MASK__SHIFT 0xa |
21465 | #define GUS_MISC2__FP_ATOMICS_ENABLE__SHIFT 0xb |
21466 | #define GUS_MISC2__L1_RET_CLKEN__SHIFT 0xc |
21467 | #define GUS_MISC2__FGCLKEN_HIGH__SHIFT 0xd |
21468 | #define GUS_MISC2__BLOCK_REQUESTS__SHIFT 0xe |
21469 | #define GUS_MISC2__REQUESTS_BLOCKED__SHIFT 0xf |
21470 | #define GUS_MISC2__RIO_ICG_L1_ROUTER_BUSY_MASK__SHIFT 0x10 |
21471 | #define GUS_MISC2__WIO_ICG_L1_ROUTER_BUSY_MASK__SHIFT 0x11 |
21472 | #define GUS_MISC2__DRAM_ICG_L1_ROUTER_BUSY_MASK__SHIFT 0x12 |
21473 | #define GUS_MISC2__RDRET_FED_MASK__SHIFT 0x13 |
21474 | #define GUS_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK 0x00000001L |
21475 | #define GUS_MISC2__CH_L1_RO_MASK_MASK 0x00000002L |
21476 | #define GUS_MISC2__SA0_L1_RO_MASK_MASK 0x00000004L |
21477 | #define GUS_MISC2__SA1_L1_RO_MASK_MASK 0x00000008L |
21478 | #define GUS_MISC2__SA2_L1_RO_MASK_MASK 0x00000010L |
21479 | #define GUS_MISC2__SA3_L1_RO_MASK_MASK 0x00000020L |
21480 | #define GUS_MISC2__CH_L1_PERF_MASK_MASK 0x00000040L |
21481 | #define GUS_MISC2__SA0_L1_PERF_MASK_MASK 0x00000080L |
21482 | #define GUS_MISC2__SA1_L1_PERF_MASK_MASK 0x00000100L |
21483 | #define GUS_MISC2__SA2_L1_PERF_MASK_MASK 0x00000200L |
21484 | #define GUS_MISC2__SA3_L1_PERF_MASK_MASK 0x00000400L |
21485 | #define GUS_MISC2__FP_ATOMICS_ENABLE_MASK 0x00000800L |
21486 | #define GUS_MISC2__L1_RET_CLKEN_MASK 0x00001000L |
21487 | #define GUS_MISC2__FGCLKEN_HIGH_MASK 0x00002000L |
21488 | #define GUS_MISC2__BLOCK_REQUESTS_MASK 0x00004000L |
21489 | #define GUS_MISC2__REQUESTS_BLOCKED_MASK 0x00008000L |
21490 | #define GUS_MISC2__RIO_ICG_L1_ROUTER_BUSY_MASK_MASK 0x00010000L |
21491 | #define GUS_MISC2__WIO_ICG_L1_ROUTER_BUSY_MASK_MASK 0x00020000L |
21492 | #define GUS_MISC2__DRAM_ICG_L1_ROUTER_BUSY_MASK_MASK 0x00040000L |
21493 | #define GUS_MISC2__RDRET_FED_MASK_MASK 0x00080000L |
21494 | //GUS_SDP_BACKDOOR_CMDCREDITS0 |
21495 | #define GUS_SDP_BACKDOOR_CMDCREDITS0__CREDITS_RECEIVED__SHIFT 0x0 |
21496 | #define GUS_SDP_BACKDOOR_CMDCREDITS0__CREDITS_RECEIVED_MASK 0xFFFFFFFFL |
21497 | //GUS_SDP_BACKDOOR_CMDCREDITS1 |
21498 | #define GUS_SDP_BACKDOOR_CMDCREDITS1__CREDITS_RECEIVED__SHIFT 0x0 |
21499 | #define GUS_SDP_BACKDOOR_CMDCREDITS1__CREDITS_RECEIVED_MASK 0x7FFFFFFFL |
21500 | //GUS_SDP_BACKDOOR_DATACREDITS0 |
21501 | #define GUS_SDP_BACKDOOR_DATACREDITS0__CREDITS_RECEIVED__SHIFT 0x0 |
21502 | #define GUS_SDP_BACKDOOR_DATACREDITS0__CREDITS_RECEIVED_MASK 0xFFFFFFFFL |
21503 | //GUS_SDP_BACKDOOR_DATACREDITS1 |
21504 | #define GUS_SDP_BACKDOOR_DATACREDITS1__CREDITS_RECEIVED__SHIFT 0x0 |
21505 | #define GUS_SDP_BACKDOOR_DATACREDITS1__CREDITS_RECEIVED_MASK 0x7FFFFFFFL |
21506 | //GUS_SDP_BACKDOOR_MISCCREDITS |
21507 | #define GUS_SDP_BACKDOOR_MISCCREDITS__RDRSP_CREDITS_RELEASED__SHIFT 0x0 |
21508 | #define GUS_SDP_BACKDOOR_MISCCREDITS__WRRSP_CREDITS_RELEASED__SHIFT 0x8 |
21509 | #define GUS_SDP_BACKDOOR_MISCCREDITS__RDRSP_CREDITS_RELEASED_MASK 0x000000FFL |
21510 | #define GUS_SDP_BACKDOOR_MISCCREDITS__WRRSP_CREDITS_RELEASED_MASK 0x0000FF00L |
21511 | //GUS_SDP_ENABLE |
21512 | #define GUS_SDP_ENABLE__ENABLE__SHIFT 0x0 |
21513 | #define GUS_SDP_ENABLE__ENABLE_MASK 0x00000001L |
21514 | //GUS_L1_CH0_CMD_IN |
21515 | #define GUS_L1_CH0_CMD_IN__COUNT__SHIFT 0x0 |
21516 | #define GUS_L1_CH0_CMD_IN__COUNT_MASK 0xFFFFFFFFL |
21517 | //GUS_L1_CH0_CMD_OUT |
21518 | #define GUS_L1_CH0_CMD_OUT__COUNT__SHIFT 0x0 |
21519 | #define GUS_L1_CH0_CMD_OUT__COUNT_MASK 0xFFFFFFFFL |
21520 | //GUS_L1_CH0_DATA_IN |
21521 | #define GUS_L1_CH0_DATA_IN__COUNT__SHIFT 0x0 |
21522 | #define GUS_L1_CH0_DATA_IN__COUNT_MASK 0xFFFFFFFFL |
21523 | //GUS_L1_CH0_DATA_OUT |
21524 | #define GUS_L1_CH0_DATA_OUT__COUNT__SHIFT 0x0 |
21525 | #define GUS_L1_CH0_DATA_OUT__COUNT_MASK 0xFFFFFFFFL |
21526 | //GUS_L1_CH0_DATA_U_IN |
21527 | #define GUS_L1_CH0_DATA_U_IN__COUNT__SHIFT 0x0 |
21528 | #define GUS_L1_CH0_DATA_U_IN__COUNT_MASK 0xFFFFFFFFL |
21529 | //GUS_L1_CH0_DATA_U_OUT |
21530 | #define GUS_L1_CH0_DATA_U_OUT__COUNT__SHIFT 0x0 |
21531 | #define GUS_L1_CH0_DATA_U_OUT__COUNT_MASK 0xFFFFFFFFL |
21532 | //GUS_L1_CH1_CMD_IN |
21533 | #define GUS_L1_CH1_CMD_IN__COUNT__SHIFT 0x0 |
21534 | #define GUS_L1_CH1_CMD_IN__COUNT_MASK 0xFFFFFFFFL |
21535 | //GUS_L1_CH1_CMD_OUT |
21536 | #define GUS_L1_CH1_CMD_OUT__COUNT__SHIFT 0x0 |
21537 | #define GUS_L1_CH1_CMD_OUT__COUNT_MASK 0xFFFFFFFFL |
21538 | //GUS_L1_CH1_DATA_IN |
21539 | #define GUS_L1_CH1_DATA_IN__COUNT__SHIFT 0x0 |
21540 | #define GUS_L1_CH1_DATA_IN__COUNT_MASK 0xFFFFFFFFL |
21541 | //GUS_L1_CH1_DATA_OUT |
21542 | #define GUS_L1_CH1_DATA_OUT__COUNT__SHIFT 0x0 |
21543 | #define GUS_L1_CH1_DATA_OUT__COUNT_MASK 0xFFFFFFFFL |
21544 | //GUS_L1_CH1_DATA_U_IN |
21545 | #define GUS_L1_CH1_DATA_U_IN__COUNT__SHIFT 0x0 |
21546 | #define GUS_L1_CH1_DATA_U_IN__COUNT_MASK 0xFFFFFFFFL |
21547 | //GUS_L1_CH1_DATA_U_OUT |
21548 | #define GUS_L1_CH1_DATA_U_OUT__COUNT__SHIFT 0x0 |
21549 | #define GUS_L1_CH1_DATA_U_OUT__COUNT_MASK 0xFFFFFFFFL |
21550 | //GUS_L1_SA0_CMD_IN |
21551 | #define GUS_L1_SA0_CMD_IN__COUNT__SHIFT 0x0 |
21552 | #define GUS_L1_SA0_CMD_IN__COUNT_MASK 0xFFFFFFFFL |
21553 | //GUS_L1_SA0_CMD_OUT |
21554 | #define GUS_L1_SA0_CMD_OUT__COUNT__SHIFT 0x0 |
21555 | #define GUS_L1_SA0_CMD_OUT__COUNT_MASK 0xFFFFFFFFL |
21556 | //GUS_L1_SA0_DATA_IN |
21557 | #define GUS_L1_SA0_DATA_IN__COUNT__SHIFT 0x0 |
21558 | #define GUS_L1_SA0_DATA_IN__COUNT_MASK 0xFFFFFFFFL |
21559 | //GUS_L1_SA0_DATA_OUT |
21560 | #define GUS_L1_SA0_DATA_OUT__COUNT__SHIFT 0x0 |
21561 | #define GUS_L1_SA0_DATA_OUT__COUNT_MASK 0xFFFFFFFFL |
21562 | //GUS_L1_SA0_DATA_U_IN |
21563 | #define GUS_L1_SA0_DATA_U_IN__COUNT__SHIFT 0x0 |
21564 | #define GUS_L1_SA0_DATA_U_IN__COUNT_MASK 0xFFFFFFFFL |
21565 | //GUS_L1_SA0_DATA_U_OUT |
21566 | #define GUS_L1_SA0_DATA_U_OUT__COUNT__SHIFT 0x0 |
21567 | #define GUS_L1_SA0_DATA_U_OUT__COUNT_MASK 0xFFFFFFFFL |
21568 | //GUS_L1_SA1_CMD_IN |
21569 | #define GUS_L1_SA1_CMD_IN__COUNT__SHIFT 0x0 |
21570 | #define GUS_L1_SA1_CMD_IN__COUNT_MASK 0xFFFFFFFFL |
21571 | //GUS_L1_SA1_CMD_OUT |
21572 | #define GUS_L1_SA1_CMD_OUT__COUNT__SHIFT 0x0 |
21573 | #define GUS_L1_SA1_CMD_OUT__COUNT_MASK 0xFFFFFFFFL |
21574 | //GUS_L1_SA1_DATA_IN |
21575 | #define GUS_L1_SA1_DATA_IN__COUNT__SHIFT 0x0 |
21576 | #define GUS_L1_SA1_DATA_IN__COUNT_MASK 0xFFFFFFFFL |
21577 | //GUS_L1_SA1_DATA_OUT |
21578 | #define GUS_L1_SA1_DATA_OUT__COUNT__SHIFT 0x0 |
21579 | #define GUS_L1_SA1_DATA_OUT__COUNT_MASK 0xFFFFFFFFL |
21580 | //GUS_L1_SA1_DATA_U_IN |
21581 | #define GUS_L1_SA1_DATA_U_IN__COUNT__SHIFT 0x0 |
21582 | #define GUS_L1_SA1_DATA_U_IN__COUNT_MASK 0xFFFFFFFFL |
21583 | //GUS_L1_SA1_DATA_U_OUT |
21584 | #define GUS_L1_SA1_DATA_U_OUT__COUNT__SHIFT 0x0 |
21585 | #define GUS_L1_SA1_DATA_U_OUT__COUNT_MASK 0xFFFFFFFFL |
21586 | //GUS_L1_SA2_CMD_IN |
21587 | #define GUS_L1_SA2_CMD_IN__COUNT__SHIFT 0x0 |
21588 | #define GUS_L1_SA2_CMD_IN__COUNT_MASK 0xFFFFFFFFL |
21589 | //GUS_L1_SA2_CMD_OUT |
21590 | #define GUS_L1_SA2_CMD_OUT__COUNT__SHIFT 0x0 |
21591 | #define GUS_L1_SA2_CMD_OUT__COUNT_MASK 0xFFFFFFFFL |
21592 | //GUS_L1_SA2_DATA_IN |
21593 | #define GUS_L1_SA2_DATA_IN__COUNT__SHIFT 0x0 |
21594 | #define GUS_L1_SA2_DATA_IN__COUNT_MASK 0xFFFFFFFFL |
21595 | //GUS_L1_SA2_DATA_OUT |
21596 | #define GUS_L1_SA2_DATA_OUT__COUNT__SHIFT 0x0 |
21597 | #define GUS_L1_SA2_DATA_OUT__COUNT_MASK 0xFFFFFFFFL |
21598 | //GUS_L1_SA2_DATA_U_IN |
21599 | #define GUS_L1_SA2_DATA_U_IN__COUNT__SHIFT 0x0 |
21600 | #define GUS_L1_SA2_DATA_U_IN__COUNT_MASK 0xFFFFFFFFL |
21601 | //GUS_L1_SA2_DATA_U_OUT |
21602 | #define GUS_L1_SA2_DATA_U_OUT__COUNT__SHIFT 0x0 |
21603 | #define GUS_L1_SA2_DATA_U_OUT__COUNT_MASK 0xFFFFFFFFL |
21604 | //GUS_L1_SA3_CMD_IN |
21605 | #define GUS_L1_SA3_CMD_IN__COUNT__SHIFT 0x0 |
21606 | #define GUS_L1_SA3_CMD_IN__COUNT_MASK 0xFFFFFFFFL |
21607 | //GUS_L1_SA3_CMD_OUT |
21608 | #define GUS_L1_SA3_CMD_OUT__COUNT__SHIFT 0x0 |
21609 | #define GUS_L1_SA3_CMD_OUT__COUNT_MASK 0xFFFFFFFFL |
21610 | //GUS_L1_SA3_DATA_IN |
21611 | #define GUS_L1_SA3_DATA_IN__COUNT__SHIFT 0x0 |
21612 | #define GUS_L1_SA3_DATA_IN__COUNT_MASK 0xFFFFFFFFL |
21613 | //GUS_L1_SA3_DATA_OUT |
21614 | #define GUS_L1_SA3_DATA_OUT__COUNT__SHIFT 0x0 |
21615 | #define GUS_L1_SA3_DATA_OUT__COUNT_MASK 0xFFFFFFFFL |
21616 | //GUS_L1_SA3_DATA_U_IN |
21617 | #define GUS_L1_SA3_DATA_U_IN__COUNT__SHIFT 0x0 |
21618 | #define GUS_L1_SA3_DATA_U_IN__COUNT_MASK 0xFFFFFFFFL |
21619 | //GUS_L1_SA3_DATA_U_OUT |
21620 | #define GUS_L1_SA3_DATA_U_OUT__COUNT__SHIFT 0x0 |
21621 | #define GUS_L1_SA3_DATA_U_OUT__COUNT_MASK 0xFFFFFFFFL |
21622 | //GUS_MISC3 |
21623 | #define GUS_MISC3__FP_ATOMICS_LOG__SHIFT 0x0 |
21624 | #define GUS_MISC3__CLEAR_LOG__SHIFT 0x1 |
21625 | #define GUS_MISC3__FP_ATOMICS_LOG_MASK 0x00000001L |
21626 | #define GUS_MISC3__CLEAR_LOG_MASK 0x00000002L |
21627 | //GUS_WRRSP_FIFO_CNTL |
21628 | #define GUS_WRRSP_FIFO_CNTL__THRESHOLD__SHIFT 0x0 |
21629 | #define GUS_WRRSP_FIFO_CNTL__THRESHOLD_MASK 0x0000003FL |
21630 | |
21631 | |
21632 | // addressBlock: gc_gfxdec0 |
21633 | //DB_RENDER_CONTROL |
21634 | #define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE__SHIFT 0x0 |
21635 | #define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE__SHIFT 0x1 |
21636 | #define DB_RENDER_CONTROL__DEPTH_COPY__SHIFT 0x2 |
21637 | #define DB_RENDER_CONTROL__STENCIL_COPY__SHIFT 0x3 |
21638 | #define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE__SHIFT 0x4 |
21639 | #define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE__SHIFT 0x5 |
21640 | #define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE__SHIFT 0x6 |
21641 | #define DB_RENDER_CONTROL__COPY_CENTROID__SHIFT 0x7 |
21642 | #define DB_RENDER_CONTROL__COPY_SAMPLE__SHIFT 0x8 |
21643 | #define DB_RENDER_CONTROL__DECOMPRESS_ENABLE__SHIFT 0xc |
21644 | #define DB_RENDER_CONTROL__PS_INVOKE_DISABLE__SHIFT 0xe |
21645 | #define DB_RENDER_CONTROL__OREO_MODE__SHIFT 0x10 |
21646 | #define DB_RENDER_CONTROL__FORCE_OREO_MODE__SHIFT 0x12 |
21647 | #define DB_RENDER_CONTROL__FORCE_EXPORT_ORDER__SHIFT 0x13 |
21648 | #define DB_RENDER_CONTROL__MAX_ALLOWED_TILES_IN_WAVE__SHIFT 0x14 |
21649 | #define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE_MASK 0x00000001L |
21650 | #define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE_MASK 0x00000002L |
21651 | #define DB_RENDER_CONTROL__DEPTH_COPY_MASK 0x00000004L |
21652 | #define DB_RENDER_CONTROL__STENCIL_COPY_MASK 0x00000008L |
21653 | #define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE_MASK 0x00000010L |
21654 | #define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE_MASK 0x00000020L |
21655 | #define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE_MASK 0x00000040L |
21656 | #define DB_RENDER_CONTROL__COPY_CENTROID_MASK 0x00000080L |
21657 | #define DB_RENDER_CONTROL__COPY_SAMPLE_MASK 0x00000F00L |
21658 | #define DB_RENDER_CONTROL__DECOMPRESS_ENABLE_MASK 0x00001000L |
21659 | #define DB_RENDER_CONTROL__PS_INVOKE_DISABLE_MASK 0x00004000L |
21660 | #define DB_RENDER_CONTROL__OREO_MODE_MASK 0x00030000L |
21661 | #define DB_RENDER_CONTROL__FORCE_OREO_MODE_MASK 0x00040000L |
21662 | #define DB_RENDER_CONTROL__FORCE_EXPORT_ORDER_MASK 0x00080000L |
21663 | #define DB_RENDER_CONTROL__MAX_ALLOWED_TILES_IN_WAVE_MASK 0x00F00000L |
21664 | //DB_COUNT_CONTROL |
21665 | #define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS__SHIFT 0x1 |
21666 | #define DB_COUNT_CONTROL__DISABLE_CONSERVATIVE_ZPASS_COUNTS__SHIFT 0x2 |
21667 | #define DB_COUNT_CONTROL__ENHANCED_CONSERVATIVE_ZPASS_COUNTS__SHIFT 0x3 |
21668 | #define DB_COUNT_CONTROL__SAMPLE_RATE__SHIFT 0x4 |
21669 | #define DB_COUNT_CONTROL__ZPASS_ENABLE__SHIFT 0x8 |
21670 | #define DB_COUNT_CONTROL__ZFAIL_ENABLE__SHIFT 0xc |
21671 | #define DB_COUNT_CONTROL__SFAIL_ENABLE__SHIFT 0x10 |
21672 | #define DB_COUNT_CONTROL__DBFAIL_ENABLE__SHIFT 0x14 |
21673 | #define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE__SHIFT 0x18 |
21674 | #define DB_COUNT_CONTROL__SLICE_ODD_ENABLE__SHIFT 0x1c |
21675 | #define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS_MASK 0x00000002L |
21676 | #define DB_COUNT_CONTROL__DISABLE_CONSERVATIVE_ZPASS_COUNTS_MASK 0x00000004L |
21677 | #define DB_COUNT_CONTROL__ENHANCED_CONSERVATIVE_ZPASS_COUNTS_MASK 0x00000008L |
21678 | #define DB_COUNT_CONTROL__SAMPLE_RATE_MASK 0x00000070L |
21679 | #define DB_COUNT_CONTROL__ZPASS_ENABLE_MASK 0x00000F00L |
21680 | #define DB_COUNT_CONTROL__ZFAIL_ENABLE_MASK 0x0000F000L |
21681 | #define DB_COUNT_CONTROL__SFAIL_ENABLE_MASK 0x000F0000L |
21682 | #define DB_COUNT_CONTROL__DBFAIL_ENABLE_MASK 0x00F00000L |
21683 | #define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE_MASK 0x0F000000L |
21684 | #define DB_COUNT_CONTROL__SLICE_ODD_ENABLE_MASK 0xF0000000L |
21685 | //DB_DEPTH_VIEW |
21686 | #define DB_DEPTH_VIEW__SLICE_START__SHIFT 0x0 |
21687 | #define DB_DEPTH_VIEW__SLICE_START_HI__SHIFT 0xb |
21688 | #define DB_DEPTH_VIEW__SLICE_MAX__SHIFT 0xd |
21689 | #define DB_DEPTH_VIEW__Z_READ_ONLY__SHIFT 0x18 |
21690 | #define DB_DEPTH_VIEW__STENCIL_READ_ONLY__SHIFT 0x19 |
21691 | #define DB_DEPTH_VIEW__MIPID__SHIFT 0x1a |
21692 | #define DB_DEPTH_VIEW__SLICE_MAX_HI__SHIFT 0x1e |
21693 | #define DB_DEPTH_VIEW__SLICE_START_MASK 0x000007FFL |
21694 | #define DB_DEPTH_VIEW__SLICE_START_HI_MASK 0x00001800L |
21695 | #define DB_DEPTH_VIEW__SLICE_MAX_MASK 0x00FFE000L |
21696 | #define DB_DEPTH_VIEW__Z_READ_ONLY_MASK 0x01000000L |
21697 | #define DB_DEPTH_VIEW__STENCIL_READ_ONLY_MASK 0x02000000L |
21698 | #define DB_DEPTH_VIEW__MIPID_MASK 0x3C000000L |
21699 | #define DB_DEPTH_VIEW__SLICE_MAX_HI_MASK 0xC0000000L |
21700 | //DB_RENDER_OVERRIDE |
21701 | #define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE__SHIFT 0x0 |
21702 | #define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0__SHIFT 0x2 |
21703 | #define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1__SHIFT 0x4 |
21704 | #define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER__SHIFT 0x6 |
21705 | #define DB_RENDER_OVERRIDE__FAST_Z_DISABLE__SHIFT 0x7 |
21706 | #define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE__SHIFT 0x8 |
21707 | #define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE__SHIFT 0x9 |
21708 | #define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL__SHIFT 0xa |
21709 | #define DB_RENDER_OVERRIDE__FORCE_Z_READ__SHIFT 0xb |
21710 | #define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ__SHIFT 0xc |
21711 | #define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE__SHIFT 0xd |
21712 | #define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP__SHIFT 0x10 |
21713 | #define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE__SHIFT 0x11 |
21714 | #define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED__SHIFT 0x12 |
21715 | #define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM__SHIFT 0x13 |
21716 | #define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT__SHIFT 0x15 |
21717 | #define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES__SHIFT 0x1a |
21718 | #define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY__SHIFT 0x1b |
21719 | #define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY__SHIFT 0x1c |
21720 | #define DB_RENDER_OVERRIDE__FORCE_Z_VALID__SHIFT 0x1d |
21721 | #define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID__SHIFT 0x1e |
21722 | #define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION__SHIFT 0x1f |
21723 | #define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE_MASK 0x00000003L |
21724 | #define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0_MASK 0x0000000CL |
21725 | #define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1_MASK 0x00000030L |
21726 | #define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER_MASK 0x00000040L |
21727 | #define DB_RENDER_OVERRIDE__FAST_Z_DISABLE_MASK 0x00000080L |
21728 | #define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE_MASK 0x00000100L |
21729 | #define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE_MASK 0x00000200L |
21730 | #define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL_MASK 0x00000400L |
21731 | #define DB_RENDER_OVERRIDE__FORCE_Z_READ_MASK 0x00000800L |
21732 | #define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ_MASK 0x00001000L |
21733 | #define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE_MASK 0x00006000L |
21734 | #define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP_MASK 0x00010000L |
21735 | #define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE_MASK 0x00020000L |
21736 | #define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED_MASK 0x00040000L |
21737 | #define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM_MASK 0x00180000L |
21738 | #define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT_MASK 0x03E00000L |
21739 | #define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES_MASK 0x04000000L |
21740 | #define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY_MASK 0x08000000L |
21741 | #define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY_MASK 0x10000000L |
21742 | #define DB_RENDER_OVERRIDE__FORCE_Z_VALID_MASK 0x20000000L |
21743 | #define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID_MASK 0x40000000L |
21744 | #define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION_MASK 0x80000000L |
21745 | //DB_RENDER_OVERRIDE2 |
21746 | #define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL__SHIFT 0x0 |
21747 | #define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN__SHIFT 0x2 |
21748 | #define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION__SHIFT 0x5 |
21749 | #define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION__SHIFT 0x6 |
21750 | #define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION__SHIFT 0x7 |
21751 | #define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH__SHIFT 0x8 |
21752 | #define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP__SHIFT 0x9 |
21753 | #define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE__SHIFT 0xa |
21754 | #define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE__SHIFT 0xb |
21755 | #define DB_RENDER_OVERRIDE2__HIZ_ZFUNC__SHIFT 0xc |
21756 | #define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF__SHIFT 0xf |
21757 | #define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF__SHIFT 0x12 |
21758 | #define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE__SHIFT 0x15 |
21759 | #define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS__SHIFT 0x16 |
21760 | #define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS__SHIFT 0x17 |
21761 | #define DB_RENDER_OVERRIDE2__ALLOW_PARTIAL_RES_HIER_KILL__SHIFT 0x19 |
21762 | #define DB_RENDER_OVERRIDE2__CENTROID_COMPUTATION_MODE__SHIFT 0x1b |
21763 | #define DB_RENDER_OVERRIDE2__DISABLE_NOZ__SHIFT 0x1d |
21764 | #define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL_MASK 0x00000003L |
21765 | #define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN_MASK 0x0000001CL |
21766 | #define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION_MASK 0x00000020L |
21767 | #define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION_MASK 0x00000040L |
21768 | #define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION_MASK 0x00000080L |
21769 | #define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH_MASK 0x00000100L |
21770 | #define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP_MASK 0x00000200L |
21771 | #define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE_MASK 0x00000400L |
21772 | #define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE_MASK 0x00000800L |
21773 | #define DB_RENDER_OVERRIDE2__HIZ_ZFUNC_MASK 0x00007000L |
21774 | #define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF_MASK 0x00038000L |
21775 | #define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF_MASK 0x001C0000L |
21776 | #define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE_MASK 0x00200000L |
21777 | #define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS_MASK 0x00400000L |
21778 | #define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS_MASK 0x00800000L |
21779 | #define DB_RENDER_OVERRIDE2__ALLOW_PARTIAL_RES_HIER_KILL_MASK 0x02000000L |
21780 | #define DB_RENDER_OVERRIDE2__CENTROID_COMPUTATION_MODE_MASK 0x18000000L |
21781 | #define DB_RENDER_OVERRIDE2__DISABLE_NOZ_MASK 0x20000000L |
21782 | //DB_HTILE_DATA_BASE |
21783 | #define DB_HTILE_DATA_BASE__BASE_256B__SHIFT 0x0 |
21784 | #define DB_HTILE_DATA_BASE__BASE_256B_MASK 0xFFFFFFFFL |
21785 | //DB_DEPTH_SIZE_XY |
21786 | #define DB_DEPTH_SIZE_XY__X_MAX__SHIFT 0x0 |
21787 | #define DB_DEPTH_SIZE_XY__Y_MAX__SHIFT 0x10 |
21788 | #define DB_DEPTH_SIZE_XY__X_MAX_MASK 0x00003FFFL |
21789 | #define DB_DEPTH_SIZE_XY__Y_MAX_MASK 0x3FFF0000L |
21790 | //DB_DEPTH_BOUNDS_MIN |
21791 | #define DB_DEPTH_BOUNDS_MIN__MIN__SHIFT 0x0 |
21792 | #define DB_DEPTH_BOUNDS_MIN__MIN_MASK 0xFFFFFFFFL |
21793 | //DB_DEPTH_BOUNDS_MAX |
21794 | #define DB_DEPTH_BOUNDS_MAX__MAX__SHIFT 0x0 |
21795 | #define DB_DEPTH_BOUNDS_MAX__MAX_MASK 0xFFFFFFFFL |
21796 | //DB_STENCIL_CLEAR |
21797 | #define DB_STENCIL_CLEAR__CLEAR__SHIFT 0x0 |
21798 | #define DB_STENCIL_CLEAR__CLEAR_MASK 0x000000FFL |
21799 | //DB_DEPTH_CLEAR |
21800 | #define DB_DEPTH_CLEAR__DEPTH_CLEAR__SHIFT 0x0 |
21801 | #define DB_DEPTH_CLEAR__DEPTH_CLEAR_MASK 0xFFFFFFFFL |
21802 | //PA_SC_SCREEN_SCISSOR_TL |
21803 | #define PA_SC_SCREEN_SCISSOR_TL__TL_X__SHIFT 0x0 |
21804 | #define PA_SC_SCREEN_SCISSOR_TL__TL_Y__SHIFT 0x10 |
21805 | #define PA_SC_SCREEN_SCISSOR_TL__TL_X_MASK 0x0000FFFFL |
21806 | #define PA_SC_SCREEN_SCISSOR_TL__TL_Y_MASK 0xFFFF0000L |
21807 | //PA_SC_SCREEN_SCISSOR_BR |
21808 | #define PA_SC_SCREEN_SCISSOR_BR__BR_X__SHIFT 0x0 |
21809 | #define PA_SC_SCREEN_SCISSOR_BR__BR_Y__SHIFT 0x10 |
21810 | #define PA_SC_SCREEN_SCISSOR_BR__BR_X_MASK 0x0000FFFFL |
21811 | #define PA_SC_SCREEN_SCISSOR_BR__BR_Y_MASK 0xFFFF0000L |
21812 | //DB_RESERVED_REG_2 |
21813 | #define DB_RESERVED_REG_2__FIELD_1__SHIFT 0x0 |
21814 | #define DB_RESERVED_REG_2__FIELD_2__SHIFT 0x4 |
21815 | #define DB_RESERVED_REG_2__FIELD_3__SHIFT 0x8 |
21816 | #define DB_RESERVED_REG_2__FIELD_4__SHIFT 0xd |
21817 | #define DB_RESERVED_REG_2__FIELD_5__SHIFT 0xf |
21818 | #define DB_RESERVED_REG_2__FIELD_6__SHIFT 0x11 |
21819 | #define DB_RESERVED_REG_2__FIELD_7__SHIFT 0x13 |
21820 | #define DB_RESERVED_REG_2__FIELD_8__SHIFT 0x1c |
21821 | #define DB_RESERVED_REG_2__FIELD_1_MASK 0x0000000FL |
21822 | #define DB_RESERVED_REG_2__FIELD_2_MASK 0x000000F0L |
21823 | #define DB_RESERVED_REG_2__FIELD_3_MASK 0x00001F00L |
21824 | #define DB_RESERVED_REG_2__FIELD_4_MASK 0x00006000L |
21825 | #define DB_RESERVED_REG_2__FIELD_5_MASK 0x00018000L |
21826 | #define DB_RESERVED_REG_2__FIELD_6_MASK 0x00060000L |
21827 | #define DB_RESERVED_REG_2__FIELD_7_MASK 0x00180000L |
21828 | #define DB_RESERVED_REG_2__FIELD_8_MASK 0xF0000000L |
21829 | //DB_Z_INFO |
21830 | #define DB_Z_INFO__FORMAT__SHIFT 0x0 |
21831 | #define DB_Z_INFO__NUM_SAMPLES__SHIFT 0x2 |
21832 | #define DB_Z_INFO__SW_MODE__SHIFT 0x4 |
21833 | #define DB_Z_INFO__FAULT_BEHAVIOR__SHIFT 0x9 |
21834 | #define DB_Z_INFO__ITERATE_FLUSH__SHIFT 0xb |
21835 | #define DB_Z_INFO__PARTIALLY_RESIDENT__SHIFT 0xc |
21836 | #define DB_Z_INFO__RESERVED_FIELD_1__SHIFT 0xd |
21837 | #define DB_Z_INFO__MAXMIP__SHIFT 0x10 |
21838 | #define DB_Z_INFO__ITERATE_256__SHIFT 0x14 |
21839 | #define DB_Z_INFO__DECOMPRESS_ON_N_ZPLANES__SHIFT 0x17 |
21840 | #define DB_Z_INFO__ALLOW_EXPCLEAR__SHIFT 0x1b |
21841 | #define DB_Z_INFO__READ_SIZE__SHIFT 0x1c |
21842 | #define DB_Z_INFO__TILE_SURFACE_ENABLE__SHIFT 0x1d |
21843 | #define DB_Z_INFO__ZRANGE_PRECISION__SHIFT 0x1f |
21844 | #define DB_Z_INFO__FORMAT_MASK 0x00000003L |
21845 | #define DB_Z_INFO__NUM_SAMPLES_MASK 0x0000000CL |
21846 | #define DB_Z_INFO__SW_MODE_MASK 0x000001F0L |
21847 | #define DB_Z_INFO__FAULT_BEHAVIOR_MASK 0x00000600L |
21848 | #define DB_Z_INFO__ITERATE_FLUSH_MASK 0x00000800L |
21849 | #define DB_Z_INFO__PARTIALLY_RESIDENT_MASK 0x00001000L |
21850 | #define DB_Z_INFO__RESERVED_FIELD_1_MASK 0x0000E000L |
21851 | #define DB_Z_INFO__MAXMIP_MASK 0x000F0000L |
21852 | #define DB_Z_INFO__ITERATE_256_MASK 0x00100000L |
21853 | #define DB_Z_INFO__DECOMPRESS_ON_N_ZPLANES_MASK 0x07800000L |
21854 | #define DB_Z_INFO__ALLOW_EXPCLEAR_MASK 0x08000000L |
21855 | #define DB_Z_INFO__READ_SIZE_MASK 0x10000000L |
21856 | #define DB_Z_INFO__TILE_SURFACE_ENABLE_MASK 0x20000000L |
21857 | #define DB_Z_INFO__ZRANGE_PRECISION_MASK 0x80000000L |
21858 | //DB_STENCIL_INFO |
21859 | #define DB_STENCIL_INFO__FORMAT__SHIFT 0x0 |
21860 | #define DB_STENCIL_INFO__SW_MODE__SHIFT 0x4 |
21861 | #define DB_STENCIL_INFO__FAULT_BEHAVIOR__SHIFT 0x9 |
21862 | #define DB_STENCIL_INFO__ITERATE_FLUSH__SHIFT 0xb |
21863 | #define DB_STENCIL_INFO__PARTIALLY_RESIDENT__SHIFT 0xc |
21864 | #define DB_STENCIL_INFO__RESERVED_FIELD_1__SHIFT 0xd |
21865 | #define DB_STENCIL_INFO__ITERATE_256__SHIFT 0x14 |
21866 | #define DB_STENCIL_INFO__ALLOW_EXPCLEAR__SHIFT 0x1b |
21867 | #define DB_STENCIL_INFO__TILE_STENCIL_DISABLE__SHIFT 0x1d |
21868 | #define DB_STENCIL_INFO__FORMAT_MASK 0x00000001L |
21869 | #define DB_STENCIL_INFO__SW_MODE_MASK 0x000001F0L |
21870 | #define DB_STENCIL_INFO__FAULT_BEHAVIOR_MASK 0x00000600L |
21871 | #define DB_STENCIL_INFO__ITERATE_FLUSH_MASK 0x00000800L |
21872 | #define DB_STENCIL_INFO__PARTIALLY_RESIDENT_MASK 0x00001000L |
21873 | #define DB_STENCIL_INFO__RESERVED_FIELD_1_MASK 0x0000E000L |
21874 | #define DB_STENCIL_INFO__ITERATE_256_MASK 0x00100000L |
21875 | #define DB_STENCIL_INFO__ALLOW_EXPCLEAR_MASK 0x08000000L |
21876 | #define DB_STENCIL_INFO__TILE_STENCIL_DISABLE_MASK 0x20000000L |
21877 | //DB_Z_READ_BASE |
21878 | #define DB_Z_READ_BASE__BASE_256B__SHIFT 0x0 |
21879 | #define DB_Z_READ_BASE__BASE_256B_MASK 0xFFFFFFFFL |
21880 | //DB_STENCIL_READ_BASE |
21881 | #define DB_STENCIL_READ_BASE__BASE_256B__SHIFT 0x0 |
21882 | #define DB_STENCIL_READ_BASE__BASE_256B_MASK 0xFFFFFFFFL |
21883 | //DB_Z_WRITE_BASE |
21884 | #define DB_Z_WRITE_BASE__BASE_256B__SHIFT 0x0 |
21885 | #define DB_Z_WRITE_BASE__BASE_256B_MASK 0xFFFFFFFFL |
21886 | //DB_STENCIL_WRITE_BASE |
21887 | #define DB_STENCIL_WRITE_BASE__BASE_256B__SHIFT 0x0 |
21888 | #define DB_STENCIL_WRITE_BASE__BASE_256B_MASK 0xFFFFFFFFL |
21889 | //DB_RESERVED_REG_1 |
21890 | #define DB_RESERVED_REG_1__FIELD_1__SHIFT 0x0 |
21891 | #define DB_RESERVED_REG_1__FIELD_2__SHIFT 0xb |
21892 | #define DB_RESERVED_REG_1__FIELD_1_MASK 0x000007FFL |
21893 | #define DB_RESERVED_REG_1__FIELD_2_MASK 0x003FF800L |
21894 | //DB_RESERVED_REG_3 |
21895 | #define DB_RESERVED_REG_3__FIELD_1__SHIFT 0x0 |
21896 | #define DB_RESERVED_REG_3__FIELD_1_MASK 0x003FFFFFL |
21897 | //DB_Z_READ_BASE_HI |
21898 | #define DB_Z_READ_BASE_HI__BASE_HI__SHIFT 0x0 |
21899 | #define DB_Z_READ_BASE_HI__BASE_HI_MASK 0x000000FFL |
21900 | //DB_STENCIL_READ_BASE_HI |
21901 | #define DB_STENCIL_READ_BASE_HI__BASE_HI__SHIFT 0x0 |
21902 | #define DB_STENCIL_READ_BASE_HI__BASE_HI_MASK 0x000000FFL |
21903 | //DB_Z_WRITE_BASE_HI |
21904 | #define DB_Z_WRITE_BASE_HI__BASE_HI__SHIFT 0x0 |
21905 | #define DB_Z_WRITE_BASE_HI__BASE_HI_MASK 0x000000FFL |
21906 | //DB_STENCIL_WRITE_BASE_HI |
21907 | #define DB_STENCIL_WRITE_BASE_HI__BASE_HI__SHIFT 0x0 |
21908 | #define DB_STENCIL_WRITE_BASE_HI__BASE_HI_MASK 0x000000FFL |
21909 | //DB_HTILE_DATA_BASE_HI |
21910 | #define DB_HTILE_DATA_BASE_HI__BASE_HI__SHIFT 0x0 |
21911 | #define DB_HTILE_DATA_BASE_HI__BASE_HI_MASK 0x000000FFL |
21912 | //DB_RMI_L2_CACHE_CONTROL |
21913 | #define DB_RMI_L2_CACHE_CONTROL__Z_WR_POLICY__SHIFT 0x0 |
21914 | #define DB_RMI_L2_CACHE_CONTROL__S_WR_POLICY__SHIFT 0x2 |
21915 | #define DB_RMI_L2_CACHE_CONTROL__HTILE_WR_POLICY__SHIFT 0x4 |
21916 | #define DB_RMI_L2_CACHE_CONTROL__ZPCPSD_WR_POLICY__SHIFT 0x6 |
21917 | #define DB_RMI_L2_CACHE_CONTROL__Z_RD_POLICY__SHIFT 0x10 |
21918 | #define DB_RMI_L2_CACHE_CONTROL__S_RD_POLICY__SHIFT 0x12 |
21919 | #define DB_RMI_L2_CACHE_CONTROL__HTILE_RD_POLICY__SHIFT 0x14 |
21920 | #define DB_RMI_L2_CACHE_CONTROL__Z_BIG_PAGE__SHIFT 0x18 |
21921 | #define DB_RMI_L2_CACHE_CONTROL__S_BIG_PAGE__SHIFT 0x19 |
21922 | #define DB_RMI_L2_CACHE_CONTROL__Z_NOALLOC__SHIFT 0x1a |
21923 | #define DB_RMI_L2_CACHE_CONTROL__S_NOALLOC__SHIFT 0x1b |
21924 | #define DB_RMI_L2_CACHE_CONTROL__HTILE_NOALLOC__SHIFT 0x1c |
21925 | #define DB_RMI_L2_CACHE_CONTROL__ZPCPSD_NOALLOC__SHIFT 0x1d |
21926 | #define DB_RMI_L2_CACHE_CONTROL__Z_WR_POLICY_MASK 0x00000003L |
21927 | #define DB_RMI_L2_CACHE_CONTROL__S_WR_POLICY_MASK 0x0000000CL |
21928 | #define DB_RMI_L2_CACHE_CONTROL__HTILE_WR_POLICY_MASK 0x00000030L |
21929 | #define DB_RMI_L2_CACHE_CONTROL__ZPCPSD_WR_POLICY_MASK 0x000000C0L |
21930 | #define DB_RMI_L2_CACHE_CONTROL__Z_RD_POLICY_MASK 0x00030000L |
21931 | #define DB_RMI_L2_CACHE_CONTROL__S_RD_POLICY_MASK 0x000C0000L |
21932 | #define DB_RMI_L2_CACHE_CONTROL__HTILE_RD_POLICY_MASK 0x00300000L |
21933 | #define DB_RMI_L2_CACHE_CONTROL__Z_BIG_PAGE_MASK 0x01000000L |
21934 | #define DB_RMI_L2_CACHE_CONTROL__S_BIG_PAGE_MASK 0x02000000L |
21935 | #define DB_RMI_L2_CACHE_CONTROL__Z_NOALLOC_MASK 0x04000000L |
21936 | #define DB_RMI_L2_CACHE_CONTROL__S_NOALLOC_MASK 0x08000000L |
21937 | #define DB_RMI_L2_CACHE_CONTROL__HTILE_NOALLOC_MASK 0x10000000L |
21938 | #define DB_RMI_L2_CACHE_CONTROL__ZPCPSD_NOALLOC_MASK 0x20000000L |
21939 | //TA_BC_BASE_ADDR |
21940 | #define TA_BC_BASE_ADDR__ADDRESS__SHIFT 0x0 |
21941 | #define TA_BC_BASE_ADDR__ADDRESS_MASK 0xFFFFFFFFL |
21942 | //TA_BC_BASE_ADDR_HI |
21943 | #define TA_BC_BASE_ADDR_HI__ADDRESS__SHIFT 0x0 |
21944 | #define TA_BC_BASE_ADDR_HI__ADDRESS_MASK 0x000000FFL |
21945 | //COHER_DEST_BASE_HI_0 |
21946 | #define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B__SHIFT 0x0 |
21947 | #define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B_MASK 0x000000FFL |
21948 | //COHER_DEST_BASE_HI_1 |
21949 | #define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B__SHIFT 0x0 |
21950 | #define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B_MASK 0x000000FFL |
21951 | //COHER_DEST_BASE_HI_2 |
21952 | #define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B__SHIFT 0x0 |
21953 | #define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B_MASK 0x000000FFL |
21954 | //COHER_DEST_BASE_HI_3 |
21955 | #define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B__SHIFT 0x0 |
21956 | #define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B_MASK 0x000000FFL |
21957 | //COHER_DEST_BASE_2 |
21958 | #define COHER_DEST_BASE_2__DEST_BASE_256B__SHIFT 0x0 |
21959 | #define COHER_DEST_BASE_2__DEST_BASE_256B_MASK 0xFFFFFFFFL |
21960 | //COHER_DEST_BASE_3 |
21961 | #define COHER_DEST_BASE_3__DEST_BASE_256B__SHIFT 0x0 |
21962 | #define COHER_DEST_BASE_3__DEST_BASE_256B_MASK 0xFFFFFFFFL |
21963 | //PA_SC_WINDOW_OFFSET |
21964 | #define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET__SHIFT 0x0 |
21965 | #define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET__SHIFT 0x10 |
21966 | #define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET_MASK 0x0000FFFFL |
21967 | #define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET_MASK 0xFFFF0000L |
21968 | //PA_SC_WINDOW_SCISSOR_TL |
21969 | #define PA_SC_WINDOW_SCISSOR_TL__TL_X__SHIFT 0x0 |
21970 | #define PA_SC_WINDOW_SCISSOR_TL__TL_Y__SHIFT 0x10 |
21971 | #define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f |
21972 | #define PA_SC_WINDOW_SCISSOR_TL__TL_X_MASK 0x00007FFFL |
21973 | #define PA_SC_WINDOW_SCISSOR_TL__TL_Y_MASK 0x7FFF0000L |
21974 | #define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L |
21975 | //PA_SC_WINDOW_SCISSOR_BR |
21976 | #define PA_SC_WINDOW_SCISSOR_BR__BR_X__SHIFT 0x0 |
21977 | #define PA_SC_WINDOW_SCISSOR_BR__BR_Y__SHIFT 0x10 |
21978 | #define PA_SC_WINDOW_SCISSOR_BR__BR_X_MASK 0x00007FFFL |
21979 | #define PA_SC_WINDOW_SCISSOR_BR__BR_Y_MASK 0x7FFF0000L |
21980 | //PA_SC_CLIPRECT_RULE |
21981 | #define PA_SC_CLIPRECT_RULE__CLIP_RULE__SHIFT 0x0 |
21982 | #define PA_SC_CLIPRECT_RULE__CLIP_RULE_MASK 0x0000FFFFL |
21983 | //PA_SC_CLIPRECT_0_TL |
21984 | #define PA_SC_CLIPRECT_0_TL__TL_X__SHIFT 0x0 |
21985 | #define PA_SC_CLIPRECT_0_TL__TL_Y__SHIFT 0x10 |
21986 | #define PA_SC_CLIPRECT_0_TL__TL_X_MASK 0x00007FFFL |
21987 | #define PA_SC_CLIPRECT_0_TL__TL_Y_MASK 0x7FFF0000L |
21988 | //PA_SC_CLIPRECT_0_BR |
21989 | #define PA_SC_CLIPRECT_0_BR__BR_X__SHIFT 0x0 |
21990 | #define PA_SC_CLIPRECT_0_BR__BR_Y__SHIFT 0x10 |
21991 | #define PA_SC_CLIPRECT_0_BR__BR_X_MASK 0x00007FFFL |
21992 | #define PA_SC_CLIPRECT_0_BR__BR_Y_MASK 0x7FFF0000L |
21993 | //PA_SC_CLIPRECT_1_TL |
21994 | #define PA_SC_CLIPRECT_1_TL__TL_X__SHIFT 0x0 |
21995 | #define PA_SC_CLIPRECT_1_TL__TL_Y__SHIFT 0x10 |
21996 | #define PA_SC_CLIPRECT_1_TL__TL_X_MASK 0x00007FFFL |
21997 | #define PA_SC_CLIPRECT_1_TL__TL_Y_MASK 0x7FFF0000L |
21998 | //PA_SC_CLIPRECT_1_BR |
21999 | #define PA_SC_CLIPRECT_1_BR__BR_X__SHIFT 0x0 |
22000 | #define PA_SC_CLIPRECT_1_BR__BR_Y__SHIFT 0x10 |
22001 | #define PA_SC_CLIPRECT_1_BR__BR_X_MASK 0x00007FFFL |
22002 | #define PA_SC_CLIPRECT_1_BR__BR_Y_MASK 0x7FFF0000L |
22003 | //PA_SC_CLIPRECT_2_TL |
22004 | #define PA_SC_CLIPRECT_2_TL__TL_X__SHIFT 0x0 |
22005 | #define PA_SC_CLIPRECT_2_TL__TL_Y__SHIFT 0x10 |
22006 | #define PA_SC_CLIPRECT_2_TL__TL_X_MASK 0x00007FFFL |
22007 | #define PA_SC_CLIPRECT_2_TL__TL_Y_MASK 0x7FFF0000L |
22008 | //PA_SC_CLIPRECT_2_BR |
22009 | #define PA_SC_CLIPRECT_2_BR__BR_X__SHIFT 0x0 |
22010 | #define PA_SC_CLIPRECT_2_BR__BR_Y__SHIFT 0x10 |
22011 | #define PA_SC_CLIPRECT_2_BR__BR_X_MASK 0x00007FFFL |
22012 | #define PA_SC_CLIPRECT_2_BR__BR_Y_MASK 0x7FFF0000L |
22013 | //PA_SC_CLIPRECT_3_TL |
22014 | #define PA_SC_CLIPRECT_3_TL__TL_X__SHIFT 0x0 |
22015 | #define PA_SC_CLIPRECT_3_TL__TL_Y__SHIFT 0x10 |
22016 | #define PA_SC_CLIPRECT_3_TL__TL_X_MASK 0x00007FFFL |
22017 | #define PA_SC_CLIPRECT_3_TL__TL_Y_MASK 0x7FFF0000L |
22018 | //PA_SC_CLIPRECT_3_BR |
22019 | #define PA_SC_CLIPRECT_3_BR__BR_X__SHIFT 0x0 |
22020 | #define PA_SC_CLIPRECT_3_BR__BR_Y__SHIFT 0x10 |
22021 | #define PA_SC_CLIPRECT_3_BR__BR_X_MASK 0x00007FFFL |
22022 | #define PA_SC_CLIPRECT_3_BR__BR_Y_MASK 0x7FFF0000L |
22023 | //PA_SC_EDGERULE |
22024 | #define PA_SC_EDGERULE__ER_TRI__SHIFT 0x0 |
22025 | #define PA_SC_EDGERULE__ER_POINT__SHIFT 0x4 |
22026 | #define PA_SC_EDGERULE__ER_RECT__SHIFT 0x8 |
22027 | #define PA_SC_EDGERULE__ER_LINE_LR__SHIFT 0xc |
22028 | #define PA_SC_EDGERULE__ER_LINE_RL__SHIFT 0x12 |
22029 | #define PA_SC_EDGERULE__ER_LINE_TB__SHIFT 0x18 |
22030 | #define PA_SC_EDGERULE__ER_LINE_BT__SHIFT 0x1c |
22031 | #define PA_SC_EDGERULE__ER_TRI_MASK 0x0000000FL |
22032 | #define PA_SC_EDGERULE__ER_POINT_MASK 0x000000F0L |
22033 | #define PA_SC_EDGERULE__ER_RECT_MASK 0x00000F00L |
22034 | #define PA_SC_EDGERULE__ER_LINE_LR_MASK 0x0003F000L |
22035 | #define PA_SC_EDGERULE__ER_LINE_RL_MASK 0x00FC0000L |
22036 | #define PA_SC_EDGERULE__ER_LINE_TB_MASK 0x0F000000L |
22037 | #define PA_SC_EDGERULE__ER_LINE_BT_MASK 0xF0000000L |
22038 | //PA_SU_HARDWARE_SCREEN_OFFSET |
22039 | #define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X__SHIFT 0x0 |
22040 | #define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y__SHIFT 0x10 |
22041 | #define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X_MASK 0x000001FFL |
22042 | #define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y_MASK 0x01FF0000L |
22043 | //CB_TARGET_MASK |
22044 | #define CB_TARGET_MASK__TARGET0_ENABLE__SHIFT 0x0 |
22045 | #define CB_TARGET_MASK__TARGET1_ENABLE__SHIFT 0x4 |
22046 | #define CB_TARGET_MASK__TARGET2_ENABLE__SHIFT 0x8 |
22047 | #define CB_TARGET_MASK__TARGET3_ENABLE__SHIFT 0xc |
22048 | #define CB_TARGET_MASK__TARGET4_ENABLE__SHIFT 0x10 |
22049 | #define CB_TARGET_MASK__TARGET5_ENABLE__SHIFT 0x14 |
22050 | #define CB_TARGET_MASK__TARGET6_ENABLE__SHIFT 0x18 |
22051 | #define CB_TARGET_MASK__TARGET7_ENABLE__SHIFT 0x1c |
22052 | #define CB_TARGET_MASK__TARGET0_ENABLE_MASK 0x0000000FL |
22053 | #define CB_TARGET_MASK__TARGET1_ENABLE_MASK 0x000000F0L |
22054 | #define CB_TARGET_MASK__TARGET2_ENABLE_MASK 0x00000F00L |
22055 | #define CB_TARGET_MASK__TARGET3_ENABLE_MASK 0x0000F000L |
22056 | #define CB_TARGET_MASK__TARGET4_ENABLE_MASK 0x000F0000L |
22057 | #define CB_TARGET_MASK__TARGET5_ENABLE_MASK 0x00F00000L |
22058 | #define CB_TARGET_MASK__TARGET6_ENABLE_MASK 0x0F000000L |
22059 | #define CB_TARGET_MASK__TARGET7_ENABLE_MASK 0xF0000000L |
22060 | //CB_SHADER_MASK |
22061 | #define CB_SHADER_MASK__OUTPUT0_ENABLE__SHIFT 0x0 |
22062 | #define CB_SHADER_MASK__OUTPUT1_ENABLE__SHIFT 0x4 |
22063 | #define CB_SHADER_MASK__OUTPUT2_ENABLE__SHIFT 0x8 |
22064 | #define CB_SHADER_MASK__OUTPUT3_ENABLE__SHIFT 0xc |
22065 | #define CB_SHADER_MASK__OUTPUT4_ENABLE__SHIFT 0x10 |
22066 | #define CB_SHADER_MASK__OUTPUT5_ENABLE__SHIFT 0x14 |
22067 | #define CB_SHADER_MASK__OUTPUT6_ENABLE__SHIFT 0x18 |
22068 | #define CB_SHADER_MASK__OUTPUT7_ENABLE__SHIFT 0x1c |
22069 | #define CB_SHADER_MASK__OUTPUT0_ENABLE_MASK 0x0000000FL |
22070 | #define CB_SHADER_MASK__OUTPUT1_ENABLE_MASK 0x000000F0L |
22071 | #define CB_SHADER_MASK__OUTPUT2_ENABLE_MASK 0x00000F00L |
22072 | #define CB_SHADER_MASK__OUTPUT3_ENABLE_MASK 0x0000F000L |
22073 | #define CB_SHADER_MASK__OUTPUT4_ENABLE_MASK 0x000F0000L |
22074 | #define CB_SHADER_MASK__OUTPUT5_ENABLE_MASK 0x00F00000L |
22075 | #define CB_SHADER_MASK__OUTPUT6_ENABLE_MASK 0x0F000000L |
22076 | #define CB_SHADER_MASK__OUTPUT7_ENABLE_MASK 0xF0000000L |
22077 | //PA_SC_GENERIC_SCISSOR_TL |
22078 | #define PA_SC_GENERIC_SCISSOR_TL__TL_X__SHIFT 0x0 |
22079 | #define PA_SC_GENERIC_SCISSOR_TL__TL_Y__SHIFT 0x10 |
22080 | #define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f |
22081 | #define PA_SC_GENERIC_SCISSOR_TL__TL_X_MASK 0x00007FFFL |
22082 | #define PA_SC_GENERIC_SCISSOR_TL__TL_Y_MASK 0x7FFF0000L |
22083 | #define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L |
22084 | //PA_SC_GENERIC_SCISSOR_BR |
22085 | #define PA_SC_GENERIC_SCISSOR_BR__BR_X__SHIFT 0x0 |
22086 | #define PA_SC_GENERIC_SCISSOR_BR__BR_Y__SHIFT 0x10 |
22087 | #define PA_SC_GENERIC_SCISSOR_BR__BR_X_MASK 0x00007FFFL |
22088 | #define PA_SC_GENERIC_SCISSOR_BR__BR_Y_MASK 0x7FFF0000L |
22089 | //COHER_DEST_BASE_0 |
22090 | #define COHER_DEST_BASE_0__DEST_BASE_256B__SHIFT 0x0 |
22091 | #define COHER_DEST_BASE_0__DEST_BASE_256B_MASK 0xFFFFFFFFL |
22092 | //COHER_DEST_BASE_1 |
22093 | #define COHER_DEST_BASE_1__DEST_BASE_256B__SHIFT 0x0 |
22094 | #define COHER_DEST_BASE_1__DEST_BASE_256B_MASK 0xFFFFFFFFL |
22095 | //PA_SC_VPORT_SCISSOR_0_TL |
22096 | #define PA_SC_VPORT_SCISSOR_0_TL__TL_X__SHIFT 0x0 |
22097 | #define PA_SC_VPORT_SCISSOR_0_TL__TL_Y__SHIFT 0x10 |
22098 | #define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f |
22099 | #define PA_SC_VPORT_SCISSOR_0_TL__TL_X_MASK 0x00007FFFL |
22100 | #define PA_SC_VPORT_SCISSOR_0_TL__TL_Y_MASK 0x7FFF0000L |
22101 | #define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L |
22102 | //PA_SC_VPORT_SCISSOR_0_BR |
22103 | #define PA_SC_VPORT_SCISSOR_0_BR__BR_X__SHIFT 0x0 |
22104 | #define PA_SC_VPORT_SCISSOR_0_BR__BR_Y__SHIFT 0x10 |
22105 | #define PA_SC_VPORT_SCISSOR_0_BR__BR_X_MASK 0x00007FFFL |
22106 | #define PA_SC_VPORT_SCISSOR_0_BR__BR_Y_MASK 0x7FFF0000L |
22107 | //PA_SC_VPORT_SCISSOR_1_TL |
22108 | #define PA_SC_VPORT_SCISSOR_1_TL__TL_X__SHIFT 0x0 |
22109 | #define PA_SC_VPORT_SCISSOR_1_TL__TL_Y__SHIFT 0x10 |
22110 | #define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f |
22111 | #define PA_SC_VPORT_SCISSOR_1_TL__TL_X_MASK 0x00007FFFL |
22112 | #define PA_SC_VPORT_SCISSOR_1_TL__TL_Y_MASK 0x7FFF0000L |
22113 | #define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L |
22114 | //PA_SC_VPORT_SCISSOR_1_BR |
22115 | #define PA_SC_VPORT_SCISSOR_1_BR__BR_X__SHIFT 0x0 |
22116 | #define PA_SC_VPORT_SCISSOR_1_BR__BR_Y__SHIFT 0x10 |
22117 | #define PA_SC_VPORT_SCISSOR_1_BR__BR_X_MASK 0x00007FFFL |
22118 | #define PA_SC_VPORT_SCISSOR_1_BR__BR_Y_MASK 0x7FFF0000L |
22119 | //PA_SC_VPORT_SCISSOR_2_TL |
22120 | #define PA_SC_VPORT_SCISSOR_2_TL__TL_X__SHIFT 0x0 |
22121 | #define PA_SC_VPORT_SCISSOR_2_TL__TL_Y__SHIFT 0x10 |
22122 | #define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f |
22123 | #define PA_SC_VPORT_SCISSOR_2_TL__TL_X_MASK 0x00007FFFL |
22124 | #define PA_SC_VPORT_SCISSOR_2_TL__TL_Y_MASK 0x7FFF0000L |
22125 | #define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L |
22126 | //PA_SC_VPORT_SCISSOR_2_BR |
22127 | #define PA_SC_VPORT_SCISSOR_2_BR__BR_X__SHIFT 0x0 |
22128 | #define PA_SC_VPORT_SCISSOR_2_BR__BR_Y__SHIFT 0x10 |
22129 | #define PA_SC_VPORT_SCISSOR_2_BR__BR_X_MASK 0x00007FFFL |
22130 | #define PA_SC_VPORT_SCISSOR_2_BR__BR_Y_MASK 0x7FFF0000L |
22131 | //PA_SC_VPORT_SCISSOR_3_TL |
22132 | #define PA_SC_VPORT_SCISSOR_3_TL__TL_X__SHIFT 0x0 |
22133 | #define PA_SC_VPORT_SCISSOR_3_TL__TL_Y__SHIFT 0x10 |
22134 | #define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f |
22135 | #define PA_SC_VPORT_SCISSOR_3_TL__TL_X_MASK 0x00007FFFL |
22136 | #define PA_SC_VPORT_SCISSOR_3_TL__TL_Y_MASK 0x7FFF0000L |
22137 | #define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L |
22138 | //PA_SC_VPORT_SCISSOR_3_BR |
22139 | #define PA_SC_VPORT_SCISSOR_3_BR__BR_X__SHIFT 0x0 |
22140 | #define PA_SC_VPORT_SCISSOR_3_BR__BR_Y__SHIFT 0x10 |
22141 | #define PA_SC_VPORT_SCISSOR_3_BR__BR_X_MASK 0x00007FFFL |
22142 | #define PA_SC_VPORT_SCISSOR_3_BR__BR_Y_MASK 0x7FFF0000L |
22143 | //PA_SC_VPORT_SCISSOR_4_TL |
22144 | #define PA_SC_VPORT_SCISSOR_4_TL__TL_X__SHIFT 0x0 |
22145 | #define PA_SC_VPORT_SCISSOR_4_TL__TL_Y__SHIFT 0x10 |
22146 | #define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f |
22147 | #define PA_SC_VPORT_SCISSOR_4_TL__TL_X_MASK 0x00007FFFL |
22148 | #define PA_SC_VPORT_SCISSOR_4_TL__TL_Y_MASK 0x7FFF0000L |
22149 | #define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L |
22150 | //PA_SC_VPORT_SCISSOR_4_BR |
22151 | #define PA_SC_VPORT_SCISSOR_4_BR__BR_X__SHIFT 0x0 |
22152 | #define PA_SC_VPORT_SCISSOR_4_BR__BR_Y__SHIFT 0x10 |
22153 | #define PA_SC_VPORT_SCISSOR_4_BR__BR_X_MASK 0x00007FFFL |
22154 | #define PA_SC_VPORT_SCISSOR_4_BR__BR_Y_MASK 0x7FFF0000L |
22155 | //PA_SC_VPORT_SCISSOR_5_TL |
22156 | #define PA_SC_VPORT_SCISSOR_5_TL__TL_X__SHIFT 0x0 |
22157 | #define PA_SC_VPORT_SCISSOR_5_TL__TL_Y__SHIFT 0x10 |
22158 | #define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f |
22159 | #define PA_SC_VPORT_SCISSOR_5_TL__TL_X_MASK 0x00007FFFL |
22160 | #define PA_SC_VPORT_SCISSOR_5_TL__TL_Y_MASK 0x7FFF0000L |
22161 | #define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L |
22162 | //PA_SC_VPORT_SCISSOR_5_BR |
22163 | #define PA_SC_VPORT_SCISSOR_5_BR__BR_X__SHIFT 0x0 |
22164 | #define PA_SC_VPORT_SCISSOR_5_BR__BR_Y__SHIFT 0x10 |
22165 | #define PA_SC_VPORT_SCISSOR_5_BR__BR_X_MASK 0x00007FFFL |
22166 | #define PA_SC_VPORT_SCISSOR_5_BR__BR_Y_MASK 0x7FFF0000L |
22167 | //PA_SC_VPORT_SCISSOR_6_TL |
22168 | #define PA_SC_VPORT_SCISSOR_6_TL__TL_X__SHIFT 0x0 |
22169 | #define PA_SC_VPORT_SCISSOR_6_TL__TL_Y__SHIFT 0x10 |
22170 | #define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f |
22171 | #define PA_SC_VPORT_SCISSOR_6_TL__TL_X_MASK 0x00007FFFL |
22172 | #define PA_SC_VPORT_SCISSOR_6_TL__TL_Y_MASK 0x7FFF0000L |
22173 | #define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L |
22174 | //PA_SC_VPORT_SCISSOR_6_BR |
22175 | #define PA_SC_VPORT_SCISSOR_6_BR__BR_X__SHIFT 0x0 |
22176 | #define PA_SC_VPORT_SCISSOR_6_BR__BR_Y__SHIFT 0x10 |
22177 | #define PA_SC_VPORT_SCISSOR_6_BR__BR_X_MASK 0x00007FFFL |
22178 | #define PA_SC_VPORT_SCISSOR_6_BR__BR_Y_MASK 0x7FFF0000L |
22179 | //PA_SC_VPORT_SCISSOR_7_TL |
22180 | #define PA_SC_VPORT_SCISSOR_7_TL__TL_X__SHIFT 0x0 |
22181 | #define PA_SC_VPORT_SCISSOR_7_TL__TL_Y__SHIFT 0x10 |
22182 | #define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f |
22183 | #define PA_SC_VPORT_SCISSOR_7_TL__TL_X_MASK 0x00007FFFL |
22184 | #define PA_SC_VPORT_SCISSOR_7_TL__TL_Y_MASK 0x7FFF0000L |
22185 | #define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L |
22186 | //PA_SC_VPORT_SCISSOR_7_BR |
22187 | #define PA_SC_VPORT_SCISSOR_7_BR__BR_X__SHIFT 0x0 |
22188 | #define PA_SC_VPORT_SCISSOR_7_BR__BR_Y__SHIFT 0x10 |
22189 | #define PA_SC_VPORT_SCISSOR_7_BR__BR_X_MASK 0x00007FFFL |
22190 | #define PA_SC_VPORT_SCISSOR_7_BR__BR_Y_MASK 0x7FFF0000L |
22191 | //PA_SC_VPORT_SCISSOR_8_TL |
22192 | #define PA_SC_VPORT_SCISSOR_8_TL__TL_X__SHIFT 0x0 |
22193 | #define PA_SC_VPORT_SCISSOR_8_TL__TL_Y__SHIFT 0x10 |
22194 | #define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f |
22195 | #define PA_SC_VPORT_SCISSOR_8_TL__TL_X_MASK 0x00007FFFL |
22196 | #define PA_SC_VPORT_SCISSOR_8_TL__TL_Y_MASK 0x7FFF0000L |
22197 | #define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L |
22198 | //PA_SC_VPORT_SCISSOR_8_BR |
22199 | #define PA_SC_VPORT_SCISSOR_8_BR__BR_X__SHIFT 0x0 |
22200 | #define PA_SC_VPORT_SCISSOR_8_BR__BR_Y__SHIFT 0x10 |
22201 | #define PA_SC_VPORT_SCISSOR_8_BR__BR_X_MASK 0x00007FFFL |
22202 | #define PA_SC_VPORT_SCISSOR_8_BR__BR_Y_MASK 0x7FFF0000L |
22203 | //PA_SC_VPORT_SCISSOR_9_TL |
22204 | #define PA_SC_VPORT_SCISSOR_9_TL__TL_X__SHIFT 0x0 |
22205 | #define PA_SC_VPORT_SCISSOR_9_TL__TL_Y__SHIFT 0x10 |
22206 | #define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f |
22207 | #define PA_SC_VPORT_SCISSOR_9_TL__TL_X_MASK 0x00007FFFL |
22208 | #define PA_SC_VPORT_SCISSOR_9_TL__TL_Y_MASK 0x7FFF0000L |
22209 | #define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L |
22210 | //PA_SC_VPORT_SCISSOR_9_BR |
22211 | #define PA_SC_VPORT_SCISSOR_9_BR__BR_X__SHIFT 0x0 |
22212 | #define PA_SC_VPORT_SCISSOR_9_BR__BR_Y__SHIFT 0x10 |
22213 | #define PA_SC_VPORT_SCISSOR_9_BR__BR_X_MASK 0x00007FFFL |
22214 | #define PA_SC_VPORT_SCISSOR_9_BR__BR_Y_MASK 0x7FFF0000L |
22215 | //PA_SC_VPORT_SCISSOR_10_TL |
22216 | #define PA_SC_VPORT_SCISSOR_10_TL__TL_X__SHIFT 0x0 |
22217 | #define PA_SC_VPORT_SCISSOR_10_TL__TL_Y__SHIFT 0x10 |
22218 | #define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f |
22219 | #define PA_SC_VPORT_SCISSOR_10_TL__TL_X_MASK 0x00007FFFL |
22220 | #define PA_SC_VPORT_SCISSOR_10_TL__TL_Y_MASK 0x7FFF0000L |
22221 | #define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L |
22222 | //PA_SC_VPORT_SCISSOR_10_BR |
22223 | #define PA_SC_VPORT_SCISSOR_10_BR__BR_X__SHIFT 0x0 |
22224 | #define PA_SC_VPORT_SCISSOR_10_BR__BR_Y__SHIFT 0x10 |
22225 | #define PA_SC_VPORT_SCISSOR_10_BR__BR_X_MASK 0x00007FFFL |
22226 | #define PA_SC_VPORT_SCISSOR_10_BR__BR_Y_MASK 0x7FFF0000L |
22227 | //PA_SC_VPORT_SCISSOR_11_TL |
22228 | #define PA_SC_VPORT_SCISSOR_11_TL__TL_X__SHIFT 0x0 |
22229 | #define PA_SC_VPORT_SCISSOR_11_TL__TL_Y__SHIFT 0x10 |
22230 | #define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f |
22231 | #define PA_SC_VPORT_SCISSOR_11_TL__TL_X_MASK 0x00007FFFL |
22232 | #define PA_SC_VPORT_SCISSOR_11_TL__TL_Y_MASK 0x7FFF0000L |
22233 | #define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L |
22234 | //PA_SC_VPORT_SCISSOR_11_BR |
22235 | #define PA_SC_VPORT_SCISSOR_11_BR__BR_X__SHIFT 0x0 |
22236 | #define PA_SC_VPORT_SCISSOR_11_BR__BR_Y__SHIFT 0x10 |
22237 | #define PA_SC_VPORT_SCISSOR_11_BR__BR_X_MASK 0x00007FFFL |
22238 | #define PA_SC_VPORT_SCISSOR_11_BR__BR_Y_MASK 0x7FFF0000L |
22239 | //PA_SC_VPORT_SCISSOR_12_TL |
22240 | #define PA_SC_VPORT_SCISSOR_12_TL__TL_X__SHIFT 0x0 |
22241 | #define PA_SC_VPORT_SCISSOR_12_TL__TL_Y__SHIFT 0x10 |
22242 | #define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f |
22243 | #define PA_SC_VPORT_SCISSOR_12_TL__TL_X_MASK 0x00007FFFL |
22244 | #define PA_SC_VPORT_SCISSOR_12_TL__TL_Y_MASK 0x7FFF0000L |
22245 | #define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L |
22246 | //PA_SC_VPORT_SCISSOR_12_BR |
22247 | #define PA_SC_VPORT_SCISSOR_12_BR__BR_X__SHIFT 0x0 |
22248 | #define PA_SC_VPORT_SCISSOR_12_BR__BR_Y__SHIFT 0x10 |
22249 | #define PA_SC_VPORT_SCISSOR_12_BR__BR_X_MASK 0x00007FFFL |
22250 | #define PA_SC_VPORT_SCISSOR_12_BR__BR_Y_MASK 0x7FFF0000L |
22251 | //PA_SC_VPORT_SCISSOR_13_TL |
22252 | #define PA_SC_VPORT_SCISSOR_13_TL__TL_X__SHIFT 0x0 |
22253 | #define PA_SC_VPORT_SCISSOR_13_TL__TL_Y__SHIFT 0x10 |
22254 | #define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f |
22255 | #define PA_SC_VPORT_SCISSOR_13_TL__TL_X_MASK 0x00007FFFL |
22256 | #define PA_SC_VPORT_SCISSOR_13_TL__TL_Y_MASK 0x7FFF0000L |
22257 | #define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L |
22258 | //PA_SC_VPORT_SCISSOR_13_BR |
22259 | #define PA_SC_VPORT_SCISSOR_13_BR__BR_X__SHIFT 0x0 |
22260 | #define PA_SC_VPORT_SCISSOR_13_BR__BR_Y__SHIFT 0x10 |
22261 | #define PA_SC_VPORT_SCISSOR_13_BR__BR_X_MASK 0x00007FFFL |
22262 | #define PA_SC_VPORT_SCISSOR_13_BR__BR_Y_MASK 0x7FFF0000L |
22263 | //PA_SC_VPORT_SCISSOR_14_TL |
22264 | #define PA_SC_VPORT_SCISSOR_14_TL__TL_X__SHIFT 0x0 |
22265 | #define PA_SC_VPORT_SCISSOR_14_TL__TL_Y__SHIFT 0x10 |
22266 | #define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f |
22267 | #define PA_SC_VPORT_SCISSOR_14_TL__TL_X_MASK 0x00007FFFL |
22268 | #define PA_SC_VPORT_SCISSOR_14_TL__TL_Y_MASK 0x7FFF0000L |
22269 | #define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L |
22270 | //PA_SC_VPORT_SCISSOR_14_BR |
22271 | #define PA_SC_VPORT_SCISSOR_14_BR__BR_X__SHIFT 0x0 |
22272 | #define PA_SC_VPORT_SCISSOR_14_BR__BR_Y__SHIFT 0x10 |
22273 | #define PA_SC_VPORT_SCISSOR_14_BR__BR_X_MASK 0x00007FFFL |
22274 | #define PA_SC_VPORT_SCISSOR_14_BR__BR_Y_MASK 0x7FFF0000L |
22275 | //PA_SC_VPORT_SCISSOR_15_TL |
22276 | #define PA_SC_VPORT_SCISSOR_15_TL__TL_X__SHIFT 0x0 |
22277 | #define PA_SC_VPORT_SCISSOR_15_TL__TL_Y__SHIFT 0x10 |
22278 | #define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f |
22279 | #define PA_SC_VPORT_SCISSOR_15_TL__TL_X_MASK 0x00007FFFL |
22280 | #define PA_SC_VPORT_SCISSOR_15_TL__TL_Y_MASK 0x7FFF0000L |
22281 | #define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000L |
22282 | //PA_SC_VPORT_SCISSOR_15_BR |
22283 | #define PA_SC_VPORT_SCISSOR_15_BR__BR_X__SHIFT 0x0 |
22284 | #define PA_SC_VPORT_SCISSOR_15_BR__BR_Y__SHIFT 0x10 |
22285 | #define PA_SC_VPORT_SCISSOR_15_BR__BR_X_MASK 0x00007FFFL |
22286 | #define PA_SC_VPORT_SCISSOR_15_BR__BR_Y_MASK 0x7FFF0000L |
22287 | //PA_SC_VPORT_ZMIN_0 |
22288 | #define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN__SHIFT 0x0 |
22289 | #define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN_MASK 0xFFFFFFFFL |
22290 | //PA_SC_VPORT_ZMAX_0 |
22291 | #define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX__SHIFT 0x0 |
22292 | #define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX_MASK 0xFFFFFFFFL |
22293 | //PA_SC_VPORT_ZMIN_1 |
22294 | #define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN__SHIFT 0x0 |
22295 | #define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN_MASK 0xFFFFFFFFL |
22296 | //PA_SC_VPORT_ZMAX_1 |
22297 | #define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX__SHIFT 0x0 |
22298 | #define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX_MASK 0xFFFFFFFFL |
22299 | //PA_SC_VPORT_ZMIN_2 |
22300 | #define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN__SHIFT 0x0 |
22301 | #define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN_MASK 0xFFFFFFFFL |
22302 | //PA_SC_VPORT_ZMAX_2 |
22303 | #define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX__SHIFT 0x0 |
22304 | #define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX_MASK 0xFFFFFFFFL |
22305 | //PA_SC_VPORT_ZMIN_3 |
22306 | #define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN__SHIFT 0x0 |
22307 | #define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN_MASK 0xFFFFFFFFL |
22308 | //PA_SC_VPORT_ZMAX_3 |
22309 | #define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX__SHIFT 0x0 |
22310 | #define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX_MASK 0xFFFFFFFFL |
22311 | //PA_SC_VPORT_ZMIN_4 |
22312 | #define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN__SHIFT 0x0 |
22313 | #define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN_MASK 0xFFFFFFFFL |
22314 | //PA_SC_VPORT_ZMAX_4 |
22315 | #define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX__SHIFT 0x0 |
22316 | #define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX_MASK 0xFFFFFFFFL |
22317 | //PA_SC_VPORT_ZMIN_5 |
22318 | #define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN__SHIFT 0x0 |
22319 | #define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN_MASK 0xFFFFFFFFL |
22320 | //PA_SC_VPORT_ZMAX_5 |
22321 | #define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX__SHIFT 0x0 |
22322 | #define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX_MASK 0xFFFFFFFFL |
22323 | //PA_SC_VPORT_ZMIN_6 |
22324 | #define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN__SHIFT 0x0 |
22325 | #define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN_MASK 0xFFFFFFFFL |
22326 | //PA_SC_VPORT_ZMAX_6 |
22327 | #define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX__SHIFT 0x0 |
22328 | #define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX_MASK 0xFFFFFFFFL |
22329 | //PA_SC_VPORT_ZMIN_7 |
22330 | #define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN__SHIFT 0x0 |
22331 | #define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN_MASK 0xFFFFFFFFL |
22332 | //PA_SC_VPORT_ZMAX_7 |
22333 | #define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX__SHIFT 0x0 |
22334 | #define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX_MASK 0xFFFFFFFFL |
22335 | //PA_SC_VPORT_ZMIN_8 |
22336 | #define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN__SHIFT 0x0 |
22337 | #define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN_MASK 0xFFFFFFFFL |
22338 | //PA_SC_VPORT_ZMAX_8 |
22339 | #define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX__SHIFT 0x0 |
22340 | #define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX_MASK 0xFFFFFFFFL |
22341 | //PA_SC_VPORT_ZMIN_9 |
22342 | #define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN__SHIFT 0x0 |
22343 | #define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN_MASK 0xFFFFFFFFL |
22344 | //PA_SC_VPORT_ZMAX_9 |
22345 | #define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX__SHIFT 0x0 |
22346 | #define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX_MASK 0xFFFFFFFFL |
22347 | //PA_SC_VPORT_ZMIN_10 |
22348 | #define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN__SHIFT 0x0 |
22349 | #define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN_MASK 0xFFFFFFFFL |
22350 | //PA_SC_VPORT_ZMAX_10 |
22351 | #define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX__SHIFT 0x0 |
22352 | #define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX_MASK 0xFFFFFFFFL |
22353 | //PA_SC_VPORT_ZMIN_11 |
22354 | #define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN__SHIFT 0x0 |
22355 | #define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN_MASK 0xFFFFFFFFL |
22356 | //PA_SC_VPORT_ZMAX_11 |
22357 | #define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX__SHIFT 0x0 |
22358 | #define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX_MASK 0xFFFFFFFFL |
22359 | //PA_SC_VPORT_ZMIN_12 |
22360 | #define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN__SHIFT 0x0 |
22361 | #define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN_MASK 0xFFFFFFFFL |
22362 | //PA_SC_VPORT_ZMAX_12 |
22363 | #define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX__SHIFT 0x0 |
22364 | #define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX_MASK 0xFFFFFFFFL |
22365 | //PA_SC_VPORT_ZMIN_13 |
22366 | #define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN__SHIFT 0x0 |
22367 | #define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN_MASK 0xFFFFFFFFL |
22368 | //PA_SC_VPORT_ZMAX_13 |
22369 | #define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX__SHIFT 0x0 |
22370 | #define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX_MASK 0xFFFFFFFFL |
22371 | //PA_SC_VPORT_ZMIN_14 |
22372 | #define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN__SHIFT 0x0 |
22373 | #define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN_MASK 0xFFFFFFFFL |
22374 | //PA_SC_VPORT_ZMAX_14 |
22375 | #define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX__SHIFT 0x0 |
22376 | #define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX_MASK 0xFFFFFFFFL |
22377 | //PA_SC_VPORT_ZMIN_15 |
22378 | #define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN__SHIFT 0x0 |
22379 | #define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN_MASK 0xFFFFFFFFL |
22380 | //PA_SC_VPORT_ZMAX_15 |
22381 | #define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX__SHIFT 0x0 |
22382 | #define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX_MASK 0xFFFFFFFFL |
22383 | //PA_SC_RASTER_CONFIG |
22384 | #define PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT 0x0 |
22385 | #define PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT 0x2 |
22386 | #define PA_SC_RASTER_CONFIG__RB_XSEL2__SHIFT 0x4 |
22387 | #define PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT 0x6 |
22388 | #define PA_SC_RASTER_CONFIG__RB_YSEL__SHIFT 0x7 |
22389 | #define PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT 0x8 |
22390 | #define PA_SC_RASTER_CONFIG__PKR_XSEL__SHIFT 0xa |
22391 | #define PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT 0xc |
22392 | #define PA_SC_RASTER_CONFIG__PKR_XSEL2__SHIFT 0xe |
22393 | #define PA_SC_RASTER_CONFIG__SC_MAP__SHIFT 0x10 |
22394 | #define PA_SC_RASTER_CONFIG__SC_XSEL__SHIFT 0x12 |
22395 | #define PA_SC_RASTER_CONFIG__SC_YSEL__SHIFT 0x14 |
22396 | #define PA_SC_RASTER_CONFIG__SE_MAP__SHIFT 0x18 |
22397 | #define PA_SC_RASTER_CONFIG__SE_XSEL__SHIFT 0x1a |
22398 | #define PA_SC_RASTER_CONFIG__SE_YSEL__SHIFT 0x1c |
22399 | #define PA_SC_RASTER_CONFIG__RB_MAP_PKR0_MASK 0x00000003L |
22400 | #define PA_SC_RASTER_CONFIG__RB_MAP_PKR1_MASK 0x0000000CL |
22401 | #define PA_SC_RASTER_CONFIG__RB_XSEL2_MASK 0x00000030L |
22402 | #define PA_SC_RASTER_CONFIG__RB_XSEL_MASK 0x00000040L |
22403 | #define PA_SC_RASTER_CONFIG__RB_YSEL_MASK 0x00000080L |
22404 | #define PA_SC_RASTER_CONFIG__PKR_MAP_MASK 0x00000300L |
22405 | #define PA_SC_RASTER_CONFIG__PKR_XSEL_MASK 0x00000C00L |
22406 | #define PA_SC_RASTER_CONFIG__PKR_YSEL_MASK 0x00003000L |
22407 | #define PA_SC_RASTER_CONFIG__PKR_XSEL2_MASK 0x0000C000L |
22408 | #define PA_SC_RASTER_CONFIG__SC_MAP_MASK 0x00030000L |
22409 | #define PA_SC_RASTER_CONFIG__SC_XSEL_MASK 0x000C0000L |
22410 | #define PA_SC_RASTER_CONFIG__SC_YSEL_MASK 0x00300000L |
22411 | #define PA_SC_RASTER_CONFIG__SE_MAP_MASK 0x03000000L |
22412 | #define PA_SC_RASTER_CONFIG__SE_XSEL_MASK 0x0C000000L |
22413 | #define PA_SC_RASTER_CONFIG__SE_YSEL_MASK 0x30000000L |
22414 | //PA_SC_RASTER_CONFIG_1 |
22415 | #define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP__SHIFT 0x0 |
22416 | #define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL__SHIFT 0x2 |
22417 | #define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL__SHIFT 0x4 |
22418 | #define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP_MASK 0x00000003L |
22419 | #define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL_MASK 0x0000000CL |
22420 | #define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL_MASK 0x00000030L |
22421 | //PA_SC_SCREEN_EXTENT_CONTROL |
22422 | #define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE__SHIFT 0x0 |
22423 | #define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE__SHIFT 0x2 |
22424 | #define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE_MASK 0x00000003L |
22425 | #define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE_MASK 0x0000000CL |
22426 | //PA_SC_TILE_STEERING_OVERRIDE |
22427 | #define PA_SC_TILE_STEERING_OVERRIDE__ENABLE__SHIFT 0x0 |
22428 | #define PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT 0xc |
22429 | #define PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT 0x10 |
22430 | #define PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT 0x14 |
22431 | #define PA_SC_TILE_STEERING_OVERRIDE__ENABLE_MASK 0x00000001L |
22432 | #define PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK 0x00003000L |
22433 | #define PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK 0x00030000L |
22434 | #define PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK 0x00300000L |
22435 | //CP_PERFMON_CNTX_CNTL |
22436 | #define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE__SHIFT 0x1f |
22437 | #define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE_MASK 0x80000000L |
22438 | //CP_PIPEID |
22439 | #define CP_PIPEID__PIPE_ID__SHIFT 0x0 |
22440 | #define CP_PIPEID__PIPE_ID_MASK 0x00000003L |
22441 | //CP_RINGID |
22442 | #define CP_RINGID__RINGID__SHIFT 0x0 |
22443 | #define CP_RINGID__RINGID_MASK 0x00000003L |
22444 | //CP_VMID |
22445 | #define CP_VMID__VMID__SHIFT 0x0 |
22446 | #define CP_VMID__VMID_MASK 0x0000000FL |
22447 | //CONTEXT_RESERVED_REG0 |
22448 | #define CONTEXT_RESERVED_REG0__DATA__SHIFT 0x0 |
22449 | #define CONTEXT_RESERVED_REG0__DATA_MASK 0xFFFFFFFFL |
22450 | //CONTEXT_RESERVED_REG1 |
22451 | #define CONTEXT_RESERVED_REG1__DATA__SHIFT 0x0 |
22452 | #define CONTEXT_RESERVED_REG1__DATA_MASK 0xFFFFFFFFL |
22453 | //PA_SC_VRS_OVERRIDE_CNTL |
22454 | #define PA_SC_VRS_OVERRIDE_CNTL__VRS_OVERRIDE_RATE_COMBINER_MODE__SHIFT 0x0 |
22455 | #define PA_SC_VRS_OVERRIDE_CNTL__VRS_RATE__SHIFT 0x4 |
22456 | #define PA_SC_VRS_OVERRIDE_CNTL__VRS_SURFACE_ENABLE__SHIFT 0xc |
22457 | #define PA_SC_VRS_OVERRIDE_CNTL__RATE_HINT_WRITE_BACK_ENABLE__SHIFT 0xd |
22458 | #define PA_SC_VRS_OVERRIDE_CNTL__VRS_FEEDBACK_RATE_OVERRIDE__SHIFT 0xe |
22459 | #define PA_SC_VRS_OVERRIDE_CNTL__VRS_OVERRIDE_RATE_COMBINER_MODE_MASK 0x00000007L |
22460 | #define PA_SC_VRS_OVERRIDE_CNTL__VRS_RATE_MASK 0x000000F0L |
22461 | #define PA_SC_VRS_OVERRIDE_CNTL__VRS_SURFACE_ENABLE_MASK 0x00001000L |
22462 | #define PA_SC_VRS_OVERRIDE_CNTL__RATE_HINT_WRITE_BACK_ENABLE_MASK 0x00002000L |
22463 | #define PA_SC_VRS_OVERRIDE_CNTL__VRS_FEEDBACK_RATE_OVERRIDE_MASK 0x00004000L |
22464 | //PA_SC_VRS_RATE_FEEDBACK_BASE |
22465 | #define PA_SC_VRS_RATE_FEEDBACK_BASE__BASE_256B__SHIFT 0x0 |
22466 | #define PA_SC_VRS_RATE_FEEDBACK_BASE__BASE_256B_MASK 0xFFFFFFFFL |
22467 | //PA_SC_VRS_RATE_FEEDBACK_BASE_EXT |
22468 | #define PA_SC_VRS_RATE_FEEDBACK_BASE_EXT__BASE_256B__SHIFT 0x0 |
22469 | #define PA_SC_VRS_RATE_FEEDBACK_BASE_EXT__BASE_256B_MASK 0x000000FFL |
22470 | //PA_SC_VRS_RATE_FEEDBACK_SIZE_XY |
22471 | #define PA_SC_VRS_RATE_FEEDBACK_SIZE_XY__X_MAX__SHIFT 0x0 |
22472 | #define PA_SC_VRS_RATE_FEEDBACK_SIZE_XY__Y_MAX__SHIFT 0x10 |
22473 | #define PA_SC_VRS_RATE_FEEDBACK_SIZE_XY__X_MAX_MASK 0x000007FFL |
22474 | #define PA_SC_VRS_RATE_FEEDBACK_SIZE_XY__Y_MAX_MASK 0x07FF0000L |
22475 | //PA_SC_VRS_RATE_CACHE_CNTL |
22476 | #define PA_SC_VRS_RATE_CACHE_CNTL__BIG_PAGE_RD__SHIFT 0x0 |
22477 | #define PA_SC_VRS_RATE_CACHE_CNTL__BIG_PAGE_WR__SHIFT 0x1 |
22478 | #define PA_SC_VRS_RATE_CACHE_CNTL__L1_RD_POLICY__SHIFT 0x2 |
22479 | #define PA_SC_VRS_RATE_CACHE_CNTL__L2_RD_POLICY__SHIFT 0x4 |
22480 | #define PA_SC_VRS_RATE_CACHE_CNTL__L2_WR_POLICY__SHIFT 0x6 |
22481 | #define PA_SC_VRS_RATE_CACHE_CNTL__LLC_RD_NOALLOC__SHIFT 0x8 |
22482 | #define PA_SC_VRS_RATE_CACHE_CNTL__LLC_WR_NOALLOC__SHIFT 0x9 |
22483 | #define PA_SC_VRS_RATE_CACHE_CNTL__NOFILL_RD__SHIFT 0xa |
22484 | #define PA_SC_VRS_RATE_CACHE_CNTL__NOFILL_WR__SHIFT 0xb |
22485 | #define PA_SC_VRS_RATE_CACHE_CNTL__PERF_CNTR_EN_RD__SHIFT 0xc |
22486 | #define PA_SC_VRS_RATE_CACHE_CNTL__PERF_CNTR_EN_WR__SHIFT 0xd |
22487 | #define PA_SC_VRS_RATE_CACHE_CNTL__BIG_PAGE_RD_MASK 0x00000001L |
22488 | #define PA_SC_VRS_RATE_CACHE_CNTL__BIG_PAGE_WR_MASK 0x00000002L |
22489 | #define PA_SC_VRS_RATE_CACHE_CNTL__L1_RD_POLICY_MASK 0x0000000CL |
22490 | #define PA_SC_VRS_RATE_CACHE_CNTL__L2_RD_POLICY_MASK 0x00000030L |
22491 | #define PA_SC_VRS_RATE_CACHE_CNTL__L2_WR_POLICY_MASK 0x000000C0L |
22492 | #define PA_SC_VRS_RATE_CACHE_CNTL__LLC_RD_NOALLOC_MASK 0x00000100L |
22493 | #define PA_SC_VRS_RATE_CACHE_CNTL__LLC_WR_NOALLOC_MASK 0x00000200L |
22494 | #define PA_SC_VRS_RATE_CACHE_CNTL__NOFILL_RD_MASK 0x00000400L |
22495 | #define PA_SC_VRS_RATE_CACHE_CNTL__NOFILL_WR_MASK 0x00000800L |
22496 | #define PA_SC_VRS_RATE_CACHE_CNTL__PERF_CNTR_EN_RD_MASK 0x00001000L |
22497 | #define PA_SC_VRS_RATE_CACHE_CNTL__PERF_CNTR_EN_WR_MASK 0x00002000L |
22498 | //PA_SC_VRS_RATE_BASE |
22499 | #define PA_SC_VRS_RATE_BASE__BASE_256B__SHIFT 0x0 |
22500 | #define PA_SC_VRS_RATE_BASE__BASE_256B_MASK 0xFFFFFFFFL |
22501 | //PA_SC_VRS_RATE_BASE_EXT |
22502 | #define PA_SC_VRS_RATE_BASE_EXT__BASE_256B__SHIFT 0x0 |
22503 | #define PA_SC_VRS_RATE_BASE_EXT__TB_SYNC_SIM_ID__SHIFT 0x1c |
22504 | #define PA_SC_VRS_RATE_BASE_EXT__BASE_256B_MASK 0x000000FFL |
22505 | #define PA_SC_VRS_RATE_BASE_EXT__TB_SYNC_SIM_ID_MASK 0xF0000000L |
22506 | //PA_SC_VRS_RATE_SIZE_XY |
22507 | #define PA_SC_VRS_RATE_SIZE_XY__X_MAX__SHIFT 0x0 |
22508 | #define PA_SC_VRS_RATE_SIZE_XY__Y_MAX__SHIFT 0x10 |
22509 | #define PA_SC_VRS_RATE_SIZE_XY__X_MAX_MASK 0x000007FFL |
22510 | #define PA_SC_VRS_RATE_SIZE_XY__Y_MAX_MASK 0x07FF0000L |
22511 | //VGT_MULTI_PRIM_IB_RESET_INDX |
22512 | #define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX__SHIFT 0x0 |
22513 | #define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX_MASK 0xFFFFFFFFL |
22514 | //CB_RMI_GL2_CACHE_CONTROL |
22515 | #define CB_RMI_GL2_CACHE_CONTROL__DCC_WR_POLICY__SHIFT 0x0 |
22516 | #define CB_RMI_GL2_CACHE_CONTROL__COLOR_WR_POLICY__SHIFT 0x2 |
22517 | #define CB_RMI_GL2_CACHE_CONTROL__DCC_RD_POLICY__SHIFT 0x14 |
22518 | #define CB_RMI_GL2_CACHE_CONTROL__COLOR_RD_POLICY__SHIFT 0x16 |
22519 | #define CB_RMI_GL2_CACHE_CONTROL__DCC_L3_BYPASS__SHIFT 0x1a |
22520 | #define CB_RMI_GL2_CACHE_CONTROL__COLOR_L3_BYPASS__SHIFT 0x1b |
22521 | #define CB_RMI_GL2_CACHE_CONTROL__COLOR_BIG_PAGE__SHIFT 0x1f |
22522 | #define CB_RMI_GL2_CACHE_CONTROL__DCC_WR_POLICY_MASK 0x00000003L |
22523 | #define CB_RMI_GL2_CACHE_CONTROL__COLOR_WR_POLICY_MASK 0x0000000CL |
22524 | #define CB_RMI_GL2_CACHE_CONTROL__DCC_RD_POLICY_MASK 0x00300000L |
22525 | #define CB_RMI_GL2_CACHE_CONTROL__COLOR_RD_POLICY_MASK 0x00C00000L |
22526 | #define CB_RMI_GL2_CACHE_CONTROL__DCC_L3_BYPASS_MASK 0x04000000L |
22527 | #define CB_RMI_GL2_CACHE_CONTROL__COLOR_L3_BYPASS_MASK 0x08000000L |
22528 | #define CB_RMI_GL2_CACHE_CONTROL__COLOR_BIG_PAGE_MASK 0x80000000L |
22529 | //CB_BLEND_RED |
22530 | #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0 |
22531 | #define CB_BLEND_RED__BLEND_RED_MASK 0xFFFFFFFFL |
22532 | //CB_BLEND_GREEN |
22533 | #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0 |
22534 | #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xFFFFFFFFL |
22535 | //CB_BLEND_BLUE |
22536 | #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0 |
22537 | #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xFFFFFFFFL |
22538 | //CB_BLEND_ALPHA |
22539 | #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0 |
22540 | #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xFFFFFFFFL |
22541 | //CB_FDCC_CONTROL |
22542 | #define CB_FDCC_CONTROL__SAMPLE_MASK_TRACKER_DISABLE__SHIFT 0x0 |
22543 | #define CB_FDCC_CONTROL__SAMPLE_MASK_TRACKER_WATERMARK__SHIFT 0x2 |
22544 | #define CB_FDCC_CONTROL__DISABLE_CONSTANT_ENCODE_AC01__SHIFT 0x8 |
22545 | #define CB_FDCC_CONTROL__DISABLE_CONSTANT_ENCODE_SINGLE__SHIFT 0x9 |
22546 | #define CB_FDCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0xa |
22547 | #define CB_FDCC_CONTROL__DISABLE_ELIMFC_SKIP_OF_AC01__SHIFT 0xc |
22548 | #define CB_FDCC_CONTROL__DISABLE_ELIMFC_SKIP_OF_SINGLE__SHIFT 0xd |
22549 | #define CB_FDCC_CONTROL__ENABLE_ELIMFC_SKIP_OF_REG__SHIFT 0xe |
22550 | #define CB_FDCC_CONTROL__SAMPLE_MASK_TRACKER_DISABLE_MASK 0x00000001L |
22551 | #define CB_FDCC_CONTROL__SAMPLE_MASK_TRACKER_WATERMARK_MASK 0x0000007CL |
22552 | #define CB_FDCC_CONTROL__DISABLE_CONSTANT_ENCODE_AC01_MASK 0x00000100L |
22553 | #define CB_FDCC_CONTROL__DISABLE_CONSTANT_ENCODE_SINGLE_MASK 0x00000200L |
22554 | #define CB_FDCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00000400L |
22555 | #define CB_FDCC_CONTROL__DISABLE_ELIMFC_SKIP_OF_AC01_MASK 0x00001000L |
22556 | #define CB_FDCC_CONTROL__DISABLE_ELIMFC_SKIP_OF_SINGLE_MASK 0x00002000L |
22557 | #define CB_FDCC_CONTROL__ENABLE_ELIMFC_SKIP_OF_REG_MASK 0x00004000L |
22558 | //CB_COVERAGE_OUT_CONTROL |
22559 | #define CB_COVERAGE_OUT_CONTROL__COVERAGE_OUT_ENABLE__SHIFT 0x0 |
22560 | #define CB_COVERAGE_OUT_CONTROL__COVERAGE_OUT_MRT__SHIFT 0x1 |
22561 | #define CB_COVERAGE_OUT_CONTROL__COVERAGE_OUT_CHANNEL__SHIFT 0x4 |
22562 | #define CB_COVERAGE_OUT_CONTROL__COVERAGE_OUT_SAMPLES__SHIFT 0x8 |
22563 | #define CB_COVERAGE_OUT_CONTROL__COVERAGE_OUT_ENABLE_MASK 0x00000001L |
22564 | #define CB_COVERAGE_OUT_CONTROL__COVERAGE_OUT_MRT_MASK 0x0000000EL |
22565 | #define CB_COVERAGE_OUT_CONTROL__COVERAGE_OUT_CHANNEL_MASK 0x00000030L |
22566 | #define CB_COVERAGE_OUT_CONTROL__COVERAGE_OUT_SAMPLES_MASK 0x00000F00L |
22567 | //DB_STENCIL_CONTROL |
22568 | #define DB_STENCIL_CONTROL__STENCILFAIL__SHIFT 0x0 |
22569 | #define DB_STENCIL_CONTROL__STENCILZPASS__SHIFT 0x4 |
22570 | #define DB_STENCIL_CONTROL__STENCILZFAIL__SHIFT 0x8 |
22571 | #define DB_STENCIL_CONTROL__STENCILFAIL_BF__SHIFT 0xc |
22572 | #define DB_STENCIL_CONTROL__STENCILZPASS_BF__SHIFT 0x10 |
22573 | #define DB_STENCIL_CONTROL__STENCILZFAIL_BF__SHIFT 0x14 |
22574 | #define DB_STENCIL_CONTROL__STENCILFAIL_MASK 0x0000000FL |
22575 | #define DB_STENCIL_CONTROL__STENCILZPASS_MASK 0x000000F0L |
22576 | #define DB_STENCIL_CONTROL__STENCILZFAIL_MASK 0x00000F00L |
22577 | #define DB_STENCIL_CONTROL__STENCILFAIL_BF_MASK 0x0000F000L |
22578 | #define DB_STENCIL_CONTROL__STENCILZPASS_BF_MASK 0x000F0000L |
22579 | #define DB_STENCIL_CONTROL__STENCILZFAIL_BF_MASK 0x00F00000L |
22580 | //DB_STENCILREFMASK |
22581 | #define DB_STENCILREFMASK__STENCILTESTVAL__SHIFT 0x0 |
22582 | #define DB_STENCILREFMASK__STENCILMASK__SHIFT 0x8 |
22583 | #define DB_STENCILREFMASK__STENCILWRITEMASK__SHIFT 0x10 |
22584 | #define DB_STENCILREFMASK__STENCILOPVAL__SHIFT 0x18 |
22585 | #define DB_STENCILREFMASK__STENCILTESTVAL_MASK 0x000000FFL |
22586 | #define DB_STENCILREFMASK__STENCILMASK_MASK 0x0000FF00L |
22587 | #define DB_STENCILREFMASK__STENCILWRITEMASK_MASK 0x00FF0000L |
22588 | #define DB_STENCILREFMASK__STENCILOPVAL_MASK 0xFF000000L |
22589 | //DB_STENCILREFMASK_BF |
22590 | #define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF__SHIFT 0x0 |
22591 | #define DB_STENCILREFMASK_BF__STENCILMASK_BF__SHIFT 0x8 |
22592 | #define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF__SHIFT 0x10 |
22593 | #define DB_STENCILREFMASK_BF__STENCILOPVAL_BF__SHIFT 0x18 |
22594 | #define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF_MASK 0x000000FFL |
22595 | #define DB_STENCILREFMASK_BF__STENCILMASK_BF_MASK 0x0000FF00L |
22596 | #define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF_MASK 0x00FF0000L |
22597 | #define DB_STENCILREFMASK_BF__STENCILOPVAL_BF_MASK 0xFF000000L |
22598 | //PA_CL_VPORT_XSCALE |
22599 | #define PA_CL_VPORT_XSCALE__VPORT_XSCALE__SHIFT 0x0 |
22600 | #define PA_CL_VPORT_XSCALE__VPORT_XSCALE_MASK 0xFFFFFFFFL |
22601 | //PA_CL_VPORT_XOFFSET |
22602 | #define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET__SHIFT 0x0 |
22603 | #define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET_MASK 0xFFFFFFFFL |
22604 | //PA_CL_VPORT_YSCALE |
22605 | #define PA_CL_VPORT_YSCALE__VPORT_YSCALE__SHIFT 0x0 |
22606 | #define PA_CL_VPORT_YSCALE__VPORT_YSCALE_MASK 0xFFFFFFFFL |
22607 | //PA_CL_VPORT_YOFFSET |
22608 | #define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET__SHIFT 0x0 |
22609 | #define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET_MASK 0xFFFFFFFFL |
22610 | //PA_CL_VPORT_ZSCALE |
22611 | #define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE__SHIFT 0x0 |
22612 | #define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE_MASK 0xFFFFFFFFL |
22613 | //PA_CL_VPORT_ZOFFSET |
22614 | #define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET__SHIFT 0x0 |
22615 | #define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET_MASK 0xFFFFFFFFL |
22616 | //PA_CL_VPORT_XSCALE_1 |
22617 | #define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE__SHIFT 0x0 |
22618 | #define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE_MASK 0xFFFFFFFFL |
22619 | //PA_CL_VPORT_XOFFSET_1 |
22620 | #define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET__SHIFT 0x0 |
22621 | #define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET_MASK 0xFFFFFFFFL |
22622 | //PA_CL_VPORT_YSCALE_1 |
22623 | #define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE__SHIFT 0x0 |
22624 | #define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE_MASK 0xFFFFFFFFL |
22625 | //PA_CL_VPORT_YOFFSET_1 |
22626 | #define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET__SHIFT 0x0 |
22627 | #define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET_MASK 0xFFFFFFFFL |
22628 | //PA_CL_VPORT_ZSCALE_1 |
22629 | #define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE__SHIFT 0x0 |
22630 | #define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE_MASK 0xFFFFFFFFL |
22631 | //PA_CL_VPORT_ZOFFSET_1 |
22632 | #define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET__SHIFT 0x0 |
22633 | #define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET_MASK 0xFFFFFFFFL |
22634 | //PA_CL_VPORT_XSCALE_2 |
22635 | #define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE__SHIFT 0x0 |
22636 | #define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE_MASK 0xFFFFFFFFL |
22637 | //PA_CL_VPORT_XOFFSET_2 |
22638 | #define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET__SHIFT 0x0 |
22639 | #define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET_MASK 0xFFFFFFFFL |
22640 | //PA_CL_VPORT_YSCALE_2 |
22641 | #define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE__SHIFT 0x0 |
22642 | #define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE_MASK 0xFFFFFFFFL |
22643 | //PA_CL_VPORT_YOFFSET_2 |
22644 | #define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET__SHIFT 0x0 |
22645 | #define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET_MASK 0xFFFFFFFFL |
22646 | //PA_CL_VPORT_ZSCALE_2 |
22647 | #define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE__SHIFT 0x0 |
22648 | #define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE_MASK 0xFFFFFFFFL |
22649 | //PA_CL_VPORT_ZOFFSET_2 |
22650 | #define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET__SHIFT 0x0 |
22651 | #define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET_MASK 0xFFFFFFFFL |
22652 | //PA_CL_VPORT_XSCALE_3 |
22653 | #define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE__SHIFT 0x0 |
22654 | #define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE_MASK 0xFFFFFFFFL |
22655 | //PA_CL_VPORT_XOFFSET_3 |
22656 | #define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET__SHIFT 0x0 |
22657 | #define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET_MASK 0xFFFFFFFFL |
22658 | //PA_CL_VPORT_YSCALE_3 |
22659 | #define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE__SHIFT 0x0 |
22660 | #define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE_MASK 0xFFFFFFFFL |
22661 | //PA_CL_VPORT_YOFFSET_3 |
22662 | #define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET__SHIFT 0x0 |
22663 | #define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET_MASK 0xFFFFFFFFL |
22664 | //PA_CL_VPORT_ZSCALE_3 |
22665 | #define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE__SHIFT 0x0 |
22666 | #define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE_MASK 0xFFFFFFFFL |
22667 | //PA_CL_VPORT_ZOFFSET_3 |
22668 | #define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET__SHIFT 0x0 |
22669 | #define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET_MASK 0xFFFFFFFFL |
22670 | //PA_CL_VPORT_XSCALE_4 |
22671 | #define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE__SHIFT 0x0 |
22672 | #define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE_MASK 0xFFFFFFFFL |
22673 | //PA_CL_VPORT_XOFFSET_4 |
22674 | #define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET__SHIFT 0x0 |
22675 | #define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET_MASK 0xFFFFFFFFL |
22676 | //PA_CL_VPORT_YSCALE_4 |
22677 | #define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE__SHIFT 0x0 |
22678 | #define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE_MASK 0xFFFFFFFFL |
22679 | //PA_CL_VPORT_YOFFSET_4 |
22680 | #define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET__SHIFT 0x0 |
22681 | #define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET_MASK 0xFFFFFFFFL |
22682 | //PA_CL_VPORT_ZSCALE_4 |
22683 | #define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE__SHIFT 0x0 |
22684 | #define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE_MASK 0xFFFFFFFFL |
22685 | //PA_CL_VPORT_ZOFFSET_4 |
22686 | #define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET__SHIFT 0x0 |
22687 | #define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET_MASK 0xFFFFFFFFL |
22688 | //PA_CL_VPORT_XSCALE_5 |
22689 | #define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE__SHIFT 0x0 |
22690 | #define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE_MASK 0xFFFFFFFFL |
22691 | //PA_CL_VPORT_XOFFSET_5 |
22692 | #define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET__SHIFT 0x0 |
22693 | #define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET_MASK 0xFFFFFFFFL |
22694 | //PA_CL_VPORT_YSCALE_5 |
22695 | #define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE__SHIFT 0x0 |
22696 | #define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE_MASK 0xFFFFFFFFL |
22697 | //PA_CL_VPORT_YOFFSET_5 |
22698 | #define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET__SHIFT 0x0 |
22699 | #define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET_MASK 0xFFFFFFFFL |
22700 | //PA_CL_VPORT_ZSCALE_5 |
22701 | #define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE__SHIFT 0x0 |
22702 | #define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE_MASK 0xFFFFFFFFL |
22703 | //PA_CL_VPORT_ZOFFSET_5 |
22704 | #define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET__SHIFT 0x0 |
22705 | #define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET_MASK 0xFFFFFFFFL |
22706 | //PA_CL_VPORT_XSCALE_6 |
22707 | #define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE__SHIFT 0x0 |
22708 | #define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE_MASK 0xFFFFFFFFL |
22709 | //PA_CL_VPORT_XOFFSET_6 |
22710 | #define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET__SHIFT 0x0 |
22711 | #define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET_MASK 0xFFFFFFFFL |
22712 | //PA_CL_VPORT_YSCALE_6 |
22713 | #define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE__SHIFT 0x0 |
22714 | #define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE_MASK 0xFFFFFFFFL |
22715 | //PA_CL_VPORT_YOFFSET_6 |
22716 | #define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET__SHIFT 0x0 |
22717 | #define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET_MASK 0xFFFFFFFFL |
22718 | //PA_CL_VPORT_ZSCALE_6 |
22719 | #define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE__SHIFT 0x0 |
22720 | #define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE_MASK 0xFFFFFFFFL |
22721 | //PA_CL_VPORT_ZOFFSET_6 |
22722 | #define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET__SHIFT 0x0 |
22723 | #define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET_MASK 0xFFFFFFFFL |
22724 | //PA_CL_VPORT_XSCALE_7 |
22725 | #define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE__SHIFT 0x0 |
22726 | #define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE_MASK 0xFFFFFFFFL |
22727 | //PA_CL_VPORT_XOFFSET_7 |
22728 | #define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET__SHIFT 0x0 |
22729 | #define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET_MASK 0xFFFFFFFFL |
22730 | //PA_CL_VPORT_YSCALE_7 |
22731 | #define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE__SHIFT 0x0 |
22732 | #define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE_MASK 0xFFFFFFFFL |
22733 | //PA_CL_VPORT_YOFFSET_7 |
22734 | #define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET__SHIFT 0x0 |
22735 | #define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET_MASK 0xFFFFFFFFL |
22736 | //PA_CL_VPORT_ZSCALE_7 |
22737 | #define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE__SHIFT 0x0 |
22738 | #define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE_MASK 0xFFFFFFFFL |
22739 | //PA_CL_VPORT_ZOFFSET_7 |
22740 | #define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET__SHIFT 0x0 |
22741 | #define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET_MASK 0xFFFFFFFFL |
22742 | //PA_CL_VPORT_XSCALE_8 |
22743 | #define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE__SHIFT 0x0 |
22744 | #define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE_MASK 0xFFFFFFFFL |
22745 | //PA_CL_VPORT_XOFFSET_8 |
22746 | #define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET__SHIFT 0x0 |
22747 | #define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET_MASK 0xFFFFFFFFL |
22748 | //PA_CL_VPORT_YSCALE_8 |
22749 | #define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE__SHIFT 0x0 |
22750 | #define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE_MASK 0xFFFFFFFFL |
22751 | //PA_CL_VPORT_YOFFSET_8 |
22752 | #define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET__SHIFT 0x0 |
22753 | #define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET_MASK 0xFFFFFFFFL |
22754 | //PA_CL_VPORT_ZSCALE_8 |
22755 | #define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE__SHIFT 0x0 |
22756 | #define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE_MASK 0xFFFFFFFFL |
22757 | //PA_CL_VPORT_ZOFFSET_8 |
22758 | #define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET__SHIFT 0x0 |
22759 | #define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET_MASK 0xFFFFFFFFL |
22760 | //PA_CL_VPORT_XSCALE_9 |
22761 | #define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE__SHIFT 0x0 |
22762 | #define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE_MASK 0xFFFFFFFFL |
22763 | //PA_CL_VPORT_XOFFSET_9 |
22764 | #define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET__SHIFT 0x0 |
22765 | #define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET_MASK 0xFFFFFFFFL |
22766 | //PA_CL_VPORT_YSCALE_9 |
22767 | #define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE__SHIFT 0x0 |
22768 | #define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE_MASK 0xFFFFFFFFL |
22769 | //PA_CL_VPORT_YOFFSET_9 |
22770 | #define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET__SHIFT 0x0 |
22771 | #define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET_MASK 0xFFFFFFFFL |
22772 | //PA_CL_VPORT_ZSCALE_9 |
22773 | #define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE__SHIFT 0x0 |
22774 | #define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE_MASK 0xFFFFFFFFL |
22775 | //PA_CL_VPORT_ZOFFSET_9 |
22776 | #define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET__SHIFT 0x0 |
22777 | #define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET_MASK 0xFFFFFFFFL |
22778 | //PA_CL_VPORT_XSCALE_10 |
22779 | #define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE__SHIFT 0x0 |
22780 | #define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE_MASK 0xFFFFFFFFL |
22781 | //PA_CL_VPORT_XOFFSET_10 |
22782 | #define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET__SHIFT 0x0 |
22783 | #define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET_MASK 0xFFFFFFFFL |
22784 | //PA_CL_VPORT_YSCALE_10 |
22785 | #define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE__SHIFT 0x0 |
22786 | #define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE_MASK 0xFFFFFFFFL |
22787 | //PA_CL_VPORT_YOFFSET_10 |
22788 | #define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET__SHIFT 0x0 |
22789 | #define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET_MASK 0xFFFFFFFFL |
22790 | //PA_CL_VPORT_ZSCALE_10 |
22791 | #define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE__SHIFT 0x0 |
22792 | #define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE_MASK 0xFFFFFFFFL |
22793 | //PA_CL_VPORT_ZOFFSET_10 |
22794 | #define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET__SHIFT 0x0 |
22795 | #define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET_MASK 0xFFFFFFFFL |
22796 | //PA_CL_VPORT_XSCALE_11 |
22797 | #define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE__SHIFT 0x0 |
22798 | #define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE_MASK 0xFFFFFFFFL |
22799 | //PA_CL_VPORT_XOFFSET_11 |
22800 | #define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET__SHIFT 0x0 |
22801 | #define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET_MASK 0xFFFFFFFFL |
22802 | //PA_CL_VPORT_YSCALE_11 |
22803 | #define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE__SHIFT 0x0 |
22804 | #define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE_MASK 0xFFFFFFFFL |
22805 | //PA_CL_VPORT_YOFFSET_11 |
22806 | #define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET__SHIFT 0x0 |
22807 | #define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET_MASK 0xFFFFFFFFL |
22808 | //PA_CL_VPORT_ZSCALE_11 |
22809 | #define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE__SHIFT 0x0 |
22810 | #define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE_MASK 0xFFFFFFFFL |
22811 | //PA_CL_VPORT_ZOFFSET_11 |
22812 | #define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET__SHIFT 0x0 |
22813 | #define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET_MASK 0xFFFFFFFFL |
22814 | //PA_CL_VPORT_XSCALE_12 |
22815 | #define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE__SHIFT 0x0 |
22816 | #define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE_MASK 0xFFFFFFFFL |
22817 | //PA_CL_VPORT_XOFFSET_12 |
22818 | #define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET__SHIFT 0x0 |
22819 | #define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET_MASK 0xFFFFFFFFL |
22820 | //PA_CL_VPORT_YSCALE_12 |
22821 | #define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE__SHIFT 0x0 |
22822 | #define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE_MASK 0xFFFFFFFFL |
22823 | //PA_CL_VPORT_YOFFSET_12 |
22824 | #define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET__SHIFT 0x0 |
22825 | #define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET_MASK 0xFFFFFFFFL |
22826 | //PA_CL_VPORT_ZSCALE_12 |
22827 | #define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE__SHIFT 0x0 |
22828 | #define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE_MASK 0xFFFFFFFFL |
22829 | //PA_CL_VPORT_ZOFFSET_12 |
22830 | #define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET__SHIFT 0x0 |
22831 | #define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET_MASK 0xFFFFFFFFL |
22832 | //PA_CL_VPORT_XSCALE_13 |
22833 | #define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE__SHIFT 0x0 |
22834 | #define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE_MASK 0xFFFFFFFFL |
22835 | //PA_CL_VPORT_XOFFSET_13 |
22836 | #define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET__SHIFT 0x0 |
22837 | #define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET_MASK 0xFFFFFFFFL |
22838 | //PA_CL_VPORT_YSCALE_13 |
22839 | #define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE__SHIFT 0x0 |
22840 | #define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE_MASK 0xFFFFFFFFL |
22841 | //PA_CL_VPORT_YOFFSET_13 |
22842 | #define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET__SHIFT 0x0 |
22843 | #define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET_MASK 0xFFFFFFFFL |
22844 | //PA_CL_VPORT_ZSCALE_13 |
22845 | #define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE__SHIFT 0x0 |
22846 | #define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE_MASK 0xFFFFFFFFL |
22847 | //PA_CL_VPORT_ZOFFSET_13 |
22848 | #define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET__SHIFT 0x0 |
22849 | #define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET_MASK 0xFFFFFFFFL |
22850 | //PA_CL_VPORT_XSCALE_14 |
22851 | #define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE__SHIFT 0x0 |
22852 | #define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE_MASK 0xFFFFFFFFL |
22853 | //PA_CL_VPORT_XOFFSET_14 |
22854 | #define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET__SHIFT 0x0 |
22855 | #define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET_MASK 0xFFFFFFFFL |
22856 | //PA_CL_VPORT_YSCALE_14 |
22857 | #define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE__SHIFT 0x0 |
22858 | #define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE_MASK 0xFFFFFFFFL |
22859 | //PA_CL_VPORT_YOFFSET_14 |
22860 | #define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET__SHIFT 0x0 |
22861 | #define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET_MASK 0xFFFFFFFFL |
22862 | //PA_CL_VPORT_ZSCALE_14 |
22863 | #define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE__SHIFT 0x0 |
22864 | #define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE_MASK 0xFFFFFFFFL |
22865 | //PA_CL_VPORT_ZOFFSET_14 |
22866 | #define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET__SHIFT 0x0 |
22867 | #define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET_MASK 0xFFFFFFFFL |
22868 | //PA_CL_VPORT_XSCALE_15 |
22869 | #define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE__SHIFT 0x0 |
22870 | #define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE_MASK 0xFFFFFFFFL |
22871 | //PA_CL_VPORT_XOFFSET_15 |
22872 | #define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET__SHIFT 0x0 |
22873 | #define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET_MASK 0xFFFFFFFFL |
22874 | //PA_CL_VPORT_YSCALE_15 |
22875 | #define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE__SHIFT 0x0 |
22876 | #define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE_MASK 0xFFFFFFFFL |
22877 | //PA_CL_VPORT_YOFFSET_15 |
22878 | #define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET__SHIFT 0x0 |
22879 | #define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET_MASK 0xFFFFFFFFL |
22880 | //PA_CL_VPORT_ZSCALE_15 |
22881 | #define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE__SHIFT 0x0 |
22882 | #define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE_MASK 0xFFFFFFFFL |
22883 | //PA_CL_VPORT_ZOFFSET_15 |
22884 | #define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET__SHIFT 0x0 |
22885 | #define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET_MASK 0xFFFFFFFFL |
22886 | //PA_CL_UCP_0_X |
22887 | #define PA_CL_UCP_0_X__DATA_REGISTER__SHIFT 0x0 |
22888 | #define PA_CL_UCP_0_X__DATA_REGISTER_MASK 0xFFFFFFFFL |
22889 | //PA_CL_UCP_0_Y |
22890 | #define PA_CL_UCP_0_Y__DATA_REGISTER__SHIFT 0x0 |
22891 | #define PA_CL_UCP_0_Y__DATA_REGISTER_MASK 0xFFFFFFFFL |
22892 | //PA_CL_UCP_0_Z |
22893 | #define PA_CL_UCP_0_Z__DATA_REGISTER__SHIFT 0x0 |
22894 | #define PA_CL_UCP_0_Z__DATA_REGISTER_MASK 0xFFFFFFFFL |
22895 | //PA_CL_UCP_0_W |
22896 | #define PA_CL_UCP_0_W__DATA_REGISTER__SHIFT 0x0 |
22897 | #define PA_CL_UCP_0_W__DATA_REGISTER_MASK 0xFFFFFFFFL |
22898 | //PA_CL_UCP_1_X |
22899 | #define PA_CL_UCP_1_X__DATA_REGISTER__SHIFT 0x0 |
22900 | #define PA_CL_UCP_1_X__DATA_REGISTER_MASK 0xFFFFFFFFL |
22901 | //PA_CL_UCP_1_Y |
22902 | #define PA_CL_UCP_1_Y__DATA_REGISTER__SHIFT 0x0 |
22903 | #define PA_CL_UCP_1_Y__DATA_REGISTER_MASK 0xFFFFFFFFL |
22904 | //PA_CL_UCP_1_Z |
22905 | #define PA_CL_UCP_1_Z__DATA_REGISTER__SHIFT 0x0 |
22906 | #define PA_CL_UCP_1_Z__DATA_REGISTER_MASK 0xFFFFFFFFL |
22907 | //PA_CL_UCP_1_W |
22908 | #define PA_CL_UCP_1_W__DATA_REGISTER__SHIFT 0x0 |
22909 | #define PA_CL_UCP_1_W__DATA_REGISTER_MASK 0xFFFFFFFFL |
22910 | //PA_CL_UCP_2_X |
22911 | #define PA_CL_UCP_2_X__DATA_REGISTER__SHIFT 0x0 |
22912 | #define PA_CL_UCP_2_X__DATA_REGISTER_MASK 0xFFFFFFFFL |
22913 | //PA_CL_UCP_2_Y |
22914 | #define PA_CL_UCP_2_Y__DATA_REGISTER__SHIFT 0x0 |
22915 | #define PA_CL_UCP_2_Y__DATA_REGISTER_MASK 0xFFFFFFFFL |
22916 | //PA_CL_UCP_2_Z |
22917 | #define PA_CL_UCP_2_Z__DATA_REGISTER__SHIFT 0x0 |
22918 | #define PA_CL_UCP_2_Z__DATA_REGISTER_MASK 0xFFFFFFFFL |
22919 | //PA_CL_UCP_2_W |
22920 | #define PA_CL_UCP_2_W__DATA_REGISTER__SHIFT 0x0 |
22921 | #define PA_CL_UCP_2_W__DATA_REGISTER_MASK 0xFFFFFFFFL |
22922 | //PA_CL_UCP_3_X |
22923 | #define PA_CL_UCP_3_X__DATA_REGISTER__SHIFT 0x0 |
22924 | #define PA_CL_UCP_3_X__DATA_REGISTER_MASK 0xFFFFFFFFL |
22925 | //PA_CL_UCP_3_Y |
22926 | #define PA_CL_UCP_3_Y__DATA_REGISTER__SHIFT 0x0 |
22927 | #define PA_CL_UCP_3_Y__DATA_REGISTER_MASK 0xFFFFFFFFL |
22928 | //PA_CL_UCP_3_Z |
22929 | #define PA_CL_UCP_3_Z__DATA_REGISTER__SHIFT 0x0 |
22930 | #define PA_CL_UCP_3_Z__DATA_REGISTER_MASK 0xFFFFFFFFL |
22931 | //PA_CL_UCP_3_W |
22932 | #define PA_CL_UCP_3_W__DATA_REGISTER__SHIFT 0x0 |
22933 | #define PA_CL_UCP_3_W__DATA_REGISTER_MASK 0xFFFFFFFFL |
22934 | //PA_CL_UCP_4_X |
22935 | #define PA_CL_UCP_4_X__DATA_REGISTER__SHIFT 0x0 |
22936 | #define PA_CL_UCP_4_X__DATA_REGISTER_MASK 0xFFFFFFFFL |
22937 | //PA_CL_UCP_4_Y |
22938 | #define PA_CL_UCP_4_Y__DATA_REGISTER__SHIFT 0x0 |
22939 | #define PA_CL_UCP_4_Y__DATA_REGISTER_MASK 0xFFFFFFFFL |
22940 | //PA_CL_UCP_4_Z |
22941 | #define PA_CL_UCP_4_Z__DATA_REGISTER__SHIFT 0x0 |
22942 | #define PA_CL_UCP_4_Z__DATA_REGISTER_MASK 0xFFFFFFFFL |
22943 | //PA_CL_UCP_4_W |
22944 | #define PA_CL_UCP_4_W__DATA_REGISTER__SHIFT 0x0 |
22945 | #define PA_CL_UCP_4_W__DATA_REGISTER_MASK 0xFFFFFFFFL |
22946 | //PA_CL_UCP_5_X |
22947 | #define PA_CL_UCP_5_X__DATA_REGISTER__SHIFT 0x0 |
22948 | #define PA_CL_UCP_5_X__DATA_REGISTER_MASK 0xFFFFFFFFL |
22949 | //PA_CL_UCP_5_Y |
22950 | #define PA_CL_UCP_5_Y__DATA_REGISTER__SHIFT 0x0 |
22951 | #define PA_CL_UCP_5_Y__DATA_REGISTER_MASK 0xFFFFFFFFL |
22952 | //PA_CL_UCP_5_Z |
22953 | #define PA_CL_UCP_5_Z__DATA_REGISTER__SHIFT 0x0 |
22954 | #define PA_CL_UCP_5_Z__DATA_REGISTER_MASK 0xFFFFFFFFL |
22955 | //PA_CL_UCP_5_W |
22956 | #define PA_CL_UCP_5_W__DATA_REGISTER__SHIFT 0x0 |
22957 | #define PA_CL_UCP_5_W__DATA_REGISTER_MASK 0xFFFFFFFFL |
22958 | //PA_CL_PROG_NEAR_CLIP_Z |
22959 | #define PA_CL_PROG_NEAR_CLIP_Z__DATA_REGISTER__SHIFT 0x0 |
22960 | #define PA_CL_PROG_NEAR_CLIP_Z__DATA_REGISTER_MASK 0xFFFFFFFFL |
22961 | //PA_RATE_CNTL |
22962 | #define PA_RATE_CNTL__VERTEX_RATE__SHIFT 0x0 |
22963 | #define PA_RATE_CNTL__PRIM_RATE__SHIFT 0x4 |
22964 | #define PA_RATE_CNTL__VERTEX_RATE_MASK 0x0000000FL |
22965 | #define PA_RATE_CNTL__PRIM_RATE_MASK 0x000000F0L |
22966 | //SPI_PS_INPUT_CNTL_0 |
22967 | #define SPI_PS_INPUT_CNTL_0__OFFSET__SHIFT 0x0 |
22968 | #define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL__SHIFT 0x8 |
22969 | #define SPI_PS_INPUT_CNTL_0__FLAT_SHADE__SHIFT 0xa |
22970 | #define SPI_PS_INPUT_CNTL_0__ROTATE_PC_PTR__SHIFT 0xb |
22971 | #define SPI_PS_INPUT_CNTL_0__PRIM_ATTR__SHIFT 0xc |
22972 | #define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX__SHIFT 0x11 |
22973 | #define SPI_PS_INPUT_CNTL_0__DUP__SHIFT 0x12 |
22974 | #define SPI_PS_INPUT_CNTL_0__FP16_INTERP_MODE__SHIFT 0x13 |
22975 | #define SPI_PS_INPUT_CNTL_0__USE_DEFAULT_ATTR1__SHIFT 0x14 |
22976 | #define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
22977 | #define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 |
22978 | #define SPI_PS_INPUT_CNTL_0__ATTR0_VALID__SHIFT 0x18 |
22979 | #define SPI_PS_INPUT_CNTL_0__ATTR1_VALID__SHIFT 0x19 |
22980 | #define SPI_PS_INPUT_CNTL_0__OFFSET_MASK 0x0000003FL |
22981 | #define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_MASK 0x00000300L |
22982 | #define SPI_PS_INPUT_CNTL_0__FLAT_SHADE_MASK 0x00000400L |
22983 | #define SPI_PS_INPUT_CNTL_0__ROTATE_PC_PTR_MASK 0x00000800L |
22984 | #define SPI_PS_INPUT_CNTL_0__PRIM_ATTR_MASK 0x00001000L |
22985 | #define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_MASK 0x00020000L |
22986 | #define SPI_PS_INPUT_CNTL_0__DUP_MASK 0x00040000L |
22987 | #define SPI_PS_INPUT_CNTL_0__FP16_INTERP_MODE_MASK 0x00080000L |
22988 | #define SPI_PS_INPUT_CNTL_0__USE_DEFAULT_ATTR1_MASK 0x00100000L |
22989 | #define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
22990 | #define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L |
22991 | #define SPI_PS_INPUT_CNTL_0__ATTR0_VALID_MASK 0x01000000L |
22992 | #define SPI_PS_INPUT_CNTL_0__ATTR1_VALID_MASK 0x02000000L |
22993 | //SPI_PS_INPUT_CNTL_1 |
22994 | #define SPI_PS_INPUT_CNTL_1__OFFSET__SHIFT 0x0 |
22995 | #define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL__SHIFT 0x8 |
22996 | #define SPI_PS_INPUT_CNTL_1__FLAT_SHADE__SHIFT 0xa |
22997 | #define SPI_PS_INPUT_CNTL_1__ROTATE_PC_PTR__SHIFT 0xb |
22998 | #define SPI_PS_INPUT_CNTL_1__PRIM_ATTR__SHIFT 0xc |
22999 | #define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX__SHIFT 0x11 |
23000 | #define SPI_PS_INPUT_CNTL_1__DUP__SHIFT 0x12 |
23001 | #define SPI_PS_INPUT_CNTL_1__FP16_INTERP_MODE__SHIFT 0x13 |
23002 | #define SPI_PS_INPUT_CNTL_1__USE_DEFAULT_ATTR1__SHIFT 0x14 |
23003 | #define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
23004 | #define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 |
23005 | #define SPI_PS_INPUT_CNTL_1__ATTR0_VALID__SHIFT 0x18 |
23006 | #define SPI_PS_INPUT_CNTL_1__ATTR1_VALID__SHIFT 0x19 |
23007 | #define SPI_PS_INPUT_CNTL_1__OFFSET_MASK 0x0000003FL |
23008 | #define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_MASK 0x00000300L |
23009 | #define SPI_PS_INPUT_CNTL_1__FLAT_SHADE_MASK 0x00000400L |
23010 | #define SPI_PS_INPUT_CNTL_1__ROTATE_PC_PTR_MASK 0x00000800L |
23011 | #define SPI_PS_INPUT_CNTL_1__PRIM_ATTR_MASK 0x00001000L |
23012 | #define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_MASK 0x00020000L |
23013 | #define SPI_PS_INPUT_CNTL_1__DUP_MASK 0x00040000L |
23014 | #define SPI_PS_INPUT_CNTL_1__FP16_INTERP_MODE_MASK 0x00080000L |
23015 | #define SPI_PS_INPUT_CNTL_1__USE_DEFAULT_ATTR1_MASK 0x00100000L |
23016 | #define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
23017 | #define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L |
23018 | #define SPI_PS_INPUT_CNTL_1__ATTR0_VALID_MASK 0x01000000L |
23019 | #define SPI_PS_INPUT_CNTL_1__ATTR1_VALID_MASK 0x02000000L |
23020 | //SPI_PS_INPUT_CNTL_2 |
23021 | #define SPI_PS_INPUT_CNTL_2__OFFSET__SHIFT 0x0 |
23022 | #define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL__SHIFT 0x8 |
23023 | #define SPI_PS_INPUT_CNTL_2__FLAT_SHADE__SHIFT 0xa |
23024 | #define SPI_PS_INPUT_CNTL_2__ROTATE_PC_PTR__SHIFT 0xb |
23025 | #define SPI_PS_INPUT_CNTL_2__PRIM_ATTR__SHIFT 0xc |
23026 | #define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX__SHIFT 0x11 |
23027 | #define SPI_PS_INPUT_CNTL_2__DUP__SHIFT 0x12 |
23028 | #define SPI_PS_INPUT_CNTL_2__FP16_INTERP_MODE__SHIFT 0x13 |
23029 | #define SPI_PS_INPUT_CNTL_2__USE_DEFAULT_ATTR1__SHIFT 0x14 |
23030 | #define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
23031 | #define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 |
23032 | #define SPI_PS_INPUT_CNTL_2__ATTR0_VALID__SHIFT 0x18 |
23033 | #define SPI_PS_INPUT_CNTL_2__ATTR1_VALID__SHIFT 0x19 |
23034 | #define SPI_PS_INPUT_CNTL_2__OFFSET_MASK 0x0000003FL |
23035 | #define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_MASK 0x00000300L |
23036 | #define SPI_PS_INPUT_CNTL_2__FLAT_SHADE_MASK 0x00000400L |
23037 | #define SPI_PS_INPUT_CNTL_2__ROTATE_PC_PTR_MASK 0x00000800L |
23038 | #define SPI_PS_INPUT_CNTL_2__PRIM_ATTR_MASK 0x00001000L |
23039 | #define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_MASK 0x00020000L |
23040 | #define SPI_PS_INPUT_CNTL_2__DUP_MASK 0x00040000L |
23041 | #define SPI_PS_INPUT_CNTL_2__FP16_INTERP_MODE_MASK 0x00080000L |
23042 | #define SPI_PS_INPUT_CNTL_2__USE_DEFAULT_ATTR1_MASK 0x00100000L |
23043 | #define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
23044 | #define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L |
23045 | #define SPI_PS_INPUT_CNTL_2__ATTR0_VALID_MASK 0x01000000L |
23046 | #define SPI_PS_INPUT_CNTL_2__ATTR1_VALID_MASK 0x02000000L |
23047 | //SPI_PS_INPUT_CNTL_3 |
23048 | #define SPI_PS_INPUT_CNTL_3__OFFSET__SHIFT 0x0 |
23049 | #define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL__SHIFT 0x8 |
23050 | #define SPI_PS_INPUT_CNTL_3__FLAT_SHADE__SHIFT 0xa |
23051 | #define SPI_PS_INPUT_CNTL_3__ROTATE_PC_PTR__SHIFT 0xb |
23052 | #define SPI_PS_INPUT_CNTL_3__PRIM_ATTR__SHIFT 0xc |
23053 | #define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX__SHIFT 0x11 |
23054 | #define SPI_PS_INPUT_CNTL_3__DUP__SHIFT 0x12 |
23055 | #define SPI_PS_INPUT_CNTL_3__FP16_INTERP_MODE__SHIFT 0x13 |
23056 | #define SPI_PS_INPUT_CNTL_3__USE_DEFAULT_ATTR1__SHIFT 0x14 |
23057 | #define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
23058 | #define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 |
23059 | #define SPI_PS_INPUT_CNTL_3__ATTR0_VALID__SHIFT 0x18 |
23060 | #define SPI_PS_INPUT_CNTL_3__ATTR1_VALID__SHIFT 0x19 |
23061 | #define SPI_PS_INPUT_CNTL_3__OFFSET_MASK 0x0000003FL |
23062 | #define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_MASK 0x00000300L |
23063 | #define SPI_PS_INPUT_CNTL_3__FLAT_SHADE_MASK 0x00000400L |
23064 | #define SPI_PS_INPUT_CNTL_3__ROTATE_PC_PTR_MASK 0x00000800L |
23065 | #define SPI_PS_INPUT_CNTL_3__PRIM_ATTR_MASK 0x00001000L |
23066 | #define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_MASK 0x00020000L |
23067 | #define SPI_PS_INPUT_CNTL_3__DUP_MASK 0x00040000L |
23068 | #define SPI_PS_INPUT_CNTL_3__FP16_INTERP_MODE_MASK 0x00080000L |
23069 | #define SPI_PS_INPUT_CNTL_3__USE_DEFAULT_ATTR1_MASK 0x00100000L |
23070 | #define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
23071 | #define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L |
23072 | #define SPI_PS_INPUT_CNTL_3__ATTR0_VALID_MASK 0x01000000L |
23073 | #define SPI_PS_INPUT_CNTL_3__ATTR1_VALID_MASK 0x02000000L |
23074 | //SPI_PS_INPUT_CNTL_4 |
23075 | #define SPI_PS_INPUT_CNTL_4__OFFSET__SHIFT 0x0 |
23076 | #define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL__SHIFT 0x8 |
23077 | #define SPI_PS_INPUT_CNTL_4__FLAT_SHADE__SHIFT 0xa |
23078 | #define SPI_PS_INPUT_CNTL_4__ROTATE_PC_PTR__SHIFT 0xb |
23079 | #define SPI_PS_INPUT_CNTL_4__PRIM_ATTR__SHIFT 0xc |
23080 | #define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX__SHIFT 0x11 |
23081 | #define SPI_PS_INPUT_CNTL_4__DUP__SHIFT 0x12 |
23082 | #define SPI_PS_INPUT_CNTL_4__FP16_INTERP_MODE__SHIFT 0x13 |
23083 | #define SPI_PS_INPUT_CNTL_4__USE_DEFAULT_ATTR1__SHIFT 0x14 |
23084 | #define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
23085 | #define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 |
23086 | #define SPI_PS_INPUT_CNTL_4__ATTR0_VALID__SHIFT 0x18 |
23087 | #define SPI_PS_INPUT_CNTL_4__ATTR1_VALID__SHIFT 0x19 |
23088 | #define SPI_PS_INPUT_CNTL_4__OFFSET_MASK 0x0000003FL |
23089 | #define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_MASK 0x00000300L |
23090 | #define SPI_PS_INPUT_CNTL_4__FLAT_SHADE_MASK 0x00000400L |
23091 | #define SPI_PS_INPUT_CNTL_4__ROTATE_PC_PTR_MASK 0x00000800L |
23092 | #define SPI_PS_INPUT_CNTL_4__PRIM_ATTR_MASK 0x00001000L |
23093 | #define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_MASK 0x00020000L |
23094 | #define SPI_PS_INPUT_CNTL_4__DUP_MASK 0x00040000L |
23095 | #define SPI_PS_INPUT_CNTL_4__FP16_INTERP_MODE_MASK 0x00080000L |
23096 | #define SPI_PS_INPUT_CNTL_4__USE_DEFAULT_ATTR1_MASK 0x00100000L |
23097 | #define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
23098 | #define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L |
23099 | #define SPI_PS_INPUT_CNTL_4__ATTR0_VALID_MASK 0x01000000L |
23100 | #define SPI_PS_INPUT_CNTL_4__ATTR1_VALID_MASK 0x02000000L |
23101 | //SPI_PS_INPUT_CNTL_5 |
23102 | #define SPI_PS_INPUT_CNTL_5__OFFSET__SHIFT 0x0 |
23103 | #define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL__SHIFT 0x8 |
23104 | #define SPI_PS_INPUT_CNTL_5__FLAT_SHADE__SHIFT 0xa |
23105 | #define SPI_PS_INPUT_CNTL_5__ROTATE_PC_PTR__SHIFT 0xb |
23106 | #define SPI_PS_INPUT_CNTL_5__PRIM_ATTR__SHIFT 0xc |
23107 | #define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX__SHIFT 0x11 |
23108 | #define SPI_PS_INPUT_CNTL_5__DUP__SHIFT 0x12 |
23109 | #define SPI_PS_INPUT_CNTL_5__FP16_INTERP_MODE__SHIFT 0x13 |
23110 | #define SPI_PS_INPUT_CNTL_5__USE_DEFAULT_ATTR1__SHIFT 0x14 |
23111 | #define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
23112 | #define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 |
23113 | #define SPI_PS_INPUT_CNTL_5__ATTR0_VALID__SHIFT 0x18 |
23114 | #define SPI_PS_INPUT_CNTL_5__ATTR1_VALID__SHIFT 0x19 |
23115 | #define SPI_PS_INPUT_CNTL_5__OFFSET_MASK 0x0000003FL |
23116 | #define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_MASK 0x00000300L |
23117 | #define SPI_PS_INPUT_CNTL_5__FLAT_SHADE_MASK 0x00000400L |
23118 | #define SPI_PS_INPUT_CNTL_5__ROTATE_PC_PTR_MASK 0x00000800L |
23119 | #define SPI_PS_INPUT_CNTL_5__PRIM_ATTR_MASK 0x00001000L |
23120 | #define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_MASK 0x00020000L |
23121 | #define SPI_PS_INPUT_CNTL_5__DUP_MASK 0x00040000L |
23122 | #define SPI_PS_INPUT_CNTL_5__FP16_INTERP_MODE_MASK 0x00080000L |
23123 | #define SPI_PS_INPUT_CNTL_5__USE_DEFAULT_ATTR1_MASK 0x00100000L |
23124 | #define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
23125 | #define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L |
23126 | #define SPI_PS_INPUT_CNTL_5__ATTR0_VALID_MASK 0x01000000L |
23127 | #define SPI_PS_INPUT_CNTL_5__ATTR1_VALID_MASK 0x02000000L |
23128 | //SPI_PS_INPUT_CNTL_6 |
23129 | #define SPI_PS_INPUT_CNTL_6__OFFSET__SHIFT 0x0 |
23130 | #define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL__SHIFT 0x8 |
23131 | #define SPI_PS_INPUT_CNTL_6__FLAT_SHADE__SHIFT 0xa |
23132 | #define SPI_PS_INPUT_CNTL_6__ROTATE_PC_PTR__SHIFT 0xb |
23133 | #define SPI_PS_INPUT_CNTL_6__PRIM_ATTR__SHIFT 0xc |
23134 | #define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX__SHIFT 0x11 |
23135 | #define SPI_PS_INPUT_CNTL_6__DUP__SHIFT 0x12 |
23136 | #define SPI_PS_INPUT_CNTL_6__FP16_INTERP_MODE__SHIFT 0x13 |
23137 | #define SPI_PS_INPUT_CNTL_6__USE_DEFAULT_ATTR1__SHIFT 0x14 |
23138 | #define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
23139 | #define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 |
23140 | #define SPI_PS_INPUT_CNTL_6__ATTR0_VALID__SHIFT 0x18 |
23141 | #define SPI_PS_INPUT_CNTL_6__ATTR1_VALID__SHIFT 0x19 |
23142 | #define SPI_PS_INPUT_CNTL_6__OFFSET_MASK 0x0000003FL |
23143 | #define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_MASK 0x00000300L |
23144 | #define SPI_PS_INPUT_CNTL_6__FLAT_SHADE_MASK 0x00000400L |
23145 | #define SPI_PS_INPUT_CNTL_6__ROTATE_PC_PTR_MASK 0x00000800L |
23146 | #define SPI_PS_INPUT_CNTL_6__PRIM_ATTR_MASK 0x00001000L |
23147 | #define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_MASK 0x00020000L |
23148 | #define SPI_PS_INPUT_CNTL_6__DUP_MASK 0x00040000L |
23149 | #define SPI_PS_INPUT_CNTL_6__FP16_INTERP_MODE_MASK 0x00080000L |
23150 | #define SPI_PS_INPUT_CNTL_6__USE_DEFAULT_ATTR1_MASK 0x00100000L |
23151 | #define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
23152 | #define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L |
23153 | #define SPI_PS_INPUT_CNTL_6__ATTR0_VALID_MASK 0x01000000L |
23154 | #define SPI_PS_INPUT_CNTL_6__ATTR1_VALID_MASK 0x02000000L |
23155 | //SPI_PS_INPUT_CNTL_7 |
23156 | #define SPI_PS_INPUT_CNTL_7__OFFSET__SHIFT 0x0 |
23157 | #define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL__SHIFT 0x8 |
23158 | #define SPI_PS_INPUT_CNTL_7__FLAT_SHADE__SHIFT 0xa |
23159 | #define SPI_PS_INPUT_CNTL_7__ROTATE_PC_PTR__SHIFT 0xb |
23160 | #define SPI_PS_INPUT_CNTL_7__PRIM_ATTR__SHIFT 0xc |
23161 | #define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX__SHIFT 0x11 |
23162 | #define SPI_PS_INPUT_CNTL_7__DUP__SHIFT 0x12 |
23163 | #define SPI_PS_INPUT_CNTL_7__FP16_INTERP_MODE__SHIFT 0x13 |
23164 | #define SPI_PS_INPUT_CNTL_7__USE_DEFAULT_ATTR1__SHIFT 0x14 |
23165 | #define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
23166 | #define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 |
23167 | #define SPI_PS_INPUT_CNTL_7__ATTR0_VALID__SHIFT 0x18 |
23168 | #define SPI_PS_INPUT_CNTL_7__ATTR1_VALID__SHIFT 0x19 |
23169 | #define SPI_PS_INPUT_CNTL_7__OFFSET_MASK 0x0000003FL |
23170 | #define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_MASK 0x00000300L |
23171 | #define SPI_PS_INPUT_CNTL_7__FLAT_SHADE_MASK 0x00000400L |
23172 | #define SPI_PS_INPUT_CNTL_7__ROTATE_PC_PTR_MASK 0x00000800L |
23173 | #define SPI_PS_INPUT_CNTL_7__PRIM_ATTR_MASK 0x00001000L |
23174 | #define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_MASK 0x00020000L |
23175 | #define SPI_PS_INPUT_CNTL_7__DUP_MASK 0x00040000L |
23176 | #define SPI_PS_INPUT_CNTL_7__FP16_INTERP_MODE_MASK 0x00080000L |
23177 | #define SPI_PS_INPUT_CNTL_7__USE_DEFAULT_ATTR1_MASK 0x00100000L |
23178 | #define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
23179 | #define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L |
23180 | #define SPI_PS_INPUT_CNTL_7__ATTR0_VALID_MASK 0x01000000L |
23181 | #define SPI_PS_INPUT_CNTL_7__ATTR1_VALID_MASK 0x02000000L |
23182 | //SPI_PS_INPUT_CNTL_8 |
23183 | #define SPI_PS_INPUT_CNTL_8__OFFSET__SHIFT 0x0 |
23184 | #define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL__SHIFT 0x8 |
23185 | #define SPI_PS_INPUT_CNTL_8__FLAT_SHADE__SHIFT 0xa |
23186 | #define SPI_PS_INPUT_CNTL_8__ROTATE_PC_PTR__SHIFT 0xb |
23187 | #define SPI_PS_INPUT_CNTL_8__PRIM_ATTR__SHIFT 0xc |
23188 | #define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX__SHIFT 0x11 |
23189 | #define SPI_PS_INPUT_CNTL_8__DUP__SHIFT 0x12 |
23190 | #define SPI_PS_INPUT_CNTL_8__FP16_INTERP_MODE__SHIFT 0x13 |
23191 | #define SPI_PS_INPUT_CNTL_8__USE_DEFAULT_ATTR1__SHIFT 0x14 |
23192 | #define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
23193 | #define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 |
23194 | #define SPI_PS_INPUT_CNTL_8__ATTR0_VALID__SHIFT 0x18 |
23195 | #define SPI_PS_INPUT_CNTL_8__ATTR1_VALID__SHIFT 0x19 |
23196 | #define SPI_PS_INPUT_CNTL_8__OFFSET_MASK 0x0000003FL |
23197 | #define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_MASK 0x00000300L |
23198 | #define SPI_PS_INPUT_CNTL_8__FLAT_SHADE_MASK 0x00000400L |
23199 | #define SPI_PS_INPUT_CNTL_8__ROTATE_PC_PTR_MASK 0x00000800L |
23200 | #define SPI_PS_INPUT_CNTL_8__PRIM_ATTR_MASK 0x00001000L |
23201 | #define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_MASK 0x00020000L |
23202 | #define SPI_PS_INPUT_CNTL_8__DUP_MASK 0x00040000L |
23203 | #define SPI_PS_INPUT_CNTL_8__FP16_INTERP_MODE_MASK 0x00080000L |
23204 | #define SPI_PS_INPUT_CNTL_8__USE_DEFAULT_ATTR1_MASK 0x00100000L |
23205 | #define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
23206 | #define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L |
23207 | #define SPI_PS_INPUT_CNTL_8__ATTR0_VALID_MASK 0x01000000L |
23208 | #define SPI_PS_INPUT_CNTL_8__ATTR1_VALID_MASK 0x02000000L |
23209 | //SPI_PS_INPUT_CNTL_9 |
23210 | #define SPI_PS_INPUT_CNTL_9__OFFSET__SHIFT 0x0 |
23211 | #define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL__SHIFT 0x8 |
23212 | #define SPI_PS_INPUT_CNTL_9__FLAT_SHADE__SHIFT 0xa |
23213 | #define SPI_PS_INPUT_CNTL_9__ROTATE_PC_PTR__SHIFT 0xb |
23214 | #define SPI_PS_INPUT_CNTL_9__PRIM_ATTR__SHIFT 0xc |
23215 | #define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX__SHIFT 0x11 |
23216 | #define SPI_PS_INPUT_CNTL_9__DUP__SHIFT 0x12 |
23217 | #define SPI_PS_INPUT_CNTL_9__FP16_INTERP_MODE__SHIFT 0x13 |
23218 | #define SPI_PS_INPUT_CNTL_9__USE_DEFAULT_ATTR1__SHIFT 0x14 |
23219 | #define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
23220 | #define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 |
23221 | #define SPI_PS_INPUT_CNTL_9__ATTR0_VALID__SHIFT 0x18 |
23222 | #define SPI_PS_INPUT_CNTL_9__ATTR1_VALID__SHIFT 0x19 |
23223 | #define SPI_PS_INPUT_CNTL_9__OFFSET_MASK 0x0000003FL |
23224 | #define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_MASK 0x00000300L |
23225 | #define SPI_PS_INPUT_CNTL_9__FLAT_SHADE_MASK 0x00000400L |
23226 | #define SPI_PS_INPUT_CNTL_9__ROTATE_PC_PTR_MASK 0x00000800L |
23227 | #define SPI_PS_INPUT_CNTL_9__PRIM_ATTR_MASK 0x00001000L |
23228 | #define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_MASK 0x00020000L |
23229 | #define SPI_PS_INPUT_CNTL_9__DUP_MASK 0x00040000L |
23230 | #define SPI_PS_INPUT_CNTL_9__FP16_INTERP_MODE_MASK 0x00080000L |
23231 | #define SPI_PS_INPUT_CNTL_9__USE_DEFAULT_ATTR1_MASK 0x00100000L |
23232 | #define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
23233 | #define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L |
23234 | #define SPI_PS_INPUT_CNTL_9__ATTR0_VALID_MASK 0x01000000L |
23235 | #define SPI_PS_INPUT_CNTL_9__ATTR1_VALID_MASK 0x02000000L |
23236 | //SPI_PS_INPUT_CNTL_10 |
23237 | #define SPI_PS_INPUT_CNTL_10__OFFSET__SHIFT 0x0 |
23238 | #define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL__SHIFT 0x8 |
23239 | #define SPI_PS_INPUT_CNTL_10__FLAT_SHADE__SHIFT 0xa |
23240 | #define SPI_PS_INPUT_CNTL_10__ROTATE_PC_PTR__SHIFT 0xb |
23241 | #define SPI_PS_INPUT_CNTL_10__PRIM_ATTR__SHIFT 0xc |
23242 | #define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX__SHIFT 0x11 |
23243 | #define SPI_PS_INPUT_CNTL_10__DUP__SHIFT 0x12 |
23244 | #define SPI_PS_INPUT_CNTL_10__FP16_INTERP_MODE__SHIFT 0x13 |
23245 | #define SPI_PS_INPUT_CNTL_10__USE_DEFAULT_ATTR1__SHIFT 0x14 |
23246 | #define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
23247 | #define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 |
23248 | #define SPI_PS_INPUT_CNTL_10__ATTR0_VALID__SHIFT 0x18 |
23249 | #define SPI_PS_INPUT_CNTL_10__ATTR1_VALID__SHIFT 0x19 |
23250 | #define SPI_PS_INPUT_CNTL_10__OFFSET_MASK 0x0000003FL |
23251 | #define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_MASK 0x00000300L |
23252 | #define SPI_PS_INPUT_CNTL_10__FLAT_SHADE_MASK 0x00000400L |
23253 | #define SPI_PS_INPUT_CNTL_10__ROTATE_PC_PTR_MASK 0x00000800L |
23254 | #define SPI_PS_INPUT_CNTL_10__PRIM_ATTR_MASK 0x00001000L |
23255 | #define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_MASK 0x00020000L |
23256 | #define SPI_PS_INPUT_CNTL_10__DUP_MASK 0x00040000L |
23257 | #define SPI_PS_INPUT_CNTL_10__FP16_INTERP_MODE_MASK 0x00080000L |
23258 | #define SPI_PS_INPUT_CNTL_10__USE_DEFAULT_ATTR1_MASK 0x00100000L |
23259 | #define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
23260 | #define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L |
23261 | #define SPI_PS_INPUT_CNTL_10__ATTR0_VALID_MASK 0x01000000L |
23262 | #define SPI_PS_INPUT_CNTL_10__ATTR1_VALID_MASK 0x02000000L |
23263 | //SPI_PS_INPUT_CNTL_11 |
23264 | #define SPI_PS_INPUT_CNTL_11__OFFSET__SHIFT 0x0 |
23265 | #define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL__SHIFT 0x8 |
23266 | #define SPI_PS_INPUT_CNTL_11__FLAT_SHADE__SHIFT 0xa |
23267 | #define SPI_PS_INPUT_CNTL_11__ROTATE_PC_PTR__SHIFT 0xb |
23268 | #define SPI_PS_INPUT_CNTL_11__PRIM_ATTR__SHIFT 0xc |
23269 | #define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX__SHIFT 0x11 |
23270 | #define SPI_PS_INPUT_CNTL_11__DUP__SHIFT 0x12 |
23271 | #define SPI_PS_INPUT_CNTL_11__FP16_INTERP_MODE__SHIFT 0x13 |
23272 | #define SPI_PS_INPUT_CNTL_11__USE_DEFAULT_ATTR1__SHIFT 0x14 |
23273 | #define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
23274 | #define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 |
23275 | #define SPI_PS_INPUT_CNTL_11__ATTR0_VALID__SHIFT 0x18 |
23276 | #define SPI_PS_INPUT_CNTL_11__ATTR1_VALID__SHIFT 0x19 |
23277 | #define SPI_PS_INPUT_CNTL_11__OFFSET_MASK 0x0000003FL |
23278 | #define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_MASK 0x00000300L |
23279 | #define SPI_PS_INPUT_CNTL_11__FLAT_SHADE_MASK 0x00000400L |
23280 | #define SPI_PS_INPUT_CNTL_11__ROTATE_PC_PTR_MASK 0x00000800L |
23281 | #define SPI_PS_INPUT_CNTL_11__PRIM_ATTR_MASK 0x00001000L |
23282 | #define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_MASK 0x00020000L |
23283 | #define SPI_PS_INPUT_CNTL_11__DUP_MASK 0x00040000L |
23284 | #define SPI_PS_INPUT_CNTL_11__FP16_INTERP_MODE_MASK 0x00080000L |
23285 | #define SPI_PS_INPUT_CNTL_11__USE_DEFAULT_ATTR1_MASK 0x00100000L |
23286 | #define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
23287 | #define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L |
23288 | #define SPI_PS_INPUT_CNTL_11__ATTR0_VALID_MASK 0x01000000L |
23289 | #define SPI_PS_INPUT_CNTL_11__ATTR1_VALID_MASK 0x02000000L |
23290 | //SPI_PS_INPUT_CNTL_12 |
23291 | #define SPI_PS_INPUT_CNTL_12__OFFSET__SHIFT 0x0 |
23292 | #define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL__SHIFT 0x8 |
23293 | #define SPI_PS_INPUT_CNTL_12__FLAT_SHADE__SHIFT 0xa |
23294 | #define SPI_PS_INPUT_CNTL_12__ROTATE_PC_PTR__SHIFT 0xb |
23295 | #define SPI_PS_INPUT_CNTL_12__PRIM_ATTR__SHIFT 0xc |
23296 | #define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX__SHIFT 0x11 |
23297 | #define SPI_PS_INPUT_CNTL_12__DUP__SHIFT 0x12 |
23298 | #define SPI_PS_INPUT_CNTL_12__FP16_INTERP_MODE__SHIFT 0x13 |
23299 | #define SPI_PS_INPUT_CNTL_12__USE_DEFAULT_ATTR1__SHIFT 0x14 |
23300 | #define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
23301 | #define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 |
23302 | #define SPI_PS_INPUT_CNTL_12__ATTR0_VALID__SHIFT 0x18 |
23303 | #define SPI_PS_INPUT_CNTL_12__ATTR1_VALID__SHIFT 0x19 |
23304 | #define SPI_PS_INPUT_CNTL_12__OFFSET_MASK 0x0000003FL |
23305 | #define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_MASK 0x00000300L |
23306 | #define SPI_PS_INPUT_CNTL_12__FLAT_SHADE_MASK 0x00000400L |
23307 | #define SPI_PS_INPUT_CNTL_12__ROTATE_PC_PTR_MASK 0x00000800L |
23308 | #define SPI_PS_INPUT_CNTL_12__PRIM_ATTR_MASK 0x00001000L |
23309 | #define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_MASK 0x00020000L |
23310 | #define SPI_PS_INPUT_CNTL_12__DUP_MASK 0x00040000L |
23311 | #define SPI_PS_INPUT_CNTL_12__FP16_INTERP_MODE_MASK 0x00080000L |
23312 | #define SPI_PS_INPUT_CNTL_12__USE_DEFAULT_ATTR1_MASK 0x00100000L |
23313 | #define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
23314 | #define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L |
23315 | #define SPI_PS_INPUT_CNTL_12__ATTR0_VALID_MASK 0x01000000L |
23316 | #define SPI_PS_INPUT_CNTL_12__ATTR1_VALID_MASK 0x02000000L |
23317 | //SPI_PS_INPUT_CNTL_13 |
23318 | #define SPI_PS_INPUT_CNTL_13__OFFSET__SHIFT 0x0 |
23319 | #define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL__SHIFT 0x8 |
23320 | #define SPI_PS_INPUT_CNTL_13__FLAT_SHADE__SHIFT 0xa |
23321 | #define SPI_PS_INPUT_CNTL_13__ROTATE_PC_PTR__SHIFT 0xb |
23322 | #define SPI_PS_INPUT_CNTL_13__PRIM_ATTR__SHIFT 0xc |
23323 | #define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX__SHIFT 0x11 |
23324 | #define SPI_PS_INPUT_CNTL_13__DUP__SHIFT 0x12 |
23325 | #define SPI_PS_INPUT_CNTL_13__FP16_INTERP_MODE__SHIFT 0x13 |
23326 | #define SPI_PS_INPUT_CNTL_13__USE_DEFAULT_ATTR1__SHIFT 0x14 |
23327 | #define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
23328 | #define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 |
23329 | #define SPI_PS_INPUT_CNTL_13__ATTR0_VALID__SHIFT 0x18 |
23330 | #define SPI_PS_INPUT_CNTL_13__ATTR1_VALID__SHIFT 0x19 |
23331 | #define SPI_PS_INPUT_CNTL_13__OFFSET_MASK 0x0000003FL |
23332 | #define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_MASK 0x00000300L |
23333 | #define SPI_PS_INPUT_CNTL_13__FLAT_SHADE_MASK 0x00000400L |
23334 | #define SPI_PS_INPUT_CNTL_13__ROTATE_PC_PTR_MASK 0x00000800L |
23335 | #define SPI_PS_INPUT_CNTL_13__PRIM_ATTR_MASK 0x00001000L |
23336 | #define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_MASK 0x00020000L |
23337 | #define SPI_PS_INPUT_CNTL_13__DUP_MASK 0x00040000L |
23338 | #define SPI_PS_INPUT_CNTL_13__FP16_INTERP_MODE_MASK 0x00080000L |
23339 | #define SPI_PS_INPUT_CNTL_13__USE_DEFAULT_ATTR1_MASK 0x00100000L |
23340 | #define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
23341 | #define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L |
23342 | #define SPI_PS_INPUT_CNTL_13__ATTR0_VALID_MASK 0x01000000L |
23343 | #define SPI_PS_INPUT_CNTL_13__ATTR1_VALID_MASK 0x02000000L |
23344 | //SPI_PS_INPUT_CNTL_14 |
23345 | #define SPI_PS_INPUT_CNTL_14__OFFSET__SHIFT 0x0 |
23346 | #define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL__SHIFT 0x8 |
23347 | #define SPI_PS_INPUT_CNTL_14__FLAT_SHADE__SHIFT 0xa |
23348 | #define SPI_PS_INPUT_CNTL_14__ROTATE_PC_PTR__SHIFT 0xb |
23349 | #define SPI_PS_INPUT_CNTL_14__PRIM_ATTR__SHIFT 0xc |
23350 | #define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX__SHIFT 0x11 |
23351 | #define SPI_PS_INPUT_CNTL_14__DUP__SHIFT 0x12 |
23352 | #define SPI_PS_INPUT_CNTL_14__FP16_INTERP_MODE__SHIFT 0x13 |
23353 | #define SPI_PS_INPUT_CNTL_14__USE_DEFAULT_ATTR1__SHIFT 0x14 |
23354 | #define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
23355 | #define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 |
23356 | #define SPI_PS_INPUT_CNTL_14__ATTR0_VALID__SHIFT 0x18 |
23357 | #define SPI_PS_INPUT_CNTL_14__ATTR1_VALID__SHIFT 0x19 |
23358 | #define SPI_PS_INPUT_CNTL_14__OFFSET_MASK 0x0000003FL |
23359 | #define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_MASK 0x00000300L |
23360 | #define SPI_PS_INPUT_CNTL_14__FLAT_SHADE_MASK 0x00000400L |
23361 | #define SPI_PS_INPUT_CNTL_14__ROTATE_PC_PTR_MASK 0x00000800L |
23362 | #define SPI_PS_INPUT_CNTL_14__PRIM_ATTR_MASK 0x00001000L |
23363 | #define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_MASK 0x00020000L |
23364 | #define SPI_PS_INPUT_CNTL_14__DUP_MASK 0x00040000L |
23365 | #define SPI_PS_INPUT_CNTL_14__FP16_INTERP_MODE_MASK 0x00080000L |
23366 | #define SPI_PS_INPUT_CNTL_14__USE_DEFAULT_ATTR1_MASK 0x00100000L |
23367 | #define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
23368 | #define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L |
23369 | #define SPI_PS_INPUT_CNTL_14__ATTR0_VALID_MASK 0x01000000L |
23370 | #define SPI_PS_INPUT_CNTL_14__ATTR1_VALID_MASK 0x02000000L |
23371 | //SPI_PS_INPUT_CNTL_15 |
23372 | #define SPI_PS_INPUT_CNTL_15__OFFSET__SHIFT 0x0 |
23373 | #define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL__SHIFT 0x8 |
23374 | #define SPI_PS_INPUT_CNTL_15__FLAT_SHADE__SHIFT 0xa |
23375 | #define SPI_PS_INPUT_CNTL_15__ROTATE_PC_PTR__SHIFT 0xb |
23376 | #define SPI_PS_INPUT_CNTL_15__PRIM_ATTR__SHIFT 0xc |
23377 | #define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX__SHIFT 0x11 |
23378 | #define SPI_PS_INPUT_CNTL_15__DUP__SHIFT 0x12 |
23379 | #define SPI_PS_INPUT_CNTL_15__FP16_INTERP_MODE__SHIFT 0x13 |
23380 | #define SPI_PS_INPUT_CNTL_15__USE_DEFAULT_ATTR1__SHIFT 0x14 |
23381 | #define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
23382 | #define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 |
23383 | #define SPI_PS_INPUT_CNTL_15__ATTR0_VALID__SHIFT 0x18 |
23384 | #define SPI_PS_INPUT_CNTL_15__ATTR1_VALID__SHIFT 0x19 |
23385 | #define SPI_PS_INPUT_CNTL_15__OFFSET_MASK 0x0000003FL |
23386 | #define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_MASK 0x00000300L |
23387 | #define SPI_PS_INPUT_CNTL_15__FLAT_SHADE_MASK 0x00000400L |
23388 | #define SPI_PS_INPUT_CNTL_15__ROTATE_PC_PTR_MASK 0x00000800L |
23389 | #define SPI_PS_INPUT_CNTL_15__PRIM_ATTR_MASK 0x00001000L |
23390 | #define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_MASK 0x00020000L |
23391 | #define SPI_PS_INPUT_CNTL_15__DUP_MASK 0x00040000L |
23392 | #define SPI_PS_INPUT_CNTL_15__FP16_INTERP_MODE_MASK 0x00080000L |
23393 | #define SPI_PS_INPUT_CNTL_15__USE_DEFAULT_ATTR1_MASK 0x00100000L |
23394 | #define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
23395 | #define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L |
23396 | #define SPI_PS_INPUT_CNTL_15__ATTR0_VALID_MASK 0x01000000L |
23397 | #define SPI_PS_INPUT_CNTL_15__ATTR1_VALID_MASK 0x02000000L |
23398 | //SPI_PS_INPUT_CNTL_16 |
23399 | #define SPI_PS_INPUT_CNTL_16__OFFSET__SHIFT 0x0 |
23400 | #define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL__SHIFT 0x8 |
23401 | #define SPI_PS_INPUT_CNTL_16__FLAT_SHADE__SHIFT 0xa |
23402 | #define SPI_PS_INPUT_CNTL_16__ROTATE_PC_PTR__SHIFT 0xb |
23403 | #define SPI_PS_INPUT_CNTL_16__PRIM_ATTR__SHIFT 0xc |
23404 | #define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX__SHIFT 0x11 |
23405 | #define SPI_PS_INPUT_CNTL_16__DUP__SHIFT 0x12 |
23406 | #define SPI_PS_INPUT_CNTL_16__FP16_INTERP_MODE__SHIFT 0x13 |
23407 | #define SPI_PS_INPUT_CNTL_16__USE_DEFAULT_ATTR1__SHIFT 0x14 |
23408 | #define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
23409 | #define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 |
23410 | #define SPI_PS_INPUT_CNTL_16__ATTR0_VALID__SHIFT 0x18 |
23411 | #define SPI_PS_INPUT_CNTL_16__ATTR1_VALID__SHIFT 0x19 |
23412 | #define SPI_PS_INPUT_CNTL_16__OFFSET_MASK 0x0000003FL |
23413 | #define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_MASK 0x00000300L |
23414 | #define SPI_PS_INPUT_CNTL_16__FLAT_SHADE_MASK 0x00000400L |
23415 | #define SPI_PS_INPUT_CNTL_16__ROTATE_PC_PTR_MASK 0x00000800L |
23416 | #define SPI_PS_INPUT_CNTL_16__PRIM_ATTR_MASK 0x00001000L |
23417 | #define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_MASK 0x00020000L |
23418 | #define SPI_PS_INPUT_CNTL_16__DUP_MASK 0x00040000L |
23419 | #define SPI_PS_INPUT_CNTL_16__FP16_INTERP_MODE_MASK 0x00080000L |
23420 | #define SPI_PS_INPUT_CNTL_16__USE_DEFAULT_ATTR1_MASK 0x00100000L |
23421 | #define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
23422 | #define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L |
23423 | #define SPI_PS_INPUT_CNTL_16__ATTR0_VALID_MASK 0x01000000L |
23424 | #define SPI_PS_INPUT_CNTL_16__ATTR1_VALID_MASK 0x02000000L |
23425 | //SPI_PS_INPUT_CNTL_17 |
23426 | #define SPI_PS_INPUT_CNTL_17__OFFSET__SHIFT 0x0 |
23427 | #define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL__SHIFT 0x8 |
23428 | #define SPI_PS_INPUT_CNTL_17__FLAT_SHADE__SHIFT 0xa |
23429 | #define SPI_PS_INPUT_CNTL_17__ROTATE_PC_PTR__SHIFT 0xb |
23430 | #define SPI_PS_INPUT_CNTL_17__PRIM_ATTR__SHIFT 0xc |
23431 | #define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX__SHIFT 0x11 |
23432 | #define SPI_PS_INPUT_CNTL_17__DUP__SHIFT 0x12 |
23433 | #define SPI_PS_INPUT_CNTL_17__FP16_INTERP_MODE__SHIFT 0x13 |
23434 | #define SPI_PS_INPUT_CNTL_17__USE_DEFAULT_ATTR1__SHIFT 0x14 |
23435 | #define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
23436 | #define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 |
23437 | #define SPI_PS_INPUT_CNTL_17__ATTR0_VALID__SHIFT 0x18 |
23438 | #define SPI_PS_INPUT_CNTL_17__ATTR1_VALID__SHIFT 0x19 |
23439 | #define SPI_PS_INPUT_CNTL_17__OFFSET_MASK 0x0000003FL |
23440 | #define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_MASK 0x00000300L |
23441 | #define SPI_PS_INPUT_CNTL_17__FLAT_SHADE_MASK 0x00000400L |
23442 | #define SPI_PS_INPUT_CNTL_17__ROTATE_PC_PTR_MASK 0x00000800L |
23443 | #define SPI_PS_INPUT_CNTL_17__PRIM_ATTR_MASK 0x00001000L |
23444 | #define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_MASK 0x00020000L |
23445 | #define SPI_PS_INPUT_CNTL_17__DUP_MASK 0x00040000L |
23446 | #define SPI_PS_INPUT_CNTL_17__FP16_INTERP_MODE_MASK 0x00080000L |
23447 | #define SPI_PS_INPUT_CNTL_17__USE_DEFAULT_ATTR1_MASK 0x00100000L |
23448 | #define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
23449 | #define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L |
23450 | #define SPI_PS_INPUT_CNTL_17__ATTR0_VALID_MASK 0x01000000L |
23451 | #define SPI_PS_INPUT_CNTL_17__ATTR1_VALID_MASK 0x02000000L |
23452 | //SPI_PS_INPUT_CNTL_18 |
23453 | #define SPI_PS_INPUT_CNTL_18__OFFSET__SHIFT 0x0 |
23454 | #define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL__SHIFT 0x8 |
23455 | #define SPI_PS_INPUT_CNTL_18__FLAT_SHADE__SHIFT 0xa |
23456 | #define SPI_PS_INPUT_CNTL_18__ROTATE_PC_PTR__SHIFT 0xb |
23457 | #define SPI_PS_INPUT_CNTL_18__PRIM_ATTR__SHIFT 0xc |
23458 | #define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX__SHIFT 0x11 |
23459 | #define SPI_PS_INPUT_CNTL_18__DUP__SHIFT 0x12 |
23460 | #define SPI_PS_INPUT_CNTL_18__FP16_INTERP_MODE__SHIFT 0x13 |
23461 | #define SPI_PS_INPUT_CNTL_18__USE_DEFAULT_ATTR1__SHIFT 0x14 |
23462 | #define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
23463 | #define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 |
23464 | #define SPI_PS_INPUT_CNTL_18__ATTR0_VALID__SHIFT 0x18 |
23465 | #define SPI_PS_INPUT_CNTL_18__ATTR1_VALID__SHIFT 0x19 |
23466 | #define SPI_PS_INPUT_CNTL_18__OFFSET_MASK 0x0000003FL |
23467 | #define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_MASK 0x00000300L |
23468 | #define SPI_PS_INPUT_CNTL_18__FLAT_SHADE_MASK 0x00000400L |
23469 | #define SPI_PS_INPUT_CNTL_18__ROTATE_PC_PTR_MASK 0x00000800L |
23470 | #define SPI_PS_INPUT_CNTL_18__PRIM_ATTR_MASK 0x00001000L |
23471 | #define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_MASK 0x00020000L |
23472 | #define SPI_PS_INPUT_CNTL_18__DUP_MASK 0x00040000L |
23473 | #define SPI_PS_INPUT_CNTL_18__FP16_INTERP_MODE_MASK 0x00080000L |
23474 | #define SPI_PS_INPUT_CNTL_18__USE_DEFAULT_ATTR1_MASK 0x00100000L |
23475 | #define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
23476 | #define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L |
23477 | #define SPI_PS_INPUT_CNTL_18__ATTR0_VALID_MASK 0x01000000L |
23478 | #define SPI_PS_INPUT_CNTL_18__ATTR1_VALID_MASK 0x02000000L |
23479 | //SPI_PS_INPUT_CNTL_19 |
23480 | #define SPI_PS_INPUT_CNTL_19__OFFSET__SHIFT 0x0 |
23481 | #define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL__SHIFT 0x8 |
23482 | #define SPI_PS_INPUT_CNTL_19__FLAT_SHADE__SHIFT 0xa |
23483 | #define SPI_PS_INPUT_CNTL_19__ROTATE_PC_PTR__SHIFT 0xb |
23484 | #define SPI_PS_INPUT_CNTL_19__PRIM_ATTR__SHIFT 0xc |
23485 | #define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX__SHIFT 0x11 |
23486 | #define SPI_PS_INPUT_CNTL_19__DUP__SHIFT 0x12 |
23487 | #define SPI_PS_INPUT_CNTL_19__FP16_INTERP_MODE__SHIFT 0x13 |
23488 | #define SPI_PS_INPUT_CNTL_19__USE_DEFAULT_ATTR1__SHIFT 0x14 |
23489 | #define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
23490 | #define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 |
23491 | #define SPI_PS_INPUT_CNTL_19__ATTR0_VALID__SHIFT 0x18 |
23492 | #define SPI_PS_INPUT_CNTL_19__ATTR1_VALID__SHIFT 0x19 |
23493 | #define SPI_PS_INPUT_CNTL_19__OFFSET_MASK 0x0000003FL |
23494 | #define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_MASK 0x00000300L |
23495 | #define SPI_PS_INPUT_CNTL_19__FLAT_SHADE_MASK 0x00000400L |
23496 | #define SPI_PS_INPUT_CNTL_19__ROTATE_PC_PTR_MASK 0x00000800L |
23497 | #define SPI_PS_INPUT_CNTL_19__PRIM_ATTR_MASK 0x00001000L |
23498 | #define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_MASK 0x00020000L |
23499 | #define SPI_PS_INPUT_CNTL_19__DUP_MASK 0x00040000L |
23500 | #define SPI_PS_INPUT_CNTL_19__FP16_INTERP_MODE_MASK 0x00080000L |
23501 | #define SPI_PS_INPUT_CNTL_19__USE_DEFAULT_ATTR1_MASK 0x00100000L |
23502 | #define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
23503 | #define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L |
23504 | #define SPI_PS_INPUT_CNTL_19__ATTR0_VALID_MASK 0x01000000L |
23505 | #define SPI_PS_INPUT_CNTL_19__ATTR1_VALID_MASK 0x02000000L |
23506 | //SPI_PS_INPUT_CNTL_20 |
23507 | #define SPI_PS_INPUT_CNTL_20__OFFSET__SHIFT 0x0 |
23508 | #define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL__SHIFT 0x8 |
23509 | #define SPI_PS_INPUT_CNTL_20__FLAT_SHADE__SHIFT 0xa |
23510 | #define SPI_PS_INPUT_CNTL_20__ROTATE_PC_PTR__SHIFT 0xb |
23511 | #define SPI_PS_INPUT_CNTL_20__PRIM_ATTR__SHIFT 0xc |
23512 | #define SPI_PS_INPUT_CNTL_20__DUP__SHIFT 0x12 |
23513 | #define SPI_PS_INPUT_CNTL_20__FP16_INTERP_MODE__SHIFT 0x13 |
23514 | #define SPI_PS_INPUT_CNTL_20__USE_DEFAULT_ATTR1__SHIFT 0x14 |
23515 | #define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
23516 | #define SPI_PS_INPUT_CNTL_20__ATTR0_VALID__SHIFT 0x18 |
23517 | #define SPI_PS_INPUT_CNTL_20__ATTR1_VALID__SHIFT 0x19 |
23518 | #define SPI_PS_INPUT_CNTL_20__OFFSET_MASK 0x0000003FL |
23519 | #define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_MASK 0x00000300L |
23520 | #define SPI_PS_INPUT_CNTL_20__FLAT_SHADE_MASK 0x00000400L |
23521 | #define SPI_PS_INPUT_CNTL_20__ROTATE_PC_PTR_MASK 0x00000800L |
23522 | #define SPI_PS_INPUT_CNTL_20__PRIM_ATTR_MASK 0x00001000L |
23523 | #define SPI_PS_INPUT_CNTL_20__DUP_MASK 0x00040000L |
23524 | #define SPI_PS_INPUT_CNTL_20__FP16_INTERP_MODE_MASK 0x00080000L |
23525 | #define SPI_PS_INPUT_CNTL_20__USE_DEFAULT_ATTR1_MASK 0x00100000L |
23526 | #define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
23527 | #define SPI_PS_INPUT_CNTL_20__ATTR0_VALID_MASK 0x01000000L |
23528 | #define SPI_PS_INPUT_CNTL_20__ATTR1_VALID_MASK 0x02000000L |
23529 | //SPI_PS_INPUT_CNTL_21 |
23530 | #define SPI_PS_INPUT_CNTL_21__OFFSET__SHIFT 0x0 |
23531 | #define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL__SHIFT 0x8 |
23532 | #define SPI_PS_INPUT_CNTL_21__FLAT_SHADE__SHIFT 0xa |
23533 | #define SPI_PS_INPUT_CNTL_21__ROTATE_PC_PTR__SHIFT 0xb |
23534 | #define SPI_PS_INPUT_CNTL_21__PRIM_ATTR__SHIFT 0xc |
23535 | #define SPI_PS_INPUT_CNTL_21__DUP__SHIFT 0x12 |
23536 | #define SPI_PS_INPUT_CNTL_21__FP16_INTERP_MODE__SHIFT 0x13 |
23537 | #define SPI_PS_INPUT_CNTL_21__USE_DEFAULT_ATTR1__SHIFT 0x14 |
23538 | #define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
23539 | #define SPI_PS_INPUT_CNTL_21__ATTR0_VALID__SHIFT 0x18 |
23540 | #define SPI_PS_INPUT_CNTL_21__ATTR1_VALID__SHIFT 0x19 |
23541 | #define SPI_PS_INPUT_CNTL_21__OFFSET_MASK 0x0000003FL |
23542 | #define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_MASK 0x00000300L |
23543 | #define SPI_PS_INPUT_CNTL_21__FLAT_SHADE_MASK 0x00000400L |
23544 | #define SPI_PS_INPUT_CNTL_21__ROTATE_PC_PTR_MASK 0x00000800L |
23545 | #define SPI_PS_INPUT_CNTL_21__PRIM_ATTR_MASK 0x00001000L |
23546 | #define SPI_PS_INPUT_CNTL_21__DUP_MASK 0x00040000L |
23547 | #define SPI_PS_INPUT_CNTL_21__FP16_INTERP_MODE_MASK 0x00080000L |
23548 | #define SPI_PS_INPUT_CNTL_21__USE_DEFAULT_ATTR1_MASK 0x00100000L |
23549 | #define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
23550 | #define SPI_PS_INPUT_CNTL_21__ATTR0_VALID_MASK 0x01000000L |
23551 | #define SPI_PS_INPUT_CNTL_21__ATTR1_VALID_MASK 0x02000000L |
23552 | //SPI_PS_INPUT_CNTL_22 |
23553 | #define SPI_PS_INPUT_CNTL_22__OFFSET__SHIFT 0x0 |
23554 | #define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL__SHIFT 0x8 |
23555 | #define SPI_PS_INPUT_CNTL_22__FLAT_SHADE__SHIFT 0xa |
23556 | #define SPI_PS_INPUT_CNTL_22__ROTATE_PC_PTR__SHIFT 0xb |
23557 | #define SPI_PS_INPUT_CNTL_22__PRIM_ATTR__SHIFT 0xc |
23558 | #define SPI_PS_INPUT_CNTL_22__DUP__SHIFT 0x12 |
23559 | #define SPI_PS_INPUT_CNTL_22__FP16_INTERP_MODE__SHIFT 0x13 |
23560 | #define SPI_PS_INPUT_CNTL_22__USE_DEFAULT_ATTR1__SHIFT 0x14 |
23561 | #define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
23562 | #define SPI_PS_INPUT_CNTL_22__ATTR0_VALID__SHIFT 0x18 |
23563 | #define SPI_PS_INPUT_CNTL_22__ATTR1_VALID__SHIFT 0x19 |
23564 | #define SPI_PS_INPUT_CNTL_22__OFFSET_MASK 0x0000003FL |
23565 | #define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_MASK 0x00000300L |
23566 | #define SPI_PS_INPUT_CNTL_22__FLAT_SHADE_MASK 0x00000400L |
23567 | #define SPI_PS_INPUT_CNTL_22__ROTATE_PC_PTR_MASK 0x00000800L |
23568 | #define SPI_PS_INPUT_CNTL_22__PRIM_ATTR_MASK 0x00001000L |
23569 | #define SPI_PS_INPUT_CNTL_22__DUP_MASK 0x00040000L |
23570 | #define SPI_PS_INPUT_CNTL_22__FP16_INTERP_MODE_MASK 0x00080000L |
23571 | #define SPI_PS_INPUT_CNTL_22__USE_DEFAULT_ATTR1_MASK 0x00100000L |
23572 | #define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
23573 | #define SPI_PS_INPUT_CNTL_22__ATTR0_VALID_MASK 0x01000000L |
23574 | #define SPI_PS_INPUT_CNTL_22__ATTR1_VALID_MASK 0x02000000L |
23575 | //SPI_PS_INPUT_CNTL_23 |
23576 | #define SPI_PS_INPUT_CNTL_23__OFFSET__SHIFT 0x0 |
23577 | #define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL__SHIFT 0x8 |
23578 | #define SPI_PS_INPUT_CNTL_23__FLAT_SHADE__SHIFT 0xa |
23579 | #define SPI_PS_INPUT_CNTL_23__ROTATE_PC_PTR__SHIFT 0xb |
23580 | #define SPI_PS_INPUT_CNTL_23__PRIM_ATTR__SHIFT 0xc |
23581 | #define SPI_PS_INPUT_CNTL_23__DUP__SHIFT 0x12 |
23582 | #define SPI_PS_INPUT_CNTL_23__FP16_INTERP_MODE__SHIFT 0x13 |
23583 | #define SPI_PS_INPUT_CNTL_23__USE_DEFAULT_ATTR1__SHIFT 0x14 |
23584 | #define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
23585 | #define SPI_PS_INPUT_CNTL_23__ATTR0_VALID__SHIFT 0x18 |
23586 | #define SPI_PS_INPUT_CNTL_23__ATTR1_VALID__SHIFT 0x19 |
23587 | #define SPI_PS_INPUT_CNTL_23__OFFSET_MASK 0x0000003FL |
23588 | #define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_MASK 0x00000300L |
23589 | #define SPI_PS_INPUT_CNTL_23__FLAT_SHADE_MASK 0x00000400L |
23590 | #define SPI_PS_INPUT_CNTL_23__ROTATE_PC_PTR_MASK 0x00000800L |
23591 | #define SPI_PS_INPUT_CNTL_23__PRIM_ATTR_MASK 0x00001000L |
23592 | #define SPI_PS_INPUT_CNTL_23__DUP_MASK 0x00040000L |
23593 | #define SPI_PS_INPUT_CNTL_23__FP16_INTERP_MODE_MASK 0x00080000L |
23594 | #define SPI_PS_INPUT_CNTL_23__USE_DEFAULT_ATTR1_MASK 0x00100000L |
23595 | #define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
23596 | #define SPI_PS_INPUT_CNTL_23__ATTR0_VALID_MASK 0x01000000L |
23597 | #define SPI_PS_INPUT_CNTL_23__ATTR1_VALID_MASK 0x02000000L |
23598 | //SPI_PS_INPUT_CNTL_24 |
23599 | #define SPI_PS_INPUT_CNTL_24__OFFSET__SHIFT 0x0 |
23600 | #define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL__SHIFT 0x8 |
23601 | #define SPI_PS_INPUT_CNTL_24__FLAT_SHADE__SHIFT 0xa |
23602 | #define SPI_PS_INPUT_CNTL_24__ROTATE_PC_PTR__SHIFT 0xb |
23603 | #define SPI_PS_INPUT_CNTL_24__PRIM_ATTR__SHIFT 0xc |
23604 | #define SPI_PS_INPUT_CNTL_24__DUP__SHIFT 0x12 |
23605 | #define SPI_PS_INPUT_CNTL_24__FP16_INTERP_MODE__SHIFT 0x13 |
23606 | #define SPI_PS_INPUT_CNTL_24__USE_DEFAULT_ATTR1__SHIFT 0x14 |
23607 | #define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
23608 | #define SPI_PS_INPUT_CNTL_24__ATTR0_VALID__SHIFT 0x18 |
23609 | #define SPI_PS_INPUT_CNTL_24__ATTR1_VALID__SHIFT 0x19 |
23610 | #define SPI_PS_INPUT_CNTL_24__OFFSET_MASK 0x0000003FL |
23611 | #define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_MASK 0x00000300L |
23612 | #define SPI_PS_INPUT_CNTL_24__FLAT_SHADE_MASK 0x00000400L |
23613 | #define SPI_PS_INPUT_CNTL_24__ROTATE_PC_PTR_MASK 0x00000800L |
23614 | #define SPI_PS_INPUT_CNTL_24__PRIM_ATTR_MASK 0x00001000L |
23615 | #define SPI_PS_INPUT_CNTL_24__DUP_MASK 0x00040000L |
23616 | #define SPI_PS_INPUT_CNTL_24__FP16_INTERP_MODE_MASK 0x00080000L |
23617 | #define SPI_PS_INPUT_CNTL_24__USE_DEFAULT_ATTR1_MASK 0x00100000L |
23618 | #define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
23619 | #define SPI_PS_INPUT_CNTL_24__ATTR0_VALID_MASK 0x01000000L |
23620 | #define SPI_PS_INPUT_CNTL_24__ATTR1_VALID_MASK 0x02000000L |
23621 | //SPI_PS_INPUT_CNTL_25 |
23622 | #define SPI_PS_INPUT_CNTL_25__OFFSET__SHIFT 0x0 |
23623 | #define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL__SHIFT 0x8 |
23624 | #define SPI_PS_INPUT_CNTL_25__FLAT_SHADE__SHIFT 0xa |
23625 | #define SPI_PS_INPUT_CNTL_25__ROTATE_PC_PTR__SHIFT 0xb |
23626 | #define SPI_PS_INPUT_CNTL_25__PRIM_ATTR__SHIFT 0xc |
23627 | #define SPI_PS_INPUT_CNTL_25__DUP__SHIFT 0x12 |
23628 | #define SPI_PS_INPUT_CNTL_25__FP16_INTERP_MODE__SHIFT 0x13 |
23629 | #define SPI_PS_INPUT_CNTL_25__USE_DEFAULT_ATTR1__SHIFT 0x14 |
23630 | #define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
23631 | #define SPI_PS_INPUT_CNTL_25__ATTR0_VALID__SHIFT 0x18 |
23632 | #define SPI_PS_INPUT_CNTL_25__ATTR1_VALID__SHIFT 0x19 |
23633 | #define SPI_PS_INPUT_CNTL_25__OFFSET_MASK 0x0000003FL |
23634 | #define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_MASK 0x00000300L |
23635 | #define SPI_PS_INPUT_CNTL_25__FLAT_SHADE_MASK 0x00000400L |
23636 | #define SPI_PS_INPUT_CNTL_25__ROTATE_PC_PTR_MASK 0x00000800L |
23637 | #define SPI_PS_INPUT_CNTL_25__PRIM_ATTR_MASK 0x00001000L |
23638 | #define SPI_PS_INPUT_CNTL_25__DUP_MASK 0x00040000L |
23639 | #define SPI_PS_INPUT_CNTL_25__FP16_INTERP_MODE_MASK 0x00080000L |
23640 | #define SPI_PS_INPUT_CNTL_25__USE_DEFAULT_ATTR1_MASK 0x00100000L |
23641 | #define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
23642 | #define SPI_PS_INPUT_CNTL_25__ATTR0_VALID_MASK 0x01000000L |
23643 | #define SPI_PS_INPUT_CNTL_25__ATTR1_VALID_MASK 0x02000000L |
23644 | //SPI_PS_INPUT_CNTL_26 |
23645 | #define SPI_PS_INPUT_CNTL_26__OFFSET__SHIFT 0x0 |
23646 | #define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL__SHIFT 0x8 |
23647 | #define SPI_PS_INPUT_CNTL_26__FLAT_SHADE__SHIFT 0xa |
23648 | #define SPI_PS_INPUT_CNTL_26__ROTATE_PC_PTR__SHIFT 0xb |
23649 | #define SPI_PS_INPUT_CNTL_26__PRIM_ATTR__SHIFT 0xc |
23650 | #define SPI_PS_INPUT_CNTL_26__DUP__SHIFT 0x12 |
23651 | #define SPI_PS_INPUT_CNTL_26__FP16_INTERP_MODE__SHIFT 0x13 |
23652 | #define SPI_PS_INPUT_CNTL_26__USE_DEFAULT_ATTR1__SHIFT 0x14 |
23653 | #define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
23654 | #define SPI_PS_INPUT_CNTL_26__ATTR0_VALID__SHIFT 0x18 |
23655 | #define SPI_PS_INPUT_CNTL_26__ATTR1_VALID__SHIFT 0x19 |
23656 | #define SPI_PS_INPUT_CNTL_26__OFFSET_MASK 0x0000003FL |
23657 | #define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_MASK 0x00000300L |
23658 | #define SPI_PS_INPUT_CNTL_26__FLAT_SHADE_MASK 0x00000400L |
23659 | #define SPI_PS_INPUT_CNTL_26__ROTATE_PC_PTR_MASK 0x00000800L |
23660 | #define SPI_PS_INPUT_CNTL_26__PRIM_ATTR_MASK 0x00001000L |
23661 | #define SPI_PS_INPUT_CNTL_26__DUP_MASK 0x00040000L |
23662 | #define SPI_PS_INPUT_CNTL_26__FP16_INTERP_MODE_MASK 0x00080000L |
23663 | #define SPI_PS_INPUT_CNTL_26__USE_DEFAULT_ATTR1_MASK 0x00100000L |
23664 | #define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
23665 | #define SPI_PS_INPUT_CNTL_26__ATTR0_VALID_MASK 0x01000000L |
23666 | #define SPI_PS_INPUT_CNTL_26__ATTR1_VALID_MASK 0x02000000L |
23667 | //SPI_PS_INPUT_CNTL_27 |
23668 | #define SPI_PS_INPUT_CNTL_27__OFFSET__SHIFT 0x0 |
23669 | #define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL__SHIFT 0x8 |
23670 | #define SPI_PS_INPUT_CNTL_27__FLAT_SHADE__SHIFT 0xa |
23671 | #define SPI_PS_INPUT_CNTL_27__ROTATE_PC_PTR__SHIFT 0xb |
23672 | #define SPI_PS_INPUT_CNTL_27__PRIM_ATTR__SHIFT 0xc |
23673 | #define SPI_PS_INPUT_CNTL_27__DUP__SHIFT 0x12 |
23674 | #define SPI_PS_INPUT_CNTL_27__FP16_INTERP_MODE__SHIFT 0x13 |
23675 | #define SPI_PS_INPUT_CNTL_27__USE_DEFAULT_ATTR1__SHIFT 0x14 |
23676 | #define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
23677 | #define SPI_PS_INPUT_CNTL_27__ATTR0_VALID__SHIFT 0x18 |
23678 | #define SPI_PS_INPUT_CNTL_27__ATTR1_VALID__SHIFT 0x19 |
23679 | #define SPI_PS_INPUT_CNTL_27__OFFSET_MASK 0x0000003FL |
23680 | #define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_MASK 0x00000300L |
23681 | #define SPI_PS_INPUT_CNTL_27__FLAT_SHADE_MASK 0x00000400L |
23682 | #define SPI_PS_INPUT_CNTL_27__ROTATE_PC_PTR_MASK 0x00000800L |
23683 | #define SPI_PS_INPUT_CNTL_27__PRIM_ATTR_MASK 0x00001000L |
23684 | #define SPI_PS_INPUT_CNTL_27__DUP_MASK 0x00040000L |
23685 | #define SPI_PS_INPUT_CNTL_27__FP16_INTERP_MODE_MASK 0x00080000L |
23686 | #define SPI_PS_INPUT_CNTL_27__USE_DEFAULT_ATTR1_MASK 0x00100000L |
23687 | #define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
23688 | #define SPI_PS_INPUT_CNTL_27__ATTR0_VALID_MASK 0x01000000L |
23689 | #define SPI_PS_INPUT_CNTL_27__ATTR1_VALID_MASK 0x02000000L |
23690 | //SPI_PS_INPUT_CNTL_28 |
23691 | #define SPI_PS_INPUT_CNTL_28__OFFSET__SHIFT 0x0 |
23692 | #define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL__SHIFT 0x8 |
23693 | #define SPI_PS_INPUT_CNTL_28__FLAT_SHADE__SHIFT 0xa |
23694 | #define SPI_PS_INPUT_CNTL_28__ROTATE_PC_PTR__SHIFT 0xb |
23695 | #define SPI_PS_INPUT_CNTL_28__PRIM_ATTR__SHIFT 0xc |
23696 | #define SPI_PS_INPUT_CNTL_28__DUP__SHIFT 0x12 |
23697 | #define SPI_PS_INPUT_CNTL_28__FP16_INTERP_MODE__SHIFT 0x13 |
23698 | #define SPI_PS_INPUT_CNTL_28__USE_DEFAULT_ATTR1__SHIFT 0x14 |
23699 | #define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
23700 | #define SPI_PS_INPUT_CNTL_28__ATTR0_VALID__SHIFT 0x18 |
23701 | #define SPI_PS_INPUT_CNTL_28__ATTR1_VALID__SHIFT 0x19 |
23702 | #define SPI_PS_INPUT_CNTL_28__OFFSET_MASK 0x0000003FL |
23703 | #define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_MASK 0x00000300L |
23704 | #define SPI_PS_INPUT_CNTL_28__FLAT_SHADE_MASK 0x00000400L |
23705 | #define SPI_PS_INPUT_CNTL_28__ROTATE_PC_PTR_MASK 0x00000800L |
23706 | #define SPI_PS_INPUT_CNTL_28__PRIM_ATTR_MASK 0x00001000L |
23707 | #define SPI_PS_INPUT_CNTL_28__DUP_MASK 0x00040000L |
23708 | #define SPI_PS_INPUT_CNTL_28__FP16_INTERP_MODE_MASK 0x00080000L |
23709 | #define SPI_PS_INPUT_CNTL_28__USE_DEFAULT_ATTR1_MASK 0x00100000L |
23710 | #define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
23711 | #define SPI_PS_INPUT_CNTL_28__ATTR0_VALID_MASK 0x01000000L |
23712 | #define SPI_PS_INPUT_CNTL_28__ATTR1_VALID_MASK 0x02000000L |
23713 | //SPI_PS_INPUT_CNTL_29 |
23714 | #define SPI_PS_INPUT_CNTL_29__OFFSET__SHIFT 0x0 |
23715 | #define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL__SHIFT 0x8 |
23716 | #define SPI_PS_INPUT_CNTL_29__FLAT_SHADE__SHIFT 0xa |
23717 | #define SPI_PS_INPUT_CNTL_29__ROTATE_PC_PTR__SHIFT 0xb |
23718 | #define SPI_PS_INPUT_CNTL_29__PRIM_ATTR__SHIFT 0xc |
23719 | #define SPI_PS_INPUT_CNTL_29__DUP__SHIFT 0x12 |
23720 | #define SPI_PS_INPUT_CNTL_29__FP16_INTERP_MODE__SHIFT 0x13 |
23721 | #define SPI_PS_INPUT_CNTL_29__USE_DEFAULT_ATTR1__SHIFT 0x14 |
23722 | #define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
23723 | #define SPI_PS_INPUT_CNTL_29__ATTR0_VALID__SHIFT 0x18 |
23724 | #define SPI_PS_INPUT_CNTL_29__ATTR1_VALID__SHIFT 0x19 |
23725 | #define SPI_PS_INPUT_CNTL_29__OFFSET_MASK 0x0000003FL |
23726 | #define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_MASK 0x00000300L |
23727 | #define SPI_PS_INPUT_CNTL_29__FLAT_SHADE_MASK 0x00000400L |
23728 | #define SPI_PS_INPUT_CNTL_29__ROTATE_PC_PTR_MASK 0x00000800L |
23729 | #define SPI_PS_INPUT_CNTL_29__PRIM_ATTR_MASK 0x00001000L |
23730 | #define SPI_PS_INPUT_CNTL_29__DUP_MASK 0x00040000L |
23731 | #define SPI_PS_INPUT_CNTL_29__FP16_INTERP_MODE_MASK 0x00080000L |
23732 | #define SPI_PS_INPUT_CNTL_29__USE_DEFAULT_ATTR1_MASK 0x00100000L |
23733 | #define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
23734 | #define SPI_PS_INPUT_CNTL_29__ATTR0_VALID_MASK 0x01000000L |
23735 | #define SPI_PS_INPUT_CNTL_29__ATTR1_VALID_MASK 0x02000000L |
23736 | //SPI_PS_INPUT_CNTL_30 |
23737 | #define SPI_PS_INPUT_CNTL_30__OFFSET__SHIFT 0x0 |
23738 | #define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL__SHIFT 0x8 |
23739 | #define SPI_PS_INPUT_CNTL_30__FLAT_SHADE__SHIFT 0xa |
23740 | #define SPI_PS_INPUT_CNTL_30__ROTATE_PC_PTR__SHIFT 0xb |
23741 | #define SPI_PS_INPUT_CNTL_30__PRIM_ATTR__SHIFT 0xc |
23742 | #define SPI_PS_INPUT_CNTL_30__DUP__SHIFT 0x12 |
23743 | #define SPI_PS_INPUT_CNTL_30__FP16_INTERP_MODE__SHIFT 0x13 |
23744 | #define SPI_PS_INPUT_CNTL_30__USE_DEFAULT_ATTR1__SHIFT 0x14 |
23745 | #define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
23746 | #define SPI_PS_INPUT_CNTL_30__ATTR0_VALID__SHIFT 0x18 |
23747 | #define SPI_PS_INPUT_CNTL_30__ATTR1_VALID__SHIFT 0x19 |
23748 | #define SPI_PS_INPUT_CNTL_30__OFFSET_MASK 0x0000003FL |
23749 | #define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_MASK 0x00000300L |
23750 | #define SPI_PS_INPUT_CNTL_30__FLAT_SHADE_MASK 0x00000400L |
23751 | #define SPI_PS_INPUT_CNTL_30__ROTATE_PC_PTR_MASK 0x00000800L |
23752 | #define SPI_PS_INPUT_CNTL_30__PRIM_ATTR_MASK 0x00001000L |
23753 | #define SPI_PS_INPUT_CNTL_30__DUP_MASK 0x00040000L |
23754 | #define SPI_PS_INPUT_CNTL_30__FP16_INTERP_MODE_MASK 0x00080000L |
23755 | #define SPI_PS_INPUT_CNTL_30__USE_DEFAULT_ATTR1_MASK 0x00100000L |
23756 | #define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
23757 | #define SPI_PS_INPUT_CNTL_30__ATTR0_VALID_MASK 0x01000000L |
23758 | #define SPI_PS_INPUT_CNTL_30__ATTR1_VALID_MASK 0x02000000L |
23759 | //SPI_PS_INPUT_CNTL_31 |
23760 | #define SPI_PS_INPUT_CNTL_31__OFFSET__SHIFT 0x0 |
23761 | #define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL__SHIFT 0x8 |
23762 | #define SPI_PS_INPUT_CNTL_31__FLAT_SHADE__SHIFT 0xa |
23763 | #define SPI_PS_INPUT_CNTL_31__ROTATE_PC_PTR__SHIFT 0xb |
23764 | #define SPI_PS_INPUT_CNTL_31__PRIM_ATTR__SHIFT 0xc |
23765 | #define SPI_PS_INPUT_CNTL_31__DUP__SHIFT 0x12 |
23766 | #define SPI_PS_INPUT_CNTL_31__FP16_INTERP_MODE__SHIFT 0x13 |
23767 | #define SPI_PS_INPUT_CNTL_31__USE_DEFAULT_ATTR1__SHIFT 0x14 |
23768 | #define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_ATTR1__SHIFT 0x15 |
23769 | #define SPI_PS_INPUT_CNTL_31__ATTR0_VALID__SHIFT 0x18 |
23770 | #define SPI_PS_INPUT_CNTL_31__ATTR1_VALID__SHIFT 0x19 |
23771 | #define SPI_PS_INPUT_CNTL_31__OFFSET_MASK 0x0000003FL |
23772 | #define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_MASK 0x00000300L |
23773 | #define SPI_PS_INPUT_CNTL_31__FLAT_SHADE_MASK 0x00000400L |
23774 | #define SPI_PS_INPUT_CNTL_31__ROTATE_PC_PTR_MASK 0x00000800L |
23775 | #define SPI_PS_INPUT_CNTL_31__PRIM_ATTR_MASK 0x00001000L |
23776 | #define SPI_PS_INPUT_CNTL_31__DUP_MASK 0x00040000L |
23777 | #define SPI_PS_INPUT_CNTL_31__FP16_INTERP_MODE_MASK 0x00080000L |
23778 | #define SPI_PS_INPUT_CNTL_31__USE_DEFAULT_ATTR1_MASK 0x00100000L |
23779 | #define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_ATTR1_MASK 0x00600000L |
23780 | #define SPI_PS_INPUT_CNTL_31__ATTR0_VALID_MASK 0x01000000L |
23781 | #define SPI_PS_INPUT_CNTL_31__ATTR1_VALID_MASK 0x02000000L |
23782 | //SPI_VS_OUT_CONFIG |
23783 | #define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT__SHIFT 0x1 |
23784 | #define SPI_VS_OUT_CONFIG__NO_PC_EXPORT__SHIFT 0x7 |
23785 | #define SPI_VS_OUT_CONFIG__PRIM_EXPORT_COUNT__SHIFT 0x8 |
23786 | #define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT_MASK 0x0000003EL |
23787 | #define SPI_VS_OUT_CONFIG__NO_PC_EXPORT_MASK 0x00000080L |
23788 | #define SPI_VS_OUT_CONFIG__PRIM_EXPORT_COUNT_MASK 0x00001F00L |
23789 | //SPI_PS_INPUT_ENA |
23790 | #define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA__SHIFT 0x0 |
23791 | #define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA__SHIFT 0x1 |
23792 | #define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA__SHIFT 0x2 |
23793 | #define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA__SHIFT 0x3 |
23794 | #define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA__SHIFT 0x4 |
23795 | #define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA__SHIFT 0x5 |
23796 | #define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA__SHIFT 0x6 |
23797 | #define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA__SHIFT 0x7 |
23798 | #define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA__SHIFT 0x8 |
23799 | #define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA__SHIFT 0x9 |
23800 | #define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA__SHIFT 0xa |
23801 | #define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA__SHIFT 0xb |
23802 | #define SPI_PS_INPUT_ENA__FRONT_FACE_ENA__SHIFT 0xc |
23803 | #define SPI_PS_INPUT_ENA__ANCILLARY_ENA__SHIFT 0xd |
23804 | #define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA__SHIFT 0xe |
23805 | #define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA__SHIFT 0xf |
23806 | #define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA_MASK 0x00000001L |
23807 | #define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA_MASK 0x00000002L |
23808 | #define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA_MASK 0x00000004L |
23809 | #define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA_MASK 0x00000008L |
23810 | #define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA_MASK 0x00000010L |
23811 | #define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA_MASK 0x00000020L |
23812 | #define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA_MASK 0x00000040L |
23813 | #define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA_MASK 0x00000080L |
23814 | #define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA_MASK 0x00000100L |
23815 | #define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA_MASK 0x00000200L |
23816 | #define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA_MASK 0x00000400L |
23817 | #define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA_MASK 0x00000800L |
23818 | #define SPI_PS_INPUT_ENA__FRONT_FACE_ENA_MASK 0x00001000L |
23819 | #define SPI_PS_INPUT_ENA__ANCILLARY_ENA_MASK 0x00002000L |
23820 | #define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA_MASK 0x00004000L |
23821 | #define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA_MASK 0x00008000L |
23822 | //SPI_PS_INPUT_ADDR |
23823 | #define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA__SHIFT 0x0 |
23824 | #define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA__SHIFT 0x1 |
23825 | #define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA__SHIFT 0x2 |
23826 | #define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA__SHIFT 0x3 |
23827 | #define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA__SHIFT 0x4 |
23828 | #define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA__SHIFT 0x5 |
23829 | #define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA__SHIFT 0x6 |
23830 | #define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA__SHIFT 0x7 |
23831 | #define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA__SHIFT 0x8 |
23832 | #define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA__SHIFT 0x9 |
23833 | #define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA__SHIFT 0xa |
23834 | #define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA__SHIFT 0xb |
23835 | #define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA__SHIFT 0xc |
23836 | #define SPI_PS_INPUT_ADDR__ANCILLARY_ENA__SHIFT 0xd |
23837 | #define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA__SHIFT 0xe |
23838 | #define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA__SHIFT 0xf |
23839 | #define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA_MASK 0x00000001L |
23840 | #define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA_MASK 0x00000002L |
23841 | #define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA_MASK 0x00000004L |
23842 | #define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA_MASK 0x00000008L |
23843 | #define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA_MASK 0x00000010L |
23844 | #define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA_MASK 0x00000020L |
23845 | #define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA_MASK 0x00000040L |
23846 | #define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA_MASK 0x00000080L |
23847 | #define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA_MASK 0x00000100L |
23848 | #define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA_MASK 0x00000200L |
23849 | #define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA_MASK 0x00000400L |
23850 | #define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA_MASK 0x00000800L |
23851 | #define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA_MASK 0x00001000L |
23852 | #define SPI_PS_INPUT_ADDR__ANCILLARY_ENA_MASK 0x00002000L |
23853 | #define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA_MASK 0x00004000L |
23854 | #define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA_MASK 0x00008000L |
23855 | //SPI_INTERP_CONTROL_0 |
23856 | #define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA__SHIFT 0x0 |
23857 | #define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA__SHIFT 0x1 |
23858 | #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X__SHIFT 0x2 |
23859 | #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y__SHIFT 0x5 |
23860 | #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z__SHIFT 0x8 |
23861 | #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W__SHIFT 0xb |
23862 | #define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1__SHIFT 0xe |
23863 | #define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA_MASK 0x00000001L |
23864 | #define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA_MASK 0x00000002L |
23865 | #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X_MASK 0x0000001CL |
23866 | #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y_MASK 0x000000E0L |
23867 | #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z_MASK 0x00000700L |
23868 | #define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W_MASK 0x00003800L |
23869 | #define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1_MASK 0x00004000L |
23870 | //SPI_PS_IN_CONTROL |
23871 | #define SPI_PS_IN_CONTROL__NUM_INTERP__SHIFT 0x0 |
23872 | #define SPI_PS_IN_CONTROL__PARAM_GEN__SHIFT 0x6 |
23873 | #define SPI_PS_IN_CONTROL__OFFCHIP_PARAM_EN__SHIFT 0x7 |
23874 | #define SPI_PS_IN_CONTROL__LATE_PC_DEALLOC__SHIFT 0x8 |
23875 | #define SPI_PS_IN_CONTROL__NUM_PRIM_INTERP__SHIFT 0x9 |
23876 | #define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE__SHIFT 0xe |
23877 | #define SPI_PS_IN_CONTROL__PS_W32_EN__SHIFT 0xf |
23878 | #define SPI_PS_IN_CONTROL__NUM_INTERP_MASK 0x0000003FL |
23879 | #define SPI_PS_IN_CONTROL__PARAM_GEN_MASK 0x00000040L |
23880 | #define SPI_PS_IN_CONTROL__OFFCHIP_PARAM_EN_MASK 0x00000080L |
23881 | #define SPI_PS_IN_CONTROL__LATE_PC_DEALLOC_MASK 0x00000100L |
23882 | #define SPI_PS_IN_CONTROL__NUM_PRIM_INTERP_MASK 0x00003E00L |
23883 | #define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE_MASK 0x00004000L |
23884 | #define SPI_PS_IN_CONTROL__PS_W32_EN_MASK 0x00008000L |
23885 | //SPI_BARYC_CNTL |
23886 | #define SPI_BARYC_CNTL__PERSP_CENTER_CNTL__SHIFT 0x0 |
23887 | #define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL__SHIFT 0x4 |
23888 | #define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL__SHIFT 0x8 |
23889 | #define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL__SHIFT 0xc |
23890 | #define SPI_BARYC_CNTL__POS_FLOAT_LOCATION__SHIFT 0x10 |
23891 | #define SPI_BARYC_CNTL__POS_FLOAT_ULC__SHIFT 0x14 |
23892 | #define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS__SHIFT 0x18 |
23893 | #define SPI_BARYC_CNTL__PERSP_CENTER_CNTL_MASK 0x00000001L |
23894 | #define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL_MASK 0x00000010L |
23895 | #define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL_MASK 0x00000100L |
23896 | #define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL_MASK 0x00001000L |
23897 | #define SPI_BARYC_CNTL__POS_FLOAT_LOCATION_MASK 0x00030000L |
23898 | #define SPI_BARYC_CNTL__POS_FLOAT_ULC_MASK 0x00100000L |
23899 | #define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS_MASK 0x01000000L |
23900 | //SPI_TMPRING_SIZE |
23901 | #define SPI_TMPRING_SIZE__WAVES__SHIFT 0x0 |
23902 | #define SPI_TMPRING_SIZE__WAVESIZE__SHIFT 0xc |
23903 | #define SPI_TMPRING_SIZE__WAVES_MASK 0x00000FFFL |
23904 | #define SPI_TMPRING_SIZE__WAVESIZE_MASK 0x07FFF000L |
23905 | //SPI_GFX_SCRATCH_BASE_LO |
23906 | #define SPI_GFX_SCRATCH_BASE_LO__DATA__SHIFT 0x0 |
23907 | #define SPI_GFX_SCRATCH_BASE_LO__DATA_MASK 0xFFFFFFFFL |
23908 | //SPI_GFX_SCRATCH_BASE_HI |
23909 | #define SPI_GFX_SCRATCH_BASE_HI__DATA__SHIFT 0x0 |
23910 | #define SPI_GFX_SCRATCH_BASE_HI__DATA_MASK 0x000000FFL |
23911 | //SPI_SHADER_IDX_FORMAT |
23912 | #define SPI_SHADER_IDX_FORMAT__IDX0_EXPORT_FORMAT__SHIFT 0x0 |
23913 | #define SPI_SHADER_IDX_FORMAT__IDX0_EXPORT_FORMAT_MASK 0x0000000FL |
23914 | //SPI_SHADER_POS_FORMAT |
23915 | #define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT__SHIFT 0x0 |
23916 | #define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT__SHIFT 0x4 |
23917 | #define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT__SHIFT 0x8 |
23918 | #define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT__SHIFT 0xc |
23919 | #define SPI_SHADER_POS_FORMAT__POS4_EXPORT_FORMAT__SHIFT 0x10 |
23920 | #define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT_MASK 0x0000000FL |
23921 | #define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT_MASK 0x000000F0L |
23922 | #define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT_MASK 0x00000F00L |
23923 | #define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT_MASK 0x0000F000L |
23924 | #define SPI_SHADER_POS_FORMAT__POS4_EXPORT_FORMAT_MASK 0x000F0000L |
23925 | //SPI_SHADER_Z_FORMAT |
23926 | #define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT__SHIFT 0x0 |
23927 | #define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT_MASK 0x0000000FL |
23928 | //SPI_SHADER_COL_FORMAT |
23929 | #define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT__SHIFT 0x0 |
23930 | #define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT__SHIFT 0x4 |
23931 | #define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT__SHIFT 0x8 |
23932 | #define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT__SHIFT 0xc |
23933 | #define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT__SHIFT 0x10 |
23934 | #define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT__SHIFT 0x14 |
23935 | #define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT__SHIFT 0x18 |
23936 | #define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT__SHIFT 0x1c |
23937 | #define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT_MASK 0x0000000FL |
23938 | #define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT_MASK 0x000000F0L |
23939 | #define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT_MASK 0x00000F00L |
23940 | #define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT_MASK 0x0000F000L |
23941 | #define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT_MASK 0x000F0000L |
23942 | #define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT_MASK 0x00F00000L |
23943 | #define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT_MASK 0x0F000000L |
23944 | #define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT_MASK 0xF0000000L |
23945 | //SX_PS_DOWNCONVERT_CONTROL |
23946 | #define SX_PS_DOWNCONVERT_CONTROL__MRT0_FMT_MAPPING_DISABLE__SHIFT 0x0 |
23947 | #define SX_PS_DOWNCONVERT_CONTROL__MRT1_FMT_MAPPING_DISABLE__SHIFT 0x1 |
23948 | #define SX_PS_DOWNCONVERT_CONTROL__MRT2_FMT_MAPPING_DISABLE__SHIFT 0x2 |
23949 | #define SX_PS_DOWNCONVERT_CONTROL__MRT3_FMT_MAPPING_DISABLE__SHIFT 0x3 |
23950 | #define SX_PS_DOWNCONVERT_CONTROL__MRT4_FMT_MAPPING_DISABLE__SHIFT 0x4 |
23951 | #define SX_PS_DOWNCONVERT_CONTROL__MRT5_FMT_MAPPING_DISABLE__SHIFT 0x5 |
23952 | #define SX_PS_DOWNCONVERT_CONTROL__MRT6_FMT_MAPPING_DISABLE__SHIFT 0x6 |
23953 | #define SX_PS_DOWNCONVERT_CONTROL__MRT7_FMT_MAPPING_DISABLE__SHIFT 0x7 |
23954 | #define SX_PS_DOWNCONVERT_CONTROL__MRT0_FMT_MAPPING_DISABLE_MASK 0x00000001L |
23955 | #define SX_PS_DOWNCONVERT_CONTROL__MRT1_FMT_MAPPING_DISABLE_MASK 0x00000002L |
23956 | #define SX_PS_DOWNCONVERT_CONTROL__MRT2_FMT_MAPPING_DISABLE_MASK 0x00000004L |
23957 | #define SX_PS_DOWNCONVERT_CONTROL__MRT3_FMT_MAPPING_DISABLE_MASK 0x00000008L |
23958 | #define SX_PS_DOWNCONVERT_CONTROL__MRT4_FMT_MAPPING_DISABLE_MASK 0x00000010L |
23959 | #define SX_PS_DOWNCONVERT_CONTROL__MRT5_FMT_MAPPING_DISABLE_MASK 0x00000020L |
23960 | #define SX_PS_DOWNCONVERT_CONTROL__MRT6_FMT_MAPPING_DISABLE_MASK 0x00000040L |
23961 | #define SX_PS_DOWNCONVERT_CONTROL__MRT7_FMT_MAPPING_DISABLE_MASK 0x00000080L |
23962 | //SX_PS_DOWNCONVERT |
23963 | #define SX_PS_DOWNCONVERT__MRT0__SHIFT 0x0 |
23964 | #define SX_PS_DOWNCONVERT__MRT1__SHIFT 0x4 |
23965 | #define SX_PS_DOWNCONVERT__MRT2__SHIFT 0x8 |
23966 | #define SX_PS_DOWNCONVERT__MRT3__SHIFT 0xc |
23967 | #define SX_PS_DOWNCONVERT__MRT4__SHIFT 0x10 |
23968 | #define SX_PS_DOWNCONVERT__MRT5__SHIFT 0x14 |
23969 | #define SX_PS_DOWNCONVERT__MRT6__SHIFT 0x18 |
23970 | #define SX_PS_DOWNCONVERT__MRT7__SHIFT 0x1c |
23971 | #define SX_PS_DOWNCONVERT__MRT0_MASK 0x0000000FL |
23972 | #define SX_PS_DOWNCONVERT__MRT1_MASK 0x000000F0L |
23973 | #define SX_PS_DOWNCONVERT__MRT2_MASK 0x00000F00L |
23974 | #define SX_PS_DOWNCONVERT__MRT3_MASK 0x0000F000L |
23975 | #define SX_PS_DOWNCONVERT__MRT4_MASK 0x000F0000L |
23976 | #define SX_PS_DOWNCONVERT__MRT5_MASK 0x00F00000L |
23977 | #define SX_PS_DOWNCONVERT__MRT6_MASK 0x0F000000L |
23978 | #define SX_PS_DOWNCONVERT__MRT7_MASK 0xF0000000L |
23979 | //SX_BLEND_OPT_EPSILON |
23980 | #define SX_BLEND_OPT_EPSILON__MRT0_EPSILON__SHIFT 0x0 |
23981 | #define SX_BLEND_OPT_EPSILON__MRT1_EPSILON__SHIFT 0x4 |
23982 | #define SX_BLEND_OPT_EPSILON__MRT2_EPSILON__SHIFT 0x8 |
23983 | #define SX_BLEND_OPT_EPSILON__MRT3_EPSILON__SHIFT 0xc |
23984 | #define SX_BLEND_OPT_EPSILON__MRT4_EPSILON__SHIFT 0x10 |
23985 | #define SX_BLEND_OPT_EPSILON__MRT5_EPSILON__SHIFT 0x14 |
23986 | #define SX_BLEND_OPT_EPSILON__MRT6_EPSILON__SHIFT 0x18 |
23987 | #define SX_BLEND_OPT_EPSILON__MRT7_EPSILON__SHIFT 0x1c |
23988 | #define SX_BLEND_OPT_EPSILON__MRT0_EPSILON_MASK 0x0000000FL |
23989 | #define SX_BLEND_OPT_EPSILON__MRT1_EPSILON_MASK 0x000000F0L |
23990 | #define SX_BLEND_OPT_EPSILON__MRT2_EPSILON_MASK 0x00000F00L |
23991 | #define SX_BLEND_OPT_EPSILON__MRT3_EPSILON_MASK 0x0000F000L |
23992 | #define SX_BLEND_OPT_EPSILON__MRT4_EPSILON_MASK 0x000F0000L |
23993 | #define SX_BLEND_OPT_EPSILON__MRT5_EPSILON_MASK 0x00F00000L |
23994 | #define SX_BLEND_OPT_EPSILON__MRT6_EPSILON_MASK 0x0F000000L |
23995 | #define SX_BLEND_OPT_EPSILON__MRT7_EPSILON_MASK 0xF0000000L |
23996 | //SX_BLEND_OPT_CONTROL |
23997 | #define SX_BLEND_OPT_CONTROL__MRT0_COLOR_OPT_DISABLE__SHIFT 0x0 |
23998 | #define SX_BLEND_OPT_CONTROL__MRT0_ALPHA_OPT_DISABLE__SHIFT 0x1 |
23999 | #define SX_BLEND_OPT_CONTROL__MRT1_COLOR_OPT_DISABLE__SHIFT 0x4 |
24000 | #define SX_BLEND_OPT_CONTROL__MRT1_ALPHA_OPT_DISABLE__SHIFT 0x5 |
24001 | #define SX_BLEND_OPT_CONTROL__MRT2_COLOR_OPT_DISABLE__SHIFT 0x8 |
24002 | #define SX_BLEND_OPT_CONTROL__MRT2_ALPHA_OPT_DISABLE__SHIFT 0x9 |
24003 | #define SX_BLEND_OPT_CONTROL__MRT3_COLOR_OPT_DISABLE__SHIFT 0xc |
24004 | #define SX_BLEND_OPT_CONTROL__MRT3_ALPHA_OPT_DISABLE__SHIFT 0xd |
24005 | #define SX_BLEND_OPT_CONTROL__MRT4_COLOR_OPT_DISABLE__SHIFT 0x10 |
24006 | #define SX_BLEND_OPT_CONTROL__MRT4_ALPHA_OPT_DISABLE__SHIFT 0x11 |
24007 | #define SX_BLEND_OPT_CONTROL__MRT5_COLOR_OPT_DISABLE__SHIFT 0x14 |
24008 | #define SX_BLEND_OPT_CONTROL__MRT5_ALPHA_OPT_DISABLE__SHIFT 0x15 |
24009 | #define SX_BLEND_OPT_CONTROL__MRT6_COLOR_OPT_DISABLE__SHIFT 0x18 |
24010 | #define SX_BLEND_OPT_CONTROL__MRT6_ALPHA_OPT_DISABLE__SHIFT 0x19 |
24011 | #define SX_BLEND_OPT_CONTROL__MRT7_COLOR_OPT_DISABLE__SHIFT 0x1c |
24012 | #define SX_BLEND_OPT_CONTROL__MRT7_ALPHA_OPT_DISABLE__SHIFT 0x1d |
24013 | #define SX_BLEND_OPT_CONTROL__PIXEN_ZERO_OPT_DISABLE__SHIFT 0x1f |
24014 | #define SX_BLEND_OPT_CONTROL__MRT0_COLOR_OPT_DISABLE_MASK 0x00000001L |
24015 | #define SX_BLEND_OPT_CONTROL__MRT0_ALPHA_OPT_DISABLE_MASK 0x00000002L |
24016 | #define SX_BLEND_OPT_CONTROL__MRT1_COLOR_OPT_DISABLE_MASK 0x00000010L |
24017 | #define SX_BLEND_OPT_CONTROL__MRT1_ALPHA_OPT_DISABLE_MASK 0x00000020L |
24018 | #define SX_BLEND_OPT_CONTROL__MRT2_COLOR_OPT_DISABLE_MASK 0x00000100L |
24019 | #define SX_BLEND_OPT_CONTROL__MRT2_ALPHA_OPT_DISABLE_MASK 0x00000200L |
24020 | #define SX_BLEND_OPT_CONTROL__MRT3_COLOR_OPT_DISABLE_MASK 0x00001000L |
24021 | #define SX_BLEND_OPT_CONTROL__MRT3_ALPHA_OPT_DISABLE_MASK 0x00002000L |
24022 | #define SX_BLEND_OPT_CONTROL__MRT4_COLOR_OPT_DISABLE_MASK 0x00010000L |
24023 | #define SX_BLEND_OPT_CONTROL__MRT4_ALPHA_OPT_DISABLE_MASK 0x00020000L |
24024 | #define SX_BLEND_OPT_CONTROL__MRT5_COLOR_OPT_DISABLE_MASK 0x00100000L |
24025 | #define SX_BLEND_OPT_CONTROL__MRT5_ALPHA_OPT_DISABLE_MASK 0x00200000L |
24026 | #define SX_BLEND_OPT_CONTROL__MRT6_COLOR_OPT_DISABLE_MASK 0x01000000L |
24027 | #define SX_BLEND_OPT_CONTROL__MRT6_ALPHA_OPT_DISABLE_MASK 0x02000000L |
24028 | #define SX_BLEND_OPT_CONTROL__MRT7_COLOR_OPT_DISABLE_MASK 0x10000000L |
24029 | #define SX_BLEND_OPT_CONTROL__MRT7_ALPHA_OPT_DISABLE_MASK 0x20000000L |
24030 | #define SX_BLEND_OPT_CONTROL__PIXEN_ZERO_OPT_DISABLE_MASK 0x80000000L |
24031 | //SX_MRT0_BLEND_OPT |
24032 | #define SX_MRT0_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 |
24033 | #define SX_MRT0_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 |
24034 | #define SX_MRT0_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 |
24035 | #define SX_MRT0_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 |
24036 | #define SX_MRT0_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 |
24037 | #define SX_MRT0_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 |
24038 | #define SX_MRT0_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L |
24039 | #define SX_MRT0_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L |
24040 | #define SX_MRT0_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L |
24041 | #define SX_MRT0_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L |
24042 | #define SX_MRT0_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L |
24043 | #define SX_MRT0_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L |
24044 | //SX_MRT1_BLEND_OPT |
24045 | #define SX_MRT1_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 |
24046 | #define SX_MRT1_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 |
24047 | #define SX_MRT1_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 |
24048 | #define SX_MRT1_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 |
24049 | #define SX_MRT1_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 |
24050 | #define SX_MRT1_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 |
24051 | #define SX_MRT1_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L |
24052 | #define SX_MRT1_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L |
24053 | #define SX_MRT1_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L |
24054 | #define SX_MRT1_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L |
24055 | #define SX_MRT1_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L |
24056 | #define SX_MRT1_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L |
24057 | //SX_MRT2_BLEND_OPT |
24058 | #define SX_MRT2_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 |
24059 | #define SX_MRT2_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 |
24060 | #define SX_MRT2_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 |
24061 | #define SX_MRT2_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 |
24062 | #define SX_MRT2_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 |
24063 | #define SX_MRT2_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 |
24064 | #define SX_MRT2_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L |
24065 | #define SX_MRT2_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L |
24066 | #define SX_MRT2_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L |
24067 | #define SX_MRT2_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L |
24068 | #define SX_MRT2_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L |
24069 | #define SX_MRT2_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L |
24070 | //SX_MRT3_BLEND_OPT |
24071 | #define SX_MRT3_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 |
24072 | #define SX_MRT3_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 |
24073 | #define SX_MRT3_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 |
24074 | #define SX_MRT3_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 |
24075 | #define SX_MRT3_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 |
24076 | #define SX_MRT3_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 |
24077 | #define SX_MRT3_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L |
24078 | #define SX_MRT3_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L |
24079 | #define SX_MRT3_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L |
24080 | #define SX_MRT3_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L |
24081 | #define SX_MRT3_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L |
24082 | #define SX_MRT3_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L |
24083 | //SX_MRT4_BLEND_OPT |
24084 | #define SX_MRT4_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 |
24085 | #define SX_MRT4_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 |
24086 | #define SX_MRT4_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 |
24087 | #define SX_MRT4_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 |
24088 | #define SX_MRT4_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 |
24089 | #define SX_MRT4_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 |
24090 | #define SX_MRT4_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L |
24091 | #define SX_MRT4_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L |
24092 | #define SX_MRT4_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L |
24093 | #define SX_MRT4_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L |
24094 | #define SX_MRT4_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L |
24095 | #define SX_MRT4_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L |
24096 | //SX_MRT5_BLEND_OPT |
24097 | #define SX_MRT5_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 |
24098 | #define SX_MRT5_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 |
24099 | #define SX_MRT5_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 |
24100 | #define SX_MRT5_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 |
24101 | #define SX_MRT5_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 |
24102 | #define SX_MRT5_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 |
24103 | #define SX_MRT5_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L |
24104 | #define SX_MRT5_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L |
24105 | #define SX_MRT5_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L |
24106 | #define SX_MRT5_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L |
24107 | #define SX_MRT5_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L |
24108 | #define SX_MRT5_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L |
24109 | //SX_MRT6_BLEND_OPT |
24110 | #define SX_MRT6_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 |
24111 | #define SX_MRT6_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 |
24112 | #define SX_MRT6_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 |
24113 | #define SX_MRT6_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 |
24114 | #define SX_MRT6_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 |
24115 | #define SX_MRT6_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 |
24116 | #define SX_MRT6_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L |
24117 | #define SX_MRT6_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L |
24118 | #define SX_MRT6_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L |
24119 | #define SX_MRT6_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L |
24120 | #define SX_MRT6_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L |
24121 | #define SX_MRT6_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L |
24122 | //SX_MRT7_BLEND_OPT |
24123 | #define SX_MRT7_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 |
24124 | #define SX_MRT7_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 |
24125 | #define SX_MRT7_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 |
24126 | #define SX_MRT7_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 |
24127 | #define SX_MRT7_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 |
24128 | #define SX_MRT7_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 |
24129 | #define SX_MRT7_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L |
24130 | #define SX_MRT7_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L |
24131 | #define SX_MRT7_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L |
24132 | #define SX_MRT7_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L |
24133 | #define SX_MRT7_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L |
24134 | #define SX_MRT7_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L |
24135 | //CB_BLEND0_CONTROL |
24136 | #define CB_BLEND0_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 |
24137 | #define CB_BLEND0_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 |
24138 | #define CB_BLEND0_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 |
24139 | #define CB_BLEND0_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 |
24140 | #define CB_BLEND0_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 |
24141 | #define CB_BLEND0_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 |
24142 | #define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d |
24143 | #define CB_BLEND0_CONTROL__ENABLE__SHIFT 0x1e |
24144 | #define CB_BLEND0_CONTROL__DISABLE_ROP3__SHIFT 0x1f |
24145 | #define CB_BLEND0_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL |
24146 | #define CB_BLEND0_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L |
24147 | #define CB_BLEND0_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L |
24148 | #define CB_BLEND0_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L |
24149 | #define CB_BLEND0_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L |
24150 | #define CB_BLEND0_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L |
24151 | #define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L |
24152 | #define CB_BLEND0_CONTROL__ENABLE_MASK 0x40000000L |
24153 | #define CB_BLEND0_CONTROL__DISABLE_ROP3_MASK 0x80000000L |
24154 | //CB_BLEND1_CONTROL |
24155 | #define CB_BLEND1_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 |
24156 | #define CB_BLEND1_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 |
24157 | #define CB_BLEND1_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 |
24158 | #define CB_BLEND1_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 |
24159 | #define CB_BLEND1_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 |
24160 | #define CB_BLEND1_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 |
24161 | #define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d |
24162 | #define CB_BLEND1_CONTROL__ENABLE__SHIFT 0x1e |
24163 | #define CB_BLEND1_CONTROL__DISABLE_ROP3__SHIFT 0x1f |
24164 | #define CB_BLEND1_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL |
24165 | #define CB_BLEND1_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L |
24166 | #define CB_BLEND1_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L |
24167 | #define CB_BLEND1_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L |
24168 | #define CB_BLEND1_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L |
24169 | #define CB_BLEND1_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L |
24170 | #define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L |
24171 | #define CB_BLEND1_CONTROL__ENABLE_MASK 0x40000000L |
24172 | #define CB_BLEND1_CONTROL__DISABLE_ROP3_MASK 0x80000000L |
24173 | //CB_BLEND2_CONTROL |
24174 | #define CB_BLEND2_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 |
24175 | #define CB_BLEND2_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 |
24176 | #define CB_BLEND2_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 |
24177 | #define CB_BLEND2_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 |
24178 | #define CB_BLEND2_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 |
24179 | #define CB_BLEND2_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 |
24180 | #define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d |
24181 | #define CB_BLEND2_CONTROL__ENABLE__SHIFT 0x1e |
24182 | #define CB_BLEND2_CONTROL__DISABLE_ROP3__SHIFT 0x1f |
24183 | #define CB_BLEND2_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL |
24184 | #define CB_BLEND2_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L |
24185 | #define CB_BLEND2_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L |
24186 | #define CB_BLEND2_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L |
24187 | #define CB_BLEND2_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L |
24188 | #define CB_BLEND2_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L |
24189 | #define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L |
24190 | #define CB_BLEND2_CONTROL__ENABLE_MASK 0x40000000L |
24191 | #define CB_BLEND2_CONTROL__DISABLE_ROP3_MASK 0x80000000L |
24192 | //CB_BLEND3_CONTROL |
24193 | #define CB_BLEND3_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 |
24194 | #define CB_BLEND3_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 |
24195 | #define CB_BLEND3_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 |
24196 | #define CB_BLEND3_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 |
24197 | #define CB_BLEND3_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 |
24198 | #define CB_BLEND3_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 |
24199 | #define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d |
24200 | #define CB_BLEND3_CONTROL__ENABLE__SHIFT 0x1e |
24201 | #define CB_BLEND3_CONTROL__DISABLE_ROP3__SHIFT 0x1f |
24202 | #define CB_BLEND3_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL |
24203 | #define CB_BLEND3_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L |
24204 | #define CB_BLEND3_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L |
24205 | #define CB_BLEND3_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L |
24206 | #define CB_BLEND3_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L |
24207 | #define CB_BLEND3_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L |
24208 | #define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L |
24209 | #define CB_BLEND3_CONTROL__ENABLE_MASK 0x40000000L |
24210 | #define CB_BLEND3_CONTROL__DISABLE_ROP3_MASK 0x80000000L |
24211 | //CB_BLEND4_CONTROL |
24212 | #define CB_BLEND4_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 |
24213 | #define CB_BLEND4_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 |
24214 | #define CB_BLEND4_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 |
24215 | #define CB_BLEND4_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 |
24216 | #define CB_BLEND4_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 |
24217 | #define CB_BLEND4_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 |
24218 | #define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d |
24219 | #define CB_BLEND4_CONTROL__ENABLE__SHIFT 0x1e |
24220 | #define CB_BLEND4_CONTROL__DISABLE_ROP3__SHIFT 0x1f |
24221 | #define CB_BLEND4_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL |
24222 | #define CB_BLEND4_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L |
24223 | #define CB_BLEND4_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L |
24224 | #define CB_BLEND4_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L |
24225 | #define CB_BLEND4_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L |
24226 | #define CB_BLEND4_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L |
24227 | #define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L |
24228 | #define CB_BLEND4_CONTROL__ENABLE_MASK 0x40000000L |
24229 | #define CB_BLEND4_CONTROL__DISABLE_ROP3_MASK 0x80000000L |
24230 | //CB_BLEND5_CONTROL |
24231 | #define CB_BLEND5_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 |
24232 | #define CB_BLEND5_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 |
24233 | #define CB_BLEND5_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 |
24234 | #define CB_BLEND5_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 |
24235 | #define CB_BLEND5_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 |
24236 | #define CB_BLEND5_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 |
24237 | #define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d |
24238 | #define CB_BLEND5_CONTROL__ENABLE__SHIFT 0x1e |
24239 | #define CB_BLEND5_CONTROL__DISABLE_ROP3__SHIFT 0x1f |
24240 | #define CB_BLEND5_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL |
24241 | #define CB_BLEND5_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L |
24242 | #define CB_BLEND5_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L |
24243 | #define CB_BLEND5_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L |
24244 | #define CB_BLEND5_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L |
24245 | #define CB_BLEND5_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L |
24246 | #define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L |
24247 | #define CB_BLEND5_CONTROL__ENABLE_MASK 0x40000000L |
24248 | #define CB_BLEND5_CONTROL__DISABLE_ROP3_MASK 0x80000000L |
24249 | //CB_BLEND6_CONTROL |
24250 | #define CB_BLEND6_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 |
24251 | #define CB_BLEND6_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 |
24252 | #define CB_BLEND6_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 |
24253 | #define CB_BLEND6_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 |
24254 | #define CB_BLEND6_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 |
24255 | #define CB_BLEND6_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 |
24256 | #define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d |
24257 | #define CB_BLEND6_CONTROL__ENABLE__SHIFT 0x1e |
24258 | #define CB_BLEND6_CONTROL__DISABLE_ROP3__SHIFT 0x1f |
24259 | #define CB_BLEND6_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL |
24260 | #define CB_BLEND6_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L |
24261 | #define CB_BLEND6_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L |
24262 | #define CB_BLEND6_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L |
24263 | #define CB_BLEND6_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L |
24264 | #define CB_BLEND6_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L |
24265 | #define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L |
24266 | #define CB_BLEND6_CONTROL__ENABLE_MASK 0x40000000L |
24267 | #define CB_BLEND6_CONTROL__DISABLE_ROP3_MASK 0x80000000L |
24268 | //CB_BLEND7_CONTROL |
24269 | #define CB_BLEND7_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 |
24270 | #define CB_BLEND7_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 |
24271 | #define CB_BLEND7_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 |
24272 | #define CB_BLEND7_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 |
24273 | #define CB_BLEND7_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 |
24274 | #define CB_BLEND7_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 |
24275 | #define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d |
24276 | #define CB_BLEND7_CONTROL__ENABLE__SHIFT 0x1e |
24277 | #define CB_BLEND7_CONTROL__DISABLE_ROP3__SHIFT 0x1f |
24278 | #define CB_BLEND7_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL |
24279 | #define CB_BLEND7_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L |
24280 | #define CB_BLEND7_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L |
24281 | #define CB_BLEND7_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L |
24282 | #define CB_BLEND7_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L |
24283 | #define CB_BLEND7_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L |
24284 | #define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L |
24285 | #define CB_BLEND7_CONTROL__ENABLE_MASK 0x40000000L |
24286 | #define CB_BLEND7_CONTROL__DISABLE_ROP3_MASK 0x80000000L |
24287 | //GFX_COPY_STATE |
24288 | #define GFX_COPY_STATE__SRC_STATE_ID__SHIFT 0x0 |
24289 | #define GFX_COPY_STATE__SRC_STATE_ID_MASK 0x00000007L |
24290 | //PA_CL_POINT_X_RAD |
24291 | #define PA_CL_POINT_X_RAD__DATA_REGISTER__SHIFT 0x0 |
24292 | #define PA_CL_POINT_X_RAD__DATA_REGISTER_MASK 0xFFFFFFFFL |
24293 | //PA_CL_POINT_Y_RAD |
24294 | #define PA_CL_POINT_Y_RAD__DATA_REGISTER__SHIFT 0x0 |
24295 | #define PA_CL_POINT_Y_RAD__DATA_REGISTER_MASK 0xFFFFFFFFL |
24296 | //PA_CL_POINT_SIZE |
24297 | #define PA_CL_POINT_SIZE__DATA_REGISTER__SHIFT 0x0 |
24298 | #define PA_CL_POINT_SIZE__DATA_REGISTER_MASK 0xFFFFFFFFL |
24299 | //PA_CL_POINT_CULL_RAD |
24300 | #define PA_CL_POINT_CULL_RAD__DATA_REGISTER__SHIFT 0x0 |
24301 | #define PA_CL_POINT_CULL_RAD__DATA_REGISTER_MASK 0xFFFFFFFFL |
24302 | //VGT_DMA_BASE_HI |
24303 | #define VGT_DMA_BASE_HI__BASE_ADDR__SHIFT 0x0 |
24304 | #define VGT_DMA_BASE_HI__BASE_ADDR_MASK 0x0000FFFFL |
24305 | //VGT_DMA_BASE |
24306 | #define VGT_DMA_BASE__BASE_ADDR__SHIFT 0x0 |
24307 | #define VGT_DMA_BASE__BASE_ADDR_MASK 0xFFFFFFFFL |
24308 | //VGT_DRAW_INITIATOR |
24309 | #define VGT_DRAW_INITIATOR__SOURCE_SELECT__SHIFT 0x0 |
24310 | #define VGT_DRAW_INITIATOR__MAJOR_MODE__SHIFT 0x2 |
24311 | #define VGT_DRAW_INITIATOR__SPRITE_EN_R6XX__SHIFT 0x4 |
24312 | #define VGT_DRAW_INITIATOR__NOT_EOP__SHIFT 0x5 |
24313 | #define VGT_DRAW_INITIATOR__USE_OPAQUE__SHIFT 0x6 |
24314 | #define VGT_DRAW_INITIATOR__REG_RT_INDEX__SHIFT 0x1d |
24315 | #define VGT_DRAW_INITIATOR__SOURCE_SELECT_MASK 0x00000003L |
24316 | #define VGT_DRAW_INITIATOR__MAJOR_MODE_MASK 0x0000000CL |
24317 | #define VGT_DRAW_INITIATOR__SPRITE_EN_R6XX_MASK 0x00000010L |
24318 | #define VGT_DRAW_INITIATOR__NOT_EOP_MASK 0x00000020L |
24319 | #define VGT_DRAW_INITIATOR__USE_OPAQUE_MASK 0x00000040L |
24320 | #define VGT_DRAW_INITIATOR__REG_RT_INDEX_MASK 0xE0000000L |
24321 | //VGT_EVENT_ADDRESS_REG |
24322 | #define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW__SHIFT 0x0 |
24323 | #define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW_MASK 0x0FFFFFFFL |
24324 | //GE_MAX_OUTPUT_PER_SUBGROUP |
24325 | #define GE_MAX_OUTPUT_PER_SUBGROUP__MAX_VERTS_PER_SUBGROUP__SHIFT 0x0 |
24326 | #define GE_MAX_OUTPUT_PER_SUBGROUP__MAX_VERTS_PER_SUBGROUP_MASK 0x000003FFL |
24327 | //DB_DEPTH_CONTROL |
24328 | #define DB_DEPTH_CONTROL__STENCIL_ENABLE__SHIFT 0x0 |
24329 | #define DB_DEPTH_CONTROL__Z_ENABLE__SHIFT 0x1 |
24330 | #define DB_DEPTH_CONTROL__Z_WRITE_ENABLE__SHIFT 0x2 |
24331 | #define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE__SHIFT 0x3 |
24332 | #define DB_DEPTH_CONTROL__ZFUNC__SHIFT 0x4 |
24333 | #define DB_DEPTH_CONTROL__BACKFACE_ENABLE__SHIFT 0x7 |
24334 | #define DB_DEPTH_CONTROL__STENCILFUNC__SHIFT 0x8 |
24335 | #define DB_DEPTH_CONTROL__STENCILFUNC_BF__SHIFT 0x14 |
24336 | #define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL__SHIFT 0x1e |
24337 | #define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS__SHIFT 0x1f |
24338 | #define DB_DEPTH_CONTROL__STENCIL_ENABLE_MASK 0x00000001L |
24339 | #define DB_DEPTH_CONTROL__Z_ENABLE_MASK 0x00000002L |
24340 | #define DB_DEPTH_CONTROL__Z_WRITE_ENABLE_MASK 0x00000004L |
24341 | #define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE_MASK 0x00000008L |
24342 | #define DB_DEPTH_CONTROL__ZFUNC_MASK 0x00000070L |
24343 | #define DB_DEPTH_CONTROL__BACKFACE_ENABLE_MASK 0x00000080L |
24344 | #define DB_DEPTH_CONTROL__STENCILFUNC_MASK 0x00000700L |
24345 | #define DB_DEPTH_CONTROL__STENCILFUNC_BF_MASK 0x00700000L |
24346 | #define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL_MASK 0x40000000L |
24347 | #define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS_MASK 0x80000000L |
24348 | //DB_EQAA |
24349 | #define DB_EQAA__MAX_ANCHOR_SAMPLES__SHIFT 0x0 |
24350 | #define DB_EQAA__PS_ITER_SAMPLES__SHIFT 0x4 |
24351 | #define DB_EQAA__MASK_EXPORT_NUM_SAMPLES__SHIFT 0x8 |
24352 | #define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES__SHIFT 0xc |
24353 | #define DB_EQAA__HIGH_QUALITY_INTERSECTIONS__SHIFT 0x10 |
24354 | #define DB_EQAA__INCOHERENT_EQAA_READS__SHIFT 0x11 |
24355 | #define DB_EQAA__INTERPOLATE_COMP_Z__SHIFT 0x12 |
24356 | #define DB_EQAA__INTERPOLATE_SRC_Z__SHIFT 0x13 |
24357 | #define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS__SHIFT 0x14 |
24358 | #define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE__SHIFT 0x15 |
24359 | #define DB_EQAA__OVERRASTERIZATION_AMOUNT__SHIFT 0x18 |
24360 | #define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION__SHIFT 0x1b |
24361 | #define DB_EQAA__MAX_ANCHOR_SAMPLES_MASK 0x00000007L |
24362 | #define DB_EQAA__PS_ITER_SAMPLES_MASK 0x00000070L |
24363 | #define DB_EQAA__MASK_EXPORT_NUM_SAMPLES_MASK 0x00000700L |
24364 | #define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES_MASK 0x00007000L |
24365 | #define DB_EQAA__HIGH_QUALITY_INTERSECTIONS_MASK 0x00010000L |
24366 | #define DB_EQAA__INCOHERENT_EQAA_READS_MASK 0x00020000L |
24367 | #define DB_EQAA__INTERPOLATE_COMP_Z_MASK 0x00040000L |
24368 | #define DB_EQAA__INTERPOLATE_SRC_Z_MASK 0x00080000L |
24369 | #define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS_MASK 0x00100000L |
24370 | #define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE_MASK 0x00200000L |
24371 | #define DB_EQAA__OVERRASTERIZATION_AMOUNT_MASK 0x07000000L |
24372 | #define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION_MASK 0x08000000L |
24373 | //CB_COLOR_CONTROL |
24374 | #define CB_COLOR_CONTROL__DISABLE_DUAL_QUAD__SHIFT 0x0 |
24375 | #define CB_COLOR_CONTROL__ENABLE_1FRAG_PS_INVOKE__SHIFT 0x1 |
24376 | #define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x3 |
24377 | #define CB_COLOR_CONTROL__MODE__SHIFT 0x4 |
24378 | #define CB_COLOR_CONTROL__ROP3__SHIFT 0x10 |
24379 | #define CB_COLOR_CONTROL__DISABLE_DUAL_QUAD_MASK 0x00000001L |
24380 | #define CB_COLOR_CONTROL__ENABLE_1FRAG_PS_INVOKE_MASK 0x00000002L |
24381 | #define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x00000008L |
24382 | #define CB_COLOR_CONTROL__MODE_MASK 0x00000070L |
24383 | #define CB_COLOR_CONTROL__ROP3_MASK 0x00FF0000L |
24384 | //DB_SHADER_CONTROL |
24385 | #define DB_SHADER_CONTROL__Z_EXPORT_ENABLE__SHIFT 0x0 |
24386 | #define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE__SHIFT 0x1 |
24387 | #define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE__SHIFT 0x2 |
24388 | #define DB_SHADER_CONTROL__Z_ORDER__SHIFT 0x4 |
24389 | #define DB_SHADER_CONTROL__KILL_ENABLE__SHIFT 0x6 |
24390 | #define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE__SHIFT 0x7 |
24391 | #define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE__SHIFT 0x8 |
24392 | #define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL__SHIFT 0x9 |
24393 | #define DB_SHADER_CONTROL__EXEC_ON_NOOP__SHIFT 0xa |
24394 | #define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE__SHIFT 0xb |
24395 | #define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER__SHIFT 0xc |
24396 | #define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT__SHIFT 0xd |
24397 | #define DB_SHADER_CONTROL__DUAL_QUAD_DISABLE__SHIFT 0xf |
24398 | #define DB_SHADER_CONTROL__PRIMITIVE_ORDERED_PIXEL_SHADER__SHIFT 0x10 |
24399 | #define DB_SHADER_CONTROL__PRE_SHADER_DEPTH_COVERAGE_ENABLE__SHIFT 0x17 |
24400 | #define DB_SHADER_CONTROL__OREO_BLEND_ENABLE__SHIFT 0x18 |
24401 | #define DB_SHADER_CONTROL__OVERRIDE_INTRINSIC_RATE_ENABLE__SHIFT 0x19 |
24402 | #define DB_SHADER_CONTROL__OVERRIDE_INTRINSIC_RATE__SHIFT 0x1a |
24403 | #define DB_SHADER_CONTROL__Z_EXPORT_ENABLE_MASK 0x00000001L |
24404 | #define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE_MASK 0x00000002L |
24405 | #define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE_MASK 0x00000004L |
24406 | #define DB_SHADER_CONTROL__Z_ORDER_MASK 0x00000030L |
24407 | #define DB_SHADER_CONTROL__KILL_ENABLE_MASK 0x00000040L |
24408 | #define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE_MASK 0x00000080L |
24409 | #define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE_MASK 0x00000100L |
24410 | #define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL_MASK 0x00000200L |
24411 | #define DB_SHADER_CONTROL__EXEC_ON_NOOP_MASK 0x00000400L |
24412 | #define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE_MASK 0x00000800L |
24413 | #define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER_MASK 0x00001000L |
24414 | #define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT_MASK 0x00006000L |
24415 | #define DB_SHADER_CONTROL__DUAL_QUAD_DISABLE_MASK 0x00008000L |
24416 | #define DB_SHADER_CONTROL__PRIMITIVE_ORDERED_PIXEL_SHADER_MASK 0x00010000L |
24417 | #define DB_SHADER_CONTROL__PRE_SHADER_DEPTH_COVERAGE_ENABLE_MASK 0x00800000L |
24418 | #define DB_SHADER_CONTROL__OREO_BLEND_ENABLE_MASK 0x01000000L |
24419 | #define DB_SHADER_CONTROL__OVERRIDE_INTRINSIC_RATE_ENABLE_MASK 0x02000000L |
24420 | #define DB_SHADER_CONTROL__OVERRIDE_INTRINSIC_RATE_MASK 0x1C000000L |
24421 | //PA_CL_CLIP_CNTL |
24422 | #define PA_CL_CLIP_CNTL__UCP_ENA_0__SHIFT 0x0 |
24423 | #define PA_CL_CLIP_CNTL__UCP_ENA_1__SHIFT 0x1 |
24424 | #define PA_CL_CLIP_CNTL__UCP_ENA_2__SHIFT 0x2 |
24425 | #define PA_CL_CLIP_CNTL__UCP_ENA_3__SHIFT 0x3 |
24426 | #define PA_CL_CLIP_CNTL__UCP_ENA_4__SHIFT 0x4 |
24427 | #define PA_CL_CLIP_CNTL__UCP_ENA_5__SHIFT 0x5 |
24428 | #define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG__SHIFT 0xd |
24429 | #define PA_CL_CLIP_CNTL__PS_UCP_MODE__SHIFT 0xe |
24430 | #define PA_CL_CLIP_CNTL__CLIP_DISABLE__SHIFT 0x10 |
24431 | #define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA__SHIFT 0x11 |
24432 | #define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA__SHIFT 0x12 |
24433 | #define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF__SHIFT 0x13 |
24434 | #define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT__SHIFT 0x14 |
24435 | #define PA_CL_CLIP_CNTL__VTX_KILL_OR__SHIFT 0x15 |
24436 | #define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL__SHIFT 0x16 |
24437 | #define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA__SHIFT 0x18 |
24438 | #define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE__SHIFT 0x19 |
24439 | #define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE__SHIFT 0x1a |
24440 | #define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE__SHIFT 0x1b |
24441 | #define PA_CL_CLIP_CNTL__ZCLIP_PROG_NEAR_ENA__SHIFT 0x1c |
24442 | #define PA_CL_CLIP_CNTL__UCP_ENA_0_MASK 0x00000001L |
24443 | #define PA_CL_CLIP_CNTL__UCP_ENA_1_MASK 0x00000002L |
24444 | #define PA_CL_CLIP_CNTL__UCP_ENA_2_MASK 0x00000004L |
24445 | #define PA_CL_CLIP_CNTL__UCP_ENA_3_MASK 0x00000008L |
24446 | #define PA_CL_CLIP_CNTL__UCP_ENA_4_MASK 0x00000010L |
24447 | #define PA_CL_CLIP_CNTL__UCP_ENA_5_MASK 0x00000020L |
24448 | #define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG_MASK 0x00002000L |
24449 | #define PA_CL_CLIP_CNTL__PS_UCP_MODE_MASK 0x0000C000L |
24450 | #define PA_CL_CLIP_CNTL__CLIP_DISABLE_MASK 0x00010000L |
24451 | #define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA_MASK 0x00020000L |
24452 | #define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA_MASK 0x00040000L |
24453 | #define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF_MASK 0x00080000L |
24454 | #define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT_MASK 0x00100000L |
24455 | #define PA_CL_CLIP_CNTL__VTX_KILL_OR_MASK 0x00200000L |
24456 | #define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL_MASK 0x00400000L |
24457 | #define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA_MASK 0x01000000L |
24458 | #define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE_MASK 0x02000000L |
24459 | #define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE_MASK 0x04000000L |
24460 | #define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE_MASK 0x08000000L |
24461 | #define PA_CL_CLIP_CNTL__ZCLIP_PROG_NEAR_ENA_MASK 0x10000000L |
24462 | //PA_SU_SC_MODE_CNTL |
24463 | #define PA_SU_SC_MODE_CNTL__CULL_FRONT__SHIFT 0x0 |
24464 | #define PA_SU_SC_MODE_CNTL__CULL_BACK__SHIFT 0x1 |
24465 | #define PA_SU_SC_MODE_CNTL__FACE__SHIFT 0x2 |
24466 | #define PA_SU_SC_MODE_CNTL__POLY_MODE__SHIFT 0x3 |
24467 | #define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE__SHIFT 0x5 |
24468 | #define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE__SHIFT 0x8 |
24469 | #define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE__SHIFT 0xb |
24470 | #define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE__SHIFT 0xc |
24471 | #define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE__SHIFT 0xd |
24472 | #define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE__SHIFT 0x10 |
24473 | #define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST__SHIFT 0x13 |
24474 | #define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS__SHIFT 0x14 |
24475 | #define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT 0x15 |
24476 | #define PA_SU_SC_MODE_CNTL__RIGHT_TRIANGLE_ALTERNATE_GRADIENT_REF__SHIFT 0x16 |
24477 | #define PA_SU_SC_MODE_CNTL__NEW_QUAD_DECOMPOSITION__SHIFT 0x17 |
24478 | #define PA_SU_SC_MODE_CNTL__KEEP_TOGETHER_ENABLE__SHIFT 0x18 |
24479 | #define PA_SU_SC_MODE_CNTL__CULL_FRONT_MASK 0x00000001L |
24480 | #define PA_SU_SC_MODE_CNTL__CULL_BACK_MASK 0x00000002L |
24481 | #define PA_SU_SC_MODE_CNTL__FACE_MASK 0x00000004L |
24482 | #define PA_SU_SC_MODE_CNTL__POLY_MODE_MASK 0x00000018L |
24483 | #define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE_MASK 0x000000E0L |
24484 | #define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE_MASK 0x00000700L |
24485 | #define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE_MASK 0x00000800L |
24486 | #define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE_MASK 0x00001000L |
24487 | #define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE_MASK 0x00002000L |
24488 | #define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE_MASK 0x00010000L |
24489 | #define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST_MASK 0x00080000L |
24490 | #define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS_MASK 0x00100000L |
24491 | #define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA_MASK 0x00200000L |
24492 | #define PA_SU_SC_MODE_CNTL__RIGHT_TRIANGLE_ALTERNATE_GRADIENT_REF_MASK 0x00400000L |
24493 | #define PA_SU_SC_MODE_CNTL__NEW_QUAD_DECOMPOSITION_MASK 0x00800000L |
24494 | #define PA_SU_SC_MODE_CNTL__KEEP_TOGETHER_ENABLE_MASK 0x01000000L |
24495 | //PA_CL_VTE_CNTL |
24496 | #define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA__SHIFT 0x0 |
24497 | #define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA__SHIFT 0x1 |
24498 | #define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA__SHIFT 0x2 |
24499 | #define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA__SHIFT 0x3 |
24500 | #define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA__SHIFT 0x4 |
24501 | #define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA__SHIFT 0x5 |
24502 | #define PA_CL_VTE_CNTL__VTX_XY_FMT__SHIFT 0x8 |
24503 | #define PA_CL_VTE_CNTL__VTX_Z_FMT__SHIFT 0x9 |
24504 | #define PA_CL_VTE_CNTL__VTX_W0_FMT__SHIFT 0xa |
24505 | #define PA_CL_VTE_CNTL__PERFCOUNTER_REF__SHIFT 0xb |
24506 | #define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA_MASK 0x00000001L |
24507 | #define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA_MASK 0x00000002L |
24508 | #define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA_MASK 0x00000004L |
24509 | #define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA_MASK 0x00000008L |
24510 | #define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA_MASK 0x00000010L |
24511 | #define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA_MASK 0x00000020L |
24512 | #define PA_CL_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100L |
24513 | #define PA_CL_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200L |
24514 | #define PA_CL_VTE_CNTL__VTX_W0_FMT_MASK 0x00000400L |
24515 | #define PA_CL_VTE_CNTL__PERFCOUNTER_REF_MASK 0x00000800L |
24516 | //PA_CL_VS_OUT_CNTL |
24517 | #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0__SHIFT 0x0 |
24518 | #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1__SHIFT 0x1 |
24519 | #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2__SHIFT 0x2 |
24520 | #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3__SHIFT 0x3 |
24521 | #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4__SHIFT 0x4 |
24522 | #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5__SHIFT 0x5 |
24523 | #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6__SHIFT 0x6 |
24524 | #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7__SHIFT 0x7 |
24525 | #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0__SHIFT 0x8 |
24526 | #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1__SHIFT 0x9 |
24527 | #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2__SHIFT 0xa |
24528 | #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3__SHIFT 0xb |
24529 | #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4__SHIFT 0xc |
24530 | #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5__SHIFT 0xd |
24531 | #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6__SHIFT 0xe |
24532 | #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7__SHIFT 0xf |
24533 | #define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE__SHIFT 0x10 |
24534 | #define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG__SHIFT 0x11 |
24535 | #define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX__SHIFT 0x12 |
24536 | #define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX__SHIFT 0x13 |
24537 | #define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG__SHIFT 0x14 |
24538 | #define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA__SHIFT 0x15 |
24539 | #define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA__SHIFT 0x16 |
24540 | #define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA__SHIFT 0x17 |
24541 | #define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA__SHIFT 0x18 |
24542 | #define PA_CL_VS_OUT_CNTL__USE_VTX_LINE_WIDTH__SHIFT 0x1b |
24543 | #define PA_CL_VS_OUT_CNTL__USE_VTX_VRS_RATE__SHIFT 0x1c |
24544 | #define PA_CL_VS_OUT_CNTL__BYPASS_VTX_RATE_COMBINER__SHIFT 0x1d |
24545 | #define PA_CL_VS_OUT_CNTL__BYPASS_PRIM_RATE_COMBINER__SHIFT 0x1e |
24546 | #define PA_CL_VS_OUT_CNTL__USE_VTX_FSR_SELECT__SHIFT 0x1f |
24547 | #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0_MASK 0x00000001L |
24548 | #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1_MASK 0x00000002L |
24549 | #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2_MASK 0x00000004L |
24550 | #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3_MASK 0x00000008L |
24551 | #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4_MASK 0x00000010L |
24552 | #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5_MASK 0x00000020L |
24553 | #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6_MASK 0x00000040L |
24554 | #define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7_MASK 0x00000080L |
24555 | #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0_MASK 0x00000100L |
24556 | #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1_MASK 0x00000200L |
24557 | #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2_MASK 0x00000400L |
24558 | #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3_MASK 0x00000800L |
24559 | #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4_MASK 0x00001000L |
24560 | #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5_MASK 0x00002000L |
24561 | #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6_MASK 0x00004000L |
24562 | #define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7_MASK 0x00008000L |
24563 | #define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE_MASK 0x00010000L |
24564 | #define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG_MASK 0x00020000L |
24565 | #define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX_MASK 0x00040000L |
24566 | #define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX_MASK 0x00080000L |
24567 | #define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG_MASK 0x00100000L |
24568 | #define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA_MASK 0x00200000L |
24569 | #define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA_MASK 0x00400000L |
24570 | #define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA_MASK 0x00800000L |
24571 | #define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA_MASK 0x01000000L |
24572 | #define PA_CL_VS_OUT_CNTL__USE_VTX_LINE_WIDTH_MASK 0x08000000L |
24573 | #define PA_CL_VS_OUT_CNTL__USE_VTX_VRS_RATE_MASK 0x10000000L |
24574 | #define PA_CL_VS_OUT_CNTL__BYPASS_VTX_RATE_COMBINER_MASK 0x20000000L |
24575 | #define PA_CL_VS_OUT_CNTL__BYPASS_PRIM_RATE_COMBINER_MASK 0x40000000L |
24576 | #define PA_CL_VS_OUT_CNTL__USE_VTX_FSR_SELECT_MASK 0x80000000L |
24577 | //PA_CL_NANINF_CNTL |
24578 | #define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD__SHIFT 0x0 |
24579 | #define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD__SHIFT 0x1 |
24580 | #define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD__SHIFT 0x2 |
24581 | #define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0__SHIFT 0x3 |
24582 | #define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN__SHIFT 0x4 |
24583 | #define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN__SHIFT 0x5 |
24584 | #define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN__SHIFT 0x6 |
24585 | #define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0__SHIFT 0x7 |
24586 | #define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF__SHIFT 0x8 |
24587 | #define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN__SHIFT 0x9 |
24588 | #define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF__SHIFT 0xa |
24589 | #define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN__SHIFT 0xb |
24590 | #define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF__SHIFT 0xc |
24591 | #define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN__SHIFT 0xd |
24592 | #define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD__SHIFT 0xe |
24593 | #define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0__SHIFT 0x14 |
24594 | #define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD_MASK 0x00000001L |
24595 | #define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD_MASK 0x00000002L |
24596 | #define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD_MASK 0x00000004L |
24597 | #define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0_MASK 0x00000008L |
24598 | #define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN_MASK 0x00000010L |
24599 | #define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN_MASK 0x00000020L |
24600 | #define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN_MASK 0x00000040L |
24601 | #define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0_MASK 0x00000080L |
24602 | #define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF_MASK 0x00000100L |
24603 | #define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN_MASK 0x00000200L |
24604 | #define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF_MASK 0x00000400L |
24605 | #define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN_MASK 0x00000800L |
24606 | #define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF_MASK 0x00001000L |
24607 | #define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN_MASK 0x00002000L |
24608 | #define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD_MASK 0x00004000L |
24609 | #define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0_MASK 0x00100000L |
24610 | //PA_SU_LINE_STIPPLE_CNTL |
24611 | #define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET__SHIFT 0x0 |
24612 | #define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH__SHIFT 0x2 |
24613 | #define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM__SHIFT 0x3 |
24614 | #define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET_MASK 0x00000003L |
24615 | #define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH_MASK 0x00000004L |
24616 | #define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM_MASK 0x00000008L |
24617 | //PA_SU_LINE_STIPPLE_SCALE |
24618 | #define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE__SHIFT 0x0 |
24619 | #define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE_MASK 0xFFFFFFFFL |
24620 | //PA_SU_PRIM_FILTER_CNTL |
24621 | #define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE__SHIFT 0x0 |
24622 | #define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE__SHIFT 0x1 |
24623 | #define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE__SHIFT 0x2 |
24624 | #define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE__SHIFT 0x3 |
24625 | #define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA__SHIFT 0x4 |
24626 | #define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA__SHIFT 0x5 |
24627 | #define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA__SHIFT 0x6 |
24628 | #define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA__SHIFT 0x7 |
24629 | #define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT__SHIFT 0x8 |
24630 | #define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION__SHIFT 0x1e |
24631 | #define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION__SHIFT 0x1f |
24632 | #define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE_MASK 0x00000001L |
24633 | #define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE_MASK 0x00000002L |
24634 | #define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE_MASK 0x00000004L |
24635 | #define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE_MASK 0x00000008L |
24636 | #define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA_MASK 0x00000010L |
24637 | #define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA_MASK 0x00000020L |
24638 | #define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA_MASK 0x00000040L |
24639 | #define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA_MASK 0x00000080L |
24640 | #define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT_MASK 0x0000FF00L |
24641 | #define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION_MASK 0x40000000L |
24642 | #define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION_MASK 0x80000000L |
24643 | //PA_SU_SMALL_PRIM_FILTER_CNTL |
24644 | #define PA_SU_SMALL_PRIM_FILTER_CNTL__SMALL_PRIM_FILTER_ENABLE__SHIFT 0x0 |
24645 | #define PA_SU_SMALL_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE__SHIFT 0x1 |
24646 | #define PA_SU_SMALL_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE__SHIFT 0x2 |
24647 | #define PA_SU_SMALL_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE__SHIFT 0x3 |
24648 | #define PA_SU_SMALL_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE__SHIFT 0x4 |
24649 | #define PA_SU_SMALL_PRIM_FILTER_CNTL__SC_1XMSAA_COMPATIBLE_DISABLE__SHIFT 0x6 |
24650 | #define PA_SU_SMALL_PRIM_FILTER_CNTL__SMALL_PRIM_FILTER_ENABLE_MASK 0x00000001L |
24651 | #define PA_SU_SMALL_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE_MASK 0x00000002L |
24652 | #define PA_SU_SMALL_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE_MASK 0x00000004L |
24653 | #define PA_SU_SMALL_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE_MASK 0x00000008L |
24654 | #define PA_SU_SMALL_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE_MASK 0x00000010L |
24655 | #define PA_SU_SMALL_PRIM_FILTER_CNTL__SC_1XMSAA_COMPATIBLE_DISABLE_MASK 0x00000040L |
24656 | //PA_CL_NGG_CNTL |
24657 | #define PA_CL_NGG_CNTL__VERTEX_REUSE_OFF__SHIFT 0x0 |
24658 | #define PA_CL_NGG_CNTL__INDEX_BUF_EDGE_FLAG_ENA__SHIFT 0x1 |
24659 | #define PA_CL_NGG_CNTL__VERTEX_REUSE_DEPTH__SHIFT 0x2 |
24660 | #define PA_CL_NGG_CNTL__VERTEX_REUSE_OFF_MASK 0x00000001L |
24661 | #define PA_CL_NGG_CNTL__INDEX_BUF_EDGE_FLAG_ENA_MASK 0x00000002L |
24662 | #define PA_CL_NGG_CNTL__VERTEX_REUSE_DEPTH_MASK 0x000003FCL |
24663 | //PA_SU_OVER_RASTERIZATION_CNTL |
24664 | #define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_TRIANGLES__SHIFT 0x0 |
24665 | #define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_LINES__SHIFT 0x1 |
24666 | #define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_POINTS__SHIFT 0x2 |
24667 | #define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_RECTANGLES__SHIFT 0x3 |
24668 | #define PA_SU_OVER_RASTERIZATION_CNTL__USE_PROVOKING_ZW__SHIFT 0x4 |
24669 | #define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_TRIANGLES_MASK 0x00000001L |
24670 | #define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_LINES_MASK 0x00000002L |
24671 | #define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_POINTS_MASK 0x00000004L |
24672 | #define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_RECTANGLES_MASK 0x00000008L |
24673 | #define PA_SU_OVER_RASTERIZATION_CNTL__USE_PROVOKING_ZW_MASK 0x00000010L |
24674 | //PA_STEREO_CNTL |
24675 | #define PA_STEREO_CNTL__STEREO_MODE__SHIFT 0x1 |
24676 | #define PA_STEREO_CNTL__RT_SLICE_MODE__SHIFT 0x5 |
24677 | #define PA_STEREO_CNTL__RT_SLICE_OFFSET__SHIFT 0x8 |
24678 | #define PA_STEREO_CNTL__VP_ID_MODE__SHIFT 0x10 |
24679 | #define PA_STEREO_CNTL__VP_ID_OFFSET__SHIFT 0x13 |
24680 | #define PA_STEREO_CNTL__FSR_MODE__SHIFT 0x18 |
24681 | #define PA_STEREO_CNTL__FSR_OFFSET__SHIFT 0x1a |
24682 | #define PA_STEREO_CNTL__STEREO_MODE_MASK 0x0000001EL |
24683 | #define PA_STEREO_CNTL__RT_SLICE_MODE_MASK 0x000000E0L |
24684 | #define PA_STEREO_CNTL__RT_SLICE_OFFSET_MASK 0x00000F00L |
24685 | #define PA_STEREO_CNTL__VP_ID_MODE_MASK 0x00070000L |
24686 | #define PA_STEREO_CNTL__VP_ID_OFFSET_MASK 0x00780000L |
24687 | #define PA_STEREO_CNTL__FSR_MODE_MASK 0x03000000L |
24688 | #define PA_STEREO_CNTL__FSR_OFFSET_MASK 0x0C000000L |
24689 | //PA_STATE_STEREO_X |
24690 | #define PA_STATE_STEREO_X__STEREO_X_OFFSET__SHIFT 0x0 |
24691 | #define PA_STATE_STEREO_X__STEREO_X_OFFSET_MASK 0xFFFFFFFFL |
24692 | //PA_CL_VRS_CNTL |
24693 | #define PA_CL_VRS_CNTL__VERTEX_RATE_COMBINER_MODE__SHIFT 0x0 |
24694 | #define PA_CL_VRS_CNTL__PRIMITIVE_RATE_COMBINER_MODE__SHIFT 0x3 |
24695 | #define PA_CL_VRS_CNTL__HTILE_RATE_COMBINER_MODE__SHIFT 0x6 |
24696 | #define PA_CL_VRS_CNTL__SAMPLE_ITER_COMBINER_MODE__SHIFT 0x9 |
24697 | #define PA_CL_VRS_CNTL__EXPOSE_VRS_PIXELS_MASK__SHIFT 0xd |
24698 | #define PA_CL_VRS_CNTL__CMASK_RATE_HINT_FORCE_ZERO__SHIFT 0xe |
24699 | #define PA_CL_VRS_CNTL__VERTEX_RATE_COMBINER_MODE_MASK 0x00000007L |
24700 | #define PA_CL_VRS_CNTL__PRIMITIVE_RATE_COMBINER_MODE_MASK 0x00000038L |
24701 | #define PA_CL_VRS_CNTL__HTILE_RATE_COMBINER_MODE_MASK 0x000001C0L |
24702 | #define PA_CL_VRS_CNTL__SAMPLE_ITER_COMBINER_MODE_MASK 0x00000E00L |
24703 | #define PA_CL_VRS_CNTL__EXPOSE_VRS_PIXELS_MASK_MASK 0x00002000L |
24704 | #define PA_CL_VRS_CNTL__CMASK_RATE_HINT_FORCE_ZERO_MASK 0x00004000L |
24705 | //PA_SU_POINT_SIZE |
24706 | #define PA_SU_POINT_SIZE__HEIGHT__SHIFT 0x0 |
24707 | #define PA_SU_POINT_SIZE__WIDTH__SHIFT 0x10 |
24708 | #define PA_SU_POINT_SIZE__HEIGHT_MASK 0x0000FFFFL |
24709 | #define PA_SU_POINT_SIZE__WIDTH_MASK 0xFFFF0000L |
24710 | //PA_SU_POINT_MINMAX |
24711 | #define PA_SU_POINT_MINMAX__MIN_SIZE__SHIFT 0x0 |
24712 | #define PA_SU_POINT_MINMAX__MAX_SIZE__SHIFT 0x10 |
24713 | #define PA_SU_POINT_MINMAX__MIN_SIZE_MASK 0x0000FFFFL |
24714 | #define PA_SU_POINT_MINMAX__MAX_SIZE_MASK 0xFFFF0000L |
24715 | //PA_SU_LINE_CNTL |
24716 | #define PA_SU_LINE_CNTL__WIDTH__SHIFT 0x0 |
24717 | #define PA_SU_LINE_CNTL__WIDTH_MASK 0x0000FFFFL |
24718 | //PA_SC_LINE_STIPPLE |
24719 | #define PA_SC_LINE_STIPPLE__LINE_PATTERN__SHIFT 0x0 |
24720 | #define PA_SC_LINE_STIPPLE__REPEAT_COUNT__SHIFT 0x10 |
24721 | #define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER__SHIFT 0x1c |
24722 | #define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL__SHIFT 0x1d |
24723 | #define PA_SC_LINE_STIPPLE__LINE_PATTERN_MASK 0x0000FFFFL |
24724 | #define PA_SC_LINE_STIPPLE__REPEAT_COUNT_MASK 0x00FF0000L |
24725 | #define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER_MASK 0x10000000L |
24726 | #define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL_MASK 0x60000000L |
24727 | //VGT_HOS_MAX_TESS_LEVEL |
24728 | #define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS__SHIFT 0x0 |
24729 | #define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS_MASK 0xFFFFFFFFL |
24730 | //VGT_HOS_MIN_TESS_LEVEL |
24731 | #define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS__SHIFT 0x0 |
24732 | #define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS_MASK 0xFFFFFFFFL |
24733 | //PA_SC_MODE_CNTL_0 |
24734 | #define PA_SC_MODE_CNTL_0__MSAA_ENABLE__SHIFT 0x0 |
24735 | #define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE__SHIFT 0x1 |
24736 | #define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE__SHIFT 0x2 |
24737 | #define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR__SHIFT 0x3 |
24738 | #define PA_SC_MODE_CNTL_0__ALTERNATE_RBS_PER_TILE__SHIFT 0x5 |
24739 | #define PA_SC_MODE_CNTL_0__COARSE_TILE_STARTS_ON_EVEN_RB__SHIFT 0x6 |
24740 | #define PA_SC_MODE_CNTL_0__MSAA_ENABLE_MASK 0x00000001L |
24741 | #define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE_MASK 0x00000002L |
24742 | #define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE_MASK 0x00000004L |
24743 | #define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR_MASK 0x00000008L |
24744 | #define PA_SC_MODE_CNTL_0__ALTERNATE_RBS_PER_TILE_MASK 0x00000020L |
24745 | #define PA_SC_MODE_CNTL_0__COARSE_TILE_STARTS_ON_EVEN_RB_MASK 0x00000040L |
24746 | //PA_SC_MODE_CNTL_1 |
24747 | #define PA_SC_MODE_CNTL_1__WALK_SIZE__SHIFT 0x0 |
24748 | #define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT__SHIFT 0x1 |
24749 | #define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST__SHIFT 0x2 |
24750 | #define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE__SHIFT 0x3 |
24751 | #define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE__SHIFT 0x4 |
24752 | #define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE__SHIFT 0x7 |
24753 | #define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE__SHIFT 0x8 |
24754 | #define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE__SHIFT 0x9 |
24755 | #define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR__SHIFT 0xa |
24756 | #define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT__SHIFT 0xb |
24757 | #define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET__SHIFT 0xc |
24758 | #define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT__SHIFT 0xd |
24759 | #define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z__SHIFT 0xe |
24760 | #define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK__SHIFT 0xf |
24761 | #define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE__SHIFT 0x10 |
24762 | #define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE__SHIFT 0x11 |
24763 | #define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE__SHIFT 0x12 |
24764 | #define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE__SHIFT 0x13 |
24765 | #define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE__SHIFT 0x14 |
24766 | #define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE__SHIFT 0x18 |
24767 | #define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE__SHIFT 0x19 |
24768 | #define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE__SHIFT 0x1a |
24769 | #define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE__SHIFT 0x1b |
24770 | #define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK__SHIFT 0x1c |
24771 | #define PA_SC_MODE_CNTL_1__WALK_SIZE_MASK 0x00000001L |
24772 | #define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT_MASK 0x00000002L |
24773 | #define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST_MASK 0x00000004L |
24774 | #define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE_MASK 0x00000008L |
24775 | #define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE_MASK 0x00000070L |
24776 | #define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE_MASK 0x00000080L |
24777 | #define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE_MASK 0x00000100L |
24778 | #define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE_MASK 0x00000200L |
24779 | #define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR_MASK 0x00000400L |
24780 | #define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT_MASK 0x00000800L |
24781 | #define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET_MASK 0x00001000L |
24782 | #define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT_MASK 0x00002000L |
24783 | #define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z_MASK 0x00004000L |
24784 | #define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK_MASK 0x00008000L |
24785 | #define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE_MASK 0x00010000L |
24786 | #define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE_MASK 0x00020000L |
24787 | #define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE_MASK 0x00040000L |
24788 | #define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE_MASK 0x00080000L |
24789 | #define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_MASK 0x00F00000L |
24790 | #define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE_MASK 0x01000000L |
24791 | #define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE_MASK 0x02000000L |
24792 | #define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE_MASK 0x04000000L |
24793 | #define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE_MASK 0x08000000L |
24794 | #define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK_MASK 0x70000000L |
24795 | //VGT_ENHANCE |
24796 | #define VGT_ENHANCE__MISC__SHIFT 0x0 |
24797 | #define VGT_ENHANCE__MISC_MASK 0xFFFFFFFFL |
24798 | //IA_ENHANCE |
24799 | #define IA_ENHANCE__MISC__SHIFT 0x0 |
24800 | #define IA_ENHANCE__MISC_MASK 0xFFFFFFFFL |
24801 | //VGT_DMA_SIZE |
24802 | #define VGT_DMA_SIZE__NUM_INDICES__SHIFT 0x0 |
24803 | #define VGT_DMA_SIZE__NUM_INDICES_MASK 0xFFFFFFFFL |
24804 | //VGT_DMA_MAX_SIZE |
24805 | #define VGT_DMA_MAX_SIZE__MAX_SIZE__SHIFT 0x0 |
24806 | #define VGT_DMA_MAX_SIZE__MAX_SIZE_MASK 0xFFFFFFFFL |
24807 | //VGT_DMA_INDEX_TYPE |
24808 | #define VGT_DMA_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0 |
24809 | #define VGT_DMA_INDEX_TYPE__SWAP_MODE__SHIFT 0x2 |
24810 | #define VGT_DMA_INDEX_TYPE__BUF_TYPE__SHIFT 0x4 |
24811 | #define VGT_DMA_INDEX_TYPE__RDREQ_POLICY__SHIFT 0x6 |
24812 | #define VGT_DMA_INDEX_TYPE__ATC__SHIFT 0x8 |
24813 | #define VGT_DMA_INDEX_TYPE__NOT_EOP__SHIFT 0x9 |
24814 | #define VGT_DMA_INDEX_TYPE__REQ_PATH__SHIFT 0xa |
24815 | #define VGT_DMA_INDEX_TYPE__MTYPE__SHIFT 0xb |
24816 | #define VGT_DMA_INDEX_TYPE__DISABLE_INSTANCE_PACKING__SHIFT 0xe |
24817 | #define VGT_DMA_INDEX_TYPE__INDEX_TYPE_MASK 0x00000003L |
24818 | #define VGT_DMA_INDEX_TYPE__SWAP_MODE_MASK 0x0000000CL |
24819 | #define VGT_DMA_INDEX_TYPE__BUF_TYPE_MASK 0x00000030L |
24820 | #define VGT_DMA_INDEX_TYPE__RDREQ_POLICY_MASK 0x000000C0L |
24821 | #define VGT_DMA_INDEX_TYPE__ATC_MASK 0x00000100L |
24822 | #define VGT_DMA_INDEX_TYPE__NOT_EOP_MASK 0x00000200L |
24823 | #define VGT_DMA_INDEX_TYPE__REQ_PATH_MASK 0x00000400L |
24824 | #define VGT_DMA_INDEX_TYPE__MTYPE_MASK 0x00003800L |
24825 | #define VGT_DMA_INDEX_TYPE__DISABLE_INSTANCE_PACKING_MASK 0x00004000L |
24826 | //WD_ENHANCE |
24827 | #define WD_ENHANCE__MISC__SHIFT 0x0 |
24828 | #define WD_ENHANCE__MISC_MASK 0xFFFFFFFFL |
24829 | //VGT_PRIMITIVEID_EN |
24830 | #define VGT_PRIMITIVEID_EN__PRIMITIVEID_EN__SHIFT 0x0 |
24831 | #define VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI__SHIFT 0x1 |
24832 | #define VGT_PRIMITIVEID_EN__NGG_DISABLE_PROVOK_REUSE__SHIFT 0x2 |
24833 | #define VGT_PRIMITIVEID_EN__PRIMITIVEID_EN_MASK 0x00000001L |
24834 | #define VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI_MASK 0x00000002L |
24835 | #define VGT_PRIMITIVEID_EN__NGG_DISABLE_PROVOK_REUSE_MASK 0x00000004L |
24836 | //VGT_DMA_NUM_INSTANCES |
24837 | #define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES__SHIFT 0x0 |
24838 | #define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES_MASK 0xFFFFFFFFL |
24839 | //VGT_PRIMITIVEID_RESET |
24840 | #define VGT_PRIMITIVEID_RESET__VALUE__SHIFT 0x0 |
24841 | #define VGT_PRIMITIVEID_RESET__VALUE_MASK 0xFFFFFFFFL |
24842 | //VGT_EVENT_INITIATOR |
24843 | #define VGT_EVENT_INITIATOR__EVENT_TYPE__SHIFT 0x0 |
24844 | #define VGT_EVENT_INITIATOR__ADDRESS_HI__SHIFT 0xa |
24845 | #define VGT_EVENT_INITIATOR__EXTENDED_EVENT__SHIFT 0x1b |
24846 | #define VGT_EVENT_INITIATOR__EVENT_TYPE_MASK 0x0000003FL |
24847 | #define VGT_EVENT_INITIATOR__ADDRESS_HI_MASK 0x07FFFC00L |
24848 | #define VGT_EVENT_INITIATOR__EXTENDED_EVENT_MASK 0x08000000L |
24849 | //VGT_DRAW_PAYLOAD_CNTL |
24850 | #define VGT_DRAW_PAYLOAD_CNTL__EN_REG_RT_INDEX__SHIFT 0x1 |
24851 | #define VGT_DRAW_PAYLOAD_CNTL__EN_PRIM_PAYLOAD__SHIFT 0x3 |
24852 | #define VGT_DRAW_PAYLOAD_CNTL__EN_DRAW_VP__SHIFT 0x4 |
24853 | #define VGT_DRAW_PAYLOAD_CNTL__EN_FSR__SHIFT 0x5 |
24854 | #define VGT_DRAW_PAYLOAD_CNTL__EN_VRS_RATE__SHIFT 0x6 |
24855 | #define VGT_DRAW_PAYLOAD_CNTL__EN_REG_RT_INDEX_MASK 0x00000002L |
24856 | #define VGT_DRAW_PAYLOAD_CNTL__EN_PRIM_PAYLOAD_MASK 0x00000008L |
24857 | #define VGT_DRAW_PAYLOAD_CNTL__EN_DRAW_VP_MASK 0x00000010L |
24858 | #define VGT_DRAW_PAYLOAD_CNTL__EN_FSR_MASK 0x00000020L |
24859 | #define VGT_DRAW_PAYLOAD_CNTL__EN_VRS_RATE_MASK 0x00000040L |
24860 | //VGT_ESGS_RING_ITEMSIZE |
24861 | #define VGT_ESGS_RING_ITEMSIZE__ITEMSIZE__SHIFT 0x0 |
24862 | #define VGT_ESGS_RING_ITEMSIZE__ITEMSIZE_MASK 0x00007FFFL |
24863 | //VGT_REUSE_OFF |
24864 | #define VGT_REUSE_OFF__REUSE_OFF__SHIFT 0x0 |
24865 | #define VGT_REUSE_OFF__REUSE_OFF_MASK 0x00000001L |
24866 | //DB_HTILE_SURFACE |
24867 | #define DB_HTILE_SURFACE__RESERVED_FIELD_1__SHIFT 0x0 |
24868 | #define DB_HTILE_SURFACE__FULL_CACHE__SHIFT 0x1 |
24869 | #define DB_HTILE_SURFACE__RESERVED_FIELD_2__SHIFT 0x2 |
24870 | #define DB_HTILE_SURFACE__RESERVED_FIELD_3__SHIFT 0x3 |
24871 | #define DB_HTILE_SURFACE__RESERVED_FIELD_4__SHIFT 0x4 |
24872 | #define DB_HTILE_SURFACE__RESERVED_FIELD_5__SHIFT 0xa |
24873 | #define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE__SHIFT 0x10 |
24874 | #define DB_HTILE_SURFACE__RESERVED_FIELD_6__SHIFT 0x11 |
24875 | #define DB_HTILE_SURFACE__PIPE_ALIGNED__SHIFT 0x12 |
24876 | #define DB_HTILE_SURFACE__RESERVED_FIELD_1_MASK 0x00000001L |
24877 | #define DB_HTILE_SURFACE__FULL_CACHE_MASK 0x00000002L |
24878 | #define DB_HTILE_SURFACE__RESERVED_FIELD_2_MASK 0x00000004L |
24879 | #define DB_HTILE_SURFACE__RESERVED_FIELD_3_MASK 0x00000008L |
24880 | #define DB_HTILE_SURFACE__RESERVED_FIELD_4_MASK 0x000003F0L |
24881 | #define DB_HTILE_SURFACE__RESERVED_FIELD_5_MASK 0x0000FC00L |
24882 | #define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE_MASK 0x00010000L |
24883 | #define DB_HTILE_SURFACE__RESERVED_FIELD_6_MASK 0x00020000L |
24884 | #define DB_HTILE_SURFACE__PIPE_ALIGNED_MASK 0x00040000L |
24885 | //DB_SRESULTS_COMPARE_STATE0 |
24886 | #define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0__SHIFT 0x0 |
24887 | #define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0__SHIFT 0x4 |
24888 | #define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0__SHIFT 0xc |
24889 | #define DB_SRESULTS_COMPARE_STATE0__ENABLE0__SHIFT 0x18 |
24890 | #define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0_MASK 0x00000007L |
24891 | #define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0_MASK 0x00000FF0L |
24892 | #define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0_MASK 0x000FF000L |
24893 | #define DB_SRESULTS_COMPARE_STATE0__ENABLE0_MASK 0x01000000L |
24894 | //DB_SRESULTS_COMPARE_STATE1 |
24895 | #define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1__SHIFT 0x0 |
24896 | #define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1__SHIFT 0x4 |
24897 | #define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1__SHIFT 0xc |
24898 | #define DB_SRESULTS_COMPARE_STATE1__ENABLE1__SHIFT 0x18 |
24899 | #define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1_MASK 0x00000007L |
24900 | #define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1_MASK 0x00000FF0L |
24901 | #define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1_MASK 0x000FF000L |
24902 | #define DB_SRESULTS_COMPARE_STATE1__ENABLE1_MASK 0x01000000L |
24903 | //DB_PRELOAD_CONTROL |
24904 | #define DB_PRELOAD_CONTROL__START_X__SHIFT 0x0 |
24905 | #define DB_PRELOAD_CONTROL__START_Y__SHIFT 0x8 |
24906 | #define DB_PRELOAD_CONTROL__MAX_X__SHIFT 0x10 |
24907 | #define DB_PRELOAD_CONTROL__MAX_Y__SHIFT 0x18 |
24908 | #define DB_PRELOAD_CONTROL__START_X_MASK 0x000000FFL |
24909 | #define DB_PRELOAD_CONTROL__START_Y_MASK 0x0000FF00L |
24910 | #define DB_PRELOAD_CONTROL__MAX_X_MASK 0x00FF0000L |
24911 | #define DB_PRELOAD_CONTROL__MAX_Y_MASK 0xFF000000L |
24912 | //VGT_STRMOUT_DRAW_OPAQUE_OFFSET |
24913 | #define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET__SHIFT 0x0 |
24914 | #define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET_MASK 0xFFFFFFFFL |
24915 | //VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE |
24916 | #define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE__SHIFT 0x0 |
24917 | #define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE_MASK 0xFFFFFFFFL |
24918 | //VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE |
24919 | #define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE__SHIFT 0x0 |
24920 | #define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE_MASK 0x000001FFL |
24921 | //VGT_GS_MAX_VERT_OUT |
24922 | #define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT__SHIFT 0x0 |
24923 | #define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT_MASK 0x000007FFL |
24924 | //GE_NGG_SUBGRP_CNTL |
24925 | #define GE_NGG_SUBGRP_CNTL__PRIM_AMP_FACTOR__SHIFT 0x0 |
24926 | #define GE_NGG_SUBGRP_CNTL__THDS_PER_SUBGRP__SHIFT 0x9 |
24927 | #define GE_NGG_SUBGRP_CNTL__PRIM_AMP_FACTOR_MASK 0x000001FFL |
24928 | #define GE_NGG_SUBGRP_CNTL__THDS_PER_SUBGRP_MASK 0x0003FE00L |
24929 | //VGT_TESS_DISTRIBUTION |
24930 | #define VGT_TESS_DISTRIBUTION__ACCUM_ISOLINE__SHIFT 0x0 |
24931 | #define VGT_TESS_DISTRIBUTION__ACCUM_TRI__SHIFT 0x8 |
24932 | #define VGT_TESS_DISTRIBUTION__ACCUM_QUAD__SHIFT 0x10 |
24933 | #define VGT_TESS_DISTRIBUTION__DONUT_SPLIT__SHIFT 0x18 |
24934 | #define VGT_TESS_DISTRIBUTION__TRAP_SPLIT__SHIFT 0x1d |
24935 | #define VGT_TESS_DISTRIBUTION__ACCUM_ISOLINE_MASK 0x000000FFL |
24936 | #define VGT_TESS_DISTRIBUTION__ACCUM_TRI_MASK 0x0000FF00L |
24937 | #define VGT_TESS_DISTRIBUTION__ACCUM_QUAD_MASK 0x00FF0000L |
24938 | #define VGT_TESS_DISTRIBUTION__DONUT_SPLIT_MASK 0x1F000000L |
24939 | #define VGT_TESS_DISTRIBUTION__TRAP_SPLIT_MASK 0xE0000000L |
24940 | //VGT_SHADER_STAGES_EN |
24941 | #define VGT_SHADER_STAGES_EN__LS_EN__SHIFT 0x0 |
24942 | #define VGT_SHADER_STAGES_EN__HS_EN__SHIFT 0x2 |
24943 | #define VGT_SHADER_STAGES_EN__ES_EN__SHIFT 0x3 |
24944 | #define VGT_SHADER_STAGES_EN__GS_EN__SHIFT 0x5 |
24945 | #define VGT_SHADER_STAGES_EN__VS_EN__SHIFT 0x6 |
24946 | #define VGT_SHADER_STAGES_EN__DYNAMIC_HS__SHIFT 0x8 |
24947 | #define VGT_SHADER_STAGES_EN__VS_WAVE_ID_EN__SHIFT 0xc |
24948 | #define VGT_SHADER_STAGES_EN__PRIMGEN_EN__SHIFT 0xd |
24949 | #define VGT_SHADER_STAGES_EN__ORDERED_ID_MODE__SHIFT 0xe |
24950 | #define VGT_SHADER_STAGES_EN__MAX_PRIMGRP_IN_WAVE__SHIFT 0xf |
24951 | #define VGT_SHADER_STAGES_EN__GS_FAST_LAUNCH__SHIFT 0x13 |
24952 | #define VGT_SHADER_STAGES_EN__HS_W32_EN__SHIFT 0x15 |
24953 | #define VGT_SHADER_STAGES_EN__GS_W32_EN__SHIFT 0x16 |
24954 | #define VGT_SHADER_STAGES_EN__VS_W32_EN__SHIFT 0x17 |
24955 | #define VGT_SHADER_STAGES_EN__NGG_WAVE_ID_EN__SHIFT 0x18 |
24956 | #define VGT_SHADER_STAGES_EN__PRIMGEN_PASSTHRU_EN__SHIFT 0x19 |
24957 | #define VGT_SHADER_STAGES_EN__PRIMGEN_PASSTHRU_NO_MSG__SHIFT 0x1a |
24958 | #define VGT_SHADER_STAGES_EN__LS_EN_MASK 0x00000003L |
24959 | #define VGT_SHADER_STAGES_EN__HS_EN_MASK 0x00000004L |
24960 | #define VGT_SHADER_STAGES_EN__ES_EN_MASK 0x00000018L |
24961 | #define VGT_SHADER_STAGES_EN__GS_EN_MASK 0x00000020L |
24962 | #define VGT_SHADER_STAGES_EN__VS_EN_MASK 0x000000C0L |
24963 | #define VGT_SHADER_STAGES_EN__DYNAMIC_HS_MASK 0x00000100L |
24964 | #define VGT_SHADER_STAGES_EN__VS_WAVE_ID_EN_MASK 0x00001000L |
24965 | #define VGT_SHADER_STAGES_EN__PRIMGEN_EN_MASK 0x00002000L |
24966 | #define VGT_SHADER_STAGES_EN__ORDERED_ID_MODE_MASK 0x00004000L |
24967 | #define VGT_SHADER_STAGES_EN__MAX_PRIMGRP_IN_WAVE_MASK 0x00078000L |
24968 | #define VGT_SHADER_STAGES_EN__GS_FAST_LAUNCH_MASK 0x00180000L |
24969 | #define VGT_SHADER_STAGES_EN__HS_W32_EN_MASK 0x00200000L |
24970 | #define VGT_SHADER_STAGES_EN__GS_W32_EN_MASK 0x00400000L |
24971 | #define VGT_SHADER_STAGES_EN__VS_W32_EN_MASK 0x00800000L |
24972 | #define VGT_SHADER_STAGES_EN__NGG_WAVE_ID_EN_MASK 0x01000000L |
24973 | #define VGT_SHADER_STAGES_EN__PRIMGEN_PASSTHRU_EN_MASK 0x02000000L |
24974 | #define VGT_SHADER_STAGES_EN__PRIMGEN_PASSTHRU_NO_MSG_MASK 0x04000000L |
24975 | //VGT_LS_HS_CONFIG |
24976 | #define VGT_LS_HS_CONFIG__NUM_PATCHES__SHIFT 0x0 |
24977 | #define VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT 0x8 |
24978 | #define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP__SHIFT 0xe |
24979 | #define VGT_LS_HS_CONFIG__NUM_PATCHES_MASK 0x000000FFL |
24980 | #define VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK 0x00003F00L |
24981 | #define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP_MASK 0x000FC000L |
24982 | //VGT_TF_PARAM |
24983 | #define VGT_TF_PARAM__TYPE__SHIFT 0x0 |
24984 | #define VGT_TF_PARAM__PARTITIONING__SHIFT 0x2 |
24985 | #define VGT_TF_PARAM__TOPOLOGY__SHIFT 0x5 |
24986 | #define VGT_TF_PARAM__RESERVED_REDUC_AXIS__SHIFT 0x8 |
24987 | #define VGT_TF_PARAM__NOT_USED__SHIFT 0x9 |
24988 | #define VGT_TF_PARAM__NUM_DS_WAVES_PER_SIMD__SHIFT 0xa |
24989 | #define VGT_TF_PARAM__DISABLE_DONUTS__SHIFT 0xe |
24990 | #define VGT_TF_PARAM__RDREQ_POLICY__SHIFT 0xf |
24991 | #define VGT_TF_PARAM__DISTRIBUTION_MODE__SHIFT 0x11 |
24992 | #define VGT_TF_PARAM__DETECT_ONE__SHIFT 0x13 |
24993 | #define VGT_TF_PARAM__DETECT_ZERO__SHIFT 0x14 |
24994 | #define VGT_TF_PARAM__MTYPE__SHIFT 0x17 |
24995 | #define VGT_TF_PARAM__TYPE_MASK 0x00000003L |
24996 | #define VGT_TF_PARAM__PARTITIONING_MASK 0x0000001CL |
24997 | #define VGT_TF_PARAM__TOPOLOGY_MASK 0x000000E0L |
24998 | #define VGT_TF_PARAM__RESERVED_REDUC_AXIS_MASK 0x00000100L |
24999 | #define VGT_TF_PARAM__NOT_USED_MASK 0x00000200L |
25000 | #define VGT_TF_PARAM__NUM_DS_WAVES_PER_SIMD_MASK 0x00003C00L |
25001 | #define VGT_TF_PARAM__DISABLE_DONUTS_MASK 0x00004000L |
25002 | #define VGT_TF_PARAM__RDREQ_POLICY_MASK 0x00018000L |
25003 | #define VGT_TF_PARAM__DISTRIBUTION_MODE_MASK 0x00060000L |
25004 | #define VGT_TF_PARAM__DETECT_ONE_MASK 0x00080000L |
25005 | #define VGT_TF_PARAM__DETECT_ZERO_MASK 0x00100000L |
25006 | #define VGT_TF_PARAM__MTYPE_MASK 0x03800000L |
25007 | //DB_ALPHA_TO_MASK |
25008 | #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE__SHIFT 0x0 |
25009 | #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0__SHIFT 0x8 |
25010 | #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1__SHIFT 0xa |
25011 | #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2__SHIFT 0xc |
25012 | #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3__SHIFT 0xe |
25013 | #define DB_ALPHA_TO_MASK__OFFSET_ROUND__SHIFT 0x10 |
25014 | #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE_MASK 0x00000001L |
25015 | #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0_MASK 0x00000300L |
25016 | #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1_MASK 0x00000C00L |
25017 | #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2_MASK 0x00003000L |
25018 | #define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3_MASK 0x0000C000L |
25019 | #define DB_ALPHA_TO_MASK__OFFSET_ROUND_MASK 0x00010000L |
25020 | //PA_SU_POLY_OFFSET_DB_FMT_CNTL |
25021 | #define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS__SHIFT 0x0 |
25022 | #define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT__SHIFT 0x8 |
25023 | #define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS_MASK 0x000000FFL |
25024 | #define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT_MASK 0x00000100L |
25025 | //PA_SU_POLY_OFFSET_CLAMP |
25026 | #define PA_SU_POLY_OFFSET_CLAMP__CLAMP__SHIFT 0x0 |
25027 | #define PA_SU_POLY_OFFSET_CLAMP__CLAMP_MASK 0xFFFFFFFFL |
25028 | //PA_SU_POLY_OFFSET_FRONT_SCALE |
25029 | #define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE__SHIFT 0x0 |
25030 | #define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE_MASK 0xFFFFFFFFL |
25031 | //PA_SU_POLY_OFFSET_FRONT_OFFSET |
25032 | #define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET__SHIFT 0x0 |
25033 | #define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET_MASK 0xFFFFFFFFL |
25034 | //PA_SU_POLY_OFFSET_BACK_SCALE |
25035 | #define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE__SHIFT 0x0 |
25036 | #define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE_MASK 0xFFFFFFFFL |
25037 | //PA_SU_POLY_OFFSET_BACK_OFFSET |
25038 | #define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET__SHIFT 0x0 |
25039 | #define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET_MASK 0xFFFFFFFFL |
25040 | //VGT_GS_INSTANCE_CNT |
25041 | #define VGT_GS_INSTANCE_CNT__ENABLE__SHIFT 0x0 |
25042 | #define VGT_GS_INSTANCE_CNT__CNT__SHIFT 0x2 |
25043 | #define VGT_GS_INSTANCE_CNT__EN_MAX_VERT_OUT_PER_GS_INSTANCE__SHIFT 0x1f |
25044 | #define VGT_GS_INSTANCE_CNT__ENABLE_MASK 0x00000001L |
25045 | #define VGT_GS_INSTANCE_CNT__CNT_MASK 0x000001FCL |
25046 | #define VGT_GS_INSTANCE_CNT__EN_MAX_VERT_OUT_PER_GS_INSTANCE_MASK 0x80000000L |
25047 | //PA_SC_CENTROID_PRIORITY_0 |
25048 | #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0__SHIFT 0x0 |
25049 | #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1__SHIFT 0x4 |
25050 | #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2__SHIFT 0x8 |
25051 | #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3__SHIFT 0xc |
25052 | #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4__SHIFT 0x10 |
25053 | #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5__SHIFT 0x14 |
25054 | #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6__SHIFT 0x18 |
25055 | #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7__SHIFT 0x1c |
25056 | #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0_MASK 0x0000000FL |
25057 | #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1_MASK 0x000000F0L |
25058 | #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2_MASK 0x00000F00L |
25059 | #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3_MASK 0x0000F000L |
25060 | #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4_MASK 0x000F0000L |
25061 | #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5_MASK 0x00F00000L |
25062 | #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6_MASK 0x0F000000L |
25063 | #define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7_MASK 0xF0000000L |
25064 | //PA_SC_CENTROID_PRIORITY_1 |
25065 | #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8__SHIFT 0x0 |
25066 | #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9__SHIFT 0x4 |
25067 | #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10__SHIFT 0x8 |
25068 | #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11__SHIFT 0xc |
25069 | #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12__SHIFT 0x10 |
25070 | #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13__SHIFT 0x14 |
25071 | #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14__SHIFT 0x18 |
25072 | #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15__SHIFT 0x1c |
25073 | #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8_MASK 0x0000000FL |
25074 | #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9_MASK 0x000000F0L |
25075 | #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10_MASK 0x00000F00L |
25076 | #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11_MASK 0x0000F000L |
25077 | #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12_MASK 0x000F0000L |
25078 | #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13_MASK 0x00F00000L |
25079 | #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14_MASK 0x0F000000L |
25080 | #define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15_MASK 0xF0000000L |
25081 | //PA_SC_LINE_CNTL |
25082 | #define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH__SHIFT 0x9 |
25083 | #define PA_SC_LINE_CNTL__LAST_PIXEL__SHIFT 0xa |
25084 | #define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA__SHIFT 0xb |
25085 | #define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA__SHIFT 0xc |
25086 | #define 0xd |
25087 | #define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH_MASK 0x00000200L |
25088 | #define PA_SC_LINE_CNTL__LAST_PIXEL_MASK 0x00000400L |
25089 | #define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA_MASK 0x00000800L |
25090 | #define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA_MASK 0x00001000L |
25091 | #define 0x00002000L |
25092 | //PA_SC_AA_CONFIG |
25093 | #define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES__SHIFT 0x0 |
25094 | #define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN__SHIFT 0x4 |
25095 | #define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST__SHIFT 0xd |
25096 | #define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES__SHIFT 0x14 |
25097 | #define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE__SHIFT 0x18 |
25098 | #define PA_SC_AA_CONFIG__COVERAGE_TO_SHADER_SELECT__SHIFT 0x1a |
25099 | #define PA_SC_AA_CONFIG__SAMPLE_COVERAGE_ENCODING__SHIFT 0x1c |
25100 | #define PA_SC_AA_CONFIG__COVERED_CENTROID_IS_CENTER__SHIFT 0x1d |
25101 | #define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES_MASK 0x00000007L |
25102 | #define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN_MASK 0x00000010L |
25103 | #define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST_MASK 0x0001E000L |
25104 | #define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES_MASK 0x00700000L |
25105 | #define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE_MASK 0x03000000L |
25106 | #define PA_SC_AA_CONFIG__COVERAGE_TO_SHADER_SELECT_MASK 0x0C000000L |
25107 | #define PA_SC_AA_CONFIG__SAMPLE_COVERAGE_ENCODING_MASK 0x10000000L |
25108 | #define PA_SC_AA_CONFIG__COVERED_CENTROID_IS_CENTER_MASK 0x20000000L |
25109 | //PA_SU_VTX_CNTL |
25110 | #define PA_SU_VTX_CNTL__PIX_CENTER__SHIFT 0x0 |
25111 | #define PA_SU_VTX_CNTL__ROUND_MODE__SHIFT 0x1 |
25112 | #define PA_SU_VTX_CNTL__QUANT_MODE__SHIFT 0x3 |
25113 | #define PA_SU_VTX_CNTL__PIX_CENTER_MASK 0x00000001L |
25114 | #define PA_SU_VTX_CNTL__ROUND_MODE_MASK 0x00000006L |
25115 | #define PA_SU_VTX_CNTL__QUANT_MODE_MASK 0x00000038L |
25116 | //PA_CL_GB_VERT_CLIP_ADJ |
25117 | #define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER__SHIFT 0x0 |
25118 | #define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER_MASK 0xFFFFFFFFL |
25119 | //PA_CL_GB_VERT_DISC_ADJ |
25120 | #define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER__SHIFT 0x0 |
25121 | #define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER_MASK 0xFFFFFFFFL |
25122 | //PA_CL_GB_HORZ_CLIP_ADJ |
25123 | #define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER__SHIFT 0x0 |
25124 | #define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER_MASK 0xFFFFFFFFL |
25125 | //PA_CL_GB_HORZ_DISC_ADJ |
25126 | #define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER__SHIFT 0x0 |
25127 | #define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER_MASK 0xFFFFFFFFL |
25128 | //PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 |
25129 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X__SHIFT 0x0 |
25130 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y__SHIFT 0x4 |
25131 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X__SHIFT 0x8 |
25132 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y__SHIFT 0xc |
25133 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X__SHIFT 0x10 |
25134 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y__SHIFT 0x14 |
25135 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X__SHIFT 0x18 |
25136 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y__SHIFT 0x1c |
25137 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X_MASK 0x0000000FL |
25138 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y_MASK 0x000000F0L |
25139 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X_MASK 0x00000F00L |
25140 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y_MASK 0x0000F000L |
25141 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X_MASK 0x000F0000L |
25142 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y_MASK 0x00F00000L |
25143 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X_MASK 0x0F000000L |
25144 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y_MASK 0xF0000000L |
25145 | //PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 |
25146 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X__SHIFT 0x0 |
25147 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y__SHIFT 0x4 |
25148 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X__SHIFT 0x8 |
25149 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y__SHIFT 0xc |
25150 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X__SHIFT 0x10 |
25151 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y__SHIFT 0x14 |
25152 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X__SHIFT 0x18 |
25153 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y__SHIFT 0x1c |
25154 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X_MASK 0x0000000FL |
25155 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y_MASK 0x000000F0L |
25156 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X_MASK 0x00000F00L |
25157 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y_MASK 0x0000F000L |
25158 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X_MASK 0x000F0000L |
25159 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y_MASK 0x00F00000L |
25160 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X_MASK 0x0F000000L |
25161 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y_MASK 0xF0000000L |
25162 | //PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 |
25163 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X__SHIFT 0x0 |
25164 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y__SHIFT 0x4 |
25165 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X__SHIFT 0x8 |
25166 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y__SHIFT 0xc |
25167 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X__SHIFT 0x10 |
25168 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y__SHIFT 0x14 |
25169 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X__SHIFT 0x18 |
25170 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y__SHIFT 0x1c |
25171 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X_MASK 0x0000000FL |
25172 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y_MASK 0x000000F0L |
25173 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X_MASK 0x00000F00L |
25174 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y_MASK 0x0000F000L |
25175 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X_MASK 0x000F0000L |
25176 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y_MASK 0x00F00000L |
25177 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X_MASK 0x0F000000L |
25178 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y_MASK 0xF0000000L |
25179 | //PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 |
25180 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X__SHIFT 0x0 |
25181 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y__SHIFT 0x4 |
25182 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X__SHIFT 0x8 |
25183 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y__SHIFT 0xc |
25184 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X__SHIFT 0x10 |
25185 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y__SHIFT 0x14 |
25186 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X__SHIFT 0x18 |
25187 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y__SHIFT 0x1c |
25188 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X_MASK 0x0000000FL |
25189 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y_MASK 0x000000F0L |
25190 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X_MASK 0x00000F00L |
25191 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y_MASK 0x0000F000L |
25192 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X_MASK 0x000F0000L |
25193 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y_MASK 0x00F00000L |
25194 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X_MASK 0x0F000000L |
25195 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y_MASK 0xF0000000L |
25196 | //PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 |
25197 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X__SHIFT 0x0 |
25198 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y__SHIFT 0x4 |
25199 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X__SHIFT 0x8 |
25200 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y__SHIFT 0xc |
25201 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X__SHIFT 0x10 |
25202 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y__SHIFT 0x14 |
25203 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X__SHIFT 0x18 |
25204 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y__SHIFT 0x1c |
25205 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X_MASK 0x0000000FL |
25206 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y_MASK 0x000000F0L |
25207 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X_MASK 0x00000F00L |
25208 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y_MASK 0x0000F000L |
25209 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X_MASK 0x000F0000L |
25210 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y_MASK 0x00F00000L |
25211 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X_MASK 0x0F000000L |
25212 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y_MASK 0xF0000000L |
25213 | //PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 |
25214 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X__SHIFT 0x0 |
25215 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y__SHIFT 0x4 |
25216 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X__SHIFT 0x8 |
25217 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y__SHIFT 0xc |
25218 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X__SHIFT 0x10 |
25219 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y__SHIFT 0x14 |
25220 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X__SHIFT 0x18 |
25221 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y__SHIFT 0x1c |
25222 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X_MASK 0x0000000FL |
25223 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y_MASK 0x000000F0L |
25224 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X_MASK 0x00000F00L |
25225 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y_MASK 0x0000F000L |
25226 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X_MASK 0x000F0000L |
25227 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y_MASK 0x00F00000L |
25228 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X_MASK 0x0F000000L |
25229 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y_MASK 0xF0000000L |
25230 | //PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 |
25231 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X__SHIFT 0x0 |
25232 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y__SHIFT 0x4 |
25233 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X__SHIFT 0x8 |
25234 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y__SHIFT 0xc |
25235 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X__SHIFT 0x10 |
25236 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y__SHIFT 0x14 |
25237 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X__SHIFT 0x18 |
25238 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y__SHIFT 0x1c |
25239 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X_MASK 0x0000000FL |
25240 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y_MASK 0x000000F0L |
25241 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X_MASK 0x00000F00L |
25242 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y_MASK 0x0000F000L |
25243 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X_MASK 0x000F0000L |
25244 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y_MASK 0x00F00000L |
25245 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X_MASK 0x0F000000L |
25246 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y_MASK 0xF0000000L |
25247 | //PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 |
25248 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X__SHIFT 0x0 |
25249 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y__SHIFT 0x4 |
25250 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X__SHIFT 0x8 |
25251 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y__SHIFT 0xc |
25252 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X__SHIFT 0x10 |
25253 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y__SHIFT 0x14 |
25254 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X__SHIFT 0x18 |
25255 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y__SHIFT 0x1c |
25256 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X_MASK 0x0000000FL |
25257 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y_MASK 0x000000F0L |
25258 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X_MASK 0x00000F00L |
25259 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y_MASK 0x0000F000L |
25260 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X_MASK 0x000F0000L |
25261 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y_MASK 0x00F00000L |
25262 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X_MASK 0x0F000000L |
25263 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y_MASK 0xF0000000L |
25264 | //PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 |
25265 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X__SHIFT 0x0 |
25266 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y__SHIFT 0x4 |
25267 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X__SHIFT 0x8 |
25268 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y__SHIFT 0xc |
25269 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X__SHIFT 0x10 |
25270 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y__SHIFT 0x14 |
25271 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X__SHIFT 0x18 |
25272 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y__SHIFT 0x1c |
25273 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X_MASK 0x0000000FL |
25274 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y_MASK 0x000000F0L |
25275 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X_MASK 0x00000F00L |
25276 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y_MASK 0x0000F000L |
25277 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X_MASK 0x000F0000L |
25278 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y_MASK 0x00F00000L |
25279 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X_MASK 0x0F000000L |
25280 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y_MASK 0xF0000000L |
25281 | //PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 |
25282 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X__SHIFT 0x0 |
25283 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y__SHIFT 0x4 |
25284 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X__SHIFT 0x8 |
25285 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y__SHIFT 0xc |
25286 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X__SHIFT 0x10 |
25287 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y__SHIFT 0x14 |
25288 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X__SHIFT 0x18 |
25289 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y__SHIFT 0x1c |
25290 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X_MASK 0x0000000FL |
25291 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y_MASK 0x000000F0L |
25292 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X_MASK 0x00000F00L |
25293 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y_MASK 0x0000F000L |
25294 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X_MASK 0x000F0000L |
25295 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y_MASK 0x00F00000L |
25296 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X_MASK 0x0F000000L |
25297 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y_MASK 0xF0000000L |
25298 | //PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 |
25299 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X__SHIFT 0x0 |
25300 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y__SHIFT 0x4 |
25301 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X__SHIFT 0x8 |
25302 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y__SHIFT 0xc |
25303 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X__SHIFT 0x10 |
25304 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y__SHIFT 0x14 |
25305 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X__SHIFT 0x18 |
25306 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y__SHIFT 0x1c |
25307 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X_MASK 0x0000000FL |
25308 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y_MASK 0x000000F0L |
25309 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X_MASK 0x00000F00L |
25310 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y_MASK 0x0000F000L |
25311 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X_MASK 0x000F0000L |
25312 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y_MASK 0x00F00000L |
25313 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X_MASK 0x0F000000L |
25314 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y_MASK 0xF0000000L |
25315 | //PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 |
25316 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X__SHIFT 0x0 |
25317 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y__SHIFT 0x4 |
25318 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X__SHIFT 0x8 |
25319 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y__SHIFT 0xc |
25320 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X__SHIFT 0x10 |
25321 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y__SHIFT 0x14 |
25322 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X__SHIFT 0x18 |
25323 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y__SHIFT 0x1c |
25324 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X_MASK 0x0000000FL |
25325 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y_MASK 0x000000F0L |
25326 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X_MASK 0x00000F00L |
25327 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y_MASK 0x0000F000L |
25328 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X_MASK 0x000F0000L |
25329 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y_MASK 0x00F00000L |
25330 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X_MASK 0x0F000000L |
25331 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y_MASK 0xF0000000L |
25332 | //PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 |
25333 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X__SHIFT 0x0 |
25334 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y__SHIFT 0x4 |
25335 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X__SHIFT 0x8 |
25336 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y__SHIFT 0xc |
25337 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X__SHIFT 0x10 |
25338 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y__SHIFT 0x14 |
25339 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X__SHIFT 0x18 |
25340 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y__SHIFT 0x1c |
25341 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X_MASK 0x0000000FL |
25342 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y_MASK 0x000000F0L |
25343 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X_MASK 0x00000F00L |
25344 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y_MASK 0x0000F000L |
25345 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X_MASK 0x000F0000L |
25346 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y_MASK 0x00F00000L |
25347 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X_MASK 0x0F000000L |
25348 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y_MASK 0xF0000000L |
25349 | //PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 |
25350 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X__SHIFT 0x0 |
25351 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y__SHIFT 0x4 |
25352 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X__SHIFT 0x8 |
25353 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y__SHIFT 0xc |
25354 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X__SHIFT 0x10 |
25355 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y__SHIFT 0x14 |
25356 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X__SHIFT 0x18 |
25357 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y__SHIFT 0x1c |
25358 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X_MASK 0x0000000FL |
25359 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y_MASK 0x000000F0L |
25360 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X_MASK 0x00000F00L |
25361 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y_MASK 0x0000F000L |
25362 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X_MASK 0x000F0000L |
25363 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y_MASK 0x00F00000L |
25364 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X_MASK 0x0F000000L |
25365 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y_MASK 0xF0000000L |
25366 | //PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 |
25367 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X__SHIFT 0x0 |
25368 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y__SHIFT 0x4 |
25369 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X__SHIFT 0x8 |
25370 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y__SHIFT 0xc |
25371 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X__SHIFT 0x10 |
25372 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y__SHIFT 0x14 |
25373 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X__SHIFT 0x18 |
25374 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y__SHIFT 0x1c |
25375 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X_MASK 0x0000000FL |
25376 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y_MASK 0x000000F0L |
25377 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X_MASK 0x00000F00L |
25378 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y_MASK 0x0000F000L |
25379 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X_MASK 0x000F0000L |
25380 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y_MASK 0x00F00000L |
25381 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X_MASK 0x0F000000L |
25382 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y_MASK 0xF0000000L |
25383 | //PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 |
25384 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X__SHIFT 0x0 |
25385 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y__SHIFT 0x4 |
25386 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X__SHIFT 0x8 |
25387 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y__SHIFT 0xc |
25388 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X__SHIFT 0x10 |
25389 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y__SHIFT 0x14 |
25390 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X__SHIFT 0x18 |
25391 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y__SHIFT 0x1c |
25392 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X_MASK 0x0000000FL |
25393 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y_MASK 0x000000F0L |
25394 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X_MASK 0x00000F00L |
25395 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y_MASK 0x0000F000L |
25396 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X_MASK 0x000F0000L |
25397 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y_MASK 0x00F00000L |
25398 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X_MASK 0x0F000000L |
25399 | #define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y_MASK 0xF0000000L |
25400 | //PA_SC_AA_MASK_X0Y0_X1Y0 |
25401 | #define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0__SHIFT 0x0 |
25402 | #define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0__SHIFT 0x10 |
25403 | #define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0_MASK 0x0000FFFFL |
25404 | #define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0_MASK 0xFFFF0000L |
25405 | //PA_SC_AA_MASK_X0Y1_X1Y1 |
25406 | #define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1__SHIFT 0x0 |
25407 | #define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1__SHIFT 0x10 |
25408 | #define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1_MASK 0x0000FFFFL |
25409 | #define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1_MASK 0xFFFF0000L |
25410 | //PA_SC_SHADER_CONTROL |
25411 | #define PA_SC_SHADER_CONTROL__REALIGN_DQUADS_AFTER_N_WAVES__SHIFT 0x0 |
25412 | #define PA_SC_SHADER_CONTROL__LOAD_COLLISION_WAVEID__SHIFT 0x2 |
25413 | #define PA_SC_SHADER_CONTROL__LOAD_INTRAWAVE_COLLISION__SHIFT 0x3 |
25414 | #define PA_SC_SHADER_CONTROL__WAVE_BREAK_REGION_SIZE__SHIFT 0x5 |
25415 | #define PA_SC_SHADER_CONTROL__DISABLE_OREO_CONFLICT_QUAD__SHIFT 0x7 |
25416 | #define PA_SC_SHADER_CONTROL__REALIGN_DQUADS_AFTER_N_WAVES_MASK 0x00000003L |
25417 | #define PA_SC_SHADER_CONTROL__LOAD_COLLISION_WAVEID_MASK 0x00000004L |
25418 | #define PA_SC_SHADER_CONTROL__LOAD_INTRAWAVE_COLLISION_MASK 0x00000008L |
25419 | #define PA_SC_SHADER_CONTROL__WAVE_BREAK_REGION_SIZE_MASK 0x00000060L |
25420 | #define PA_SC_SHADER_CONTROL__DISABLE_OREO_CONFLICT_QUAD_MASK 0x00000080L |
25421 | //PA_SC_BINNER_CNTL_0 |
25422 | #define PA_SC_BINNER_CNTL_0__BINNING_MODE__SHIFT 0x0 |
25423 | #define PA_SC_BINNER_CNTL_0__BIN_SIZE_X__SHIFT 0x2 |
25424 | #define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y__SHIFT 0x3 |
25425 | #define PA_SC_BINNER_CNTL_0__BIN_SIZE_X_EXTEND__SHIFT 0x4 |
25426 | #define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_EXTEND__SHIFT 0x7 |
25427 | #define PA_SC_BINNER_CNTL_0__CONTEXT_STATES_PER_BIN__SHIFT 0xa |
25428 | #define PA_SC_BINNER_CNTL_0__PERSISTENT_STATES_PER_BIN__SHIFT 0xd |
25429 | #define PA_SC_BINNER_CNTL_0__DISABLE_START_OF_PRIM__SHIFT 0x12 |
25430 | #define PA_SC_BINNER_CNTL_0__FPOVS_PER_BATCH__SHIFT 0x13 |
25431 | #define PA_SC_BINNER_CNTL_0__OPTIMAL_BIN_SELECTION__SHIFT 0x1b |
25432 | #define PA_SC_BINNER_CNTL_0__FLUSH_ON_BINNING_TRANSITION__SHIFT 0x1c |
25433 | #define PA_SC_BINNER_CNTL_0__BIN_MAPPING_MODE__SHIFT 0x1d |
25434 | #define PA_SC_BINNER_CNTL_0__FSR_EXPANSION_ENABLE__SHIFT 0x1f |
25435 | #define PA_SC_BINNER_CNTL_0__BINNING_MODE_MASK 0x00000003L |
25436 | #define PA_SC_BINNER_CNTL_0__BIN_SIZE_X_MASK 0x00000004L |
25437 | #define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_MASK 0x00000008L |
25438 | #define PA_SC_BINNER_CNTL_0__BIN_SIZE_X_EXTEND_MASK 0x00000070L |
25439 | #define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_EXTEND_MASK 0x00000380L |
25440 | #define PA_SC_BINNER_CNTL_0__CONTEXT_STATES_PER_BIN_MASK 0x00001C00L |
25441 | #define PA_SC_BINNER_CNTL_0__PERSISTENT_STATES_PER_BIN_MASK 0x0003E000L |
25442 | #define PA_SC_BINNER_CNTL_0__DISABLE_START_OF_PRIM_MASK 0x00040000L |
25443 | #define PA_SC_BINNER_CNTL_0__FPOVS_PER_BATCH_MASK 0x07F80000L |
25444 | #define PA_SC_BINNER_CNTL_0__OPTIMAL_BIN_SELECTION_MASK 0x08000000L |
25445 | #define PA_SC_BINNER_CNTL_0__FLUSH_ON_BINNING_TRANSITION_MASK 0x10000000L |
25446 | #define PA_SC_BINNER_CNTL_0__BIN_MAPPING_MODE_MASK 0x60000000L |
25447 | #define PA_SC_BINNER_CNTL_0__FSR_EXPANSION_ENABLE_MASK 0x80000000L |
25448 | //PA_SC_BINNER_CNTL_1 |
25449 | #define PA_SC_BINNER_CNTL_1__MAX_ALLOC_COUNT__SHIFT 0x0 |
25450 | #define PA_SC_BINNER_CNTL_1__MAX_PRIM_PER_BATCH__SHIFT 0x10 |
25451 | #define PA_SC_BINNER_CNTL_1__MAX_ALLOC_COUNT_MASK 0x0000FFFFL |
25452 | #define PA_SC_BINNER_CNTL_1__MAX_PRIM_PER_BATCH_MASK 0xFFFF0000L |
25453 | //PA_SC_CONSERVATIVE_RASTERIZATION_CNTL |
25454 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_ENABLE__SHIFT 0x0 |
25455 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_SAMPLE_SELECT__SHIFT 0x1 |
25456 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_ENABLE__SHIFT 0x5 |
25457 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_SAMPLE_SELECT__SHIFT 0x6 |
25458 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PBB_UNCERTAINTY_REGION_ENABLE__SHIFT 0xa |
25459 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_EXTENT__SHIFT 0xb |
25460 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_OFFSET__SHIFT 0xc |
25461 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_OVER_RAST_INNER_TO_NORMAL__SHIFT 0xd |
25462 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_UNDER_RAST_INNER_TO_NORMAL__SHIFT 0xe |
25463 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__DEGENERATE_OVERRIDE_INNER_TO_NORMAL_DISABLE__SHIFT 0xf |
25464 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_MODE__SHIFT 0x10 |
25465 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OUTER_UNCERTAINTY_EDGERULE_OVERRIDE__SHIFT 0x12 |
25466 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__INNER_UNCERTAINTY_EDGERULE_OVERRIDE__SHIFT 0x13 |
25467 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__NULL_SQUAD_AA_MASK_ENABLE__SHIFT 0x14 |
25468 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__COVERAGE_AA_MASK_ENABLE__SHIFT 0x15 |
25469 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PREZ_AA_MASK_ENABLE__SHIFT 0x16 |
25470 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__POSTZ_AA_MASK_ENABLE__SHIFT 0x17 |
25471 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__CENTROID_SAMPLE_OVERRIDE__SHIFT 0x18 |
25472 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_MULT__SHIFT 0x19 |
25473 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_PBB_MULT__SHIFT 0x1b |
25474 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_ENABLE_MASK 0x00000001L |
25475 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_SAMPLE_SELECT_MASK 0x0000001EL |
25476 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_ENABLE_MASK 0x00000020L |
25477 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_SAMPLE_SELECT_MASK 0x000003C0L |
25478 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PBB_UNCERTAINTY_REGION_ENABLE_MASK 0x00000400L |
25479 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_EXTENT_MASK 0x00000800L |
25480 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_OFFSET_MASK 0x00001000L |
25481 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_OVER_RAST_INNER_TO_NORMAL_MASK 0x00002000L |
25482 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_UNDER_RAST_INNER_TO_NORMAL_MASK 0x00004000L |
25483 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__DEGENERATE_OVERRIDE_INNER_TO_NORMAL_DISABLE_MASK 0x00008000L |
25484 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_MODE_MASK 0x00030000L |
25485 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OUTER_UNCERTAINTY_EDGERULE_OVERRIDE_MASK 0x00040000L |
25486 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__INNER_UNCERTAINTY_EDGERULE_OVERRIDE_MASK 0x00080000L |
25487 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__NULL_SQUAD_AA_MASK_ENABLE_MASK 0x00100000L |
25488 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__COVERAGE_AA_MASK_ENABLE_MASK 0x00200000L |
25489 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PREZ_AA_MASK_ENABLE_MASK 0x00400000L |
25490 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__POSTZ_AA_MASK_ENABLE_MASK 0x00800000L |
25491 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__CENTROID_SAMPLE_OVERRIDE_MASK 0x01000000L |
25492 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_MULT_MASK 0x06000000L |
25493 | #define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_PBB_MULT_MASK 0x18000000L |
25494 | //PA_SC_NGG_MODE_CNTL |
25495 | #define PA_SC_NGG_MODE_CNTL__MAX_DEALLOCS_IN_WAVE__SHIFT 0x0 |
25496 | #define PA_SC_NGG_MODE_CNTL__DISABLE_FPOG_AND_DEALLOC_CONFLICT__SHIFT 0xc |
25497 | #define PA_SC_NGG_MODE_CNTL__DISABLE_MAX_DEALLOC__SHIFT 0xd |
25498 | #define PA_SC_NGG_MODE_CNTL__DISABLE_MAX_ATTRIBUTES__SHIFT 0xe |
25499 | #define PA_SC_NGG_MODE_CNTL__MAX_FPOVS_IN_WAVE__SHIFT 0x10 |
25500 | #define PA_SC_NGG_MODE_CNTL__MAX_ATTRIBUTES_IN_WAVE__SHIFT 0x18 |
25501 | #define PA_SC_NGG_MODE_CNTL__MAX_DEALLOCS_IN_WAVE_MASK 0x000007FFL |
25502 | #define PA_SC_NGG_MODE_CNTL__DISABLE_FPOG_AND_DEALLOC_CONFLICT_MASK 0x00001000L |
25503 | #define PA_SC_NGG_MODE_CNTL__DISABLE_MAX_DEALLOC_MASK 0x00002000L |
25504 | #define PA_SC_NGG_MODE_CNTL__DISABLE_MAX_ATTRIBUTES_MASK 0x00004000L |
25505 | #define PA_SC_NGG_MODE_CNTL__MAX_FPOVS_IN_WAVE_MASK 0x00FF0000L |
25506 | #define PA_SC_NGG_MODE_CNTL__MAX_ATTRIBUTES_IN_WAVE_MASK 0xFF000000L |
25507 | //PA_SC_BINNER_CNTL_2 |
25508 | #define PA_SC_BINNER_CNTL_2__BIN_SIZE_X_MULT_BY_1P5X__SHIFT 0x0 |
25509 | #define PA_SC_BINNER_CNTL_2__BIN_SIZE_Y_MULT_BY_1P5X__SHIFT 0x1 |
25510 | #define PA_SC_BINNER_CNTL_2__ENABLE_LIGHT_VOLUME_RENDERING_OPTIMIZATION__SHIFT 0x2 |
25511 | #define PA_SC_BINNER_CNTL_2__DUAL_LIGHT_SHAFT_IN_DRAW__SHIFT 0x3 |
25512 | #define PA_SC_BINNER_CNTL_2__LIGHT_SHAFT_DRAW_CALL_LIMIT__SHIFT 0x4 |
25513 | #define PA_SC_BINNER_CNTL_2__CONTEXT_DONE_EVENTS_PER_BIN__SHIFT 0x7 |
25514 | #define PA_SC_BINNER_CNTL_2__ZPP_ENABLED__SHIFT 0xb |
25515 | #define PA_SC_BINNER_CNTL_2__ZPP_OPTIMIZATION_ENABLED__SHIFT 0xc |
25516 | #define PA_SC_BINNER_CNTL_2__ZPP_AREA_THRESHOLD__SHIFT 0xd |
25517 | #define PA_SC_BINNER_CNTL_2__DISABLE_NOPCEXPORT_BREAKBATCH_CONDITION__SHIFT 0x15 |
25518 | #define PA_SC_BINNER_CNTL_2__BIN_SIZE_X_MULT_BY_1P5X_MASK 0x00000001L |
25519 | #define PA_SC_BINNER_CNTL_2__BIN_SIZE_Y_MULT_BY_1P5X_MASK 0x00000002L |
25520 | #define PA_SC_BINNER_CNTL_2__ENABLE_LIGHT_VOLUME_RENDERING_OPTIMIZATION_MASK 0x00000004L |
25521 | #define PA_SC_BINNER_CNTL_2__DUAL_LIGHT_SHAFT_IN_DRAW_MASK 0x00000008L |
25522 | #define PA_SC_BINNER_CNTL_2__LIGHT_SHAFT_DRAW_CALL_LIMIT_MASK 0x00000070L |
25523 | #define PA_SC_BINNER_CNTL_2__CONTEXT_DONE_EVENTS_PER_BIN_MASK 0x00000780L |
25524 | #define PA_SC_BINNER_CNTL_2__ZPP_ENABLED_MASK 0x00000800L |
25525 | #define PA_SC_BINNER_CNTL_2__ZPP_OPTIMIZATION_ENABLED_MASK 0x00001000L |
25526 | #define PA_SC_BINNER_CNTL_2__ZPP_AREA_THRESHOLD_MASK 0x001FE000L |
25527 | #define PA_SC_BINNER_CNTL_2__DISABLE_NOPCEXPORT_BREAKBATCH_CONDITION_MASK 0x00200000L |
25528 | //CB_COLOR0_BASE |
25529 | #define CB_COLOR0_BASE__BASE_256B__SHIFT 0x0 |
25530 | #define CB_COLOR0_BASE__BASE_256B_MASK 0xFFFFFFFFL |
25531 | //CB_COLOR0_VIEW |
25532 | #define CB_COLOR0_VIEW__SLICE_START__SHIFT 0x0 |
25533 | #define CB_COLOR0_VIEW__SLICE_MAX__SHIFT 0xd |
25534 | #define CB_COLOR0_VIEW__MIP_LEVEL__SHIFT 0x1a |
25535 | #define CB_COLOR0_VIEW__SLICE_START_MASK 0x00001FFFL |
25536 | #define CB_COLOR0_VIEW__SLICE_MAX_MASK 0x03FFE000L |
25537 | #define CB_COLOR0_VIEW__MIP_LEVEL_MASK 0x3C000000L |
25538 | //CB_COLOR0_INFO |
25539 | #define CB_COLOR0_INFO__FORMAT__SHIFT 0x0 |
25540 | #define CB_COLOR0_INFO__LINEAR_GENERAL__SHIFT 0x7 |
25541 | #define CB_COLOR0_INFO__NUMBER_TYPE__SHIFT 0x8 |
25542 | #define CB_COLOR0_INFO__COMP_SWAP__SHIFT 0xb |
25543 | #define CB_COLOR0_INFO__BLEND_CLAMP__SHIFT 0xf |
25544 | #define CB_COLOR0_INFO__BLEND_BYPASS__SHIFT 0x10 |
25545 | #define CB_COLOR0_INFO__SIMPLE_FLOAT__SHIFT 0x11 |
25546 | #define CB_COLOR0_INFO__ROUND_MODE__SHIFT 0x12 |
25547 | #define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 |
25548 | #define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 |
25549 | #define CB_COLOR0_INFO__FORMAT_MASK 0x0000001FL |
25550 | #define CB_COLOR0_INFO__LINEAR_GENERAL_MASK 0x00000080L |
25551 | #define CB_COLOR0_INFO__NUMBER_TYPE_MASK 0x00000700L |
25552 | #define CB_COLOR0_INFO__COMP_SWAP_MASK 0x00001800L |
25553 | #define CB_COLOR0_INFO__BLEND_CLAMP_MASK 0x00008000L |
25554 | #define CB_COLOR0_INFO__BLEND_BYPASS_MASK 0x00010000L |
25555 | #define CB_COLOR0_INFO__SIMPLE_FLOAT_MASK 0x00020000L |
25556 | #define CB_COLOR0_INFO__ROUND_MODE_MASK 0x00040000L |
25557 | #define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L |
25558 | #define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L |
25559 | //CB_COLOR0_ATTRIB |
25560 | #define CB_COLOR0_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0 |
25561 | #define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x2 |
25562 | #define CB_COLOR0_ATTRIB__DISABLE_FMASK_NOALLOC_OPT__SHIFT 0x3 |
25563 | #define CB_COLOR0_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX__SHIFT 0x4 |
25564 | #define CB_COLOR0_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX__SHIFT 0x5 |
25565 | #define CB_COLOR0_ATTRIB__NUM_FRAGMENTS_MASK 0x00000003L |
25566 | #define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00000004L |
25567 | #define CB_COLOR0_ATTRIB__DISABLE_FMASK_NOALLOC_OPT_MASK 0x00000008L |
25568 | #define CB_COLOR0_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX_MASK 0x00000010L |
25569 | #define CB_COLOR0_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX_MASK 0x00000020L |
25570 | //CB_COLOR0_FDCC_CONTROL |
25571 | #define CB_COLOR0_FDCC_CONTROL__SAMPLE_MASK_TRACKER_DISABLE__SHIFT 0x0 |
25572 | #define CB_COLOR0_FDCC_CONTROL__SAMPLE_MASK_TRACKER_FEA_FORCE__SHIFT 0x1 |
25573 | #define CB_COLOR0_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 |
25574 | #define CB_COLOR0_FDCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 |
25575 | #define CB_COLOR0_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 |
25576 | #define CB_COLOR0_FDCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 |
25577 | #define CB_COLOR0_FDCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 |
25578 | #define CB_COLOR0_FDCC_CONTROL__INDEPENDENT_128B_BLOCKS__SHIFT 0xa |
25579 | #define CB_COLOR0_FDCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0x12 |
25580 | #define CB_COLOR0_FDCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT 0x13 |
25581 | #define CB_COLOR0_FDCC_CONTROL__SKIP_LOW_COMP_RATIO__SHIFT 0x15 |
25582 | #define CB_COLOR0_FDCC_CONTROL__FDCC_ENABLE__SHIFT 0x16 |
25583 | #define CB_COLOR0_FDCC_CONTROL__DCC_COMPRESS_DISABLE__SHIFT 0x17 |
25584 | #define CB_COLOR0_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE__SHIFT 0x18 |
25585 | #define CB_COLOR0_FDCC_CONTROL__SAMPLE_MASK_TRACKER_DISABLE_MASK 0x00000001L |
25586 | #define CB_COLOR0_FDCC_CONTROL__SAMPLE_MASK_TRACKER_FEA_FORCE_MASK 0x00000002L |
25587 | #define CB_COLOR0_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL |
25588 | #define CB_COLOR0_FDCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L |
25589 | #define CB_COLOR0_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L |
25590 | #define CB_COLOR0_FDCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L |
25591 | #define CB_COLOR0_FDCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L |
25592 | #define CB_COLOR0_FDCC_CONTROL__INDEPENDENT_128B_BLOCKS_MASK 0x00000400L |
25593 | #define CB_COLOR0_FDCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00040000L |
25594 | #define CB_COLOR0_FDCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK 0x00080000L |
25595 | #define CB_COLOR0_FDCC_CONTROL__SKIP_LOW_COMP_RATIO_MASK 0x00200000L |
25596 | #define CB_COLOR0_FDCC_CONTROL__FDCC_ENABLE_MASK 0x00400000L |
25597 | #define CB_COLOR0_FDCC_CONTROL__DCC_COMPRESS_DISABLE_MASK 0x00800000L |
25598 | #define CB_COLOR0_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE_MASK 0x01000000L |
25599 | //CB_COLOR0_DCC_BASE |
25600 | #define CB_COLOR0_DCC_BASE__BASE_256B__SHIFT 0x0 |
25601 | #define CB_COLOR0_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL |
25602 | //CB_COLOR1_BASE |
25603 | #define CB_COLOR1_BASE__BASE_256B__SHIFT 0x0 |
25604 | #define CB_COLOR1_BASE__BASE_256B_MASK 0xFFFFFFFFL |
25605 | //CB_COLOR1_VIEW |
25606 | #define CB_COLOR1_VIEW__SLICE_START__SHIFT 0x0 |
25607 | #define CB_COLOR1_VIEW__SLICE_MAX__SHIFT 0xd |
25608 | #define CB_COLOR1_VIEW__MIP_LEVEL__SHIFT 0x1a |
25609 | #define CB_COLOR1_VIEW__SLICE_START_MASK 0x00001FFFL |
25610 | #define CB_COLOR1_VIEW__SLICE_MAX_MASK 0x03FFE000L |
25611 | #define CB_COLOR1_VIEW__MIP_LEVEL_MASK 0x3C000000L |
25612 | //CB_COLOR1_INFO |
25613 | #define CB_COLOR1_INFO__FORMAT__SHIFT 0x0 |
25614 | #define CB_COLOR1_INFO__LINEAR_GENERAL__SHIFT 0x7 |
25615 | #define CB_COLOR1_INFO__NUMBER_TYPE__SHIFT 0x8 |
25616 | #define CB_COLOR1_INFO__COMP_SWAP__SHIFT 0xb |
25617 | #define CB_COLOR1_INFO__BLEND_CLAMP__SHIFT 0xf |
25618 | #define CB_COLOR1_INFO__BLEND_BYPASS__SHIFT 0x10 |
25619 | #define CB_COLOR1_INFO__SIMPLE_FLOAT__SHIFT 0x11 |
25620 | #define CB_COLOR1_INFO__ROUND_MODE__SHIFT 0x12 |
25621 | #define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 |
25622 | #define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 |
25623 | #define CB_COLOR1_INFO__FORMAT_MASK 0x0000001FL |
25624 | #define CB_COLOR1_INFO__LINEAR_GENERAL_MASK 0x00000080L |
25625 | #define CB_COLOR1_INFO__NUMBER_TYPE_MASK 0x00000700L |
25626 | #define CB_COLOR1_INFO__COMP_SWAP_MASK 0x00001800L |
25627 | #define CB_COLOR1_INFO__BLEND_CLAMP_MASK 0x00008000L |
25628 | #define CB_COLOR1_INFO__BLEND_BYPASS_MASK 0x00010000L |
25629 | #define CB_COLOR1_INFO__SIMPLE_FLOAT_MASK 0x00020000L |
25630 | #define CB_COLOR1_INFO__ROUND_MODE_MASK 0x00040000L |
25631 | #define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L |
25632 | #define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L |
25633 | //CB_COLOR1_ATTRIB |
25634 | #define CB_COLOR1_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0 |
25635 | #define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x2 |
25636 | #define CB_COLOR1_ATTRIB__DISABLE_FMASK_NOALLOC_OPT__SHIFT 0x3 |
25637 | #define CB_COLOR1_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX__SHIFT 0x4 |
25638 | #define CB_COLOR1_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX__SHIFT 0x5 |
25639 | #define CB_COLOR1_ATTRIB__NUM_FRAGMENTS_MASK 0x00000003L |
25640 | #define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00000004L |
25641 | #define CB_COLOR1_ATTRIB__DISABLE_FMASK_NOALLOC_OPT_MASK 0x00000008L |
25642 | #define CB_COLOR1_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX_MASK 0x00000010L |
25643 | #define CB_COLOR1_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX_MASK 0x00000020L |
25644 | //CB_COLOR1_FDCC_CONTROL |
25645 | #define CB_COLOR1_FDCC_CONTROL__SAMPLE_MASK_TRACKER_DISABLE__SHIFT 0x0 |
25646 | #define CB_COLOR1_FDCC_CONTROL__SAMPLE_MASK_TRACKER_FEA_FORCE__SHIFT 0x1 |
25647 | #define CB_COLOR1_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 |
25648 | #define CB_COLOR1_FDCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 |
25649 | #define CB_COLOR1_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 |
25650 | #define CB_COLOR1_FDCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 |
25651 | #define CB_COLOR1_FDCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 |
25652 | #define CB_COLOR1_FDCC_CONTROL__INDEPENDENT_128B_BLOCKS__SHIFT 0xa |
25653 | #define CB_COLOR1_FDCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0x12 |
25654 | #define CB_COLOR1_FDCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT 0x13 |
25655 | #define CB_COLOR1_FDCC_CONTROL__SKIP_LOW_COMP_RATIO__SHIFT 0x15 |
25656 | #define CB_COLOR1_FDCC_CONTROL__FDCC_ENABLE__SHIFT 0x16 |
25657 | #define CB_COLOR1_FDCC_CONTROL__DCC_COMPRESS_DISABLE__SHIFT 0x17 |
25658 | #define CB_COLOR1_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE__SHIFT 0x18 |
25659 | #define CB_COLOR1_FDCC_CONTROL__SAMPLE_MASK_TRACKER_DISABLE_MASK 0x00000001L |
25660 | #define CB_COLOR1_FDCC_CONTROL__SAMPLE_MASK_TRACKER_FEA_FORCE_MASK 0x00000002L |
25661 | #define CB_COLOR1_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL |
25662 | #define CB_COLOR1_FDCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L |
25663 | #define CB_COLOR1_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L |
25664 | #define CB_COLOR1_FDCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L |
25665 | #define CB_COLOR1_FDCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L |
25666 | #define CB_COLOR1_FDCC_CONTROL__INDEPENDENT_128B_BLOCKS_MASK 0x00000400L |
25667 | #define CB_COLOR1_FDCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00040000L |
25668 | #define CB_COLOR1_FDCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK 0x00080000L |
25669 | #define CB_COLOR1_FDCC_CONTROL__SKIP_LOW_COMP_RATIO_MASK 0x00200000L |
25670 | #define CB_COLOR1_FDCC_CONTROL__FDCC_ENABLE_MASK 0x00400000L |
25671 | #define CB_COLOR1_FDCC_CONTROL__DCC_COMPRESS_DISABLE_MASK 0x00800000L |
25672 | #define CB_COLOR1_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE_MASK 0x01000000L |
25673 | //CB_COLOR1_DCC_BASE |
25674 | #define CB_COLOR1_DCC_BASE__BASE_256B__SHIFT 0x0 |
25675 | #define CB_COLOR1_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL |
25676 | //CB_COLOR2_BASE |
25677 | #define CB_COLOR2_BASE__BASE_256B__SHIFT 0x0 |
25678 | #define CB_COLOR2_BASE__BASE_256B_MASK 0xFFFFFFFFL |
25679 | //CB_COLOR2_VIEW |
25680 | #define CB_COLOR2_VIEW__SLICE_START__SHIFT 0x0 |
25681 | #define CB_COLOR2_VIEW__SLICE_MAX__SHIFT 0xd |
25682 | #define CB_COLOR2_VIEW__MIP_LEVEL__SHIFT 0x1a |
25683 | #define CB_COLOR2_VIEW__SLICE_START_MASK 0x00001FFFL |
25684 | #define CB_COLOR2_VIEW__SLICE_MAX_MASK 0x03FFE000L |
25685 | #define CB_COLOR2_VIEW__MIP_LEVEL_MASK 0x3C000000L |
25686 | //CB_COLOR2_INFO |
25687 | #define CB_COLOR2_INFO__FORMAT__SHIFT 0x0 |
25688 | #define CB_COLOR2_INFO__LINEAR_GENERAL__SHIFT 0x7 |
25689 | #define CB_COLOR2_INFO__NUMBER_TYPE__SHIFT 0x8 |
25690 | #define CB_COLOR2_INFO__COMP_SWAP__SHIFT 0xb |
25691 | #define CB_COLOR2_INFO__BLEND_CLAMP__SHIFT 0xf |
25692 | #define CB_COLOR2_INFO__BLEND_BYPASS__SHIFT 0x10 |
25693 | #define CB_COLOR2_INFO__SIMPLE_FLOAT__SHIFT 0x11 |
25694 | #define CB_COLOR2_INFO__ROUND_MODE__SHIFT 0x12 |
25695 | #define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 |
25696 | #define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 |
25697 | #define CB_COLOR2_INFO__FORMAT_MASK 0x0000001FL |
25698 | #define CB_COLOR2_INFO__LINEAR_GENERAL_MASK 0x00000080L |
25699 | #define CB_COLOR2_INFO__NUMBER_TYPE_MASK 0x00000700L |
25700 | #define CB_COLOR2_INFO__COMP_SWAP_MASK 0x00001800L |
25701 | #define CB_COLOR2_INFO__BLEND_CLAMP_MASK 0x00008000L |
25702 | #define CB_COLOR2_INFO__BLEND_BYPASS_MASK 0x00010000L |
25703 | #define CB_COLOR2_INFO__SIMPLE_FLOAT_MASK 0x00020000L |
25704 | #define CB_COLOR2_INFO__ROUND_MODE_MASK 0x00040000L |
25705 | #define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L |
25706 | #define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L |
25707 | //CB_COLOR2_ATTRIB |
25708 | #define CB_COLOR2_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0 |
25709 | #define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x2 |
25710 | #define CB_COLOR2_ATTRIB__DISABLE_FMASK_NOALLOC_OPT__SHIFT 0x3 |
25711 | #define CB_COLOR2_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX__SHIFT 0x4 |
25712 | #define CB_COLOR2_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX__SHIFT 0x5 |
25713 | #define CB_COLOR2_ATTRIB__NUM_FRAGMENTS_MASK 0x00000003L |
25714 | #define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00000004L |
25715 | #define CB_COLOR2_ATTRIB__DISABLE_FMASK_NOALLOC_OPT_MASK 0x00000008L |
25716 | #define CB_COLOR2_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX_MASK 0x00000010L |
25717 | #define CB_COLOR2_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX_MASK 0x00000020L |
25718 | //CB_COLOR2_FDCC_CONTROL |
25719 | #define CB_COLOR2_FDCC_CONTROL__SAMPLE_MASK_TRACKER_DISABLE__SHIFT 0x0 |
25720 | #define CB_COLOR2_FDCC_CONTROL__SAMPLE_MASK_TRACKER_FEA_FORCE__SHIFT 0x1 |
25721 | #define CB_COLOR2_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 |
25722 | #define CB_COLOR2_FDCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 |
25723 | #define CB_COLOR2_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 |
25724 | #define CB_COLOR2_FDCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 |
25725 | #define CB_COLOR2_FDCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 |
25726 | #define CB_COLOR2_FDCC_CONTROL__INDEPENDENT_128B_BLOCKS__SHIFT 0xa |
25727 | #define CB_COLOR2_FDCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0x12 |
25728 | #define CB_COLOR2_FDCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT 0x13 |
25729 | #define CB_COLOR2_FDCC_CONTROL__SKIP_LOW_COMP_RATIO__SHIFT 0x15 |
25730 | #define CB_COLOR2_FDCC_CONTROL__FDCC_ENABLE__SHIFT 0x16 |
25731 | #define CB_COLOR2_FDCC_CONTROL__DCC_COMPRESS_DISABLE__SHIFT 0x17 |
25732 | #define CB_COLOR2_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE__SHIFT 0x18 |
25733 | #define CB_COLOR2_FDCC_CONTROL__SAMPLE_MASK_TRACKER_DISABLE_MASK 0x00000001L |
25734 | #define CB_COLOR2_FDCC_CONTROL__SAMPLE_MASK_TRACKER_FEA_FORCE_MASK 0x00000002L |
25735 | #define CB_COLOR2_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL |
25736 | #define CB_COLOR2_FDCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L |
25737 | #define CB_COLOR2_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L |
25738 | #define CB_COLOR2_FDCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L |
25739 | #define CB_COLOR2_FDCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L |
25740 | #define CB_COLOR2_FDCC_CONTROL__INDEPENDENT_128B_BLOCKS_MASK 0x00000400L |
25741 | #define CB_COLOR2_FDCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00040000L |
25742 | #define CB_COLOR2_FDCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK 0x00080000L |
25743 | #define CB_COLOR2_FDCC_CONTROL__SKIP_LOW_COMP_RATIO_MASK 0x00200000L |
25744 | #define CB_COLOR2_FDCC_CONTROL__FDCC_ENABLE_MASK 0x00400000L |
25745 | #define CB_COLOR2_FDCC_CONTROL__DCC_COMPRESS_DISABLE_MASK 0x00800000L |
25746 | #define CB_COLOR2_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE_MASK 0x01000000L |
25747 | //CB_COLOR2_DCC_BASE |
25748 | #define CB_COLOR2_DCC_BASE__BASE_256B__SHIFT 0x0 |
25749 | #define CB_COLOR2_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL |
25750 | //CB_COLOR3_BASE |
25751 | #define CB_COLOR3_BASE__BASE_256B__SHIFT 0x0 |
25752 | #define CB_COLOR3_BASE__BASE_256B_MASK 0xFFFFFFFFL |
25753 | //CB_COLOR3_VIEW |
25754 | #define CB_COLOR3_VIEW__SLICE_START__SHIFT 0x0 |
25755 | #define CB_COLOR3_VIEW__SLICE_MAX__SHIFT 0xd |
25756 | #define CB_COLOR3_VIEW__MIP_LEVEL__SHIFT 0x1a |
25757 | #define CB_COLOR3_VIEW__SLICE_START_MASK 0x00001FFFL |
25758 | #define CB_COLOR3_VIEW__SLICE_MAX_MASK 0x03FFE000L |
25759 | #define CB_COLOR3_VIEW__MIP_LEVEL_MASK 0x3C000000L |
25760 | //CB_COLOR3_INFO |
25761 | #define CB_COLOR3_INFO__FORMAT__SHIFT 0x0 |
25762 | #define CB_COLOR3_INFO__LINEAR_GENERAL__SHIFT 0x7 |
25763 | #define CB_COLOR3_INFO__NUMBER_TYPE__SHIFT 0x8 |
25764 | #define CB_COLOR3_INFO__COMP_SWAP__SHIFT 0xb |
25765 | #define CB_COLOR3_INFO__BLEND_CLAMP__SHIFT 0xf |
25766 | #define CB_COLOR3_INFO__BLEND_BYPASS__SHIFT 0x10 |
25767 | #define CB_COLOR3_INFO__SIMPLE_FLOAT__SHIFT 0x11 |
25768 | #define CB_COLOR3_INFO__ROUND_MODE__SHIFT 0x12 |
25769 | #define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 |
25770 | #define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 |
25771 | #define CB_COLOR3_INFO__FORMAT_MASK 0x0000001FL |
25772 | #define CB_COLOR3_INFO__LINEAR_GENERAL_MASK 0x00000080L |
25773 | #define CB_COLOR3_INFO__NUMBER_TYPE_MASK 0x00000700L |
25774 | #define CB_COLOR3_INFO__COMP_SWAP_MASK 0x00001800L |
25775 | #define CB_COLOR3_INFO__BLEND_CLAMP_MASK 0x00008000L |
25776 | #define CB_COLOR3_INFO__BLEND_BYPASS_MASK 0x00010000L |
25777 | #define CB_COLOR3_INFO__SIMPLE_FLOAT_MASK 0x00020000L |
25778 | #define CB_COLOR3_INFO__ROUND_MODE_MASK 0x00040000L |
25779 | #define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L |
25780 | #define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L |
25781 | //CB_COLOR3_ATTRIB |
25782 | #define CB_COLOR3_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0 |
25783 | #define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x2 |
25784 | #define CB_COLOR3_ATTRIB__DISABLE_FMASK_NOALLOC_OPT__SHIFT 0x3 |
25785 | #define CB_COLOR3_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX__SHIFT 0x4 |
25786 | #define CB_COLOR3_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX__SHIFT 0x5 |
25787 | #define CB_COLOR3_ATTRIB__NUM_FRAGMENTS_MASK 0x00000003L |
25788 | #define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00000004L |
25789 | #define CB_COLOR3_ATTRIB__DISABLE_FMASK_NOALLOC_OPT_MASK 0x00000008L |
25790 | #define CB_COLOR3_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX_MASK 0x00000010L |
25791 | #define CB_COLOR3_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX_MASK 0x00000020L |
25792 | //CB_COLOR3_FDCC_CONTROL |
25793 | #define CB_COLOR3_FDCC_CONTROL__SAMPLE_MASK_TRACKER_DISABLE__SHIFT 0x0 |
25794 | #define CB_COLOR3_FDCC_CONTROL__SAMPLE_MASK_TRACKER_FEA_FORCE__SHIFT 0x1 |
25795 | #define CB_COLOR3_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 |
25796 | #define CB_COLOR3_FDCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 |
25797 | #define CB_COLOR3_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 |
25798 | #define CB_COLOR3_FDCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 |
25799 | #define CB_COLOR3_FDCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 |
25800 | #define CB_COLOR3_FDCC_CONTROL__INDEPENDENT_128B_BLOCKS__SHIFT 0xa |
25801 | #define CB_COLOR3_FDCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0x12 |
25802 | #define CB_COLOR3_FDCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT 0x13 |
25803 | #define CB_COLOR3_FDCC_CONTROL__SKIP_LOW_COMP_RATIO__SHIFT 0x15 |
25804 | #define CB_COLOR3_FDCC_CONTROL__FDCC_ENABLE__SHIFT 0x16 |
25805 | #define CB_COLOR3_FDCC_CONTROL__DCC_COMPRESS_DISABLE__SHIFT 0x17 |
25806 | #define CB_COLOR3_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE__SHIFT 0x18 |
25807 | #define CB_COLOR3_FDCC_CONTROL__SAMPLE_MASK_TRACKER_DISABLE_MASK 0x00000001L |
25808 | #define CB_COLOR3_FDCC_CONTROL__SAMPLE_MASK_TRACKER_FEA_FORCE_MASK 0x00000002L |
25809 | #define CB_COLOR3_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL |
25810 | #define CB_COLOR3_FDCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L |
25811 | #define CB_COLOR3_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L |
25812 | #define CB_COLOR3_FDCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L |
25813 | #define CB_COLOR3_FDCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L |
25814 | #define CB_COLOR3_FDCC_CONTROL__INDEPENDENT_128B_BLOCKS_MASK 0x00000400L |
25815 | #define CB_COLOR3_FDCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00040000L |
25816 | #define CB_COLOR3_FDCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK 0x00080000L |
25817 | #define CB_COLOR3_FDCC_CONTROL__SKIP_LOW_COMP_RATIO_MASK 0x00200000L |
25818 | #define CB_COLOR3_FDCC_CONTROL__FDCC_ENABLE_MASK 0x00400000L |
25819 | #define CB_COLOR3_FDCC_CONTROL__DCC_COMPRESS_DISABLE_MASK 0x00800000L |
25820 | #define CB_COLOR3_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE_MASK 0x01000000L |
25821 | //CB_COLOR3_DCC_BASE |
25822 | #define CB_COLOR3_DCC_BASE__BASE_256B__SHIFT 0x0 |
25823 | #define CB_COLOR3_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL |
25824 | //CB_COLOR4_BASE |
25825 | #define CB_COLOR4_BASE__BASE_256B__SHIFT 0x0 |
25826 | #define CB_COLOR4_BASE__BASE_256B_MASK 0xFFFFFFFFL |
25827 | //CB_COLOR4_VIEW |
25828 | #define CB_COLOR4_VIEW__SLICE_START__SHIFT 0x0 |
25829 | #define CB_COLOR4_VIEW__SLICE_MAX__SHIFT 0xd |
25830 | #define CB_COLOR4_VIEW__MIP_LEVEL__SHIFT 0x1a |
25831 | #define CB_COLOR4_VIEW__SLICE_START_MASK 0x00001FFFL |
25832 | #define CB_COLOR4_VIEW__SLICE_MAX_MASK 0x03FFE000L |
25833 | #define CB_COLOR4_VIEW__MIP_LEVEL_MASK 0x3C000000L |
25834 | //CB_COLOR4_INFO |
25835 | #define CB_COLOR4_INFO__FORMAT__SHIFT 0x0 |
25836 | #define CB_COLOR4_INFO__LINEAR_GENERAL__SHIFT 0x7 |
25837 | #define CB_COLOR4_INFO__NUMBER_TYPE__SHIFT 0x8 |
25838 | #define CB_COLOR4_INFO__COMP_SWAP__SHIFT 0xb |
25839 | #define CB_COLOR4_INFO__BLEND_CLAMP__SHIFT 0xf |
25840 | #define CB_COLOR4_INFO__BLEND_BYPASS__SHIFT 0x10 |
25841 | #define CB_COLOR4_INFO__SIMPLE_FLOAT__SHIFT 0x11 |
25842 | #define CB_COLOR4_INFO__ROUND_MODE__SHIFT 0x12 |
25843 | #define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 |
25844 | #define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 |
25845 | #define CB_COLOR4_INFO__FORMAT_MASK 0x0000001FL |
25846 | #define CB_COLOR4_INFO__LINEAR_GENERAL_MASK 0x00000080L |
25847 | #define CB_COLOR4_INFO__NUMBER_TYPE_MASK 0x00000700L |
25848 | #define CB_COLOR4_INFO__COMP_SWAP_MASK 0x00001800L |
25849 | #define CB_COLOR4_INFO__BLEND_CLAMP_MASK 0x00008000L |
25850 | #define CB_COLOR4_INFO__BLEND_BYPASS_MASK 0x00010000L |
25851 | #define CB_COLOR4_INFO__SIMPLE_FLOAT_MASK 0x00020000L |
25852 | #define CB_COLOR4_INFO__ROUND_MODE_MASK 0x00040000L |
25853 | #define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L |
25854 | #define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L |
25855 | //CB_COLOR4_ATTRIB |
25856 | #define CB_COLOR4_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0 |
25857 | #define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x2 |
25858 | #define CB_COLOR4_ATTRIB__DISABLE_FMASK_NOALLOC_OPT__SHIFT 0x3 |
25859 | #define CB_COLOR4_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX__SHIFT 0x4 |
25860 | #define CB_COLOR4_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX__SHIFT 0x5 |
25861 | #define CB_COLOR4_ATTRIB__NUM_FRAGMENTS_MASK 0x00000003L |
25862 | #define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00000004L |
25863 | #define CB_COLOR4_ATTRIB__DISABLE_FMASK_NOALLOC_OPT_MASK 0x00000008L |
25864 | #define CB_COLOR4_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX_MASK 0x00000010L |
25865 | #define CB_COLOR4_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX_MASK 0x00000020L |
25866 | //CB_COLOR4_FDCC_CONTROL |
25867 | #define CB_COLOR4_FDCC_CONTROL__SAMPLE_MASK_TRACKER_DISABLE__SHIFT 0x0 |
25868 | #define CB_COLOR4_FDCC_CONTROL__SAMPLE_MASK_TRACKER_FEA_FORCE__SHIFT 0x1 |
25869 | #define CB_COLOR4_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 |
25870 | #define CB_COLOR4_FDCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 |
25871 | #define CB_COLOR4_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 |
25872 | #define CB_COLOR4_FDCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 |
25873 | #define CB_COLOR4_FDCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 |
25874 | #define CB_COLOR4_FDCC_CONTROL__INDEPENDENT_128B_BLOCKS__SHIFT 0xa |
25875 | #define CB_COLOR4_FDCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0x12 |
25876 | #define CB_COLOR4_FDCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT 0x13 |
25877 | #define CB_COLOR4_FDCC_CONTROL__SKIP_LOW_COMP_RATIO__SHIFT 0x15 |
25878 | #define CB_COLOR4_FDCC_CONTROL__FDCC_ENABLE__SHIFT 0x16 |
25879 | #define CB_COLOR4_FDCC_CONTROL__DCC_COMPRESS_DISABLE__SHIFT 0x17 |
25880 | #define CB_COLOR4_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE__SHIFT 0x18 |
25881 | #define CB_COLOR4_FDCC_CONTROL__SAMPLE_MASK_TRACKER_DISABLE_MASK 0x00000001L |
25882 | #define CB_COLOR4_FDCC_CONTROL__SAMPLE_MASK_TRACKER_FEA_FORCE_MASK 0x00000002L |
25883 | #define CB_COLOR4_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL |
25884 | #define CB_COLOR4_FDCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L |
25885 | #define CB_COLOR4_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L |
25886 | #define CB_COLOR4_FDCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L |
25887 | #define CB_COLOR4_FDCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L |
25888 | #define CB_COLOR4_FDCC_CONTROL__INDEPENDENT_128B_BLOCKS_MASK 0x00000400L |
25889 | #define CB_COLOR4_FDCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00040000L |
25890 | #define CB_COLOR4_FDCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK 0x00080000L |
25891 | #define CB_COLOR4_FDCC_CONTROL__SKIP_LOW_COMP_RATIO_MASK 0x00200000L |
25892 | #define CB_COLOR4_FDCC_CONTROL__FDCC_ENABLE_MASK 0x00400000L |
25893 | #define CB_COLOR4_FDCC_CONTROL__DCC_COMPRESS_DISABLE_MASK 0x00800000L |
25894 | #define CB_COLOR4_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE_MASK 0x01000000L |
25895 | //CB_COLOR4_DCC_BASE |
25896 | #define CB_COLOR4_DCC_BASE__BASE_256B__SHIFT 0x0 |
25897 | #define CB_COLOR4_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL |
25898 | //CB_COLOR5_BASE |
25899 | #define CB_COLOR5_BASE__BASE_256B__SHIFT 0x0 |
25900 | #define CB_COLOR5_BASE__BASE_256B_MASK 0xFFFFFFFFL |
25901 | //CB_COLOR5_VIEW |
25902 | #define CB_COLOR5_VIEW__SLICE_START__SHIFT 0x0 |
25903 | #define CB_COLOR5_VIEW__SLICE_MAX__SHIFT 0xd |
25904 | #define CB_COLOR5_VIEW__MIP_LEVEL__SHIFT 0x1a |
25905 | #define CB_COLOR5_VIEW__SLICE_START_MASK 0x00001FFFL |
25906 | #define CB_COLOR5_VIEW__SLICE_MAX_MASK 0x03FFE000L |
25907 | #define CB_COLOR5_VIEW__MIP_LEVEL_MASK 0x3C000000L |
25908 | //CB_COLOR5_INFO |
25909 | #define CB_COLOR5_INFO__FORMAT__SHIFT 0x0 |
25910 | #define CB_COLOR5_INFO__LINEAR_GENERAL__SHIFT 0x7 |
25911 | #define CB_COLOR5_INFO__NUMBER_TYPE__SHIFT 0x8 |
25912 | #define CB_COLOR5_INFO__COMP_SWAP__SHIFT 0xb |
25913 | #define CB_COLOR5_INFO__BLEND_CLAMP__SHIFT 0xf |
25914 | #define CB_COLOR5_INFO__BLEND_BYPASS__SHIFT 0x10 |
25915 | #define CB_COLOR5_INFO__SIMPLE_FLOAT__SHIFT 0x11 |
25916 | #define CB_COLOR5_INFO__ROUND_MODE__SHIFT 0x12 |
25917 | #define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 |
25918 | #define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 |
25919 | #define CB_COLOR5_INFO__FORMAT_MASK 0x0000001FL |
25920 | #define CB_COLOR5_INFO__LINEAR_GENERAL_MASK 0x00000080L |
25921 | #define CB_COLOR5_INFO__NUMBER_TYPE_MASK 0x00000700L |
25922 | #define CB_COLOR5_INFO__COMP_SWAP_MASK 0x00001800L |
25923 | #define CB_COLOR5_INFO__BLEND_CLAMP_MASK 0x00008000L |
25924 | #define CB_COLOR5_INFO__BLEND_BYPASS_MASK 0x00010000L |
25925 | #define CB_COLOR5_INFO__SIMPLE_FLOAT_MASK 0x00020000L |
25926 | #define CB_COLOR5_INFO__ROUND_MODE_MASK 0x00040000L |
25927 | #define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L |
25928 | #define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L |
25929 | //CB_COLOR5_ATTRIB |
25930 | #define CB_COLOR5_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0 |
25931 | #define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x2 |
25932 | #define CB_COLOR5_ATTRIB__DISABLE_FMASK_NOALLOC_OPT__SHIFT 0x3 |
25933 | #define CB_COLOR5_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX__SHIFT 0x4 |
25934 | #define CB_COLOR5_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX__SHIFT 0x5 |
25935 | #define CB_COLOR5_ATTRIB__NUM_FRAGMENTS_MASK 0x00000003L |
25936 | #define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00000004L |
25937 | #define CB_COLOR5_ATTRIB__DISABLE_FMASK_NOALLOC_OPT_MASK 0x00000008L |
25938 | #define CB_COLOR5_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX_MASK 0x00000010L |
25939 | #define CB_COLOR5_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX_MASK 0x00000020L |
25940 | //CB_COLOR5_FDCC_CONTROL |
25941 | #define CB_COLOR5_FDCC_CONTROL__SAMPLE_MASK_TRACKER_DISABLE__SHIFT 0x0 |
25942 | #define CB_COLOR5_FDCC_CONTROL__SAMPLE_MASK_TRACKER_FEA_FORCE__SHIFT 0x1 |
25943 | #define CB_COLOR5_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 |
25944 | #define CB_COLOR5_FDCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 |
25945 | #define CB_COLOR5_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 |
25946 | #define CB_COLOR5_FDCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 |
25947 | #define CB_COLOR5_FDCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 |
25948 | #define CB_COLOR5_FDCC_CONTROL__INDEPENDENT_128B_BLOCKS__SHIFT 0xa |
25949 | #define CB_COLOR5_FDCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0x12 |
25950 | #define CB_COLOR5_FDCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT 0x13 |
25951 | #define CB_COLOR5_FDCC_CONTROL__SKIP_LOW_COMP_RATIO__SHIFT 0x15 |
25952 | #define CB_COLOR5_FDCC_CONTROL__FDCC_ENABLE__SHIFT 0x16 |
25953 | #define CB_COLOR5_FDCC_CONTROL__DCC_COMPRESS_DISABLE__SHIFT 0x17 |
25954 | #define CB_COLOR5_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE__SHIFT 0x18 |
25955 | #define CB_COLOR5_FDCC_CONTROL__SAMPLE_MASK_TRACKER_DISABLE_MASK 0x00000001L |
25956 | #define CB_COLOR5_FDCC_CONTROL__SAMPLE_MASK_TRACKER_FEA_FORCE_MASK 0x00000002L |
25957 | #define CB_COLOR5_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL |
25958 | #define CB_COLOR5_FDCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L |
25959 | #define CB_COLOR5_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L |
25960 | #define CB_COLOR5_FDCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L |
25961 | #define CB_COLOR5_FDCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L |
25962 | #define CB_COLOR5_FDCC_CONTROL__INDEPENDENT_128B_BLOCKS_MASK 0x00000400L |
25963 | #define CB_COLOR5_FDCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00040000L |
25964 | #define CB_COLOR5_FDCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK 0x00080000L |
25965 | #define CB_COLOR5_FDCC_CONTROL__SKIP_LOW_COMP_RATIO_MASK 0x00200000L |
25966 | #define CB_COLOR5_FDCC_CONTROL__FDCC_ENABLE_MASK 0x00400000L |
25967 | #define CB_COLOR5_FDCC_CONTROL__DCC_COMPRESS_DISABLE_MASK 0x00800000L |
25968 | #define CB_COLOR5_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE_MASK 0x01000000L |
25969 | //CB_COLOR5_DCC_BASE |
25970 | #define CB_COLOR5_DCC_BASE__BASE_256B__SHIFT 0x0 |
25971 | #define CB_COLOR5_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL |
25972 | //CB_COLOR6_BASE |
25973 | #define CB_COLOR6_BASE__BASE_256B__SHIFT 0x0 |
25974 | #define CB_COLOR6_BASE__BASE_256B_MASK 0xFFFFFFFFL |
25975 | //CB_COLOR6_VIEW |
25976 | #define CB_COLOR6_VIEW__SLICE_START__SHIFT 0x0 |
25977 | #define CB_COLOR6_VIEW__SLICE_MAX__SHIFT 0xd |
25978 | #define CB_COLOR6_VIEW__MIP_LEVEL__SHIFT 0x1a |
25979 | #define CB_COLOR6_VIEW__SLICE_START_MASK 0x00001FFFL |
25980 | #define CB_COLOR6_VIEW__SLICE_MAX_MASK 0x03FFE000L |
25981 | #define CB_COLOR6_VIEW__MIP_LEVEL_MASK 0x3C000000L |
25982 | //CB_COLOR6_INFO |
25983 | #define CB_COLOR6_INFO__FORMAT__SHIFT 0x0 |
25984 | #define CB_COLOR6_INFO__LINEAR_GENERAL__SHIFT 0x7 |
25985 | #define CB_COLOR6_INFO__NUMBER_TYPE__SHIFT 0x8 |
25986 | #define CB_COLOR6_INFO__COMP_SWAP__SHIFT 0xb |
25987 | #define CB_COLOR6_INFO__BLEND_CLAMP__SHIFT 0xf |
25988 | #define CB_COLOR6_INFO__BLEND_BYPASS__SHIFT 0x10 |
25989 | #define CB_COLOR6_INFO__SIMPLE_FLOAT__SHIFT 0x11 |
25990 | #define CB_COLOR6_INFO__ROUND_MODE__SHIFT 0x12 |
25991 | #define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 |
25992 | #define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 |
25993 | #define CB_COLOR6_INFO__FORMAT_MASK 0x0000001FL |
25994 | #define CB_COLOR6_INFO__LINEAR_GENERAL_MASK 0x00000080L |
25995 | #define CB_COLOR6_INFO__NUMBER_TYPE_MASK 0x00000700L |
25996 | #define CB_COLOR6_INFO__COMP_SWAP_MASK 0x00001800L |
25997 | #define CB_COLOR6_INFO__BLEND_CLAMP_MASK 0x00008000L |
25998 | #define CB_COLOR6_INFO__BLEND_BYPASS_MASK 0x00010000L |
25999 | #define CB_COLOR6_INFO__SIMPLE_FLOAT_MASK 0x00020000L |
26000 | #define CB_COLOR6_INFO__ROUND_MODE_MASK 0x00040000L |
26001 | #define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L |
26002 | #define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L |
26003 | //CB_COLOR6_ATTRIB |
26004 | #define CB_COLOR6_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0 |
26005 | #define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x2 |
26006 | #define CB_COLOR6_ATTRIB__DISABLE_FMASK_NOALLOC_OPT__SHIFT 0x3 |
26007 | #define CB_COLOR6_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX__SHIFT 0x4 |
26008 | #define CB_COLOR6_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX__SHIFT 0x5 |
26009 | #define CB_COLOR6_ATTRIB__NUM_FRAGMENTS_MASK 0x00000003L |
26010 | #define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00000004L |
26011 | #define CB_COLOR6_ATTRIB__DISABLE_FMASK_NOALLOC_OPT_MASK 0x00000008L |
26012 | #define CB_COLOR6_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX_MASK 0x00000010L |
26013 | #define CB_COLOR6_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX_MASK 0x00000020L |
26014 | //CB_COLOR6_FDCC_CONTROL |
26015 | #define CB_COLOR6_FDCC_CONTROL__SAMPLE_MASK_TRACKER_DISABLE__SHIFT 0x0 |
26016 | #define CB_COLOR6_FDCC_CONTROL__SAMPLE_MASK_TRACKER_FEA_FORCE__SHIFT 0x1 |
26017 | #define CB_COLOR6_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 |
26018 | #define CB_COLOR6_FDCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 |
26019 | #define CB_COLOR6_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 |
26020 | #define CB_COLOR6_FDCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 |
26021 | #define CB_COLOR6_FDCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 |
26022 | #define CB_COLOR6_FDCC_CONTROL__INDEPENDENT_128B_BLOCKS__SHIFT 0xa |
26023 | #define CB_COLOR6_FDCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0x12 |
26024 | #define CB_COLOR6_FDCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT 0x13 |
26025 | #define CB_COLOR6_FDCC_CONTROL__SKIP_LOW_COMP_RATIO__SHIFT 0x15 |
26026 | #define CB_COLOR6_FDCC_CONTROL__FDCC_ENABLE__SHIFT 0x16 |
26027 | #define CB_COLOR6_FDCC_CONTROL__DCC_COMPRESS_DISABLE__SHIFT 0x17 |
26028 | #define CB_COLOR6_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE__SHIFT 0x18 |
26029 | #define CB_COLOR6_FDCC_CONTROL__SAMPLE_MASK_TRACKER_DISABLE_MASK 0x00000001L |
26030 | #define CB_COLOR6_FDCC_CONTROL__SAMPLE_MASK_TRACKER_FEA_FORCE_MASK 0x00000002L |
26031 | #define CB_COLOR6_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL |
26032 | #define CB_COLOR6_FDCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L |
26033 | #define CB_COLOR6_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L |
26034 | #define CB_COLOR6_FDCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L |
26035 | #define CB_COLOR6_FDCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L |
26036 | #define CB_COLOR6_FDCC_CONTROL__INDEPENDENT_128B_BLOCKS_MASK 0x00000400L |
26037 | #define CB_COLOR6_FDCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00040000L |
26038 | #define CB_COLOR6_FDCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK 0x00080000L |
26039 | #define CB_COLOR6_FDCC_CONTROL__SKIP_LOW_COMP_RATIO_MASK 0x00200000L |
26040 | #define CB_COLOR6_FDCC_CONTROL__FDCC_ENABLE_MASK 0x00400000L |
26041 | #define CB_COLOR6_FDCC_CONTROL__DCC_COMPRESS_DISABLE_MASK 0x00800000L |
26042 | #define CB_COLOR6_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE_MASK 0x01000000L |
26043 | //CB_COLOR6_DCC_BASE |
26044 | #define CB_COLOR6_DCC_BASE__BASE_256B__SHIFT 0x0 |
26045 | #define CB_COLOR6_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL |
26046 | //CB_COLOR7_BASE |
26047 | #define CB_COLOR7_BASE__BASE_256B__SHIFT 0x0 |
26048 | #define CB_COLOR7_BASE__BASE_256B_MASK 0xFFFFFFFFL |
26049 | //CB_COLOR7_VIEW |
26050 | #define CB_COLOR7_VIEW__SLICE_START__SHIFT 0x0 |
26051 | #define CB_COLOR7_VIEW__SLICE_MAX__SHIFT 0xd |
26052 | #define CB_COLOR7_VIEW__MIP_LEVEL__SHIFT 0x1a |
26053 | #define CB_COLOR7_VIEW__SLICE_START_MASK 0x00001FFFL |
26054 | #define CB_COLOR7_VIEW__SLICE_MAX_MASK 0x03FFE000L |
26055 | #define CB_COLOR7_VIEW__MIP_LEVEL_MASK 0x3C000000L |
26056 | //CB_COLOR7_INFO |
26057 | #define CB_COLOR7_INFO__FORMAT__SHIFT 0x0 |
26058 | #define CB_COLOR7_INFO__LINEAR_GENERAL__SHIFT 0x7 |
26059 | #define CB_COLOR7_INFO__NUMBER_TYPE__SHIFT 0x8 |
26060 | #define CB_COLOR7_INFO__COMP_SWAP__SHIFT 0xb |
26061 | #define CB_COLOR7_INFO__BLEND_CLAMP__SHIFT 0xf |
26062 | #define CB_COLOR7_INFO__BLEND_BYPASS__SHIFT 0x10 |
26063 | #define CB_COLOR7_INFO__SIMPLE_FLOAT__SHIFT 0x11 |
26064 | #define CB_COLOR7_INFO__ROUND_MODE__SHIFT 0x12 |
26065 | #define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 |
26066 | #define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 |
26067 | #define CB_COLOR7_INFO__FORMAT_MASK 0x0000001FL |
26068 | #define CB_COLOR7_INFO__LINEAR_GENERAL_MASK 0x00000080L |
26069 | #define CB_COLOR7_INFO__NUMBER_TYPE_MASK 0x00000700L |
26070 | #define CB_COLOR7_INFO__COMP_SWAP_MASK 0x00001800L |
26071 | #define CB_COLOR7_INFO__BLEND_CLAMP_MASK 0x00008000L |
26072 | #define CB_COLOR7_INFO__BLEND_BYPASS_MASK 0x00010000L |
26073 | #define CB_COLOR7_INFO__SIMPLE_FLOAT_MASK 0x00020000L |
26074 | #define CB_COLOR7_INFO__ROUND_MODE_MASK 0x00040000L |
26075 | #define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x00700000L |
26076 | #define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x03800000L |
26077 | //CB_COLOR7_ATTRIB |
26078 | #define CB_COLOR7_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0 |
26079 | #define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x2 |
26080 | #define CB_COLOR7_ATTRIB__DISABLE_FMASK_NOALLOC_OPT__SHIFT 0x3 |
26081 | #define CB_COLOR7_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX__SHIFT 0x4 |
26082 | #define CB_COLOR7_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX__SHIFT 0x5 |
26083 | #define CB_COLOR7_ATTRIB__NUM_FRAGMENTS_MASK 0x00000003L |
26084 | #define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00000004L |
26085 | #define CB_COLOR7_ATTRIB__DISABLE_FMASK_NOALLOC_OPT_MASK 0x00000008L |
26086 | #define CB_COLOR7_ATTRIB__LIMIT_COLOR_FETCH_TO_256B_MAX_MASK 0x00000010L |
26087 | #define CB_COLOR7_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX_MASK 0x00000020L |
26088 | //CB_COLOR7_FDCC_CONTROL |
26089 | #define CB_COLOR7_FDCC_CONTROL__SAMPLE_MASK_TRACKER_DISABLE__SHIFT 0x0 |
26090 | #define CB_COLOR7_FDCC_CONTROL__SAMPLE_MASK_TRACKER_FEA_FORCE__SHIFT 0x1 |
26091 | #define CB_COLOR7_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 |
26092 | #define CB_COLOR7_FDCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 |
26093 | #define CB_COLOR7_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 |
26094 | #define CB_COLOR7_FDCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 |
26095 | #define CB_COLOR7_FDCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 |
26096 | #define CB_COLOR7_FDCC_CONTROL__INDEPENDENT_128B_BLOCKS__SHIFT 0xa |
26097 | #define CB_COLOR7_FDCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG__SHIFT 0x12 |
26098 | #define CB_COLOR7_FDCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE__SHIFT 0x13 |
26099 | #define CB_COLOR7_FDCC_CONTROL__SKIP_LOW_COMP_RATIO__SHIFT 0x15 |
26100 | #define CB_COLOR7_FDCC_CONTROL__FDCC_ENABLE__SHIFT 0x16 |
26101 | #define CB_COLOR7_FDCC_CONTROL__DCC_COMPRESS_DISABLE__SHIFT 0x17 |
26102 | #define CB_COLOR7_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE__SHIFT 0x18 |
26103 | #define CB_COLOR7_FDCC_CONTROL__SAMPLE_MASK_TRACKER_DISABLE_MASK 0x00000001L |
26104 | #define CB_COLOR7_FDCC_CONTROL__SAMPLE_MASK_TRACKER_FEA_FORCE_MASK 0x00000002L |
26105 | #define CB_COLOR7_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x0000000CL |
26106 | #define CB_COLOR7_FDCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x00000010L |
26107 | #define CB_COLOR7_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L |
26108 | #define CB_COLOR7_FDCC_CONTROL__COLOR_TRANSFORM_MASK 0x00000180L |
26109 | #define CB_COLOR7_FDCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x00000200L |
26110 | #define CB_COLOR7_FDCC_CONTROL__INDEPENDENT_128B_BLOCKS_MASK 0x00000400L |
26111 | #define CB_COLOR7_FDCC_CONTROL__DISABLE_CONSTANT_ENCODE_REG_MASK 0x00040000L |
26112 | #define CB_COLOR7_FDCC_CONTROL__ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK 0x00080000L |
26113 | #define CB_COLOR7_FDCC_CONTROL__SKIP_LOW_COMP_RATIO_MASK 0x00200000L |
26114 | #define CB_COLOR7_FDCC_CONTROL__FDCC_ENABLE_MASK 0x00400000L |
26115 | #define CB_COLOR7_FDCC_CONTROL__DCC_COMPRESS_DISABLE_MASK 0x00800000L |
26116 | #define CB_COLOR7_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE_MASK 0x01000000L |
26117 | //CB_COLOR7_DCC_BASE |
26118 | #define CB_COLOR7_DCC_BASE__BASE_256B__SHIFT 0x0 |
26119 | #define CB_COLOR7_DCC_BASE__BASE_256B_MASK 0xFFFFFFFFL |
26120 | //CB_COLOR0_BASE_EXT |
26121 | #define CB_COLOR0_BASE_EXT__BASE_256B__SHIFT 0x0 |
26122 | #define CB_COLOR0_BASE_EXT__BASE_256B_MASK 0x000000FFL |
26123 | //CB_COLOR1_BASE_EXT |
26124 | #define CB_COLOR1_BASE_EXT__BASE_256B__SHIFT 0x0 |
26125 | #define CB_COLOR1_BASE_EXT__BASE_256B_MASK 0x000000FFL |
26126 | //CB_COLOR2_BASE_EXT |
26127 | #define CB_COLOR2_BASE_EXT__BASE_256B__SHIFT 0x0 |
26128 | #define CB_COLOR2_BASE_EXT__BASE_256B_MASK 0x000000FFL |
26129 | //CB_COLOR3_BASE_EXT |
26130 | #define CB_COLOR3_BASE_EXT__BASE_256B__SHIFT 0x0 |
26131 | #define CB_COLOR3_BASE_EXT__BASE_256B_MASK 0x000000FFL |
26132 | //CB_COLOR4_BASE_EXT |
26133 | #define CB_COLOR4_BASE_EXT__BASE_256B__SHIFT 0x0 |
26134 | #define CB_COLOR4_BASE_EXT__BASE_256B_MASK 0x000000FFL |
26135 | //CB_COLOR5_BASE_EXT |
26136 | #define CB_COLOR5_BASE_EXT__BASE_256B__SHIFT 0x0 |
26137 | #define CB_COLOR5_BASE_EXT__BASE_256B_MASK 0x000000FFL |
26138 | //CB_COLOR6_BASE_EXT |
26139 | #define CB_COLOR6_BASE_EXT__BASE_256B__SHIFT 0x0 |
26140 | #define CB_COLOR6_BASE_EXT__BASE_256B_MASK 0x000000FFL |
26141 | //CB_COLOR7_BASE_EXT |
26142 | #define CB_COLOR7_BASE_EXT__BASE_256B__SHIFT 0x0 |
26143 | #define CB_COLOR7_BASE_EXT__BASE_256B_MASK 0x000000FFL |
26144 | //CB_COLOR0_DCC_BASE_EXT |
26145 | #define CB_COLOR0_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 |
26146 | #define CB_COLOR0_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL |
26147 | //CB_COLOR1_DCC_BASE_EXT |
26148 | #define CB_COLOR1_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 |
26149 | #define CB_COLOR1_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL |
26150 | //CB_COLOR2_DCC_BASE_EXT |
26151 | #define CB_COLOR2_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 |
26152 | #define CB_COLOR2_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL |
26153 | //CB_COLOR3_DCC_BASE_EXT |
26154 | #define CB_COLOR3_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 |
26155 | #define CB_COLOR3_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL |
26156 | //CB_COLOR4_DCC_BASE_EXT |
26157 | #define CB_COLOR4_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 |
26158 | #define CB_COLOR4_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL |
26159 | //CB_COLOR5_DCC_BASE_EXT |
26160 | #define CB_COLOR5_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 |
26161 | #define CB_COLOR5_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL |
26162 | //CB_COLOR6_DCC_BASE_EXT |
26163 | #define CB_COLOR6_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 |
26164 | #define CB_COLOR6_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL |
26165 | //CB_COLOR7_DCC_BASE_EXT |
26166 | #define CB_COLOR7_DCC_BASE_EXT__BASE_256B__SHIFT 0x0 |
26167 | #define CB_COLOR7_DCC_BASE_EXT__BASE_256B_MASK 0x000000FFL |
26168 | //CB_COLOR0_ATTRIB2 |
26169 | #define CB_COLOR0_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 |
26170 | #define CB_COLOR0_ATTRIB2__MIP0_WIDTH__SHIFT 0xe |
26171 | #define CB_COLOR0_ATTRIB2__MAX_MIP__SHIFT 0x1c |
26172 | #define CB_COLOR0_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL |
26173 | #define CB_COLOR0_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L |
26174 | #define CB_COLOR0_ATTRIB2__MAX_MIP_MASK 0xF0000000L |
26175 | //CB_COLOR1_ATTRIB2 |
26176 | #define CB_COLOR1_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 |
26177 | #define CB_COLOR1_ATTRIB2__MIP0_WIDTH__SHIFT 0xe |
26178 | #define CB_COLOR1_ATTRIB2__MAX_MIP__SHIFT 0x1c |
26179 | #define CB_COLOR1_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL |
26180 | #define CB_COLOR1_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L |
26181 | #define CB_COLOR1_ATTRIB2__MAX_MIP_MASK 0xF0000000L |
26182 | //CB_COLOR2_ATTRIB2 |
26183 | #define CB_COLOR2_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 |
26184 | #define CB_COLOR2_ATTRIB2__MIP0_WIDTH__SHIFT 0xe |
26185 | #define CB_COLOR2_ATTRIB2__MAX_MIP__SHIFT 0x1c |
26186 | #define CB_COLOR2_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL |
26187 | #define CB_COLOR2_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L |
26188 | #define CB_COLOR2_ATTRIB2__MAX_MIP_MASK 0xF0000000L |
26189 | //CB_COLOR3_ATTRIB2 |
26190 | #define CB_COLOR3_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 |
26191 | #define CB_COLOR3_ATTRIB2__MIP0_WIDTH__SHIFT 0xe |
26192 | #define CB_COLOR3_ATTRIB2__MAX_MIP__SHIFT 0x1c |
26193 | #define CB_COLOR3_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL |
26194 | #define CB_COLOR3_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L |
26195 | #define CB_COLOR3_ATTRIB2__MAX_MIP_MASK 0xF0000000L |
26196 | //CB_COLOR4_ATTRIB2 |
26197 | #define CB_COLOR4_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 |
26198 | #define CB_COLOR4_ATTRIB2__MIP0_WIDTH__SHIFT 0xe |
26199 | #define CB_COLOR4_ATTRIB2__MAX_MIP__SHIFT 0x1c |
26200 | #define CB_COLOR4_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL |
26201 | #define CB_COLOR4_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L |
26202 | #define CB_COLOR4_ATTRIB2__MAX_MIP_MASK 0xF0000000L |
26203 | //CB_COLOR5_ATTRIB2 |
26204 | #define CB_COLOR5_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 |
26205 | #define CB_COLOR5_ATTRIB2__MIP0_WIDTH__SHIFT 0xe |
26206 | #define CB_COLOR5_ATTRIB2__MAX_MIP__SHIFT 0x1c |
26207 | #define CB_COLOR5_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL |
26208 | #define CB_COLOR5_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L |
26209 | #define CB_COLOR5_ATTRIB2__MAX_MIP_MASK 0xF0000000L |
26210 | //CB_COLOR6_ATTRIB2 |
26211 | #define CB_COLOR6_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 |
26212 | #define CB_COLOR6_ATTRIB2__MIP0_WIDTH__SHIFT 0xe |
26213 | #define CB_COLOR6_ATTRIB2__MAX_MIP__SHIFT 0x1c |
26214 | #define CB_COLOR6_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL |
26215 | #define CB_COLOR6_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L |
26216 | #define CB_COLOR6_ATTRIB2__MAX_MIP_MASK 0xF0000000L |
26217 | //CB_COLOR7_ATTRIB2 |
26218 | #define CB_COLOR7_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 |
26219 | #define CB_COLOR7_ATTRIB2__MIP0_WIDTH__SHIFT 0xe |
26220 | #define CB_COLOR7_ATTRIB2__MAX_MIP__SHIFT 0x1c |
26221 | #define CB_COLOR7_ATTRIB2__MIP0_HEIGHT_MASK 0x00003FFFL |
26222 | #define CB_COLOR7_ATTRIB2__MIP0_WIDTH_MASK 0x0FFFC000L |
26223 | #define CB_COLOR7_ATTRIB2__MAX_MIP_MASK 0xF0000000L |
26224 | //CB_COLOR0_ATTRIB3 |
26225 | #define CB_COLOR0_ATTRIB3__MIP0_DEPTH__SHIFT 0x0 |
26226 | #define CB_COLOR0_ATTRIB3__META_LINEAR__SHIFT 0xd |
26227 | #define CB_COLOR0_ATTRIB3__COLOR_SW_MODE__SHIFT 0xe |
26228 | #define CB_COLOR0_ATTRIB3__RESOURCE_TYPE__SHIFT 0x18 |
26229 | #define CB_COLOR0_ATTRIB3__DCC_PIPE_ALIGNED__SHIFT 0x1e |
26230 | #define CB_COLOR0_ATTRIB3__MIP0_DEPTH_MASK 0x00001FFFL |
26231 | #define CB_COLOR0_ATTRIB3__META_LINEAR_MASK 0x00002000L |
26232 | #define CB_COLOR0_ATTRIB3__COLOR_SW_MODE_MASK 0x0007C000L |
26233 | #define CB_COLOR0_ATTRIB3__RESOURCE_TYPE_MASK 0x03000000L |
26234 | #define CB_COLOR0_ATTRIB3__DCC_PIPE_ALIGNED_MASK 0x40000000L |
26235 | //CB_COLOR1_ATTRIB3 |
26236 | #define CB_COLOR1_ATTRIB3__MIP0_DEPTH__SHIFT 0x0 |
26237 | #define CB_COLOR1_ATTRIB3__META_LINEAR__SHIFT 0xd |
26238 | #define CB_COLOR1_ATTRIB3__COLOR_SW_MODE__SHIFT 0xe |
26239 | #define CB_COLOR1_ATTRIB3__RESOURCE_TYPE__SHIFT 0x18 |
26240 | #define CB_COLOR1_ATTRIB3__DCC_PIPE_ALIGNED__SHIFT 0x1e |
26241 | #define CB_COLOR1_ATTRIB3__MIP0_DEPTH_MASK 0x00001FFFL |
26242 | #define CB_COLOR1_ATTRIB3__META_LINEAR_MASK 0x00002000L |
26243 | #define CB_COLOR1_ATTRIB3__COLOR_SW_MODE_MASK 0x0007C000L |
26244 | #define CB_COLOR1_ATTRIB3__RESOURCE_TYPE_MASK 0x03000000L |
26245 | #define CB_COLOR1_ATTRIB3__DCC_PIPE_ALIGNED_MASK 0x40000000L |
26246 | //CB_COLOR2_ATTRIB3 |
26247 | #define CB_COLOR2_ATTRIB3__MIP0_DEPTH__SHIFT 0x0 |
26248 | #define CB_COLOR2_ATTRIB3__META_LINEAR__SHIFT 0xd |
26249 | #define CB_COLOR2_ATTRIB3__COLOR_SW_MODE__SHIFT 0xe |
26250 | #define CB_COLOR2_ATTRIB3__RESOURCE_TYPE__SHIFT 0x18 |
26251 | #define CB_COLOR2_ATTRIB3__DCC_PIPE_ALIGNED__SHIFT 0x1e |
26252 | #define CB_COLOR2_ATTRIB3__MIP0_DEPTH_MASK 0x00001FFFL |
26253 | #define CB_COLOR2_ATTRIB3__META_LINEAR_MASK 0x00002000L |
26254 | #define CB_COLOR2_ATTRIB3__COLOR_SW_MODE_MASK 0x0007C000L |
26255 | #define CB_COLOR2_ATTRIB3__RESOURCE_TYPE_MASK 0x03000000L |
26256 | #define CB_COLOR2_ATTRIB3__DCC_PIPE_ALIGNED_MASK 0x40000000L |
26257 | //CB_COLOR3_ATTRIB3 |
26258 | #define CB_COLOR3_ATTRIB3__MIP0_DEPTH__SHIFT 0x0 |
26259 | #define CB_COLOR3_ATTRIB3__META_LINEAR__SHIFT 0xd |
26260 | #define CB_COLOR3_ATTRIB3__COLOR_SW_MODE__SHIFT 0xe |
26261 | #define CB_COLOR3_ATTRIB3__RESOURCE_TYPE__SHIFT 0x18 |
26262 | #define CB_COLOR3_ATTRIB3__DCC_PIPE_ALIGNED__SHIFT 0x1e |
26263 | #define CB_COLOR3_ATTRIB3__MIP0_DEPTH_MASK 0x00001FFFL |
26264 | #define CB_COLOR3_ATTRIB3__META_LINEAR_MASK 0x00002000L |
26265 | #define CB_COLOR3_ATTRIB3__COLOR_SW_MODE_MASK 0x0007C000L |
26266 | #define CB_COLOR3_ATTRIB3__RESOURCE_TYPE_MASK 0x03000000L |
26267 | #define CB_COLOR3_ATTRIB3__DCC_PIPE_ALIGNED_MASK 0x40000000L |
26268 | //CB_COLOR4_ATTRIB3 |
26269 | #define CB_COLOR4_ATTRIB3__MIP0_DEPTH__SHIFT 0x0 |
26270 | #define CB_COLOR4_ATTRIB3__META_LINEAR__SHIFT 0xd |
26271 | #define CB_COLOR4_ATTRIB3__COLOR_SW_MODE__SHIFT 0xe |
26272 | #define CB_COLOR4_ATTRIB3__RESOURCE_TYPE__SHIFT 0x18 |
26273 | #define CB_COLOR4_ATTRIB3__DCC_PIPE_ALIGNED__SHIFT 0x1e |
26274 | #define CB_COLOR4_ATTRIB3__MIP0_DEPTH_MASK 0x00001FFFL |
26275 | #define CB_COLOR4_ATTRIB3__META_LINEAR_MASK 0x00002000L |
26276 | #define CB_COLOR4_ATTRIB3__COLOR_SW_MODE_MASK 0x0007C000L |
26277 | #define CB_COLOR4_ATTRIB3__RESOURCE_TYPE_MASK 0x03000000L |
26278 | #define CB_COLOR4_ATTRIB3__DCC_PIPE_ALIGNED_MASK 0x40000000L |
26279 | //CB_COLOR5_ATTRIB3 |
26280 | #define CB_COLOR5_ATTRIB3__MIP0_DEPTH__SHIFT 0x0 |
26281 | #define CB_COLOR5_ATTRIB3__META_LINEAR__SHIFT 0xd |
26282 | #define CB_COLOR5_ATTRIB3__COLOR_SW_MODE__SHIFT 0xe |
26283 | #define CB_COLOR5_ATTRIB3__RESOURCE_TYPE__SHIFT 0x18 |
26284 | #define CB_COLOR5_ATTRIB3__DCC_PIPE_ALIGNED__SHIFT 0x1e |
26285 | #define CB_COLOR5_ATTRIB3__MIP0_DEPTH_MASK 0x00001FFFL |
26286 | #define CB_COLOR5_ATTRIB3__META_LINEAR_MASK 0x00002000L |
26287 | #define CB_COLOR5_ATTRIB3__COLOR_SW_MODE_MASK 0x0007C000L |
26288 | #define CB_COLOR5_ATTRIB3__RESOURCE_TYPE_MASK 0x03000000L |
26289 | #define CB_COLOR5_ATTRIB3__DCC_PIPE_ALIGNED_MASK 0x40000000L |
26290 | //CB_COLOR6_ATTRIB3 |
26291 | #define CB_COLOR6_ATTRIB3__MIP0_DEPTH__SHIFT 0x0 |
26292 | #define CB_COLOR6_ATTRIB3__META_LINEAR__SHIFT 0xd |
26293 | #define CB_COLOR6_ATTRIB3__COLOR_SW_MODE__SHIFT 0xe |
26294 | #define CB_COLOR6_ATTRIB3__RESOURCE_TYPE__SHIFT 0x18 |
26295 | #define CB_COLOR6_ATTRIB3__DCC_PIPE_ALIGNED__SHIFT 0x1e |
26296 | #define CB_COLOR6_ATTRIB3__MIP0_DEPTH_MASK 0x00001FFFL |
26297 | #define CB_COLOR6_ATTRIB3__META_LINEAR_MASK 0x00002000L |
26298 | #define CB_COLOR6_ATTRIB3__COLOR_SW_MODE_MASK 0x0007C000L |
26299 | #define CB_COLOR6_ATTRIB3__RESOURCE_TYPE_MASK 0x03000000L |
26300 | #define CB_COLOR6_ATTRIB3__DCC_PIPE_ALIGNED_MASK 0x40000000L |
26301 | //CB_COLOR7_ATTRIB3 |
26302 | #define CB_COLOR7_ATTRIB3__MIP0_DEPTH__SHIFT 0x0 |
26303 | #define CB_COLOR7_ATTRIB3__META_LINEAR__SHIFT 0xd |
26304 | #define CB_COLOR7_ATTRIB3__COLOR_SW_MODE__SHIFT 0xe |
26305 | #define CB_COLOR7_ATTRIB3__RESOURCE_TYPE__SHIFT 0x18 |
26306 | #define CB_COLOR7_ATTRIB3__DCC_PIPE_ALIGNED__SHIFT 0x1e |
26307 | #define CB_COLOR7_ATTRIB3__MIP0_DEPTH_MASK 0x00001FFFL |
26308 | #define CB_COLOR7_ATTRIB3__META_LINEAR_MASK 0x00002000L |
26309 | #define CB_COLOR7_ATTRIB3__COLOR_SW_MODE_MASK 0x0007C000L |
26310 | #define CB_COLOR7_ATTRIB3__RESOURCE_TYPE_MASK 0x03000000L |
26311 | #define CB_COLOR7_ATTRIB3__DCC_PIPE_ALIGNED_MASK 0x40000000L |
26312 | |
26313 | |
26314 | // addressBlock: gc_pfvf_cpdec |
26315 | //CONFIG_RESERVED_REG0 |
26316 | #define CONFIG_RESERVED_REG0__DATA__SHIFT 0x0 |
26317 | #define CONFIG_RESERVED_REG0__DATA_MASK 0xFFFFFFFFL |
26318 | //CONFIG_RESERVED_REG1 |
26319 | #define CONFIG_RESERVED_REG1__DATA__SHIFT 0x0 |
26320 | #define CONFIG_RESERVED_REG1__DATA_MASK 0xFFFFFFFFL |
26321 | //CP_MEC_CNTL |
26322 | #define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET__SHIFT 0x10 |
26323 | #define CP_MEC_CNTL__MEC_ME1_PIPE1_RESET__SHIFT 0x11 |
26324 | #define CP_MEC_CNTL__MEC_ME1_PIPE2_RESET__SHIFT 0x12 |
26325 | #define CP_MEC_CNTL__MEC_ME1_PIPE3_RESET__SHIFT 0x13 |
26326 | #define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET__SHIFT 0x14 |
26327 | #define CP_MEC_CNTL__MEC_ME2_PIPE1_RESET__SHIFT 0x15 |
26328 | #define CP_MEC_CNTL__MEC_ME2_PIPE2_RESET__SHIFT 0x16 |
26329 | #define CP_MEC_CNTL__MEC_ME2_PIPE3_RESET__SHIFT 0x17 |
26330 | #define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE__SHIFT 0x1b |
26331 | #define CP_MEC_CNTL__MEC_ME2_HALT__SHIFT 0x1c |
26332 | #define CP_MEC_CNTL__MEC_ME2_STEP__SHIFT 0x1d |
26333 | #define CP_MEC_CNTL__MEC_ME1_HALT__SHIFT 0x1e |
26334 | #define CP_MEC_CNTL__MEC_ME1_STEP__SHIFT 0x1f |
26335 | #define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET_MASK 0x00010000L |
26336 | #define CP_MEC_CNTL__MEC_ME1_PIPE1_RESET_MASK 0x00020000L |
26337 | #define CP_MEC_CNTL__MEC_ME1_PIPE2_RESET_MASK 0x00040000L |
26338 | #define CP_MEC_CNTL__MEC_ME1_PIPE3_RESET_MASK 0x00080000L |
26339 | #define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET_MASK 0x00100000L |
26340 | #define CP_MEC_CNTL__MEC_ME2_PIPE1_RESET_MASK 0x00200000L |
26341 | #define CP_MEC_CNTL__MEC_ME2_PIPE2_RESET_MASK 0x00400000L |
26342 | #define CP_MEC_CNTL__MEC_ME2_PIPE3_RESET_MASK 0x00800000L |
26343 | #define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE_MASK 0x08000000L |
26344 | #define CP_MEC_CNTL__MEC_ME2_HALT_MASK 0x10000000L |
26345 | #define CP_MEC_CNTL__MEC_ME2_STEP_MASK 0x20000000L |
26346 | #define CP_MEC_CNTL__MEC_ME1_HALT_MASK 0x40000000L |
26347 | #define CP_MEC_CNTL__MEC_ME1_STEP_MASK 0x80000000L |
26348 | //CP_ME_CNTL |
26349 | #define CP_ME_CNTL__CE_INVALIDATE_ICACHE__SHIFT 0x4 |
26350 | #define CP_ME_CNTL__PFP_INVALIDATE_ICACHE__SHIFT 0x6 |
26351 | #define CP_ME_CNTL__ME_INVALIDATE_ICACHE__SHIFT 0x8 |
26352 | #define CP_ME_CNTL__PFP_PIPE0_DISABLE__SHIFT 0xc |
26353 | #define CP_ME_CNTL__PFP_PIPE1_DISABLE__SHIFT 0xd |
26354 | #define CP_ME_CNTL__ME_PIPE0_DISABLE__SHIFT 0xe |
26355 | #define CP_ME_CNTL__ME_PIPE1_DISABLE__SHIFT 0xf |
26356 | #define CP_ME_CNTL__CE_PIPE0_RESET__SHIFT 0x10 |
26357 | #define CP_ME_CNTL__CE_PIPE1_RESET__SHIFT 0x11 |
26358 | #define CP_ME_CNTL__PFP_PIPE0_RESET__SHIFT 0x12 |
26359 | #define CP_ME_CNTL__PFP_PIPE1_RESET__SHIFT 0x13 |
26360 | #define CP_ME_CNTL__ME_PIPE0_RESET__SHIFT 0x14 |
26361 | #define CP_ME_CNTL__ME_PIPE1_RESET__SHIFT 0x15 |
26362 | #define CP_ME_CNTL__CE_HALT__SHIFT 0x18 |
26363 | #define CP_ME_CNTL__CE_STEP__SHIFT 0x19 |
26364 | #define CP_ME_CNTL__PFP_HALT__SHIFT 0x1a |
26365 | #define CP_ME_CNTL__PFP_STEP__SHIFT 0x1b |
26366 | #define CP_ME_CNTL__ME_HALT__SHIFT 0x1c |
26367 | #define CP_ME_CNTL__ME_STEP__SHIFT 0x1d |
26368 | #define CP_ME_CNTL__CE_INVALIDATE_ICACHE_MASK 0x00000010L |
26369 | #define CP_ME_CNTL__PFP_INVALIDATE_ICACHE_MASK 0x00000040L |
26370 | #define CP_ME_CNTL__ME_INVALIDATE_ICACHE_MASK 0x00000100L |
26371 | #define CP_ME_CNTL__PFP_PIPE0_DISABLE_MASK 0x00001000L |
26372 | #define CP_ME_CNTL__PFP_PIPE1_DISABLE_MASK 0x00002000L |
26373 | #define CP_ME_CNTL__ME_PIPE0_DISABLE_MASK 0x00004000L |
26374 | #define CP_ME_CNTL__ME_PIPE1_DISABLE_MASK 0x00008000L |
26375 | #define CP_ME_CNTL__CE_PIPE0_RESET_MASK 0x00010000L |
26376 | #define CP_ME_CNTL__CE_PIPE1_RESET_MASK 0x00020000L |
26377 | #define CP_ME_CNTL__PFP_PIPE0_RESET_MASK 0x00040000L |
26378 | #define CP_ME_CNTL__PFP_PIPE1_RESET_MASK 0x00080000L |
26379 | #define CP_ME_CNTL__ME_PIPE0_RESET_MASK 0x00100000L |
26380 | #define CP_ME_CNTL__ME_PIPE1_RESET_MASK 0x00200000L |
26381 | #define CP_ME_CNTL__CE_HALT_MASK 0x01000000L |
26382 | #define CP_ME_CNTL__CE_STEP_MASK 0x02000000L |
26383 | #define CP_ME_CNTL__PFP_HALT_MASK 0x04000000L |
26384 | #define CP_ME_CNTL__PFP_STEP_MASK 0x08000000L |
26385 | #define CP_ME_CNTL__ME_HALT_MASK 0x10000000L |
26386 | #define CP_ME_CNTL__ME_STEP_MASK 0x20000000L |
26387 | |
26388 | |
26389 | // addressBlock: gc_pfvf_grbmdec |
26390 | //GRBM_GFX_CNTL |
26391 | #define GRBM_GFX_CNTL__PIPEID__SHIFT 0x0 |
26392 | #define GRBM_GFX_CNTL__MEID__SHIFT 0x2 |
26393 | #define GRBM_GFX_CNTL__VMID__SHIFT 0x4 |
26394 | #define GRBM_GFX_CNTL__QUEUEID__SHIFT 0x8 |
26395 | #define GRBM_GFX_CNTL__CTXID__SHIFT 0xb |
26396 | #define GRBM_GFX_CNTL__PIPEID_MASK 0x00000003L |
26397 | #define GRBM_GFX_CNTL__MEID_MASK 0x0000000CL |
26398 | #define GRBM_GFX_CNTL__VMID_MASK 0x000000F0L |
26399 | #define GRBM_GFX_CNTL__QUEUEID_MASK 0x00000700L |
26400 | #define GRBM_GFX_CNTL__CTXID_MASK 0x00003800L |
26401 | //GRBM_NOWHERE |
26402 | #define GRBM_NOWHERE__DATA__SHIFT 0x0 |
26403 | #define GRBM_NOWHERE__DATA_MASK 0xFFFFFFFFL |
26404 | |
26405 | |
26406 | // addressBlock: gc_pfvf_padec |
26407 | //PA_SC_VRS_SURFACE_CNTL |
26408 | #define PA_SC_VRS_SURFACE_CNTL__VRC_CONTEXT_DONE_SYNC_DISABLE__SHIFT 0x6 |
26409 | #define PA_SC_VRS_SURFACE_CNTL__VRS_FEEDBACK_RATE_OVERRIDE__SHIFT 0x7 |
26410 | #define PA_SC_VRS_SURFACE_CNTL__VRC_FLUSH_EVENT_MASK_DISABLE__SHIFT 0x8 |
26411 | #define PA_SC_VRS_SURFACE_CNTL__VRC_PREFETCH_DISABLE__SHIFT 0xd |
26412 | #define PA_SC_VRS_SURFACE_CNTL__VRC_FLUSH_NO_INV_DISABLE__SHIFT 0xe |
26413 | #define PA_SC_VRS_SURFACE_CNTL__VRC_NONSTALLING_FLUSH_DISABLE__SHIFT 0xf |
26414 | #define PA_SC_VRS_SURFACE_CNTL__VRC_PARTIAL_FLUSH_DISABLE__SHIFT 0x10 |
26415 | #define PA_SC_VRS_SURFACE_CNTL__VRC_AUTO_FLUSH__SHIFT 0x11 |
26416 | #define PA_SC_VRS_SURFACE_CNTL__VRC_EOP_SYNC_DISABLE__SHIFT 0x12 |
26417 | #define PA_SC_VRS_SURFACE_CNTL__VRC_MAX_TAGS__SHIFT 0x13 |
26418 | #define PA_SC_VRS_SURFACE_CNTL__VRC_EVICT_POINT__SHIFT 0x1a |
26419 | #define PA_SC_VRS_SURFACE_CNTL__VRC_CONTEXT_DONE_SYNC_DISABLE_MASK 0x00000040L |
26420 | #define PA_SC_VRS_SURFACE_CNTL__VRS_FEEDBACK_RATE_OVERRIDE_MASK 0x00000080L |
26421 | #define PA_SC_VRS_SURFACE_CNTL__VRC_FLUSH_EVENT_MASK_DISABLE_MASK 0x00001F00L |
26422 | #define PA_SC_VRS_SURFACE_CNTL__VRC_PREFETCH_DISABLE_MASK 0x00002000L |
26423 | #define PA_SC_VRS_SURFACE_CNTL__VRC_FLUSH_NO_INV_DISABLE_MASK 0x00004000L |
26424 | #define PA_SC_VRS_SURFACE_CNTL__VRC_NONSTALLING_FLUSH_DISABLE_MASK 0x00008000L |
26425 | #define PA_SC_VRS_SURFACE_CNTL__VRC_PARTIAL_FLUSH_DISABLE_MASK 0x00010000L |
26426 | #define PA_SC_VRS_SURFACE_CNTL__VRC_AUTO_FLUSH_MASK 0x00020000L |
26427 | #define PA_SC_VRS_SURFACE_CNTL__VRC_EOP_SYNC_DISABLE_MASK 0x00040000L |
26428 | #define PA_SC_VRS_SURFACE_CNTL__VRC_MAX_TAGS_MASK 0x03F80000L |
26429 | #define PA_SC_VRS_SURFACE_CNTL__VRC_EVICT_POINT_MASK 0xFC000000L |
26430 | //PA_SC_ENHANCE |
26431 | #define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER__SHIFT 0x0 |
26432 | #define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX__SHIFT 0x1 |
26433 | #define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX__SHIFT 0x2 |
26434 | #define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS__SHIFT 0x3 |
26435 | #define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID__SHIFT 0x4 |
26436 | #define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX__SHIFT 0x5 |
26437 | #define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER__SHIFT 0x6 |
26438 | #define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION__SHIFT 0x7 |
26439 | #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM__SHIFT 0x8 |
26440 | #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE__SHIFT 0x9 |
26441 | #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE__SHIFT 0xa |
26442 | #define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE__SHIFT 0xb |
26443 | #define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS__SHIFT 0xc |
26444 | #define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE__SHIFT 0xd |
26445 | #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE__SHIFT 0xe |
26446 | #define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE__SHIFT 0xf |
26447 | #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST__SHIFT 0x10 |
26448 | #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING__SHIFT 0x11 |
26449 | #define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY__SHIFT 0x12 |
26450 | #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING__SHIFT 0x13 |
26451 | #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING__SHIFT 0x14 |
26452 | #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS__SHIFT 0x15 |
26453 | #define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID__SHIFT 0x16 |
26454 | #define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO__SHIFT 0x17 |
26455 | #define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT__SHIFT 0x18 |
26456 | #define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING__SHIFT 0x19 |
26457 | #define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET__SHIFT 0x1a |
26458 | #define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET__SHIFT 0x1b |
26459 | #define PA_SC_ENHANCE__IOO_DISABLE_SCAN_UNSELECTED_FIFOS_FOR_DUAL_GFX_RING_CHANGE__SHIFT 0x1c |
26460 | #define PA_SC_ENHANCE__OOO_USE_ABSOLUTE_FIFO_COUNT_IN_THRESHOLD_SWITCHING__SHIFT 0x1d |
26461 | #define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK 0x00000001L |
26462 | #define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX_MASK 0x00000002L |
26463 | #define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX_MASK 0x00000004L |
26464 | #define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS_MASK 0x00000008L |
26465 | #define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID_MASK 0x00000010L |
26466 | #define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX_MASK 0x00000020L |
26467 | #define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER_MASK 0x00000040L |
26468 | #define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION_MASK 0x00000080L |
26469 | #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM_MASK 0x00000100L |
26470 | #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE_MASK 0x00000200L |
26471 | #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE_MASK 0x00000400L |
26472 | #define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE_MASK 0x00000800L |
26473 | #define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS_MASK 0x00001000L |
26474 | #define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE_MASK 0x00002000L |
26475 | #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE_MASK 0x00004000L |
26476 | #define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE_MASK 0x00008000L |
26477 | #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST_MASK 0x00010000L |
26478 | #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING_MASK 0x00020000L |
26479 | #define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY_MASK 0x00040000L |
26480 | #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING_MASK 0x00080000L |
26481 | #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING_MASK 0x00100000L |
26482 | #define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS_MASK 0x00200000L |
26483 | #define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID_MASK 0x00400000L |
26484 | #define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO_MASK 0x00800000L |
26485 | #define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT_MASK 0x01000000L |
26486 | #define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING_MASK 0x02000000L |
26487 | #define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET_MASK 0x04000000L |
26488 | #define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET_MASK 0x08000000L |
26489 | #define PA_SC_ENHANCE__IOO_DISABLE_SCAN_UNSELECTED_FIFOS_FOR_DUAL_GFX_RING_CHANGE_MASK 0x10000000L |
26490 | #define PA_SC_ENHANCE__OOO_USE_ABSOLUTE_FIFO_COUNT_IN_THRESHOLD_SWITCHING_MASK 0x20000000L |
26491 | //PA_SC_ENHANCE_1 |
26492 | #define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_ENABLE__SHIFT 0x0 |
26493 | #define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE__SHIFT 0x1 |
26494 | #define PA_SC_ENHANCE_1__DISABLE_SC_BINNING__SHIFT 0x3 |
26495 | #define PA_SC_ENHANCE_1__BYPASS_PBB__SHIFT 0x4 |
26496 | #define PA_SC_ENHANCE_1__DISABLE_NONBINNED_LIVE_PRIM_DG1_LS0_CL0_EOPKT_POKE__SHIFT 0x5 |
26497 | #define PA_SC_ENHANCE_1__ECO_SPARE1__SHIFT 0x6 |
26498 | #define PA_SC_ENHANCE_1__ECO_SPARE2__SHIFT 0x7 |
26499 | #define PA_SC_ENHANCE_1__ECO_SPARE3__SHIFT 0x8 |
26500 | #define PA_SC_ENHANCE_1__DISABLE_SC_PROCESS_RESET_PBB__SHIFT 0x9 |
26501 | #define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_OPT__SHIFT 0xa |
26502 | #define PA_SC_ENHANCE_1__ENABLE_DFSM_FLUSH_EVENT_TO_FLUSH_POPS_CAM__SHIFT 0xb |
26503 | #define PA_SC_ENHANCE_1__DEBUG_PIXEL_PICKER_COUNT_PIXELS__SHIFT 0xd |
26504 | #define PA_SC_ENHANCE_1__DISABLE_SC_DB_TILE_INTF_FINE_CLOCK_GATE__SHIFT 0xe |
26505 | #define PA_SC_ENHANCE_1__DISABLE_PACKER_ODC_ENHANCE__SHIFT 0x10 |
26506 | #define PA_SC_ENHANCE_1__OPTIMAL_BIN_SELECTION__SHIFT 0x12 |
26507 | #define PA_SC_ENHANCE_1__DISABLE_FORCE_SOP_ALL_EVENTS__SHIFT 0x13 |
26508 | #define PA_SC_ENHANCE_1__DISABLE_PBB_CLK_OPTIMIZATION__SHIFT 0x14 |
26509 | #define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_CLK_OPTIMIZATION__SHIFT 0x15 |
26510 | #define PA_SC_ENHANCE_1__DISABLE_PBB_BINNING_CLK_OPTIMIZATION__SHIFT 0x16 |
26511 | #define PA_SC_ENHANCE_1__DISABLE_INTF_CG__SHIFT 0x17 |
26512 | #define PA_SC_ENHANCE_1__IOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT__SHIFT 0x18 |
26513 | #define PA_SC_ENHANCE_1__DISABLE_SHADER_PROFILING_FOR_POWER__SHIFT 0x19 |
26514 | #define PA_SC_ENHANCE_1__FLUSH_ON_BINNING_TRANSITION__SHIFT 0x1a |
26515 | #define PA_SC_ENHANCE_1__DISABLE_QUAD_PROC_FDCE_ENHANCE__SHIFT 0x1b |
26516 | #define PA_SC_ENHANCE_1__DISABLE_SC_PS_PA_ARBITER_FIX__SHIFT 0x1c |
26517 | #define PA_SC_ENHANCE_1__DISABLE_SC_PS_PA_ARBITER_FIX_1__SHIFT 0x1d |
26518 | #define PA_SC_ENHANCE_1__PASS_VPZ_EVENT_TO_SPI__SHIFT 0x1e |
26519 | #define PA_SC_ENHANCE_1__DISABLE_FSR_NEAR_AXIS_LINE_VERT_ORDER_SORT_FIX__SHIFT 0x1f |
26520 | #define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_ENABLE_MASK 0x00000001L |
26521 | #define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_MASK 0x00000006L |
26522 | #define PA_SC_ENHANCE_1__DISABLE_SC_BINNING_MASK 0x00000008L |
26523 | #define PA_SC_ENHANCE_1__BYPASS_PBB_MASK 0x00000010L |
26524 | #define PA_SC_ENHANCE_1__DISABLE_NONBINNED_LIVE_PRIM_DG1_LS0_CL0_EOPKT_POKE_MASK 0x00000020L |
26525 | #define PA_SC_ENHANCE_1__ECO_SPARE1_MASK 0x00000040L |
26526 | #define PA_SC_ENHANCE_1__ECO_SPARE2_MASK 0x00000080L |
26527 | #define PA_SC_ENHANCE_1__ECO_SPARE3_MASK 0x00000100L |
26528 | #define PA_SC_ENHANCE_1__DISABLE_SC_PROCESS_RESET_PBB_MASK 0x00000200L |
26529 | #define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_OPT_MASK 0x00000400L |
26530 | #define PA_SC_ENHANCE_1__ENABLE_DFSM_FLUSH_EVENT_TO_FLUSH_POPS_CAM_MASK 0x00000800L |
26531 | #define PA_SC_ENHANCE_1__DEBUG_PIXEL_PICKER_COUNT_PIXELS_MASK 0x00002000L |
26532 | #define PA_SC_ENHANCE_1__DISABLE_SC_DB_TILE_INTF_FINE_CLOCK_GATE_MASK 0x00004000L |
26533 | #define PA_SC_ENHANCE_1__DISABLE_PACKER_ODC_ENHANCE_MASK 0x00010000L |
26534 | #define PA_SC_ENHANCE_1__OPTIMAL_BIN_SELECTION_MASK 0x00040000L |
26535 | #define PA_SC_ENHANCE_1__DISABLE_FORCE_SOP_ALL_EVENTS_MASK 0x00080000L |
26536 | #define PA_SC_ENHANCE_1__DISABLE_PBB_CLK_OPTIMIZATION_MASK 0x00100000L |
26537 | #define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_CLK_OPTIMIZATION_MASK 0x00200000L |
26538 | #define PA_SC_ENHANCE_1__DISABLE_PBB_BINNING_CLK_OPTIMIZATION_MASK 0x00400000L |
26539 | #define PA_SC_ENHANCE_1__DISABLE_INTF_CG_MASK 0x00800000L |
26540 | #define PA_SC_ENHANCE_1__IOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT_MASK 0x01000000L |
26541 | #define PA_SC_ENHANCE_1__DISABLE_SHADER_PROFILING_FOR_POWER_MASK 0x02000000L |
26542 | #define PA_SC_ENHANCE_1__FLUSH_ON_BINNING_TRANSITION_MASK 0x04000000L |
26543 | #define PA_SC_ENHANCE_1__DISABLE_QUAD_PROC_FDCE_ENHANCE_MASK 0x08000000L |
26544 | #define PA_SC_ENHANCE_1__DISABLE_SC_PS_PA_ARBITER_FIX_MASK 0x10000000L |
26545 | #define PA_SC_ENHANCE_1__DISABLE_SC_PS_PA_ARBITER_FIX_1_MASK 0x20000000L |
26546 | #define PA_SC_ENHANCE_1__PASS_VPZ_EVENT_TO_SPI_MASK 0x40000000L |
26547 | #define PA_SC_ENHANCE_1__DISABLE_FSR_NEAR_AXIS_LINE_VERT_ORDER_SORT_FIX_MASK 0x80000000L |
26548 | //PA_SC_ENHANCE_2 |
26549 | #define PA_SC_ENHANCE_2__DISABLE_SC_MEM_MACRO_FINE_CLOCK_GATE__SHIFT 0x0 |
26550 | #define PA_SC_ENHANCE_2__DISABLE_SC_DB_QUAD_INTF_FINE_CLOCK_GATE__SHIFT 0x1 |
26551 | #define PA_SC_ENHANCE_2__DISABLE_SC_BCI_QUAD_INTF_FINE_CLOCK_GATE__SHIFT 0x2 |
26552 | #define PA_SC_ENHANCE_2__DISABLE_SC_BCI_PRIM_INTF_FINE_CLOCK_GATE__SHIFT 0x3 |
26553 | #define PA_SC_ENHANCE_2__ENABLE_LPOV_WAVE_BREAK__SHIFT 0x4 |
26554 | #define PA_SC_ENHANCE_2__ENABLE_FPOV_WAVE_BREAK__SHIFT 0x5 |
26555 | #define PA_SC_ENHANCE_2__ENABLE_SC_SEND_DB_VPZ_FOR_EN_PRIM_PAYLOAD__SHIFT 0x7 |
26556 | #define PA_SC_ENHANCE_2__DISABLE_BREAK_BATCH_ON_GFX_PIPE_SWITCH__SHIFT 0x8 |
26557 | #define PA_SC_ENHANCE_2__DISABLE_FULL_TILE_WAVE_BREAK__SHIFT 0x9 |
26558 | #define PA_SC_ENHANCE_2__ENABLE_VPZ_INJECTION_BEFORE_NULL_PRIMS__SHIFT 0xa |
26559 | #define PA_SC_ENHANCE_2__PBB_TIMEOUT_THRESHOLD_MODE__SHIFT 0xb |
26560 | #define PA_SC_ENHANCE_2__DISABLE_PACKER_GRAD_FDCE_ENHANCE__SHIFT 0xc |
26561 | #define PA_SC_ENHANCE_2__DISABLE_SC_SPI_INTF_EARLY_WAKEUP__SHIFT 0xd |
26562 | #define PA_SC_ENHANCE_2__DISABLE_SC_BCI_INTF_EARLY_WAKEUP__SHIFT 0xe |
26563 | #define PA_SC_ENHANCE_2__DISABLE_EXPOSED_GT_DETAIL_RATE_TILE_COV_ADJ__SHIFT 0xf |
26564 | #define PA_SC_ENHANCE_2__PBB_WARP_CLK_MAIN_CLK_WAKEUP__SHIFT 0x10 |
26565 | #define PA_SC_ENHANCE_2__PBB_MAIN_CLK_REG_BUSY_WAKEUP__SHIFT 0x11 |
26566 | #define PA_SC_ENHANCE_2__DISABLE_BREAK_BATCH_ON_GFX_PIPELINE_RESET__SHIFT 0x12 |
26567 | #define PA_SC_ENHANCE_2__DISABLE_SC_DBR_DATAPATH_FGCG__SHIFT 0x15 |
26568 | #define PA_SC_ENHANCE_2__FSR_BB_OPTIMIZATION_DISABLE_OVERRIDE__SHIFT 0x16 |
26569 | #define PA_SC_ENHANCE_2__PROCESS_RESET_FORCE_STILE_MASK_TO_ZERO__SHIFT 0x17 |
26570 | #define PA_SC_ENHANCE_2__BREAK_WHEN_ONE_NULL_PRIM_BATCH__SHIFT 0x1a |
26571 | #define PA_SC_ENHANCE_2__NULL_PRIM_BREAK_BATCH_LIMIT__SHIFT 0x1b |
26572 | #define PA_SC_ENHANCE_2__DISABLE_MAX_DEALLOC_FORCE_EOV_RESET_N_WAVES_COUNT__SHIFT 0x1e |
26573 | #define PA_SC_ENHANCE_2__RSVD__SHIFT 0x1f |
26574 | #define PA_SC_ENHANCE_2__DISABLE_SC_MEM_MACRO_FINE_CLOCK_GATE_MASK 0x00000001L |
26575 | #define PA_SC_ENHANCE_2__DISABLE_SC_DB_QUAD_INTF_FINE_CLOCK_GATE_MASK 0x00000002L |
26576 | #define PA_SC_ENHANCE_2__DISABLE_SC_BCI_QUAD_INTF_FINE_CLOCK_GATE_MASK 0x00000004L |
26577 | #define PA_SC_ENHANCE_2__DISABLE_SC_BCI_PRIM_INTF_FINE_CLOCK_GATE_MASK 0x00000008L |
26578 | #define PA_SC_ENHANCE_2__ENABLE_LPOV_WAVE_BREAK_MASK 0x00000010L |
26579 | #define PA_SC_ENHANCE_2__ENABLE_FPOV_WAVE_BREAK_MASK 0x00000020L |
26580 | #define PA_SC_ENHANCE_2__ENABLE_SC_SEND_DB_VPZ_FOR_EN_PRIM_PAYLOAD_MASK 0x00000080L |
26581 | #define PA_SC_ENHANCE_2__DISABLE_BREAK_BATCH_ON_GFX_PIPE_SWITCH_MASK 0x00000100L |
26582 | #define PA_SC_ENHANCE_2__DISABLE_FULL_TILE_WAVE_BREAK_MASK 0x00000200L |
26583 | #define PA_SC_ENHANCE_2__ENABLE_VPZ_INJECTION_BEFORE_NULL_PRIMS_MASK 0x00000400L |
26584 | #define PA_SC_ENHANCE_2__PBB_TIMEOUT_THRESHOLD_MODE_MASK 0x00000800L |
26585 | #define PA_SC_ENHANCE_2__DISABLE_PACKER_GRAD_FDCE_ENHANCE_MASK 0x00001000L |
26586 | #define PA_SC_ENHANCE_2__DISABLE_SC_SPI_INTF_EARLY_WAKEUP_MASK 0x00002000L |
26587 | #define PA_SC_ENHANCE_2__DISABLE_SC_BCI_INTF_EARLY_WAKEUP_MASK 0x00004000L |
26588 | #define PA_SC_ENHANCE_2__DISABLE_EXPOSED_GT_DETAIL_RATE_TILE_COV_ADJ_MASK 0x00008000L |
26589 | #define PA_SC_ENHANCE_2__PBB_WARP_CLK_MAIN_CLK_WAKEUP_MASK 0x00010000L |
26590 | #define PA_SC_ENHANCE_2__PBB_MAIN_CLK_REG_BUSY_WAKEUP_MASK 0x00020000L |
26591 | #define PA_SC_ENHANCE_2__DISABLE_BREAK_BATCH_ON_GFX_PIPELINE_RESET_MASK 0x00040000L |
26592 | #define PA_SC_ENHANCE_2__DISABLE_SC_DBR_DATAPATH_FGCG_MASK 0x00200000L |
26593 | #define PA_SC_ENHANCE_2__FSR_BB_OPTIMIZATION_DISABLE_OVERRIDE_MASK 0x00400000L |
26594 | #define PA_SC_ENHANCE_2__PROCESS_RESET_FORCE_STILE_MASK_TO_ZERO_MASK 0x00800000L |
26595 | #define PA_SC_ENHANCE_2__BREAK_WHEN_ONE_NULL_PRIM_BATCH_MASK 0x04000000L |
26596 | #define PA_SC_ENHANCE_2__NULL_PRIM_BREAK_BATCH_LIMIT_MASK 0x38000000L |
26597 | #define PA_SC_ENHANCE_2__DISABLE_MAX_DEALLOC_FORCE_EOV_RESET_N_WAVES_COUNT_MASK 0x40000000L |
26598 | #define PA_SC_ENHANCE_2__RSVD_MASK 0x80000000L |
26599 | //PA_SC_ENHANCE_3 |
26600 | #define PA_SC_ENHANCE_3__FORCE_USE_OF_SC_CENTROID_DATA__SHIFT 0x0 |
26601 | #define PA_SC_ENHANCE_3__DISABLE_RB_MASK_COPY_FOR_NONP2_SA_PAIR_HARVEST__SHIFT 0x2 |
26602 | #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO__SHIFT 0x3 |
26603 | #define PA_SC_ENHANCE_3__DISABLE_PKR_BCI_QUAD_NEW_PRIM_DATA_LOAD_OPTIMIZATION__SHIFT 0x4 |
26604 | #define PA_SC_ENHANCE_3__DISABLE_CP_CONTEXT_DONE_PERFCOUNT_SAMPLE_EN__SHIFT 0x5 |
26605 | #define PA_SC_ENHANCE_3__ENABLE_SINGLE_PA_EOPKT_FIRST_PHASE_FILTER__SHIFT 0x6 |
26606 | #define PA_SC_ENHANCE_3__ENABLE_SINGLE_PA_EOPKT_LAST_PHASE_FILTER__SHIFT 0x7 |
26607 | #define PA_SC_ENHANCE_3__ENABLE_SINGLE_PA_EOPKT_LAST_PHASE_FILTER_FOR_PBB_BINNED_PRIMS__SHIFT 0x8 |
26608 | #define PA_SC_ENHANCE_3__DISABLE_SET_VPZ_DIRTY_EOPKT_LAST_PHASE_ONLY__SHIFT 0x9 |
26609 | #define PA_SC_ENHANCE_3__DISABLE_PBB_EOP_OPTIMIZATION_WITH_SAME_CONTEXT_BATCHES__SHIFT 0xa |
26610 | #define PA_SC_ENHANCE_3__DISABLE_FAST_NULL_PRIM_OPTIMIZATION__SHIFT 0xb |
26611 | #define PA_SC_ENHANCE_3__USE_PBB_PRIM_STORAGE_WHEN_STALLED__SHIFT 0xc |
26612 | #define PA_SC_ENHANCE_3__DISABLE_LIGHT_VOLUME_RENDERING_OPTIMIZATION__SHIFT 0xd |
26613 | #define PA_SC_ENHANCE_3__DISABLE_ZPRE_PASS_OPTIMIZATION__SHIFT 0xe |
26614 | #define PA_SC_ENHANCE_3__DISABLE_EVENT_INCLUSION_IN_CONTEXT_STATES_PER_BIN__SHIFT 0xf |
26615 | #define PA_SC_ENHANCE_3__DISABLE_PIXEL_WAIT_SYNC_COUNTERS__SHIFT 0x10 |
26616 | #define PA_SC_ENHANCE_3__DISABLE_SC_CPG_PSINVOC_SEDC_ISOLATION_ACCUM__SHIFT 0x11 |
26617 | #define PA_SC_ENHANCE_3__DISABLE_SC_QP_VRS_RATE_FB_FINE_CLOCK_GATE__SHIFT 0x12 |
26618 | #define PA_SC_ENHANCE_3__DISABLE_SC_QP_VRS_RATE_CACHE_RD_FINE_CLOCK_GATE__SHIFT 0x13 |
26619 | #define PA_SC_ENHANCE_3__DISABLE_PKR_FORCE_EOV_MAX_REZ_CNT_FOR_SPI_BACKPRESSURE_ONLY__SHIFT 0x14 |
26620 | #define PA_SC_ENHANCE_3__DISABLE_PKR_FORCE_EOV_MAX_CLK_CNT_FOR_SPI_BACKPRESSURE_ONLY__SHIFT 0x15 |
26621 | #define PA_SC_ENHANCE_3__DO_NOT_INCLUDE_OREO_WAVEID_IN_FORCE_EOV_MAX_CNT_DISABLE__SHIFT 0x16 |
26622 | #define PA_SC_ENHANCE_3__DISABLE_PWS_PRE_DEPTH_WAIT_SYNC_VPZ_INSERTION__SHIFT 0x17 |
26623 | #define PA_SC_ENHANCE_3__PKR_CNT_FORCE_EOV_AT_QS_EMPTY_ONLY__SHIFT 0x18 |
26624 | #define PA_SC_ENHANCE_3__PKR_S0_FORCE_EOV_STALL__SHIFT 0x19 |
26625 | #define PA_SC_ENHANCE_3__PKR_S1_FORCE_EOV_STALL__SHIFT 0x1a |
26626 | #define PA_SC_ENHANCE_3__PKR_S2_FORCE_EOV_STALL__SHIFT 0x1b |
26627 | #define PA_SC_ENHANCE_3__ECO_SPARE0__SHIFT 0x1c |
26628 | #define PA_SC_ENHANCE_3__ECO_SPARE1__SHIFT 0x1d |
26629 | #define PA_SC_ENHANCE_3__ECO_SPARE2__SHIFT 0x1e |
26630 | #define PA_SC_ENHANCE_3__ECO_SPARE3__SHIFT 0x1f |
26631 | #define PA_SC_ENHANCE_3__FORCE_USE_OF_SC_CENTROID_DATA_MASK 0x00000001L |
26632 | #define PA_SC_ENHANCE_3__DISABLE_RB_MASK_COPY_FOR_NONP2_SA_PAIR_HARVEST_MASK 0x00000004L |
26633 | #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO_MASK 0x00000008L |
26634 | #define PA_SC_ENHANCE_3__DISABLE_PKR_BCI_QUAD_NEW_PRIM_DATA_LOAD_OPTIMIZATION_MASK 0x00000010L |
26635 | #define PA_SC_ENHANCE_3__DISABLE_CP_CONTEXT_DONE_PERFCOUNT_SAMPLE_EN_MASK 0x00000020L |
26636 | #define PA_SC_ENHANCE_3__ENABLE_SINGLE_PA_EOPKT_FIRST_PHASE_FILTER_MASK 0x00000040L |
26637 | #define PA_SC_ENHANCE_3__ENABLE_SINGLE_PA_EOPKT_LAST_PHASE_FILTER_MASK 0x00000080L |
26638 | #define PA_SC_ENHANCE_3__ENABLE_SINGLE_PA_EOPKT_LAST_PHASE_FILTER_FOR_PBB_BINNED_PRIMS_MASK 0x00000100L |
26639 | #define PA_SC_ENHANCE_3__DISABLE_SET_VPZ_DIRTY_EOPKT_LAST_PHASE_ONLY_MASK 0x00000200L |
26640 | #define PA_SC_ENHANCE_3__DISABLE_PBB_EOP_OPTIMIZATION_WITH_SAME_CONTEXT_BATCHES_MASK 0x00000400L |
26641 | #define PA_SC_ENHANCE_3__DISABLE_FAST_NULL_PRIM_OPTIMIZATION_MASK 0x00000800L |
26642 | #define PA_SC_ENHANCE_3__USE_PBB_PRIM_STORAGE_WHEN_STALLED_MASK 0x00001000L |
26643 | #define PA_SC_ENHANCE_3__DISABLE_LIGHT_VOLUME_RENDERING_OPTIMIZATION_MASK 0x00002000L |
26644 | #define PA_SC_ENHANCE_3__DISABLE_ZPRE_PASS_OPTIMIZATION_MASK 0x00004000L |
26645 | #define PA_SC_ENHANCE_3__DISABLE_EVENT_INCLUSION_IN_CONTEXT_STATES_PER_BIN_MASK 0x00008000L |
26646 | #define PA_SC_ENHANCE_3__DISABLE_PIXEL_WAIT_SYNC_COUNTERS_MASK 0x00010000L |
26647 | #define PA_SC_ENHANCE_3__DISABLE_SC_CPG_PSINVOC_SEDC_ISOLATION_ACCUM_MASK 0x00020000L |
26648 | #define PA_SC_ENHANCE_3__DISABLE_SC_QP_VRS_RATE_FB_FINE_CLOCK_GATE_MASK 0x00040000L |
26649 | #define PA_SC_ENHANCE_3__DISABLE_SC_QP_VRS_RATE_CACHE_RD_FINE_CLOCK_GATE_MASK 0x00080000L |
26650 | #define PA_SC_ENHANCE_3__DISABLE_PKR_FORCE_EOV_MAX_REZ_CNT_FOR_SPI_BACKPRESSURE_ONLY_MASK 0x00100000L |
26651 | #define PA_SC_ENHANCE_3__DISABLE_PKR_FORCE_EOV_MAX_CLK_CNT_FOR_SPI_BACKPRESSURE_ONLY_MASK 0x00200000L |
26652 | #define PA_SC_ENHANCE_3__DO_NOT_INCLUDE_OREO_WAVEID_IN_FORCE_EOV_MAX_CNT_DISABLE_MASK 0x00400000L |
26653 | #define PA_SC_ENHANCE_3__DISABLE_PWS_PRE_DEPTH_WAIT_SYNC_VPZ_INSERTION_MASK 0x00800000L |
26654 | #define PA_SC_ENHANCE_3__PKR_CNT_FORCE_EOV_AT_QS_EMPTY_ONLY_MASK 0x01000000L |
26655 | #define PA_SC_ENHANCE_3__PKR_S0_FORCE_EOV_STALL_MASK 0x02000000L |
26656 | #define PA_SC_ENHANCE_3__PKR_S1_FORCE_EOV_STALL_MASK 0x04000000L |
26657 | #define PA_SC_ENHANCE_3__PKR_S2_FORCE_EOV_STALL_MASK 0x08000000L |
26658 | #define PA_SC_ENHANCE_3__ECO_SPARE0_MASK 0x10000000L |
26659 | #define PA_SC_ENHANCE_3__ECO_SPARE1_MASK 0x20000000L |
26660 | #define PA_SC_ENHANCE_3__ECO_SPARE2_MASK 0x40000000L |
26661 | #define PA_SC_ENHANCE_3__ECO_SPARE3_MASK 0x80000000L |
26662 | //PA_SC_BINNER_CNTL_OVERRIDE |
26663 | #define PA_SC_BINNER_CNTL_OVERRIDE__BINNING_MODE__SHIFT 0x0 |
26664 | #define PA_SC_BINNER_CNTL_OVERRIDE__CONTEXT_STATES_PER_BIN__SHIFT 0xa |
26665 | #define PA_SC_BINNER_CNTL_OVERRIDE__PERSISTENT_STATES_PER_BIN__SHIFT 0xd |
26666 | #define PA_SC_BINNER_CNTL_OVERRIDE__FPOVS_PER_BATCH__SHIFT 0x13 |
26667 | #define PA_SC_BINNER_CNTL_OVERRIDE__DIRECT_OVERRIDE_MODE__SHIFT 0x1b |
26668 | #define PA_SC_BINNER_CNTL_OVERRIDE__OVERRIDE__SHIFT 0x1c |
26669 | #define PA_SC_BINNER_CNTL_OVERRIDE__BINNING_MODE_MASK 0x00000003L |
26670 | #define PA_SC_BINNER_CNTL_OVERRIDE__CONTEXT_STATES_PER_BIN_MASK 0x00001C00L |
26671 | #define PA_SC_BINNER_CNTL_OVERRIDE__PERSISTENT_STATES_PER_BIN_MASK 0x0003E000L |
26672 | #define PA_SC_BINNER_CNTL_OVERRIDE__FPOVS_PER_BATCH_MASK 0x07F80000L |
26673 | #define PA_SC_BINNER_CNTL_OVERRIDE__DIRECT_OVERRIDE_MODE_MASK 0x08000000L |
26674 | #define PA_SC_BINNER_CNTL_OVERRIDE__OVERRIDE_MASK 0xF0000000L |
26675 | //PA_SC_PBB_OVERRIDE_FLAG |
26676 | #define PA_SC_PBB_OVERRIDE_FLAG__OVERRIDE__SHIFT 0x0 |
26677 | #define PA_SC_PBB_OVERRIDE_FLAG__PIPE_ID__SHIFT 0x1 |
26678 | #define PA_SC_PBB_OVERRIDE_FLAG__OVERRIDE_MASK 0x00000001L |
26679 | #define PA_SC_PBB_OVERRIDE_FLAG__PIPE_ID_MASK 0x00000002L |
26680 | //PA_SC_DSM_CNTL |
26681 | #define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0__SHIFT 0x0 |
26682 | #define PA_SC_DSM_CNTL__FORCE_EOV_REZ_1__SHIFT 0x1 |
26683 | #define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0_MASK 0x00000001L |
26684 | #define PA_SC_DSM_CNTL__FORCE_EOV_REZ_1_MASK 0x00000002L |
26685 | //PA_SC_TILE_STEERING_CREST_OVERRIDE |
26686 | #define PA_SC_TILE_STEERING_CREST_OVERRIDE__ONE_RB_MODE_ENABLE__SHIFT 0x0 |
26687 | #define PA_SC_TILE_STEERING_CREST_OVERRIDE__SE_SELECT__SHIFT 0x1 |
26688 | #define PA_SC_TILE_STEERING_CREST_OVERRIDE__RB_SELECT__SHIFT 0x5 |
26689 | #define PA_SC_TILE_STEERING_CREST_OVERRIDE__SA_SELECT__SHIFT 0x8 |
26690 | #define PA_SC_TILE_STEERING_CREST_OVERRIDE__FORCE_TILE_STEERING_OVERRIDE_USE__SHIFT 0x1f |
26691 | #define PA_SC_TILE_STEERING_CREST_OVERRIDE__ONE_RB_MODE_ENABLE_MASK 0x00000001L |
26692 | #define PA_SC_TILE_STEERING_CREST_OVERRIDE__SE_SELECT_MASK 0x00000006L |
26693 | #define PA_SC_TILE_STEERING_CREST_OVERRIDE__RB_SELECT_MASK 0x00000060L |
26694 | #define PA_SC_TILE_STEERING_CREST_OVERRIDE__SA_SELECT_MASK 0x00000700L |
26695 | #define PA_SC_TILE_STEERING_CREST_OVERRIDE__FORCE_TILE_STEERING_OVERRIDE_USE_MASK 0x80000000L |
26696 | //PA_SC_FIFO_SIZE |
26697 | #define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT 0x0 |
26698 | #define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT 0x6 |
26699 | #define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT 0xf |
26700 | #define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT 0x15 |
26701 | #define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE_MASK 0x0000003FL |
26702 | #define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE_MASK 0x00007FC0L |
26703 | #define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE_MASK 0x001F8000L |
26704 | #define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE_MASK 0xFFE00000L |
26705 | //PA_SC_IF_FIFO_SIZE |
26706 | #define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE__SHIFT 0x0 |
26707 | #define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE__SHIFT 0x6 |
26708 | #define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE__SHIFT 0xc |
26709 | #define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE__SHIFT 0x12 |
26710 | #define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE_MASK 0x0000003FL |
26711 | #define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE_MASK 0x00000FC0L |
26712 | #define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE_MASK 0x0003F000L |
26713 | #define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE_MASK 0x00FC0000L |
26714 | //PA_SC_PACKER_WAVE_ID_CNTL |
26715 | #define PA_SC_PACKER_WAVE_ID_CNTL__WAVE_TABLE_SIZE__SHIFT 0x0 |
26716 | #define PA_SC_PACKER_WAVE_ID_CNTL__SC_DB_WAVE_IF_FIFO_SIZE__SHIFT 0xa |
26717 | #define PA_SC_PACKER_WAVE_ID_CNTL__DISABLE_SC_DB_WAVE_IF_FGCG_EN__SHIFT 0x10 |
26718 | #define PA_SC_PACKER_WAVE_ID_CNTL__SC_SPI_WAVE_IF_FIFO_SIZE__SHIFT 0x11 |
26719 | #define PA_SC_PACKER_WAVE_ID_CNTL__DISABLE_SC_SPI_WAVE_IF_FGCG_EN__SHIFT 0x17 |
26720 | #define PA_SC_PACKER_WAVE_ID_CNTL__DEBUG_CONFLICT_QUAD__SHIFT 0x18 |
26721 | #define PA_SC_PACKER_WAVE_ID_CNTL__DISABLE_OREO_CONFLICT_QUAD__SHIFT 0x1f |
26722 | #define PA_SC_PACKER_WAVE_ID_CNTL__WAVE_TABLE_SIZE_MASK 0x000003FFL |
26723 | #define PA_SC_PACKER_WAVE_ID_CNTL__SC_DB_WAVE_IF_FIFO_SIZE_MASK 0x0000FC00L |
26724 | #define PA_SC_PACKER_WAVE_ID_CNTL__DISABLE_SC_DB_WAVE_IF_FGCG_EN_MASK 0x00010000L |
26725 | #define PA_SC_PACKER_WAVE_ID_CNTL__SC_SPI_WAVE_IF_FIFO_SIZE_MASK 0x007E0000L |
26726 | #define PA_SC_PACKER_WAVE_ID_CNTL__DISABLE_SC_SPI_WAVE_IF_FGCG_EN_MASK 0x00800000L |
26727 | #define PA_SC_PACKER_WAVE_ID_CNTL__DEBUG_CONFLICT_QUAD_MASK 0x0F000000L |
26728 | #define PA_SC_PACKER_WAVE_ID_CNTL__DISABLE_OREO_CONFLICT_QUAD_MASK 0x80000000L |
26729 | //PA_SC_ATM_CNTL |
26730 | #define PA_SC_ATM_CNTL__SC_PC_IF_SIZE__SHIFT 0x0 |
26731 | #define PA_SC_ATM_CNTL__DISABLE_SC_PC_IF_FGCG_EN__SHIFT 0x7 |
26732 | #define PA_SC_ATM_CNTL__MAX_ATTRIBUTES_IN_WAVE__SHIFT 0x8 |
26733 | #define PA_SC_ATM_CNTL__DISABLE_MAX_ATTRIBUTES__SHIFT 0x10 |
26734 | #define PA_SC_ATM_CNTL__SELECT_MAX_ATTRIBUTES__SHIFT 0x11 |
26735 | #define PA_SC_ATM_CNTL__SC_PC_IF_SIZE_MASK 0x0000003FL |
26736 | #define PA_SC_ATM_CNTL__DISABLE_SC_PC_IF_FGCG_EN_MASK 0x00000080L |
26737 | #define PA_SC_ATM_CNTL__MAX_ATTRIBUTES_IN_WAVE_MASK 0x0000FF00L |
26738 | #define PA_SC_ATM_CNTL__DISABLE_MAX_ATTRIBUTES_MASK 0x00010000L |
26739 | #define PA_SC_ATM_CNTL__SELECT_MAX_ATTRIBUTES_MASK 0x00020000L |
26740 | //PA_SC_PKR_WAVE_TABLE_CNTL |
26741 | #define PA_SC_PKR_WAVE_TABLE_CNTL__SIZE__SHIFT 0x0 |
26742 | #define PA_SC_PKR_WAVE_TABLE_CNTL__SIZE_MASK 0x0000003FL |
26743 | //PA_SC_FORCE_EOV_MAX_CNTS |
26744 | #define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT 0x0 |
26745 | #define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT 0x10 |
26746 | #define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT_MASK 0x0000FFFFL |
26747 | #define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT_MASK 0xFFFF0000L |
26748 | //PA_SC_BINNER_EVENT_CNTL_0 |
26749 | #define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_0__SHIFT 0x0 |
26750 | #define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS1__SHIFT 0x2 |
26751 | #define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS2__SHIFT 0x4 |
26752 | #define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS3__SHIFT 0x6 |
26753 | #define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_TS__SHIFT 0x8 |
26754 | #define PA_SC_BINNER_EVENT_CNTL_0__CONTEXT_DONE__SHIFT 0xa |
26755 | #define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH__SHIFT 0xc |
26756 | #define PA_SC_BINNER_EVENT_CNTL_0__CS_PARTIAL_FLUSH__SHIFT 0xe |
26757 | #define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_SYNC__SHIFT 0x10 |
26758 | #define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_9__SHIFT 0x12 |
26759 | #define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_RESET__SHIFT 0x14 |
26760 | #define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_INCR_DE__SHIFT 0x16 |
26761 | #define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_IB_END__SHIFT 0x18 |
26762 | #define PA_SC_BINNER_EVENT_CNTL_0__RST_PIX_CNT__SHIFT 0x1a |
26763 | #define PA_SC_BINNER_EVENT_CNTL_0__BREAK_BATCH__SHIFT 0x1c |
26764 | #define PA_SC_BINNER_EVENT_CNTL_0__VS_PARTIAL_FLUSH__SHIFT 0x1e |
26765 | #define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_0_MASK 0x00000003L |
26766 | #define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS1_MASK 0x0000000CL |
26767 | #define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS2_MASK 0x00000030L |
26768 | #define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS3_MASK 0x000000C0L |
26769 | #define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_TS_MASK 0x00000300L |
26770 | #define PA_SC_BINNER_EVENT_CNTL_0__CONTEXT_DONE_MASK 0x00000C00L |
26771 | #define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_MASK 0x00003000L |
26772 | #define PA_SC_BINNER_EVENT_CNTL_0__CS_PARTIAL_FLUSH_MASK 0x0000C000L |
26773 | #define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_SYNC_MASK 0x00030000L |
26774 | #define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_9_MASK 0x000C0000L |
26775 | #define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_RESET_MASK 0x00300000L |
26776 | #define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_INCR_DE_MASK 0x00C00000L |
26777 | #define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_IB_END_MASK 0x03000000L |
26778 | #define PA_SC_BINNER_EVENT_CNTL_0__RST_PIX_CNT_MASK 0x0C000000L |
26779 | #define PA_SC_BINNER_EVENT_CNTL_0__BREAK_BATCH_MASK 0x30000000L |
26780 | #define PA_SC_BINNER_EVENT_CNTL_0__VS_PARTIAL_FLUSH_MASK 0xC0000000L |
26781 | //PA_SC_BINNER_EVENT_CNTL_1 |
26782 | #define PA_SC_BINNER_EVENT_CNTL_1__PS_PARTIAL_FLUSH__SHIFT 0x0 |
26783 | #define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_HS_OUTPUT__SHIFT 0x2 |
26784 | #define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_DFSM__SHIFT 0x4 |
26785 | #define PA_SC_BINNER_EVENT_CNTL_1__RESET_TO_LOWEST_VGT__SHIFT 0x6 |
26786 | #define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_TS_EVENT__SHIFT 0x8 |
26787 | #define PA_SC_BINNER_EVENT_CNTL_1__WAIT_SYNC__SHIFT 0xa |
26788 | #define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_EVENT__SHIFT 0xc |
26789 | #define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_START__SHIFT 0xe |
26790 | #define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_STOP__SHIFT 0x10 |
26791 | #define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_START__SHIFT 0x12 |
26792 | #define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_STOP__SHIFT 0x14 |
26793 | #define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_SAMPLE__SHIFT 0x16 |
26794 | #define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_ES_OUTPUT__SHIFT 0x18 |
26795 | #define PA_SC_BINNER_EVENT_CNTL_1__BIN_CONF_OVERRIDE_CHECK__SHIFT 0x1a |
26796 | #define PA_SC_BINNER_EVENT_CNTL_1__SAMPLE_PIPELINESTAT__SHIFT 0x1c |
26797 | #define PA_SC_BINNER_EVENT_CNTL_1__SO_VGTSTREAMOUT_FLUSH__SHIFT 0x1e |
26798 | #define PA_SC_BINNER_EVENT_CNTL_1__PS_PARTIAL_FLUSH_MASK 0x00000003L |
26799 | #define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_HS_OUTPUT_MASK 0x0000000CL |
26800 | #define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_DFSM_MASK 0x00000030L |
26801 | #define PA_SC_BINNER_EVENT_CNTL_1__RESET_TO_LOWEST_VGT_MASK 0x000000C0L |
26802 | #define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_TS_EVENT_MASK 0x00000300L |
26803 | #define PA_SC_BINNER_EVENT_CNTL_1__WAIT_SYNC_MASK 0x00000C00L |
26804 | #define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_EVENT_MASK 0x00003000L |
26805 | #define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_START_MASK 0x0000C000L |
26806 | #define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_STOP_MASK 0x00030000L |
26807 | #define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_START_MASK 0x000C0000L |
26808 | #define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_STOP_MASK 0x00300000L |
26809 | #define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_SAMPLE_MASK 0x00C00000L |
26810 | #define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_ES_OUTPUT_MASK 0x03000000L |
26811 | #define PA_SC_BINNER_EVENT_CNTL_1__BIN_CONF_OVERRIDE_CHECK_MASK 0x0C000000L |
26812 | #define PA_SC_BINNER_EVENT_CNTL_1__SAMPLE_PIPELINESTAT_MASK 0x30000000L |
26813 | #define PA_SC_BINNER_EVENT_CNTL_1__SO_VGTSTREAMOUT_FLUSH_MASK 0xC0000000L |
26814 | //PA_SC_BINNER_EVENT_CNTL_2 |
26815 | #define PA_SC_BINNER_EVENT_CNTL_2__SAMPLE_STREAMOUTSTATS__SHIFT 0x0 |
26816 | #define PA_SC_BINNER_EVENT_CNTL_2__RESET_VTX_CNT__SHIFT 0x2 |
26817 | #define PA_SC_BINNER_EVENT_CNTL_2__BLOCK_CONTEXT_DONE__SHIFT 0x4 |
26818 | #define PA_SC_BINNER_EVENT_CNTL_2__RESERVED_35__SHIFT 0x6 |
26819 | #define PA_SC_BINNER_EVENT_CNTL_2__VGT_FLUSH__SHIFT 0x8 |
26820 | #define PA_SC_BINNER_EVENT_CNTL_2__TGID_ROLLOVER__SHIFT 0xa |
26821 | #define PA_SC_BINNER_EVENT_CNTL_2__SQ_NON_EVENT__SHIFT 0xc |
26822 | #define PA_SC_BINNER_EVENT_CNTL_2__SC_SEND_DB_VPZ__SHIFT 0xe |
26823 | #define PA_SC_BINNER_EVENT_CNTL_2__BOTTOM_OF_PIPE_TS__SHIFT 0x10 |
26824 | #define PA_SC_BINNER_EVENT_CNTL_2__RESERVED_41__SHIFT 0x12 |
26825 | #define PA_SC_BINNER_EVENT_CNTL_2__DB_CACHE_FLUSH_AND_INV__SHIFT 0x14 |
26826 | #define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_DATA_TS__SHIFT 0x16 |
26827 | #define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_META__SHIFT 0x18 |
26828 | #define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_DATA_TS__SHIFT 0x1a |
26829 | #define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_META__SHIFT 0x1c |
26830 | #define PA_SC_BINNER_EVENT_CNTL_2__CS_DONE__SHIFT 0x1e |
26831 | #define PA_SC_BINNER_EVENT_CNTL_2__SAMPLE_STREAMOUTSTATS_MASK 0x00000003L |
26832 | #define PA_SC_BINNER_EVENT_CNTL_2__RESET_VTX_CNT_MASK 0x0000000CL |
26833 | #define PA_SC_BINNER_EVENT_CNTL_2__BLOCK_CONTEXT_DONE_MASK 0x00000030L |
26834 | #define PA_SC_BINNER_EVENT_CNTL_2__RESERVED_35_MASK 0x000000C0L |
26835 | #define PA_SC_BINNER_EVENT_CNTL_2__VGT_FLUSH_MASK 0x00000300L |
26836 | #define PA_SC_BINNER_EVENT_CNTL_2__TGID_ROLLOVER_MASK 0x00000C00L |
26837 | #define PA_SC_BINNER_EVENT_CNTL_2__SQ_NON_EVENT_MASK 0x00003000L |
26838 | #define PA_SC_BINNER_EVENT_CNTL_2__SC_SEND_DB_VPZ_MASK 0x0000C000L |
26839 | #define PA_SC_BINNER_EVENT_CNTL_2__BOTTOM_OF_PIPE_TS_MASK 0x00030000L |
26840 | #define PA_SC_BINNER_EVENT_CNTL_2__RESERVED_41_MASK 0x000C0000L |
26841 | #define PA_SC_BINNER_EVENT_CNTL_2__DB_CACHE_FLUSH_AND_INV_MASK 0x00300000L |
26842 | #define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_DATA_TS_MASK 0x00C00000L |
26843 | #define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_META_MASK 0x03000000L |
26844 | #define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_DATA_TS_MASK 0x0C000000L |
26845 | #define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_META_MASK 0x30000000L |
26846 | #define PA_SC_BINNER_EVENT_CNTL_2__CS_DONE_MASK 0xC0000000L |
26847 | //PA_SC_BINNER_EVENT_CNTL_3 |
26848 | #define PA_SC_BINNER_EVENT_CNTL_3__PS_DONE__SHIFT 0x0 |
26849 | #define PA_SC_BINNER_EVENT_CNTL_3__FLUSH_AND_INV_CB_PIXEL_DATA__SHIFT 0x2 |
26850 | #define PA_SC_BINNER_EVENT_CNTL_3__RESERVED_50__SHIFT 0x4 |
26851 | #define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_START__SHIFT 0x6 |
26852 | #define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_STOP__SHIFT 0x8 |
26853 | #define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_MARKER__SHIFT 0xa |
26854 | #define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_DRAW__SHIFT 0xc |
26855 | #define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FINISH__SHIFT 0xe |
26856 | #define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_CONTROL__SHIFT 0x10 |
26857 | #define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_DUMP__SHIFT 0x12 |
26858 | #define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_RESET__SHIFT 0x14 |
26859 | #define PA_SC_BINNER_EVENT_CNTL_3__CONTEXT_SUSPEND__SHIFT 0x16 |
26860 | #define PA_SC_BINNER_EVENT_CNTL_3__OFFCHIP_HS_DEALLOC__SHIFT 0x18 |
26861 | #define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_NGG_PIPELINE__SHIFT 0x1a |
26862 | #define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_PIPELINE_NOT_USED__SHIFT 0x1c |
26863 | #define PA_SC_BINNER_EVENT_CNTL_3__DRAW_DONE__SHIFT 0x1e |
26864 | #define PA_SC_BINNER_EVENT_CNTL_3__PS_DONE_MASK 0x00000003L |
26865 | #define PA_SC_BINNER_EVENT_CNTL_3__FLUSH_AND_INV_CB_PIXEL_DATA_MASK 0x0000000CL |
26866 | #define PA_SC_BINNER_EVENT_CNTL_3__RESERVED_50_MASK 0x00000030L |
26867 | #define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_START_MASK 0x000000C0L |
26868 | #define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_STOP_MASK 0x00000300L |
26869 | #define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_MARKER_MASK 0x00000C00L |
26870 | #define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_DRAW_MASK 0x00003000L |
26871 | #define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FINISH_MASK 0x0000C000L |
26872 | #define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_CONTROL_MASK 0x00030000L |
26873 | #define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_DUMP_MASK 0x000C0000L |
26874 | #define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_RESET_MASK 0x00300000L |
26875 | #define PA_SC_BINNER_EVENT_CNTL_3__CONTEXT_SUSPEND_MASK 0x00C00000L |
26876 | #define PA_SC_BINNER_EVENT_CNTL_3__OFFCHIP_HS_DEALLOC_MASK 0x03000000L |
26877 | #define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_NGG_PIPELINE_MASK 0x0C000000L |
26878 | #define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_PIPELINE_NOT_USED_MASK 0x30000000L |
26879 | #define PA_SC_BINNER_EVENT_CNTL_3__DRAW_DONE_MASK 0xC0000000L |
26880 | //PA_SC_BINNER_TIMEOUT_COUNTER |
26881 | #define PA_SC_BINNER_TIMEOUT_COUNTER__THRESHOLD__SHIFT 0x0 |
26882 | #define PA_SC_BINNER_TIMEOUT_COUNTER__THRESHOLD_MASK 0xFFFFFFFFL |
26883 | //PA_SC_BINNER_PERF_CNTL_0 |
26884 | #define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_PRIMS_THRESHOLD__SHIFT 0x0 |
26885 | #define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_PRIMS_THRESHOLD__SHIFT 0xa |
26886 | #define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_CONTEXT_THRESHOLD__SHIFT 0x14 |
26887 | #define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_CONTEXT_THRESHOLD__SHIFT 0x17 |
26888 | #define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_PRIMS_THRESHOLD_MASK 0x000003FFL |
26889 | #define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_PRIMS_THRESHOLD_MASK 0x000FFC00L |
26890 | #define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_CONTEXT_THRESHOLD_MASK 0x00700000L |
26891 | #define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_CONTEXT_THRESHOLD_MASK 0x03800000L |
26892 | //PA_SC_BINNER_PERF_CNTL_1 |
26893 | #define PA_SC_BINNER_PERF_CNTL_1__BIN_HIST_NUM_PERSISTENT_STATE_THRESHOLD__SHIFT 0x0 |
26894 | #define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_PERSISTENT_STATE_THRESHOLD__SHIFT 0x5 |
26895 | #define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_TRIV_REJECTED_PRIMS_THRESHOLD__SHIFT 0xa |
26896 | #define PA_SC_BINNER_PERF_CNTL_1__BIN_HIST_NUM_PERSISTENT_STATE_THRESHOLD_MASK 0x0000001FL |
26897 | #define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_PERSISTENT_STATE_THRESHOLD_MASK 0x000003E0L |
26898 | #define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_TRIV_REJECTED_PRIMS_THRESHOLD_MASK 0x03FFFC00L |
26899 | //PA_SC_BINNER_PERF_CNTL_2 |
26900 | #define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_ROWS_PER_PRIM_THRESHOLD__SHIFT 0x0 |
26901 | #define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_COLUMNS_PER_ROW_THRESHOLD__SHIFT 0xb |
26902 | #define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_ROWS_PER_PRIM_THRESHOLD_MASK 0x000007FFL |
26903 | #define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_COLUMNS_PER_ROW_THRESHOLD_MASK 0x003FF800L |
26904 | //PA_SC_BINNER_PERF_CNTL_3 |
26905 | #define PA_SC_BINNER_PERF_CNTL_3__BATCH_HIST_NUM_PS_WAVE_BREAKS_THRESHOLD__SHIFT 0x0 |
26906 | #define PA_SC_BINNER_PERF_CNTL_3__BATCH_HIST_NUM_PS_WAVE_BREAKS_THRESHOLD_MASK 0xFFFFFFFFL |
26907 | //PA_SC_P3D_TRAP_SCREEN_HV_LOCK |
26908 | #define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0 |
26909 | #define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x00000001L |
26910 | //PA_SC_HP3D_TRAP_SCREEN_HV_LOCK |
26911 | #define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0 |
26912 | #define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x00000001L |
26913 | //PA_SC_TRAP_SCREEN_HV_LOCK |
26914 | #define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0 |
26915 | #define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x00000001L |
26916 | //PA_PH_INTERFACE_FIFO_SIZE |
26917 | #define PA_PH_INTERFACE_FIFO_SIZE__PA_PH_IF_FIFO_SIZE__SHIFT 0x0 |
26918 | #define PA_PH_INTERFACE_FIFO_SIZE__PH_SC_IF_FIFO_SIZE__SHIFT 0x10 |
26919 | #define PA_PH_INTERFACE_FIFO_SIZE__PA_PH_IF_FIFO_SIZE_MASK 0x000003FFL |
26920 | #define PA_PH_INTERFACE_FIFO_SIZE__PH_SC_IF_FIFO_SIZE_MASK 0x003F0000L |
26921 | //PA_PH_ENHANCE |
26922 | #define PA_PH_ENHANCE__ECO_SPARE0__SHIFT 0x0 |
26923 | #define PA_PH_ENHANCE__ECO_SPARE1__SHIFT 0x1 |
26924 | #define PA_PH_ENHANCE__ECO_SPARE2__SHIFT 0x2 |
26925 | #define PA_PH_ENHANCE__ECO_SPARE3__SHIFT 0x3 |
26926 | #define PA_PH_ENHANCE__DISABLE_PH_SC_INTF_FINE_CLOCK_GATE__SHIFT 0x4 |
26927 | #define PA_PH_ENHANCE__DISABLE_FOPKT__SHIFT 0x5 |
26928 | #define PA_PH_ENHANCE__DISABLE_FOPKT_SCAN_POST_RESET__SHIFT 0x6 |
26929 | #define PA_PH_ENHANCE__DISABLE_PH_SC_INTF_CLKEN_CLOCK_GATE__SHIFT 0x7 |
26930 | #define PA_PH_ENHANCE__DISABLE_PH_DEBUG_REG_FGCG__SHIFT 0x8 |
26931 | #define PA_PH_ENHANCE__DISABLE_PH_PERF_REG_FGCG__SHIFT 0x9 |
26932 | #define PA_PH_ENHANCE__ENABLE_PH_INTF_CLKEN_STRETCH__SHIFT 0xa |
26933 | #define PA_PH_ENHANCE__DISABLE_USE_LAST_PH_ARBITER_PERFCOUNTER_SAMPLE_EVENT__SHIFT 0xd |
26934 | #define PA_PH_ENHANCE__USE_PERFCOUNTER_START_STOP_EVENTS__SHIFT 0xe |
26935 | #define PA_PH_ENHANCE__FORCE_PH_PERFCOUNTER_SAMPLE_ENABLE_ON__SHIFT 0xf |
26936 | #define PA_PH_ENHANCE__PH_SPI_GE_THROTTLE_MODE__SHIFT 0x10 |
26937 | #define PA_PH_ENHANCE__PH_SPI_GE_THROTTLE_MODE_DISABLE__SHIFT 0x11 |
26938 | #define PA_PH_ENHANCE__PH_SPI_GE_THROTTLE_PERFCOUNTER_COUNT_MODE__SHIFT 0x12 |
26939 | #define PA_PH_ENHANCE__ECO_SPARE0_MASK 0x00000001L |
26940 | #define PA_PH_ENHANCE__ECO_SPARE1_MASK 0x00000002L |
26941 | #define PA_PH_ENHANCE__ECO_SPARE2_MASK 0x00000004L |
26942 | #define PA_PH_ENHANCE__ECO_SPARE3_MASK 0x00000008L |
26943 | #define PA_PH_ENHANCE__DISABLE_PH_SC_INTF_FINE_CLOCK_GATE_MASK 0x00000010L |
26944 | #define PA_PH_ENHANCE__DISABLE_FOPKT_MASK 0x00000020L |
26945 | #define PA_PH_ENHANCE__DISABLE_FOPKT_SCAN_POST_RESET_MASK 0x00000040L |
26946 | #define PA_PH_ENHANCE__DISABLE_PH_SC_INTF_CLKEN_CLOCK_GATE_MASK 0x00000080L |
26947 | #define PA_PH_ENHANCE__DISABLE_PH_DEBUG_REG_FGCG_MASK 0x00000100L |
26948 | #define PA_PH_ENHANCE__DISABLE_PH_PERF_REG_FGCG_MASK 0x00000200L |
26949 | #define PA_PH_ENHANCE__ENABLE_PH_INTF_CLKEN_STRETCH_MASK 0x00001C00L |
26950 | #define PA_PH_ENHANCE__DISABLE_USE_LAST_PH_ARBITER_PERFCOUNTER_SAMPLE_EVENT_MASK 0x00002000L |
26951 | #define PA_PH_ENHANCE__USE_PERFCOUNTER_START_STOP_EVENTS_MASK 0x00004000L |
26952 | #define PA_PH_ENHANCE__FORCE_PH_PERFCOUNTER_SAMPLE_ENABLE_ON_MASK 0x00008000L |
26953 | #define PA_PH_ENHANCE__PH_SPI_GE_THROTTLE_MODE_MASK 0x00010000L |
26954 | #define PA_PH_ENHANCE__PH_SPI_GE_THROTTLE_MODE_DISABLE_MASK 0x00020000L |
26955 | #define PA_PH_ENHANCE__PH_SPI_GE_THROTTLE_PERFCOUNTER_COUNT_MODE_MASK 0x00040000L |
26956 | //PA_SC_VRS_SURFACE_CNTL_1 |
26957 | #define PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE__SHIFT 0x0 |
26958 | #define PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_SHADER_KILL_ENABLE__SHIFT 0x1 |
26959 | #define PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_MASK_OPS_ENABLE__SHIFT 0x2 |
26960 | #define PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_RATE_16XAA__SHIFT 0x3 |
26961 | #define PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_Z_OR_STENCIL__SHIFT 0x4 |
26962 | #define PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_PRE_SHADER_DEPTH_COVERAGE_ENABLED__SHIFT 0x5 |
26963 | #define PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_POST_DEPTH_IMPORT__SHIFT 0x6 |
26964 | #define PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_POPS__SHIFT 0x7 |
26965 | #define PA_SC_VRS_SURFACE_CNTL_1__USE_ONLY_VRS_RATE_FINE_CFG__SHIFT 0x8 |
26966 | #define PA_SC_VRS_SURFACE_CNTL_1__DISABLE_SSAA_VRS_RATE_NORMALIZATION__SHIFT 0xc |
26967 | #define PA_SC_VRS_SURFACE_CNTL_1__DISABLE_PS_ITER_RATE_COMBINER_PASSTHRU_OVERRIDE__SHIFT 0xf |
26968 | #define PA_SC_VRS_SURFACE_CNTL_1__DISABLE_CMASK_RATE_HINT_FORCE_ZERO_OVERRIDE__SHIFT 0x13 |
26969 | #define PA_SC_VRS_SURFACE_CNTL_1__DISABLE_SSAA_DETAIL_TO_EXPOSED_RATE_CLAMPING__SHIFT 0x14 |
26970 | #define PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_0__SHIFT 0x15 |
26971 | #define PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_1__SHIFT 0x16 |
26972 | #define PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_2__SHIFT 0x17 |
26973 | #define PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_3__SHIFT 0x18 |
26974 | #define PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_4__SHIFT 0x19 |
26975 | #define PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_5__SHIFT 0x1a |
26976 | #define PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_6__SHIFT 0x1b |
26977 | #define PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_7__SHIFT 0x1c |
26978 | #define PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_8__SHIFT 0x1d |
26979 | #define PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_9__SHIFT 0x1e |
26980 | #define PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_10__SHIFT 0x1f |
26981 | #define PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_MASK 0x00000001L |
26982 | #define PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_SHADER_KILL_ENABLE_MASK 0x00000002L |
26983 | #define PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_MASK_OPS_ENABLE_MASK 0x00000004L |
26984 | #define PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_RATE_16XAA_MASK 0x00000008L |
26985 | #define PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_Z_OR_STENCIL_MASK 0x00000010L |
26986 | #define PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_PRE_SHADER_DEPTH_COVERAGE_ENABLED_MASK 0x00000020L |
26987 | #define PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_POST_DEPTH_IMPORT_MASK 0x00000040L |
26988 | #define PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_POPS_MASK 0x00000080L |
26989 | #define PA_SC_VRS_SURFACE_CNTL_1__USE_ONLY_VRS_RATE_FINE_CFG_MASK 0x00000100L |
26990 | #define PA_SC_VRS_SURFACE_CNTL_1__DISABLE_SSAA_VRS_RATE_NORMALIZATION_MASK 0x00001000L |
26991 | #define PA_SC_VRS_SURFACE_CNTL_1__DISABLE_PS_ITER_RATE_COMBINER_PASSTHRU_OVERRIDE_MASK 0x00008000L |
26992 | #define PA_SC_VRS_SURFACE_CNTL_1__DISABLE_CMASK_RATE_HINT_FORCE_ZERO_OVERRIDE_MASK 0x00080000L |
26993 | #define PA_SC_VRS_SURFACE_CNTL_1__DISABLE_SSAA_DETAIL_TO_EXPOSED_RATE_CLAMPING_MASK 0x00100000L |
26994 | #define PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_0_MASK 0x00200000L |
26995 | #define PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_1_MASK 0x00400000L |
26996 | #define PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_2_MASK 0x00800000L |
26997 | #define PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_3_MASK 0x01000000L |
26998 | #define PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_4_MASK 0x02000000L |
26999 | #define PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_5_MASK 0x04000000L |
27000 | #define PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_6_MASK 0x08000000L |
27001 | #define PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_7_MASK 0x10000000L |
27002 | #define PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_8_MASK 0x20000000L |
27003 | #define PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_9_MASK 0x40000000L |
27004 | #define PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_10_MASK 0x80000000L |
27005 | |
27006 | |
27007 | // addressBlock: gc_pfvf_sqdec |
27008 | //SQ_RUNTIME_CONFIG |
27009 | #define SQ_RUNTIME_CONFIG__UNUSED_REGISTER__SHIFT 0x0 |
27010 | #define SQ_RUNTIME_CONFIG__UNUSED_REGISTER_MASK 0x00000001L |
27011 | //SQ_DEBUG_STS_GLOBAL |
27012 | #define SQ_DEBUG_STS_GLOBAL__BUSY__SHIFT 0x0 |
27013 | #define SQ_DEBUG_STS_GLOBAL__INTERRUPT_BUSY__SHIFT 0x1 |
27014 | #define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SA0__SHIFT 0x4 |
27015 | #define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SA1__SHIFT 0x10 |
27016 | #define SQ_DEBUG_STS_GLOBAL__BUSY_MASK 0x00000001L |
27017 | #define SQ_DEBUG_STS_GLOBAL__INTERRUPT_BUSY_MASK 0x00000002L |
27018 | #define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SA0_MASK 0x0000FFF0L |
27019 | #define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SA1_MASK 0x0FFF0000L |
27020 | //SQ_DEBUG_STS_GLOBAL2 |
27021 | #define SQ_DEBUG_STS_GLOBAL2__REG_FIFO_LEVEL_GFX0__SHIFT 0x0 |
27022 | #define SQ_DEBUG_STS_GLOBAL2__REG_FIFO_LEVEL_GFX1__SHIFT 0x8 |
27023 | #define SQ_DEBUG_STS_GLOBAL2__REG_FIFO_LEVEL_COMPUTE__SHIFT 0x10 |
27024 | #define SQ_DEBUG_STS_GLOBAL2__REG_FIFO_LEVEL_GFX0_MASK 0x000000FFL |
27025 | #define SQ_DEBUG_STS_GLOBAL2__REG_FIFO_LEVEL_GFX1_MASK 0x0000FF00L |
27026 | #define SQ_DEBUG_STS_GLOBAL2__REG_FIFO_LEVEL_COMPUTE_MASK 0x00FF0000L |
27027 | //SH_MEM_BASES |
27028 | #define SH_MEM_BASES__PRIVATE_BASE__SHIFT 0x0 |
27029 | #define SH_MEM_BASES__SHARED_BASE__SHIFT 0x10 |
27030 | #define SH_MEM_BASES__PRIVATE_BASE_MASK 0x0000FFFFL |
27031 | #define SH_MEM_BASES__SHARED_BASE_MASK 0xFFFF0000L |
27032 | //SH_MEM_CONFIG |
27033 | #define SH_MEM_CONFIG__ADDRESS_MODE__SHIFT 0x0 |
27034 | #define SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT 0x2 |
27035 | #define SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT 0xe |
27036 | #define SH_MEM_CONFIG__ICACHE_USE_GL1__SHIFT 0x12 |
27037 | #define SH_MEM_CONFIG__ADDRESS_MODE_MASK 0x00000001L |
27038 | #define SH_MEM_CONFIG__ALIGNMENT_MODE_MASK 0x0000000CL |
27039 | #define SH_MEM_CONFIG__INITIAL_INST_PREFETCH_MASK 0x0000C000L |
27040 | #define SH_MEM_CONFIG__ICACHE_USE_GL1_MASK 0x00040000L |
27041 | //SQ_DEBUG |
27042 | #define SQ_DEBUG__SINGLE_MEMOP__SHIFT 0x0 |
27043 | #define SQ_DEBUG__SINGLE_ALU_OP__SHIFT 0x1 |
27044 | #define SQ_DEBUG__WAIT_DEP_CTR_ZERO__SHIFT 0x2 |
27045 | #define SQ_DEBUG__SINGLE_MEMOP_MASK 0x00000001L |
27046 | #define SQ_DEBUG__SINGLE_ALU_OP_MASK 0x00000002L |
27047 | #define SQ_DEBUG__WAIT_DEP_CTR_ZERO_MASK 0x00000004L |
27048 | //SQ_SHADER_TBA_LO |
27049 | #define SQ_SHADER_TBA_LO__ADDR_LO__SHIFT 0x0 |
27050 | #define SQ_SHADER_TBA_LO__ADDR_LO_MASK 0xFFFFFFFFL |
27051 | //SQ_SHADER_TBA_HI |
27052 | #define SQ_SHADER_TBA_HI__ADDR_HI__SHIFT 0x0 |
27053 | #define SQ_SHADER_TBA_HI__TRAP_EN__SHIFT 0x1f |
27054 | #define SQ_SHADER_TBA_HI__ADDR_HI_MASK 0x000000FFL |
27055 | #define SQ_SHADER_TBA_HI__TRAP_EN_MASK 0x80000000L |
27056 | //SQ_SHADER_TMA_LO |
27057 | #define SQ_SHADER_TMA_LO__ADDR_LO__SHIFT 0x0 |
27058 | #define SQ_SHADER_TMA_LO__ADDR_LO_MASK 0xFFFFFFFFL |
27059 | //SQ_SHADER_TMA_HI |
27060 | #define SQ_SHADER_TMA_HI__ADDR_HI__SHIFT 0x0 |
27061 | #define SQ_SHADER_TMA_HI__ADDR_HI_MASK 0x000000FFL |
27062 | |
27063 | |
27064 | // addressBlock: gc_pfonly_cpdec |
27065 | //CP_DEBUG_2 |
27066 | #define CP_DEBUG_2__CHIU_NOALLOC_OVERRIDE__SHIFT 0xc |
27067 | #define CP_DEBUG_2__RCIU_SECURE_CHECK_DISABLE__SHIFT 0xd |
27068 | #define CP_DEBUG_2__RB_PACKET_INJECTOR_DISABLE__SHIFT 0xe |
27069 | #define CP_DEBUG_2__CNTX_DONE_COPY_STATE_DISABLE__SHIFT 0xf |
27070 | #define CP_DEBUG_2__NOP_DISCARD_DISABLE__SHIFT 0x10 |
27071 | #define CP_DEBUG_2__DC_INTERLEAVE_DISABLE__SHIFT 0x11 |
27072 | #define CP_DEBUG_2__BC_LOOKUP_CB_DB_FLUSH_DISABLE__SHIFT 0x1b |
27073 | #define CP_DEBUG_2__DC_FORCE_CLK_EN__SHIFT 0x1c |
27074 | #define CP_DEBUG_2__DC_DISABLE_BROADCAST__SHIFT 0x1d |
27075 | #define CP_DEBUG_2__NOT_EOP_HW_DETECT_DISABLE__SHIFT 0x1e |
27076 | #define CP_DEBUG_2__PFP_DDID_HW_DETECT_DISABLE__SHIFT 0x1f |
27077 | #define CP_DEBUG_2__CHIU_NOALLOC_OVERRIDE_MASK 0x00001000L |
27078 | #define CP_DEBUG_2__RCIU_SECURE_CHECK_DISABLE_MASK 0x00002000L |
27079 | #define CP_DEBUG_2__RB_PACKET_INJECTOR_DISABLE_MASK 0x00004000L |
27080 | #define CP_DEBUG_2__CNTX_DONE_COPY_STATE_DISABLE_MASK 0x00008000L |
27081 | #define CP_DEBUG_2__NOP_DISCARD_DISABLE_MASK 0x00010000L |
27082 | #define CP_DEBUG_2__DC_INTERLEAVE_DISABLE_MASK 0x00020000L |
27083 | #define CP_DEBUG_2__BC_LOOKUP_CB_DB_FLUSH_DISABLE_MASK 0x08000000L |
27084 | #define CP_DEBUG_2__DC_FORCE_CLK_EN_MASK 0x10000000L |
27085 | #define CP_DEBUG_2__DC_DISABLE_BROADCAST_MASK 0x20000000L |
27086 | #define CP_DEBUG_2__NOT_EOP_HW_DETECT_DISABLE_MASK 0x40000000L |
27087 | #define CP_DEBUG_2__PFP_DDID_HW_DETECT_DISABLE_MASK 0x80000000L |
27088 | //CP_FETCHER_SOURCE |
27089 | #define CP_FETCHER_SOURCE__ME_SRC__SHIFT 0x0 |
27090 | #define CP_FETCHER_SOURCE__ME_SRC_MASK 0x00000001L |
27091 | //CP_DFY_CNTL |
27092 | #define CP_DFY_CNTL__POLICY__SHIFT 0x8 |
27093 | #define CP_DFY_CNTL__VOL__SHIFT 0xa |
27094 | #define CP_DFY_CNTL__MTYPE__SHIFT 0xc |
27095 | #define CP_DFY_CNTL__REPEATER_FGCG_DISABLE__SHIFT 0x19 |
27096 | #define CP_DFY_CNTL__TPI_SDP_SEL__SHIFT 0x1a |
27097 | #define CP_DFY_CNTL__WRITE_DIS__SHIFT 0x1b |
27098 | #define CP_DFY_CNTL__LFSR_RESET__SHIFT 0x1c |
27099 | #define CP_DFY_CNTL__MODE__SHIFT 0x1d |
27100 | #define CP_DFY_CNTL__ENABLE__SHIFT 0x1f |
27101 | #define CP_DFY_CNTL__POLICY_MASK 0x00000300L |
27102 | #define CP_DFY_CNTL__VOL_MASK 0x00000400L |
27103 | #define CP_DFY_CNTL__MTYPE_MASK 0x00007000L |
27104 | #define CP_DFY_CNTL__REPEATER_FGCG_DISABLE_MASK 0x02000000L |
27105 | #define CP_DFY_CNTL__TPI_SDP_SEL_MASK 0x04000000L |
27106 | #define CP_DFY_CNTL__WRITE_DIS_MASK 0x08000000L |
27107 | #define CP_DFY_CNTL__LFSR_RESET_MASK 0x10000000L |
27108 | #define CP_DFY_CNTL__MODE_MASK 0x60000000L |
27109 | #define CP_DFY_CNTL__ENABLE_MASK 0x80000000L |
27110 | //CP_DFY_STAT |
27111 | #define CP_DFY_STAT__BURST_COUNT__SHIFT 0x0 |
27112 | #define CP_DFY_STAT__TAGS_PENDING__SHIFT 0x10 |
27113 | #define CP_DFY_STAT__BUSY__SHIFT 0x1f |
27114 | #define CP_DFY_STAT__BURST_COUNT_MASK 0x0000FFFFL |
27115 | #define CP_DFY_STAT__TAGS_PENDING_MASK 0x07FF0000L |
27116 | #define CP_DFY_STAT__BUSY_MASK 0x80000000L |
27117 | //CP_DFY_ADDR_HI |
27118 | #define CP_DFY_ADDR_HI__ADDR_HI__SHIFT 0x0 |
27119 | #define CP_DFY_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL |
27120 | //CP_DFY_ADDR_LO |
27121 | #define CP_DFY_ADDR_LO__ADDR_LO__SHIFT 0x5 |
27122 | #define CP_DFY_ADDR_LO__ADDR_LO_MASK 0xFFFFFFE0L |
27123 | //CP_DFY_DATA_0 |
27124 | #define CP_DFY_DATA_0__DATA__SHIFT 0x0 |
27125 | #define CP_DFY_DATA_0__DATA_MASK 0xFFFFFFFFL |
27126 | //CP_DFY_DATA_1 |
27127 | #define CP_DFY_DATA_1__DATA__SHIFT 0x0 |
27128 | #define CP_DFY_DATA_1__DATA_MASK 0xFFFFFFFFL |
27129 | //CP_DFY_DATA_2 |
27130 | #define CP_DFY_DATA_2__DATA__SHIFT 0x0 |
27131 | #define CP_DFY_DATA_2__DATA_MASK 0xFFFFFFFFL |
27132 | //CP_DFY_DATA_3 |
27133 | #define CP_DFY_DATA_3__DATA__SHIFT 0x0 |
27134 | #define CP_DFY_DATA_3__DATA_MASK 0xFFFFFFFFL |
27135 | //CP_DFY_DATA_4 |
27136 | #define CP_DFY_DATA_4__DATA__SHIFT 0x0 |
27137 | #define CP_DFY_DATA_4__DATA_MASK 0xFFFFFFFFL |
27138 | //CP_DFY_DATA_5 |
27139 | #define CP_DFY_DATA_5__DATA__SHIFT 0x0 |
27140 | #define CP_DFY_DATA_5__DATA_MASK 0xFFFFFFFFL |
27141 | //CP_DFY_DATA_6 |
27142 | #define CP_DFY_DATA_6__DATA__SHIFT 0x0 |
27143 | #define CP_DFY_DATA_6__DATA_MASK 0xFFFFFFFFL |
27144 | //CP_DFY_DATA_7 |
27145 | #define CP_DFY_DATA_7__DATA__SHIFT 0x0 |
27146 | #define CP_DFY_DATA_7__DATA_MASK 0xFFFFFFFFL |
27147 | //CP_DFY_DATA_8 |
27148 | #define CP_DFY_DATA_8__DATA__SHIFT 0x0 |
27149 | #define CP_DFY_DATA_8__DATA_MASK 0xFFFFFFFFL |
27150 | //CP_DFY_DATA_9 |
27151 | #define CP_DFY_DATA_9__DATA__SHIFT 0x0 |
27152 | #define CP_DFY_DATA_9__DATA_MASK 0xFFFFFFFFL |
27153 | //CP_DFY_DATA_10 |
27154 | #define CP_DFY_DATA_10__DATA__SHIFT 0x0 |
27155 | #define CP_DFY_DATA_10__DATA_MASK 0xFFFFFFFFL |
27156 | //CP_DFY_DATA_11 |
27157 | #define CP_DFY_DATA_11__DATA__SHIFT 0x0 |
27158 | #define CP_DFY_DATA_11__DATA_MASK 0xFFFFFFFFL |
27159 | //CP_DFY_DATA_12 |
27160 | #define CP_DFY_DATA_12__DATA__SHIFT 0x0 |
27161 | #define CP_DFY_DATA_12__DATA_MASK 0xFFFFFFFFL |
27162 | //CP_DFY_DATA_13 |
27163 | #define CP_DFY_DATA_13__DATA__SHIFT 0x0 |
27164 | #define CP_DFY_DATA_13__DATA_MASK 0xFFFFFFFFL |
27165 | //CP_DFY_DATA_14 |
27166 | #define CP_DFY_DATA_14__DATA__SHIFT 0x0 |
27167 | #define CP_DFY_DATA_14__DATA_MASK 0xFFFFFFFFL |
27168 | //CP_DFY_DATA_15 |
27169 | #define CP_DFY_DATA_15__DATA__SHIFT 0x0 |
27170 | #define CP_DFY_DATA_15__DATA_MASK 0xFFFFFFFFL |
27171 | //CP_DFY_CMD |
27172 | #define CP_DFY_CMD__SIZE__SHIFT 0x10 |
27173 | #define CP_DFY_CMD__SIZE_MASK 0xFFFF0000L |
27174 | |
27175 | |
27176 | // addressBlock: gc_pfonly_cpphqddec |
27177 | //CP_HPD_MES_ROQ_OFFSETS |
27178 | #define CP_HPD_MES_ROQ_OFFSETS__IQ_OFFSET__SHIFT 0x0 |
27179 | #define CP_HPD_MES_ROQ_OFFSETS__PQ_OFFSET__SHIFT 0x8 |
27180 | #define CP_HPD_MES_ROQ_OFFSETS__IB_OFFSET__SHIFT 0x10 |
27181 | #define CP_HPD_MES_ROQ_OFFSETS__IQ_OFFSET_MASK 0x00000007L |
27182 | #define CP_HPD_MES_ROQ_OFFSETS__PQ_OFFSET_MASK 0x00003F00L |
27183 | #define CP_HPD_MES_ROQ_OFFSETS__IB_OFFSET_MASK 0x007F0000L |
27184 | //CP_HPD_ROQ_OFFSETS |
27185 | #define CP_HPD_ROQ_OFFSETS__IQ_OFFSET__SHIFT 0x0 |
27186 | #define CP_HPD_ROQ_OFFSETS__PQ_OFFSET__SHIFT 0x8 |
27187 | #define CP_HPD_ROQ_OFFSETS__IB_OFFSET__SHIFT 0x10 |
27188 | #define CP_HPD_ROQ_OFFSETS__IQ_OFFSET_MASK 0x00000007L |
27189 | #define CP_HPD_ROQ_OFFSETS__PQ_OFFSET_MASK 0x00003F00L |
27190 | #define CP_HPD_ROQ_OFFSETS__IB_OFFSET_MASK 0x007F0000L |
27191 | //CP_HPD_STATUS0 |
27192 | #define CP_HPD_STATUS0__QUEUE_STATE__SHIFT 0x0 |
27193 | #define CP_HPD_STATUS0__MAPPED_QUEUE__SHIFT 0x5 |
27194 | #define CP_HPD_STATUS0__QUEUE_AVAILABLE__SHIFT 0x8 |
27195 | #define CP_HPD_STATUS0__FETCHING_MQD__SHIFT 0x10 |
27196 | #define CP_HPD_STATUS0__PEND_TXFER_SIZE_PQIB__SHIFT 0x11 |
27197 | #define CP_HPD_STATUS0__PEND_TXFER_SIZE_IQ__SHIFT 0x12 |
27198 | #define CP_HPD_STATUS0__FORCE_QUEUE_STATE__SHIFT 0x14 |
27199 | #define CP_HPD_STATUS0__MASTER_QUEUE_IDLE_DIS__SHIFT 0x1b |
27200 | #define CP_HPD_STATUS0__ENABLE_OFFLOAD_CHECK__SHIFT 0x1c |
27201 | #define CP_HPD_STATUS0__FREEZE_QUEUE_STATE__SHIFT 0x1e |
27202 | #define CP_HPD_STATUS0__FORCE_QUEUE__SHIFT 0x1f |
27203 | #define CP_HPD_STATUS0__QUEUE_STATE_MASK 0x0000001FL |
27204 | #define CP_HPD_STATUS0__MAPPED_QUEUE_MASK 0x000000E0L |
27205 | #define CP_HPD_STATUS0__QUEUE_AVAILABLE_MASK 0x0000FF00L |
27206 | #define CP_HPD_STATUS0__FETCHING_MQD_MASK 0x00010000L |
27207 | #define CP_HPD_STATUS0__PEND_TXFER_SIZE_PQIB_MASK 0x00020000L |
27208 | #define CP_HPD_STATUS0__PEND_TXFER_SIZE_IQ_MASK 0x00040000L |
27209 | #define CP_HPD_STATUS0__FORCE_QUEUE_STATE_MASK 0x01F00000L |
27210 | #define CP_HPD_STATUS0__MASTER_QUEUE_IDLE_DIS_MASK 0x08000000L |
27211 | #define CP_HPD_STATUS0__ENABLE_OFFLOAD_CHECK_MASK 0x30000000L |
27212 | #define CP_HPD_STATUS0__FREEZE_QUEUE_STATE_MASK 0x40000000L |
27213 | #define CP_HPD_STATUS0__FORCE_QUEUE_MASK 0x80000000L |
27214 | |
27215 | |
27216 | // addressBlock: gc_pfonly_didtdec |
27217 | //DIDT_INDEX_AUTO_INCR_EN |
27218 | #define DIDT_INDEX_AUTO_INCR_EN__DIDT_INDEX_AUTO_INCR_EN__SHIFT 0x0 |
27219 | #define DIDT_INDEX_AUTO_INCR_EN__DIDT_INDEX_AUTO_INCR_EN_MASK 0x00000001L |
27220 | //DIDT_EDC_CTRL |
27221 | #define DIDT_EDC_CTRL__EDC_EN__SHIFT 0x0 |
27222 | #define DIDT_EDC_CTRL__EDC_SW_RST__SHIFT 0x1 |
27223 | #define DIDT_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2 |
27224 | #define DIDT_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3 |
27225 | #define DIDT_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 |
27226 | #define DIDT_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT 0xa |
27227 | #define DIDT_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0xe |
27228 | #define DIDT_EDC_CTRL__EDC_ALGORITHM_MODE__SHIFT 0xf |
27229 | #define DIDT_EDC_CTRL__EDC_AVGDIV__SHIFT 0x10 |
27230 | #define DIDT_EDC_CTRL__EDC_THRESHOLD_RSHIFT_SEL__SHIFT 0x14 |
27231 | #define DIDT_EDC_CTRL__EDC_THRESHOLD_RSHIFT_BIT_NUMS__SHIFT 0x15 |
27232 | #define DIDT_EDC_CTRL__RLC_FORCE_STALL_EN__SHIFT 0x18 |
27233 | #define DIDT_EDC_CTRL__RLC_STALL_LEVEL_SEL__SHIFT 0x19 |
27234 | #define DIDT_EDC_CTRL__EDC_EN_MASK 0x00000001L |
27235 | #define DIDT_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L |
27236 | #define DIDT_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L |
27237 | #define DIDT_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L |
27238 | #define DIDT_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000003F0L |
27239 | #define DIDT_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK 0x00003C00L |
27240 | #define DIDT_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00004000L |
27241 | #define DIDT_EDC_CTRL__EDC_ALGORITHM_MODE_MASK 0x00008000L |
27242 | #define DIDT_EDC_CTRL__EDC_AVGDIV_MASK 0x000F0000L |
27243 | #define DIDT_EDC_CTRL__EDC_THRESHOLD_RSHIFT_SEL_MASK 0x00100000L |
27244 | #define DIDT_EDC_CTRL__EDC_THRESHOLD_RSHIFT_BIT_NUMS_MASK 0x00E00000L |
27245 | #define DIDT_EDC_CTRL__RLC_FORCE_STALL_EN_MASK 0x01000000L |
27246 | #define DIDT_EDC_CTRL__RLC_STALL_LEVEL_SEL_MASK 0x02000000L |
27247 | //DIDT_EDC_THROTTLE_CTRL |
27248 | #define DIDT_EDC_THROTTLE_CTRL__SQ_STALL_EN__SHIFT 0x0 |
27249 | #define DIDT_EDC_THROTTLE_CTRL__DB_STALL_EN__SHIFT 0x1 |
27250 | #define DIDT_EDC_THROTTLE_CTRL__TCP_STALL_EN__SHIFT 0x2 |
27251 | #define DIDT_EDC_THROTTLE_CTRL__TD_STALL_EN__SHIFT 0x3 |
27252 | #define DIDT_EDC_THROTTLE_CTRL__PATTERN_EXTEND_EN__SHIFT 0x4 |
27253 | #define DIDT_EDC_THROTTLE_CTRL__PATTERN_EXTEND_MODE__SHIFT 0x5 |
27254 | #define DIDT_EDC_THROTTLE_CTRL__SQ_STALL_EN_MASK 0x00000001L |
27255 | #define DIDT_EDC_THROTTLE_CTRL__DB_STALL_EN_MASK 0x00000002L |
27256 | #define DIDT_EDC_THROTTLE_CTRL__TCP_STALL_EN_MASK 0x00000004L |
27257 | #define DIDT_EDC_THROTTLE_CTRL__TD_STALL_EN_MASK 0x00000008L |
27258 | #define DIDT_EDC_THROTTLE_CTRL__PATTERN_EXTEND_EN_MASK 0x00000010L |
27259 | #define DIDT_EDC_THROTTLE_CTRL__PATTERN_EXTEND_MODE_MASK 0x000000E0L |
27260 | //DIDT_EDC_THRESHOLD |
27261 | #define DIDT_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x0 |
27262 | #define DIDT_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xFFFFFFFFL |
27263 | //DIDT_EDC_STALL_PATTERN_1_2 |
27264 | #define DIDT_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT 0x0 |
27265 | #define DIDT_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT 0x10 |
27266 | #define DIDT_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK 0x00007FFFL |
27267 | #define DIDT_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK 0x7FFF0000L |
27268 | //DIDT_EDC_STALL_PATTERN_3_4 |
27269 | #define DIDT_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT 0x0 |
27270 | #define DIDT_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT 0x10 |
27271 | #define DIDT_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK 0x00007FFFL |
27272 | #define DIDT_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK 0x7FFF0000L |
27273 | //DIDT_EDC_STALL_PATTERN_5_6 |
27274 | #define DIDT_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT 0x0 |
27275 | #define DIDT_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT 0x10 |
27276 | #define DIDT_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK 0x00007FFFL |
27277 | #define DIDT_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK 0x7FFF0000L |
27278 | //DIDT_EDC_STALL_PATTERN_7 |
27279 | #define DIDT_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT 0x0 |
27280 | #define DIDT_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK 0x00007FFFL |
27281 | //DIDT_EDC_STATUS |
27282 | #define DIDT_EDC_STATUS__EDC_FSM_STATE__SHIFT 0x0 |
27283 | #define DIDT_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT 0x1 |
27284 | #define DIDT_EDC_STATUS__EDC_FSM_STATE_MASK 0x00000001L |
27285 | #define DIDT_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK 0x0000000EL |
27286 | //DIDT_EDC_DYNAMIC_THRESHOLD_RO |
27287 | #define DIDT_EDC_DYNAMIC_THRESHOLD_RO__EDC_DYNAMIC_THRESHOLD_RO__SHIFT 0x0 |
27288 | #define DIDT_EDC_DYNAMIC_THRESHOLD_RO__EDC_DYNAMIC_THRESHOLD_RO_MASK 0x00000001L |
27289 | //DIDT_EDC_OVERFLOW |
27290 | #define DIDT_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT 0x0 |
27291 | #define DIDT_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT 0x1 |
27292 | #define DIDT_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK 0x00000001L |
27293 | #define DIDT_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK 0x0001FFFEL |
27294 | //DIDT_EDC_ROLLING_POWER_DELTA |
27295 | #define DIDT_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT 0x0 |
27296 | #define DIDT_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK 0xFFFFFFFFL |
27297 | //DIDT_IND_INDEX |
27298 | #define DIDT_IND_INDEX__DIDT_IND_INDEX__SHIFT 0x0 |
27299 | #define DIDT_IND_INDEX__DIDT_IND_INDEX_MASK 0xFFFFFFFFL |
27300 | //DIDT_IND_DATA |
27301 | #define DIDT_IND_DATA__DIDT_IND_DATA__SHIFT 0x0 |
27302 | #define DIDT_IND_DATA__DIDT_IND_DATA_MASK 0xFFFFFFFFL |
27303 | |
27304 | |
27305 | // addressBlock: gc_pfonly_spidec |
27306 | //SPI_CDBG_SYS_GFX |
27307 | #define SPI_CDBG_SYS_GFX__PS_EN__SHIFT 0x0 |
27308 | #define SPI_CDBG_SYS_GFX__GS_EN__SHIFT 0x2 |
27309 | #define SPI_CDBG_SYS_GFX__HS_EN__SHIFT 0x4 |
27310 | #define SPI_CDBG_SYS_GFX__CS_EN__SHIFT 0x6 |
27311 | #define SPI_CDBG_SYS_GFX__PS_EN_MASK 0x0001L |
27312 | #define SPI_CDBG_SYS_GFX__GS_EN_MASK 0x0004L |
27313 | #define SPI_CDBG_SYS_GFX__HS_EN_MASK 0x0010L |
27314 | #define SPI_CDBG_SYS_GFX__CS_EN_MASK 0x0040L |
27315 | //SPI_CDBG_SYS_HP3D |
27316 | #define SPI_CDBG_SYS_HP3D__PS_EN__SHIFT 0x0 |
27317 | #define SPI_CDBG_SYS_HP3D__GS_EN__SHIFT 0x2 |
27318 | #define SPI_CDBG_SYS_HP3D__HS_EN__SHIFT 0x4 |
27319 | #define SPI_CDBG_SYS_HP3D__CS_EN__SHIFT 0x6 |
27320 | #define SPI_CDBG_SYS_HP3D__PS_EN_MASK 0x0001L |
27321 | #define SPI_CDBG_SYS_HP3D__GS_EN_MASK 0x0004L |
27322 | #define SPI_CDBG_SYS_HP3D__HS_EN_MASK 0x0010L |
27323 | #define SPI_CDBG_SYS_HP3D__CS_EN_MASK 0x0040L |
27324 | //SPI_CDBG_SYS_CS0 |
27325 | #define SPI_CDBG_SYS_CS0__PIPE0__SHIFT 0x0 |
27326 | #define SPI_CDBG_SYS_CS0__PIPE1__SHIFT 0x8 |
27327 | #define SPI_CDBG_SYS_CS0__PIPE2__SHIFT 0x10 |
27328 | #define SPI_CDBG_SYS_CS0__PIPE3__SHIFT 0x18 |
27329 | #define SPI_CDBG_SYS_CS0__PIPE0_MASK 0x000000FFL |
27330 | #define SPI_CDBG_SYS_CS0__PIPE1_MASK 0x0000FF00L |
27331 | #define SPI_CDBG_SYS_CS0__PIPE2_MASK 0x00FF0000L |
27332 | #define SPI_CDBG_SYS_CS0__PIPE3_MASK 0xFF000000L |
27333 | //SPI_GDBG_WAVE_CNTL |
27334 | #define SPI_GDBG_WAVE_CNTL__STALL_RA__SHIFT 0x0 |
27335 | #define SPI_GDBG_WAVE_CNTL__STALL_LAUNCH__SHIFT 0x1 |
27336 | #define SPI_GDBG_WAVE_CNTL__STALL_RA_MASK 0x00000001L |
27337 | #define SPI_GDBG_WAVE_CNTL__STALL_LAUNCH_MASK 0x00000002L |
27338 | //SPI_GDBG_TRAP_CONFIG |
27339 | #define SPI_GDBG_TRAP_CONFIG__PIPE0_EN__SHIFT 0x0 |
27340 | #define SPI_GDBG_TRAP_CONFIG__PIPE1_EN__SHIFT 0x8 |
27341 | #define SPI_GDBG_TRAP_CONFIG__PIPE2_EN__SHIFT 0x10 |
27342 | #define SPI_GDBG_TRAP_CONFIG__PIPE3_EN__SHIFT 0x18 |
27343 | #define SPI_GDBG_TRAP_CONFIG__PIPE0_EN_MASK 0x000000FFL |
27344 | #define SPI_GDBG_TRAP_CONFIG__PIPE1_EN_MASK 0x0000FF00L |
27345 | #define SPI_GDBG_TRAP_CONFIG__PIPE2_EN_MASK 0x00FF0000L |
27346 | #define SPI_GDBG_TRAP_CONFIG__PIPE3_EN_MASK 0xFF000000L |
27347 | //SPI_GDBG_WAVE_CNTL3 |
27348 | #define SPI_GDBG_WAVE_CNTL3__STALL_PS__SHIFT 0x0 |
27349 | #define SPI_GDBG_WAVE_CNTL3__STALL_GS__SHIFT 0x2 |
27350 | #define SPI_GDBG_WAVE_CNTL3__STALL_HS__SHIFT 0x3 |
27351 | #define SPI_GDBG_WAVE_CNTL3__STALL_CSG__SHIFT 0x4 |
27352 | #define SPI_GDBG_WAVE_CNTL3__STALL_CS0__SHIFT 0x5 |
27353 | #define SPI_GDBG_WAVE_CNTL3__STALL_CS1__SHIFT 0x6 |
27354 | #define SPI_GDBG_WAVE_CNTL3__STALL_CS2__SHIFT 0x7 |
27355 | #define SPI_GDBG_WAVE_CNTL3__STALL_CS3__SHIFT 0x8 |
27356 | #define SPI_GDBG_WAVE_CNTL3__STALL_CS4__SHIFT 0x9 |
27357 | #define SPI_GDBG_WAVE_CNTL3__STALL_CS5__SHIFT 0xa |
27358 | #define SPI_GDBG_WAVE_CNTL3__STALL_CS6__SHIFT 0xb |
27359 | #define SPI_GDBG_WAVE_CNTL3__STALL_CS7__SHIFT 0xc |
27360 | #define SPI_GDBG_WAVE_CNTL3__STALL_DURATION__SHIFT 0xd |
27361 | #define SPI_GDBG_WAVE_CNTL3__STALL_MULT__SHIFT 0x1c |
27362 | #define SPI_GDBG_WAVE_CNTL3__STALL_PS_MASK 0x00000001L |
27363 | #define SPI_GDBG_WAVE_CNTL3__STALL_GS_MASK 0x00000004L |
27364 | #define SPI_GDBG_WAVE_CNTL3__STALL_HS_MASK 0x00000008L |
27365 | #define SPI_GDBG_WAVE_CNTL3__STALL_CSG_MASK 0x00000010L |
27366 | #define SPI_GDBG_WAVE_CNTL3__STALL_CS0_MASK 0x00000020L |
27367 | #define SPI_GDBG_WAVE_CNTL3__STALL_CS1_MASK 0x00000040L |
27368 | #define SPI_GDBG_WAVE_CNTL3__STALL_CS2_MASK 0x00000080L |
27369 | #define SPI_GDBG_WAVE_CNTL3__STALL_CS3_MASK 0x00000100L |
27370 | #define SPI_GDBG_WAVE_CNTL3__STALL_CS4_MASK 0x00000200L |
27371 | #define SPI_GDBG_WAVE_CNTL3__STALL_CS5_MASK 0x00000400L |
27372 | #define SPI_GDBG_WAVE_CNTL3__STALL_CS6_MASK 0x00000800L |
27373 | #define SPI_GDBG_WAVE_CNTL3__STALL_CS7_MASK 0x00001000L |
27374 | #define SPI_GDBG_WAVE_CNTL3__STALL_DURATION_MASK 0x0FFFE000L |
27375 | #define SPI_GDBG_WAVE_CNTL3__STALL_MULT_MASK 0x10000000L |
27376 | //SPI_RESET_DEBUG |
27377 | #define SPI_RESET_DEBUG__DISABLE_GFX_RESET__SHIFT 0x0 |
27378 | #define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PER_VMID__SHIFT 0x1 |
27379 | #define SPI_RESET_DEBUG__DISABLE_GFX_RESET_ALL_VMID__SHIFT 0x2 |
27380 | #define SPI_RESET_DEBUG__DISABLE_GFX_RESET_RESOURCE__SHIFT 0x3 |
27381 | #define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PRIORITY__SHIFT 0x4 |
27382 | #define SPI_RESET_DEBUG__DISABLE_GFX_RESET_MASK 0x01L |
27383 | #define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PER_VMID_MASK 0x02L |
27384 | #define SPI_RESET_DEBUG__DISABLE_GFX_RESET_ALL_VMID_MASK 0x04L |
27385 | #define SPI_RESET_DEBUG__DISABLE_GFX_RESET_RESOURCE_MASK 0x08L |
27386 | #define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PRIORITY_MASK 0x10L |
27387 | //SPI_ARB_CNTL_0 |
27388 | #define SPI_ARB_CNTL_0__EXP_ARB_COL_WT__SHIFT 0x0 |
27389 | #define SPI_ARB_CNTL_0__EXP_ARB_POS_WT__SHIFT 0x4 |
27390 | #define SPI_ARB_CNTL_0__EXP_ARB_GDS_WT__SHIFT 0x8 |
27391 | #define SPI_ARB_CNTL_0__EXP_ARB_COL_WT_MASK 0x0000000FL |
27392 | #define SPI_ARB_CNTL_0__EXP_ARB_POS_WT_MASK 0x000000F0L |
27393 | #define SPI_ARB_CNTL_0__EXP_ARB_GDS_WT_MASK 0x00000F00L |
27394 | //SPI_FEATURE_CTRL |
27395 | #define SPI_FEATURE_CTRL__TUNNELING_WAVE_LIMIT__SHIFT 0x0 |
27396 | #define SPI_FEATURE_CTRL__RA_PROBE_IGNORE__SHIFT 0x4 |
27397 | #define SPI_FEATURE_CTRL__PS_THROTTLE_MAX_WAVE_LIMIT__SHIFT 0x5 |
27398 | #define SPI_FEATURE_CTRL__RA_PROBE_SKEW_WIF_CTRL__SHIFT 0xb |
27399 | #define SPI_FEATURE_CTRL__RA_PROBE_SKEW_OOO_CTRL__SHIFT 0xd |
27400 | #define SPI_FEATURE_CTRL__RA_PROBE_SKEW_DISABLE__SHIFT 0xe |
27401 | #define SPI_FEATURE_CTRL__TUNNELING_WAVE_LIMIT_MASK 0x0000000FL |
27402 | #define SPI_FEATURE_CTRL__RA_PROBE_IGNORE_MASK 0x00000010L |
27403 | #define SPI_FEATURE_CTRL__PS_THROTTLE_MAX_WAVE_LIMIT_MASK 0x000007E0L |
27404 | #define SPI_FEATURE_CTRL__RA_PROBE_SKEW_WIF_CTRL_MASK 0x00001800L |
27405 | #define SPI_FEATURE_CTRL__RA_PROBE_SKEW_OOO_CTRL_MASK 0x00002000L |
27406 | #define SPI_FEATURE_CTRL__RA_PROBE_SKEW_DISABLE_MASK 0x00004000L |
27407 | //SPI_SHADER_RSRC_LIMIT_CTRL |
27408 | #define SPI_SHADER_RSRC_LIMIT_CTRL__WAVES_PER_SIMD32__SHIFT 0x0 |
27409 | #define SPI_SHADER_RSRC_LIMIT_CTRL__VGPR_PER_SIMD32__SHIFT 0x5 |
27410 | #define SPI_SHADER_RSRC_LIMIT_CTRL__VGPR_WRAP_DISABLE__SHIFT 0xc |
27411 | #define SPI_SHADER_RSRC_LIMIT_CTRL__BARRIER_LIMIT__SHIFT 0xd |
27412 | #define SPI_SHADER_RSRC_LIMIT_CTRL__BARRIER_LIMIT_HIERARCHY_LEVEL__SHIFT 0x13 |
27413 | #define SPI_SHADER_RSRC_LIMIT_CTRL__LDS_LIMIT__SHIFT 0x14 |
27414 | #define SPI_SHADER_RSRC_LIMIT_CTRL__LDS_LIMIT_HIERARCHY_LEVEL__SHIFT 0x1c |
27415 | #define SPI_SHADER_RSRC_LIMIT_CTRL__PERFORMANCE_LIMIT_ENABLE__SHIFT 0x1f |
27416 | #define SPI_SHADER_RSRC_LIMIT_CTRL__WAVES_PER_SIMD32_MASK 0x0000001FL |
27417 | #define SPI_SHADER_RSRC_LIMIT_CTRL__VGPR_PER_SIMD32_MASK 0x00000FE0L |
27418 | #define SPI_SHADER_RSRC_LIMIT_CTRL__VGPR_WRAP_DISABLE_MASK 0x00001000L |
27419 | #define SPI_SHADER_RSRC_LIMIT_CTRL__BARRIER_LIMIT_MASK 0x0007E000L |
27420 | #define SPI_SHADER_RSRC_LIMIT_CTRL__BARRIER_LIMIT_HIERARCHY_LEVEL_MASK 0x00080000L |
27421 | #define SPI_SHADER_RSRC_LIMIT_CTRL__LDS_LIMIT_MASK 0x0FF00000L |
27422 | #define SPI_SHADER_RSRC_LIMIT_CTRL__LDS_LIMIT_HIERARCHY_LEVEL_MASK 0x10000000L |
27423 | #define SPI_SHADER_RSRC_LIMIT_CTRL__PERFORMANCE_LIMIT_ENABLE_MASK 0x80000000L |
27424 | //SPI_COMPUTE_WF_CTX_SAVE_STATUS |
27425 | #define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE0_SAVE_BUSY__SHIFT 0x0 |
27426 | #define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE1_SAVE_BUSY__SHIFT 0x1 |
27427 | #define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE2_SAVE_BUSY__SHIFT 0x2 |
27428 | #define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE3_SAVE_BUSY__SHIFT 0x3 |
27429 | #define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE4_SAVE_BUSY__SHIFT 0x4 |
27430 | #define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE5_SAVE_BUSY__SHIFT 0x5 |
27431 | #define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE6_SAVE_BUSY__SHIFT 0x6 |
27432 | #define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE7_SAVE_BUSY__SHIFT 0x7 |
27433 | #define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE0_SAVE_BUSY__SHIFT 0x8 |
27434 | #define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE1_SAVE_BUSY__SHIFT 0x9 |
27435 | #define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE2_SAVE_BUSY__SHIFT 0xa |
27436 | #define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE3_SAVE_BUSY__SHIFT 0xb |
27437 | #define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE4_SAVE_BUSY__SHIFT 0xc |
27438 | #define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE5_SAVE_BUSY__SHIFT 0xd |
27439 | #define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE6_SAVE_BUSY__SHIFT 0xe |
27440 | #define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE7_SAVE_BUSY__SHIFT 0xf |
27441 | #define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE0_SAVE_BUSY__SHIFT 0x10 |
27442 | #define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE1_SAVE_BUSY__SHIFT 0x11 |
27443 | #define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE2_SAVE_BUSY__SHIFT 0x12 |
27444 | #define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE3_SAVE_BUSY__SHIFT 0x13 |
27445 | #define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE4_SAVE_BUSY__SHIFT 0x14 |
27446 | #define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE5_SAVE_BUSY__SHIFT 0x15 |
27447 | #define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE6_SAVE_BUSY__SHIFT 0x16 |
27448 | #define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE7_SAVE_BUSY__SHIFT 0x17 |
27449 | #define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE0_SAVE_BUSY__SHIFT 0x18 |
27450 | #define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE1_SAVE_BUSY__SHIFT 0x19 |
27451 | #define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE2_SAVE_BUSY__SHIFT 0x1a |
27452 | #define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE3_SAVE_BUSY__SHIFT 0x1b |
27453 | #define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE4_SAVE_BUSY__SHIFT 0x1c |
27454 | #define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE5_SAVE_BUSY__SHIFT 0x1d |
27455 | #define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE6_SAVE_BUSY__SHIFT 0x1e |
27456 | #define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE7_SAVE_BUSY__SHIFT 0x1f |
27457 | #define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE0_SAVE_BUSY_MASK 0x00000001L |
27458 | #define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE1_SAVE_BUSY_MASK 0x00000002L |
27459 | #define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE2_SAVE_BUSY_MASK 0x00000004L |
27460 | #define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE3_SAVE_BUSY_MASK 0x00000008L |
27461 | #define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE4_SAVE_BUSY_MASK 0x00000010L |
27462 | #define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE5_SAVE_BUSY_MASK 0x00000020L |
27463 | #define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE6_SAVE_BUSY_MASK 0x00000040L |
27464 | #define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE7_SAVE_BUSY_MASK 0x00000080L |
27465 | #define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE0_SAVE_BUSY_MASK 0x00000100L |
27466 | #define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE1_SAVE_BUSY_MASK 0x00000200L |
27467 | #define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE2_SAVE_BUSY_MASK 0x00000400L |
27468 | #define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE3_SAVE_BUSY_MASK 0x00000800L |
27469 | #define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE4_SAVE_BUSY_MASK 0x00001000L |
27470 | #define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE5_SAVE_BUSY_MASK 0x00002000L |
27471 | #define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE6_SAVE_BUSY_MASK 0x00004000L |
27472 | #define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE7_SAVE_BUSY_MASK 0x00008000L |
27473 | #define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE0_SAVE_BUSY_MASK 0x00010000L |
27474 | #define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE1_SAVE_BUSY_MASK 0x00020000L |
27475 | #define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE2_SAVE_BUSY_MASK 0x00040000L |
27476 | #define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE3_SAVE_BUSY_MASK 0x00080000L |
27477 | #define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE4_SAVE_BUSY_MASK 0x00100000L |
27478 | #define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE5_SAVE_BUSY_MASK 0x00200000L |
27479 | #define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE6_SAVE_BUSY_MASK 0x00400000L |
27480 | #define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE7_SAVE_BUSY_MASK 0x00800000L |
27481 | #define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE0_SAVE_BUSY_MASK 0x01000000L |
27482 | #define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE1_SAVE_BUSY_MASK 0x02000000L |
27483 | #define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE2_SAVE_BUSY_MASK 0x04000000L |
27484 | #define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE3_SAVE_BUSY_MASK 0x08000000L |
27485 | #define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE4_SAVE_BUSY_MASK 0x10000000L |
27486 | #define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE5_SAVE_BUSY_MASK 0x20000000L |
27487 | #define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE6_SAVE_BUSY_MASK 0x40000000L |
27488 | #define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE7_SAVE_BUSY_MASK 0x80000000L |
27489 | |
27490 | |
27491 | // addressBlock: gc_pfonly_tcpdec |
27492 | //TCP_INVALIDATE |
27493 | #define TCP_INVALIDATE__START__SHIFT 0x0 |
27494 | #define TCP_INVALIDATE__START_MASK 0x00000001L |
27495 | //TCP_STATUS |
27496 | #define TCP_STATUS__TCP_BUSY__SHIFT 0x0 |
27497 | #define TCP_STATUS__INPUT_BUSY__SHIFT 0x1 |
27498 | #define TCP_STATUS__ADRS_BUSY__SHIFT 0x2 |
27499 | #define TCP_STATUS__TAGRAMS_BUSY__SHIFT 0x3 |
27500 | #define TCP_STATUS__CNTRL_BUSY__SHIFT 0x4 |
27501 | #define TCP_STATUS__LFIFO_BUSY__SHIFT 0x5 |
27502 | #define TCP_STATUS__READ_BUSY__SHIFT 0x6 |
27503 | #define TCP_STATUS__FORMAT_BUSY__SHIFT 0x7 |
27504 | #define TCP_STATUS__VM_BUSY__SHIFT 0x8 |
27505 | #define TCP_STATUS__MEMIF_BUSY__SHIFT 0x9 |
27506 | #define TCP_STATUS__GCR_BUSY__SHIFT 0xa |
27507 | #define TCP_STATUS__OFIFO_BUSY__SHIFT 0xb |
27508 | #define TCP_STATUS__OFIFO_QUEUE_BUSY__SHIFT 0xc |
27509 | #define TCP_STATUS__XNACK_PRT__SHIFT 0xf |
27510 | #define TCP_STATUS__TCP_BUSY_MASK 0x00000001L |
27511 | #define TCP_STATUS__INPUT_BUSY_MASK 0x00000002L |
27512 | #define TCP_STATUS__ADRS_BUSY_MASK 0x00000004L |
27513 | #define TCP_STATUS__TAGRAMS_BUSY_MASK 0x00000008L |
27514 | #define TCP_STATUS__CNTRL_BUSY_MASK 0x00000010L |
27515 | #define TCP_STATUS__LFIFO_BUSY_MASK 0x00000020L |
27516 | #define TCP_STATUS__READ_BUSY_MASK 0x00000040L |
27517 | #define TCP_STATUS__FORMAT_BUSY_MASK 0x00000080L |
27518 | #define TCP_STATUS__VM_BUSY_MASK 0x00000100L |
27519 | #define TCP_STATUS__MEMIF_BUSY_MASK 0x00000200L |
27520 | #define TCP_STATUS__GCR_BUSY_MASK 0x00000400L |
27521 | #define TCP_STATUS__OFIFO_BUSY_MASK 0x00000800L |
27522 | #define TCP_STATUS__OFIFO_QUEUE_BUSY_MASK 0x00003000L |
27523 | #define TCP_STATUS__XNACK_PRT_MASK 0x00008000L |
27524 | //TCP_CNTL |
27525 | #define TCP_CNTL__FORCE_HIT__SHIFT 0x0 |
27526 | #define TCP_CNTL__FORCE_MISS__SHIFT 0x1 |
27527 | #define TCP_CNTL__FLAT_BUF_CACHE_SWIZZLE__SHIFT 0x5 |
27528 | #define TCP_CNTL__TD_DATA_EN_OVERRIDE__SHIFT 0x6 |
27529 | #define TCP_CNTL__ENABLE_128B_DCC_COMP_READ_FOR_INDEP64__SHIFT 0x7 |
27530 | #define TCP_CNTL__DISABLE_WRITE_COMBINING__SHIFT 0x9 |
27531 | #define TCP_CNTL__FORCE_EOW_TOTAL_CNT__SHIFT 0xf |
27532 | #define TCP_CNTL__FORCE_EOW_SET_CNT__SHIFT 0x16 |
27533 | #define TCP_CNTL__DISABLE_Z_MAP__SHIFT 0x1c |
27534 | #define TCP_CNTL__FORCE_ORDER_BETWEEN_READ_WRITE_TO_SAME_ADDRESS__SHIFT 0x1d |
27535 | #define TCP_CNTL__ASTC_VE_MSB_TOLERANT__SHIFT 0x1f |
27536 | #define TCP_CNTL__FORCE_HIT_MASK 0x00000001L |
27537 | #define TCP_CNTL__FORCE_MISS_MASK 0x00000002L |
27538 | #define TCP_CNTL__FLAT_BUF_CACHE_SWIZZLE_MASK 0x00000020L |
27539 | #define TCP_CNTL__TD_DATA_EN_OVERRIDE_MASK 0x00000040L |
27540 | #define TCP_CNTL__ENABLE_128B_DCC_COMP_READ_FOR_INDEP64_MASK 0x00000080L |
27541 | #define TCP_CNTL__DISABLE_WRITE_COMBINING_MASK 0x00000200L |
27542 | #define TCP_CNTL__FORCE_EOW_TOTAL_CNT_MASK 0x001F8000L |
27543 | #define TCP_CNTL__FORCE_EOW_SET_CNT_MASK 0x07C00000L |
27544 | #define TCP_CNTL__DISABLE_Z_MAP_MASK 0x10000000L |
27545 | #define TCP_CNTL__FORCE_ORDER_BETWEEN_READ_WRITE_TO_SAME_ADDRESS_MASK 0x20000000L |
27546 | #define TCP_CNTL__ASTC_VE_MSB_TOLERANT_MASK 0x80000000L |
27547 | //TCP_CNTL2 |
27548 | #define TCP_CNTL2__LS_DISABLE_CLOCKS__SHIFT 0x0 |
27549 | #define TCP_CNTL2__TCP_FMT_MGCG_DISABLE__SHIFT 0x8 |
27550 | #define TCP_CNTL2__TCPF_LATENCY_BYPASS_DISABLE__SHIFT 0x9 |
27551 | #define TCP_CNTL2__TCP_WRITE_DATA_MGCG_DISABLE__SHIFT 0xa |
27552 | #define TCP_CNTL2__TCP_INNER_BLOCK_MGCG_DISABLE__SHIFT 0xb |
27553 | #define TCP_CNTL2__TCP_ADRS_IMG_CALC_MGCG_DISABLE__SHIFT 0xc |
27554 | #define TCP_CNTL2__V64_COMBINE_ENABLE__SHIFT 0xd |
27555 | #define TCP_CNTL2__TAGRAM_ADDR_SWIZZLE_DISABLE__SHIFT 0xe |
27556 | #define TCP_CNTL2__RETURN_ORDER_OVERRIDE__SHIFT 0xf |
27557 | #define TCP_CNTL2__POWER_OPT_DISABLE__SHIFT 0x10 |
27558 | #define TCP_CNTL2__GCR_RSP_FGCG_DISABLE__SHIFT 0x11 |
27559 | #define TCP_CNTL2__PERF_EN_OVERRIDE__SHIFT 0x12 |
27560 | #define TCP_CNTL2__TC_TD_RAM_CLKEN_DISABLE__SHIFT 0x14 |
27561 | #define TCP_CNTL2__TC_TD_DATA_CLKEN_DISABLE__SHIFT 0x15 |
27562 | #define TCP_CNTL2__TCP_GL1_REQ_CLKEN_DISABLE__SHIFT 0x16 |
27563 | #define TCP_CNTL2__TCP_GL1R_SRC_CLKEN_DISABLE__SHIFT 0x17 |
27564 | #define TCP_CNTL2__SPARE_BIT__SHIFT 0x1a |
27565 | #define TCP_CNTL2__TAGRAM_XY_BIAS_OVERRIDE__SHIFT 0x1b |
27566 | #define TCP_CNTL2__TCP_REQ_MGCG_DISABLE__SHIFT 0x1d |
27567 | #define TCP_CNTL2__TCP_MISS_MGCG_DISABLE__SHIFT 0x1e |
27568 | #define TCP_CNTL2__DISABLE_MIPMAP_PARAM_CALC_SELF_GATING__SHIFT 0x1f |
27569 | #define TCP_CNTL2__LS_DISABLE_CLOCKS_MASK 0x000000FFL |
27570 | #define TCP_CNTL2__TCP_FMT_MGCG_DISABLE_MASK 0x00000100L |
27571 | #define TCP_CNTL2__TCPF_LATENCY_BYPASS_DISABLE_MASK 0x00000200L |
27572 | #define TCP_CNTL2__TCP_WRITE_DATA_MGCG_DISABLE_MASK 0x00000400L |
27573 | #define TCP_CNTL2__TCP_INNER_BLOCK_MGCG_DISABLE_MASK 0x00000800L |
27574 | #define TCP_CNTL2__TCP_ADRS_IMG_CALC_MGCG_DISABLE_MASK 0x00001000L |
27575 | #define TCP_CNTL2__V64_COMBINE_ENABLE_MASK 0x00002000L |
27576 | #define TCP_CNTL2__TAGRAM_ADDR_SWIZZLE_DISABLE_MASK 0x00004000L |
27577 | #define TCP_CNTL2__RETURN_ORDER_OVERRIDE_MASK 0x00008000L |
27578 | #define TCP_CNTL2__POWER_OPT_DISABLE_MASK 0x00010000L |
27579 | #define TCP_CNTL2__GCR_RSP_FGCG_DISABLE_MASK 0x00020000L |
27580 | #define TCP_CNTL2__PERF_EN_OVERRIDE_MASK 0x000C0000L |
27581 | #define TCP_CNTL2__TC_TD_RAM_CLKEN_DISABLE_MASK 0x00100000L |
27582 | #define TCP_CNTL2__TC_TD_DATA_CLKEN_DISABLE_MASK 0x00200000L |
27583 | #define TCP_CNTL2__TCP_GL1_REQ_CLKEN_DISABLE_MASK 0x00400000L |
27584 | #define TCP_CNTL2__TCP_GL1R_SRC_CLKEN_DISABLE_MASK 0x00800000L |
27585 | #define TCP_CNTL2__SPARE_BIT_MASK 0x04000000L |
27586 | #define TCP_CNTL2__TAGRAM_XY_BIAS_OVERRIDE_MASK 0x18000000L |
27587 | #define TCP_CNTL2__TCP_REQ_MGCG_DISABLE_MASK 0x20000000L |
27588 | #define TCP_CNTL2__TCP_MISS_MGCG_DISABLE_MASK 0x40000000L |
27589 | #define TCP_CNTL2__DISABLE_MIPMAP_PARAM_CALC_SELF_GATING_MASK 0x80000000L |
27590 | //TCP_CREDIT |
27591 | #define TCP_CREDIT__LFIFO_RAM_DEPTH__SHIFT 0x0 |
27592 | #define TCP_CREDIT__GL1_REQ_CREDIT__SHIFT 0xa |
27593 | #define TCP_CREDIT__REQ_FIFO_CREDIT__SHIFT 0x10 |
27594 | #define TCP_CREDIT__TD_RAM_CREDIT__SHIFT 0x17 |
27595 | #define TCP_CREDIT__TD_DATA_CREDIT__SHIFT 0x1d |
27596 | #define TCP_CREDIT__LFIFO_RAM_DEPTH_MASK 0x000003FFL |
27597 | #define TCP_CREDIT__GL1_REQ_CREDIT_MASK 0x0000FC00L |
27598 | #define TCP_CREDIT__REQ_FIFO_CREDIT_MASK 0x007F0000L |
27599 | #define TCP_CREDIT__TD_RAM_CREDIT_MASK 0x0F800000L |
27600 | #define TCP_CREDIT__TD_DATA_CREDIT_MASK 0xE0000000L |
27601 | |
27602 | |
27603 | // addressBlock: gc_pfonly_gdsdec |
27604 | //GDS_ENHANCE2 |
27605 | #define GDS_ENHANCE2__DISABLE_MEMORY_VIOLATION_REPORT__SHIFT 0x0 |
27606 | #define GDS_ENHANCE2__GDS_INTERFACES_FGCG_OVERRIDE__SHIFT 0x1 |
27607 | #define GDS_ENHANCE2__DISABLE_PIPE_MEMORY_RD_OPT__SHIFT 0x2 |
27608 | #define GDS_ENHANCE2__UNUSED__SHIFT 0x3 |
27609 | #define GDS_ENHANCE2__DISABLE_MEMORY_VIOLATION_REPORT_MASK 0x00000001L |
27610 | #define GDS_ENHANCE2__GDS_INTERFACES_FGCG_OVERRIDE_MASK 0x00000002L |
27611 | #define GDS_ENHANCE2__DISABLE_PIPE_MEMORY_RD_OPT_MASK 0x00000004L |
27612 | #define GDS_ENHANCE2__UNUSED_MASK 0xFFFFFFF8L |
27613 | //GDS_OA_CGPG_RESTORE |
27614 | #define GDS_OA_CGPG_RESTORE__VMID__SHIFT 0x0 |
27615 | #define GDS_OA_CGPG_RESTORE__MEID__SHIFT 0x8 |
27616 | #define GDS_OA_CGPG_RESTORE__PIPEID__SHIFT 0xc |
27617 | #define GDS_OA_CGPG_RESTORE__QUEUEID__SHIFT 0x10 |
27618 | #define GDS_OA_CGPG_RESTORE__UNUSED__SHIFT 0x14 |
27619 | #define GDS_OA_CGPG_RESTORE__VMID_MASK 0x000000FFL |
27620 | #define GDS_OA_CGPG_RESTORE__MEID_MASK 0x00000F00L |
27621 | #define GDS_OA_CGPG_RESTORE__PIPEID_MASK 0x0000F000L |
27622 | #define GDS_OA_CGPG_RESTORE__QUEUEID_MASK 0x000F0000L |
27623 | #define GDS_OA_CGPG_RESTORE__UNUSED_MASK 0xFFF00000L |
27624 | |
27625 | |
27626 | // addressBlock: gc_pfonly_utcl1dec |
27627 | //UTCL1_CTRL_0 |
27628 | #define UTCL1_CTRL_0__UTCL1_L0_REQ_VFIFO_DISABLE__SHIFT 0x0 |
27629 | #define UTCL1_CTRL_0__UTCL1_UTCL2_INVACK_CDC_FIFO_DISABLE__SHIFT 0x1 |
27630 | #define UTCL1_CTRL_0__RESERVED_0__SHIFT 0x2 |
27631 | #define UTCL1_CTRL_0__UTCL1_UTCL2_REQ_CREDITS__SHIFT 0x3 |
27632 | #define UTCL1_CTRL_0__UTCL1_UTCL0_INVREQ_CREDITS__SHIFT 0x9 |
27633 | #define UTCL1_CTRL_0__UTCL1_LIMIT_INV_TO_ONE__SHIFT 0xd |
27634 | #define UTCL1_CTRL_0__UTCL1_LIMIT_XLAT_TO_ONE__SHIFT 0xe |
27635 | #define UTCL1_CTRL_0__UTCL1_UTCL2_FGCG_REPEATERS_OVERRIDE__SHIFT 0xf |
27636 | #define UTCL1_CTRL_0__UTCL1_INV_FILTER_VMID__SHIFT 0x10 |
27637 | #define UTCL1_CTRL_0__UTCL1_RANGE_INV_FORCE_CHK_ALL__SHIFT 0x11 |
27638 | #define UTCL1_CTRL_0__UTCL1_UTCL0_RET_FGCG_REPEATERS_OVERRIDE__SHIFT 0x12 |
27639 | #define UTCL1_CTRL_0__UTCL1_UTCL0_INVREQ_FGCG_REPEATERS_OVERRIDE__SHIFT 0x13 |
27640 | #define UTCL1_CTRL_0__GCRD_FGCG_DISABLE__SHIFT 0x14 |
27641 | #define UTCL1_CTRL_0__UTCL1_MH_RANGE_INV_TO_VMID_OVERRIDE__SHIFT 0x15 |
27642 | #define UTCL1_CTRL_0__UTCL1_MH_DISABLE_DUPLICATES__SHIFT 0x16 |
27643 | #define UTCL1_CTRL_0__UTCL1_MH_DISABLE_REQUEST_SQUASHING__SHIFT 0x17 |
27644 | #define UTCL1_CTRL_0__UTCL1_MH_DISABLE_RECENT_BUFFER__SHIFT 0x18 |
27645 | #define UTCL1_CTRL_0__UTCL1_XLAT_FAULT_LOCK_CTRL__SHIFT 0x19 |
27646 | #define UTCL1_CTRL_0__UTCL1_REDUCE_CC_SIZE__SHIFT 0x1b |
27647 | #define UTCL1_CTRL_0__RESERVED_1__SHIFT 0x1d |
27648 | #define UTCL1_CTRL_0__MH_SPARE0__SHIFT 0x1e |
27649 | #define UTCL1_CTRL_0__RESERVED_2__SHIFT 0x1f |
27650 | #define UTCL1_CTRL_0__UTCL1_L0_REQ_VFIFO_DISABLE_MASK 0x00000001L |
27651 | #define UTCL1_CTRL_0__UTCL1_UTCL2_INVACK_CDC_FIFO_DISABLE_MASK 0x00000002L |
27652 | #define UTCL1_CTRL_0__RESERVED_0_MASK 0x00000004L |
27653 | #define UTCL1_CTRL_0__UTCL1_UTCL2_REQ_CREDITS_MASK 0x000001F8L |
27654 | #define UTCL1_CTRL_0__UTCL1_UTCL0_INVREQ_CREDITS_MASK 0x00001E00L |
27655 | #define UTCL1_CTRL_0__UTCL1_LIMIT_INV_TO_ONE_MASK 0x00002000L |
27656 | #define UTCL1_CTRL_0__UTCL1_LIMIT_XLAT_TO_ONE_MASK 0x00004000L |
27657 | #define UTCL1_CTRL_0__UTCL1_UTCL2_FGCG_REPEATERS_OVERRIDE_MASK 0x00008000L |
27658 | #define UTCL1_CTRL_0__UTCL1_INV_FILTER_VMID_MASK 0x00010000L |
27659 | #define UTCL1_CTRL_0__UTCL1_RANGE_INV_FORCE_CHK_ALL_MASK 0x00020000L |
27660 | #define UTCL1_CTRL_0__UTCL1_UTCL0_RET_FGCG_REPEATERS_OVERRIDE_MASK 0x00040000L |
27661 | #define UTCL1_CTRL_0__UTCL1_UTCL0_INVREQ_FGCG_REPEATERS_OVERRIDE_MASK 0x00080000L |
27662 | #define UTCL1_CTRL_0__GCRD_FGCG_DISABLE_MASK 0x00100000L |
27663 | #define UTCL1_CTRL_0__UTCL1_MH_RANGE_INV_TO_VMID_OVERRIDE_MASK 0x00200000L |
27664 | #define UTCL1_CTRL_0__UTCL1_MH_DISABLE_DUPLICATES_MASK 0x00400000L |
27665 | #define UTCL1_CTRL_0__UTCL1_MH_DISABLE_REQUEST_SQUASHING_MASK 0x00800000L |
27666 | #define UTCL1_CTRL_0__UTCL1_MH_DISABLE_RECENT_BUFFER_MASK 0x01000000L |
27667 | #define UTCL1_CTRL_0__UTCL1_XLAT_FAULT_LOCK_CTRL_MASK 0x06000000L |
27668 | #define UTCL1_CTRL_0__UTCL1_REDUCE_CC_SIZE_MASK 0x18000000L |
27669 | #define UTCL1_CTRL_0__RESERVED_1_MASK 0x20000000L |
27670 | #define UTCL1_CTRL_0__MH_SPARE0_MASK 0x40000000L |
27671 | #define UTCL1_CTRL_0__RESERVED_2_MASK 0x80000000L |
27672 | //UTCL1_UTCL0_INVREQ_DISABLE |
27673 | #define UTCL1_UTCL0_INVREQ_DISABLE__UTCL1_UTCL0_INVREQ_DISABLE__SHIFT 0x0 |
27674 | #define UTCL1_UTCL0_INVREQ_DISABLE__UTCL1_UTCL0_INVREQ_DISABLE_MASK 0xFFFFFFFFL |
27675 | //UTCL1_CTRL_2 |
27676 | #define UTCL1_CTRL_2__UTCL1_RNG_TO_VMID_INV_OVRD__SHIFT 0x0 |
27677 | #define UTCL1_CTRL_2__UTCL1_PMM_INTERRUPT_CREDITS_OVERRIDE__SHIFT 0x4 |
27678 | #define UTCL1_CTRL_2__UTCL1_CACHE_WRITE_PERM__SHIFT 0xa |
27679 | #define UTCL1_CTRL_2__UTCL1_PAGE_OVRD_DISABLE__SHIFT 0xb |
27680 | #define UTCL1_CTRL_2__UTCL1_SPARE0__SHIFT 0xc |
27681 | #define UTCL1_CTRL_2__UTCL1_SPARE1__SHIFT 0xd |
27682 | #define UTCL1_CTRL_2__RESERVED__SHIFT 0xe |
27683 | #define UTCL1_CTRL_2__UTCL1_RNG_TO_VMID_INV_OVRD_MASK 0x0000000FL |
27684 | #define UTCL1_CTRL_2__UTCL1_PMM_INTERRUPT_CREDITS_OVERRIDE_MASK 0x000003F0L |
27685 | #define UTCL1_CTRL_2__UTCL1_CACHE_WRITE_PERM_MASK 0x00000400L |
27686 | #define UTCL1_CTRL_2__UTCL1_PAGE_OVRD_DISABLE_MASK 0x00000800L |
27687 | #define UTCL1_CTRL_2__UTCL1_SPARE0_MASK 0x00001000L |
27688 | #define UTCL1_CTRL_2__UTCL1_SPARE1_MASK 0x00002000L |
27689 | #define UTCL1_CTRL_2__RESERVED_MASK 0xFFFFC000L |
27690 | //UTCL1_FIFO_SIZING |
27691 | #define UTCL1_FIFO_SIZING__UTCL1_UTCL2_INVACK_CDC_FIFO_THRESH__SHIFT 0x0 |
27692 | #define UTCL1_FIFO_SIZING__UTCL1_GENERAL_SIZING_CTRL_LOW__SHIFT 0x3 |
27693 | #define UTCL1_FIFO_SIZING__UTCL1_GENERAL_SIZING_CTRL_HIGH__SHIFT 0x10 |
27694 | #define UTCL1_FIFO_SIZING__UTCL1_UTCL2_INVACK_CDC_FIFO_THRESH_MASK 0x00000007L |
27695 | #define UTCL1_FIFO_SIZING__UTCL1_GENERAL_SIZING_CTRL_LOW_MASK 0x0000FFF8L |
27696 | #define UTCL1_FIFO_SIZING__UTCL1_GENERAL_SIZING_CTRL_HIGH_MASK 0xFFFF0000L |
27697 | //GCRD_SA0_TARGETS_DISABLE |
27698 | #define GCRD_SA0_TARGETS_DISABLE__GCRD_SA0_TARGETS_DISABLE__SHIFT 0x0 |
27699 | #define GCRD_SA0_TARGETS_DISABLE__GCRD_SA0_TARGETS_DISABLE_MASK 0x0007FFFFL |
27700 | //GCRD_SA1_TARGETS_DISABLE |
27701 | #define GCRD_SA1_TARGETS_DISABLE__GCRD_SA1_TARGETS_DISABLE__SHIFT 0x0 |
27702 | #define GCRD_SA1_TARGETS_DISABLE__GCRD_SA1_TARGETS_DISABLE_MASK 0x0007FFFFL |
27703 | //GCRD_CREDIT_SAFE |
27704 | #define GCRD_CREDIT_SAFE__GCRD_CHAIN_CREDIT_SAFE_REG__SHIFT 0x0 |
27705 | #define GCRD_CREDIT_SAFE__GCRD_TARGET_CREDIT_SAFE_REG__SHIFT 0x4 |
27706 | #define GCRD_CREDIT_SAFE__GCRD_CHAIN_CREDIT_SAFE_REG_MASK 0x00000007L |
27707 | #define GCRD_CREDIT_SAFE__GCRD_TARGET_CREDIT_SAFE_REG_MASK 0x00000070L |
27708 | |
27709 | |
27710 | // addressBlock: gc_pfonly_pmmdec |
27711 | //GCR_GENERAL_CNTL |
27712 | #define GCR_GENERAL_CNTL__FORCE_4K_L2_RESP__SHIFT 0x0 |
27713 | #define GCR_GENERAL_CNTL__REDUCE_HALF_MAIN_WQ__SHIFT 0x1 |
27714 | #define GCR_GENERAL_CNTL__REDUCE_HALF_PHY_WQ__SHIFT 0x2 |
27715 | #define GCR_GENERAL_CNTL__FORCE_INV_ALL__SHIFT 0x3 |
27716 | #define GCR_GENERAL_CNTL__HI_PRIORITY_CNTL__SHIFT 0x4 |
27717 | #define GCR_GENERAL_CNTL__HI_PRIORITY_DISABLE__SHIFT 0x6 |
27718 | #define GCR_GENERAL_CNTL__BIG_PAGE_FILTER_DISABLE__SHIFT 0x7 |
27719 | #define GCR_GENERAL_CNTL__PERF_CNTR_ENABLE__SHIFT 0x8 |
27720 | #define GCR_GENERAL_CNTL__FORCE_SINGLE_WQ__SHIFT 0x9 |
27721 | #define GCR_GENERAL_CNTL__UTCL2_REQ_PERM__SHIFT 0xa |
27722 | #define GCR_GENERAL_CNTL__TARGET_MGCG_CLKEN_DIS__SHIFT 0xd |
27723 | #define GCR_GENERAL_CNTL__MIXED_RANGE_MODE_DIS__SHIFT 0xe |
27724 | #define GCR_GENERAL_CNTL__ENABLE_16K_UTCL2_REQ__SHIFT 0xf |
27725 | #define GCR_GENERAL_CNTL__DISABLE_FGCG__SHIFT 0x10 |
27726 | #define GCR_GENERAL_CNTL__CLIENT_ID__SHIFT 0x14 |
27727 | #define GCR_GENERAL_CNTL__FORCE_4K_L2_RESP_MASK 0x00000001L |
27728 | #define GCR_GENERAL_CNTL__REDUCE_HALF_MAIN_WQ_MASK 0x00000002L |
27729 | #define GCR_GENERAL_CNTL__REDUCE_HALF_PHY_WQ_MASK 0x00000004L |
27730 | #define GCR_GENERAL_CNTL__FORCE_INV_ALL_MASK 0x00000008L |
27731 | #define GCR_GENERAL_CNTL__HI_PRIORITY_CNTL_MASK 0x00000030L |
27732 | #define GCR_GENERAL_CNTL__HI_PRIORITY_DISABLE_MASK 0x00000040L |
27733 | #define GCR_GENERAL_CNTL__BIG_PAGE_FILTER_DISABLE_MASK 0x00000080L |
27734 | #define GCR_GENERAL_CNTL__PERF_CNTR_ENABLE_MASK 0x00000100L |
27735 | #define GCR_GENERAL_CNTL__FORCE_SINGLE_WQ_MASK 0x00000200L |
27736 | #define GCR_GENERAL_CNTL__UTCL2_REQ_PERM_MASK 0x00001C00L |
27737 | #define GCR_GENERAL_CNTL__TARGET_MGCG_CLKEN_DIS_MASK 0x00002000L |
27738 | #define GCR_GENERAL_CNTL__MIXED_RANGE_MODE_DIS_MASK 0x00004000L |
27739 | #define GCR_GENERAL_CNTL__ENABLE_16K_UTCL2_REQ_MASK 0x00008000L |
27740 | #define GCR_GENERAL_CNTL__DISABLE_FGCG_MASK 0x00010000L |
27741 | #define GCR_GENERAL_CNTL__CLIENT_ID_MASK 0x1FF00000L |
27742 | //GCR_TARGET_DISABLE |
27743 | #define GCR_TARGET_DISABLE__DISABLE_SE0_PHY__SHIFT 0x0 |
27744 | #define GCR_TARGET_DISABLE__DISABLE_SE0_VIRT__SHIFT 0x1 |
27745 | #define GCR_TARGET_DISABLE__DISABLE_SE1_PHY__SHIFT 0x2 |
27746 | #define GCR_TARGET_DISABLE__DISABLE_SE1_VIRT__SHIFT 0x3 |
27747 | #define GCR_TARGET_DISABLE__DISABLE_SE2_PHY__SHIFT 0x4 |
27748 | #define GCR_TARGET_DISABLE__DISABLE_SE2_VIRT__SHIFT 0x5 |
27749 | #define GCR_TARGET_DISABLE__DISABLE_GL2A0_PHY__SHIFT 0x6 |
27750 | #define GCR_TARGET_DISABLE__DISABLE_GL2A1_PHY__SHIFT 0x7 |
27751 | #define GCR_TARGET_DISABLE__DISABLE_GL2A2_PHY__SHIFT 0x8 |
27752 | #define GCR_TARGET_DISABLE__DISABLE_GL2A3_PHY__SHIFT 0x9 |
27753 | #define GCR_TARGET_DISABLE__DISABLE_SE3_PHY__SHIFT 0xa |
27754 | #define GCR_TARGET_DISABLE__DISABLE_SE3_VIRT__SHIFT 0xb |
27755 | #define GCR_TARGET_DISABLE__DISABLE_SE4_PHY__SHIFT 0xc |
27756 | #define GCR_TARGET_DISABLE__DISABLE_SE4_VIRT__SHIFT 0xd |
27757 | #define GCR_TARGET_DISABLE__DISABLE_SE5_PHY__SHIFT 0xe |
27758 | #define GCR_TARGET_DISABLE__DISABLE_SE5_VIRT__SHIFT 0xf |
27759 | #define GCR_TARGET_DISABLE__SE0_INACTIVE_STATUS__SHIFT 0x10 |
27760 | #define GCR_TARGET_DISABLE__SE1_INACTIVE_STATUS__SHIFT 0x11 |
27761 | #define GCR_TARGET_DISABLE__SE2_INACTIVE_STATUS__SHIFT 0x12 |
27762 | #define GCR_TARGET_DISABLE__SE3_INACTIVE_STATUS__SHIFT 0x13 |
27763 | #define GCR_TARGET_DISABLE__SE4_INACTIVE_STATUS__SHIFT 0x14 |
27764 | #define GCR_TARGET_DISABLE__SE5_INACTIVE_STATUS__SHIFT 0x15 |
27765 | #define GCR_TARGET_DISABLE__DISABLE_SE0_PHY_MASK 0x00000001L |
27766 | #define GCR_TARGET_DISABLE__DISABLE_SE0_VIRT_MASK 0x00000002L |
27767 | #define GCR_TARGET_DISABLE__DISABLE_SE1_PHY_MASK 0x00000004L |
27768 | #define GCR_TARGET_DISABLE__DISABLE_SE1_VIRT_MASK 0x00000008L |
27769 | #define GCR_TARGET_DISABLE__DISABLE_SE2_PHY_MASK 0x00000010L |
27770 | #define GCR_TARGET_DISABLE__DISABLE_SE2_VIRT_MASK 0x00000020L |
27771 | #define GCR_TARGET_DISABLE__DISABLE_GL2A0_PHY_MASK 0x00000040L |
27772 | #define GCR_TARGET_DISABLE__DISABLE_GL2A1_PHY_MASK 0x00000080L |
27773 | #define GCR_TARGET_DISABLE__DISABLE_GL2A2_PHY_MASK 0x00000100L |
27774 | #define GCR_TARGET_DISABLE__DISABLE_GL2A3_PHY_MASK 0x00000200L |
27775 | #define GCR_TARGET_DISABLE__DISABLE_SE3_PHY_MASK 0x00000400L |
27776 | #define GCR_TARGET_DISABLE__DISABLE_SE3_VIRT_MASK 0x00000800L |
27777 | #define GCR_TARGET_DISABLE__DISABLE_SE4_PHY_MASK 0x00001000L |
27778 | #define GCR_TARGET_DISABLE__DISABLE_SE4_VIRT_MASK 0x00002000L |
27779 | #define GCR_TARGET_DISABLE__DISABLE_SE5_PHY_MASK 0x00004000L |
27780 | #define GCR_TARGET_DISABLE__DISABLE_SE5_VIRT_MASK 0x00008000L |
27781 | #define GCR_TARGET_DISABLE__SE0_INACTIVE_STATUS_MASK 0x00010000L |
27782 | #define GCR_TARGET_DISABLE__SE1_INACTIVE_STATUS_MASK 0x00020000L |
27783 | #define GCR_TARGET_DISABLE__SE2_INACTIVE_STATUS_MASK 0x00040000L |
27784 | #define GCR_TARGET_DISABLE__SE3_INACTIVE_STATUS_MASK 0x00080000L |
27785 | #define GCR_TARGET_DISABLE__SE4_INACTIVE_STATUS_MASK 0x00100000L |
27786 | #define GCR_TARGET_DISABLE__SE5_INACTIVE_STATUS_MASK 0x00200000L |
27787 | //GCR_CMD_STATUS |
27788 | #define GCR_CMD_STATUS__GCR_CONTROL__SHIFT 0x0 |
27789 | #define GCR_CMD_STATUS__GCR_SRC__SHIFT 0x13 |
27790 | #define GCR_CMD_STATUS__GCR_TLB_SHOOTDOWN__SHIFT 0x17 |
27791 | #define GCR_CMD_STATUS__GCR_TLB_SHOOTDOWN_VMID__SHIFT 0x18 |
27792 | #define GCR_CMD_STATUS__UTCL2_NACK_STATUS__SHIFT 0x1c |
27793 | #define GCR_CMD_STATUS__GCR_SEQ_OP_ERROR__SHIFT 0x1e |
27794 | #define GCR_CMD_STATUS__UTCL2_NACK_ERROR__SHIFT 0x1f |
27795 | #define GCR_CMD_STATUS__GCR_CONTROL_MASK 0x0007FFFFL |
27796 | #define GCR_CMD_STATUS__GCR_SRC_MASK 0x00380000L |
27797 | #define GCR_CMD_STATUS__GCR_TLB_SHOOTDOWN_MASK 0x00800000L |
27798 | #define GCR_CMD_STATUS__GCR_TLB_SHOOTDOWN_VMID_MASK 0x0F000000L |
27799 | #define GCR_CMD_STATUS__UTCL2_NACK_STATUS_MASK 0x30000000L |
27800 | #define GCR_CMD_STATUS__GCR_SEQ_OP_ERROR_MASK 0x40000000L |
27801 | #define GCR_CMD_STATUS__UTCL2_NACK_ERROR_MASK 0x80000000L |
27802 | //GCR_SPARE |
27803 | #define GCR_SPARE__SPARE_BIT_1__SHIFT 0x1 |
27804 | #define GCR_SPARE__SPARE_BIT_2__SHIFT 0x2 |
27805 | #define GCR_SPARE__SPARE_BIT_3__SHIFT 0x3 |
27806 | #define GCR_SPARE__SPARE_BIT_4__SHIFT 0x4 |
27807 | #define GCR_SPARE__SPARE_BIT_5__SHIFT 0x5 |
27808 | #define GCR_SPARE__SPARE_BIT_6__SHIFT 0x6 |
27809 | #define GCR_SPARE__SPARE_BIT_7__SHIFT 0x7 |
27810 | #define GCR_SPARE__UTCL2_REQ_CREDIT__SHIFT 0x8 |
27811 | #define GCR_SPARE__GCRD_GL2A_REQ_CREDIT__SHIFT 0x10 |
27812 | #define GCR_SPARE__GCRD_SE_REQ_CREDIT__SHIFT 0x14 |
27813 | #define GCR_SPARE__SPARE_BIT_31_24__SHIFT 0x18 |
27814 | #define GCR_SPARE__SPARE_BIT_1_MASK 0x00000002L |
27815 | #define GCR_SPARE__SPARE_BIT_2_MASK 0x00000004L |
27816 | #define GCR_SPARE__SPARE_BIT_3_MASK 0x00000008L |
27817 | #define GCR_SPARE__SPARE_BIT_4_MASK 0x00000010L |
27818 | #define GCR_SPARE__SPARE_BIT_5_MASK 0x00000020L |
27819 | #define GCR_SPARE__SPARE_BIT_6_MASK 0x00000040L |
27820 | #define GCR_SPARE__SPARE_BIT_7_MASK 0x00000080L |
27821 | #define GCR_SPARE__UTCL2_REQ_CREDIT_MASK 0x0000FF00L |
27822 | #define GCR_SPARE__GCRD_GL2A_REQ_CREDIT_MASK 0x000F0000L |
27823 | #define GCR_SPARE__GCRD_SE_REQ_CREDIT_MASK 0x00F00000L |
27824 | #define GCR_SPARE__SPARE_BIT_31_24_MASK 0xFF000000L |
27825 | //PMM_CNTL2 |
27826 | #define PMM_CNTL2__GCEA_MAM_DISABLE__SHIFT 0x0 |
27827 | #define PMM_CNTL2__ABIT_FORCE_FLUSH_OVERRIDE__SHIFT 0x18 |
27828 | #define PMM_CNTL2__ABIT_TIMER_FLUSH_OVERRIDE__SHIFT 0x19 |
27829 | #define PMM_CNTL2__PMM_IH_INTERRUPT_CREDITS_OVERRIDE__SHIFT 0x1a |
27830 | #define PMM_CNTL2__ABIT_INTR_ON_FLUSH_DONE__SHIFT 0x1e |
27831 | #define PMM_CNTL2__RESERVED__SHIFT 0x1f |
27832 | #define PMM_CNTL2__GCEA_MAM_DISABLE_MASK 0x00FFFFFFL |
27833 | #define PMM_CNTL2__ABIT_FORCE_FLUSH_OVERRIDE_MASK 0x01000000L |
27834 | #define PMM_CNTL2__ABIT_TIMER_FLUSH_OVERRIDE_MASK 0x02000000L |
27835 | #define PMM_CNTL2__PMM_IH_INTERRUPT_CREDITS_OVERRIDE_MASK 0x3C000000L |
27836 | #define PMM_CNTL2__ABIT_INTR_ON_FLUSH_DONE_MASK 0x40000000L |
27837 | #define PMM_CNTL2__RESERVED_MASK 0x80000000L |
27838 | |
27839 | |
27840 | // addressBlock: gc_pfonly_gccacdec |
27841 | //GC_CAC_CTRL_1 |
27842 | #define GC_CAC_CTRL_1__CAC_WINDOW__SHIFT 0x0 |
27843 | #define GC_CAC_CTRL_1__TDP_WINDOW__SHIFT 0x8 |
27844 | #define GC_CAC_CTRL_1__CAC_WINDOW_MASK 0x000000FFL |
27845 | #define GC_CAC_CTRL_1__TDP_WINDOW_MASK 0xFFFFFF00L |
27846 | //GC_CAC_CTRL_2 |
27847 | #define GC_CAC_CTRL_2__CAC_ENABLE__SHIFT 0x0 |
27848 | #define GC_CAC_CTRL_2__GC_LCAC_ENABLE__SHIFT 0x1 |
27849 | #define GC_CAC_CTRL_2__GC_CAC_INDEX_AUTO_INCR_EN__SHIFT 0x2 |
27850 | #define GC_CAC_CTRL_2__TOGGLE_EN__SHIFT 0x3 |
27851 | #define GC_CAC_CTRL_2__INTR_EN__SHIFT 0x4 |
27852 | #define GC_CAC_CTRL_2__CAC_COUNTER_SNAP_SEL__SHIFT 0x5 |
27853 | #define GC_CAC_CTRL_2__SE_AGGR_ACC_EN__SHIFT 0x6 |
27854 | #define GC_CAC_CTRL_2__GC_AGGR_ACC_EN__SHIFT 0xe |
27855 | #define GC_CAC_CTRL_2__CAC_ENABLE_MASK 0x00000001L |
27856 | #define GC_CAC_CTRL_2__GC_LCAC_ENABLE_MASK 0x00000002L |
27857 | #define GC_CAC_CTRL_2__GC_CAC_INDEX_AUTO_INCR_EN_MASK 0x00000004L |
27858 | #define GC_CAC_CTRL_2__TOGGLE_EN_MASK 0x00000008L |
27859 | #define GC_CAC_CTRL_2__INTR_EN_MASK 0x00000010L |
27860 | #define GC_CAC_CTRL_2__CAC_COUNTER_SNAP_SEL_MASK 0x00000020L |
27861 | #define GC_CAC_CTRL_2__SE_AGGR_ACC_EN_MASK 0x00003FC0L |
27862 | #define GC_CAC_CTRL_2__GC_AGGR_ACC_EN_MASK 0x00004000L |
27863 | //GC_CAC_AGGR_LOWER |
27864 | #define GC_CAC_AGGR_LOWER__GC_AGGR_31_0__SHIFT 0x0 |
27865 | #define GC_CAC_AGGR_LOWER__GC_AGGR_31_0_MASK 0xFFFFFFFFL |
27866 | //GC_CAC_AGGR_UPPER |
27867 | #define GC_CAC_AGGR_UPPER__GC_AGGR_63_32__SHIFT 0x0 |
27868 | #define GC_CAC_AGGR_UPPER__GC_AGGR_63_32_MASK 0xFFFFFFFFL |
27869 | //SE0_CAC_AGGR_LOWER |
27870 | #define SE0_CAC_AGGR_LOWER__SE0_AGGR_31_0__SHIFT 0x0 |
27871 | #define SE0_CAC_AGGR_LOWER__SE0_AGGR_31_0_MASK 0xFFFFFFFFL |
27872 | //SE0_CAC_AGGR_UPPER |
27873 | #define SE0_CAC_AGGR_UPPER__SE0_AGGR_63_32__SHIFT 0x0 |
27874 | #define SE0_CAC_AGGR_UPPER__SE0_AGGR_63_32_MASK 0xFFFFFFFFL |
27875 | //SE1_CAC_AGGR_LOWER |
27876 | #define SE1_CAC_AGGR_LOWER__SE1_AGGR_31_0__SHIFT 0x0 |
27877 | #define SE1_CAC_AGGR_LOWER__SE1_AGGR_31_0_MASK 0xFFFFFFFFL |
27878 | //SE1_CAC_AGGR_UPPER |
27879 | #define SE1_CAC_AGGR_UPPER__SE1_AGGR_63_32__SHIFT 0x0 |
27880 | #define SE1_CAC_AGGR_UPPER__SE1_AGGR_63_32_MASK 0xFFFFFFFFL |
27881 | //SE2_CAC_AGGR_LOWER |
27882 | #define SE2_CAC_AGGR_LOWER__SE2_AGGR_31_0__SHIFT 0x0 |
27883 | #define SE2_CAC_AGGR_LOWER__SE2_AGGR_31_0_MASK 0xFFFFFFFFL |
27884 | //SE2_CAC_AGGR_UPPER |
27885 | #define SE2_CAC_AGGR_UPPER__SE2_AGGR_63_32__SHIFT 0x0 |
27886 | #define SE2_CAC_AGGR_UPPER__SE2_AGGR_63_32_MASK 0xFFFFFFFFL |
27887 | //GC_CAC_AGGR_GFXCLK_CYCLE |
27888 | #define GC_CAC_AGGR_GFXCLK_CYCLE__GC_AGGR_GFXCLK_CYCLE__SHIFT 0x0 |
27889 | #define GC_CAC_AGGR_GFXCLK_CYCLE__GC_AGGR_GFXCLK_CYCLE_MASK 0xFFFFFFFFL |
27890 | //SE0_CAC_AGGR_GFXCLK_CYCLE |
27891 | #define SE0_CAC_AGGR_GFXCLK_CYCLE__SE0_AGGR_GFXCLK_CYCLE__SHIFT 0x0 |
27892 | #define SE0_CAC_AGGR_GFXCLK_CYCLE__SE0_AGGR_GFXCLK_CYCLE_MASK 0xFFFFFFFFL |
27893 | //SE1_CAC_AGGR_GFXCLK_CYCLE |
27894 | #define SE1_CAC_AGGR_GFXCLK_CYCLE__SE1_AGGR_GFXCLK_CYCLE__SHIFT 0x0 |
27895 | #define SE1_CAC_AGGR_GFXCLK_CYCLE__SE1_AGGR_GFXCLK_CYCLE_MASK 0xFFFFFFFFL |
27896 | //SE2_CAC_AGGR_GFXCLK_CYCLE |
27897 | #define SE2_CAC_AGGR_GFXCLK_CYCLE__SE2_AGGR_GFXCLK_CYCLE__SHIFT 0x0 |
27898 | #define SE2_CAC_AGGR_GFXCLK_CYCLE__SE2_AGGR_GFXCLK_CYCLE_MASK 0xFFFFFFFFL |
27899 | //GC_EDC_CTRL |
27900 | #define GC_EDC_CTRL__EDC_EN__SHIFT 0x0 |
27901 | #define GC_EDC_CTRL__EDC_SW_RST__SHIFT 0x1 |
27902 | #define GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2 |
27903 | #define GC_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3 |
27904 | #define GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 |
27905 | #define GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0xa |
27906 | #define GC_EDC_CTRL__EDC_THROTTLE_PATTERN_BIT_NUMS__SHIFT 0xb |
27907 | #define GC_EDC_CTRL__EDC_LEVEL_SEL__SHIFT 0xf |
27908 | #define GC_EDC_CTRL__EDC_ALGORITHM_MODE__SHIFT 0x10 |
27909 | #define GC_EDC_CTRL__EDC_AVGDIV__SHIFT 0x11 |
27910 | #define GC_EDC_CTRL__PSM_THROTTLE_SRC_SEL__SHIFT 0x15 |
27911 | #define GC_EDC_CTRL__THROTTLE_SRC0_MASK__SHIFT 0x18 |
27912 | #define GC_EDC_CTRL__THROTTLE_SRC1_MASK__SHIFT 0x19 |
27913 | #define GC_EDC_CTRL__THROTTLE_SRC2_MASK__SHIFT 0x1a |
27914 | #define GC_EDC_CTRL__THROTTLE_SRC3_MASK__SHIFT 0x1b |
27915 | #define GC_EDC_CTRL__EDC_CREDIT_SHIFT_BIT_NUMS__SHIFT 0x1c |
27916 | #define GC_EDC_CTRL__EDC_EN_MASK 0x00000001L |
27917 | #define GC_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L |
27918 | #define GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L |
27919 | #define GC_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L |
27920 | #define GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000003F0L |
27921 | #define GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00000400L |
27922 | #define GC_EDC_CTRL__EDC_THROTTLE_PATTERN_BIT_NUMS_MASK 0x00007800L |
27923 | #define GC_EDC_CTRL__EDC_LEVEL_SEL_MASK 0x00008000L |
27924 | #define GC_EDC_CTRL__EDC_ALGORITHM_MODE_MASK 0x00010000L |
27925 | #define GC_EDC_CTRL__EDC_AVGDIV_MASK 0x001E0000L |
27926 | #define GC_EDC_CTRL__PSM_THROTTLE_SRC_SEL_MASK 0x00E00000L |
27927 | #define GC_EDC_CTRL__THROTTLE_SRC0_MASK_MASK 0x01000000L |
27928 | #define GC_EDC_CTRL__THROTTLE_SRC1_MASK_MASK 0x02000000L |
27929 | #define GC_EDC_CTRL__THROTTLE_SRC2_MASK_MASK 0x04000000L |
27930 | #define GC_EDC_CTRL__THROTTLE_SRC3_MASK_MASK 0x08000000L |
27931 | #define GC_EDC_CTRL__EDC_CREDIT_SHIFT_BIT_NUMS_MASK 0xF0000000L |
27932 | //GC_EDC_THRESHOLD |
27933 | #define GC_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x0 |
27934 | #define GC_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xFFFFFFFFL |
27935 | //GC_EDC_STRETCH_CTRL |
27936 | #define GC_EDC_STRETCH_CTRL__EDC_STRETCH_EN__SHIFT 0x0 |
27937 | #define GC_EDC_STRETCH_CTRL__EDC_STRETCH_DELAY__SHIFT 0x1 |
27938 | #define GC_EDC_STRETCH_CTRL__EDC_UNSTRETCH_DELAY__SHIFT 0xa |
27939 | #define GC_EDC_STRETCH_CTRL__EDC_STRETCH_EN_MASK 0x00000001L |
27940 | #define GC_EDC_STRETCH_CTRL__EDC_STRETCH_DELAY_MASK 0x000003FEL |
27941 | #define GC_EDC_STRETCH_CTRL__EDC_UNSTRETCH_DELAY_MASK 0x0007FC00L |
27942 | //GC_EDC_STRETCH_THRESHOLD |
27943 | #define GC_EDC_STRETCH_THRESHOLD__EDC_STRETCH_THRESHOLD__SHIFT 0x0 |
27944 | #define GC_EDC_STRETCH_THRESHOLD__EDC_STRETCH_THRESHOLD_MASK 0xFFFFFFFFL |
27945 | //EDC_HYSTERESIS_CNTL |
27946 | #define EDC_HYSTERESIS_CNTL__MAX_HYSTERESIS__SHIFT 0x0 |
27947 | #define EDC_HYSTERESIS_CNTL__EDC_AGGR_TIMER__SHIFT 0x8 |
27948 | #define EDC_HYSTERESIS_CNTL__PATTERN_EXTEND_EN__SHIFT 0x10 |
27949 | #define EDC_HYSTERESIS_CNTL__PATTERN_EXTEND_MODE__SHIFT 0x11 |
27950 | #define EDC_HYSTERESIS_CNTL__EDC_AGGR_MODE__SHIFT 0x14 |
27951 | #define EDC_HYSTERESIS_CNTL__MAX_HYSTERESIS_MASK 0x000000FFL |
27952 | #define EDC_HYSTERESIS_CNTL__EDC_AGGR_TIMER_MASK 0x0000FF00L |
27953 | #define EDC_HYSTERESIS_CNTL__PATTERN_EXTEND_EN_MASK 0x00010000L |
27954 | #define EDC_HYSTERESIS_CNTL__PATTERN_EXTEND_MODE_MASK 0x000E0000L |
27955 | #define EDC_HYSTERESIS_CNTL__EDC_AGGR_MODE_MASK 0x00100000L |
27956 | //GC_THROTTLE_CTRL |
27957 | #define GC_THROTTLE_CTRL__THROTTLE_CTRL_SW_RST__SHIFT 0x0 |
27958 | #define GC_THROTTLE_CTRL__GC_EDC_STALL_EN__SHIFT 0x1 |
27959 | #define GC_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT 0x2 |
27960 | #define GC_THROTTLE_CTRL__PWRBRK_POLARITY_CNTL__SHIFT 0x3 |
27961 | #define GC_THROTTLE_CTRL__PCC_STALL_EN__SHIFT 0x4 |
27962 | #define GC_THROTTLE_CTRL__PATTERN_MODE__SHIFT 0x5 |
27963 | #define GC_THROTTLE_CTRL__GC_EDC_ONLY_MODE__SHIFT 0x6 |
27964 | #define GC_THROTTLE_CTRL__GC_EDC_OVERRIDE__SHIFT 0x7 |
27965 | #define GC_THROTTLE_CTRL__PCC_OVERRIDE__SHIFT 0x8 |
27966 | #define GC_THROTTLE_CTRL__PWRBRK_OVERRIDE__SHIFT 0x9 |
27967 | #define GC_THROTTLE_CTRL__GC_EDC_PERF_COUNTER_EN__SHIFT 0xa |
27968 | #define GC_THROTTLE_CTRL__PCC_PERF_COUNTER_EN__SHIFT 0xb |
27969 | #define GC_THROTTLE_CTRL__PWRBRK_PERF_COUNTER_EN__SHIFT 0xc |
27970 | #define GC_THROTTLE_CTRL__RELEASE_STEP_INTERVAL__SHIFT 0xd |
27971 | #define GC_THROTTLE_CTRL__FIXED_PATTERN_PERF_COUNTER_EN__SHIFT 0x17 |
27972 | #define GC_THROTTLE_CTRL__FIXED_PATTERN_LOG_INDEX__SHIFT 0x18 |
27973 | #define GC_THROTTLE_CTRL__LUT_HW_UPDATE__SHIFT 0x1d |
27974 | #define GC_THROTTLE_CTRL__THROTTLE_CTRL_CLK_EN_OVERRIDE__SHIFT 0x1e |
27975 | #define GC_THROTTLE_CTRL__PCC_POLARITY_CNTL__SHIFT 0x1f |
27976 | #define GC_THROTTLE_CTRL__THROTTLE_CTRL_SW_RST_MASK 0x00000001L |
27977 | #define GC_THROTTLE_CTRL__GC_EDC_STALL_EN_MASK 0x00000002L |
27978 | #define GC_THROTTLE_CTRL__PWRBRK_STALL_EN_MASK 0x00000004L |
27979 | #define GC_THROTTLE_CTRL__PWRBRK_POLARITY_CNTL_MASK 0x00000008L |
27980 | #define GC_THROTTLE_CTRL__PCC_STALL_EN_MASK 0x00000010L |
27981 | #define GC_THROTTLE_CTRL__PATTERN_MODE_MASK 0x00000020L |
27982 | #define GC_THROTTLE_CTRL__GC_EDC_ONLY_MODE_MASK 0x00000040L |
27983 | #define GC_THROTTLE_CTRL__GC_EDC_OVERRIDE_MASK 0x00000080L |
27984 | #define GC_THROTTLE_CTRL__PCC_OVERRIDE_MASK 0x00000100L |
27985 | #define GC_THROTTLE_CTRL__PWRBRK_OVERRIDE_MASK 0x00000200L |
27986 | #define GC_THROTTLE_CTRL__GC_EDC_PERF_COUNTER_EN_MASK 0x00000400L |
27987 | #define GC_THROTTLE_CTRL__PCC_PERF_COUNTER_EN_MASK 0x00000800L |
27988 | #define GC_THROTTLE_CTRL__PWRBRK_PERF_COUNTER_EN_MASK 0x00001000L |
27989 | #define GC_THROTTLE_CTRL__RELEASE_STEP_INTERVAL_MASK 0x007FE000L |
27990 | #define GC_THROTTLE_CTRL__FIXED_PATTERN_PERF_COUNTER_EN_MASK 0x00800000L |
27991 | #define GC_THROTTLE_CTRL__FIXED_PATTERN_LOG_INDEX_MASK 0x1F000000L |
27992 | #define GC_THROTTLE_CTRL__LUT_HW_UPDATE_MASK 0x20000000L |
27993 | #define GC_THROTTLE_CTRL__THROTTLE_CTRL_CLK_EN_OVERRIDE_MASK 0x40000000L |
27994 | #define GC_THROTTLE_CTRL__PCC_POLARITY_CNTL_MASK 0x80000000L |
27995 | //GC_THROTTLE_CTRL1 |
27996 | #define GC_THROTTLE_CTRL1__PCC_FP_PROGRAM_STEP_EN__SHIFT 0x0 |
27997 | #define GC_THROTTLE_CTRL1__PCC_PROGRAM_MIN_STEP__SHIFT 0x1 |
27998 | #define GC_THROTTLE_CTRL1__PCC_PROGRAM_MAX_STEP__SHIFT 0x5 |
27999 | #define GC_THROTTLE_CTRL1__PCC_PROGRAM_UPWARDS_STEP_SIZE__SHIFT 0xa |
28000 | #define GC_THROTTLE_CTRL1__PWRBRK_FP_PROGRAM_STEP_EN__SHIFT 0xd |
28001 | #define GC_THROTTLE_CTRL1__PWRBRK_PROGRAM_MIN_STEP__SHIFT 0xe |
28002 | #define GC_THROTTLE_CTRL1__PWRBRK_PROGRAM_MAX_STEP__SHIFT 0x12 |
28003 | #define GC_THROTTLE_CTRL1__PWRBRK_PROGRAM_UPWARDS_STEP_SIZE__SHIFT 0x17 |
28004 | #define GC_THROTTLE_CTRL1__FIXED_PATTERN_SELECT__SHIFT 0x1a |
28005 | #define GC_THROTTLE_CTRL1__GC_EDC_STRETCH_PERF_COUNTER_EN__SHIFT 0x1e |
28006 | #define GC_THROTTLE_CTRL1__GC_EDC_UNSTRETCH_PERF_COUNTER_EN__SHIFT 0x1f |
28007 | #define GC_THROTTLE_CTRL1__PCC_FP_PROGRAM_STEP_EN_MASK 0x00000001L |
28008 | #define GC_THROTTLE_CTRL1__PCC_PROGRAM_MIN_STEP_MASK 0x0000001EL |
28009 | #define GC_THROTTLE_CTRL1__PCC_PROGRAM_MAX_STEP_MASK 0x000003E0L |
28010 | #define GC_THROTTLE_CTRL1__PCC_PROGRAM_UPWARDS_STEP_SIZE_MASK 0x00001C00L |
28011 | #define GC_THROTTLE_CTRL1__PWRBRK_FP_PROGRAM_STEP_EN_MASK 0x00002000L |
28012 | #define GC_THROTTLE_CTRL1__PWRBRK_PROGRAM_MIN_STEP_MASK 0x0003C000L |
28013 | #define GC_THROTTLE_CTRL1__PWRBRK_PROGRAM_MAX_STEP_MASK 0x007C0000L |
28014 | #define GC_THROTTLE_CTRL1__PWRBRK_PROGRAM_UPWARDS_STEP_SIZE_MASK 0x03800000L |
28015 | #define GC_THROTTLE_CTRL1__FIXED_PATTERN_SELECT_MASK 0x0C000000L |
28016 | #define GC_THROTTLE_CTRL1__GC_EDC_STRETCH_PERF_COUNTER_EN_MASK 0x40000000L |
28017 | #define GC_THROTTLE_CTRL1__GC_EDC_UNSTRETCH_PERF_COUNTER_EN_MASK 0x80000000L |
28018 | //PCC_STALL_PATTERN_CTRL |
28019 | #define PCC_STALL_PATTERN_CTRL__PCC_STEP_INTERVAL__SHIFT 0x0 |
28020 | #define PCC_STALL_PATTERN_CTRL__PCC_BEGIN_STEP__SHIFT 0xa |
28021 | #define PCC_STALL_PATTERN_CTRL__PCC_END_STEP__SHIFT 0xf |
28022 | #define PCC_STALL_PATTERN_CTRL__PCC_THROTTLE_PATTERN_BIT_NUMS__SHIFT 0x14 |
28023 | #define PCC_STALL_PATTERN_CTRL__PCC_INST_THROT_INCR__SHIFT 0x18 |
28024 | #define PCC_STALL_PATTERN_CTRL__PCC_INST_THROT_DECR__SHIFT 0x19 |
28025 | #define PCC_STALL_PATTERN_CTRL__PCC_DITHER_MODE__SHIFT 0x1a |
28026 | #define PCC_STALL_PATTERN_CTRL__PCC_STEP_INTERVAL_MASK 0x000003FFL |
28027 | #define PCC_STALL_PATTERN_CTRL__PCC_BEGIN_STEP_MASK 0x00007C00L |
28028 | #define PCC_STALL_PATTERN_CTRL__PCC_END_STEP_MASK 0x000F8000L |
28029 | #define PCC_STALL_PATTERN_CTRL__PCC_THROTTLE_PATTERN_BIT_NUMS_MASK 0x00F00000L |
28030 | #define PCC_STALL_PATTERN_CTRL__PCC_INST_THROT_INCR_MASK 0x01000000L |
28031 | #define PCC_STALL_PATTERN_CTRL__PCC_INST_THROT_DECR_MASK 0x02000000L |
28032 | #define PCC_STALL_PATTERN_CTRL__PCC_DITHER_MODE_MASK 0x04000000L |
28033 | //PWRBRK_STALL_PATTERN_CTRL |
28034 | #define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_STEP_INTERVAL__SHIFT 0x0 |
28035 | #define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_BEGIN_STEP__SHIFT 0xa |
28036 | #define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_END_STEP__SHIFT 0xf |
28037 | #define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_THROTTLE_PATTERN_BIT_NUMS__SHIFT 0x14 |
28038 | #define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_STEP_INTERVAL_MASK 0x000003FFL |
28039 | #define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_BEGIN_STEP_MASK 0x00007C00L |
28040 | #define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_END_STEP_MASK 0x000F8000L |
28041 | #define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_THROTTLE_PATTERN_BIT_NUMS_MASK 0x00F00000L |
28042 | //PCC_STALL_PATTERN_1_2 |
28043 | #define PCC_STALL_PATTERN_1_2__PCC_STALL_PATTERN_1__SHIFT 0x0 |
28044 | #define PCC_STALL_PATTERN_1_2__PCC_STALL_PATTERN_2__SHIFT 0x10 |
28045 | #define PCC_STALL_PATTERN_1_2__PCC_STALL_PATTERN_1_MASK 0x00007FFFL |
28046 | #define PCC_STALL_PATTERN_1_2__PCC_STALL_PATTERN_2_MASK 0x7FFF0000L |
28047 | //PCC_STALL_PATTERN_3_4 |
28048 | #define PCC_STALL_PATTERN_3_4__PCC_STALL_PATTERN_3__SHIFT 0x0 |
28049 | #define PCC_STALL_PATTERN_3_4__PCC_STALL_PATTERN_4__SHIFT 0x10 |
28050 | #define PCC_STALL_PATTERN_3_4__PCC_STALL_PATTERN_3_MASK 0x00007FFFL |
28051 | #define PCC_STALL_PATTERN_3_4__PCC_STALL_PATTERN_4_MASK 0x7FFF0000L |
28052 | //PCC_STALL_PATTERN_5_6 |
28053 | #define PCC_STALL_PATTERN_5_6__PCC_STALL_PATTERN_5__SHIFT 0x0 |
28054 | #define PCC_STALL_PATTERN_5_6__PCC_STALL_PATTERN_6__SHIFT 0x10 |
28055 | #define PCC_STALL_PATTERN_5_6__PCC_STALL_PATTERN_5_MASK 0x00007FFFL |
28056 | #define PCC_STALL_PATTERN_5_6__PCC_STALL_PATTERN_6_MASK 0x7FFF0000L |
28057 | //PCC_STALL_PATTERN_7 |
28058 | #define PCC_STALL_PATTERN_7__PCC_STALL_PATTERN_7__SHIFT 0x0 |
28059 | #define PCC_STALL_PATTERN_7__PCC_STALL_PATTERN_7_MASK 0x00007FFFL |
28060 | //PWRBRK_STALL_PATTERN_1_2 |
28061 | #define PWRBRK_STALL_PATTERN_1_2__PWRBRK_STALL_PATTERN_1__SHIFT 0x0 |
28062 | #define PWRBRK_STALL_PATTERN_1_2__PWRBRK_STALL_PATTERN_2__SHIFT 0x10 |
28063 | #define PWRBRK_STALL_PATTERN_1_2__PWRBRK_STALL_PATTERN_1_MASK 0x00007FFFL |
28064 | #define PWRBRK_STALL_PATTERN_1_2__PWRBRK_STALL_PATTERN_2_MASK 0x7FFF0000L |
28065 | //PWRBRK_STALL_PATTERN_3_4 |
28066 | #define PWRBRK_STALL_PATTERN_3_4__PWRBRK_STALL_PATTERN_3__SHIFT 0x0 |
28067 | #define PWRBRK_STALL_PATTERN_3_4__PWRBRK_STALL_PATTERN_4__SHIFT 0x10 |
28068 | #define PWRBRK_STALL_PATTERN_3_4__PWRBRK_STALL_PATTERN_3_MASK 0x00007FFFL |
28069 | #define PWRBRK_STALL_PATTERN_3_4__PWRBRK_STALL_PATTERN_4_MASK 0x7FFF0000L |
28070 | //PWRBRK_STALL_PATTERN_5_6 |
28071 | #define PWRBRK_STALL_PATTERN_5_6__PWRBRK_STALL_PATTERN_5__SHIFT 0x0 |
28072 | #define PWRBRK_STALL_PATTERN_5_6__PWRBRK_STALL_PATTERN_6__SHIFT 0x10 |
28073 | #define PWRBRK_STALL_PATTERN_5_6__PWRBRK_STALL_PATTERN_5_MASK 0x00007FFFL |
28074 | #define PWRBRK_STALL_PATTERN_5_6__PWRBRK_STALL_PATTERN_6_MASK 0x7FFF0000L |
28075 | //PWRBRK_STALL_PATTERN_7 |
28076 | #define PWRBRK_STALL_PATTERN_7__PWRBRK_STALL_PATTERN_7__SHIFT 0x0 |
28077 | #define PWRBRK_STALL_PATTERN_7__PWRBRK_STALL_PATTERN_7_MASK 0x00007FFFL |
28078 | //DIDT_STALL_PATTERN_CTRL |
28079 | #define DIDT_STALL_PATTERN_CTRL__DIDT_DROOP_CTRL_EN__SHIFT 0x0 |
28080 | #define DIDT_STALL_PATTERN_CTRL__DIDT_DROOP_SW_RST__SHIFT 0x1 |
28081 | #define DIDT_STALL_PATTERN_CTRL__DIDT_DROOP_CLK_EN_OVERRIDE__SHIFT 0x2 |
28082 | #define DIDT_STALL_PATTERN_CTRL__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT 0x3 |
28083 | #define DIDT_STALL_PATTERN_CTRL__DIDT_PATTERN_EXTEND_EN__SHIFT 0x7 |
28084 | #define DIDT_STALL_PATTERN_CTRL__DIDT_PATTERN_EXTEND_MODE__SHIFT 0x8 |
28085 | #define DIDT_STALL_PATTERN_CTRL__DIDT_DROOP_CTRL_EN_MASK 0x00000001L |
28086 | #define DIDT_STALL_PATTERN_CTRL__DIDT_DROOP_SW_RST_MASK 0x00000002L |
28087 | #define DIDT_STALL_PATTERN_CTRL__DIDT_DROOP_CLK_EN_OVERRIDE_MASK 0x00000004L |
28088 | #define DIDT_STALL_PATTERN_CTRL__DIDT_STALL_PATTERN_BIT_NUMS_MASK 0x00000078L |
28089 | #define DIDT_STALL_PATTERN_CTRL__DIDT_PATTERN_EXTEND_EN_MASK 0x00000080L |
28090 | #define DIDT_STALL_PATTERN_CTRL__DIDT_PATTERN_EXTEND_MODE_MASK 0x00000700L |
28091 | //DIDT_STALL_PATTERN_1_2 |
28092 | #define DIDT_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT 0x0 |
28093 | #define DIDT_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT 0x10 |
28094 | #define DIDT_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK 0x00007FFFL |
28095 | #define DIDT_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK 0x7FFF0000L |
28096 | //DIDT_STALL_PATTERN_3_4 |
28097 | #define DIDT_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT 0x0 |
28098 | #define DIDT_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT 0x10 |
28099 | #define DIDT_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK 0x00007FFFL |
28100 | #define DIDT_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK 0x7FFF0000L |
28101 | //DIDT_STALL_PATTERN_5_6 |
28102 | #define DIDT_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT 0x0 |
28103 | #define DIDT_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT 0x10 |
28104 | #define DIDT_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK 0x00007FFFL |
28105 | #define DIDT_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK 0x7FFF0000L |
28106 | //DIDT_STALL_PATTERN_7 |
28107 | #define DIDT_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT 0x0 |
28108 | #define DIDT_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK 0x00007FFFL |
28109 | //PCC_PWRBRK_HYSTERESIS_CTRL |
28110 | #define PCC_PWRBRK_HYSTERESIS_CTRL__PCC_MAX_HYSTERESIS__SHIFT 0x0 |
28111 | #define PCC_PWRBRK_HYSTERESIS_CTRL__PWRBRK_MAX_HYSTERESIS__SHIFT 0x8 |
28112 | #define PCC_PWRBRK_HYSTERESIS_CTRL__PCC_MAX_HYSTERESIS_MASK 0x000000FFL |
28113 | #define PCC_PWRBRK_HYSTERESIS_CTRL__PWRBRK_MAX_HYSTERESIS_MASK 0x0000FF00L |
28114 | //EDC_STRETCH_PERF_COUNTER |
28115 | #define EDC_STRETCH_PERF_COUNTER__STRETCH_PERF_COUNTER__SHIFT 0x0 |
28116 | #define EDC_STRETCH_PERF_COUNTER__STRETCH_PERF_COUNTER_MASK 0xFFFFFFFFL |
28117 | //EDC_UNSTRETCH_PERF_COUNTER |
28118 | #define EDC_UNSTRETCH_PERF_COUNTER__UNSTRETCH_PERF_COUNTER__SHIFT 0x0 |
28119 | #define EDC_UNSTRETCH_PERF_COUNTER__UNSTRETCH_PERF_COUNTER_MASK 0xFFFFFFFFL |
28120 | //EDC_STRETCH_NUM_PERF_COUNTER |
28121 | #define EDC_STRETCH_NUM_PERF_COUNTER__STRETCH_NUM_PERF_COUNTER__SHIFT 0x0 |
28122 | #define EDC_STRETCH_NUM_PERF_COUNTER__STRETCH_NUM_PERF_COUNTER_MASK 0xFFFFFFFFL |
28123 | //GC_EDC_STATUS |
28124 | #define GC_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT 0x0 |
28125 | #define GC_EDC_STATUS__GPIO_IN_0__SHIFT 0x3 |
28126 | #define GC_EDC_STATUS__GPIO_IN_1__SHIFT 0x4 |
28127 | #define GC_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK 0x00000007L |
28128 | #define GC_EDC_STATUS__GPIO_IN_0_MASK 0x00000008L |
28129 | #define GC_EDC_STATUS__GPIO_IN_1_MASK 0x00000010L |
28130 | //GC_EDC_OVERFLOW |
28131 | #define GC_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT 0x0 |
28132 | #define GC_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT 0x1 |
28133 | #define GC_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK 0x00000001L |
28134 | #define GC_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK 0x0001FFFEL |
28135 | //GC_EDC_ROLLING_POWER_DELTA |
28136 | #define GC_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT 0x0 |
28137 | #define GC_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK 0xFFFFFFFFL |
28138 | //GC_THROTTLE_STATUS |
28139 | #define GC_THROTTLE_STATUS__FSM_STATE__SHIFT 0x0 |
28140 | #define GC_THROTTLE_STATUS__PATTERN_INDEX__SHIFT 0x4 |
28141 | #define GC_THROTTLE_STATUS__FSM_STATE_MASK 0x0000000FL |
28142 | #define GC_THROTTLE_STATUS__PATTERN_INDEX_MASK 0x000001F0L |
28143 | //EDC_PERF_COUNTER |
28144 | #define EDC_PERF_COUNTER__EDC_PERF_COUNTER__SHIFT 0x0 |
28145 | #define EDC_PERF_COUNTER__EDC_PERF_COUNTER_MASK 0xFFFFFFFFL |
28146 | //PCC_PERF_COUNTER |
28147 | #define PCC_PERF_COUNTER__PCC_PERF_COUNTER__SHIFT 0x0 |
28148 | #define PCC_PERF_COUNTER__PCC_PERF_COUNTER_MASK 0xFFFFFFFFL |
28149 | //PWRBRK_PERF_COUNTER |
28150 | #define PWRBRK_PERF_COUNTER__PWRBRK_PERF_COUNTER__SHIFT 0x0 |
28151 | #define PWRBRK_PERF_COUNTER__PWRBRK_PERF_COUNTER_MASK 0xFFFFFFFFL |
28152 | //EDC_HYSTERESIS_STAT |
28153 | #define EDC_HYSTERESIS_STAT__HYSTERESIS_CNT__SHIFT 0x0 |
28154 | #define EDC_HYSTERESIS_STAT__EDC_STATUS__SHIFT 0x8 |
28155 | #define EDC_HYSTERESIS_STAT__EDC_CREDIT_INCR_OVERFLOW__SHIFT 0x9 |
28156 | #define EDC_HYSTERESIS_STAT__EDC_THRESHOLD_SEL__SHIFT 0xa |
28157 | #define EDC_HYSTERESIS_STAT__HYSTERESIS_CNT_MASK 0x000000FFL |
28158 | #define EDC_HYSTERESIS_STAT__EDC_STATUS_MASK 0x00000100L |
28159 | #define EDC_HYSTERESIS_STAT__EDC_CREDIT_INCR_OVERFLOW_MASK 0x00000200L |
28160 | #define EDC_HYSTERESIS_STAT__EDC_THRESHOLD_SEL_MASK 0x00000400L |
28161 | //GC_CAC_WEIGHT_CP_0 |
28162 | #define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG0__SHIFT 0x0 |
28163 | #define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG1__SHIFT 0x10 |
28164 | #define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG0_MASK 0x0000FFFFL |
28165 | #define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG1_MASK 0xFFFF0000L |
28166 | //GC_CAC_WEIGHT_CP_1 |
28167 | #define GC_CAC_WEIGHT_CP_1__WEIGHT_CP_SIG2__SHIFT 0x0 |
28168 | #define GC_CAC_WEIGHT_CP_1__WEIGHT_CP_SIG2_MASK 0x0000FFFFL |
28169 | //GC_CAC_WEIGHT_EA_0 |
28170 | #define GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG0__SHIFT 0x0 |
28171 | #define GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG1__SHIFT 0x10 |
28172 | #define GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG0_MASK 0x0000FFFFL |
28173 | #define GC_CAC_WEIGHT_EA_0__WEIGHT_EA_SIG1_MASK 0xFFFF0000L |
28174 | //GC_CAC_WEIGHT_EA_1 |
28175 | #define GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG2__SHIFT 0x0 |
28176 | #define GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG3__SHIFT 0x10 |
28177 | #define GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG2_MASK 0x0000FFFFL |
28178 | #define GC_CAC_WEIGHT_EA_1__WEIGHT_EA_SIG3_MASK 0xFFFF0000L |
28179 | //GC_CAC_WEIGHT_EA_2 |
28180 | #define GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG4__SHIFT 0x0 |
28181 | #define GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG5__SHIFT 0x10 |
28182 | #define GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG4_MASK 0x0000FFFFL |
28183 | #define GC_CAC_WEIGHT_EA_2__WEIGHT_EA_SIG5_MASK 0xFFFF0000L |
28184 | //GC_CAC_WEIGHT_UTCL2_ROUTER_0 |
28185 | #define GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG0__SHIFT 0x0 |
28186 | #define GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG1__SHIFT 0x10 |
28187 | #define GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG0_MASK 0x0000FFFFL |
28188 | #define GC_CAC_WEIGHT_UTCL2_ROUTER_0__WEIGHT_UTCL2_ROUTER_SIG1_MASK 0xFFFF0000L |
28189 | //GC_CAC_WEIGHT_UTCL2_ROUTER_1 |
28190 | #define GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG2__SHIFT 0x0 |
28191 | #define GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG3__SHIFT 0x10 |
28192 | #define GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG2_MASK 0x0000FFFFL |
28193 | #define GC_CAC_WEIGHT_UTCL2_ROUTER_1__WEIGHT_UTCL2_ROUTER_SIG3_MASK 0xFFFF0000L |
28194 | //GC_CAC_WEIGHT_UTCL2_ROUTER_2 |
28195 | #define GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG4__SHIFT 0x0 |
28196 | #define GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG5__SHIFT 0x10 |
28197 | #define GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG4_MASK 0x0000FFFFL |
28198 | #define GC_CAC_WEIGHT_UTCL2_ROUTER_2__WEIGHT_UTCL2_ROUTER_SIG5_MASK 0xFFFF0000L |
28199 | //GC_CAC_WEIGHT_UTCL2_ROUTER_3 |
28200 | #define GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG6__SHIFT 0x0 |
28201 | #define GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG7__SHIFT 0x10 |
28202 | #define GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG6_MASK 0x0000FFFFL |
28203 | #define GC_CAC_WEIGHT_UTCL2_ROUTER_3__WEIGHT_UTCL2_ROUTER_SIG7_MASK 0xFFFF0000L |
28204 | //GC_CAC_WEIGHT_UTCL2_ROUTER_4 |
28205 | #define GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG8__SHIFT 0x0 |
28206 | #define GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG9__SHIFT 0x10 |
28207 | #define GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG8_MASK 0x0000FFFFL |
28208 | #define GC_CAC_WEIGHT_UTCL2_ROUTER_4__WEIGHT_UTCL2_ROUTER_SIG9_MASK 0xFFFF0000L |
28209 | //GC_CAC_WEIGHT_UTCL2_VML2_0 |
28210 | #define GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG0__SHIFT 0x0 |
28211 | #define GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG1__SHIFT 0x10 |
28212 | #define GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG0_MASK 0x0000FFFFL |
28213 | #define GC_CAC_WEIGHT_UTCL2_VML2_0__WEIGHT_UTCL2_VML2_SIG1_MASK 0xFFFF0000L |
28214 | //GC_CAC_WEIGHT_UTCL2_VML2_1 |
28215 | #define GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG2__SHIFT 0x0 |
28216 | #define GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG3__SHIFT 0x10 |
28217 | #define GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG2_MASK 0x0000FFFFL |
28218 | #define GC_CAC_WEIGHT_UTCL2_VML2_1__WEIGHT_UTCL2_VML2_SIG3_MASK 0xFFFF0000L |
28219 | //GC_CAC_WEIGHT_UTCL2_VML2_2 |
28220 | #define GC_CAC_WEIGHT_UTCL2_VML2_2__WEIGHT_UTCL2_VML2_SIG4__SHIFT 0x0 |
28221 | #define GC_CAC_WEIGHT_UTCL2_VML2_2__WEIGHT_UTCL2_VML2_SIG4_MASK 0x0000FFFFL |
28222 | //GC_CAC_WEIGHT_UTCL2_WALKER_0 |
28223 | #define GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG0__SHIFT 0x0 |
28224 | #define GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG1__SHIFT 0x10 |
28225 | #define GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG0_MASK 0x0000FFFFL |
28226 | #define GC_CAC_WEIGHT_UTCL2_WALKER_0__WEIGHT_UTCL2_WALKER_SIG1_MASK 0xFFFF0000L |
28227 | //GC_CAC_WEIGHT_UTCL2_WALKER_1 |
28228 | #define GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG2__SHIFT 0x0 |
28229 | #define GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG3__SHIFT 0x10 |
28230 | #define GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG2_MASK 0x0000FFFFL |
28231 | #define GC_CAC_WEIGHT_UTCL2_WALKER_1__WEIGHT_UTCL2_WALKER_SIG3_MASK 0xFFFF0000L |
28232 | //GC_CAC_WEIGHT_UTCL2_WALKER_2 |
28233 | #define GC_CAC_WEIGHT_UTCL2_WALKER_2__WEIGHT_UTCL2_WALKER_SIG4__SHIFT 0x0 |
28234 | #define GC_CAC_WEIGHT_UTCL2_WALKER_2__WEIGHT_UTCL2_WALKER_SIG4_MASK 0x0000FFFFL |
28235 | //GC_CAC_WEIGHT_GDS_0 |
28236 | #define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG0__SHIFT 0x0 |
28237 | #define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG1__SHIFT 0x10 |
28238 | #define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG0_MASK 0x0000FFFFL |
28239 | #define GC_CAC_WEIGHT_GDS_0__WEIGHT_GDS_SIG1_MASK 0xFFFF0000L |
28240 | //GC_CAC_WEIGHT_GDS_1 |
28241 | #define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG2__SHIFT 0x0 |
28242 | #define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG3__SHIFT 0x10 |
28243 | #define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG2_MASK 0x0000FFFFL |
28244 | #define GC_CAC_WEIGHT_GDS_1__WEIGHT_GDS_SIG3_MASK 0xFFFF0000L |
28245 | //GC_CAC_WEIGHT_GDS_2 |
28246 | #define GC_CAC_WEIGHT_GDS_2__WEIGHT_GDS_SIG4__SHIFT 0x0 |
28247 | #define GC_CAC_WEIGHT_GDS_2__WEIGHT_GDS_SIG4_MASK 0x0000FFFFL |
28248 | //GC_CAC_WEIGHT_GE_0 |
28249 | #define GC_CAC_WEIGHT_GE_0__WEIGHT_GE_SIG0__SHIFT 0x0 |
28250 | #define GC_CAC_WEIGHT_GE_0__WEIGHT_GE_SIG1__SHIFT 0x10 |
28251 | #define GC_CAC_WEIGHT_GE_0__WEIGHT_GE_SIG0_MASK 0x0000FFFFL |
28252 | #define GC_CAC_WEIGHT_GE_0__WEIGHT_GE_SIG1_MASK 0xFFFF0000L |
28253 | //GC_CAC_WEIGHT_GE_1 |
28254 | #define GC_CAC_WEIGHT_GE_1__WEIGHT_GE_SIG2__SHIFT 0x0 |
28255 | #define GC_CAC_WEIGHT_GE_1__WEIGHT_GE_SIG3__SHIFT 0x10 |
28256 | #define GC_CAC_WEIGHT_GE_1__WEIGHT_GE_SIG2_MASK 0x0000FFFFL |
28257 | #define GC_CAC_WEIGHT_GE_1__WEIGHT_GE_SIG3_MASK 0xFFFF0000L |
28258 | //GC_CAC_WEIGHT_GE_2 |
28259 | #define GC_CAC_WEIGHT_GE_2__WEIGHT_GE_SIG4__SHIFT 0x0 |
28260 | #define GC_CAC_WEIGHT_GE_2__WEIGHT_GE_SIG5__SHIFT 0x10 |
28261 | #define GC_CAC_WEIGHT_GE_2__WEIGHT_GE_SIG4_MASK 0x0000FFFFL |
28262 | #define GC_CAC_WEIGHT_GE_2__WEIGHT_GE_SIG5_MASK 0xFFFF0000L |
28263 | //GC_CAC_WEIGHT_GE_3 |
28264 | #define GC_CAC_WEIGHT_GE_3__WEIGHT_GE_SIG6__SHIFT 0x0 |
28265 | #define GC_CAC_WEIGHT_GE_3__WEIGHT_GE_SIG6_MASK 0x0000FFFFL |
28266 | //GC_CAC_WEIGHT_PMM_0 |
28267 | #define GC_CAC_WEIGHT_PMM_0__WEIGHT_PMM_SIG0__SHIFT 0x0 |
28268 | #define GC_CAC_WEIGHT_PMM_0__WEIGHT_PMM_SIG0_MASK 0x0000FFFFL |
28269 | //GC_CAC_WEIGHT_GL2C_0 |
28270 | #define GC_CAC_WEIGHT_GL2C_0__WEIGHT_GL2C_SIG0__SHIFT 0x0 |
28271 | #define GC_CAC_WEIGHT_GL2C_0__WEIGHT_GL2C_SIG1__SHIFT 0x10 |
28272 | #define GC_CAC_WEIGHT_GL2C_0__WEIGHT_GL2C_SIG0_MASK 0x0000FFFFL |
28273 | #define GC_CAC_WEIGHT_GL2C_0__WEIGHT_GL2C_SIG1_MASK 0xFFFF0000L |
28274 | //GC_CAC_WEIGHT_GL2C_1 |
28275 | #define GC_CAC_WEIGHT_GL2C_1__WEIGHT_GL2C_SIG2__SHIFT 0x0 |
28276 | #define GC_CAC_WEIGHT_GL2C_1__WEIGHT_GL2C_SIG3__SHIFT 0x10 |
28277 | #define GC_CAC_WEIGHT_GL2C_1__WEIGHT_GL2C_SIG2_MASK 0x0000FFFFL |
28278 | #define GC_CAC_WEIGHT_GL2C_1__WEIGHT_GL2C_SIG3_MASK 0xFFFF0000L |
28279 | //GC_CAC_WEIGHT_GL2C_2 |
28280 | #define GC_CAC_WEIGHT_GL2C_2__WEIGHT_GL2C_SIG4__SHIFT 0x0 |
28281 | #define GC_CAC_WEIGHT_GL2C_2__WEIGHT_GL2C_SIG4_MASK 0x0000FFFFL |
28282 | //GC_CAC_WEIGHT_PH_0 |
28283 | #define GC_CAC_WEIGHT_PH_0__WEIGHT_PH_SIG0__SHIFT 0x0 |
28284 | #define GC_CAC_WEIGHT_PH_0__WEIGHT_PH_SIG1__SHIFT 0x10 |
28285 | #define GC_CAC_WEIGHT_PH_0__WEIGHT_PH_SIG0_MASK 0x0000FFFFL |
28286 | #define GC_CAC_WEIGHT_PH_0__WEIGHT_PH_SIG1_MASK 0xFFFF0000L |
28287 | //GC_CAC_WEIGHT_PH_1 |
28288 | #define GC_CAC_WEIGHT_PH_1__WEIGHT_PH_SIG2__SHIFT 0x0 |
28289 | #define GC_CAC_WEIGHT_PH_1__WEIGHT_PH_SIG3__SHIFT 0x10 |
28290 | #define GC_CAC_WEIGHT_PH_1__WEIGHT_PH_SIG2_MASK 0x0000FFFFL |
28291 | #define GC_CAC_WEIGHT_PH_1__WEIGHT_PH_SIG3_MASK 0xFFFF0000L |
28292 | //GC_CAC_WEIGHT_PH_2 |
28293 | #define GC_CAC_WEIGHT_PH_2__WEIGHT_PH_SIG4__SHIFT 0x0 |
28294 | #define GC_CAC_WEIGHT_PH_2__WEIGHT_PH_SIG5__SHIFT 0x10 |
28295 | #define GC_CAC_WEIGHT_PH_2__WEIGHT_PH_SIG4_MASK 0x0000FFFFL |
28296 | #define GC_CAC_WEIGHT_PH_2__WEIGHT_PH_SIG5_MASK 0xFFFF0000L |
28297 | //GC_CAC_WEIGHT_PH_3 |
28298 | #define GC_CAC_WEIGHT_PH_3__WEIGHT_PH_SIG6__SHIFT 0x0 |
28299 | #define GC_CAC_WEIGHT_PH_3__WEIGHT_PH_SIG7__SHIFT 0x10 |
28300 | #define GC_CAC_WEIGHT_PH_3__WEIGHT_PH_SIG6_MASK 0x0000FFFFL |
28301 | #define GC_CAC_WEIGHT_PH_3__WEIGHT_PH_SIG7_MASK 0xFFFF0000L |
28302 | //GC_CAC_WEIGHT_SDMA_0 |
28303 | #define GC_CAC_WEIGHT_SDMA_0__WEIGHT_SDMA_SIG0__SHIFT 0x0 |
28304 | #define GC_CAC_WEIGHT_SDMA_0__WEIGHT_SDMA_SIG1__SHIFT 0x10 |
28305 | #define GC_CAC_WEIGHT_SDMA_0__WEIGHT_SDMA_SIG0_MASK 0x0000FFFFL |
28306 | #define GC_CAC_WEIGHT_SDMA_0__WEIGHT_SDMA_SIG1_MASK 0xFFFF0000L |
28307 | //GC_CAC_WEIGHT_SDMA_1 |
28308 | #define GC_CAC_WEIGHT_SDMA_1__WEIGHT_SDMA_SIG2__SHIFT 0x0 |
28309 | #define GC_CAC_WEIGHT_SDMA_1__WEIGHT_SDMA_SIG3__SHIFT 0x10 |
28310 | #define GC_CAC_WEIGHT_SDMA_1__WEIGHT_SDMA_SIG2_MASK 0x0000FFFFL |
28311 | #define GC_CAC_WEIGHT_SDMA_1__WEIGHT_SDMA_SIG3_MASK 0xFFFF0000L |
28312 | //GC_CAC_WEIGHT_SDMA_2 |
28313 | #define GC_CAC_WEIGHT_SDMA_2__WEIGHT_SDMA_SIG4__SHIFT 0x0 |
28314 | #define GC_CAC_WEIGHT_SDMA_2__WEIGHT_SDMA_SIG5__SHIFT 0x10 |
28315 | #define GC_CAC_WEIGHT_SDMA_2__WEIGHT_SDMA_SIG4_MASK 0x0000FFFFL |
28316 | #define GC_CAC_WEIGHT_SDMA_2__WEIGHT_SDMA_SIG5_MASK 0xFFFF0000L |
28317 | //GC_CAC_WEIGHT_SDMA_3 |
28318 | #define GC_CAC_WEIGHT_SDMA_3__WEIGHT_SDMA_SIG6__SHIFT 0x0 |
28319 | #define GC_CAC_WEIGHT_SDMA_3__WEIGHT_SDMA_SIG7__SHIFT 0x10 |
28320 | #define GC_CAC_WEIGHT_SDMA_3__WEIGHT_SDMA_SIG6_MASK 0x0000FFFFL |
28321 | #define GC_CAC_WEIGHT_SDMA_3__WEIGHT_SDMA_SIG7_MASK 0xFFFF0000L |
28322 | //GC_CAC_WEIGHT_SDMA_4 |
28323 | #define GC_CAC_WEIGHT_SDMA_4__WEIGHT_SDMA_SIG8__SHIFT 0x0 |
28324 | #define GC_CAC_WEIGHT_SDMA_4__WEIGHT_SDMA_SIG9__SHIFT 0x10 |
28325 | #define GC_CAC_WEIGHT_SDMA_4__WEIGHT_SDMA_SIG8_MASK 0x0000FFFFL |
28326 | #define GC_CAC_WEIGHT_SDMA_4__WEIGHT_SDMA_SIG9_MASK 0xFFFF0000L |
28327 | //GC_CAC_WEIGHT_SDMA_5 |
28328 | #define GC_CAC_WEIGHT_SDMA_5__WEIGHT_SDMA_SIG10__SHIFT 0x0 |
28329 | #define GC_CAC_WEIGHT_SDMA_5__WEIGHT_SDMA_SIG11__SHIFT 0x10 |
28330 | #define GC_CAC_WEIGHT_SDMA_5__WEIGHT_SDMA_SIG10_MASK 0x0000FFFFL |
28331 | #define GC_CAC_WEIGHT_SDMA_5__WEIGHT_SDMA_SIG11_MASK 0xFFFF0000L |
28332 | //GC_CAC_WEIGHT_CHC_0 |
28333 | #define GC_CAC_WEIGHT_CHC_0__WEIGHT_CHC_SIG0__SHIFT 0x0 |
28334 | #define GC_CAC_WEIGHT_CHC_0__WEIGHT_CHC_SIG1__SHIFT 0x10 |
28335 | #define GC_CAC_WEIGHT_CHC_0__WEIGHT_CHC_SIG0_MASK 0x0000FFFFL |
28336 | #define GC_CAC_WEIGHT_CHC_0__WEIGHT_CHC_SIG1_MASK 0xFFFF0000L |
28337 | //GC_CAC_WEIGHT_CHC_1 |
28338 | #define GC_CAC_WEIGHT_CHC_1__WEIGHT_CHC_SIG2__SHIFT 0x0 |
28339 | #define GC_CAC_WEIGHT_CHC_1__WEIGHT_CHC_SIG2_MASK 0x0000FFFFL |
28340 | //GC_CAC_WEIGHT_GUS_0 |
28341 | #define GC_CAC_WEIGHT_GUS_0__WEIGHT_GUS_SIG0__SHIFT 0x0 |
28342 | #define GC_CAC_WEIGHT_GUS_0__WEIGHT_GUS_SIG1__SHIFT 0x10 |
28343 | #define GC_CAC_WEIGHT_GUS_0__WEIGHT_GUS_SIG0_MASK 0x0000FFFFL |
28344 | #define GC_CAC_WEIGHT_GUS_0__WEIGHT_GUS_SIG1_MASK 0xFFFF0000L |
28345 | //GC_CAC_WEIGHT_GUS_1 |
28346 | #define GC_CAC_WEIGHT_GUS_1__WEIGHT_GUS_SIG2__SHIFT 0x0 |
28347 | #define GC_CAC_WEIGHT_GUS_1__WEIGHT_GUS_SIG2_MASK 0x0000FFFFL |
28348 | //GC_CAC_WEIGHT_RLC_0 |
28349 | #define GC_CAC_WEIGHT_RLC_0__WEIGHT_RLC_SIG0__SHIFT 0x0 |
28350 | #define GC_CAC_WEIGHT_RLC_0__WEIGHT_RLC_SIG0_MASK 0x0000FFFFL |
28351 | //GC_CAC_WEIGHT_GRBM_0 |
28352 | #define GC_CAC_WEIGHT_GRBM_0__WEIGHT_GRBM_SIG0__SHIFT 0x0 |
28353 | #define GC_CAC_WEIGHT_GRBM_0__WEIGHT_GRBM_SIG1__SHIFT 0x10 |
28354 | #define GC_CAC_WEIGHT_GRBM_0__WEIGHT_GRBM_SIG0_MASK 0x0000FFFFL |
28355 | #define GC_CAC_WEIGHT_GRBM_0__WEIGHT_GRBM_SIG1_MASK 0xFFFF0000L |
28356 | //GC_EDC_CLK_MONITOR_CTRL |
28357 | #define GC_EDC_CLK_MONITOR_CTRL__EDC_CLK_MONITOR_EN__SHIFT 0x0 |
28358 | #define GC_EDC_CLK_MONITOR_CTRL__EDC_CLK_MONITOR_INTERVAL__SHIFT 0x1 |
28359 | #define GC_EDC_CLK_MONITOR_CTRL__EDC_CLK_MONITOR_THRESHOLD__SHIFT 0x5 |
28360 | #define GC_EDC_CLK_MONITOR_CTRL__EDC_CLK_MONITOR_EN_MASK 0x00000001L |
28361 | #define GC_EDC_CLK_MONITOR_CTRL__EDC_CLK_MONITOR_INTERVAL_MASK 0x0000001EL |
28362 | #define GC_EDC_CLK_MONITOR_CTRL__EDC_CLK_MONITOR_THRESHOLD_MASK 0x0001FFE0L |
28363 | //GC_CAC_IND_INDEX |
28364 | #define GC_CAC_IND_INDEX__GC_CAC_IND_ADDR__SHIFT 0x0 |
28365 | #define GC_CAC_IND_INDEX__GC_CAC_IND_ADDR_MASK 0xFFFFFFFFL |
28366 | //GC_CAC_IND_DATA |
28367 | #define GC_CAC_IND_DATA__GC_CAC_IND_DATA__SHIFT 0x0 |
28368 | #define GC_CAC_IND_DATA__GC_CAC_IND_DATA_MASK 0xFFFFFFFFL |
28369 | //SE_CAC_CTRL_1 |
28370 | #define SE_CAC_CTRL_1__CAC_WINDOW__SHIFT 0x0 |
28371 | #define SE_CAC_CTRL_1__TDP_WINDOW__SHIFT 0x8 |
28372 | #define SE_CAC_CTRL_1__CAC_WINDOW_MASK 0x000000FFL |
28373 | #define SE_CAC_CTRL_1__TDP_WINDOW_MASK 0xFFFFFF00L |
28374 | //SE_CAC_CTRL_2 |
28375 | #define SE_CAC_CTRL_2__CAC_ENABLE__SHIFT 0x0 |
28376 | #define SE_CAC_CTRL_2__SE_LCAC_ENABLE__SHIFT 0x1 |
28377 | #define SE_CAC_CTRL_2__WGP_CAC_CLK_OVERRIDE__SHIFT 0x2 |
28378 | #define SE_CAC_CTRL_2__SE_CAC_INDEX_AUTO_INCR_EN__SHIFT 0x3 |
28379 | #define SE_CAC_CTRL_2__CAC_ENABLE_MASK 0x00000001L |
28380 | #define SE_CAC_CTRL_2__SE_LCAC_ENABLE_MASK 0x00000002L |
28381 | #define SE_CAC_CTRL_2__WGP_CAC_CLK_OVERRIDE_MASK 0x00000004L |
28382 | #define SE_CAC_CTRL_2__SE_CAC_INDEX_AUTO_INCR_EN_MASK 0x00000008L |
28383 | //SE_CAC_WEIGHT_TA_0 |
28384 | #define SE_CAC_WEIGHT_TA_0__WEIGHT_TA_SIG0__SHIFT 0x0 |
28385 | #define SE_CAC_WEIGHT_TA_0__WEIGHT_TA_SIG0_MASK 0x0000FFFFL |
28386 | //SE_CAC_WEIGHT_TD_0 |
28387 | #define SE_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG0__SHIFT 0x0 |
28388 | #define SE_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG1__SHIFT 0x10 |
28389 | #define SE_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG0_MASK 0x0000FFFFL |
28390 | #define SE_CAC_WEIGHT_TD_0__WEIGHT_TD_SIG1_MASK 0xFFFF0000L |
28391 | //SE_CAC_WEIGHT_TD_1 |
28392 | #define SE_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG2__SHIFT 0x0 |
28393 | #define SE_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG3__SHIFT 0x10 |
28394 | #define SE_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG2_MASK 0x0000FFFFL |
28395 | #define SE_CAC_WEIGHT_TD_1__WEIGHT_TD_SIG3_MASK 0xFFFF0000L |
28396 | //SE_CAC_WEIGHT_TD_2 |
28397 | #define SE_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG4__SHIFT 0x0 |
28398 | #define SE_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG5__SHIFT 0x10 |
28399 | #define SE_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG4_MASK 0x0000FFFFL |
28400 | #define SE_CAC_WEIGHT_TD_2__WEIGHT_TD_SIG5_MASK 0xFFFF0000L |
28401 | //SE_CAC_WEIGHT_TD_3 |
28402 | #define SE_CAC_WEIGHT_TD_3__WEIGHT_TD_SIG6__SHIFT 0x0 |
28403 | #define SE_CAC_WEIGHT_TD_3__WEIGHT_TD_SIG7__SHIFT 0x10 |
28404 | #define SE_CAC_WEIGHT_TD_3__WEIGHT_TD_SIG6_MASK 0x0000FFFFL |
28405 | #define SE_CAC_WEIGHT_TD_3__WEIGHT_TD_SIG7_MASK 0xFFFF0000L |
28406 | //SE_CAC_WEIGHT_TD_4 |
28407 | #define SE_CAC_WEIGHT_TD_4__WEIGHT_TD_SIG8__SHIFT 0x0 |
28408 | #define SE_CAC_WEIGHT_TD_4__WEIGHT_TD_SIG9__SHIFT 0x10 |
28409 | #define SE_CAC_WEIGHT_TD_4__WEIGHT_TD_SIG8_MASK 0x0000FFFFL |
28410 | #define SE_CAC_WEIGHT_TD_4__WEIGHT_TD_SIG9_MASK 0xFFFF0000L |
28411 | //SE_CAC_WEIGHT_TD_5 |
28412 | #define SE_CAC_WEIGHT_TD_5__WEIGHT_TD_SIG10__SHIFT 0x0 |
28413 | #define SE_CAC_WEIGHT_TD_5__WEIGHT_TD_SIG10_MASK 0x0000FFFFL |
28414 | //SE_CAC_WEIGHT_TCP_0 |
28415 | #define SE_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG0__SHIFT 0x0 |
28416 | #define SE_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG1__SHIFT 0x10 |
28417 | #define SE_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG0_MASK 0x0000FFFFL |
28418 | #define SE_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG1_MASK 0xFFFF0000L |
28419 | //SE_CAC_WEIGHT_TCP_1 |
28420 | #define SE_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG2__SHIFT 0x0 |
28421 | #define SE_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG3__SHIFT 0x10 |
28422 | #define SE_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG2_MASK 0x0000FFFFL |
28423 | #define SE_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG3_MASK 0xFFFF0000L |
28424 | //SE_CAC_WEIGHT_TCP_2 |
28425 | #define SE_CAC_WEIGHT_TCP_2__WEIGHT_TCP_SIG4__SHIFT 0x0 |
28426 | #define SE_CAC_WEIGHT_TCP_2__WEIGHT_TCP_SIG5__SHIFT 0x10 |
28427 | #define SE_CAC_WEIGHT_TCP_2__WEIGHT_TCP_SIG4_MASK 0x0000FFFFL |
28428 | #define SE_CAC_WEIGHT_TCP_2__WEIGHT_TCP_SIG5_MASK 0xFFFF0000L |
28429 | //SE_CAC_WEIGHT_TCP_3 |
28430 | #define SE_CAC_WEIGHT_TCP_3__WEIGHT_TCP_SIG6__SHIFT 0x0 |
28431 | #define SE_CAC_WEIGHT_TCP_3__WEIGHT_TCP_SIG7__SHIFT 0x10 |
28432 | #define SE_CAC_WEIGHT_TCP_3__WEIGHT_TCP_SIG6_MASK 0x0000FFFFL |
28433 | #define SE_CAC_WEIGHT_TCP_3__WEIGHT_TCP_SIG7_MASK 0xFFFF0000L |
28434 | //SE_CAC_WEIGHT_SQ_0 |
28435 | #define SE_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG0__SHIFT 0x0 |
28436 | #define SE_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG1__SHIFT 0x10 |
28437 | #define SE_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG0_MASK 0x0000FFFFL |
28438 | #define SE_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG1_MASK 0xFFFF0000L |
28439 | //SE_CAC_WEIGHT_SQ_1 |
28440 | #define SE_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG2__SHIFT 0x0 |
28441 | #define SE_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG3__SHIFT 0x10 |
28442 | #define SE_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG2_MASK 0x0000FFFFL |
28443 | #define SE_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG3_MASK 0xFFFF0000L |
28444 | //SE_CAC_WEIGHT_SQ_2 |
28445 | #define SE_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG4__SHIFT 0x0 |
28446 | #define SE_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG4_MASK 0x0000FFFFL |
28447 | //SE_CAC_WEIGHT_SP_0 |
28448 | #define SE_CAC_WEIGHT_SP_0__WEIGHT_SP_SIG0__SHIFT 0x0 |
28449 | #define SE_CAC_WEIGHT_SP_0__WEIGHT_SP_SIG1__SHIFT 0x10 |
28450 | #define SE_CAC_WEIGHT_SP_0__WEIGHT_SP_SIG0_MASK 0x0000FFFFL |
28451 | #define SE_CAC_WEIGHT_SP_0__WEIGHT_SP_SIG1_MASK 0xFFFF0000L |
28452 | //SE_CAC_WEIGHT_SP_1 |
28453 | #define SE_CAC_WEIGHT_SP_1__WEIGHT_SP_SIG2__SHIFT 0x0 |
28454 | #define SE_CAC_WEIGHT_SP_1__WEIGHT_SP_SIG2_MASK 0x0000FFFFL |
28455 | //SE_CAC_WEIGHT_LDS_0 |
28456 | #define SE_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG0__SHIFT 0x0 |
28457 | #define SE_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG1__SHIFT 0x10 |
28458 | #define SE_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG0_MASK 0x0000FFFFL |
28459 | #define SE_CAC_WEIGHT_LDS_0__WEIGHT_LDS_SIG1_MASK 0xFFFF0000L |
28460 | //SE_CAC_WEIGHT_LDS_1 |
28461 | #define SE_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG2__SHIFT 0x0 |
28462 | #define SE_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG3__SHIFT 0x10 |
28463 | #define SE_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG2_MASK 0x0000FFFFL |
28464 | #define SE_CAC_WEIGHT_LDS_1__WEIGHT_LDS_SIG3_MASK 0xFFFF0000L |
28465 | //SE_CAC_WEIGHT_LDS_2 |
28466 | #define SE_CAC_WEIGHT_LDS_2__WEIGHT_LDS_SIG4__SHIFT 0x0 |
28467 | #define SE_CAC_WEIGHT_LDS_2__WEIGHT_LDS_SIG5__SHIFT 0x10 |
28468 | #define SE_CAC_WEIGHT_LDS_2__WEIGHT_LDS_SIG4_MASK 0x0000FFFFL |
28469 | #define SE_CAC_WEIGHT_LDS_2__WEIGHT_LDS_SIG5_MASK 0xFFFF0000L |
28470 | //SE_CAC_WEIGHT_LDS_3 |
28471 | #define SE_CAC_WEIGHT_LDS_3__WEIGHT_LDS_SIG6__SHIFT 0x0 |
28472 | #define SE_CAC_WEIGHT_LDS_3__WEIGHT_LDS_SIG7__SHIFT 0x10 |
28473 | #define SE_CAC_WEIGHT_LDS_3__WEIGHT_LDS_SIG6_MASK 0x0000FFFFL |
28474 | #define SE_CAC_WEIGHT_LDS_3__WEIGHT_LDS_SIG7_MASK 0xFFFF0000L |
28475 | //SE_CAC_WEIGHT_SQC_0 |
28476 | #define SE_CAC_WEIGHT_SQC_0__WEIGHT_SQC_SIG0__SHIFT 0x0 |
28477 | #define SE_CAC_WEIGHT_SQC_0__WEIGHT_SQC_SIG1__SHIFT 0x10 |
28478 | #define SE_CAC_WEIGHT_SQC_0__WEIGHT_SQC_SIG0_MASK 0x0000FFFFL |
28479 | #define SE_CAC_WEIGHT_SQC_0__WEIGHT_SQC_SIG1_MASK 0xFFFF0000L |
28480 | //SE_CAC_WEIGHT_SQC_1 |
28481 | #define SE_CAC_WEIGHT_SQC_1__WEIGHT_SQC_SIG2__SHIFT 0x0 |
28482 | #define SE_CAC_WEIGHT_SQC_1__WEIGHT_SQC_SIG2_MASK 0x0000FFFFL |
28483 | //SE_CAC_WEIGHT_CU_0 |
28484 | #define SE_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG0__SHIFT 0x0 |
28485 | #define SE_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG0_MASK 0x0000FFFFL |
28486 | //SE_CAC_WEIGHT_BCI_0 |
28487 | #define SE_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG0__SHIFT 0x0 |
28488 | #define SE_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG1__SHIFT 0x10 |
28489 | #define SE_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG0_MASK 0x0000FFFFL |
28490 | #define SE_CAC_WEIGHT_BCI_0__WEIGHT_BCI_SIG1_MASK 0xFFFF0000L |
28491 | //SE_CAC_WEIGHT_CB_0 |
28492 | #define SE_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG0__SHIFT 0x0 |
28493 | #define SE_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG1__SHIFT 0x10 |
28494 | #define SE_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG0_MASK 0x0000FFFFL |
28495 | #define SE_CAC_WEIGHT_CB_0__WEIGHT_CB_SIG1_MASK 0xFFFF0000L |
28496 | //SE_CAC_WEIGHT_CB_1 |
28497 | #define SE_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG2__SHIFT 0x0 |
28498 | #define SE_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG3__SHIFT 0x10 |
28499 | #define SE_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG2_MASK 0x0000FFFFL |
28500 | #define SE_CAC_WEIGHT_CB_1__WEIGHT_CB_SIG3_MASK 0xFFFF0000L |
28501 | //SE_CAC_WEIGHT_CB_2 |
28502 | #define SE_CAC_WEIGHT_CB_2__WEIGHT_CB_SIG4__SHIFT 0x0 |
28503 | #define SE_CAC_WEIGHT_CB_2__WEIGHT_CB_SIG5__SHIFT 0x10 |
28504 | #define SE_CAC_WEIGHT_CB_2__WEIGHT_CB_SIG4_MASK 0x0000FFFFL |
28505 | #define SE_CAC_WEIGHT_CB_2__WEIGHT_CB_SIG5_MASK 0xFFFF0000L |
28506 | //SE_CAC_WEIGHT_CB_3 |
28507 | #define SE_CAC_WEIGHT_CB_3__WEIGHT_CB_SIG6__SHIFT 0x0 |
28508 | #define SE_CAC_WEIGHT_CB_3__WEIGHT_CB_SIG7__SHIFT 0x10 |
28509 | #define SE_CAC_WEIGHT_CB_3__WEIGHT_CB_SIG6_MASK 0x0000FFFFL |
28510 | #define SE_CAC_WEIGHT_CB_3__WEIGHT_CB_SIG7_MASK 0xFFFF0000L |
28511 | //SE_CAC_WEIGHT_CB_4 |
28512 | #define SE_CAC_WEIGHT_CB_4__WEIGHT_CB_SIG8__SHIFT 0x0 |
28513 | #define SE_CAC_WEIGHT_CB_4__WEIGHT_CB_SIG9__SHIFT 0x10 |
28514 | #define SE_CAC_WEIGHT_CB_4__WEIGHT_CB_SIG8_MASK 0x0000FFFFL |
28515 | #define SE_CAC_WEIGHT_CB_4__WEIGHT_CB_SIG9_MASK 0xFFFF0000L |
28516 | //SE_CAC_WEIGHT_CB_5 |
28517 | #define SE_CAC_WEIGHT_CB_5__WEIGHT_CB_SIG10__SHIFT 0x0 |
28518 | #define SE_CAC_WEIGHT_CB_5__WEIGHT_CB_SIG11__SHIFT 0x10 |
28519 | #define SE_CAC_WEIGHT_CB_5__WEIGHT_CB_SIG10_MASK 0x0000FFFFL |
28520 | #define SE_CAC_WEIGHT_CB_5__WEIGHT_CB_SIG11_MASK 0xFFFF0000L |
28521 | //SE_CAC_WEIGHT_CB_6 |
28522 | #define SE_CAC_WEIGHT_CB_6__WEIGHT_CB_SIG12__SHIFT 0x0 |
28523 | #define SE_CAC_WEIGHT_CB_6__WEIGHT_CB_SIG13__SHIFT 0x10 |
28524 | #define SE_CAC_WEIGHT_CB_6__WEIGHT_CB_SIG12_MASK 0x0000FFFFL |
28525 | #define SE_CAC_WEIGHT_CB_6__WEIGHT_CB_SIG13_MASK 0xFFFF0000L |
28526 | //SE_CAC_WEIGHT_CB_7 |
28527 | #define SE_CAC_WEIGHT_CB_7__WEIGHT_CB_SIG14__SHIFT 0x0 |
28528 | #define SE_CAC_WEIGHT_CB_7__WEIGHT_CB_SIG15__SHIFT 0x10 |
28529 | #define SE_CAC_WEIGHT_CB_7__WEIGHT_CB_SIG14_MASK 0x0000FFFFL |
28530 | #define SE_CAC_WEIGHT_CB_7__WEIGHT_CB_SIG15_MASK 0xFFFF0000L |
28531 | //SE_CAC_WEIGHT_CB_8 |
28532 | #define SE_CAC_WEIGHT_CB_8__WEIGHT_CB_SIG16__SHIFT 0x0 |
28533 | #define SE_CAC_WEIGHT_CB_8__WEIGHT_CB_SIG17__SHIFT 0x10 |
28534 | #define SE_CAC_WEIGHT_CB_8__WEIGHT_CB_SIG16_MASK 0x0000FFFFL |
28535 | #define SE_CAC_WEIGHT_CB_8__WEIGHT_CB_SIG17_MASK 0xFFFF0000L |
28536 | //SE_CAC_WEIGHT_CB_9 |
28537 | #define SE_CAC_WEIGHT_CB_9__WEIGHT_CB_SIG18__SHIFT 0x0 |
28538 | #define SE_CAC_WEIGHT_CB_9__WEIGHT_CB_SIG19__SHIFT 0x10 |
28539 | #define SE_CAC_WEIGHT_CB_9__WEIGHT_CB_SIG18_MASK 0x0000FFFFL |
28540 | #define SE_CAC_WEIGHT_CB_9__WEIGHT_CB_SIG19_MASK 0xFFFF0000L |
28541 | //SE_CAC_WEIGHT_CB_10 |
28542 | #define SE_CAC_WEIGHT_CB_10__WEIGHT_CB_SIG20__SHIFT 0x0 |
28543 | #define SE_CAC_WEIGHT_CB_10__WEIGHT_CB_SIG21__SHIFT 0x10 |
28544 | #define SE_CAC_WEIGHT_CB_10__WEIGHT_CB_SIG20_MASK 0x0000FFFFL |
28545 | #define SE_CAC_WEIGHT_CB_10__WEIGHT_CB_SIG21_MASK 0xFFFF0000L |
28546 | //SE_CAC_WEIGHT_CB_11 |
28547 | #define SE_CAC_WEIGHT_CB_11__WEIGHT_CB_SIG22__SHIFT 0x0 |
28548 | #define SE_CAC_WEIGHT_CB_11__WEIGHT_CB_SIG23__SHIFT 0x10 |
28549 | #define SE_CAC_WEIGHT_CB_11__WEIGHT_CB_SIG22_MASK 0x0000FFFFL |
28550 | #define SE_CAC_WEIGHT_CB_11__WEIGHT_CB_SIG23_MASK 0xFFFF0000L |
28551 | //SE_CAC_WEIGHT_DB_0 |
28552 | #define SE_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG0__SHIFT 0x0 |
28553 | #define SE_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG1__SHIFT 0x10 |
28554 | #define SE_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG0_MASK 0x0000FFFFL |
28555 | #define SE_CAC_WEIGHT_DB_0__WEIGHT_DB_SIG1_MASK 0xFFFF0000L |
28556 | //SE_CAC_WEIGHT_DB_1 |
28557 | #define SE_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG2__SHIFT 0x0 |
28558 | #define SE_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG3__SHIFT 0x10 |
28559 | #define SE_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG2_MASK 0x0000FFFFL |
28560 | #define SE_CAC_WEIGHT_DB_1__WEIGHT_DB_SIG3_MASK 0xFFFF0000L |
28561 | //SE_CAC_WEIGHT_DB_2 |
28562 | #define SE_CAC_WEIGHT_DB_2__WEIGHT_DB_SIG4__SHIFT 0x0 |
28563 | #define SE_CAC_WEIGHT_DB_2__WEIGHT_DB_SIG5__SHIFT 0x10 |
28564 | #define SE_CAC_WEIGHT_DB_2__WEIGHT_DB_SIG4_MASK 0x0000FFFFL |
28565 | #define SE_CAC_WEIGHT_DB_2__WEIGHT_DB_SIG5_MASK 0xFFFF0000L |
28566 | //SE_CAC_WEIGHT_DB_3 |
28567 | #define SE_CAC_WEIGHT_DB_3__WEIGHT_DB_SIG6__SHIFT 0x0 |
28568 | #define SE_CAC_WEIGHT_DB_3__WEIGHT_DB_SIG7__SHIFT 0x10 |
28569 | #define SE_CAC_WEIGHT_DB_3__WEIGHT_DB_SIG6_MASK 0x0000FFFFL |
28570 | #define SE_CAC_WEIGHT_DB_3__WEIGHT_DB_SIG7_MASK 0xFFFF0000L |
28571 | //SE_CAC_WEIGHT_DB_4 |
28572 | #define SE_CAC_WEIGHT_DB_4__WEIGHT_DB_SIG8__SHIFT 0x0 |
28573 | #define SE_CAC_WEIGHT_DB_4__WEIGHT_DB_SIG9__SHIFT 0x10 |
28574 | #define SE_CAC_WEIGHT_DB_4__WEIGHT_DB_SIG8_MASK 0x0000FFFFL |
28575 | #define SE_CAC_WEIGHT_DB_4__WEIGHT_DB_SIG9_MASK 0xFFFF0000L |
28576 | //SE_CAC_WEIGHT_RMI_0 |
28577 | #define SE_CAC_WEIGHT_RMI_0__WEIGHT_RMI_SIG0__SHIFT 0x0 |
28578 | #define SE_CAC_WEIGHT_RMI_0__WEIGHT_RMI_SIG1__SHIFT 0x10 |
28579 | #define SE_CAC_WEIGHT_RMI_0__WEIGHT_RMI_SIG0_MASK 0x0000FFFFL |
28580 | #define SE_CAC_WEIGHT_RMI_0__WEIGHT_RMI_SIG1_MASK 0xFFFF0000L |
28581 | //SE_CAC_WEIGHT_RMI_1 |
28582 | #define SE_CAC_WEIGHT_RMI_1__WEIGHT_RMI_SIG2__SHIFT 0x0 |
28583 | #define SE_CAC_WEIGHT_RMI_1__WEIGHT_RMI_SIG3__SHIFT 0x10 |
28584 | #define SE_CAC_WEIGHT_RMI_1__WEIGHT_RMI_SIG2_MASK 0x0000FFFFL |
28585 | #define SE_CAC_WEIGHT_RMI_1__WEIGHT_RMI_SIG3_MASK 0xFFFF0000L |
28586 | //SE_CAC_WEIGHT_SX_0 |
28587 | #define SE_CAC_WEIGHT_SX_0__WEIGHT_SX_SIG0__SHIFT 0x0 |
28588 | #define SE_CAC_WEIGHT_SX_0__WEIGHT_SX_SIG0_MASK 0x0000FFFFL |
28589 | //SE_CAC_WEIGHT_SXRB_0 |
28590 | #define SE_CAC_WEIGHT_SXRB_0__WEIGHT_SXRB_SIG0__SHIFT 0x0 |
28591 | #define SE_CAC_WEIGHT_SXRB_0__WEIGHT_SXRB_SIG0_MASK 0x0000FFFFL |
28592 | //SE_CAC_WEIGHT_UTCL1_0 |
28593 | #define SE_CAC_WEIGHT_UTCL1_0__WEIGHT_UTCL1_SIG0__SHIFT 0x0 |
28594 | #define SE_CAC_WEIGHT_UTCL1_0__WEIGHT_UTCL1_SIG0_MASK 0x0000FFFFL |
28595 | //SE_CAC_WEIGHT_GL1C_0 |
28596 | #define SE_CAC_WEIGHT_GL1C_0__WEIGHT_GL1C_SIG0__SHIFT 0x0 |
28597 | #define SE_CAC_WEIGHT_GL1C_0__WEIGHT_GL1C_SIG1__SHIFT 0x10 |
28598 | #define SE_CAC_WEIGHT_GL1C_0__WEIGHT_GL1C_SIG0_MASK 0x0000FFFFL |
28599 | #define SE_CAC_WEIGHT_GL1C_0__WEIGHT_GL1C_SIG1_MASK 0xFFFF0000L |
28600 | //SE_CAC_WEIGHT_GL1C_1 |
28601 | #define SE_CAC_WEIGHT_GL1C_1__WEIGHT_GL1C_SIG2__SHIFT 0x0 |
28602 | #define SE_CAC_WEIGHT_GL1C_1__WEIGHT_GL1C_SIG3__SHIFT 0x10 |
28603 | #define SE_CAC_WEIGHT_GL1C_1__WEIGHT_GL1C_SIG2_MASK 0x0000FFFFL |
28604 | #define SE_CAC_WEIGHT_GL1C_1__WEIGHT_GL1C_SIG3_MASK 0xFFFF0000L |
28605 | //SE_CAC_WEIGHT_GL1C_2 |
28606 | #define SE_CAC_WEIGHT_GL1C_2__WEIGHT_GL1C_SIG4__SHIFT 0x0 |
28607 | #define SE_CAC_WEIGHT_GL1C_2__WEIGHT_GL1C_SIG4_MASK 0x0000FFFFL |
28608 | //SE_CAC_WEIGHT_SPI_0 |
28609 | #define SE_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG0__SHIFT 0x0 |
28610 | #define SE_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG1__SHIFT 0x10 |
28611 | #define SE_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG0_MASK 0x0000FFFFL |
28612 | #define SE_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG1_MASK 0xFFFF0000L |
28613 | //SE_CAC_WEIGHT_SPI_1 |
28614 | #define SE_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG2__SHIFT 0x0 |
28615 | #define SE_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG3__SHIFT 0x10 |
28616 | #define SE_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG2_MASK 0x0000FFFFL |
28617 | #define SE_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG3_MASK 0xFFFF0000L |
28618 | //SE_CAC_WEIGHT_SPI_2 |
28619 | #define SE_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG4__SHIFT 0x0 |
28620 | #define SE_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG4_MASK 0x0000FFFFL |
28621 | //SE_CAC_WEIGHT_PC_0 |
28622 | #define SE_CAC_WEIGHT_PC_0__WEIGHT_PC_SIG0__SHIFT 0x0 |
28623 | #define SE_CAC_WEIGHT_PC_0__WEIGHT_PC_SIG0_MASK 0x0000FFFFL |
28624 | //SE_CAC_WEIGHT_PA_0 |
28625 | #define SE_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG0__SHIFT 0x0 |
28626 | #define SE_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG1__SHIFT 0x10 |
28627 | #define SE_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG0_MASK 0x0000FFFFL |
28628 | #define SE_CAC_WEIGHT_PA_0__WEIGHT_PA_SIG1_MASK 0xFFFF0000L |
28629 | //SE_CAC_WEIGHT_PA_1 |
28630 | #define SE_CAC_WEIGHT_PA_1__WEIGHT_PA_SIG2__SHIFT 0x0 |
28631 | #define SE_CAC_WEIGHT_PA_1__WEIGHT_PA_SIG3__SHIFT 0x10 |
28632 | #define SE_CAC_WEIGHT_PA_1__WEIGHT_PA_SIG2_MASK 0x0000FFFFL |
28633 | #define SE_CAC_WEIGHT_PA_1__WEIGHT_PA_SIG3_MASK 0xFFFF0000L |
28634 | //SE_CAC_WEIGHT_PA_2 |
28635 | #define SE_CAC_WEIGHT_PA_2__WEIGHT_PA_SIG4__SHIFT 0x0 |
28636 | #define SE_CAC_WEIGHT_PA_2__WEIGHT_PA_SIG5__SHIFT 0x10 |
28637 | #define SE_CAC_WEIGHT_PA_2__WEIGHT_PA_SIG4_MASK 0x0000FFFFL |
28638 | #define SE_CAC_WEIGHT_PA_2__WEIGHT_PA_SIG5_MASK 0xFFFF0000L |
28639 | //SE_CAC_WEIGHT_PA_3 |
28640 | #define SE_CAC_WEIGHT_PA_3__WEIGHT_PA_SIG6__SHIFT 0x0 |
28641 | #define SE_CAC_WEIGHT_PA_3__WEIGHT_PA_SIG7__SHIFT 0x10 |
28642 | #define SE_CAC_WEIGHT_PA_3__WEIGHT_PA_SIG6_MASK 0x0000FFFFL |
28643 | #define SE_CAC_WEIGHT_PA_3__WEIGHT_PA_SIG7_MASK 0xFFFF0000L |
28644 | //SE_CAC_WEIGHT_SC_0 |
28645 | #define SE_CAC_WEIGHT_SC_0__WEIGHT_SC_SIG0__SHIFT 0x0 |
28646 | #define SE_CAC_WEIGHT_SC_0__WEIGHT_SC_SIG1__SHIFT 0x10 |
28647 | #define SE_CAC_WEIGHT_SC_0__WEIGHT_SC_SIG0_MASK 0x0000FFFFL |
28648 | #define SE_CAC_WEIGHT_SC_0__WEIGHT_SC_SIG1_MASK 0xFFFF0000L |
28649 | //SE_CAC_WEIGHT_SC_1 |
28650 | #define SE_CAC_WEIGHT_SC_1__WEIGHT_SC_SIG2__SHIFT 0x0 |
28651 | #define SE_CAC_WEIGHT_SC_1__WEIGHT_SC_SIG3__SHIFT 0x10 |
28652 | #define SE_CAC_WEIGHT_SC_1__WEIGHT_SC_SIG2_MASK 0x0000FFFFL |
28653 | #define SE_CAC_WEIGHT_SC_1__WEIGHT_SC_SIG3_MASK 0xFFFF0000L |
28654 | //SE_CAC_WEIGHT_SC_2 |
28655 | #define SE_CAC_WEIGHT_SC_2__WEIGHT_SC_SIG4__SHIFT 0x0 |
28656 | #define SE_CAC_WEIGHT_SC_2__WEIGHT_SC_SIG5__SHIFT 0x10 |
28657 | #define SE_CAC_WEIGHT_SC_2__WEIGHT_SC_SIG4_MASK 0x0000FFFFL |
28658 | #define SE_CAC_WEIGHT_SC_2__WEIGHT_SC_SIG5_MASK 0xFFFF0000L |
28659 | //SE_CAC_WEIGHT_SC_3 |
28660 | #define SE_CAC_WEIGHT_SC_3__WEIGHT_SC_SIG6__SHIFT 0x0 |
28661 | #define SE_CAC_WEIGHT_SC_3__WEIGHT_SC_SIG7__SHIFT 0x10 |
28662 | #define SE_CAC_WEIGHT_SC_3__WEIGHT_SC_SIG6_MASK 0x0000FFFFL |
28663 | #define SE_CAC_WEIGHT_SC_3__WEIGHT_SC_SIG7_MASK 0xFFFF0000L |
28664 | //SE_CAC_WINDOW_AGGR_VALUE |
28665 | #define SE_CAC_WINDOW_AGGR_VALUE__SE_CAC_WINDOW_AGGR_VALUE__SHIFT 0x0 |
28666 | #define SE_CAC_WINDOW_AGGR_VALUE__SE_CAC_WINDOW_AGGR_VALUE_MASK 0xFFFFFFFFL |
28667 | //SE_CAC_WINDOW_GFXCLK_CYCLE |
28668 | #define SE_CAC_WINDOW_GFXCLK_CYCLE__SE_CAC_WINDOW_GFXCLK_CYCLE__SHIFT 0x0 |
28669 | #define SE_CAC_WINDOW_GFXCLK_CYCLE__SE_CAC_WINDOW_GFXCLK_CYCLE_MASK 0x000003FFL |
28670 | //SE_CAC_IND_INDEX |
28671 | #define SE_CAC_IND_INDEX__SE_CAC_IND_ADDR__SHIFT 0x0 |
28672 | #define SE_CAC_IND_INDEX__SE_CAC_IND_ADDR_MASK 0xFFFFFFFFL |
28673 | //SE_CAC_IND_DATA |
28674 | #define SE_CAC_IND_DATA__SE_CAC_IND_DATA__SHIFT 0x0 |
28675 | #define SE_CAC_IND_DATA__SE_CAC_IND_DATA_MASK 0xFFFFFFFFL |
28676 | |
28677 | |
28678 | // addressBlock: gc_pfonly2_spidec |
28679 | //SPI_RESOURCE_RESERVE_CU_0 |
28680 | #define SPI_RESOURCE_RESERVE_CU_0__VGPR__SHIFT 0x0 |
28681 | #define SPI_RESOURCE_RESERVE_CU_0__SGPR__SHIFT 0x4 |
28682 | #define SPI_RESOURCE_RESERVE_CU_0__LDS__SHIFT 0x8 |
28683 | #define SPI_RESOURCE_RESERVE_CU_0__WAVES__SHIFT 0xc |
28684 | #define SPI_RESOURCE_RESERVE_CU_0__BARRIERS__SHIFT 0xf |
28685 | #define SPI_RESOURCE_RESERVE_CU_0__VGPR_MASK 0x0000000FL |
28686 | #define SPI_RESOURCE_RESERVE_CU_0__SGPR_MASK 0x000000F0L |
28687 | #define SPI_RESOURCE_RESERVE_CU_0__LDS_MASK 0x00000F00L |
28688 | #define SPI_RESOURCE_RESERVE_CU_0__WAVES_MASK 0x00007000L |
28689 | #define SPI_RESOURCE_RESERVE_CU_0__BARRIERS_MASK 0x00078000L |
28690 | //SPI_RESOURCE_RESERVE_CU_1 |
28691 | #define SPI_RESOURCE_RESERVE_CU_1__VGPR__SHIFT 0x0 |
28692 | #define SPI_RESOURCE_RESERVE_CU_1__SGPR__SHIFT 0x4 |
28693 | #define SPI_RESOURCE_RESERVE_CU_1__LDS__SHIFT 0x8 |
28694 | #define SPI_RESOURCE_RESERVE_CU_1__WAVES__SHIFT 0xc |
28695 | #define SPI_RESOURCE_RESERVE_CU_1__BARRIERS__SHIFT 0xf |
28696 | #define SPI_RESOURCE_RESERVE_CU_1__VGPR_MASK 0x0000000FL |
28697 | #define SPI_RESOURCE_RESERVE_CU_1__SGPR_MASK 0x000000F0L |
28698 | #define SPI_RESOURCE_RESERVE_CU_1__LDS_MASK 0x00000F00L |
28699 | #define SPI_RESOURCE_RESERVE_CU_1__WAVES_MASK 0x00007000L |
28700 | #define SPI_RESOURCE_RESERVE_CU_1__BARRIERS_MASK 0x00078000L |
28701 | //SPI_RESOURCE_RESERVE_CU_2 |
28702 | #define SPI_RESOURCE_RESERVE_CU_2__VGPR__SHIFT 0x0 |
28703 | #define SPI_RESOURCE_RESERVE_CU_2__SGPR__SHIFT 0x4 |
28704 | #define SPI_RESOURCE_RESERVE_CU_2__LDS__SHIFT 0x8 |
28705 | #define SPI_RESOURCE_RESERVE_CU_2__WAVES__SHIFT 0xc |
28706 | #define SPI_RESOURCE_RESERVE_CU_2__BARRIERS__SHIFT 0xf |
28707 | #define SPI_RESOURCE_RESERVE_CU_2__VGPR_MASK 0x0000000FL |
28708 | #define SPI_RESOURCE_RESERVE_CU_2__SGPR_MASK 0x000000F0L |
28709 | #define SPI_RESOURCE_RESERVE_CU_2__LDS_MASK 0x00000F00L |
28710 | #define SPI_RESOURCE_RESERVE_CU_2__WAVES_MASK 0x00007000L |
28711 | #define SPI_RESOURCE_RESERVE_CU_2__BARRIERS_MASK 0x00078000L |
28712 | //SPI_RESOURCE_RESERVE_CU_3 |
28713 | #define SPI_RESOURCE_RESERVE_CU_3__VGPR__SHIFT 0x0 |
28714 | #define SPI_RESOURCE_RESERVE_CU_3__SGPR__SHIFT 0x4 |
28715 | #define SPI_RESOURCE_RESERVE_CU_3__LDS__SHIFT 0x8 |
28716 | #define SPI_RESOURCE_RESERVE_CU_3__WAVES__SHIFT 0xc |
28717 | #define SPI_RESOURCE_RESERVE_CU_3__BARRIERS__SHIFT 0xf |
28718 | #define SPI_RESOURCE_RESERVE_CU_3__VGPR_MASK 0x0000000FL |
28719 | #define SPI_RESOURCE_RESERVE_CU_3__SGPR_MASK 0x000000F0L |
28720 | #define SPI_RESOURCE_RESERVE_CU_3__LDS_MASK 0x00000F00L |
28721 | #define SPI_RESOURCE_RESERVE_CU_3__WAVES_MASK 0x00007000L |
28722 | #define SPI_RESOURCE_RESERVE_CU_3__BARRIERS_MASK 0x00078000L |
28723 | //SPI_RESOURCE_RESERVE_CU_4 |
28724 | #define SPI_RESOURCE_RESERVE_CU_4__VGPR__SHIFT 0x0 |
28725 | #define SPI_RESOURCE_RESERVE_CU_4__SGPR__SHIFT 0x4 |
28726 | #define SPI_RESOURCE_RESERVE_CU_4__LDS__SHIFT 0x8 |
28727 | #define SPI_RESOURCE_RESERVE_CU_4__WAVES__SHIFT 0xc |
28728 | #define SPI_RESOURCE_RESERVE_CU_4__BARRIERS__SHIFT 0xf |
28729 | #define SPI_RESOURCE_RESERVE_CU_4__VGPR_MASK 0x0000000FL |
28730 | #define SPI_RESOURCE_RESERVE_CU_4__SGPR_MASK 0x000000F0L |
28731 | #define SPI_RESOURCE_RESERVE_CU_4__LDS_MASK 0x00000F00L |
28732 | #define SPI_RESOURCE_RESERVE_CU_4__WAVES_MASK 0x00007000L |
28733 | #define SPI_RESOURCE_RESERVE_CU_4__BARRIERS_MASK 0x00078000L |
28734 | //SPI_RESOURCE_RESERVE_CU_5 |
28735 | #define SPI_RESOURCE_RESERVE_CU_5__VGPR__SHIFT 0x0 |
28736 | #define SPI_RESOURCE_RESERVE_CU_5__SGPR__SHIFT 0x4 |
28737 | #define SPI_RESOURCE_RESERVE_CU_5__LDS__SHIFT 0x8 |
28738 | #define SPI_RESOURCE_RESERVE_CU_5__WAVES__SHIFT 0xc |
28739 | #define SPI_RESOURCE_RESERVE_CU_5__BARRIERS__SHIFT 0xf |
28740 | #define SPI_RESOURCE_RESERVE_CU_5__VGPR_MASK 0x0000000FL |
28741 | #define SPI_RESOURCE_RESERVE_CU_5__SGPR_MASK 0x000000F0L |
28742 | #define SPI_RESOURCE_RESERVE_CU_5__LDS_MASK 0x00000F00L |
28743 | #define SPI_RESOURCE_RESERVE_CU_5__WAVES_MASK 0x00007000L |
28744 | #define SPI_RESOURCE_RESERVE_CU_5__BARRIERS_MASK 0x00078000L |
28745 | //SPI_RESOURCE_RESERVE_CU_6 |
28746 | #define SPI_RESOURCE_RESERVE_CU_6__VGPR__SHIFT 0x0 |
28747 | #define SPI_RESOURCE_RESERVE_CU_6__SGPR__SHIFT 0x4 |
28748 | #define SPI_RESOURCE_RESERVE_CU_6__LDS__SHIFT 0x8 |
28749 | #define SPI_RESOURCE_RESERVE_CU_6__WAVES__SHIFT 0xc |
28750 | #define SPI_RESOURCE_RESERVE_CU_6__BARRIERS__SHIFT 0xf |
28751 | #define SPI_RESOURCE_RESERVE_CU_6__VGPR_MASK 0x0000000FL |
28752 | #define SPI_RESOURCE_RESERVE_CU_6__SGPR_MASK 0x000000F0L |
28753 | #define SPI_RESOURCE_RESERVE_CU_6__LDS_MASK 0x00000F00L |
28754 | #define SPI_RESOURCE_RESERVE_CU_6__WAVES_MASK 0x00007000L |
28755 | #define SPI_RESOURCE_RESERVE_CU_6__BARRIERS_MASK 0x00078000L |
28756 | //SPI_RESOURCE_RESERVE_CU_7 |
28757 | #define SPI_RESOURCE_RESERVE_CU_7__VGPR__SHIFT 0x0 |
28758 | #define SPI_RESOURCE_RESERVE_CU_7__SGPR__SHIFT 0x4 |
28759 | #define SPI_RESOURCE_RESERVE_CU_7__LDS__SHIFT 0x8 |
28760 | #define SPI_RESOURCE_RESERVE_CU_7__WAVES__SHIFT 0xc |
28761 | #define SPI_RESOURCE_RESERVE_CU_7__BARRIERS__SHIFT 0xf |
28762 | #define SPI_RESOURCE_RESERVE_CU_7__VGPR_MASK 0x0000000FL |
28763 | #define SPI_RESOURCE_RESERVE_CU_7__SGPR_MASK 0x000000F0L |
28764 | #define SPI_RESOURCE_RESERVE_CU_7__LDS_MASK 0x00000F00L |
28765 | #define SPI_RESOURCE_RESERVE_CU_7__WAVES_MASK 0x00007000L |
28766 | #define SPI_RESOURCE_RESERVE_CU_7__BARRIERS_MASK 0x00078000L |
28767 | //SPI_RESOURCE_RESERVE_CU_8 |
28768 | #define SPI_RESOURCE_RESERVE_CU_8__VGPR__SHIFT 0x0 |
28769 | #define SPI_RESOURCE_RESERVE_CU_8__SGPR__SHIFT 0x4 |
28770 | #define SPI_RESOURCE_RESERVE_CU_8__LDS__SHIFT 0x8 |
28771 | #define SPI_RESOURCE_RESERVE_CU_8__WAVES__SHIFT 0xc |
28772 | #define SPI_RESOURCE_RESERVE_CU_8__BARRIERS__SHIFT 0xf |
28773 | #define SPI_RESOURCE_RESERVE_CU_8__VGPR_MASK 0x0000000FL |
28774 | #define SPI_RESOURCE_RESERVE_CU_8__SGPR_MASK 0x000000F0L |
28775 | #define SPI_RESOURCE_RESERVE_CU_8__LDS_MASK 0x00000F00L |
28776 | #define SPI_RESOURCE_RESERVE_CU_8__WAVES_MASK 0x00007000L |
28777 | #define SPI_RESOURCE_RESERVE_CU_8__BARRIERS_MASK 0x00078000L |
28778 | //SPI_RESOURCE_RESERVE_CU_9 |
28779 | #define SPI_RESOURCE_RESERVE_CU_9__VGPR__SHIFT 0x0 |
28780 | #define SPI_RESOURCE_RESERVE_CU_9__SGPR__SHIFT 0x4 |
28781 | #define SPI_RESOURCE_RESERVE_CU_9__LDS__SHIFT 0x8 |
28782 | #define SPI_RESOURCE_RESERVE_CU_9__WAVES__SHIFT 0xc |
28783 | #define SPI_RESOURCE_RESERVE_CU_9__BARRIERS__SHIFT 0xf |
28784 | #define SPI_RESOURCE_RESERVE_CU_9__VGPR_MASK 0x0000000FL |
28785 | #define SPI_RESOURCE_RESERVE_CU_9__SGPR_MASK 0x000000F0L |
28786 | #define SPI_RESOURCE_RESERVE_CU_9__LDS_MASK 0x00000F00L |
28787 | #define SPI_RESOURCE_RESERVE_CU_9__WAVES_MASK 0x00007000L |
28788 | #define SPI_RESOURCE_RESERVE_CU_9__BARRIERS_MASK 0x00078000L |
28789 | //SPI_RESOURCE_RESERVE_CU_10 |
28790 | #define SPI_RESOURCE_RESERVE_CU_10__VGPR__SHIFT 0x0 |
28791 | #define SPI_RESOURCE_RESERVE_CU_10__SGPR__SHIFT 0x4 |
28792 | #define SPI_RESOURCE_RESERVE_CU_10__LDS__SHIFT 0x8 |
28793 | #define SPI_RESOURCE_RESERVE_CU_10__WAVES__SHIFT 0xc |
28794 | #define SPI_RESOURCE_RESERVE_CU_10__BARRIERS__SHIFT 0xf |
28795 | #define SPI_RESOURCE_RESERVE_CU_10__VGPR_MASK 0x0000000FL |
28796 | #define SPI_RESOURCE_RESERVE_CU_10__SGPR_MASK 0x000000F0L |
28797 | #define SPI_RESOURCE_RESERVE_CU_10__LDS_MASK 0x00000F00L |
28798 | #define SPI_RESOURCE_RESERVE_CU_10__WAVES_MASK 0x00007000L |
28799 | #define SPI_RESOURCE_RESERVE_CU_10__BARRIERS_MASK 0x00078000L |
28800 | //SPI_RESOURCE_RESERVE_CU_11 |
28801 | #define SPI_RESOURCE_RESERVE_CU_11__VGPR__SHIFT 0x0 |
28802 | #define SPI_RESOURCE_RESERVE_CU_11__SGPR__SHIFT 0x4 |
28803 | #define SPI_RESOURCE_RESERVE_CU_11__LDS__SHIFT 0x8 |
28804 | #define SPI_RESOURCE_RESERVE_CU_11__WAVES__SHIFT 0xc |
28805 | #define SPI_RESOURCE_RESERVE_CU_11__BARRIERS__SHIFT 0xf |
28806 | #define SPI_RESOURCE_RESERVE_CU_11__VGPR_MASK 0x0000000FL |
28807 | #define SPI_RESOURCE_RESERVE_CU_11__SGPR_MASK 0x000000F0L |
28808 | #define SPI_RESOURCE_RESERVE_CU_11__LDS_MASK 0x00000F00L |
28809 | #define SPI_RESOURCE_RESERVE_CU_11__WAVES_MASK 0x00007000L |
28810 | #define SPI_RESOURCE_RESERVE_CU_11__BARRIERS_MASK 0x00078000L |
28811 | //SPI_RESOURCE_RESERVE_CU_12 |
28812 | #define SPI_RESOURCE_RESERVE_CU_12__VGPR__SHIFT 0x0 |
28813 | #define SPI_RESOURCE_RESERVE_CU_12__SGPR__SHIFT 0x4 |
28814 | #define SPI_RESOURCE_RESERVE_CU_12__LDS__SHIFT 0x8 |
28815 | #define SPI_RESOURCE_RESERVE_CU_12__WAVES__SHIFT 0xc |
28816 | #define SPI_RESOURCE_RESERVE_CU_12__BARRIERS__SHIFT 0xf |
28817 | #define SPI_RESOURCE_RESERVE_CU_12__VGPR_MASK 0x0000000FL |
28818 | #define SPI_RESOURCE_RESERVE_CU_12__SGPR_MASK 0x000000F0L |
28819 | #define SPI_RESOURCE_RESERVE_CU_12__LDS_MASK 0x00000F00L |
28820 | #define SPI_RESOURCE_RESERVE_CU_12__WAVES_MASK 0x00007000L |
28821 | #define SPI_RESOURCE_RESERVE_CU_12__BARRIERS_MASK 0x00078000L |
28822 | //SPI_RESOURCE_RESERVE_CU_13 |
28823 | #define SPI_RESOURCE_RESERVE_CU_13__VGPR__SHIFT 0x0 |
28824 | #define SPI_RESOURCE_RESERVE_CU_13__SGPR__SHIFT 0x4 |
28825 | #define SPI_RESOURCE_RESERVE_CU_13__LDS__SHIFT 0x8 |
28826 | #define SPI_RESOURCE_RESERVE_CU_13__WAVES__SHIFT 0xc |
28827 | #define SPI_RESOURCE_RESERVE_CU_13__BARRIERS__SHIFT 0xf |
28828 | #define SPI_RESOURCE_RESERVE_CU_13__VGPR_MASK 0x0000000FL |
28829 | #define SPI_RESOURCE_RESERVE_CU_13__SGPR_MASK 0x000000F0L |
28830 | #define SPI_RESOURCE_RESERVE_CU_13__LDS_MASK 0x00000F00L |
28831 | #define SPI_RESOURCE_RESERVE_CU_13__WAVES_MASK 0x00007000L |
28832 | #define SPI_RESOURCE_RESERVE_CU_13__BARRIERS_MASK 0x00078000L |
28833 | //SPI_RESOURCE_RESERVE_CU_14 |
28834 | #define SPI_RESOURCE_RESERVE_CU_14__VGPR__SHIFT 0x0 |
28835 | #define SPI_RESOURCE_RESERVE_CU_14__SGPR__SHIFT 0x4 |
28836 | #define SPI_RESOURCE_RESERVE_CU_14__LDS__SHIFT 0x8 |
28837 | #define SPI_RESOURCE_RESERVE_CU_14__WAVES__SHIFT 0xc |
28838 | #define SPI_RESOURCE_RESERVE_CU_14__BARRIERS__SHIFT 0xf |
28839 | #define SPI_RESOURCE_RESERVE_CU_14__VGPR_MASK 0x0000000FL |
28840 | #define SPI_RESOURCE_RESERVE_CU_14__SGPR_MASK 0x000000F0L |
28841 | #define SPI_RESOURCE_RESERVE_CU_14__LDS_MASK 0x00000F00L |
28842 | #define SPI_RESOURCE_RESERVE_CU_14__WAVES_MASK 0x00007000L |
28843 | #define SPI_RESOURCE_RESERVE_CU_14__BARRIERS_MASK 0x00078000L |
28844 | //SPI_RESOURCE_RESERVE_CU_15 |
28845 | #define SPI_RESOURCE_RESERVE_CU_15__VGPR__SHIFT 0x0 |
28846 | #define SPI_RESOURCE_RESERVE_CU_15__SGPR__SHIFT 0x4 |
28847 | #define SPI_RESOURCE_RESERVE_CU_15__LDS__SHIFT 0x8 |
28848 | #define SPI_RESOURCE_RESERVE_CU_15__WAVES__SHIFT 0xc |
28849 | #define SPI_RESOURCE_RESERVE_CU_15__BARRIERS__SHIFT 0xf |
28850 | #define SPI_RESOURCE_RESERVE_CU_15__VGPR_MASK 0x0000000FL |
28851 | #define SPI_RESOURCE_RESERVE_CU_15__SGPR_MASK 0x000000F0L |
28852 | #define SPI_RESOURCE_RESERVE_CU_15__LDS_MASK 0x00000F00L |
28853 | #define SPI_RESOURCE_RESERVE_CU_15__WAVES_MASK 0x00007000L |
28854 | #define SPI_RESOURCE_RESERVE_CU_15__BARRIERS_MASK 0x00078000L |
28855 | //SPI_RESOURCE_RESERVE_EN_CU_0 |
28856 | #define SPI_RESOURCE_RESERVE_EN_CU_0__EN__SHIFT 0x0 |
28857 | #define SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK__SHIFT 0x1 |
28858 | #define SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK__SHIFT 0x10 |
28859 | #define SPI_RESOURCE_RESERVE_EN_CU_0__EN_MASK 0x00000001L |
28860 | #define SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK_MASK 0x0000FFFEL |
28861 | #define SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK_MASK 0x00FF0000L |
28862 | //SPI_RESOURCE_RESERVE_EN_CU_1 |
28863 | #define SPI_RESOURCE_RESERVE_EN_CU_1__EN__SHIFT 0x0 |
28864 | #define SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK__SHIFT 0x1 |
28865 | #define SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK__SHIFT 0x10 |
28866 | #define SPI_RESOURCE_RESERVE_EN_CU_1__EN_MASK 0x00000001L |
28867 | #define SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK_MASK 0x0000FFFEL |
28868 | #define SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK_MASK 0x00FF0000L |
28869 | //SPI_RESOURCE_RESERVE_EN_CU_2 |
28870 | #define SPI_RESOURCE_RESERVE_EN_CU_2__EN__SHIFT 0x0 |
28871 | #define SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK__SHIFT 0x1 |
28872 | #define SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK__SHIFT 0x10 |
28873 | #define SPI_RESOURCE_RESERVE_EN_CU_2__EN_MASK 0x00000001L |
28874 | #define SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK_MASK 0x0000FFFEL |
28875 | #define SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK_MASK 0x00FF0000L |
28876 | //SPI_RESOURCE_RESERVE_EN_CU_3 |
28877 | #define SPI_RESOURCE_RESERVE_EN_CU_3__EN__SHIFT 0x0 |
28878 | #define SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK__SHIFT 0x1 |
28879 | #define SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK__SHIFT 0x10 |
28880 | #define SPI_RESOURCE_RESERVE_EN_CU_3__EN_MASK 0x00000001L |
28881 | #define SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK_MASK 0x0000FFFEL |
28882 | #define SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK_MASK 0x00FF0000L |
28883 | //SPI_RESOURCE_RESERVE_EN_CU_4 |
28884 | #define SPI_RESOURCE_RESERVE_EN_CU_4__EN__SHIFT 0x0 |
28885 | #define SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK__SHIFT 0x1 |
28886 | #define SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK__SHIFT 0x10 |
28887 | #define SPI_RESOURCE_RESERVE_EN_CU_4__EN_MASK 0x00000001L |
28888 | #define SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK_MASK 0x0000FFFEL |
28889 | #define SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK_MASK 0x00FF0000L |
28890 | //SPI_RESOURCE_RESERVE_EN_CU_5 |
28891 | #define SPI_RESOURCE_RESERVE_EN_CU_5__EN__SHIFT 0x0 |
28892 | #define SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK__SHIFT 0x1 |
28893 | #define SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK__SHIFT 0x10 |
28894 | #define SPI_RESOURCE_RESERVE_EN_CU_5__EN_MASK 0x00000001L |
28895 | #define SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK_MASK 0x0000FFFEL |
28896 | #define SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK_MASK 0x00FF0000L |
28897 | //SPI_RESOURCE_RESERVE_EN_CU_6 |
28898 | #define SPI_RESOURCE_RESERVE_EN_CU_6__EN__SHIFT 0x0 |
28899 | #define SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK__SHIFT 0x1 |
28900 | #define SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK__SHIFT 0x10 |
28901 | #define SPI_RESOURCE_RESERVE_EN_CU_6__EN_MASK 0x00000001L |
28902 | #define SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK_MASK 0x0000FFFEL |
28903 | #define SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK_MASK 0x00FF0000L |
28904 | //SPI_RESOURCE_RESERVE_EN_CU_7 |
28905 | #define SPI_RESOURCE_RESERVE_EN_CU_7__EN__SHIFT 0x0 |
28906 | #define SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK__SHIFT 0x1 |
28907 | #define SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK__SHIFT 0x10 |
28908 | #define SPI_RESOURCE_RESERVE_EN_CU_7__EN_MASK 0x00000001L |
28909 | #define SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK_MASK 0x0000FFFEL |
28910 | #define SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK_MASK 0x00FF0000L |
28911 | //SPI_RESOURCE_RESERVE_EN_CU_8 |
28912 | #define SPI_RESOURCE_RESERVE_EN_CU_8__EN__SHIFT 0x0 |
28913 | #define SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK__SHIFT 0x1 |
28914 | #define SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK__SHIFT 0x10 |
28915 | #define SPI_RESOURCE_RESERVE_EN_CU_8__EN_MASK 0x00000001L |
28916 | #define SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK_MASK 0x0000FFFEL |
28917 | #define SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK_MASK 0x00FF0000L |
28918 | //SPI_RESOURCE_RESERVE_EN_CU_9 |
28919 | #define SPI_RESOURCE_RESERVE_EN_CU_9__EN__SHIFT 0x0 |
28920 | #define SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK__SHIFT 0x1 |
28921 | #define SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK__SHIFT 0x10 |
28922 | #define SPI_RESOURCE_RESERVE_EN_CU_9__EN_MASK 0x00000001L |
28923 | #define SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK_MASK 0x0000FFFEL |
28924 | #define SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK_MASK 0x00FF0000L |
28925 | //SPI_RESOURCE_RESERVE_EN_CU_10 |
28926 | #define SPI_RESOURCE_RESERVE_EN_CU_10__EN__SHIFT 0x0 |
28927 | #define SPI_RESOURCE_RESERVE_EN_CU_10__TYPE_MASK__SHIFT 0x1 |
28928 | #define SPI_RESOURCE_RESERVE_EN_CU_10__QUEUE_MASK__SHIFT 0x10 |
28929 | #define SPI_RESOURCE_RESERVE_EN_CU_10__EN_MASK 0x00000001L |
28930 | #define SPI_RESOURCE_RESERVE_EN_CU_10__TYPE_MASK_MASK 0x0000FFFEL |
28931 | #define SPI_RESOURCE_RESERVE_EN_CU_10__QUEUE_MASK_MASK 0x00FF0000L |
28932 | //SPI_RESOURCE_RESERVE_EN_CU_11 |
28933 | #define SPI_RESOURCE_RESERVE_EN_CU_11__EN__SHIFT 0x0 |
28934 | #define SPI_RESOURCE_RESERVE_EN_CU_11__TYPE_MASK__SHIFT 0x1 |
28935 | #define SPI_RESOURCE_RESERVE_EN_CU_11__QUEUE_MASK__SHIFT 0x10 |
28936 | #define SPI_RESOURCE_RESERVE_EN_CU_11__EN_MASK 0x00000001L |
28937 | #define SPI_RESOURCE_RESERVE_EN_CU_11__TYPE_MASK_MASK 0x0000FFFEL |
28938 | #define SPI_RESOURCE_RESERVE_EN_CU_11__QUEUE_MASK_MASK 0x00FF0000L |
28939 | //SPI_RESOURCE_RESERVE_EN_CU_12 |
28940 | #define SPI_RESOURCE_RESERVE_EN_CU_12__EN__SHIFT 0x0 |
28941 | #define SPI_RESOURCE_RESERVE_EN_CU_12__TYPE_MASK__SHIFT 0x1 |
28942 | #define SPI_RESOURCE_RESERVE_EN_CU_12__QUEUE_MASK__SHIFT 0x10 |
28943 | #define SPI_RESOURCE_RESERVE_EN_CU_12__EN_MASK 0x00000001L |
28944 | #define SPI_RESOURCE_RESERVE_EN_CU_12__TYPE_MASK_MASK 0x0000FFFEL |
28945 | #define SPI_RESOURCE_RESERVE_EN_CU_12__QUEUE_MASK_MASK 0x00FF0000L |
28946 | //SPI_RESOURCE_RESERVE_EN_CU_13 |
28947 | #define SPI_RESOURCE_RESERVE_EN_CU_13__EN__SHIFT 0x0 |
28948 | #define SPI_RESOURCE_RESERVE_EN_CU_13__TYPE_MASK__SHIFT 0x1 |
28949 | #define SPI_RESOURCE_RESERVE_EN_CU_13__QUEUE_MASK__SHIFT 0x10 |
28950 | #define SPI_RESOURCE_RESERVE_EN_CU_13__EN_MASK 0x00000001L |
28951 | #define SPI_RESOURCE_RESERVE_EN_CU_13__TYPE_MASK_MASK 0x0000FFFEL |
28952 | #define SPI_RESOURCE_RESERVE_EN_CU_13__QUEUE_MASK_MASK 0x00FF0000L |
28953 | //SPI_RESOURCE_RESERVE_EN_CU_14 |
28954 | #define SPI_RESOURCE_RESERVE_EN_CU_14__EN__SHIFT 0x0 |
28955 | #define SPI_RESOURCE_RESERVE_EN_CU_14__TYPE_MASK__SHIFT 0x1 |
28956 | #define SPI_RESOURCE_RESERVE_EN_CU_14__QUEUE_MASK__SHIFT 0x10 |
28957 | #define SPI_RESOURCE_RESERVE_EN_CU_14__EN_MASK 0x00000001L |
28958 | #define SPI_RESOURCE_RESERVE_EN_CU_14__TYPE_MASK_MASK 0x0000FFFEL |
28959 | #define SPI_RESOURCE_RESERVE_EN_CU_14__QUEUE_MASK_MASK 0x00FF0000L |
28960 | //SPI_RESOURCE_RESERVE_EN_CU_15 |
28961 | #define SPI_RESOURCE_RESERVE_EN_CU_15__EN__SHIFT 0x0 |
28962 | #define SPI_RESOURCE_RESERVE_EN_CU_15__TYPE_MASK__SHIFT 0x1 |
28963 | #define SPI_RESOURCE_RESERVE_EN_CU_15__QUEUE_MASK__SHIFT 0x10 |
28964 | #define SPI_RESOURCE_RESERVE_EN_CU_15__EN_MASK 0x00000001L |
28965 | #define SPI_RESOURCE_RESERVE_EN_CU_15__TYPE_MASK_MASK 0x0000FFFEL |
28966 | #define SPI_RESOURCE_RESERVE_EN_CU_15__QUEUE_MASK_MASK 0x00FF0000L |
28967 | |
28968 | |
28969 | // addressBlock: gc_gfxudec |
28970 | //CP_EOP_DONE_ADDR_LO |
28971 | #define CP_EOP_DONE_ADDR_LO__ADDR_LO__SHIFT 0x2 |
28972 | #define CP_EOP_DONE_ADDR_LO__ADDR_LO_MASK 0xFFFFFFFCL |
28973 | //CP_EOP_DONE_ADDR_HI |
28974 | #define CP_EOP_DONE_ADDR_HI__ADDR_HI__SHIFT 0x0 |
28975 | #define CP_EOP_DONE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL |
28976 | //CP_EOP_DONE_DATA_LO |
28977 | #define CP_EOP_DONE_DATA_LO__DATA_LO__SHIFT 0x0 |
28978 | #define CP_EOP_DONE_DATA_LO__DATA_LO_MASK 0xFFFFFFFFL |
28979 | //CP_EOP_DONE_DATA_HI |
28980 | #define CP_EOP_DONE_DATA_HI__DATA_HI__SHIFT 0x0 |
28981 | #define CP_EOP_DONE_DATA_HI__DATA_HI_MASK 0xFFFFFFFFL |
28982 | //CP_EOP_LAST_FENCE_LO |
28983 | #define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO__SHIFT 0x0 |
28984 | #define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO_MASK 0xFFFFFFFFL |
28985 | //CP_EOP_LAST_FENCE_HI |
28986 | #define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI__SHIFT 0x0 |
28987 | #define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI_MASK 0xFFFFFFFFL |
28988 | //CP_PIPE_STATS_ADDR_LO |
28989 | #define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO__SHIFT 0x2 |
28990 | #define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO_MASK 0xFFFFFFFCL |
28991 | //CP_PIPE_STATS_ADDR_HI |
28992 | #define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI__SHIFT 0x0 |
28993 | #define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI_MASK 0x0000FFFFL |
28994 | //CP_VGT_IAVERT_COUNT_LO |
28995 | #define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO__SHIFT 0x0 |
28996 | #define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO_MASK 0xFFFFFFFFL |
28997 | //CP_VGT_IAVERT_COUNT_HI |
28998 | #define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI__SHIFT 0x0 |
28999 | #define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI_MASK 0xFFFFFFFFL |
29000 | //CP_VGT_IAPRIM_COUNT_LO |
29001 | #define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO__SHIFT 0x0 |
29002 | #define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO_MASK 0xFFFFFFFFL |
29003 | //CP_VGT_IAPRIM_COUNT_HI |
29004 | #define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI__SHIFT 0x0 |
29005 | #define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI_MASK 0xFFFFFFFFL |
29006 | //CP_VGT_GSPRIM_COUNT_LO |
29007 | #define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO__SHIFT 0x0 |
29008 | #define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO_MASK 0xFFFFFFFFL |
29009 | //CP_VGT_GSPRIM_COUNT_HI |
29010 | #define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI__SHIFT 0x0 |
29011 | #define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI_MASK 0xFFFFFFFFL |
29012 | //CP_VGT_VSINVOC_COUNT_LO |
29013 | #define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO__SHIFT 0x0 |
29014 | #define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO_MASK 0xFFFFFFFFL |
29015 | //CP_VGT_VSINVOC_COUNT_HI |
29016 | #define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI__SHIFT 0x0 |
29017 | #define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI_MASK 0xFFFFFFFFL |
29018 | //CP_VGT_GSINVOC_COUNT_LO |
29019 | #define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO__SHIFT 0x0 |
29020 | #define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO_MASK 0xFFFFFFFFL |
29021 | //CP_VGT_GSINVOC_COUNT_HI |
29022 | #define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI__SHIFT 0x0 |
29023 | #define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI_MASK 0xFFFFFFFFL |
29024 | //CP_VGT_HSINVOC_COUNT_LO |
29025 | #define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO__SHIFT 0x0 |
29026 | #define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO_MASK 0xFFFFFFFFL |
29027 | //CP_VGT_HSINVOC_COUNT_HI |
29028 | #define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI__SHIFT 0x0 |
29029 | #define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI_MASK 0xFFFFFFFFL |
29030 | //CP_VGT_DSINVOC_COUNT_LO |
29031 | #define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO__SHIFT 0x0 |
29032 | #define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO_MASK 0xFFFFFFFFL |
29033 | //CP_VGT_DSINVOC_COUNT_HI |
29034 | #define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI__SHIFT 0x0 |
29035 | #define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI_MASK 0xFFFFFFFFL |
29036 | //CP_PA_CINVOC_COUNT_LO |
29037 | #define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO__SHIFT 0x0 |
29038 | #define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO_MASK 0xFFFFFFFFL |
29039 | //CP_PA_CINVOC_COUNT_HI |
29040 | #define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI__SHIFT 0x0 |
29041 | #define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI_MASK 0xFFFFFFFFL |
29042 | //CP_PA_CPRIM_COUNT_LO |
29043 | #define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO__SHIFT 0x0 |
29044 | #define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO_MASK 0xFFFFFFFFL |
29045 | //CP_PA_CPRIM_COUNT_HI |
29046 | #define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI__SHIFT 0x0 |
29047 | #define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI_MASK 0xFFFFFFFFL |
29048 | //CP_SC_PSINVOC_COUNT0_LO |
29049 | #define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO__SHIFT 0x0 |
29050 | #define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO_MASK 0xFFFFFFFFL |
29051 | //CP_SC_PSINVOC_COUNT0_HI |
29052 | #define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI__SHIFT 0x0 |
29053 | #define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI_MASK 0xFFFFFFFFL |
29054 | //CP_SC_PSINVOC_COUNT1_LO |
29055 | #define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE__SHIFT 0x0 |
29056 | #define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE_MASK 0xFFFFFFFFL |
29057 | //CP_SC_PSINVOC_COUNT1_HI |
29058 | #define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE__SHIFT 0x0 |
29059 | #define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE_MASK 0xFFFFFFFFL |
29060 | //CP_VGT_CSINVOC_COUNT_LO |
29061 | #define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO__SHIFT 0x0 |
29062 | #define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO_MASK 0xFFFFFFFFL |
29063 | //CP_VGT_CSINVOC_COUNT_HI |
29064 | #define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI__SHIFT 0x0 |
29065 | #define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI_MASK 0xFFFFFFFFL |
29066 | //CP_VGT_ASINVOC_COUNT_LO |
29067 | #define CP_VGT_ASINVOC_COUNT_LO__ASINVOC_COUNT_LO__SHIFT 0x0 |
29068 | #define CP_VGT_ASINVOC_COUNT_LO__ASINVOC_COUNT_LO_MASK 0xFFFFFFFFL |
29069 | //CP_VGT_ASINVOC_COUNT_HI |
29070 | #define CP_VGT_ASINVOC_COUNT_HI__ASINVOC_COUNT_HI__SHIFT 0x0 |
29071 | #define CP_VGT_ASINVOC_COUNT_HI__ASINVOC_COUNT_HI_MASK 0xFFFFFFFFL |
29072 | //CP_PIPE_STATS_CONTROL |
29073 | #define CP_PIPE_STATS_CONTROL__CACHE_POLICY__SHIFT 0x19 |
29074 | #define CP_PIPE_STATS_CONTROL__CACHE_POLICY_MASK 0x06000000L |
29075 | //SCRATCH_REG0 |
29076 | #define SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x0 |
29077 | #define SCRATCH_REG0__SCRATCH_REG0_MASK 0xFFFFFFFFL |
29078 | //SCRATCH_REG1 |
29079 | #define SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x0 |
29080 | #define SCRATCH_REG1__SCRATCH_REG1_MASK 0xFFFFFFFFL |
29081 | //SCRATCH_REG2 |
29082 | #define SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x0 |
29083 | #define SCRATCH_REG2__SCRATCH_REG2_MASK 0xFFFFFFFFL |
29084 | //SCRATCH_REG3 |
29085 | #define SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x0 |
29086 | #define SCRATCH_REG3__SCRATCH_REG3_MASK 0xFFFFFFFFL |
29087 | //SCRATCH_REG4 |
29088 | #define SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x0 |
29089 | #define SCRATCH_REG4__SCRATCH_REG4_MASK 0xFFFFFFFFL |
29090 | //SCRATCH_REG5 |
29091 | #define SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x0 |
29092 | #define SCRATCH_REG5__SCRATCH_REG5_MASK 0xFFFFFFFFL |
29093 | //SCRATCH_REG6 |
29094 | #define SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x0 |
29095 | #define SCRATCH_REG6__SCRATCH_REG6_MASK 0xFFFFFFFFL |
29096 | //SCRATCH_REG7 |
29097 | #define SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x0 |
29098 | #define SCRATCH_REG7__SCRATCH_REG7_MASK 0xFFFFFFFFL |
29099 | //SCRATCH_REG_ATOMIC |
29100 | #define SCRATCH_REG_ATOMIC__IMMED__SHIFT 0x0 |
29101 | #define SCRATCH_REG_ATOMIC__ID__SHIFT 0x18 |
29102 | #define SCRATCH_REG_ATOMIC__reserved27__SHIFT 0x1b |
29103 | #define SCRATCH_REG_ATOMIC__OP__SHIFT 0x1c |
29104 | #define SCRATCH_REG_ATOMIC__reserved31__SHIFT 0x1f |
29105 | #define SCRATCH_REG_ATOMIC__IMMED_MASK 0x00FFFFFFL |
29106 | #define SCRATCH_REG_ATOMIC__ID_MASK 0x07000000L |
29107 | #define SCRATCH_REG_ATOMIC__reserved27_MASK 0x08000000L |
29108 | #define SCRATCH_REG_ATOMIC__OP_MASK 0x70000000L |
29109 | #define SCRATCH_REG_ATOMIC__reserved31_MASK 0x80000000L |
29110 | //SCRATCH_REG_CMPSWAP_ATOMIC |
29111 | #define SCRATCH_REG_CMPSWAP_ATOMIC__IMMED_COMPARE__SHIFT 0x0 |
29112 | #define SCRATCH_REG_CMPSWAP_ATOMIC__IMMED_REPLACE__SHIFT 0xc |
29113 | #define SCRATCH_REG_CMPSWAP_ATOMIC__ID__SHIFT 0x18 |
29114 | #define SCRATCH_REG_CMPSWAP_ATOMIC__reserved27__SHIFT 0x1b |
29115 | #define SCRATCH_REG_CMPSWAP_ATOMIC__OP__SHIFT 0x1c |
29116 | #define SCRATCH_REG_CMPSWAP_ATOMIC__reserved31__SHIFT 0x1f |
29117 | #define SCRATCH_REG_CMPSWAP_ATOMIC__IMMED_COMPARE_MASK 0x00000FFFL |
29118 | #define SCRATCH_REG_CMPSWAP_ATOMIC__IMMED_REPLACE_MASK 0x00FFF000L |
29119 | #define SCRATCH_REG_CMPSWAP_ATOMIC__ID_MASK 0x07000000L |
29120 | #define SCRATCH_REG_CMPSWAP_ATOMIC__reserved27_MASK 0x08000000L |
29121 | #define SCRATCH_REG_CMPSWAP_ATOMIC__OP_MASK 0x70000000L |
29122 | #define SCRATCH_REG_CMPSWAP_ATOMIC__reserved31_MASK 0x80000000L |
29123 | //CP_APPEND_DDID_CNT |
29124 | #define CP_APPEND_DDID_CNT__DATA__SHIFT 0x0 |
29125 | #define CP_APPEND_DDID_CNT__DATA_MASK 0x000000FFL |
29126 | //CP_APPEND_DATA_HI |
29127 | #define CP_APPEND_DATA_HI__DATA__SHIFT 0x0 |
29128 | #define CP_APPEND_DATA_HI__DATA_MASK 0xFFFFFFFFL |
29129 | //CP_APPEND_LAST_CS_FENCE_HI |
29130 | #define CP_APPEND_LAST_CS_FENCE_HI__LAST_FENCE__SHIFT 0x0 |
29131 | #define CP_APPEND_LAST_CS_FENCE_HI__LAST_FENCE_MASK 0xFFFFFFFFL |
29132 | //CP_APPEND_LAST_PS_FENCE_HI |
29133 | #define CP_APPEND_LAST_PS_FENCE_HI__LAST_FENCE__SHIFT 0x0 |
29134 | #define CP_APPEND_LAST_PS_FENCE_HI__LAST_FENCE_MASK 0xFFFFFFFFL |
29135 | //CP_PFP_ATOMIC_PREOP_LO |
29136 | #define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0 |
29137 | #define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xFFFFFFFFL |
29138 | //CP_PFP_ATOMIC_PREOP_HI |
29139 | #define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0 |
29140 | #define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xFFFFFFFFL |
29141 | //CP_PFP_GDS_ATOMIC0_PREOP_LO |
29142 | #define CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0 |
29143 | #define CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xFFFFFFFFL |
29144 | //CP_PFP_GDS_ATOMIC0_PREOP_HI |
29145 | #define CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0 |
29146 | #define CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xFFFFFFFFL |
29147 | //CP_PFP_GDS_ATOMIC1_PREOP_LO |
29148 | #define CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0 |
29149 | #define CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xFFFFFFFFL |
29150 | //CP_PFP_GDS_ATOMIC1_PREOP_HI |
29151 | #define CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0 |
29152 | #define CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xFFFFFFFFL |
29153 | //CP_APPEND_ADDR_LO |
29154 | #define CP_APPEND_ADDR_LO__MEM_ADDR_LO__SHIFT 0x2 |
29155 | #define CP_APPEND_ADDR_LO__MEM_ADDR_LO_MASK 0xFFFFFFFCL |
29156 | //CP_APPEND_ADDR_HI |
29157 | #define CP_APPEND_ADDR_HI__MEM_ADDR_HI__SHIFT 0x0 |
29158 | #define CP_APPEND_ADDR_HI__CS_PS_SEL__SHIFT 0x10 |
29159 | #define CP_APPEND_ADDR_HI__FENCE_SIZE__SHIFT 0x12 |
29160 | #define CP_APPEND_ADDR_HI__PWS_ENABLE__SHIFT 0x13 |
29161 | #define CP_APPEND_ADDR_HI__CACHE_POLICY__SHIFT 0x19 |
29162 | #define CP_APPEND_ADDR_HI__COMMAND__SHIFT 0x1d |
29163 | #define CP_APPEND_ADDR_HI__MEM_ADDR_HI_MASK 0x0000FFFFL |
29164 | #define CP_APPEND_ADDR_HI__CS_PS_SEL_MASK 0x00030000L |
29165 | #define CP_APPEND_ADDR_HI__FENCE_SIZE_MASK 0x00040000L |
29166 | #define CP_APPEND_ADDR_HI__PWS_ENABLE_MASK 0x00080000L |
29167 | #define CP_APPEND_ADDR_HI__CACHE_POLICY_MASK 0x06000000L |
29168 | #define CP_APPEND_ADDR_HI__COMMAND_MASK 0xE0000000L |
29169 | //CP_APPEND_DATA |
29170 | #define CP_APPEND_DATA__DATA__SHIFT 0x0 |
29171 | #define CP_APPEND_DATA__DATA_MASK 0xFFFFFFFFL |
29172 | //CP_APPEND_DATA_LO |
29173 | #define CP_APPEND_DATA_LO__DATA__SHIFT 0x0 |
29174 | #define CP_APPEND_DATA_LO__DATA_MASK 0xFFFFFFFFL |
29175 | //CP_APPEND_LAST_CS_FENCE |
29176 | #define CP_APPEND_LAST_CS_FENCE__LAST_FENCE__SHIFT 0x0 |
29177 | #define CP_APPEND_LAST_CS_FENCE__LAST_FENCE_MASK 0xFFFFFFFFL |
29178 | //CP_APPEND_LAST_CS_FENCE_LO |
29179 | #define CP_APPEND_LAST_CS_FENCE_LO__LAST_FENCE__SHIFT 0x0 |
29180 | #define CP_APPEND_LAST_CS_FENCE_LO__LAST_FENCE_MASK 0xFFFFFFFFL |
29181 | //CP_APPEND_LAST_PS_FENCE |
29182 | #define CP_APPEND_LAST_PS_FENCE__LAST_FENCE__SHIFT 0x0 |
29183 | #define CP_APPEND_LAST_PS_FENCE__LAST_FENCE_MASK 0xFFFFFFFFL |
29184 | //CP_APPEND_LAST_PS_FENCE_LO |
29185 | #define CP_APPEND_LAST_PS_FENCE_LO__LAST_FENCE__SHIFT 0x0 |
29186 | #define CP_APPEND_LAST_PS_FENCE_LO__LAST_FENCE_MASK 0xFFFFFFFFL |
29187 | //CP_ATOMIC_PREOP_LO |
29188 | #define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0 |
29189 | #define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xFFFFFFFFL |
29190 | //CP_ME_ATOMIC_PREOP_LO |
29191 | #define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0 |
29192 | #define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xFFFFFFFFL |
29193 | //CP_ATOMIC_PREOP_HI |
29194 | #define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0 |
29195 | #define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xFFFFFFFFL |
29196 | //CP_ME_ATOMIC_PREOP_HI |
29197 | #define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0 |
29198 | #define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xFFFFFFFFL |
29199 | //CP_GDS_ATOMIC0_PREOP_LO |
29200 | #define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0 |
29201 | #define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xFFFFFFFFL |
29202 | //CP_ME_GDS_ATOMIC0_PREOP_LO |
29203 | #define CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0 |
29204 | #define CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xFFFFFFFFL |
29205 | //CP_GDS_ATOMIC0_PREOP_HI |
29206 | #define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0 |
29207 | #define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xFFFFFFFFL |
29208 | //CP_ME_GDS_ATOMIC0_PREOP_HI |
29209 | #define CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0 |
29210 | #define CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xFFFFFFFFL |
29211 | //CP_GDS_ATOMIC1_PREOP_LO |
29212 | #define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0 |
29213 | #define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xFFFFFFFFL |
29214 | //CP_ME_GDS_ATOMIC1_PREOP_LO |
29215 | #define CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0 |
29216 | #define CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xFFFFFFFFL |
29217 | //CP_GDS_ATOMIC1_PREOP_HI |
29218 | #define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0 |
29219 | #define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xFFFFFFFFL |
29220 | //CP_ME_GDS_ATOMIC1_PREOP_HI |
29221 | #define CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0 |
29222 | #define CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xFFFFFFFFL |
29223 | //CP_ME_MC_WADDR_LO |
29224 | #define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO__SHIFT 0x2 |
29225 | #define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO_MASK 0xFFFFFFFCL |
29226 | //CP_ME_MC_WADDR_HI |
29227 | #define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI__SHIFT 0x0 |
29228 | #define CP_ME_MC_WADDR_HI__WRITE_CONFIRM__SHIFT 0x11 |
29229 | #define CP_ME_MC_WADDR_HI__WRITE64__SHIFT 0x12 |
29230 | #define CP_ME_MC_WADDR_HI__CACHE_POLICY__SHIFT 0x16 |
29231 | #define CP_ME_MC_WADDR_HI__VMID__SHIFT 0x18 |
29232 | #define CP_ME_MC_WADDR_HI__RINGID__SHIFT 0x1c |
29233 | #define CP_ME_MC_WADDR_HI__PRIVILEGE__SHIFT 0x1f |
29234 | #define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI_MASK 0x0000FFFFL |
29235 | #define CP_ME_MC_WADDR_HI__WRITE_CONFIRM_MASK 0x00020000L |
29236 | #define CP_ME_MC_WADDR_HI__WRITE64_MASK 0x00040000L |
29237 | #define CP_ME_MC_WADDR_HI__CACHE_POLICY_MASK 0x00C00000L |
29238 | #define CP_ME_MC_WADDR_HI__VMID_MASK 0x0F000000L |
29239 | #define CP_ME_MC_WADDR_HI__RINGID_MASK 0x30000000L |
29240 | #define CP_ME_MC_WADDR_HI__PRIVILEGE_MASK 0x80000000L |
29241 | //CP_ME_MC_WDATA_LO |
29242 | #define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO__SHIFT 0x0 |
29243 | #define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO_MASK 0xFFFFFFFFL |
29244 | //CP_ME_MC_WDATA_HI |
29245 | #define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI__SHIFT 0x0 |
29246 | #define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI_MASK 0xFFFFFFFFL |
29247 | //CP_ME_MC_RADDR_LO |
29248 | #define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO__SHIFT 0x2 |
29249 | #define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO_MASK 0xFFFFFFFCL |
29250 | //CP_ME_MC_RADDR_HI |
29251 | #define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI__SHIFT 0x0 |
29252 | #define CP_ME_MC_RADDR_HI__SIZE__SHIFT 0x10 |
29253 | #define CP_ME_MC_RADDR_HI__CACHE_POLICY__SHIFT 0x16 |
29254 | #define CP_ME_MC_RADDR_HI__VMID__SHIFT 0x18 |
29255 | #define CP_ME_MC_RADDR_HI__PRIVILEGE__SHIFT 0x1f |
29256 | #define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI_MASK 0x0000FFFFL |
29257 | #define CP_ME_MC_RADDR_HI__SIZE_MASK 0x000F0000L |
29258 | #define CP_ME_MC_RADDR_HI__CACHE_POLICY_MASK 0x00C00000L |
29259 | #define CP_ME_MC_RADDR_HI__VMID_MASK 0x0F000000L |
29260 | #define CP_ME_MC_RADDR_HI__PRIVILEGE_MASK 0x80000000L |
29261 | //CP_SEM_WAIT_TIMER |
29262 | #define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER__SHIFT 0x0 |
29263 | #define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER_MASK 0xFFFFFFFFL |
29264 | //CP_SIG_SEM_ADDR_LO |
29265 | #define CP_SIG_SEM_ADDR_LO__SEM_PRIV__SHIFT 0x0 |
29266 | #define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT 0x3 |
29267 | #define CP_SIG_SEM_ADDR_LO__SEM_PRIV_MASK 0x00000001L |
29268 | #define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO_MASK 0xFFFFFFF8L |
29269 | //CP_SIG_SEM_ADDR_HI |
29270 | #define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT 0x0 |
29271 | #define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x10 |
29272 | #define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x14 |
29273 | #define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x18 |
29274 | #define CP_SIG_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x1d |
29275 | #define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI_MASK 0x0000FFFFL |
29276 | #define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK 0x00010000L |
29277 | #define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK 0x00100000L |
29278 | #define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x03000000L |
29279 | #define CP_SIG_SEM_ADDR_HI__SEM_SELECT_MASK 0xE0000000L |
29280 | //CP_WAIT_REG_MEM_TIMEOUT |
29281 | #define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT__SHIFT 0x0 |
29282 | #define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT_MASK 0xFFFFFFFFL |
29283 | //CP_WAIT_SEM_ADDR_LO |
29284 | #define CP_WAIT_SEM_ADDR_LO__SEM_PRIV__SHIFT 0x0 |
29285 | #define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT 0x3 |
29286 | #define CP_WAIT_SEM_ADDR_LO__SEM_PRIV_MASK 0x00000001L |
29287 | #define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO_MASK 0xFFFFFFF8L |
29288 | //CP_WAIT_SEM_ADDR_HI |
29289 | #define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT 0x0 |
29290 | #define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x10 |
29291 | #define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x14 |
29292 | #define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x18 |
29293 | #define CP_WAIT_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x1d |
29294 | #define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI_MASK 0x0000FFFFL |
29295 | #define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK 0x00010000L |
29296 | #define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK 0x00100000L |
29297 | #define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x03000000L |
29298 | #define CP_WAIT_SEM_ADDR_HI__SEM_SELECT_MASK 0xE0000000L |
29299 | //CP_DMA_PFP_CONTROL |
29300 | #define CP_DMA_PFP_CONTROL__VMID__SHIFT 0x0 |
29301 | #define CP_DMA_PFP_CONTROL__TMZ__SHIFT 0x4 |
29302 | #define CP_DMA_PFP_CONTROL__MEMLOG_CLEAR__SHIFT 0xa |
29303 | #define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY__SHIFT 0xd |
29304 | #define CP_DMA_PFP_CONTROL__SRC_VOLATLE__SHIFT 0xf |
29305 | #define CP_DMA_PFP_CONTROL__DST_SELECT__SHIFT 0x14 |
29306 | #define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY__SHIFT 0x19 |
29307 | #define CP_DMA_PFP_CONTROL__DST_VOLATLE__SHIFT 0x1b |
29308 | #define CP_DMA_PFP_CONTROL__SRC_SELECT__SHIFT 0x1d |
29309 | #define CP_DMA_PFP_CONTROL__VMID_MASK 0x0000000FL |
29310 | #define CP_DMA_PFP_CONTROL__TMZ_MASK 0x00000010L |
29311 | #define CP_DMA_PFP_CONTROL__MEMLOG_CLEAR_MASK 0x00000400L |
29312 | #define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY_MASK 0x00006000L |
29313 | #define CP_DMA_PFP_CONTROL__SRC_VOLATLE_MASK 0x00008000L |
29314 | #define CP_DMA_PFP_CONTROL__DST_SELECT_MASK 0x00300000L |
29315 | #define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY_MASK 0x06000000L |
29316 | #define CP_DMA_PFP_CONTROL__DST_VOLATLE_MASK 0x08000000L |
29317 | #define CP_DMA_PFP_CONTROL__SRC_SELECT_MASK 0x60000000L |
29318 | //CP_DMA_ME_CONTROL |
29319 | #define CP_DMA_ME_CONTROL__VMID__SHIFT 0x0 |
29320 | #define CP_DMA_ME_CONTROL__TMZ__SHIFT 0x4 |
29321 | #define CP_DMA_ME_CONTROL__MEMLOG_CLEAR__SHIFT 0xa |
29322 | #define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY__SHIFT 0xd |
29323 | #define CP_DMA_ME_CONTROL__SRC_VOLATLE__SHIFT 0xf |
29324 | #define CP_DMA_ME_CONTROL__DST_SELECT__SHIFT 0x14 |
29325 | #define CP_DMA_ME_CONTROL__DST_CACHE_POLICY__SHIFT 0x19 |
29326 | #define CP_DMA_ME_CONTROL__DST_VOLATLE__SHIFT 0x1b |
29327 | #define CP_DMA_ME_CONTROL__SRC_SELECT__SHIFT 0x1d |
29328 | #define CP_DMA_ME_CONTROL__VMID_MASK 0x0000000FL |
29329 | #define CP_DMA_ME_CONTROL__TMZ_MASK 0x00000010L |
29330 | #define CP_DMA_ME_CONTROL__MEMLOG_CLEAR_MASK 0x00000400L |
29331 | #define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY_MASK 0x00006000L |
29332 | #define CP_DMA_ME_CONTROL__SRC_VOLATLE_MASK 0x00008000L |
29333 | #define CP_DMA_ME_CONTROL__DST_SELECT_MASK 0x00300000L |
29334 | #define CP_DMA_ME_CONTROL__DST_CACHE_POLICY_MASK 0x06000000L |
29335 | #define CP_DMA_ME_CONTROL__DST_VOLATLE_MASK 0x08000000L |
29336 | #define CP_DMA_ME_CONTROL__SRC_SELECT_MASK 0x60000000L |
29337 | //CP_DMA_ME_SRC_ADDR |
29338 | #define CP_DMA_ME_SRC_ADDR__SRC_ADDR__SHIFT 0x0 |
29339 | #define CP_DMA_ME_SRC_ADDR__SRC_ADDR_MASK 0xFFFFFFFFL |
29340 | //CP_DMA_ME_SRC_ADDR_HI |
29341 | #define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x0 |
29342 | #define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0x0000FFFFL |
29343 | //CP_DMA_ME_DST_ADDR |
29344 | #define CP_DMA_ME_DST_ADDR__DST_ADDR__SHIFT 0x0 |
29345 | #define CP_DMA_ME_DST_ADDR__DST_ADDR_MASK 0xFFFFFFFFL |
29346 | //CP_DMA_ME_DST_ADDR_HI |
29347 | #define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x0 |
29348 | #define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI_MASK 0x0000FFFFL |
29349 | //CP_DMA_ME_COMMAND |
29350 | #define CP_DMA_ME_COMMAND__BYTE_COUNT__SHIFT 0x0 |
29351 | #define CP_DMA_ME_COMMAND__SAS__SHIFT 0x1a |
29352 | #define CP_DMA_ME_COMMAND__DAS__SHIFT 0x1b |
29353 | #define CP_DMA_ME_COMMAND__SAIC__SHIFT 0x1c |
29354 | #define CP_DMA_ME_COMMAND__DAIC__SHIFT 0x1d |
29355 | #define CP_DMA_ME_COMMAND__RAW_WAIT__SHIFT 0x1e |
29356 | #define CP_DMA_ME_COMMAND__DIS_WC__SHIFT 0x1f |
29357 | #define CP_DMA_ME_COMMAND__BYTE_COUNT_MASK 0x03FFFFFFL |
29358 | #define CP_DMA_ME_COMMAND__SAS_MASK 0x04000000L |
29359 | #define CP_DMA_ME_COMMAND__DAS_MASK 0x08000000L |
29360 | #define CP_DMA_ME_COMMAND__SAIC_MASK 0x10000000L |
29361 | #define CP_DMA_ME_COMMAND__DAIC_MASK 0x20000000L |
29362 | #define CP_DMA_ME_COMMAND__RAW_WAIT_MASK 0x40000000L |
29363 | #define CP_DMA_ME_COMMAND__DIS_WC_MASK 0x80000000L |
29364 | //CP_DMA_PFP_SRC_ADDR |
29365 | #define CP_DMA_PFP_SRC_ADDR__SRC_ADDR__SHIFT 0x0 |
29366 | #define CP_DMA_PFP_SRC_ADDR__SRC_ADDR_MASK 0xFFFFFFFFL |
29367 | //CP_DMA_PFP_SRC_ADDR_HI |
29368 | #define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x0 |
29369 | #define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0x0000FFFFL |
29370 | //CP_DMA_PFP_DST_ADDR |
29371 | #define CP_DMA_PFP_DST_ADDR__DST_ADDR__SHIFT 0x0 |
29372 | #define CP_DMA_PFP_DST_ADDR__DST_ADDR_MASK 0xFFFFFFFFL |
29373 | //CP_DMA_PFP_DST_ADDR_HI |
29374 | #define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x0 |
29375 | #define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI_MASK 0x0000FFFFL |
29376 | //CP_DMA_PFP_COMMAND |
29377 | #define CP_DMA_PFP_COMMAND__BYTE_COUNT__SHIFT 0x0 |
29378 | #define CP_DMA_PFP_COMMAND__SAS__SHIFT 0x1a |
29379 | #define CP_DMA_PFP_COMMAND__DAS__SHIFT 0x1b |
29380 | #define CP_DMA_PFP_COMMAND__SAIC__SHIFT 0x1c |
29381 | #define CP_DMA_PFP_COMMAND__DAIC__SHIFT 0x1d |
29382 | #define CP_DMA_PFP_COMMAND__RAW_WAIT__SHIFT 0x1e |
29383 | #define CP_DMA_PFP_COMMAND__DIS_WC__SHIFT 0x1f |
29384 | #define CP_DMA_PFP_COMMAND__BYTE_COUNT_MASK 0x03FFFFFFL |
29385 | #define CP_DMA_PFP_COMMAND__SAS_MASK 0x04000000L |
29386 | #define CP_DMA_PFP_COMMAND__DAS_MASK 0x08000000L |
29387 | #define CP_DMA_PFP_COMMAND__SAIC_MASK 0x10000000L |
29388 | #define CP_DMA_PFP_COMMAND__DAIC_MASK 0x20000000L |
29389 | #define CP_DMA_PFP_COMMAND__RAW_WAIT_MASK 0x40000000L |
29390 | #define CP_DMA_PFP_COMMAND__DIS_WC_MASK 0x80000000L |
29391 | //CP_DMA_CNTL |
29392 | #define CP_DMA_CNTL__UTCL1_FAULT_CONTROL__SHIFT 0x0 |
29393 | #define CP_DMA_CNTL__WATCH_CONTROL__SHIFT 0x1 |
29394 | #define CP_DMA_CNTL__MIN_AVAILSZ__SHIFT 0x4 |
29395 | #define CP_DMA_CNTL__BUFFER_DEPTH__SHIFT 0x10 |
29396 | #define CP_DMA_CNTL__PIO_FIFO_EMPTY__SHIFT 0x1c |
29397 | #define CP_DMA_CNTL__PIO_FIFO_FULL__SHIFT 0x1d |
29398 | #define CP_DMA_CNTL__PIO_COUNT__SHIFT 0x1e |
29399 | #define CP_DMA_CNTL__UTCL1_FAULT_CONTROL_MASK 0x00000001L |
29400 | #define CP_DMA_CNTL__WATCH_CONTROL_MASK 0x00000002L |
29401 | #define CP_DMA_CNTL__MIN_AVAILSZ_MASK 0x00000030L |
29402 | #define CP_DMA_CNTL__BUFFER_DEPTH_MASK 0x01FF0000L |
29403 | #define CP_DMA_CNTL__PIO_FIFO_EMPTY_MASK 0x10000000L |
29404 | #define CP_DMA_CNTL__PIO_FIFO_FULL_MASK 0x20000000L |
29405 | #define CP_DMA_CNTL__PIO_COUNT_MASK 0xC0000000L |
29406 | //CP_DMA_READ_TAGS |
29407 | #define CP_DMA_READ_TAGS__DMA_READ_TAG__SHIFT 0x0 |
29408 | #define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID__SHIFT 0x1c |
29409 | #define CP_DMA_READ_TAGS__DMA_READ_TAG_MASK 0x03FFFFFFL |
29410 | #define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID_MASK 0x10000000L |
29411 | //CP_PFP_IB_CONTROL |
29412 | #define CP_PFP_IB_CONTROL__IB_EN__SHIFT 0x0 |
29413 | #define CP_PFP_IB_CONTROL__IB_EN_MASK 0x000000FFL |
29414 | //CP_PFP_LOAD_CONTROL |
29415 | #define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN__SHIFT 0x0 |
29416 | #define CP_PFP_LOAD_CONTROL__CNTX_REG_EN__SHIFT 0x1 |
29417 | #define CP_PFP_LOAD_CONTROL__UCONFIG_REG_EN__SHIFT 0xf |
29418 | #define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN__SHIFT 0x10 |
29419 | #define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN__SHIFT 0x18 |
29420 | #define CP_PFP_LOAD_CONTROL__LOAD_ORDINAL__SHIFT 0x1f |
29421 | #define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN_MASK 0x00000001L |
29422 | #define CP_PFP_LOAD_CONTROL__CNTX_REG_EN_MASK 0x00000002L |
29423 | #define CP_PFP_LOAD_CONTROL__UCONFIG_REG_EN_MASK 0x00008000L |
29424 | #define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN_MASK 0x00010000L |
29425 | #define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN_MASK 0x01000000L |
29426 | #define CP_PFP_LOAD_CONTROL__LOAD_ORDINAL_MASK 0x80000000L |
29427 | //CP_SCRATCH_INDEX |
29428 | #define CP_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0 |
29429 | #define CP_SCRATCH_INDEX__SCRATCH_INDEX_64BIT_MODE__SHIFT 0x1f |
29430 | #define CP_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0x000001FFL |
29431 | #define CP_SCRATCH_INDEX__SCRATCH_INDEX_64BIT_MODE_MASK 0x80000000L |
29432 | //CP_SCRATCH_DATA |
29433 | #define CP_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0 |
29434 | #define CP_SCRATCH_DATA__SCRATCH_DATA_MASK 0xFFFFFFFFL |
29435 | //CP_RB_OFFSET |
29436 | #define CP_RB_OFFSET__RB_OFFSET__SHIFT 0x0 |
29437 | #define CP_RB_OFFSET__RB_OFFSET_MASK 0x000FFFFFL |
29438 | //CP_IB1_OFFSET |
29439 | #define CP_IB1_OFFSET__IB1_OFFSET__SHIFT 0x0 |
29440 | #define CP_IB1_OFFSET__IB1_OFFSET_MASK 0x000FFFFFL |
29441 | //CP_IB2_OFFSET |
29442 | #define CP_IB2_OFFSET__IB2_OFFSET__SHIFT 0x0 |
29443 | #define CP_IB2_OFFSET__IB2_OFFSET_MASK 0x000FFFFFL |
29444 | //CP_IB1_PREAMBLE_BEGIN |
29445 | #define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN__SHIFT 0x0 |
29446 | #define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN_MASK 0x000FFFFFL |
29447 | //CP_IB1_PREAMBLE_END |
29448 | #define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END__SHIFT 0x0 |
29449 | #define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END_MASK 0x000FFFFFL |
29450 | //CP_IB2_PREAMBLE_BEGIN |
29451 | #define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN__SHIFT 0x0 |
29452 | #define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN_MASK 0x000FFFFFL |
29453 | //CP_IB2_PREAMBLE_END |
29454 | #define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END__SHIFT 0x0 |
29455 | #define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END_MASK 0x000FFFFFL |
29456 | //CP_DMA_ME_CMD_ADDR_LO |
29457 | #define CP_DMA_ME_CMD_ADDR_LO__RSVD__SHIFT 0x0 |
29458 | #define CP_DMA_ME_CMD_ADDR_LO__ADDR_LO__SHIFT 0x2 |
29459 | #define CP_DMA_ME_CMD_ADDR_LO__RSVD_MASK 0x00000003L |
29460 | #define CP_DMA_ME_CMD_ADDR_LO__ADDR_LO_MASK 0xFFFFFFFCL |
29461 | //CP_DMA_ME_CMD_ADDR_HI |
29462 | #define CP_DMA_ME_CMD_ADDR_HI__ADDR_HI__SHIFT 0x0 |
29463 | #define CP_DMA_ME_CMD_ADDR_HI__RSVD__SHIFT 0x10 |
29464 | #define CP_DMA_ME_CMD_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL |
29465 | #define CP_DMA_ME_CMD_ADDR_HI__RSVD_MASK 0xFFFF0000L |
29466 | //CP_DMA_PFP_CMD_ADDR_LO |
29467 | #define CP_DMA_PFP_CMD_ADDR_LO__RSVD__SHIFT 0x0 |
29468 | #define CP_DMA_PFP_CMD_ADDR_LO__ADDR_LO__SHIFT 0x2 |
29469 | #define CP_DMA_PFP_CMD_ADDR_LO__RSVD_MASK 0x00000003L |
29470 | #define CP_DMA_PFP_CMD_ADDR_LO__ADDR_LO_MASK 0xFFFFFFFCL |
29471 | //CP_DMA_PFP_CMD_ADDR_HI |
29472 | #define CP_DMA_PFP_CMD_ADDR_HI__ADDR_HI__SHIFT 0x0 |
29473 | #define CP_DMA_PFP_CMD_ADDR_HI__RSVD__SHIFT 0x10 |
29474 | #define CP_DMA_PFP_CMD_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL |
29475 | #define CP_DMA_PFP_CMD_ADDR_HI__RSVD_MASK 0xFFFF0000L |
29476 | //CP_APPEND_CMD_ADDR_LO |
29477 | #define CP_APPEND_CMD_ADDR_LO__RSVD__SHIFT 0x0 |
29478 | #define CP_APPEND_CMD_ADDR_LO__ADDR_LO__SHIFT 0x2 |
29479 | #define CP_APPEND_CMD_ADDR_LO__RSVD_MASK 0x00000003L |
29480 | #define CP_APPEND_CMD_ADDR_LO__ADDR_LO_MASK 0xFFFFFFFCL |
29481 | //CP_APPEND_CMD_ADDR_HI |
29482 | #define CP_APPEND_CMD_ADDR_HI__ADDR_HI__SHIFT 0x0 |
29483 | #define CP_APPEND_CMD_ADDR_HI__RSVD__SHIFT 0x10 |
29484 | #define CP_APPEND_CMD_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL |
29485 | #define CP_APPEND_CMD_ADDR_HI__RSVD_MASK 0xFFFF0000L |
29486 | //UCONFIG_RESERVED_REG0 |
29487 | #define UCONFIG_RESERVED_REG0__DATA__SHIFT 0x0 |
29488 | #define UCONFIG_RESERVED_REG0__DATA_MASK 0xFFFFFFFFL |
29489 | //UCONFIG_RESERVED_REG1 |
29490 | #define UCONFIG_RESERVED_REG1__DATA__SHIFT 0x0 |
29491 | #define UCONFIG_RESERVED_REG1__DATA_MASK 0xFFFFFFFFL |
29492 | //CP_PA_MSPRIM_COUNT_LO |
29493 | #define CP_PA_MSPRIM_COUNT_LO__MSPRIM_COUNT_LO__SHIFT 0x0 |
29494 | #define CP_PA_MSPRIM_COUNT_LO__MSPRIM_COUNT_LO_MASK 0xFFFFFFFFL |
29495 | //CP_PA_MSPRIM_COUNT_HI |
29496 | #define CP_PA_MSPRIM_COUNT_HI__MSPRIM_COUNT_HI__SHIFT 0x0 |
29497 | #define CP_PA_MSPRIM_COUNT_HI__MSPRIM_COUNT_HI_MASK 0xFFFFFFFFL |
29498 | //CP_GE_MSINVOC_COUNT_LO |
29499 | #define CP_GE_MSINVOC_COUNT_LO__MSINVOC_COUNT_LO__SHIFT 0x0 |
29500 | #define CP_GE_MSINVOC_COUNT_LO__MSINVOC_COUNT_LO_MASK 0xFFFFFFFFL |
29501 | //CP_GE_MSINVOC_COUNT_HI |
29502 | #define CP_GE_MSINVOC_COUNT_HI__MSINVOC_COUNT_HI__SHIFT 0x0 |
29503 | #define CP_GE_MSINVOC_COUNT_HI__MSINVOC_COUNT_HI_MASK 0xFFFFFFFFL |
29504 | //CP_IB1_CMD_BUFSZ |
29505 | #define CP_IB1_CMD_BUFSZ__IB1_CMD_REQSZ__SHIFT 0x0 |
29506 | #define CP_IB1_CMD_BUFSZ__IB1_CMD_REQSZ_MASK 0x000FFFFFL |
29507 | //CP_IB2_CMD_BUFSZ |
29508 | #define CP_IB2_CMD_BUFSZ__IB2_CMD_REQSZ__SHIFT 0x0 |
29509 | #define CP_IB2_CMD_BUFSZ__IB2_CMD_REQSZ_MASK 0x000FFFFFL |
29510 | //CP_ST_CMD_BUFSZ |
29511 | #define CP_ST_CMD_BUFSZ__ST_CMD_REQSZ__SHIFT 0x0 |
29512 | #define CP_ST_CMD_BUFSZ__ST_CMD_REQSZ_MASK 0x000FFFFFL |
29513 | //CP_IB1_BASE_LO |
29514 | #define CP_IB1_BASE_LO__IB1_BASE_LO__SHIFT 0x2 |
29515 | #define CP_IB1_BASE_LO__IB1_BASE_LO_MASK 0xFFFFFFFCL |
29516 | //CP_IB1_BASE_HI |
29517 | #define CP_IB1_BASE_HI__IB1_BASE_HI__SHIFT 0x0 |
29518 | #define CP_IB1_BASE_HI__IB1_BASE_HI_MASK 0x0000FFFFL |
29519 | //CP_IB1_BUFSZ |
29520 | #define CP_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x0 |
29521 | #define CP_IB1_BUFSZ__IB1_BUFSZ_MASK 0x000FFFFFL |
29522 | //CP_IB2_BASE_LO |
29523 | #define CP_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x2 |
29524 | #define CP_IB2_BASE_LO__IB2_BASE_LO_MASK 0xFFFFFFFCL |
29525 | //CP_IB2_BASE_HI |
29526 | #define CP_IB2_BASE_HI__IB2_BASE_HI__SHIFT 0x0 |
29527 | #define CP_IB2_BASE_HI__IB2_BASE_HI_MASK 0x0000FFFFL |
29528 | //CP_IB2_BUFSZ |
29529 | #define CP_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x0 |
29530 | #define CP_IB2_BUFSZ__IB2_BUFSZ_MASK 0x000FFFFFL |
29531 | //CP_ST_BASE_LO |
29532 | #define CP_ST_BASE_LO__ST_BASE_LO__SHIFT 0x2 |
29533 | #define CP_ST_BASE_LO__ST_BASE_LO_MASK 0xFFFFFFFCL |
29534 | //CP_ST_BASE_HI |
29535 | #define CP_ST_BASE_HI__ST_BASE_HI__SHIFT 0x0 |
29536 | #define CP_ST_BASE_HI__ST_BASE_HI_MASK 0x0000FFFFL |
29537 | //CP_ST_BUFSZ |
29538 | #define CP_ST_BUFSZ__ST_BUFSZ__SHIFT 0x0 |
29539 | #define CP_ST_BUFSZ__ST_BUFSZ_MASK 0x000FFFFFL |
29540 | //CP_EOP_DONE_EVENT_CNTL |
29541 | #define CP_EOP_DONE_EVENT_CNTL__GCR_CNTL__SHIFT 0xc |
29542 | #define CP_EOP_DONE_EVENT_CNTL__CACHE_POLICY__SHIFT 0x19 |
29543 | #define CP_EOP_DONE_EVENT_CNTL__EOP_VOLATILE__SHIFT 0x1b |
29544 | #define CP_EOP_DONE_EVENT_CNTL__EXECUTE__SHIFT 0x1c |
29545 | #define CP_EOP_DONE_EVENT_CNTL__GLK_INV__SHIFT 0x1e |
29546 | #define CP_EOP_DONE_EVENT_CNTL__PWS_ENABLE__SHIFT 0x1f |
29547 | #define CP_EOP_DONE_EVENT_CNTL__GCR_CNTL_MASK 0x01FFF000L |
29548 | #define CP_EOP_DONE_EVENT_CNTL__CACHE_POLICY_MASK 0x06000000L |
29549 | #define CP_EOP_DONE_EVENT_CNTL__EOP_VOLATILE_MASK 0x08000000L |
29550 | #define CP_EOP_DONE_EVENT_CNTL__EXECUTE_MASK 0x10000000L |
29551 | #define CP_EOP_DONE_EVENT_CNTL__GLK_INV_MASK 0x40000000L |
29552 | #define CP_EOP_DONE_EVENT_CNTL__PWS_ENABLE_MASK 0x80000000L |
29553 | //CP_EOP_DONE_DATA_CNTL |
29554 | #define CP_EOP_DONE_DATA_CNTL__DST_SEL__SHIFT 0x10 |
29555 | #define CP_EOP_DONE_DATA_CNTL__SEMAPHORE_SIGNAL_TYPE__SHIFT 0x13 |
29556 | #define CP_EOP_DONE_DATA_CNTL__ACTION_PIPE_ID__SHIFT 0x14 |
29557 | #define CP_EOP_DONE_DATA_CNTL__ACTION_ID__SHIFT 0x16 |
29558 | #define CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT 0x18 |
29559 | #define CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT 0x1d |
29560 | #define CP_EOP_DONE_DATA_CNTL__DST_SEL_MASK 0x00030000L |
29561 | #define CP_EOP_DONE_DATA_CNTL__SEMAPHORE_SIGNAL_TYPE_MASK 0x00080000L |
29562 | #define CP_EOP_DONE_DATA_CNTL__ACTION_PIPE_ID_MASK 0x00300000L |
29563 | #define CP_EOP_DONE_DATA_CNTL__ACTION_ID_MASK 0x00C00000L |
29564 | #define CP_EOP_DONE_DATA_CNTL__INT_SEL_MASK 0x07000000L |
29565 | #define CP_EOP_DONE_DATA_CNTL__DATA_SEL_MASK 0xE0000000L |
29566 | //CP_EOP_DONE_CNTX_ID |
29567 | #define CP_EOP_DONE_CNTX_ID__CNTX_ID__SHIFT 0x0 |
29568 | #define CP_EOP_DONE_CNTX_ID__CNTX_ID_MASK 0xFFFFFFFFL |
29569 | //CP_DB_BASE_LO |
29570 | #define CP_DB_BASE_LO__DB_BASE_LO__SHIFT 0x2 |
29571 | #define CP_DB_BASE_LO__DB_BASE_LO_MASK 0xFFFFFFFCL |
29572 | //CP_DB_BASE_HI |
29573 | #define CP_DB_BASE_HI__DB_BASE_HI__SHIFT 0x0 |
29574 | #define CP_DB_BASE_HI__DB_BASE_HI_MASK 0x0000FFFFL |
29575 | //CP_DB_BUFSZ |
29576 | #define CP_DB_BUFSZ__DB_BUFSZ__SHIFT 0x0 |
29577 | #define CP_DB_BUFSZ__DB_BUFSZ_MASK 0x000FFFFFL |
29578 | //CP_DB_CMD_BUFSZ |
29579 | #define CP_DB_CMD_BUFSZ__DB_CMD_REQSZ__SHIFT 0x0 |
29580 | #define CP_DB_CMD_BUFSZ__DB_CMD_REQSZ_MASK 0x000FFFFFL |
29581 | //CP_PFP_COMPLETION_STATUS |
29582 | #define CP_PFP_COMPLETION_STATUS__STATUS__SHIFT 0x0 |
29583 | #define CP_PFP_COMPLETION_STATUS__STATUS_MASK 0x00000003L |
29584 | //CP_PRED_NOT_VISIBLE |
29585 | #define CP_PRED_NOT_VISIBLE__NOT_VISIBLE__SHIFT 0x0 |
29586 | #define CP_PRED_NOT_VISIBLE__NOT_VISIBLE_MASK 0x00000001L |
29587 | //CP_PFP_METADATA_BASE_ADDR |
29588 | #define CP_PFP_METADATA_BASE_ADDR__ADDR_LO__SHIFT 0x0 |
29589 | #define CP_PFP_METADATA_BASE_ADDR__ADDR_LO_MASK 0xFFFFFFFFL |
29590 | //CP_PFP_METADATA_BASE_ADDR_HI |
29591 | #define CP_PFP_METADATA_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0 |
29592 | #define CP_PFP_METADATA_BASE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL |
29593 | //CP_DRAW_INDX_INDR_ADDR |
29594 | #define CP_DRAW_INDX_INDR_ADDR__ADDR_LO__SHIFT 0x0 |
29595 | #define CP_DRAW_INDX_INDR_ADDR__ADDR_LO_MASK 0xFFFFFFFFL |
29596 | //CP_DRAW_INDX_INDR_ADDR_HI |
29597 | #define CP_DRAW_INDX_INDR_ADDR_HI__ADDR_HI__SHIFT 0x0 |
29598 | #define CP_DRAW_INDX_INDR_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL |
29599 | //CP_DISPATCH_INDR_ADDR |
29600 | #define CP_DISPATCH_INDR_ADDR__ADDR_LO__SHIFT 0x0 |
29601 | #define CP_DISPATCH_INDR_ADDR__ADDR_LO_MASK 0xFFFFFFFFL |
29602 | //CP_DISPATCH_INDR_ADDR_HI |
29603 | #define CP_DISPATCH_INDR_ADDR_HI__ADDR_HI__SHIFT 0x0 |
29604 | #define CP_DISPATCH_INDR_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL |
29605 | //CP_INDEX_BASE_ADDR |
29606 | #define CP_INDEX_BASE_ADDR__ADDR_LO__SHIFT 0x0 |
29607 | #define CP_INDEX_BASE_ADDR__ADDR_LO_MASK 0xFFFFFFFFL |
29608 | //CP_INDEX_BASE_ADDR_HI |
29609 | #define CP_INDEX_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0 |
29610 | #define CP_INDEX_BASE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL |
29611 | //CP_INDEX_TYPE |
29612 | #define CP_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0 |
29613 | #define CP_INDEX_TYPE__INDEX_TYPE_MASK 0x00000003L |
29614 | //CP_GDS_BKUP_ADDR |
29615 | #define CP_GDS_BKUP_ADDR__ADDR_LO__SHIFT 0x0 |
29616 | #define CP_GDS_BKUP_ADDR__ADDR_LO_MASK 0xFFFFFFFFL |
29617 | //CP_GDS_BKUP_ADDR_HI |
29618 | #define CP_GDS_BKUP_ADDR_HI__ADDR_HI__SHIFT 0x0 |
29619 | #define CP_GDS_BKUP_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL |
29620 | //CP_SAMPLE_STATUS |
29621 | #define CP_SAMPLE_STATUS__Z_PASS_ACITVE__SHIFT 0x0 |
29622 | #define CP_SAMPLE_STATUS__STREAMOUT_ACTIVE__SHIFT 0x1 |
29623 | #define CP_SAMPLE_STATUS__PIPELINE_ACTIVE__SHIFT 0x2 |
29624 | #define CP_SAMPLE_STATUS__STIPPLE_ACTIVE__SHIFT 0x3 |
29625 | #define CP_SAMPLE_STATUS__VGT_BUFFERS_ACTIVE__SHIFT 0x4 |
29626 | #define CP_SAMPLE_STATUS__SCREEN_EXT_ACTIVE__SHIFT 0x5 |
29627 | #define CP_SAMPLE_STATUS__DRAW_INDIRECT_ACTIVE__SHIFT 0x6 |
29628 | #define CP_SAMPLE_STATUS__DISP_INDIRECT_ACTIVE__SHIFT 0x7 |
29629 | #define CP_SAMPLE_STATUS__Z_PASS_ACITVE_MASK 0x00000001L |
29630 | #define CP_SAMPLE_STATUS__STREAMOUT_ACTIVE_MASK 0x00000002L |
29631 | #define CP_SAMPLE_STATUS__PIPELINE_ACTIVE_MASK 0x00000004L |
29632 | #define CP_SAMPLE_STATUS__STIPPLE_ACTIVE_MASK 0x00000008L |
29633 | #define CP_SAMPLE_STATUS__VGT_BUFFERS_ACTIVE_MASK 0x00000010L |
29634 | #define CP_SAMPLE_STATUS__SCREEN_EXT_ACTIVE_MASK 0x00000020L |
29635 | #define CP_SAMPLE_STATUS__DRAW_INDIRECT_ACTIVE_MASK 0x00000040L |
29636 | #define CP_SAMPLE_STATUS__DISP_INDIRECT_ACTIVE_MASK 0x00000080L |
29637 | //CP_ME_COHER_CNTL |
29638 | #define CP_ME_COHER_CNTL__DEST_BASE_0_ENA__SHIFT 0x0 |
29639 | #define CP_ME_COHER_CNTL__DEST_BASE_1_ENA__SHIFT 0x1 |
29640 | #define CP_ME_COHER_CNTL__CB0_DEST_BASE_ENA__SHIFT 0x6 |
29641 | #define CP_ME_COHER_CNTL__CB1_DEST_BASE_ENA__SHIFT 0x7 |
29642 | #define CP_ME_COHER_CNTL__CB2_DEST_BASE_ENA__SHIFT 0x8 |
29643 | #define CP_ME_COHER_CNTL__CB3_DEST_BASE_ENA__SHIFT 0x9 |
29644 | #define CP_ME_COHER_CNTL__CB4_DEST_BASE_ENA__SHIFT 0xa |
29645 | #define CP_ME_COHER_CNTL__CB5_DEST_BASE_ENA__SHIFT 0xb |
29646 | #define CP_ME_COHER_CNTL__CB6_DEST_BASE_ENA__SHIFT 0xc |
29647 | #define CP_ME_COHER_CNTL__CB7_DEST_BASE_ENA__SHIFT 0xd |
29648 | #define CP_ME_COHER_CNTL__DB_DEST_BASE_ENA__SHIFT 0xe |
29649 | #define CP_ME_COHER_CNTL__DEST_BASE_2_ENA__SHIFT 0x13 |
29650 | #define CP_ME_COHER_CNTL__DEST_BASE_3_ENA__SHIFT 0x15 |
29651 | #define CP_ME_COHER_CNTL__DEST_BASE_0_ENA_MASK 0x00000001L |
29652 | #define CP_ME_COHER_CNTL__DEST_BASE_1_ENA_MASK 0x00000002L |
29653 | #define CP_ME_COHER_CNTL__CB0_DEST_BASE_ENA_MASK 0x00000040L |
29654 | #define CP_ME_COHER_CNTL__CB1_DEST_BASE_ENA_MASK 0x00000080L |
29655 | #define CP_ME_COHER_CNTL__CB2_DEST_BASE_ENA_MASK 0x00000100L |
29656 | #define CP_ME_COHER_CNTL__CB3_DEST_BASE_ENA_MASK 0x00000200L |
29657 | #define CP_ME_COHER_CNTL__CB4_DEST_BASE_ENA_MASK 0x00000400L |
29658 | #define CP_ME_COHER_CNTL__CB5_DEST_BASE_ENA_MASK 0x00000800L |
29659 | #define CP_ME_COHER_CNTL__CB6_DEST_BASE_ENA_MASK 0x00001000L |
29660 | #define CP_ME_COHER_CNTL__CB7_DEST_BASE_ENA_MASK 0x00002000L |
29661 | #define CP_ME_COHER_CNTL__DB_DEST_BASE_ENA_MASK 0x00004000L |
29662 | #define CP_ME_COHER_CNTL__DEST_BASE_2_ENA_MASK 0x00080000L |
29663 | #define CP_ME_COHER_CNTL__DEST_BASE_3_ENA_MASK 0x00200000L |
29664 | //CP_ME_COHER_SIZE |
29665 | #define CP_ME_COHER_SIZE__COHER_SIZE_256B__SHIFT 0x0 |
29666 | #define CP_ME_COHER_SIZE__COHER_SIZE_256B_MASK 0xFFFFFFFFL |
29667 | //CP_ME_COHER_SIZE_HI |
29668 | #define CP_ME_COHER_SIZE_HI__COHER_SIZE_HI_256B__SHIFT 0x0 |
29669 | #define CP_ME_COHER_SIZE_HI__COHER_SIZE_HI_256B_MASK 0x000000FFL |
29670 | //CP_ME_COHER_BASE |
29671 | #define CP_ME_COHER_BASE__COHER_BASE_256B__SHIFT 0x0 |
29672 | #define CP_ME_COHER_BASE__COHER_BASE_256B_MASK 0xFFFFFFFFL |
29673 | //CP_ME_COHER_BASE_HI |
29674 | #define CP_ME_COHER_BASE_HI__COHER_BASE_HI_256B__SHIFT 0x0 |
29675 | #define CP_ME_COHER_BASE_HI__COHER_BASE_HI_256B_MASK 0x000000FFL |
29676 | //CP_ME_COHER_STATUS |
29677 | #define CP_ME_COHER_STATUS__MATCHING_GFX_CNTX__SHIFT 0x0 |
29678 | #define CP_ME_COHER_STATUS__STATUS__SHIFT 0x1f |
29679 | #define CP_ME_COHER_STATUS__MATCHING_GFX_CNTX_MASK 0x000000FFL |
29680 | #define CP_ME_COHER_STATUS__STATUS_MASK 0x80000000L |
29681 | //RLC_GPM_PERF_COUNT_0 |
29682 | #define RLC_GPM_PERF_COUNT_0__FEATURE_SEL__SHIFT 0x0 |
29683 | #define RLC_GPM_PERF_COUNT_0__SE_INDEX__SHIFT 0x4 |
29684 | #define RLC_GPM_PERF_COUNT_0__SA_INDEX__SHIFT 0x8 |
29685 | #define RLC_GPM_PERF_COUNT_0__WGP_INDEX__SHIFT 0xc |
29686 | #define RLC_GPM_PERF_COUNT_0__EVENT_SEL__SHIFT 0x10 |
29687 | #define RLC_GPM_PERF_COUNT_0__UNUSED__SHIFT 0x12 |
29688 | #define RLC_GPM_PERF_COUNT_0__ENABLE__SHIFT 0x14 |
29689 | #define RLC_GPM_PERF_COUNT_0__RESERVED__SHIFT 0x15 |
29690 | #define RLC_GPM_PERF_COUNT_0__FEATURE_SEL_MASK 0x0000000FL |
29691 | #define RLC_GPM_PERF_COUNT_0__SE_INDEX_MASK 0x000000F0L |
29692 | #define RLC_GPM_PERF_COUNT_0__SA_INDEX_MASK 0x00000F00L |
29693 | #define RLC_GPM_PERF_COUNT_0__WGP_INDEX_MASK 0x0000F000L |
29694 | #define RLC_GPM_PERF_COUNT_0__EVENT_SEL_MASK 0x00030000L |
29695 | #define RLC_GPM_PERF_COUNT_0__UNUSED_MASK 0x000C0000L |
29696 | #define RLC_GPM_PERF_COUNT_0__ENABLE_MASK 0x00100000L |
29697 | #define RLC_GPM_PERF_COUNT_0__RESERVED_MASK 0xFFE00000L |
29698 | //RLC_GPM_PERF_COUNT_1 |
29699 | #define RLC_GPM_PERF_COUNT_1__FEATURE_SEL__SHIFT 0x0 |
29700 | #define RLC_GPM_PERF_COUNT_1__SE_INDEX__SHIFT 0x4 |
29701 | #define RLC_GPM_PERF_COUNT_1__SA_INDEX__SHIFT 0x8 |
29702 | #define RLC_GPM_PERF_COUNT_1__WGP_INDEX__SHIFT 0xc |
29703 | #define RLC_GPM_PERF_COUNT_1__EVENT_SEL__SHIFT 0x10 |
29704 | #define RLC_GPM_PERF_COUNT_1__UNUSED__SHIFT 0x12 |
29705 | #define RLC_GPM_PERF_COUNT_1__ENABLE__SHIFT 0x14 |
29706 | #define RLC_GPM_PERF_COUNT_1__RESERVED__SHIFT 0x15 |
29707 | #define RLC_GPM_PERF_COUNT_1__FEATURE_SEL_MASK 0x0000000FL |
29708 | #define RLC_GPM_PERF_COUNT_1__SE_INDEX_MASK 0x000000F0L |
29709 | #define RLC_GPM_PERF_COUNT_1__SA_INDEX_MASK 0x00000F00L |
29710 | #define RLC_GPM_PERF_COUNT_1__WGP_INDEX_MASK 0x0000F000L |
29711 | #define RLC_GPM_PERF_COUNT_1__EVENT_SEL_MASK 0x00030000L |
29712 | #define RLC_GPM_PERF_COUNT_1__UNUSED_MASK 0x000C0000L |
29713 | #define RLC_GPM_PERF_COUNT_1__ENABLE_MASK 0x00100000L |
29714 | #define RLC_GPM_PERF_COUNT_1__RESERVED_MASK 0xFFE00000L |
29715 | //GRBM_GFX_INDEX |
29716 | #define GRBM_GFX_INDEX__INSTANCE_INDEX__SHIFT 0x0 |
29717 | #define GRBM_GFX_INDEX__SA_INDEX__SHIFT 0x8 |
29718 | #define GRBM_GFX_INDEX__SE_INDEX__SHIFT 0x10 |
29719 | #define GRBM_GFX_INDEX__SA_BROADCAST_WRITES__SHIFT 0x1d |
29720 | #define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT 0x1e |
29721 | #define GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT 0x1f |
29722 | #define GRBM_GFX_INDEX__INSTANCE_INDEX_MASK 0x000000FFL |
29723 | #define GRBM_GFX_INDEX__SA_INDEX_MASK 0x0000FF00L |
29724 | #define GRBM_GFX_INDEX__SE_INDEX_MASK 0x00FF0000L |
29725 | #define GRBM_GFX_INDEX__SA_BROADCAST_WRITES_MASK 0x20000000L |
29726 | #define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK 0x40000000L |
29727 | #define GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK 0x80000000L |
29728 | //VGT_PRIMITIVE_TYPE |
29729 | #define VGT_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT 0x0 |
29730 | #define VGT_PRIMITIVE_TYPE__PRIM_TYPE_MASK 0x0000003FL |
29731 | //VGT_INDEX_TYPE |
29732 | #define VGT_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0 |
29733 | #define VGT_INDEX_TYPE__DISABLE_INSTANCE_PACKING__SHIFT 0xe |
29734 | #define VGT_INDEX_TYPE__INDEX_TYPE_MASK 0x00000003L |
29735 | #define VGT_INDEX_TYPE__DISABLE_INSTANCE_PACKING_MASK 0x00004000L |
29736 | //GE_MIN_VTX_INDX |
29737 | #define GE_MIN_VTX_INDX__MIN_INDX__SHIFT 0x0 |
29738 | #define GE_MIN_VTX_INDX__MIN_INDX_MASK 0xFFFFFFFFL |
29739 | //GE_INDX_OFFSET |
29740 | #define GE_INDX_OFFSET__INDX_OFFSET__SHIFT 0x0 |
29741 | #define GE_INDX_OFFSET__INDX_OFFSET_MASK 0xFFFFFFFFL |
29742 | //GE_MULTI_PRIM_IB_RESET_EN |
29743 | #define GE_MULTI_PRIM_IB_RESET_EN__RESET_EN__SHIFT 0x0 |
29744 | #define GE_MULTI_PRIM_IB_RESET_EN__MATCH_ALL_BITS__SHIFT 0x1 |
29745 | #define GE_MULTI_PRIM_IB_RESET_EN__DISABLE_FOR_AUTO_INDEX__SHIFT 0x2 |
29746 | #define GE_MULTI_PRIM_IB_RESET_EN__RESET_EN_MASK 0x00000001L |
29747 | #define GE_MULTI_PRIM_IB_RESET_EN__MATCH_ALL_BITS_MASK 0x00000002L |
29748 | #define GE_MULTI_PRIM_IB_RESET_EN__DISABLE_FOR_AUTO_INDEX_MASK 0x00000004L |
29749 | //VGT_NUM_INDICES |
29750 | #define VGT_NUM_INDICES__NUM_INDICES__SHIFT 0x0 |
29751 | #define VGT_NUM_INDICES__NUM_INDICES_MASK 0xFFFFFFFFL |
29752 | //VGT_NUM_INSTANCES |
29753 | #define VGT_NUM_INSTANCES__NUM_INSTANCES__SHIFT 0x0 |
29754 | #define VGT_NUM_INSTANCES__NUM_INSTANCES_MASK 0xFFFFFFFFL |
29755 | //VGT_TF_RING_SIZE |
29756 | #define VGT_TF_RING_SIZE__SIZE__SHIFT 0x0 |
29757 | #define VGT_TF_RING_SIZE__SIZE_MASK 0x0001FFFFL |
29758 | //VGT_HS_OFFCHIP_PARAM |
29759 | #define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING__SHIFT 0x0 |
29760 | #define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY__SHIFT 0xa |
29761 | #define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING_MASK 0x000003FFL |
29762 | #define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY_MASK 0x00000C00L |
29763 | //VGT_TF_MEMORY_BASE |
29764 | #define VGT_TF_MEMORY_BASE__BASE__SHIFT 0x0 |
29765 | #define VGT_TF_MEMORY_BASE__BASE_MASK 0xFFFFFFFFL |
29766 | //GE_MAX_VTX_INDX |
29767 | #define GE_MAX_VTX_INDX__MAX_INDX__SHIFT 0x0 |
29768 | #define GE_MAX_VTX_INDX__MAX_INDX_MASK 0xFFFFFFFFL |
29769 | //VGT_INSTANCE_BASE_ID |
29770 | #define VGT_INSTANCE_BASE_ID__INSTANCE_BASE_ID__SHIFT 0x0 |
29771 | #define VGT_INSTANCE_BASE_ID__INSTANCE_BASE_ID_MASK 0xFFFFFFFFL |
29772 | //GE_CNTL |
29773 | #define GE_CNTL__PRIMS_PER_SUBGRP__SHIFT 0x0 |
29774 | #define GE_CNTL__VERTS_PER_SUBGRP__SHIFT 0x9 |
29775 | #define GE_CNTL__BREAK_SUBGRP_AT_EOI__SHIFT 0x12 |
29776 | #define GE_CNTL__PACKET_TO_ONE_PA__SHIFT 0x13 |
29777 | #define GE_CNTL__BREAK_PRIMGRP_AT_EOI__SHIFT 0x14 |
29778 | #define GE_CNTL__PRIM_GRP_SIZE__SHIFT 0x15 |
29779 | #define GE_CNTL__GCR_DISABLE__SHIFT 0x1e |
29780 | #define GE_CNTL__DIS_PG_SIZE_ADJUST_FOR_STRIP__SHIFT 0x1f |
29781 | #define GE_CNTL__PRIMS_PER_SUBGRP_MASK 0x000001FFL |
29782 | #define GE_CNTL__VERTS_PER_SUBGRP_MASK 0x0003FE00L |
29783 | #define GE_CNTL__BREAK_SUBGRP_AT_EOI_MASK 0x00040000L |
29784 | #define GE_CNTL__PACKET_TO_ONE_PA_MASK 0x00080000L |
29785 | #define GE_CNTL__BREAK_PRIMGRP_AT_EOI_MASK 0x00100000L |
29786 | #define GE_CNTL__PRIM_GRP_SIZE_MASK 0x3FE00000L |
29787 | #define GE_CNTL__GCR_DISABLE_MASK 0x40000000L |
29788 | #define GE_CNTL__DIS_PG_SIZE_ADJUST_FOR_STRIP_MASK 0x80000000L |
29789 | //GE_USER_VGPR1 |
29790 | #define GE_USER_VGPR1__DATA__SHIFT 0x0 |
29791 | #define GE_USER_VGPR1__DATA_MASK 0xFFFFFFFFL |
29792 | //GE_USER_VGPR2 |
29793 | #define GE_USER_VGPR2__DATA__SHIFT 0x0 |
29794 | #define GE_USER_VGPR2__DATA_MASK 0xFFFFFFFFL |
29795 | //GE_USER_VGPR3 |
29796 | #define GE_USER_VGPR3__DATA__SHIFT 0x0 |
29797 | #define GE_USER_VGPR3__DATA_MASK 0xFFFFFFFFL |
29798 | //GE_STEREO_CNTL |
29799 | #define GE_STEREO_CNTL__RT_SLICE__SHIFT 0x0 |
29800 | #define GE_STEREO_CNTL__VIEWPORT__SHIFT 0x3 |
29801 | #define GE_STEREO_CNTL__FSR_SELECT__SHIFT 0x7 |
29802 | #define GE_STEREO_CNTL__EN_STEREO__SHIFT 0x8 |
29803 | #define GE_STEREO_CNTL__RT_SLICE_MASK 0x00000007L |
29804 | #define GE_STEREO_CNTL__VIEWPORT_MASK 0x00000078L |
29805 | #define GE_STEREO_CNTL__FSR_SELECT_MASK 0x00000080L |
29806 | #define GE_STEREO_CNTL__EN_STEREO_MASK 0x00000100L |
29807 | //GE_PC_ALLOC |
29808 | #define GE_PC_ALLOC__OVERSUB_EN__SHIFT 0x0 |
29809 | #define GE_PC_ALLOC__NUM_PC_LINES__SHIFT 0x1 |
29810 | #define GE_PC_ALLOC__OVERSUB_EN_MASK 0x00000001L |
29811 | #define GE_PC_ALLOC__NUM_PC_LINES_MASK 0x000007FEL |
29812 | //VGT_TF_MEMORY_BASE_HI |
29813 | #define VGT_TF_MEMORY_BASE_HI__BASE_HI__SHIFT 0x0 |
29814 | #define VGT_TF_MEMORY_BASE_HI__BASE_HI_MASK 0x000000FFL |
29815 | //GE_USER_VGPR_EN |
29816 | #define GE_USER_VGPR_EN__EN_USER_VGPR1__SHIFT 0x0 |
29817 | #define GE_USER_VGPR_EN__EN_USER_VGPR2__SHIFT 0x1 |
29818 | #define GE_USER_VGPR_EN__EN_USER_VGPR3__SHIFT 0x2 |
29819 | #define GE_USER_VGPR_EN__EN_USER_VGPR1_MASK 0x00000001L |
29820 | #define GE_USER_VGPR_EN__EN_USER_VGPR2_MASK 0x00000002L |
29821 | #define GE_USER_VGPR_EN__EN_USER_VGPR3_MASK 0x00000004L |
29822 | //GE_GS_FAST_LAUNCH_WG_DIM |
29823 | #define GE_GS_FAST_LAUNCH_WG_DIM__GS_FL_DIM_X__SHIFT 0x0 |
29824 | #define GE_GS_FAST_LAUNCH_WG_DIM__GS_FL_DIM_Y__SHIFT 0x10 |
29825 | #define GE_GS_FAST_LAUNCH_WG_DIM__GS_FL_DIM_X_MASK 0x0000FFFFL |
29826 | #define GE_GS_FAST_LAUNCH_WG_DIM__GS_FL_DIM_Y_MASK 0xFFFF0000L |
29827 | //GE_GS_FAST_LAUNCH_WG_DIM_1 |
29828 | #define GE_GS_FAST_LAUNCH_WG_DIM_1__GS_FL_DIM_Z__SHIFT 0x0 |
29829 | #define GE_GS_FAST_LAUNCH_WG_DIM_1__GS_FL_DIM_Z_MASK 0x0000FFFFL |
29830 | //VGT_GS_OUT_PRIM_TYPE |
29831 | #define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE__SHIFT 0x0 |
29832 | #define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_MASK 0x0000003FL |
29833 | //PA_SU_LINE_STIPPLE_VALUE |
29834 | #define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE__SHIFT 0x0 |
29835 | #define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE_MASK 0x00FFFFFFL |
29836 | //PA_SC_LINE_STIPPLE_STATE |
29837 | #define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR__SHIFT 0x0 |
29838 | #define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT__SHIFT 0x8 |
29839 | #define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR_MASK 0x0000000FL |
29840 | #define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT_MASK 0x0000FF00L |
29841 | //PA_SC_SCREEN_EXTENT_MIN_0 |
29842 | #define PA_SC_SCREEN_EXTENT_MIN_0__X__SHIFT 0x0 |
29843 | #define PA_SC_SCREEN_EXTENT_MIN_0__Y__SHIFT 0x10 |
29844 | #define PA_SC_SCREEN_EXTENT_MIN_0__X_MASK 0x0000FFFFL |
29845 | #define PA_SC_SCREEN_EXTENT_MIN_0__Y_MASK 0xFFFF0000L |
29846 | //PA_SC_SCREEN_EXTENT_MAX_0 |
29847 | #define PA_SC_SCREEN_EXTENT_MAX_0__X__SHIFT 0x0 |
29848 | #define PA_SC_SCREEN_EXTENT_MAX_0__Y__SHIFT 0x10 |
29849 | #define PA_SC_SCREEN_EXTENT_MAX_0__X_MASK 0x0000FFFFL |
29850 | #define PA_SC_SCREEN_EXTENT_MAX_0__Y_MASK 0xFFFF0000L |
29851 | //PA_SC_SCREEN_EXTENT_MIN_1 |
29852 | #define PA_SC_SCREEN_EXTENT_MIN_1__X__SHIFT 0x0 |
29853 | #define PA_SC_SCREEN_EXTENT_MIN_1__Y__SHIFT 0x10 |
29854 | #define PA_SC_SCREEN_EXTENT_MIN_1__X_MASK 0x0000FFFFL |
29855 | #define PA_SC_SCREEN_EXTENT_MIN_1__Y_MASK 0xFFFF0000L |
29856 | //PA_SC_SCREEN_EXTENT_MAX_1 |
29857 | #define PA_SC_SCREEN_EXTENT_MAX_1__X__SHIFT 0x0 |
29858 | #define PA_SC_SCREEN_EXTENT_MAX_1__Y__SHIFT 0x10 |
29859 | #define PA_SC_SCREEN_EXTENT_MAX_1__X_MASK 0x0000FFFFL |
29860 | #define PA_SC_SCREEN_EXTENT_MAX_1__Y_MASK 0xFFFF0000L |
29861 | //PA_SC_P3D_TRAP_SCREEN_HV_EN |
29862 | #define PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0 |
29863 | #define PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1 |
29864 | #define PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x00000001L |
29865 | #define PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x00000002L |
29866 | //PA_SC_P3D_TRAP_SCREEN_H |
29867 | #define PA_SC_P3D_TRAP_SCREEN_H__X_COORD__SHIFT 0x0 |
29868 | #define PA_SC_P3D_TRAP_SCREEN_H__X_COORD_MASK 0x00003FFFL |
29869 | //PA_SC_P3D_TRAP_SCREEN_V |
29870 | #define PA_SC_P3D_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0 |
29871 | #define PA_SC_P3D_TRAP_SCREEN_V__Y_COORD_MASK 0x00003FFFL |
29872 | //PA_SC_P3D_TRAP_SCREEN_OCCURRENCE |
29873 | #define PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0 |
29874 | #define PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0x0000FFFFL |
29875 | //PA_SC_P3D_TRAP_SCREEN_COUNT |
29876 | #define PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0 |
29877 | #define PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT_MASK 0x0000FFFFL |
29878 | //PA_SC_HP3D_TRAP_SCREEN_HV_EN |
29879 | #define PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0 |
29880 | #define PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1 |
29881 | #define PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x00000001L |
29882 | #define PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x00000002L |
29883 | //PA_SC_HP3D_TRAP_SCREEN_H |
29884 | #define PA_SC_HP3D_TRAP_SCREEN_H__X_COORD__SHIFT 0x0 |
29885 | #define PA_SC_HP3D_TRAP_SCREEN_H__X_COORD_MASK 0x00003FFFL |
29886 | //PA_SC_HP3D_TRAP_SCREEN_V |
29887 | #define PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0 |
29888 | #define PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD_MASK 0x00003FFFL |
29889 | //PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE |
29890 | #define PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0 |
29891 | #define PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0x0000FFFFL |
29892 | //PA_SC_HP3D_TRAP_SCREEN_COUNT |
29893 | #define PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0 |
29894 | #define PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT_MASK 0x0000FFFFL |
29895 | //PA_SC_TRAP_SCREEN_HV_EN |
29896 | #define PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0 |
29897 | #define PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1 |
29898 | #define PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x00000001L |
29899 | #define PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x00000002L |
29900 | //PA_SC_TRAP_SCREEN_H |
29901 | #define PA_SC_TRAP_SCREEN_H__X_COORD__SHIFT 0x0 |
29902 | #define PA_SC_TRAP_SCREEN_H__X_COORD_MASK 0x00003FFFL |
29903 | //PA_SC_TRAP_SCREEN_V |
29904 | #define PA_SC_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0 |
29905 | #define PA_SC_TRAP_SCREEN_V__Y_COORD_MASK 0x00003FFFL |
29906 | //PA_SC_TRAP_SCREEN_OCCURRENCE |
29907 | #define PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0 |
29908 | #define PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0x0000FFFFL |
29909 | //PA_SC_TRAP_SCREEN_COUNT |
29910 | #define PA_SC_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0 |
29911 | #define PA_SC_TRAP_SCREEN_COUNT__COUNT_MASK 0x0000FFFFL |
29912 | //SQ_THREAD_TRACE_USERDATA_0 |
29913 | #define SQ_THREAD_TRACE_USERDATA_0__DATA__SHIFT 0x0 |
29914 | #define SQ_THREAD_TRACE_USERDATA_0__DATA_MASK 0xFFFFFFFFL |
29915 | //SQ_THREAD_TRACE_USERDATA_1 |
29916 | #define SQ_THREAD_TRACE_USERDATA_1__DATA__SHIFT 0x0 |
29917 | #define SQ_THREAD_TRACE_USERDATA_1__DATA_MASK 0xFFFFFFFFL |
29918 | //SQ_THREAD_TRACE_USERDATA_2 |
29919 | #define SQ_THREAD_TRACE_USERDATA_2__DATA__SHIFT 0x0 |
29920 | #define SQ_THREAD_TRACE_USERDATA_2__DATA_MASK 0xFFFFFFFFL |
29921 | //SQ_THREAD_TRACE_USERDATA_3 |
29922 | #define SQ_THREAD_TRACE_USERDATA_3__DATA__SHIFT 0x0 |
29923 | #define SQ_THREAD_TRACE_USERDATA_3__DATA_MASK 0xFFFFFFFFL |
29924 | //SQ_THREAD_TRACE_USERDATA_4 |
29925 | #define SQ_THREAD_TRACE_USERDATA_4__DATA__SHIFT 0x0 |
29926 | #define SQ_THREAD_TRACE_USERDATA_4__DATA_MASK 0xFFFFFFFFL |
29927 | //SQ_THREAD_TRACE_USERDATA_5 |
29928 | #define SQ_THREAD_TRACE_USERDATA_5__DATA__SHIFT 0x0 |
29929 | #define SQ_THREAD_TRACE_USERDATA_5__DATA_MASK 0xFFFFFFFFL |
29930 | //SQ_THREAD_TRACE_USERDATA_6 |
29931 | #define SQ_THREAD_TRACE_USERDATA_6__DATA__SHIFT 0x0 |
29932 | #define SQ_THREAD_TRACE_USERDATA_6__DATA_MASK 0xFFFFFFFFL |
29933 | //SQ_THREAD_TRACE_USERDATA_7 |
29934 | #define SQ_THREAD_TRACE_USERDATA_7__DATA__SHIFT 0x0 |
29935 | #define SQ_THREAD_TRACE_USERDATA_7__DATA_MASK 0xFFFFFFFFL |
29936 | //SQC_CACHES |
29937 | #define SQC_CACHES__TARGET_INST__SHIFT 0x0 |
29938 | #define SQC_CACHES__TARGET_DATA__SHIFT 0x1 |
29939 | #define SQC_CACHES__INVALIDATE__SHIFT 0x2 |
29940 | #define SQC_CACHES__COMPLETE__SHIFT 0x10 |
29941 | #define SQC_CACHES__TARGET_INST_MASK 0x00000001L |
29942 | #define SQC_CACHES__TARGET_DATA_MASK 0x00000002L |
29943 | #define SQC_CACHES__INVALIDATE_MASK 0x00000004L |
29944 | #define SQC_CACHES__COMPLETE_MASK 0x00010000L |
29945 | //TA_CS_BC_BASE_ADDR |
29946 | #define TA_CS_BC_BASE_ADDR__ADDRESS__SHIFT 0x0 |
29947 | #define TA_CS_BC_BASE_ADDR__ADDRESS_MASK 0xFFFFFFFFL |
29948 | //TA_CS_BC_BASE_ADDR_HI |
29949 | #define TA_CS_BC_BASE_ADDR_HI__ADDRESS__SHIFT 0x0 |
29950 | #define TA_CS_BC_BASE_ADDR_HI__ADDRESS_MASK 0x000000FFL |
29951 | //DB_OCCLUSION_COUNT0_LOW |
29952 | #define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW__SHIFT 0x0 |
29953 | #define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW_MASK 0xFFFFFFFFL |
29954 | //DB_OCCLUSION_COUNT0_HI |
29955 | #define DB_OCCLUSION_COUNT0_HI__COUNT_HI__SHIFT 0x0 |
29956 | #define DB_OCCLUSION_COUNT0_HI__COUNT_HI_MASK 0x7FFFFFFFL |
29957 | //DB_OCCLUSION_COUNT1_LOW |
29958 | #define DB_OCCLUSION_COUNT1_LOW__COUNT_LOW__SHIFT 0x0 |
29959 | #define DB_OCCLUSION_COUNT1_LOW__COUNT_LOW_MASK 0xFFFFFFFFL |
29960 | //DB_OCCLUSION_COUNT1_HI |
29961 | #define DB_OCCLUSION_COUNT1_HI__COUNT_HI__SHIFT 0x0 |
29962 | #define DB_OCCLUSION_COUNT1_HI__COUNT_HI_MASK 0x7FFFFFFFL |
29963 | //DB_OCCLUSION_COUNT2_LOW |
29964 | #define DB_OCCLUSION_COUNT2_LOW__COUNT_LOW__SHIFT 0x0 |
29965 | #define DB_OCCLUSION_COUNT2_LOW__COUNT_LOW_MASK 0xFFFFFFFFL |
29966 | //DB_OCCLUSION_COUNT2_HI |
29967 | #define DB_OCCLUSION_COUNT2_HI__COUNT_HI__SHIFT 0x0 |
29968 | #define DB_OCCLUSION_COUNT2_HI__COUNT_HI_MASK 0x7FFFFFFFL |
29969 | //DB_OCCLUSION_COUNT3_LOW |
29970 | #define DB_OCCLUSION_COUNT3_LOW__COUNT_LOW__SHIFT 0x0 |
29971 | #define DB_OCCLUSION_COUNT3_LOW__COUNT_LOW_MASK 0xFFFFFFFFL |
29972 | //DB_OCCLUSION_COUNT3_HI |
29973 | #define DB_OCCLUSION_COUNT3_HI__COUNT_HI__SHIFT 0x0 |
29974 | #define DB_OCCLUSION_COUNT3_HI__COUNT_HI_MASK 0x7FFFFFFFL |
29975 | //GDS_RD_ADDR |
29976 | #define GDS_RD_ADDR__READ_ADDR__SHIFT 0x0 |
29977 | #define GDS_RD_ADDR__READ_ADDR_MASK 0xFFFFFFFFL |
29978 | //GDS_RD_DATA |
29979 | #define GDS_RD_DATA__READ_DATA__SHIFT 0x0 |
29980 | #define GDS_RD_DATA__READ_DATA_MASK 0xFFFFFFFFL |
29981 | //GDS_RD_BURST_ADDR |
29982 | #define GDS_RD_BURST_ADDR__BURST_ADDR__SHIFT 0x0 |
29983 | #define GDS_RD_BURST_ADDR__BURST_ADDR_MASK 0xFFFFFFFFL |
29984 | //GDS_RD_BURST_COUNT |
29985 | #define GDS_RD_BURST_COUNT__BURST_COUNT__SHIFT 0x0 |
29986 | #define GDS_RD_BURST_COUNT__BURST_COUNT_MASK 0xFFFFFFFFL |
29987 | //GDS_RD_BURST_DATA |
29988 | #define GDS_RD_BURST_DATA__BURST_DATA__SHIFT 0x0 |
29989 | #define GDS_RD_BURST_DATA__BURST_DATA_MASK 0xFFFFFFFFL |
29990 | //GDS_WR_ADDR |
29991 | #define GDS_WR_ADDR__WRITE_ADDR__SHIFT 0x0 |
29992 | #define GDS_WR_ADDR__WRITE_ADDR_MASK 0xFFFFFFFFL |
29993 | //GDS_WR_DATA |
29994 | #define GDS_WR_DATA__WRITE_DATA__SHIFT 0x0 |
29995 | #define GDS_WR_DATA__WRITE_DATA_MASK 0xFFFFFFFFL |
29996 | //GDS_WR_BURST_ADDR |
29997 | #define GDS_WR_BURST_ADDR__WRITE_ADDR__SHIFT 0x0 |
29998 | #define GDS_WR_BURST_ADDR__WRITE_ADDR_MASK 0xFFFFFFFFL |
29999 | //GDS_WR_BURST_DATA |
30000 | #define GDS_WR_BURST_DATA__WRITE_DATA__SHIFT 0x0 |
30001 | #define GDS_WR_BURST_DATA__WRITE_DATA_MASK 0xFFFFFFFFL |
30002 | //GDS_WRITE_COMPLETE |
30003 | #define GDS_WRITE_COMPLETE__WRITE_COMPLETE__SHIFT 0x0 |
30004 | #define GDS_WRITE_COMPLETE__WRITE_COMPLETE_MASK 0xFFFFFFFFL |
30005 | //GDS_ATOM_CNTL |
30006 | #define GDS_ATOM_CNTL__AINC__SHIFT 0x0 |
30007 | #define GDS_ATOM_CNTL__UNUSED1__SHIFT 0x6 |
30008 | #define GDS_ATOM_CNTL__DMODE__SHIFT 0x8 |
30009 | #define GDS_ATOM_CNTL__UNUSED2__SHIFT 0xa |
30010 | #define GDS_ATOM_CNTL__AINC_MASK 0x0000003FL |
30011 | #define GDS_ATOM_CNTL__UNUSED1_MASK 0x000000C0L |
30012 | #define GDS_ATOM_CNTL__DMODE_MASK 0x00000300L |
30013 | #define GDS_ATOM_CNTL__UNUSED2_MASK 0xFFFFFC00L |
30014 | //GDS_ATOM_COMPLETE |
30015 | #define GDS_ATOM_COMPLETE__COMPLETE__SHIFT 0x0 |
30016 | #define GDS_ATOM_COMPLETE__UNUSED__SHIFT 0x1 |
30017 | #define GDS_ATOM_COMPLETE__COMPLETE_MASK 0x00000001L |
30018 | #define GDS_ATOM_COMPLETE__UNUSED_MASK 0xFFFFFFFEL |
30019 | //GDS_ATOM_BASE |
30020 | #define GDS_ATOM_BASE__BASE__SHIFT 0x0 |
30021 | #define GDS_ATOM_BASE__UNUSED__SHIFT 0xc |
30022 | #define GDS_ATOM_BASE__BASE_MASK 0x00000FFFL |
30023 | #define GDS_ATOM_BASE__UNUSED_MASK 0xFFFFF000L |
30024 | //GDS_ATOM_SIZE |
30025 | #define GDS_ATOM_SIZE__SIZE__SHIFT 0x0 |
30026 | #define GDS_ATOM_SIZE__UNUSED__SHIFT 0xd |
30027 | #define GDS_ATOM_SIZE__SIZE_MASK 0x00001FFFL |
30028 | #define GDS_ATOM_SIZE__UNUSED_MASK 0xFFFFE000L |
30029 | //GDS_ATOM_OFFSET0 |
30030 | #define GDS_ATOM_OFFSET0__OFFSET0__SHIFT 0x0 |
30031 | #define GDS_ATOM_OFFSET0__UNUSED__SHIFT 0x8 |
30032 | #define GDS_ATOM_OFFSET0__OFFSET0_MASK 0x000000FFL |
30033 | #define GDS_ATOM_OFFSET0__UNUSED_MASK 0xFFFFFF00L |
30034 | //GDS_ATOM_OFFSET1 |
30035 | #define GDS_ATOM_OFFSET1__OFFSET1__SHIFT 0x0 |
30036 | #define GDS_ATOM_OFFSET1__UNUSED__SHIFT 0x8 |
30037 | #define GDS_ATOM_OFFSET1__OFFSET1_MASK 0x000000FFL |
30038 | #define GDS_ATOM_OFFSET1__UNUSED_MASK 0xFFFFFF00L |
30039 | //GDS_ATOM_DST |
30040 | #define GDS_ATOM_DST__DST__SHIFT 0x0 |
30041 | #define GDS_ATOM_DST__DST_MASK 0xFFFFFFFFL |
30042 | //GDS_ATOM_OP |
30043 | #define GDS_ATOM_OP__OP__SHIFT 0x0 |
30044 | #define GDS_ATOM_OP__UNUSED__SHIFT 0x8 |
30045 | #define GDS_ATOM_OP__OP_MASK 0x000000FFL |
30046 | #define GDS_ATOM_OP__UNUSED_MASK 0xFFFFFF00L |
30047 | //GDS_ATOM_SRC0 |
30048 | #define GDS_ATOM_SRC0__DATA__SHIFT 0x0 |
30049 | #define GDS_ATOM_SRC0__DATA_MASK 0xFFFFFFFFL |
30050 | //GDS_ATOM_SRC0_U |
30051 | #define GDS_ATOM_SRC0_U__DATA__SHIFT 0x0 |
30052 | #define GDS_ATOM_SRC0_U__DATA_MASK 0xFFFFFFFFL |
30053 | //GDS_ATOM_SRC1 |
30054 | #define GDS_ATOM_SRC1__DATA__SHIFT 0x0 |
30055 | #define GDS_ATOM_SRC1__DATA_MASK 0xFFFFFFFFL |
30056 | //GDS_ATOM_SRC1_U |
30057 | #define GDS_ATOM_SRC1_U__DATA__SHIFT 0x0 |
30058 | #define GDS_ATOM_SRC1_U__DATA_MASK 0xFFFFFFFFL |
30059 | //GDS_ATOM_READ0 |
30060 | #define GDS_ATOM_READ0__DATA__SHIFT 0x0 |
30061 | #define GDS_ATOM_READ0__DATA_MASK 0xFFFFFFFFL |
30062 | //GDS_ATOM_READ0_U |
30063 | #define GDS_ATOM_READ0_U__DATA__SHIFT 0x0 |
30064 | #define GDS_ATOM_READ0_U__DATA_MASK 0xFFFFFFFFL |
30065 | //GDS_ATOM_READ1 |
30066 | #define GDS_ATOM_READ1__DATA__SHIFT 0x0 |
30067 | #define GDS_ATOM_READ1__DATA_MASK 0xFFFFFFFFL |
30068 | //GDS_ATOM_READ1_U |
30069 | #define GDS_ATOM_READ1_U__DATA__SHIFT 0x0 |
30070 | #define GDS_ATOM_READ1_U__DATA_MASK 0xFFFFFFFFL |
30071 | //GDS_GWS_RESOURCE_CNTL |
30072 | #define GDS_GWS_RESOURCE_CNTL__INDEX__SHIFT 0x0 |
30073 | #define GDS_GWS_RESOURCE_CNTL__UNUSED__SHIFT 0x6 |
30074 | #define GDS_GWS_RESOURCE_CNTL__INDEX_MASK 0x0000003FL |
30075 | #define GDS_GWS_RESOURCE_CNTL__UNUSED_MASK 0xFFFFFFC0L |
30076 | //GDS_GWS_RESOURCE |
30077 | #define GDS_GWS_RESOURCE__FLAG__SHIFT 0x0 |
30078 | #define GDS_GWS_RESOURCE__COUNTER__SHIFT 0x1 |
30079 | #define GDS_GWS_RESOURCE__TYPE__SHIFT 0xd |
30080 | #define GDS_GWS_RESOURCE__DED__SHIFT 0xe |
30081 | #define GDS_GWS_RESOURCE__RELEASE_ALL__SHIFT 0xf |
30082 | #define GDS_GWS_RESOURCE__HEAD_QUEUE__SHIFT 0x10 |
30083 | #define GDS_GWS_RESOURCE__HEAD_VALID__SHIFT 0x1d |
30084 | #define GDS_GWS_RESOURCE__HEAD_FLAG__SHIFT 0x1e |
30085 | #define GDS_GWS_RESOURCE__HALTED__SHIFT 0x1f |
30086 | #define GDS_GWS_RESOURCE__FLAG_MASK 0x00000001L |
30087 | #define GDS_GWS_RESOURCE__COUNTER_MASK 0x00001FFEL |
30088 | #define GDS_GWS_RESOURCE__TYPE_MASK 0x00002000L |
30089 | #define GDS_GWS_RESOURCE__DED_MASK 0x00004000L |
30090 | #define GDS_GWS_RESOURCE__RELEASE_ALL_MASK 0x00008000L |
30091 | #define GDS_GWS_RESOURCE__HEAD_QUEUE_MASK 0x1FFF0000L |
30092 | #define GDS_GWS_RESOURCE__HEAD_VALID_MASK 0x20000000L |
30093 | #define GDS_GWS_RESOURCE__HEAD_FLAG_MASK 0x40000000L |
30094 | #define GDS_GWS_RESOURCE__HALTED_MASK 0x80000000L |
30095 | //GDS_GWS_RESOURCE_CNT |
30096 | #define GDS_GWS_RESOURCE_CNT__RESOURCE_CNT__SHIFT 0x0 |
30097 | #define GDS_GWS_RESOURCE_CNT__UNUSED__SHIFT 0x10 |
30098 | #define GDS_GWS_RESOURCE_CNT__RESOURCE_CNT_MASK 0x0000FFFFL |
30099 | #define GDS_GWS_RESOURCE_CNT__UNUSED_MASK 0xFFFF0000L |
30100 | //GDS_OA_CNTL |
30101 | #define GDS_OA_CNTL__INDEX__SHIFT 0x0 |
30102 | #define GDS_OA_CNTL__UNUSED__SHIFT 0x4 |
30103 | #define GDS_OA_CNTL__INDEX_MASK 0x0000000FL |
30104 | #define GDS_OA_CNTL__UNUSED_MASK 0xFFFFFFF0L |
30105 | //GDS_OA_COUNTER |
30106 | #define GDS_OA_COUNTER__SPACE_AVAILABLE__SHIFT 0x0 |
30107 | #define GDS_OA_COUNTER__SPACE_AVAILABLE_MASK 0xFFFFFFFFL |
30108 | //GDS_OA_ADDRESS |
30109 | #define GDS_OA_ADDRESS__DS_ADDRESS__SHIFT 0x0 |
30110 | #define GDS_OA_ADDRESS__CRAWLER_TYPE__SHIFT 0x10 |
30111 | #define GDS_OA_ADDRESS__CRAWLER__SHIFT 0x14 |
30112 | #define GDS_OA_ADDRESS__UNUSED__SHIFT 0x18 |
30113 | #define GDS_OA_ADDRESS__NO_ALLOC__SHIFT 0x1e |
30114 | #define GDS_OA_ADDRESS__ENABLE__SHIFT 0x1f |
30115 | #define GDS_OA_ADDRESS__DS_ADDRESS_MASK 0x0000FFFFL |
30116 | #define GDS_OA_ADDRESS__CRAWLER_TYPE_MASK 0x000F0000L |
30117 | #define GDS_OA_ADDRESS__CRAWLER_MASK 0x00F00000L |
30118 | #define GDS_OA_ADDRESS__UNUSED_MASK 0x3F000000L |
30119 | #define GDS_OA_ADDRESS__NO_ALLOC_MASK 0x40000000L |
30120 | #define GDS_OA_ADDRESS__ENABLE_MASK 0x80000000L |
30121 | //GDS_OA_INCDEC |
30122 | #define GDS_OA_INCDEC__VALUE__SHIFT 0x0 |
30123 | #define GDS_OA_INCDEC__INCDEC__SHIFT 0x1f |
30124 | #define GDS_OA_INCDEC__VALUE_MASK 0x7FFFFFFFL |
30125 | #define GDS_OA_INCDEC__INCDEC_MASK 0x80000000L |
30126 | //GDS_OA_RING_SIZE |
30127 | #define GDS_OA_RING_SIZE__RING_SIZE__SHIFT 0x0 |
30128 | #define GDS_OA_RING_SIZE__RING_SIZE_MASK 0xFFFFFFFFL |
30129 | //GDS_STRMOUT_DWORDS_WRITTEN_0 |
30130 | #define GDS_STRMOUT_DWORDS_WRITTEN_0__DATA__SHIFT 0x0 |
30131 | #define GDS_STRMOUT_DWORDS_WRITTEN_0__DATA_MASK 0xFFFFFFFFL |
30132 | //GDS_STRMOUT_DWORDS_WRITTEN_1 |
30133 | #define GDS_STRMOUT_DWORDS_WRITTEN_1__DATA__SHIFT 0x0 |
30134 | #define GDS_STRMOUT_DWORDS_WRITTEN_1__DATA_MASK 0xFFFFFFFFL |
30135 | //GDS_STRMOUT_DWORDS_WRITTEN_2 |
30136 | #define GDS_STRMOUT_DWORDS_WRITTEN_2__DATA__SHIFT 0x0 |
30137 | #define GDS_STRMOUT_DWORDS_WRITTEN_2__DATA_MASK 0xFFFFFFFFL |
30138 | //GDS_STRMOUT_DWORDS_WRITTEN_3 |
30139 | #define GDS_STRMOUT_DWORDS_WRITTEN_3__DATA__SHIFT 0x0 |
30140 | #define GDS_STRMOUT_DWORDS_WRITTEN_3__DATA_MASK 0xFFFFFFFFL |
30141 | //GDS_GS_0 |
30142 | #define GDS_GS_0__DATA__SHIFT 0x0 |
30143 | #define GDS_GS_0__DATA_MASK 0xFFFFFFFFL |
30144 | //GDS_GS_1 |
30145 | #define GDS_GS_1__DATA__SHIFT 0x0 |
30146 | #define GDS_GS_1__DATA_MASK 0xFFFFFFFFL |
30147 | //GDS_GS_2 |
30148 | #define GDS_GS_2__DATA__SHIFT 0x0 |
30149 | #define GDS_GS_2__DATA_MASK 0xFFFFFFFFL |
30150 | //GDS_GS_3 |
30151 | #define GDS_GS_3__DATA__SHIFT 0x0 |
30152 | #define GDS_GS_3__DATA_MASK 0xFFFFFFFFL |
30153 | //GDS_STRMOUT_PRIMS_NEEDED_0_LO |
30154 | #define GDS_STRMOUT_PRIMS_NEEDED_0_LO__DATA__SHIFT 0x0 |
30155 | #define GDS_STRMOUT_PRIMS_NEEDED_0_LO__DATA_MASK 0xFFFFFFFFL |
30156 | //GDS_STRMOUT_PRIMS_NEEDED_0_HI |
30157 | #define GDS_STRMOUT_PRIMS_NEEDED_0_HI__DATA__SHIFT 0x0 |
30158 | #define GDS_STRMOUT_PRIMS_NEEDED_0_HI__DATA_MASK 0xFFFFFFFFL |
30159 | //GDS_STRMOUT_PRIMS_WRITTEN_0_LO |
30160 | #define GDS_STRMOUT_PRIMS_WRITTEN_0_LO__DATA__SHIFT 0x0 |
30161 | #define GDS_STRMOUT_PRIMS_WRITTEN_0_LO__DATA_MASK 0xFFFFFFFFL |
30162 | //GDS_STRMOUT_PRIMS_WRITTEN_0_HI |
30163 | #define GDS_STRMOUT_PRIMS_WRITTEN_0_HI__DATA__SHIFT 0x0 |
30164 | #define GDS_STRMOUT_PRIMS_WRITTEN_0_HI__DATA_MASK 0xFFFFFFFFL |
30165 | //GDS_STRMOUT_PRIMS_NEEDED_1_LO |
30166 | #define GDS_STRMOUT_PRIMS_NEEDED_1_LO__DATA__SHIFT 0x0 |
30167 | #define GDS_STRMOUT_PRIMS_NEEDED_1_LO__DATA_MASK 0xFFFFFFFFL |
30168 | //GDS_STRMOUT_PRIMS_NEEDED_1_HI |
30169 | #define GDS_STRMOUT_PRIMS_NEEDED_1_HI__DATA__SHIFT 0x0 |
30170 | #define GDS_STRMOUT_PRIMS_NEEDED_1_HI__DATA_MASK 0xFFFFFFFFL |
30171 | //GDS_STRMOUT_PRIMS_WRITTEN_1_LO |
30172 | #define GDS_STRMOUT_PRIMS_WRITTEN_1_LO__DATA__SHIFT 0x0 |
30173 | #define GDS_STRMOUT_PRIMS_WRITTEN_1_LO__DATA_MASK 0xFFFFFFFFL |
30174 | //GDS_STRMOUT_PRIMS_WRITTEN_1_HI |
30175 | #define GDS_STRMOUT_PRIMS_WRITTEN_1_HI__DATA__SHIFT 0x0 |
30176 | #define GDS_STRMOUT_PRIMS_WRITTEN_1_HI__DATA_MASK 0xFFFFFFFFL |
30177 | //GDS_STRMOUT_PRIMS_NEEDED_2_LO |
30178 | #define GDS_STRMOUT_PRIMS_NEEDED_2_LO__DATA__SHIFT 0x0 |
30179 | #define GDS_STRMOUT_PRIMS_NEEDED_2_LO__DATA_MASK 0xFFFFFFFFL |
30180 | //GDS_STRMOUT_PRIMS_NEEDED_2_HI |
30181 | #define GDS_STRMOUT_PRIMS_NEEDED_2_HI__DATA__SHIFT 0x0 |
30182 | #define GDS_STRMOUT_PRIMS_NEEDED_2_HI__DATA_MASK 0xFFFFFFFFL |
30183 | //GDS_STRMOUT_PRIMS_WRITTEN_2_LO |
30184 | #define GDS_STRMOUT_PRIMS_WRITTEN_2_LO__DATA__SHIFT 0x0 |
30185 | #define GDS_STRMOUT_PRIMS_WRITTEN_2_LO__DATA_MASK 0xFFFFFFFFL |
30186 | //GDS_STRMOUT_PRIMS_WRITTEN_2_HI |
30187 | #define GDS_STRMOUT_PRIMS_WRITTEN_2_HI__DATA__SHIFT 0x0 |
30188 | #define GDS_STRMOUT_PRIMS_WRITTEN_2_HI__DATA_MASK 0xFFFFFFFFL |
30189 | //GDS_STRMOUT_PRIMS_NEEDED_3_LO |
30190 | #define GDS_STRMOUT_PRIMS_NEEDED_3_LO__DATA__SHIFT 0x0 |
30191 | #define GDS_STRMOUT_PRIMS_NEEDED_3_LO__DATA_MASK 0xFFFFFFFFL |
30192 | //GDS_STRMOUT_PRIMS_NEEDED_3_HI |
30193 | #define GDS_STRMOUT_PRIMS_NEEDED_3_HI__DATA__SHIFT 0x0 |
30194 | #define GDS_STRMOUT_PRIMS_NEEDED_3_HI__DATA_MASK 0xFFFFFFFFL |
30195 | //GDS_STRMOUT_PRIMS_WRITTEN_3_LO |
30196 | #define GDS_STRMOUT_PRIMS_WRITTEN_3_LO__DATA__SHIFT 0x0 |
30197 | #define GDS_STRMOUT_PRIMS_WRITTEN_3_LO__DATA_MASK 0xFFFFFFFFL |
30198 | //GDS_STRMOUT_PRIMS_WRITTEN_3_HI |
30199 | #define GDS_STRMOUT_PRIMS_WRITTEN_3_HI__DATA__SHIFT 0x0 |
30200 | #define GDS_STRMOUT_PRIMS_WRITTEN_3_HI__DATA_MASK 0xFFFFFFFFL |
30201 | //SPI_CONFIG_CNTL |
30202 | #define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY__SHIFT 0x0 |
30203 | #define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER__SHIFT 0x15 |
30204 | #define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS__SHIFT 0x18 |
30205 | #define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS__SHIFT 0x19 |
30206 | #define SPI_CONFIG_CNTL__ALLOC_ARB_LRU_ENA__SHIFT 0x1c |
30207 | #define SPI_CONFIG_CNTL__EXP_ARB_LRU_ENA__SHIFT 0x1d |
30208 | #define SPI_CONFIG_CNTL__PS_PKR_PRIORITY_CNTL__SHIFT 0x1e |
30209 | #define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY_MASK 0x001FFFFFL |
30210 | #define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER_MASK 0x00E00000L |
30211 | #define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS_MASK 0x01000000L |
30212 | #define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS_MASK 0x02000000L |
30213 | #define SPI_CONFIG_CNTL__ALLOC_ARB_LRU_ENA_MASK 0x10000000L |
30214 | #define SPI_CONFIG_CNTL__EXP_ARB_LRU_ENA_MASK 0x20000000L |
30215 | #define SPI_CONFIG_CNTL__PS_PKR_PRIORITY_CNTL_MASK 0xC0000000L |
30216 | //SPI_CONFIG_CNTL_1 |
30217 | #define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT 0x0 |
30218 | #define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW__SHIFT 0x4 |
30219 | #define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE__SHIFT 0x5 |
30220 | #define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT__SHIFT 0x7 |
30221 | #define SPI_CONFIG_CNTL_1__PS_GROUP_TIMEOUT_MODE__SHIFT 0x8 |
30222 | #define SPI_CONFIG_CNTL_1__OREO_EXPALLOC_STALL__SHIFT 0x9 |
30223 | #define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT__SHIFT 0xa |
30224 | #define SPI_CONFIG_CNTL_1__CSC_PWR_SAVE_DISABLE__SHIFT 0xe |
30225 | #define SPI_CONFIG_CNTL_1__CSG_PWR_SAVE_DISABLE__SHIFT 0xf |
30226 | #define SPI_CONFIG_CNTL_1__MAX_VTX_SYNC_CNT__SHIFT 0x10 |
30227 | #define SPI_CONFIG_CNTL_1__EN_USER_ACCUM__SHIFT 0x15 |
30228 | #define SPI_CONFIG_CNTL_1__SA_SCREEN_MAP__SHIFT 0x16 |
30229 | #define SPI_CONFIG_CNTL_1__PS_GROUP_TIMEOUT__SHIFT 0x17 |
30230 | #define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY_MASK 0x0000000FL |
30231 | #define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW_MASK 0x00000010L |
30232 | #define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE_MASK 0x00000060L |
30233 | #define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT_MASK 0x00000080L |
30234 | #define SPI_CONFIG_CNTL_1__PS_GROUP_TIMEOUT_MODE_MASK 0x00000100L |
30235 | #define SPI_CONFIG_CNTL_1__OREO_EXPALLOC_STALL_MASK 0x00000200L |
30236 | #define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT_MASK 0x00003C00L |
30237 | #define SPI_CONFIG_CNTL_1__CSC_PWR_SAVE_DISABLE_MASK 0x00004000L |
30238 | #define SPI_CONFIG_CNTL_1__CSG_PWR_SAVE_DISABLE_MASK 0x00008000L |
30239 | #define SPI_CONFIG_CNTL_1__MAX_VTX_SYNC_CNT_MASK 0x001F0000L |
30240 | #define SPI_CONFIG_CNTL_1__EN_USER_ACCUM_MASK 0x00200000L |
30241 | #define SPI_CONFIG_CNTL_1__SA_SCREEN_MAP_MASK 0x00400000L |
30242 | #define SPI_CONFIG_CNTL_1__PS_GROUP_TIMEOUT_MASK 0xFF800000L |
30243 | //SPI_CONFIG_CNTL_2 |
30244 | #define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD__SHIFT 0x0 |
30245 | #define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD__SHIFT 0x4 |
30246 | #define SPI_CONFIG_CNTL_2__PWS_CSG_WAIT_DISABLE__SHIFT 0x8 |
30247 | #define SPI_CONFIG_CNTL_2__PWS_HS_WAIT_DISABLE__SHIFT 0x9 |
30248 | #define SPI_CONFIG_CNTL_2__PWS_GS_WAIT_DISABLE__SHIFT 0xa |
30249 | #define SPI_CONFIG_CNTL_2__PWS_PS_WAIT_DISABLE__SHIFT 0xb |
30250 | #define SPI_CONFIG_CNTL_2__CSC_HALT_ACK_DELAY__SHIFT 0xc |
30251 | #define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD_MASK 0x0000000FL |
30252 | #define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD_MASK 0x000000F0L |
30253 | #define SPI_CONFIG_CNTL_2__PWS_CSG_WAIT_DISABLE_MASK 0x00000100L |
30254 | #define SPI_CONFIG_CNTL_2__PWS_HS_WAIT_DISABLE_MASK 0x00000200L |
30255 | #define SPI_CONFIG_CNTL_2__PWS_GS_WAIT_DISABLE_MASK 0x00000400L |
30256 | #define SPI_CONFIG_CNTL_2__PWS_PS_WAIT_DISABLE_MASK 0x00000800L |
30257 | #define SPI_CONFIG_CNTL_2__CSC_HALT_ACK_DELAY_MASK 0x0001F000L |
30258 | //SPI_WAVE_LIMIT_CNTL |
30259 | #define SPI_WAVE_LIMIT_CNTL__PS_WAVE_GRAN__SHIFT 0x0 |
30260 | #define SPI_WAVE_LIMIT_CNTL__GS_WAVE_GRAN__SHIFT 0x4 |
30261 | #define SPI_WAVE_LIMIT_CNTL__HS_WAVE_GRAN__SHIFT 0x6 |
30262 | #define SPI_WAVE_LIMIT_CNTL__PS_WAVE_GRAN_MASK 0x00000003L |
30263 | #define SPI_WAVE_LIMIT_CNTL__GS_WAVE_GRAN_MASK 0x00000030L |
30264 | #define SPI_WAVE_LIMIT_CNTL__HS_WAVE_GRAN_MASK 0x000000C0L |
30265 | //SPI_GS_THROTTLE_CNTL1 |
30266 | #define SPI_GS_THROTTLE_CNTL1__PH_POLL_INTERVAL__SHIFT 0x0 |
30267 | #define SPI_GS_THROTTLE_CNTL1__PH_THROTTLE_BASE__SHIFT 0x4 |
30268 | #define SPI_GS_THROTTLE_CNTL1__PH_THROTTLE_STEP_SIZE__SHIFT 0x8 |
30269 | #define SPI_GS_THROTTLE_CNTL1__SPI_VGPR_THRESHOLD__SHIFT 0xc |
30270 | #define SPI_GS_THROTTLE_CNTL1__SPI_LDS_THRESHOLD__SHIFT 0x10 |
30271 | #define SPI_GS_THROTTLE_CNTL1__SPI_POLL_INTERVAL__SHIFT 0x14 |
30272 | #define SPI_GS_THROTTLE_CNTL1__SPI_THROTTLE_BASE__SHIFT 0x18 |
30273 | #define SPI_GS_THROTTLE_CNTL1__SPI_THROTTLE_STEP_SIZE__SHIFT 0x1c |
30274 | #define SPI_GS_THROTTLE_CNTL1__PH_POLL_INTERVAL_MASK 0x0000000FL |
30275 | #define SPI_GS_THROTTLE_CNTL1__PH_THROTTLE_BASE_MASK 0x000000F0L |
30276 | #define SPI_GS_THROTTLE_CNTL1__PH_THROTTLE_STEP_SIZE_MASK 0x00000F00L |
30277 | #define SPI_GS_THROTTLE_CNTL1__SPI_VGPR_THRESHOLD_MASK 0x0000F000L |
30278 | #define SPI_GS_THROTTLE_CNTL1__SPI_LDS_THRESHOLD_MASK 0x000F0000L |
30279 | #define SPI_GS_THROTTLE_CNTL1__SPI_POLL_INTERVAL_MASK 0x00F00000L |
30280 | #define SPI_GS_THROTTLE_CNTL1__SPI_THROTTLE_BASE_MASK 0x0F000000L |
30281 | #define SPI_GS_THROTTLE_CNTL1__SPI_THROTTLE_STEP_SIZE_MASK 0xF0000000L |
30282 | //SPI_GS_THROTTLE_CNTL2 |
30283 | #define SPI_GS_THROTTLE_CNTL2__SPI_THROTTLE_MODE__SHIFT 0x0 |
30284 | #define SPI_GS_THROTTLE_CNTL2__GRP_LIFETIME_THRESHOLD__SHIFT 0x2 |
30285 | #define SPI_GS_THROTTLE_CNTL2__GRP_LIFETIME_THRESHOLD_FACTOR__SHIFT 0x6 |
30286 | #define SPI_GS_THROTTLE_CNTL2__GRP_LIFETIME_PENALTY1__SHIFT 0x8 |
30287 | #define SPI_GS_THROTTLE_CNTL2__GRP_LIFETIME_PENALTY2__SHIFT 0xb |
30288 | #define SPI_GS_THROTTLE_CNTL2__PS_STALL_THRESHOLD__SHIFT 0xe |
30289 | #define SPI_GS_THROTTLE_CNTL2__PH_MODE__SHIFT 0x10 |
30290 | #define SPI_GS_THROTTLE_CNTL2__RESERVED__SHIFT 0x11 |
30291 | #define SPI_GS_THROTTLE_CNTL2__SPI_THROTTLE_MODE_MASK 0x00000003L |
30292 | #define SPI_GS_THROTTLE_CNTL2__GRP_LIFETIME_THRESHOLD_MASK 0x0000003CL |
30293 | #define SPI_GS_THROTTLE_CNTL2__GRP_LIFETIME_THRESHOLD_FACTOR_MASK 0x000000C0L |
30294 | #define SPI_GS_THROTTLE_CNTL2__GRP_LIFETIME_PENALTY1_MASK 0x00000700L |
30295 | #define SPI_GS_THROTTLE_CNTL2__GRP_LIFETIME_PENALTY2_MASK 0x00003800L |
30296 | #define SPI_GS_THROTTLE_CNTL2__PS_STALL_THRESHOLD_MASK 0x0000C000L |
30297 | #define SPI_GS_THROTTLE_CNTL2__PH_MODE_MASK 0x00010000L |
30298 | #define SPI_GS_THROTTLE_CNTL2__RESERVED_MASK 0xFFFE0000L |
30299 | //SPI_ATTRIBUTE_RING_BASE |
30300 | #define SPI_ATTRIBUTE_RING_BASE__BASE__SHIFT 0x0 |
30301 | #define SPI_ATTRIBUTE_RING_BASE__BASE_MASK 0xFFFFFFFFL |
30302 | //SPI_ATTRIBUTE_RING_SIZE |
30303 | #define SPI_ATTRIBUTE_RING_SIZE__MEM_SIZE__SHIFT 0x0 |
30304 | #define SPI_ATTRIBUTE_RING_SIZE__BIG_PAGE__SHIFT 0x10 |
30305 | #define SPI_ATTRIBUTE_RING_SIZE__L1_POLICY__SHIFT 0x11 |
30306 | #define SPI_ATTRIBUTE_RING_SIZE__L2_POLICY__SHIFT 0x13 |
30307 | #define SPI_ATTRIBUTE_RING_SIZE__LLC_NOALLOC__SHIFT 0x15 |
30308 | #define SPI_ATTRIBUTE_RING_SIZE__GL1_PERF_COUNTER_DISABLE__SHIFT 0x16 |
30309 | #define SPI_ATTRIBUTE_RING_SIZE__MEM_SIZE_MASK 0x000000FFL |
30310 | #define SPI_ATTRIBUTE_RING_SIZE__BIG_PAGE_MASK 0x00010000L |
30311 | #define SPI_ATTRIBUTE_RING_SIZE__L1_POLICY_MASK 0x00060000L |
30312 | #define SPI_ATTRIBUTE_RING_SIZE__L2_POLICY_MASK 0x00180000L |
30313 | #define SPI_ATTRIBUTE_RING_SIZE__LLC_NOALLOC_MASK 0x00200000L |
30314 | #define SPI_ATTRIBUTE_RING_SIZE__GL1_PERF_COUNTER_DISABLE_MASK 0x00400000L |
30315 | |
30316 | |
30317 | // addressBlock: gc_cprs64dec |
30318 | //CP_MES_PRGRM_CNTR_START |
30319 | #define CP_MES_PRGRM_CNTR_START__IP_START__SHIFT 0x0 |
30320 | #define CP_MES_PRGRM_CNTR_START__IP_START_MASK 0xFFFFFFFFL |
30321 | //CP_MES_INTR_ROUTINE_START |
30322 | #define CP_MES_INTR_ROUTINE_START__IR_START__SHIFT 0x0 |
30323 | #define CP_MES_INTR_ROUTINE_START__IR_START_MASK 0xFFFFFFFFL |
30324 | //CP_MES_MTVEC_LO |
30325 | #define CP_MES_MTVEC_LO__ADDR_LO__SHIFT 0x0 |
30326 | #define CP_MES_MTVEC_LO__ADDR_LO_MASK 0xFFFFFFFFL |
30327 | //CP_MES_INTR_ROUTINE_START_HI |
30328 | #define CP_MES_INTR_ROUTINE_START_HI__IR_START__SHIFT 0x0 |
30329 | #define CP_MES_INTR_ROUTINE_START_HI__IR_START_MASK 0xFFFFFFFFL |
30330 | //CP_MES_MTVEC_HI |
30331 | #define CP_MES_MTVEC_HI__ADDR_LO__SHIFT 0x0 |
30332 | #define CP_MES_MTVEC_HI__ADDR_LO_MASK 0xFFFFFFFFL |
30333 | //CP_MES_CNTL |
30334 | #define CP_MES_CNTL__MES_INVALIDATE_ICACHE__SHIFT 0x4 |
30335 | #define CP_MES_CNTL__MES_PIPE0_RESET__SHIFT 0x10 |
30336 | #define CP_MES_CNTL__MES_PIPE1_RESET__SHIFT 0x11 |
30337 | #define CP_MES_CNTL__MES_PIPE2_RESET__SHIFT 0x12 |
30338 | #define CP_MES_CNTL__MES_PIPE3_RESET__SHIFT 0x13 |
30339 | #define CP_MES_CNTL__MES_PIPE0_ACTIVE__SHIFT 0x1a |
30340 | #define CP_MES_CNTL__MES_PIPE1_ACTIVE__SHIFT 0x1b |
30341 | #define CP_MES_CNTL__MES_PIPE2_ACTIVE__SHIFT 0x1c |
30342 | #define CP_MES_CNTL__MES_PIPE3_ACTIVE__SHIFT 0x1d |
30343 | #define CP_MES_CNTL__MES_HALT__SHIFT 0x1e |
30344 | #define CP_MES_CNTL__MES_STEP__SHIFT 0x1f |
30345 | #define CP_MES_CNTL__MES_INVALIDATE_ICACHE_MASK 0x00000010L |
30346 | #define CP_MES_CNTL__MES_PIPE0_RESET_MASK 0x00010000L |
30347 | #define CP_MES_CNTL__MES_PIPE1_RESET_MASK 0x00020000L |
30348 | #define CP_MES_CNTL__MES_PIPE2_RESET_MASK 0x00040000L |
30349 | #define CP_MES_CNTL__MES_PIPE3_RESET_MASK 0x00080000L |
30350 | #define CP_MES_CNTL__MES_PIPE0_ACTIVE_MASK 0x04000000L |
30351 | #define CP_MES_CNTL__MES_PIPE1_ACTIVE_MASK 0x08000000L |
30352 | #define CP_MES_CNTL__MES_PIPE2_ACTIVE_MASK 0x10000000L |
30353 | #define CP_MES_CNTL__MES_PIPE3_ACTIVE_MASK 0x20000000L |
30354 | #define CP_MES_CNTL__MES_HALT_MASK 0x40000000L |
30355 | #define CP_MES_CNTL__MES_STEP_MASK 0x80000000L |
30356 | //CP_MES_PIPE_PRIORITY_CNTS |
30357 | #define CP_MES_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0 |
30358 | #define CP_MES_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8 |
30359 | #define CP_MES_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10 |
30360 | #define CP_MES_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18 |
30361 | #define CP_MES_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL |
30362 | #define CP_MES_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L |
30363 | #define CP_MES_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L |
30364 | #define CP_MES_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L |
30365 | //CP_MES_PIPE0_PRIORITY |
30366 | #define CP_MES_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0 |
30367 | #define CP_MES_PIPE0_PRIORITY__PRIORITY_MASK 0x00000003L |
30368 | //CP_MES_PIPE1_PRIORITY |
30369 | #define CP_MES_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0 |
30370 | #define CP_MES_PIPE1_PRIORITY__PRIORITY_MASK 0x00000003L |
30371 | //CP_MES_PIPE2_PRIORITY |
30372 | #define CP_MES_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0 |
30373 | #define CP_MES_PIPE2_PRIORITY__PRIORITY_MASK 0x00000003L |
30374 | //CP_MES_PIPE3_PRIORITY |
30375 | #define CP_MES_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0 |
30376 | #define CP_MES_PIPE3_PRIORITY__PRIORITY_MASK 0x00000003L |
30377 | //CP_MES_HEADER_DUMP |
30378 | #define 0x0 |
30379 | #define 0xFFFFFFFFL |
30380 | //CP_MES_MIE_LO |
30381 | #define CP_MES_MIE_LO__MES_INT__SHIFT 0x0 |
30382 | #define CP_MES_MIE_LO__MES_INT_MASK 0xFFFFFFFFL |
30383 | //CP_MES_MIE_HI |
30384 | #define CP_MES_MIE_HI__MES_INT__SHIFT 0x0 |
30385 | #define CP_MES_MIE_HI__MES_INT_MASK 0xFFFFFFFFL |
30386 | //CP_MES_INTERRUPT |
30387 | #define CP_MES_INTERRUPT__MES_INT__SHIFT 0x0 |
30388 | #define CP_MES_INTERRUPT__MES_INT_MASK 0xFFFFFFFFL |
30389 | //CP_MES_SCRATCH_INDEX |
30390 | #define CP_MES_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0 |
30391 | #define CP_MES_SCRATCH_INDEX__SCRATCH_INDEX_64BIT_MODE__SHIFT 0x1f |
30392 | #define CP_MES_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0x000001FFL |
30393 | #define CP_MES_SCRATCH_INDEX__SCRATCH_INDEX_64BIT_MODE_MASK 0x80000000L |
30394 | //CP_MES_SCRATCH_DATA |
30395 | #define CP_MES_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0 |
30396 | #define CP_MES_SCRATCH_DATA__SCRATCH_DATA_MASK 0xFFFFFFFFL |
30397 | //CP_MES_INSTR_PNTR |
30398 | #define CP_MES_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0 |
30399 | #define CP_MES_INSTR_PNTR__INSTR_PNTR_MASK 0x000FFFFFL |
30400 | //CP_MES_MSCRATCH_HI |
30401 | #define CP_MES_MSCRATCH_HI__DATA__SHIFT 0x0 |
30402 | #define CP_MES_MSCRATCH_HI__DATA_MASK 0xFFFFFFFFL |
30403 | //CP_MES_MSCRATCH_LO |
30404 | #define CP_MES_MSCRATCH_LO__DATA__SHIFT 0x0 |
30405 | #define CP_MES_MSCRATCH_LO__DATA_MASK 0xFFFFFFFFL |
30406 | //CP_MES_MSTATUS_LO |
30407 | #define CP_MES_MSTATUS_LO__STATUS_LO__SHIFT 0x0 |
30408 | #define CP_MES_MSTATUS_LO__STATUS_LO_MASK 0xFFFFFFFFL |
30409 | //CP_MES_MSTATUS_HI |
30410 | #define CP_MES_MSTATUS_HI__STATUS_HI__SHIFT 0x0 |
30411 | #define CP_MES_MSTATUS_HI__STATUS_HI_MASK 0xFFFFFFFFL |
30412 | //CP_MES_MEPC_LO |
30413 | #define CP_MES_MEPC_LO__MEPC_LO__SHIFT 0x0 |
30414 | #define CP_MES_MEPC_LO__MEPC_LO_MASK 0xFFFFFFFFL |
30415 | //CP_MES_MEPC_HI |
30416 | #define CP_MES_MEPC_HI__MEPC_HI__SHIFT 0x0 |
30417 | #define CP_MES_MEPC_HI__MEPC_HI_MASK 0xFFFFFFFFL |
30418 | //CP_MES_MCAUSE_LO |
30419 | #define CP_MES_MCAUSE_LO__CAUSE_LO__SHIFT 0x0 |
30420 | #define CP_MES_MCAUSE_LO__CAUSE_LO_MASK 0xFFFFFFFFL |
30421 | //CP_MES_MCAUSE_HI |
30422 | #define CP_MES_MCAUSE_HI__CAUSE_HI__SHIFT 0x0 |
30423 | #define CP_MES_MCAUSE_HI__CAUSE_HI_MASK 0xFFFFFFFFL |
30424 | //CP_MES_MBADADDR_LO |
30425 | #define CP_MES_MBADADDR_LO__ADDR_LO__SHIFT 0x0 |
30426 | #define CP_MES_MBADADDR_LO__ADDR_LO_MASK 0xFFFFFFFFL |
30427 | //CP_MES_MBADADDR_HI |
30428 | #define CP_MES_MBADADDR_HI__ADDR_HI__SHIFT 0x0 |
30429 | #define CP_MES_MBADADDR_HI__ADDR_HI_MASK 0xFFFFFFFFL |
30430 | //CP_MES_MIP_LO |
30431 | #define CP_MES_MIP_LO__MIP_LO__SHIFT 0x0 |
30432 | #define CP_MES_MIP_LO__MIP_LO_MASK 0xFFFFFFFFL |
30433 | //CP_MES_MIP_HI |
30434 | #define CP_MES_MIP_HI__MIP_HI__SHIFT 0x0 |
30435 | #define CP_MES_MIP_HI__MIP_HI_MASK 0xFFFFFFFFL |
30436 | //CP_MES_IC_OP_CNTL |
30437 | #define CP_MES_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT 0x0 |
30438 | #define CP_MES_IC_OP_CNTL__PRIME_ICACHE__SHIFT 0x4 |
30439 | #define CP_MES_IC_OP_CNTL__ICACHE_PRIMED__SHIFT 0x5 |
30440 | #define CP_MES_IC_OP_CNTL__INVALIDATE_CACHE_MASK 0x00000001L |
30441 | #define CP_MES_IC_OP_CNTL__PRIME_ICACHE_MASK 0x00000010L |
30442 | #define CP_MES_IC_OP_CNTL__ICACHE_PRIMED_MASK 0x00000020L |
30443 | //CP_MES_MCYCLE_LO |
30444 | #define CP_MES_MCYCLE_LO__CYCLE_LO__SHIFT 0x0 |
30445 | #define CP_MES_MCYCLE_LO__CYCLE_LO_MASK 0xFFFFFFFFL |
30446 | //CP_MES_MCYCLE_HI |
30447 | #define CP_MES_MCYCLE_HI__CYCLE_HI__SHIFT 0x0 |
30448 | #define CP_MES_MCYCLE_HI__CYCLE_HI_MASK 0xFFFFFFFFL |
30449 | //CP_MES_MTIME_LO |
30450 | #define CP_MES_MTIME_LO__TIME_LO__SHIFT 0x0 |
30451 | #define CP_MES_MTIME_LO__TIME_LO_MASK 0xFFFFFFFFL |
30452 | //CP_MES_MTIME_HI |
30453 | #define CP_MES_MTIME_HI__TIME_HI__SHIFT 0x0 |
30454 | #define CP_MES_MTIME_HI__TIME_HI_MASK 0xFFFFFFFFL |
30455 | //CP_MES_MINSTRET_LO |
30456 | #define CP_MES_MINSTRET_LO__INSTRET_LO__SHIFT 0x0 |
30457 | #define CP_MES_MINSTRET_LO__INSTRET_LO_MASK 0xFFFFFFFFL |
30458 | //CP_MES_MINSTRET_HI |
30459 | #define CP_MES_MINSTRET_HI__INSTRET_HI__SHIFT 0x0 |
30460 | #define CP_MES_MINSTRET_HI__INSTRET_HI_MASK 0xFFFFFFFFL |
30461 | //CP_MES_MISA_LO |
30462 | #define CP_MES_MISA_LO__MISA_LO__SHIFT 0x0 |
30463 | #define CP_MES_MISA_LO__MISA_LO_MASK 0xFFFFFFFFL |
30464 | //CP_MES_MISA_HI |
30465 | #define CP_MES_MISA_HI__MISA_HI__SHIFT 0x0 |
30466 | #define CP_MES_MISA_HI__MISA_HI_MASK 0xFFFFFFFFL |
30467 | //CP_MES_MVENDORID_LO |
30468 | #define CP_MES_MVENDORID_LO__MVENDORID_LO__SHIFT 0x0 |
30469 | #define CP_MES_MVENDORID_LO__MVENDORID_LO_MASK 0xFFFFFFFFL |
30470 | //CP_MES_MVENDORID_HI |
30471 | #define CP_MES_MVENDORID_HI__MVENDORID_HI__SHIFT 0x0 |
30472 | #define CP_MES_MVENDORID_HI__MVENDORID_HI_MASK 0xFFFFFFFFL |
30473 | //CP_MES_MARCHID_LO |
30474 | #define CP_MES_MARCHID_LO__MARCHID_LO__SHIFT 0x0 |
30475 | #define CP_MES_MARCHID_LO__MARCHID_LO_MASK 0xFFFFFFFFL |
30476 | //CP_MES_MARCHID_HI |
30477 | #define CP_MES_MARCHID_HI__MARCHID_HI__SHIFT 0x0 |
30478 | #define CP_MES_MARCHID_HI__MARCHID_HI_MASK 0xFFFFFFFFL |
30479 | //CP_MES_MIMPID_LO |
30480 | #define CP_MES_MIMPID_LO__MIMPID_LO__SHIFT 0x0 |
30481 | #define CP_MES_MIMPID_LO__MIMPID_LO_MASK 0xFFFFFFFFL |
30482 | //CP_MES_MIMPID_HI |
30483 | #define CP_MES_MIMPID_HI__MIMPID_HI__SHIFT 0x0 |
30484 | #define CP_MES_MIMPID_HI__MIMPID_HI_MASK 0xFFFFFFFFL |
30485 | //CP_MES_MHARTID_LO |
30486 | #define CP_MES_MHARTID_LO__MHARTID_LO__SHIFT 0x0 |
30487 | #define CP_MES_MHARTID_LO__MHARTID_LO_MASK 0xFFFFFFFFL |
30488 | //CP_MES_MHARTID_HI |
30489 | #define CP_MES_MHARTID_HI__MHARTID_HI__SHIFT 0x0 |
30490 | #define CP_MES_MHARTID_HI__MHARTID_HI_MASK 0xFFFFFFFFL |
30491 | //CP_MES_DC_BASE_CNTL |
30492 | #define CP_MES_DC_BASE_CNTL__VMID__SHIFT 0x0 |
30493 | #define CP_MES_DC_BASE_CNTL__CACHE_POLICY__SHIFT 0x18 |
30494 | #define CP_MES_DC_BASE_CNTL__VMID_MASK 0x0000000FL |
30495 | #define CP_MES_DC_BASE_CNTL__CACHE_POLICY_MASK 0x03000000L |
30496 | //CP_MES_DC_OP_CNTL |
30497 | #define CP_MES_DC_OP_CNTL__INVALIDATE_DCACHE__SHIFT 0x0 |
30498 | #define CP_MES_DC_OP_CNTL__INVALIDATE_DCACHE_COMPLETE__SHIFT 0x1 |
30499 | #define CP_MES_DC_OP_CNTL__BYPASS_ALL__SHIFT 0x2 |
30500 | #define CP_MES_DC_OP_CNTL__INVALIDATE_DCACHE_MASK 0x00000001L |
30501 | #define CP_MES_DC_OP_CNTL__INVALIDATE_DCACHE_COMPLETE_MASK 0x00000002L |
30502 | #define CP_MES_DC_OP_CNTL__BYPASS_ALL_MASK 0x00000004L |
30503 | //CP_MES_MTIMECMP_LO |
30504 | #define CP_MES_MTIMECMP_LO__TIME_LO__SHIFT 0x0 |
30505 | #define CP_MES_MTIMECMP_LO__TIME_LO_MASK 0xFFFFFFFFL |
30506 | //CP_MES_MTIMECMP_HI |
30507 | #define CP_MES_MTIMECMP_HI__TIME_HI__SHIFT 0x0 |
30508 | #define CP_MES_MTIMECMP_HI__TIME_HI_MASK 0xFFFFFFFFL |
30509 | //CP_MES_PROCESS_QUANTUM_PIPE0 |
30510 | #define CP_MES_PROCESS_QUANTUM_PIPE0__QUANTUM_DURATION__SHIFT 0x0 |
30511 | #define CP_MES_PROCESS_QUANTUM_PIPE0__TIMER_EXPIRED__SHIFT 0x1c |
30512 | #define CP_MES_PROCESS_QUANTUM_PIPE0__QUANTUM_SCALE__SHIFT 0x1d |
30513 | #define CP_MES_PROCESS_QUANTUM_PIPE0__QUANTUM_EN__SHIFT 0x1f |
30514 | #define CP_MES_PROCESS_QUANTUM_PIPE0__QUANTUM_DURATION_MASK 0x0FFFFFFFL |
30515 | #define CP_MES_PROCESS_QUANTUM_PIPE0__TIMER_EXPIRED_MASK 0x10000000L |
30516 | #define CP_MES_PROCESS_QUANTUM_PIPE0__QUANTUM_SCALE_MASK 0x60000000L |
30517 | #define CP_MES_PROCESS_QUANTUM_PIPE0__QUANTUM_EN_MASK 0x80000000L |
30518 | //CP_MES_PROCESS_QUANTUM_PIPE1 |
30519 | #define CP_MES_PROCESS_QUANTUM_PIPE1__QUANTUM_DURATION__SHIFT 0x0 |
30520 | #define CP_MES_PROCESS_QUANTUM_PIPE1__TIMER_EXPIRED__SHIFT 0x1c |
30521 | #define CP_MES_PROCESS_QUANTUM_PIPE1__QUANTUM_SCALE__SHIFT 0x1d |
30522 | #define CP_MES_PROCESS_QUANTUM_PIPE1__QUANTUM_EN__SHIFT 0x1f |
30523 | #define CP_MES_PROCESS_QUANTUM_PIPE1__QUANTUM_DURATION_MASK 0x0FFFFFFFL |
30524 | #define CP_MES_PROCESS_QUANTUM_PIPE1__TIMER_EXPIRED_MASK 0x10000000L |
30525 | #define CP_MES_PROCESS_QUANTUM_PIPE1__QUANTUM_SCALE_MASK 0x60000000L |
30526 | #define CP_MES_PROCESS_QUANTUM_PIPE1__QUANTUM_EN_MASK 0x80000000L |
30527 | //CP_MES_DOORBELL_CONTROL1 |
30528 | #define CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET__SHIFT 0x2 |
30529 | #define CP_MES_DOORBELL_CONTROL1__DOORBELL_EN__SHIFT 0x1e |
30530 | #define CP_MES_DOORBELL_CONTROL1__DOORBELL_HIT__SHIFT 0x1f |
30531 | #define CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET_MASK 0x0FFFFFFCL |
30532 | #define CP_MES_DOORBELL_CONTROL1__DOORBELL_EN_MASK 0x40000000L |
30533 | #define CP_MES_DOORBELL_CONTROL1__DOORBELL_HIT_MASK 0x80000000L |
30534 | //CP_MES_DOORBELL_CONTROL2 |
30535 | #define CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET__SHIFT 0x2 |
30536 | #define CP_MES_DOORBELL_CONTROL2__DOORBELL_EN__SHIFT 0x1e |
30537 | #define CP_MES_DOORBELL_CONTROL2__DOORBELL_HIT__SHIFT 0x1f |
30538 | #define CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET_MASK 0x0FFFFFFCL |
30539 | #define CP_MES_DOORBELL_CONTROL2__DOORBELL_EN_MASK 0x40000000L |
30540 | #define CP_MES_DOORBELL_CONTROL2__DOORBELL_HIT_MASK 0x80000000L |
30541 | //CP_MES_DOORBELL_CONTROL3 |
30542 | #define CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET__SHIFT 0x2 |
30543 | #define CP_MES_DOORBELL_CONTROL3__DOORBELL_EN__SHIFT 0x1e |
30544 | #define CP_MES_DOORBELL_CONTROL3__DOORBELL_HIT__SHIFT 0x1f |
30545 | #define CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET_MASK 0x0FFFFFFCL |
30546 | #define CP_MES_DOORBELL_CONTROL3__DOORBELL_EN_MASK 0x40000000L |
30547 | #define CP_MES_DOORBELL_CONTROL3__DOORBELL_HIT_MASK 0x80000000L |
30548 | //CP_MES_DOORBELL_CONTROL4 |
30549 | #define CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET__SHIFT 0x2 |
30550 | #define CP_MES_DOORBELL_CONTROL4__DOORBELL_EN__SHIFT 0x1e |
30551 | #define CP_MES_DOORBELL_CONTROL4__DOORBELL_HIT__SHIFT 0x1f |
30552 | #define CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET_MASK 0x0FFFFFFCL |
30553 | #define CP_MES_DOORBELL_CONTROL4__DOORBELL_EN_MASK 0x40000000L |
30554 | #define CP_MES_DOORBELL_CONTROL4__DOORBELL_HIT_MASK 0x80000000L |
30555 | //CP_MES_DOORBELL_CONTROL5 |
30556 | #define CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET__SHIFT 0x2 |
30557 | #define CP_MES_DOORBELL_CONTROL5__DOORBELL_EN__SHIFT 0x1e |
30558 | #define CP_MES_DOORBELL_CONTROL5__DOORBELL_HIT__SHIFT 0x1f |
30559 | #define CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET_MASK 0x0FFFFFFCL |
30560 | #define CP_MES_DOORBELL_CONTROL5__DOORBELL_EN_MASK 0x40000000L |
30561 | #define CP_MES_DOORBELL_CONTROL5__DOORBELL_HIT_MASK 0x80000000L |
30562 | //CP_MES_DOORBELL_CONTROL6 |
30563 | #define CP_MES_DOORBELL_CONTROL6__DOORBELL_OFFSET__SHIFT 0x2 |
30564 | #define CP_MES_DOORBELL_CONTROL6__DOORBELL_EN__SHIFT 0x1e |
30565 | #define CP_MES_DOORBELL_CONTROL6__DOORBELL_HIT__SHIFT 0x1f |
30566 | #define CP_MES_DOORBELL_CONTROL6__DOORBELL_OFFSET_MASK 0x0FFFFFFCL |
30567 | #define CP_MES_DOORBELL_CONTROL6__DOORBELL_EN_MASK 0x40000000L |
30568 | #define CP_MES_DOORBELL_CONTROL6__DOORBELL_HIT_MASK 0x80000000L |
30569 | //CP_MES_GP0_LO |
30570 | #define CP_MES_GP0_LO__PG_VIRT_HALTED__SHIFT 0x0 |
30571 | #define CP_MES_GP0_LO__DATA__SHIFT 0x1 |
30572 | #define CP_MES_GP0_LO__PG_VIRT_HALTED_MASK 0x00000001L |
30573 | #define CP_MES_GP0_LO__DATA_MASK 0xFFFFFFFEL |
30574 | //CP_MES_GP0_HI |
30575 | #define CP_MES_GP0_HI__M_RET_ADDR__SHIFT 0x0 |
30576 | #define CP_MES_GP0_HI__M_RET_ADDR_MASK 0xFFFFFFFFL |
30577 | //CP_MES_GP1_LO |
30578 | #define CP_MES_GP1_LO__RD_WR_SELECT_LO__SHIFT 0x0 |
30579 | #define CP_MES_GP1_LO__RD_WR_SELECT_LO_MASK 0xFFFFFFFFL |
30580 | //CP_MES_GP1_HI |
30581 | #define CP_MES_GP1_HI__RD_WR_SELECT_HI__SHIFT 0x0 |
30582 | #define CP_MES_GP1_HI__RD_WR_SELECT_HI_MASK 0xFFFFFFFFL |
30583 | //CP_MES_GP2_LO |
30584 | #define CP_MES_GP2_LO__STACK_PNTR_LO__SHIFT 0x0 |
30585 | #define CP_MES_GP2_LO__STACK_PNTR_LO_MASK 0xFFFFFFFFL |
30586 | //CP_MES_GP2_HI |
30587 | #define CP_MES_GP2_HI__STACK_PNTR_HI__SHIFT 0x0 |
30588 | #define CP_MES_GP2_HI__STACK_PNTR_HI_MASK 0xFFFFFFFFL |
30589 | //CP_MES_GP3_LO |
30590 | #define CP_MES_GP3_LO__DATA__SHIFT 0x0 |
30591 | #define CP_MES_GP3_LO__DATA_MASK 0xFFFFFFFFL |
30592 | //CP_MES_GP3_HI |
30593 | #define CP_MES_GP3_HI__DATA__SHIFT 0x0 |
30594 | #define CP_MES_GP3_HI__DATA_MASK 0xFFFFFFFFL |
30595 | //CP_MES_GP4_LO |
30596 | #define CP_MES_GP4_LO__DATA__SHIFT 0x0 |
30597 | #define CP_MES_GP4_LO__DATA_MASK 0xFFFFFFFFL |
30598 | //CP_MES_GP4_HI |
30599 | #define CP_MES_GP4_HI__DATA__SHIFT 0x0 |
30600 | #define CP_MES_GP4_HI__DATA_MASK 0xFFFFFFFFL |
30601 | //CP_MES_GP5_LO |
30602 | #define CP_MES_GP5_LO__PG_VIRT_HALTED__SHIFT 0x0 |
30603 | #define CP_MES_GP5_LO__DATA__SHIFT 0x1 |
30604 | #define CP_MES_GP5_LO__PG_VIRT_HALTED_MASK 0x00000001L |
30605 | #define CP_MES_GP5_LO__DATA_MASK 0xFFFFFFFEL |
30606 | //CP_MES_GP5_HI |
30607 | #define CP_MES_GP5_HI__M_RET_ADDR__SHIFT 0x0 |
30608 | #define CP_MES_GP5_HI__M_RET_ADDR_MASK 0xFFFFFFFFL |
30609 | //CP_MES_GP6_LO |
30610 | #define CP_MES_GP6_LO__RD_WR_SELECT_LO__SHIFT 0x0 |
30611 | #define CP_MES_GP6_LO__RD_WR_SELECT_LO_MASK 0xFFFFFFFFL |
30612 | //CP_MES_GP6_HI |
30613 | #define CP_MES_GP6_HI__RD_WR_SELECT_HI__SHIFT 0x0 |
30614 | #define CP_MES_GP6_HI__RD_WR_SELECT_HI_MASK 0xFFFFFFFFL |
30615 | //CP_MES_GP7_LO |
30616 | #define CP_MES_GP7_LO__STACK_PNTR_LO__SHIFT 0x0 |
30617 | #define CP_MES_GP7_LO__STACK_PNTR_LO_MASK 0xFFFFFFFFL |
30618 | //CP_MES_GP7_HI |
30619 | #define CP_MES_GP7_HI__STACK_PNTR_HI__SHIFT 0x0 |
30620 | #define CP_MES_GP7_HI__STACK_PNTR_HI_MASK 0xFFFFFFFFL |
30621 | //CP_MES_GP8_LO |
30622 | #define CP_MES_GP8_LO__DATA__SHIFT 0x0 |
30623 | #define CP_MES_GP8_LO__DATA_MASK 0xFFFFFFFFL |
30624 | //CP_MES_GP8_HI |
30625 | #define CP_MES_GP8_HI__DATA__SHIFT 0x0 |
30626 | #define CP_MES_GP8_HI__DATA_MASK 0xFFFFFFFFL |
30627 | //CP_MES_GP9_LO |
30628 | #define CP_MES_GP9_LO__DATA__SHIFT 0x0 |
30629 | #define CP_MES_GP9_LO__DATA_MASK 0xFFFFFFFFL |
30630 | //CP_MES_GP9_HI |
30631 | #define CP_MES_GP9_HI__DATA__SHIFT 0x0 |
30632 | #define CP_MES_GP9_HI__DATA_MASK 0xFFFFFFFFL |
30633 | //CP_MES_LOCAL_BASE0_LO |
30634 | #define CP_MES_LOCAL_BASE0_LO__BASE0_LO__SHIFT 0x10 |
30635 | #define CP_MES_LOCAL_BASE0_LO__BASE0_LO_MASK 0xFFFF0000L |
30636 | //CP_MES_LOCAL_BASE0_HI |
30637 | #define CP_MES_LOCAL_BASE0_HI__BASE0_HI__SHIFT 0x0 |
30638 | #define CP_MES_LOCAL_BASE0_HI__BASE0_HI_MASK 0x0000FFFFL |
30639 | //CP_MES_LOCAL_MASK0_LO |
30640 | #define CP_MES_LOCAL_MASK0_LO__MASK0_LO__SHIFT 0x10 |
30641 | #define CP_MES_LOCAL_MASK0_LO__MASK0_LO_MASK 0xFFFF0000L |
30642 | //CP_MES_LOCAL_MASK0_HI |
30643 | #define CP_MES_LOCAL_MASK0_HI__MASK0_HI__SHIFT 0x0 |
30644 | #define CP_MES_LOCAL_MASK0_HI__MASK0_HI_MASK 0x0000FFFFL |
30645 | //CP_MES_LOCAL_APERTURE |
30646 | #define CP_MES_LOCAL_APERTURE__APERTURE__SHIFT 0x0 |
30647 | #define CP_MES_LOCAL_APERTURE__APERTURE_MASK 0x00000007L |
30648 | //CP_MES_LOCAL_INSTR_BASE_LO |
30649 | #define CP_MES_LOCAL_INSTR_BASE_LO__BASE_LO__SHIFT 0x10 |
30650 | #define CP_MES_LOCAL_INSTR_BASE_LO__BASE_LO_MASK 0xFFFF0000L |
30651 | //CP_MES_LOCAL_INSTR_BASE_HI |
30652 | #define CP_MES_LOCAL_INSTR_BASE_HI__BASE_HI__SHIFT 0x0 |
30653 | #define CP_MES_LOCAL_INSTR_BASE_HI__BASE_HI_MASK 0x0000FFFFL |
30654 | //CP_MES_LOCAL_INSTR_MASK_LO |
30655 | #define CP_MES_LOCAL_INSTR_MASK_LO__MASK_LO__SHIFT 0x10 |
30656 | #define CP_MES_LOCAL_INSTR_MASK_LO__MASK_LO_MASK 0xFFFF0000L |
30657 | //CP_MES_LOCAL_INSTR_MASK_HI |
30658 | #define CP_MES_LOCAL_INSTR_MASK_HI__MASK_HI__SHIFT 0x0 |
30659 | #define CP_MES_LOCAL_INSTR_MASK_HI__MASK_HI_MASK 0x0000FFFFL |
30660 | //CP_MES_LOCAL_INSTR_APERTURE |
30661 | #define CP_MES_LOCAL_INSTR_APERTURE__APERTURE__SHIFT 0x0 |
30662 | #define CP_MES_LOCAL_INSTR_APERTURE__APERTURE_MASK 0x00000007L |
30663 | //CP_MES_LOCAL_SCRATCH_APERTURE |
30664 | #define CP_MES_LOCAL_SCRATCH_APERTURE__APERTURE__SHIFT 0x0 |
30665 | #define CP_MES_LOCAL_SCRATCH_APERTURE__APERTURE_MASK 0x00000007L |
30666 | //CP_MES_LOCAL_SCRATCH_BASE_LO |
30667 | #define CP_MES_LOCAL_SCRATCH_BASE_LO__BASE_LO__SHIFT 0x10 |
30668 | #define CP_MES_LOCAL_SCRATCH_BASE_LO__BASE_LO_MASK 0xFFFF0000L |
30669 | //CP_MES_LOCAL_SCRATCH_BASE_HI |
30670 | #define CP_MES_LOCAL_SCRATCH_BASE_HI__BASE_HI__SHIFT 0x0 |
30671 | #define CP_MES_LOCAL_SCRATCH_BASE_HI__BASE_HI_MASK 0x0000FFFFL |
30672 | //CP_MES_PERFCOUNT_CNTL |
30673 | #define CP_MES_PERFCOUNT_CNTL__EVENT_SEL__SHIFT 0x0 |
30674 | #define CP_MES_PERFCOUNT_CNTL__EVENT_SEL_MASK 0x0000001FL |
30675 | //CP_MES_PENDING_INTERRUPT |
30676 | #define CP_MES_PENDING_INTERRUPT__PENDING_INTERRUPT__SHIFT 0x0 |
30677 | #define CP_MES_PENDING_INTERRUPT__PENDING_INTERRUPT_MASK 0xFFFFFFFFL |
30678 | //CP_MES_PRGRM_CNTR_START_HI |
30679 | #define CP_MES_PRGRM_CNTR_START_HI__IP_START__SHIFT 0x0 |
30680 | #define CP_MES_PRGRM_CNTR_START_HI__IP_START_MASK 0x3FFFFFFFL |
30681 | //CP_MES_INTERRUPT_DATA_16 |
30682 | #define CP_MES_INTERRUPT_DATA_16__DATA__SHIFT 0x0 |
30683 | #define CP_MES_INTERRUPT_DATA_16__DATA_MASK 0xFFFFFFFFL |
30684 | //CP_MES_INTERRUPT_DATA_17 |
30685 | #define CP_MES_INTERRUPT_DATA_17__DATA__SHIFT 0x0 |
30686 | #define CP_MES_INTERRUPT_DATA_17__DATA_MASK 0xFFFFFFFFL |
30687 | //CP_MES_INTERRUPT_DATA_18 |
30688 | #define CP_MES_INTERRUPT_DATA_18__DATA__SHIFT 0x0 |
30689 | #define CP_MES_INTERRUPT_DATA_18__DATA_MASK 0xFFFFFFFFL |
30690 | //CP_MES_INTERRUPT_DATA_19 |
30691 | #define CP_MES_INTERRUPT_DATA_19__DATA__SHIFT 0x0 |
30692 | #define CP_MES_INTERRUPT_DATA_19__DATA_MASK 0xFFFFFFFFL |
30693 | //CP_MES_INTERRUPT_DATA_20 |
30694 | #define CP_MES_INTERRUPT_DATA_20__DATA__SHIFT 0x0 |
30695 | #define CP_MES_INTERRUPT_DATA_20__DATA_MASK 0xFFFFFFFFL |
30696 | //CP_MES_INTERRUPT_DATA_21 |
30697 | #define CP_MES_INTERRUPT_DATA_21__DATA__SHIFT 0x0 |
30698 | #define CP_MES_INTERRUPT_DATA_21__DATA_MASK 0xFFFFFFFFL |
30699 | //CP_MES_INTERRUPT_DATA_22 |
30700 | #define CP_MES_INTERRUPT_DATA_22__DATA__SHIFT 0x0 |
30701 | #define CP_MES_INTERRUPT_DATA_22__DATA_MASK 0xFFFFFFFFL |
30702 | //CP_MES_INTERRUPT_DATA_23 |
30703 | #define CP_MES_INTERRUPT_DATA_23__DATA__SHIFT 0x0 |
30704 | #define CP_MES_INTERRUPT_DATA_23__DATA_MASK 0xFFFFFFFFL |
30705 | //CP_MES_INTERRUPT_DATA_24 |
30706 | #define CP_MES_INTERRUPT_DATA_24__DATA__SHIFT 0x0 |
30707 | #define CP_MES_INTERRUPT_DATA_24__DATA_MASK 0xFFFFFFFFL |
30708 | //CP_MES_INTERRUPT_DATA_25 |
30709 | #define CP_MES_INTERRUPT_DATA_25__DATA__SHIFT 0x0 |
30710 | #define CP_MES_INTERRUPT_DATA_25__DATA_MASK 0xFFFFFFFFL |
30711 | //CP_MES_INTERRUPT_DATA_26 |
30712 | #define CP_MES_INTERRUPT_DATA_26__DATA__SHIFT 0x0 |
30713 | #define CP_MES_INTERRUPT_DATA_26__DATA_MASK 0xFFFFFFFFL |
30714 | //CP_MES_INTERRUPT_DATA_27 |
30715 | #define CP_MES_INTERRUPT_DATA_27__DATA__SHIFT 0x0 |
30716 | #define CP_MES_INTERRUPT_DATA_27__DATA_MASK 0xFFFFFFFFL |
30717 | //CP_MES_INTERRUPT_DATA_28 |
30718 | #define CP_MES_INTERRUPT_DATA_28__DATA__SHIFT 0x0 |
30719 | #define CP_MES_INTERRUPT_DATA_28__DATA_MASK 0xFFFFFFFFL |
30720 | //CP_MES_INTERRUPT_DATA_29 |
30721 | #define CP_MES_INTERRUPT_DATA_29__DATA__SHIFT 0x0 |
30722 | #define CP_MES_INTERRUPT_DATA_29__DATA_MASK 0xFFFFFFFFL |
30723 | //CP_MES_INTERRUPT_DATA_30 |
30724 | #define CP_MES_INTERRUPT_DATA_30__DATA__SHIFT 0x0 |
30725 | #define CP_MES_INTERRUPT_DATA_30__DATA_MASK 0xFFFFFFFFL |
30726 | //CP_MES_INTERRUPT_DATA_31 |
30727 | #define CP_MES_INTERRUPT_DATA_31__DATA__SHIFT 0x0 |
30728 | #define CP_MES_INTERRUPT_DATA_31__DATA_MASK 0xFFFFFFFFL |
30729 | //CP_MES_DC_APERTURE0_BASE |
30730 | #define CP_MES_DC_APERTURE0_BASE__BASE__SHIFT 0x0 |
30731 | #define CP_MES_DC_APERTURE0_BASE__BASE_MASK 0xFFFFFFFFL |
30732 | //CP_MES_DC_APERTURE0_MASK |
30733 | #define CP_MES_DC_APERTURE0_MASK__MASK__SHIFT 0x0 |
30734 | #define CP_MES_DC_APERTURE0_MASK__MASK_MASK 0xFFFFFFFFL |
30735 | //CP_MES_DC_APERTURE0_CNTL |
30736 | #define CP_MES_DC_APERTURE0_CNTL__VMID__SHIFT 0x0 |
30737 | #define CP_MES_DC_APERTURE0_CNTL__BYPASS_MODE__SHIFT 0x4 |
30738 | #define CP_MES_DC_APERTURE0_CNTL__VMID_MASK 0x0000000FL |
30739 | #define CP_MES_DC_APERTURE0_CNTL__BYPASS_MODE_MASK 0x00000010L |
30740 | //CP_MES_DC_APERTURE1_BASE |
30741 | #define CP_MES_DC_APERTURE1_BASE__BASE__SHIFT 0x0 |
30742 | #define CP_MES_DC_APERTURE1_BASE__BASE_MASK 0xFFFFFFFFL |
30743 | //CP_MES_DC_APERTURE1_MASK |
30744 | #define CP_MES_DC_APERTURE1_MASK__MASK__SHIFT 0x0 |
30745 | #define CP_MES_DC_APERTURE1_MASK__MASK_MASK 0xFFFFFFFFL |
30746 | //CP_MES_DC_APERTURE1_CNTL |
30747 | #define CP_MES_DC_APERTURE1_CNTL__VMID__SHIFT 0x0 |
30748 | #define CP_MES_DC_APERTURE1_CNTL__BYPASS_MODE__SHIFT 0x4 |
30749 | #define CP_MES_DC_APERTURE1_CNTL__VMID_MASK 0x0000000FL |
30750 | #define CP_MES_DC_APERTURE1_CNTL__BYPASS_MODE_MASK 0x00000010L |
30751 | //CP_MES_DC_APERTURE2_BASE |
30752 | #define CP_MES_DC_APERTURE2_BASE__BASE__SHIFT 0x0 |
30753 | #define CP_MES_DC_APERTURE2_BASE__BASE_MASK 0xFFFFFFFFL |
30754 | //CP_MES_DC_APERTURE2_MASK |
30755 | #define CP_MES_DC_APERTURE2_MASK__MASK__SHIFT 0x0 |
30756 | #define CP_MES_DC_APERTURE2_MASK__MASK_MASK 0xFFFFFFFFL |
30757 | //CP_MES_DC_APERTURE2_CNTL |
30758 | #define CP_MES_DC_APERTURE2_CNTL__VMID__SHIFT 0x0 |
30759 | #define CP_MES_DC_APERTURE2_CNTL__BYPASS_MODE__SHIFT 0x4 |
30760 | #define CP_MES_DC_APERTURE2_CNTL__VMID_MASK 0x0000000FL |
30761 | #define CP_MES_DC_APERTURE2_CNTL__BYPASS_MODE_MASK 0x00000010L |
30762 | //CP_MES_DC_APERTURE3_BASE |
30763 | #define CP_MES_DC_APERTURE3_BASE__BASE__SHIFT 0x0 |
30764 | #define CP_MES_DC_APERTURE3_BASE__BASE_MASK 0xFFFFFFFFL |
30765 | //CP_MES_DC_APERTURE3_MASK |
30766 | #define CP_MES_DC_APERTURE3_MASK__MASK__SHIFT 0x0 |
30767 | #define CP_MES_DC_APERTURE3_MASK__MASK_MASK 0xFFFFFFFFL |
30768 | //CP_MES_DC_APERTURE3_CNTL |
30769 | #define CP_MES_DC_APERTURE3_CNTL__VMID__SHIFT 0x0 |
30770 | #define CP_MES_DC_APERTURE3_CNTL__BYPASS_MODE__SHIFT 0x4 |
30771 | #define CP_MES_DC_APERTURE3_CNTL__VMID_MASK 0x0000000FL |
30772 | #define CP_MES_DC_APERTURE3_CNTL__BYPASS_MODE_MASK 0x00000010L |
30773 | //CP_MES_DC_APERTURE4_BASE |
30774 | #define CP_MES_DC_APERTURE4_BASE__BASE__SHIFT 0x0 |
30775 | #define CP_MES_DC_APERTURE4_BASE__BASE_MASK 0xFFFFFFFFL |
30776 | //CP_MES_DC_APERTURE4_MASK |
30777 | #define CP_MES_DC_APERTURE4_MASK__MASK__SHIFT 0x0 |
30778 | #define CP_MES_DC_APERTURE4_MASK__MASK_MASK 0xFFFFFFFFL |
30779 | //CP_MES_DC_APERTURE4_CNTL |
30780 | #define CP_MES_DC_APERTURE4_CNTL__VMID__SHIFT 0x0 |
30781 | #define CP_MES_DC_APERTURE4_CNTL__BYPASS_MODE__SHIFT 0x4 |
30782 | #define CP_MES_DC_APERTURE4_CNTL__VMID_MASK 0x0000000FL |
30783 | #define CP_MES_DC_APERTURE4_CNTL__BYPASS_MODE_MASK 0x00000010L |
30784 | //CP_MES_DC_APERTURE5_BASE |
30785 | #define CP_MES_DC_APERTURE5_BASE__BASE__SHIFT 0x0 |
30786 | #define CP_MES_DC_APERTURE5_BASE__BASE_MASK 0xFFFFFFFFL |
30787 | //CP_MES_DC_APERTURE5_MASK |
30788 | #define CP_MES_DC_APERTURE5_MASK__MASK__SHIFT 0x0 |
30789 | #define CP_MES_DC_APERTURE5_MASK__MASK_MASK 0xFFFFFFFFL |
30790 | //CP_MES_DC_APERTURE5_CNTL |
30791 | #define CP_MES_DC_APERTURE5_CNTL__VMID__SHIFT 0x0 |
30792 | #define CP_MES_DC_APERTURE5_CNTL__BYPASS_MODE__SHIFT 0x4 |
30793 | #define CP_MES_DC_APERTURE5_CNTL__VMID_MASK 0x0000000FL |
30794 | #define CP_MES_DC_APERTURE5_CNTL__BYPASS_MODE_MASK 0x00000010L |
30795 | //CP_MES_DC_APERTURE6_BASE |
30796 | #define CP_MES_DC_APERTURE6_BASE__BASE__SHIFT 0x0 |
30797 | #define CP_MES_DC_APERTURE6_BASE__BASE_MASK 0xFFFFFFFFL |
30798 | //CP_MES_DC_APERTURE6_MASK |
30799 | #define CP_MES_DC_APERTURE6_MASK__MASK__SHIFT 0x0 |
30800 | #define CP_MES_DC_APERTURE6_MASK__MASK_MASK 0xFFFFFFFFL |
30801 | //CP_MES_DC_APERTURE6_CNTL |
30802 | #define CP_MES_DC_APERTURE6_CNTL__VMID__SHIFT 0x0 |
30803 | #define CP_MES_DC_APERTURE6_CNTL__BYPASS_MODE__SHIFT 0x4 |
30804 | #define CP_MES_DC_APERTURE6_CNTL__VMID_MASK 0x0000000FL |
30805 | #define CP_MES_DC_APERTURE6_CNTL__BYPASS_MODE_MASK 0x00000010L |
30806 | //CP_MES_DC_APERTURE7_BASE |
30807 | #define CP_MES_DC_APERTURE7_BASE__BASE__SHIFT 0x0 |
30808 | #define CP_MES_DC_APERTURE7_BASE__BASE_MASK 0xFFFFFFFFL |
30809 | //CP_MES_DC_APERTURE7_MASK |
30810 | #define CP_MES_DC_APERTURE7_MASK__MASK__SHIFT 0x0 |
30811 | #define CP_MES_DC_APERTURE7_MASK__MASK_MASK 0xFFFFFFFFL |
30812 | //CP_MES_DC_APERTURE7_CNTL |
30813 | #define CP_MES_DC_APERTURE7_CNTL__VMID__SHIFT 0x0 |
30814 | #define CP_MES_DC_APERTURE7_CNTL__BYPASS_MODE__SHIFT 0x4 |
30815 | #define CP_MES_DC_APERTURE7_CNTL__VMID_MASK 0x0000000FL |
30816 | #define CP_MES_DC_APERTURE7_CNTL__BYPASS_MODE_MASK 0x00000010L |
30817 | //CP_MES_DC_APERTURE8_BASE |
30818 | #define CP_MES_DC_APERTURE8_BASE__BASE__SHIFT 0x0 |
30819 | #define CP_MES_DC_APERTURE8_BASE__BASE_MASK 0xFFFFFFFFL |
30820 | //CP_MES_DC_APERTURE8_MASK |
30821 | #define CP_MES_DC_APERTURE8_MASK__MASK__SHIFT 0x0 |
30822 | #define CP_MES_DC_APERTURE8_MASK__MASK_MASK 0xFFFFFFFFL |
30823 | //CP_MES_DC_APERTURE8_CNTL |
30824 | #define CP_MES_DC_APERTURE8_CNTL__VMID__SHIFT 0x0 |
30825 | #define CP_MES_DC_APERTURE8_CNTL__BYPASS_MODE__SHIFT 0x4 |
30826 | #define CP_MES_DC_APERTURE8_CNTL__VMID_MASK 0x0000000FL |
30827 | #define CP_MES_DC_APERTURE8_CNTL__BYPASS_MODE_MASK 0x00000010L |
30828 | //CP_MES_DC_APERTURE9_BASE |
30829 | #define CP_MES_DC_APERTURE9_BASE__BASE__SHIFT 0x0 |
30830 | #define CP_MES_DC_APERTURE9_BASE__BASE_MASK 0xFFFFFFFFL |
30831 | //CP_MES_DC_APERTURE9_MASK |
30832 | #define CP_MES_DC_APERTURE9_MASK__MASK__SHIFT 0x0 |
30833 | #define CP_MES_DC_APERTURE9_MASK__MASK_MASK 0xFFFFFFFFL |
30834 | //CP_MES_DC_APERTURE9_CNTL |
30835 | #define CP_MES_DC_APERTURE9_CNTL__VMID__SHIFT 0x0 |
30836 | #define CP_MES_DC_APERTURE9_CNTL__BYPASS_MODE__SHIFT 0x4 |
30837 | #define CP_MES_DC_APERTURE9_CNTL__VMID_MASK 0x0000000FL |
30838 | #define CP_MES_DC_APERTURE9_CNTL__BYPASS_MODE_MASK 0x00000010L |
30839 | //CP_MES_DC_APERTURE10_BASE |
30840 | #define CP_MES_DC_APERTURE10_BASE__BASE__SHIFT 0x0 |
30841 | #define CP_MES_DC_APERTURE10_BASE__BASE_MASK 0xFFFFFFFFL |
30842 | //CP_MES_DC_APERTURE10_MASK |
30843 | #define CP_MES_DC_APERTURE10_MASK__MASK__SHIFT 0x0 |
30844 | #define CP_MES_DC_APERTURE10_MASK__MASK_MASK 0xFFFFFFFFL |
30845 | //CP_MES_DC_APERTURE10_CNTL |
30846 | #define CP_MES_DC_APERTURE10_CNTL__VMID__SHIFT 0x0 |
30847 | #define CP_MES_DC_APERTURE10_CNTL__BYPASS_MODE__SHIFT 0x4 |
30848 | #define CP_MES_DC_APERTURE10_CNTL__VMID_MASK 0x0000000FL |
30849 | #define CP_MES_DC_APERTURE10_CNTL__BYPASS_MODE_MASK 0x00000010L |
30850 | //CP_MES_DC_APERTURE11_BASE |
30851 | #define CP_MES_DC_APERTURE11_BASE__BASE__SHIFT 0x0 |
30852 | #define CP_MES_DC_APERTURE11_BASE__BASE_MASK 0xFFFFFFFFL |
30853 | //CP_MES_DC_APERTURE11_MASK |
30854 | #define CP_MES_DC_APERTURE11_MASK__MASK__SHIFT 0x0 |
30855 | #define CP_MES_DC_APERTURE11_MASK__MASK_MASK 0xFFFFFFFFL |
30856 | //CP_MES_DC_APERTURE11_CNTL |
30857 | #define CP_MES_DC_APERTURE11_CNTL__VMID__SHIFT 0x0 |
30858 | #define CP_MES_DC_APERTURE11_CNTL__BYPASS_MODE__SHIFT 0x4 |
30859 | #define CP_MES_DC_APERTURE11_CNTL__VMID_MASK 0x0000000FL |
30860 | #define CP_MES_DC_APERTURE11_CNTL__BYPASS_MODE_MASK 0x00000010L |
30861 | //CP_MES_DC_APERTURE12_BASE |
30862 | #define CP_MES_DC_APERTURE12_BASE__BASE__SHIFT 0x0 |
30863 | #define CP_MES_DC_APERTURE12_BASE__BASE_MASK 0xFFFFFFFFL |
30864 | //CP_MES_DC_APERTURE12_MASK |
30865 | #define CP_MES_DC_APERTURE12_MASK__MASK__SHIFT 0x0 |
30866 | #define CP_MES_DC_APERTURE12_MASK__MASK_MASK 0xFFFFFFFFL |
30867 | //CP_MES_DC_APERTURE12_CNTL |
30868 | #define CP_MES_DC_APERTURE12_CNTL__VMID__SHIFT 0x0 |
30869 | #define CP_MES_DC_APERTURE12_CNTL__BYPASS_MODE__SHIFT 0x4 |
30870 | #define CP_MES_DC_APERTURE12_CNTL__VMID_MASK 0x0000000FL |
30871 | #define CP_MES_DC_APERTURE12_CNTL__BYPASS_MODE_MASK 0x00000010L |
30872 | //CP_MES_DC_APERTURE13_BASE |
30873 | #define CP_MES_DC_APERTURE13_BASE__BASE__SHIFT 0x0 |
30874 | #define CP_MES_DC_APERTURE13_BASE__BASE_MASK 0xFFFFFFFFL |
30875 | //CP_MES_DC_APERTURE13_MASK |
30876 | #define CP_MES_DC_APERTURE13_MASK__MASK__SHIFT 0x0 |
30877 | #define CP_MES_DC_APERTURE13_MASK__MASK_MASK 0xFFFFFFFFL |
30878 | //CP_MES_DC_APERTURE13_CNTL |
30879 | #define CP_MES_DC_APERTURE13_CNTL__VMID__SHIFT 0x0 |
30880 | #define CP_MES_DC_APERTURE13_CNTL__BYPASS_MODE__SHIFT 0x4 |
30881 | #define CP_MES_DC_APERTURE13_CNTL__VMID_MASK 0x0000000FL |
30882 | #define CP_MES_DC_APERTURE13_CNTL__BYPASS_MODE_MASK 0x00000010L |
30883 | //CP_MES_DC_APERTURE14_BASE |
30884 | #define CP_MES_DC_APERTURE14_BASE__BASE__SHIFT 0x0 |
30885 | #define CP_MES_DC_APERTURE14_BASE__BASE_MASK 0xFFFFFFFFL |
30886 | //CP_MES_DC_APERTURE14_MASK |
30887 | #define CP_MES_DC_APERTURE14_MASK__MASK__SHIFT 0x0 |
30888 | #define CP_MES_DC_APERTURE14_MASK__MASK_MASK 0xFFFFFFFFL |
30889 | //CP_MES_DC_APERTURE14_CNTL |
30890 | #define CP_MES_DC_APERTURE14_CNTL__VMID__SHIFT 0x0 |
30891 | #define CP_MES_DC_APERTURE14_CNTL__BYPASS_MODE__SHIFT 0x4 |
30892 | #define CP_MES_DC_APERTURE14_CNTL__VMID_MASK 0x0000000FL |
30893 | #define CP_MES_DC_APERTURE14_CNTL__BYPASS_MODE_MASK 0x00000010L |
30894 | //CP_MES_DC_APERTURE15_BASE |
30895 | #define CP_MES_DC_APERTURE15_BASE__BASE__SHIFT 0x0 |
30896 | #define CP_MES_DC_APERTURE15_BASE__BASE_MASK 0xFFFFFFFFL |
30897 | //CP_MES_DC_APERTURE15_MASK |
30898 | #define CP_MES_DC_APERTURE15_MASK__MASK__SHIFT 0x0 |
30899 | #define CP_MES_DC_APERTURE15_MASK__MASK_MASK 0xFFFFFFFFL |
30900 | //CP_MES_DC_APERTURE15_CNTL |
30901 | #define CP_MES_DC_APERTURE15_CNTL__VMID__SHIFT 0x0 |
30902 | #define CP_MES_DC_APERTURE15_CNTL__BYPASS_MODE__SHIFT 0x4 |
30903 | #define CP_MES_DC_APERTURE15_CNTL__VMID_MASK 0x0000000FL |
30904 | #define CP_MES_DC_APERTURE15_CNTL__BYPASS_MODE_MASK 0x00000010L |
30905 | //CP_MEC_RS64_PRGRM_CNTR_START |
30906 | #define CP_MEC_RS64_PRGRM_CNTR_START__IP_START__SHIFT 0x0 |
30907 | #define CP_MEC_RS64_PRGRM_CNTR_START__IP_START_MASK 0xFFFFFFFFL |
30908 | //CP_MEC_MTVEC_LO |
30909 | #define CP_MEC_MTVEC_LO__ADDR_LO__SHIFT 0x0 |
30910 | #define CP_MEC_MTVEC_LO__ADDR_LO_MASK 0xFFFFFFFFL |
30911 | //CP_MEC_MTVEC_HI |
30912 | #define CP_MEC_MTVEC_HI__ADDR_LO__SHIFT 0x0 |
30913 | #define CP_MEC_MTVEC_HI__ADDR_LO_MASK 0xFFFFFFFFL |
30914 | //CP_MEC_ISA_CNTL |
30915 | #define CP_MEC_ISA_CNTL__ISA_MODE__SHIFT 0x0 |
30916 | #define CP_MEC_ISA_CNTL__ISA_MODE_MASK 0x00000001L |
30917 | //CP_MEC_RS64_CNTL |
30918 | #define CP_MEC_RS64_CNTL__MEC_INVALIDATE_ICACHE__SHIFT 0x4 |
30919 | #define CP_MEC_RS64_CNTL__MEC_PIPE0_RESET__SHIFT 0x10 |
30920 | #define CP_MEC_RS64_CNTL__MEC_PIPE1_RESET__SHIFT 0x11 |
30921 | #define CP_MEC_RS64_CNTL__MEC_PIPE2_RESET__SHIFT 0x12 |
30922 | #define CP_MEC_RS64_CNTL__MEC_PIPE3_RESET__SHIFT 0x13 |
30923 | #define CP_MEC_RS64_CNTL__MEC_PIPE0_ACTIVE__SHIFT 0x1a |
30924 | #define CP_MEC_RS64_CNTL__MEC_PIPE1_ACTIVE__SHIFT 0x1b |
30925 | #define CP_MEC_RS64_CNTL__MEC_PIPE2_ACTIVE__SHIFT 0x1c |
30926 | #define CP_MEC_RS64_CNTL__MEC_PIPE3_ACTIVE__SHIFT 0x1d |
30927 | #define CP_MEC_RS64_CNTL__MEC_HALT__SHIFT 0x1e |
30928 | #define CP_MEC_RS64_CNTL__MEC_STEP__SHIFT 0x1f |
30929 | #define CP_MEC_RS64_CNTL__MEC_INVALIDATE_ICACHE_MASK 0x00000010L |
30930 | #define CP_MEC_RS64_CNTL__MEC_PIPE0_RESET_MASK 0x00010000L |
30931 | #define CP_MEC_RS64_CNTL__MEC_PIPE1_RESET_MASK 0x00020000L |
30932 | #define CP_MEC_RS64_CNTL__MEC_PIPE2_RESET_MASK 0x00040000L |
30933 | #define CP_MEC_RS64_CNTL__MEC_PIPE3_RESET_MASK 0x00080000L |
30934 | #define CP_MEC_RS64_CNTL__MEC_PIPE0_ACTIVE_MASK 0x04000000L |
30935 | #define CP_MEC_RS64_CNTL__MEC_PIPE1_ACTIVE_MASK 0x08000000L |
30936 | #define CP_MEC_RS64_CNTL__MEC_PIPE2_ACTIVE_MASK 0x10000000L |
30937 | #define CP_MEC_RS64_CNTL__MEC_PIPE3_ACTIVE_MASK 0x20000000L |
30938 | #define CP_MEC_RS64_CNTL__MEC_HALT_MASK 0x40000000L |
30939 | #define CP_MEC_RS64_CNTL__MEC_STEP_MASK 0x80000000L |
30940 | //CP_MEC_MIE_LO |
30941 | #define CP_MEC_MIE_LO__MEC_INT__SHIFT 0x0 |
30942 | #define CP_MEC_MIE_LO__MEC_INT_MASK 0xFFFFFFFFL |
30943 | //CP_MEC_MIE_HI |
30944 | #define CP_MEC_MIE_HI__MEC_INT__SHIFT 0x0 |
30945 | #define CP_MEC_MIE_HI__MEC_INT_MASK 0xFFFFFFFFL |
30946 | //CP_MEC_RS64_INTERRUPT |
30947 | #define CP_MEC_RS64_INTERRUPT__MEC_INT__SHIFT 0x0 |
30948 | #define CP_MEC_RS64_INTERRUPT__MEC_INT_MASK 0xFFFFFFFFL |
30949 | //CP_MEC_RS64_INSTR_PNTR |
30950 | #define CP_MEC_RS64_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0 |
30951 | #define CP_MEC_RS64_INSTR_PNTR__INSTR_PNTR_MASK 0x000FFFFFL |
30952 | //CP_MEC_MIP_LO |
30953 | #define CP_MEC_MIP_LO__MIP_LO__SHIFT 0x0 |
30954 | #define CP_MEC_MIP_LO__MIP_LO_MASK 0xFFFFFFFFL |
30955 | //CP_MEC_MIP_HI |
30956 | #define CP_MEC_MIP_HI__MIP_HI__SHIFT 0x0 |
30957 | #define CP_MEC_MIP_HI__MIP_HI_MASK 0xFFFFFFFFL |
30958 | //CP_MEC_DC_BASE_CNTL |
30959 | #define CP_MEC_DC_BASE_CNTL__VMID__SHIFT 0x0 |
30960 | #define CP_MEC_DC_BASE_CNTL__CACHE_POLICY__SHIFT 0x18 |
30961 | #define CP_MEC_DC_BASE_CNTL__VMID_MASK 0x0000000FL |
30962 | #define CP_MEC_DC_BASE_CNTL__CACHE_POLICY_MASK 0x03000000L |
30963 | //CP_MEC_DC_OP_CNTL |
30964 | #define CP_MEC_DC_OP_CNTL__INVALIDATE_DCACHE__SHIFT 0x0 |
30965 | #define CP_MEC_DC_OP_CNTL__INVALIDATE_DCACHE_COMPLETE__SHIFT 0x1 |
30966 | #define CP_MEC_DC_OP_CNTL__BYPASS_ALL__SHIFT 0x2 |
30967 | #define CP_MEC_DC_OP_CNTL__INVALIDATE_DCACHE_MASK 0x00000001L |
30968 | #define CP_MEC_DC_OP_CNTL__INVALIDATE_DCACHE_COMPLETE_MASK 0x00000002L |
30969 | #define CP_MEC_DC_OP_CNTL__BYPASS_ALL_MASK 0x00000004L |
30970 | //CP_MEC_MTIMECMP_LO |
30971 | #define CP_MEC_MTIMECMP_LO__TIME_LO__SHIFT 0x0 |
30972 | #define CP_MEC_MTIMECMP_LO__TIME_LO_MASK 0xFFFFFFFFL |
30973 | //CP_MEC_MTIMECMP_HI |
30974 | #define CP_MEC_MTIMECMP_HI__TIME_HI__SHIFT 0x0 |
30975 | #define CP_MEC_MTIMECMP_HI__TIME_HI_MASK 0xFFFFFFFFL |
30976 | //CP_MEC_GP0_LO |
30977 | #define CP_MEC_GP0_LO__PG_VIRT_HALTED__SHIFT 0x0 |
30978 | #define CP_MEC_GP0_LO__DATA__SHIFT 0x1 |
30979 | #define CP_MEC_GP0_LO__PG_VIRT_HALTED_MASK 0x00000001L |
30980 | #define CP_MEC_GP0_LO__DATA_MASK 0xFFFFFFFEL |
30981 | //CP_MEC_GP0_HI |
30982 | #define CP_MEC_GP0_HI__M_RET_ADDR__SHIFT 0x0 |
30983 | #define CP_MEC_GP0_HI__M_RET_ADDR_MASK 0xFFFFFFFFL |
30984 | //CP_MEC_GP1_LO |
30985 | #define CP_MEC_GP1_LO__RD_WR_SELECT_LO__SHIFT 0x0 |
30986 | #define CP_MEC_GP1_LO__RD_WR_SELECT_LO_MASK 0xFFFFFFFFL |
30987 | //CP_MEC_GP1_HI |
30988 | #define CP_MEC_GP1_HI__RD_WR_SELECT_HI__SHIFT 0x0 |
30989 | #define CP_MEC_GP1_HI__RD_WR_SELECT_HI_MASK 0xFFFFFFFFL |
30990 | //CP_MEC_GP2_LO |
30991 | #define CP_MEC_GP2_LO__STACK_PNTR_LO__SHIFT 0x0 |
30992 | #define CP_MEC_GP2_LO__STACK_PNTR_LO_MASK 0xFFFFFFFFL |
30993 | //CP_MEC_GP2_HI |
30994 | #define CP_MEC_GP2_HI__STACK_PNTR_HI__SHIFT 0x0 |
30995 | #define CP_MEC_GP2_HI__STACK_PNTR_HI_MASK 0xFFFFFFFFL |
30996 | //CP_MEC_GP3_LO |
30997 | #define CP_MEC_GP3_LO__DATA__SHIFT 0x0 |
30998 | #define CP_MEC_GP3_LO__DATA_MASK 0xFFFFFFFFL |
30999 | //CP_MEC_GP3_HI |
31000 | #define CP_MEC_GP3_HI__DATA__SHIFT 0x0 |
31001 | #define CP_MEC_GP3_HI__DATA_MASK 0xFFFFFFFFL |
31002 | //CP_MEC_GP4_LO |
31003 | #define CP_MEC_GP4_LO__DATA__SHIFT 0x0 |
31004 | #define CP_MEC_GP4_LO__DATA_MASK 0xFFFFFFFFL |
31005 | //CP_MEC_GP4_HI |
31006 | #define CP_MEC_GP4_HI__DATA__SHIFT 0x0 |
31007 | #define CP_MEC_GP4_HI__DATA_MASK 0xFFFFFFFFL |
31008 | //CP_MEC_GP5_LO |
31009 | #define CP_MEC_GP5_LO__PG_VIRT_HALTED__SHIFT 0x0 |
31010 | #define CP_MEC_GP5_LO__DATA__SHIFT 0x1 |
31011 | #define CP_MEC_GP5_LO__PG_VIRT_HALTED_MASK 0x00000001L |
31012 | #define CP_MEC_GP5_LO__DATA_MASK 0xFFFFFFFEL |
31013 | //CP_MEC_GP5_HI |
31014 | #define CP_MEC_GP5_HI__M_RET_ADDR__SHIFT 0x0 |
31015 | #define CP_MEC_GP5_HI__M_RET_ADDR_MASK 0xFFFFFFFFL |
31016 | //CP_MEC_GP6_LO |
31017 | #define CP_MEC_GP6_LO__RD_WR_SELECT_LO__SHIFT 0x0 |
31018 | #define CP_MEC_GP6_LO__RD_WR_SELECT_LO_MASK 0xFFFFFFFFL |
31019 | //CP_MEC_GP6_HI |
31020 | #define CP_MEC_GP6_HI__RD_WR_SELECT_HI__SHIFT 0x0 |
31021 | #define CP_MEC_GP6_HI__RD_WR_SELECT_HI_MASK 0xFFFFFFFFL |
31022 | //CP_MEC_GP7_LO |
31023 | #define CP_MEC_GP7_LO__STACK_PNTR_LO__SHIFT 0x0 |
31024 | #define CP_MEC_GP7_LO__STACK_PNTR_LO_MASK 0xFFFFFFFFL |
31025 | //CP_MEC_GP7_HI |
31026 | #define CP_MEC_GP7_HI__STACK_PNTR_HI__SHIFT 0x0 |
31027 | #define CP_MEC_GP7_HI__STACK_PNTR_HI_MASK 0xFFFFFFFFL |
31028 | //CP_MEC_GP8_LO |
31029 | #define CP_MEC_GP8_LO__DATA__SHIFT 0x0 |
31030 | #define CP_MEC_GP8_LO__DATA_MASK 0xFFFFFFFFL |
31031 | //CP_MEC_GP8_HI |
31032 | #define CP_MEC_GP8_HI__DATA__SHIFT 0x0 |
31033 | #define CP_MEC_GP8_HI__DATA_MASK 0xFFFFFFFFL |
31034 | //CP_MEC_GP9_LO |
31035 | #define CP_MEC_GP9_LO__DATA__SHIFT 0x0 |
31036 | #define CP_MEC_GP9_LO__DATA_MASK 0xFFFFFFFFL |
31037 | //CP_MEC_GP9_HI |
31038 | #define CP_MEC_GP9_HI__DATA__SHIFT 0x0 |
31039 | #define CP_MEC_GP9_HI__DATA_MASK 0xFFFFFFFFL |
31040 | //CP_MEC_LOCAL_BASE0_LO |
31041 | #define CP_MEC_LOCAL_BASE0_LO__BASE0_LO__SHIFT 0x10 |
31042 | #define CP_MEC_LOCAL_BASE0_LO__BASE0_LO_MASK 0xFFFF0000L |
31043 | //CP_MEC_LOCAL_BASE0_HI |
31044 | #define CP_MEC_LOCAL_BASE0_HI__BASE0_HI__SHIFT 0x0 |
31045 | #define CP_MEC_LOCAL_BASE0_HI__BASE0_HI_MASK 0x0000FFFFL |
31046 | //CP_MEC_LOCAL_MASK0_LO |
31047 | #define CP_MEC_LOCAL_MASK0_LO__MASK0_LO__SHIFT 0x10 |
31048 | #define CP_MEC_LOCAL_MASK0_LO__MASK0_LO_MASK 0xFFFF0000L |
31049 | //CP_MEC_LOCAL_MASK0_HI |
31050 | #define CP_MEC_LOCAL_MASK0_HI__MASK0_HI__SHIFT 0x0 |
31051 | #define CP_MEC_LOCAL_MASK0_HI__MASK0_HI_MASK 0x0000FFFFL |
31052 | //CP_MEC_LOCAL_APERTURE |
31053 | #define CP_MEC_LOCAL_APERTURE__APERTURE__SHIFT 0x0 |
31054 | #define CP_MEC_LOCAL_APERTURE__APERTURE_MASK 0x00000007L |
31055 | //CP_MEC_LOCAL_INSTR_BASE_LO |
31056 | #define CP_MEC_LOCAL_INSTR_BASE_LO__BASE_LO__SHIFT 0x10 |
31057 | #define CP_MEC_LOCAL_INSTR_BASE_LO__BASE_LO_MASK 0xFFFF0000L |
31058 | //CP_MEC_LOCAL_INSTR_BASE_HI |
31059 | #define CP_MEC_LOCAL_INSTR_BASE_HI__BASE_HI__SHIFT 0x0 |
31060 | #define CP_MEC_LOCAL_INSTR_BASE_HI__BASE_HI_MASK 0x0000FFFFL |
31061 | //CP_MEC_LOCAL_INSTR_MASK_LO |
31062 | #define CP_MEC_LOCAL_INSTR_MASK_LO__MASK_LO__SHIFT 0x10 |
31063 | #define CP_MEC_LOCAL_INSTR_MASK_LO__MASK_LO_MASK 0xFFFF0000L |
31064 | //CP_MEC_LOCAL_INSTR_MASK_HI |
31065 | #define CP_MEC_LOCAL_INSTR_MASK_HI__MASK_HI__SHIFT 0x0 |
31066 | #define CP_MEC_LOCAL_INSTR_MASK_HI__MASK_HI_MASK 0x0000FFFFL |
31067 | //CP_MEC_LOCAL_INSTR_APERTURE |
31068 | #define CP_MEC_LOCAL_INSTR_APERTURE__APERTURE__SHIFT 0x0 |
31069 | #define CP_MEC_LOCAL_INSTR_APERTURE__APERTURE_MASK 0x00000007L |
31070 | //CP_MEC_LOCAL_SCRATCH_APERTURE |
31071 | #define CP_MEC_LOCAL_SCRATCH_APERTURE__APERTURE__SHIFT 0x0 |
31072 | #define CP_MEC_LOCAL_SCRATCH_APERTURE__APERTURE_MASK 0x00000007L |
31073 | //CP_MEC_LOCAL_SCRATCH_BASE_LO |
31074 | #define CP_MEC_LOCAL_SCRATCH_BASE_LO__BASE_LO__SHIFT 0x10 |
31075 | #define CP_MEC_LOCAL_SCRATCH_BASE_LO__BASE_LO_MASK 0xFFFF0000L |
31076 | //CP_MEC_LOCAL_SCRATCH_BASE_HI |
31077 | #define CP_MEC_LOCAL_SCRATCH_BASE_HI__BASE_HI__SHIFT 0x0 |
31078 | #define CP_MEC_LOCAL_SCRATCH_BASE_HI__BASE_HI_MASK 0x0000FFFFL |
31079 | //CP_MEC_RS64_PERFCOUNT_CNTL |
31080 | #define CP_MEC_RS64_PERFCOUNT_CNTL__EVENT_SEL__SHIFT 0x0 |
31081 | #define CP_MEC_RS64_PERFCOUNT_CNTL__EVENT_SEL_MASK 0x0000001FL |
31082 | //CP_MEC_RS64_PENDING_INTERRUPT |
31083 | #define CP_MEC_RS64_PENDING_INTERRUPT__PENDING_INTERRUPT__SHIFT 0x0 |
31084 | #define CP_MEC_RS64_PENDING_INTERRUPT__PENDING_INTERRUPT_MASK 0xFFFFFFFFL |
31085 | //CP_MEC_RS64_PRGRM_CNTR_START_HI |
31086 | #define CP_MEC_RS64_PRGRM_CNTR_START_HI__IP_START__SHIFT 0x0 |
31087 | #define CP_MEC_RS64_PRGRM_CNTR_START_HI__IP_START_MASK 0x3FFFFFFFL |
31088 | //CP_MEC_RS64_INTERRUPT_DATA_16 |
31089 | #define CP_MEC_RS64_INTERRUPT_DATA_16__DATA__SHIFT 0x0 |
31090 | #define CP_MEC_RS64_INTERRUPT_DATA_16__DATA_MASK 0xFFFFFFFFL |
31091 | //CP_MEC_RS64_INTERRUPT_DATA_17 |
31092 | #define CP_MEC_RS64_INTERRUPT_DATA_17__DATA__SHIFT 0x0 |
31093 | #define CP_MEC_RS64_INTERRUPT_DATA_17__DATA_MASK 0xFFFFFFFFL |
31094 | //CP_MEC_RS64_INTERRUPT_DATA_18 |
31095 | #define CP_MEC_RS64_INTERRUPT_DATA_18__DATA__SHIFT 0x0 |
31096 | #define CP_MEC_RS64_INTERRUPT_DATA_18__DATA_MASK 0xFFFFFFFFL |
31097 | //CP_MEC_RS64_INTERRUPT_DATA_19 |
31098 | #define CP_MEC_RS64_INTERRUPT_DATA_19__DATA__SHIFT 0x0 |
31099 | #define CP_MEC_RS64_INTERRUPT_DATA_19__DATA_MASK 0xFFFFFFFFL |
31100 | //CP_MEC_RS64_INTERRUPT_DATA_20 |
31101 | #define CP_MEC_RS64_INTERRUPT_DATA_20__DATA__SHIFT 0x0 |
31102 | #define CP_MEC_RS64_INTERRUPT_DATA_20__DATA_MASK 0xFFFFFFFFL |
31103 | //CP_MEC_RS64_INTERRUPT_DATA_21 |
31104 | #define CP_MEC_RS64_INTERRUPT_DATA_21__DATA__SHIFT 0x0 |
31105 | #define CP_MEC_RS64_INTERRUPT_DATA_21__DATA_MASK 0xFFFFFFFFL |
31106 | //CP_MEC_RS64_INTERRUPT_DATA_22 |
31107 | #define CP_MEC_RS64_INTERRUPT_DATA_22__DATA__SHIFT 0x0 |
31108 | #define CP_MEC_RS64_INTERRUPT_DATA_22__DATA_MASK 0xFFFFFFFFL |
31109 | //CP_MEC_RS64_INTERRUPT_DATA_23 |
31110 | #define CP_MEC_RS64_INTERRUPT_DATA_23__DATA__SHIFT 0x0 |
31111 | #define CP_MEC_RS64_INTERRUPT_DATA_23__DATA_MASK 0xFFFFFFFFL |
31112 | //CP_MEC_RS64_INTERRUPT_DATA_24 |
31113 | #define CP_MEC_RS64_INTERRUPT_DATA_24__DATA__SHIFT 0x0 |
31114 | #define CP_MEC_RS64_INTERRUPT_DATA_24__DATA_MASK 0xFFFFFFFFL |
31115 | //CP_MEC_RS64_INTERRUPT_DATA_25 |
31116 | #define CP_MEC_RS64_INTERRUPT_DATA_25__DATA__SHIFT 0x0 |
31117 | #define CP_MEC_RS64_INTERRUPT_DATA_25__DATA_MASK 0xFFFFFFFFL |
31118 | //CP_MEC_RS64_INTERRUPT_DATA_26 |
31119 | #define CP_MEC_RS64_INTERRUPT_DATA_26__DATA__SHIFT 0x0 |
31120 | #define CP_MEC_RS64_INTERRUPT_DATA_26__DATA_MASK 0xFFFFFFFFL |
31121 | //CP_MEC_RS64_INTERRUPT_DATA_27 |
31122 | #define CP_MEC_RS64_INTERRUPT_DATA_27__DATA__SHIFT 0x0 |
31123 | #define CP_MEC_RS64_INTERRUPT_DATA_27__DATA_MASK 0xFFFFFFFFL |
31124 | //CP_MEC_RS64_INTERRUPT_DATA_28 |
31125 | #define CP_MEC_RS64_INTERRUPT_DATA_28__DATA__SHIFT 0x0 |
31126 | #define CP_MEC_RS64_INTERRUPT_DATA_28__DATA_MASK 0xFFFFFFFFL |
31127 | //CP_MEC_RS64_INTERRUPT_DATA_29 |
31128 | #define CP_MEC_RS64_INTERRUPT_DATA_29__DATA__SHIFT 0x0 |
31129 | #define CP_MEC_RS64_INTERRUPT_DATA_29__DATA_MASK 0xFFFFFFFFL |
31130 | //CP_MEC_RS64_INTERRUPT_DATA_30 |
31131 | #define CP_MEC_RS64_INTERRUPT_DATA_30__DATA__SHIFT 0x0 |
31132 | #define CP_MEC_RS64_INTERRUPT_DATA_30__DATA_MASK 0xFFFFFFFFL |
31133 | //CP_MEC_RS64_INTERRUPT_DATA_31 |
31134 | #define CP_MEC_RS64_INTERRUPT_DATA_31__DATA__SHIFT 0x0 |
31135 | #define CP_MEC_RS64_INTERRUPT_DATA_31__DATA_MASK 0xFFFFFFFFL |
31136 | //CP_MEC_DC_APERTURE0_BASE |
31137 | #define CP_MEC_DC_APERTURE0_BASE__BASE__SHIFT 0x0 |
31138 | #define CP_MEC_DC_APERTURE0_BASE__BASE_MASK 0xFFFFFFFFL |
31139 | //CP_MEC_DC_APERTURE0_MASK |
31140 | #define CP_MEC_DC_APERTURE0_MASK__MASK__SHIFT 0x0 |
31141 | #define CP_MEC_DC_APERTURE0_MASK__MASK_MASK 0xFFFFFFFFL |
31142 | //CP_MEC_DC_APERTURE0_CNTL |
31143 | #define CP_MEC_DC_APERTURE0_CNTL__VMID__SHIFT 0x0 |
31144 | #define CP_MEC_DC_APERTURE0_CNTL__BYPASS_MODE__SHIFT 0x4 |
31145 | #define CP_MEC_DC_APERTURE0_CNTL__VMID_MASK 0x0000000FL |
31146 | #define CP_MEC_DC_APERTURE0_CNTL__BYPASS_MODE_MASK 0x00000010L |
31147 | //CP_MEC_DC_APERTURE1_BASE |
31148 | #define CP_MEC_DC_APERTURE1_BASE__BASE__SHIFT 0x0 |
31149 | #define CP_MEC_DC_APERTURE1_BASE__BASE_MASK 0xFFFFFFFFL |
31150 | //CP_MEC_DC_APERTURE1_MASK |
31151 | #define CP_MEC_DC_APERTURE1_MASK__MASK__SHIFT 0x0 |
31152 | #define CP_MEC_DC_APERTURE1_MASK__MASK_MASK 0xFFFFFFFFL |
31153 | //CP_MEC_DC_APERTURE1_CNTL |
31154 | #define CP_MEC_DC_APERTURE1_CNTL__VMID__SHIFT 0x0 |
31155 | #define CP_MEC_DC_APERTURE1_CNTL__BYPASS_MODE__SHIFT 0x4 |
31156 | #define CP_MEC_DC_APERTURE1_CNTL__VMID_MASK 0x0000000FL |
31157 | #define CP_MEC_DC_APERTURE1_CNTL__BYPASS_MODE_MASK 0x00000010L |
31158 | //CP_MEC_DC_APERTURE2_BASE |
31159 | #define CP_MEC_DC_APERTURE2_BASE__BASE__SHIFT 0x0 |
31160 | #define CP_MEC_DC_APERTURE2_BASE__BASE_MASK 0xFFFFFFFFL |
31161 | //CP_MEC_DC_APERTURE2_MASK |
31162 | #define CP_MEC_DC_APERTURE2_MASK__MASK__SHIFT 0x0 |
31163 | #define CP_MEC_DC_APERTURE2_MASK__MASK_MASK 0xFFFFFFFFL |
31164 | //CP_MEC_DC_APERTURE2_CNTL |
31165 | #define CP_MEC_DC_APERTURE2_CNTL__VMID__SHIFT 0x0 |
31166 | #define CP_MEC_DC_APERTURE2_CNTL__BYPASS_MODE__SHIFT 0x4 |
31167 | #define CP_MEC_DC_APERTURE2_CNTL__VMID_MASK 0x0000000FL |
31168 | #define CP_MEC_DC_APERTURE2_CNTL__BYPASS_MODE_MASK 0x00000010L |
31169 | //CP_MEC_DC_APERTURE3_BASE |
31170 | #define CP_MEC_DC_APERTURE3_BASE__BASE__SHIFT 0x0 |
31171 | #define CP_MEC_DC_APERTURE3_BASE__BASE_MASK 0xFFFFFFFFL |
31172 | //CP_MEC_DC_APERTURE3_MASK |
31173 | #define CP_MEC_DC_APERTURE3_MASK__MASK__SHIFT 0x0 |
31174 | #define CP_MEC_DC_APERTURE3_MASK__MASK_MASK 0xFFFFFFFFL |
31175 | //CP_MEC_DC_APERTURE3_CNTL |
31176 | #define CP_MEC_DC_APERTURE3_CNTL__VMID__SHIFT 0x0 |
31177 | #define CP_MEC_DC_APERTURE3_CNTL__BYPASS_MODE__SHIFT 0x4 |
31178 | #define CP_MEC_DC_APERTURE3_CNTL__VMID_MASK 0x0000000FL |
31179 | #define CP_MEC_DC_APERTURE3_CNTL__BYPASS_MODE_MASK 0x00000010L |
31180 | //CP_MEC_DC_APERTURE4_BASE |
31181 | #define CP_MEC_DC_APERTURE4_BASE__BASE__SHIFT 0x0 |
31182 | #define CP_MEC_DC_APERTURE4_BASE__BASE_MASK 0xFFFFFFFFL |
31183 | //CP_MEC_DC_APERTURE4_MASK |
31184 | #define CP_MEC_DC_APERTURE4_MASK__MASK__SHIFT 0x0 |
31185 | #define CP_MEC_DC_APERTURE4_MASK__MASK_MASK 0xFFFFFFFFL |
31186 | //CP_MEC_DC_APERTURE4_CNTL |
31187 | #define CP_MEC_DC_APERTURE4_CNTL__VMID__SHIFT 0x0 |
31188 | #define CP_MEC_DC_APERTURE4_CNTL__BYPASS_MODE__SHIFT 0x4 |
31189 | #define CP_MEC_DC_APERTURE4_CNTL__VMID_MASK 0x0000000FL |
31190 | #define CP_MEC_DC_APERTURE4_CNTL__BYPASS_MODE_MASK 0x00000010L |
31191 | //CP_MEC_DC_APERTURE5_BASE |
31192 | #define CP_MEC_DC_APERTURE5_BASE__BASE__SHIFT 0x0 |
31193 | #define CP_MEC_DC_APERTURE5_BASE__BASE_MASK 0xFFFFFFFFL |
31194 | //CP_MEC_DC_APERTURE5_MASK |
31195 | #define CP_MEC_DC_APERTURE5_MASK__MASK__SHIFT 0x0 |
31196 | #define CP_MEC_DC_APERTURE5_MASK__MASK_MASK 0xFFFFFFFFL |
31197 | //CP_MEC_DC_APERTURE5_CNTL |
31198 | #define CP_MEC_DC_APERTURE5_CNTL__VMID__SHIFT 0x0 |
31199 | #define CP_MEC_DC_APERTURE5_CNTL__BYPASS_MODE__SHIFT 0x4 |
31200 | #define CP_MEC_DC_APERTURE5_CNTL__VMID_MASK 0x0000000FL |
31201 | #define CP_MEC_DC_APERTURE5_CNTL__BYPASS_MODE_MASK 0x00000010L |
31202 | //CP_MEC_DC_APERTURE6_BASE |
31203 | #define CP_MEC_DC_APERTURE6_BASE__BASE__SHIFT 0x0 |
31204 | #define CP_MEC_DC_APERTURE6_BASE__BASE_MASK 0xFFFFFFFFL |
31205 | //CP_MEC_DC_APERTURE6_MASK |
31206 | #define CP_MEC_DC_APERTURE6_MASK__MASK__SHIFT 0x0 |
31207 | #define CP_MEC_DC_APERTURE6_MASK__MASK_MASK 0xFFFFFFFFL |
31208 | //CP_MEC_DC_APERTURE6_CNTL |
31209 | #define CP_MEC_DC_APERTURE6_CNTL__VMID__SHIFT 0x0 |
31210 | #define CP_MEC_DC_APERTURE6_CNTL__BYPASS_MODE__SHIFT 0x4 |
31211 | #define CP_MEC_DC_APERTURE6_CNTL__VMID_MASK 0x0000000FL |
31212 | #define CP_MEC_DC_APERTURE6_CNTL__BYPASS_MODE_MASK 0x00000010L |
31213 | //CP_MEC_DC_APERTURE7_BASE |
31214 | #define CP_MEC_DC_APERTURE7_BASE__BASE__SHIFT 0x0 |
31215 | #define CP_MEC_DC_APERTURE7_BASE__BASE_MASK 0xFFFFFFFFL |
31216 | //CP_MEC_DC_APERTURE7_MASK |
31217 | #define CP_MEC_DC_APERTURE7_MASK__MASK__SHIFT 0x0 |
31218 | #define CP_MEC_DC_APERTURE7_MASK__MASK_MASK 0xFFFFFFFFL |
31219 | //CP_MEC_DC_APERTURE7_CNTL |
31220 | #define CP_MEC_DC_APERTURE7_CNTL__VMID__SHIFT 0x0 |
31221 | #define CP_MEC_DC_APERTURE7_CNTL__BYPASS_MODE__SHIFT 0x4 |
31222 | #define CP_MEC_DC_APERTURE7_CNTL__VMID_MASK 0x0000000FL |
31223 | #define CP_MEC_DC_APERTURE7_CNTL__BYPASS_MODE_MASK 0x00000010L |
31224 | //CP_MEC_DC_APERTURE8_BASE |
31225 | #define CP_MEC_DC_APERTURE8_BASE__BASE__SHIFT 0x0 |
31226 | #define CP_MEC_DC_APERTURE8_BASE__BASE_MASK 0xFFFFFFFFL |
31227 | //CP_MEC_DC_APERTURE8_MASK |
31228 | #define CP_MEC_DC_APERTURE8_MASK__MASK__SHIFT 0x0 |
31229 | #define CP_MEC_DC_APERTURE8_MASK__MASK_MASK 0xFFFFFFFFL |
31230 | //CP_MEC_DC_APERTURE8_CNTL |
31231 | #define CP_MEC_DC_APERTURE8_CNTL__VMID__SHIFT 0x0 |
31232 | #define CP_MEC_DC_APERTURE8_CNTL__BYPASS_MODE__SHIFT 0x4 |
31233 | #define CP_MEC_DC_APERTURE8_CNTL__VMID_MASK 0x0000000FL |
31234 | #define CP_MEC_DC_APERTURE8_CNTL__BYPASS_MODE_MASK 0x00000010L |
31235 | //CP_MEC_DC_APERTURE9_BASE |
31236 | #define CP_MEC_DC_APERTURE9_BASE__BASE__SHIFT 0x0 |
31237 | #define CP_MEC_DC_APERTURE9_BASE__BASE_MASK 0xFFFFFFFFL |
31238 | //CP_MEC_DC_APERTURE9_MASK |
31239 | #define CP_MEC_DC_APERTURE9_MASK__MASK__SHIFT 0x0 |
31240 | #define CP_MEC_DC_APERTURE9_MASK__MASK_MASK 0xFFFFFFFFL |
31241 | //CP_MEC_DC_APERTURE9_CNTL |
31242 | #define CP_MEC_DC_APERTURE9_CNTL__VMID__SHIFT 0x0 |
31243 | #define CP_MEC_DC_APERTURE9_CNTL__BYPASS_MODE__SHIFT 0x4 |
31244 | #define CP_MEC_DC_APERTURE9_CNTL__VMID_MASK 0x0000000FL |
31245 | #define CP_MEC_DC_APERTURE9_CNTL__BYPASS_MODE_MASK 0x00000010L |
31246 | //CP_MEC_DC_APERTURE10_BASE |
31247 | #define CP_MEC_DC_APERTURE10_BASE__BASE__SHIFT 0x0 |
31248 | #define CP_MEC_DC_APERTURE10_BASE__BASE_MASK 0xFFFFFFFFL |
31249 | //CP_MEC_DC_APERTURE10_MASK |
31250 | #define CP_MEC_DC_APERTURE10_MASK__MASK__SHIFT 0x0 |
31251 | #define CP_MEC_DC_APERTURE10_MASK__MASK_MASK 0xFFFFFFFFL |
31252 | //CP_MEC_DC_APERTURE10_CNTL |
31253 | #define CP_MEC_DC_APERTURE10_CNTL__VMID__SHIFT 0x0 |
31254 | #define CP_MEC_DC_APERTURE10_CNTL__BYPASS_MODE__SHIFT 0x4 |
31255 | #define CP_MEC_DC_APERTURE10_CNTL__VMID_MASK 0x0000000FL |
31256 | #define CP_MEC_DC_APERTURE10_CNTL__BYPASS_MODE_MASK 0x00000010L |
31257 | //CP_MEC_DC_APERTURE11_BASE |
31258 | #define CP_MEC_DC_APERTURE11_BASE__BASE__SHIFT 0x0 |
31259 | #define CP_MEC_DC_APERTURE11_BASE__BASE_MASK 0xFFFFFFFFL |
31260 | //CP_MEC_DC_APERTURE11_MASK |
31261 | #define CP_MEC_DC_APERTURE11_MASK__MASK__SHIFT 0x0 |
31262 | #define CP_MEC_DC_APERTURE11_MASK__MASK_MASK 0xFFFFFFFFL |
31263 | //CP_MEC_DC_APERTURE11_CNTL |
31264 | #define CP_MEC_DC_APERTURE11_CNTL__VMID__SHIFT 0x0 |
31265 | #define CP_MEC_DC_APERTURE11_CNTL__BYPASS_MODE__SHIFT 0x4 |
31266 | #define CP_MEC_DC_APERTURE11_CNTL__VMID_MASK 0x0000000FL |
31267 | #define CP_MEC_DC_APERTURE11_CNTL__BYPASS_MODE_MASK 0x00000010L |
31268 | //CP_MEC_DC_APERTURE12_BASE |
31269 | #define CP_MEC_DC_APERTURE12_BASE__BASE__SHIFT 0x0 |
31270 | #define CP_MEC_DC_APERTURE12_BASE__BASE_MASK 0xFFFFFFFFL |
31271 | //CP_MEC_DC_APERTURE12_MASK |
31272 | #define CP_MEC_DC_APERTURE12_MASK__MASK__SHIFT 0x0 |
31273 | #define CP_MEC_DC_APERTURE12_MASK__MASK_MASK 0xFFFFFFFFL |
31274 | //CP_MEC_DC_APERTURE12_CNTL |
31275 | #define CP_MEC_DC_APERTURE12_CNTL__VMID__SHIFT 0x0 |
31276 | #define CP_MEC_DC_APERTURE12_CNTL__BYPASS_MODE__SHIFT 0x4 |
31277 | #define CP_MEC_DC_APERTURE12_CNTL__VMID_MASK 0x0000000FL |
31278 | #define CP_MEC_DC_APERTURE12_CNTL__BYPASS_MODE_MASK 0x00000010L |
31279 | //CP_MEC_DC_APERTURE13_BASE |
31280 | #define CP_MEC_DC_APERTURE13_BASE__BASE__SHIFT 0x0 |
31281 | #define CP_MEC_DC_APERTURE13_BASE__BASE_MASK 0xFFFFFFFFL |
31282 | //CP_MEC_DC_APERTURE13_MASK |
31283 | #define CP_MEC_DC_APERTURE13_MASK__MASK__SHIFT 0x0 |
31284 | #define CP_MEC_DC_APERTURE13_MASK__MASK_MASK 0xFFFFFFFFL |
31285 | //CP_MEC_DC_APERTURE13_CNTL |
31286 | #define CP_MEC_DC_APERTURE13_CNTL__VMID__SHIFT 0x0 |
31287 | #define CP_MEC_DC_APERTURE13_CNTL__BYPASS_MODE__SHIFT 0x4 |
31288 | #define CP_MEC_DC_APERTURE13_CNTL__VMID_MASK 0x0000000FL |
31289 | #define CP_MEC_DC_APERTURE13_CNTL__BYPASS_MODE_MASK 0x00000010L |
31290 | //CP_MEC_DC_APERTURE14_BASE |
31291 | #define CP_MEC_DC_APERTURE14_BASE__BASE__SHIFT 0x0 |
31292 | #define CP_MEC_DC_APERTURE14_BASE__BASE_MASK 0xFFFFFFFFL |
31293 | //CP_MEC_DC_APERTURE14_MASK |
31294 | #define CP_MEC_DC_APERTURE14_MASK__MASK__SHIFT 0x0 |
31295 | #define CP_MEC_DC_APERTURE14_MASK__MASK_MASK 0xFFFFFFFFL |
31296 | //CP_MEC_DC_APERTURE14_CNTL |
31297 | #define CP_MEC_DC_APERTURE14_CNTL__VMID__SHIFT 0x0 |
31298 | #define CP_MEC_DC_APERTURE14_CNTL__BYPASS_MODE__SHIFT 0x4 |
31299 | #define CP_MEC_DC_APERTURE14_CNTL__VMID_MASK 0x0000000FL |
31300 | #define CP_MEC_DC_APERTURE14_CNTL__BYPASS_MODE_MASK 0x00000010L |
31301 | //CP_MEC_DC_APERTURE15_BASE |
31302 | #define CP_MEC_DC_APERTURE15_BASE__BASE__SHIFT 0x0 |
31303 | #define CP_MEC_DC_APERTURE15_BASE__BASE_MASK 0xFFFFFFFFL |
31304 | //CP_MEC_DC_APERTURE15_MASK |
31305 | #define CP_MEC_DC_APERTURE15_MASK__MASK__SHIFT 0x0 |
31306 | #define CP_MEC_DC_APERTURE15_MASK__MASK_MASK 0xFFFFFFFFL |
31307 | //CP_MEC_DC_APERTURE15_CNTL |
31308 | #define CP_MEC_DC_APERTURE15_CNTL__VMID__SHIFT 0x0 |
31309 | #define CP_MEC_DC_APERTURE15_CNTL__BYPASS_MODE__SHIFT 0x4 |
31310 | #define CP_MEC_DC_APERTURE15_CNTL__VMID_MASK 0x0000000FL |
31311 | #define CP_MEC_DC_APERTURE15_CNTL__BYPASS_MODE_MASK 0x00000010L |
31312 | //CP_CPC_IC_OP_CNTL |
31313 | #define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT 0x0 |
31314 | #define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE_COMPLETE__SHIFT 0x1 |
31315 | #define CP_CPC_IC_OP_CNTL__PRIME_ICACHE__SHIFT 0x4 |
31316 | #define CP_CPC_IC_OP_CNTL__ICACHE_PRIMED__SHIFT 0x5 |
31317 | #define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE_MASK 0x00000001L |
31318 | #define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE_COMPLETE_MASK 0x00000002L |
31319 | #define CP_CPC_IC_OP_CNTL__PRIME_ICACHE_MASK 0x00000010L |
31320 | #define CP_CPC_IC_OP_CNTL__ICACHE_PRIMED_MASK 0x00000020L |
31321 | //CP_GFX_CNTL |
31322 | #define CP_GFX_CNTL__ENGINE_SEL__SHIFT 0x0 |
31323 | #define CP_GFX_CNTL__CONFIG__SHIFT 0x1 |
31324 | #define CP_GFX_CNTL__ENGINE_SEL_MASK 0x00000001L |
31325 | #define CP_GFX_CNTL__CONFIG_MASK 0x00000006L |
31326 | //CP_GFX_RS64_INTERRUPT0 |
31327 | #define CP_GFX_RS64_INTERRUPT0__ME_INT__SHIFT 0x0 |
31328 | #define CP_GFX_RS64_INTERRUPT0__ME_INT_MASK 0xFFFFFFFFL |
31329 | //CP_GFX_RS64_INTR_EN0 |
31330 | #define CP_GFX_RS64_INTR_EN0__ME_INT__SHIFT 0x0 |
31331 | #define CP_GFX_RS64_INTR_EN0__ME_INT_MASK 0xFFFFFFFFL |
31332 | //CP_GFX_RS64_INTR_EN1 |
31333 | #define CP_GFX_RS64_INTR_EN1__ME_INT__SHIFT 0x0 |
31334 | #define CP_GFX_RS64_INTR_EN1__ME_INT_MASK 0xFFFFFFFFL |
31335 | //CP_GFX_RS64_DC_BASE_CNTL |
31336 | #define CP_GFX_RS64_DC_BASE_CNTL__VMID__SHIFT 0x0 |
31337 | #define CP_GFX_RS64_DC_BASE_CNTL__CACHE_POLICY__SHIFT 0x18 |
31338 | #define CP_GFX_RS64_DC_BASE_CNTL__VMID_MASK 0x0000000FL |
31339 | #define CP_GFX_RS64_DC_BASE_CNTL__CACHE_POLICY_MASK 0x03000000L |
31340 | //CP_GFX_RS64_DC_OP_CNTL |
31341 | #define CP_GFX_RS64_DC_OP_CNTL__INVALIDATE_DCACHE__SHIFT 0x0 |
31342 | #define CP_GFX_RS64_DC_OP_CNTL__INVALIDATE_DCACHE_COMPLETE__SHIFT 0x1 |
31343 | #define CP_GFX_RS64_DC_OP_CNTL__BYPASS_ALL__SHIFT 0x2 |
31344 | #define CP_GFX_RS64_DC_OP_CNTL__RESERVED__SHIFT 0x3 |
31345 | #define CP_GFX_RS64_DC_OP_CNTL__PRIME_DCACHE__SHIFT 0x4 |
31346 | #define CP_GFX_RS64_DC_OP_CNTL__DCACHE_PRIMED__SHIFT 0x5 |
31347 | #define CP_GFX_RS64_DC_OP_CNTL__INVALIDATE_DCACHE_MASK 0x00000001L |
31348 | #define CP_GFX_RS64_DC_OP_CNTL__INVALIDATE_DCACHE_COMPLETE_MASK 0x00000002L |
31349 | #define CP_GFX_RS64_DC_OP_CNTL__BYPASS_ALL_MASK 0x00000004L |
31350 | #define CP_GFX_RS64_DC_OP_CNTL__RESERVED_MASK 0x00000008L |
31351 | #define CP_GFX_RS64_DC_OP_CNTL__PRIME_DCACHE_MASK 0x00000010L |
31352 | #define CP_GFX_RS64_DC_OP_CNTL__DCACHE_PRIMED_MASK 0x00000020L |
31353 | //CP_GFX_RS64_LOCAL_BASE0_LO |
31354 | #define CP_GFX_RS64_LOCAL_BASE0_LO__BASE0_LO__SHIFT 0x10 |
31355 | #define CP_GFX_RS64_LOCAL_BASE0_LO__BASE0_LO_MASK 0xFFFF0000L |
31356 | //CP_GFX_RS64_LOCAL_BASE0_HI |
31357 | #define CP_GFX_RS64_LOCAL_BASE0_HI__BASE0_HI__SHIFT 0x0 |
31358 | #define CP_GFX_RS64_LOCAL_BASE0_HI__BASE0_HI_MASK 0x0000FFFFL |
31359 | //CP_GFX_RS64_LOCAL_MASK0_LO |
31360 | #define CP_GFX_RS64_LOCAL_MASK0_LO__MASK0_LO__SHIFT 0x10 |
31361 | #define CP_GFX_RS64_LOCAL_MASK0_LO__MASK0_LO_MASK 0xFFFF0000L |
31362 | //CP_GFX_RS64_LOCAL_MASK0_HI |
31363 | #define CP_GFX_RS64_LOCAL_MASK0_HI__MASK0_HI__SHIFT 0x0 |
31364 | #define CP_GFX_RS64_LOCAL_MASK0_HI__MASK0_HI_MASK 0x0000FFFFL |
31365 | //CP_GFX_RS64_LOCAL_APERTURE |
31366 | #define CP_GFX_RS64_LOCAL_APERTURE__APERTURE__SHIFT 0x0 |
31367 | #define CP_GFX_RS64_LOCAL_APERTURE__APERTURE_MASK 0x00000007L |
31368 | //CP_GFX_RS64_LOCAL_INSTR_BASE_LO |
31369 | #define CP_GFX_RS64_LOCAL_INSTR_BASE_LO__BASE_LO__SHIFT 0x10 |
31370 | #define CP_GFX_RS64_LOCAL_INSTR_BASE_LO__BASE_LO_MASK 0xFFFF0000L |
31371 | //CP_GFX_RS64_LOCAL_INSTR_BASE_HI |
31372 | #define CP_GFX_RS64_LOCAL_INSTR_BASE_HI__BASE_HI__SHIFT 0x0 |
31373 | #define CP_GFX_RS64_LOCAL_INSTR_BASE_HI__BASE_HI_MASK 0x0000FFFFL |
31374 | //CP_GFX_RS64_LOCAL_INSTR_MASK_LO |
31375 | #define CP_GFX_RS64_LOCAL_INSTR_MASK_LO__MASK_LO__SHIFT 0x10 |
31376 | #define CP_GFX_RS64_LOCAL_INSTR_MASK_LO__MASK_LO_MASK 0xFFFF0000L |
31377 | //CP_GFX_RS64_LOCAL_INSTR_MASK_HI |
31378 | #define CP_GFX_RS64_LOCAL_INSTR_MASK_HI__MASK_HI__SHIFT 0x0 |
31379 | #define CP_GFX_RS64_LOCAL_INSTR_MASK_HI__MASK_HI_MASK 0x0000FFFFL |
31380 | //CP_GFX_RS64_LOCAL_INSTR_APERTURE |
31381 | #define CP_GFX_RS64_LOCAL_INSTR_APERTURE__APERTURE__SHIFT 0x0 |
31382 | #define CP_GFX_RS64_LOCAL_INSTR_APERTURE__APERTURE_MASK 0x00000007L |
31383 | //CP_GFX_RS64_LOCAL_SCRATCH_APERTURE |
31384 | #define CP_GFX_RS64_LOCAL_SCRATCH_APERTURE__APERTURE__SHIFT 0x0 |
31385 | #define CP_GFX_RS64_LOCAL_SCRATCH_APERTURE__APERTURE_MASK 0x00000007L |
31386 | //CP_GFX_RS64_LOCAL_SCRATCH_BASE_LO |
31387 | #define CP_GFX_RS64_LOCAL_SCRATCH_BASE_LO__BASE_LO__SHIFT 0x10 |
31388 | #define CP_GFX_RS64_LOCAL_SCRATCH_BASE_LO__BASE_LO_MASK 0xFFFF0000L |
31389 | //CP_GFX_RS64_LOCAL_SCRATCH_BASE_HI |
31390 | #define CP_GFX_RS64_LOCAL_SCRATCH_BASE_HI__BASE_HI__SHIFT 0x0 |
31391 | #define CP_GFX_RS64_LOCAL_SCRATCH_BASE_HI__BASE_HI_MASK 0x0000FFFFL |
31392 | //CP_GFX_RS64_PERFCOUNT_CNTL0 |
31393 | #define CP_GFX_RS64_PERFCOUNT_CNTL0__EVENT_SEL__SHIFT 0x0 |
31394 | #define CP_GFX_RS64_PERFCOUNT_CNTL0__EVENT_SEL_MASK 0x0000001FL |
31395 | //CP_GFX_RS64_PERFCOUNT_CNTL1 |
31396 | #define CP_GFX_RS64_PERFCOUNT_CNTL1__EVENT_SEL__SHIFT 0x0 |
31397 | #define CP_GFX_RS64_PERFCOUNT_CNTL1__EVENT_SEL_MASK 0x0000001FL |
31398 | //CP_GFX_RS64_MIP_LO0 |
31399 | #define CP_GFX_RS64_MIP_LO0__MIP_LO__SHIFT 0x0 |
31400 | #define CP_GFX_RS64_MIP_LO0__MIP_LO_MASK 0xFFFFFFFFL |
31401 | //CP_GFX_RS64_MIP_LO1 |
31402 | #define CP_GFX_RS64_MIP_LO1__MIP_LO__SHIFT 0x0 |
31403 | #define CP_GFX_RS64_MIP_LO1__MIP_LO_MASK 0xFFFFFFFFL |
31404 | //CP_GFX_RS64_MIP_HI0 |
31405 | #define CP_GFX_RS64_MIP_HI0__MIP_HI__SHIFT 0x0 |
31406 | #define CP_GFX_RS64_MIP_HI0__MIP_HI_MASK 0xFFFFFFFFL |
31407 | //CP_GFX_RS64_MIP_HI1 |
31408 | #define CP_GFX_RS64_MIP_HI1__MIP_HI__SHIFT 0x0 |
31409 | #define CP_GFX_RS64_MIP_HI1__MIP_HI_MASK 0xFFFFFFFFL |
31410 | //CP_GFX_RS64_MTIMECMP_LO0 |
31411 | #define CP_GFX_RS64_MTIMECMP_LO0__TIME_LO__SHIFT 0x0 |
31412 | #define CP_GFX_RS64_MTIMECMP_LO0__TIME_LO_MASK 0xFFFFFFFFL |
31413 | //CP_GFX_RS64_MTIMECMP_LO1 |
31414 | #define CP_GFX_RS64_MTIMECMP_LO1__TIME_LO__SHIFT 0x0 |
31415 | #define CP_GFX_RS64_MTIMECMP_LO1__TIME_LO_MASK 0xFFFFFFFFL |
31416 | //CP_GFX_RS64_MTIMECMP_HI0 |
31417 | #define CP_GFX_RS64_MTIMECMP_HI0__TIME_HI__SHIFT 0x0 |
31418 | #define CP_GFX_RS64_MTIMECMP_HI0__TIME_HI_MASK 0xFFFFFFFFL |
31419 | //CP_GFX_RS64_MTIMECMP_HI1 |
31420 | #define CP_GFX_RS64_MTIMECMP_HI1__TIME_HI__SHIFT 0x0 |
31421 | #define CP_GFX_RS64_MTIMECMP_HI1__TIME_HI_MASK 0xFFFFFFFFL |
31422 | //CP_GFX_RS64_GP0_LO0 |
31423 | #define CP_GFX_RS64_GP0_LO0__PG_VIRT_HALTED__SHIFT 0x0 |
31424 | #define CP_GFX_RS64_GP0_LO0__DATA__SHIFT 0x1 |
31425 | #define CP_GFX_RS64_GP0_LO0__PG_VIRT_HALTED_MASK 0x00000001L |
31426 | #define CP_GFX_RS64_GP0_LO0__DATA_MASK 0xFFFFFFFEL |
31427 | //CP_GFX_RS64_GP0_LO1 |
31428 | #define CP_GFX_RS64_GP0_LO1__PG_VIRT_HALTED__SHIFT 0x0 |
31429 | #define CP_GFX_RS64_GP0_LO1__DATA__SHIFT 0x1 |
31430 | #define CP_GFX_RS64_GP0_LO1__PG_VIRT_HALTED_MASK 0x00000001L |
31431 | #define CP_GFX_RS64_GP0_LO1__DATA_MASK 0xFFFFFFFEL |
31432 | //CP_GFX_RS64_GP0_HI0 |
31433 | #define CP_GFX_RS64_GP0_HI0__M_RET_ADDR__SHIFT 0x0 |
31434 | #define CP_GFX_RS64_GP0_HI0__M_RET_ADDR_MASK 0xFFFFFFFFL |
31435 | //CP_GFX_RS64_GP0_HI1 |
31436 | #define CP_GFX_RS64_GP0_HI1__M_RET_ADDR__SHIFT 0x0 |
31437 | #define CP_GFX_RS64_GP0_HI1__M_RET_ADDR_MASK 0xFFFFFFFFL |
31438 | //CP_GFX_RS64_GP1_LO0 |
31439 | #define CP_GFX_RS64_GP1_LO0__RD_WR_SELECT_LO__SHIFT 0x0 |
31440 | #define CP_GFX_RS64_GP1_LO0__RD_WR_SELECT_LO_MASK 0xFFFFFFFFL |
31441 | //CP_GFX_RS64_GP1_LO1 |
31442 | #define CP_GFX_RS64_GP1_LO1__RD_WR_SELECT_LO__SHIFT 0x0 |
31443 | #define CP_GFX_RS64_GP1_LO1__RD_WR_SELECT_LO_MASK 0xFFFFFFFFL |
31444 | //CP_GFX_RS64_GP1_HI0 |
31445 | #define CP_GFX_RS64_GP1_HI0__RD_WR_SELECT_HI__SHIFT 0x0 |
31446 | #define CP_GFX_RS64_GP1_HI0__RD_WR_SELECT_HI_MASK 0xFFFFFFFFL |
31447 | //CP_GFX_RS64_GP1_HI1 |
31448 | #define CP_GFX_RS64_GP1_HI1__RD_WR_SELECT_HI__SHIFT 0x0 |
31449 | #define CP_GFX_RS64_GP1_HI1__RD_WR_SELECT_HI_MASK 0xFFFFFFFFL |
31450 | //CP_GFX_RS64_GP2_LO0 |
31451 | #define CP_GFX_RS64_GP2_LO0__STACK_PNTR_LO__SHIFT 0x0 |
31452 | #define CP_GFX_RS64_GP2_LO0__STACK_PNTR_LO_MASK 0xFFFFFFFFL |
31453 | //CP_GFX_RS64_GP2_LO1 |
31454 | #define CP_GFX_RS64_GP2_LO1__STACK_PNTR_LO__SHIFT 0x0 |
31455 | #define CP_GFX_RS64_GP2_LO1__STACK_PNTR_LO_MASK 0xFFFFFFFFL |
31456 | //CP_GFX_RS64_GP2_HI0 |
31457 | #define CP_GFX_RS64_GP2_HI0__STACK_PNTR_HI__SHIFT 0x0 |
31458 | #define CP_GFX_RS64_GP2_HI0__STACK_PNTR_HI_MASK 0xFFFFFFFFL |
31459 | //CP_GFX_RS64_GP2_HI1 |
31460 | #define CP_GFX_RS64_GP2_HI1__STACK_PNTR_HI__SHIFT 0x0 |
31461 | #define CP_GFX_RS64_GP2_HI1__STACK_PNTR_HI_MASK 0xFFFFFFFFL |
31462 | //CP_GFX_RS64_GP3_LO0 |
31463 | #define CP_GFX_RS64_GP3_LO0__DATA__SHIFT 0x0 |
31464 | #define CP_GFX_RS64_GP3_LO0__DATA_MASK 0xFFFFFFFFL |
31465 | //CP_GFX_RS64_GP3_LO1 |
31466 | #define CP_GFX_RS64_GP3_LO1__DATA__SHIFT 0x0 |
31467 | #define CP_GFX_RS64_GP3_LO1__DATA_MASK 0xFFFFFFFFL |
31468 | //CP_GFX_RS64_GP3_HI0 |
31469 | #define CP_GFX_RS64_GP3_HI0__DATA__SHIFT 0x0 |
31470 | #define CP_GFX_RS64_GP3_HI0__DATA_MASK 0xFFFFFFFFL |
31471 | //CP_GFX_RS64_GP3_HI1 |
31472 | #define CP_GFX_RS64_GP3_HI1__DATA__SHIFT 0x0 |
31473 | #define CP_GFX_RS64_GP3_HI1__DATA_MASK 0xFFFFFFFFL |
31474 | //CP_GFX_RS64_GP4_LO0 |
31475 | #define CP_GFX_RS64_GP4_LO0__DATA__SHIFT 0x0 |
31476 | #define CP_GFX_RS64_GP4_LO0__DATA_MASK 0xFFFFFFFFL |
31477 | //CP_GFX_RS64_GP4_LO1 |
31478 | #define CP_GFX_RS64_GP4_LO1__DATA__SHIFT 0x0 |
31479 | #define CP_GFX_RS64_GP4_LO1__DATA_MASK 0xFFFFFFFFL |
31480 | //CP_GFX_RS64_GP4_HI0 |
31481 | #define CP_GFX_RS64_GP4_HI0__DATA__SHIFT 0x0 |
31482 | #define CP_GFX_RS64_GP4_HI0__DATA_MASK 0xFFFFFFFFL |
31483 | //CP_GFX_RS64_GP4_HI1 |
31484 | #define CP_GFX_RS64_GP4_HI1__DATA__SHIFT 0x0 |
31485 | #define CP_GFX_RS64_GP4_HI1__DATA_MASK 0xFFFFFFFFL |
31486 | //CP_GFX_RS64_GP5_LO0 |
31487 | #define CP_GFX_RS64_GP5_LO0__PG_VIRT_HALTED__SHIFT 0x0 |
31488 | #define CP_GFX_RS64_GP5_LO0__DATA__SHIFT 0x1 |
31489 | #define CP_GFX_RS64_GP5_LO0__PG_VIRT_HALTED_MASK 0x00000001L |
31490 | #define CP_GFX_RS64_GP5_LO0__DATA_MASK 0xFFFFFFFEL |
31491 | //CP_GFX_RS64_GP5_LO1 |
31492 | #define CP_GFX_RS64_GP5_LO1__PG_VIRT_HALTED__SHIFT 0x0 |
31493 | #define CP_GFX_RS64_GP5_LO1__DATA__SHIFT 0x1 |
31494 | #define CP_GFX_RS64_GP5_LO1__PG_VIRT_HALTED_MASK 0x00000001L |
31495 | #define CP_GFX_RS64_GP5_LO1__DATA_MASK 0xFFFFFFFEL |
31496 | //CP_GFX_RS64_GP5_HI0 |
31497 | #define CP_GFX_RS64_GP5_HI0__M_RET_ADDR__SHIFT 0x0 |
31498 | #define CP_GFX_RS64_GP5_HI0__M_RET_ADDR_MASK 0xFFFFFFFFL |
31499 | //CP_GFX_RS64_GP5_HI1 |
31500 | #define CP_GFX_RS64_GP5_HI1__M_RET_ADDR__SHIFT 0x0 |
31501 | #define CP_GFX_RS64_GP5_HI1__M_RET_ADDR_MASK 0xFFFFFFFFL |
31502 | //CP_GFX_RS64_GP6_LO |
31503 | #define CP_GFX_RS64_GP6_LO__RD_WR_SELECT_LO__SHIFT 0x0 |
31504 | #define CP_GFX_RS64_GP6_LO__RD_WR_SELECT_LO_MASK 0xFFFFFFFFL |
31505 | //CP_GFX_RS64_GP6_HI |
31506 | #define CP_GFX_RS64_GP6_HI__RD_WR_SELECT_HI__SHIFT 0x0 |
31507 | #define CP_GFX_RS64_GP6_HI__RD_WR_SELECT_HI_MASK 0xFFFFFFFFL |
31508 | //CP_GFX_RS64_GP7_LO |
31509 | #define CP_GFX_RS64_GP7_LO__STACK_PNTR_LO__SHIFT 0x0 |
31510 | #define CP_GFX_RS64_GP7_LO__STACK_PNTR_LO_MASK 0xFFFFFFFFL |
31511 | //CP_GFX_RS64_GP7_HI |
31512 | #define CP_GFX_RS64_GP7_HI__STACK_PNTR_HI__SHIFT 0x0 |
31513 | #define CP_GFX_RS64_GP7_HI__STACK_PNTR_HI_MASK 0xFFFFFFFFL |
31514 | //CP_GFX_RS64_GP8_LO |
31515 | #define CP_GFX_RS64_GP8_LO__DATA__SHIFT 0x0 |
31516 | #define CP_GFX_RS64_GP8_LO__DATA_MASK 0xFFFFFFFFL |
31517 | //CP_GFX_RS64_GP8_HI |
31518 | #define CP_GFX_RS64_GP8_HI__DATA__SHIFT 0x0 |
31519 | #define CP_GFX_RS64_GP8_HI__DATA_MASK 0xFFFFFFFFL |
31520 | //CP_GFX_RS64_GP9_LO |
31521 | #define CP_GFX_RS64_GP9_LO__DATA__SHIFT 0x0 |
31522 | #define CP_GFX_RS64_GP9_LO__DATA_MASK 0xFFFFFFFFL |
31523 | //CP_GFX_RS64_GP9_HI |
31524 | #define CP_GFX_RS64_GP9_HI__DATA__SHIFT 0x0 |
31525 | #define CP_GFX_RS64_GP9_HI__DATA_MASK 0xFFFFFFFFL |
31526 | //CP_GFX_RS64_INSTR_PNTR0 |
31527 | #define CP_GFX_RS64_INSTR_PNTR0__INSTR_PNTR__SHIFT 0x0 |
31528 | #define CP_GFX_RS64_INSTR_PNTR0__INSTR_PNTR_MASK 0x000FFFFFL |
31529 | //CP_GFX_RS64_INSTR_PNTR1 |
31530 | #define CP_GFX_RS64_INSTR_PNTR1__INSTR_PNTR__SHIFT 0x0 |
31531 | #define CP_GFX_RS64_INSTR_PNTR1__INSTR_PNTR_MASK 0x000FFFFFL |
31532 | //CP_GFX_RS64_PENDING_INTERRUPT0 |
31533 | #define CP_GFX_RS64_PENDING_INTERRUPT0__PENDING_INTERRUPT__SHIFT 0x0 |
31534 | #define CP_GFX_RS64_PENDING_INTERRUPT0__PENDING_INTERRUPT_MASK 0xFFFFFFFFL |
31535 | //CP_GFX_RS64_PENDING_INTERRUPT1 |
31536 | #define CP_GFX_RS64_PENDING_INTERRUPT1__PENDING_INTERRUPT__SHIFT 0x0 |
31537 | #define CP_GFX_RS64_PENDING_INTERRUPT1__PENDING_INTERRUPT_MASK 0xFFFFFFFFL |
31538 | //CP_GFX_RS64_DC_APERTURE0_BASE0 |
31539 | #define CP_GFX_RS64_DC_APERTURE0_BASE0__BASE__SHIFT 0x0 |
31540 | #define CP_GFX_RS64_DC_APERTURE0_BASE0__BASE_MASK 0xFFFFFFFFL |
31541 | //CP_GFX_RS64_DC_APERTURE0_MASK0 |
31542 | #define CP_GFX_RS64_DC_APERTURE0_MASK0__MASK__SHIFT 0x0 |
31543 | #define CP_GFX_RS64_DC_APERTURE0_MASK0__MASK_MASK 0xFFFFFFFFL |
31544 | //CP_GFX_RS64_DC_APERTURE0_CNTL0 |
31545 | #define CP_GFX_RS64_DC_APERTURE0_CNTL0__VMID__SHIFT 0x0 |
31546 | #define CP_GFX_RS64_DC_APERTURE0_CNTL0__BYPASS_MODE__SHIFT 0x4 |
31547 | #define CP_GFX_RS64_DC_APERTURE0_CNTL0__VMID_MASK 0x0000000FL |
31548 | #define CP_GFX_RS64_DC_APERTURE0_CNTL0__BYPASS_MODE_MASK 0x00000010L |
31549 | //CP_GFX_RS64_DC_APERTURE1_BASE0 |
31550 | #define CP_GFX_RS64_DC_APERTURE1_BASE0__BASE__SHIFT 0x0 |
31551 | #define CP_GFX_RS64_DC_APERTURE1_BASE0__BASE_MASK 0xFFFFFFFFL |
31552 | //CP_GFX_RS64_DC_APERTURE1_MASK0 |
31553 | #define CP_GFX_RS64_DC_APERTURE1_MASK0__MASK__SHIFT 0x0 |
31554 | #define CP_GFX_RS64_DC_APERTURE1_MASK0__MASK_MASK 0xFFFFFFFFL |
31555 | //CP_GFX_RS64_DC_APERTURE1_CNTL0 |
31556 | #define CP_GFX_RS64_DC_APERTURE1_CNTL0__VMID__SHIFT 0x0 |
31557 | #define CP_GFX_RS64_DC_APERTURE1_CNTL0__BYPASS_MODE__SHIFT 0x4 |
31558 | #define CP_GFX_RS64_DC_APERTURE1_CNTL0__VMID_MASK 0x0000000FL |
31559 | #define CP_GFX_RS64_DC_APERTURE1_CNTL0__BYPASS_MODE_MASK 0x00000010L |
31560 | //CP_GFX_RS64_DC_APERTURE2_BASE0 |
31561 | #define CP_GFX_RS64_DC_APERTURE2_BASE0__BASE__SHIFT 0x0 |
31562 | #define CP_GFX_RS64_DC_APERTURE2_BASE0__BASE_MASK 0xFFFFFFFFL |
31563 | //CP_GFX_RS64_DC_APERTURE2_MASK0 |
31564 | #define CP_GFX_RS64_DC_APERTURE2_MASK0__MASK__SHIFT 0x0 |
31565 | #define CP_GFX_RS64_DC_APERTURE2_MASK0__MASK_MASK 0xFFFFFFFFL |
31566 | //CP_GFX_RS64_DC_APERTURE2_CNTL0 |
31567 | #define CP_GFX_RS64_DC_APERTURE2_CNTL0__VMID__SHIFT 0x0 |
31568 | #define CP_GFX_RS64_DC_APERTURE2_CNTL0__BYPASS_MODE__SHIFT 0x4 |
31569 | #define CP_GFX_RS64_DC_APERTURE2_CNTL0__VMID_MASK 0x0000000FL |
31570 | #define CP_GFX_RS64_DC_APERTURE2_CNTL0__BYPASS_MODE_MASK 0x00000010L |
31571 | //CP_GFX_RS64_DC_APERTURE3_BASE0 |
31572 | #define CP_GFX_RS64_DC_APERTURE3_BASE0__BASE__SHIFT 0x0 |
31573 | #define CP_GFX_RS64_DC_APERTURE3_BASE0__BASE_MASK 0xFFFFFFFFL |
31574 | //CP_GFX_RS64_DC_APERTURE3_MASK0 |
31575 | #define CP_GFX_RS64_DC_APERTURE3_MASK0__MASK__SHIFT 0x0 |
31576 | #define CP_GFX_RS64_DC_APERTURE3_MASK0__MASK_MASK 0xFFFFFFFFL |
31577 | //CP_GFX_RS64_DC_APERTURE3_CNTL0 |
31578 | #define CP_GFX_RS64_DC_APERTURE3_CNTL0__VMID__SHIFT 0x0 |
31579 | #define CP_GFX_RS64_DC_APERTURE3_CNTL0__BYPASS_MODE__SHIFT 0x4 |
31580 | #define CP_GFX_RS64_DC_APERTURE3_CNTL0__VMID_MASK 0x0000000FL |
31581 | #define CP_GFX_RS64_DC_APERTURE3_CNTL0__BYPASS_MODE_MASK 0x00000010L |
31582 | //CP_GFX_RS64_DC_APERTURE4_BASE0 |
31583 | #define CP_GFX_RS64_DC_APERTURE4_BASE0__BASE__SHIFT 0x0 |
31584 | #define CP_GFX_RS64_DC_APERTURE4_BASE0__BASE_MASK 0xFFFFFFFFL |
31585 | //CP_GFX_RS64_DC_APERTURE4_MASK0 |
31586 | #define CP_GFX_RS64_DC_APERTURE4_MASK0__MASK__SHIFT 0x0 |
31587 | #define CP_GFX_RS64_DC_APERTURE4_MASK0__MASK_MASK 0xFFFFFFFFL |
31588 | //CP_GFX_RS64_DC_APERTURE4_CNTL0 |
31589 | #define CP_GFX_RS64_DC_APERTURE4_CNTL0__VMID__SHIFT 0x0 |
31590 | #define CP_GFX_RS64_DC_APERTURE4_CNTL0__BYPASS_MODE__SHIFT 0x4 |
31591 | #define CP_GFX_RS64_DC_APERTURE4_CNTL0__VMID_MASK 0x0000000FL |
31592 | #define CP_GFX_RS64_DC_APERTURE4_CNTL0__BYPASS_MODE_MASK 0x00000010L |
31593 | //CP_GFX_RS64_DC_APERTURE5_BASE0 |
31594 | #define CP_GFX_RS64_DC_APERTURE5_BASE0__BASE__SHIFT 0x0 |
31595 | #define CP_GFX_RS64_DC_APERTURE5_BASE0__BASE_MASK 0xFFFFFFFFL |
31596 | //CP_GFX_RS64_DC_APERTURE5_MASK0 |
31597 | #define CP_GFX_RS64_DC_APERTURE5_MASK0__MASK__SHIFT 0x0 |
31598 | #define CP_GFX_RS64_DC_APERTURE5_MASK0__MASK_MASK 0xFFFFFFFFL |
31599 | //CP_GFX_RS64_DC_APERTURE5_CNTL0 |
31600 | #define CP_GFX_RS64_DC_APERTURE5_CNTL0__VMID__SHIFT 0x0 |
31601 | #define CP_GFX_RS64_DC_APERTURE5_CNTL0__BYPASS_MODE__SHIFT 0x4 |
31602 | #define CP_GFX_RS64_DC_APERTURE5_CNTL0__VMID_MASK 0x0000000FL |
31603 | #define CP_GFX_RS64_DC_APERTURE5_CNTL0__BYPASS_MODE_MASK 0x00000010L |
31604 | //CP_GFX_RS64_DC_APERTURE6_BASE0 |
31605 | #define CP_GFX_RS64_DC_APERTURE6_BASE0__BASE__SHIFT 0x0 |
31606 | #define CP_GFX_RS64_DC_APERTURE6_BASE0__BASE_MASK 0xFFFFFFFFL |
31607 | //CP_GFX_RS64_DC_APERTURE6_MASK0 |
31608 | #define CP_GFX_RS64_DC_APERTURE6_MASK0__MASK__SHIFT 0x0 |
31609 | #define CP_GFX_RS64_DC_APERTURE6_MASK0__MASK_MASK 0xFFFFFFFFL |
31610 | //CP_GFX_RS64_DC_APERTURE6_CNTL0 |
31611 | #define CP_GFX_RS64_DC_APERTURE6_CNTL0__VMID__SHIFT 0x0 |
31612 | #define CP_GFX_RS64_DC_APERTURE6_CNTL0__BYPASS_MODE__SHIFT 0x4 |
31613 | #define CP_GFX_RS64_DC_APERTURE6_CNTL0__VMID_MASK 0x0000000FL |
31614 | #define CP_GFX_RS64_DC_APERTURE6_CNTL0__BYPASS_MODE_MASK 0x00000010L |
31615 | //CP_GFX_RS64_DC_APERTURE7_BASE0 |
31616 | #define CP_GFX_RS64_DC_APERTURE7_BASE0__BASE__SHIFT 0x0 |
31617 | #define CP_GFX_RS64_DC_APERTURE7_BASE0__BASE_MASK 0xFFFFFFFFL |
31618 | //CP_GFX_RS64_DC_APERTURE7_MASK0 |
31619 | #define CP_GFX_RS64_DC_APERTURE7_MASK0__MASK__SHIFT 0x0 |
31620 | #define CP_GFX_RS64_DC_APERTURE7_MASK0__MASK_MASK 0xFFFFFFFFL |
31621 | //CP_GFX_RS64_DC_APERTURE7_CNTL0 |
31622 | #define CP_GFX_RS64_DC_APERTURE7_CNTL0__VMID__SHIFT 0x0 |
31623 | #define CP_GFX_RS64_DC_APERTURE7_CNTL0__BYPASS_MODE__SHIFT 0x4 |
31624 | #define CP_GFX_RS64_DC_APERTURE7_CNTL0__VMID_MASK 0x0000000FL |
31625 | #define CP_GFX_RS64_DC_APERTURE7_CNTL0__BYPASS_MODE_MASK 0x00000010L |
31626 | //CP_GFX_RS64_DC_APERTURE8_BASE0 |
31627 | #define CP_GFX_RS64_DC_APERTURE8_BASE0__BASE__SHIFT 0x0 |
31628 | #define CP_GFX_RS64_DC_APERTURE8_BASE0__BASE_MASK 0xFFFFFFFFL |
31629 | //CP_GFX_RS64_DC_APERTURE8_MASK0 |
31630 | #define CP_GFX_RS64_DC_APERTURE8_MASK0__MASK__SHIFT 0x0 |
31631 | #define CP_GFX_RS64_DC_APERTURE8_MASK0__MASK_MASK 0xFFFFFFFFL |
31632 | //CP_GFX_RS64_DC_APERTURE8_CNTL0 |
31633 | #define CP_GFX_RS64_DC_APERTURE8_CNTL0__VMID__SHIFT 0x0 |
31634 | #define CP_GFX_RS64_DC_APERTURE8_CNTL0__BYPASS_MODE__SHIFT 0x4 |
31635 | #define CP_GFX_RS64_DC_APERTURE8_CNTL0__VMID_MASK 0x0000000FL |
31636 | #define CP_GFX_RS64_DC_APERTURE8_CNTL0__BYPASS_MODE_MASK 0x00000010L |
31637 | //CP_GFX_RS64_DC_APERTURE9_BASE0 |
31638 | #define CP_GFX_RS64_DC_APERTURE9_BASE0__BASE__SHIFT 0x0 |
31639 | #define CP_GFX_RS64_DC_APERTURE9_BASE0__BASE_MASK 0xFFFFFFFFL |
31640 | //CP_GFX_RS64_DC_APERTURE9_MASK0 |
31641 | #define CP_GFX_RS64_DC_APERTURE9_MASK0__MASK__SHIFT 0x0 |
31642 | #define CP_GFX_RS64_DC_APERTURE9_MASK0__MASK_MASK 0xFFFFFFFFL |
31643 | //CP_GFX_RS64_DC_APERTURE9_CNTL0 |
31644 | #define CP_GFX_RS64_DC_APERTURE9_CNTL0__VMID__SHIFT 0x0 |
31645 | #define CP_GFX_RS64_DC_APERTURE9_CNTL0__BYPASS_MODE__SHIFT 0x4 |
31646 | #define CP_GFX_RS64_DC_APERTURE9_CNTL0__VMID_MASK 0x0000000FL |
31647 | #define CP_GFX_RS64_DC_APERTURE9_CNTL0__BYPASS_MODE_MASK 0x00000010L |
31648 | //CP_GFX_RS64_DC_APERTURE10_BASE0 |
31649 | #define CP_GFX_RS64_DC_APERTURE10_BASE0__BASE__SHIFT 0x0 |
31650 | #define CP_GFX_RS64_DC_APERTURE10_BASE0__BASE_MASK 0xFFFFFFFFL |
31651 | //CP_GFX_RS64_DC_APERTURE10_MASK0 |
31652 | #define CP_GFX_RS64_DC_APERTURE10_MASK0__MASK__SHIFT 0x0 |
31653 | #define CP_GFX_RS64_DC_APERTURE10_MASK0__MASK_MASK 0xFFFFFFFFL |
31654 | //CP_GFX_RS64_DC_APERTURE10_CNTL0 |
31655 | #define CP_GFX_RS64_DC_APERTURE10_CNTL0__VMID__SHIFT 0x0 |
31656 | #define CP_GFX_RS64_DC_APERTURE10_CNTL0__BYPASS_MODE__SHIFT 0x4 |
31657 | #define CP_GFX_RS64_DC_APERTURE10_CNTL0__VMID_MASK 0x0000000FL |
31658 | #define CP_GFX_RS64_DC_APERTURE10_CNTL0__BYPASS_MODE_MASK 0x00000010L |
31659 | //CP_GFX_RS64_DC_APERTURE11_BASE0 |
31660 | #define CP_GFX_RS64_DC_APERTURE11_BASE0__BASE__SHIFT 0x0 |
31661 | #define CP_GFX_RS64_DC_APERTURE11_BASE0__BASE_MASK 0xFFFFFFFFL |
31662 | //CP_GFX_RS64_DC_APERTURE11_MASK0 |
31663 | #define CP_GFX_RS64_DC_APERTURE11_MASK0__MASK__SHIFT 0x0 |
31664 | #define CP_GFX_RS64_DC_APERTURE11_MASK0__MASK_MASK 0xFFFFFFFFL |
31665 | //CP_GFX_RS64_DC_APERTURE11_CNTL0 |
31666 | #define CP_GFX_RS64_DC_APERTURE11_CNTL0__VMID__SHIFT 0x0 |
31667 | #define CP_GFX_RS64_DC_APERTURE11_CNTL0__BYPASS_MODE__SHIFT 0x4 |
31668 | #define CP_GFX_RS64_DC_APERTURE11_CNTL0__VMID_MASK 0x0000000FL |
31669 | #define CP_GFX_RS64_DC_APERTURE11_CNTL0__BYPASS_MODE_MASK 0x00000010L |
31670 | //CP_GFX_RS64_DC_APERTURE12_BASE0 |
31671 | #define CP_GFX_RS64_DC_APERTURE12_BASE0__BASE__SHIFT 0x0 |
31672 | #define CP_GFX_RS64_DC_APERTURE12_BASE0__BASE_MASK 0xFFFFFFFFL |
31673 | //CP_GFX_RS64_DC_APERTURE12_MASK0 |
31674 | #define CP_GFX_RS64_DC_APERTURE12_MASK0__MASK__SHIFT 0x0 |
31675 | #define CP_GFX_RS64_DC_APERTURE12_MASK0__MASK_MASK 0xFFFFFFFFL |
31676 | //CP_GFX_RS64_DC_APERTURE12_CNTL0 |
31677 | #define CP_GFX_RS64_DC_APERTURE12_CNTL0__VMID__SHIFT 0x0 |
31678 | #define CP_GFX_RS64_DC_APERTURE12_CNTL0__BYPASS_MODE__SHIFT 0x4 |
31679 | #define CP_GFX_RS64_DC_APERTURE12_CNTL0__VMID_MASK 0x0000000FL |
31680 | #define CP_GFX_RS64_DC_APERTURE12_CNTL0__BYPASS_MODE_MASK 0x00000010L |
31681 | //CP_GFX_RS64_DC_APERTURE13_BASE0 |
31682 | #define CP_GFX_RS64_DC_APERTURE13_BASE0__BASE__SHIFT 0x0 |
31683 | #define CP_GFX_RS64_DC_APERTURE13_BASE0__BASE_MASK 0xFFFFFFFFL |
31684 | //CP_GFX_RS64_DC_APERTURE13_MASK0 |
31685 | #define CP_GFX_RS64_DC_APERTURE13_MASK0__MASK__SHIFT 0x0 |
31686 | #define CP_GFX_RS64_DC_APERTURE13_MASK0__MASK_MASK 0xFFFFFFFFL |
31687 | //CP_GFX_RS64_DC_APERTURE13_CNTL0 |
31688 | #define CP_GFX_RS64_DC_APERTURE13_CNTL0__VMID__SHIFT 0x0 |
31689 | #define CP_GFX_RS64_DC_APERTURE13_CNTL0__BYPASS_MODE__SHIFT 0x4 |
31690 | #define CP_GFX_RS64_DC_APERTURE13_CNTL0__VMID_MASK 0x0000000FL |
31691 | #define CP_GFX_RS64_DC_APERTURE13_CNTL0__BYPASS_MODE_MASK 0x00000010L |
31692 | //CP_GFX_RS64_DC_APERTURE14_BASE0 |
31693 | #define CP_GFX_RS64_DC_APERTURE14_BASE0__BASE__SHIFT 0x0 |
31694 | #define CP_GFX_RS64_DC_APERTURE14_BASE0__BASE_MASK 0xFFFFFFFFL |
31695 | //CP_GFX_RS64_DC_APERTURE14_MASK0 |
31696 | #define CP_GFX_RS64_DC_APERTURE14_MASK0__MASK__SHIFT 0x0 |
31697 | #define CP_GFX_RS64_DC_APERTURE14_MASK0__MASK_MASK 0xFFFFFFFFL |
31698 | //CP_GFX_RS64_DC_APERTURE14_CNTL0 |
31699 | #define CP_GFX_RS64_DC_APERTURE14_CNTL0__VMID__SHIFT 0x0 |
31700 | #define CP_GFX_RS64_DC_APERTURE14_CNTL0__BYPASS_MODE__SHIFT 0x4 |
31701 | #define CP_GFX_RS64_DC_APERTURE14_CNTL0__VMID_MASK 0x0000000FL |
31702 | #define CP_GFX_RS64_DC_APERTURE14_CNTL0__BYPASS_MODE_MASK 0x00000010L |
31703 | //CP_GFX_RS64_DC_APERTURE15_BASE0 |
31704 | #define CP_GFX_RS64_DC_APERTURE15_BASE0__BASE__SHIFT 0x0 |
31705 | #define CP_GFX_RS64_DC_APERTURE15_BASE0__BASE_MASK 0xFFFFFFFFL |
31706 | //CP_GFX_RS64_DC_APERTURE15_MASK0 |
31707 | #define CP_GFX_RS64_DC_APERTURE15_MASK0__MASK__SHIFT 0x0 |
31708 | #define CP_GFX_RS64_DC_APERTURE15_MASK0__MASK_MASK 0xFFFFFFFFL |
31709 | //CP_GFX_RS64_DC_APERTURE15_CNTL0 |
31710 | #define CP_GFX_RS64_DC_APERTURE15_CNTL0__VMID__SHIFT 0x0 |
31711 | #define CP_GFX_RS64_DC_APERTURE15_CNTL0__BYPASS_MODE__SHIFT 0x4 |
31712 | #define CP_GFX_RS64_DC_APERTURE15_CNTL0__VMID_MASK 0x0000000FL |
31713 | #define CP_GFX_RS64_DC_APERTURE15_CNTL0__BYPASS_MODE_MASK 0x00000010L |
31714 | //CP_GFX_RS64_DC_APERTURE0_BASE1 |
31715 | #define CP_GFX_RS64_DC_APERTURE0_BASE1__BASE__SHIFT 0x0 |
31716 | #define CP_GFX_RS64_DC_APERTURE0_BASE1__BASE_MASK 0xFFFFFFFFL |
31717 | //CP_GFX_RS64_DC_APERTURE0_MASK1 |
31718 | #define CP_GFX_RS64_DC_APERTURE0_MASK1__MASK__SHIFT 0x0 |
31719 | #define CP_GFX_RS64_DC_APERTURE0_MASK1__MASK_MASK 0xFFFFFFFFL |
31720 | //CP_GFX_RS64_DC_APERTURE0_CNTL1 |
31721 | #define CP_GFX_RS64_DC_APERTURE0_CNTL1__VMID__SHIFT 0x0 |
31722 | #define CP_GFX_RS64_DC_APERTURE0_CNTL1__BYPASS_MODE__SHIFT 0x4 |
31723 | #define CP_GFX_RS64_DC_APERTURE0_CNTL1__VMID_MASK 0x0000000FL |
31724 | #define CP_GFX_RS64_DC_APERTURE0_CNTL1__BYPASS_MODE_MASK 0x00000010L |
31725 | //CP_GFX_RS64_DC_APERTURE1_BASE1 |
31726 | #define CP_GFX_RS64_DC_APERTURE1_BASE1__BASE__SHIFT 0x0 |
31727 | #define CP_GFX_RS64_DC_APERTURE1_BASE1__BASE_MASK 0xFFFFFFFFL |
31728 | //CP_GFX_RS64_DC_APERTURE1_MASK1 |
31729 | #define CP_GFX_RS64_DC_APERTURE1_MASK1__MASK__SHIFT 0x0 |
31730 | #define CP_GFX_RS64_DC_APERTURE1_MASK1__MASK_MASK 0xFFFFFFFFL |
31731 | //CP_GFX_RS64_DC_APERTURE1_CNTL1 |
31732 | #define CP_GFX_RS64_DC_APERTURE1_CNTL1__VMID__SHIFT 0x0 |
31733 | #define CP_GFX_RS64_DC_APERTURE1_CNTL1__BYPASS_MODE__SHIFT 0x4 |
31734 | #define CP_GFX_RS64_DC_APERTURE1_CNTL1__VMID_MASK 0x0000000FL |
31735 | #define CP_GFX_RS64_DC_APERTURE1_CNTL1__BYPASS_MODE_MASK 0x00000010L |
31736 | //CP_GFX_RS64_DC_APERTURE2_BASE1 |
31737 | #define CP_GFX_RS64_DC_APERTURE2_BASE1__BASE__SHIFT 0x0 |
31738 | #define CP_GFX_RS64_DC_APERTURE2_BASE1__BASE_MASK 0xFFFFFFFFL |
31739 | //CP_GFX_RS64_DC_APERTURE2_MASK1 |
31740 | #define CP_GFX_RS64_DC_APERTURE2_MASK1__MASK__SHIFT 0x0 |
31741 | #define CP_GFX_RS64_DC_APERTURE2_MASK1__MASK_MASK 0xFFFFFFFFL |
31742 | //CP_GFX_RS64_DC_APERTURE2_CNTL1 |
31743 | #define CP_GFX_RS64_DC_APERTURE2_CNTL1__VMID__SHIFT 0x0 |
31744 | #define CP_GFX_RS64_DC_APERTURE2_CNTL1__BYPASS_MODE__SHIFT 0x4 |
31745 | #define CP_GFX_RS64_DC_APERTURE2_CNTL1__VMID_MASK 0x0000000FL |
31746 | #define CP_GFX_RS64_DC_APERTURE2_CNTL1__BYPASS_MODE_MASK 0x00000010L |
31747 | //CP_GFX_RS64_DC_APERTURE3_BASE1 |
31748 | #define CP_GFX_RS64_DC_APERTURE3_BASE1__BASE__SHIFT 0x0 |
31749 | #define CP_GFX_RS64_DC_APERTURE3_BASE1__BASE_MASK 0xFFFFFFFFL |
31750 | //CP_GFX_RS64_DC_APERTURE3_MASK1 |
31751 | #define CP_GFX_RS64_DC_APERTURE3_MASK1__MASK__SHIFT 0x0 |
31752 | #define CP_GFX_RS64_DC_APERTURE3_MASK1__MASK_MASK 0xFFFFFFFFL |
31753 | //CP_GFX_RS64_DC_APERTURE3_CNTL1 |
31754 | #define CP_GFX_RS64_DC_APERTURE3_CNTL1__VMID__SHIFT 0x0 |
31755 | #define CP_GFX_RS64_DC_APERTURE3_CNTL1__BYPASS_MODE__SHIFT 0x4 |
31756 | #define CP_GFX_RS64_DC_APERTURE3_CNTL1__VMID_MASK 0x0000000FL |
31757 | #define CP_GFX_RS64_DC_APERTURE3_CNTL1__BYPASS_MODE_MASK 0x00000010L |
31758 | //CP_GFX_RS64_DC_APERTURE4_BASE1 |
31759 | #define CP_GFX_RS64_DC_APERTURE4_BASE1__BASE__SHIFT 0x0 |
31760 | #define CP_GFX_RS64_DC_APERTURE4_BASE1__BASE_MASK 0xFFFFFFFFL |
31761 | //CP_GFX_RS64_DC_APERTURE4_MASK1 |
31762 | #define CP_GFX_RS64_DC_APERTURE4_MASK1__MASK__SHIFT 0x0 |
31763 | #define CP_GFX_RS64_DC_APERTURE4_MASK1__MASK_MASK 0xFFFFFFFFL |
31764 | //CP_GFX_RS64_DC_APERTURE4_CNTL1 |
31765 | #define CP_GFX_RS64_DC_APERTURE4_CNTL1__VMID__SHIFT 0x0 |
31766 | #define CP_GFX_RS64_DC_APERTURE4_CNTL1__BYPASS_MODE__SHIFT 0x4 |
31767 | #define CP_GFX_RS64_DC_APERTURE4_CNTL1__VMID_MASK 0x0000000FL |
31768 | #define CP_GFX_RS64_DC_APERTURE4_CNTL1__BYPASS_MODE_MASK 0x00000010L |
31769 | //CP_GFX_RS64_DC_APERTURE5_BASE1 |
31770 | #define CP_GFX_RS64_DC_APERTURE5_BASE1__BASE__SHIFT 0x0 |
31771 | #define CP_GFX_RS64_DC_APERTURE5_BASE1__BASE_MASK 0xFFFFFFFFL |
31772 | //CP_GFX_RS64_DC_APERTURE5_MASK1 |
31773 | #define CP_GFX_RS64_DC_APERTURE5_MASK1__MASK__SHIFT 0x0 |
31774 | #define CP_GFX_RS64_DC_APERTURE5_MASK1__MASK_MASK 0xFFFFFFFFL |
31775 | //CP_GFX_RS64_DC_APERTURE5_CNTL1 |
31776 | #define CP_GFX_RS64_DC_APERTURE5_CNTL1__VMID__SHIFT 0x0 |
31777 | #define CP_GFX_RS64_DC_APERTURE5_CNTL1__BYPASS_MODE__SHIFT 0x4 |
31778 | #define CP_GFX_RS64_DC_APERTURE5_CNTL1__VMID_MASK 0x0000000FL |
31779 | #define CP_GFX_RS64_DC_APERTURE5_CNTL1__BYPASS_MODE_MASK 0x00000010L |
31780 | //CP_GFX_RS64_DC_APERTURE6_BASE1 |
31781 | #define CP_GFX_RS64_DC_APERTURE6_BASE1__BASE__SHIFT 0x0 |
31782 | #define CP_GFX_RS64_DC_APERTURE6_BASE1__BASE_MASK 0xFFFFFFFFL |
31783 | //CP_GFX_RS64_DC_APERTURE6_MASK1 |
31784 | #define CP_GFX_RS64_DC_APERTURE6_MASK1__MASK__SHIFT 0x0 |
31785 | #define CP_GFX_RS64_DC_APERTURE6_MASK1__MASK_MASK 0xFFFFFFFFL |
31786 | //CP_GFX_RS64_DC_APERTURE6_CNTL1 |
31787 | #define CP_GFX_RS64_DC_APERTURE6_CNTL1__VMID__SHIFT 0x0 |
31788 | #define CP_GFX_RS64_DC_APERTURE6_CNTL1__BYPASS_MODE__SHIFT 0x4 |
31789 | #define CP_GFX_RS64_DC_APERTURE6_CNTL1__VMID_MASK 0x0000000FL |
31790 | #define CP_GFX_RS64_DC_APERTURE6_CNTL1__BYPASS_MODE_MASK 0x00000010L |
31791 | //CP_GFX_RS64_DC_APERTURE7_BASE1 |
31792 | #define CP_GFX_RS64_DC_APERTURE7_BASE1__BASE__SHIFT 0x0 |
31793 | #define CP_GFX_RS64_DC_APERTURE7_BASE1__BASE_MASK 0xFFFFFFFFL |
31794 | //CP_GFX_RS64_DC_APERTURE7_MASK1 |
31795 | #define CP_GFX_RS64_DC_APERTURE7_MASK1__MASK__SHIFT 0x0 |
31796 | #define CP_GFX_RS64_DC_APERTURE7_MASK1__MASK_MASK 0xFFFFFFFFL |
31797 | //CP_GFX_RS64_DC_APERTURE7_CNTL1 |
31798 | #define CP_GFX_RS64_DC_APERTURE7_CNTL1__VMID__SHIFT 0x0 |
31799 | #define CP_GFX_RS64_DC_APERTURE7_CNTL1__BYPASS_MODE__SHIFT 0x4 |
31800 | #define CP_GFX_RS64_DC_APERTURE7_CNTL1__VMID_MASK 0x0000000FL |
31801 | #define CP_GFX_RS64_DC_APERTURE7_CNTL1__BYPASS_MODE_MASK 0x00000010L |
31802 | //CP_GFX_RS64_DC_APERTURE8_BASE1 |
31803 | #define CP_GFX_RS64_DC_APERTURE8_BASE1__BASE__SHIFT 0x0 |
31804 | #define CP_GFX_RS64_DC_APERTURE8_BASE1__BASE_MASK 0xFFFFFFFFL |
31805 | //CP_GFX_RS64_DC_APERTURE8_MASK1 |
31806 | #define CP_GFX_RS64_DC_APERTURE8_MASK1__MASK__SHIFT 0x0 |
31807 | #define CP_GFX_RS64_DC_APERTURE8_MASK1__MASK_MASK 0xFFFFFFFFL |
31808 | //CP_GFX_RS64_DC_APERTURE8_CNTL1 |
31809 | #define CP_GFX_RS64_DC_APERTURE8_CNTL1__VMID__SHIFT 0x0 |
31810 | #define CP_GFX_RS64_DC_APERTURE8_CNTL1__BYPASS_MODE__SHIFT 0x4 |
31811 | #define CP_GFX_RS64_DC_APERTURE8_CNTL1__VMID_MASK 0x0000000FL |
31812 | #define CP_GFX_RS64_DC_APERTURE8_CNTL1__BYPASS_MODE_MASK 0x00000010L |
31813 | //CP_GFX_RS64_DC_APERTURE9_BASE1 |
31814 | #define CP_GFX_RS64_DC_APERTURE9_BASE1__BASE__SHIFT 0x0 |
31815 | #define CP_GFX_RS64_DC_APERTURE9_BASE1__BASE_MASK 0xFFFFFFFFL |
31816 | //CP_GFX_RS64_DC_APERTURE9_MASK1 |
31817 | #define CP_GFX_RS64_DC_APERTURE9_MASK1__MASK__SHIFT 0x0 |
31818 | #define CP_GFX_RS64_DC_APERTURE9_MASK1__MASK_MASK 0xFFFFFFFFL |
31819 | //CP_GFX_RS64_DC_APERTURE9_CNTL1 |
31820 | #define CP_GFX_RS64_DC_APERTURE9_CNTL1__VMID__SHIFT 0x0 |
31821 | #define CP_GFX_RS64_DC_APERTURE9_CNTL1__BYPASS_MODE__SHIFT 0x4 |
31822 | #define CP_GFX_RS64_DC_APERTURE9_CNTL1__VMID_MASK 0x0000000FL |
31823 | #define CP_GFX_RS64_DC_APERTURE9_CNTL1__BYPASS_MODE_MASK 0x00000010L |
31824 | //CP_GFX_RS64_DC_APERTURE10_BASE1 |
31825 | #define CP_GFX_RS64_DC_APERTURE10_BASE1__BASE__SHIFT 0x0 |
31826 | #define CP_GFX_RS64_DC_APERTURE10_BASE1__BASE_MASK 0xFFFFFFFFL |
31827 | //CP_GFX_RS64_DC_APERTURE10_MASK1 |
31828 | #define CP_GFX_RS64_DC_APERTURE10_MASK1__MASK__SHIFT 0x0 |
31829 | #define CP_GFX_RS64_DC_APERTURE10_MASK1__MASK_MASK 0xFFFFFFFFL |
31830 | //CP_GFX_RS64_DC_APERTURE10_CNTL1 |
31831 | #define CP_GFX_RS64_DC_APERTURE10_CNTL1__VMID__SHIFT 0x0 |
31832 | #define CP_GFX_RS64_DC_APERTURE10_CNTL1__BYPASS_MODE__SHIFT 0x4 |
31833 | #define CP_GFX_RS64_DC_APERTURE10_CNTL1__VMID_MASK 0x0000000FL |
31834 | #define CP_GFX_RS64_DC_APERTURE10_CNTL1__BYPASS_MODE_MASK 0x00000010L |
31835 | //CP_GFX_RS64_DC_APERTURE11_BASE1 |
31836 | #define CP_GFX_RS64_DC_APERTURE11_BASE1__BASE__SHIFT 0x0 |
31837 | #define CP_GFX_RS64_DC_APERTURE11_BASE1__BASE_MASK 0xFFFFFFFFL |
31838 | //CP_GFX_RS64_DC_APERTURE11_MASK1 |
31839 | #define CP_GFX_RS64_DC_APERTURE11_MASK1__MASK__SHIFT 0x0 |
31840 | #define CP_GFX_RS64_DC_APERTURE11_MASK1__MASK_MASK 0xFFFFFFFFL |
31841 | //CP_GFX_RS64_DC_APERTURE11_CNTL1 |
31842 | #define CP_GFX_RS64_DC_APERTURE11_CNTL1__VMID__SHIFT 0x0 |
31843 | #define CP_GFX_RS64_DC_APERTURE11_CNTL1__BYPASS_MODE__SHIFT 0x4 |
31844 | #define CP_GFX_RS64_DC_APERTURE11_CNTL1__VMID_MASK 0x0000000FL |
31845 | #define CP_GFX_RS64_DC_APERTURE11_CNTL1__BYPASS_MODE_MASK 0x00000010L |
31846 | //CP_GFX_RS64_DC_APERTURE12_BASE1 |
31847 | #define CP_GFX_RS64_DC_APERTURE12_BASE1__BASE__SHIFT 0x0 |
31848 | #define CP_GFX_RS64_DC_APERTURE12_BASE1__BASE_MASK 0xFFFFFFFFL |
31849 | //CP_GFX_RS64_DC_APERTURE12_MASK1 |
31850 | #define CP_GFX_RS64_DC_APERTURE12_MASK1__MASK__SHIFT 0x0 |
31851 | #define CP_GFX_RS64_DC_APERTURE12_MASK1__MASK_MASK 0xFFFFFFFFL |
31852 | //CP_GFX_RS64_DC_APERTURE12_CNTL1 |
31853 | #define CP_GFX_RS64_DC_APERTURE12_CNTL1__VMID__SHIFT 0x0 |
31854 | #define CP_GFX_RS64_DC_APERTURE12_CNTL1__BYPASS_MODE__SHIFT 0x4 |
31855 | #define CP_GFX_RS64_DC_APERTURE12_CNTL1__VMID_MASK 0x0000000FL |
31856 | #define CP_GFX_RS64_DC_APERTURE12_CNTL1__BYPASS_MODE_MASK 0x00000010L |
31857 | //CP_GFX_RS64_DC_APERTURE13_BASE1 |
31858 | #define CP_GFX_RS64_DC_APERTURE13_BASE1__BASE__SHIFT 0x0 |
31859 | #define CP_GFX_RS64_DC_APERTURE13_BASE1__BASE_MASK 0xFFFFFFFFL |
31860 | //CP_GFX_RS64_DC_APERTURE13_MASK1 |
31861 | #define CP_GFX_RS64_DC_APERTURE13_MASK1__MASK__SHIFT 0x0 |
31862 | #define CP_GFX_RS64_DC_APERTURE13_MASK1__MASK_MASK 0xFFFFFFFFL |
31863 | //CP_GFX_RS64_DC_APERTURE13_CNTL1 |
31864 | #define CP_GFX_RS64_DC_APERTURE13_CNTL1__VMID__SHIFT 0x0 |
31865 | #define CP_GFX_RS64_DC_APERTURE13_CNTL1__BYPASS_MODE__SHIFT 0x4 |
31866 | #define CP_GFX_RS64_DC_APERTURE13_CNTL1__VMID_MASK 0x0000000FL |
31867 | #define CP_GFX_RS64_DC_APERTURE13_CNTL1__BYPASS_MODE_MASK 0x00000010L |
31868 | //CP_GFX_RS64_DC_APERTURE14_BASE1 |
31869 | #define CP_GFX_RS64_DC_APERTURE14_BASE1__BASE__SHIFT 0x0 |
31870 | #define CP_GFX_RS64_DC_APERTURE14_BASE1__BASE_MASK 0xFFFFFFFFL |
31871 | //CP_GFX_RS64_DC_APERTURE14_MASK1 |
31872 | #define CP_GFX_RS64_DC_APERTURE14_MASK1__MASK__SHIFT 0x0 |
31873 | #define CP_GFX_RS64_DC_APERTURE14_MASK1__MASK_MASK 0xFFFFFFFFL |
31874 | //CP_GFX_RS64_DC_APERTURE14_CNTL1 |
31875 | #define CP_GFX_RS64_DC_APERTURE14_CNTL1__VMID__SHIFT 0x0 |
31876 | #define CP_GFX_RS64_DC_APERTURE14_CNTL1__BYPASS_MODE__SHIFT 0x4 |
31877 | #define CP_GFX_RS64_DC_APERTURE14_CNTL1__VMID_MASK 0x0000000FL |
31878 | #define CP_GFX_RS64_DC_APERTURE14_CNTL1__BYPASS_MODE_MASK 0x00000010L |
31879 | //CP_GFX_RS64_DC_APERTURE15_BASE1 |
31880 | #define CP_GFX_RS64_DC_APERTURE15_BASE1__BASE__SHIFT 0x0 |
31881 | #define CP_GFX_RS64_DC_APERTURE15_BASE1__BASE_MASK 0xFFFFFFFFL |
31882 | //CP_GFX_RS64_DC_APERTURE15_MASK1 |
31883 | #define CP_GFX_RS64_DC_APERTURE15_MASK1__MASK__SHIFT 0x0 |
31884 | #define CP_GFX_RS64_DC_APERTURE15_MASK1__MASK_MASK 0xFFFFFFFFL |
31885 | //CP_GFX_RS64_DC_APERTURE15_CNTL1 |
31886 | #define CP_GFX_RS64_DC_APERTURE15_CNTL1__VMID__SHIFT 0x0 |
31887 | #define CP_GFX_RS64_DC_APERTURE15_CNTL1__BYPASS_MODE__SHIFT 0x4 |
31888 | #define CP_GFX_RS64_DC_APERTURE15_CNTL1__VMID_MASK 0x0000000FL |
31889 | #define CP_GFX_RS64_DC_APERTURE15_CNTL1__BYPASS_MODE_MASK 0x00000010L |
31890 | //CP_GFX_RS64_INTERRUPT1 |
31891 | #define CP_GFX_RS64_INTERRUPT1__ME_INT__SHIFT 0x0 |
31892 | #define CP_GFX_RS64_INTERRUPT1__ME_INT_MASK 0xFFFFFFFFL |
31893 | |
31894 | |
31895 | // addressBlock: gc_gl1dec |
31896 | //GL1_ARB_CTRL |
31897 | #define GL1_ARB_CTRL__NUM_MEM_PIPES__SHIFT 0x0 |
31898 | #define GL1_ARB_CTRL__FGCG_DISABLE__SHIFT 0x2 |
31899 | #define GL1_ARB_CTRL__PERF_CNTR_EN_OVERRIDE__SHIFT 0x3 |
31900 | #define GL1_ARB_CTRL__CHICKEN_BITS__SHIFT 0x4 |
31901 | #define GL1_ARB_CTRL__NUM_MEM_PIPES_MASK 0x00000003L |
31902 | #define GL1_ARB_CTRL__FGCG_DISABLE_MASK 0x00000004L |
31903 | #define GL1_ARB_CTRL__PERF_CNTR_EN_OVERRIDE_MASK 0x00000008L |
31904 | #define GL1_ARB_CTRL__CHICKEN_BITS_MASK 0x00000FF0L |
31905 | //GL1_DRAM_BURST_MASK |
31906 | #define GL1_DRAM_BURST_MASK__DRAM_BURST_ADDR_MASK__SHIFT 0x0 |
31907 | #define GL1_DRAM_BURST_MASK__DRAM_BURST_ADDR_MASK_MASK 0x000000FFL |
31908 | //GL1_ARB_STATUS |
31909 | #define GL1_ARB_STATUS__REQ_ARB_BUSY__SHIFT 0x0 |
31910 | #define GL1_ARB_STATUS__RET_ARB_BUSY__SHIFT 0x1 |
31911 | #define GL1_ARB_STATUS__REQ_ARB_BUSY_MASK 0x00000001L |
31912 | #define GL1_ARB_STATUS__RET_ARB_BUSY_MASK 0x00000002L |
31913 | //GL1_DRAM_BURST_CTRL |
31914 | #define GL1_DRAM_BURST_CTRL__MAX_DRAM_BURST__SHIFT 0x0 |
31915 | #define GL1_DRAM_BURST_CTRL__BURST_DISABLE__SHIFT 0x3 |
31916 | #define GL1_DRAM_BURST_CTRL__GATHER_64B_BURST_DISABLE__SHIFT 0x4 |
31917 | #define GL1_DRAM_BURST_CTRL__GATHER_32B_BURST_DISABLE__SHIFT 0x5 |
31918 | #define GL1_DRAM_BURST_CTRL__WRITE_BURSTABLE_STALL_DISABLE__SHIFT 0x8 |
31919 | #define GL1_DRAM_BURST_CTRL__MAX_DRAM_BURST_MASK 0x00000007L |
31920 | #define GL1_DRAM_BURST_CTRL__BURST_DISABLE_MASK 0x00000008L |
31921 | #define GL1_DRAM_BURST_CTRL__GATHER_64B_BURST_DISABLE_MASK 0x00000010L |
31922 | #define GL1_DRAM_BURST_CTRL__GATHER_32B_BURST_DISABLE_MASK 0x00000020L |
31923 | #define GL1_DRAM_BURST_CTRL__WRITE_BURSTABLE_STALL_DISABLE_MASK 0x00000100L |
31924 | //GL1I_GL1R_REP_FGCG_OVERRIDE |
31925 | #define GL1I_GL1R_REP_FGCG_OVERRIDE__GL1A_GL1IR_REP_FGCG_OVERRIDE__SHIFT 0x0 |
31926 | #define GL1I_GL1R_REP_FGCG_OVERRIDE__GL1A_GL1IW_REP_FGCG_OVERRIDE__SHIFT 0x1 |
31927 | #define GL1I_GL1R_REP_FGCG_OVERRIDE__GL1A_GL1R_SRC_REP_FGCG_OVERRIDE__SHIFT 0x2 |
31928 | #define GL1I_GL1R_REP_FGCG_OVERRIDE__GL1A_GL1R_RET_REP_FGCG_OVERRIDE__SHIFT 0x3 |
31929 | #define GL1I_GL1R_REP_FGCG_OVERRIDE__GL1A_GL1IR_REP_FGCG_OVERRIDE_MASK 0x00000001L |
31930 | #define GL1I_GL1R_REP_FGCG_OVERRIDE__GL1A_GL1IW_REP_FGCG_OVERRIDE_MASK 0x00000002L |
31931 | #define GL1I_GL1R_REP_FGCG_OVERRIDE__GL1A_GL1R_SRC_REP_FGCG_OVERRIDE_MASK 0x00000004L |
31932 | #define GL1I_GL1R_REP_FGCG_OVERRIDE__GL1A_GL1R_RET_REP_FGCG_OVERRIDE_MASK 0x00000008L |
31933 | //GL1C_CTRL |
31934 | #define GL1C_CTRL__FORCE_MISS__SHIFT 0x0 |
31935 | #define GL1C_CTRL__FORCE_HIT__SHIFT 0x1 |
31936 | #define GL1C_CTRL__NOFILL_32B__SHIFT 0x2 |
31937 | #define GL1C_CTRL__NOFILL_64B__SHIFT 0x3 |
31938 | #define GL1C_CTRL__LATENCY_FIFO_SIZE__SHIFT 0x4 |
31939 | #define GL1C_CTRL__ACK_QUEUE_DISABLE__SHIFT 0x8 |
31940 | #define GL1C_CTRL__RMI_META_READ_MISS_QUEUE_DISABLE__SHIFT 0x9 |
31941 | #define GL1C_CTRL__HIT_QUEUE_DISABLE__SHIFT 0xa |
31942 | #define GL1C_CTRL__GL2_REQ_CREDITS__SHIFT 0xb |
31943 | #define GL1C_CTRL__GL2_DATA_CREDITS__SHIFT 0x12 |
31944 | #define GL1C_CTRL__TO_L1_REPEATER_FGCG_DISABLE__SHIFT 0x19 |
31945 | #define GL1C_CTRL__TO_L2_REPEATER_FGCG_DISABLE__SHIFT 0x1a |
31946 | #define GL1C_CTRL__GCR_RSP_FGCG_DISABLE__SHIFT 0x1b |
31947 | #define GL1C_CTRL__DISABLE_HASH_TO_UPPER_16_SETS__SHIFT 0x1c |
31948 | #define GL1C_CTRL__DISABLE_PERF_WR_DATA_ALLOC_COUNT__SHIFT 0x1d |
31949 | #define GL1C_CTRL__DISABLE_PERF_SPLIT_EVICT_WRITE__SHIFT 0x1e |
31950 | #define GL1C_CTRL__FORCE_MISS_MASK 0x00000001L |
31951 | #define GL1C_CTRL__FORCE_HIT_MASK 0x00000002L |
31952 | #define GL1C_CTRL__NOFILL_32B_MASK 0x00000004L |
31953 | #define GL1C_CTRL__NOFILL_64B_MASK 0x00000008L |
31954 | #define GL1C_CTRL__LATENCY_FIFO_SIZE_MASK 0x000000F0L |
31955 | #define GL1C_CTRL__ACK_QUEUE_DISABLE_MASK 0x00000100L |
31956 | #define GL1C_CTRL__RMI_META_READ_MISS_QUEUE_DISABLE_MASK 0x00000200L |
31957 | #define GL1C_CTRL__HIT_QUEUE_DISABLE_MASK 0x00000400L |
31958 | #define GL1C_CTRL__GL2_REQ_CREDITS_MASK 0x0003F800L |
31959 | #define GL1C_CTRL__GL2_DATA_CREDITS_MASK 0x01FC0000L |
31960 | #define GL1C_CTRL__TO_L1_REPEATER_FGCG_DISABLE_MASK 0x02000000L |
31961 | #define GL1C_CTRL__TO_L2_REPEATER_FGCG_DISABLE_MASK 0x04000000L |
31962 | #define GL1C_CTRL__GCR_RSP_FGCG_DISABLE_MASK 0x08000000L |
31963 | #define GL1C_CTRL__DISABLE_HASH_TO_UPPER_16_SETS_MASK 0x10000000L |
31964 | #define GL1C_CTRL__DISABLE_PERF_WR_DATA_ALLOC_COUNT_MASK 0x20000000L |
31965 | #define GL1C_CTRL__DISABLE_PERF_SPLIT_EVICT_WRITE_MASK 0x40000000L |
31966 | //GL1C_STATUS |
31967 | #define GL1C_STATUS__INPUT_BUFFER_VC0_FIFO_FULL__SHIFT 0x0 |
31968 | #define GL1C_STATUS__OUTPUT_FIFOS_BUSY__SHIFT 0x1 |
31969 | #define GL1C_STATUS__SRC_DATA_FIFO_VC0_FULL__SHIFT 0x2 |
31970 | #define GL1C_STATUS__GL2_REQ_VC0_STALL__SHIFT 0x3 |
31971 | #define GL1C_STATUS__GL2_DATA_VC0_STALL__SHIFT 0x4 |
31972 | #define GL1C_STATUS__GL2_REQ_VC1_STALL__SHIFT 0x5 |
31973 | #define GL1C_STATUS__GL2_DATA_VC1_STALL__SHIFT 0x6 |
31974 | #define GL1C_STATUS__INPUT_BUFFER_VC0_BUSY__SHIFT 0x7 |
31975 | #define GL1C_STATUS__SRC_DATA_FIFO_VC0_BUSY__SHIFT 0x8 |
31976 | #define GL1C_STATUS__GL2_RH_BUSY__SHIFT 0x9 |
31977 | #define GL1C_STATUS__NUM_REQ_PENDING_FROM_L2__SHIFT 0xa |
31978 | #define GL1C_STATUS__LATENCY_FIFO_FULL_STALL__SHIFT 0x14 |
31979 | #define GL1C_STATUS__TAG_STALL__SHIFT 0x15 |
31980 | #define GL1C_STATUS__TAG_BUSY__SHIFT 0x16 |
31981 | #define GL1C_STATUS__TAG_ACK_STALL__SHIFT 0x17 |
31982 | #define GL1C_STATUS__TAG_GCR_INV_STALL__SHIFT 0x18 |
31983 | #define GL1C_STATUS__TAG_NO_AVAILABLE_LINE_TO_EVICT_STALL__SHIFT 0x19 |
31984 | #define GL1C_STATUS__TAG_EVICT__SHIFT 0x1a |
31985 | #define GL1C_STATUS__TAG_REQUEST_STATE_OPERATION__SHIFT 0x1b |
31986 | #define GL1C_STATUS__TRACKER_LAST_SET_MATCHES_CURRENT_SET__SHIFT 0x1f |
31987 | #define GL1C_STATUS__INPUT_BUFFER_VC0_FIFO_FULL_MASK 0x00000001L |
31988 | #define GL1C_STATUS__OUTPUT_FIFOS_BUSY_MASK 0x00000002L |
31989 | #define GL1C_STATUS__SRC_DATA_FIFO_VC0_FULL_MASK 0x00000004L |
31990 | #define GL1C_STATUS__GL2_REQ_VC0_STALL_MASK 0x00000008L |
31991 | #define GL1C_STATUS__GL2_DATA_VC0_STALL_MASK 0x00000010L |
31992 | #define GL1C_STATUS__GL2_REQ_VC1_STALL_MASK 0x00000020L |
31993 | #define GL1C_STATUS__GL2_DATA_VC1_STALL_MASK 0x00000040L |
31994 | #define GL1C_STATUS__INPUT_BUFFER_VC0_BUSY_MASK 0x00000080L |
31995 | #define GL1C_STATUS__SRC_DATA_FIFO_VC0_BUSY_MASK 0x00000100L |
31996 | #define GL1C_STATUS__GL2_RH_BUSY_MASK 0x00000200L |
31997 | #define GL1C_STATUS__NUM_REQ_PENDING_FROM_L2_MASK 0x000FFC00L |
31998 | #define GL1C_STATUS__LATENCY_FIFO_FULL_STALL_MASK 0x00100000L |
31999 | #define GL1C_STATUS__TAG_STALL_MASK 0x00200000L |
32000 | #define GL1C_STATUS__TAG_BUSY_MASK 0x00400000L |
32001 | #define GL1C_STATUS__TAG_ACK_STALL_MASK 0x00800000L |
32002 | #define GL1C_STATUS__TAG_GCR_INV_STALL_MASK 0x01000000L |
32003 | #define GL1C_STATUS__TAG_NO_AVAILABLE_LINE_TO_EVICT_STALL_MASK 0x02000000L |
32004 | #define GL1C_STATUS__TAG_EVICT_MASK 0x04000000L |
32005 | #define GL1C_STATUS__TAG_REQUEST_STATE_OPERATION_MASK 0x78000000L |
32006 | #define GL1C_STATUS__TRACKER_LAST_SET_MATCHES_CURRENT_SET_MASK 0x80000000L |
32007 | //GL1C_UTCL0_CNTL2 |
32008 | #define GL1C_UTCL0_CNTL2__SPARE__SHIFT 0x0 |
32009 | #define GL1C_UTCL0_CNTL2__COMP_SYNC_DISABLE__SHIFT 0x8 |
32010 | #define GL1C_UTCL0_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9 |
32011 | #define GL1C_UTCL0_CNTL2__ANY_LINE_VALID__SHIFT 0xa |
32012 | #define GL1C_UTCL0_CNTL2__FORCE_SNOOP__SHIFT 0xe |
32013 | #define GL1C_UTCL0_CNTL2__DISABLE_BURST__SHIFT 0x11 |
32014 | #define GL1C_UTCL0_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a |
32015 | #define GL1C_UTCL0_CNTL2__FGCG_DISABLE__SHIFT 0x1e |
32016 | #define GL1C_UTCL0_CNTL2__BIG_PAGE_DISABLE__SHIFT 0x1f |
32017 | #define GL1C_UTCL0_CNTL2__SPARE_MASK 0x000000FFL |
32018 | #define GL1C_UTCL0_CNTL2__COMP_SYNC_DISABLE_MASK 0x00000100L |
32019 | #define GL1C_UTCL0_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L |
32020 | #define GL1C_UTCL0_CNTL2__ANY_LINE_VALID_MASK 0x00000400L |
32021 | #define GL1C_UTCL0_CNTL2__FORCE_SNOOP_MASK 0x00004000L |
32022 | #define GL1C_UTCL0_CNTL2__DISABLE_BURST_MASK 0x00020000L |
32023 | #define GL1C_UTCL0_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L |
32024 | #define GL1C_UTCL0_CNTL2__FGCG_DISABLE_MASK 0x40000000L |
32025 | #define GL1C_UTCL0_CNTL2__BIG_PAGE_DISABLE_MASK 0x80000000L |
32026 | //GL1C_UTCL0_STATUS |
32027 | #define GL1C_UTCL0_STATUS__FAULT_DETECTED__SHIFT 0x0 |
32028 | #define GL1C_UTCL0_STATUS__RETRY_DETECTED__SHIFT 0x1 |
32029 | #define GL1C_UTCL0_STATUS__PRT_DETECTED__SHIFT 0x2 |
32030 | #define GL1C_UTCL0_STATUS__FAULT_DETECTED_MASK 0x00000001L |
32031 | #define GL1C_UTCL0_STATUS__RETRY_DETECTED_MASK 0x00000002L |
32032 | #define GL1C_UTCL0_STATUS__PRT_DETECTED_MASK 0x00000004L |
32033 | //GL1C_UTCL0_RETRY |
32034 | #define GL1C_UTCL0_RETRY__INCR__SHIFT 0x0 |
32035 | #define GL1C_UTCL0_RETRY__COUNT__SHIFT 0x8 |
32036 | #define GL1C_UTCL0_RETRY__INCR_MASK 0x000000FFL |
32037 | #define GL1C_UTCL0_RETRY__COUNT_MASK 0x00000F00L |
32038 | //GL1C_CTRL2 |
32039 | #define GL1C_CTRL2__UTCL0_INFLIGHT_MAX__SHIFT 0x0 |
32040 | #define GL1C_CTRL2__UTCL0_SD_SIDEBAND_IF_DISABLE__SHIFT 0x8 |
32041 | #define GL1C_CTRL2__REDUCE_REQ_PROTECTION_LINE_LEVEL__SHIFT 0x9 |
32042 | #define GL1C_CTRL2__UTCL0_INFLIGHT_MAX_MASK 0x000000FFL |
32043 | #define GL1C_CTRL2__UTCL0_SD_SIDEBAND_IF_DISABLE_MASK 0x00000100L |
32044 | #define GL1C_CTRL2__REDUCE_REQ_PROTECTION_LINE_LEVEL_MASK 0x00003E00L |
32045 | |
32046 | |
32047 | // addressBlock: gc_chdec |
32048 | //CH_ARB_CTRL |
32049 | #define CH_ARB_CTRL__NUM_MEM_PIPES__SHIFT 0x0 |
32050 | #define CH_ARB_CTRL__UC_IO_WR_PATH__SHIFT 0x2 |
32051 | #define CH_ARB_CTRL__FGCG_DISABLE__SHIFT 0x3 |
32052 | #define CH_ARB_CTRL__PERF_CNTR_EN_OVERRIDE__SHIFT 0x4 |
32053 | #define CH_ARB_CTRL__CHICKEN_BITS__SHIFT 0x5 |
32054 | #define CH_ARB_CTRL__NUM_MEM_PIPES_MASK 0x00000003L |
32055 | #define CH_ARB_CTRL__UC_IO_WR_PATH_MASK 0x00000004L |
32056 | #define CH_ARB_CTRL__FGCG_DISABLE_MASK 0x00000008L |
32057 | #define CH_ARB_CTRL__PERF_CNTR_EN_OVERRIDE_MASK 0x00000010L |
32058 | #define CH_ARB_CTRL__CHICKEN_BITS_MASK 0x00001FE0L |
32059 | //CH_DRAM_BURST_MASK |
32060 | #define CH_DRAM_BURST_MASK__DRAM_BURST_ADDR_MASK__SHIFT 0x0 |
32061 | #define CH_DRAM_BURST_MASK__DRAM_BURST_ADDR_MASK_MASK 0x000000FFL |
32062 | //CH_ARB_STATUS |
32063 | #define CH_ARB_STATUS__REQ_ARB_BUSY__SHIFT 0x0 |
32064 | #define CH_ARB_STATUS__RET_ARB_BUSY__SHIFT 0x1 |
32065 | #define CH_ARB_STATUS__REQ_ARB_BUSY_MASK 0x00000001L |
32066 | #define CH_ARB_STATUS__RET_ARB_BUSY_MASK 0x00000002L |
32067 | //CH_DRAM_BURST_CTRL |
32068 | #define CH_DRAM_BURST_CTRL__MAX_DRAM_BURST__SHIFT 0x0 |
32069 | #define CH_DRAM_BURST_CTRL__BURST_DISABLE__SHIFT 0x3 |
32070 | #define CH_DRAM_BURST_CTRL__GATHER_64B_MEMORY_BURST_DISABLE__SHIFT 0x4 |
32071 | #define CH_DRAM_BURST_CTRL__GATHER_64B_IO_BURST_DISABLE__SHIFT 0x5 |
32072 | #define CH_DRAM_BURST_CTRL__GATHER_32B_MEMORY_BURST_DISABLE__SHIFT 0x6 |
32073 | #define CH_DRAM_BURST_CTRL__GATHER_32B_IO_BURST_DISABLE__SHIFT 0x7 |
32074 | #define CH_DRAM_BURST_CTRL__WRITE_BURSTABLE_STALL_DISABLE__SHIFT 0x8 |
32075 | #define CH_DRAM_BURST_CTRL__MAX_DRAM_BURST_MASK 0x00000007L |
32076 | #define CH_DRAM_BURST_CTRL__BURST_DISABLE_MASK 0x00000008L |
32077 | #define CH_DRAM_BURST_CTRL__GATHER_64B_MEMORY_BURST_DISABLE_MASK 0x00000010L |
32078 | #define CH_DRAM_BURST_CTRL__GATHER_64B_IO_BURST_DISABLE_MASK 0x00000020L |
32079 | #define CH_DRAM_BURST_CTRL__GATHER_32B_MEMORY_BURST_DISABLE_MASK 0x00000040L |
32080 | #define CH_DRAM_BURST_CTRL__GATHER_32B_IO_BURST_DISABLE_MASK 0x00000080L |
32081 | #define CH_DRAM_BURST_CTRL__WRITE_BURSTABLE_STALL_DISABLE_MASK 0x00000100L |
32082 | //CHA_CHC_CREDITS |
32083 | #define CHA_CHC_CREDITS__CHC_REQ_CREDITS__SHIFT 0x0 |
32084 | #define CHA_CHC_CREDITS__CHCG_REQ_CREDITS__SHIFT 0x8 |
32085 | #define CHA_CHC_CREDITS__CHC_REQ_CREDITS_MASK 0x000000FFL |
32086 | #define CHA_CHC_CREDITS__CHCG_REQ_CREDITS_MASK 0x0000FF00L |
32087 | //CHA_CLIENT_FREE_DELAY |
32088 | #define CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_0_FREE_DELAY__SHIFT 0x0 |
32089 | #define CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_1_FREE_DELAY__SHIFT 0x3 |
32090 | #define CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_2_FREE_DELAY__SHIFT 0x6 |
32091 | #define CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_3_FREE_DELAY__SHIFT 0x9 |
32092 | #define CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_4_FREE_DELAY__SHIFT 0xc |
32093 | #define CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_0_FREE_DELAY_MASK 0x00000007L |
32094 | #define CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_1_FREE_DELAY_MASK 0x00000038L |
32095 | #define CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_2_FREE_DELAY_MASK 0x000001C0L |
32096 | #define CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_3_FREE_DELAY_MASK 0x00000E00L |
32097 | #define CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_4_FREE_DELAY_MASK 0x00007000L |
32098 | //CHI_CHR_REP_FGCG_OVERRIDE |
32099 | #define CHI_CHR_REP_FGCG_OVERRIDE__CHA_CHIW_REP_FGCG_OVERRIDE__SHIFT 0x0 |
32100 | #define CHI_CHR_REP_FGCG_OVERRIDE__CHA_CHIR_REP_FGCG_OVERRIDE__SHIFT 0x1 |
32101 | #define CHI_CHR_REP_FGCG_OVERRIDE__CHA_CHR_SRC_REP_FGCG_OVERRIDE__SHIFT 0x2 |
32102 | #define CHI_CHR_REP_FGCG_OVERRIDE__CHA_CHR_RET_REP_FGCG_OVERRIDE__SHIFT 0x3 |
32103 | #define CHI_CHR_REP_FGCG_OVERRIDE__CHA_CHIW_REP_FGCG_OVERRIDE_MASK 0x00000001L |
32104 | #define CHI_CHR_REP_FGCG_OVERRIDE__CHA_CHIR_REP_FGCG_OVERRIDE_MASK 0x00000002L |
32105 | #define CHI_CHR_REP_FGCG_OVERRIDE__CHA_CHR_SRC_REP_FGCG_OVERRIDE_MASK 0x00000004L |
32106 | #define CHI_CHR_REP_FGCG_OVERRIDE__CHA_CHR_RET_REP_FGCG_OVERRIDE_MASK 0x00000008L |
32107 | //CH_VC5_ENABLE |
32108 | #define CH_VC5_ENABLE__UTCL2_VC5_ENABLE__SHIFT 0x1 |
32109 | #define CH_VC5_ENABLE__UTCL2_VC5_ENABLE_MASK 0x00000002L |
32110 | //CHC_CTRL |
32111 | #define CHC_CTRL__BUFFER_DEPTH_MAX__SHIFT 0x0 |
32112 | #define CHC_CTRL__GL2_REQ_CREDITS__SHIFT 0x4 |
32113 | #define CHC_CTRL__GL2_DATA_CREDITS__SHIFT 0xb |
32114 | #define CHC_CTRL__TO_L1_REPEATER_FGCG_DISABLE__SHIFT 0x12 |
32115 | #define CHC_CTRL__TO_L2_REPEATER_FGCG_DISABLE__SHIFT 0x13 |
32116 | #define CHC_CTRL__DISABLE_PERF_WR_DATA_ALLOC_COUNT__SHIFT 0x1d |
32117 | #define CHC_CTRL__BUFFER_DEPTH_MAX_MASK 0x0000000FL |
32118 | #define CHC_CTRL__GL2_REQ_CREDITS_MASK 0x000007F0L |
32119 | #define CHC_CTRL__GL2_DATA_CREDITS_MASK 0x0003F800L |
32120 | #define CHC_CTRL__TO_L1_REPEATER_FGCG_DISABLE_MASK 0x00040000L |
32121 | #define CHC_CTRL__TO_L2_REPEATER_FGCG_DISABLE_MASK 0x00080000L |
32122 | #define CHC_CTRL__DISABLE_PERF_WR_DATA_ALLOC_COUNT_MASK 0x20000000L |
32123 | //CHC_STATUS |
32124 | #define CHC_STATUS__INPUT_BUFFER_VC0_FIFO_FULL__SHIFT 0x0 |
32125 | #define CHC_STATUS__OUTPUT_FIFOS_BUSY__SHIFT 0x1 |
32126 | #define CHC_STATUS__SRC_DATA_FIFO_VC0_FULL__SHIFT 0x2 |
32127 | #define CHC_STATUS__GL2_REQ_VC0_STALL__SHIFT 0x3 |
32128 | #define CHC_STATUS__GL2_DATA_VC0_STALL__SHIFT 0x4 |
32129 | #define CHC_STATUS__GL2_REQ_VC1_STALL__SHIFT 0x5 |
32130 | #define CHC_STATUS__GL2_DATA_VC1_STALL__SHIFT 0x6 |
32131 | #define CHC_STATUS__INPUT_BUFFER_VC0_BUSY__SHIFT 0x7 |
32132 | #define CHC_STATUS__SRC_DATA_FIFO_VC0_BUSY__SHIFT 0x8 |
32133 | #define CHC_STATUS__GL2_RH_BUSY__SHIFT 0x9 |
32134 | #define CHC_STATUS__NUM_REQ_PENDING_FROM_L2__SHIFT 0xa |
32135 | #define CHC_STATUS__VIRTUAL_FIFO_FULL_STALL__SHIFT 0x14 |
32136 | #define CHC_STATUS__REQUEST_TRACKER_BUFFER_STALL__SHIFT 0x15 |
32137 | #define CHC_STATUS__REQUEST_TRACKER_BUSY__SHIFT 0x16 |
32138 | #define CHC_STATUS__BUFFER_FULL__SHIFT 0x17 |
32139 | #define CHC_STATUS__INPUT_BUFFER_VC0_FIFO_FULL_MASK 0x00000001L |
32140 | #define CHC_STATUS__OUTPUT_FIFOS_BUSY_MASK 0x00000002L |
32141 | #define CHC_STATUS__SRC_DATA_FIFO_VC0_FULL_MASK 0x00000004L |
32142 | #define CHC_STATUS__GL2_REQ_VC0_STALL_MASK 0x00000008L |
32143 | #define CHC_STATUS__GL2_DATA_VC0_STALL_MASK 0x00000010L |
32144 | #define CHC_STATUS__GL2_REQ_VC1_STALL_MASK 0x00000020L |
32145 | #define CHC_STATUS__GL2_DATA_VC1_STALL_MASK 0x00000040L |
32146 | #define CHC_STATUS__INPUT_BUFFER_VC0_BUSY_MASK 0x00000080L |
32147 | #define CHC_STATUS__SRC_DATA_FIFO_VC0_BUSY_MASK 0x00000100L |
32148 | #define CHC_STATUS__GL2_RH_BUSY_MASK 0x00000200L |
32149 | #define CHC_STATUS__NUM_REQ_PENDING_FROM_L2_MASK 0x000FFC00L |
32150 | #define CHC_STATUS__VIRTUAL_FIFO_FULL_STALL_MASK 0x00100000L |
32151 | #define CHC_STATUS__REQUEST_TRACKER_BUFFER_STALL_MASK 0x00200000L |
32152 | #define CHC_STATUS__REQUEST_TRACKER_BUSY_MASK 0x00400000L |
32153 | #define CHC_STATUS__BUFFER_FULL_MASK 0x00800000L |
32154 | //CHCG_CTRL |
32155 | #define CHCG_CTRL__BUFFER_DEPTH_MAX__SHIFT 0x0 |
32156 | #define CHCG_CTRL__VC0_BUFFER_DEPTH_MAX__SHIFT 0x4 |
32157 | #define CHCG_CTRL__GL2_REQ_CREDITS__SHIFT 0x8 |
32158 | #define CHCG_CTRL__GL2_DATA_CREDITS__SHIFT 0xf |
32159 | #define CHCG_CTRL__TO_L1_REPEATER_FGCG_DISABLE__SHIFT 0x16 |
32160 | #define CHCG_CTRL__TO_L2_REPEATER_FGCG_DISABLE__SHIFT 0x17 |
32161 | #define CHCG_CTRL__BUFFER_DEPTH_MAX_MASK 0x0000000FL |
32162 | #define CHCG_CTRL__VC0_BUFFER_DEPTH_MAX_MASK 0x000000F0L |
32163 | #define CHCG_CTRL__GL2_REQ_CREDITS_MASK 0x00007F00L |
32164 | #define CHCG_CTRL__GL2_DATA_CREDITS_MASK 0x003F8000L |
32165 | #define CHCG_CTRL__TO_L1_REPEATER_FGCG_DISABLE_MASK 0x00400000L |
32166 | #define CHCG_CTRL__TO_L2_REPEATER_FGCG_DISABLE_MASK 0x00800000L |
32167 | //CHCG_STATUS |
32168 | #define CHCG_STATUS__INPUT_BUFFER_VC0_FIFO_FULL__SHIFT 0x0 |
32169 | #define CHCG_STATUS__OUTPUT_FIFOS_BUSY__SHIFT 0x1 |
32170 | #define CHCG_STATUS__SRC_DATA_FIFO_VC0_FULL__SHIFT 0x2 |
32171 | #define CHCG_STATUS__GL2_REQ_VC0_STALL__SHIFT 0x3 |
32172 | #define CHCG_STATUS__GL2_DATA_VC0_STALL__SHIFT 0x4 |
32173 | #define CHCG_STATUS__GL2_REQ_VC1_STALL__SHIFT 0x5 |
32174 | #define CHCG_STATUS__GL2_DATA_VC1_STALL__SHIFT 0x6 |
32175 | #define CHCG_STATUS__INPUT_BUFFER_VC0_BUSY__SHIFT 0x7 |
32176 | #define CHCG_STATUS__SRC_DATA_FIFO_VC0_BUSY__SHIFT 0x8 |
32177 | #define CHCG_STATUS__GL2_RH_BUSY__SHIFT 0x9 |
32178 | #define CHCG_STATUS__NUM_REQ_PENDING_FROM_L2__SHIFT 0xa |
32179 | #define CHCG_STATUS__VIRTUAL_FIFO_FULL_STALL__SHIFT 0x14 |
32180 | #define CHCG_STATUS__REQUEST_TRACKER_BUFFER_STALL__SHIFT 0x15 |
32181 | #define CHCG_STATUS__REQUEST_TRACKER_BUSY__SHIFT 0x16 |
32182 | #define CHCG_STATUS__BUFFER_FULL__SHIFT 0x17 |
32183 | #define CHCG_STATUS__INPUT_BUFFER_VC1_BUSY__SHIFT 0x18 |
32184 | #define CHCG_STATUS__SRC_DATA_FIFO_VC1_BUSY__SHIFT 0x19 |
32185 | #define CHCG_STATUS__INPUT_BUFFER_VC1_FIFO_FULL__SHIFT 0x1a |
32186 | #define CHCG_STATUS__SRC_DATA_FIFO_VC1_FULL__SHIFT 0x1b |
32187 | #define CHCG_STATUS__INPUT_BUFFER_VC0_FIFO_FULL_MASK 0x00000001L |
32188 | #define CHCG_STATUS__OUTPUT_FIFOS_BUSY_MASK 0x00000002L |
32189 | #define CHCG_STATUS__SRC_DATA_FIFO_VC0_FULL_MASK 0x00000004L |
32190 | #define CHCG_STATUS__GL2_REQ_VC0_STALL_MASK 0x00000008L |
32191 | #define CHCG_STATUS__GL2_DATA_VC0_STALL_MASK 0x00000010L |
32192 | #define CHCG_STATUS__GL2_REQ_VC1_STALL_MASK 0x00000020L |
32193 | #define CHCG_STATUS__GL2_DATA_VC1_STALL_MASK 0x00000040L |
32194 | #define CHCG_STATUS__INPUT_BUFFER_VC0_BUSY_MASK 0x00000080L |
32195 | #define CHCG_STATUS__SRC_DATA_FIFO_VC0_BUSY_MASK 0x00000100L |
32196 | #define CHCG_STATUS__GL2_RH_BUSY_MASK 0x00000200L |
32197 | #define CHCG_STATUS__NUM_REQ_PENDING_FROM_L2_MASK 0x000FFC00L |
32198 | #define CHCG_STATUS__VIRTUAL_FIFO_FULL_STALL_MASK 0x00100000L |
32199 | #define CHCG_STATUS__REQUEST_TRACKER_BUFFER_STALL_MASK 0x00200000L |
32200 | #define CHCG_STATUS__REQUEST_TRACKER_BUSY_MASK 0x00400000L |
32201 | #define CHCG_STATUS__BUFFER_FULL_MASK 0x00800000L |
32202 | #define CHCG_STATUS__INPUT_BUFFER_VC1_BUSY_MASK 0x01000000L |
32203 | #define CHCG_STATUS__SRC_DATA_FIFO_VC1_BUSY_MASK 0x02000000L |
32204 | #define CHCG_STATUS__INPUT_BUFFER_VC1_FIFO_FULL_MASK 0x04000000L |
32205 | #define CHCG_STATUS__SRC_DATA_FIFO_VC1_FULL_MASK 0x08000000L |
32206 | |
32207 | |
32208 | // addressBlock: gc_gl2dec |
32209 | //GL2C_CTRL |
32210 | #define GL2C_CTRL__CACHE_SIZE__SHIFT 0x0 |
32211 | #define GL2C_CTRL__RATE__SHIFT 0x2 |
32212 | #define GL2C_CTRL__WRITEBACK_MARGIN__SHIFT 0x4 |
32213 | #define GL2C_CTRL__METADATA_LATENCY_FIFO_SIZE__SHIFT 0x8 |
32214 | #define GL2C_CTRL__SRC_FIFO_SIZE__SHIFT 0xc |
32215 | #define GL2C_CTRL__LATENCY_FIFO_SIZE__SHIFT 0x10 |
32216 | #define GL2C_CTRL__METADATA_TO_HI_PRIORITY__SHIFT 0x14 |
32217 | #define GL2C_CTRL__LINEAR_SET_HASH__SHIFT 0x15 |
32218 | #define GL2C_CTRL__FORCE_HIT_QUEUE_POP__SHIFT 0x16 |
32219 | #define GL2C_CTRL__MDC_SIZE__SHIFT 0x18 |
32220 | #define GL2C_CTRL__METADATA_TO_HIT_QUEUE__SHIFT 0x1a |
32221 | #define GL2C_CTRL__IGNORE_FULLY_WRITTEN__SHIFT 0x1b |
32222 | #define GL2C_CTRL__MDC_SIDEBAND_FIFO_SIZE__SHIFT 0x1c |
32223 | #define GL2C_CTRL__CACHE_SIZE_MASK 0x00000003L |
32224 | #define GL2C_CTRL__RATE_MASK 0x0000000CL |
32225 | #define GL2C_CTRL__WRITEBACK_MARGIN_MASK 0x000000F0L |
32226 | #define GL2C_CTRL__METADATA_LATENCY_FIFO_SIZE_MASK 0x00000F00L |
32227 | #define GL2C_CTRL__SRC_FIFO_SIZE_MASK 0x0000F000L |
32228 | #define GL2C_CTRL__LATENCY_FIFO_SIZE_MASK 0x000F0000L |
32229 | #define GL2C_CTRL__METADATA_TO_HI_PRIORITY_MASK 0x00100000L |
32230 | #define GL2C_CTRL__LINEAR_SET_HASH_MASK 0x00200000L |
32231 | #define GL2C_CTRL__FORCE_HIT_QUEUE_POP_MASK 0x00C00000L |
32232 | #define GL2C_CTRL__MDC_SIZE_MASK 0x03000000L |
32233 | #define GL2C_CTRL__METADATA_TO_HIT_QUEUE_MASK 0x04000000L |
32234 | #define GL2C_CTRL__IGNORE_FULLY_WRITTEN_MASK 0x08000000L |
32235 | #define GL2C_CTRL__MDC_SIDEBAND_FIFO_SIZE_MASK 0xF0000000L |
32236 | //GL2C_CTRL2 |
32237 | #define GL2C_CTRL2__PROBE_FIFO_SIZE__SHIFT 0x0 |
32238 | #define GL2C_CTRL2__ADDR_MATCH_DISABLE__SHIFT 0x4 |
32239 | #define GL2C_CTRL2__FILL_SIZE_32__SHIFT 0x5 |
32240 | #define GL2C_CTRL2__RB_TO_HI_PRIORITY__SHIFT 0x6 |
32241 | #define GL2C_CTRL2__HIT_UNDER_MISS_DISABLE__SHIFT 0x7 |
32242 | #define GL2C_CTRL2__RO_DISABLE__SHIFT 0x8 |
32243 | #define GL2C_CTRL2__FORCE_MDC_INV__SHIFT 0x9 |
32244 | #define GL2C_CTRL2__GCR_ARB_CTRL__SHIFT 0xa |
32245 | #define GL2C_CTRL2__GCR_ALL_SET__SHIFT 0xd |
32246 | #define GL2C_CTRL2__FILL_SIZE_64__SHIFT 0x11 |
32247 | #define GL2C_CTRL2__USE_EA_EARLYWRRET_ON_WRITEBACK__SHIFT 0x12 |
32248 | #define GL2C_CTRL2__WRITEBACK_ALL_WAIT_FOR_ALL_EA_WRITE_COMPLETE__SHIFT 0x13 |
32249 | #define GL2C_CTRL2__METADATA_VOLATILE_EN__SHIFT 0x14 |
32250 | #define GL2C_CTRL2__RB_VOLATILE_EN__SHIFT 0x15 |
32251 | #define GL2C_CTRL2__PROBE_UNSHARED_EN__SHIFT 0x16 |
32252 | #define GL2C_CTRL2__MAX_MIN_CTRL__SHIFT 0x17 |
32253 | #define GL2C_CTRL2__MDC_UC_TO_C_RO_EN__SHIFT 0x1a |
32254 | #define GL2C_CTRL2__PROBE_FIFO_SIZE_MASK 0x0000000FL |
32255 | #define GL2C_CTRL2__ADDR_MATCH_DISABLE_MASK 0x00000010L |
32256 | #define GL2C_CTRL2__FILL_SIZE_32_MASK 0x00000020L |
32257 | #define GL2C_CTRL2__RB_TO_HI_PRIORITY_MASK 0x00000040L |
32258 | #define GL2C_CTRL2__HIT_UNDER_MISS_DISABLE_MASK 0x00000080L |
32259 | #define GL2C_CTRL2__RO_DISABLE_MASK 0x00000100L |
32260 | #define GL2C_CTRL2__FORCE_MDC_INV_MASK 0x00000200L |
32261 | #define GL2C_CTRL2__GCR_ARB_CTRL_MASK 0x00001C00L |
32262 | #define GL2C_CTRL2__GCR_ALL_SET_MASK 0x00002000L |
32263 | #define GL2C_CTRL2__FILL_SIZE_64_MASK 0x00020000L |
32264 | #define GL2C_CTRL2__USE_EA_EARLYWRRET_ON_WRITEBACK_MASK 0x00040000L |
32265 | #define GL2C_CTRL2__WRITEBACK_ALL_WAIT_FOR_ALL_EA_WRITE_COMPLETE_MASK 0x00080000L |
32266 | #define GL2C_CTRL2__METADATA_VOLATILE_EN_MASK 0x00100000L |
32267 | #define GL2C_CTRL2__RB_VOLATILE_EN_MASK 0x00200000L |
32268 | #define GL2C_CTRL2__PROBE_UNSHARED_EN_MASK 0x00400000L |
32269 | #define GL2C_CTRL2__MAX_MIN_CTRL_MASK 0x01800000L |
32270 | #define GL2C_CTRL2__MDC_UC_TO_C_RO_EN_MASK 0x04000000L |
32271 | //GL2C_STATUS |
32272 | #define GL2C_STATUS__NONCACHEABLE_FLOAT_ATOMIC__SHIFT 0x0 |
32273 | #define GL2C_STATUS__NONCACHEABLE_U8_ATOMIC__SHIFT 0x4 |
32274 | #define GL2C_STATUS__NONCACHEABLE_CLAMP_SUB_ATOMIC__SHIFT 0x5 |
32275 | #define GL2C_STATUS__WRRET_NACK_FAULT__SHIFT 0x6 |
32276 | #define GL2C_STATUS__RDRET_NACK_FAULT__SHIFT 0x7 |
32277 | #define GL2C_STATUS__METADATA_FED__SHIFT 0x8 |
32278 | #define GL2C_STATUS__FED_FSM_STATE__SHIFT 0x9 |
32279 | #define GL2C_STATUS__SAFE_MODE_FED__SHIFT 0xb |
32280 | #define GL2C_STATUS__DCC_OUT_INVALID_KEY_ERROR_CODE__SHIFT 0x12 |
32281 | #define GL2C_STATUS__NONCACHEABLE_FLOAT_ATOMIC_MASK 0x00000001L |
32282 | #define GL2C_STATUS__NONCACHEABLE_U8_ATOMIC_MASK 0x00000010L |
32283 | #define GL2C_STATUS__NONCACHEABLE_CLAMP_SUB_ATOMIC_MASK 0x00000020L |
32284 | #define GL2C_STATUS__WRRET_NACK_FAULT_MASK 0x00000040L |
32285 | #define GL2C_STATUS__RDRET_NACK_FAULT_MASK 0x00000080L |
32286 | #define GL2C_STATUS__METADATA_FED_MASK 0x00000100L |
32287 | #define GL2C_STATUS__FED_FSM_STATE_MASK 0x00000600L |
32288 | #define GL2C_STATUS__SAFE_MODE_FED_MASK 0x00000800L |
32289 | #define GL2C_STATUS__DCC_OUT_INVALID_KEY_ERROR_CODE_MASK 0x007C0000L |
32290 | //GL2C_ADDR_MATCH_MASK |
32291 | #define GL2C_ADDR_MATCH_MASK__ADDR_MASK__SHIFT 0x0 |
32292 | #define GL2C_ADDR_MATCH_MASK__ADDR_MASK_MASK 0xFFFFFFFFL |
32293 | //GL2C_ADDR_MATCH_SIZE |
32294 | #define GL2C_ADDR_MATCH_SIZE__MAX_COUNT__SHIFT 0x0 |
32295 | #define GL2C_ADDR_MATCH_SIZE__MAX_COUNT_MASK 0x00000007L |
32296 | //GL2C_WBINVL2 |
32297 | #define GL2C_WBINVL2__DONE__SHIFT 0x4 |
32298 | #define GL2C_WBINVL2__DONE_MASK 0x00000010L |
32299 | //GL2C_SOFT_RESET |
32300 | #define GL2C_SOFT_RESET__HALT_FOR_RESET__SHIFT 0x0 |
32301 | #define GL2C_SOFT_RESET__HALT_FOR_RESET_MASK 0x00000001L |
32302 | //GL2C_CM_CTRL0 |
32303 | #define GL2C_CM_CTRL0__HASH_MASK__SHIFT 0x0 |
32304 | #define GL2C_CM_CTRL0__HASH_MASK_MASK 0xFFFFFFFFL |
32305 | //GL2C_CM_CTRL1 |
32306 | #define GL2C_CM_CTRL1__HASH_MASK__SHIFT 0x0 |
32307 | #define GL2C_CM_CTRL1__BURST_TIMER__SHIFT 0x8 |
32308 | #define GL2C_CM_CTRL1__RVF_SIZE__SHIFT 0x10 |
32309 | #define GL2C_CM_CTRL1__WRITE_COH_MODE__SHIFT 0x17 |
32310 | #define GL2C_CM_CTRL1__MDC_ARB_MODE__SHIFT 0x19 |
32311 | #define GL2C_CM_CTRL1__READ_REQ_ONLY__SHIFT 0x1a |
32312 | #define GL2C_CM_CTRL1__COMP_TO_CONSTANT_EN__SHIFT 0x1b |
32313 | #define GL2C_CM_CTRL1__COMP_TO_SINGLE_EN__SHIFT 0x1c |
32314 | #define GL2C_CM_CTRL1__BURST_MODE__SHIFT 0x1d |
32315 | #define GL2C_CM_CTRL1__UNCOMP_READBACK_FILTER__SHIFT 0x1e |
32316 | #define GL2C_CM_CTRL1__WAIT_ATOMIC_RECOMP_WRITE__SHIFT 0x1f |
32317 | #define GL2C_CM_CTRL1__HASH_MASK_MASK 0x0000000FL |
32318 | #define GL2C_CM_CTRL1__BURST_TIMER_MASK 0x0000FF00L |
32319 | #define GL2C_CM_CTRL1__RVF_SIZE_MASK 0x000F0000L |
32320 | #define GL2C_CM_CTRL1__WRITE_COH_MODE_MASK 0x01800000L |
32321 | #define GL2C_CM_CTRL1__MDC_ARB_MODE_MASK 0x02000000L |
32322 | #define GL2C_CM_CTRL1__READ_REQ_ONLY_MASK 0x04000000L |
32323 | #define GL2C_CM_CTRL1__COMP_TO_CONSTANT_EN_MASK 0x08000000L |
32324 | #define GL2C_CM_CTRL1__COMP_TO_SINGLE_EN_MASK 0x10000000L |
32325 | #define GL2C_CM_CTRL1__BURST_MODE_MASK 0x20000000L |
32326 | #define GL2C_CM_CTRL1__UNCOMP_READBACK_FILTER_MASK 0x40000000L |
32327 | #define GL2C_CM_CTRL1__WAIT_ATOMIC_RECOMP_WRITE_MASK 0x80000000L |
32328 | //GL2C_CM_STALL |
32329 | #define GL2C_CM_STALL__QUEUE__SHIFT 0x0 |
32330 | #define GL2C_CM_STALL__QUEUE_MASK 0xFFFFFFFFL |
32331 | //GL2C_CM_CTRL2 |
32332 | #define GL2C_CM_CTRL2__READ_BURST_TIMER__SHIFT 0x0 |
32333 | #define GL2C_CM_CTRL2__VRS_DISABLE__SHIFT 0x8 |
32334 | #define GL2C_CM_CTRL2__SKIP_LOW_COMP_RATIO__SHIFT 0x9 |
32335 | #define GL2C_CM_CTRL2__CM_NBC_IND64_DISABLE__SHIFT 0xa |
32336 | #define GL2C_CM_CTRL2__PARTIAL_WR_OPT_MODE__SHIFT 0xb |
32337 | #define GL2C_CM_CTRL2__PARTIAL_WR_OPT_METADATA_WR_MODE__SHIFT 0xc |
32338 | #define GL2C_CM_CTRL2__PARTIAL_WR_OPT_MAX_UNCOMP_BLK_SZ_MODE__SHIFT 0xd |
32339 | #define GL2C_CM_CTRL2__PARTIAL_WR_OPT_SECTOR_READBACK_MODE__SHIFT 0xf |
32340 | #define GL2C_CM_CTRL2__RECOMP_DISABLE__SHIFT 0x10 |
32341 | #define GL2C_CM_CTRL2__DCC_COMP_KEY_ERROR_DETECTION_EN__SHIFT 0x11 |
32342 | #define GL2C_CM_CTRL2__DCC_CLEAR_FRAG2DCC_KEY_ERROR_CODE__SHIFT 0x12 |
32343 | #define GL2C_CM_CTRL2__READ_BURST_TIMER_MASK 0x000000FFL |
32344 | #define GL2C_CM_CTRL2__VRS_DISABLE_MASK 0x00000100L |
32345 | #define GL2C_CM_CTRL2__SKIP_LOW_COMP_RATIO_MASK 0x00000200L |
32346 | #define GL2C_CM_CTRL2__CM_NBC_IND64_DISABLE_MASK 0x00000400L |
32347 | #define GL2C_CM_CTRL2__PARTIAL_WR_OPT_MODE_MASK 0x00000800L |
32348 | #define GL2C_CM_CTRL2__PARTIAL_WR_OPT_METADATA_WR_MODE_MASK 0x00001000L |
32349 | #define GL2C_CM_CTRL2__PARTIAL_WR_OPT_MAX_UNCOMP_BLK_SZ_MODE_MASK 0x00006000L |
32350 | #define GL2C_CM_CTRL2__PARTIAL_WR_OPT_SECTOR_READBACK_MODE_MASK 0x00008000L |
32351 | #define GL2C_CM_CTRL2__RECOMP_DISABLE_MASK 0x00010000L |
32352 | #define GL2C_CM_CTRL2__DCC_COMP_KEY_ERROR_DETECTION_EN_MASK 0x00020000L |
32353 | #define GL2C_CM_CTRL2__DCC_CLEAR_FRAG2DCC_KEY_ERROR_CODE_MASK 0x00040000L |
32354 | //GL2C_CTRL3 |
32355 | #define GL2C_CTRL3__METADATA_MTYPE_COHERENCY__SHIFT 0x0 |
32356 | #define GL2C_CTRL3__METADATA_NOFILL__SHIFT 0x3 |
32357 | #define GL2C_CTRL3__METADATA_NEXT_CL_PREFETCH__SHIFT 0x4 |
32358 | #define GL2C_CTRL3__BANK_LINEAR_HASH_MODE__SHIFT 0x5 |
32359 | #define GL2C_CTRL3__HTILE_TO_HI_PRIORITY__SHIFT 0x6 |
32360 | #define GL2C_CTRL3__UNCACHED_WRITE_ATOMIC_TO_UC_WRITE__SHIFT 0x7 |
32361 | #define GL2C_CTRL3__IO_CHANNEL_ENABLE__SHIFT 0x8 |
32362 | #define GL2C_CTRL3__FMASK_TO_HI_PRIORITY__SHIFT 0x9 |
32363 | #define GL2C_CTRL3__DCC_CMASK_TO_HI_PRIORITY__SHIFT 0xa |
32364 | #define GL2C_CTRL3__BANK_LINEAR_HASH_ENABLE__SHIFT 0xb |
32365 | #define GL2C_CTRL3__HASH_256B_ENABLE__SHIFT 0xc |
32366 | #define GL2C_CTRL3__DECOMP_NBC_IND64_DISABLE__SHIFT 0xd |
32367 | #define GL2C_CTRL3__FORCE_READ_ON_WRITE_OP__SHIFT 0xe |
32368 | #define GL2C_CTRL3__FGCG_OVERRIDE__SHIFT 0xf |
32369 | #define GL2C_CTRL3__FORCE_MTYPE_UC__SHIFT 0x10 |
32370 | #define GL2C_CTRL3__DGPU_SHARED_MODE__SHIFT 0x11 |
32371 | #define GL2C_CTRL3__WRITE_SET_SECTOR_FULLY_WRITTEN__SHIFT 0x12 |
32372 | #define GL2C_CTRL3__EA_READ_SIZE_LIMIT__SHIFT 0x13 |
32373 | #define GL2C_CTRL3__READ_BYPASS_AS_UC__SHIFT 0x14 |
32374 | #define GL2C_CTRL3__WB_OPT_ENABLE__SHIFT 0x15 |
32375 | #define GL2C_CTRL3__WB_OPT_BURST_MAX_COUNT__SHIFT 0x16 |
32376 | #define GL2C_CTRL3__SET_GROUP_LINEAR_HASH_ENABLE__SHIFT 0x18 |
32377 | #define GL2C_CTRL3__EA_GMI_DISABLE__SHIFT 0x19 |
32378 | #define GL2C_CTRL3__SQC_TO_HI_PRIORITY__SHIFT 0x1a |
32379 | #define GL2C_CTRL3__INF_NAN_CLAMP__SHIFT 0x1b |
32380 | #define GL2C_CTRL3__SCRATCH__SHIFT 0x1c |
32381 | #define GL2C_CTRL3__METADATA_MTYPE_COHERENCY_MASK 0x00000003L |
32382 | #define GL2C_CTRL3__METADATA_NOFILL_MASK 0x00000008L |
32383 | #define GL2C_CTRL3__METADATA_NEXT_CL_PREFETCH_MASK 0x00000010L |
32384 | #define GL2C_CTRL3__BANK_LINEAR_HASH_MODE_MASK 0x00000020L |
32385 | #define GL2C_CTRL3__HTILE_TO_HI_PRIORITY_MASK 0x00000040L |
32386 | #define GL2C_CTRL3__UNCACHED_WRITE_ATOMIC_TO_UC_WRITE_MASK 0x00000080L |
32387 | #define GL2C_CTRL3__IO_CHANNEL_ENABLE_MASK 0x00000100L |
32388 | #define GL2C_CTRL3__FMASK_TO_HI_PRIORITY_MASK 0x00000200L |
32389 | #define GL2C_CTRL3__DCC_CMASK_TO_HI_PRIORITY_MASK 0x00000400L |
32390 | #define GL2C_CTRL3__BANK_LINEAR_HASH_ENABLE_MASK 0x00000800L |
32391 | #define GL2C_CTRL3__HASH_256B_ENABLE_MASK 0x00001000L |
32392 | #define GL2C_CTRL3__DECOMP_NBC_IND64_DISABLE_MASK 0x00002000L |
32393 | #define GL2C_CTRL3__FORCE_READ_ON_WRITE_OP_MASK 0x00004000L |
32394 | #define GL2C_CTRL3__FGCG_OVERRIDE_MASK 0x00008000L |
32395 | #define GL2C_CTRL3__FORCE_MTYPE_UC_MASK 0x00010000L |
32396 | #define GL2C_CTRL3__DGPU_SHARED_MODE_MASK 0x00020000L |
32397 | #define GL2C_CTRL3__WRITE_SET_SECTOR_FULLY_WRITTEN_MASK 0x00040000L |
32398 | #define GL2C_CTRL3__EA_READ_SIZE_LIMIT_MASK 0x00080000L |
32399 | #define GL2C_CTRL3__READ_BYPASS_AS_UC_MASK 0x00100000L |
32400 | #define GL2C_CTRL3__WB_OPT_ENABLE_MASK 0x00200000L |
32401 | #define GL2C_CTRL3__WB_OPT_BURST_MAX_COUNT_MASK 0x00C00000L |
32402 | #define GL2C_CTRL3__SET_GROUP_LINEAR_HASH_ENABLE_MASK 0x01000000L |
32403 | #define GL2C_CTRL3__EA_GMI_DISABLE_MASK 0x02000000L |
32404 | #define GL2C_CTRL3__SQC_TO_HI_PRIORITY_MASK 0x04000000L |
32405 | #define GL2C_CTRL3__INF_NAN_CLAMP_MASK 0x08000000L |
32406 | #define GL2C_CTRL3__SCRATCH_MASK 0xF0000000L |
32407 | //GL2C_LB_CTR_CTRL |
32408 | #define GL2C_LB_CTR_CTRL__START__SHIFT 0x0 |
32409 | #define GL2C_LB_CTR_CTRL__LOAD__SHIFT 0x1 |
32410 | #define GL2C_LB_CTR_CTRL__CLEAR__SHIFT 0x2 |
32411 | #define GL2C_LB_CTR_CTRL__PERF_CNTR_EN_OVERRIDE__SHIFT 0x1f |
32412 | #define GL2C_LB_CTR_CTRL__START_MASK 0x00000001L |
32413 | #define GL2C_LB_CTR_CTRL__LOAD_MASK 0x00000002L |
32414 | #define GL2C_LB_CTR_CTRL__CLEAR_MASK 0x00000004L |
32415 | #define GL2C_LB_CTR_CTRL__PERF_CNTR_EN_OVERRIDE_MASK 0x80000000L |
32416 | //GL2C_LB_DATA0 |
32417 | #define GL2C_LB_DATA0__DATA__SHIFT 0x0 |
32418 | #define GL2C_LB_DATA0__DATA_MASK 0xFFFFFFFFL |
32419 | //GL2C_LB_DATA1 |
32420 | #define GL2C_LB_DATA1__DATA__SHIFT 0x0 |
32421 | #define GL2C_LB_DATA1__DATA_MASK 0xFFFFFFFFL |
32422 | //GL2C_LB_DATA2 |
32423 | #define GL2C_LB_DATA2__DATA__SHIFT 0x0 |
32424 | #define GL2C_LB_DATA2__DATA_MASK 0xFFFFFFFFL |
32425 | //GL2C_LB_DATA3 |
32426 | #define GL2C_LB_DATA3__DATA__SHIFT 0x0 |
32427 | #define GL2C_LB_DATA3__DATA_MASK 0xFFFFFFFFL |
32428 | //GL2C_LB_CTR_SEL0 |
32429 | #define GL2C_LB_CTR_SEL0__SEL0__SHIFT 0x0 |
32430 | #define GL2C_LB_CTR_SEL0__DIV0__SHIFT 0xf |
32431 | #define GL2C_LB_CTR_SEL0__SEL1__SHIFT 0x10 |
32432 | #define GL2C_LB_CTR_SEL0__DIV1__SHIFT 0x1f |
32433 | #define GL2C_LB_CTR_SEL0__SEL0_MASK 0x000000FFL |
32434 | #define GL2C_LB_CTR_SEL0__DIV0_MASK 0x00008000L |
32435 | #define GL2C_LB_CTR_SEL0__SEL1_MASK 0x00FF0000L |
32436 | #define GL2C_LB_CTR_SEL0__DIV1_MASK 0x80000000L |
32437 | //GL2C_LB_CTR_SEL1 |
32438 | #define GL2C_LB_CTR_SEL1__SEL2__SHIFT 0x0 |
32439 | #define GL2C_LB_CTR_SEL1__DIV2__SHIFT 0xf |
32440 | #define GL2C_LB_CTR_SEL1__SEL3__SHIFT 0x10 |
32441 | #define GL2C_LB_CTR_SEL1__DIV3__SHIFT 0x1f |
32442 | #define GL2C_LB_CTR_SEL1__SEL2_MASK 0x000000FFL |
32443 | #define GL2C_LB_CTR_SEL1__DIV2_MASK 0x00008000L |
32444 | #define GL2C_LB_CTR_SEL1__SEL3_MASK 0x00FF0000L |
32445 | #define GL2C_LB_CTR_SEL1__DIV3_MASK 0x80000000L |
32446 | //GL2C_CTRL4 |
32447 | #define GL2C_CTRL4__METADATA_WR_OP_CID__SHIFT 0x0 |
32448 | #define GL2C_CTRL4__SPA_CHANNEL_ENABLE__SHIFT 0x1 |
32449 | #define GL2C_CTRL4__SRC_FIFO_MDC_LOW_PRIORITY__SHIFT 0x2 |
32450 | #define GL2C_CTRL4__WRITEBACK_FIFO_STALL_ENABLE__SHIFT 0x3 |
32451 | #define GL2C_CTRL4__CM_MGCG_MODE__SHIFT 0x4 |
32452 | #define GL2C_CTRL4__MDC_MGCG_MODE__SHIFT 0x5 |
32453 | #define GL2C_CTRL4__TAG_MGCG_MODE__SHIFT 0x6 |
32454 | #define GL2C_CTRL4__CORE_MGCG_MODE__SHIFT 0x7 |
32455 | #define GL2C_CTRL4__EXECUTE_MGCG_MODE__SHIFT 0x8 |
32456 | #define GL2C_CTRL4__EA_NACK_DISABLE__SHIFT 0x9 |
32457 | #define GL2C_CTRL4__FED_SAFE_MODE__SHIFT 0xa |
32458 | #define GL2C_CTRL4__FLUSH_SET_COUNTER_MASK_DISABLE__SHIFT 0xb |
32459 | #define GL2C_CTRL4__NO_WRITE_ACK_TO_HIT_QUEUE__SHIFT 0x1a |
32460 | #define GL2C_CTRL4__METADATA_WR_OP_CID_MASK 0x00000001L |
32461 | #define GL2C_CTRL4__SPA_CHANNEL_ENABLE_MASK 0x00000002L |
32462 | #define GL2C_CTRL4__SRC_FIFO_MDC_LOW_PRIORITY_MASK 0x00000004L |
32463 | #define GL2C_CTRL4__WRITEBACK_FIFO_STALL_ENABLE_MASK 0x00000008L |
32464 | #define GL2C_CTRL4__CM_MGCG_MODE_MASK 0x00000010L |
32465 | #define GL2C_CTRL4__MDC_MGCG_MODE_MASK 0x00000020L |
32466 | #define GL2C_CTRL4__TAG_MGCG_MODE_MASK 0x00000040L |
32467 | #define GL2C_CTRL4__CORE_MGCG_MODE_MASK 0x00000080L |
32468 | #define GL2C_CTRL4__EXECUTE_MGCG_MODE_MASK 0x00000100L |
32469 | #define GL2C_CTRL4__EA_NACK_DISABLE_MASK 0x00000200L |
32470 | #define GL2C_CTRL4__FED_SAFE_MODE_MASK 0x00000400L |
32471 | #define GL2C_CTRL4__FLUSH_SET_COUNTER_MASK_DISABLE_MASK 0x00000800L |
32472 | #define GL2C_CTRL4__NO_WRITE_ACK_TO_HIT_QUEUE_MASK 0x04000000L |
32473 | //GL2C_DISCARD_STALL_CTRL |
32474 | #define GL2C_DISCARD_STALL_CTRL__LIMIT__SHIFT 0x0 |
32475 | #define GL2C_DISCARD_STALL_CTRL__WINDOW__SHIFT 0xf |
32476 | #define GL2C_DISCARD_STALL_CTRL__DROP_NEXT__SHIFT 0x1e |
32477 | #define GL2C_DISCARD_STALL_CTRL__ENABLE__SHIFT 0x1f |
32478 | #define GL2C_DISCARD_STALL_CTRL__LIMIT_MASK 0x00007FFFL |
32479 | #define GL2C_DISCARD_STALL_CTRL__WINDOW_MASK 0x3FFF8000L |
32480 | #define GL2C_DISCARD_STALL_CTRL__DROP_NEXT_MASK 0x40000000L |
32481 | #define GL2C_DISCARD_STALL_CTRL__ENABLE_MASK 0x80000000L |
32482 | //GL2A_ADDR_MATCH_CTRL |
32483 | #define GL2A_ADDR_MATCH_CTRL__DISABLE__SHIFT 0x0 |
32484 | #define GL2A_ADDR_MATCH_CTRL__DISABLE_MASK 0xFFFFFFFFL |
32485 | //GL2A_ADDR_MATCH_MASK |
32486 | #define GL2A_ADDR_MATCH_MASK__ADDR_MASK__SHIFT 0x0 |
32487 | #define GL2A_ADDR_MATCH_MASK__ADDR_MASK_MASK 0xFFFFFFFFL |
32488 | //GL2A_ADDR_MATCH_SIZE |
32489 | #define GL2A_ADDR_MATCH_SIZE__MAX_COUNT__SHIFT 0x0 |
32490 | #define GL2A_ADDR_MATCH_SIZE__MAX_COUNT_MASK 0x00000007L |
32491 | //GL2A_PRIORITY_CTRL |
32492 | #define GL2A_PRIORITY_CTRL__DISABLE__SHIFT 0x0 |
32493 | #define GL2A_PRIORITY_CTRL__DISABLE_MASK 0xFFFFFFFFL |
32494 | //GL2A_CTRL |
32495 | #define GL2A_CTRL__RTN_ARB_TIMER_RESET_VALUE__SHIFT 0x0 |
32496 | #define GL2A_CTRL__STAY_ON_BURST__SHIFT 0x1 |
32497 | #define GL2A_CTRL__FGCG_OVERRIDE__SHIFT 0x2 |
32498 | #define GL2A_CTRL__CLIENT_ARB_PRIO_STAY__SHIFT 0x3 |
32499 | #define GL2A_CTRL__GCRD_CREDIT_SAFE_REG__SHIFT 0x4 |
32500 | #define GL2A_CTRL__REQ_CREDIT_SAFE_REG__SHIFT 0x8 |
32501 | #define GL2A_CTRL__WRITE_COMBINE_TIMEOUT_COUNT__SHIFT 0xc |
32502 | #define GL2A_CTRL__INTERNAL_RETURN_BYPASS_ENABLE__SHIFT 0x11 |
32503 | #define GL2A_CTRL__ADDR_REMOVE_COLBITS__SHIFT 0x12 |
32504 | #define GL2A_CTRL__RTN_ARB_TIMER_RESET_VALUE_MASK 0x00000001L |
32505 | #define GL2A_CTRL__STAY_ON_BURST_MASK 0x00000002L |
32506 | #define GL2A_CTRL__FGCG_OVERRIDE_MASK 0x00000004L |
32507 | #define GL2A_CTRL__CLIENT_ARB_PRIO_STAY_MASK 0x00000008L |
32508 | #define GL2A_CTRL__GCRD_CREDIT_SAFE_REG_MASK 0x000000F0L |
32509 | #define GL2A_CTRL__REQ_CREDIT_SAFE_REG_MASK 0x00000F00L |
32510 | #define GL2A_CTRL__WRITE_COMBINE_TIMEOUT_COUNT_MASK 0x0001F000L |
32511 | #define GL2A_CTRL__INTERNAL_RETURN_BYPASS_ENABLE_MASK 0x00020000L |
32512 | #define GL2A_CTRL__ADDR_REMOVE_COLBITS_MASK 0x00040000L |
32513 | //GL2A_RESP_THROTTLE_CTRL |
32514 | #define GL2A_RESP_THROTTLE_CTRL__DISABLE__SHIFT 0x0 |
32515 | #define GL2A_RESP_THROTTLE_CTRL__CREDIT_GL1__SHIFT 0x10 |
32516 | #define GL2A_RESP_THROTTLE_CTRL__CREDIT_CH__SHIFT 0x18 |
32517 | #define GL2A_RESP_THROTTLE_CTRL__DISABLE_MASK 0x0000FFFFL |
32518 | #define GL2A_RESP_THROTTLE_CTRL__CREDIT_GL1_MASK 0x00FF0000L |
32519 | #define GL2A_RESP_THROTTLE_CTRL__CREDIT_CH_MASK 0xFF000000L |
32520 | |
32521 | |
32522 | // addressBlock: gc_gl1hdec |
32523 | //GL1H_ARB_CTRL |
32524 | #define GL1H_ARB_CTRL__REQ_FGCG_DISABLE__SHIFT 0x0 |
32525 | #define GL1H_ARB_CTRL__SRC_FGCG_DISABLE__SHIFT 0x1 |
32526 | #define GL1H_ARB_CTRL__RET_FGCG_DISABLE__SHIFT 0x2 |
32527 | #define GL1H_ARB_CTRL__CHICKEN_BITS__SHIFT 0x3 |
32528 | #define GL1H_ARB_CTRL__PERF_CNTR_EN_OVERRIDE__SHIFT 0xb |
32529 | #define GL1H_ARB_CTRL__REQ_FGCG_DISABLE_MASK 0x00000001L |
32530 | #define GL1H_ARB_CTRL__SRC_FGCG_DISABLE_MASK 0x00000002L |
32531 | #define GL1H_ARB_CTRL__RET_FGCG_DISABLE_MASK 0x00000004L |
32532 | #define GL1H_ARB_CTRL__CHICKEN_BITS_MASK 0x000007F8L |
32533 | #define GL1H_ARB_CTRL__PERF_CNTR_EN_OVERRIDE_MASK 0x00000800L |
32534 | //GL1H_GL1_CREDITS |
32535 | #define GL1H_GL1_CREDITS__GL1_REQ_CREDITS__SHIFT 0x0 |
32536 | #define GL1H_GL1_CREDITS__GL1_REQ_CREDITS_MASK 0x000000FFL |
32537 | //GL1H_BURST_MASK |
32538 | #define GL1H_BURST_MASK__BURST_ADDR_MASK__SHIFT 0x0 |
32539 | #define GL1H_BURST_MASK__BURST_ADDR_MASK_MASK 0x000000FFL |
32540 | //GL1H_BURST_CTRL |
32541 | #define GL1H_BURST_CTRL__MAX_BURST_SIZE__SHIFT 0x0 |
32542 | #define GL1H_BURST_CTRL__BURST_DISABLE__SHIFT 0x3 |
32543 | #define GL1H_BURST_CTRL__SPARE_BURST_CTRL_BITS__SHIFT 0x4 |
32544 | #define GL1H_BURST_CTRL__MAX_BURST_SIZE_MASK 0x00000007L |
32545 | #define GL1H_BURST_CTRL__BURST_DISABLE_MASK 0x00000008L |
32546 | #define GL1H_BURST_CTRL__SPARE_BURST_CTRL_BITS_MASK 0x00000030L |
32547 | //GL1H_ARB_STATUS |
32548 | #define GL1H_ARB_STATUS__REQ_ARB_BUSY__SHIFT 0x0 |
32549 | #define GL1H_ARB_STATUS__CLIENT1_ILLEGAL_REQ__SHIFT 0x1 |
32550 | #define GL1H_ARB_STATUS__REQ_ARB_BUSY_MASK 0x00000001L |
32551 | #define GL1H_ARB_STATUS__CLIENT1_ILLEGAL_REQ_MASK 0x00000002L |
32552 | |
32553 | |
32554 | // addressBlock: gc_perfddec |
32555 | //CPG_PERFCOUNTER1_LO |
32556 | #define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
32557 | #define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
32558 | //CPG_PERFCOUNTER1_HI |
32559 | #define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
32560 | #define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
32561 | //CPG_PERFCOUNTER0_LO |
32562 | #define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
32563 | #define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
32564 | //CPG_PERFCOUNTER0_HI |
32565 | #define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
32566 | #define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
32567 | //CPC_PERFCOUNTER1_LO |
32568 | #define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
32569 | #define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
32570 | //CPC_PERFCOUNTER1_HI |
32571 | #define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
32572 | #define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
32573 | //CPC_PERFCOUNTER0_LO |
32574 | #define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
32575 | #define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
32576 | //CPC_PERFCOUNTER0_HI |
32577 | #define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
32578 | #define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
32579 | //CPF_PERFCOUNTER1_LO |
32580 | #define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
32581 | #define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
32582 | //CPF_PERFCOUNTER1_HI |
32583 | #define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
32584 | #define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
32585 | //CPF_PERFCOUNTER0_LO |
32586 | #define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
32587 | #define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
32588 | //CPF_PERFCOUNTER0_HI |
32589 | #define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
32590 | #define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
32591 | //CPF_LATENCY_STATS_DATA |
32592 | #define CPF_LATENCY_STATS_DATA__DATA__SHIFT 0x0 |
32593 | #define CPF_LATENCY_STATS_DATA__DATA_MASK 0xFFFFFFFFL |
32594 | //CPG_LATENCY_STATS_DATA |
32595 | #define CPG_LATENCY_STATS_DATA__DATA__SHIFT 0x0 |
32596 | #define CPG_LATENCY_STATS_DATA__DATA_MASK 0xFFFFFFFFL |
32597 | //CPC_LATENCY_STATS_DATA |
32598 | #define CPC_LATENCY_STATS_DATA__DATA__SHIFT 0x0 |
32599 | #define CPC_LATENCY_STATS_DATA__DATA_MASK 0xFFFFFFFFL |
32600 | //GRBM_PERFCOUNTER0_LO |
32601 | #define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
32602 | #define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
32603 | //GRBM_PERFCOUNTER0_HI |
32604 | #define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
32605 | #define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
32606 | //GRBM_PERFCOUNTER1_LO |
32607 | #define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
32608 | #define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
32609 | //GRBM_PERFCOUNTER1_HI |
32610 | #define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
32611 | #define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
32612 | //GRBM_SE0_PERFCOUNTER_LO |
32613 | #define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0 |
32614 | #define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
32615 | //GRBM_SE0_PERFCOUNTER_HI |
32616 | #define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0 |
32617 | #define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
32618 | //GRBM_SE1_PERFCOUNTER_LO |
32619 | #define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0 |
32620 | #define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
32621 | //GRBM_SE1_PERFCOUNTER_HI |
32622 | #define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0 |
32623 | #define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
32624 | //GRBM_SE2_PERFCOUNTER_LO |
32625 | #define GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0 |
32626 | #define GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
32627 | //GRBM_SE2_PERFCOUNTER_HI |
32628 | #define GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0 |
32629 | #define GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
32630 | //GRBM_SE3_PERFCOUNTER_LO |
32631 | #define GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0 |
32632 | #define GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
32633 | //GRBM_SE3_PERFCOUNTER_HI |
32634 | #define GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0 |
32635 | #define GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
32636 | //GE1_PERFCOUNTER0_LO |
32637 | #define GE1_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
32638 | #define GE1_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
32639 | //GE1_PERFCOUNTER0_HI |
32640 | #define GE1_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
32641 | #define GE1_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
32642 | //GE1_PERFCOUNTER1_LO |
32643 | #define GE1_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
32644 | #define GE1_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
32645 | //GE1_PERFCOUNTER1_HI |
32646 | #define GE1_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
32647 | #define GE1_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
32648 | //GE1_PERFCOUNTER2_LO |
32649 | #define GE1_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 |
32650 | #define GE1_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
32651 | //GE1_PERFCOUNTER2_HI |
32652 | #define GE1_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 |
32653 | #define GE1_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
32654 | //GE1_PERFCOUNTER3_LO |
32655 | #define GE1_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 |
32656 | #define GE1_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
32657 | //GE1_PERFCOUNTER3_HI |
32658 | #define GE1_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 |
32659 | #define GE1_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
32660 | //GE2_DIST_PERFCOUNTER0_LO |
32661 | #define GE2_DIST_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
32662 | #define GE2_DIST_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
32663 | //GE2_DIST_PERFCOUNTER0_HI |
32664 | #define GE2_DIST_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
32665 | #define GE2_DIST_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
32666 | //GE2_DIST_PERFCOUNTER1_LO |
32667 | #define GE2_DIST_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
32668 | #define GE2_DIST_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
32669 | //GE2_DIST_PERFCOUNTER1_HI |
32670 | #define GE2_DIST_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
32671 | #define GE2_DIST_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
32672 | //GE2_DIST_PERFCOUNTER2_LO |
32673 | #define GE2_DIST_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 |
32674 | #define GE2_DIST_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
32675 | //GE2_DIST_PERFCOUNTER2_HI |
32676 | #define GE2_DIST_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 |
32677 | #define GE2_DIST_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
32678 | //GE2_DIST_PERFCOUNTER3_LO |
32679 | #define GE2_DIST_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 |
32680 | #define GE2_DIST_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
32681 | //GE2_DIST_PERFCOUNTER3_HI |
32682 | #define GE2_DIST_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 |
32683 | #define GE2_DIST_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
32684 | //GE2_SE_PERFCOUNTER0_LO |
32685 | #define GE2_SE_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
32686 | #define GE2_SE_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
32687 | //GE2_SE_PERFCOUNTER0_HI |
32688 | #define GE2_SE_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
32689 | #define GE2_SE_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
32690 | //GE2_SE_PERFCOUNTER1_LO |
32691 | #define GE2_SE_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
32692 | #define GE2_SE_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
32693 | //GE2_SE_PERFCOUNTER1_HI |
32694 | #define GE2_SE_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
32695 | #define GE2_SE_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
32696 | //GE2_SE_PERFCOUNTER2_LO |
32697 | #define GE2_SE_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 |
32698 | #define GE2_SE_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
32699 | //GE2_SE_PERFCOUNTER2_HI |
32700 | #define GE2_SE_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 |
32701 | #define GE2_SE_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
32702 | //GE2_SE_PERFCOUNTER3_LO |
32703 | #define GE2_SE_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 |
32704 | #define GE2_SE_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
32705 | //GE2_SE_PERFCOUNTER3_HI |
32706 | #define GE2_SE_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 |
32707 | #define GE2_SE_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
32708 | //PA_SU_PERFCOUNTER0_LO |
32709 | #define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
32710 | #define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
32711 | //PA_SU_PERFCOUNTER0_HI |
32712 | #define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
32713 | #define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
32714 | //PA_SU_PERFCOUNTER1_LO |
32715 | #define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
32716 | #define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
32717 | //PA_SU_PERFCOUNTER1_HI |
32718 | #define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
32719 | #define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
32720 | //PA_SU_PERFCOUNTER2_LO |
32721 | #define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 |
32722 | #define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
32723 | //PA_SU_PERFCOUNTER2_HI |
32724 | #define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 |
32725 | #define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
32726 | //PA_SU_PERFCOUNTER3_LO |
32727 | #define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 |
32728 | #define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
32729 | //PA_SU_PERFCOUNTER3_HI |
32730 | #define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 |
32731 | #define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
32732 | //PA_SC_PERFCOUNTER0_LO |
32733 | #define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
32734 | #define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
32735 | //PA_SC_PERFCOUNTER0_HI |
32736 | #define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
32737 | #define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
32738 | //PA_SC_PERFCOUNTER1_LO |
32739 | #define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
32740 | #define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
32741 | //PA_SC_PERFCOUNTER1_HI |
32742 | #define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
32743 | #define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
32744 | //PA_SC_PERFCOUNTER2_LO |
32745 | #define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 |
32746 | #define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
32747 | //PA_SC_PERFCOUNTER2_HI |
32748 | #define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 |
32749 | #define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
32750 | //PA_SC_PERFCOUNTER3_LO |
32751 | #define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 |
32752 | #define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
32753 | //PA_SC_PERFCOUNTER3_HI |
32754 | #define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 |
32755 | #define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
32756 | //PA_SC_PERFCOUNTER4_LO |
32757 | #define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0 |
32758 | #define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
32759 | //PA_SC_PERFCOUNTER4_HI |
32760 | #define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0 |
32761 | #define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
32762 | //PA_SC_PERFCOUNTER5_LO |
32763 | #define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0 |
32764 | #define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
32765 | //PA_SC_PERFCOUNTER5_HI |
32766 | #define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0 |
32767 | #define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
32768 | //PA_SC_PERFCOUNTER6_LO |
32769 | #define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x0 |
32770 | #define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
32771 | //PA_SC_PERFCOUNTER6_HI |
32772 | #define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x0 |
32773 | #define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
32774 | //PA_SC_PERFCOUNTER7_LO |
32775 | #define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x0 |
32776 | #define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
32777 | //PA_SC_PERFCOUNTER7_HI |
32778 | #define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x0 |
32779 | #define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
32780 | //SPI_PERFCOUNTER0_HI |
32781 | #define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
32782 | #define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
32783 | //SPI_PERFCOUNTER0_LO |
32784 | #define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
32785 | #define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
32786 | //SPI_PERFCOUNTER1_HI |
32787 | #define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
32788 | #define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
32789 | //SPI_PERFCOUNTER1_LO |
32790 | #define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
32791 | #define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
32792 | //SPI_PERFCOUNTER2_HI |
32793 | #define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 |
32794 | #define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
32795 | //SPI_PERFCOUNTER2_LO |
32796 | #define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 |
32797 | #define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
32798 | //SPI_PERFCOUNTER3_HI |
32799 | #define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 |
32800 | #define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
32801 | //SPI_PERFCOUNTER3_LO |
32802 | #define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 |
32803 | #define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
32804 | //SPI_PERFCOUNTER4_HI |
32805 | #define SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0 |
32806 | #define SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
32807 | //SPI_PERFCOUNTER4_LO |
32808 | #define SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0 |
32809 | #define SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
32810 | //SPI_PERFCOUNTER5_HI |
32811 | #define SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0 |
32812 | #define SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
32813 | //SPI_PERFCOUNTER5_LO |
32814 | #define SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0 |
32815 | #define SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
32816 | //PC_PERFCOUNTER0_HI |
32817 | #define PC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
32818 | #define PC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
32819 | //PC_PERFCOUNTER0_LO |
32820 | #define PC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
32821 | #define PC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
32822 | //PC_PERFCOUNTER1_HI |
32823 | #define PC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
32824 | #define PC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
32825 | //PC_PERFCOUNTER1_LO |
32826 | #define PC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
32827 | #define PC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
32828 | //PC_PERFCOUNTER2_HI |
32829 | #define PC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 |
32830 | #define PC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
32831 | //PC_PERFCOUNTER2_LO |
32832 | #define PC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 |
32833 | #define PC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
32834 | //PC_PERFCOUNTER3_HI |
32835 | #define PC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 |
32836 | #define PC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
32837 | //PC_PERFCOUNTER3_LO |
32838 | #define PC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 |
32839 | #define PC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
32840 | //SQ_PERFCOUNTER0_LO |
32841 | #define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
32842 | #define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
32843 | //SQ_PERFCOUNTER1_LO |
32844 | #define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
32845 | #define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
32846 | //SQ_PERFCOUNTER2_LO |
32847 | #define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 |
32848 | #define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
32849 | //SQ_PERFCOUNTER3_LO |
32850 | #define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 |
32851 | #define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
32852 | //SQ_PERFCOUNTER4_LO |
32853 | #define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0 |
32854 | #define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
32855 | //SQ_PERFCOUNTER5_LO |
32856 | #define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0 |
32857 | #define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
32858 | //SQ_PERFCOUNTER6_LO |
32859 | #define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x0 |
32860 | #define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
32861 | //SQ_PERFCOUNTER7_LO |
32862 | #define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x0 |
32863 | #define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
32864 | //SQG_PERFCOUNTER0_LO |
32865 | #define SQG_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
32866 | #define SQG_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
32867 | //SQG_PERFCOUNTER0_HI |
32868 | #define SQG_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
32869 | #define SQG_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
32870 | //SQG_PERFCOUNTER1_LO |
32871 | #define SQG_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
32872 | #define SQG_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
32873 | //SQG_PERFCOUNTER1_HI |
32874 | #define SQG_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
32875 | #define SQG_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
32876 | //SQG_PERFCOUNTER2_LO |
32877 | #define SQG_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 |
32878 | #define SQG_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
32879 | //SQG_PERFCOUNTER2_HI |
32880 | #define SQG_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 |
32881 | #define SQG_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
32882 | //SQG_PERFCOUNTER3_LO |
32883 | #define SQG_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 |
32884 | #define SQG_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
32885 | //SQG_PERFCOUNTER3_HI |
32886 | #define SQG_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 |
32887 | #define SQG_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
32888 | //SQG_PERFCOUNTER4_LO |
32889 | #define SQG_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0 |
32890 | #define SQG_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
32891 | //SQG_PERFCOUNTER4_HI |
32892 | #define SQG_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0 |
32893 | #define SQG_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
32894 | //SQG_PERFCOUNTER5_LO |
32895 | #define SQG_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0 |
32896 | #define SQG_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
32897 | //SQG_PERFCOUNTER5_HI |
32898 | #define SQG_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0 |
32899 | #define SQG_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
32900 | //SQG_PERFCOUNTER6_LO |
32901 | #define SQG_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x0 |
32902 | #define SQG_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
32903 | //SQG_PERFCOUNTER6_HI |
32904 | #define SQG_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x0 |
32905 | #define SQG_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
32906 | //SQG_PERFCOUNTER7_LO |
32907 | #define SQG_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x0 |
32908 | #define SQG_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
32909 | //SQG_PERFCOUNTER7_HI |
32910 | #define SQG_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x0 |
32911 | #define SQG_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
32912 | //SX_PERFCOUNTER0_LO |
32913 | #define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
32914 | #define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
32915 | //SX_PERFCOUNTER0_HI |
32916 | #define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
32917 | #define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
32918 | //SX_PERFCOUNTER1_LO |
32919 | #define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
32920 | #define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
32921 | //SX_PERFCOUNTER1_HI |
32922 | #define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
32923 | #define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
32924 | //SX_PERFCOUNTER2_LO |
32925 | #define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 |
32926 | #define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
32927 | //SX_PERFCOUNTER2_HI |
32928 | #define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 |
32929 | #define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
32930 | //SX_PERFCOUNTER3_LO |
32931 | #define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 |
32932 | #define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
32933 | //SX_PERFCOUNTER3_HI |
32934 | #define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 |
32935 | #define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
32936 | //GCEA_PERFCOUNTER2_LO |
32937 | #define GCEA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 |
32938 | #define GCEA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
32939 | //GCEA_PERFCOUNTER2_HI |
32940 | #define GCEA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 |
32941 | #define GCEA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
32942 | //GCEA_PERFCOUNTER_LO |
32943 | #define GCEA_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 |
32944 | #define GCEA_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL |
32945 | //GCEA_PERFCOUNTER_HI |
32946 | #define GCEA_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 |
32947 | #define GCEA_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 |
32948 | #define GCEA_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL |
32949 | #define GCEA_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L |
32950 | //GDS_PERFCOUNTER0_LO |
32951 | #define GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
32952 | #define GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
32953 | //GDS_PERFCOUNTER0_HI |
32954 | #define GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
32955 | #define GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
32956 | //GDS_PERFCOUNTER1_LO |
32957 | #define GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
32958 | #define GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
32959 | //GDS_PERFCOUNTER1_HI |
32960 | #define GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
32961 | #define GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
32962 | //GDS_PERFCOUNTER2_LO |
32963 | #define GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 |
32964 | #define GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
32965 | //GDS_PERFCOUNTER2_HI |
32966 | #define GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 |
32967 | #define GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
32968 | //GDS_PERFCOUNTER3_LO |
32969 | #define GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 |
32970 | #define GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
32971 | //GDS_PERFCOUNTER3_HI |
32972 | #define GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 |
32973 | #define GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
32974 | //TA_PERFCOUNTER0_LO |
32975 | #define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
32976 | #define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
32977 | //TA_PERFCOUNTER0_HI |
32978 | #define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
32979 | #define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
32980 | //TA_PERFCOUNTER1_LO |
32981 | #define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
32982 | #define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
32983 | //TA_PERFCOUNTER1_HI |
32984 | #define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
32985 | #define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
32986 | //TD_PERFCOUNTER0_LO |
32987 | #define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
32988 | #define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
32989 | //TD_PERFCOUNTER0_HI |
32990 | #define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
32991 | #define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
32992 | //TD_PERFCOUNTER1_LO |
32993 | #define TD_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
32994 | #define TD_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
32995 | //TD_PERFCOUNTER1_HI |
32996 | #define TD_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
32997 | #define TD_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
32998 | //TCP_PERFCOUNTER0_LO |
32999 | #define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
33000 | #define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
33001 | //TCP_PERFCOUNTER0_HI |
33002 | #define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
33003 | #define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
33004 | //TCP_PERFCOUNTER1_LO |
33005 | #define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
33006 | #define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
33007 | //TCP_PERFCOUNTER1_HI |
33008 | #define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
33009 | #define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
33010 | //TCP_PERFCOUNTER2_LO |
33011 | #define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 |
33012 | #define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
33013 | //TCP_PERFCOUNTER2_HI |
33014 | #define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 |
33015 | #define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
33016 | //TCP_PERFCOUNTER3_LO |
33017 | #define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 |
33018 | #define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
33019 | //TCP_PERFCOUNTER3_HI |
33020 | #define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 |
33021 | #define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
33022 | //TCP_PERFCOUNTER_FILTER |
33023 | #define TCP_PERFCOUNTER_FILTER__BUFFER__SHIFT 0x0 |
33024 | #define TCP_PERFCOUNTER_FILTER__FLAT__SHIFT 0x1 |
33025 | #define TCP_PERFCOUNTER_FILTER__DIM__SHIFT 0x2 |
33026 | #define TCP_PERFCOUNTER_FILTER__DATA_FORMAT__SHIFT 0x5 |
33027 | #define TCP_PERFCOUNTER_FILTER__NUM_FORMAT__SHIFT 0xd |
33028 | #define TCP_PERFCOUNTER_FILTER__SW_MODE__SHIFT 0x11 |
33029 | #define TCP_PERFCOUNTER_FILTER__NUM_SAMPLES__SHIFT 0x16 |
33030 | #define TCP_PERFCOUNTER_FILTER__OPCODE_TYPE__SHIFT 0x18 |
33031 | #define TCP_PERFCOUNTER_FILTER__SLC__SHIFT 0x1b |
33032 | #define TCP_PERFCOUNTER_FILTER__DLC__SHIFT 0x1c |
33033 | #define TCP_PERFCOUNTER_FILTER__GLC__SHIFT 0x1d |
33034 | #define TCP_PERFCOUNTER_FILTER__COMPRESSION_ENABLE__SHIFT 0x1e |
33035 | #define TCP_PERFCOUNTER_FILTER__BUFFER_MASK 0x00000001L |
33036 | #define TCP_PERFCOUNTER_FILTER__FLAT_MASK 0x00000002L |
33037 | #define TCP_PERFCOUNTER_FILTER__DIM_MASK 0x0000001CL |
33038 | #define TCP_PERFCOUNTER_FILTER__DATA_FORMAT_MASK 0x00000FE0L |
33039 | #define TCP_PERFCOUNTER_FILTER__NUM_FORMAT_MASK 0x0001E000L |
33040 | #define TCP_PERFCOUNTER_FILTER__SW_MODE_MASK 0x003E0000L |
33041 | #define TCP_PERFCOUNTER_FILTER__NUM_SAMPLES_MASK 0x00C00000L |
33042 | #define TCP_PERFCOUNTER_FILTER__OPCODE_TYPE_MASK 0x07000000L |
33043 | #define TCP_PERFCOUNTER_FILTER__SLC_MASK 0x08000000L |
33044 | #define TCP_PERFCOUNTER_FILTER__DLC_MASK 0x10000000L |
33045 | #define TCP_PERFCOUNTER_FILTER__GLC_MASK 0x20000000L |
33046 | #define TCP_PERFCOUNTER_FILTER__COMPRESSION_ENABLE_MASK 0x40000000L |
33047 | //TCP_PERFCOUNTER_FILTER2 |
33048 | #define TCP_PERFCOUNTER_FILTER2__REQ_MODE__SHIFT 0x0 |
33049 | #define TCP_PERFCOUNTER_FILTER2__REQ_MODE_MASK 0x00000007L |
33050 | //TCP_PERFCOUNTER_FILTER_EN |
33051 | #define TCP_PERFCOUNTER_FILTER_EN__BUFFER__SHIFT 0x0 |
33052 | #define TCP_PERFCOUNTER_FILTER_EN__FLAT__SHIFT 0x1 |
33053 | #define TCP_PERFCOUNTER_FILTER_EN__DIM__SHIFT 0x2 |
33054 | #define TCP_PERFCOUNTER_FILTER_EN__DATA_FORMAT__SHIFT 0x3 |
33055 | #define TCP_PERFCOUNTER_FILTER_EN__NUM_FORMAT__SHIFT 0x4 |
33056 | #define TCP_PERFCOUNTER_FILTER_EN__SW_MODE__SHIFT 0x5 |
33057 | #define TCP_PERFCOUNTER_FILTER_EN__NUM_SAMPLES__SHIFT 0x6 |
33058 | #define TCP_PERFCOUNTER_FILTER_EN__OPCODE_TYPE__SHIFT 0x7 |
33059 | #define TCP_PERFCOUNTER_FILTER_EN__SLC__SHIFT 0x8 |
33060 | #define TCP_PERFCOUNTER_FILTER_EN__DLC__SHIFT 0x9 |
33061 | #define TCP_PERFCOUNTER_FILTER_EN__GLC__SHIFT 0xa |
33062 | #define TCP_PERFCOUNTER_FILTER_EN__COMPRESSION_ENABLE__SHIFT 0xb |
33063 | #define TCP_PERFCOUNTER_FILTER_EN__REQ_MODE__SHIFT 0xc |
33064 | #define TCP_PERFCOUNTER_FILTER_EN__BUFFER_MASK 0x00000001L |
33065 | #define TCP_PERFCOUNTER_FILTER_EN__FLAT_MASK 0x00000002L |
33066 | #define TCP_PERFCOUNTER_FILTER_EN__DIM_MASK 0x00000004L |
33067 | #define TCP_PERFCOUNTER_FILTER_EN__DATA_FORMAT_MASK 0x00000008L |
33068 | #define TCP_PERFCOUNTER_FILTER_EN__NUM_FORMAT_MASK 0x00000010L |
33069 | #define TCP_PERFCOUNTER_FILTER_EN__SW_MODE_MASK 0x00000020L |
33070 | #define TCP_PERFCOUNTER_FILTER_EN__NUM_SAMPLES_MASK 0x00000040L |
33071 | #define TCP_PERFCOUNTER_FILTER_EN__OPCODE_TYPE_MASK 0x00000080L |
33072 | #define TCP_PERFCOUNTER_FILTER_EN__SLC_MASK 0x00000100L |
33073 | #define TCP_PERFCOUNTER_FILTER_EN__DLC_MASK 0x00000200L |
33074 | #define TCP_PERFCOUNTER_FILTER_EN__GLC_MASK 0x00000400L |
33075 | #define TCP_PERFCOUNTER_FILTER_EN__COMPRESSION_ENABLE_MASK 0x00000800L |
33076 | #define TCP_PERFCOUNTER_FILTER_EN__REQ_MODE_MASK 0x00001000L |
33077 | //GL2C_PERFCOUNTER0_LO |
33078 | #define GL2C_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
33079 | #define GL2C_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
33080 | //GL2C_PERFCOUNTER0_HI |
33081 | #define GL2C_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
33082 | #define GL2C_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
33083 | //GL2C_PERFCOUNTER1_LO |
33084 | #define GL2C_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
33085 | #define GL2C_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
33086 | //GL2C_PERFCOUNTER1_HI |
33087 | #define GL2C_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
33088 | #define GL2C_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
33089 | //GL2C_PERFCOUNTER2_LO |
33090 | #define GL2C_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 |
33091 | #define GL2C_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
33092 | //GL2C_PERFCOUNTER2_HI |
33093 | #define GL2C_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 |
33094 | #define GL2C_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
33095 | //GL2C_PERFCOUNTER3_LO |
33096 | #define GL2C_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 |
33097 | #define GL2C_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
33098 | //GL2C_PERFCOUNTER3_HI |
33099 | #define GL2C_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 |
33100 | #define GL2C_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
33101 | //GL2A_PERFCOUNTER0_LO |
33102 | #define GL2A_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
33103 | #define GL2A_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
33104 | //GL2A_PERFCOUNTER0_HI |
33105 | #define GL2A_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
33106 | #define GL2A_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
33107 | //GL2A_PERFCOUNTER1_LO |
33108 | #define GL2A_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
33109 | #define GL2A_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
33110 | //GL2A_PERFCOUNTER1_HI |
33111 | #define GL2A_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
33112 | #define GL2A_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
33113 | //GL2A_PERFCOUNTER2_LO |
33114 | #define GL2A_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 |
33115 | #define GL2A_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
33116 | //GL2A_PERFCOUNTER2_HI |
33117 | #define GL2A_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 |
33118 | #define GL2A_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
33119 | //GL2A_PERFCOUNTER3_LO |
33120 | #define GL2A_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 |
33121 | #define GL2A_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
33122 | //GL2A_PERFCOUNTER3_HI |
33123 | #define GL2A_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 |
33124 | #define GL2A_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
33125 | //GL1C_PERFCOUNTER0_LO |
33126 | #define GL1C_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
33127 | #define GL1C_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
33128 | //GL1C_PERFCOUNTER0_HI |
33129 | #define GL1C_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
33130 | #define GL1C_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
33131 | //GL1C_PERFCOUNTER1_LO |
33132 | #define GL1C_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
33133 | #define GL1C_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
33134 | //GL1C_PERFCOUNTER1_HI |
33135 | #define GL1C_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
33136 | #define GL1C_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
33137 | //GL1C_PERFCOUNTER2_LO |
33138 | #define GL1C_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 |
33139 | #define GL1C_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
33140 | //GL1C_PERFCOUNTER2_HI |
33141 | #define GL1C_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 |
33142 | #define GL1C_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
33143 | //GL1C_PERFCOUNTER3_LO |
33144 | #define GL1C_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 |
33145 | #define GL1C_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
33146 | //GL1C_PERFCOUNTER3_HI |
33147 | #define GL1C_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 |
33148 | #define GL1C_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
33149 | //CHC_PERFCOUNTER0_LO |
33150 | #define CHC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
33151 | #define CHC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
33152 | //CHC_PERFCOUNTER0_HI |
33153 | #define CHC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
33154 | #define CHC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
33155 | //CHC_PERFCOUNTER1_LO |
33156 | #define CHC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
33157 | #define CHC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
33158 | //CHC_PERFCOUNTER1_HI |
33159 | #define CHC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
33160 | #define CHC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
33161 | //CHC_PERFCOUNTER2_LO |
33162 | #define CHC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 |
33163 | #define CHC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
33164 | //CHC_PERFCOUNTER2_HI |
33165 | #define CHC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 |
33166 | #define CHC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
33167 | //CHC_PERFCOUNTER3_LO |
33168 | #define CHC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 |
33169 | #define CHC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
33170 | //CHC_PERFCOUNTER3_HI |
33171 | #define CHC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 |
33172 | #define CHC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
33173 | //CHCG_PERFCOUNTER0_LO |
33174 | #define CHCG_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
33175 | #define CHCG_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
33176 | //CHCG_PERFCOUNTER0_HI |
33177 | #define CHCG_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
33178 | #define CHCG_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
33179 | //CHCG_PERFCOUNTER1_LO |
33180 | #define CHCG_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
33181 | #define CHCG_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
33182 | //CHCG_PERFCOUNTER1_HI |
33183 | #define CHCG_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
33184 | #define CHCG_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
33185 | //CHCG_PERFCOUNTER2_LO |
33186 | #define CHCG_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 |
33187 | #define CHCG_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
33188 | //CHCG_PERFCOUNTER2_HI |
33189 | #define CHCG_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 |
33190 | #define CHCG_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
33191 | //CHCG_PERFCOUNTER3_LO |
33192 | #define CHCG_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 |
33193 | #define CHCG_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
33194 | //CHCG_PERFCOUNTER3_HI |
33195 | #define CHCG_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 |
33196 | #define CHCG_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
33197 | //CB_PERFCOUNTER0_LO |
33198 | #define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
33199 | #define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
33200 | //CB_PERFCOUNTER0_HI |
33201 | #define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
33202 | #define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
33203 | //CB_PERFCOUNTER1_LO |
33204 | #define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
33205 | #define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
33206 | //CB_PERFCOUNTER1_HI |
33207 | #define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
33208 | #define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
33209 | //CB_PERFCOUNTER2_LO |
33210 | #define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 |
33211 | #define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
33212 | //CB_PERFCOUNTER2_HI |
33213 | #define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 |
33214 | #define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
33215 | //CB_PERFCOUNTER3_LO |
33216 | #define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 |
33217 | #define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
33218 | //CB_PERFCOUNTER3_HI |
33219 | #define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 |
33220 | #define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
33221 | //DB_PERFCOUNTER0_LO |
33222 | #define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
33223 | #define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
33224 | //DB_PERFCOUNTER0_HI |
33225 | #define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
33226 | #define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
33227 | //DB_PERFCOUNTER1_LO |
33228 | #define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
33229 | #define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
33230 | //DB_PERFCOUNTER1_HI |
33231 | #define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
33232 | #define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
33233 | //DB_PERFCOUNTER2_LO |
33234 | #define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 |
33235 | #define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
33236 | //DB_PERFCOUNTER2_HI |
33237 | #define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 |
33238 | #define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
33239 | //DB_PERFCOUNTER3_LO |
33240 | #define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 |
33241 | #define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
33242 | //DB_PERFCOUNTER3_HI |
33243 | #define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 |
33244 | #define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
33245 | //RLC_PERFCOUNTER0_LO |
33246 | #define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
33247 | #define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
33248 | //RLC_PERFCOUNTER0_HI |
33249 | #define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
33250 | #define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
33251 | //RLC_PERFCOUNTER1_LO |
33252 | #define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
33253 | #define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
33254 | //RLC_PERFCOUNTER1_HI |
33255 | #define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
33256 | #define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
33257 | //RMI_PERFCOUNTER0_LO |
33258 | #define RMI_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
33259 | #define RMI_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
33260 | //RMI_PERFCOUNTER0_HI |
33261 | #define RMI_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
33262 | #define RMI_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
33263 | //RMI_PERFCOUNTER1_LO |
33264 | #define RMI_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
33265 | #define RMI_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
33266 | //RMI_PERFCOUNTER1_HI |
33267 | #define RMI_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
33268 | #define RMI_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
33269 | //RMI_PERFCOUNTER2_LO |
33270 | #define RMI_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 |
33271 | #define RMI_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
33272 | //RMI_PERFCOUNTER2_HI |
33273 | #define RMI_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 |
33274 | #define RMI_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
33275 | //RMI_PERFCOUNTER3_LO |
33276 | #define RMI_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 |
33277 | #define RMI_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
33278 | //RMI_PERFCOUNTER3_HI |
33279 | #define RMI_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 |
33280 | #define RMI_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
33281 | //GCR_PERFCOUNTER0_LO |
33282 | #define GCR_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
33283 | #define GCR_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
33284 | //GCR_PERFCOUNTER0_HI |
33285 | #define GCR_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
33286 | #define GCR_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
33287 | //GCR_PERFCOUNTER1_LO |
33288 | #define GCR_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
33289 | #define GCR_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
33290 | //GCR_PERFCOUNTER1_HI |
33291 | #define GCR_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
33292 | #define GCR_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
33293 | //PA_PH_PERFCOUNTER0_LO |
33294 | #define PA_PH_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
33295 | #define PA_PH_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
33296 | //PA_PH_PERFCOUNTER0_HI |
33297 | #define PA_PH_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
33298 | #define PA_PH_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
33299 | //PA_PH_PERFCOUNTER1_LO |
33300 | #define PA_PH_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
33301 | #define PA_PH_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
33302 | //PA_PH_PERFCOUNTER1_HI |
33303 | #define PA_PH_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
33304 | #define PA_PH_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
33305 | //PA_PH_PERFCOUNTER2_LO |
33306 | #define PA_PH_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 |
33307 | #define PA_PH_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
33308 | //PA_PH_PERFCOUNTER2_HI |
33309 | #define PA_PH_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 |
33310 | #define PA_PH_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
33311 | //PA_PH_PERFCOUNTER3_LO |
33312 | #define PA_PH_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 |
33313 | #define PA_PH_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
33314 | //PA_PH_PERFCOUNTER3_HI |
33315 | #define PA_PH_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 |
33316 | #define PA_PH_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
33317 | //PA_PH_PERFCOUNTER4_LO |
33318 | #define PA_PH_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0 |
33319 | #define PA_PH_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
33320 | //PA_PH_PERFCOUNTER4_HI |
33321 | #define PA_PH_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0 |
33322 | #define PA_PH_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
33323 | //PA_PH_PERFCOUNTER5_LO |
33324 | #define PA_PH_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0 |
33325 | #define PA_PH_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
33326 | //PA_PH_PERFCOUNTER5_HI |
33327 | #define PA_PH_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0 |
33328 | #define PA_PH_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
33329 | //PA_PH_PERFCOUNTER6_LO |
33330 | #define PA_PH_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x0 |
33331 | #define PA_PH_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
33332 | //PA_PH_PERFCOUNTER6_HI |
33333 | #define PA_PH_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x0 |
33334 | #define PA_PH_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
33335 | //PA_PH_PERFCOUNTER7_LO |
33336 | #define PA_PH_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x0 |
33337 | #define PA_PH_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
33338 | //PA_PH_PERFCOUNTER7_HI |
33339 | #define PA_PH_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x0 |
33340 | #define PA_PH_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
33341 | //UTCL1_PERFCOUNTER0_LO |
33342 | #define UTCL1_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
33343 | #define UTCL1_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
33344 | //UTCL1_PERFCOUNTER0_HI |
33345 | #define UTCL1_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
33346 | #define UTCL1_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
33347 | //UTCL1_PERFCOUNTER1_LO |
33348 | #define UTCL1_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
33349 | #define UTCL1_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
33350 | //UTCL1_PERFCOUNTER1_HI |
33351 | #define UTCL1_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
33352 | #define UTCL1_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
33353 | //UTCL1_PERFCOUNTER2_LO |
33354 | #define UTCL1_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 |
33355 | #define UTCL1_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
33356 | //UTCL1_PERFCOUNTER2_HI |
33357 | #define UTCL1_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 |
33358 | #define UTCL1_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
33359 | //UTCL1_PERFCOUNTER3_LO |
33360 | #define UTCL1_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 |
33361 | #define UTCL1_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
33362 | //UTCL1_PERFCOUNTER3_HI |
33363 | #define UTCL1_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 |
33364 | #define UTCL1_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
33365 | //GL1A_PERFCOUNTER0_LO |
33366 | #define GL1A_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
33367 | #define GL1A_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
33368 | //GL1A_PERFCOUNTER0_HI |
33369 | #define GL1A_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
33370 | #define GL1A_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
33371 | //GL1A_PERFCOUNTER1_LO |
33372 | #define GL1A_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
33373 | #define GL1A_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
33374 | //GL1A_PERFCOUNTER1_HI |
33375 | #define GL1A_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
33376 | #define GL1A_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
33377 | //GL1A_PERFCOUNTER2_LO |
33378 | #define GL1A_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 |
33379 | #define GL1A_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
33380 | //GL1A_PERFCOUNTER2_HI |
33381 | #define GL1A_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 |
33382 | #define GL1A_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
33383 | //GL1A_PERFCOUNTER3_LO |
33384 | #define GL1A_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 |
33385 | #define GL1A_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
33386 | //GL1A_PERFCOUNTER3_HI |
33387 | #define GL1A_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 |
33388 | #define GL1A_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
33389 | //GL1H_PERFCOUNTER0_LO |
33390 | #define GL1H_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
33391 | #define GL1H_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
33392 | //GL1H_PERFCOUNTER0_HI |
33393 | #define GL1H_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
33394 | #define GL1H_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
33395 | //GL1H_PERFCOUNTER1_LO |
33396 | #define GL1H_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
33397 | #define GL1H_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
33398 | //GL1H_PERFCOUNTER1_HI |
33399 | #define GL1H_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
33400 | #define GL1H_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
33401 | //GL1H_PERFCOUNTER2_LO |
33402 | #define GL1H_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 |
33403 | #define GL1H_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
33404 | //GL1H_PERFCOUNTER2_HI |
33405 | #define GL1H_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 |
33406 | #define GL1H_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
33407 | //GL1H_PERFCOUNTER3_LO |
33408 | #define GL1H_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 |
33409 | #define GL1H_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
33410 | //GL1H_PERFCOUNTER3_HI |
33411 | #define GL1H_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 |
33412 | #define GL1H_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
33413 | //CHA_PERFCOUNTER0_LO |
33414 | #define CHA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 |
33415 | #define CHA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
33416 | //CHA_PERFCOUNTER0_HI |
33417 | #define CHA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 |
33418 | #define CHA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
33419 | //CHA_PERFCOUNTER1_LO |
33420 | #define CHA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 |
33421 | #define CHA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
33422 | //CHA_PERFCOUNTER1_HI |
33423 | #define CHA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 |
33424 | #define CHA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
33425 | //CHA_PERFCOUNTER2_LO |
33426 | #define CHA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 |
33427 | #define CHA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
33428 | //CHA_PERFCOUNTER2_HI |
33429 | #define CHA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 |
33430 | #define CHA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
33431 | //CHA_PERFCOUNTER3_LO |
33432 | #define CHA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 |
33433 | #define CHA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
33434 | //CHA_PERFCOUNTER3_HI |
33435 | #define CHA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 |
33436 | #define CHA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
33437 | //GUS_PERFCOUNTER2_LO |
33438 | #define GUS_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 |
33439 | #define GUS_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL |
33440 | //GUS_PERFCOUNTER2_HI |
33441 | #define GUS_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 |
33442 | #define GUS_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL |
33443 | //GUS_PERFCOUNTER_LO |
33444 | #define GUS_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 |
33445 | #define GUS_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL |
33446 | //GUS_PERFCOUNTER_HI |
33447 | #define GUS_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 |
33448 | #define GUS_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 |
33449 | #define GUS_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL |
33450 | #define GUS_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L |
33451 | |
33452 | |
33453 | // addressBlock: gc_perfsdec |
33454 | //CPG_PERFCOUNTER1_SELECT |
33455 | #define CPG_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
33456 | #define CPG_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14 |
33457 | #define CPG_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x1c |
33458 | #define CPG_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL |
33459 | #define CPG_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00F00000L |
33460 | #define CPG_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xF0000000L |
33461 | //CPG_PERFCOUNTER0_SELECT1 |
33462 | #define CPG_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
33463 | #define CPG_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
33464 | #define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT 0x18 |
33465 | #define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT 0x1c |
33466 | #define CPG_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL |
33467 | #define CPG_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
33468 | #define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK 0x0F000000L |
33469 | #define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK 0xF0000000L |
33470 | //CPG_PERFCOUNTER0_SELECT |
33471 | #define CPG_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
33472 | #define CPG_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
33473 | #define CPG_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14 |
33474 | #define CPG_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT 0x18 |
33475 | #define CPG_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT 0x1c |
33476 | #define CPG_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL |
33477 | #define CPG_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L |
33478 | #define CPG_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L |
33479 | #define CPG_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK 0x0F000000L |
33480 | #define CPG_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK 0xF0000000L |
33481 | //CPC_PERFCOUNTER1_SELECT |
33482 | #define CPC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
33483 | #define CPC_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14 |
33484 | #define CPC_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x1c |
33485 | #define CPC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL |
33486 | #define CPC_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00F00000L |
33487 | #define CPC_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xF0000000L |
33488 | //CPC_PERFCOUNTER0_SELECT1 |
33489 | #define CPC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
33490 | #define CPC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
33491 | #define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT 0x18 |
33492 | #define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT 0x1c |
33493 | #define CPC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL |
33494 | #define CPC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
33495 | #define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK 0x0F000000L |
33496 | #define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK 0xF0000000L |
33497 | //CPF_PERFCOUNTER1_SELECT |
33498 | #define CPF_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
33499 | #define CPF_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14 |
33500 | #define CPF_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x1c |
33501 | #define CPF_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL |
33502 | #define CPF_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00F00000L |
33503 | #define CPF_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xF0000000L |
33504 | //CPF_PERFCOUNTER0_SELECT1 |
33505 | #define CPF_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
33506 | #define CPF_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
33507 | #define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT 0x18 |
33508 | #define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT 0x1c |
33509 | #define CPF_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL |
33510 | #define CPF_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
33511 | #define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK 0x0F000000L |
33512 | #define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK 0xF0000000L |
33513 | //CPF_PERFCOUNTER0_SELECT |
33514 | #define CPF_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
33515 | #define CPF_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
33516 | #define CPF_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14 |
33517 | #define CPF_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT 0x18 |
33518 | #define CPF_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT 0x1c |
33519 | #define CPF_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL |
33520 | #define CPF_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L |
33521 | #define CPF_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L |
33522 | #define CPF_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK 0x0F000000L |
33523 | #define CPF_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK 0xF0000000L |
33524 | //CP_PERFMON_CNTL |
33525 | #define CP_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 |
33526 | #define CP_PERFMON_CNTL__SPM_PERFMON_STATE__SHIFT 0x4 |
33527 | #define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT 0x8 |
33528 | #define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa |
33529 | #define CP_PERFMON_CNTL__PERFMON_STATE_MASK 0x0000000FL |
33530 | #define CP_PERFMON_CNTL__SPM_PERFMON_STATE_MASK 0x000000F0L |
33531 | #define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK 0x00000300L |
33532 | #define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x00000400L |
33533 | //CPC_PERFCOUNTER0_SELECT |
33534 | #define CPC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
33535 | #define CPC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
33536 | #define CPC_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14 |
33537 | #define CPC_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT 0x18 |
33538 | #define CPC_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT 0x1c |
33539 | #define CPC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL |
33540 | #define CPC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L |
33541 | #define CPC_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L |
33542 | #define CPC_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK 0x0F000000L |
33543 | #define CPC_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK 0xF0000000L |
33544 | //CPF_TC_PERF_COUNTER_WINDOW_SELECT |
33545 | #define CPF_TC_PERF_COUNTER_WINDOW_SELECT__INDEX__SHIFT 0x0 |
33546 | #define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS__SHIFT 0x1e |
33547 | #define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE__SHIFT 0x1f |
33548 | #define CPF_TC_PERF_COUNTER_WINDOW_SELECT__INDEX_MASK 0x00000007L |
33549 | #define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS_MASK 0x40000000L |
33550 | #define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE_MASK 0x80000000L |
33551 | //CPG_TC_PERF_COUNTER_WINDOW_SELECT |
33552 | #define CPG_TC_PERF_COUNTER_WINDOW_SELECT__INDEX__SHIFT 0x0 |
33553 | #define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS__SHIFT 0x1e |
33554 | #define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE__SHIFT 0x1f |
33555 | #define CPG_TC_PERF_COUNTER_WINDOW_SELECT__INDEX_MASK 0x0000001FL |
33556 | #define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS_MASK 0x40000000L |
33557 | #define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE_MASK 0x80000000L |
33558 | //CPF_LATENCY_STATS_SELECT |
33559 | #define CPF_LATENCY_STATS_SELECT__INDEX__SHIFT 0x0 |
33560 | #define CPF_LATENCY_STATS_SELECT__CLEAR__SHIFT 0x1e |
33561 | #define CPF_LATENCY_STATS_SELECT__ENABLE__SHIFT 0x1f |
33562 | #define CPF_LATENCY_STATS_SELECT__INDEX_MASK 0x0000000FL |
33563 | #define CPF_LATENCY_STATS_SELECT__CLEAR_MASK 0x40000000L |
33564 | #define CPF_LATENCY_STATS_SELECT__ENABLE_MASK 0x80000000L |
33565 | //CPG_LATENCY_STATS_SELECT |
33566 | #define CPG_LATENCY_STATS_SELECT__INDEX__SHIFT 0x0 |
33567 | #define CPG_LATENCY_STATS_SELECT__CLEAR__SHIFT 0x1e |
33568 | #define CPG_LATENCY_STATS_SELECT__ENABLE__SHIFT 0x1f |
33569 | #define CPG_LATENCY_STATS_SELECT__INDEX_MASK 0x0000001FL |
33570 | #define CPG_LATENCY_STATS_SELECT__CLEAR_MASK 0x40000000L |
33571 | #define CPG_LATENCY_STATS_SELECT__ENABLE_MASK 0x80000000L |
33572 | //CPC_LATENCY_STATS_SELECT |
33573 | #define CPC_LATENCY_STATS_SELECT__INDEX__SHIFT 0x0 |
33574 | #define CPC_LATENCY_STATS_SELECT__CLEAR__SHIFT 0x1e |
33575 | #define CPC_LATENCY_STATS_SELECT__ENABLE__SHIFT 0x1f |
33576 | #define CPC_LATENCY_STATS_SELECT__INDEX_MASK 0x0000001FL |
33577 | #define CPC_LATENCY_STATS_SELECT__CLEAR_MASK 0x40000000L |
33578 | #define CPC_LATENCY_STATS_SELECT__ENABLE_MASK 0x80000000L |
33579 | //CPC_TC_PERF_COUNTER_WINDOW_SELECT |
33580 | #define CPC_TC_PERF_COUNTER_WINDOW_SELECT__INDEX__SHIFT 0x0 |
33581 | #define CPC_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS__SHIFT 0x1e |
33582 | #define CPC_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE__SHIFT 0x1f |
33583 | #define CPC_TC_PERF_COUNTER_WINDOW_SELECT__INDEX_MASK 0x0000001FL |
33584 | #define CPC_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS_MASK 0x40000000L |
33585 | #define CPC_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE_MASK 0x80000000L |
33586 | //CP_DRAW_OBJECT |
33587 | #define CP_DRAW_OBJECT__OBJECT__SHIFT 0x0 |
33588 | #define CP_DRAW_OBJECT__OBJECT_MASK 0xFFFFFFFFL |
33589 | //CP_DRAW_OBJECT_COUNTER |
33590 | #define CP_DRAW_OBJECT_COUNTER__COUNT__SHIFT 0x0 |
33591 | #define CP_DRAW_OBJECT_COUNTER__COUNT_MASK 0x0000FFFFL |
33592 | //CP_DRAW_WINDOW_MASK_HI |
33593 | #define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI__SHIFT 0x0 |
33594 | #define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI_MASK 0xFFFFFFFFL |
33595 | //CP_DRAW_WINDOW_HI |
33596 | #define CP_DRAW_WINDOW_HI__WINDOW_HI__SHIFT 0x0 |
33597 | #define CP_DRAW_WINDOW_HI__WINDOW_HI_MASK 0xFFFFFFFFL |
33598 | //CP_DRAW_WINDOW_LO |
33599 | #define CP_DRAW_WINDOW_LO__MIN__SHIFT 0x0 |
33600 | #define CP_DRAW_WINDOW_LO__MAX__SHIFT 0x10 |
33601 | #define CP_DRAW_WINDOW_LO__MIN_MASK 0x0000FFFFL |
33602 | #define CP_DRAW_WINDOW_LO__MAX_MASK 0xFFFF0000L |
33603 | //CP_DRAW_WINDOW_CNTL |
33604 | #define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX__SHIFT 0x0 |
33605 | #define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN__SHIFT 0x1 |
33606 | #define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI__SHIFT 0x2 |
33607 | #define CP_DRAW_WINDOW_CNTL__MODE__SHIFT 0x8 |
33608 | #define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX_MASK 0x00000001L |
33609 | #define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN_MASK 0x00000002L |
33610 | #define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI_MASK 0x00000004L |
33611 | #define CP_DRAW_WINDOW_CNTL__MODE_MASK 0x00000100L |
33612 | //GRBM_PERFCOUNTER0_SELECT |
33613 | #define GRBM_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
33614 | #define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa |
33615 | #define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb |
33616 | #define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xd |
33617 | #define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xe |
33618 | #define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x10 |
33619 | #define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x11 |
33620 | #define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x12 |
33621 | #define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT 0x13 |
33622 | #define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x14 |
33623 | #define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x15 |
33624 | #define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT 0x16 |
33625 | #define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT 0x18 |
33626 | #define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x19 |
33627 | #define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x1a |
33628 | #define GRBM_PERFCOUNTER0_SELECT__TCP_BUSY_USER_DEFINED_MASK__SHIFT 0x1b |
33629 | #define GRBM_PERFCOUNTER0_SELECT__GE_BUSY_USER_DEFINED_MASK__SHIFT 0x1c |
33630 | #define GRBM_PERFCOUNTER0_SELECT__UTCL2_BUSY_USER_DEFINED_MASK__SHIFT 0x1d |
33631 | #define GRBM_PERFCOUNTER0_SELECT__EA_BUSY_USER_DEFINED_MASK__SHIFT 0x1e |
33632 | #define GRBM_PERFCOUNTER0_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x1f |
33633 | #define GRBM_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x0000003FL |
33634 | #define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L |
33635 | #define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L |
33636 | #define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00002000L |
33637 | #define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00004000L |
33638 | #define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00010000L |
33639 | #define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00020000L |
33640 | #define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00040000L |
33641 | #define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK 0x00080000L |
33642 | #define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00100000L |
33643 | #define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00200000L |
33644 | #define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK 0x00400000L |
33645 | #define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK 0x01000000L |
33646 | #define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x02000000L |
33647 | #define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x04000000L |
33648 | #define GRBM_PERFCOUNTER0_SELECT__TCP_BUSY_USER_DEFINED_MASK_MASK 0x08000000L |
33649 | #define GRBM_PERFCOUNTER0_SELECT__GE_BUSY_USER_DEFINED_MASK_MASK 0x10000000L |
33650 | #define GRBM_PERFCOUNTER0_SELECT__UTCL2_BUSY_USER_DEFINED_MASK_MASK 0x20000000L |
33651 | #define GRBM_PERFCOUNTER0_SELECT__EA_BUSY_USER_DEFINED_MASK_MASK 0x40000000L |
33652 | #define GRBM_PERFCOUNTER0_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x80000000L |
33653 | //GRBM_PERFCOUNTER1_SELECT |
33654 | #define GRBM_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
33655 | #define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa |
33656 | #define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb |
33657 | #define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xd |
33658 | #define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xe |
33659 | #define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x10 |
33660 | #define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x11 |
33661 | #define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x12 |
33662 | #define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT 0x13 |
33663 | #define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x14 |
33664 | #define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x15 |
33665 | #define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT 0x16 |
33666 | #define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT 0x18 |
33667 | #define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x19 |
33668 | #define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x1a |
33669 | #define GRBM_PERFCOUNTER1_SELECT__TCP_BUSY_USER_DEFINED_MASK__SHIFT 0x1b |
33670 | #define GRBM_PERFCOUNTER1_SELECT__GE_BUSY_USER_DEFINED_MASK__SHIFT 0x1c |
33671 | #define GRBM_PERFCOUNTER1_SELECT__UTCL2_BUSY_USER_DEFINED_MASK__SHIFT 0x1d |
33672 | #define GRBM_PERFCOUNTER1_SELECT__EA_BUSY_USER_DEFINED_MASK__SHIFT 0x1e |
33673 | #define GRBM_PERFCOUNTER1_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x1f |
33674 | #define GRBM_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x0000003FL |
33675 | #define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L |
33676 | #define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L |
33677 | #define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00002000L |
33678 | #define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00004000L |
33679 | #define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00010000L |
33680 | #define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00020000L |
33681 | #define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00040000L |
33682 | #define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK 0x00080000L |
33683 | #define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00100000L |
33684 | #define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00200000L |
33685 | #define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK 0x00400000L |
33686 | #define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK 0x01000000L |
33687 | #define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x02000000L |
33688 | #define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x04000000L |
33689 | #define GRBM_PERFCOUNTER1_SELECT__TCP_BUSY_USER_DEFINED_MASK_MASK 0x08000000L |
33690 | #define GRBM_PERFCOUNTER1_SELECT__GE_BUSY_USER_DEFINED_MASK_MASK 0x10000000L |
33691 | #define GRBM_PERFCOUNTER1_SELECT__UTCL2_BUSY_USER_DEFINED_MASK_MASK 0x20000000L |
33692 | #define GRBM_PERFCOUNTER1_SELECT__EA_BUSY_USER_DEFINED_MASK_MASK 0x40000000L |
33693 | #define GRBM_PERFCOUNTER1_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x80000000L |
33694 | //GRBM_SE0_PERFCOUNTER_SELECT |
33695 | #define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0 |
33696 | #define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa |
33697 | #define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb |
33698 | #define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc |
33699 | #define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd |
33700 | #define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf |
33701 | #define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10 |
33702 | #define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11 |
33703 | #define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12 |
33704 | #define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14 |
33705 | #define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15 |
33706 | #define GRBM_SE0_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x16 |
33707 | #define GRBM_SE0_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK__SHIFT 0x17 |
33708 | #define GRBM_SE0_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK__SHIFT 0x18 |
33709 | #define GRBM_SE0_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK__SHIFT 0x19 |
33710 | #define GRBM_SE0_PERFCOUNTER_SELECT__GL1H_BUSY_USER_DEFINED_MASK__SHIFT 0x1a |
33711 | #define GRBM_SE0_PERFCOUNTER_SELECT__PC_BUSY_USER_DEFINED_MASK__SHIFT 0x1b |
33712 | #define GRBM_SE0_PERFCOUNTER_SELECT__SEDC_BUSY_USER_DEFINED_MASK__SHIFT 0x1c |
33713 | #define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x0000003FL |
33714 | #define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L |
33715 | #define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L |
33716 | #define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00001000L |
33717 | #define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00002000L |
33718 | #define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00008000L |
33719 | #define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00010000L |
33720 | #define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00020000L |
33721 | #define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00040000L |
33722 | #define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00100000L |
33723 | #define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x00200000L |
33724 | #define GRBM_SE0_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x00400000L |
33725 | #define GRBM_SE0_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK_MASK 0x00800000L |
33726 | #define GRBM_SE0_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK_MASK 0x01000000L |
33727 | #define GRBM_SE0_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK_MASK 0x02000000L |
33728 | #define GRBM_SE0_PERFCOUNTER_SELECT__GL1H_BUSY_USER_DEFINED_MASK_MASK 0x04000000L |
33729 | #define GRBM_SE0_PERFCOUNTER_SELECT__PC_BUSY_USER_DEFINED_MASK_MASK 0x08000000L |
33730 | #define GRBM_SE0_PERFCOUNTER_SELECT__SEDC_BUSY_USER_DEFINED_MASK_MASK 0x10000000L |
33731 | //GRBM_SE1_PERFCOUNTER_SELECT |
33732 | #define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0 |
33733 | #define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa |
33734 | #define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb |
33735 | #define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc |
33736 | #define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd |
33737 | #define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf |
33738 | #define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10 |
33739 | #define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11 |
33740 | #define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12 |
33741 | #define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14 |
33742 | #define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15 |
33743 | #define GRBM_SE1_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x16 |
33744 | #define GRBM_SE1_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK__SHIFT 0x17 |
33745 | #define GRBM_SE1_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK__SHIFT 0x18 |
33746 | #define GRBM_SE1_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK__SHIFT 0x19 |
33747 | #define GRBM_SE1_PERFCOUNTER_SELECT__GL1H_BUSY_USER_DEFINED_MASK__SHIFT 0x1a |
33748 | #define GRBM_SE1_PERFCOUNTER_SELECT__PC_BUSY_USER_DEFINED_MASK__SHIFT 0x1b |
33749 | #define GRBM_SE1_PERFCOUNTER_SELECT__SEDC_BUSY_USER_DEFINED_MASK__SHIFT 0x1c |
33750 | #define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x0000003FL |
33751 | #define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L |
33752 | #define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L |
33753 | #define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00001000L |
33754 | #define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00002000L |
33755 | #define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00008000L |
33756 | #define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00010000L |
33757 | #define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00020000L |
33758 | #define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00040000L |
33759 | #define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00100000L |
33760 | #define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x00200000L |
33761 | #define GRBM_SE1_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x00400000L |
33762 | #define GRBM_SE1_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK_MASK 0x00800000L |
33763 | #define GRBM_SE1_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK_MASK 0x01000000L |
33764 | #define GRBM_SE1_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK_MASK 0x02000000L |
33765 | #define GRBM_SE1_PERFCOUNTER_SELECT__GL1H_BUSY_USER_DEFINED_MASK_MASK 0x04000000L |
33766 | #define GRBM_SE1_PERFCOUNTER_SELECT__PC_BUSY_USER_DEFINED_MASK_MASK 0x08000000L |
33767 | #define GRBM_SE1_PERFCOUNTER_SELECT__SEDC_BUSY_USER_DEFINED_MASK_MASK 0x10000000L |
33768 | //GRBM_SE2_PERFCOUNTER_SELECT |
33769 | #define GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0 |
33770 | #define GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa |
33771 | #define GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb |
33772 | #define GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc |
33773 | #define GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd |
33774 | #define GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf |
33775 | #define GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10 |
33776 | #define GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11 |
33777 | #define GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12 |
33778 | #define GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14 |
33779 | #define GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15 |
33780 | #define GRBM_SE2_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x16 |
33781 | #define GRBM_SE2_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK__SHIFT 0x17 |
33782 | #define GRBM_SE2_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK__SHIFT 0x18 |
33783 | #define GRBM_SE2_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK__SHIFT 0x19 |
33784 | #define GRBM_SE2_PERFCOUNTER_SELECT__GL1H_BUSY_USER_DEFINED_MASK__SHIFT 0x1a |
33785 | #define GRBM_SE2_PERFCOUNTER_SELECT__PC_BUSY_USER_DEFINED_MASK__SHIFT 0x1b |
33786 | #define GRBM_SE2_PERFCOUNTER_SELECT__SEDC_BUSY_USER_DEFINED_MASK__SHIFT 0x1c |
33787 | #define GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x0000003FL |
33788 | #define GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L |
33789 | #define GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L |
33790 | #define GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00001000L |
33791 | #define GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00002000L |
33792 | #define GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00008000L |
33793 | #define GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00010000L |
33794 | #define GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00020000L |
33795 | #define GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00040000L |
33796 | #define GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00100000L |
33797 | #define GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x00200000L |
33798 | #define GRBM_SE2_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x00400000L |
33799 | #define GRBM_SE2_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK_MASK 0x00800000L |
33800 | #define GRBM_SE2_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK_MASK 0x01000000L |
33801 | #define GRBM_SE2_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK_MASK 0x02000000L |
33802 | #define GRBM_SE2_PERFCOUNTER_SELECT__GL1H_BUSY_USER_DEFINED_MASK_MASK 0x04000000L |
33803 | #define GRBM_SE2_PERFCOUNTER_SELECT__PC_BUSY_USER_DEFINED_MASK_MASK 0x08000000L |
33804 | #define GRBM_SE2_PERFCOUNTER_SELECT__SEDC_BUSY_USER_DEFINED_MASK_MASK 0x10000000L |
33805 | //GRBM_SE3_PERFCOUNTER_SELECT |
33806 | #define GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0 |
33807 | #define GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa |
33808 | #define GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb |
33809 | #define GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc |
33810 | #define GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd |
33811 | #define GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf |
33812 | #define GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10 |
33813 | #define GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11 |
33814 | #define GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12 |
33815 | #define GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14 |
33816 | #define GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15 |
33817 | #define GRBM_SE3_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK__SHIFT 0x16 |
33818 | #define GRBM_SE3_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK__SHIFT 0x17 |
33819 | #define GRBM_SE3_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK__SHIFT 0x18 |
33820 | #define GRBM_SE3_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK__SHIFT 0x19 |
33821 | #define GRBM_SE3_PERFCOUNTER_SELECT__GL1H_BUSY_USER_DEFINED_MASK__SHIFT 0x1a |
33822 | #define GRBM_SE3_PERFCOUNTER_SELECT__PC_BUSY_USER_DEFINED_MASK__SHIFT 0x1b |
33823 | #define GRBM_SE3_PERFCOUNTER_SELECT__SEDC_BUSY_USER_DEFINED_MASK__SHIFT 0x1c |
33824 | #define GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x0000003FL |
33825 | #define GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L |
33826 | #define GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L |
33827 | #define GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00001000L |
33828 | #define GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00002000L |
33829 | #define GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00008000L |
33830 | #define GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00010000L |
33831 | #define GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00020000L |
33832 | #define GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00040000L |
33833 | #define GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00100000L |
33834 | #define GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x00200000L |
33835 | #define GRBM_SE3_PERFCOUNTER_SELECT__RMI_BUSY_USER_DEFINED_MASK_MASK 0x00400000L |
33836 | #define GRBM_SE3_PERFCOUNTER_SELECT__UTCL1_BUSY_USER_DEFINED_MASK_MASK 0x00800000L |
33837 | #define GRBM_SE3_PERFCOUNTER_SELECT__TCP_BUSY_USER_DEFINED_MASK_MASK 0x01000000L |
33838 | #define GRBM_SE3_PERFCOUNTER_SELECT__GL1CC_BUSY_USER_DEFINED_MASK_MASK 0x02000000L |
33839 | #define GRBM_SE3_PERFCOUNTER_SELECT__GL1H_BUSY_USER_DEFINED_MASK_MASK 0x04000000L |
33840 | #define GRBM_SE3_PERFCOUNTER_SELECT__PC_BUSY_USER_DEFINED_MASK_MASK 0x08000000L |
33841 | #define GRBM_SE3_PERFCOUNTER_SELECT__SEDC_BUSY_USER_DEFINED_MASK_MASK 0x10000000L |
33842 | //GRBM_PERFCOUNTER0_SELECT_HI |
33843 | #define GRBM_PERFCOUNTER0_SELECT_HI__UTCL1_BUSY_USER_DEFINED_MASK__SHIFT 0x1 |
33844 | #define GRBM_PERFCOUNTER0_SELECT_HI__GL2CC_BUSY_USER_DEFINED_MASK__SHIFT 0x2 |
33845 | #define GRBM_PERFCOUNTER0_SELECT_HI__SDMA_BUSY_USER_DEFINED_MASK__SHIFT 0x3 |
33846 | #define GRBM_PERFCOUNTER0_SELECT_HI__CH_BUSY_USER_DEFINED_MASK__SHIFT 0x4 |
33847 | #define GRBM_PERFCOUNTER0_SELECT_HI__PH_BUSY_USER_DEFINED_MASK__SHIFT 0x5 |
33848 | #define GRBM_PERFCOUNTER0_SELECT_HI__PMM_BUSY_USER_DEFINED_MASK__SHIFT 0x6 |
33849 | #define GRBM_PERFCOUNTER0_SELECT_HI__GUS_BUSY_USER_DEFINED_MASK__SHIFT 0x7 |
33850 | #define GRBM_PERFCOUNTER0_SELECT_HI__GL1CC_BUSY_USER_DEFINED_MASK__SHIFT 0x8 |
33851 | #define GRBM_PERFCOUNTER0_SELECT_HI__GL1H_BUSY_USER_DEFINED_MASK__SHIFT 0x9 |
33852 | #define GRBM_PERFCOUNTER0_SELECT_HI__UTCL1_BUSY_USER_DEFINED_MASK_MASK 0x00000002L |
33853 | #define GRBM_PERFCOUNTER0_SELECT_HI__GL2CC_BUSY_USER_DEFINED_MASK_MASK 0x00000004L |
33854 | #define GRBM_PERFCOUNTER0_SELECT_HI__SDMA_BUSY_USER_DEFINED_MASK_MASK 0x00000008L |
33855 | #define GRBM_PERFCOUNTER0_SELECT_HI__CH_BUSY_USER_DEFINED_MASK_MASK 0x00000010L |
33856 | #define GRBM_PERFCOUNTER0_SELECT_HI__PH_BUSY_USER_DEFINED_MASK_MASK 0x00000020L |
33857 | #define GRBM_PERFCOUNTER0_SELECT_HI__PMM_BUSY_USER_DEFINED_MASK_MASK 0x00000040L |
33858 | #define GRBM_PERFCOUNTER0_SELECT_HI__GUS_BUSY_USER_DEFINED_MASK_MASK 0x00000080L |
33859 | #define GRBM_PERFCOUNTER0_SELECT_HI__GL1CC_BUSY_USER_DEFINED_MASK_MASK 0x00000100L |
33860 | #define GRBM_PERFCOUNTER0_SELECT_HI__GL1H_BUSY_USER_DEFINED_MASK_MASK 0x00000200L |
33861 | //GRBM_PERFCOUNTER1_SELECT_HI |
33862 | #define GRBM_PERFCOUNTER1_SELECT_HI__UTCL1_BUSY_USER_DEFINED_MASK__SHIFT 0x1 |
33863 | #define GRBM_PERFCOUNTER1_SELECT_HI__GL2CC_BUSY_USER_DEFINED_MASK__SHIFT 0x2 |
33864 | #define GRBM_PERFCOUNTER1_SELECT_HI__SDMA_BUSY_USER_DEFINED_MASK__SHIFT 0x3 |
33865 | #define GRBM_PERFCOUNTER1_SELECT_HI__CH_BUSY_USER_DEFINED_MASK__SHIFT 0x4 |
33866 | #define GRBM_PERFCOUNTER1_SELECT_HI__PH_BUSY_USER_DEFINED_MASK__SHIFT 0x5 |
33867 | #define GRBM_PERFCOUNTER1_SELECT_HI__PMM_BUSY_USER_DEFINED_MASK__SHIFT 0x6 |
33868 | #define GRBM_PERFCOUNTER1_SELECT_HI__GUS_BUSY_USER_DEFINED_MASK__SHIFT 0x7 |
33869 | #define GRBM_PERFCOUNTER1_SELECT_HI__GL1CC_BUSY_USER_DEFINED_MASK__SHIFT 0x8 |
33870 | #define GRBM_PERFCOUNTER1_SELECT_HI__GL1H_BUSY_USER_DEFINED_MASK__SHIFT 0x9 |
33871 | #define GRBM_PERFCOUNTER1_SELECT_HI__UTCL1_BUSY_USER_DEFINED_MASK_MASK 0x00000002L |
33872 | #define GRBM_PERFCOUNTER1_SELECT_HI__GL2CC_BUSY_USER_DEFINED_MASK_MASK 0x00000004L |
33873 | #define GRBM_PERFCOUNTER1_SELECT_HI__SDMA_BUSY_USER_DEFINED_MASK_MASK 0x00000008L |
33874 | #define GRBM_PERFCOUNTER1_SELECT_HI__CH_BUSY_USER_DEFINED_MASK_MASK 0x00000010L |
33875 | #define GRBM_PERFCOUNTER1_SELECT_HI__PH_BUSY_USER_DEFINED_MASK_MASK 0x00000020L |
33876 | #define GRBM_PERFCOUNTER1_SELECT_HI__PMM_BUSY_USER_DEFINED_MASK_MASK 0x00000040L |
33877 | #define GRBM_PERFCOUNTER1_SELECT_HI__GUS_BUSY_USER_DEFINED_MASK_MASK 0x00000080L |
33878 | #define GRBM_PERFCOUNTER1_SELECT_HI__GL1CC_BUSY_USER_DEFINED_MASK_MASK 0x00000100L |
33879 | #define GRBM_PERFCOUNTER1_SELECT_HI__GL1H_BUSY_USER_DEFINED_MASK_MASK 0x00000200L |
33880 | //GE1_PERFCOUNTER0_SELECT |
33881 | #define GE1_PERFCOUNTER0_SELECT__PERF_SEL0__SHIFT 0x0 |
33882 | #define GE1_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
33883 | #define GE1_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 |
33884 | #define GE1_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 |
33885 | #define GE1_PERFCOUNTER0_SELECT__PERF_MODE0__SHIFT 0x1c |
33886 | #define GE1_PERFCOUNTER0_SELECT__PERF_SEL0_MASK 0x000003FFL |
33887 | #define GE1_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L |
33888 | #define GE1_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L |
33889 | #define GE1_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L |
33890 | #define GE1_PERFCOUNTER0_SELECT__PERF_MODE0_MASK 0xF0000000L |
33891 | //GE1_PERFCOUNTER0_SELECT1 |
33892 | #define GE1_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
33893 | #define GE1_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
33894 | #define GE1_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 |
33895 | #define GE1_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c |
33896 | #define GE1_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL |
33897 | #define GE1_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
33898 | #define GE1_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L |
33899 | #define GE1_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L |
33900 | //GE1_PERFCOUNTER1_SELECT |
33901 | #define GE1_PERFCOUNTER1_SELECT__PERF_SEL0__SHIFT 0x0 |
33902 | #define GE1_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa |
33903 | #define GE1_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 |
33904 | #define GE1_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 |
33905 | #define GE1_PERFCOUNTER1_SELECT__PERF_MODE0__SHIFT 0x1c |
33906 | #define GE1_PERFCOUNTER1_SELECT__PERF_SEL0_MASK 0x000003FFL |
33907 | #define GE1_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L |
33908 | #define GE1_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L |
33909 | #define GE1_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L |
33910 | #define GE1_PERFCOUNTER1_SELECT__PERF_MODE0_MASK 0xF0000000L |
33911 | //GE1_PERFCOUNTER1_SELECT1 |
33912 | #define GE1_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 |
33913 | #define GE1_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa |
33914 | #define GE1_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 |
33915 | #define GE1_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c |
33916 | #define GE1_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL |
33917 | #define GE1_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
33918 | #define GE1_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L |
33919 | #define GE1_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L |
33920 | //GE1_PERFCOUNTER2_SELECT |
33921 | #define GE1_PERFCOUNTER2_SELECT__PERF_SEL0__SHIFT 0x0 |
33922 | #define GE1_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa |
33923 | #define GE1_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 |
33924 | #define GE1_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 |
33925 | #define GE1_PERFCOUNTER2_SELECT__PERF_MODE0__SHIFT 0x1c |
33926 | #define GE1_PERFCOUNTER2_SELECT__PERF_SEL0_MASK 0x000003FFL |
33927 | #define GE1_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L |
33928 | #define GE1_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L |
33929 | #define GE1_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L |
33930 | #define GE1_PERFCOUNTER2_SELECT__PERF_MODE0_MASK 0xF0000000L |
33931 | //GE1_PERFCOUNTER2_SELECT1 |
33932 | #define GE1_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 |
33933 | #define GE1_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa |
33934 | #define GE1_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18 |
33935 | #define GE1_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c |
33936 | #define GE1_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL |
33937 | #define GE1_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
33938 | #define GE1_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L |
33939 | #define GE1_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L |
33940 | //GE1_PERFCOUNTER3_SELECT |
33941 | #define GE1_PERFCOUNTER3_SELECT__PERF_SEL0__SHIFT 0x0 |
33942 | #define GE1_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa |
33943 | #define GE1_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 |
33944 | #define GE1_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18 |
33945 | #define GE1_PERFCOUNTER3_SELECT__PERF_MODE0__SHIFT 0x1c |
33946 | #define GE1_PERFCOUNTER3_SELECT__PERF_SEL0_MASK 0x000003FFL |
33947 | #define GE1_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L |
33948 | #define GE1_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L |
33949 | #define GE1_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L |
33950 | #define GE1_PERFCOUNTER3_SELECT__PERF_MODE0_MASK 0xF0000000L |
33951 | //GE1_PERFCOUNTER3_SELECT1 |
33952 | #define GE1_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0 |
33953 | #define GE1_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa |
33954 | #define GE1_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT 0x18 |
33955 | #define GE1_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT 0x1c |
33956 | #define GE1_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003FFL |
33957 | #define GE1_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
33958 | #define GE1_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK 0x0F000000L |
33959 | #define GE1_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK 0xF0000000L |
33960 | //GE2_DIST_PERFCOUNTER0_SELECT |
33961 | #define GE2_DIST_PERFCOUNTER0_SELECT__PERF_SEL0__SHIFT 0x0 |
33962 | #define GE2_DIST_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
33963 | #define GE2_DIST_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 |
33964 | #define GE2_DIST_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 |
33965 | #define GE2_DIST_PERFCOUNTER0_SELECT__PERF_MODE0__SHIFT 0x1c |
33966 | #define GE2_DIST_PERFCOUNTER0_SELECT__PERF_SEL0_MASK 0x000003FFL |
33967 | #define GE2_DIST_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L |
33968 | #define GE2_DIST_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L |
33969 | #define GE2_DIST_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L |
33970 | #define GE2_DIST_PERFCOUNTER0_SELECT__PERF_MODE0_MASK 0xF0000000L |
33971 | //GE2_DIST_PERFCOUNTER0_SELECT1 |
33972 | #define GE2_DIST_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
33973 | #define GE2_DIST_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
33974 | #define GE2_DIST_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 |
33975 | #define GE2_DIST_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c |
33976 | #define GE2_DIST_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL |
33977 | #define GE2_DIST_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
33978 | #define GE2_DIST_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L |
33979 | #define GE2_DIST_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L |
33980 | //GE2_DIST_PERFCOUNTER1_SELECT |
33981 | #define GE2_DIST_PERFCOUNTER1_SELECT__PERF_SEL0__SHIFT 0x0 |
33982 | #define GE2_DIST_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa |
33983 | #define GE2_DIST_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 |
33984 | #define GE2_DIST_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 |
33985 | #define GE2_DIST_PERFCOUNTER1_SELECT__PERF_MODE0__SHIFT 0x1c |
33986 | #define GE2_DIST_PERFCOUNTER1_SELECT__PERF_SEL0_MASK 0x000003FFL |
33987 | #define GE2_DIST_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L |
33988 | #define GE2_DIST_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L |
33989 | #define GE2_DIST_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L |
33990 | #define GE2_DIST_PERFCOUNTER1_SELECT__PERF_MODE0_MASK 0xF0000000L |
33991 | //GE2_DIST_PERFCOUNTER1_SELECT1 |
33992 | #define GE2_DIST_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 |
33993 | #define GE2_DIST_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa |
33994 | #define GE2_DIST_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 |
33995 | #define GE2_DIST_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c |
33996 | #define GE2_DIST_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL |
33997 | #define GE2_DIST_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
33998 | #define GE2_DIST_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L |
33999 | #define GE2_DIST_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L |
34000 | //GE2_DIST_PERFCOUNTER2_SELECT |
34001 | #define GE2_DIST_PERFCOUNTER2_SELECT__PERF_SEL0__SHIFT 0x0 |
34002 | #define GE2_DIST_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa |
34003 | #define GE2_DIST_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 |
34004 | #define GE2_DIST_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 |
34005 | #define GE2_DIST_PERFCOUNTER2_SELECT__PERF_MODE0__SHIFT 0x1c |
34006 | #define GE2_DIST_PERFCOUNTER2_SELECT__PERF_SEL0_MASK 0x000003FFL |
34007 | #define GE2_DIST_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L |
34008 | #define GE2_DIST_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L |
34009 | #define GE2_DIST_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L |
34010 | #define GE2_DIST_PERFCOUNTER2_SELECT__PERF_MODE0_MASK 0xF0000000L |
34011 | //GE2_DIST_PERFCOUNTER2_SELECT1 |
34012 | #define GE2_DIST_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 |
34013 | #define GE2_DIST_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa |
34014 | #define GE2_DIST_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18 |
34015 | #define GE2_DIST_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c |
34016 | #define GE2_DIST_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL |
34017 | #define GE2_DIST_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
34018 | #define GE2_DIST_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L |
34019 | #define GE2_DIST_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L |
34020 | //GE2_DIST_PERFCOUNTER3_SELECT |
34021 | #define GE2_DIST_PERFCOUNTER3_SELECT__PERF_SEL0__SHIFT 0x0 |
34022 | #define GE2_DIST_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa |
34023 | #define GE2_DIST_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 |
34024 | #define GE2_DIST_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18 |
34025 | #define GE2_DIST_PERFCOUNTER3_SELECT__PERF_MODE0__SHIFT 0x1c |
34026 | #define GE2_DIST_PERFCOUNTER3_SELECT__PERF_SEL0_MASK 0x000003FFL |
34027 | #define GE2_DIST_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L |
34028 | #define GE2_DIST_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L |
34029 | #define GE2_DIST_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L |
34030 | #define GE2_DIST_PERFCOUNTER3_SELECT__PERF_MODE0_MASK 0xF0000000L |
34031 | //GE2_DIST_PERFCOUNTER3_SELECT1 |
34032 | #define GE2_DIST_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0 |
34033 | #define GE2_DIST_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa |
34034 | #define GE2_DIST_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT 0x18 |
34035 | #define GE2_DIST_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT 0x1c |
34036 | #define GE2_DIST_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003FFL |
34037 | #define GE2_DIST_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
34038 | #define GE2_DIST_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK 0x0F000000L |
34039 | #define GE2_DIST_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK 0xF0000000L |
34040 | //GE2_SE_PERFCOUNTER0_SELECT |
34041 | #define GE2_SE_PERFCOUNTER0_SELECT__PERF_SEL0__SHIFT 0x0 |
34042 | #define GE2_SE_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
34043 | #define GE2_SE_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 |
34044 | #define GE2_SE_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 |
34045 | #define GE2_SE_PERFCOUNTER0_SELECT__PERF_MODE0__SHIFT 0x1c |
34046 | #define GE2_SE_PERFCOUNTER0_SELECT__PERF_SEL0_MASK 0x000003FFL |
34047 | #define GE2_SE_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L |
34048 | #define GE2_SE_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L |
34049 | #define GE2_SE_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L |
34050 | #define GE2_SE_PERFCOUNTER0_SELECT__PERF_MODE0_MASK 0xF0000000L |
34051 | //GE2_SE_PERFCOUNTER0_SELECT1 |
34052 | #define GE2_SE_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
34053 | #define GE2_SE_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
34054 | #define GE2_SE_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 |
34055 | #define GE2_SE_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c |
34056 | #define GE2_SE_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL |
34057 | #define GE2_SE_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
34058 | #define GE2_SE_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L |
34059 | #define GE2_SE_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L |
34060 | //GE2_SE_PERFCOUNTER1_SELECT |
34061 | #define GE2_SE_PERFCOUNTER1_SELECT__PERF_SEL0__SHIFT 0x0 |
34062 | #define GE2_SE_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa |
34063 | #define GE2_SE_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 |
34064 | #define GE2_SE_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 |
34065 | #define GE2_SE_PERFCOUNTER1_SELECT__PERF_MODE0__SHIFT 0x1c |
34066 | #define GE2_SE_PERFCOUNTER1_SELECT__PERF_SEL0_MASK 0x000003FFL |
34067 | #define GE2_SE_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L |
34068 | #define GE2_SE_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L |
34069 | #define GE2_SE_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L |
34070 | #define GE2_SE_PERFCOUNTER1_SELECT__PERF_MODE0_MASK 0xF0000000L |
34071 | //GE2_SE_PERFCOUNTER1_SELECT1 |
34072 | #define GE2_SE_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 |
34073 | #define GE2_SE_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa |
34074 | #define GE2_SE_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 |
34075 | #define GE2_SE_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c |
34076 | #define GE2_SE_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL |
34077 | #define GE2_SE_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
34078 | #define GE2_SE_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L |
34079 | #define GE2_SE_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L |
34080 | //GE2_SE_PERFCOUNTER2_SELECT |
34081 | #define GE2_SE_PERFCOUNTER2_SELECT__PERF_SEL0__SHIFT 0x0 |
34082 | #define GE2_SE_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa |
34083 | #define GE2_SE_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 |
34084 | #define GE2_SE_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 |
34085 | #define GE2_SE_PERFCOUNTER2_SELECT__PERF_MODE0__SHIFT 0x1c |
34086 | #define GE2_SE_PERFCOUNTER2_SELECT__PERF_SEL0_MASK 0x000003FFL |
34087 | #define GE2_SE_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L |
34088 | #define GE2_SE_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L |
34089 | #define GE2_SE_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L |
34090 | #define GE2_SE_PERFCOUNTER2_SELECT__PERF_MODE0_MASK 0xF0000000L |
34091 | //GE2_SE_PERFCOUNTER2_SELECT1 |
34092 | #define GE2_SE_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 |
34093 | #define GE2_SE_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa |
34094 | #define GE2_SE_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18 |
34095 | #define GE2_SE_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c |
34096 | #define GE2_SE_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL |
34097 | #define GE2_SE_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
34098 | #define GE2_SE_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L |
34099 | #define GE2_SE_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L |
34100 | //GE2_SE_PERFCOUNTER3_SELECT |
34101 | #define GE2_SE_PERFCOUNTER3_SELECT__PERF_SEL0__SHIFT 0x0 |
34102 | #define GE2_SE_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa |
34103 | #define GE2_SE_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 |
34104 | #define GE2_SE_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18 |
34105 | #define GE2_SE_PERFCOUNTER3_SELECT__PERF_MODE0__SHIFT 0x1c |
34106 | #define GE2_SE_PERFCOUNTER3_SELECT__PERF_SEL0_MASK 0x000003FFL |
34107 | #define GE2_SE_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L |
34108 | #define GE2_SE_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L |
34109 | #define GE2_SE_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L |
34110 | #define GE2_SE_PERFCOUNTER3_SELECT__PERF_MODE0_MASK 0xF0000000L |
34111 | //GE2_SE_PERFCOUNTER3_SELECT1 |
34112 | #define GE2_SE_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0 |
34113 | #define GE2_SE_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa |
34114 | #define GE2_SE_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT 0x18 |
34115 | #define GE2_SE_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT 0x1c |
34116 | #define GE2_SE_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003FFL |
34117 | #define GE2_SE_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
34118 | #define GE2_SE_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK 0x0F000000L |
34119 | #define GE2_SE_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK 0xF0000000L |
34120 | //PA_SU_PERFCOUNTER0_SELECT |
34121 | #define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
34122 | #define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
34123 | #define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 |
34124 | #define PA_SU_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 |
34125 | #define PA_SU_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c |
34126 | #define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL |
34127 | #define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L |
34128 | #define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L |
34129 | #define PA_SU_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L |
34130 | #define PA_SU_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L |
34131 | //PA_SU_PERFCOUNTER0_SELECT1 |
34132 | #define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
34133 | #define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
34134 | #define PA_SU_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 |
34135 | #define PA_SU_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c |
34136 | #define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL |
34137 | #define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
34138 | #define PA_SU_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L |
34139 | #define PA_SU_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L |
34140 | //PA_SU_PERFCOUNTER1_SELECT |
34141 | #define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
34142 | #define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa |
34143 | #define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 |
34144 | #define PA_SU_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 |
34145 | #define PA_SU_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c |
34146 | #define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL |
34147 | #define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L |
34148 | #define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L |
34149 | #define PA_SU_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L |
34150 | #define PA_SU_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L |
34151 | //PA_SU_PERFCOUNTER1_SELECT1 |
34152 | #define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 |
34153 | #define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa |
34154 | #define PA_SU_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 |
34155 | #define PA_SU_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c |
34156 | #define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL |
34157 | #define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
34158 | #define PA_SU_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L |
34159 | #define PA_SU_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L |
34160 | //PA_SU_PERFCOUNTER2_SELECT |
34161 | #define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 |
34162 | #define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa |
34163 | #define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 |
34164 | #define PA_SU_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 |
34165 | #define PA_SU_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c |
34166 | #define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL |
34167 | #define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L |
34168 | #define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L |
34169 | #define PA_SU_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L |
34170 | #define PA_SU_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L |
34171 | //PA_SU_PERFCOUNTER2_SELECT1 |
34172 | #define PA_SU_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 |
34173 | #define PA_SU_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa |
34174 | #define PA_SU_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18 |
34175 | #define PA_SU_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c |
34176 | #define PA_SU_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL |
34177 | #define PA_SU_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
34178 | #define PA_SU_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L |
34179 | #define PA_SU_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L |
34180 | //PA_SU_PERFCOUNTER3_SELECT |
34181 | #define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 |
34182 | #define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa |
34183 | #define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 |
34184 | #define PA_SU_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18 |
34185 | #define PA_SU_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c |
34186 | #define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL |
34187 | #define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L |
34188 | #define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L |
34189 | #define PA_SU_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L |
34190 | #define PA_SU_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L |
34191 | //PA_SU_PERFCOUNTER3_SELECT1 |
34192 | #define PA_SU_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0 |
34193 | #define PA_SU_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa |
34194 | #define PA_SU_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT 0x18 |
34195 | #define PA_SU_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT 0x1c |
34196 | #define PA_SU_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003FFL |
34197 | #define PA_SU_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
34198 | #define PA_SU_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK 0x0F000000L |
34199 | #define PA_SU_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK 0xF0000000L |
34200 | //PA_SC_PERFCOUNTER0_SELECT |
34201 | #define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
34202 | #define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
34203 | #define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 |
34204 | #define PA_SC_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 |
34205 | #define PA_SC_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c |
34206 | #define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL |
34207 | #define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L |
34208 | #define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L |
34209 | #define PA_SC_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L |
34210 | #define PA_SC_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L |
34211 | //PA_SC_PERFCOUNTER0_SELECT1 |
34212 | #define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
34213 | #define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
34214 | #define PA_SC_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 |
34215 | #define PA_SC_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c |
34216 | #define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL |
34217 | #define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
34218 | #define PA_SC_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L |
34219 | #define PA_SC_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L |
34220 | //PA_SC_PERFCOUNTER1_SELECT |
34221 | #define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
34222 | #define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL |
34223 | //PA_SC_PERFCOUNTER2_SELECT |
34224 | #define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 |
34225 | #define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL |
34226 | //PA_SC_PERFCOUNTER3_SELECT |
34227 | #define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 |
34228 | #define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL |
34229 | //PA_SC_PERFCOUNTER4_SELECT |
34230 | #define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0 |
34231 | #define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x000003FFL |
34232 | //PA_SC_PERFCOUNTER5_SELECT |
34233 | #define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0 |
34234 | #define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x000003FFL |
34235 | //PA_SC_PERFCOUNTER6_SELECT |
34236 | #define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x0 |
34237 | #define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0x000003FFL |
34238 | //PA_SC_PERFCOUNTER7_SELECT |
34239 | #define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x0 |
34240 | #define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0x000003FFL |
34241 | //SPI_PERFCOUNTER0_SELECT |
34242 | #define SPI_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
34243 | #define SPI_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
34244 | #define SPI_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 |
34245 | #define SPI_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 |
34246 | #define SPI_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c |
34247 | #define SPI_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL |
34248 | #define SPI_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L |
34249 | #define SPI_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L |
34250 | #define SPI_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L |
34251 | #define SPI_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L |
34252 | //SPI_PERFCOUNTER1_SELECT |
34253 | #define SPI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
34254 | #define SPI_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa |
34255 | #define SPI_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 |
34256 | #define SPI_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 |
34257 | #define SPI_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c |
34258 | #define SPI_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL |
34259 | #define SPI_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L |
34260 | #define SPI_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L |
34261 | #define SPI_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L |
34262 | #define SPI_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L |
34263 | //SPI_PERFCOUNTER2_SELECT |
34264 | #define SPI_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 |
34265 | #define SPI_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa |
34266 | #define SPI_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 |
34267 | #define SPI_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 |
34268 | #define SPI_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c |
34269 | #define SPI_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL |
34270 | #define SPI_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L |
34271 | #define SPI_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L |
34272 | #define SPI_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L |
34273 | #define SPI_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L |
34274 | //SPI_PERFCOUNTER3_SELECT |
34275 | #define SPI_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 |
34276 | #define SPI_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa |
34277 | #define SPI_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 |
34278 | #define SPI_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18 |
34279 | #define SPI_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c |
34280 | #define SPI_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL |
34281 | #define SPI_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L |
34282 | #define SPI_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L |
34283 | #define SPI_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L |
34284 | #define SPI_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L |
34285 | //SPI_PERFCOUNTER0_SELECT1 |
34286 | #define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
34287 | #define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
34288 | #define SPI_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 |
34289 | #define SPI_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c |
34290 | #define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL |
34291 | #define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
34292 | #define SPI_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L |
34293 | #define SPI_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L |
34294 | //SPI_PERFCOUNTER1_SELECT1 |
34295 | #define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 |
34296 | #define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa |
34297 | #define SPI_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 |
34298 | #define SPI_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c |
34299 | #define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL |
34300 | #define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
34301 | #define SPI_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L |
34302 | #define SPI_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L |
34303 | //SPI_PERFCOUNTER2_SELECT1 |
34304 | #define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 |
34305 | #define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa |
34306 | #define SPI_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18 |
34307 | #define SPI_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c |
34308 | #define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL |
34309 | #define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
34310 | #define SPI_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L |
34311 | #define SPI_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L |
34312 | //SPI_PERFCOUNTER3_SELECT1 |
34313 | #define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0 |
34314 | #define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa |
34315 | #define SPI_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT 0x18 |
34316 | #define SPI_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT 0x1c |
34317 | #define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003FFL |
34318 | #define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
34319 | #define SPI_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK 0x0F000000L |
34320 | #define SPI_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK 0xF0000000L |
34321 | //SPI_PERFCOUNTER4_SELECT |
34322 | #define SPI_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0 |
34323 | #define SPI_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x000003FFL |
34324 | //SPI_PERFCOUNTER5_SELECT |
34325 | #define SPI_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0 |
34326 | #define SPI_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x000003FFL |
34327 | //SPI_PERFCOUNTER_BINS |
34328 | #define SPI_PERFCOUNTER_BINS__BIN0_MIN__SHIFT 0x0 |
34329 | #define SPI_PERFCOUNTER_BINS__BIN0_MAX__SHIFT 0x4 |
34330 | #define SPI_PERFCOUNTER_BINS__BIN1_MIN__SHIFT 0x8 |
34331 | #define SPI_PERFCOUNTER_BINS__BIN1_MAX__SHIFT 0xc |
34332 | #define SPI_PERFCOUNTER_BINS__BIN2_MIN__SHIFT 0x10 |
34333 | #define SPI_PERFCOUNTER_BINS__BIN2_MAX__SHIFT 0x14 |
34334 | #define SPI_PERFCOUNTER_BINS__BIN3_MIN__SHIFT 0x18 |
34335 | #define SPI_PERFCOUNTER_BINS__BIN3_MAX__SHIFT 0x1c |
34336 | #define SPI_PERFCOUNTER_BINS__BIN0_MIN_MASK 0x0000000FL |
34337 | #define SPI_PERFCOUNTER_BINS__BIN0_MAX_MASK 0x000000F0L |
34338 | #define SPI_PERFCOUNTER_BINS__BIN1_MIN_MASK 0x00000F00L |
34339 | #define SPI_PERFCOUNTER_BINS__BIN1_MAX_MASK 0x0000F000L |
34340 | #define SPI_PERFCOUNTER_BINS__BIN2_MIN_MASK 0x000F0000L |
34341 | #define SPI_PERFCOUNTER_BINS__BIN2_MAX_MASK 0x00F00000L |
34342 | #define SPI_PERFCOUNTER_BINS__BIN3_MIN_MASK 0x0F000000L |
34343 | #define SPI_PERFCOUNTER_BINS__BIN3_MAX_MASK 0xF0000000L |
34344 | //PC_PERFCOUNTER0_SELECT |
34345 | #define PC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
34346 | #define PC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
34347 | #define PC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 |
34348 | #define PC_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 |
34349 | #define PC_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c |
34350 | #define PC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL |
34351 | #define PC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L |
34352 | #define PC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L |
34353 | #define PC_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L |
34354 | #define PC_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L |
34355 | //PC_PERFCOUNTER1_SELECT |
34356 | #define PC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
34357 | #define PC_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa |
34358 | #define PC_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 |
34359 | #define PC_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 |
34360 | #define PC_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c |
34361 | #define PC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL |
34362 | #define PC_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L |
34363 | #define PC_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L |
34364 | #define PC_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L |
34365 | #define PC_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L |
34366 | //PC_PERFCOUNTER2_SELECT |
34367 | #define PC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 |
34368 | #define PC_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa |
34369 | #define PC_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 |
34370 | #define PC_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 |
34371 | #define PC_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c |
34372 | #define PC_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL |
34373 | #define PC_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L |
34374 | #define PC_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L |
34375 | #define PC_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L |
34376 | #define PC_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L |
34377 | //PC_PERFCOUNTER3_SELECT |
34378 | #define PC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 |
34379 | #define PC_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa |
34380 | #define PC_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 |
34381 | #define PC_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18 |
34382 | #define PC_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c |
34383 | #define PC_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL |
34384 | #define PC_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L |
34385 | #define PC_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L |
34386 | #define PC_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L |
34387 | #define PC_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L |
34388 | //PC_PERFCOUNTER0_SELECT1 |
34389 | #define PC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
34390 | #define PC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
34391 | #define PC_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 |
34392 | #define PC_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c |
34393 | #define PC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL |
34394 | #define PC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
34395 | #define PC_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L |
34396 | #define PC_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L |
34397 | //PC_PERFCOUNTER1_SELECT1 |
34398 | #define PC_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 |
34399 | #define PC_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa |
34400 | #define PC_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 |
34401 | #define PC_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c |
34402 | #define PC_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL |
34403 | #define PC_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
34404 | #define PC_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L |
34405 | #define PC_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L |
34406 | //PC_PERFCOUNTER2_SELECT1 |
34407 | #define PC_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 |
34408 | #define PC_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa |
34409 | #define PC_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18 |
34410 | #define PC_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c |
34411 | #define PC_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL |
34412 | #define PC_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
34413 | #define PC_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L |
34414 | #define PC_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L |
34415 | //PC_PERFCOUNTER3_SELECT1 |
34416 | #define PC_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0 |
34417 | #define PC_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa |
34418 | #define PC_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT 0x18 |
34419 | #define PC_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT 0x1c |
34420 | #define PC_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003FFL |
34421 | #define PC_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
34422 | #define PC_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK 0x0F000000L |
34423 | #define PC_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK 0xF0000000L |
34424 | //SQ_PERFCOUNTER0_SELECT |
34425 | #define SQ_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
34426 | #define SQ_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14 |
34427 | #define SQ_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c |
34428 | #define SQ_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000001FFL |
34429 | #define SQ_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L |
34430 | #define SQ_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L |
34431 | //SQ_PERFCOUNTER1_SELECT |
34432 | #define SQ_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
34433 | #define SQ_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14 |
34434 | #define SQ_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c |
34435 | #define SQ_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000001FFL |
34436 | #define SQ_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00F00000L |
34437 | #define SQ_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L |
34438 | //SQ_PERFCOUNTER2_SELECT |
34439 | #define SQ_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 |
34440 | #define SQ_PERFCOUNTER2_SELECT__SPM_MODE__SHIFT 0x14 |
34441 | #define SQ_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c |
34442 | #define SQ_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000001FFL |
34443 | #define SQ_PERFCOUNTER2_SELECT__SPM_MODE_MASK 0x00F00000L |
34444 | #define SQ_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L |
34445 | //SQ_PERFCOUNTER3_SELECT |
34446 | #define SQ_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 |
34447 | #define SQ_PERFCOUNTER3_SELECT__SPM_MODE__SHIFT 0x14 |
34448 | #define SQ_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c |
34449 | #define SQ_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000001FFL |
34450 | #define SQ_PERFCOUNTER3_SELECT__SPM_MODE_MASK 0x00F00000L |
34451 | #define SQ_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L |
34452 | //SQ_PERFCOUNTER4_SELECT |
34453 | #define SQ_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0 |
34454 | #define SQ_PERFCOUNTER4_SELECT__SPM_MODE__SHIFT 0x14 |
34455 | #define SQ_PERFCOUNTER4_SELECT__PERF_MODE__SHIFT 0x1c |
34456 | #define SQ_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x000001FFL |
34457 | #define SQ_PERFCOUNTER4_SELECT__SPM_MODE_MASK 0x00F00000L |
34458 | #define SQ_PERFCOUNTER4_SELECT__PERF_MODE_MASK 0xF0000000L |
34459 | //SQ_PERFCOUNTER5_SELECT |
34460 | #define SQ_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0 |
34461 | #define SQ_PERFCOUNTER5_SELECT__SPM_MODE__SHIFT 0x14 |
34462 | #define SQ_PERFCOUNTER5_SELECT__PERF_MODE__SHIFT 0x1c |
34463 | #define SQ_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x000001FFL |
34464 | #define SQ_PERFCOUNTER5_SELECT__SPM_MODE_MASK 0x00F00000L |
34465 | #define SQ_PERFCOUNTER5_SELECT__PERF_MODE_MASK 0xF0000000L |
34466 | //SQ_PERFCOUNTER6_SELECT |
34467 | #define SQ_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x0 |
34468 | #define SQ_PERFCOUNTER6_SELECT__SPM_MODE__SHIFT 0x14 |
34469 | #define SQ_PERFCOUNTER6_SELECT__PERF_MODE__SHIFT 0x1c |
34470 | #define SQ_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0x000001FFL |
34471 | #define SQ_PERFCOUNTER6_SELECT__SPM_MODE_MASK 0x00F00000L |
34472 | #define SQ_PERFCOUNTER6_SELECT__PERF_MODE_MASK 0xF0000000L |
34473 | //SQ_PERFCOUNTER7_SELECT |
34474 | #define SQ_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x0 |
34475 | #define SQ_PERFCOUNTER7_SELECT__SPM_MODE__SHIFT 0x14 |
34476 | #define SQ_PERFCOUNTER7_SELECT__PERF_MODE__SHIFT 0x1c |
34477 | #define SQ_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0x000001FFL |
34478 | #define SQ_PERFCOUNTER7_SELECT__SPM_MODE_MASK 0x00F00000L |
34479 | #define SQ_PERFCOUNTER7_SELECT__PERF_MODE_MASK 0xF0000000L |
34480 | //SQ_PERFCOUNTER8_SELECT |
34481 | #define SQ_PERFCOUNTER8_SELECT__PERF_SEL__SHIFT 0x0 |
34482 | #define SQ_PERFCOUNTER8_SELECT__SPM_MODE__SHIFT 0x14 |
34483 | #define SQ_PERFCOUNTER8_SELECT__PERF_MODE__SHIFT 0x1c |
34484 | #define SQ_PERFCOUNTER8_SELECT__PERF_SEL_MASK 0x000001FFL |
34485 | #define SQ_PERFCOUNTER8_SELECT__SPM_MODE_MASK 0x00F00000L |
34486 | #define SQ_PERFCOUNTER8_SELECT__PERF_MODE_MASK 0xF0000000L |
34487 | //SQ_PERFCOUNTER9_SELECT |
34488 | #define SQ_PERFCOUNTER9_SELECT__PERF_SEL__SHIFT 0x0 |
34489 | #define SQ_PERFCOUNTER9_SELECT__SPM_MODE__SHIFT 0x14 |
34490 | #define SQ_PERFCOUNTER9_SELECT__PERF_MODE__SHIFT 0x1c |
34491 | #define SQ_PERFCOUNTER9_SELECT__PERF_SEL_MASK 0x000001FFL |
34492 | #define SQ_PERFCOUNTER9_SELECT__SPM_MODE_MASK 0x00F00000L |
34493 | #define SQ_PERFCOUNTER9_SELECT__PERF_MODE_MASK 0xF0000000L |
34494 | //SQ_PERFCOUNTER10_SELECT |
34495 | #define SQ_PERFCOUNTER10_SELECT__PERF_SEL__SHIFT 0x0 |
34496 | #define SQ_PERFCOUNTER10_SELECT__SPM_MODE__SHIFT 0x14 |
34497 | #define SQ_PERFCOUNTER10_SELECT__PERF_MODE__SHIFT 0x1c |
34498 | #define SQ_PERFCOUNTER10_SELECT__PERF_SEL_MASK 0x000001FFL |
34499 | #define SQ_PERFCOUNTER10_SELECT__SPM_MODE_MASK 0x00F00000L |
34500 | #define SQ_PERFCOUNTER10_SELECT__PERF_MODE_MASK 0xF0000000L |
34501 | //SQ_PERFCOUNTER11_SELECT |
34502 | #define SQ_PERFCOUNTER11_SELECT__PERF_SEL__SHIFT 0x0 |
34503 | #define SQ_PERFCOUNTER11_SELECT__SPM_MODE__SHIFT 0x14 |
34504 | #define SQ_PERFCOUNTER11_SELECT__PERF_MODE__SHIFT 0x1c |
34505 | #define SQ_PERFCOUNTER11_SELECT__PERF_SEL_MASK 0x000001FFL |
34506 | #define SQ_PERFCOUNTER11_SELECT__SPM_MODE_MASK 0x00F00000L |
34507 | #define SQ_PERFCOUNTER11_SELECT__PERF_MODE_MASK 0xF0000000L |
34508 | //SQ_PERFCOUNTER12_SELECT |
34509 | #define SQ_PERFCOUNTER12_SELECT__PERF_SEL__SHIFT 0x0 |
34510 | #define SQ_PERFCOUNTER12_SELECT__SPM_MODE__SHIFT 0x14 |
34511 | #define SQ_PERFCOUNTER12_SELECT__PERF_MODE__SHIFT 0x1c |
34512 | #define SQ_PERFCOUNTER12_SELECT__PERF_SEL_MASK 0x000001FFL |
34513 | #define SQ_PERFCOUNTER12_SELECT__SPM_MODE_MASK 0x00F00000L |
34514 | #define SQ_PERFCOUNTER12_SELECT__PERF_MODE_MASK 0xF0000000L |
34515 | //SQ_PERFCOUNTER13_SELECT |
34516 | #define SQ_PERFCOUNTER13_SELECT__PERF_SEL__SHIFT 0x0 |
34517 | #define SQ_PERFCOUNTER13_SELECT__SPM_MODE__SHIFT 0x14 |
34518 | #define SQ_PERFCOUNTER13_SELECT__PERF_MODE__SHIFT 0x1c |
34519 | #define SQ_PERFCOUNTER13_SELECT__PERF_SEL_MASK 0x000001FFL |
34520 | #define SQ_PERFCOUNTER13_SELECT__SPM_MODE_MASK 0x00F00000L |
34521 | #define SQ_PERFCOUNTER13_SELECT__PERF_MODE_MASK 0xF0000000L |
34522 | //SQ_PERFCOUNTER14_SELECT |
34523 | #define SQ_PERFCOUNTER14_SELECT__PERF_SEL__SHIFT 0x0 |
34524 | #define SQ_PERFCOUNTER14_SELECT__SPM_MODE__SHIFT 0x14 |
34525 | #define SQ_PERFCOUNTER14_SELECT__PERF_MODE__SHIFT 0x1c |
34526 | #define SQ_PERFCOUNTER14_SELECT__PERF_SEL_MASK 0x000001FFL |
34527 | #define SQ_PERFCOUNTER14_SELECT__SPM_MODE_MASK 0x00F00000L |
34528 | #define SQ_PERFCOUNTER14_SELECT__PERF_MODE_MASK 0xF0000000L |
34529 | //SQ_PERFCOUNTER15_SELECT |
34530 | #define SQ_PERFCOUNTER15_SELECT__PERF_SEL__SHIFT 0x0 |
34531 | #define SQ_PERFCOUNTER15_SELECT__SPM_MODE__SHIFT 0x14 |
34532 | #define SQ_PERFCOUNTER15_SELECT__PERF_MODE__SHIFT 0x1c |
34533 | #define SQ_PERFCOUNTER15_SELECT__PERF_SEL_MASK 0x000001FFL |
34534 | #define SQ_PERFCOUNTER15_SELECT__SPM_MODE_MASK 0x00F00000L |
34535 | #define SQ_PERFCOUNTER15_SELECT__PERF_MODE_MASK 0xF0000000L |
34536 | //SQG_PERFCOUNTER0_SELECT |
34537 | #define SQG_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
34538 | #define SQG_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14 |
34539 | #define SQG_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c |
34540 | #define SQG_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000001FFL |
34541 | #define SQG_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L |
34542 | #define SQG_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L |
34543 | //SQG_PERFCOUNTER1_SELECT |
34544 | #define SQG_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
34545 | #define SQG_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14 |
34546 | #define SQG_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c |
34547 | #define SQG_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000001FFL |
34548 | #define SQG_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00F00000L |
34549 | #define SQG_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L |
34550 | //SQG_PERFCOUNTER2_SELECT |
34551 | #define SQG_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 |
34552 | #define SQG_PERFCOUNTER2_SELECT__SPM_MODE__SHIFT 0x14 |
34553 | #define SQG_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c |
34554 | #define SQG_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000001FFL |
34555 | #define SQG_PERFCOUNTER2_SELECT__SPM_MODE_MASK 0x00F00000L |
34556 | #define SQG_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L |
34557 | //SQG_PERFCOUNTER3_SELECT |
34558 | #define SQG_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 |
34559 | #define SQG_PERFCOUNTER3_SELECT__SPM_MODE__SHIFT 0x14 |
34560 | #define SQG_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c |
34561 | #define SQG_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000001FFL |
34562 | #define SQG_PERFCOUNTER3_SELECT__SPM_MODE_MASK 0x00F00000L |
34563 | #define SQG_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L |
34564 | //SQG_PERFCOUNTER4_SELECT |
34565 | #define SQG_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0 |
34566 | #define SQG_PERFCOUNTER4_SELECT__SPM_MODE__SHIFT 0x14 |
34567 | #define SQG_PERFCOUNTER4_SELECT__PERF_MODE__SHIFT 0x1c |
34568 | #define SQG_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x000001FFL |
34569 | #define SQG_PERFCOUNTER4_SELECT__SPM_MODE_MASK 0x00F00000L |
34570 | #define SQG_PERFCOUNTER4_SELECT__PERF_MODE_MASK 0xF0000000L |
34571 | //SQG_PERFCOUNTER5_SELECT |
34572 | #define SQG_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0 |
34573 | #define SQG_PERFCOUNTER5_SELECT__SPM_MODE__SHIFT 0x14 |
34574 | #define SQG_PERFCOUNTER5_SELECT__PERF_MODE__SHIFT 0x1c |
34575 | #define SQG_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x000001FFL |
34576 | #define SQG_PERFCOUNTER5_SELECT__SPM_MODE_MASK 0x00F00000L |
34577 | #define SQG_PERFCOUNTER5_SELECT__PERF_MODE_MASK 0xF0000000L |
34578 | //SQG_PERFCOUNTER6_SELECT |
34579 | #define SQG_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x0 |
34580 | #define SQG_PERFCOUNTER6_SELECT__SPM_MODE__SHIFT 0x14 |
34581 | #define SQG_PERFCOUNTER6_SELECT__PERF_MODE__SHIFT 0x1c |
34582 | #define SQG_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0x000001FFL |
34583 | #define SQG_PERFCOUNTER6_SELECT__SPM_MODE_MASK 0x00F00000L |
34584 | #define SQG_PERFCOUNTER6_SELECT__PERF_MODE_MASK 0xF0000000L |
34585 | //SQG_PERFCOUNTER7_SELECT |
34586 | #define SQG_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x0 |
34587 | #define SQG_PERFCOUNTER7_SELECT__SPM_MODE__SHIFT 0x14 |
34588 | #define SQG_PERFCOUNTER7_SELECT__PERF_MODE__SHIFT 0x1c |
34589 | #define SQG_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0x000001FFL |
34590 | #define SQG_PERFCOUNTER7_SELECT__SPM_MODE_MASK 0x00F00000L |
34591 | #define SQG_PERFCOUNTER7_SELECT__PERF_MODE_MASK 0xF0000000L |
34592 | //SQG_PERFCOUNTER_CTRL |
34593 | #define SQG_PERFCOUNTER_CTRL__PS_EN__SHIFT 0x0 |
34594 | #define SQG_PERFCOUNTER_CTRL__GS_EN__SHIFT 0x2 |
34595 | #define SQG_PERFCOUNTER_CTRL__HS_EN__SHIFT 0x4 |
34596 | #define SQG_PERFCOUNTER_CTRL__CS_EN__SHIFT 0x6 |
34597 | #define SQG_PERFCOUNTER_CTRL__DISABLE_ME0PIPE0_PERF__SHIFT 0xe |
34598 | #define SQG_PERFCOUNTER_CTRL__DISABLE_ME0PIPE1_PERF__SHIFT 0xf |
34599 | #define SQG_PERFCOUNTER_CTRL__DISABLE_ME1PIPE0_PERF__SHIFT 0x10 |
34600 | #define SQG_PERFCOUNTER_CTRL__DISABLE_ME1PIPE1_PERF__SHIFT 0x11 |
34601 | #define SQG_PERFCOUNTER_CTRL__DISABLE_ME1PIPE2_PERF__SHIFT 0x12 |
34602 | #define SQG_PERFCOUNTER_CTRL__DISABLE_ME1PIPE3_PERF__SHIFT 0x13 |
34603 | #define SQG_PERFCOUNTER_CTRL__PS_EN_MASK 0x00000001L |
34604 | #define SQG_PERFCOUNTER_CTRL__GS_EN_MASK 0x00000004L |
34605 | #define SQG_PERFCOUNTER_CTRL__HS_EN_MASK 0x00000010L |
34606 | #define SQG_PERFCOUNTER_CTRL__CS_EN_MASK 0x00000040L |
34607 | #define SQG_PERFCOUNTER_CTRL__DISABLE_ME0PIPE0_PERF_MASK 0x00004000L |
34608 | #define SQG_PERFCOUNTER_CTRL__DISABLE_ME0PIPE1_PERF_MASK 0x00008000L |
34609 | #define SQG_PERFCOUNTER_CTRL__DISABLE_ME1PIPE0_PERF_MASK 0x00010000L |
34610 | #define SQG_PERFCOUNTER_CTRL__DISABLE_ME1PIPE1_PERF_MASK 0x00020000L |
34611 | #define SQG_PERFCOUNTER_CTRL__DISABLE_ME1PIPE2_PERF_MASK 0x00040000L |
34612 | #define SQG_PERFCOUNTER_CTRL__DISABLE_ME1PIPE3_PERF_MASK 0x00080000L |
34613 | //SQG_PERFCOUNTER_CTRL2 |
34614 | #define SQG_PERFCOUNTER_CTRL2__FORCE_EN__SHIFT 0x0 |
34615 | #define SQG_PERFCOUNTER_CTRL2__VMID_EN__SHIFT 0x1 |
34616 | #define SQG_PERFCOUNTER_CTRL2__FORCE_EN_MASK 0x00000001L |
34617 | #define SQG_PERFCOUNTER_CTRL2__VMID_EN_MASK 0x0001FFFEL |
34618 | //SQG_PERF_SAMPLE_FINISH |
34619 | #define SQG_PERF_SAMPLE_FINISH__STATUS__SHIFT 0x0 |
34620 | #define SQG_PERF_SAMPLE_FINISH__STATUS_MASK 0x0000007FL |
34621 | //SQ_PERFCOUNTER_CTRL |
34622 | #define SQ_PERFCOUNTER_CTRL__PS_EN__SHIFT 0x0 |
34623 | #define SQ_PERFCOUNTER_CTRL__GS_EN__SHIFT 0x2 |
34624 | #define SQ_PERFCOUNTER_CTRL__HS_EN__SHIFT 0x4 |
34625 | #define SQ_PERFCOUNTER_CTRL__CS_EN__SHIFT 0x6 |
34626 | #define SQ_PERFCOUNTER_CTRL__DISABLE_ME0PIPE0_PERF__SHIFT 0xe |
34627 | #define SQ_PERFCOUNTER_CTRL__DISABLE_ME0PIPE1_PERF__SHIFT 0xf |
34628 | #define SQ_PERFCOUNTER_CTRL__DISABLE_ME1PIPE0_PERF__SHIFT 0x10 |
34629 | #define SQ_PERFCOUNTER_CTRL__DISABLE_ME1PIPE1_PERF__SHIFT 0x11 |
34630 | #define SQ_PERFCOUNTER_CTRL__DISABLE_ME1PIPE2_PERF__SHIFT 0x12 |
34631 | #define SQ_PERFCOUNTER_CTRL__DISABLE_ME1PIPE3_PERF__SHIFT 0x13 |
34632 | #define SQ_PERFCOUNTER_CTRL__PS_EN_MASK 0x00000001L |
34633 | #define SQ_PERFCOUNTER_CTRL__GS_EN_MASK 0x00000004L |
34634 | #define SQ_PERFCOUNTER_CTRL__HS_EN_MASK 0x00000010L |
34635 | #define SQ_PERFCOUNTER_CTRL__CS_EN_MASK 0x00000040L |
34636 | #define SQ_PERFCOUNTER_CTRL__DISABLE_ME0PIPE0_PERF_MASK 0x00004000L |
34637 | #define SQ_PERFCOUNTER_CTRL__DISABLE_ME0PIPE1_PERF_MASK 0x00008000L |
34638 | #define SQ_PERFCOUNTER_CTRL__DISABLE_ME1PIPE0_PERF_MASK 0x00010000L |
34639 | #define SQ_PERFCOUNTER_CTRL__DISABLE_ME1PIPE1_PERF_MASK 0x00020000L |
34640 | #define SQ_PERFCOUNTER_CTRL__DISABLE_ME1PIPE2_PERF_MASK 0x00040000L |
34641 | #define SQ_PERFCOUNTER_CTRL__DISABLE_ME1PIPE3_PERF_MASK 0x00080000L |
34642 | //SQ_PERFCOUNTER_CTRL2 |
34643 | #define SQ_PERFCOUNTER_CTRL2__FORCE_EN__SHIFT 0x0 |
34644 | #define SQ_PERFCOUNTER_CTRL2__VMID_EN__SHIFT 0x1 |
34645 | #define SQ_PERFCOUNTER_CTRL2__FORCE_EN_MASK 0x00000001L |
34646 | #define SQ_PERFCOUNTER_CTRL2__VMID_EN_MASK 0x0001FFFEL |
34647 | //SQ_THREAD_TRACE_BUF0_BASE |
34648 | #define SQ_THREAD_TRACE_BUF0_BASE__BASE_LO__SHIFT 0x0 |
34649 | #define SQ_THREAD_TRACE_BUF0_BASE__BASE_LO_MASK 0xFFFFFFFFL |
34650 | //SQ_THREAD_TRACE_BUF0_SIZE |
34651 | #define SQ_THREAD_TRACE_BUF0_SIZE__BASE_HI__SHIFT 0x0 |
34652 | #define SQ_THREAD_TRACE_BUF0_SIZE__SIZE__SHIFT 0x8 |
34653 | #define SQ_THREAD_TRACE_BUF0_SIZE__BASE_HI_MASK 0x0000000FL |
34654 | #define SQ_THREAD_TRACE_BUF0_SIZE__SIZE_MASK 0x3FFFFF00L |
34655 | //SQ_THREAD_TRACE_BUF1_BASE |
34656 | #define SQ_THREAD_TRACE_BUF1_BASE__BASE_LO__SHIFT 0x0 |
34657 | #define SQ_THREAD_TRACE_BUF1_BASE__BASE_LO_MASK 0xFFFFFFFFL |
34658 | //SQ_THREAD_TRACE_BUF1_SIZE |
34659 | #define SQ_THREAD_TRACE_BUF1_SIZE__BASE_HI__SHIFT 0x0 |
34660 | #define SQ_THREAD_TRACE_BUF1_SIZE__SIZE__SHIFT 0x8 |
34661 | #define SQ_THREAD_TRACE_BUF1_SIZE__BASE_HI_MASK 0x0000000FL |
34662 | #define SQ_THREAD_TRACE_BUF1_SIZE__SIZE_MASK 0x3FFFFF00L |
34663 | //SQ_THREAD_TRACE_CTRL |
34664 | #define SQ_THREAD_TRACE_CTRL__MODE__SHIFT 0x0 |
34665 | #define SQ_THREAD_TRACE_CTRL__ALL_VMID__SHIFT 0x2 |
34666 | #define SQ_THREAD_TRACE_CTRL__GL1_PERF_EN__SHIFT 0x3 |
34667 | #define SQ_THREAD_TRACE_CTRL__INTERRUPT_EN__SHIFT 0x4 |
34668 | #define SQ_THREAD_TRACE_CTRL__DOUBLE_BUFFER__SHIFT 0x5 |
34669 | #define SQ_THREAD_TRACE_CTRL__HIWATER__SHIFT 0x6 |
34670 | #define SQ_THREAD_TRACE_CTRL__REG_AT_HWM__SHIFT 0x9 |
34671 | #define SQ_THREAD_TRACE_CTRL__SPI_STALL_EN__SHIFT 0xb |
34672 | #define SQ_THREAD_TRACE_CTRL__SQ_STALL_EN__SHIFT 0xc |
34673 | #define SQ_THREAD_TRACE_CTRL__UTIL_TIMER__SHIFT 0xd |
34674 | #define SQ_THREAD_TRACE_CTRL__WAVESTART_MODE__SHIFT 0xe |
34675 | #define SQ_THREAD_TRACE_CTRL__RT_FREQ__SHIFT 0x10 |
34676 | #define SQ_THREAD_TRACE_CTRL__SYNC_COUNT_MARKERS__SHIFT 0x12 |
34677 | #define SQ_THREAD_TRACE_CTRL__SYNC_COUNT_DRAWS__SHIFT 0x13 |
34678 | #define SQ_THREAD_TRACE_CTRL__LOWATER_OFFSET__SHIFT 0x14 |
34679 | #define SQ_THREAD_TRACE_CTRL__AUTO_FLUSH_PADDING_DIS__SHIFT 0x1c |
34680 | #define SQ_THREAD_TRACE_CTRL__AUTO_FLUSH_MODE__SHIFT 0x1d |
34681 | #define SQ_THREAD_TRACE_CTRL__DRAW_EVENT_EN__SHIFT 0x1f |
34682 | #define SQ_THREAD_TRACE_CTRL__MODE_MASK 0x00000003L |
34683 | #define SQ_THREAD_TRACE_CTRL__ALL_VMID_MASK 0x00000004L |
34684 | #define SQ_THREAD_TRACE_CTRL__GL1_PERF_EN_MASK 0x00000008L |
34685 | #define SQ_THREAD_TRACE_CTRL__INTERRUPT_EN_MASK 0x00000010L |
34686 | #define SQ_THREAD_TRACE_CTRL__DOUBLE_BUFFER_MASK 0x00000020L |
34687 | #define SQ_THREAD_TRACE_CTRL__HIWATER_MASK 0x000001C0L |
34688 | #define SQ_THREAD_TRACE_CTRL__REG_AT_HWM_MASK 0x00000600L |
34689 | #define SQ_THREAD_TRACE_CTRL__SPI_STALL_EN_MASK 0x00000800L |
34690 | #define SQ_THREAD_TRACE_CTRL__SQ_STALL_EN_MASK 0x00001000L |
34691 | #define SQ_THREAD_TRACE_CTRL__UTIL_TIMER_MASK 0x00002000L |
34692 | #define SQ_THREAD_TRACE_CTRL__WAVESTART_MODE_MASK 0x0000C000L |
34693 | #define SQ_THREAD_TRACE_CTRL__RT_FREQ_MASK 0x00030000L |
34694 | #define SQ_THREAD_TRACE_CTRL__SYNC_COUNT_MARKERS_MASK 0x00040000L |
34695 | #define SQ_THREAD_TRACE_CTRL__SYNC_COUNT_DRAWS_MASK 0x00080000L |
34696 | #define SQ_THREAD_TRACE_CTRL__LOWATER_OFFSET_MASK 0x00700000L |
34697 | #define SQ_THREAD_TRACE_CTRL__AUTO_FLUSH_PADDING_DIS_MASK 0x10000000L |
34698 | #define SQ_THREAD_TRACE_CTRL__AUTO_FLUSH_MODE_MASK 0x20000000L |
34699 | #define SQ_THREAD_TRACE_CTRL__DRAW_EVENT_EN_MASK 0x80000000L |
34700 | //SQ_THREAD_TRACE_MASK |
34701 | #define SQ_THREAD_TRACE_MASK__SIMD_SEL__SHIFT 0x0 |
34702 | #define SQ_THREAD_TRACE_MASK__WGP_SEL__SHIFT 0x4 |
34703 | #define SQ_THREAD_TRACE_MASK__SA_SEL__SHIFT 0x9 |
34704 | #define SQ_THREAD_TRACE_MASK__WTYPE_INCLUDE__SHIFT 0xa |
34705 | #define SQ_THREAD_TRACE_MASK__EXCLUDE_NONDETAIL_SHADERDATA__SHIFT 0x11 |
34706 | #define SQ_THREAD_TRACE_MASK__SIMD_SEL_MASK 0x00000003L |
34707 | #define SQ_THREAD_TRACE_MASK__WGP_SEL_MASK 0x000000F0L |
34708 | #define SQ_THREAD_TRACE_MASK__SA_SEL_MASK 0x00000200L |
34709 | #define SQ_THREAD_TRACE_MASK__WTYPE_INCLUDE_MASK 0x0001FC00L |
34710 | #define SQ_THREAD_TRACE_MASK__EXCLUDE_NONDETAIL_SHADERDATA_MASK 0x00020000L |
34711 | //SQ_THREAD_TRACE_TOKEN_MASK |
34712 | #define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_EXCLUDE__SHIFT 0x0 |
34713 | #define SQ_THREAD_TRACE_TOKEN_MASK__TTRACE_EXEC__SHIFT 0xb |
34714 | #define SQ_THREAD_TRACE_TOKEN_MASK__BOP_EVENTS_TOKEN_INCLUDE__SHIFT 0xc |
34715 | #define SQ_THREAD_TRACE_TOKEN_MASK__REG_INCLUDE__SHIFT 0x10 |
34716 | #define SQ_THREAD_TRACE_TOKEN_MASK__INST_EXCLUDE__SHIFT 0x18 |
34717 | #define SQ_THREAD_TRACE_TOKEN_MASK__REG_EXCLUDE__SHIFT 0x1a |
34718 | #define SQ_THREAD_TRACE_TOKEN_MASK__REG_DETAIL_ALL__SHIFT 0x1f |
34719 | #define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_EXCLUDE_MASK 0x000007FFL |
34720 | #define SQ_THREAD_TRACE_TOKEN_MASK__TTRACE_EXEC_MASK 0x00000800L |
34721 | #define SQ_THREAD_TRACE_TOKEN_MASK__BOP_EVENTS_TOKEN_INCLUDE_MASK 0x00001000L |
34722 | #define SQ_THREAD_TRACE_TOKEN_MASK__REG_INCLUDE_MASK 0x00FF0000L |
34723 | #define SQ_THREAD_TRACE_TOKEN_MASK__INST_EXCLUDE_MASK 0x03000000L |
34724 | #define SQ_THREAD_TRACE_TOKEN_MASK__REG_EXCLUDE_MASK 0x1C000000L |
34725 | #define SQ_THREAD_TRACE_TOKEN_MASK__REG_DETAIL_ALL_MASK 0x80000000L |
34726 | //SQ_THREAD_TRACE_WPTR |
34727 | #define SQ_THREAD_TRACE_WPTR__OFFSET__SHIFT 0x0 |
34728 | #define SQ_THREAD_TRACE_WPTR__BUFFER_ID__SHIFT 0x1f |
34729 | #define SQ_THREAD_TRACE_WPTR__OFFSET_MASK 0x1FFFFFFFL |
34730 | #define SQ_THREAD_TRACE_WPTR__BUFFER_ID_MASK 0x80000000L |
34731 | //SQ_THREAD_TRACE_STATUS |
34732 | #define SQ_THREAD_TRACE_STATUS__FINISH_PENDING__SHIFT 0x0 |
34733 | #define SQ_THREAD_TRACE_STATUS__FINISH_DONE__SHIFT 0xc |
34734 | #define SQ_THREAD_TRACE_STATUS__WRITE_ERROR__SHIFT 0x18 |
34735 | #define SQ_THREAD_TRACE_STATUS__BUSY__SHIFT 0x19 |
34736 | #define SQ_THREAD_TRACE_STATUS__OWNER_VMID__SHIFT 0x1c |
34737 | #define SQ_THREAD_TRACE_STATUS__FINISH_PENDING_MASK 0x00000FFFL |
34738 | #define SQ_THREAD_TRACE_STATUS__FINISH_DONE_MASK 0x00FFF000L |
34739 | #define SQ_THREAD_TRACE_STATUS__WRITE_ERROR_MASK 0x01000000L |
34740 | #define SQ_THREAD_TRACE_STATUS__BUSY_MASK 0x02000000L |
34741 | #define SQ_THREAD_TRACE_STATUS__OWNER_VMID_MASK 0xF0000000L |
34742 | //SQ_THREAD_TRACE_STATUS2 |
34743 | #define SQ_THREAD_TRACE_STATUS2__BUF0_FULL__SHIFT 0x0 |
34744 | #define SQ_THREAD_TRACE_STATUS2__BUF1_FULL__SHIFT 0x1 |
34745 | #define SQ_THREAD_TRACE_STATUS2__PACKET_LOST_BUF_NO_LOCKDOWN__SHIFT 0x4 |
34746 | #define SQ_THREAD_TRACE_STATUS2__BUF_ISSUE_STATUS__SHIFT 0x8 |
34747 | #define SQ_THREAD_TRACE_STATUS2__BUF_ISSUE__SHIFT 0xd |
34748 | #define SQ_THREAD_TRACE_STATUS2__WRITE_BUF_FULL__SHIFT 0xe |
34749 | #define SQ_THREAD_TRACE_STATUS2__BUF0_FULL_MASK 0x00000001L |
34750 | #define SQ_THREAD_TRACE_STATUS2__BUF1_FULL_MASK 0x00000002L |
34751 | #define SQ_THREAD_TRACE_STATUS2__PACKET_LOST_BUF_NO_LOCKDOWN_MASK 0x00000010L |
34752 | #define SQ_THREAD_TRACE_STATUS2__BUF_ISSUE_STATUS_MASK 0x00001F00L |
34753 | #define SQ_THREAD_TRACE_STATUS2__BUF_ISSUE_MASK 0x00002000L |
34754 | #define SQ_THREAD_TRACE_STATUS2__WRITE_BUF_FULL_MASK 0x00004000L |
34755 | //SQ_THREAD_TRACE_GFX_DRAW_CNTR |
34756 | #define SQ_THREAD_TRACE_GFX_DRAW_CNTR__CNTR__SHIFT 0x0 |
34757 | #define SQ_THREAD_TRACE_GFX_DRAW_CNTR__CNTR_MASK 0xFFFFFFFFL |
34758 | //SQ_THREAD_TRACE_GFX_MARKER_CNTR |
34759 | #define SQ_THREAD_TRACE_GFX_MARKER_CNTR__CNTR__SHIFT 0x0 |
34760 | #define SQ_THREAD_TRACE_GFX_MARKER_CNTR__CNTR_MASK 0xFFFFFFFFL |
34761 | //SQ_THREAD_TRACE_HP3D_DRAW_CNTR |
34762 | #define SQ_THREAD_TRACE_HP3D_DRAW_CNTR__CNTR__SHIFT 0x0 |
34763 | #define SQ_THREAD_TRACE_HP3D_DRAW_CNTR__CNTR_MASK 0xFFFFFFFFL |
34764 | //SQ_THREAD_TRACE_HP3D_MARKER_CNTR |
34765 | #define SQ_THREAD_TRACE_HP3D_MARKER_CNTR__CNTR__SHIFT 0x0 |
34766 | #define SQ_THREAD_TRACE_HP3D_MARKER_CNTR__CNTR_MASK 0xFFFFFFFFL |
34767 | //SQ_THREAD_TRACE_DROPPED_CNTR |
34768 | #define SQ_THREAD_TRACE_DROPPED_CNTR__CNTR__SHIFT 0x0 |
34769 | #define SQ_THREAD_TRACE_DROPPED_CNTR__CNTR_MASK 0xFFFFFFFFL |
34770 | //GCEA_PERFCOUNTER2_SELECT |
34771 | #define GCEA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 |
34772 | #define GCEA_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa |
34773 | #define GCEA_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 |
34774 | #define GCEA_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 |
34775 | #define GCEA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c |
34776 | #define GCEA_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL |
34777 | #define GCEA_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L |
34778 | #define GCEA_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L |
34779 | #define GCEA_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L |
34780 | #define GCEA_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L |
34781 | //GCEA_PERFCOUNTER2_SELECT1 |
34782 | #define GCEA_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 |
34783 | #define GCEA_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa |
34784 | #define GCEA_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18 |
34785 | #define GCEA_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c |
34786 | #define GCEA_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL |
34787 | #define GCEA_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
34788 | #define GCEA_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L |
34789 | #define GCEA_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L |
34790 | //GCEA_PERFCOUNTER2_MODE |
34791 | #define GCEA_PERFCOUNTER2_MODE__COMPARE_MODE0__SHIFT 0x0 |
34792 | #define GCEA_PERFCOUNTER2_MODE__COMPARE_MODE1__SHIFT 0x2 |
34793 | #define GCEA_PERFCOUNTER2_MODE__COMPARE_MODE2__SHIFT 0x4 |
34794 | #define GCEA_PERFCOUNTER2_MODE__COMPARE_MODE3__SHIFT 0x6 |
34795 | #define GCEA_PERFCOUNTER2_MODE__COMPARE_VALUE0__SHIFT 0x8 |
34796 | #define GCEA_PERFCOUNTER2_MODE__COMPARE_VALUE1__SHIFT 0xc |
34797 | #define GCEA_PERFCOUNTER2_MODE__COMPARE_VALUE2__SHIFT 0x10 |
34798 | #define GCEA_PERFCOUNTER2_MODE__COMPARE_VALUE3__SHIFT 0x14 |
34799 | #define GCEA_PERFCOUNTER2_MODE__COMPARE_MODE0_MASK 0x00000003L |
34800 | #define GCEA_PERFCOUNTER2_MODE__COMPARE_MODE1_MASK 0x0000000CL |
34801 | #define GCEA_PERFCOUNTER2_MODE__COMPARE_MODE2_MASK 0x00000030L |
34802 | #define GCEA_PERFCOUNTER2_MODE__COMPARE_MODE3_MASK 0x000000C0L |
34803 | #define GCEA_PERFCOUNTER2_MODE__COMPARE_VALUE0_MASK 0x00000F00L |
34804 | #define GCEA_PERFCOUNTER2_MODE__COMPARE_VALUE1_MASK 0x0000F000L |
34805 | #define GCEA_PERFCOUNTER2_MODE__COMPARE_VALUE2_MASK 0x000F0000L |
34806 | #define GCEA_PERFCOUNTER2_MODE__COMPARE_VALUE3_MASK 0x00F00000L |
34807 | //GCEA_PERFCOUNTER0_CFG |
34808 | #define GCEA_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 |
34809 | #define GCEA_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 |
34810 | #define GCEA_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 |
34811 | #define GCEA_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c |
34812 | #define GCEA_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d |
34813 | #define GCEA_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL |
34814 | #define GCEA_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L |
34815 | #define GCEA_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L |
34816 | #define GCEA_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L |
34817 | #define GCEA_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L |
34818 | //GCEA_PERFCOUNTER1_CFG |
34819 | #define GCEA_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 |
34820 | #define GCEA_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 |
34821 | #define GCEA_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 |
34822 | #define GCEA_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c |
34823 | #define GCEA_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d |
34824 | #define GCEA_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL |
34825 | #define GCEA_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L |
34826 | #define GCEA_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L |
34827 | #define GCEA_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L |
34828 | #define GCEA_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L |
34829 | //GCEA_PERFCOUNTER_RSLT_CNTL |
34830 | #define GCEA_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 |
34831 | #define GCEA_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 |
34832 | #define GCEA_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 |
34833 | #define GCEA_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 |
34834 | #define GCEA_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 |
34835 | #define GCEA_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a |
34836 | #define GCEA_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL |
34837 | #define GCEA_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L |
34838 | #define GCEA_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L |
34839 | #define GCEA_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L |
34840 | #define GCEA_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L |
34841 | #define GCEA_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L |
34842 | //SX_PERFCOUNTER0_SELECT |
34843 | #define SX_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
34844 | #define SX_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
34845 | #define SX_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 |
34846 | #define SX_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 |
34847 | #define SX_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c |
34848 | #define SX_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL |
34849 | #define SX_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L |
34850 | #define SX_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L |
34851 | #define SX_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L |
34852 | #define SX_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L |
34853 | //SX_PERFCOUNTER1_SELECT |
34854 | #define SX_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
34855 | #define SX_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa |
34856 | #define SX_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 |
34857 | #define SX_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 |
34858 | #define SX_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c |
34859 | #define SX_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL |
34860 | #define SX_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L |
34861 | #define SX_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L |
34862 | #define SX_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L |
34863 | #define SX_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L |
34864 | //SX_PERFCOUNTER2_SELECT |
34865 | #define SX_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 |
34866 | #define SX_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 |
34867 | #define SX_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c |
34868 | #define SX_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL |
34869 | #define SX_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L |
34870 | #define SX_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L |
34871 | //SX_PERFCOUNTER3_SELECT |
34872 | #define SX_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 |
34873 | #define SX_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 |
34874 | #define SX_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c |
34875 | #define SX_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL |
34876 | #define SX_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L |
34877 | #define SX_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L |
34878 | //SX_PERFCOUNTER0_SELECT1 |
34879 | #define SX_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
34880 | #define SX_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
34881 | #define SX_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 |
34882 | #define SX_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c |
34883 | #define SX_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL |
34884 | #define SX_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
34885 | #define SX_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L |
34886 | #define SX_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L |
34887 | //SX_PERFCOUNTER1_SELECT1 |
34888 | #define SX_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 |
34889 | #define SX_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa |
34890 | #define SX_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 |
34891 | #define SX_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c |
34892 | #define SX_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL |
34893 | #define SX_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
34894 | #define SX_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L |
34895 | #define SX_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L |
34896 | //GDS_PERFCOUNTER0_SELECT |
34897 | #define GDS_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
34898 | #define GDS_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
34899 | #define GDS_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 |
34900 | #define GDS_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 |
34901 | #define GDS_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c |
34902 | #define GDS_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL |
34903 | #define GDS_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L |
34904 | #define GDS_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L |
34905 | #define GDS_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L |
34906 | #define GDS_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L |
34907 | //GDS_PERFCOUNTER1_SELECT |
34908 | #define GDS_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
34909 | #define GDS_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa |
34910 | #define GDS_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 |
34911 | #define GDS_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 |
34912 | #define GDS_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c |
34913 | #define GDS_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL |
34914 | #define GDS_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L |
34915 | #define GDS_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L |
34916 | #define GDS_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L |
34917 | #define GDS_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L |
34918 | //GDS_PERFCOUNTER2_SELECT |
34919 | #define GDS_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 |
34920 | #define GDS_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa |
34921 | #define GDS_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 |
34922 | #define GDS_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 |
34923 | #define GDS_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c |
34924 | #define GDS_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL |
34925 | #define GDS_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L |
34926 | #define GDS_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L |
34927 | #define GDS_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L |
34928 | #define GDS_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L |
34929 | //GDS_PERFCOUNTER3_SELECT |
34930 | #define GDS_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 |
34931 | #define GDS_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa |
34932 | #define GDS_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 |
34933 | #define GDS_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18 |
34934 | #define GDS_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c |
34935 | #define GDS_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL |
34936 | #define GDS_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L |
34937 | #define GDS_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L |
34938 | #define GDS_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L |
34939 | #define GDS_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L |
34940 | //GDS_PERFCOUNTER0_SELECT1 |
34941 | #define GDS_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
34942 | #define GDS_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
34943 | #define GDS_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 |
34944 | #define GDS_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c |
34945 | #define GDS_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL |
34946 | #define GDS_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
34947 | #define GDS_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L |
34948 | #define GDS_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L |
34949 | //GDS_PERFCOUNTER1_SELECT1 |
34950 | #define GDS_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 |
34951 | #define GDS_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa |
34952 | #define GDS_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 |
34953 | #define GDS_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c |
34954 | #define GDS_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL |
34955 | #define GDS_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
34956 | #define GDS_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L |
34957 | #define GDS_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L |
34958 | //GDS_PERFCOUNTER2_SELECT1 |
34959 | #define GDS_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 |
34960 | #define GDS_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa |
34961 | #define GDS_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18 |
34962 | #define GDS_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c |
34963 | #define GDS_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL |
34964 | #define GDS_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
34965 | #define GDS_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L |
34966 | #define GDS_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L |
34967 | //GDS_PERFCOUNTER3_SELECT1 |
34968 | #define GDS_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0 |
34969 | #define GDS_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa |
34970 | #define GDS_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT 0x18 |
34971 | #define GDS_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT 0x1c |
34972 | #define GDS_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003FFL |
34973 | #define GDS_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
34974 | #define GDS_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK 0x0F000000L |
34975 | #define GDS_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK 0xF0000000L |
34976 | //TA_PERFCOUNTER0_SELECT |
34977 | #define TA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
34978 | #define TA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
34979 | #define TA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 |
34980 | #define TA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 |
34981 | #define TA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c |
34982 | #define TA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL |
34983 | #define TA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L |
34984 | #define TA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L |
34985 | #define TA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L |
34986 | #define TA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L |
34987 | //TA_PERFCOUNTER0_SELECT1 |
34988 | #define TA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
34989 | #define TA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
34990 | #define TA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 |
34991 | #define TA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c |
34992 | #define TA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL |
34993 | #define TA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
34994 | #define TA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L |
34995 | #define TA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L |
34996 | //TA_PERFCOUNTER1_SELECT |
34997 | #define TA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
34998 | #define TA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 |
34999 | #define TA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c |
35000 | #define TA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL |
35001 | #define TA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L |
35002 | #define TA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L |
35003 | //TD_PERFCOUNTER0_SELECT |
35004 | #define TD_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
35005 | #define TD_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
35006 | #define TD_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 |
35007 | #define TD_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 |
35008 | #define TD_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c |
35009 | #define TD_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL |
35010 | #define TD_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L |
35011 | #define TD_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L |
35012 | #define TD_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L |
35013 | #define TD_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L |
35014 | //TD_PERFCOUNTER0_SELECT1 |
35015 | #define TD_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
35016 | #define TD_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
35017 | #define TD_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 |
35018 | #define TD_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c |
35019 | #define TD_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL |
35020 | #define TD_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
35021 | #define TD_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L |
35022 | #define TD_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L |
35023 | //TD_PERFCOUNTER1_SELECT |
35024 | #define TD_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
35025 | #define TD_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 |
35026 | #define TD_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c |
35027 | #define TD_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL |
35028 | #define TD_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L |
35029 | #define TD_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L |
35030 | //TCP_PERFCOUNTER0_SELECT |
35031 | #define TCP_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
35032 | #define TCP_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
35033 | #define TCP_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 |
35034 | #define TCP_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 |
35035 | #define TCP_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c |
35036 | #define TCP_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL |
35037 | #define TCP_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L |
35038 | #define TCP_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L |
35039 | #define TCP_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L |
35040 | #define TCP_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L |
35041 | //TCP_PERFCOUNTER0_SELECT1 |
35042 | #define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
35043 | #define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
35044 | #define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 |
35045 | #define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c |
35046 | #define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL |
35047 | #define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
35048 | #define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L |
35049 | #define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L |
35050 | //TCP_PERFCOUNTER1_SELECT |
35051 | #define TCP_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
35052 | #define TCP_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa |
35053 | #define TCP_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 |
35054 | #define TCP_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 |
35055 | #define TCP_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c |
35056 | #define TCP_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL |
35057 | #define TCP_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L |
35058 | #define TCP_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L |
35059 | #define TCP_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L |
35060 | #define TCP_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L |
35061 | //TCP_PERFCOUNTER1_SELECT1 |
35062 | #define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 |
35063 | #define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa |
35064 | #define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 |
35065 | #define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c |
35066 | #define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL |
35067 | #define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
35068 | #define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L |
35069 | #define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L |
35070 | //TCP_PERFCOUNTER2_SELECT |
35071 | #define TCP_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 |
35072 | #define TCP_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 |
35073 | #define TCP_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c |
35074 | #define TCP_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL |
35075 | #define TCP_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L |
35076 | #define TCP_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L |
35077 | //TCP_PERFCOUNTER3_SELECT |
35078 | #define TCP_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 |
35079 | #define TCP_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 |
35080 | #define TCP_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c |
35081 | #define TCP_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL |
35082 | #define TCP_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L |
35083 | #define TCP_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L |
35084 | //GL2C_PERFCOUNTER0_SELECT |
35085 | #define GL2C_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
35086 | #define GL2C_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
35087 | #define GL2C_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 |
35088 | #define GL2C_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 |
35089 | #define GL2C_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c |
35090 | #define GL2C_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL |
35091 | #define GL2C_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L |
35092 | #define GL2C_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L |
35093 | #define GL2C_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L |
35094 | #define GL2C_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L |
35095 | //GL2C_PERFCOUNTER0_SELECT1 |
35096 | #define GL2C_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
35097 | #define GL2C_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
35098 | #define GL2C_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18 |
35099 | #define GL2C_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c |
35100 | #define GL2C_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL |
35101 | #define GL2C_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
35102 | #define GL2C_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0x0F000000L |
35103 | #define GL2C_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xF0000000L |
35104 | //GL2C_PERFCOUNTER1_SELECT |
35105 | #define GL2C_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
35106 | #define GL2C_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa |
35107 | #define GL2C_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 |
35108 | #define GL2C_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 |
35109 | #define GL2C_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c |
35110 | #define GL2C_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL |
35111 | #define GL2C_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L |
35112 | #define GL2C_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L |
35113 | #define GL2C_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L |
35114 | #define GL2C_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L |
35115 | //GL2C_PERFCOUNTER1_SELECT1 |
35116 | #define GL2C_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 |
35117 | #define GL2C_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa |
35118 | #define GL2C_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x18 |
35119 | #define GL2C_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x1c |
35120 | #define GL2C_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL |
35121 | #define GL2C_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
35122 | #define GL2C_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0x0F000000L |
35123 | #define GL2C_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xF0000000L |
35124 | //GL2C_PERFCOUNTER2_SELECT |
35125 | #define GL2C_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 |
35126 | #define GL2C_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 |
35127 | #define GL2C_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c |
35128 | #define GL2C_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL |
35129 | #define GL2C_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L |
35130 | #define GL2C_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L |
35131 | //GL2C_PERFCOUNTER3_SELECT |
35132 | #define GL2C_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 |
35133 | #define GL2C_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 |
35134 | #define GL2C_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c |
35135 | #define GL2C_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL |
35136 | #define GL2C_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L |
35137 | #define GL2C_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L |
35138 | //GL2A_PERFCOUNTER0_SELECT |
35139 | #define GL2A_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
35140 | #define GL2A_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
35141 | #define GL2A_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 |
35142 | #define GL2A_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 |
35143 | #define GL2A_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c |
35144 | #define GL2A_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL |
35145 | #define GL2A_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L |
35146 | #define GL2A_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L |
35147 | #define GL2A_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L |
35148 | #define GL2A_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L |
35149 | //GL2A_PERFCOUNTER0_SELECT1 |
35150 | #define GL2A_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
35151 | #define GL2A_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
35152 | #define GL2A_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18 |
35153 | #define GL2A_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c |
35154 | #define GL2A_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL |
35155 | #define GL2A_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
35156 | #define GL2A_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0x0F000000L |
35157 | #define GL2A_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xF0000000L |
35158 | //GL2A_PERFCOUNTER1_SELECT |
35159 | #define GL2A_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
35160 | #define GL2A_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa |
35161 | #define GL2A_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 |
35162 | #define GL2A_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 |
35163 | #define GL2A_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c |
35164 | #define GL2A_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL |
35165 | #define GL2A_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L |
35166 | #define GL2A_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L |
35167 | #define GL2A_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L |
35168 | #define GL2A_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L |
35169 | //GL2A_PERFCOUNTER1_SELECT1 |
35170 | #define GL2A_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 |
35171 | #define GL2A_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa |
35172 | #define GL2A_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x18 |
35173 | #define GL2A_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x1c |
35174 | #define GL2A_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL |
35175 | #define GL2A_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
35176 | #define GL2A_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0x0F000000L |
35177 | #define GL2A_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xF0000000L |
35178 | //GL2A_PERFCOUNTER2_SELECT |
35179 | #define GL2A_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 |
35180 | #define GL2A_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 |
35181 | #define GL2A_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c |
35182 | #define GL2A_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL |
35183 | #define GL2A_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L |
35184 | #define GL2A_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L |
35185 | //GL2A_PERFCOUNTER3_SELECT |
35186 | #define GL2A_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 |
35187 | #define GL2A_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 |
35188 | #define GL2A_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c |
35189 | #define GL2A_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL |
35190 | #define GL2A_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L |
35191 | #define GL2A_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L |
35192 | //GL1C_PERFCOUNTER0_SELECT |
35193 | #define GL1C_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
35194 | #define GL1C_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
35195 | #define GL1C_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 |
35196 | #define GL1C_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 |
35197 | #define GL1C_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c |
35198 | #define GL1C_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL |
35199 | #define GL1C_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L |
35200 | #define GL1C_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L |
35201 | #define GL1C_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L |
35202 | #define GL1C_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L |
35203 | //GL1C_PERFCOUNTER0_SELECT1 |
35204 | #define GL1C_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
35205 | #define GL1C_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
35206 | #define GL1C_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18 |
35207 | #define GL1C_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c |
35208 | #define GL1C_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL |
35209 | #define GL1C_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
35210 | #define GL1C_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0x0F000000L |
35211 | #define GL1C_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xF0000000L |
35212 | //GL1C_PERFCOUNTER1_SELECT |
35213 | #define GL1C_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
35214 | #define GL1C_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 |
35215 | #define GL1C_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c |
35216 | #define GL1C_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL |
35217 | #define GL1C_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L |
35218 | #define GL1C_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L |
35219 | //GL1C_PERFCOUNTER2_SELECT |
35220 | #define GL1C_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 |
35221 | #define GL1C_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 |
35222 | #define GL1C_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c |
35223 | #define GL1C_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL |
35224 | #define GL1C_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L |
35225 | #define GL1C_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L |
35226 | //GL1C_PERFCOUNTER3_SELECT |
35227 | #define GL1C_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 |
35228 | #define GL1C_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 |
35229 | #define GL1C_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c |
35230 | #define GL1C_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL |
35231 | #define GL1C_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L |
35232 | #define GL1C_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L |
35233 | //CHC_PERFCOUNTER0_SELECT |
35234 | #define CHC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
35235 | #define CHC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
35236 | #define CHC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 |
35237 | #define CHC_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 |
35238 | #define CHC_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c |
35239 | #define CHC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL |
35240 | #define CHC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L |
35241 | #define CHC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L |
35242 | #define CHC_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L |
35243 | #define CHC_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L |
35244 | //CHC_PERFCOUNTER0_SELECT1 |
35245 | #define CHC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
35246 | #define CHC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
35247 | #define CHC_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18 |
35248 | #define CHC_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c |
35249 | #define CHC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL |
35250 | #define CHC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
35251 | #define CHC_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0x0F000000L |
35252 | #define CHC_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xF0000000L |
35253 | //CHC_PERFCOUNTER1_SELECT |
35254 | #define CHC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
35255 | #define CHC_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 |
35256 | #define CHC_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c |
35257 | #define CHC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL |
35258 | #define CHC_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L |
35259 | #define CHC_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L |
35260 | //CHC_PERFCOUNTER2_SELECT |
35261 | #define CHC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 |
35262 | #define CHC_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 |
35263 | #define CHC_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c |
35264 | #define CHC_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL |
35265 | #define CHC_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L |
35266 | #define CHC_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L |
35267 | //CHC_PERFCOUNTER3_SELECT |
35268 | #define CHC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 |
35269 | #define CHC_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 |
35270 | #define CHC_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c |
35271 | #define CHC_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL |
35272 | #define CHC_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L |
35273 | #define CHC_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L |
35274 | //CHCG_PERFCOUNTER0_SELECT |
35275 | #define CHCG_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
35276 | #define CHCG_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
35277 | #define CHCG_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 |
35278 | #define CHCG_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 |
35279 | #define CHCG_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c |
35280 | #define CHCG_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL |
35281 | #define CHCG_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L |
35282 | #define CHCG_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L |
35283 | #define CHCG_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L |
35284 | #define CHCG_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L |
35285 | //CHCG_PERFCOUNTER0_SELECT1 |
35286 | #define CHCG_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
35287 | #define CHCG_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
35288 | #define CHCG_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18 |
35289 | #define CHCG_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c |
35290 | #define CHCG_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL |
35291 | #define CHCG_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
35292 | #define CHCG_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0x0F000000L |
35293 | #define CHCG_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xF0000000L |
35294 | //CHCG_PERFCOUNTER1_SELECT |
35295 | #define CHCG_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
35296 | #define CHCG_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 |
35297 | #define CHCG_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c |
35298 | #define CHCG_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL |
35299 | #define CHCG_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L |
35300 | #define CHCG_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L |
35301 | //CHCG_PERFCOUNTER2_SELECT |
35302 | #define CHCG_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 |
35303 | #define CHCG_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 |
35304 | #define CHCG_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c |
35305 | #define CHCG_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL |
35306 | #define CHCG_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L |
35307 | #define CHCG_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L |
35308 | //CHCG_PERFCOUNTER3_SELECT |
35309 | #define CHCG_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 |
35310 | #define CHCG_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 |
35311 | #define CHCG_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c |
35312 | #define CHCG_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL |
35313 | #define CHCG_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L |
35314 | #define CHCG_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L |
35315 | //CB_PERFCOUNTER_FILTER |
35316 | #define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE__SHIFT 0x0 |
35317 | #define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL__SHIFT 0x1 |
35318 | #define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE__SHIFT 0x4 |
35319 | #define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL__SHIFT 0x5 |
35320 | #define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE__SHIFT 0xa |
35321 | #define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL__SHIFT 0xb |
35322 | #define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE__SHIFT 0xc |
35323 | #define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL__SHIFT 0xd |
35324 | #define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE__SHIFT 0x11 |
35325 | #define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL__SHIFT 0x12 |
35326 | #define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE__SHIFT 0x15 |
35327 | #define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL__SHIFT 0x16 |
35328 | #define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE_MASK 0x00000001L |
35329 | #define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL_MASK 0x0000000EL |
35330 | #define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE_MASK 0x00000010L |
35331 | #define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL_MASK 0x000003E0L |
35332 | #define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE_MASK 0x00000400L |
35333 | #define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL_MASK 0x00000800L |
35334 | #define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE_MASK 0x00001000L |
35335 | #define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL_MASK 0x0000E000L |
35336 | #define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE_MASK 0x00020000L |
35337 | #define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL_MASK 0x001C0000L |
35338 | #define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE_MASK 0x00200000L |
35339 | #define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL_MASK 0x00C00000L |
35340 | //CB_PERFCOUNTER0_SELECT |
35341 | #define CB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
35342 | #define CB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
35343 | #define CB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 |
35344 | #define CB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 |
35345 | #define CB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c |
35346 | #define CB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL |
35347 | #define CB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L |
35348 | #define CB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L |
35349 | #define CB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L |
35350 | #define CB_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L |
35351 | //CB_PERFCOUNTER0_SELECT1 |
35352 | #define CB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
35353 | #define CB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
35354 | #define CB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 |
35355 | #define CB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c |
35356 | #define CB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL |
35357 | #define CB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
35358 | #define CB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L |
35359 | #define CB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L |
35360 | //CB_PERFCOUNTER1_SELECT |
35361 | #define CB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
35362 | #define CB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c |
35363 | #define CB_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL |
35364 | #define CB_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L |
35365 | //CB_PERFCOUNTER2_SELECT |
35366 | #define CB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 |
35367 | #define CB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c |
35368 | #define CB_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL |
35369 | #define CB_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L |
35370 | //CB_PERFCOUNTER3_SELECT |
35371 | #define CB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 |
35372 | #define CB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c |
35373 | #define CB_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL |
35374 | #define CB_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L |
35375 | //DB_PERFCOUNTER0_SELECT |
35376 | #define DB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
35377 | #define DB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
35378 | #define DB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 |
35379 | #define DB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 |
35380 | #define DB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c |
35381 | #define DB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL |
35382 | #define DB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L |
35383 | #define DB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L |
35384 | #define DB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L |
35385 | #define DB_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L |
35386 | //DB_PERFCOUNTER0_SELECT1 |
35387 | #define DB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
35388 | #define DB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
35389 | #define DB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 |
35390 | #define DB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c |
35391 | #define DB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL |
35392 | #define DB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
35393 | #define DB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L |
35394 | #define DB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L |
35395 | //DB_PERFCOUNTER1_SELECT |
35396 | #define DB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
35397 | #define DB_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa |
35398 | #define DB_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 |
35399 | #define DB_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 |
35400 | #define DB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c |
35401 | #define DB_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL |
35402 | #define DB_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L |
35403 | #define DB_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L |
35404 | #define DB_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L |
35405 | #define DB_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L |
35406 | //DB_PERFCOUNTER1_SELECT1 |
35407 | #define DB_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 |
35408 | #define DB_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa |
35409 | #define DB_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 |
35410 | #define DB_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c |
35411 | #define DB_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL |
35412 | #define DB_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
35413 | #define DB_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L |
35414 | #define DB_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L |
35415 | //DB_PERFCOUNTER2_SELECT |
35416 | #define DB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 |
35417 | #define DB_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa |
35418 | #define DB_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 |
35419 | #define DB_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 |
35420 | #define DB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c |
35421 | #define DB_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL |
35422 | #define DB_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L |
35423 | #define DB_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L |
35424 | #define DB_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L |
35425 | #define DB_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L |
35426 | //DB_PERFCOUNTER3_SELECT |
35427 | #define DB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 |
35428 | #define DB_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa |
35429 | #define DB_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 |
35430 | #define DB_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18 |
35431 | #define DB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c |
35432 | #define DB_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL |
35433 | #define DB_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L |
35434 | #define DB_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L |
35435 | #define DB_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L |
35436 | #define DB_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L |
35437 | //RLC_SPM_PERFMON_CNTL |
35438 | #define RLC_SPM_PERFMON_CNTL__RESERVED1__SHIFT 0x0 |
35439 | #define RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE__SHIFT 0xc |
35440 | #define RLC_SPM_PERFMON_CNTL__DISABLE_GFXCLOCK_COUNT__SHIFT 0xe |
35441 | #define RLC_SPM_PERFMON_CNTL__RESERVED__SHIFT 0xf |
35442 | #define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL__SHIFT 0x10 |
35443 | #define RLC_SPM_PERFMON_CNTL__RESERVED1_MASK 0x00000FFFL |
35444 | #define RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE_MASK 0x00003000L |
35445 | #define RLC_SPM_PERFMON_CNTL__DISABLE_GFXCLOCK_COUNT_MASK 0x00004000L |
35446 | #define RLC_SPM_PERFMON_CNTL__RESERVED_MASK 0x00008000L |
35447 | #define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL_MASK 0xFFFF0000L |
35448 | //RLC_SPM_PERFMON_RING_BASE_LO |
35449 | #define RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO__SHIFT 0x0 |
35450 | #define RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO_MASK 0xFFFFFFFFL |
35451 | //RLC_SPM_PERFMON_RING_BASE_HI |
35452 | #define RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI__SHIFT 0x0 |
35453 | #define RLC_SPM_PERFMON_RING_BASE_HI__RESERVED__SHIFT 0x10 |
35454 | #define RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI_MASK 0x0000FFFFL |
35455 | #define RLC_SPM_PERFMON_RING_BASE_HI__RESERVED_MASK 0xFFFF0000L |
35456 | //RLC_SPM_PERFMON_RING_SIZE |
35457 | #define RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE__SHIFT 0x0 |
35458 | #define RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE_MASK 0xFFFFFFFFL |
35459 | //RLC_SPM_RING_WRPTR |
35460 | #define RLC_SPM_RING_WRPTR__RESERVED__SHIFT 0x0 |
35461 | #define RLC_SPM_RING_WRPTR__PERFMON_RING_WRPTR__SHIFT 0x5 |
35462 | #define RLC_SPM_RING_WRPTR__RESERVED_MASK 0x0000001FL |
35463 | #define RLC_SPM_RING_WRPTR__PERFMON_RING_WRPTR_MASK 0xFFFFFFE0L |
35464 | //RLC_SPM_RING_RDPTR |
35465 | #define RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR__SHIFT 0x0 |
35466 | #define RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR_MASK 0xFFFFFFFFL |
35467 | //RLC_SPM_SEGMENT_THRESHOLD |
35468 | #define RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD__SHIFT 0x0 |
35469 | #define RLC_SPM_SEGMENT_THRESHOLD__RESERVED__SHIFT 0x8 |
35470 | #define RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD_MASK 0x000000FFL |
35471 | #define RLC_SPM_SEGMENT_THRESHOLD__RESERVED_MASK 0xFFFFFF00L |
35472 | //RLC_SPM_PERFMON_SEGMENT_SIZE |
35473 | #define RLC_SPM_PERFMON_SEGMENT_SIZE__TOTAL_NUM_SEGMENT__SHIFT 0x0 |
35474 | #define RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_SEGMENT__SHIFT 0x10 |
35475 | #define RLC_SPM_PERFMON_SEGMENT_SIZE__SE_NUM_SEGMENT__SHIFT 0x18 |
35476 | #define RLC_SPM_PERFMON_SEGMENT_SIZE__TOTAL_NUM_SEGMENT_MASK 0x0000FFFFL |
35477 | #define RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_SEGMENT_MASK 0x00FF0000L |
35478 | #define RLC_SPM_PERFMON_SEGMENT_SIZE__SE_NUM_SEGMENT_MASK 0xFF000000L |
35479 | //RLC_SPM_GLOBAL_MUXSEL_ADDR |
35480 | #define RLC_SPM_GLOBAL_MUXSEL_ADDR__ADDR__SHIFT 0x0 |
35481 | #define RLC_SPM_GLOBAL_MUXSEL_ADDR__ADDR_MASK 0x00000FFFL |
35482 | //RLC_SPM_GLOBAL_MUXSEL_DATA |
35483 | #define RLC_SPM_GLOBAL_MUXSEL_DATA__SEL0__SHIFT 0x0 |
35484 | #define RLC_SPM_GLOBAL_MUXSEL_DATA__SEL1__SHIFT 0x10 |
35485 | #define RLC_SPM_GLOBAL_MUXSEL_DATA__SEL0_MASK 0x0000FFFFL |
35486 | #define RLC_SPM_GLOBAL_MUXSEL_DATA__SEL1_MASK 0xFFFF0000L |
35487 | //RLC_SPM_SE_MUXSEL_ADDR |
35488 | #define RLC_SPM_SE_MUXSEL_ADDR__ADDR__SHIFT 0x0 |
35489 | #define RLC_SPM_SE_MUXSEL_ADDR__ADDR_MASK 0x00000FFFL |
35490 | //RLC_SPM_SE_MUXSEL_DATA |
35491 | #define RLC_SPM_SE_MUXSEL_DATA__SEL0__SHIFT 0x0 |
35492 | #define RLC_SPM_SE_MUXSEL_DATA__SEL1__SHIFT 0x10 |
35493 | #define RLC_SPM_SE_MUXSEL_DATA__SEL0_MASK 0x0000FFFFL |
35494 | #define RLC_SPM_SE_MUXSEL_DATA__SEL1_MASK 0xFFFF0000L |
35495 | //RLC_SPM_ACCUM_DATARAM_ADDR |
35496 | #define RLC_SPM_ACCUM_DATARAM_ADDR__addr__SHIFT 0x0 |
35497 | #define RLC_SPM_ACCUM_DATARAM_ADDR__RESERVED__SHIFT 0x7 |
35498 | #define RLC_SPM_ACCUM_DATARAM_ADDR__addr_MASK 0x0000007FL |
35499 | #define RLC_SPM_ACCUM_DATARAM_ADDR__RESERVED_MASK 0xFFFFFF80L |
35500 | //RLC_SPM_ACCUM_DATARAM_DATA |
35501 | #define RLC_SPM_ACCUM_DATARAM_DATA__data__SHIFT 0x0 |
35502 | #define RLC_SPM_ACCUM_DATARAM_DATA__data_MASK 0xFFFFFFFFL |
35503 | //RLC_SPM_ACCUM_SWA_DATARAM_ADDR |
35504 | #define RLC_SPM_ACCUM_SWA_DATARAM_ADDR__addr__SHIFT 0x0 |
35505 | #define RLC_SPM_ACCUM_SWA_DATARAM_ADDR__RESERVED__SHIFT 0x7 |
35506 | #define RLC_SPM_ACCUM_SWA_DATARAM_ADDR__addr_MASK 0x0000007FL |
35507 | #define RLC_SPM_ACCUM_SWA_DATARAM_ADDR__RESERVED_MASK 0xFFFFFF80L |
35508 | //RLC_SPM_ACCUM_SWA_DATARAM_DATA |
35509 | #define RLC_SPM_ACCUM_SWA_DATARAM_DATA__data__SHIFT 0x0 |
35510 | #define RLC_SPM_ACCUM_SWA_DATARAM_DATA__data_MASK 0xFFFFFFFFL |
35511 | //RLC_SPM_ACCUM_CTRLRAM_ADDR |
35512 | #define RLC_SPM_ACCUM_CTRLRAM_ADDR__addr__SHIFT 0x0 |
35513 | #define RLC_SPM_ACCUM_CTRLRAM_ADDR__RESERVED__SHIFT 0xb |
35514 | #define RLC_SPM_ACCUM_CTRLRAM_ADDR__addr_MASK 0x000007FFL |
35515 | #define RLC_SPM_ACCUM_CTRLRAM_ADDR__RESERVED_MASK 0xFFFFF800L |
35516 | //RLC_SPM_ACCUM_CTRLRAM_DATA |
35517 | #define RLC_SPM_ACCUM_CTRLRAM_DATA__data__SHIFT 0x0 |
35518 | #define RLC_SPM_ACCUM_CTRLRAM_DATA__RESERVED__SHIFT 0x8 |
35519 | #define RLC_SPM_ACCUM_CTRLRAM_DATA__data_MASK 0x000000FFL |
35520 | #define RLC_SPM_ACCUM_CTRLRAM_DATA__RESERVED_MASK 0xFFFFFF00L |
35521 | //RLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET |
35522 | #define RLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET__global_offset__SHIFT 0x0 |
35523 | #define RLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET__spmwithaccum_se_offset__SHIFT 0x8 |
35524 | #define RLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET__spmwithaccum_global_offset__SHIFT 0x10 |
35525 | #define RLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET__RESERVED__SHIFT 0x18 |
35526 | #define RLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET__global_offset_MASK 0x000000FFL |
35527 | #define RLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET__spmwithaccum_se_offset_MASK 0x0000FF00L |
35528 | #define RLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET__spmwithaccum_global_offset_MASK 0x00FF0000L |
35529 | #define RLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET__RESERVED_MASK 0xFF000000L |
35530 | //RLC_SPM_ACCUM_STATUS |
35531 | #define RLC_SPM_ACCUM_STATUS__NumbSamplesCompleted__SHIFT 0x0 |
35532 | #define RLC_SPM_ACCUM_STATUS__AccumDone__SHIFT 0x8 |
35533 | #define RLC_SPM_ACCUM_STATUS__SpmDone__SHIFT 0x9 |
35534 | #define RLC_SPM_ACCUM_STATUS__AccumOverflow__SHIFT 0xa |
35535 | #define RLC_SPM_ACCUM_STATUS__AccumArmed__SHIFT 0xb |
35536 | #define RLC_SPM_ACCUM_STATUS__SequenceInProgress__SHIFT 0xc |
35537 | #define RLC_SPM_ACCUM_STATUS__FinalSequenceInProgress__SHIFT 0xd |
35538 | #define RLC_SPM_ACCUM_STATUS__AllFifosEmpty__SHIFT 0xe |
35539 | #define RLC_SPM_ACCUM_STATUS__FSMIsIdle__SHIFT 0xf |
35540 | #define RLC_SPM_ACCUM_STATUS__SwaAccumDone__SHIFT 0x10 |
35541 | #define RLC_SPM_ACCUM_STATUS__SwaSpmDone__SHIFT 0x11 |
35542 | #define RLC_SPM_ACCUM_STATUS__SwaAccumOverflow__SHIFT 0x12 |
35543 | #define RLC_SPM_ACCUM_STATUS__SwaAccumArmed__SHIFT 0x13 |
35544 | #define RLC_SPM_ACCUM_STATUS__AllSegsDone__SHIFT 0x14 |
35545 | #define RLC_SPM_ACCUM_STATUS__RearmSwaPending__SHIFT 0x15 |
35546 | #define RLC_SPM_ACCUM_STATUS__RearmSppPending__SHIFT 0x16 |
35547 | #define RLC_SPM_ACCUM_STATUS__MultiSampleAborted__SHIFT 0x17 |
35548 | #define RLC_SPM_ACCUM_STATUS__RESERVED__SHIFT 0x18 |
35549 | #define RLC_SPM_ACCUM_STATUS__NumbSamplesCompleted_MASK 0x000000FFL |
35550 | #define RLC_SPM_ACCUM_STATUS__AccumDone_MASK 0x00000100L |
35551 | #define RLC_SPM_ACCUM_STATUS__SpmDone_MASK 0x00000200L |
35552 | #define RLC_SPM_ACCUM_STATUS__AccumOverflow_MASK 0x00000400L |
35553 | #define RLC_SPM_ACCUM_STATUS__AccumArmed_MASK 0x00000800L |
35554 | #define RLC_SPM_ACCUM_STATUS__SequenceInProgress_MASK 0x00001000L |
35555 | #define RLC_SPM_ACCUM_STATUS__FinalSequenceInProgress_MASK 0x00002000L |
35556 | #define RLC_SPM_ACCUM_STATUS__AllFifosEmpty_MASK 0x00004000L |
35557 | #define RLC_SPM_ACCUM_STATUS__FSMIsIdle_MASK 0x00008000L |
35558 | #define RLC_SPM_ACCUM_STATUS__SwaAccumDone_MASK 0x00010000L |
35559 | #define RLC_SPM_ACCUM_STATUS__SwaSpmDone_MASK 0x00020000L |
35560 | #define RLC_SPM_ACCUM_STATUS__SwaAccumOverflow_MASK 0x00040000L |
35561 | #define RLC_SPM_ACCUM_STATUS__SwaAccumArmed_MASK 0x00080000L |
35562 | #define RLC_SPM_ACCUM_STATUS__AllSegsDone_MASK 0x00100000L |
35563 | #define RLC_SPM_ACCUM_STATUS__RearmSwaPending_MASK 0x00200000L |
35564 | #define RLC_SPM_ACCUM_STATUS__RearmSppPending_MASK 0x00400000L |
35565 | #define RLC_SPM_ACCUM_STATUS__MultiSampleAborted_MASK 0x00800000L |
35566 | #define RLC_SPM_ACCUM_STATUS__RESERVED_MASK 0xFF000000L |
35567 | //RLC_SPM_ACCUM_CTRL |
35568 | #define RLC_SPM_ACCUM_CTRL__StrobeResetPerfMonitors__SHIFT 0x0 |
35569 | #define RLC_SPM_ACCUM_CTRL__StrobeStartAccumulation__SHIFT 0x1 |
35570 | #define RLC_SPM_ACCUM_CTRL__StrobeRearmAccum__SHIFT 0x2 |
35571 | #define RLC_SPM_ACCUM_CTRL__StrobeResetSpmBlock__SHIFT 0x3 |
35572 | #define RLC_SPM_ACCUM_CTRL__StrobeStartSpm__SHIFT 0x4 |
35573 | #define RLC_SPM_ACCUM_CTRL__StrobeRearmSwaAccum__SHIFT 0x8 |
35574 | #define RLC_SPM_ACCUM_CTRL__StrobeStartSwa__SHIFT 0x9 |
35575 | #define RLC_SPM_ACCUM_CTRL__StrobePerfmonSampleWires__SHIFT 0xa |
35576 | #define RLC_SPM_ACCUM_CTRL__RESERVED__SHIFT 0xb |
35577 | #define RLC_SPM_ACCUM_CTRL__StrobeResetPerfMonitors_MASK 0x00000001L |
35578 | #define RLC_SPM_ACCUM_CTRL__StrobeStartAccumulation_MASK 0x00000002L |
35579 | #define RLC_SPM_ACCUM_CTRL__StrobeRearmAccum_MASK 0x00000004L |
35580 | #define RLC_SPM_ACCUM_CTRL__StrobeResetSpmBlock_MASK 0x00000008L |
35581 | #define RLC_SPM_ACCUM_CTRL__StrobeStartSpm_MASK 0x000000F0L |
35582 | #define RLC_SPM_ACCUM_CTRL__StrobeRearmSwaAccum_MASK 0x00000100L |
35583 | #define RLC_SPM_ACCUM_CTRL__StrobeStartSwa_MASK 0x00000200L |
35584 | #define RLC_SPM_ACCUM_CTRL__StrobePerfmonSampleWires_MASK 0x00000400L |
35585 | #define RLC_SPM_ACCUM_CTRL__RESERVED_MASK 0xFFFFF800L |
35586 | //RLC_SPM_ACCUM_MODE |
35587 | #define RLC_SPM_ACCUM_MODE__EnableAccum__SHIFT 0x0 |
35588 | #define RLC_SPM_ACCUM_MODE__EnableSpmWithAccumMode__SHIFT 0x1 |
35589 | #define RLC_SPM_ACCUM_MODE__EnableSPPMode__SHIFT 0x2 |
35590 | #define RLC_SPM_ACCUM_MODE__AutoResetPerfmonDisable__SHIFT 0x3 |
35591 | #define RLC_SPM_ACCUM_MODE__AutoAccumEn__SHIFT 0x5 |
35592 | #define RLC_SPM_ACCUM_MODE__SwaAutoAccumEn__SHIFT 0x6 |
35593 | #define RLC_SPM_ACCUM_MODE__AutoSpmEn__SHIFT 0x7 |
35594 | #define RLC_SPM_ACCUM_MODE__SwaAutoSpmEn__SHIFT 0x8 |
35595 | #define RLC_SPM_ACCUM_MODE__Globals_LoadOverride__SHIFT 0x9 |
35596 | #define RLC_SPM_ACCUM_MODE__Globals_SwaLoadOverride__SHIFT 0xa |
35597 | #define RLC_SPM_ACCUM_MODE__SE0_LoadOverride__SHIFT 0xb |
35598 | #define RLC_SPM_ACCUM_MODE__SE0_SwaLoadOverride__SHIFT 0xc |
35599 | #define RLC_SPM_ACCUM_MODE__SE1_LoadOverride__SHIFT 0xd |
35600 | #define RLC_SPM_ACCUM_MODE__SE1_SwaLoadOverride__SHIFT 0xe |
35601 | #define RLC_SPM_ACCUM_MODE__SE2_LoadOverride__SHIFT 0xf |
35602 | #define RLC_SPM_ACCUM_MODE__SE2_SwaLoadOverride__SHIFT 0x10 |
35603 | #define RLC_SPM_ACCUM_MODE__EnableAccum_MASK 0x00000001L |
35604 | #define RLC_SPM_ACCUM_MODE__EnableSpmWithAccumMode_MASK 0x00000002L |
35605 | #define RLC_SPM_ACCUM_MODE__EnableSPPMode_MASK 0x00000004L |
35606 | #define RLC_SPM_ACCUM_MODE__AutoResetPerfmonDisable_MASK 0x00000008L |
35607 | #define RLC_SPM_ACCUM_MODE__AutoAccumEn_MASK 0x00000020L |
35608 | #define RLC_SPM_ACCUM_MODE__SwaAutoAccumEn_MASK 0x00000040L |
35609 | #define RLC_SPM_ACCUM_MODE__AutoSpmEn_MASK 0x00000080L |
35610 | #define RLC_SPM_ACCUM_MODE__SwaAutoSpmEn_MASK 0x00000100L |
35611 | #define RLC_SPM_ACCUM_MODE__Globals_LoadOverride_MASK 0x00000200L |
35612 | #define RLC_SPM_ACCUM_MODE__Globals_SwaLoadOverride_MASK 0x00000400L |
35613 | #define RLC_SPM_ACCUM_MODE__SE0_LoadOverride_MASK 0x00000800L |
35614 | #define RLC_SPM_ACCUM_MODE__SE0_SwaLoadOverride_MASK 0x00001000L |
35615 | #define RLC_SPM_ACCUM_MODE__SE1_LoadOverride_MASK 0x00002000L |
35616 | #define RLC_SPM_ACCUM_MODE__SE1_SwaLoadOverride_MASK 0x00004000L |
35617 | #define RLC_SPM_ACCUM_MODE__SE2_LoadOverride_MASK 0x00008000L |
35618 | #define RLC_SPM_ACCUM_MODE__SE2_SwaLoadOverride_MASK 0x00010000L |
35619 | //RLC_SPM_ACCUM_THRESHOLD |
35620 | #define RLC_SPM_ACCUM_THRESHOLD__Threshold__SHIFT 0x0 |
35621 | #define RLC_SPM_ACCUM_THRESHOLD__Threshold_MASK 0x0000FFFFL |
35622 | //RLC_SPM_ACCUM_SAMPLES_REQUESTED |
35623 | #define RLC_SPM_ACCUM_SAMPLES_REQUESTED__SamplesRequested__SHIFT 0x0 |
35624 | #define RLC_SPM_ACCUM_SAMPLES_REQUESTED__SamplesRequested_MASK 0x000000FFL |
35625 | //RLC_SPM_ACCUM_DATARAM_WRCOUNT |
35626 | #define RLC_SPM_ACCUM_DATARAM_WRCOUNT__DataRamWrCount__SHIFT 0x0 |
35627 | #define RLC_SPM_ACCUM_DATARAM_WRCOUNT__RESERVED__SHIFT 0x13 |
35628 | #define RLC_SPM_ACCUM_DATARAM_WRCOUNT__DataRamWrCount_MASK 0x0007FFFFL |
35629 | #define RLC_SPM_ACCUM_DATARAM_WRCOUNT__RESERVED_MASK 0xFFF80000L |
35630 | //RLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS |
35631 | #define RLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS__spp_addr_region__SHIFT 0x0 |
35632 | #define RLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS__swa_addr_region__SHIFT 0x8 |
35633 | #define RLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS__RESERVED__SHIFT 0x10 |
35634 | #define RLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS__spp_addr_region_MASK 0x000000FFL |
35635 | #define RLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS__swa_addr_region_MASK 0x0000FF00L |
35636 | #define RLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS__RESERVED_MASK 0xFFFF0000L |
35637 | //RLC_SPM_PAUSE |
35638 | #define RLC_SPM_PAUSE__PAUSE__SHIFT 0x0 |
35639 | #define RLC_SPM_PAUSE__PAUSED__SHIFT 0x1 |
35640 | #define RLC_SPM_PAUSE__PAUSE_MASK 0x00000001L |
35641 | #define RLC_SPM_PAUSE__PAUSED_MASK 0x00000002L |
35642 | //RLC_SPM_STATUS |
35643 | #define RLC_SPM_STATUS__CTL_BUSY__SHIFT 0x0 |
35644 | #define RLC_SPM_STATUS__RSPM_REG_BUSY__SHIFT 0x1 |
35645 | #define RLC_SPM_STATUS__SPM_RSPM_BUSY__SHIFT 0x2 |
35646 | #define RLC_SPM_STATUS__SPM_RSPM_IO_BUSY__SHIFT 0x3 |
35647 | #define RLC_SPM_STATUS__SE_RSPM_IO_BUSY__SHIFT 0x4 |
35648 | #define RLC_SPM_STATUS__ACCUM_BUSY__SHIFT 0xf |
35649 | #define RLC_SPM_STATUS__FSM_MASTER_STATE__SHIFT 0x10 |
35650 | #define RLC_SPM_STATUS__FSM_MEMORY_STATE__SHIFT 0x14 |
35651 | #define RLC_SPM_STATUS__CTL_REQ_STATE__SHIFT 0x18 |
35652 | #define RLC_SPM_STATUS__CTL_RET_STATE__SHIFT 0x1a |
35653 | #define RLC_SPM_STATUS__CTL_BUSY_MASK 0x00000001L |
35654 | #define RLC_SPM_STATUS__RSPM_REG_BUSY_MASK 0x00000002L |
35655 | #define RLC_SPM_STATUS__SPM_RSPM_BUSY_MASK 0x00000004L |
35656 | #define RLC_SPM_STATUS__SPM_RSPM_IO_BUSY_MASK 0x00000008L |
35657 | #define RLC_SPM_STATUS__SE_RSPM_IO_BUSY_MASK 0x00000FF0L |
35658 | #define RLC_SPM_STATUS__ACCUM_BUSY_MASK 0x00008000L |
35659 | #define RLC_SPM_STATUS__FSM_MASTER_STATE_MASK 0x000F0000L |
35660 | #define RLC_SPM_STATUS__FSM_MEMORY_STATE_MASK 0x00F00000L |
35661 | #define RLC_SPM_STATUS__CTL_REQ_STATE_MASK 0x03000000L |
35662 | #define RLC_SPM_STATUS__CTL_RET_STATE_MASK 0x04000000L |
35663 | //RLC_SPM_GFXCLOCK_LOWCOUNT |
35664 | #define RLC_SPM_GFXCLOCK_LOWCOUNT__GFXCLOCK_LOWCOUNT__SHIFT 0x0 |
35665 | #define RLC_SPM_GFXCLOCK_LOWCOUNT__GFXCLOCK_LOWCOUNT_MASK 0xFFFFFFFFL |
35666 | //RLC_SPM_GFXCLOCK_HIGHCOUNT |
35667 | #define RLC_SPM_GFXCLOCK_HIGHCOUNT__GFXCLOCK_HIGHCOUNT__SHIFT 0x0 |
35668 | #define RLC_SPM_GFXCLOCK_HIGHCOUNT__GFXCLOCK_HIGHCOUNT_MASK 0xFFFFFFFFL |
35669 | //RLC_SPM_MODE |
35670 | #define RLC_SPM_MODE__MODE__SHIFT 0x0 |
35671 | #define RLC_SPM_MODE__MODE_MASK 0x00000001L |
35672 | //RLC_SPM_RSPM_REQ_DATA_LO |
35673 | #define RLC_SPM_RSPM_REQ_DATA_LO__DATA__SHIFT 0x0 |
35674 | #define RLC_SPM_RSPM_REQ_DATA_LO__DATA_MASK 0xFFFFFFFFL |
35675 | //RLC_SPM_RSPM_REQ_DATA_HI |
35676 | #define RLC_SPM_RSPM_REQ_DATA_HI__DATA__SHIFT 0x0 |
35677 | #define RLC_SPM_RSPM_REQ_DATA_HI__DATA_MASK 0x00000FFFL |
35678 | //RLC_SPM_RSPM_REQ_OP |
35679 | #define RLC_SPM_RSPM_REQ_OP__OP__SHIFT 0x0 |
35680 | #define RLC_SPM_RSPM_REQ_OP__OP_MASK 0x0000000FL |
35681 | //RLC_SPM_RSPM_RET_DATA |
35682 | #define RLC_SPM_RSPM_RET_DATA__DATA__SHIFT 0x0 |
35683 | #define RLC_SPM_RSPM_RET_DATA__DATA_MASK 0xFFFFFFFFL |
35684 | //RLC_SPM_RSPM_RET_OP |
35685 | #define RLC_SPM_RSPM_RET_OP__OP__SHIFT 0x0 |
35686 | #define RLC_SPM_RSPM_RET_OP__VALID__SHIFT 0x8 |
35687 | #define RLC_SPM_RSPM_RET_OP__OP_MASK 0x0000000FL |
35688 | #define RLC_SPM_RSPM_RET_OP__VALID_MASK 0x00000100L |
35689 | //RLC_SPM_SE_RSPM_REQ_DATA_LO |
35690 | #define RLC_SPM_SE_RSPM_REQ_DATA_LO__DATA__SHIFT 0x0 |
35691 | #define RLC_SPM_SE_RSPM_REQ_DATA_LO__DATA_MASK 0xFFFFFFFFL |
35692 | //RLC_SPM_SE_RSPM_REQ_DATA_HI |
35693 | #define RLC_SPM_SE_RSPM_REQ_DATA_HI__DATA__SHIFT 0x0 |
35694 | #define RLC_SPM_SE_RSPM_REQ_DATA_HI__DATA_MASK 0x00000FFFL |
35695 | //RLC_SPM_SE_RSPM_REQ_OP |
35696 | #define RLC_SPM_SE_RSPM_REQ_OP__OP__SHIFT 0x0 |
35697 | #define RLC_SPM_SE_RSPM_REQ_OP__OP_MASK 0x0000000FL |
35698 | //RLC_SPM_SE_RSPM_RET_DATA |
35699 | #define RLC_SPM_SE_RSPM_RET_DATA__DATA__SHIFT 0x0 |
35700 | #define RLC_SPM_SE_RSPM_RET_DATA__DATA_MASK 0xFFFFFFFFL |
35701 | //RLC_SPM_SE_RSPM_RET_OP |
35702 | #define RLC_SPM_SE_RSPM_RET_OP__OP__SHIFT 0x0 |
35703 | #define RLC_SPM_SE_RSPM_RET_OP__VALID__SHIFT 0x8 |
35704 | #define RLC_SPM_SE_RSPM_RET_OP__OP_MASK 0x0000000FL |
35705 | #define RLC_SPM_SE_RSPM_RET_OP__VALID_MASK 0x00000100L |
35706 | //RLC_SPM_RSPM_CMD |
35707 | #define RLC_SPM_RSPM_CMD__CMD__SHIFT 0x0 |
35708 | #define RLC_SPM_RSPM_CMD__CMD_MASK 0x0000000FL |
35709 | //RLC_SPM_RSPM_CMD_ACK |
35710 | #define RLC_SPM_RSPM_CMD_ACK__SE0_ACK__SHIFT 0x0 |
35711 | #define RLC_SPM_RSPM_CMD_ACK__SE1_ACK__SHIFT 0x1 |
35712 | #define RLC_SPM_RSPM_CMD_ACK__SE2_ACK__SHIFT 0x2 |
35713 | #define RLC_SPM_RSPM_CMD_ACK__SE3_ACK__SHIFT 0x3 |
35714 | #define RLC_SPM_RSPM_CMD_ACK__SE4_ACK__SHIFT 0x4 |
35715 | #define RLC_SPM_RSPM_CMD_ACK__SE5_ACK__SHIFT 0x5 |
35716 | #define RLC_SPM_RSPM_CMD_ACK__SE6_ACK__SHIFT 0x6 |
35717 | #define RLC_SPM_RSPM_CMD_ACK__SE7_ACK__SHIFT 0x7 |
35718 | #define RLC_SPM_RSPM_CMD_ACK__SPM_ACK__SHIFT 0x8 |
35719 | #define RLC_SPM_RSPM_CMD_ACK__SE0_ACK_MASK 0x00000001L |
35720 | #define RLC_SPM_RSPM_CMD_ACK__SE1_ACK_MASK 0x00000002L |
35721 | #define RLC_SPM_RSPM_CMD_ACK__SE2_ACK_MASK 0x00000004L |
35722 | #define RLC_SPM_RSPM_CMD_ACK__SE3_ACK_MASK 0x00000008L |
35723 | #define RLC_SPM_RSPM_CMD_ACK__SE4_ACK_MASK 0x00000010L |
35724 | #define RLC_SPM_RSPM_CMD_ACK__SE5_ACK_MASK 0x00000020L |
35725 | #define RLC_SPM_RSPM_CMD_ACK__SE6_ACK_MASK 0x00000040L |
35726 | #define RLC_SPM_RSPM_CMD_ACK__SE7_ACK_MASK 0x00000080L |
35727 | #define RLC_SPM_RSPM_CMD_ACK__SPM_ACK_MASK 0x00000100L |
35728 | //RLC_SPM_SPARE |
35729 | #define RLC_SPM_SPARE__SPARE__SHIFT 0x0 |
35730 | #define RLC_SPM_SPARE__SPARE_MASK 0xFFFFFFFFL |
35731 | //RLC_PERFMON_CNTL |
35732 | #define RLC_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 |
35733 | #define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa |
35734 | #define RLC_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000007L |
35735 | #define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x00000400L |
35736 | //RLC_PERFCOUNTER0_SELECT |
35737 | #define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 |
35738 | #define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x000000FFL |
35739 | //RLC_PERFCOUNTER1_SELECT |
35740 | #define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 |
35741 | #define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x000000FFL |
35742 | //RLC_GPU_IOV_PERF_CNT_CNTL |
35743 | #define RLC_GPU_IOV_PERF_CNT_CNTL__ENABLE__SHIFT 0x0 |
35744 | #define RLC_GPU_IOV_PERF_CNT_CNTL__MODE_SELECT__SHIFT 0x1 |
35745 | #define RLC_GPU_IOV_PERF_CNT_CNTL__RESET__SHIFT 0x2 |
35746 | #define RLC_GPU_IOV_PERF_CNT_CNTL__RESERVED__SHIFT 0x3 |
35747 | #define RLC_GPU_IOV_PERF_CNT_CNTL__ENABLE_MASK 0x00000001L |
35748 | #define RLC_GPU_IOV_PERF_CNT_CNTL__MODE_SELECT_MASK 0x00000002L |
35749 | #define RLC_GPU_IOV_PERF_CNT_CNTL__RESET_MASK 0x00000004L |
35750 | #define RLC_GPU_IOV_PERF_CNT_CNTL__RESERVED_MASK 0xFFFFFFF8L |
35751 | //RLC_GPU_IOV_PERF_CNT_WR_ADDR |
35752 | #define RLC_GPU_IOV_PERF_CNT_WR_ADDR__VFID__SHIFT 0x0 |
35753 | #define RLC_GPU_IOV_PERF_CNT_WR_ADDR__CNT_ID__SHIFT 0x4 |
35754 | #define RLC_GPU_IOV_PERF_CNT_WR_ADDR__RESERVED__SHIFT 0x6 |
35755 | #define RLC_GPU_IOV_PERF_CNT_WR_ADDR__VFID_MASK 0x0000000FL |
35756 | #define RLC_GPU_IOV_PERF_CNT_WR_ADDR__CNT_ID_MASK 0x00000030L |
35757 | #define RLC_GPU_IOV_PERF_CNT_WR_ADDR__RESERVED_MASK 0xFFFFFFC0L |
35758 | //RLC_GPU_IOV_PERF_CNT_WR_DATA |
35759 | #define RLC_GPU_IOV_PERF_CNT_WR_DATA__DATA__SHIFT 0x0 |
35760 | #define RLC_GPU_IOV_PERF_CNT_WR_DATA__DATA_MASK 0xFFFFFFFFL |
35761 | //RLC_GPU_IOV_PERF_CNT_RD_ADDR |
35762 | #define RLC_GPU_IOV_PERF_CNT_RD_ADDR__VFID__SHIFT 0x0 |
35763 | #define RLC_GPU_IOV_PERF_CNT_RD_ADDR__CNT_ID__SHIFT 0x4 |
35764 | #define RLC_GPU_IOV_PERF_CNT_RD_ADDR__RESERVED__SHIFT 0x6 |
35765 | #define RLC_GPU_IOV_PERF_CNT_RD_ADDR__VFID_MASK 0x0000000FL |
35766 | #define RLC_GPU_IOV_PERF_CNT_RD_ADDR__CNT_ID_MASK 0x00000030L |
35767 | #define RLC_GPU_IOV_PERF_CNT_RD_ADDR__RESERVED_MASK 0xFFFFFFC0L |
35768 | //RLC_GPU_IOV_PERF_CNT_RD_DATA |
35769 | #define RLC_GPU_IOV_PERF_CNT_RD_DATA__DATA__SHIFT 0x0 |
35770 | #define RLC_GPU_IOV_PERF_CNT_RD_DATA__DATA_MASK 0xFFFFFFFFL |
35771 | //RMI_PERFCOUNTER0_SELECT |
35772 | #define RMI_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
35773 | #define RMI_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
35774 | #define RMI_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 |
35775 | #define RMI_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 |
35776 | #define RMI_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c |
35777 | #define RMI_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL |
35778 | #define RMI_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L |
35779 | #define RMI_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L |
35780 | #define RMI_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L |
35781 | #define RMI_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L |
35782 | //RMI_PERFCOUNTER0_SELECT1 |
35783 | #define RMI_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
35784 | #define RMI_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
35785 | #define RMI_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 |
35786 | #define RMI_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c |
35787 | #define RMI_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL |
35788 | #define RMI_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
35789 | #define RMI_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L |
35790 | #define RMI_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L |
35791 | //RMI_PERFCOUNTER1_SELECT |
35792 | #define RMI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
35793 | #define RMI_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c |
35794 | #define RMI_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL |
35795 | #define RMI_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L |
35796 | //RMI_PERFCOUNTER2_SELECT |
35797 | #define RMI_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 |
35798 | #define RMI_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa |
35799 | #define RMI_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 |
35800 | #define RMI_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 |
35801 | #define RMI_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c |
35802 | #define RMI_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL |
35803 | #define RMI_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L |
35804 | #define RMI_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L |
35805 | #define RMI_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L |
35806 | #define RMI_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L |
35807 | //RMI_PERFCOUNTER2_SELECT1 |
35808 | #define RMI_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 |
35809 | #define RMI_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa |
35810 | #define RMI_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18 |
35811 | #define RMI_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c |
35812 | #define RMI_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL |
35813 | #define RMI_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
35814 | #define RMI_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L |
35815 | #define RMI_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L |
35816 | //RMI_PERFCOUNTER3_SELECT |
35817 | #define RMI_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 |
35818 | #define RMI_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c |
35819 | #define RMI_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL |
35820 | #define RMI_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L |
35821 | //RMI_PERF_COUNTER_CNTL |
35822 | #define RMI_PERF_COUNTER_CNTL__TRANS_BASED_PERF_EN_SEL__SHIFT 0x0 |
35823 | #define RMI_PERF_COUNTER_CNTL__EVENT_BASED_PERF_EN_SEL__SHIFT 0x2 |
35824 | #define RMI_PERF_COUNTER_CNTL__TC_PERF_EN_SEL__SHIFT 0x4 |
35825 | #define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK0__SHIFT 0x6 |
35826 | #define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK1__SHIFT 0x8 |
35827 | #define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_CID__SHIFT 0xa |
35828 | #define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_VMID__SHIFT 0xe |
35829 | #define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_BURST_LENGTH_THRESHOLD__SHIFT 0x13 |
35830 | #define RMI_PERF_COUNTER_CNTL__PERF_SOFT_RESET__SHIFT 0x19 |
35831 | #define RMI_PERF_COUNTER_CNTL__PERF_CNTR_SPM_SEL__SHIFT 0x1a |
35832 | #define RMI_PERF_COUNTER_CNTL__TRANS_BASED_PERF_EN_SEL_MASK 0x00000003L |
35833 | #define RMI_PERF_COUNTER_CNTL__EVENT_BASED_PERF_EN_SEL_MASK 0x0000000CL |
35834 | #define RMI_PERF_COUNTER_CNTL__TC_PERF_EN_SEL_MASK 0x00000030L |
35835 | #define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK0_MASK 0x000000C0L |
35836 | #define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK1_MASK 0x00000300L |
35837 | #define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_CID_MASK 0x00003C00L |
35838 | #define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_VMID_MASK 0x0007C000L |
35839 | #define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_BURST_LENGTH_THRESHOLD_MASK 0x01F80000L |
35840 | #define RMI_PERF_COUNTER_CNTL__PERF_SOFT_RESET_MASK 0x02000000L |
35841 | #define RMI_PERF_COUNTER_CNTL__PERF_CNTR_SPM_SEL_MASK 0x04000000L |
35842 | //GCR_PERFCOUNTER0_SELECT |
35843 | #define GCR_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
35844 | #define GCR_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
35845 | #define GCR_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 |
35846 | #define GCR_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 |
35847 | #define GCR_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c |
35848 | #define GCR_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL |
35849 | #define GCR_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L |
35850 | #define GCR_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L |
35851 | #define GCR_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L |
35852 | #define GCR_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L |
35853 | //GCR_PERFCOUNTER0_SELECT1 |
35854 | #define GCR_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
35855 | #define GCR_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
35856 | #define GCR_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 |
35857 | #define GCR_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c |
35858 | #define GCR_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL |
35859 | #define GCR_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
35860 | #define GCR_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L |
35861 | #define GCR_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L |
35862 | //GCR_PERFCOUNTER1_SELECT |
35863 | #define GCR_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
35864 | #define GCR_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 |
35865 | #define GCR_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c |
35866 | #define GCR_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL |
35867 | #define GCR_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L |
35868 | #define GCR_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L |
35869 | //PA_PH_PERFCOUNTER0_SELECT |
35870 | #define PA_PH_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
35871 | #define PA_PH_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
35872 | #define PA_PH_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 |
35873 | #define PA_PH_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 |
35874 | #define PA_PH_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c |
35875 | #define PA_PH_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL |
35876 | #define PA_PH_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L |
35877 | #define PA_PH_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L |
35878 | #define PA_PH_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L |
35879 | #define PA_PH_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L |
35880 | //PA_PH_PERFCOUNTER0_SELECT1 |
35881 | #define PA_PH_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
35882 | #define PA_PH_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
35883 | #define PA_PH_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 |
35884 | #define PA_PH_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c |
35885 | #define PA_PH_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL |
35886 | #define PA_PH_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
35887 | #define PA_PH_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L |
35888 | #define PA_PH_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L |
35889 | //PA_PH_PERFCOUNTER1_SELECT |
35890 | #define PA_PH_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
35891 | #define PA_PH_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa |
35892 | #define PA_PH_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 |
35893 | #define PA_PH_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 |
35894 | #define PA_PH_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c |
35895 | #define PA_PH_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL |
35896 | #define PA_PH_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L |
35897 | #define PA_PH_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L |
35898 | #define PA_PH_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L |
35899 | #define PA_PH_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L |
35900 | //PA_PH_PERFCOUNTER2_SELECT |
35901 | #define PA_PH_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 |
35902 | #define PA_PH_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa |
35903 | #define PA_PH_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 |
35904 | #define PA_PH_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 |
35905 | #define PA_PH_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c |
35906 | #define PA_PH_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL |
35907 | #define PA_PH_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L |
35908 | #define PA_PH_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L |
35909 | #define PA_PH_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L |
35910 | #define PA_PH_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L |
35911 | //PA_PH_PERFCOUNTER3_SELECT |
35912 | #define PA_PH_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 |
35913 | #define PA_PH_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa |
35914 | #define PA_PH_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 |
35915 | #define PA_PH_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18 |
35916 | #define PA_PH_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c |
35917 | #define PA_PH_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL |
35918 | #define PA_PH_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L |
35919 | #define PA_PH_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L |
35920 | #define PA_PH_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L |
35921 | #define PA_PH_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L |
35922 | //PA_PH_PERFCOUNTER4_SELECT |
35923 | #define PA_PH_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0 |
35924 | #define PA_PH_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x000003FFL |
35925 | //PA_PH_PERFCOUNTER5_SELECT |
35926 | #define PA_PH_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0 |
35927 | #define PA_PH_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x000003FFL |
35928 | //PA_PH_PERFCOUNTER6_SELECT |
35929 | #define PA_PH_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x0 |
35930 | #define PA_PH_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0x000003FFL |
35931 | //PA_PH_PERFCOUNTER7_SELECT |
35932 | #define PA_PH_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x0 |
35933 | #define PA_PH_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0x000003FFL |
35934 | //PA_PH_PERFCOUNTER1_SELECT1 |
35935 | #define PA_PH_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 |
35936 | #define PA_PH_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa |
35937 | #define PA_PH_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 |
35938 | #define PA_PH_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c |
35939 | #define PA_PH_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL |
35940 | #define PA_PH_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
35941 | #define PA_PH_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L |
35942 | #define PA_PH_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L |
35943 | //PA_PH_PERFCOUNTER2_SELECT1 |
35944 | #define PA_PH_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 |
35945 | #define PA_PH_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa |
35946 | #define PA_PH_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18 |
35947 | #define PA_PH_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c |
35948 | #define PA_PH_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL |
35949 | #define PA_PH_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
35950 | #define PA_PH_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L |
35951 | #define PA_PH_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L |
35952 | //PA_PH_PERFCOUNTER3_SELECT1 |
35953 | #define PA_PH_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0 |
35954 | #define PA_PH_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa |
35955 | #define PA_PH_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT 0x18 |
35956 | #define PA_PH_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT 0x1c |
35957 | #define PA_PH_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003FFL |
35958 | #define PA_PH_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
35959 | #define PA_PH_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK 0x0F000000L |
35960 | #define PA_PH_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK 0xF0000000L |
35961 | //UTCL1_PERFCOUNTER0_SELECT |
35962 | #define UTCL1_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
35963 | #define UTCL1_PERFCOUNTER0_SELECT__COUNTER_MODE__SHIFT 0x1c |
35964 | #define UTCL1_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL |
35965 | #define UTCL1_PERFCOUNTER0_SELECT__COUNTER_MODE_MASK 0xF0000000L |
35966 | //UTCL1_PERFCOUNTER1_SELECT |
35967 | #define UTCL1_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
35968 | #define UTCL1_PERFCOUNTER1_SELECT__COUNTER_MODE__SHIFT 0x1c |
35969 | #define UTCL1_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL |
35970 | #define UTCL1_PERFCOUNTER1_SELECT__COUNTER_MODE_MASK 0xF0000000L |
35971 | //UTCL1_PERFCOUNTER2_SELECT |
35972 | #define UTCL1_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 |
35973 | #define UTCL1_PERFCOUNTER2_SELECT__COUNTER_MODE__SHIFT 0x1c |
35974 | #define UTCL1_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL |
35975 | #define UTCL1_PERFCOUNTER2_SELECT__COUNTER_MODE_MASK 0xF0000000L |
35976 | //UTCL1_PERFCOUNTER3_SELECT |
35977 | #define UTCL1_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 |
35978 | #define UTCL1_PERFCOUNTER3_SELECT__COUNTER_MODE__SHIFT 0x1c |
35979 | #define UTCL1_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL |
35980 | #define UTCL1_PERFCOUNTER3_SELECT__COUNTER_MODE_MASK 0xF0000000L |
35981 | //GL1A_PERFCOUNTER0_SELECT |
35982 | #define GL1A_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
35983 | #define GL1A_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
35984 | #define GL1A_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 |
35985 | #define GL1A_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 |
35986 | #define GL1A_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c |
35987 | #define GL1A_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL |
35988 | #define GL1A_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L |
35989 | #define GL1A_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L |
35990 | #define GL1A_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L |
35991 | #define GL1A_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L |
35992 | //GL1A_PERFCOUNTER0_SELECT1 |
35993 | #define GL1A_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
35994 | #define GL1A_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
35995 | #define GL1A_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18 |
35996 | #define GL1A_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c |
35997 | #define GL1A_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL |
35998 | #define GL1A_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
35999 | #define GL1A_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0x0F000000L |
36000 | #define GL1A_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xF0000000L |
36001 | //GL1A_PERFCOUNTER1_SELECT |
36002 | #define GL1A_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
36003 | #define GL1A_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 |
36004 | #define GL1A_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c |
36005 | #define GL1A_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL |
36006 | #define GL1A_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L |
36007 | #define GL1A_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L |
36008 | //GL1A_PERFCOUNTER2_SELECT |
36009 | #define GL1A_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 |
36010 | #define GL1A_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 |
36011 | #define GL1A_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c |
36012 | #define GL1A_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL |
36013 | #define GL1A_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L |
36014 | #define GL1A_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L |
36015 | //GL1A_PERFCOUNTER3_SELECT |
36016 | #define GL1A_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 |
36017 | #define GL1A_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 |
36018 | #define GL1A_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c |
36019 | #define GL1A_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL |
36020 | #define GL1A_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L |
36021 | #define GL1A_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L |
36022 | //GL1H_PERFCOUNTER0_SELECT |
36023 | #define GL1H_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
36024 | #define GL1H_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
36025 | #define GL1H_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 |
36026 | #define GL1H_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 |
36027 | #define GL1H_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c |
36028 | #define GL1H_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL |
36029 | #define GL1H_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L |
36030 | #define GL1H_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L |
36031 | #define GL1H_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L |
36032 | #define GL1H_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L |
36033 | //GL1H_PERFCOUNTER0_SELECT1 |
36034 | #define GL1H_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
36035 | #define GL1H_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
36036 | #define GL1H_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18 |
36037 | #define GL1H_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c |
36038 | #define GL1H_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL |
36039 | #define GL1H_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
36040 | #define GL1H_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0x0F000000L |
36041 | #define GL1H_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xF0000000L |
36042 | //GL1H_PERFCOUNTER1_SELECT |
36043 | #define GL1H_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
36044 | #define GL1H_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 |
36045 | #define GL1H_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c |
36046 | #define GL1H_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL |
36047 | #define GL1H_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L |
36048 | #define GL1H_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L |
36049 | //GL1H_PERFCOUNTER2_SELECT |
36050 | #define GL1H_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 |
36051 | #define GL1H_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 |
36052 | #define GL1H_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c |
36053 | #define GL1H_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL |
36054 | #define GL1H_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L |
36055 | #define GL1H_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L |
36056 | //GL1H_PERFCOUNTER3_SELECT |
36057 | #define GL1H_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 |
36058 | #define GL1H_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 |
36059 | #define GL1H_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c |
36060 | #define GL1H_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL |
36061 | #define GL1H_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L |
36062 | #define GL1H_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L |
36063 | //CHA_PERFCOUNTER0_SELECT |
36064 | #define CHA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 |
36065 | #define CHA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa |
36066 | #define CHA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 |
36067 | #define CHA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 |
36068 | #define CHA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c |
36069 | #define CHA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL |
36070 | #define CHA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L |
36071 | #define CHA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L |
36072 | #define CHA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L |
36073 | #define CHA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L |
36074 | //CHA_PERFCOUNTER0_SELECT1 |
36075 | #define CHA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 |
36076 | #define CHA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa |
36077 | #define CHA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18 |
36078 | #define CHA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c |
36079 | #define CHA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL |
36080 | #define CHA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
36081 | #define CHA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0x0F000000L |
36082 | #define CHA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xF0000000L |
36083 | //CHA_PERFCOUNTER1_SELECT |
36084 | #define CHA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 |
36085 | #define CHA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 |
36086 | #define CHA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c |
36087 | #define CHA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL |
36088 | #define CHA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L |
36089 | #define CHA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L |
36090 | //CHA_PERFCOUNTER2_SELECT |
36091 | #define CHA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 |
36092 | #define CHA_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 |
36093 | #define CHA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c |
36094 | #define CHA_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL |
36095 | #define CHA_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L |
36096 | #define CHA_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L |
36097 | //CHA_PERFCOUNTER3_SELECT |
36098 | #define CHA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 |
36099 | #define CHA_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 |
36100 | #define CHA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c |
36101 | #define CHA_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL |
36102 | #define CHA_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L |
36103 | #define CHA_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L |
36104 | //GUS_PERFCOUNTER2_SELECT |
36105 | #define GUS_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 |
36106 | #define GUS_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa |
36107 | #define GUS_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 |
36108 | #define GUS_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 |
36109 | #define GUS_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c |
36110 | #define GUS_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL |
36111 | #define GUS_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L |
36112 | #define GUS_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L |
36113 | #define GUS_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L |
36114 | #define GUS_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L |
36115 | //GUS_PERFCOUNTER2_SELECT1 |
36116 | #define GUS_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 |
36117 | #define GUS_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa |
36118 | #define GUS_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18 |
36119 | #define GUS_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c |
36120 | #define GUS_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL |
36121 | #define GUS_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L |
36122 | #define GUS_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L |
36123 | #define GUS_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L |
36124 | //GUS_PERFCOUNTER2_MODE |
36125 | #define GUS_PERFCOUNTER2_MODE__COMPARE_MODE0__SHIFT 0x0 |
36126 | #define GUS_PERFCOUNTER2_MODE__COMPARE_MODE1__SHIFT 0x2 |
36127 | #define GUS_PERFCOUNTER2_MODE__COMPARE_MODE2__SHIFT 0x4 |
36128 | #define GUS_PERFCOUNTER2_MODE__COMPARE_MODE3__SHIFT 0x6 |
36129 | #define GUS_PERFCOUNTER2_MODE__COMPARE_VALUE0__SHIFT 0x8 |
36130 | #define GUS_PERFCOUNTER2_MODE__COMPARE_VALUE1__SHIFT 0xc |
36131 | #define GUS_PERFCOUNTER2_MODE__COMPARE_VALUE2__SHIFT 0x10 |
36132 | #define GUS_PERFCOUNTER2_MODE__COMPARE_VALUE3__SHIFT 0x14 |
36133 | #define GUS_PERFCOUNTER2_MODE__COMPARE_MODE0_MASK 0x00000003L |
36134 | #define GUS_PERFCOUNTER2_MODE__COMPARE_MODE1_MASK 0x0000000CL |
36135 | #define GUS_PERFCOUNTER2_MODE__COMPARE_MODE2_MASK 0x00000030L |
36136 | #define GUS_PERFCOUNTER2_MODE__COMPARE_MODE3_MASK 0x000000C0L |
36137 | #define GUS_PERFCOUNTER2_MODE__COMPARE_VALUE0_MASK 0x00000F00L |
36138 | #define GUS_PERFCOUNTER2_MODE__COMPARE_VALUE1_MASK 0x0000F000L |
36139 | #define GUS_PERFCOUNTER2_MODE__COMPARE_VALUE2_MASK 0x000F0000L |
36140 | #define GUS_PERFCOUNTER2_MODE__COMPARE_VALUE3_MASK 0x00F00000L |
36141 | //GUS_PERFCOUNTER0_CFG |
36142 | #define GUS_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 |
36143 | #define GUS_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 |
36144 | #define GUS_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 |
36145 | #define GUS_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c |
36146 | #define GUS_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d |
36147 | #define GUS_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL |
36148 | #define GUS_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L |
36149 | #define GUS_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L |
36150 | #define GUS_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L |
36151 | #define GUS_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L |
36152 | //GUS_PERFCOUNTER1_CFG |
36153 | #define GUS_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 |
36154 | #define GUS_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 |
36155 | #define GUS_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 |
36156 | #define GUS_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c |
36157 | #define GUS_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d |
36158 | #define GUS_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL |
36159 | #define GUS_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L |
36160 | #define GUS_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L |
36161 | #define GUS_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L |
36162 | #define GUS_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L |
36163 | //GUS_PERFCOUNTER_RSLT_CNTL |
36164 | #define GUS_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 |
36165 | #define GUS_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 |
36166 | #define GUS_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 |
36167 | #define GUS_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 |
36168 | #define GUS_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 |
36169 | #define GUS_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a |
36170 | #define GUS_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL |
36171 | #define GUS_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L |
36172 | #define GUS_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L |
36173 | #define GUS_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L |
36174 | #define GUS_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L |
36175 | #define GUS_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L |
36176 | |
36177 | |
36178 | // addressBlock: gc_gdfll_gdfll_dec |
36179 | //GDFLL_EDC_HYSTERESIS_CNTL |
36180 | #define GDFLL_EDC_HYSTERESIS_CNTL__MAX_HYSTERESIS__SHIFT 0x0 |
36181 | #define GDFLL_EDC_HYSTERESIS_CNTL__MAX_HYSTERESIS_MASK 0x000000FFL |
36182 | //GDFLL_EDC_HYSTERESIS_STAT |
36183 | #define GDFLL_EDC_HYSTERESIS_STAT__HYSTERESIS_CNT__SHIFT 0x0 |
36184 | #define GDFLL_EDC_HYSTERESIS_STAT__EDC__SHIFT 0x8 |
36185 | #define GDFLL_EDC_HYSTERESIS_STAT__HYSTERESIS_CNT_MASK 0x000000FFL |
36186 | #define GDFLL_EDC_HYSTERESIS_STAT__EDC_MASK 0x00000100L |
36187 | |
36188 | |
36189 | // addressBlock: gc_gdfll_se_gdfll_dec |
36190 | //GDFLL_SE_EDC_HYSTERESIS_CNTL |
36191 | #define GDFLL_SE_EDC_HYSTERESIS_CNTL__MAX_HYSTERESIS__SHIFT 0x0 |
36192 | #define GDFLL_SE_EDC_HYSTERESIS_CNTL__MAX_HYSTERESIS_MASK 0x000000FFL |
36193 | //GDFLL_SE_EDC_HYSTERESIS_STAT |
36194 | #define GDFLL_SE_EDC_HYSTERESIS_STAT__HYSTERESIS_CNT__SHIFT 0x0 |
36195 | #define GDFLL_SE_EDC_HYSTERESIS_STAT__EDC__SHIFT 0x8 |
36196 | #define GDFLL_SE_EDC_HYSTERESIS_STAT__HYSTERESIS_CNT_MASK 0x000000FFL |
36197 | #define GDFLL_SE_EDC_HYSTERESIS_STAT__EDC_MASK 0x00000100L |
36198 | |
36199 | |
36200 | // addressBlock: gc_grtavfs_grtavfs_dec |
36201 | //GRTAVFS_RTAVFS_REG_ADDR |
36202 | #define GRTAVFS_RTAVFS_REG_ADDR__RTAVFSADDR__SHIFT 0x0 |
36203 | #define GRTAVFS_RTAVFS_REG_ADDR__RTAVFSADDR_MASK 0x000003FFL |
36204 | //GRTAVFS_RTAVFS_WR_DATA |
36205 | #define GRTAVFS_RTAVFS_WR_DATA__RTAVFSDATA__SHIFT 0x0 |
36206 | #define GRTAVFS_RTAVFS_WR_DATA__RTAVFSDATA_MASK 0xFFFFFFFFL |
36207 | //GRTAVFS_GENERAL_0 |
36208 | #define GRTAVFS_GENERAL_0__DATA__SHIFT 0x0 |
36209 | #define GRTAVFS_GENERAL_0__DATA_MASK 0xFFFFFFFFL |
36210 | //GRTAVFS_RTAVFS_RD_DATA |
36211 | #define GRTAVFS_RTAVFS_RD_DATA__RTAVFSDATA__SHIFT 0x0 |
36212 | #define GRTAVFS_RTAVFS_RD_DATA__RTAVFSDATA_MASK 0xFFFFFFFFL |
36213 | //GRTAVFS_RTAVFS_REG_CTRL |
36214 | #define GRTAVFS_RTAVFS_REG_CTRL__SET_WR_EN__SHIFT 0x0 |
36215 | #define GRTAVFS_RTAVFS_REG_CTRL__SET_RD_EN__SHIFT 0x1 |
36216 | #define GRTAVFS_RTAVFS_REG_CTRL__SET_WR_EN_MASK 0x00000001L |
36217 | #define GRTAVFS_RTAVFS_REG_CTRL__SET_RD_EN_MASK 0x00000002L |
36218 | //GRTAVFS_RTAVFS_REG_STATUS |
36219 | #define GRTAVFS_RTAVFS_REG_STATUS__RTAVFS_WR_ACK__SHIFT 0x0 |
36220 | #define GRTAVFS_RTAVFS_REG_STATUS__RTAVFS_RD_DATA_VALID__SHIFT 0x1 |
36221 | #define GRTAVFS_RTAVFS_REG_STATUS__RTAVFS_WR_ACK_MASK 0x00000001L |
36222 | #define GRTAVFS_RTAVFS_REG_STATUS__RTAVFS_RD_DATA_VALID_MASK 0x00000002L |
36223 | //GRTAVFS_TARG_FREQ |
36224 | #define GRTAVFS_TARG_FREQ__TARGET_FREQUENCY__SHIFT 0x0 |
36225 | #define GRTAVFS_TARG_FREQ__REQUEST__SHIFT 0x10 |
36226 | #define GRTAVFS_TARG_FREQ__RESERVED__SHIFT 0x11 |
36227 | #define GRTAVFS_TARG_FREQ__TARGET_FREQUENCY_MASK 0x0000FFFFL |
36228 | #define GRTAVFS_TARG_FREQ__REQUEST_MASK 0x00010000L |
36229 | #define GRTAVFS_TARG_FREQ__RESERVED_MASK 0xFFFE0000L |
36230 | //GRTAVFS_TARG_VOLT |
36231 | #define GRTAVFS_TARG_VOLT__TARGET_VOLTAGE__SHIFT 0x0 |
36232 | #define GRTAVFS_TARG_VOLT__VALID__SHIFT 0xa |
36233 | #define GRTAVFS_TARG_VOLT__RESERVED__SHIFT 0xb |
36234 | #define GRTAVFS_TARG_VOLT__TARGET_VOLTAGE_MASK 0x000003FFL |
36235 | #define GRTAVFS_TARG_VOLT__VALID_MASK 0x00000400L |
36236 | #define GRTAVFS_TARG_VOLT__RESERVED_MASK 0xFFFFF800L |
36237 | //GRTAVFS_SOFT_RESET |
36238 | #define GRTAVFS_SOFT_RESET__RESETN_OVERRIDE__SHIFT 0x0 |
36239 | #define GRTAVFS_SOFT_RESET__RESERVED__SHIFT 0x1 |
36240 | #define GRTAVFS_SOFT_RESET__RESETN_OVERRIDE_MASK 0x00000001L |
36241 | #define GRTAVFS_SOFT_RESET__RESERVED_MASK 0xFFFFFFFEL |
36242 | //GRTAVFS_PSM_CNTL |
36243 | #define GRTAVFS_PSM_CNTL__PSM_COUNT__SHIFT 0x0 |
36244 | #define GRTAVFS_PSM_CNTL__PSM_SAMPLE_EN__SHIFT 0xe |
36245 | #define GRTAVFS_PSM_CNTL__RESERVED__SHIFT 0xf |
36246 | #define GRTAVFS_PSM_CNTL__PSM_COUNT_MASK 0x00003FFFL |
36247 | #define GRTAVFS_PSM_CNTL__PSM_SAMPLE_EN_MASK 0x00004000L |
36248 | #define GRTAVFS_PSM_CNTL__RESERVED_MASK 0xFFFF8000L |
36249 | //GRTAVFS_CLK_CNTL |
36250 | #define GRTAVFS_CLK_CNTL__GRTAVFS_MUX_CLK_SEL__SHIFT 0x0 |
36251 | #define GRTAVFS_CLK_CNTL__FORCE_GRTAVFS_CLK_SEL__SHIFT 0x1 |
36252 | #define GRTAVFS_CLK_CNTL__RESERVED__SHIFT 0x2 |
36253 | #define GRTAVFS_CLK_CNTL__GRTAVFS_MUX_CLK_SEL_MASK 0x00000001L |
36254 | #define GRTAVFS_CLK_CNTL__FORCE_GRTAVFS_CLK_SEL_MASK 0x00000002L |
36255 | #define GRTAVFS_CLK_CNTL__RESERVED_MASK 0xFFFFFFFCL |
36256 | |
36257 | |
36258 | // addressBlock: gc_grtavfs_se_grtavfs_dec |
36259 | //GRTAVFS_SE_RTAVFS_REG_ADDR |
36260 | #define GRTAVFS_SE_RTAVFS_REG_ADDR__RTAVFSADDR__SHIFT 0x0 |
36261 | #define GRTAVFS_SE_RTAVFS_REG_ADDR__RTAVFSADDR_MASK 0x000003FFL |
36262 | //GRTAVFS_SE_RTAVFS_WR_DATA |
36263 | #define GRTAVFS_SE_RTAVFS_WR_DATA__RTAVFSDATA__SHIFT 0x0 |
36264 | #define GRTAVFS_SE_RTAVFS_WR_DATA__RTAVFSDATA_MASK 0xFFFFFFFFL |
36265 | //GRTAVFS_SE_GENERAL_0 |
36266 | #define GRTAVFS_SE_GENERAL_0__DATA__SHIFT 0x0 |
36267 | #define GRTAVFS_SE_GENERAL_0__DATA_MASK 0xFFFFFFFFL |
36268 | //GRTAVFS_SE_RTAVFS_RD_DATA |
36269 | #define GRTAVFS_SE_RTAVFS_RD_DATA__RTAVFSDATA__SHIFT 0x0 |
36270 | #define GRTAVFS_SE_RTAVFS_RD_DATA__RTAVFSDATA_MASK 0xFFFFFFFFL |
36271 | //GRTAVFS_SE_RTAVFS_REG_CTRL |
36272 | #define GRTAVFS_SE_RTAVFS_REG_CTRL__SET_WR_EN__SHIFT 0x0 |
36273 | #define GRTAVFS_SE_RTAVFS_REG_CTRL__SET_RD_EN__SHIFT 0x1 |
36274 | #define GRTAVFS_SE_RTAVFS_REG_CTRL__SET_WR_EN_MASK 0x00000001L |
36275 | #define GRTAVFS_SE_RTAVFS_REG_CTRL__SET_RD_EN_MASK 0x00000002L |
36276 | //GRTAVFS_SE_RTAVFS_REG_STATUS |
36277 | #define GRTAVFS_SE_RTAVFS_REG_STATUS__RTAVFS_WR_ACK__SHIFT 0x0 |
36278 | #define GRTAVFS_SE_RTAVFS_REG_STATUS__RTAVFS_RD_DATA_VALID__SHIFT 0x1 |
36279 | #define GRTAVFS_SE_RTAVFS_REG_STATUS__RTAVFS_WR_ACK_MASK 0x00000001L |
36280 | #define GRTAVFS_SE_RTAVFS_REG_STATUS__RTAVFS_RD_DATA_VALID_MASK 0x00000002L |
36281 | //GRTAVFS_SE_TARG_FREQ |
36282 | #define GRTAVFS_SE_TARG_FREQ__TARGET_FREQUENCY__SHIFT 0x0 |
36283 | #define GRTAVFS_SE_TARG_FREQ__REQUEST__SHIFT 0x10 |
36284 | #define GRTAVFS_SE_TARG_FREQ__RESERVED__SHIFT 0x11 |
36285 | #define GRTAVFS_SE_TARG_FREQ__TARGET_FREQUENCY_MASK 0x0000FFFFL |
36286 | #define GRTAVFS_SE_TARG_FREQ__REQUEST_MASK 0x00010000L |
36287 | #define GRTAVFS_SE_TARG_FREQ__RESERVED_MASK 0xFFFE0000L |
36288 | //GRTAVFS_SE_TARG_VOLT |
36289 | #define GRTAVFS_SE_TARG_VOLT__TARGET_VOLTAGE__SHIFT 0x0 |
36290 | #define GRTAVFS_SE_TARG_VOLT__VALID__SHIFT 0xa |
36291 | #define GRTAVFS_SE_TARG_VOLT__RESERVED__SHIFT 0xb |
36292 | #define GRTAVFS_SE_TARG_VOLT__TARGET_VOLTAGE_MASK 0x000003FFL |
36293 | #define GRTAVFS_SE_TARG_VOLT__VALID_MASK 0x00000400L |
36294 | #define GRTAVFS_SE_TARG_VOLT__RESERVED_MASK 0xFFFFF800L |
36295 | //GRTAVFS_SE_SOFT_RESET |
36296 | #define GRTAVFS_SE_SOFT_RESET__RESETN_OVERRIDE__SHIFT 0x0 |
36297 | #define GRTAVFS_SE_SOFT_RESET__RESERVED__SHIFT 0x1 |
36298 | #define GRTAVFS_SE_SOFT_RESET__RESETN_OVERRIDE_MASK 0x00000001L |
36299 | #define GRTAVFS_SE_SOFT_RESET__RESERVED_MASK 0xFFFFFFFEL |
36300 | //GRTAVFS_SE_PSM_CNTL |
36301 | #define GRTAVFS_SE_PSM_CNTL__PSM_COUNT__SHIFT 0x0 |
36302 | #define GRTAVFS_SE_PSM_CNTL__PSM_SAMPLE_EN__SHIFT 0xe |
36303 | #define GRTAVFS_SE_PSM_CNTL__RESERVED__SHIFT 0xf |
36304 | #define GRTAVFS_SE_PSM_CNTL__PSM_COUNT_MASK 0x00003FFFL |
36305 | #define GRTAVFS_SE_PSM_CNTL__PSM_SAMPLE_EN_MASK 0x00004000L |
36306 | #define GRTAVFS_SE_PSM_CNTL__RESERVED_MASK 0xFFFF8000L |
36307 | //GRTAVFS_SE_CLK_CNTL |
36308 | #define GRTAVFS_SE_CLK_CNTL__GRTAVFS_MUX_CLK_SEL__SHIFT 0x0 |
36309 | #define GRTAVFS_SE_CLK_CNTL__FORCE_GRTAVFS_CLK_SEL__SHIFT 0x1 |
36310 | #define GRTAVFS_SE_CLK_CNTL__RESERVED__SHIFT 0x2 |
36311 | #define GRTAVFS_SE_CLK_CNTL__GRTAVFS_MUX_CLK_SEL_MASK 0x00000001L |
36312 | #define GRTAVFS_SE_CLK_CNTL__FORCE_GRTAVFS_CLK_SEL_MASK 0x00000002L |
36313 | #define GRTAVFS_SE_CLK_CNTL__RESERVED_MASK 0xFFFFFFFCL |
36314 | |
36315 | |
36316 | // addressBlock: gc_grtavfsdec |
36317 | //RTAVFS_RTAVFS_REG_ADDR |
36318 | #define RTAVFS_RTAVFS_REG_ADDR__RTAVFSADDR__SHIFT 0x0 |
36319 | #define RTAVFS_RTAVFS_REG_ADDR__RTAVFSADDR_MASK 0x000003FFL |
36320 | //RTAVFS_RTAVFS_WR_DATA |
36321 | #define RTAVFS_RTAVFS_WR_DATA__RTAVFSDATA__SHIFT 0x0 |
36322 | #define RTAVFS_RTAVFS_WR_DATA__RTAVFSDATA_MASK 0xFFFFFFFFL |
36323 | |
36324 | |
36325 | // addressBlock: gc_hypdec |
36326 | //GFX_PIPE_PRIORITY |
36327 | #define GFX_PIPE_PRIORITY__HP_PIPE_SELECT__SHIFT 0x0 |
36328 | #define GFX_PIPE_PRIORITY__HP_PIPE_SELECT_MASK 0x00000001L |
36329 | //RLC_GPU_IOV_VF_ENABLE |
36330 | #define RLC_GPU_IOV_VF_ENABLE__VF_ENABLE__SHIFT 0x0 |
36331 | #define RLC_GPU_IOV_VF_ENABLE__RESERVED__SHIFT 0x1 |
36332 | #define RLC_GPU_IOV_VF_ENABLE__VF_NUM__SHIFT 0x10 |
36333 | #define RLC_GPU_IOV_VF_ENABLE__VF_ENABLE_MASK 0x00000001L |
36334 | #define RLC_GPU_IOV_VF_ENABLE__RESERVED_MASK 0x0000FFFEL |
36335 | #define RLC_GPU_IOV_VF_ENABLE__VF_NUM_MASK 0xFFFF0000L |
36336 | //RLC_GPU_IOV_CFG_REG6 |
36337 | #define RLC_GPU_IOV_CFG_REG6__CNTXT_SIZE__SHIFT 0x0 |
36338 | #define RLC_GPU_IOV_CFG_REG6__CNTXT_LOCATION__SHIFT 0x7 |
36339 | #define RLC_GPU_IOV_CFG_REG6__RESERVED__SHIFT 0x8 |
36340 | #define RLC_GPU_IOV_CFG_REG6__CNTXT_OFFSET__SHIFT 0xa |
36341 | #define RLC_GPU_IOV_CFG_REG6__CNTXT_SIZE_MASK 0x0000007FL |
36342 | #define RLC_GPU_IOV_CFG_REG6__CNTXT_LOCATION_MASK 0x00000080L |
36343 | #define RLC_GPU_IOV_CFG_REG6__RESERVED_MASK 0x00000300L |
36344 | #define RLC_GPU_IOV_CFG_REG6__CNTXT_OFFSET_MASK 0xFFFFFC00L |
36345 | //RLC_SDMA0_STATUS |
36346 | #define RLC_SDMA0_STATUS__STATUS__SHIFT 0x0 |
36347 | #define RLC_SDMA0_STATUS__STATUS_MASK 0xFFFFFFFFL |
36348 | //RLC_SDMA1_STATUS |
36349 | #define RLC_SDMA1_STATUS__STATUS__SHIFT 0x0 |
36350 | #define RLC_SDMA1_STATUS__STATUS_MASK 0xFFFFFFFFL |
36351 | //RLC_SDMA2_STATUS |
36352 | #define RLC_SDMA2_STATUS__STATUS__SHIFT 0x0 |
36353 | #define RLC_SDMA2_STATUS__STATUS_MASK 0xFFFFFFFFL |
36354 | //RLC_SDMA3_STATUS |
36355 | #define RLC_SDMA3_STATUS__STATUS__SHIFT 0x0 |
36356 | #define RLC_SDMA3_STATUS__STATUS_MASK 0xFFFFFFFFL |
36357 | //RLC_SDMA0_BUSY_STATUS |
36358 | #define RLC_SDMA0_BUSY_STATUS__BUSY_STATUS__SHIFT 0x0 |
36359 | #define RLC_SDMA0_BUSY_STATUS__BUSY_STATUS_MASK 0xFFFFFFFFL |
36360 | //RLC_SDMA1_BUSY_STATUS |
36361 | #define RLC_SDMA1_BUSY_STATUS__BUSY_STATUS__SHIFT 0x0 |
36362 | #define RLC_SDMA1_BUSY_STATUS__BUSY_STATUS_MASK 0xFFFFFFFFL |
36363 | //RLC_SDMA2_BUSY_STATUS |
36364 | #define RLC_SDMA2_BUSY_STATUS__BUSY_STATUS__SHIFT 0x0 |
36365 | #define RLC_SDMA2_BUSY_STATUS__BUSY_STATUS_MASK 0xFFFFFFFFL |
36366 | //RLC_SDMA3_BUSY_STATUS |
36367 | #define RLC_SDMA3_BUSY_STATUS__BUSY_STATUS__SHIFT 0x0 |
36368 | #define RLC_SDMA3_BUSY_STATUS__BUSY_STATUS_MASK 0xFFFFFFFFL |
36369 | //RLC_GPU_IOV_CFG_REG8 |
36370 | #define RLC_GPU_IOV_CFG_REG8__VM_BUSY_STATUS__SHIFT 0x0 |
36371 | #define RLC_GPU_IOV_CFG_REG8__VM_BUSY_STATUS_MASK 0xFFFFFFFFL |
36372 | //RLC_RLCV_TIMER_INT_0 |
36373 | #define RLC_RLCV_TIMER_INT_0__TIMER__SHIFT 0x0 |
36374 | #define RLC_RLCV_TIMER_INT_0__TIMER_MASK 0xFFFFFFFFL |
36375 | //RLC_RLCV_TIMER_INT_1 |
36376 | #define RLC_RLCV_TIMER_INT_1__TIMER__SHIFT 0x0 |
36377 | #define RLC_RLCV_TIMER_INT_1__TIMER_MASK 0xFFFFFFFFL |
36378 | //RLC_RLCV_TIMER_CTRL |
36379 | #define RLC_RLCV_TIMER_CTRL__TIMER_0_EN__SHIFT 0x0 |
36380 | #define RLC_RLCV_TIMER_CTRL__TIMER_1_EN__SHIFT 0x1 |
36381 | #define RLC_RLCV_TIMER_CTRL__TIMER_0_AUTO_REARM__SHIFT 0x2 |
36382 | #define RLC_RLCV_TIMER_CTRL__TIMER_1_AUTO_REARM__SHIFT 0x3 |
36383 | #define RLC_RLCV_TIMER_CTRL__TIMER_0_INT_CLEAR__SHIFT 0x4 |
36384 | #define RLC_RLCV_TIMER_CTRL__TIMER_1_INT_CLEAR__SHIFT 0x5 |
36385 | #define RLC_RLCV_TIMER_CTRL__RESERVED__SHIFT 0x6 |
36386 | #define RLC_RLCV_TIMER_CTRL__TIMER_0_EN_MASK 0x00000001L |
36387 | #define RLC_RLCV_TIMER_CTRL__TIMER_1_EN_MASK 0x00000002L |
36388 | #define RLC_RLCV_TIMER_CTRL__TIMER_0_AUTO_REARM_MASK 0x00000004L |
36389 | #define RLC_RLCV_TIMER_CTRL__TIMER_1_AUTO_REARM_MASK 0x00000008L |
36390 | #define RLC_RLCV_TIMER_CTRL__TIMER_0_INT_CLEAR_MASK 0x00000010L |
36391 | #define RLC_RLCV_TIMER_CTRL__TIMER_1_INT_CLEAR_MASK 0x00000020L |
36392 | #define RLC_RLCV_TIMER_CTRL__RESERVED_MASK 0xFFFFFFC0L |
36393 | //RLC_RLCV_TIMER_STAT |
36394 | #define RLC_RLCV_TIMER_STAT__TIMER_0_STAT__SHIFT 0x0 |
36395 | #define RLC_RLCV_TIMER_STAT__TIMER_1_STAT__SHIFT 0x1 |
36396 | #define RLC_RLCV_TIMER_STAT__RESERVED__SHIFT 0x2 |
36397 | #define RLC_RLCV_TIMER_STAT__TIMER_0_ENABLE_SYNC__SHIFT 0x8 |
36398 | #define RLC_RLCV_TIMER_STAT__TIMER_1_ENABLE_SYNC__SHIFT 0x9 |
36399 | #define RLC_RLCV_TIMER_STAT__TIMER_0_AUTO_REARM_SYNC__SHIFT 0xa |
36400 | #define RLC_RLCV_TIMER_STAT__TIMER_1_AUTO_REARM_SYNC__SHIFT 0xb |
36401 | #define RLC_RLCV_TIMER_STAT__TIMER_0_STAT_MASK 0x00000001L |
36402 | #define RLC_RLCV_TIMER_STAT__TIMER_1_STAT_MASK 0x00000002L |
36403 | #define RLC_RLCV_TIMER_STAT__RESERVED_MASK 0x000000FCL |
36404 | #define RLC_RLCV_TIMER_STAT__TIMER_0_ENABLE_SYNC_MASK 0x00000100L |
36405 | #define RLC_RLCV_TIMER_STAT__TIMER_1_ENABLE_SYNC_MASK 0x00000200L |
36406 | #define RLC_RLCV_TIMER_STAT__TIMER_0_AUTO_REARM_SYNC_MASK 0x00000400L |
36407 | #define RLC_RLCV_TIMER_STAT__TIMER_1_AUTO_REARM_SYNC_MASK 0x00000800L |
36408 | //RLC_GPU_IOV_VF_DOORBELL_STATUS |
36409 | #define RLC_GPU_IOV_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS__SHIFT 0x0 |
36410 | #define RLC_GPU_IOV_VF_DOORBELL_STATUS__PF_DOORBELL_STATUS__SHIFT 0x1f |
36411 | #define RLC_GPU_IOV_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_MASK 0x7FFFFFFFL |
36412 | #define RLC_GPU_IOV_VF_DOORBELL_STATUS__PF_DOORBELL_STATUS_MASK 0x80000000L |
36413 | //RLC_GPU_IOV_VF_DOORBELL_STATUS_SET |
36414 | #define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__VF_DOORBELL_STATUS_SET__SHIFT 0x0 |
36415 | #define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__PF_DOORBELL_STATUS_SET__SHIFT 0x1f |
36416 | #define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__VF_DOORBELL_STATUS_SET_MASK 0x7FFFFFFFL |
36417 | #define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__PF_DOORBELL_STATUS_SET_MASK 0x80000000L |
36418 | //RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR |
36419 | #define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__VF_DOORBELL_STATUS_CLR__SHIFT 0x0 |
36420 | #define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__PF_DOORBELL_STATUS_CLR__SHIFT 0x1f |
36421 | #define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__VF_DOORBELL_STATUS_CLR_MASK 0x7FFFFFFFL |
36422 | #define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__PF_DOORBELL_STATUS_CLR_MASK 0x80000000L |
36423 | //RLC_GPU_IOV_VF_MASK |
36424 | #define RLC_GPU_IOV_VF_MASK__VF_MASK__SHIFT 0x0 |
36425 | #define RLC_GPU_IOV_VF_MASK__VF_MASK_MASK 0x7FFFFFFFL |
36426 | //RLC_HYP_SEMAPHORE_0 |
36427 | #define RLC_HYP_SEMAPHORE_0__CLIENT_ID__SHIFT 0x0 |
36428 | #define RLC_HYP_SEMAPHORE_0__RESERVED__SHIFT 0x5 |
36429 | #define RLC_HYP_SEMAPHORE_0__CLIENT_ID_MASK 0x0000001FL |
36430 | #define RLC_HYP_SEMAPHORE_0__RESERVED_MASK 0xFFFFFFE0L |
36431 | //RLC_HYP_SEMAPHORE_1 |
36432 | #define RLC_HYP_SEMAPHORE_1__CLIENT_ID__SHIFT 0x0 |
36433 | #define RLC_HYP_SEMAPHORE_1__RESERVED__SHIFT 0x5 |
36434 | #define RLC_HYP_SEMAPHORE_1__CLIENT_ID_MASK 0x0000001FL |
36435 | #define RLC_HYP_SEMAPHORE_1__RESERVED_MASK 0xFFFFFFE0L |
36436 | //RLC_BUSY_CLK_CNTL |
36437 | #define RLC_BUSY_CLK_CNTL__BUSY_OFF_LATENCY__SHIFT 0x0 |
36438 | #define RLC_BUSY_CLK_CNTL__GRBM_BUSY_OFF_LATENCY__SHIFT 0x8 |
36439 | #define RLC_BUSY_CLK_CNTL__BUSY_OFF_LATENCY_MASK 0x0000003FL |
36440 | #define RLC_BUSY_CLK_CNTL__GRBM_BUSY_OFF_LATENCY_MASK 0x00003F00L |
36441 | //RLC_CLK_CNTL |
36442 | #define RLC_CLK_CNTL__RLC_SRM_ICG_OVERRIDE__SHIFT 0x0 |
36443 | #define RLC_CLK_CNTL__RLC_IMU_ICG_OVERRIDE__SHIFT 0x1 |
36444 | #define RLC_CLK_CNTL__RLC_SPM_ICG_OVERRIDE__SHIFT 0x2 |
36445 | #define RLC_CLK_CNTL__RLC_SPM_RSPM_ICG_OVERRIDE__SHIFT 0x3 |
36446 | #define RLC_CLK_CNTL__RLC_GPM_ICG_OVERRIDE__SHIFT 0x4 |
36447 | #define RLC_CLK_CNTL__RLC_CMN_ICG_OVERRIDE__SHIFT 0x5 |
36448 | #define RLC_CLK_CNTL__RLC_TC_ICG_OVERRIDE__SHIFT 0x6 |
36449 | #define RLC_CLK_CNTL__RLC_REG_ICG_OVERRIDE__SHIFT 0x7 |
36450 | #define RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE__SHIFT 0x8 |
36451 | #define RLC_CLK_CNTL__RESERVED_9__SHIFT 0x9 |
36452 | #define RLC_CLK_CNTL__RLC_SPP_ICG_OVERRIDE__SHIFT 0xa |
36453 | #define RLC_CLK_CNTL__RESERVED_11__SHIFT 0xb |
36454 | #define RLC_CLK_CNTL__RLC_TC_FGCG_REP_OVERRIDE__SHIFT 0xc |
36455 | #define RLC_CLK_CNTL__RLC_DFLL_ICG_OVERRIDE__SHIFT 0xd |
36456 | #define RLC_CLK_CNTL__RESERVED_15__SHIFT 0xf |
36457 | #define RLC_CLK_CNTL__RLC_LX6_CORE_ICG_OVERRIDE__SHIFT 0x10 |
36458 | #define RLC_CLK_CNTL__RLC_LX6_ICG_OVERRIDE__SHIFT 0x11 |
36459 | #define RLC_CLK_CNTL__RLC_UTCL2_FGCG_OVERRIDE__SHIFT 0x12 |
36460 | #define RLC_CLK_CNTL__RLC_IH_GASKET_ICG_OVERRIDE__SHIFT 0x13 |
36461 | #define RLC_CLK_CNTL__RESERVED__SHIFT 0x14 |
36462 | #define RLC_CLK_CNTL__RLC_SRM_ICG_OVERRIDE_MASK 0x00000001L |
36463 | #define RLC_CLK_CNTL__RLC_IMU_ICG_OVERRIDE_MASK 0x00000002L |
36464 | #define RLC_CLK_CNTL__RLC_SPM_ICG_OVERRIDE_MASK 0x00000004L |
36465 | #define RLC_CLK_CNTL__RLC_SPM_RSPM_ICG_OVERRIDE_MASK 0x00000008L |
36466 | #define RLC_CLK_CNTL__RLC_GPM_ICG_OVERRIDE_MASK 0x00000010L |
36467 | #define RLC_CLK_CNTL__RLC_CMN_ICG_OVERRIDE_MASK 0x00000020L |
36468 | #define RLC_CLK_CNTL__RLC_TC_ICG_OVERRIDE_MASK 0x00000040L |
36469 | #define RLC_CLK_CNTL__RLC_REG_ICG_OVERRIDE_MASK 0x00000080L |
36470 | #define RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK 0x00000100L |
36471 | #define RLC_CLK_CNTL__RESERVED_9_MASK 0x00000200L |
36472 | #define RLC_CLK_CNTL__RLC_SPP_ICG_OVERRIDE_MASK 0x00000400L |
36473 | #define RLC_CLK_CNTL__RESERVED_11_MASK 0x00000800L |
36474 | #define RLC_CLK_CNTL__RLC_TC_FGCG_REP_OVERRIDE_MASK 0x00001000L |
36475 | #define RLC_CLK_CNTL__RLC_DFLL_ICG_OVERRIDE_MASK 0x00002000L |
36476 | #define RLC_CLK_CNTL__RESERVED_15_MASK 0x00008000L |
36477 | #define RLC_CLK_CNTL__RLC_LX6_CORE_ICG_OVERRIDE_MASK 0x00010000L |
36478 | #define RLC_CLK_CNTL__RLC_LX6_ICG_OVERRIDE_MASK 0x00020000L |
36479 | #define RLC_CLK_CNTL__RLC_UTCL2_FGCG_OVERRIDE_MASK 0x00040000L |
36480 | #define RLC_CLK_CNTL__RLC_IH_GASKET_ICG_OVERRIDE_MASK 0x00080000L |
36481 | #define RLC_CLK_CNTL__RESERVED_MASK 0xFFF00000L |
36482 | //RLC_PACE_TIMER_STAT |
36483 | #define RLC_PACE_TIMER_STAT__TIMER_0_STAT__SHIFT 0x0 |
36484 | #define RLC_PACE_TIMER_STAT__TIMER_1_STAT__SHIFT 0x1 |
36485 | #define RLC_PACE_TIMER_STAT__RESERVED__SHIFT 0x2 |
36486 | #define RLC_PACE_TIMER_STAT__TIMER_0_ENABLE_SYNC__SHIFT 0x8 |
36487 | #define RLC_PACE_TIMER_STAT__TIMER_1_ENABLE_SYNC__SHIFT 0x9 |
36488 | #define RLC_PACE_TIMER_STAT__TIMER_0_AUTO_REARM_SYNC__SHIFT 0xa |
36489 | #define RLC_PACE_TIMER_STAT__TIMER_1_AUTO_REARM_SYNC__SHIFT 0xb |
36490 | #define RLC_PACE_TIMER_STAT__TIMER_0_STAT_MASK 0x00000001L |
36491 | #define RLC_PACE_TIMER_STAT__TIMER_1_STAT_MASK 0x00000002L |
36492 | #define RLC_PACE_TIMER_STAT__RESERVED_MASK 0x000000FCL |
36493 | #define RLC_PACE_TIMER_STAT__TIMER_0_ENABLE_SYNC_MASK 0x00000100L |
36494 | #define RLC_PACE_TIMER_STAT__TIMER_1_ENABLE_SYNC_MASK 0x00000200L |
36495 | #define RLC_PACE_TIMER_STAT__TIMER_0_AUTO_REARM_SYNC_MASK 0x00000400L |
36496 | #define RLC_PACE_TIMER_STAT__TIMER_1_AUTO_REARM_SYNC_MASK 0x00000800L |
36497 | //RLC_GPU_IOV_SCH_BLOCK |
36498 | #define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_ID__SHIFT 0x0 |
36499 | #define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Ver__SHIFT 0x4 |
36500 | #define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Size__SHIFT 0x8 |
36501 | #define RLC_GPU_IOV_SCH_BLOCK__RESERVED__SHIFT 0x10 |
36502 | #define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_ID_MASK 0x0000000FL |
36503 | #define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Ver_MASK 0x000000F0L |
36504 | #define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Size_MASK 0x0000FF00L |
36505 | #define RLC_GPU_IOV_SCH_BLOCK__RESERVED_MASK 0xFFFF0000L |
36506 | //RLC_GPU_IOV_CFG_REG1 |
36507 | #define RLC_GPU_IOV_CFG_REG1__CMD_TYPE__SHIFT 0x0 |
36508 | #define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE__SHIFT 0x4 |
36509 | #define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_INTR_EN__SHIFT 0x5 |
36510 | #define RLC_GPU_IOV_CFG_REG1__RESERVED__SHIFT 0x6 |
36511 | #define RLC_GPU_IOV_CFG_REG1__FCN_ID__SHIFT 0x8 |
36512 | #define RLC_GPU_IOV_CFG_REG1__NEXT_FCN_ID__SHIFT 0x10 |
36513 | #define RLC_GPU_IOV_CFG_REG1__RESERVED1__SHIFT 0x18 |
36514 | #define RLC_GPU_IOV_CFG_REG1__CMD_TYPE_MASK 0x0000000FL |
36515 | #define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_MASK 0x00000010L |
36516 | #define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_INTR_EN_MASK 0x00000020L |
36517 | #define RLC_GPU_IOV_CFG_REG1__RESERVED_MASK 0x000000C0L |
36518 | #define RLC_GPU_IOV_CFG_REG1__FCN_ID_MASK 0x0000FF00L |
36519 | #define RLC_GPU_IOV_CFG_REG1__NEXT_FCN_ID_MASK 0x00FF0000L |
36520 | #define RLC_GPU_IOV_CFG_REG1__RESERVED1_MASK 0xFF000000L |
36521 | //RLC_GPU_IOV_CFG_REG2 |
36522 | #define RLC_GPU_IOV_CFG_REG2__CMD_STATUS__SHIFT 0x0 |
36523 | #define RLC_GPU_IOV_CFG_REG2__RESERVED__SHIFT 0x4 |
36524 | #define RLC_GPU_IOV_CFG_REG2__CMD_STATUS_MASK 0x0000000FL |
36525 | #define RLC_GPU_IOV_CFG_REG2__RESERVED_MASK 0xFFFFFFF0L |
36526 | //RLC_GPU_IOV_VM_BUSY_STATUS |
36527 | #define RLC_GPU_IOV_VM_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 |
36528 | #define RLC_GPU_IOV_VM_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL |
36529 | //RLC_GPU_IOV_SCH_0 |
36530 | #define RLC_GPU_IOV_SCH_0__ACTIVE_FUNCTIONS__SHIFT 0x0 |
36531 | #define RLC_GPU_IOV_SCH_0__ACTIVE_FUNCTIONS_MASK 0xFFFFFFFFL |
36532 | //RLC_GPU_IOV_ACTIVE_FCN_ID |
36533 | #define RLC_GPU_IOV_ACTIVE_FCN_ID__VF_ID__SHIFT 0x0 |
36534 | #define RLC_GPU_IOV_ACTIVE_FCN_ID__RESERVED_7_4__SHIFT 0x4 |
36535 | #define RLC_GPU_IOV_ACTIVE_FCN_ID__ACTIVE_FCN_ID_STATUS__SHIFT 0x8 |
36536 | #define RLC_GPU_IOV_ACTIVE_FCN_ID__RESERVED_30_12__SHIFT 0xc |
36537 | #define RLC_GPU_IOV_ACTIVE_FCN_ID__PF_VF__SHIFT 0x1f |
36538 | #define RLC_GPU_IOV_ACTIVE_FCN_ID__VF_ID_MASK 0x0000000FL |
36539 | #define RLC_GPU_IOV_ACTIVE_FCN_ID__RESERVED_7_4_MASK 0x000000F0L |
36540 | #define RLC_GPU_IOV_ACTIVE_FCN_ID__ACTIVE_FCN_ID_STATUS_MASK 0x00000F00L |
36541 | #define RLC_GPU_IOV_ACTIVE_FCN_ID__RESERVED_30_12_MASK 0x7FFFF000L |
36542 | #define RLC_GPU_IOV_ACTIVE_FCN_ID__PF_VF_MASK 0x80000000L |
36543 | //RLC_GPU_IOV_SCH_3 |
36544 | #define RLC_GPU_IOV_SCH_3__Time_Quanta_Def__SHIFT 0x0 |
36545 | #define RLC_GPU_IOV_SCH_3__Time_Quanta_Def_MASK 0xFFFFFFFFL |
36546 | //RLC_GPU_IOV_SCH_1 |
36547 | #define RLC_GPU_IOV_SCH_1__DATA__SHIFT 0x0 |
36548 | #define RLC_GPU_IOV_SCH_1__DATA_MASK 0xFFFFFFFFL |
36549 | //RLC_GPU_IOV_SCH_2 |
36550 | #define RLC_GPU_IOV_SCH_2__DATA__SHIFT 0x0 |
36551 | #define RLC_GPU_IOV_SCH_2__DATA_MASK 0xFFFFFFFFL |
36552 | //RLC_PACE_INT_FORCE |
36553 | #define RLC_PACE_INT_FORCE__FORCE_INT__SHIFT 0x0 |
36554 | #define RLC_PACE_INT_FORCE__FORCE_INT_MASK 0xFFFFFFFFL |
36555 | //RLC_PACE_INT_CLEAR |
36556 | #define RLC_PACE_INT_CLEAR__SMU_STRETCH_PCC_CLEAR__SHIFT 0x0 |
36557 | #define RLC_PACE_INT_CLEAR__SMU_PCC_CLEAR__SHIFT 0x1 |
36558 | #define RLC_PACE_INT_CLEAR__SMU_STRETCH_PCC_CLEAR_MASK 0x00000001L |
36559 | #define RLC_PACE_INT_CLEAR__SMU_PCC_CLEAR_MASK 0x00000002L |
36560 | //RLC_GPU_IOV_INT_STAT |
36561 | #define RLC_GPU_IOV_INT_STAT__STATUS__SHIFT 0x0 |
36562 | #define RLC_GPU_IOV_INT_STAT__STATUS_MASK 0xFFFFFFFFL |
36563 | //RLC_IH_COOKIE |
36564 | #define RLC_IH_COOKIE__DATA__SHIFT 0x0 |
36565 | #define RLC_IH_COOKIE__DATA_MASK 0xFFFFFFFFL |
36566 | //RLC_IH_COOKIE_CNTL |
36567 | #define RLC_IH_COOKIE_CNTL__CREDIT__SHIFT 0x0 |
36568 | #define RLC_IH_COOKIE_CNTL__RESET_COUNTER__SHIFT 0x2 |
36569 | #define RLC_IH_COOKIE_CNTL__CREDIT_MASK 0x00000003L |
36570 | #define RLC_IH_COOKIE_CNTL__RESET_COUNTER_MASK 0x00000004L |
36571 | //RLC_HYP_RLCG_UCODE_CHKSUM |
36572 | #define RLC_HYP_RLCG_UCODE_CHKSUM__UCODE_CHKSUM__SHIFT 0x0 |
36573 | #define RLC_HYP_RLCG_UCODE_CHKSUM__UCODE_CHKSUM_MASK 0xFFFFFFFFL |
36574 | //RLC_HYP_RLCP_UCODE_CHKSUM |
36575 | #define RLC_HYP_RLCP_UCODE_CHKSUM__UCODE_CHKSUM__SHIFT 0x0 |
36576 | #define RLC_HYP_RLCP_UCODE_CHKSUM__UCODE_CHKSUM_MASK 0xFFFFFFFFL |
36577 | //RLC_HYP_RLCV_UCODE_CHKSUM |
36578 | #define RLC_HYP_RLCV_UCODE_CHKSUM__UCODE_CHKSUM__SHIFT 0x0 |
36579 | #define RLC_HYP_RLCV_UCODE_CHKSUM__UCODE_CHKSUM_MASK 0xFFFFFFFFL |
36580 | //RLC_GPU_IOV_F32_CNTL |
36581 | #define RLC_GPU_IOV_F32_CNTL__ENABLE__SHIFT 0x0 |
36582 | #define RLC_GPU_IOV_F32_CNTL__ENABLE_MASK 0x00000001L |
36583 | //RLC_GPU_IOV_F32_RESET |
36584 | #define RLC_GPU_IOV_F32_RESET__RESET__SHIFT 0x0 |
36585 | #define RLC_GPU_IOV_F32_RESET__RESET_MASK 0x00000001L |
36586 | //RLC_GPU_IOV_UCODE_ADDR |
36587 | #define RLC_GPU_IOV_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 |
36588 | #define RLC_GPU_IOV_UCODE_ADDR__RESERVED__SHIFT 0xc |
36589 | #define RLC_GPU_IOV_UCODE_ADDR__UCODE_ADDR_MASK 0x00000FFFL |
36590 | #define RLC_GPU_IOV_UCODE_ADDR__RESERVED_MASK 0xFFFFF000L |
36591 | //RLC_GPU_IOV_UCODE_DATA |
36592 | #define RLC_GPU_IOV_UCODE_DATA__UCODE_DATA__SHIFT 0x0 |
36593 | #define RLC_GPU_IOV_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL |
36594 | //RLC_GPU_IOV_SMU_RESPONSE |
36595 | #define RLC_GPU_IOV_SMU_RESPONSE__RESP__SHIFT 0x0 |
36596 | #define RLC_GPU_IOV_SMU_RESPONSE__RESP_MASK 0xFFFFFFFFL |
36597 | //RLC_GPU_IOV_F32_INVALIDATE_CACHE |
36598 | #define RLC_GPU_IOV_F32_INVALIDATE_CACHE__INVALIDATE_CACHE__SHIFT 0x0 |
36599 | #define RLC_GPU_IOV_F32_INVALIDATE_CACHE__INVALIDATE_CACHE_MASK 0x00000001L |
36600 | //RLC_GPU_IOV_VIRT_RESET_REQ |
36601 | #define RLC_GPU_IOV_VIRT_RESET_REQ__VF_FLR__SHIFT 0x0 |
36602 | #define RLC_GPU_IOV_VIRT_RESET_REQ__SOFT_PF_FLR__SHIFT 0x1f |
36603 | #define RLC_GPU_IOV_VIRT_RESET_REQ__VF_FLR_MASK 0x7FFFFFFFL |
36604 | #define RLC_GPU_IOV_VIRT_RESET_REQ__SOFT_PF_FLR_MASK 0x80000000L |
36605 | //RLC_GPU_IOV_RLC_RESPONSE |
36606 | #define RLC_GPU_IOV_RLC_RESPONSE__RESP__SHIFT 0x0 |
36607 | #define RLC_GPU_IOV_RLC_RESPONSE__RESP_MASK 0xFFFFFFFFL |
36608 | //RLC_GPU_IOV_INT_DISABLE |
36609 | #define RLC_GPU_IOV_INT_DISABLE__DISABLE_INT__SHIFT 0x0 |
36610 | #define RLC_GPU_IOV_INT_DISABLE__DISABLE_INT_MASK 0xFFFFFFFFL |
36611 | //RLC_GPU_IOV_INT_FORCE |
36612 | #define RLC_GPU_IOV_INT_FORCE__FORCE_INT__SHIFT 0x0 |
36613 | #define RLC_GPU_IOV_INT_FORCE__FORCE_INT_MASK 0xFFFFFFFFL |
36614 | //RLC_GPU_IOV_SCRATCH_ADDR |
36615 | #define RLC_GPU_IOV_SCRATCH_ADDR__ADDR__SHIFT 0x0 |
36616 | #define RLC_GPU_IOV_SCRATCH_ADDR__ADDR_MASK 0x0000FFFFL |
36617 | //RLC_GPU_IOV_SCRATCH_DATA |
36618 | #define RLC_GPU_IOV_SCRATCH_DATA__DATA__SHIFT 0x0 |
36619 | #define RLC_GPU_IOV_SCRATCH_DATA__DATA_MASK 0xFFFFFFFFL |
36620 | //RLC_HYP_SEMAPHORE_2 |
36621 | #define RLC_HYP_SEMAPHORE_2__CLIENT_ID__SHIFT 0x0 |
36622 | #define RLC_HYP_SEMAPHORE_2__RESERVED__SHIFT 0x5 |
36623 | #define RLC_HYP_SEMAPHORE_2__CLIENT_ID_MASK 0x0000001FL |
36624 | #define RLC_HYP_SEMAPHORE_2__RESERVED_MASK 0xFFFFFFE0L |
36625 | //RLC_HYP_SEMAPHORE_3 |
36626 | #define RLC_HYP_SEMAPHORE_3__CLIENT_ID__SHIFT 0x0 |
36627 | #define RLC_HYP_SEMAPHORE_3__RESERVED__SHIFT 0x5 |
36628 | #define RLC_HYP_SEMAPHORE_3__CLIENT_ID_MASK 0x0000001FL |
36629 | #define RLC_HYP_SEMAPHORE_3__RESERVED_MASK 0xFFFFFFE0L |
36630 | //RLC_LX6_SCRATCH_ADDR |
36631 | #define RLC_LX6_SCRATCH_ADDR__ADDR__SHIFT 0x0 |
36632 | #define RLC_LX6_SCRATCH_ADDR__ADDR_MASK 0x000000FFL |
36633 | //RLC_LX6_CORE1_SCRATCH_ADDR |
36634 | #define RLC_LX6_CORE1_SCRATCH_ADDR__ADDR__SHIFT 0x0 |
36635 | #define RLC_LX6_CORE1_SCRATCH_ADDR__ADDR_MASK 0x000000FFL |
36636 | //RLC_GPM_UCODE_ADDR |
36637 | #define RLC_GPM_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 |
36638 | #define RLC_GPM_UCODE_ADDR__RESERVED__SHIFT 0xe |
36639 | #define RLC_GPM_UCODE_ADDR__UCODE_ADDR_MASK 0x00003FFFL |
36640 | #define RLC_GPM_UCODE_ADDR__RESERVED_MASK 0xFFFFC000L |
36641 | //RLC_GPM_UCODE_DATA |
36642 | #define RLC_GPM_UCODE_DATA__UCODE_DATA__SHIFT 0x0 |
36643 | #define RLC_GPM_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL |
36644 | //RLC_GPM_IRAM_ADDR |
36645 | #define RLC_GPM_IRAM_ADDR__ADDR__SHIFT 0x0 |
36646 | #define RLC_GPM_IRAM_ADDR__ADDR_MASK 0xFFFFFFFFL |
36647 | //RLC_GPM_IRAM_DATA |
36648 | #define RLC_GPM_IRAM_DATA__DATA__SHIFT 0x0 |
36649 | #define RLC_GPM_IRAM_DATA__DATA_MASK 0xFFFFFFFFL |
36650 | //RLC_RLCP_IRAM_ADDR |
36651 | #define RLC_RLCP_IRAM_ADDR__ADDR__SHIFT 0x0 |
36652 | #define RLC_RLCP_IRAM_ADDR__ADDR_MASK 0xFFFFFFFFL |
36653 | //RLC_RLCP_IRAM_DATA |
36654 | #define RLC_RLCP_IRAM_DATA__DATA__SHIFT 0x0 |
36655 | #define RLC_RLCP_IRAM_DATA__DATA_MASK 0xFFFFFFFFL |
36656 | //RLC_RLCV_IRAM_ADDR |
36657 | #define RLC_RLCV_IRAM_ADDR__ADDR__SHIFT 0x0 |
36658 | #define RLC_RLCV_IRAM_ADDR__ADDR_MASK 0xFFFFFFFFL |
36659 | //RLC_RLCV_IRAM_DATA |
36660 | #define RLC_RLCV_IRAM_DATA__DATA__SHIFT 0x0 |
36661 | #define RLC_RLCV_IRAM_DATA__DATA_MASK 0xFFFFFFFFL |
36662 | //RLC_LX6_DRAM_ADDR |
36663 | #define RLC_LX6_DRAM_ADDR__ADDR__SHIFT 0x0 |
36664 | #define RLC_LX6_DRAM_ADDR__ADDR_MASK 0x000007FFL |
36665 | //RLC_LX6_DRAM_DATA |
36666 | #define RLC_LX6_DRAM_DATA__DATA__SHIFT 0x0 |
36667 | #define RLC_LX6_DRAM_DATA__DATA_MASK 0xFFFFFFFFL |
36668 | //RLC_LX6_IRAM_ADDR |
36669 | #define RLC_LX6_IRAM_ADDR__ADDR__SHIFT 0x0 |
36670 | #define RLC_LX6_IRAM_ADDR__ADDR_MASK 0x00000FFFL |
36671 | //RLC_LX6_IRAM_DATA |
36672 | #define RLC_LX6_IRAM_DATA__DATA__SHIFT 0x0 |
36673 | #define RLC_LX6_IRAM_DATA__DATA_MASK 0xFFFFFFFFL |
36674 | //RLC_PACE_UCODE_ADDR |
36675 | #define RLC_PACE_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 |
36676 | #define RLC_PACE_UCODE_ADDR__RESERVED__SHIFT 0xc |
36677 | #define RLC_PACE_UCODE_ADDR__UCODE_ADDR_MASK 0x00000FFFL |
36678 | #define RLC_PACE_UCODE_ADDR__RESERVED_MASK 0xFFFFF000L |
36679 | //RLC_PACE_UCODE_DATA |
36680 | #define RLC_PACE_UCODE_DATA__UCODE_DATA__SHIFT 0x0 |
36681 | #define RLC_PACE_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL |
36682 | //RLC_GPM_SCRATCH_ADDR |
36683 | #define RLC_GPM_SCRATCH_ADDR__ADDR__SHIFT 0x0 |
36684 | #define RLC_GPM_SCRATCH_ADDR__ADDR_MASK 0x0000FFFFL |
36685 | //RLC_GPM_SCRATCH_DATA |
36686 | #define RLC_GPM_SCRATCH_DATA__DATA__SHIFT 0x0 |
36687 | #define RLC_GPM_SCRATCH_DATA__DATA_MASK 0xFFFFFFFFL |
36688 | //RLC_SRM_DRAM_ADDR |
36689 | #define RLC_SRM_DRAM_ADDR__ADDR__SHIFT 0x0 |
36690 | #define RLC_SRM_DRAM_ADDR__RESERVED__SHIFT 0xd |
36691 | #define RLC_SRM_DRAM_ADDR__ADDR_MASK 0x00001FFFL |
36692 | #define RLC_SRM_DRAM_ADDR__RESERVED_MASK 0xFFFFE000L |
36693 | //RLC_SRM_DRAM_DATA |
36694 | #define RLC_SRM_DRAM_DATA__DATA__SHIFT 0x0 |
36695 | #define RLC_SRM_DRAM_DATA__DATA_MASK 0xFFFFFFFFL |
36696 | //RLC_SRM_ARAM_ADDR |
36697 | #define RLC_SRM_ARAM_ADDR__ADDR__SHIFT 0x0 |
36698 | #define RLC_SRM_ARAM_ADDR__RESERVED__SHIFT 0xd |
36699 | #define RLC_SRM_ARAM_ADDR__ADDR_MASK 0x00001FFFL |
36700 | #define RLC_SRM_ARAM_ADDR__RESERVED_MASK 0xFFFFE000L |
36701 | //RLC_SRM_ARAM_DATA |
36702 | #define RLC_SRM_ARAM_DATA__DATA__SHIFT 0x0 |
36703 | #define RLC_SRM_ARAM_DATA__DATA_MASK 0xFFFFFFFFL |
36704 | //RLC_PACE_SCRATCH_ADDR |
36705 | #define RLC_PACE_SCRATCH_ADDR__ADDR__SHIFT 0x0 |
36706 | #define RLC_PACE_SCRATCH_ADDR__ADDR_MASK 0x0000FFFFL |
36707 | //RLC_PACE_SCRATCH_DATA |
36708 | #define RLC_PACE_SCRATCH_DATA__DATA__SHIFT 0x0 |
36709 | #define RLC_PACE_SCRATCH_DATA__DATA_MASK 0xFFFFFFFFL |
36710 | //RLC_GTS_OFFSET_LSB |
36711 | #define RLC_GTS_OFFSET_LSB__DATA__SHIFT 0x0 |
36712 | #define RLC_GTS_OFFSET_LSB__DATA_MASK 0xFFFFFFFFL |
36713 | //RLC_GTS_OFFSET_MSB |
36714 | #define RLC_GTS_OFFSET_MSB__DATA__SHIFT 0x0 |
36715 | #define RLC_GTS_OFFSET_MSB__DATA_MASK 0xFFFFFFFFL |
36716 | //GL2_PIPE_STEER_0 |
36717 | #define GL2_PIPE_STEER_0__PIPE_0_TO_CHAN_IN_Q0__SHIFT 0x0 |
36718 | #define GL2_PIPE_STEER_0__PIPE_1_TO_CHAN_IN_Q0__SHIFT 0x4 |
36719 | #define GL2_PIPE_STEER_0__PIPE_2_TO_CHAN_IN_Q0__SHIFT 0x8 |
36720 | #define GL2_PIPE_STEER_0__PIPE_3_TO_CHAN_IN_Q0__SHIFT 0xc |
36721 | #define GL2_PIPE_STEER_0__PIPE_0_TO_CHAN_IN_Q1__SHIFT 0x10 |
36722 | #define GL2_PIPE_STEER_0__PIPE_1_TO_CHAN_IN_Q1__SHIFT 0x14 |
36723 | #define GL2_PIPE_STEER_0__PIPE_2_TO_CHAN_IN_Q1__SHIFT 0x18 |
36724 | #define GL2_PIPE_STEER_0__PIPE_3_TO_CHAN_IN_Q1__SHIFT 0x1c |
36725 | #define GL2_PIPE_STEER_0__PIPE_0_TO_CHAN_IN_Q0_MASK 0x00000007L |
36726 | #define GL2_PIPE_STEER_0__PIPE_1_TO_CHAN_IN_Q0_MASK 0x00000070L |
36727 | #define GL2_PIPE_STEER_0__PIPE_2_TO_CHAN_IN_Q0_MASK 0x00000700L |
36728 | #define GL2_PIPE_STEER_0__PIPE_3_TO_CHAN_IN_Q0_MASK 0x00007000L |
36729 | #define GL2_PIPE_STEER_0__PIPE_0_TO_CHAN_IN_Q1_MASK 0x00070000L |
36730 | #define GL2_PIPE_STEER_0__PIPE_1_TO_CHAN_IN_Q1_MASK 0x00700000L |
36731 | #define GL2_PIPE_STEER_0__PIPE_2_TO_CHAN_IN_Q1_MASK 0x07000000L |
36732 | #define GL2_PIPE_STEER_0__PIPE_3_TO_CHAN_IN_Q1_MASK 0x70000000L |
36733 | //GL2_PIPE_STEER_1 |
36734 | #define GL2_PIPE_STEER_1__PIPE_0_TO_CHAN_IN_Q2__SHIFT 0x0 |
36735 | #define GL2_PIPE_STEER_1__PIPE_1_TO_CHAN_IN_Q2__SHIFT 0x4 |
36736 | #define GL2_PIPE_STEER_1__PIPE_2_TO_CHAN_IN_Q2__SHIFT 0x8 |
36737 | #define GL2_PIPE_STEER_1__PIPE_3_TO_CHAN_IN_Q2__SHIFT 0xc |
36738 | #define GL2_PIPE_STEER_1__PIPE_0_TO_CHAN_IN_Q3__SHIFT 0x10 |
36739 | #define GL2_PIPE_STEER_1__PIPE_1_TO_CHAN_IN_Q3__SHIFT 0x14 |
36740 | #define GL2_PIPE_STEER_1__PIPE_2_TO_CHAN_IN_Q3__SHIFT 0x18 |
36741 | #define GL2_PIPE_STEER_1__PIPE_3_TO_CHAN_IN_Q3__SHIFT 0x1c |
36742 | #define GL2_PIPE_STEER_1__PIPE_0_TO_CHAN_IN_Q2_MASK 0x00000007L |
36743 | #define GL2_PIPE_STEER_1__PIPE_1_TO_CHAN_IN_Q2_MASK 0x00000070L |
36744 | #define GL2_PIPE_STEER_1__PIPE_2_TO_CHAN_IN_Q2_MASK 0x00000700L |
36745 | #define GL2_PIPE_STEER_1__PIPE_3_TO_CHAN_IN_Q2_MASK 0x00007000L |
36746 | #define GL2_PIPE_STEER_1__PIPE_0_TO_CHAN_IN_Q3_MASK 0x00070000L |
36747 | #define GL2_PIPE_STEER_1__PIPE_1_TO_CHAN_IN_Q3_MASK 0x00700000L |
36748 | #define GL2_PIPE_STEER_1__PIPE_2_TO_CHAN_IN_Q3_MASK 0x07000000L |
36749 | #define GL2_PIPE_STEER_1__PIPE_3_TO_CHAN_IN_Q3_MASK 0x70000000L |
36750 | //GL2_PIPE_STEER_2 |
36751 | #define GL2_PIPE_STEER_2__PIPE_4_TO_CHAN_IN_Q0__SHIFT 0x0 |
36752 | #define GL2_PIPE_STEER_2__PIPE_5_TO_CHAN_IN_Q0__SHIFT 0x4 |
36753 | #define GL2_PIPE_STEER_2__PIPE_6_TO_CHAN_IN_Q0__SHIFT 0x8 |
36754 | #define GL2_PIPE_STEER_2__PIPE_7_TO_CHAN_IN_Q0__SHIFT 0xc |
36755 | #define GL2_PIPE_STEER_2__PIPE_4_TO_CHAN_IN_Q1__SHIFT 0x10 |
36756 | #define GL2_PIPE_STEER_2__PIPE_5_TO_CHAN_IN_Q1__SHIFT 0x14 |
36757 | #define GL2_PIPE_STEER_2__PIPE_6_TO_CHAN_IN_Q1__SHIFT 0x18 |
36758 | #define GL2_PIPE_STEER_2__PIPE_7_TO_CHAN_IN_Q1__SHIFT 0x1c |
36759 | #define GL2_PIPE_STEER_2__PIPE_4_TO_CHAN_IN_Q0_MASK 0x00000007L |
36760 | #define GL2_PIPE_STEER_2__PIPE_5_TO_CHAN_IN_Q0_MASK 0x00000070L |
36761 | #define GL2_PIPE_STEER_2__PIPE_6_TO_CHAN_IN_Q0_MASK 0x00000700L |
36762 | #define GL2_PIPE_STEER_2__PIPE_7_TO_CHAN_IN_Q0_MASK 0x00007000L |
36763 | #define GL2_PIPE_STEER_2__PIPE_4_TO_CHAN_IN_Q1_MASK 0x00070000L |
36764 | #define GL2_PIPE_STEER_2__PIPE_5_TO_CHAN_IN_Q1_MASK 0x00700000L |
36765 | #define GL2_PIPE_STEER_2__PIPE_6_TO_CHAN_IN_Q1_MASK 0x07000000L |
36766 | #define GL2_PIPE_STEER_2__PIPE_7_TO_CHAN_IN_Q1_MASK 0x70000000L |
36767 | //GL2_PIPE_STEER_3 |
36768 | #define GL2_PIPE_STEER_3__PIPE_4_TO_CHAN_IN_Q2__SHIFT 0x0 |
36769 | #define GL2_PIPE_STEER_3__PIPE_5_TO_CHAN_IN_Q2__SHIFT 0x4 |
36770 | #define GL2_PIPE_STEER_3__PIPE_6_TO_CHAN_IN_Q2__SHIFT 0x8 |
36771 | #define GL2_PIPE_STEER_3__PIPE_7_TO_CHAN_IN_Q2__SHIFT 0xc |
36772 | #define GL2_PIPE_STEER_3__PIPE_4_TO_CHAN_IN_Q3__SHIFT 0x10 |
36773 | #define GL2_PIPE_STEER_3__PIPE_5_TO_CHAN_IN_Q3__SHIFT 0x14 |
36774 | #define GL2_PIPE_STEER_3__PIPE_6_TO_CHAN_IN_Q3__SHIFT 0x18 |
36775 | #define GL2_PIPE_STEER_3__PIPE_7_TO_CHAN_IN_Q3__SHIFT 0x1c |
36776 | #define GL2_PIPE_STEER_3__PIPE_4_TO_CHAN_IN_Q2_MASK 0x00000007L |
36777 | #define GL2_PIPE_STEER_3__PIPE_5_TO_CHAN_IN_Q2_MASK 0x00000070L |
36778 | #define GL2_PIPE_STEER_3__PIPE_6_TO_CHAN_IN_Q2_MASK 0x00000700L |
36779 | #define GL2_PIPE_STEER_3__PIPE_7_TO_CHAN_IN_Q2_MASK 0x00007000L |
36780 | #define GL2_PIPE_STEER_3__PIPE_4_TO_CHAN_IN_Q3_MASK 0x00070000L |
36781 | #define GL2_PIPE_STEER_3__PIPE_5_TO_CHAN_IN_Q3_MASK 0x00700000L |
36782 | #define GL2_PIPE_STEER_3__PIPE_6_TO_CHAN_IN_Q3_MASK 0x07000000L |
36783 | #define GL2_PIPE_STEER_3__PIPE_7_TO_CHAN_IN_Q3_MASK 0x70000000L |
36784 | //GL1_PIPE_STEER |
36785 | #define GL1_PIPE_STEER__PIPE0__SHIFT 0x0 |
36786 | #define GL1_PIPE_STEER__PIPE1__SHIFT 0x2 |
36787 | #define GL1_PIPE_STEER__PIPE2__SHIFT 0x4 |
36788 | #define GL1_PIPE_STEER__PIPE3__SHIFT 0x6 |
36789 | #define GL1_PIPE_STEER__PIPE0_MASK 0x00000003L |
36790 | #define GL1_PIPE_STEER__PIPE1_MASK 0x0000000CL |
36791 | #define GL1_PIPE_STEER__PIPE2_MASK 0x00000030L |
36792 | #define GL1_PIPE_STEER__PIPE3_MASK 0x000000C0L |
36793 | //CH_PIPE_STEER |
36794 | #define CH_PIPE_STEER__PIPE0__SHIFT 0x0 |
36795 | #define CH_PIPE_STEER__PIPE1__SHIFT 0x2 |
36796 | #define CH_PIPE_STEER__PIPE2__SHIFT 0x4 |
36797 | #define CH_PIPE_STEER__PIPE3__SHIFT 0x6 |
36798 | #define CH_PIPE_STEER__PIPE0_MASK 0x00000003L |
36799 | #define CH_PIPE_STEER__PIPE1_MASK 0x0000000CL |
36800 | #define CH_PIPE_STEER__PIPE2_MASK 0x00000030L |
36801 | #define CH_PIPE_STEER__PIPE3_MASK 0x000000C0L |
36802 | //GC_USER_SHADER_ARRAY_CONFIG |
36803 | #define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT 0x10 |
36804 | #define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK 0xFFFF0000L |
36805 | //GC_USER_PRIM_CONFIG |
36806 | #define GC_USER_PRIM_CONFIG__INACTIVE_PA__SHIFT 0x4 |
36807 | #define GC_USER_PRIM_CONFIG__INACTIVE_PA_MASK 0x000FFFF0L |
36808 | //GC_USER_SA_UNIT_DISABLE |
36809 | #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT 0x8 |
36810 | #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK 0x00FFFF00L |
36811 | //GC_USER_RB_REDUNDANCY |
36812 | #define GC_USER_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8 |
36813 | #define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc |
36814 | #define GC_USER_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10 |
36815 | #define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14 |
36816 | #define GC_USER_RB_REDUNDANCY__FAILED_RB0_MASK 0x00000F00L |
36817 | #define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x00001000L |
36818 | #define GC_USER_RB_REDUNDANCY__FAILED_RB1_MASK 0x000F0000L |
36819 | #define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x00100000L |
36820 | //GC_USER_RB_BACKEND_DISABLE |
36821 | #define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x4 |
36822 | #define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0xFFFFFFF0L |
36823 | //GC_USER_RMI_REDUNDANCY |
36824 | #define GC_USER_RMI_REDUNDANCY__REPAIR_EN_IN_0__SHIFT 0x1 |
36825 | #define GC_USER_RMI_REDUNDANCY__REPAIR_EN_IN_1__SHIFT 0x2 |
36826 | #define GC_USER_RMI_REDUNDANCY__REPAIR_RMI_OVERRIDE__SHIFT 0x3 |
36827 | #define GC_USER_RMI_REDUNDANCY__REPAIR_ID_SWAP__SHIFT 0x4 |
36828 | #define GC_USER_RMI_REDUNDANCY__REPAIR_EN_IN_0_MASK 0x00000002L |
36829 | #define GC_USER_RMI_REDUNDANCY__REPAIR_EN_IN_1_MASK 0x00000004L |
36830 | #define GC_USER_RMI_REDUNDANCY__REPAIR_RMI_OVERRIDE_MASK 0x00000008L |
36831 | #define GC_USER_RMI_REDUNDANCY__REPAIR_ID_SWAP_MASK 0x00000010L |
36832 | //CGTS_USER_TCC_DISABLE |
36833 | #define CGTS_USER_TCC_DISABLE__HI_TCC_DISABLE__SHIFT 0x8 |
36834 | #define CGTS_USER_TCC_DISABLE__TCC_DISABLE__SHIFT 0x10 |
36835 | #define CGTS_USER_TCC_DISABLE__HI_TCC_DISABLE_MASK 0x0000FF00L |
36836 | #define CGTS_USER_TCC_DISABLE__TCC_DISABLE_MASK 0xFFFF0000L |
36837 | //GC_USER_SHADER_RATE_CONFIG |
36838 | #define GC_USER_SHADER_RATE_CONFIG__DPFP_RATE__SHIFT 0x1 |
36839 | #define GC_USER_SHADER_RATE_CONFIG__DPFP_RATE_MASK 0x00000006L |
36840 | //RLC_GPU_IOV_SDMA0_STATUS |
36841 | #define RLC_GPU_IOV_SDMA0_STATUS__STATUS__SHIFT 0x0 |
36842 | #define RLC_GPU_IOV_SDMA0_STATUS__STATUS_MASK 0xFFFFFFFFL |
36843 | //RLC_GPU_IOV_SDMA1_STATUS |
36844 | #define RLC_GPU_IOV_SDMA1_STATUS__STATUS__SHIFT 0x0 |
36845 | #define RLC_GPU_IOV_SDMA1_STATUS__STATUS_MASK 0xFFFFFFFFL |
36846 | //RLC_GPU_IOV_SDMA2_STATUS |
36847 | #define RLC_GPU_IOV_SDMA2_STATUS__STATUS__SHIFT 0x0 |
36848 | #define RLC_GPU_IOV_SDMA2_STATUS__STATUS_MASK 0xFFFFFFFFL |
36849 | //RLC_GPU_IOV_SDMA3_STATUS |
36850 | #define RLC_GPU_IOV_SDMA3_STATUS__STATUS__SHIFT 0x0 |
36851 | #define RLC_GPU_IOV_SDMA3_STATUS__STATUS_MASK 0xFFFFFFFFL |
36852 | //RLC_GPU_IOV_SDMA4_STATUS |
36853 | #define RLC_GPU_IOV_SDMA4_STATUS__STATUS__SHIFT 0x0 |
36854 | #define RLC_GPU_IOV_SDMA4_STATUS__STATUS_MASK 0xFFFFFFFFL |
36855 | //RLC_GPU_IOV_SDMA5_STATUS |
36856 | #define RLC_GPU_IOV_SDMA5_STATUS__STATUS__SHIFT 0x0 |
36857 | #define RLC_GPU_IOV_SDMA5_STATUS__STATUS_MASK 0xFFFFFFFFL |
36858 | //RLC_GPU_IOV_SDMA6_STATUS |
36859 | #define RLC_GPU_IOV_SDMA6_STATUS__STATUS__SHIFT 0x0 |
36860 | #define RLC_GPU_IOV_SDMA6_STATUS__STATUS_MASK 0xFFFFFFFFL |
36861 | //RLC_GPU_IOV_SDMA7_STATUS |
36862 | #define RLC_GPU_IOV_SDMA7_STATUS__STATUS__SHIFT 0x0 |
36863 | #define RLC_GPU_IOV_SDMA7_STATUS__STATUS_MASK 0xFFFFFFFFL |
36864 | //RLC_GPU_IOV_SDMA0_BUSY_STATUS |
36865 | #define RLC_GPU_IOV_SDMA0_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 |
36866 | #define RLC_GPU_IOV_SDMA0_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL |
36867 | //RLC_GPU_IOV_SDMA1_BUSY_STATUS |
36868 | #define RLC_GPU_IOV_SDMA1_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 |
36869 | #define RLC_GPU_IOV_SDMA1_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL |
36870 | //RLC_GPU_IOV_SDMA2_BUSY_STATUS |
36871 | #define RLC_GPU_IOV_SDMA2_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 |
36872 | #define RLC_GPU_IOV_SDMA2_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL |
36873 | //RLC_GPU_IOV_SDMA3_BUSY_STATUS |
36874 | #define RLC_GPU_IOV_SDMA3_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 |
36875 | #define RLC_GPU_IOV_SDMA3_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL |
36876 | //RLC_GPU_IOV_SDMA4_BUSY_STATUS |
36877 | #define RLC_GPU_IOV_SDMA4_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 |
36878 | #define RLC_GPU_IOV_SDMA4_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL |
36879 | //RLC_GPU_IOV_SDMA5_BUSY_STATUS |
36880 | #define RLC_GPU_IOV_SDMA5_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 |
36881 | #define RLC_GPU_IOV_SDMA5_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL |
36882 | //RLC_GPU_IOV_SDMA6_BUSY_STATUS |
36883 | #define RLC_GPU_IOV_SDMA6_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 |
36884 | #define RLC_GPU_IOV_SDMA6_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL |
36885 | //RLC_GPU_IOV_SDMA7_BUSY_STATUS |
36886 | #define RLC_GPU_IOV_SDMA7_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 |
36887 | #define RLC_GPU_IOV_SDMA7_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL |
36888 | |
36889 | |
36890 | // addressBlock: gc_cphypdec |
36891 | //CP_HYP_PFP_UCODE_ADDR |
36892 | #define CP_HYP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 |
36893 | #define CP_HYP_PFP_UCODE_ADDR__UCODE_ADDR_MASK 0x000FFFFFL |
36894 | //CP_PFP_UCODE_ADDR |
36895 | #define CP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 |
36896 | #define CP_PFP_UCODE_ADDR__UCODE_ADDR_MASK 0x000FFFFFL |
36897 | //CP_HYP_PFP_UCODE_DATA |
36898 | #define CP_HYP_PFP_UCODE_DATA__UCODE_DATA__SHIFT 0x0 |
36899 | #define CP_HYP_PFP_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL |
36900 | //CP_PFP_UCODE_DATA |
36901 | #define CP_PFP_UCODE_DATA__UCODE_DATA__SHIFT 0x0 |
36902 | #define CP_PFP_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL |
36903 | //CP_HYP_ME_UCODE_ADDR |
36904 | #define CP_HYP_ME_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 |
36905 | #define CP_HYP_ME_UCODE_ADDR__UCODE_ADDR_MASK 0x000FFFFFL |
36906 | //CP_ME_RAM_RADDR |
36907 | #define CP_ME_RAM_RADDR__ME_RAM_RADDR__SHIFT 0x0 |
36908 | #define CP_ME_RAM_RADDR__ME_RAM_RADDR_MASK 0x000FFFFFL |
36909 | //CP_ME_RAM_WADDR |
36910 | #define CP_ME_RAM_WADDR__ME_RAM_WADDR__SHIFT 0x0 |
36911 | #define CP_ME_RAM_WADDR__ME_RAM_WADDR_MASK 0x001FFFFFL |
36912 | //CP_HYP_ME_UCODE_DATA |
36913 | #define CP_HYP_ME_UCODE_DATA__UCODE_DATA__SHIFT 0x0 |
36914 | #define CP_HYP_ME_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL |
36915 | //CP_ME_RAM_DATA |
36916 | #define CP_ME_RAM_DATA__ME_RAM_DATA__SHIFT 0x0 |
36917 | #define CP_ME_RAM_DATA__ME_RAM_DATA_MASK 0xFFFFFFFFL |
36918 | //CP_HYP_MEC1_UCODE_ADDR |
36919 | #define CP_HYP_MEC1_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 |
36920 | #define CP_HYP_MEC1_UCODE_ADDR__UCODE_ADDR_MASK 0x000FFFFFL |
36921 | //CP_MEC_ME1_UCODE_ADDR |
36922 | #define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 |
36923 | #define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR_MASK 0x000FFFFFL |
36924 | //CP_HYP_MEC1_UCODE_DATA |
36925 | #define CP_HYP_MEC1_UCODE_DATA__UCODE_DATA__SHIFT 0x0 |
36926 | #define CP_HYP_MEC1_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL |
36927 | //CP_MEC_ME1_UCODE_DATA |
36928 | #define CP_MEC_ME1_UCODE_DATA__UCODE_DATA__SHIFT 0x0 |
36929 | #define CP_MEC_ME1_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL |
36930 | //CP_HYP_MEC2_UCODE_ADDR |
36931 | #define CP_HYP_MEC2_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 |
36932 | #define CP_HYP_MEC2_UCODE_ADDR__UCODE_ADDR_MASK 0x000FFFFFL |
36933 | //CP_MEC_ME2_UCODE_ADDR |
36934 | #define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 |
36935 | #define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR_MASK 0x000FFFFFL |
36936 | //CP_HYP_MEC2_UCODE_DATA |
36937 | #define CP_HYP_MEC2_UCODE_DATA__UCODE_DATA__SHIFT 0x0 |
36938 | #define CP_HYP_MEC2_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL |
36939 | //CP_MEC_ME2_UCODE_DATA |
36940 | #define CP_MEC_ME2_UCODE_DATA__UCODE_DATA__SHIFT 0x0 |
36941 | #define CP_MEC_ME2_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL |
36942 | //CP_HYP_PFP_UCODE_CHKSUM |
36943 | #define CP_HYP_PFP_UCODE_CHKSUM__UCODE_CHKSUM__SHIFT 0x0 |
36944 | #define CP_HYP_PFP_UCODE_CHKSUM__UCODE_CHKSUM_MASK 0xFFFFFFFFL |
36945 | //CP_HYP_ME_UCODE_CHKSUM |
36946 | #define CP_HYP_ME_UCODE_CHKSUM__UCODE_CHKSUM__SHIFT 0x0 |
36947 | #define CP_HYP_ME_UCODE_CHKSUM__UCODE_CHKSUM_MASK 0xFFFFFFFFL |
36948 | //CP_HYP_MEC_ME1_UCODE_CHKSUM |
36949 | #define CP_HYP_MEC_ME1_UCODE_CHKSUM__UCODE_CHKSUM__SHIFT 0x0 |
36950 | #define CP_HYP_MEC_ME1_UCODE_CHKSUM__UCODE_CHKSUM_MASK 0xFFFFFFFFL |
36951 | //CP_HYP_MEC_ME2_UCODE_CHKSUM |
36952 | #define CP_HYP_MEC_ME2_UCODE_CHKSUM__UCODE_CHKSUM__SHIFT 0x0 |
36953 | #define CP_HYP_MEC_ME2_UCODE_CHKSUM__UCODE_CHKSUM_MASK 0xFFFFFFFFL |
36954 | //CP_PFP_IC_BASE_LO |
36955 | #define CP_PFP_IC_BASE_LO__IC_BASE_LO__SHIFT 0xc |
36956 | #define CP_PFP_IC_BASE_LO__IC_BASE_LO_MASK 0xFFFFF000L |
36957 | //CP_PFP_IC_BASE_HI |
36958 | #define CP_PFP_IC_BASE_HI__IC_BASE_HI__SHIFT 0x0 |
36959 | #define CP_PFP_IC_BASE_HI__IC_BASE_HI_MASK 0x0000FFFFL |
36960 | //CP_PFP_IC_BASE_CNTL |
36961 | #define CP_PFP_IC_BASE_CNTL__VMID__SHIFT 0x0 |
36962 | #define CP_PFP_IC_BASE_CNTL__ADDRESS_CLAMP__SHIFT 0x4 |
36963 | #define CP_PFP_IC_BASE_CNTL__EXE_DISABLE__SHIFT 0x17 |
36964 | #define CP_PFP_IC_BASE_CNTL__CACHE_POLICY__SHIFT 0x18 |
36965 | #define CP_PFP_IC_BASE_CNTL__VMID_MASK 0x0000000FL |
36966 | #define CP_PFP_IC_BASE_CNTL__ADDRESS_CLAMP_MASK 0x00000010L |
36967 | #define CP_PFP_IC_BASE_CNTL__EXE_DISABLE_MASK 0x00800000L |
36968 | #define CP_PFP_IC_BASE_CNTL__CACHE_POLICY_MASK 0x03000000L |
36969 | //CP_PFP_IC_OP_CNTL |
36970 | #define CP_PFP_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT 0x0 |
36971 | #define CP_PFP_IC_OP_CNTL__INVALIDATE_CACHE_COMPLETE__SHIFT 0x1 |
36972 | #define CP_PFP_IC_OP_CNTL__PRIME_ICACHE__SHIFT 0x4 |
36973 | #define CP_PFP_IC_OP_CNTL__ICACHE_PRIMED__SHIFT 0x5 |
36974 | #define CP_PFP_IC_OP_CNTL__INVALIDATE_CACHE_MASK 0x00000001L |
36975 | #define CP_PFP_IC_OP_CNTL__INVALIDATE_CACHE_COMPLETE_MASK 0x00000002L |
36976 | #define CP_PFP_IC_OP_CNTL__PRIME_ICACHE_MASK 0x00000010L |
36977 | #define CP_PFP_IC_OP_CNTL__ICACHE_PRIMED_MASK 0x00000020L |
36978 | //CP_ME_IC_BASE_LO |
36979 | #define CP_ME_IC_BASE_LO__IC_BASE_LO__SHIFT 0xc |
36980 | #define CP_ME_IC_BASE_LO__IC_BASE_LO_MASK 0xFFFFF000L |
36981 | //CP_ME_IC_BASE_HI |
36982 | #define CP_ME_IC_BASE_HI__IC_BASE_HI__SHIFT 0x0 |
36983 | #define CP_ME_IC_BASE_HI__IC_BASE_HI_MASK 0x0000FFFFL |
36984 | //CP_ME_IC_BASE_CNTL |
36985 | #define CP_ME_IC_BASE_CNTL__VMID__SHIFT 0x0 |
36986 | #define CP_ME_IC_BASE_CNTL__ADDRESS_CLAMP__SHIFT 0x4 |
36987 | #define CP_ME_IC_BASE_CNTL__EXE_DISABLE__SHIFT 0x17 |
36988 | #define CP_ME_IC_BASE_CNTL__CACHE_POLICY__SHIFT 0x18 |
36989 | #define CP_ME_IC_BASE_CNTL__VMID_MASK 0x0000000FL |
36990 | #define CP_ME_IC_BASE_CNTL__ADDRESS_CLAMP_MASK 0x00000010L |
36991 | #define CP_ME_IC_BASE_CNTL__EXE_DISABLE_MASK 0x00800000L |
36992 | #define CP_ME_IC_BASE_CNTL__CACHE_POLICY_MASK 0x03000000L |
36993 | //CP_ME_IC_OP_CNTL |
36994 | #define CP_ME_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT 0x0 |
36995 | #define CP_ME_IC_OP_CNTL__INVALIDATE_CACHE_COMPLETE__SHIFT 0x1 |
36996 | #define CP_ME_IC_OP_CNTL__PRIME_ICACHE__SHIFT 0x4 |
36997 | #define CP_ME_IC_OP_CNTL__ICACHE_PRIMED__SHIFT 0x5 |
36998 | #define CP_ME_IC_OP_CNTL__INVALIDATE_CACHE_MASK 0x00000001L |
36999 | #define CP_ME_IC_OP_CNTL__INVALIDATE_CACHE_COMPLETE_MASK 0x00000002L |
37000 | #define CP_ME_IC_OP_CNTL__PRIME_ICACHE_MASK 0x00000010L |
37001 | #define CP_ME_IC_OP_CNTL__ICACHE_PRIMED_MASK 0x00000020L |
37002 | //CP_CPC_IC_BASE_LO |
37003 | #define CP_CPC_IC_BASE_LO__IC_BASE_LO__SHIFT 0xc |
37004 | #define CP_CPC_IC_BASE_LO__IC_BASE_LO_MASK 0xFFFFF000L |
37005 | //CP_CPC_IC_BASE_HI |
37006 | #define CP_CPC_IC_BASE_HI__IC_BASE_HI__SHIFT 0x0 |
37007 | #define CP_CPC_IC_BASE_HI__IC_BASE_HI_MASK 0x0000FFFFL |
37008 | //CP_CPC_IC_BASE_CNTL |
37009 | #define CP_CPC_IC_BASE_CNTL__VMID__SHIFT 0x0 |
37010 | #define CP_CPC_IC_BASE_CNTL__ADDRESS_CLAMP__SHIFT 0x4 |
37011 | #define CP_CPC_IC_BASE_CNTL__EXE_DISABLE__SHIFT 0x17 |
37012 | #define CP_CPC_IC_BASE_CNTL__CACHE_POLICY__SHIFT 0x18 |
37013 | #define CP_CPC_IC_BASE_CNTL__VMID_MASK 0x0000000FL |
37014 | #define CP_CPC_IC_BASE_CNTL__ADDRESS_CLAMP_MASK 0x00000010L |
37015 | #define CP_CPC_IC_BASE_CNTL__EXE_DISABLE_MASK 0x00800000L |
37016 | #define CP_CPC_IC_BASE_CNTL__CACHE_POLICY_MASK 0x03000000L |
37017 | //CP_MES_IC_BASE_LO |
37018 | #define CP_MES_IC_BASE_LO__IC_BASE_LO__SHIFT 0xc |
37019 | #define CP_MES_IC_BASE_LO__IC_BASE_LO_MASK 0xFFFFF000L |
37020 | //CP_MES_MIBASE_LO |
37021 | #define CP_MES_MIBASE_LO__IC_BASE_LO__SHIFT 0xc |
37022 | #define CP_MES_MIBASE_LO__IC_BASE_LO_MASK 0xFFFFF000L |
37023 | //CP_MES_IC_BASE_HI |
37024 | #define CP_MES_IC_BASE_HI__IC_BASE_HI__SHIFT 0x0 |
37025 | #define CP_MES_IC_BASE_HI__IC_BASE_HI_MASK 0x0000FFFFL |
37026 | //CP_MES_MIBASE_HI |
37027 | #define CP_MES_MIBASE_HI__IC_BASE_HI__SHIFT 0x0 |
37028 | #define CP_MES_MIBASE_HI__IC_BASE_HI_MASK 0x0000FFFFL |
37029 | //CP_MES_IC_BASE_CNTL |
37030 | #define CP_MES_IC_BASE_CNTL__VMID__SHIFT 0x0 |
37031 | #define CP_MES_IC_BASE_CNTL__EXE_DISABLE__SHIFT 0x17 |
37032 | #define CP_MES_IC_BASE_CNTL__CACHE_POLICY__SHIFT 0x18 |
37033 | #define CP_MES_IC_BASE_CNTL__VMID_MASK 0x0000000FL |
37034 | #define CP_MES_IC_BASE_CNTL__EXE_DISABLE_MASK 0x00800000L |
37035 | #define CP_MES_IC_BASE_CNTL__CACHE_POLICY_MASK 0x03000000L |
37036 | //CP_MES_DC_BASE_LO |
37037 | #define CP_MES_DC_BASE_LO__DC_BASE_LO__SHIFT 0x10 |
37038 | #define CP_MES_DC_BASE_LO__DC_BASE_LO_MASK 0xFFFF0000L |
37039 | //CP_MES_MDBASE_LO |
37040 | #define CP_MES_MDBASE_LO__BASE_LO__SHIFT 0x10 |
37041 | #define CP_MES_MDBASE_LO__BASE_LO_MASK 0xFFFF0000L |
37042 | //CP_MES_DC_BASE_HI |
37043 | #define CP_MES_DC_BASE_HI__DC_BASE_HI__SHIFT 0x0 |
37044 | #define CP_MES_DC_BASE_HI__DC_BASE_HI_MASK 0x0000FFFFL |
37045 | //CP_MES_MDBASE_HI |
37046 | #define CP_MES_MDBASE_HI__BASE_HI__SHIFT 0x0 |
37047 | #define CP_MES_MDBASE_HI__BASE_HI_MASK 0x0000FFFFL |
37048 | //CP_MES_MIBOUND_LO |
37049 | #define CP_MES_MIBOUND_LO__BOUND_LO__SHIFT 0x0 |
37050 | #define CP_MES_MIBOUND_LO__BOUND_LO_MASK 0xFFFFFFFFL |
37051 | //CP_MES_MIBOUND_HI |
37052 | #define CP_MES_MIBOUND_HI__BOUND_HI__SHIFT 0x0 |
37053 | #define CP_MES_MIBOUND_HI__BOUND_HI_MASK 0xFFFFFFFFL |
37054 | //CP_MES_MDBOUND_LO |
37055 | #define CP_MES_MDBOUND_LO__BOUND_LO__SHIFT 0x0 |
37056 | #define CP_MES_MDBOUND_LO__BOUND_LO_MASK 0xFFFFFFFFL |
37057 | //CP_MES_MDBOUND_HI |
37058 | #define CP_MES_MDBOUND_HI__BOUND_HI__SHIFT 0x0 |
37059 | #define CP_MES_MDBOUND_HI__BOUND_HI_MASK 0xFFFFFFFFL |
37060 | //CP_GFX_RS64_DC_BASE0_LO |
37061 | #define CP_GFX_RS64_DC_BASE0_LO__DC_BASE_LO__SHIFT 0x10 |
37062 | #define CP_GFX_RS64_DC_BASE0_LO__DC_BASE_LO_MASK 0xFFFF0000L |
37063 | //CP_GFX_RS64_DC_BASE1_LO |
37064 | #define CP_GFX_RS64_DC_BASE1_LO__DC_BASE_LO__SHIFT 0x10 |
37065 | #define CP_GFX_RS64_DC_BASE1_LO__DC_BASE_LO_MASK 0xFFFF0000L |
37066 | //CP_GFX_RS64_DC_BASE0_HI |
37067 | #define CP_GFX_RS64_DC_BASE0_HI__DC_BASE_HI__SHIFT 0x0 |
37068 | #define CP_GFX_RS64_DC_BASE0_HI__DC_BASE_HI_MASK 0x0000FFFFL |
37069 | //CP_GFX_RS64_DC_BASE1_HI |
37070 | #define CP_GFX_RS64_DC_BASE1_HI__DC_BASE_HI__SHIFT 0x0 |
37071 | #define CP_GFX_RS64_DC_BASE1_HI__DC_BASE_HI_MASK 0x0000FFFFL |
37072 | //CP_GFX_RS64_MIBOUND_LO |
37073 | #define CP_GFX_RS64_MIBOUND_LO__BOUND__SHIFT 0x0 |
37074 | #define CP_GFX_RS64_MIBOUND_LO__BOUND_MASK 0xFFFFFFFFL |
37075 | //CP_GFX_RS64_MIBOUND_HI |
37076 | #define CP_GFX_RS64_MIBOUND_HI__BOUND__SHIFT 0x0 |
37077 | #define CP_GFX_RS64_MIBOUND_HI__BOUND_MASK 0xFFFFFFFFL |
37078 | //CP_MEC_DC_BASE_LO |
37079 | #define CP_MEC_DC_BASE_LO__DC_BASE_LO__SHIFT 0x10 |
37080 | #define CP_MEC_DC_BASE_LO__DC_BASE_LO_MASK 0xFFFF0000L |
37081 | //CP_MEC_MDBASE_LO |
37082 | #define CP_MEC_MDBASE_LO__BASE_LO__SHIFT 0x10 |
37083 | #define CP_MEC_MDBASE_LO__BASE_LO_MASK 0xFFFF0000L |
37084 | //CP_MEC_DC_BASE_HI |
37085 | #define CP_MEC_DC_BASE_HI__DC_BASE_HI__SHIFT 0x0 |
37086 | #define CP_MEC_DC_BASE_HI__DC_BASE_HI_MASK 0x0000FFFFL |
37087 | //CP_MEC_MDBASE_HI |
37088 | #define CP_MEC_MDBASE_HI__BASE_HI__SHIFT 0x0 |
37089 | #define CP_MEC_MDBASE_HI__BASE_HI_MASK 0x0000FFFFL |
37090 | //CP_MEC_MIBOUND_LO |
37091 | #define CP_MEC_MIBOUND_LO__BOUND_LO__SHIFT 0x0 |
37092 | #define CP_MEC_MIBOUND_LO__BOUND_LO_MASK 0xFFFFFFFFL |
37093 | //CP_MEC_MIBOUND_HI |
37094 | #define CP_MEC_MIBOUND_HI__BOUND_HI__SHIFT 0x0 |
37095 | #define CP_MEC_MIBOUND_HI__BOUND_HI_MASK 0xFFFFFFFFL |
37096 | //CP_MEC_MDBOUND_LO |
37097 | #define CP_MEC_MDBOUND_LO__BOUND_LO__SHIFT 0x0 |
37098 | #define CP_MEC_MDBOUND_LO__BOUND_LO_MASK 0xFFFFFFFFL |
37099 | //CP_MEC_MDBOUND_HI |
37100 | #define CP_MEC_MDBOUND_HI__BOUND_HI__SHIFT 0x0 |
37101 | #define CP_MEC_MDBOUND_HI__BOUND_HI_MASK 0xFFFFFFFFL |
37102 | |
37103 | |
37104 | // addressBlock: gc_grbm_hypdec |
37105 | //GRBM_GFX_INDEX_SR_SELECT |
37106 | #define GRBM_GFX_INDEX_SR_SELECT__INDEX__SHIFT 0x0 |
37107 | #define GRBM_GFX_INDEX_SR_SELECT__VF_PF__SHIFT 0x1f |
37108 | #define GRBM_GFX_INDEX_SR_SELECT__INDEX_MASK 0x00000007L |
37109 | #define GRBM_GFX_INDEX_SR_SELECT__VF_PF_MASK 0x80000000L |
37110 | //GRBM_GFX_INDEX_SR_DATA |
37111 | #define GRBM_GFX_INDEX_SR_DATA__INSTANCE_INDEX__SHIFT 0x0 |
37112 | #define GRBM_GFX_INDEX_SR_DATA__SA_INDEX__SHIFT 0x8 |
37113 | #define GRBM_GFX_INDEX_SR_DATA__SE_INDEX__SHIFT 0x10 |
37114 | #define GRBM_GFX_INDEX_SR_DATA__SA_BROADCAST_WRITES__SHIFT 0x1d |
37115 | #define GRBM_GFX_INDEX_SR_DATA__INSTANCE_BROADCAST_WRITES__SHIFT 0x1e |
37116 | #define GRBM_GFX_INDEX_SR_DATA__SE_BROADCAST_WRITES__SHIFT 0x1f |
37117 | #define GRBM_GFX_INDEX_SR_DATA__INSTANCE_INDEX_MASK 0x000000FFL |
37118 | #define GRBM_GFX_INDEX_SR_DATA__SA_INDEX_MASK 0x0000FF00L |
37119 | #define GRBM_GFX_INDEX_SR_DATA__SE_INDEX_MASK 0x00FF0000L |
37120 | #define GRBM_GFX_INDEX_SR_DATA__SA_BROADCAST_WRITES_MASK 0x20000000L |
37121 | #define GRBM_GFX_INDEX_SR_DATA__INSTANCE_BROADCAST_WRITES_MASK 0x40000000L |
37122 | #define GRBM_GFX_INDEX_SR_DATA__SE_BROADCAST_WRITES_MASK 0x80000000L |
37123 | //GRBM_GFX_CNTL_SR_SELECT |
37124 | #define GRBM_GFX_CNTL_SR_SELECT__INDEX__SHIFT 0x0 |
37125 | #define GRBM_GFX_CNTL_SR_SELECT__VF_PF__SHIFT 0x1f |
37126 | #define GRBM_GFX_CNTL_SR_SELECT__INDEX_MASK 0x00000007L |
37127 | #define GRBM_GFX_CNTL_SR_SELECT__VF_PF_MASK 0x80000000L |
37128 | //GRBM_GFX_CNTL_SR_DATA |
37129 | #define GRBM_GFX_CNTL_SR_DATA__PIPEID__SHIFT 0x0 |
37130 | #define GRBM_GFX_CNTL_SR_DATA__MEID__SHIFT 0x2 |
37131 | #define GRBM_GFX_CNTL_SR_DATA__VMID__SHIFT 0x4 |
37132 | #define GRBM_GFX_CNTL_SR_DATA__QUEUEID__SHIFT 0x8 |
37133 | #define GRBM_GFX_CNTL_SR_DATA__PIPEID_MASK 0x00000003L |
37134 | #define GRBM_GFX_CNTL_SR_DATA__MEID_MASK 0x0000000CL |
37135 | #define GRBM_GFX_CNTL_SR_DATA__VMID_MASK 0x000000F0L |
37136 | #define GRBM_GFX_CNTL_SR_DATA__QUEUEID_MASK 0x00000700L |
37137 | //GC_IH_COOKIE_0_PTR |
37138 | #define GC_IH_COOKIE_0_PTR__ADDR__SHIFT 0x0 |
37139 | #define GC_IH_COOKIE_0_PTR__ADDR_MASK 0x000FFFFFL |
37140 | //GRBM_SE_REMAP_CNTL |
37141 | #define GRBM_SE_REMAP_CNTL__SE0_REMAP_EN__SHIFT 0x0 |
37142 | #define GRBM_SE_REMAP_CNTL__SE0_REMAP__SHIFT 0x1 |
37143 | #define GRBM_SE_REMAP_CNTL__SE1_REMAP_EN__SHIFT 0x4 |
37144 | #define GRBM_SE_REMAP_CNTL__SE1_REMAP__SHIFT 0x5 |
37145 | #define GRBM_SE_REMAP_CNTL__SE2_REMAP_EN__SHIFT 0x8 |
37146 | #define GRBM_SE_REMAP_CNTL__SE2_REMAP__SHIFT 0x9 |
37147 | #define GRBM_SE_REMAP_CNTL__SE3_REMAP_EN__SHIFT 0xc |
37148 | #define GRBM_SE_REMAP_CNTL__SE3_REMAP__SHIFT 0xd |
37149 | #define GRBM_SE_REMAP_CNTL__SE4_REMAP_EN__SHIFT 0x10 |
37150 | #define GRBM_SE_REMAP_CNTL__SE4_REMAP__SHIFT 0x11 |
37151 | #define GRBM_SE_REMAP_CNTL__SE5_REMAP_EN__SHIFT 0x14 |
37152 | #define GRBM_SE_REMAP_CNTL__SE5_REMAP__SHIFT 0x15 |
37153 | #define GRBM_SE_REMAP_CNTL__SE6_REMAP_EN__SHIFT 0x18 |
37154 | #define GRBM_SE_REMAP_CNTL__SE6_REMAP__SHIFT 0x19 |
37155 | #define GRBM_SE_REMAP_CNTL__SE7_REMAP_EN__SHIFT 0x1c |
37156 | #define GRBM_SE_REMAP_CNTL__SE7_REMAP__SHIFT 0x1d |
37157 | #define GRBM_SE_REMAP_CNTL__SE0_REMAP_EN_MASK 0x00000001L |
37158 | #define GRBM_SE_REMAP_CNTL__SE0_REMAP_MASK 0x0000000EL |
37159 | #define GRBM_SE_REMAP_CNTL__SE1_REMAP_EN_MASK 0x00000010L |
37160 | #define GRBM_SE_REMAP_CNTL__SE1_REMAP_MASK 0x000000E0L |
37161 | #define GRBM_SE_REMAP_CNTL__SE2_REMAP_EN_MASK 0x00000100L |
37162 | #define GRBM_SE_REMAP_CNTL__SE2_REMAP_MASK 0x00000E00L |
37163 | #define GRBM_SE_REMAP_CNTL__SE3_REMAP_EN_MASK 0x00001000L |
37164 | #define GRBM_SE_REMAP_CNTL__SE3_REMAP_MASK 0x0000E000L |
37165 | #define GRBM_SE_REMAP_CNTL__SE4_REMAP_EN_MASK 0x00010000L |
37166 | #define GRBM_SE_REMAP_CNTL__SE4_REMAP_MASK 0x000E0000L |
37167 | #define GRBM_SE_REMAP_CNTL__SE5_REMAP_EN_MASK 0x00100000L |
37168 | #define GRBM_SE_REMAP_CNTL__SE5_REMAP_MASK 0x00E00000L |
37169 | #define GRBM_SE_REMAP_CNTL__SE6_REMAP_EN_MASK 0x01000000L |
37170 | #define GRBM_SE_REMAP_CNTL__SE6_REMAP_MASK 0x0E000000L |
37171 | #define GRBM_SE_REMAP_CNTL__SE7_REMAP_EN_MASK 0x10000000L |
37172 | #define GRBM_SE_REMAP_CNTL__SE7_REMAP_MASK 0xE0000000L |
37173 | |
37174 | |
37175 | // addressBlock: gc_gcvmsharedhvdec |
37176 | //GCMC_VM_FB_SIZE_OFFSET_VF0 |
37177 | #define GCMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE__SHIFT 0x0 |
37178 | #define GCMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET__SHIFT 0x10 |
37179 | #define GCMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE_MASK 0x0000FFFFL |
37180 | #define GCMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET_MASK 0xFFFF0000L |
37181 | //GCMC_VM_FB_SIZE_OFFSET_VF1 |
37182 | #define GCMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE__SHIFT 0x0 |
37183 | #define GCMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET__SHIFT 0x10 |
37184 | #define GCMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE_MASK 0x0000FFFFL |
37185 | #define GCMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET_MASK 0xFFFF0000L |
37186 | //GCMC_VM_FB_SIZE_OFFSET_VF2 |
37187 | #define GCMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE__SHIFT 0x0 |
37188 | #define GCMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET__SHIFT 0x10 |
37189 | #define GCMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE_MASK 0x0000FFFFL |
37190 | #define GCMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET_MASK 0xFFFF0000L |
37191 | //GCMC_VM_FB_SIZE_OFFSET_VF3 |
37192 | #define GCMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE__SHIFT 0x0 |
37193 | #define GCMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET__SHIFT 0x10 |
37194 | #define GCMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE_MASK 0x0000FFFFL |
37195 | #define GCMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET_MASK 0xFFFF0000L |
37196 | //GCMC_VM_FB_SIZE_OFFSET_VF4 |
37197 | #define GCMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE__SHIFT 0x0 |
37198 | #define GCMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET__SHIFT 0x10 |
37199 | #define GCMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE_MASK 0x0000FFFFL |
37200 | #define GCMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET_MASK 0xFFFF0000L |
37201 | //GCMC_VM_FB_SIZE_OFFSET_VF5 |
37202 | #define GCMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE__SHIFT 0x0 |
37203 | #define GCMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET__SHIFT 0x10 |
37204 | #define GCMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE_MASK 0x0000FFFFL |
37205 | #define GCMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET_MASK 0xFFFF0000L |
37206 | //GCMC_VM_FB_SIZE_OFFSET_VF6 |
37207 | #define GCMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE__SHIFT 0x0 |
37208 | #define GCMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET__SHIFT 0x10 |
37209 | #define GCMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE_MASK 0x0000FFFFL |
37210 | #define GCMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET_MASK 0xFFFF0000L |
37211 | //GCMC_VM_FB_SIZE_OFFSET_VF7 |
37212 | #define GCMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE__SHIFT 0x0 |
37213 | #define GCMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET__SHIFT 0x10 |
37214 | #define GCMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE_MASK 0x0000FFFFL |
37215 | #define GCMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET_MASK 0xFFFF0000L |
37216 | //GCMC_VM_FB_SIZE_OFFSET_VF8 |
37217 | #define GCMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE__SHIFT 0x0 |
37218 | #define GCMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET__SHIFT 0x10 |
37219 | #define GCMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE_MASK 0x0000FFFFL |
37220 | #define GCMC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET_MASK 0xFFFF0000L |
37221 | //GCMC_VM_FB_SIZE_OFFSET_VF9 |
37222 | #define GCMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE__SHIFT 0x0 |
37223 | #define GCMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET__SHIFT 0x10 |
37224 | #define GCMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE_MASK 0x0000FFFFL |
37225 | #define GCMC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET_MASK 0xFFFF0000L |
37226 | //GCMC_VM_FB_SIZE_OFFSET_VF10 |
37227 | #define GCMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE__SHIFT 0x0 |
37228 | #define GCMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET__SHIFT 0x10 |
37229 | #define GCMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE_MASK 0x0000FFFFL |
37230 | #define GCMC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET_MASK 0xFFFF0000L |
37231 | //GCMC_VM_FB_SIZE_OFFSET_VF11 |
37232 | #define GCMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE__SHIFT 0x0 |
37233 | #define GCMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET__SHIFT 0x10 |
37234 | #define GCMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE_MASK 0x0000FFFFL |
37235 | #define GCMC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET_MASK 0xFFFF0000L |
37236 | //GCMC_VM_FB_SIZE_OFFSET_VF12 |
37237 | #define GCMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE__SHIFT 0x0 |
37238 | #define GCMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET__SHIFT 0x10 |
37239 | #define GCMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE_MASK 0x0000FFFFL |
37240 | #define GCMC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET_MASK 0xFFFF0000L |
37241 | //GCMC_VM_FB_SIZE_OFFSET_VF13 |
37242 | #define GCMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE__SHIFT 0x0 |
37243 | #define GCMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET__SHIFT 0x10 |
37244 | #define GCMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE_MASK 0x0000FFFFL |
37245 | #define GCMC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET_MASK 0xFFFF0000L |
37246 | //GCMC_VM_FB_SIZE_OFFSET_VF14 |
37247 | #define GCMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE__SHIFT 0x0 |
37248 | #define GCMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET__SHIFT 0x10 |
37249 | #define GCMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE_MASK 0x0000FFFFL |
37250 | #define GCMC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET_MASK 0xFFFF0000L |
37251 | //GCMC_VM_FB_SIZE_OFFSET_VF15 |
37252 | #define GCMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE__SHIFT 0x0 |
37253 | #define GCMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET__SHIFT 0x10 |
37254 | #define GCMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE_MASK 0x0000FFFFL |
37255 | #define GCMC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET_MASK 0xFFFF0000L |
37256 | |
37257 | |
37258 | // addressBlock: gc_rlcdec |
37259 | //RLC_CNTL |
37260 | #define RLC_CNTL__RLC_ENABLE_F32__SHIFT 0x0 |
37261 | #define RLC_CNTL__FORCE_RETRY__SHIFT 0x1 |
37262 | #define RLC_CNTL__READ_CACHE_DISABLE__SHIFT 0x2 |
37263 | #define RLC_CNTL__RLC_STEP_F32__SHIFT 0x3 |
37264 | #define RLC_CNTL__RESERVED__SHIFT 0x4 |
37265 | #define RLC_CNTL__RLC_ENABLE_F32_MASK 0x00000001L |
37266 | #define RLC_CNTL__FORCE_RETRY_MASK 0x00000002L |
37267 | #define RLC_CNTL__READ_CACHE_DISABLE_MASK 0x00000004L |
37268 | #define RLC_CNTL__RLC_STEP_F32_MASK 0x00000008L |
37269 | #define RLC_CNTL__RESERVED_MASK 0xFFFFFFF0L |
37270 | //RLC_F32_UCODE_VERSION |
37271 | #define RLC_F32_UCODE_VERSION__THREAD0_VERSION__SHIFT 0x0 |
37272 | #define RLC_F32_UCODE_VERSION__THREAD1_VERSION__SHIFT 0xa |
37273 | #define RLC_F32_UCODE_VERSION__THREAD2_VERSION__SHIFT 0x14 |
37274 | #define RLC_F32_UCODE_VERSION__THREAD0_VERSION_MASK 0x000003FFL |
37275 | #define RLC_F32_UCODE_VERSION__THREAD1_VERSION_MASK 0x000FFC00L |
37276 | #define RLC_F32_UCODE_VERSION__THREAD2_VERSION_MASK 0x3FF00000L |
37277 | //RLC_STAT |
37278 | #define RLC_STAT__RLC_BUSY__SHIFT 0x0 |
37279 | #define RLC_STAT__RLC_SRM_BUSY__SHIFT 0x1 |
37280 | #define RLC_STAT__RLC_GPM_BUSY__SHIFT 0x2 |
37281 | #define RLC_STAT__RLC_SPM_BUSY__SHIFT 0x3 |
37282 | #define RLC_STAT__MC_BUSY__SHIFT 0x4 |
37283 | #define RLC_STAT__RLC_THREAD_0_BUSY__SHIFT 0x5 |
37284 | #define RLC_STAT__RLC_THREAD_1_BUSY__SHIFT 0x6 |
37285 | #define RLC_STAT__RLC_THREAD_2_BUSY__SHIFT 0x7 |
37286 | #define RLC_STAT__RESERVED__SHIFT 0x8 |
37287 | #define RLC_STAT__RLC_BUSY_MASK 0x00000001L |
37288 | #define RLC_STAT__RLC_SRM_BUSY_MASK 0x00000002L |
37289 | #define RLC_STAT__RLC_GPM_BUSY_MASK 0x00000004L |
37290 | #define RLC_STAT__RLC_SPM_BUSY_MASK 0x00000008L |
37291 | #define RLC_STAT__MC_BUSY_MASK 0x00000010L |
37292 | #define RLC_STAT__RLC_THREAD_0_BUSY_MASK 0x00000020L |
37293 | #define RLC_STAT__RLC_THREAD_1_BUSY_MASK 0x00000040L |
37294 | #define RLC_STAT__RLC_THREAD_2_BUSY_MASK 0x00000080L |
37295 | #define RLC_STAT__RESERVED_MASK 0xFFFFFF00L |
37296 | //RLC_REFCLOCK_TIMESTAMP_LSB |
37297 | #define RLC_REFCLOCK_TIMESTAMP_LSB__TIMESTAMP_LSB__SHIFT 0x0 |
37298 | #define RLC_REFCLOCK_TIMESTAMP_LSB__TIMESTAMP_LSB_MASK 0xFFFFFFFFL |
37299 | //RLC_REFCLOCK_TIMESTAMP_MSB |
37300 | #define RLC_REFCLOCK_TIMESTAMP_MSB__TIMESTAMP_MSB__SHIFT 0x0 |
37301 | #define RLC_REFCLOCK_TIMESTAMP_MSB__TIMESTAMP_MSB_MASK 0xFFFFFFFFL |
37302 | //RLC_GPM_TIMER_INT_0 |
37303 | #define RLC_GPM_TIMER_INT_0__TIMER__SHIFT 0x0 |
37304 | #define RLC_GPM_TIMER_INT_0__TIMER_MASK 0xFFFFFFFFL |
37305 | //RLC_GPM_TIMER_INT_1 |
37306 | #define RLC_GPM_TIMER_INT_1__TIMER__SHIFT 0x0 |
37307 | #define RLC_GPM_TIMER_INT_1__TIMER_MASK 0xFFFFFFFFL |
37308 | //RLC_GPM_TIMER_INT_2 |
37309 | #define RLC_GPM_TIMER_INT_2__TIMER__SHIFT 0x0 |
37310 | #define RLC_GPM_TIMER_INT_2__TIMER_MASK 0xFFFFFFFFL |
37311 | //RLC_GPM_TIMER_INT_3 |
37312 | #define RLC_GPM_TIMER_INT_3__TIMER__SHIFT 0x0 |
37313 | #define RLC_GPM_TIMER_INT_3__TIMER_MASK 0xFFFFFFFFL |
37314 | //RLC_GPM_TIMER_INT_4 |
37315 | #define RLC_GPM_TIMER_INT_4__TIMER__SHIFT 0x0 |
37316 | #define RLC_GPM_TIMER_INT_4__TIMER_MASK 0xFFFFFFFFL |
37317 | //RLC_GPM_TIMER_CTRL |
37318 | #define RLC_GPM_TIMER_CTRL__TIMER_0_EN__SHIFT 0x0 |
37319 | #define RLC_GPM_TIMER_CTRL__TIMER_1_EN__SHIFT 0x1 |
37320 | #define RLC_GPM_TIMER_CTRL__TIMER_2_EN__SHIFT 0x2 |
37321 | #define RLC_GPM_TIMER_CTRL__TIMER_3_EN__SHIFT 0x3 |
37322 | #define RLC_GPM_TIMER_CTRL__TIMER_4_EN__SHIFT 0x4 |
37323 | #define RLC_GPM_TIMER_CTRL__RESERVED_1__SHIFT 0x5 |
37324 | #define RLC_GPM_TIMER_CTRL__TIMER_0_AUTO_REARM__SHIFT 0x8 |
37325 | #define RLC_GPM_TIMER_CTRL__TIMER_1_AUTO_REARM__SHIFT 0x9 |
37326 | #define RLC_GPM_TIMER_CTRL__TIMER_2_AUTO_REARM__SHIFT 0xa |
37327 | #define RLC_GPM_TIMER_CTRL__TIMER_3_AUTO_REARM__SHIFT 0xb |
37328 | #define RLC_GPM_TIMER_CTRL__TIMER_4_AUTO_REARM__SHIFT 0xc |
37329 | #define RLC_GPM_TIMER_CTRL__RESERVED_2__SHIFT 0xd |
37330 | #define RLC_GPM_TIMER_CTRL__TIMER_0_INT_CLEAR__SHIFT 0x10 |
37331 | #define RLC_GPM_TIMER_CTRL__TIMER_1_INT_CLEAR__SHIFT 0x11 |
37332 | #define RLC_GPM_TIMER_CTRL__TIMER_2_INT_CLEAR__SHIFT 0x12 |
37333 | #define RLC_GPM_TIMER_CTRL__TIMER_3_INT_CLEAR__SHIFT 0x13 |
37334 | #define RLC_GPM_TIMER_CTRL__TIMER_4_INT_CLEAR__SHIFT 0x14 |
37335 | #define RLC_GPM_TIMER_CTRL__RESERVED__SHIFT 0x15 |
37336 | #define RLC_GPM_TIMER_CTRL__TIMER_0_EN_MASK 0x00000001L |
37337 | #define RLC_GPM_TIMER_CTRL__TIMER_1_EN_MASK 0x00000002L |
37338 | #define RLC_GPM_TIMER_CTRL__TIMER_2_EN_MASK 0x00000004L |
37339 | #define RLC_GPM_TIMER_CTRL__TIMER_3_EN_MASK 0x00000008L |
37340 | #define RLC_GPM_TIMER_CTRL__TIMER_4_EN_MASK 0x00000010L |
37341 | #define RLC_GPM_TIMER_CTRL__RESERVED_1_MASK 0x000000E0L |
37342 | #define RLC_GPM_TIMER_CTRL__TIMER_0_AUTO_REARM_MASK 0x00000100L |
37343 | #define RLC_GPM_TIMER_CTRL__TIMER_1_AUTO_REARM_MASK 0x00000200L |
37344 | #define RLC_GPM_TIMER_CTRL__TIMER_2_AUTO_REARM_MASK 0x00000400L |
37345 | #define RLC_GPM_TIMER_CTRL__TIMER_3_AUTO_REARM_MASK 0x00000800L |
37346 | #define RLC_GPM_TIMER_CTRL__TIMER_4_AUTO_REARM_MASK 0x00001000L |
37347 | #define RLC_GPM_TIMER_CTRL__RESERVED_2_MASK 0x0000E000L |
37348 | #define RLC_GPM_TIMER_CTRL__TIMER_0_INT_CLEAR_MASK 0x00010000L |
37349 | #define RLC_GPM_TIMER_CTRL__TIMER_1_INT_CLEAR_MASK 0x00020000L |
37350 | #define RLC_GPM_TIMER_CTRL__TIMER_2_INT_CLEAR_MASK 0x00040000L |
37351 | #define RLC_GPM_TIMER_CTRL__TIMER_3_INT_CLEAR_MASK 0x00080000L |
37352 | #define RLC_GPM_TIMER_CTRL__TIMER_4_INT_CLEAR_MASK 0x00100000L |
37353 | #define RLC_GPM_TIMER_CTRL__RESERVED_MASK 0xFFE00000L |
37354 | //RLC_GPM_TIMER_STAT |
37355 | #define RLC_GPM_TIMER_STAT__TIMER_0_STAT__SHIFT 0x0 |
37356 | #define RLC_GPM_TIMER_STAT__TIMER_1_STAT__SHIFT 0x1 |
37357 | #define RLC_GPM_TIMER_STAT__TIMER_2_STAT__SHIFT 0x2 |
37358 | #define RLC_GPM_TIMER_STAT__TIMER_3_STAT__SHIFT 0x3 |
37359 | #define RLC_GPM_TIMER_STAT__TIMER_4_STAT__SHIFT 0x4 |
37360 | #define RLC_GPM_TIMER_STAT__RESERVED_1__SHIFT 0x5 |
37361 | #define RLC_GPM_TIMER_STAT__TIMER_0_ENABLE_SYNC__SHIFT 0x8 |
37362 | #define RLC_GPM_TIMER_STAT__TIMER_1_ENABLE_SYNC__SHIFT 0x9 |
37363 | #define RLC_GPM_TIMER_STAT__TIMER_2_ENABLE_SYNC__SHIFT 0xa |
37364 | #define RLC_GPM_TIMER_STAT__TIMER_3_ENABLE_SYNC__SHIFT 0xb |
37365 | #define RLC_GPM_TIMER_STAT__TIMER_4_ENABLE_SYNC__SHIFT 0xc |
37366 | #define RLC_GPM_TIMER_STAT__RESERVED_2__SHIFT 0xd |
37367 | #define RLC_GPM_TIMER_STAT__TIMER_0_AUTO_REARM_SYNC__SHIFT 0x10 |
37368 | #define RLC_GPM_TIMER_STAT__TIMER_1_AUTO_REARM_SYNC__SHIFT 0x11 |
37369 | #define RLC_GPM_TIMER_STAT__TIMER_2_AUTO_REARM_SYNC__SHIFT 0x12 |
37370 | #define RLC_GPM_TIMER_STAT__TIMER_3_AUTO_REARM_SYNC__SHIFT 0x13 |
37371 | #define RLC_GPM_TIMER_STAT__TIMER_4_AUTO_REARM_SYNC__SHIFT 0x14 |
37372 | #define RLC_GPM_TIMER_STAT__RESERVED__SHIFT 0x15 |
37373 | #define RLC_GPM_TIMER_STAT__TIMER_0_STAT_MASK 0x00000001L |
37374 | #define RLC_GPM_TIMER_STAT__TIMER_1_STAT_MASK 0x00000002L |
37375 | #define RLC_GPM_TIMER_STAT__TIMER_2_STAT_MASK 0x00000004L |
37376 | #define RLC_GPM_TIMER_STAT__TIMER_3_STAT_MASK 0x00000008L |
37377 | #define RLC_GPM_TIMER_STAT__TIMER_4_STAT_MASK 0x00000010L |
37378 | #define RLC_GPM_TIMER_STAT__RESERVED_1_MASK 0x000000E0L |
37379 | #define RLC_GPM_TIMER_STAT__TIMER_0_ENABLE_SYNC_MASK 0x00000100L |
37380 | #define RLC_GPM_TIMER_STAT__TIMER_1_ENABLE_SYNC_MASK 0x00000200L |
37381 | #define RLC_GPM_TIMER_STAT__TIMER_2_ENABLE_SYNC_MASK 0x00000400L |
37382 | #define RLC_GPM_TIMER_STAT__TIMER_3_ENABLE_SYNC_MASK 0x00000800L |
37383 | #define RLC_GPM_TIMER_STAT__TIMER_4_ENABLE_SYNC_MASK 0x00001000L |
37384 | #define RLC_GPM_TIMER_STAT__RESERVED_2_MASK 0x0000E000L |
37385 | #define RLC_GPM_TIMER_STAT__TIMER_0_AUTO_REARM_SYNC_MASK 0x00010000L |
37386 | #define RLC_GPM_TIMER_STAT__TIMER_1_AUTO_REARM_SYNC_MASK 0x00020000L |
37387 | #define RLC_GPM_TIMER_STAT__TIMER_2_AUTO_REARM_SYNC_MASK 0x00040000L |
37388 | #define RLC_GPM_TIMER_STAT__TIMER_3_AUTO_REARM_SYNC_MASK 0x00080000L |
37389 | #define RLC_GPM_TIMER_STAT__TIMER_4_AUTO_REARM_SYNC_MASK 0x00100000L |
37390 | #define RLC_GPM_TIMER_STAT__RESERVED_MASK 0xFFE00000L |
37391 | //RLC_GPM_LEGACY_INT_STAT |
37392 | #define RLC_GPM_LEGACY_INT_STAT__SPP_PVT_INT_CHANGED__SHIFT 0x0 |
37393 | #define RLC_GPM_LEGACY_INT_STAT__CP_RLC_STAT_INVAL_PEND_CHANGED__SHIFT 0x1 |
37394 | #define RLC_GPM_LEGACY_INT_STAT__RLC_EOF_INT_CHANGED__SHIFT 0x2 |
37395 | #define RLC_GPM_LEGACY_INT_STAT__RLC_PG_CNTL_CHANGED__SHIFT 0x3 |
37396 | #define RLC_GPM_LEGACY_INT_STAT__STORE_LOAD_TIMER3_EXPIRED_T0__SHIFT 0x4 |
37397 | #define RLC_GPM_LEGACY_INT_STAT__SPP_PVT_INT_CHANGED_MASK 0x00000001L |
37398 | #define RLC_GPM_LEGACY_INT_STAT__CP_RLC_STAT_INVAL_PEND_CHANGED_MASK 0x00000002L |
37399 | #define RLC_GPM_LEGACY_INT_STAT__RLC_EOF_INT_CHANGED_MASK 0x00000004L |
37400 | #define RLC_GPM_LEGACY_INT_STAT__RLC_PG_CNTL_CHANGED_MASK 0x00000008L |
37401 | #define RLC_GPM_LEGACY_INT_STAT__STORE_LOAD_TIMER3_EXPIRED_T0_MASK 0x00000010L |
37402 | //RLC_GPM_LEGACY_INT_CLEAR |
37403 | #define RLC_GPM_LEGACY_INT_CLEAR__SPP_PVT_INT_CHANGED__SHIFT 0x0 |
37404 | #define RLC_GPM_LEGACY_INT_CLEAR__CP_RLC_STAT_INVAL_PEND_CHANGED__SHIFT 0x1 |
37405 | #define RLC_GPM_LEGACY_INT_CLEAR__RLC_EOF_INT_CHANGED__SHIFT 0x2 |
37406 | #define RLC_GPM_LEGACY_INT_CLEAR__RLC_PG_CNTL_CHANGED__SHIFT 0x3 |
37407 | #define RLC_GPM_LEGACY_INT_CLEAR__RESERVED_4__SHIFT 0x4 |
37408 | #define RLC_GPM_LEGACY_INT_CLEAR__SPP_PVT_INT_CHANGED_MASK 0x00000001L |
37409 | #define RLC_GPM_LEGACY_INT_CLEAR__CP_RLC_STAT_INVAL_PEND_CHANGED_MASK 0x00000002L |
37410 | #define RLC_GPM_LEGACY_INT_CLEAR__RLC_EOF_INT_CHANGED_MASK 0x00000004L |
37411 | #define RLC_GPM_LEGACY_INT_CLEAR__RLC_PG_CNTL_CHANGED_MASK 0x00000008L |
37412 | #define RLC_GPM_LEGACY_INT_CLEAR__RESERVED_4_MASK 0x00000010L |
37413 | //RLC_INT_STAT |
37414 | #define RLC_INT_STAT__LAST_CP_RLC_INT_ID__SHIFT 0x0 |
37415 | #define RLC_INT_STAT__CP_RLC_INT_PENDING__SHIFT 0x8 |
37416 | #define RLC_INT_STAT__RESERVED__SHIFT 0x9 |
37417 | #define RLC_INT_STAT__LAST_CP_RLC_INT_ID_MASK 0x000000FFL |
37418 | #define RLC_INT_STAT__CP_RLC_INT_PENDING_MASK 0x00000100L |
37419 | #define RLC_INT_STAT__RESERVED_MASK 0xFFFFFE00L |
37420 | //RLC_MGCG_CTRL |
37421 | #define RLC_MGCG_CTRL__MGCG_EN__SHIFT 0x0 |
37422 | #define RLC_MGCG_CTRL__SILICON_EN__SHIFT 0x1 |
37423 | #define RLC_MGCG_CTRL__SIMULATION_EN__SHIFT 0x2 |
37424 | #define RLC_MGCG_CTRL__ON_DELAY__SHIFT 0x3 |
37425 | #define RLC_MGCG_CTRL__OFF_HYSTERESIS__SHIFT 0x7 |
37426 | #define RLC_MGCG_CTRL__SPARE__SHIFT 0xf |
37427 | #define RLC_MGCG_CTRL__MGCG_EN_MASK 0x00000001L |
37428 | #define RLC_MGCG_CTRL__SILICON_EN_MASK 0x00000002L |
37429 | #define RLC_MGCG_CTRL__SIMULATION_EN_MASK 0x00000004L |
37430 | #define RLC_MGCG_CTRL__ON_DELAY_MASK 0x00000078L |
37431 | #define RLC_MGCG_CTRL__OFF_HYSTERESIS_MASK 0x00007F80L |
37432 | #define RLC_MGCG_CTRL__SPARE_MASK 0xFFFF8000L |
37433 | //RLC_JUMP_TABLE_RESTORE |
37434 | #define RLC_JUMP_TABLE_RESTORE__ADDR__SHIFT 0x0 |
37435 | #define RLC_JUMP_TABLE_RESTORE__ADDR_MASK 0xFFFFFFFFL |
37436 | //RLC_PG_DELAY_2 |
37437 | #define RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE__SHIFT 0x0 |
37438 | #define RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT 0x8 |
37439 | #define RLC_PG_DELAY_2__PERWGP_TIMEOUT_VALUE__SHIFT 0x10 |
37440 | #define RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE_MASK 0x000000FFL |
37441 | #define RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK 0x0000FF00L |
37442 | #define RLC_PG_DELAY_2__PERWGP_TIMEOUT_VALUE_MASK 0xFFFF0000L |
37443 | //RLC_GPU_CLOCK_COUNT_LSB |
37444 | #define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB__SHIFT 0x0 |
37445 | #define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB_MASK 0xFFFFFFFFL |
37446 | //RLC_GPU_CLOCK_COUNT_MSB |
37447 | #define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB__SHIFT 0x0 |
37448 | #define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB_MASK 0xFFFFFFFFL |
37449 | //RLC_CAPTURE_GPU_CLOCK_COUNT |
37450 | #define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE__SHIFT 0x0 |
37451 | #define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED__SHIFT 0x1 |
37452 | #define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE_MASK 0x00000001L |
37453 | #define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED_MASK 0xFFFFFFFEL |
37454 | //RLC_UCODE_CNTL |
37455 | #define RLC_UCODE_CNTL__RLC_UCODE_FLAGS__SHIFT 0x0 |
37456 | #define RLC_UCODE_CNTL__RLC_UCODE_FLAGS_MASK 0xFFFFFFFFL |
37457 | //RLC_GPM_THREAD_RESET |
37458 | #define RLC_GPM_THREAD_RESET__THREAD0_RESET__SHIFT 0x0 |
37459 | #define RLC_GPM_THREAD_RESET__THREAD1_RESET__SHIFT 0x1 |
37460 | #define RLC_GPM_THREAD_RESET__THREAD2_RESET__SHIFT 0x2 |
37461 | #define RLC_GPM_THREAD_RESET__THREAD3_RESET__SHIFT 0x3 |
37462 | #define RLC_GPM_THREAD_RESET__RESERVED__SHIFT 0x4 |
37463 | #define RLC_GPM_THREAD_RESET__THREAD0_RESET_MASK 0x00000001L |
37464 | #define RLC_GPM_THREAD_RESET__THREAD1_RESET_MASK 0x00000002L |
37465 | #define RLC_GPM_THREAD_RESET__THREAD2_RESET_MASK 0x00000004L |
37466 | #define RLC_GPM_THREAD_RESET__THREAD3_RESET_MASK 0x00000008L |
37467 | #define RLC_GPM_THREAD_RESET__RESERVED_MASK 0xFFFFFFF0L |
37468 | //RLC_GPM_CP_DMA_COMPLETE_T0 |
37469 | #define RLC_GPM_CP_DMA_COMPLETE_T0__DATA__SHIFT 0x0 |
37470 | #define RLC_GPM_CP_DMA_COMPLETE_T0__RESERVED__SHIFT 0x1 |
37471 | #define RLC_GPM_CP_DMA_COMPLETE_T0__DATA_MASK 0x00000001L |
37472 | #define RLC_GPM_CP_DMA_COMPLETE_T0__RESERVED_MASK 0xFFFFFFFEL |
37473 | //RLC_GPM_CP_DMA_COMPLETE_T1 |
37474 | #define RLC_GPM_CP_DMA_COMPLETE_T1__DATA__SHIFT 0x0 |
37475 | #define RLC_GPM_CP_DMA_COMPLETE_T1__RESERVED__SHIFT 0x1 |
37476 | #define RLC_GPM_CP_DMA_COMPLETE_T1__DATA_MASK 0x00000001L |
37477 | #define RLC_GPM_CP_DMA_COMPLETE_T1__RESERVED_MASK 0xFFFFFFFEL |
37478 | //RLC_GPM_THREAD_INVALIDATE_CACHE |
37479 | #define RLC_GPM_THREAD_INVALIDATE_CACHE__THREAD0_INVALIDATE_CACHE__SHIFT 0x0 |
37480 | #define RLC_GPM_THREAD_INVALIDATE_CACHE__THREAD1_INVALIDATE_CACHE__SHIFT 0x1 |
37481 | #define RLC_GPM_THREAD_INVALIDATE_CACHE__THREAD2_INVALIDATE_CACHE__SHIFT 0x2 |
37482 | #define RLC_GPM_THREAD_INVALIDATE_CACHE__THREAD3_INVALIDATE_CACHE__SHIFT 0x3 |
37483 | #define RLC_GPM_THREAD_INVALIDATE_CACHE__RESERVED__SHIFT 0x4 |
37484 | #define RLC_GPM_THREAD_INVALIDATE_CACHE__THREAD0_INVALIDATE_CACHE_MASK 0x00000001L |
37485 | #define RLC_GPM_THREAD_INVALIDATE_CACHE__THREAD1_INVALIDATE_CACHE_MASK 0x00000002L |
37486 | #define RLC_GPM_THREAD_INVALIDATE_CACHE__THREAD2_INVALIDATE_CACHE_MASK 0x00000004L |
37487 | #define RLC_GPM_THREAD_INVALIDATE_CACHE__THREAD3_INVALIDATE_CACHE_MASK 0x00000008L |
37488 | #define RLC_GPM_THREAD_INVALIDATE_CACHE__RESERVED_MASK 0xFFFFFFF0L |
37489 | //RLC_CLK_COUNT_GFXCLK_LSB |
37490 | #define RLC_CLK_COUNT_GFXCLK_LSB__COUNTER__SHIFT 0x0 |
37491 | #define RLC_CLK_COUNT_GFXCLK_LSB__COUNTER_MASK 0xFFFFFFFFL |
37492 | //RLC_CLK_COUNT_GFXCLK_MSB |
37493 | #define RLC_CLK_COUNT_GFXCLK_MSB__COUNTER__SHIFT 0x0 |
37494 | #define RLC_CLK_COUNT_GFXCLK_MSB__COUNTER_MASK 0xFFFFFFFFL |
37495 | //RLC_CLK_COUNT_REFCLK_LSB |
37496 | #define RLC_CLK_COUNT_REFCLK_LSB__COUNTER__SHIFT 0x0 |
37497 | #define RLC_CLK_COUNT_REFCLK_LSB__COUNTER_MASK 0xFFFFFFFFL |
37498 | //RLC_CLK_COUNT_REFCLK_MSB |
37499 | #define RLC_CLK_COUNT_REFCLK_MSB__COUNTER__SHIFT 0x0 |
37500 | #define RLC_CLK_COUNT_REFCLK_MSB__COUNTER_MASK 0xFFFFFFFFL |
37501 | //RLC_CLK_COUNT_CTRL |
37502 | #define RLC_CLK_COUNT_CTRL__GFXCLK_RUN__SHIFT 0x0 |
37503 | #define RLC_CLK_COUNT_CTRL__GFXCLK_RESET__SHIFT 0x1 |
37504 | #define RLC_CLK_COUNT_CTRL__GFXCLK_SAMPLE__SHIFT 0x2 |
37505 | #define RLC_CLK_COUNT_CTRL__REFCLK_RUN__SHIFT 0x3 |
37506 | #define RLC_CLK_COUNT_CTRL__REFCLK_RESET__SHIFT 0x4 |
37507 | #define RLC_CLK_COUNT_CTRL__REFCLK_SAMPLE__SHIFT 0x5 |
37508 | #define RLC_CLK_COUNT_CTRL__GFXCLK_RUN_MASK 0x00000001L |
37509 | #define RLC_CLK_COUNT_CTRL__GFXCLK_RESET_MASK 0x00000002L |
37510 | #define RLC_CLK_COUNT_CTRL__GFXCLK_SAMPLE_MASK 0x00000004L |
37511 | #define RLC_CLK_COUNT_CTRL__REFCLK_RUN_MASK 0x00000008L |
37512 | #define RLC_CLK_COUNT_CTRL__REFCLK_RESET_MASK 0x00000010L |
37513 | #define RLC_CLK_COUNT_CTRL__REFCLK_SAMPLE_MASK 0x00000020L |
37514 | //RLC_CLK_COUNT_STAT |
37515 | #define RLC_CLK_COUNT_STAT__GFXCLK_VALID__SHIFT 0x0 |
37516 | #define RLC_CLK_COUNT_STAT__REFCLK_VALID__SHIFT 0x1 |
37517 | #define RLC_CLK_COUNT_STAT__REFCLK_RUN_RESYNC__SHIFT 0x2 |
37518 | #define RLC_CLK_COUNT_STAT__REFCLK_RESET_RESYNC__SHIFT 0x3 |
37519 | #define RLC_CLK_COUNT_STAT__REFCLK_SAMPLE_RESYNC__SHIFT 0x4 |
37520 | #define RLC_CLK_COUNT_STAT__RESERVED__SHIFT 0x5 |
37521 | #define RLC_CLK_COUNT_STAT__GFXCLK_VALID_MASK 0x00000001L |
37522 | #define RLC_CLK_COUNT_STAT__REFCLK_VALID_MASK 0x00000002L |
37523 | #define RLC_CLK_COUNT_STAT__REFCLK_RUN_RESYNC_MASK 0x00000004L |
37524 | #define RLC_CLK_COUNT_STAT__REFCLK_RESET_RESYNC_MASK 0x00000008L |
37525 | #define RLC_CLK_COUNT_STAT__REFCLK_SAMPLE_RESYNC_MASK 0x00000010L |
37526 | #define RLC_CLK_COUNT_STAT__RESERVED_MASK 0xFFFFFFE0L |
37527 | //RLC_RLCG_DOORBELL_CNTL |
37528 | #define RLC_RLCG_DOORBELL_CNTL__DOORBELL_0_MODE__SHIFT 0x0 |
37529 | #define RLC_RLCG_DOORBELL_CNTL__DOORBELL_1_MODE__SHIFT 0x2 |
37530 | #define RLC_RLCG_DOORBELL_CNTL__DOORBELL_2_MODE__SHIFT 0x4 |
37531 | #define RLC_RLCG_DOORBELL_CNTL__DOORBELL_3_MODE__SHIFT 0x6 |
37532 | #define RLC_RLCG_DOORBELL_CNTL__DOORBELL_ID__SHIFT 0x10 |
37533 | #define RLC_RLCG_DOORBELL_CNTL__DOORBELL_ID_EN__SHIFT 0x15 |
37534 | #define RLC_RLCG_DOORBELL_CNTL__RESERVED__SHIFT 0x16 |
37535 | #define RLC_RLCG_DOORBELL_CNTL__DOORBELL_0_MODE_MASK 0x00000003L |
37536 | #define RLC_RLCG_DOORBELL_CNTL__DOORBELL_1_MODE_MASK 0x0000000CL |
37537 | #define RLC_RLCG_DOORBELL_CNTL__DOORBELL_2_MODE_MASK 0x00000030L |
37538 | #define RLC_RLCG_DOORBELL_CNTL__DOORBELL_3_MODE_MASK 0x000000C0L |
37539 | #define RLC_RLCG_DOORBELL_CNTL__DOORBELL_ID_MASK 0x001F0000L |
37540 | #define RLC_RLCG_DOORBELL_CNTL__DOORBELL_ID_EN_MASK 0x00200000L |
37541 | #define RLC_RLCG_DOORBELL_CNTL__RESERVED_MASK 0xFFC00000L |
37542 | //RLC_RLCG_DOORBELL_STAT |
37543 | #define RLC_RLCG_DOORBELL_STAT__DOORBELL_0_VALID__SHIFT 0x0 |
37544 | #define RLC_RLCG_DOORBELL_STAT__DOORBELL_1_VALID__SHIFT 0x1 |
37545 | #define RLC_RLCG_DOORBELL_STAT__DOORBELL_2_VALID__SHIFT 0x2 |
37546 | #define RLC_RLCG_DOORBELL_STAT__DOORBELL_3_VALID__SHIFT 0x3 |
37547 | #define RLC_RLCG_DOORBELL_STAT__DOORBELL_0_VALID_MASK 0x00000001L |
37548 | #define RLC_RLCG_DOORBELL_STAT__DOORBELL_1_VALID_MASK 0x00000002L |
37549 | #define RLC_RLCG_DOORBELL_STAT__DOORBELL_2_VALID_MASK 0x00000004L |
37550 | #define RLC_RLCG_DOORBELL_STAT__DOORBELL_3_VALID_MASK 0x00000008L |
37551 | //RLC_RLCG_DOORBELL_0_DATA_LO |
37552 | #define RLC_RLCG_DOORBELL_0_DATA_LO__DATA__SHIFT 0x0 |
37553 | #define RLC_RLCG_DOORBELL_0_DATA_LO__DATA_MASK 0xFFFFFFFFL |
37554 | //RLC_RLCG_DOORBELL_0_DATA_HI |
37555 | #define RLC_RLCG_DOORBELL_0_DATA_HI__DATA__SHIFT 0x0 |
37556 | #define RLC_RLCG_DOORBELL_0_DATA_HI__DATA_MASK 0xFFFFFFFFL |
37557 | //RLC_RLCG_DOORBELL_1_DATA_LO |
37558 | #define RLC_RLCG_DOORBELL_1_DATA_LO__DATA__SHIFT 0x0 |
37559 | #define RLC_RLCG_DOORBELL_1_DATA_LO__DATA_MASK 0xFFFFFFFFL |
37560 | //RLC_RLCG_DOORBELL_1_DATA_HI |
37561 | #define RLC_RLCG_DOORBELL_1_DATA_HI__DATA__SHIFT 0x0 |
37562 | #define RLC_RLCG_DOORBELL_1_DATA_HI__DATA_MASK 0xFFFFFFFFL |
37563 | //RLC_RLCG_DOORBELL_2_DATA_LO |
37564 | #define RLC_RLCG_DOORBELL_2_DATA_LO__DATA__SHIFT 0x0 |
37565 | #define RLC_RLCG_DOORBELL_2_DATA_LO__DATA_MASK 0xFFFFFFFFL |
37566 | //RLC_RLCG_DOORBELL_2_DATA_HI |
37567 | #define RLC_RLCG_DOORBELL_2_DATA_HI__DATA__SHIFT 0x0 |
37568 | #define RLC_RLCG_DOORBELL_2_DATA_HI__DATA_MASK 0xFFFFFFFFL |
37569 | //RLC_RLCG_DOORBELL_3_DATA_LO |
37570 | #define RLC_RLCG_DOORBELL_3_DATA_LO__DATA__SHIFT 0x0 |
37571 | #define RLC_RLCG_DOORBELL_3_DATA_LO__DATA_MASK 0xFFFFFFFFL |
37572 | //RLC_RLCG_DOORBELL_3_DATA_HI |
37573 | #define RLC_RLCG_DOORBELL_3_DATA_HI__DATA__SHIFT 0x0 |
37574 | #define RLC_RLCG_DOORBELL_3_DATA_HI__DATA_MASK 0xFFFFFFFFL |
37575 | //RLC_GPU_CLOCK_32_RES_SEL |
37576 | #define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL__SHIFT 0x0 |
37577 | #define RLC_GPU_CLOCK_32_RES_SEL__RESERVED__SHIFT 0x6 |
37578 | #define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL_MASK 0x0000003FL |
37579 | #define RLC_GPU_CLOCK_32_RES_SEL__RESERVED_MASK 0xFFFFFFC0L |
37580 | //RLC_GPU_CLOCK_32 |
37581 | #define RLC_GPU_CLOCK_32__GPU_CLOCK_32__SHIFT 0x0 |
37582 | #define RLC_GPU_CLOCK_32__GPU_CLOCK_32_MASK 0xFFFFFFFFL |
37583 | //RLC_PG_CNTL |
37584 | #define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE__SHIFT 0x0 |
37585 | #define RLC_PG_CNTL__GFX_POWER_GATING_SRC__SHIFT 0x1 |
37586 | #define RLC_PG_CNTL__DYN_PER_WGP_PG_ENABLE__SHIFT 0x2 |
37587 | #define RLC_PG_CNTL__STATIC_PER_WGP_PG_ENABLE__SHIFT 0x3 |
37588 | #define RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE__SHIFT 0x4 |
37589 | #define RLC_PG_CNTL__RESERVED__SHIFT 0x5 |
37590 | #define RLC_PG_CNTL__MEM_DS_DISABLE__SHIFT 0xd |
37591 | #define RLC_PG_CNTL__PG_OVERRIDE__SHIFT 0xe |
37592 | #define RLC_PG_CNTL__CP_PG_DISABLE__SHIFT 0xf |
37593 | #define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE__SHIFT 0x10 |
37594 | #define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE__SHIFT 0x11 |
37595 | #define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE__SHIFT 0x12 |
37596 | #define RLC_PG_CNTL__RESERVED1__SHIFT 0x13 |
37597 | #define RLC_PG_CNTL__Ultra_Low_Voltage_Enable__SHIFT 0x15 |
37598 | #define RLC_PG_CNTL__RESERVED2__SHIFT 0x16 |
37599 | #define RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE__SHIFT 0x17 |
37600 | #define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK 0x00000001L |
37601 | #define RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK 0x00000002L |
37602 | #define RLC_PG_CNTL__DYN_PER_WGP_PG_ENABLE_MASK 0x00000004L |
37603 | #define RLC_PG_CNTL__STATIC_PER_WGP_PG_ENABLE_MASK 0x00000008L |
37604 | #define RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE_MASK 0x00000010L |
37605 | #define RLC_PG_CNTL__RESERVED_MASK 0x00001FE0L |
37606 | #define RLC_PG_CNTL__MEM_DS_DISABLE_MASK 0x00002000L |
37607 | #define RLC_PG_CNTL__PG_OVERRIDE_MASK 0x00004000L |
37608 | #define RLC_PG_CNTL__CP_PG_DISABLE_MASK 0x00008000L |
37609 | #define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE_MASK 0x00010000L |
37610 | #define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK 0x00020000L |
37611 | #define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK 0x00040000L |
37612 | #define RLC_PG_CNTL__RESERVED1_MASK 0x00180000L |
37613 | #define RLC_PG_CNTL__Ultra_Low_Voltage_Enable_MASK 0x00200000L |
37614 | #define RLC_PG_CNTL__RESERVED2_MASK 0x00400000L |
37615 | #define RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK 0x00800000L |
37616 | //RLC_GPM_THREAD_PRIORITY |
37617 | #define RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY__SHIFT 0x0 |
37618 | #define RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY__SHIFT 0x8 |
37619 | #define RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY__SHIFT 0x10 |
37620 | #define RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY__SHIFT 0x18 |
37621 | #define RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY_MASK 0x000000FFL |
37622 | #define RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY_MASK 0x0000FF00L |
37623 | #define RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY_MASK 0x00FF0000L |
37624 | #define RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY_MASK 0xFF000000L |
37625 | //RLC_GPM_THREAD_ENABLE |
37626 | #define RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE__SHIFT 0x0 |
37627 | #define RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE__SHIFT 0x1 |
37628 | #define RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE__SHIFT 0x2 |
37629 | #define RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE__SHIFT 0x3 |
37630 | #define RLC_GPM_THREAD_ENABLE__RESERVED__SHIFT 0x4 |
37631 | #define RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE_MASK 0x00000001L |
37632 | #define RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE_MASK 0x00000002L |
37633 | #define RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE_MASK 0x00000004L |
37634 | #define RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE_MASK 0x00000008L |
37635 | #define RLC_GPM_THREAD_ENABLE__RESERVED_MASK 0xFFFFFFF0L |
37636 | //RLC_RLCG_DOORBELL_RANGE |
37637 | #define RLC_RLCG_DOORBELL_RANGE__LOWER_ADDR_RESERVED__SHIFT 0x0 |
37638 | #define RLC_RLCG_DOORBELL_RANGE__LOWER_ADDR__SHIFT 0x2 |
37639 | #define RLC_RLCG_DOORBELL_RANGE__UPPER_ADDR_RESERVED__SHIFT 0x10 |
37640 | #define RLC_RLCG_DOORBELL_RANGE__UPPER_ADDR__SHIFT 0x12 |
37641 | #define RLC_RLCG_DOORBELL_RANGE__LOWER_ADDR_RESERVED_MASK 0x00000003L |
37642 | #define RLC_RLCG_DOORBELL_RANGE__LOWER_ADDR_MASK 0x00000FFCL |
37643 | #define RLC_RLCG_DOORBELL_RANGE__UPPER_ADDR_RESERVED_MASK 0x00030000L |
37644 | #define RLC_RLCG_DOORBELL_RANGE__UPPER_ADDR_MASK 0x0FFC0000L |
37645 | //RLC_RLCS_FED_STATUS_0 |
37646 | #define RLC_RLCS_FED_STATUS_0__RLC_FED_ERR__SHIFT 0x0 |
37647 | #define RLC_RLCS_FED_STATUS_0__UTCL2_FED_ERR__SHIFT 0x1 |
37648 | #define RLC_RLCS_FED_STATUS_0__GE_FED_ERR__SHIFT 0x2 |
37649 | #define RLC_RLCS_FED_STATUS_0__CPC_FED_ERR__SHIFT 0x3 |
37650 | #define RLC_RLCS_FED_STATUS_0__CPF_FED_ERR__SHIFT 0x4 |
37651 | #define RLC_RLCS_FED_STATUS_0__CPG_FED_ERR__SHIFT 0x5 |
37652 | #define RLC_RLCS_FED_STATUS_0__SDMA0_FED_ERR__SHIFT 0x6 |
37653 | #define RLC_RLCS_FED_STATUS_0__SDMA1_FED_ERR__SHIFT 0x7 |
37654 | #define RLC_RLCS_FED_STATUS_0__RLC_FED_ERR_MASK 0x00000001L |
37655 | #define RLC_RLCS_FED_STATUS_0__UTCL2_FED_ERR_MASK 0x00000002L |
37656 | #define RLC_RLCS_FED_STATUS_0__GE_FED_ERR_MASK 0x00000004L |
37657 | #define RLC_RLCS_FED_STATUS_0__CPC_FED_ERR_MASK 0x00000008L |
37658 | #define RLC_RLCS_FED_STATUS_0__CPF_FED_ERR_MASK 0x00000010L |
37659 | #define RLC_RLCS_FED_STATUS_0__CPG_FED_ERR_MASK 0x00000020L |
37660 | #define RLC_RLCS_FED_STATUS_0__SDMA0_FED_ERR_MASK 0x00000040L |
37661 | #define RLC_RLCS_FED_STATUS_0__SDMA1_FED_ERR_MASK 0x00000080L |
37662 | //RLC_RLCS_FED_STATUS_1 |
37663 | #define RLC_RLCS_FED_STATUS_1__GL2C0_FED_ERR__SHIFT 0x0 |
37664 | #define RLC_RLCS_FED_STATUS_1__GL2C1_FED_ERR__SHIFT 0x1 |
37665 | #define RLC_RLCS_FED_STATUS_1__GL2C2_FED_ERR__SHIFT 0x2 |
37666 | #define RLC_RLCS_FED_STATUS_1__GL2C3_FED_ERR__SHIFT 0x3 |
37667 | #define RLC_RLCS_FED_STATUS_1__GL2C4_FED_ERR__SHIFT 0x4 |
37668 | #define RLC_RLCS_FED_STATUS_1__GL2C5_FED_ERR__SHIFT 0x5 |
37669 | #define RLC_RLCS_FED_STATUS_1__GL2C6_FED_ERR__SHIFT 0x6 |
37670 | #define RLC_RLCS_FED_STATUS_1__GL2C7_FED_ERR__SHIFT 0x7 |
37671 | #define RLC_RLCS_FED_STATUS_1__GL2C8_FED_ERR__SHIFT 0x8 |
37672 | #define RLC_RLCS_FED_STATUS_1__GL2C9_FED_ERR__SHIFT 0x9 |
37673 | #define RLC_RLCS_FED_STATUS_1__GL2C10_FED_ERR__SHIFT 0xa |
37674 | #define RLC_RLCS_FED_STATUS_1__GL2C11_FED_ERR__SHIFT 0xb |
37675 | #define RLC_RLCS_FED_STATUS_1__GL2C12_FED_ERR__SHIFT 0xc |
37676 | #define RLC_RLCS_FED_STATUS_1__GL2C13_FED_ERR__SHIFT 0xd |
37677 | #define RLC_RLCS_FED_STATUS_1__GL2C14_FED_ERR__SHIFT 0xe |
37678 | #define RLC_RLCS_FED_STATUS_1__GL2C15_FED_ERR__SHIFT 0xf |
37679 | #define RLC_RLCS_FED_STATUS_1__GL2C0_FED_ERR_MASK 0x00000001L |
37680 | #define RLC_RLCS_FED_STATUS_1__GL2C1_FED_ERR_MASK 0x00000002L |
37681 | #define RLC_RLCS_FED_STATUS_1__GL2C2_FED_ERR_MASK 0x00000004L |
37682 | #define RLC_RLCS_FED_STATUS_1__GL2C3_FED_ERR_MASK 0x00000008L |
37683 | #define RLC_RLCS_FED_STATUS_1__GL2C4_FED_ERR_MASK 0x00000010L |
37684 | #define RLC_RLCS_FED_STATUS_1__GL2C5_FED_ERR_MASK 0x00000020L |
37685 | #define RLC_RLCS_FED_STATUS_1__GL2C6_FED_ERR_MASK 0x00000040L |
37686 | #define RLC_RLCS_FED_STATUS_1__GL2C7_FED_ERR_MASK 0x00000080L |
37687 | #define RLC_RLCS_FED_STATUS_1__GL2C8_FED_ERR_MASK 0x00000100L |
37688 | #define RLC_RLCS_FED_STATUS_1__GL2C9_FED_ERR_MASK 0x00000200L |
37689 | #define RLC_RLCS_FED_STATUS_1__GL2C10_FED_ERR_MASK 0x00000400L |
37690 | #define RLC_RLCS_FED_STATUS_1__GL2C11_FED_ERR_MASK 0x00000800L |
37691 | #define RLC_RLCS_FED_STATUS_1__GL2C12_FED_ERR_MASK 0x00001000L |
37692 | #define RLC_RLCS_FED_STATUS_1__GL2C13_FED_ERR_MASK 0x00002000L |
37693 | #define RLC_RLCS_FED_STATUS_1__GL2C14_FED_ERR_MASK 0x00004000L |
37694 | #define RLC_RLCS_FED_STATUS_1__GL2C15_FED_ERR_MASK 0x00008000L |
37695 | //RLC_CGTT_MGCG_OVERRIDE |
37696 | #define RLC_CGTT_MGCG_OVERRIDE__RLC_REPEATER_FGCG_OVERRIDE__SHIFT 0x0 |
37697 | #define RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE__SHIFT 0x1 |
37698 | #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE__SHIFT 0x2 |
37699 | #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE__SHIFT 0x3 |
37700 | #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE__SHIFT 0x4 |
37701 | #define RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE__SHIFT 0x5 |
37702 | #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE__SHIFT 0x6 |
37703 | #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE__SHIFT 0x7 |
37704 | #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE__SHIFT 0x8 |
37705 | #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE__SHIFT 0x9 |
37706 | #define RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE__SHIFT 0xa |
37707 | #define RLC_CGTT_MGCG_OVERRIDE__RESERVED_16_11__SHIFT 0xb |
37708 | #define RLC_CGTT_MGCG_OVERRIDE__GC_CAC_MGCG_CLK_CNTL__SHIFT 0x11 |
37709 | #define RLC_CGTT_MGCG_OVERRIDE__SE_CAC_MGCG_CLK_CNTL__SHIFT 0x12 |
37710 | #define RLC_CGTT_MGCG_OVERRIDE__RESERVED_31_19__SHIFT 0x13 |
37711 | #define RLC_CGTT_MGCG_OVERRIDE__RLC_REPEATER_FGCG_OVERRIDE_MASK 0x00000001L |
37712 | #define RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK 0x00000002L |
37713 | #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK 0x00000004L |
37714 | #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK 0x00000008L |
37715 | #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK 0x00000010L |
37716 | #define RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK 0x00000020L |
37717 | #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK 0x00000040L |
37718 | #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK 0x00000080L |
37719 | #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK 0x00000100L |
37720 | #define RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK 0x00000200L |
37721 | #define RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK 0x00000400L |
37722 | #define RLC_CGTT_MGCG_OVERRIDE__RESERVED_16_11_MASK 0x0001F800L |
37723 | #define RLC_CGTT_MGCG_OVERRIDE__GC_CAC_MGCG_CLK_CNTL_MASK 0x00020000L |
37724 | #define RLC_CGTT_MGCG_OVERRIDE__SE_CAC_MGCG_CLK_CNTL_MASK 0x00040000L |
37725 | #define RLC_CGTT_MGCG_OVERRIDE__RESERVED_31_19_MASK 0xFFF80000L |
37726 | //RLC_CGCG_CGLS_CTRL |
37727 | #define RLC_CGCG_CGLS_CTRL__CGCG_EN__SHIFT 0x0 |
37728 | #define RLC_CGCG_CGLS_CTRL__CGLS_EN__SHIFT 0x1 |
37729 | #define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT 0x2 |
37730 | #define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT 0x8 |
37731 | #define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER__SHIFT 0x1b |
37732 | #define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL__SHIFT 0x1c |
37733 | #define RLC_CGCG_CGLS_CTRL__SLEEP_MODE__SHIFT 0x1d |
37734 | #define RLC_CGCG_CGLS_CTRL__SIM_SILICON_EN__SHIFT 0x1f |
37735 | #define RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK 0x00000001L |
37736 | #define RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK 0x00000002L |
37737 | #define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK 0x000000FCL |
37738 | #define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK 0x07FFFF00L |
37739 | #define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER_MASK 0x08000000L |
37740 | #define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL_MASK 0x10000000L |
37741 | #define RLC_CGCG_CGLS_CTRL__SLEEP_MODE_MASK 0x60000000L |
37742 | #define RLC_CGCG_CGLS_CTRL__SIM_SILICON_EN_MASK 0x80000000L |
37743 | //RLC_CGCG_RAMP_CTRL |
37744 | #define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT__SHIFT 0x0 |
37745 | #define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT__SHIFT 0x4 |
37746 | #define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT__SHIFT 0x8 |
37747 | #define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT__SHIFT 0xc |
37748 | #define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT__SHIFT 0x10 |
37749 | #define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT__SHIFT 0x1c |
37750 | #define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT_MASK 0x0000000FL |
37751 | #define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT_MASK 0x000000F0L |
37752 | #define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT_MASK 0x00000F00L |
37753 | #define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT_MASK 0x0000F000L |
37754 | #define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT_MASK 0x0FFF0000L |
37755 | #define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT_MASK 0xF0000000L |
37756 | //RLC_DYN_PG_STATUS |
37757 | #define RLC_DYN_PG_STATUS__PG_STATUS_WGP_MASK__SHIFT 0x0 |
37758 | #define RLC_DYN_PG_STATUS__PG_STATUS_WGP_MASK_MASK 0xFFFFFFFFL |
37759 | //RLC_DYN_PG_REQUEST |
37760 | #define RLC_DYN_PG_REQUEST__PG_REQUEST_WGP_MASK__SHIFT 0x0 |
37761 | #define RLC_DYN_PG_REQUEST__PG_REQUEST_WGP_MASK_MASK 0xFFFFFFFFL |
37762 | //RLC_PG_DELAY |
37763 | #define RLC_PG_DELAY__POWER_UP_DELAY__SHIFT 0x0 |
37764 | #define RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT 0x8 |
37765 | #define RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT 0x10 |
37766 | #define RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT 0x18 |
37767 | #define RLC_PG_DELAY__POWER_UP_DELAY_MASK 0x000000FFL |
37768 | #define RLC_PG_DELAY__POWER_DOWN_DELAY_MASK 0x0000FF00L |
37769 | #define RLC_PG_DELAY__CMD_PROPAGATE_DELAY_MASK 0x00FF0000L |
37770 | #define RLC_PG_DELAY__MEM_SLEEP_DELAY_MASK 0xFF000000L |
37771 | //RLC_WGP_STATUS |
37772 | #define RLC_WGP_STATUS__WORK_PENDING__SHIFT 0x0 |
37773 | #define RLC_WGP_STATUS__WORK_PENDING_MASK 0xFFFFFFFFL |
37774 | //RLC_PG_ALWAYS_ON_WGP_MASK |
37775 | #define RLC_PG_ALWAYS_ON_WGP_MASK__AON_WGP_MASK__SHIFT 0x0 |
37776 | #define RLC_PG_ALWAYS_ON_WGP_MASK__AON_WGP_MASK_MASK 0xFFFFFFFFL |
37777 | //RLC_MAX_PG_WGP |
37778 | #define RLC_MAX_PG_WGP__MAX_POWERED_UP_WGP__SHIFT 0x0 |
37779 | #define RLC_MAX_PG_WGP__SPARE__SHIFT 0x8 |
37780 | #define RLC_MAX_PG_WGP__MAX_POWERED_UP_WGP_MASK 0x000000FFL |
37781 | #define RLC_MAX_PG_WGP__SPARE_MASK 0xFFFFFF00L |
37782 | //RLC_AUTO_PG_CTRL |
37783 | #define RLC_AUTO_PG_CTRL__AUTO_PG_EN__SHIFT 0x0 |
37784 | #define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN__SHIFT 0x1 |
37785 | #define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN__SHIFT 0x2 |
37786 | #define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT 0x3 |
37787 | #define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD__SHIFT 0x13 |
37788 | #define RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK 0x00000001L |
37789 | #define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN_MASK 0x00000002L |
37790 | #define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN_MASK 0x00000004L |
37791 | #define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK 0x0007FFF8L |
37792 | #define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK 0xFFF80000L |
37793 | //RLC_SERDES_RD_INDEX |
37794 | #define RLC_SERDES_RD_INDEX__DATA_REG_ID__SHIFT 0x0 |
37795 | #define RLC_SERDES_RD_INDEX__SPARE__SHIFT 0x2 |
37796 | #define RLC_SERDES_RD_INDEX__DATA_REG_ID_MASK 0x00000003L |
37797 | #define RLC_SERDES_RD_INDEX__SPARE_MASK 0xFFFFFFFCL |
37798 | //RLC_SERDES_RD_DATA_0 |
37799 | #define RLC_SERDES_RD_DATA_0__DATA__SHIFT 0x0 |
37800 | #define RLC_SERDES_RD_DATA_0__DATA_MASK 0xFFFFFFFFL |
37801 | //RLC_SERDES_RD_DATA_1 |
37802 | #define RLC_SERDES_RD_DATA_1__DATA__SHIFT 0x0 |
37803 | #define RLC_SERDES_RD_DATA_1__DATA_MASK 0xFFFFFFFFL |
37804 | //RLC_SERDES_RD_DATA_2 |
37805 | #define RLC_SERDES_RD_DATA_2__DATA__SHIFT 0x0 |
37806 | #define RLC_SERDES_RD_DATA_2__DATA_MASK 0xFFFFFFFFL |
37807 | //RLC_SERDES_RD_DATA_3 |
37808 | #define RLC_SERDES_RD_DATA_3__DATA__SHIFT 0x0 |
37809 | #define RLC_SERDES_RD_DATA_3__DATA_MASK 0xFFFFFFFFL |
37810 | //RLC_SERDES_MASK |
37811 | #define RLC_SERDES_MASK__GC_CENTER_HUB_0__SHIFT 0x0 |
37812 | #define RLC_SERDES_MASK__GC_CENTER_HUB_1__SHIFT 0x1 |
37813 | #define RLC_SERDES_MASK__RESERVED__SHIFT 0x2 |
37814 | #define RLC_SERDES_MASK__GC_SE_0__SHIFT 0x10 |
37815 | #define RLC_SERDES_MASK__GC_SE_1__SHIFT 0x11 |
37816 | #define RLC_SERDES_MASK__GC_SE_2__SHIFT 0x12 |
37817 | #define RLC_SERDES_MASK__GC_SE_3__SHIFT 0x13 |
37818 | #define RLC_SERDES_MASK__GC_SE_4__SHIFT 0x14 |
37819 | #define RLC_SERDES_MASK__GC_SE_5__SHIFT 0x15 |
37820 | #define RLC_SERDES_MASK__GC_SE_6__SHIFT 0x16 |
37821 | #define RLC_SERDES_MASK__GC_SE_7__SHIFT 0x17 |
37822 | #define RLC_SERDES_MASK__RESERVED_31_24__SHIFT 0x18 |
37823 | #define RLC_SERDES_MASK__GC_CENTER_HUB_0_MASK 0x00000001L |
37824 | #define RLC_SERDES_MASK__GC_CENTER_HUB_1_MASK 0x00000002L |
37825 | #define RLC_SERDES_MASK__RESERVED_MASK 0x0000FFFCL |
37826 | #define RLC_SERDES_MASK__GC_SE_0_MASK 0x00010000L |
37827 | #define RLC_SERDES_MASK__GC_SE_1_MASK 0x00020000L |
37828 | #define RLC_SERDES_MASK__GC_SE_2_MASK 0x00040000L |
37829 | #define RLC_SERDES_MASK__GC_SE_3_MASK 0x00080000L |
37830 | #define RLC_SERDES_MASK__GC_SE_4_MASK 0x00100000L |
37831 | #define RLC_SERDES_MASK__GC_SE_5_MASK 0x00200000L |
37832 | #define RLC_SERDES_MASK__GC_SE_6_MASK 0x00400000L |
37833 | #define RLC_SERDES_MASK__GC_SE_7_MASK 0x00800000L |
37834 | #define RLC_SERDES_MASK__RESERVED_31_24_MASK 0xFF000000L |
37835 | //RLC_SERDES_CTRL |
37836 | #define RLC_SERDES_CTRL__BPM_BROADCAST__SHIFT 0x0 |
37837 | #define RLC_SERDES_CTRL__BPM_REG_WRITE__SHIFT 0x1 |
37838 | #define RLC_SERDES_CTRL__BPM_LONG_CMD__SHIFT 0x2 |
37839 | #define RLC_SERDES_CTRL__BPM_ADDR__SHIFT 0x3 |
37840 | #define RLC_SERDES_CTRL__REG_ADDR__SHIFT 0x10 |
37841 | #define RLC_SERDES_CTRL__BPM_BROADCAST_MASK 0x000001L |
37842 | #define RLC_SERDES_CTRL__BPM_REG_WRITE_MASK 0x000002L |
37843 | #define RLC_SERDES_CTRL__BPM_LONG_CMD_MASK 0x000004L |
37844 | #define RLC_SERDES_CTRL__BPM_ADDR_MASK 0x00FFF8L |
37845 | #define RLC_SERDES_CTRL__REG_ADDR_MASK 0xFF0000L |
37846 | //RLC_SERDES_DATA |
37847 | #define RLC_SERDES_DATA__DATA__SHIFT 0x0 |
37848 | #define RLC_SERDES_DATA__DATA_MASK 0xFFFFFFFFL |
37849 | //RLC_SERDES_BUSY |
37850 | #define RLC_SERDES_BUSY__GC_CENTER_HUB_0__SHIFT 0x0 |
37851 | #define RLC_SERDES_BUSY__GC_CENTER_HUB_1__SHIFT 0x1 |
37852 | #define RLC_SERDES_BUSY__RESERVED__SHIFT 0x2 |
37853 | #define RLC_SERDES_BUSY__GC_SE_0__SHIFT 0x10 |
37854 | #define RLC_SERDES_BUSY__GC_SE_1__SHIFT 0x11 |
37855 | #define RLC_SERDES_BUSY__GC_SE_2__SHIFT 0x12 |
37856 | #define RLC_SERDES_BUSY__GC_SE_3__SHIFT 0x13 |
37857 | #define RLC_SERDES_BUSY__GC_SE_4__SHIFT 0x14 |
37858 | #define RLC_SERDES_BUSY__GC_SE_5__SHIFT 0x15 |
37859 | #define RLC_SERDES_BUSY__GC_SE_6__SHIFT 0x16 |
37860 | #define RLC_SERDES_BUSY__GC_SE_7__SHIFT 0x17 |
37861 | #define RLC_SERDES_BUSY__RESERVED_29_24__SHIFT 0x18 |
37862 | #define RLC_SERDES_BUSY__RD_FIFO_NOT_EMPTY__SHIFT 0x1e |
37863 | #define RLC_SERDES_BUSY__RD_PENDING__SHIFT 0x1f |
37864 | #define RLC_SERDES_BUSY__GC_CENTER_HUB_0_MASK 0x00000001L |
37865 | #define RLC_SERDES_BUSY__GC_CENTER_HUB_1_MASK 0x00000002L |
37866 | #define RLC_SERDES_BUSY__RESERVED_MASK 0x0000FFFCL |
37867 | #define RLC_SERDES_BUSY__GC_SE_0_MASK 0x00010000L |
37868 | #define RLC_SERDES_BUSY__GC_SE_1_MASK 0x00020000L |
37869 | #define RLC_SERDES_BUSY__GC_SE_2_MASK 0x00040000L |
37870 | #define RLC_SERDES_BUSY__GC_SE_3_MASK 0x00080000L |
37871 | #define RLC_SERDES_BUSY__GC_SE_4_MASK 0x00100000L |
37872 | #define RLC_SERDES_BUSY__GC_SE_5_MASK 0x00200000L |
37873 | #define RLC_SERDES_BUSY__GC_SE_6_MASK 0x00400000L |
37874 | #define RLC_SERDES_BUSY__GC_SE_7_MASK 0x00800000L |
37875 | #define RLC_SERDES_BUSY__RESERVED_29_24_MASK 0x3F000000L |
37876 | #define RLC_SERDES_BUSY__RD_FIFO_NOT_EMPTY_MASK 0x40000000L |
37877 | #define RLC_SERDES_BUSY__RD_PENDING_MASK 0x80000000L |
37878 | //RLC_GPM_GENERAL_0 |
37879 | #define RLC_GPM_GENERAL_0__DATA__SHIFT 0x0 |
37880 | #define RLC_GPM_GENERAL_0__DATA_MASK 0xFFFFFFFFL |
37881 | //RLC_GPM_GENERAL_1 |
37882 | #define RLC_GPM_GENERAL_1__DATA__SHIFT 0x0 |
37883 | #define RLC_GPM_GENERAL_1__DATA_MASK 0xFFFFFFFFL |
37884 | //RLC_GPM_GENERAL_2 |
37885 | #define RLC_GPM_GENERAL_2__DATA__SHIFT 0x0 |
37886 | #define RLC_GPM_GENERAL_2__DATA_MASK 0xFFFFFFFFL |
37887 | //RLC_GPM_GENERAL_3 |
37888 | #define RLC_GPM_GENERAL_3__DATA__SHIFT 0x0 |
37889 | #define RLC_GPM_GENERAL_3__DATA_MASK 0xFFFFFFFFL |
37890 | //RLC_GPM_GENERAL_4 |
37891 | #define RLC_GPM_GENERAL_4__DATA__SHIFT 0x0 |
37892 | #define RLC_GPM_GENERAL_4__DATA_MASK 0xFFFFFFFFL |
37893 | //RLC_GPM_GENERAL_5 |
37894 | #define RLC_GPM_GENERAL_5__DATA__SHIFT 0x0 |
37895 | #define RLC_GPM_GENERAL_5__DATA_MASK 0xFFFFFFFFL |
37896 | //RLC_GPM_GENERAL_6 |
37897 | #define RLC_GPM_GENERAL_6__DATA__SHIFT 0x0 |
37898 | #define RLC_GPM_GENERAL_6__DATA_MASK 0xFFFFFFFFL |
37899 | //RLC_GPM_GENERAL_7 |
37900 | #define RLC_GPM_GENERAL_7__DATA__SHIFT 0x0 |
37901 | #define RLC_GPM_GENERAL_7__DATA_MASK 0xFFFFFFFFL |
37902 | //RLC_STATIC_PG_STATUS |
37903 | #define RLC_STATIC_PG_STATUS__PG_STATUS_WGP_MASK__SHIFT 0x0 |
37904 | #define RLC_STATIC_PG_STATUS__PG_STATUS_WGP_MASK_MASK 0xFFFFFFFFL |
37905 | //RLC_GPM_GENERAL_16 |
37906 | #define RLC_GPM_GENERAL_16__DATA__SHIFT 0x0 |
37907 | #define RLC_GPM_GENERAL_16__DATA_MASK 0xFFFFFFFFL |
37908 | //RLC_PG_DELAY_3 |
37909 | #define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT 0x0 |
37910 | #define RLC_PG_DELAY_3__RESERVED__SHIFT 0x8 |
37911 | #define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK 0x000000FFL |
37912 | #define RLC_PG_DELAY_3__RESERVED_MASK 0xFFFFFF00L |
37913 | //RLC_GPR_REG1 |
37914 | #define RLC_GPR_REG1__DATA__SHIFT 0x0 |
37915 | #define RLC_GPR_REG1__DATA_MASK 0xFFFFFFFFL |
37916 | //RLC_GPR_REG2 |
37917 | #define RLC_GPR_REG2__DATA__SHIFT 0x0 |
37918 | #define RLC_GPR_REG2__DATA_MASK 0xFFFFFFFFL |
37919 | //RLC_GPM_INT_DISABLE_TH0 |
37920 | #define RLC_GPM_INT_DISABLE_TH0__DISABLE_INT__SHIFT 0x0 |
37921 | #define RLC_GPM_INT_DISABLE_TH0__DISABLE_INT_MASK 0xFFFFFFFFL |
37922 | //RLC_GPM_LEGACY_INT_DISABLE |
37923 | #define RLC_GPM_LEGACY_INT_DISABLE__SPP_PVT_INT_CHANGED__SHIFT 0x0 |
37924 | #define RLC_GPM_LEGACY_INT_DISABLE__CP_RLC_STAT_INVAL_PEND_CHANGED__SHIFT 0x1 |
37925 | #define RLC_GPM_LEGACY_INT_DISABLE__RLC_EOF_INT_CHANGED__SHIFT 0x2 |
37926 | #define RLC_GPM_LEGACY_INT_DISABLE__RLC_PG_CNTL_CHANGED__SHIFT 0x3 |
37927 | #define RLC_GPM_LEGACY_INT_DISABLE__STORE_LOAD_TIMER3_EXPIRED_T0__SHIFT 0x4 |
37928 | #define RLC_GPM_LEGACY_INT_DISABLE__SPP_PVT_INT_CHANGED_MASK 0x00000001L |
37929 | #define RLC_GPM_LEGACY_INT_DISABLE__CP_RLC_STAT_INVAL_PEND_CHANGED_MASK 0x00000002L |
37930 | #define RLC_GPM_LEGACY_INT_DISABLE__RLC_EOF_INT_CHANGED_MASK 0x00000004L |
37931 | #define RLC_GPM_LEGACY_INT_DISABLE__RLC_PG_CNTL_CHANGED_MASK 0x00000008L |
37932 | #define RLC_GPM_LEGACY_INT_DISABLE__STORE_LOAD_TIMER3_EXPIRED_T0_MASK 0x00000010L |
37933 | //RLC_GPM_INT_FORCE_TH0 |
37934 | #define RLC_GPM_INT_FORCE_TH0__FORCE_INT__SHIFT 0x0 |
37935 | #define RLC_GPM_INT_FORCE_TH0__FORCE_INT_MASK 0xFFFFFFFFL |
37936 | //RLC_SRM_CNTL |
37937 | #define RLC_SRM_CNTL__SRM_ENABLE__SHIFT 0x0 |
37938 | #define RLC_SRM_CNTL__AUTO_INCR_ADDR__SHIFT 0x1 |
37939 | #define RLC_SRM_CNTL__RESERVED__SHIFT 0x2 |
37940 | #define RLC_SRM_CNTL__SRM_ENABLE_MASK 0x00000001L |
37941 | #define RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK 0x00000002L |
37942 | #define RLC_SRM_CNTL__RESERVED_MASK 0xFFFFFFFCL |
37943 | //RLC_SRM_GPM_COMMAND_STATUS |
37944 | #define RLC_SRM_GPM_COMMAND_STATUS__FIFO_EMPTY__SHIFT 0x0 |
37945 | #define RLC_SRM_GPM_COMMAND_STATUS__FIFO_FULL__SHIFT 0x1 |
37946 | #define RLC_SRM_GPM_COMMAND_STATUS__RESERVED__SHIFT 0x2 |
37947 | #define RLC_SRM_GPM_COMMAND_STATUS__FIFO_EMPTY_MASK 0x00000001L |
37948 | #define RLC_SRM_GPM_COMMAND_STATUS__FIFO_FULL_MASK 0x00000002L |
37949 | #define RLC_SRM_GPM_COMMAND_STATUS__RESERVED_MASK 0xFFFFFFFCL |
37950 | //RLC_SRM_INDEX_CNTL_ADDR_0 |
37951 | #define RLC_SRM_INDEX_CNTL_ADDR_0__ADDRESS__SHIFT 0x0 |
37952 | #define RLC_SRM_INDEX_CNTL_ADDR_0__ADDRESS_MASK 0x0003FFFFL |
37953 | //RLC_SRM_INDEX_CNTL_ADDR_1 |
37954 | #define RLC_SRM_INDEX_CNTL_ADDR_1__ADDRESS__SHIFT 0x0 |
37955 | #define RLC_SRM_INDEX_CNTL_ADDR_1__ADDRESS_MASK 0x0003FFFFL |
37956 | //RLC_SRM_INDEX_CNTL_ADDR_2 |
37957 | #define RLC_SRM_INDEX_CNTL_ADDR_2__ADDRESS__SHIFT 0x0 |
37958 | #define RLC_SRM_INDEX_CNTL_ADDR_2__ADDRESS_MASK 0x0003FFFFL |
37959 | //RLC_SRM_INDEX_CNTL_ADDR_3 |
37960 | #define RLC_SRM_INDEX_CNTL_ADDR_3__ADDRESS__SHIFT 0x0 |
37961 | #define RLC_SRM_INDEX_CNTL_ADDR_3__ADDRESS_MASK 0x0003FFFFL |
37962 | //RLC_SRM_INDEX_CNTL_ADDR_4 |
37963 | #define RLC_SRM_INDEX_CNTL_ADDR_4__ADDRESS__SHIFT 0x0 |
37964 | #define RLC_SRM_INDEX_CNTL_ADDR_4__ADDRESS_MASK 0x0003FFFFL |
37965 | //RLC_SRM_INDEX_CNTL_ADDR_5 |
37966 | #define RLC_SRM_INDEX_CNTL_ADDR_5__ADDRESS__SHIFT 0x0 |
37967 | #define RLC_SRM_INDEX_CNTL_ADDR_5__ADDRESS_MASK 0x0003FFFFL |
37968 | //RLC_SRM_INDEX_CNTL_ADDR_6 |
37969 | #define RLC_SRM_INDEX_CNTL_ADDR_6__ADDRESS__SHIFT 0x0 |
37970 | #define RLC_SRM_INDEX_CNTL_ADDR_6__ADDRESS_MASK 0x0003FFFFL |
37971 | //RLC_SRM_INDEX_CNTL_ADDR_7 |
37972 | #define RLC_SRM_INDEX_CNTL_ADDR_7__ADDRESS__SHIFT 0x0 |
37973 | #define RLC_SRM_INDEX_CNTL_ADDR_7__ADDRESS_MASK 0x0003FFFFL |
37974 | //RLC_SRM_INDEX_CNTL_DATA_0 |
37975 | #define RLC_SRM_INDEX_CNTL_DATA_0__DATA__SHIFT 0x0 |
37976 | #define RLC_SRM_INDEX_CNTL_DATA_0__DATA_MASK 0xFFFFFFFFL |
37977 | //RLC_SRM_INDEX_CNTL_DATA_1 |
37978 | #define RLC_SRM_INDEX_CNTL_DATA_1__DATA__SHIFT 0x0 |
37979 | #define RLC_SRM_INDEX_CNTL_DATA_1__DATA_MASK 0xFFFFFFFFL |
37980 | //RLC_SRM_INDEX_CNTL_DATA_2 |
37981 | #define RLC_SRM_INDEX_CNTL_DATA_2__DATA__SHIFT 0x0 |
37982 | #define RLC_SRM_INDEX_CNTL_DATA_2__DATA_MASK 0xFFFFFFFFL |
37983 | //RLC_SRM_INDEX_CNTL_DATA_3 |
37984 | #define RLC_SRM_INDEX_CNTL_DATA_3__DATA__SHIFT 0x0 |
37985 | #define RLC_SRM_INDEX_CNTL_DATA_3__DATA_MASK 0xFFFFFFFFL |
37986 | //RLC_SRM_INDEX_CNTL_DATA_4 |
37987 | #define RLC_SRM_INDEX_CNTL_DATA_4__DATA__SHIFT 0x0 |
37988 | #define RLC_SRM_INDEX_CNTL_DATA_4__DATA_MASK 0xFFFFFFFFL |
37989 | //RLC_SRM_INDEX_CNTL_DATA_5 |
37990 | #define RLC_SRM_INDEX_CNTL_DATA_5__DATA__SHIFT 0x0 |
37991 | #define RLC_SRM_INDEX_CNTL_DATA_5__DATA_MASK 0xFFFFFFFFL |
37992 | //RLC_SRM_INDEX_CNTL_DATA_6 |
37993 | #define RLC_SRM_INDEX_CNTL_DATA_6__DATA__SHIFT 0x0 |
37994 | #define RLC_SRM_INDEX_CNTL_DATA_6__DATA_MASK 0xFFFFFFFFL |
37995 | //RLC_SRM_INDEX_CNTL_DATA_7 |
37996 | #define RLC_SRM_INDEX_CNTL_DATA_7__DATA__SHIFT 0x0 |
37997 | #define RLC_SRM_INDEX_CNTL_DATA_7__DATA_MASK 0xFFFFFFFFL |
37998 | //RLC_SRM_STAT |
37999 | #define RLC_SRM_STAT__SRM_BUSY__SHIFT 0x0 |
38000 | #define RLC_SRM_STAT__SRM_BUSY_DELAY__SHIFT 0x1 |
38001 | #define RLC_SRM_STAT__RESERVED__SHIFT 0x2 |
38002 | #define RLC_SRM_STAT__SRM_BUSY_MASK 0x00000001L |
38003 | #define RLC_SRM_STAT__SRM_BUSY_DELAY_MASK 0x00000002L |
38004 | #define RLC_SRM_STAT__RESERVED_MASK 0xFFFFFFFCL |
38005 | //RLC_GPM_GENERAL_8 |
38006 | #define RLC_GPM_GENERAL_8__DATA__SHIFT 0x0 |
38007 | #define RLC_GPM_GENERAL_8__DATA_MASK 0xFFFFFFFFL |
38008 | //RLC_GPM_GENERAL_9 |
38009 | #define RLC_GPM_GENERAL_9__DATA__SHIFT 0x0 |
38010 | #define RLC_GPM_GENERAL_9__DATA_MASK 0xFFFFFFFFL |
38011 | //RLC_GPM_GENERAL_10 |
38012 | #define RLC_GPM_GENERAL_10__DATA__SHIFT 0x0 |
38013 | #define RLC_GPM_GENERAL_10__DATA_MASK 0xFFFFFFFFL |
38014 | //RLC_GPM_GENERAL_11 |
38015 | #define RLC_GPM_GENERAL_11__DATA__SHIFT 0x0 |
38016 | #define RLC_GPM_GENERAL_11__DATA_MASK 0xFFFFFFFFL |
38017 | //RLC_GPM_GENERAL_12 |
38018 | #define RLC_GPM_GENERAL_12__DATA__SHIFT 0x0 |
38019 | #define RLC_GPM_GENERAL_12__DATA_MASK 0xFFFFFFFFL |
38020 | //RLC_GPM_UTCL1_CNTL_0 |
38021 | #define RLC_GPM_UTCL1_CNTL_0__XNACK_REDO_TIMER_CNT__SHIFT 0x0 |
38022 | #define RLC_GPM_UTCL1_CNTL_0__DROP_MODE__SHIFT 0x18 |
38023 | #define RLC_GPM_UTCL1_CNTL_0__BYPASS__SHIFT 0x19 |
38024 | #define RLC_GPM_UTCL1_CNTL_0__INVALIDATE__SHIFT 0x1a |
38025 | #define RLC_GPM_UTCL1_CNTL_0__FRAG_LIMIT_MODE__SHIFT 0x1b |
38026 | #define RLC_GPM_UTCL1_CNTL_0__FORCE_SNOOP__SHIFT 0x1c |
38027 | #define RLC_GPM_UTCL1_CNTL_0__RESERVED__SHIFT 0x1e |
38028 | #define RLC_GPM_UTCL1_CNTL_0__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL |
38029 | #define RLC_GPM_UTCL1_CNTL_0__DROP_MODE_MASK 0x01000000L |
38030 | #define RLC_GPM_UTCL1_CNTL_0__BYPASS_MASK 0x02000000L |
38031 | #define RLC_GPM_UTCL1_CNTL_0__INVALIDATE_MASK 0x04000000L |
38032 | #define RLC_GPM_UTCL1_CNTL_0__FRAG_LIMIT_MODE_MASK 0x08000000L |
38033 | #define RLC_GPM_UTCL1_CNTL_0__FORCE_SNOOP_MASK 0x10000000L |
38034 | #define RLC_GPM_UTCL1_CNTL_0__RESERVED_MASK 0xC0000000L |
38035 | //RLC_GPM_UTCL1_CNTL_1 |
38036 | #define RLC_GPM_UTCL1_CNTL_1__XNACK_REDO_TIMER_CNT__SHIFT 0x0 |
38037 | #define RLC_GPM_UTCL1_CNTL_1__DROP_MODE__SHIFT 0x18 |
38038 | #define RLC_GPM_UTCL1_CNTL_1__BYPASS__SHIFT 0x19 |
38039 | #define RLC_GPM_UTCL1_CNTL_1__INVALIDATE__SHIFT 0x1a |
38040 | #define RLC_GPM_UTCL1_CNTL_1__FRAG_LIMIT_MODE__SHIFT 0x1b |
38041 | #define RLC_GPM_UTCL1_CNTL_1__FORCE_SNOOP__SHIFT 0x1c |
38042 | #define RLC_GPM_UTCL1_CNTL_1__RESERVED__SHIFT 0x1e |
38043 | #define RLC_GPM_UTCL1_CNTL_1__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL |
38044 | #define RLC_GPM_UTCL1_CNTL_1__DROP_MODE_MASK 0x01000000L |
38045 | #define RLC_GPM_UTCL1_CNTL_1__BYPASS_MASK 0x02000000L |
38046 | #define RLC_GPM_UTCL1_CNTL_1__INVALIDATE_MASK 0x04000000L |
38047 | #define RLC_GPM_UTCL1_CNTL_1__FRAG_LIMIT_MODE_MASK 0x08000000L |
38048 | #define RLC_GPM_UTCL1_CNTL_1__FORCE_SNOOP_MASK 0x10000000L |
38049 | #define RLC_GPM_UTCL1_CNTL_1__RESERVED_MASK 0xC0000000L |
38050 | //RLC_GPM_UTCL1_CNTL_2 |
38051 | #define RLC_GPM_UTCL1_CNTL_2__XNACK_REDO_TIMER_CNT__SHIFT 0x0 |
38052 | #define RLC_GPM_UTCL1_CNTL_2__DROP_MODE__SHIFT 0x18 |
38053 | #define RLC_GPM_UTCL1_CNTL_2__BYPASS__SHIFT 0x19 |
38054 | #define RLC_GPM_UTCL1_CNTL_2__INVALIDATE__SHIFT 0x1a |
38055 | #define RLC_GPM_UTCL1_CNTL_2__FRAG_LIMIT_MODE__SHIFT 0x1b |
38056 | #define RLC_GPM_UTCL1_CNTL_2__FORCE_SNOOP__SHIFT 0x1c |
38057 | #define RLC_GPM_UTCL1_CNTL_2__RESERVED__SHIFT 0x1e |
38058 | #define RLC_GPM_UTCL1_CNTL_2__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL |
38059 | #define RLC_GPM_UTCL1_CNTL_2__DROP_MODE_MASK 0x01000000L |
38060 | #define RLC_GPM_UTCL1_CNTL_2__BYPASS_MASK 0x02000000L |
38061 | #define RLC_GPM_UTCL1_CNTL_2__INVALIDATE_MASK 0x04000000L |
38062 | #define RLC_GPM_UTCL1_CNTL_2__FRAG_LIMIT_MODE_MASK 0x08000000L |
38063 | #define RLC_GPM_UTCL1_CNTL_2__FORCE_SNOOP_MASK 0x10000000L |
38064 | #define RLC_GPM_UTCL1_CNTL_2__RESERVED_MASK 0xC0000000L |
38065 | //RLC_SPM_UTCL1_CNTL |
38066 | #define RLC_SPM_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 |
38067 | #define RLC_SPM_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 |
38068 | #define RLC_SPM_UTCL1_CNTL__BYPASS__SHIFT 0x19 |
38069 | #define RLC_SPM_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a |
38070 | #define RLC_SPM_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b |
38071 | #define RLC_SPM_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c |
38072 | #define RLC_SPM_UTCL1_CNTL__RESERVED__SHIFT 0x1e |
38073 | #define RLC_SPM_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL |
38074 | #define RLC_SPM_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L |
38075 | #define RLC_SPM_UTCL1_CNTL__BYPASS_MASK 0x02000000L |
38076 | #define RLC_SPM_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L |
38077 | #define RLC_SPM_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L |
38078 | #define RLC_SPM_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L |
38079 | #define RLC_SPM_UTCL1_CNTL__RESERVED_MASK 0xC0000000L |
38080 | //RLC_UTCL1_STATUS_2 |
38081 | #define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_BUSY__SHIFT 0x0 |
38082 | #define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_BUSY__SHIFT 0x1 |
38083 | #define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_BUSY__SHIFT 0x2 |
38084 | #define RLC_UTCL1_STATUS_2__SPM_UTCL1_BUSY__SHIFT 0x3 |
38085 | #define RLC_UTCL1_STATUS_2__RESERVED_1__SHIFT 0x4 |
38086 | #define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_StallOnTrans__SHIFT 0x5 |
38087 | #define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_StallOnTrans__SHIFT 0x6 |
38088 | #define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_StallOnTrans__SHIFT 0x7 |
38089 | #define RLC_UTCL1_STATUS_2__SPM_UTCL1_StallOnTrans__SHIFT 0x8 |
38090 | #define RLC_UTCL1_STATUS_2__RESERVED__SHIFT 0x9 |
38091 | #define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_BUSY_MASK 0x00000001L |
38092 | #define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_BUSY_MASK 0x00000002L |
38093 | #define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_BUSY_MASK 0x00000004L |
38094 | #define RLC_UTCL1_STATUS_2__SPM_UTCL1_BUSY_MASK 0x00000008L |
38095 | #define RLC_UTCL1_STATUS_2__RESERVED_1_MASK 0x00000010L |
38096 | #define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_StallOnTrans_MASK 0x00000020L |
38097 | #define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_StallOnTrans_MASK 0x00000040L |
38098 | #define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_StallOnTrans_MASK 0x00000080L |
38099 | #define RLC_UTCL1_STATUS_2__SPM_UTCL1_StallOnTrans_MASK 0x00000100L |
38100 | #define RLC_UTCL1_STATUS_2__RESERVED_MASK 0xFFFFFE00L |
38101 | //RLC_SPM_UTCL1_ERROR_1 |
38102 | #define RLC_SPM_UTCL1_ERROR_1__Translated_ReqError__SHIFT 0x0 |
38103 | #define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorVmid__SHIFT 0x2 |
38104 | #define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT 0x6 |
38105 | #define RLC_SPM_UTCL1_ERROR_1__Translated_ReqError_MASK 0x00000003L |
38106 | #define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorVmid_MASK 0x0000003CL |
38107 | #define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorAddr_MSB_MASK 0x000003C0L |
38108 | //RLC_SPM_UTCL1_ERROR_2 |
38109 | #define RLC_SPM_UTCL1_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT 0x0 |
38110 | #define RLC_SPM_UTCL1_ERROR_2__Translated_ReqErrorAddr_LSB_MASK 0xFFFFFFFFL |
38111 | //RLC_GPM_UTCL1_TH0_ERROR_1 |
38112 | #define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqError__SHIFT 0x0 |
38113 | #define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorVmid__SHIFT 0x2 |
38114 | #define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT 0x6 |
38115 | #define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqError_MASK 0x00000003L |
38116 | #define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorVmid_MASK 0x0000003CL |
38117 | #define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorAddr_MSB_MASK 0x000003C0L |
38118 | //RLC_GPM_UTCL1_TH0_ERROR_2 |
38119 | #define RLC_GPM_UTCL1_TH0_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT 0x0 |
38120 | #define RLC_GPM_UTCL1_TH0_ERROR_2__Translated_ReqErrorAddr_LSB_MASK 0xFFFFFFFFL |
38121 | //RLC_GPM_UTCL1_TH1_ERROR_1 |
38122 | #define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqError__SHIFT 0x0 |
38123 | #define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorVmid__SHIFT 0x2 |
38124 | #define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT 0x6 |
38125 | #define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqError_MASK 0x00000003L |
38126 | #define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorVmid_MASK 0x0000003CL |
38127 | #define RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorAddr_MSB_MASK 0x000003C0L |
38128 | //RLC_GPM_UTCL1_TH1_ERROR_2 |
38129 | #define RLC_GPM_UTCL1_TH1_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT 0x0 |
38130 | #define RLC_GPM_UTCL1_TH1_ERROR_2__Translated_ReqErrorAddr_LSB_MASK 0xFFFFFFFFL |
38131 | //RLC_GPM_UTCL1_TH2_ERROR_1 |
38132 | #define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqError__SHIFT 0x0 |
38133 | #define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorVmid__SHIFT 0x2 |
38134 | #define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT 0x6 |
38135 | #define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqError_MASK 0x00000003L |
38136 | #define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorVmid_MASK 0x0000003CL |
38137 | #define RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorAddr_MSB_MASK 0x000003C0L |
38138 | //RLC_GPM_UTCL1_TH2_ERROR_2 |
38139 | #define RLC_GPM_UTCL1_TH2_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT 0x0 |
38140 | #define RLC_GPM_UTCL1_TH2_ERROR_2__Translated_ReqErrorAddr_LSB_MASK 0xFFFFFFFFL |
38141 | //RLC_CGCG_CGLS_CTRL_3D |
38142 | #define RLC_CGCG_CGLS_CTRL_3D__CGCG_EN__SHIFT 0x0 |
38143 | #define RLC_CGCG_CGLS_CTRL_3D__CGLS_EN__SHIFT 0x1 |
38144 | #define RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT 0x2 |
38145 | #define RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT 0x8 |
38146 | #define RLC_CGCG_CGLS_CTRL_3D__CGCG_CONTROLLER__SHIFT 0x1b |
38147 | #define RLC_CGCG_CGLS_CTRL_3D__CGCG_REG_CTRL__SHIFT 0x1c |
38148 | #define RLC_CGCG_CGLS_CTRL_3D__SLEEP_MODE__SHIFT 0x1d |
38149 | #define RLC_CGCG_CGLS_CTRL_3D__SIM_SILICON_EN__SHIFT 0x1f |
38150 | #define RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK 0x00000001L |
38151 | #define RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK 0x00000002L |
38152 | #define RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY_MASK 0x000000FCL |
38153 | #define RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD_MASK 0x07FFFF00L |
38154 | #define RLC_CGCG_CGLS_CTRL_3D__CGCG_CONTROLLER_MASK 0x08000000L |
38155 | #define RLC_CGCG_CGLS_CTRL_3D__CGCG_REG_CTRL_MASK 0x10000000L |
38156 | #define RLC_CGCG_CGLS_CTRL_3D__SLEEP_MODE_MASK 0x60000000L |
38157 | #define RLC_CGCG_CGLS_CTRL_3D__SIM_SILICON_EN_MASK 0x80000000L |
38158 | //RLC_CGCG_RAMP_CTRL_3D |
38159 | #define RLC_CGCG_RAMP_CTRL_3D__DOWN_DIV_START_UNIT__SHIFT 0x0 |
38160 | #define RLC_CGCG_RAMP_CTRL_3D__DOWN_DIV_STEP_UNIT__SHIFT 0x4 |
38161 | #define RLC_CGCG_RAMP_CTRL_3D__UP_DIV_START_UNIT__SHIFT 0x8 |
38162 | #define RLC_CGCG_RAMP_CTRL_3D__UP_DIV_STEP_UNIT__SHIFT 0xc |
38163 | #define RLC_CGCG_RAMP_CTRL_3D__STEP_DELAY_CNT__SHIFT 0x10 |
38164 | #define RLC_CGCG_RAMP_CTRL_3D__STEP_DELAY_UNIT__SHIFT 0x1c |
38165 | #define RLC_CGCG_RAMP_CTRL_3D__DOWN_DIV_START_UNIT_MASK 0x0000000FL |
38166 | #define RLC_CGCG_RAMP_CTRL_3D__DOWN_DIV_STEP_UNIT_MASK 0x000000F0L |
38167 | #define RLC_CGCG_RAMP_CTRL_3D__UP_DIV_START_UNIT_MASK 0x00000F00L |
38168 | #define RLC_CGCG_RAMP_CTRL_3D__UP_DIV_STEP_UNIT_MASK 0x0000F000L |
38169 | #define RLC_CGCG_RAMP_CTRL_3D__STEP_DELAY_CNT_MASK 0x0FFF0000L |
38170 | #define RLC_CGCG_RAMP_CTRL_3D__STEP_DELAY_UNIT_MASK 0xF0000000L |
38171 | //RLC_SEMAPHORE_0 |
38172 | #define RLC_SEMAPHORE_0__CLIENT_ID__SHIFT 0x0 |
38173 | #define RLC_SEMAPHORE_0__RESERVED__SHIFT 0x5 |
38174 | #define RLC_SEMAPHORE_0__CLIENT_ID_MASK 0x0000001FL |
38175 | #define RLC_SEMAPHORE_0__RESERVED_MASK 0xFFFFFFE0L |
38176 | //RLC_SEMAPHORE_1 |
38177 | #define RLC_SEMAPHORE_1__CLIENT_ID__SHIFT 0x0 |
38178 | #define RLC_SEMAPHORE_1__RESERVED__SHIFT 0x5 |
38179 | #define RLC_SEMAPHORE_1__CLIENT_ID_MASK 0x0000001FL |
38180 | #define RLC_SEMAPHORE_1__RESERVED_MASK 0xFFFFFFE0L |
38181 | //RLC_SEMAPHORE_2 |
38182 | #define RLC_SEMAPHORE_2__CLIENT_ID__SHIFT 0x0 |
38183 | #define RLC_SEMAPHORE_2__RESERVED__SHIFT 0x5 |
38184 | #define RLC_SEMAPHORE_2__CLIENT_ID_MASK 0x0000001FL |
38185 | #define RLC_SEMAPHORE_2__RESERVED_MASK 0xFFFFFFE0L |
38186 | //RLC_SEMAPHORE_3 |
38187 | #define RLC_SEMAPHORE_3__CLIENT_ID__SHIFT 0x0 |
38188 | #define RLC_SEMAPHORE_3__RESERVED__SHIFT 0x5 |
38189 | #define RLC_SEMAPHORE_3__CLIENT_ID_MASK 0x0000001FL |
38190 | #define RLC_SEMAPHORE_3__RESERVED_MASK 0xFFFFFFE0L |
38191 | //RLC_PACE_INT_STAT |
38192 | #define RLC_PACE_INT_STAT__STATUS__SHIFT 0x0 |
38193 | #define RLC_PACE_INT_STAT__STATUS_MASK 0xFFFFFFFFL |
38194 | //RLC_UTCL1_STATUS |
38195 | #define RLC_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 |
38196 | #define RLC_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 |
38197 | #define RLC_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 |
38198 | #define RLC_UTCL1_STATUS__RESERVED__SHIFT 0x3 |
38199 | #define RLC_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8 |
38200 | #define RLC_UTCL1_STATUS__RESERVED_1__SHIFT 0xe |
38201 | #define RLC_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10 |
38202 | #define RLC_UTCL1_STATUS__RESERVED_2__SHIFT 0x16 |
38203 | #define RLC_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18 |
38204 | #define RLC_UTCL1_STATUS__RESERVED_3__SHIFT 0x1e |
38205 | #define RLC_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L |
38206 | #define RLC_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L |
38207 | #define RLC_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L |
38208 | #define RLC_UTCL1_STATUS__RESERVED_MASK 0x000000F8L |
38209 | #define RLC_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L |
38210 | #define RLC_UTCL1_STATUS__RESERVED_1_MASK 0x0000C000L |
38211 | #define RLC_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L |
38212 | #define RLC_UTCL1_STATUS__RESERVED_2_MASK 0x00C00000L |
38213 | #define RLC_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L |
38214 | #define RLC_UTCL1_STATUS__RESERVED_3_MASK 0xC0000000L |
38215 | //RLC_R2I_CNTL_0 |
38216 | #define RLC_R2I_CNTL_0__Data__SHIFT 0x0 |
38217 | #define RLC_R2I_CNTL_0__Data_MASK 0xFFFFFFFFL |
38218 | //RLC_R2I_CNTL_1 |
38219 | #define RLC_R2I_CNTL_1__Data__SHIFT 0x0 |
38220 | #define RLC_R2I_CNTL_1__Data_MASK 0xFFFFFFFFL |
38221 | //RLC_R2I_CNTL_2 |
38222 | #define RLC_R2I_CNTL_2__Data__SHIFT 0x0 |
38223 | #define RLC_R2I_CNTL_2__Data_MASK 0xFFFFFFFFL |
38224 | //RLC_R2I_CNTL_3 |
38225 | #define RLC_R2I_CNTL_3__Data__SHIFT 0x0 |
38226 | #define RLC_R2I_CNTL_3__Data_MASK 0xFFFFFFFFL |
38227 | //RLC_GPM_INT_STAT_TH0 |
38228 | #define RLC_GPM_INT_STAT_TH0__STATUS__SHIFT 0x0 |
38229 | #define RLC_GPM_INT_STAT_TH0__STATUS_MASK 0xFFFFFFFFL |
38230 | //RLC_GPM_GENERAL_13 |
38231 | #define RLC_GPM_GENERAL_13__DATA__SHIFT 0x0 |
38232 | #define RLC_GPM_GENERAL_13__DATA_MASK 0xFFFFFFFFL |
38233 | //RLC_GPM_GENERAL_14 |
38234 | #define RLC_GPM_GENERAL_14__DATA__SHIFT 0x0 |
38235 | #define RLC_GPM_GENERAL_14__DATA_MASK 0xFFFFFFFFL |
38236 | //RLC_GPM_GENERAL_15 |
38237 | #define RLC_GPM_GENERAL_15__DATA__SHIFT 0x0 |
38238 | #define RLC_GPM_GENERAL_15__DATA_MASK 0xFFFFFFFFL |
38239 | //RLC_CAPTURE_GPU_CLOCK_COUNT_1 |
38240 | #define RLC_CAPTURE_GPU_CLOCK_COUNT_1__CAPTURE__SHIFT 0x0 |
38241 | #define RLC_CAPTURE_GPU_CLOCK_COUNT_1__RESERVED__SHIFT 0x1 |
38242 | #define RLC_CAPTURE_GPU_CLOCK_COUNT_1__CAPTURE_MASK 0x00000001L |
38243 | #define RLC_CAPTURE_GPU_CLOCK_COUNT_1__RESERVED_MASK 0xFFFFFFFEL |
38244 | //RLC_GPU_CLOCK_COUNT_LSB_2 |
38245 | #define RLC_GPU_CLOCK_COUNT_LSB_2__GPU_CLOCKS_LSB__SHIFT 0x0 |
38246 | #define RLC_GPU_CLOCK_COUNT_LSB_2__GPU_CLOCKS_LSB_MASK 0xFFFFFFFFL |
38247 | //RLC_GPU_CLOCK_COUNT_MSB_2 |
38248 | #define RLC_GPU_CLOCK_COUNT_MSB_2__GPU_CLOCKS_MSB__SHIFT 0x0 |
38249 | #define RLC_GPU_CLOCK_COUNT_MSB_2__GPU_CLOCKS_MSB_MASK 0xFFFFFFFFL |
38250 | //RLC_PACE_INT_DISABLE |
38251 | #define RLC_PACE_INT_DISABLE__DISABLE_INT__SHIFT 0x0 |
38252 | #define RLC_PACE_INT_DISABLE__DISABLE_INT_MASK 0xFFFFFFFFL |
38253 | //RLC_CAPTURE_GPU_CLOCK_COUNT_2 |
38254 | #define RLC_CAPTURE_GPU_CLOCK_COUNT_2__CAPTURE__SHIFT 0x0 |
38255 | #define RLC_CAPTURE_GPU_CLOCK_COUNT_2__RESERVED__SHIFT 0x1 |
38256 | #define RLC_CAPTURE_GPU_CLOCK_COUNT_2__CAPTURE_MASK 0x00000001L |
38257 | #define RLC_CAPTURE_GPU_CLOCK_COUNT_2__RESERVED_MASK 0xFFFFFFFEL |
38258 | //RLC_RLCV_DOORBELL_RANGE |
38259 | #define RLC_RLCV_DOORBELL_RANGE__LOWER_ADDR_RESERVED__SHIFT 0x0 |
38260 | #define RLC_RLCV_DOORBELL_RANGE__LOWER_ADDR__SHIFT 0x2 |
38261 | #define RLC_RLCV_DOORBELL_RANGE__UPPER_ADDR_RESERVED__SHIFT 0x10 |
38262 | #define RLC_RLCV_DOORBELL_RANGE__UPPER_ADDR__SHIFT 0x12 |
38263 | #define RLC_RLCV_DOORBELL_RANGE__LOWER_ADDR_RESERVED_MASK 0x00000003L |
38264 | #define RLC_RLCV_DOORBELL_RANGE__LOWER_ADDR_MASK 0x00000FFCL |
38265 | #define RLC_RLCV_DOORBELL_RANGE__UPPER_ADDR_RESERVED_MASK 0x00030000L |
38266 | #define RLC_RLCV_DOORBELL_RANGE__UPPER_ADDR_MASK 0x0FFC0000L |
38267 | //RLC_RLCV_DOORBELL_CNTL |
38268 | #define RLC_RLCV_DOORBELL_CNTL__DOORBELL_0_MODE__SHIFT 0x0 |
38269 | #define RLC_RLCV_DOORBELL_CNTL__DOORBELL_1_MODE__SHIFT 0x2 |
38270 | #define RLC_RLCV_DOORBELL_CNTL__DOORBELL_2_MODE__SHIFT 0x4 |
38271 | #define RLC_RLCV_DOORBELL_CNTL__DOORBELL_3_MODE__SHIFT 0x6 |
38272 | #define RLC_RLCV_DOORBELL_CNTL__DOORBELL_ID__SHIFT 0x10 |
38273 | #define RLC_RLCV_DOORBELL_CNTL__DOORBELL_ID_EN__SHIFT 0x15 |
38274 | #define RLC_RLCV_DOORBELL_CNTL__DOORBELL_0_MODE_MASK 0x00000003L |
38275 | #define RLC_RLCV_DOORBELL_CNTL__DOORBELL_1_MODE_MASK 0x0000000CL |
38276 | #define RLC_RLCV_DOORBELL_CNTL__DOORBELL_2_MODE_MASK 0x00000030L |
38277 | #define RLC_RLCV_DOORBELL_CNTL__DOORBELL_3_MODE_MASK 0x000000C0L |
38278 | #define RLC_RLCV_DOORBELL_CNTL__DOORBELL_ID_MASK 0x001F0000L |
38279 | #define RLC_RLCV_DOORBELL_CNTL__DOORBELL_ID_EN_MASK 0x00200000L |
38280 | //RLC_RLCV_DOORBELL_STAT |
38281 | #define RLC_RLCV_DOORBELL_STAT__DOORBELL_0_VALID__SHIFT 0x0 |
38282 | #define RLC_RLCV_DOORBELL_STAT__DOORBELL_1_VALID__SHIFT 0x1 |
38283 | #define RLC_RLCV_DOORBELL_STAT__DOORBELL_2_VALID__SHIFT 0x2 |
38284 | #define RLC_RLCV_DOORBELL_STAT__DOORBELL_3_VALID__SHIFT 0x3 |
38285 | #define RLC_RLCV_DOORBELL_STAT__DOORBELL_0_VALID_MASK 0x00000001L |
38286 | #define RLC_RLCV_DOORBELL_STAT__DOORBELL_1_VALID_MASK 0x00000002L |
38287 | #define RLC_RLCV_DOORBELL_STAT__DOORBELL_2_VALID_MASK 0x00000004L |
38288 | #define RLC_RLCV_DOORBELL_STAT__DOORBELL_3_VALID_MASK 0x00000008L |
38289 | //RLC_RLCV_DOORBELL_0_DATA_LO |
38290 | #define RLC_RLCV_DOORBELL_0_DATA_LO__DATA__SHIFT 0x0 |
38291 | #define RLC_RLCV_DOORBELL_0_DATA_LO__DATA_MASK 0xFFFFFFFFL |
38292 | //RLC_RLCV_DOORBELL_0_DATA_HI |
38293 | #define RLC_RLCV_DOORBELL_0_DATA_HI__DATA__SHIFT 0x0 |
38294 | #define RLC_RLCV_DOORBELL_0_DATA_HI__DATA_MASK 0xFFFFFFFFL |
38295 | //RLC_RLCV_DOORBELL_1_DATA_LO |
38296 | #define RLC_RLCV_DOORBELL_1_DATA_LO__DATA__SHIFT 0x0 |
38297 | #define RLC_RLCV_DOORBELL_1_DATA_LO__DATA_MASK 0xFFFFFFFFL |
38298 | //RLC_RLCV_DOORBELL_1_DATA_HI |
38299 | #define RLC_RLCV_DOORBELL_1_DATA_HI__DATA__SHIFT 0x0 |
38300 | #define RLC_RLCV_DOORBELL_1_DATA_HI__DATA_MASK 0xFFFFFFFFL |
38301 | //RLC_RLCV_DOORBELL_2_DATA_LO |
38302 | #define RLC_RLCV_DOORBELL_2_DATA_LO__DATA__SHIFT 0x0 |
38303 | #define RLC_RLCV_DOORBELL_2_DATA_LO__DATA_MASK 0xFFFFFFFFL |
38304 | //RLC_RLCV_DOORBELL_2_DATA_HI |
38305 | #define RLC_RLCV_DOORBELL_2_DATA_HI__DATA__SHIFT 0x0 |
38306 | #define RLC_RLCV_DOORBELL_2_DATA_HI__DATA_MASK 0xFFFFFFFFL |
38307 | //RLC_RLCV_DOORBELL_3_DATA_LO |
38308 | #define RLC_RLCV_DOORBELL_3_DATA_LO__DATA__SHIFT 0x0 |
38309 | #define RLC_RLCV_DOORBELL_3_DATA_LO__DATA_MASK 0xFFFFFFFFL |
38310 | //RLC_RLCV_DOORBELL_3_DATA_HI |
38311 | #define RLC_RLCV_DOORBELL_3_DATA_HI__DATA__SHIFT 0x0 |
38312 | #define RLC_RLCV_DOORBELL_3_DATA_HI__DATA_MASK 0xFFFFFFFFL |
38313 | //RLC_GPU_CLOCK_COUNT_LSB_1 |
38314 | #define RLC_GPU_CLOCK_COUNT_LSB_1__GPU_CLOCKS_LSB__SHIFT 0x0 |
38315 | #define RLC_GPU_CLOCK_COUNT_LSB_1__GPU_CLOCKS_LSB_MASK 0xFFFFFFFFL |
38316 | //RLC_GPU_CLOCK_COUNT_MSB_1 |
38317 | #define RLC_GPU_CLOCK_COUNT_MSB_1__GPU_CLOCKS_MSB__SHIFT 0x0 |
38318 | #define RLC_GPU_CLOCK_COUNT_MSB_1__GPU_CLOCKS_MSB_MASK 0xFFFFFFFFL |
38319 | //RLC_RLCV_SPARE_INT |
38320 | #define RLC_RLCV_SPARE_INT__INTERRUPT__SHIFT 0x0 |
38321 | #define RLC_RLCV_SPARE_INT__RESERVED__SHIFT 0x1 |
38322 | #define RLC_RLCV_SPARE_INT__INTERRUPT_MASK 0x00000001L |
38323 | #define RLC_RLCV_SPARE_INT__RESERVED_MASK 0xFFFFFFFEL |
38324 | //RLC_FIREWALL_VIOLATION |
38325 | #define RLC_FIREWALL_VIOLATION__ADDR__SHIFT 0x0 |
38326 | #define RLC_FIREWALL_VIOLATION__ADDR_MASK 0xFFFFFFFFL |
38327 | //RLC_PACE_TIMER_INT_0 |
38328 | #define RLC_PACE_TIMER_INT_0__TIMER__SHIFT 0x0 |
38329 | #define RLC_PACE_TIMER_INT_0__TIMER_MASK 0xFFFFFFFFL |
38330 | //RLC_PACE_TIMER_INT_1 |
38331 | #define RLC_PACE_TIMER_INT_1__TIMER__SHIFT 0x0 |
38332 | #define RLC_PACE_TIMER_INT_1__TIMER_MASK 0xFFFFFFFFL |
38333 | //RLC_PACE_TIMER_CTRL |
38334 | #define RLC_PACE_TIMER_CTRL__TIMER_0_EN__SHIFT 0x0 |
38335 | #define RLC_PACE_TIMER_CTRL__TIMER_1_EN__SHIFT 0x1 |
38336 | #define RLC_PACE_TIMER_CTRL__TIMER_0_AUTO_REARM__SHIFT 0x2 |
38337 | #define RLC_PACE_TIMER_CTRL__TIMER_1_AUTO_REARM__SHIFT 0x3 |
38338 | #define RLC_PACE_TIMER_CTRL__TIMER_0_INT_CLEAR__SHIFT 0x4 |
38339 | #define RLC_PACE_TIMER_CTRL__TIMER_1_INT_CLEAR__SHIFT 0x5 |
38340 | #define RLC_PACE_TIMER_CTRL__RESERVED__SHIFT 0x6 |
38341 | #define RLC_PACE_TIMER_CTRL__TIMER_0_EN_MASK 0x00000001L |
38342 | #define RLC_PACE_TIMER_CTRL__TIMER_1_EN_MASK 0x00000002L |
38343 | #define RLC_PACE_TIMER_CTRL__TIMER_0_AUTO_REARM_MASK 0x00000004L |
38344 | #define RLC_PACE_TIMER_CTRL__TIMER_1_AUTO_REARM_MASK 0x00000008L |
38345 | #define RLC_PACE_TIMER_CTRL__TIMER_0_INT_CLEAR_MASK 0x00000010L |
38346 | #define RLC_PACE_TIMER_CTRL__TIMER_1_INT_CLEAR_MASK 0x00000020L |
38347 | #define RLC_PACE_TIMER_CTRL__RESERVED_MASK 0xFFFFFFC0L |
38348 | //RLC_SMU_CLK_REQ |
38349 | #define RLC_SMU_CLK_REQ__VALID__SHIFT 0x0 |
38350 | #define RLC_SMU_CLK_REQ__VALID_MASK 0x00000001L |
38351 | //RLC_CP_STAT_INVAL_STAT |
38352 | #define RLC_CP_STAT_INVAL_STAT__CPG_STAT_INVAL_PEND__SHIFT 0x0 |
38353 | #define RLC_CP_STAT_INVAL_STAT__CPC_STAT_INVAL_PEND__SHIFT 0x1 |
38354 | #define RLC_CP_STAT_INVAL_STAT__CPF_STAT_INVAL_PEND__SHIFT 0x2 |
38355 | #define RLC_CP_STAT_INVAL_STAT__CPG_STAT_INVAL_PEND_CHANGED__SHIFT 0x3 |
38356 | #define RLC_CP_STAT_INVAL_STAT__CPC_STAT_INVAL_PEND_CHANGED__SHIFT 0x4 |
38357 | #define RLC_CP_STAT_INVAL_STAT__CPF_STAT_INVAL_PEND_CHANGED__SHIFT 0x5 |
38358 | #define RLC_CP_STAT_INVAL_STAT__CPG_STAT_INVAL_PEND_MASK 0x00000001L |
38359 | #define RLC_CP_STAT_INVAL_STAT__CPC_STAT_INVAL_PEND_MASK 0x00000002L |
38360 | #define RLC_CP_STAT_INVAL_STAT__CPF_STAT_INVAL_PEND_MASK 0x00000004L |
38361 | #define RLC_CP_STAT_INVAL_STAT__CPG_STAT_INVAL_PEND_CHANGED_MASK 0x00000008L |
38362 | #define RLC_CP_STAT_INVAL_STAT__CPC_STAT_INVAL_PEND_CHANGED_MASK 0x00000010L |
38363 | #define RLC_CP_STAT_INVAL_STAT__CPF_STAT_INVAL_PEND_CHANGED_MASK 0x00000020L |
38364 | //RLC_CP_STAT_INVAL_CTRL |
38365 | #define RLC_CP_STAT_INVAL_CTRL__CPG_STAT_INVAL_PEND_EN__SHIFT 0x0 |
38366 | #define RLC_CP_STAT_INVAL_CTRL__CPC_STAT_INVAL_PEND_EN__SHIFT 0x1 |
38367 | #define RLC_CP_STAT_INVAL_CTRL__CPF_STAT_INVAL_PEND_EN__SHIFT 0x2 |
38368 | #define RLC_CP_STAT_INVAL_CTRL__CPG_STAT_INVAL_PEND_EN_MASK 0x00000001L |
38369 | #define RLC_CP_STAT_INVAL_CTRL__CPC_STAT_INVAL_PEND_EN_MASK 0x00000002L |
38370 | #define RLC_CP_STAT_INVAL_CTRL__CPF_STAT_INVAL_PEND_EN_MASK 0x00000004L |
38371 | //RLC_SPARE |
38372 | #define RLC_SPARE__SPARE__SHIFT 0x0 |
38373 | #define RLC_SPARE__SPARE_MASK 0xFFFFFFFFL |
38374 | //RLC_SPP_CTRL |
38375 | #define RLC_SPP_CTRL__ENABLE__SHIFT 0x0 |
38376 | #define RLC_SPP_CTRL__ENABLE_PPROF__SHIFT 0x1 |
38377 | #define RLC_SPP_CTRL__ENABLE_PWR_OPT__SHIFT 0x2 |
38378 | #define RLC_SPP_CTRL__PAUSE__SHIFT 0x3 |
38379 | #define RLC_SPP_CTRL__ENABLE_MASK 0x00000001L |
38380 | #define RLC_SPP_CTRL__ENABLE_PPROF_MASK 0x00000002L |
38381 | #define RLC_SPP_CTRL__ENABLE_PWR_OPT_MASK 0x00000004L |
38382 | #define RLC_SPP_CTRL__PAUSE_MASK 0x00000008L |
38383 | //RLC_SPP_SHADER_PROFILE_EN |
38384 | #define RLC_SPP_SHADER_PROFILE_EN__PS_ENABLE__SHIFT 0x0 |
38385 | #define RLC_SPP_SHADER_PROFILE_EN__RESERVED_1__SHIFT 0x1 |
38386 | #define RLC_SPP_SHADER_PROFILE_EN__GS_ENABLE__SHIFT 0x2 |
38387 | #define RLC_SPP_SHADER_PROFILE_EN__HS_ENABLE__SHIFT 0x3 |
38388 | #define RLC_SPP_SHADER_PROFILE_EN__CSG_ENABLE__SHIFT 0x4 |
38389 | #define RLC_SPP_SHADER_PROFILE_EN__CS_ENABLE__SHIFT 0x5 |
38390 | #define RLC_SPP_SHADER_PROFILE_EN__PS_STOP_CONDITION__SHIFT 0x6 |
38391 | #define RLC_SPP_SHADER_PROFILE_EN__RESERVED_7__SHIFT 0x7 |
38392 | #define RLC_SPP_SHADER_PROFILE_EN__GS_STOP_CONDITION__SHIFT 0x8 |
38393 | #define RLC_SPP_SHADER_PROFILE_EN__HS_STOP_CONDITION__SHIFT 0x9 |
38394 | #define RLC_SPP_SHADER_PROFILE_EN__CSG_STOP_CONDITION__SHIFT 0xa |
38395 | #define RLC_SPP_SHADER_PROFILE_EN__CS_STOP_CONDITION__SHIFT 0xb |
38396 | #define RLC_SPP_SHADER_PROFILE_EN__PS_START_CONDITION__SHIFT 0xc |
38397 | #define RLC_SPP_SHADER_PROFILE_EN__CS_START_CONDITION__SHIFT 0xd |
38398 | #define RLC_SPP_SHADER_PROFILE_EN__FORCE_MISS__SHIFT 0xe |
38399 | #define RLC_SPP_SHADER_PROFILE_EN__FORCE_UNLOCKED__SHIFT 0xf |
38400 | #define RLC_SPP_SHADER_PROFILE_EN__ENABLE_PROF_INFO_LOCK__SHIFT 0x10 |
38401 | #define RLC_SPP_SHADER_PROFILE_EN__PS_ENABLE_MASK 0x00000001L |
38402 | #define RLC_SPP_SHADER_PROFILE_EN__RESERVED_1_MASK 0x00000002L |
38403 | #define RLC_SPP_SHADER_PROFILE_EN__GS_ENABLE_MASK 0x00000004L |
38404 | #define RLC_SPP_SHADER_PROFILE_EN__HS_ENABLE_MASK 0x00000008L |
38405 | #define RLC_SPP_SHADER_PROFILE_EN__CSG_ENABLE_MASK 0x00000010L |
38406 | #define RLC_SPP_SHADER_PROFILE_EN__CS_ENABLE_MASK 0x00000020L |
38407 | #define RLC_SPP_SHADER_PROFILE_EN__PS_STOP_CONDITION_MASK 0x00000040L |
38408 | #define RLC_SPP_SHADER_PROFILE_EN__RESERVED_7_MASK 0x00000080L |
38409 | #define RLC_SPP_SHADER_PROFILE_EN__GS_STOP_CONDITION_MASK 0x00000100L |
38410 | #define RLC_SPP_SHADER_PROFILE_EN__HS_STOP_CONDITION_MASK 0x00000200L |
38411 | #define RLC_SPP_SHADER_PROFILE_EN__CSG_STOP_CONDITION_MASK 0x00000400L |
38412 | #define RLC_SPP_SHADER_PROFILE_EN__CS_STOP_CONDITION_MASK 0x00000800L |
38413 | #define RLC_SPP_SHADER_PROFILE_EN__PS_START_CONDITION_MASK 0x00001000L |
38414 | #define RLC_SPP_SHADER_PROFILE_EN__CS_START_CONDITION_MASK 0x00002000L |
38415 | #define RLC_SPP_SHADER_PROFILE_EN__FORCE_MISS_MASK 0x00004000L |
38416 | #define RLC_SPP_SHADER_PROFILE_EN__FORCE_UNLOCKED_MASK 0x00008000L |
38417 | #define RLC_SPP_SHADER_PROFILE_EN__ENABLE_PROF_INFO_LOCK_MASK 0x00010000L |
38418 | //RLC_SPP_SSF_CAPTURE_EN |
38419 | #define RLC_SPP_SSF_CAPTURE_EN__PS_ENABLE__SHIFT 0x0 |
38420 | #define RLC_SPP_SSF_CAPTURE_EN__RESERVED_1__SHIFT 0x1 |
38421 | #define RLC_SPP_SSF_CAPTURE_EN__GS_ENABLE__SHIFT 0x2 |
38422 | #define RLC_SPP_SSF_CAPTURE_EN__HS_ENABLE__SHIFT 0x3 |
38423 | #define RLC_SPP_SSF_CAPTURE_EN__CSG_ENABLE__SHIFT 0x4 |
38424 | #define RLC_SPP_SSF_CAPTURE_EN__CS_ENABLE__SHIFT 0x5 |
38425 | #define RLC_SPP_SSF_CAPTURE_EN__PS_ENABLE_MASK 0x00000001L |
38426 | #define RLC_SPP_SSF_CAPTURE_EN__RESERVED_1_MASK 0x00000002L |
38427 | #define RLC_SPP_SSF_CAPTURE_EN__GS_ENABLE_MASK 0x00000004L |
38428 | #define RLC_SPP_SSF_CAPTURE_EN__HS_ENABLE_MASK 0x00000008L |
38429 | #define RLC_SPP_SSF_CAPTURE_EN__CSG_ENABLE_MASK 0x00000010L |
38430 | #define RLC_SPP_SSF_CAPTURE_EN__CS_ENABLE_MASK 0x00000020L |
38431 | //RLC_SPP_SSF_THRESHOLD_0 |
38432 | #define RLC_SPP_SSF_THRESHOLD_0__PS_THRESHOLD__SHIFT 0x0 |
38433 | #define RLC_SPP_SSF_THRESHOLD_0__RESERVED__SHIFT 0x10 |
38434 | #define RLC_SPP_SSF_THRESHOLD_0__PS_THRESHOLD_MASK 0x0000FFFFL |
38435 | #define RLC_SPP_SSF_THRESHOLD_0__RESERVED_MASK 0xFFFF0000L |
38436 | //RLC_SPP_SSF_THRESHOLD_1 |
38437 | #define RLC_SPP_SSF_THRESHOLD_1__GS_THRESHOLD__SHIFT 0x0 |
38438 | #define RLC_SPP_SSF_THRESHOLD_1__HS_THRESHOLD__SHIFT 0x10 |
38439 | #define RLC_SPP_SSF_THRESHOLD_1__GS_THRESHOLD_MASK 0x0000FFFFL |
38440 | #define RLC_SPP_SSF_THRESHOLD_1__HS_THRESHOLD_MASK 0xFFFF0000L |
38441 | //RLC_SPP_SSF_THRESHOLD_2 |
38442 | #define RLC_SPP_SSF_THRESHOLD_2__CSG_THRESHOLD__SHIFT 0x0 |
38443 | #define RLC_SPP_SSF_THRESHOLD_2__CS_THRESHOLD__SHIFT 0x10 |
38444 | #define RLC_SPP_SSF_THRESHOLD_2__CSG_THRESHOLD_MASK 0x0000FFFFL |
38445 | #define RLC_SPP_SSF_THRESHOLD_2__CS_THRESHOLD_MASK 0xFFFF0000L |
38446 | //RLC_SPP_INFLIGHT_RD_ADDR |
38447 | #define RLC_SPP_INFLIGHT_RD_ADDR__ADDR__SHIFT 0x0 |
38448 | #define RLC_SPP_INFLIGHT_RD_ADDR__ADDR_MASK 0x0000001FL |
38449 | //RLC_SPP_INFLIGHT_RD_DATA |
38450 | #define RLC_SPP_INFLIGHT_RD_DATA__DATA__SHIFT 0x0 |
38451 | #define RLC_SPP_INFLIGHT_RD_DATA__DATA_MASK 0xFFFFFFFFL |
38452 | //RLC_SPP_PROF_INFO_1 |
38453 | #define RLC_SPP_PROF_INFO_1__SH_ID__SHIFT 0x0 |
38454 | #define RLC_SPP_PROF_INFO_1__SH_ID_MASK 0xFFFFFFFFL |
38455 | //RLC_SPP_PROF_INFO_2 |
38456 | #define RLC_SPP_PROF_INFO_2__SH_TYPE__SHIFT 0x0 |
38457 | #define RLC_SPP_PROF_INFO_2__CAM_HIT__SHIFT 0x4 |
38458 | #define RLC_SPP_PROF_INFO_2__CAM_LOCK__SHIFT 0x5 |
38459 | #define RLC_SPP_PROF_INFO_2__CAM_CONFLICT__SHIFT 0x6 |
38460 | #define RLC_SPP_PROF_INFO_2__SH_TYPE_MASK 0x0000000FL |
38461 | #define RLC_SPP_PROF_INFO_2__CAM_HIT_MASK 0x00000010L |
38462 | #define RLC_SPP_PROF_INFO_2__CAM_LOCK_MASK 0x00000020L |
38463 | #define RLC_SPP_PROF_INFO_2__CAM_CONFLICT_MASK 0x00000040L |
38464 | //RLC_SPP_GLOBAL_SH_ID |
38465 | #define RLC_SPP_GLOBAL_SH_ID__SH_ID__SHIFT 0x0 |
38466 | #define RLC_SPP_GLOBAL_SH_ID__SH_ID_MASK 0xFFFFFFFFL |
38467 | //RLC_SPP_GLOBAL_SH_ID_VALID |
38468 | #define RLC_SPP_GLOBAL_SH_ID_VALID__VALID__SHIFT 0x0 |
38469 | #define RLC_SPP_GLOBAL_SH_ID_VALID__VALID_MASK 0x00000001L |
38470 | //RLC_SPP_STATUS |
38471 | #define RLC_SPP_STATUS__RESERVED_0__SHIFT 0x0 |
38472 | #define RLC_SPP_STATUS__SSF_BUSY__SHIFT 0x1 |
38473 | #define RLC_SPP_STATUS__EVENT_ARB_BUSY__SHIFT 0x2 |
38474 | #define RLC_SPP_STATUS__SPP_BUSY__SHIFT 0x1f |
38475 | #define RLC_SPP_STATUS__RESERVED_0_MASK 0x00000001L |
38476 | #define RLC_SPP_STATUS__SSF_BUSY_MASK 0x00000002L |
38477 | #define RLC_SPP_STATUS__EVENT_ARB_BUSY_MASK 0x00000004L |
38478 | #define RLC_SPP_STATUS__SPP_BUSY_MASK 0x80000000L |
38479 | //RLC_SPP_PVT_STAT_0 |
38480 | #define RLC_SPP_PVT_STAT_0__LEVEL_0_COUNTER__SHIFT 0x0 |
38481 | #define RLC_SPP_PVT_STAT_0__LEVEL_1_COUNTER__SHIFT 0x8 |
38482 | #define RLC_SPP_PVT_STAT_0__LEVEL_2_COUNTER__SHIFT 0x10 |
38483 | #define RLC_SPP_PVT_STAT_0__LEVEL_3_COUNTER__SHIFT 0x18 |
38484 | #define RLC_SPP_PVT_STAT_0__LEVEL_0_COUNTER_MASK 0x000000FFL |
38485 | #define RLC_SPP_PVT_STAT_0__LEVEL_1_COUNTER_MASK 0x0000FF00L |
38486 | #define RLC_SPP_PVT_STAT_0__LEVEL_2_COUNTER_MASK 0x00FF0000L |
38487 | #define RLC_SPP_PVT_STAT_0__LEVEL_3_COUNTER_MASK 0xFF000000L |
38488 | //RLC_SPP_PVT_STAT_1 |
38489 | #define RLC_SPP_PVT_STAT_1__LEVEL_4_COUNTER__SHIFT 0x0 |
38490 | #define RLC_SPP_PVT_STAT_1__LEVEL_5_COUNTER__SHIFT 0x8 |
38491 | #define RLC_SPP_PVT_STAT_1__LEVEL_6_COUNTER__SHIFT 0x10 |
38492 | #define RLC_SPP_PVT_STAT_1__LEVEL_7_COUNTER__SHIFT 0x18 |
38493 | #define RLC_SPP_PVT_STAT_1__LEVEL_4_COUNTER_MASK 0x000000FFL |
38494 | #define RLC_SPP_PVT_STAT_1__LEVEL_5_COUNTER_MASK 0x0000FF00L |
38495 | #define RLC_SPP_PVT_STAT_1__LEVEL_6_COUNTER_MASK 0x00FF0000L |
38496 | #define RLC_SPP_PVT_STAT_1__LEVEL_7_COUNTER_MASK 0xFF000000L |
38497 | //RLC_SPP_PVT_STAT_2 |
38498 | #define RLC_SPP_PVT_STAT_2__LEVEL_8_COUNTER__SHIFT 0x0 |
38499 | #define RLC_SPP_PVT_STAT_2__LEVEL_9_COUNTER__SHIFT 0x8 |
38500 | #define RLC_SPP_PVT_STAT_2__LEVEL_10_COUNTER__SHIFT 0x10 |
38501 | #define RLC_SPP_PVT_STAT_2__LEVEL_11_COUNTER__SHIFT 0x18 |
38502 | #define RLC_SPP_PVT_STAT_2__LEVEL_8_COUNTER_MASK 0x000000FFL |
38503 | #define RLC_SPP_PVT_STAT_2__LEVEL_9_COUNTER_MASK 0x0000FF00L |
38504 | #define RLC_SPP_PVT_STAT_2__LEVEL_10_COUNTER_MASK 0x00FF0000L |
38505 | #define RLC_SPP_PVT_STAT_2__LEVEL_11_COUNTER_MASK 0xFF000000L |
38506 | //RLC_SPP_PVT_STAT_3 |
38507 | #define RLC_SPP_PVT_STAT_3__LEVEL_12_COUNTER__SHIFT 0x0 |
38508 | #define RLC_SPP_PVT_STAT_3__LEVEL_13_COUNTER__SHIFT 0x8 |
38509 | #define RLC_SPP_PVT_STAT_3__LEVEL_14_COUNTER__SHIFT 0x10 |
38510 | #define RLC_SPP_PVT_STAT_3__LEVEL_15_COUNTER__SHIFT 0x18 |
38511 | #define RLC_SPP_PVT_STAT_3__LEVEL_12_COUNTER_MASK 0x000000FFL |
38512 | #define RLC_SPP_PVT_STAT_3__LEVEL_13_COUNTER_MASK 0x0000FF00L |
38513 | #define RLC_SPP_PVT_STAT_3__LEVEL_14_COUNTER_MASK 0x00FF0000L |
38514 | #define RLC_SPP_PVT_STAT_3__LEVEL_15_COUNTER_MASK 0xFF000000L |
38515 | //RLC_SPP_PVT_LEVEL_MAX |
38516 | #define RLC_SPP_PVT_LEVEL_MAX__LEVEL__SHIFT 0x0 |
38517 | #define RLC_SPP_PVT_LEVEL_MAX__LEVEL_MASK 0x0000000FL |
38518 | //RLC_SPP_STALL_STATE_UPDATE |
38519 | #define RLC_SPP_STALL_STATE_UPDATE__STALL__SHIFT 0x0 |
38520 | #define RLC_SPP_STALL_STATE_UPDATE__ENABLE__SHIFT 0x1 |
38521 | #define RLC_SPP_STALL_STATE_UPDATE__STALL_MASK 0x00000001L |
38522 | #define RLC_SPP_STALL_STATE_UPDATE__ENABLE_MASK 0x00000002L |
38523 | //RLC_SPP_PBB_INFO |
38524 | #define RLC_SPP_PBB_INFO__PIPE0_OVERRIDE__SHIFT 0x0 |
38525 | #define RLC_SPP_PBB_INFO__PIPE0_OVERRIDE_VALID__SHIFT 0x1 |
38526 | #define RLC_SPP_PBB_INFO__PIPE1_OVERRIDE__SHIFT 0x2 |
38527 | #define RLC_SPP_PBB_INFO__PIPE1_OVERRIDE_VALID__SHIFT 0x3 |
38528 | #define RLC_SPP_PBB_INFO__PIPE0_OVERRIDE_MASK 0x00000001L |
38529 | #define RLC_SPP_PBB_INFO__PIPE0_OVERRIDE_VALID_MASK 0x00000002L |
38530 | #define RLC_SPP_PBB_INFO__PIPE1_OVERRIDE_MASK 0x00000004L |
38531 | #define RLC_SPP_PBB_INFO__PIPE1_OVERRIDE_VALID_MASK 0x00000008L |
38532 | //RLC_SPP_RESET |
38533 | #define RLC_SPP_RESET__SSF_RESET__SHIFT 0x0 |
38534 | #define RLC_SPP_RESET__EVENT_ARB_RESET__SHIFT 0x1 |
38535 | #define RLC_SPP_RESET__CAM_RESET__SHIFT 0x2 |
38536 | #define RLC_SPP_RESET__PVT_RESET__SHIFT 0x3 |
38537 | #define RLC_SPP_RESET__SSF_RESET_MASK 0x00000001L |
38538 | #define RLC_SPP_RESET__EVENT_ARB_RESET_MASK 0x00000002L |
38539 | #define RLC_SPP_RESET__CAM_RESET_MASK 0x00000004L |
38540 | #define RLC_SPP_RESET__PVT_RESET_MASK 0x00000008L |
38541 | //RLC_RLCP_DOORBELL_RANGE |
38542 | #define RLC_RLCP_DOORBELL_RANGE__LOWER_ADDR_RESERVED__SHIFT 0x0 |
38543 | #define RLC_RLCP_DOORBELL_RANGE__LOWER_ADDR__SHIFT 0x2 |
38544 | #define RLC_RLCP_DOORBELL_RANGE__UPPER_ADDR_RESERVED__SHIFT 0x10 |
38545 | #define RLC_RLCP_DOORBELL_RANGE__UPPER_ADDR__SHIFT 0x12 |
38546 | #define RLC_RLCP_DOORBELL_RANGE__LOWER_ADDR_RESERVED_MASK 0x00000003L |
38547 | #define RLC_RLCP_DOORBELL_RANGE__LOWER_ADDR_MASK 0x00000FFCL |
38548 | #define RLC_RLCP_DOORBELL_RANGE__UPPER_ADDR_RESERVED_MASK 0x00030000L |
38549 | #define RLC_RLCP_DOORBELL_RANGE__UPPER_ADDR_MASK 0x0FFC0000L |
38550 | //RLC_RLCP_DOORBELL_CNTL |
38551 | #define RLC_RLCP_DOORBELL_CNTL__DOORBELL_0_MODE__SHIFT 0x0 |
38552 | #define RLC_RLCP_DOORBELL_CNTL__DOORBELL_1_MODE__SHIFT 0x2 |
38553 | #define RLC_RLCP_DOORBELL_CNTL__DOORBELL_2_MODE__SHIFT 0x4 |
38554 | #define RLC_RLCP_DOORBELL_CNTL__DOORBELL_3_MODE__SHIFT 0x6 |
38555 | #define RLC_RLCP_DOORBELL_CNTL__DOORBELL_ID__SHIFT 0x10 |
38556 | #define RLC_RLCP_DOORBELL_CNTL__DOORBELL_ID_EN__SHIFT 0x15 |
38557 | #define RLC_RLCP_DOORBELL_CNTL__DOORBELL_0_MODE_MASK 0x00000003L |
38558 | #define RLC_RLCP_DOORBELL_CNTL__DOORBELL_1_MODE_MASK 0x0000000CL |
38559 | #define RLC_RLCP_DOORBELL_CNTL__DOORBELL_2_MODE_MASK 0x00000030L |
38560 | #define RLC_RLCP_DOORBELL_CNTL__DOORBELL_3_MODE_MASK 0x000000C0L |
38561 | #define RLC_RLCP_DOORBELL_CNTL__DOORBELL_ID_MASK 0x001F0000L |
38562 | #define RLC_RLCP_DOORBELL_CNTL__DOORBELL_ID_EN_MASK 0x00200000L |
38563 | //RLC_RLCP_DOORBELL_STAT |
38564 | #define RLC_RLCP_DOORBELL_STAT__DOORBELL_0_VALID__SHIFT 0x0 |
38565 | #define RLC_RLCP_DOORBELL_STAT__DOORBELL_1_VALID__SHIFT 0x1 |
38566 | #define RLC_RLCP_DOORBELL_STAT__DOORBELL_2_VALID__SHIFT 0x2 |
38567 | #define RLC_RLCP_DOORBELL_STAT__DOORBELL_3_VALID__SHIFT 0x3 |
38568 | #define RLC_RLCP_DOORBELL_STAT__DOORBELL_0_VALID_MASK 0x00000001L |
38569 | #define RLC_RLCP_DOORBELL_STAT__DOORBELL_1_VALID_MASK 0x00000002L |
38570 | #define RLC_RLCP_DOORBELL_STAT__DOORBELL_2_VALID_MASK 0x00000004L |
38571 | #define RLC_RLCP_DOORBELL_STAT__DOORBELL_3_VALID_MASK 0x00000008L |
38572 | //RLC_RLCP_DOORBELL_0_DATA_LO |
38573 | #define RLC_RLCP_DOORBELL_0_DATA_LO__DATA__SHIFT 0x0 |
38574 | #define RLC_RLCP_DOORBELL_0_DATA_LO__DATA_MASK 0xFFFFFFFFL |
38575 | //RLC_RLCP_DOORBELL_0_DATA_HI |
38576 | #define RLC_RLCP_DOORBELL_0_DATA_HI__DATA__SHIFT 0x0 |
38577 | #define RLC_RLCP_DOORBELL_0_DATA_HI__DATA_MASK 0xFFFFFFFFL |
38578 | //RLC_RLCP_DOORBELL_1_DATA_LO |
38579 | #define RLC_RLCP_DOORBELL_1_DATA_LO__DATA__SHIFT 0x0 |
38580 | #define RLC_RLCP_DOORBELL_1_DATA_LO__DATA_MASK 0xFFFFFFFFL |
38581 | //RLC_RLCP_DOORBELL_1_DATA_HI |
38582 | #define RLC_RLCP_DOORBELL_1_DATA_HI__DATA__SHIFT 0x0 |
38583 | #define RLC_RLCP_DOORBELL_1_DATA_HI__DATA_MASK 0xFFFFFFFFL |
38584 | //RLC_RLCP_DOORBELL_2_DATA_LO |
38585 | #define RLC_RLCP_DOORBELL_2_DATA_LO__DATA__SHIFT 0x0 |
38586 | #define RLC_RLCP_DOORBELL_2_DATA_LO__DATA_MASK 0xFFFFFFFFL |
38587 | //RLC_RLCP_DOORBELL_2_DATA_HI |
38588 | #define RLC_RLCP_DOORBELL_2_DATA_HI__DATA__SHIFT 0x0 |
38589 | #define RLC_RLCP_DOORBELL_2_DATA_HI__DATA_MASK 0xFFFFFFFFL |
38590 | //RLC_RLCP_DOORBELL_3_DATA_LO |
38591 | #define RLC_RLCP_DOORBELL_3_DATA_LO__DATA__SHIFT 0x0 |
38592 | #define RLC_RLCP_DOORBELL_3_DATA_LO__DATA_MASK 0xFFFFFFFFL |
38593 | //RLC_RLCP_DOORBELL_3_DATA_HI |
38594 | #define RLC_RLCP_DOORBELL_3_DATA_HI__DATA__SHIFT 0x0 |
38595 | #define RLC_RLCP_DOORBELL_3_DATA_HI__DATA_MASK 0xFFFFFFFFL |
38596 | //RLC_CAC_MASK_CNTL |
38597 | #define RLC_CAC_MASK_CNTL__RLC_CAC_MASK__SHIFT 0x0 |
38598 | #define RLC_CAC_MASK_CNTL__RLC_CAC_MASK_MASK 0xFFFFFFFFL |
38599 | //RLC_POWER_RESIDENCY_CNTR_CTRL |
38600 | #define RLC_POWER_RESIDENCY_CNTR_CTRL__RESET__SHIFT 0x0 |
38601 | #define RLC_POWER_RESIDENCY_CNTR_CTRL__ENABLE__SHIFT 0x1 |
38602 | #define RLC_POWER_RESIDENCY_CNTR_CTRL__RESET_ACK__SHIFT 0x2 |
38603 | #define RLC_POWER_RESIDENCY_CNTR_CTRL__ENABLE_ACK__SHIFT 0x3 |
38604 | #define RLC_POWER_RESIDENCY_CNTR_CTRL__COUNTER_OVERFLOW__SHIFT 0x4 |
38605 | #define RLC_POWER_RESIDENCY_CNTR_CTRL__RESERVED__SHIFT 0x5 |
38606 | #define RLC_POWER_RESIDENCY_CNTR_CTRL__RESET_MASK 0x00000001L |
38607 | #define RLC_POWER_RESIDENCY_CNTR_CTRL__ENABLE_MASK 0x00000002L |
38608 | #define RLC_POWER_RESIDENCY_CNTR_CTRL__RESET_ACK_MASK 0x00000004L |
38609 | #define RLC_POWER_RESIDENCY_CNTR_CTRL__ENABLE_ACK_MASK 0x00000008L |
38610 | #define RLC_POWER_RESIDENCY_CNTR_CTRL__COUNTER_OVERFLOW_MASK 0x00000010L |
38611 | #define RLC_POWER_RESIDENCY_CNTR_CTRL__RESERVED_MASK 0xFFFFFFE0L |
38612 | //RLC_CLK_RESIDENCY_CNTR_CTRL |
38613 | #define RLC_CLK_RESIDENCY_CNTR_CTRL__RESET__SHIFT 0x0 |
38614 | #define RLC_CLK_RESIDENCY_CNTR_CTRL__ENABLE__SHIFT 0x1 |
38615 | #define RLC_CLK_RESIDENCY_CNTR_CTRL__RESET_ACK__SHIFT 0x2 |
38616 | #define RLC_CLK_RESIDENCY_CNTR_CTRL__ENABLE_ACK__SHIFT 0x3 |
38617 | #define RLC_CLK_RESIDENCY_CNTR_CTRL__COUNTER_OVERFLOW__SHIFT 0x4 |
38618 | #define RLC_CLK_RESIDENCY_CNTR_CTRL__RESERVED__SHIFT 0x5 |
38619 | #define RLC_CLK_RESIDENCY_CNTR_CTRL__RESET_MASK 0x00000001L |
38620 | #define RLC_CLK_RESIDENCY_CNTR_CTRL__ENABLE_MASK 0x00000002L |
38621 | #define RLC_CLK_RESIDENCY_CNTR_CTRL__RESET_ACK_MASK 0x00000004L |
38622 | #define RLC_CLK_RESIDENCY_CNTR_CTRL__ENABLE_ACK_MASK 0x00000008L |
38623 | #define RLC_CLK_RESIDENCY_CNTR_CTRL__COUNTER_OVERFLOW_MASK 0x00000010L |
38624 | #define RLC_CLK_RESIDENCY_CNTR_CTRL__RESERVED_MASK 0xFFFFFFE0L |
38625 | //RLC_DS_RESIDENCY_CNTR_CTRL |
38626 | #define RLC_DS_RESIDENCY_CNTR_CTRL__RESET__SHIFT 0x0 |
38627 | #define RLC_DS_RESIDENCY_CNTR_CTRL__ENABLE__SHIFT 0x1 |
38628 | #define RLC_DS_RESIDENCY_CNTR_CTRL__RESET_ACK__SHIFT 0x2 |
38629 | #define RLC_DS_RESIDENCY_CNTR_CTRL__ENABLE_ACK__SHIFT 0x3 |
38630 | #define RLC_DS_RESIDENCY_CNTR_CTRL__COUNTER_OVERFLOW__SHIFT 0x4 |
38631 | #define RLC_DS_RESIDENCY_CNTR_CTRL__RESERVED__SHIFT 0x5 |
38632 | #define RLC_DS_RESIDENCY_CNTR_CTRL__RESET_MASK 0x00000001L |
38633 | #define RLC_DS_RESIDENCY_CNTR_CTRL__ENABLE_MASK 0x00000002L |
38634 | #define RLC_DS_RESIDENCY_CNTR_CTRL__RESET_ACK_MASK 0x00000004L |
38635 | #define RLC_DS_RESIDENCY_CNTR_CTRL__ENABLE_ACK_MASK 0x00000008L |
38636 | #define RLC_DS_RESIDENCY_CNTR_CTRL__COUNTER_OVERFLOW_MASK 0x00000010L |
38637 | #define RLC_DS_RESIDENCY_CNTR_CTRL__RESERVED_MASK 0xFFFFFFE0L |
38638 | //RLC_ULV_RESIDENCY_CNTR_CTRL |
38639 | #define RLC_ULV_RESIDENCY_CNTR_CTRL__RESET__SHIFT 0x0 |
38640 | #define RLC_ULV_RESIDENCY_CNTR_CTRL__ENABLE__SHIFT 0x1 |
38641 | #define RLC_ULV_RESIDENCY_CNTR_CTRL__RESET_ACK__SHIFT 0x2 |
38642 | #define RLC_ULV_RESIDENCY_CNTR_CTRL__ENABLE_ACK__SHIFT 0x3 |
38643 | #define RLC_ULV_RESIDENCY_CNTR_CTRL__COUNTER_OVERFLOW__SHIFT 0x4 |
38644 | #define RLC_ULV_RESIDENCY_CNTR_CTRL__RESERVED__SHIFT 0x5 |
38645 | #define RLC_ULV_RESIDENCY_CNTR_CTRL__RESET_MASK 0x00000001L |
38646 | #define RLC_ULV_RESIDENCY_CNTR_CTRL__ENABLE_MASK 0x00000002L |
38647 | #define RLC_ULV_RESIDENCY_CNTR_CTRL__RESET_ACK_MASK 0x00000004L |
38648 | #define RLC_ULV_RESIDENCY_CNTR_CTRL__ENABLE_ACK_MASK 0x00000008L |
38649 | #define RLC_ULV_RESIDENCY_CNTR_CTRL__COUNTER_OVERFLOW_MASK 0x00000010L |
38650 | #define RLC_ULV_RESIDENCY_CNTR_CTRL__RESERVED_MASK 0xFFFFFFE0L |
38651 | //RLC_PCC_RESIDENCY_CNTR_CTRL |
38652 | #define RLC_PCC_RESIDENCY_CNTR_CTRL__RESET__SHIFT 0x0 |
38653 | #define RLC_PCC_RESIDENCY_CNTR_CTRL__ENABLE__SHIFT 0x1 |
38654 | #define RLC_PCC_RESIDENCY_CNTR_CTRL__RESET_ACK__SHIFT 0x2 |
38655 | #define RLC_PCC_RESIDENCY_CNTR_CTRL__ENABLE_ACK__SHIFT 0x3 |
38656 | #define RLC_PCC_RESIDENCY_CNTR_CTRL__COUNTER_OVERFLOW__SHIFT 0x4 |
38657 | #define RLC_PCC_RESIDENCY_CNTR_CTRL__EVENT_SEL__SHIFT 0x5 |
38658 | #define RLC_PCC_RESIDENCY_CNTR_CTRL__RESERVED__SHIFT 0x9 |
38659 | #define RLC_PCC_RESIDENCY_CNTR_CTRL__RESET_MASK 0x00000001L |
38660 | #define RLC_PCC_RESIDENCY_CNTR_CTRL__ENABLE_MASK 0x00000002L |
38661 | #define RLC_PCC_RESIDENCY_CNTR_CTRL__RESET_ACK_MASK 0x00000004L |
38662 | #define RLC_PCC_RESIDENCY_CNTR_CTRL__ENABLE_ACK_MASK 0x00000008L |
38663 | #define RLC_PCC_RESIDENCY_CNTR_CTRL__COUNTER_OVERFLOW_MASK 0x00000010L |
38664 | #define RLC_PCC_RESIDENCY_CNTR_CTRL__EVENT_SEL_MASK 0x000001E0L |
38665 | #define RLC_PCC_RESIDENCY_CNTR_CTRL__RESERVED_MASK 0xFFFFFE00L |
38666 | //RLC_GENERAL_RESIDENCY_CNTR_CTRL |
38667 | #define RLC_GENERAL_RESIDENCY_CNTR_CTRL__RESET__SHIFT 0x0 |
38668 | #define RLC_GENERAL_RESIDENCY_CNTR_CTRL__ENABLE__SHIFT 0x1 |
38669 | #define RLC_GENERAL_RESIDENCY_CNTR_CTRL__RESET_ACK__SHIFT 0x2 |
38670 | #define RLC_GENERAL_RESIDENCY_CNTR_CTRL__ENABLE_ACK__SHIFT 0x3 |
38671 | #define RLC_GENERAL_RESIDENCY_CNTR_CTRL__COUNTER_OVERFLOW__SHIFT 0x4 |
38672 | #define RLC_GENERAL_RESIDENCY_CNTR_CTRL__RESERVED__SHIFT 0x5 |
38673 | #define RLC_GENERAL_RESIDENCY_CNTR_CTRL__RESET_MASK 0x00000001L |
38674 | #define RLC_GENERAL_RESIDENCY_CNTR_CTRL__ENABLE_MASK 0x00000002L |
38675 | #define RLC_GENERAL_RESIDENCY_CNTR_CTRL__RESET_ACK_MASK 0x00000004L |
38676 | #define RLC_GENERAL_RESIDENCY_CNTR_CTRL__ENABLE_ACK_MASK 0x00000008L |
38677 | #define RLC_GENERAL_RESIDENCY_CNTR_CTRL__COUNTER_OVERFLOW_MASK 0x00000010L |
38678 | #define RLC_GENERAL_RESIDENCY_CNTR_CTRL__RESERVED_MASK 0xFFFFFFE0L |
38679 | //RLC_POWER_RESIDENCY_EVENT_CNTR |
38680 | #define RLC_POWER_RESIDENCY_EVENT_CNTR__DATA__SHIFT 0x0 |
38681 | #define RLC_POWER_RESIDENCY_EVENT_CNTR__DATA_MASK 0xFFFFFFFFL |
38682 | //RLC_CLK_RESIDENCY_EVENT_CNTR |
38683 | #define RLC_CLK_RESIDENCY_EVENT_CNTR__DATA__SHIFT 0x0 |
38684 | #define RLC_CLK_RESIDENCY_EVENT_CNTR__DATA_MASK 0xFFFFFFFFL |
38685 | //RLC_DS_RESIDENCY_EVENT_CNTR |
38686 | #define RLC_DS_RESIDENCY_EVENT_CNTR__DATA__SHIFT 0x0 |
38687 | #define RLC_DS_RESIDENCY_EVENT_CNTR__DATA_MASK 0xFFFFFFFFL |
38688 | //RLC_ULV_RESIDENCY_EVENT_CNTR |
38689 | #define RLC_ULV_RESIDENCY_EVENT_CNTR__DATA__SHIFT 0x0 |
38690 | #define RLC_ULV_RESIDENCY_EVENT_CNTR__DATA_MASK 0xFFFFFFFFL |
38691 | //RLC_PCC_RESIDENCY_EVENT_CNTR |
38692 | #define RLC_PCC_RESIDENCY_EVENT_CNTR__DATA__SHIFT 0x0 |
38693 | #define RLC_PCC_RESIDENCY_EVENT_CNTR__DATA_MASK 0xFFFFFFFFL |
38694 | //RLC_GENERAL_RESIDENCY_EVENT_CNTR |
38695 | #define RLC_GENERAL_RESIDENCY_EVENT_CNTR__DATA__SHIFT 0x0 |
38696 | #define RLC_GENERAL_RESIDENCY_EVENT_CNTR__DATA_MASK 0xFFFFFFFFL |
38697 | //RLC_POWER_RESIDENCY_REF_CNTR |
38698 | #define RLC_POWER_RESIDENCY_REF_CNTR__DATA__SHIFT 0x0 |
38699 | #define RLC_POWER_RESIDENCY_REF_CNTR__DATA_MASK 0xFFFFFFFFL |
38700 | //RLC_CLK_RESIDENCY_REF_CNTR |
38701 | #define RLC_CLK_RESIDENCY_REF_CNTR__DATA__SHIFT 0x0 |
38702 | #define RLC_CLK_RESIDENCY_REF_CNTR__DATA_MASK 0xFFFFFFFFL |
38703 | //RLC_DS_RESIDENCY_REF_CNTR |
38704 | #define RLC_DS_RESIDENCY_REF_CNTR__DATA__SHIFT 0x0 |
38705 | #define RLC_DS_RESIDENCY_REF_CNTR__DATA_MASK 0xFFFFFFFFL |
38706 | //RLC_ULV_RESIDENCY_REF_CNTR |
38707 | #define RLC_ULV_RESIDENCY_REF_CNTR__DATA__SHIFT 0x0 |
38708 | #define RLC_ULV_RESIDENCY_REF_CNTR__DATA_MASK 0xFFFFFFFFL |
38709 | //RLC_PCC_RESIDENCY_REF_CNTR |
38710 | #define RLC_PCC_RESIDENCY_REF_CNTR__DATA__SHIFT 0x0 |
38711 | #define RLC_PCC_RESIDENCY_REF_CNTR__DATA_MASK 0xFFFFFFFFL |
38712 | //RLC_GENERAL_RESIDENCY_REF_CNTR |
38713 | #define RLC_GENERAL_RESIDENCY_REF_CNTR__DATA__SHIFT 0x0 |
38714 | #define RLC_GENERAL_RESIDENCY_REF_CNTR__DATA_MASK 0xFFFFFFFFL |
38715 | //RLC_GFX_IH_CLIENT_CTRL |
38716 | #define RLC_GFX_IH_CLIENT_CTRL__SE_INTERRUPT_MASK__SHIFT 0x0 |
38717 | #define RLC_GFX_IH_CLIENT_CTRL__SDMA_INTERRUPT_MASK__SHIFT 0x8 |
38718 | #define RLC_GFX_IH_CLIENT_CTRL__UTCL2_INTERRUPT_MASK__SHIFT 0xc |
38719 | #define RLC_GFX_IH_CLIENT_CTRL__PMM_INTERRUPT_MASK__SHIFT 0xd |
38720 | #define RLC_GFX_IH_CLIENT_CTRL__FED_INTERRUPT_MASK__SHIFT 0xe |
38721 | #define RLC_GFX_IH_CLIENT_CTRL__RESERVED_15__SHIFT 0xf |
38722 | #define RLC_GFX_IH_CLIENT_CTRL__SE_INTERRUPT_ERROR_CLEAR__SHIFT 0x10 |
38723 | #define RLC_GFX_IH_CLIENT_CTRL__SDMA_INTERRUPT_ERROR_CLEAR__SHIFT 0x18 |
38724 | #define RLC_GFX_IH_CLIENT_CTRL__UTCL2_INTERRUPT_ERROR_CLEAR__SHIFT 0x1c |
38725 | #define RLC_GFX_IH_CLIENT_CTRL__PMM_INTERRUPT_ERROR_CLEAR__SHIFT 0x1d |
38726 | #define RLC_GFX_IH_CLIENT_CTRL__FED_INTERRUPT_ERROR_CLEAR__SHIFT 0x1e |
38727 | #define RLC_GFX_IH_CLIENT_CTRL__RESERVED_31__SHIFT 0x1f |
38728 | #define RLC_GFX_IH_CLIENT_CTRL__SE_INTERRUPT_MASK_MASK 0x000000FFL |
38729 | #define RLC_GFX_IH_CLIENT_CTRL__SDMA_INTERRUPT_MASK_MASK 0x00000F00L |
38730 | #define RLC_GFX_IH_CLIENT_CTRL__UTCL2_INTERRUPT_MASK_MASK 0x00001000L |
38731 | #define RLC_GFX_IH_CLIENT_CTRL__PMM_INTERRUPT_MASK_MASK 0x00002000L |
38732 | #define RLC_GFX_IH_CLIENT_CTRL__FED_INTERRUPT_MASK_MASK 0x00004000L |
38733 | #define RLC_GFX_IH_CLIENT_CTRL__RESERVED_15_MASK 0x00008000L |
38734 | #define RLC_GFX_IH_CLIENT_CTRL__SE_INTERRUPT_ERROR_CLEAR_MASK 0x00FF0000L |
38735 | #define RLC_GFX_IH_CLIENT_CTRL__SDMA_INTERRUPT_ERROR_CLEAR_MASK 0x0F000000L |
38736 | #define RLC_GFX_IH_CLIENT_CTRL__UTCL2_INTERRUPT_ERROR_CLEAR_MASK 0x10000000L |
38737 | #define RLC_GFX_IH_CLIENT_CTRL__PMM_INTERRUPT_ERROR_CLEAR_MASK 0x20000000L |
38738 | #define RLC_GFX_IH_CLIENT_CTRL__FED_INTERRUPT_ERROR_CLEAR_MASK 0x40000000L |
38739 | #define RLC_GFX_IH_CLIENT_CTRL__RESERVED_31_MASK 0x80000000L |
38740 | //RLC_GFX_IH_ARBITER_STAT |
38741 | #define RLC_GFX_IH_ARBITER_STAT__CLIENT_GRANTED__SHIFT 0x0 |
38742 | #define RLC_GFX_IH_ARBITER_STAT__RESERVED__SHIFT 0x10 |
38743 | #define RLC_GFX_IH_ARBITER_STAT__LAST_CLIENT_GRANTED__SHIFT 0x1c |
38744 | #define RLC_GFX_IH_ARBITER_STAT__CLIENT_GRANTED_MASK 0x0000FFFFL |
38745 | #define RLC_GFX_IH_ARBITER_STAT__RESERVED_MASK 0x0FFF0000L |
38746 | #define RLC_GFX_IH_ARBITER_STAT__LAST_CLIENT_GRANTED_MASK 0xF0000000L |
38747 | //RLC_GFX_IH_CLIENT_SE_STAT_L |
38748 | #define RLC_GFX_IH_CLIENT_SE_STAT_L__SE0_BUFFER_LEVEL__SHIFT 0x0 |
38749 | #define RLC_GFX_IH_CLIENT_SE_STAT_L__SE0_BUFFER_LOADING__SHIFT 0x4 |
38750 | #define RLC_GFX_IH_CLIENT_SE_STAT_L__SE0_BUFFER_OVERFLOW__SHIFT 0x5 |
38751 | #define RLC_GFX_IH_CLIENT_SE_STAT_L__SE0_PROTOCOL_ERROR__SHIFT 0x6 |
38752 | #define RLC_GFX_IH_CLIENT_SE_STAT_L__SE0_RESERVED__SHIFT 0x7 |
38753 | #define RLC_GFX_IH_CLIENT_SE_STAT_L__SE1_BUFFER_LEVEL__SHIFT 0x8 |
38754 | #define RLC_GFX_IH_CLIENT_SE_STAT_L__SE1_BUFFER_LOADING__SHIFT 0xc |
38755 | #define RLC_GFX_IH_CLIENT_SE_STAT_L__SE1_BUFFER_OVERFLOW__SHIFT 0xd |
38756 | #define RLC_GFX_IH_CLIENT_SE_STAT_L__SE1_PROTOCOL_ERROR__SHIFT 0xe |
38757 | #define RLC_GFX_IH_CLIENT_SE_STAT_L__SE1_RESERVED__SHIFT 0xf |
38758 | #define RLC_GFX_IH_CLIENT_SE_STAT_L__SE2_BUFFER_LEVEL__SHIFT 0x10 |
38759 | #define RLC_GFX_IH_CLIENT_SE_STAT_L__SE2_BUFFER_LOADING__SHIFT 0x14 |
38760 | #define RLC_GFX_IH_CLIENT_SE_STAT_L__SE2_BUFFER_OVERFLOW__SHIFT 0x15 |
38761 | #define RLC_GFX_IH_CLIENT_SE_STAT_L__SE2_PROTOCOL_ERROR__SHIFT 0x16 |
38762 | #define RLC_GFX_IH_CLIENT_SE_STAT_L__SE2_RESERVED__SHIFT 0x17 |
38763 | #define RLC_GFX_IH_CLIENT_SE_STAT_L__SE3_BUFFER_LEVEL__SHIFT 0x18 |
38764 | #define RLC_GFX_IH_CLIENT_SE_STAT_L__SE3_BUFFER_LOADING__SHIFT 0x1c |
38765 | #define RLC_GFX_IH_CLIENT_SE_STAT_L__SE3_BUFFER_OVERFLOW__SHIFT 0x1d |
38766 | #define RLC_GFX_IH_CLIENT_SE_STAT_L__SE3_PROTOCOL_ERROR__SHIFT 0x1e |
38767 | #define RLC_GFX_IH_CLIENT_SE_STAT_L__SE3_RESERVED__SHIFT 0x1f |
38768 | #define RLC_GFX_IH_CLIENT_SE_STAT_L__SE0_BUFFER_LEVEL_MASK 0x0000000FL |
38769 | #define RLC_GFX_IH_CLIENT_SE_STAT_L__SE0_BUFFER_LOADING_MASK 0x00000010L |
38770 | #define RLC_GFX_IH_CLIENT_SE_STAT_L__SE0_BUFFER_OVERFLOW_MASK 0x00000020L |
38771 | #define RLC_GFX_IH_CLIENT_SE_STAT_L__SE0_PROTOCOL_ERROR_MASK 0x00000040L |
38772 | #define RLC_GFX_IH_CLIENT_SE_STAT_L__SE0_RESERVED_MASK 0x00000080L |
38773 | #define RLC_GFX_IH_CLIENT_SE_STAT_L__SE1_BUFFER_LEVEL_MASK 0x00000F00L |
38774 | #define RLC_GFX_IH_CLIENT_SE_STAT_L__SE1_BUFFER_LOADING_MASK 0x00001000L |
38775 | #define RLC_GFX_IH_CLIENT_SE_STAT_L__SE1_BUFFER_OVERFLOW_MASK 0x00002000L |
38776 | #define RLC_GFX_IH_CLIENT_SE_STAT_L__SE1_PROTOCOL_ERROR_MASK 0x00004000L |
38777 | #define RLC_GFX_IH_CLIENT_SE_STAT_L__SE1_RESERVED_MASK 0x00008000L |
38778 | #define RLC_GFX_IH_CLIENT_SE_STAT_L__SE2_BUFFER_LEVEL_MASK 0x000F0000L |
38779 | #define RLC_GFX_IH_CLIENT_SE_STAT_L__SE2_BUFFER_LOADING_MASK 0x00100000L |
38780 | #define RLC_GFX_IH_CLIENT_SE_STAT_L__SE2_BUFFER_OVERFLOW_MASK 0x00200000L |
38781 | #define RLC_GFX_IH_CLIENT_SE_STAT_L__SE2_PROTOCOL_ERROR_MASK 0x00400000L |
38782 | #define RLC_GFX_IH_CLIENT_SE_STAT_L__SE2_RESERVED_MASK 0x00800000L |
38783 | #define RLC_GFX_IH_CLIENT_SE_STAT_L__SE3_BUFFER_LEVEL_MASK 0x0F000000L |
38784 | #define RLC_GFX_IH_CLIENT_SE_STAT_L__SE3_BUFFER_LOADING_MASK 0x10000000L |
38785 | #define RLC_GFX_IH_CLIENT_SE_STAT_L__SE3_BUFFER_OVERFLOW_MASK 0x20000000L |
38786 | #define RLC_GFX_IH_CLIENT_SE_STAT_L__SE3_PROTOCOL_ERROR_MASK 0x40000000L |
38787 | #define RLC_GFX_IH_CLIENT_SE_STAT_L__SE3_RESERVED_MASK 0x80000000L |
38788 | //RLC_GFX_IH_CLIENT_SE_STAT_H |
38789 | #define RLC_GFX_IH_CLIENT_SE_STAT_H__SE4_BUFFER_LEVEL__SHIFT 0x0 |
38790 | #define RLC_GFX_IH_CLIENT_SE_STAT_H__SE4_BUFFER_LOADING__SHIFT 0x4 |
38791 | #define RLC_GFX_IH_CLIENT_SE_STAT_H__SE4_BUFFER_OVERFLOW__SHIFT 0x5 |
38792 | #define RLC_GFX_IH_CLIENT_SE_STAT_H__SE4_PROTOCOL_ERROR__SHIFT 0x6 |
38793 | #define RLC_GFX_IH_CLIENT_SE_STAT_H__SE4_RESERVED__SHIFT 0x7 |
38794 | #define RLC_GFX_IH_CLIENT_SE_STAT_H__SE5_BUFFER_LEVEL__SHIFT 0x8 |
38795 | #define RLC_GFX_IH_CLIENT_SE_STAT_H__SE5_BUFFER_LOADING__SHIFT 0xc |
38796 | #define RLC_GFX_IH_CLIENT_SE_STAT_H__SE5_BUFFER_OVERFLOW__SHIFT 0xd |
38797 | #define RLC_GFX_IH_CLIENT_SE_STAT_H__SE5_PROTOCOL_ERROR__SHIFT 0xe |
38798 | #define RLC_GFX_IH_CLIENT_SE_STAT_H__SE5_RESERVED__SHIFT 0xf |
38799 | #define RLC_GFX_IH_CLIENT_SE_STAT_H__SE6_BUFFER_LEVEL__SHIFT 0x10 |
38800 | #define RLC_GFX_IH_CLIENT_SE_STAT_H__SE6_BUFFER_LOADING__SHIFT 0x14 |
38801 | #define RLC_GFX_IH_CLIENT_SE_STAT_H__SE6_BUFFER_OVERFLOW__SHIFT 0x15 |
38802 | #define RLC_GFX_IH_CLIENT_SE_STAT_H__SE6_PROTOCOL_ERROR__SHIFT 0x16 |
38803 | #define RLC_GFX_IH_CLIENT_SE_STAT_H__SE6_RESERVED__SHIFT 0x17 |
38804 | #define RLC_GFX_IH_CLIENT_SE_STAT_H__SE7_BUFFER_LEVEL__SHIFT 0x18 |
38805 | #define RLC_GFX_IH_CLIENT_SE_STAT_H__SE7_BUFFER_LOADING__SHIFT 0x1c |
38806 | #define RLC_GFX_IH_CLIENT_SE_STAT_H__SE7_BUFFER_OVERFLOW__SHIFT 0x1d |
38807 | #define RLC_GFX_IH_CLIENT_SE_STAT_H__SE7_PROTOCOL_ERROR__SHIFT 0x1e |
38808 | #define RLC_GFX_IH_CLIENT_SE_STAT_H__SE7_RESERVED__SHIFT 0x1f |
38809 | #define RLC_GFX_IH_CLIENT_SE_STAT_H__SE4_BUFFER_LEVEL_MASK 0x0000000FL |
38810 | #define RLC_GFX_IH_CLIENT_SE_STAT_H__SE4_BUFFER_LOADING_MASK 0x00000010L |
38811 | #define RLC_GFX_IH_CLIENT_SE_STAT_H__SE4_BUFFER_OVERFLOW_MASK 0x00000020L |
38812 | #define RLC_GFX_IH_CLIENT_SE_STAT_H__SE4_PROTOCOL_ERROR_MASK 0x00000040L |
38813 | #define RLC_GFX_IH_CLIENT_SE_STAT_H__SE4_RESERVED_MASK 0x00000080L |
38814 | #define RLC_GFX_IH_CLIENT_SE_STAT_H__SE5_BUFFER_LEVEL_MASK 0x00000F00L |
38815 | #define RLC_GFX_IH_CLIENT_SE_STAT_H__SE5_BUFFER_LOADING_MASK 0x00001000L |
38816 | #define RLC_GFX_IH_CLIENT_SE_STAT_H__SE5_BUFFER_OVERFLOW_MASK 0x00002000L |
38817 | #define RLC_GFX_IH_CLIENT_SE_STAT_H__SE5_PROTOCOL_ERROR_MASK 0x00004000L |
38818 | #define RLC_GFX_IH_CLIENT_SE_STAT_H__SE5_RESERVED_MASK 0x00008000L |
38819 | #define RLC_GFX_IH_CLIENT_SE_STAT_H__SE6_BUFFER_LEVEL_MASK 0x000F0000L |
38820 | #define RLC_GFX_IH_CLIENT_SE_STAT_H__SE6_BUFFER_LOADING_MASK 0x00100000L |
38821 | #define RLC_GFX_IH_CLIENT_SE_STAT_H__SE6_BUFFER_OVERFLOW_MASK 0x00200000L |
38822 | #define RLC_GFX_IH_CLIENT_SE_STAT_H__SE6_PROTOCOL_ERROR_MASK 0x00400000L |
38823 | #define RLC_GFX_IH_CLIENT_SE_STAT_H__SE6_RESERVED_MASK 0x00800000L |
38824 | #define RLC_GFX_IH_CLIENT_SE_STAT_H__SE7_BUFFER_LEVEL_MASK 0x0F000000L |
38825 | #define RLC_GFX_IH_CLIENT_SE_STAT_H__SE7_BUFFER_LOADING_MASK 0x10000000L |
38826 | #define RLC_GFX_IH_CLIENT_SE_STAT_H__SE7_BUFFER_OVERFLOW_MASK 0x20000000L |
38827 | #define RLC_GFX_IH_CLIENT_SE_STAT_H__SE7_PROTOCOL_ERROR_MASK 0x40000000L |
38828 | #define RLC_GFX_IH_CLIENT_SE_STAT_H__SE7_RESERVED_MASK 0x80000000L |
38829 | //RLC_GFX_IH_CLIENT_SDMA_STAT |
38830 | #define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA0_BUFFER_LEVEL__SHIFT 0x0 |
38831 | #define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA0_BUFFER_LOADING__SHIFT 0x4 |
38832 | #define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA0_BUFFER_OVERFLOW__SHIFT 0x5 |
38833 | #define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA0_PROTOCOL_ERROR__SHIFT 0x6 |
38834 | #define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA0_RESERVED__SHIFT 0x7 |
38835 | #define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA1_BUFFER_LEVEL__SHIFT 0x8 |
38836 | #define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA1_BUFFER_LOADING__SHIFT 0xc |
38837 | #define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA1_BUFFER_OVERFLOW__SHIFT 0xd |
38838 | #define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA1_PROTOCOL_ERROR__SHIFT 0xe |
38839 | #define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA1_RESERVED__SHIFT 0xf |
38840 | #define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA2_BUFFER_LEVEL__SHIFT 0x10 |
38841 | #define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA2_BUFFER_LOADING__SHIFT 0x14 |
38842 | #define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA2_BUFFER_OVERFLOW__SHIFT 0x15 |
38843 | #define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA2_PROTOCOL_ERROR__SHIFT 0x16 |
38844 | #define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA2_RESERVED__SHIFT 0x17 |
38845 | #define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA3_BUFFER_LEVEL__SHIFT 0x18 |
38846 | #define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA3_BUFFER_LOADING__SHIFT 0x1c |
38847 | #define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA3_BUFFER_OVERFLOW__SHIFT 0x1d |
38848 | #define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA3_PROTOCOL_ERROR__SHIFT 0x1e |
38849 | #define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA3_RESERVED__SHIFT 0x1f |
38850 | #define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA0_BUFFER_LEVEL_MASK 0x0000000FL |
38851 | #define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA0_BUFFER_LOADING_MASK 0x00000010L |
38852 | #define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA0_BUFFER_OVERFLOW_MASK 0x00000020L |
38853 | #define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA0_PROTOCOL_ERROR_MASK 0x00000040L |
38854 | #define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA0_RESERVED_MASK 0x00000080L |
38855 | #define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA1_BUFFER_LEVEL_MASK 0x00000F00L |
38856 | #define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA1_BUFFER_LOADING_MASK 0x00001000L |
38857 | #define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA1_BUFFER_OVERFLOW_MASK 0x00002000L |
38858 | #define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA1_PROTOCOL_ERROR_MASK 0x00004000L |
38859 | #define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA1_RESERVED_MASK 0x00008000L |
38860 | #define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA2_BUFFER_LEVEL_MASK 0x000F0000L |
38861 | #define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA2_BUFFER_LOADING_MASK 0x00100000L |
38862 | #define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA2_BUFFER_OVERFLOW_MASK 0x00200000L |
38863 | #define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA2_PROTOCOL_ERROR_MASK 0x00400000L |
38864 | #define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA2_RESERVED_MASK 0x00800000L |
38865 | #define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA3_BUFFER_LEVEL_MASK 0x0F000000L |
38866 | #define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA3_BUFFER_LOADING_MASK 0x10000000L |
38867 | #define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA3_BUFFER_OVERFLOW_MASK 0x20000000L |
38868 | #define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA3_PROTOCOL_ERROR_MASK 0x40000000L |
38869 | #define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA3_RESERVED_MASK 0x80000000L |
38870 | //RLC_GFX_IH_CLIENT_OTHER_STAT |
38871 | #define RLC_GFX_IH_CLIENT_OTHER_STAT__UTCL2_BUFFER_LEVEL__SHIFT 0x0 |
38872 | #define RLC_GFX_IH_CLIENT_OTHER_STAT__UTCL2_BUFFER_LOADING__SHIFT 0x4 |
38873 | #define RLC_GFX_IH_CLIENT_OTHER_STAT__UTCL2_BUFFER_OVERFLOW__SHIFT 0x5 |
38874 | #define RLC_GFX_IH_CLIENT_OTHER_STAT__UTCL2_PROTOCOL_ERROR__SHIFT 0x6 |
38875 | #define RLC_GFX_IH_CLIENT_OTHER_STAT__UTCL2_RESERVED__SHIFT 0x7 |
38876 | #define RLC_GFX_IH_CLIENT_OTHER_STAT__PMM_BUFFER_LEVEL__SHIFT 0x8 |
38877 | #define RLC_GFX_IH_CLIENT_OTHER_STAT__PMM_BUFFER_LOADING__SHIFT 0xc |
38878 | #define RLC_GFX_IH_CLIENT_OTHER_STAT__PMM_BUFFER_OVERFLOW__SHIFT 0xd |
38879 | #define RLC_GFX_IH_CLIENT_OTHER_STAT__PMM_PROTOCOL_ERROR__SHIFT 0xe |
38880 | #define RLC_GFX_IH_CLIENT_OTHER_STAT__PMM_RESERVED__SHIFT 0xf |
38881 | #define RLC_GFX_IH_CLIENT_OTHER_STAT__FED_BUFFER_LEVEL__SHIFT 0x10 |
38882 | #define RLC_GFX_IH_CLIENT_OTHER_STAT__FED_BUFFER_LOADING__SHIFT 0x14 |
38883 | #define RLC_GFX_IH_CLIENT_OTHER_STAT__FED_BUFFER_OVERFLOW__SHIFT 0x15 |
38884 | #define RLC_GFX_IH_CLIENT_OTHER_STAT__FED_PROTOCOL_ERROR__SHIFT 0x16 |
38885 | #define RLC_GFX_IH_CLIENT_OTHER_STAT__FED_RESERVED__SHIFT 0x17 |
38886 | #define RLC_GFX_IH_CLIENT_OTHER_STAT__RESERVED_31_24__SHIFT 0x18 |
38887 | #define RLC_GFX_IH_CLIENT_OTHER_STAT__UTCL2_BUFFER_LEVEL_MASK 0x0000000FL |
38888 | #define RLC_GFX_IH_CLIENT_OTHER_STAT__UTCL2_BUFFER_LOADING_MASK 0x00000010L |
38889 | #define RLC_GFX_IH_CLIENT_OTHER_STAT__UTCL2_BUFFER_OVERFLOW_MASK 0x00000020L |
38890 | #define RLC_GFX_IH_CLIENT_OTHER_STAT__UTCL2_PROTOCOL_ERROR_MASK 0x00000040L |
38891 | #define RLC_GFX_IH_CLIENT_OTHER_STAT__UTCL2_RESERVED_MASK 0x00000080L |
38892 | #define RLC_GFX_IH_CLIENT_OTHER_STAT__PMM_BUFFER_LEVEL_MASK 0x00000F00L |
38893 | #define RLC_GFX_IH_CLIENT_OTHER_STAT__PMM_BUFFER_LOADING_MASK 0x00001000L |
38894 | #define RLC_GFX_IH_CLIENT_OTHER_STAT__PMM_BUFFER_OVERFLOW_MASK 0x00002000L |
38895 | #define RLC_GFX_IH_CLIENT_OTHER_STAT__PMM_PROTOCOL_ERROR_MASK 0x00004000L |
38896 | #define RLC_GFX_IH_CLIENT_OTHER_STAT__PMM_RESERVED_MASK 0x00008000L |
38897 | #define RLC_GFX_IH_CLIENT_OTHER_STAT__FED_BUFFER_LEVEL_MASK 0x000F0000L |
38898 | #define RLC_GFX_IH_CLIENT_OTHER_STAT__FED_BUFFER_LOADING_MASK 0x00100000L |
38899 | #define RLC_GFX_IH_CLIENT_OTHER_STAT__FED_BUFFER_OVERFLOW_MASK 0x00200000L |
38900 | #define RLC_GFX_IH_CLIENT_OTHER_STAT__FED_PROTOCOL_ERROR_MASK 0x00400000L |
38901 | #define RLC_GFX_IH_CLIENT_OTHER_STAT__FED_RESERVED_MASK 0x00800000L |
38902 | #define RLC_GFX_IH_CLIENT_OTHER_STAT__RESERVED_31_24_MASK 0xFF000000L |
38903 | //RLC_SPM_GLOBAL_DELAY_IND_ADDR |
38904 | #define RLC_SPM_GLOBAL_DELAY_IND_ADDR__ADDR__SHIFT 0x0 |
38905 | #define RLC_SPM_GLOBAL_DELAY_IND_ADDR__ADDR_MASK 0x00000FFFL |
38906 | //RLC_SPM_GLOBAL_DELAY_IND_DATA |
38907 | #define RLC_SPM_GLOBAL_DELAY_IND_DATA__DATA__SHIFT 0x0 |
38908 | #define RLC_SPM_GLOBAL_DELAY_IND_DATA__DATA_MASK 0x0000003FL |
38909 | //RLC_SPM_SE_DELAY_IND_ADDR |
38910 | #define RLC_SPM_SE_DELAY_IND_ADDR__ADDR__SHIFT 0x0 |
38911 | #define RLC_SPM_SE_DELAY_IND_ADDR__ADDR_MASK 0x00000FFFL |
38912 | //RLC_SPM_SE_DELAY_IND_DATA |
38913 | #define RLC_SPM_SE_DELAY_IND_DATA__DATA__SHIFT 0x0 |
38914 | #define RLC_SPM_SE_DELAY_IND_DATA__DATA_MASK 0x0000003FL |
38915 | //RLC_LX6_CNTL |
38916 | #define RLC_LX6_CNTL__BRESET__SHIFT 0x0 |
38917 | #define RLC_LX6_CNTL__RUNSTALL__SHIFT 0x1 |
38918 | #define RLC_LX6_CNTL__PDEBUG_ENABLE__SHIFT 0x2 |
38919 | #define RLC_LX6_CNTL__STAT_VECTOR_SEL__SHIFT 0x3 |
38920 | #define RLC_LX6_CNTL__BRESET_MASK 0x00000001L |
38921 | #define RLC_LX6_CNTL__RUNSTALL_MASK 0x00000002L |
38922 | #define RLC_LX6_CNTL__PDEBUG_ENABLE_MASK 0x00000004L |
38923 | #define RLC_LX6_CNTL__STAT_VECTOR_SEL_MASK 0x00000008L |
38924 | //RLC_XT_CORE_STATUS |
38925 | #define RLC_XT_CORE_STATUS__P_WAIT_MODE__SHIFT 0x0 |
38926 | #define RLC_XT_CORE_STATUS__P_FATAL_ERROR__SHIFT 0x1 |
38927 | #define RLC_XT_CORE_STATUS__DOUBLE_EXCEPTION_ERROR__SHIFT 0x2 |
38928 | #define RLC_XT_CORE_STATUS__P_WAIT_MODE_MASK 0x00000001L |
38929 | #define RLC_XT_CORE_STATUS__P_FATAL_ERROR_MASK 0x00000002L |
38930 | #define RLC_XT_CORE_STATUS__DOUBLE_EXCEPTION_ERROR_MASK 0x00000004L |
38931 | //RLC_XT_CORE_INTERRUPT |
38932 | #define RLC_XT_CORE_INTERRUPT__EXTINT1__SHIFT 0x0 |
38933 | #define RLC_XT_CORE_INTERRUPT__EXTINT2__SHIFT 0x1a |
38934 | #define RLC_XT_CORE_INTERRUPT__NMI__SHIFT 0x1b |
38935 | #define RLC_XT_CORE_INTERRUPT__EXTINT1_MASK 0x03FFFFFFL |
38936 | #define RLC_XT_CORE_INTERRUPT__EXTINT2_MASK 0x04000000L |
38937 | #define RLC_XT_CORE_INTERRUPT__NMI_MASK 0x08000000L |
38938 | //RLC_XT_CORE_FAULT_INFO |
38939 | #define RLC_XT_CORE_FAULT_INFO__FAULT_INFO__SHIFT 0x0 |
38940 | #define RLC_XT_CORE_FAULT_INFO__FAULT_INFO_MASK 0xFFFFFFFFL |
38941 | //RLC_XT_CORE_ALT_RESET_VEC |
38942 | #define RLC_XT_CORE_ALT_RESET_VEC__ALT_RESET_VEC__SHIFT 0x0 |
38943 | #define RLC_XT_CORE_ALT_RESET_VEC__ALT_RESET_VEC_MASK 0xFFFFFFFFL |
38944 | //RLC_XT_CORE_RESERVED |
38945 | #define RLC_XT_CORE_RESERVED__RESERVED__SHIFT 0x0 |
38946 | #define RLC_XT_CORE_RESERVED__RESERVED_MASK 0xFFFFFFFFL |
38947 | //RLC_XT_INT_VEC_FORCE |
38948 | #define RLC_XT_INT_VEC_FORCE__NUM_0__SHIFT 0x0 |
38949 | #define RLC_XT_INT_VEC_FORCE__NUM_1__SHIFT 0x1 |
38950 | #define RLC_XT_INT_VEC_FORCE__NUM_2__SHIFT 0x2 |
38951 | #define RLC_XT_INT_VEC_FORCE__NUM_3__SHIFT 0x3 |
38952 | #define RLC_XT_INT_VEC_FORCE__NUM_4__SHIFT 0x4 |
38953 | #define RLC_XT_INT_VEC_FORCE__NUM_5__SHIFT 0x5 |
38954 | #define RLC_XT_INT_VEC_FORCE__NUM_6__SHIFT 0x6 |
38955 | #define RLC_XT_INT_VEC_FORCE__NUM_7__SHIFT 0x7 |
38956 | #define RLC_XT_INT_VEC_FORCE__NUM_8__SHIFT 0x8 |
38957 | #define RLC_XT_INT_VEC_FORCE__NUM_9__SHIFT 0x9 |
38958 | #define RLC_XT_INT_VEC_FORCE__NUM_10__SHIFT 0xa |
38959 | #define RLC_XT_INT_VEC_FORCE__NUM_11__SHIFT 0xb |
38960 | #define RLC_XT_INT_VEC_FORCE__NUM_12__SHIFT 0xc |
38961 | #define RLC_XT_INT_VEC_FORCE__NUM_13__SHIFT 0xd |
38962 | #define RLC_XT_INT_VEC_FORCE__NUM_14__SHIFT 0xe |
38963 | #define RLC_XT_INT_VEC_FORCE__NUM_15__SHIFT 0xf |
38964 | #define RLC_XT_INT_VEC_FORCE__NUM_16__SHIFT 0x10 |
38965 | #define RLC_XT_INT_VEC_FORCE__NUM_17__SHIFT 0x11 |
38966 | #define RLC_XT_INT_VEC_FORCE__NUM_18__SHIFT 0x12 |
38967 | #define RLC_XT_INT_VEC_FORCE__NUM_19__SHIFT 0x13 |
38968 | #define RLC_XT_INT_VEC_FORCE__NUM_20__SHIFT 0x14 |
38969 | #define RLC_XT_INT_VEC_FORCE__NUM_21__SHIFT 0x15 |
38970 | #define RLC_XT_INT_VEC_FORCE__NUM_22__SHIFT 0x16 |
38971 | #define RLC_XT_INT_VEC_FORCE__NUM_23__SHIFT 0x17 |
38972 | #define RLC_XT_INT_VEC_FORCE__NUM_24__SHIFT 0x18 |
38973 | #define RLC_XT_INT_VEC_FORCE__NUM_25__SHIFT 0x19 |
38974 | #define RLC_XT_INT_VEC_FORCE__NUM_0_MASK 0x00000001L |
38975 | #define RLC_XT_INT_VEC_FORCE__NUM_1_MASK 0x00000002L |
38976 | #define RLC_XT_INT_VEC_FORCE__NUM_2_MASK 0x00000004L |
38977 | #define RLC_XT_INT_VEC_FORCE__NUM_3_MASK 0x00000008L |
38978 | #define RLC_XT_INT_VEC_FORCE__NUM_4_MASK 0x00000010L |
38979 | #define RLC_XT_INT_VEC_FORCE__NUM_5_MASK 0x00000020L |
38980 | #define RLC_XT_INT_VEC_FORCE__NUM_6_MASK 0x00000040L |
38981 | #define RLC_XT_INT_VEC_FORCE__NUM_7_MASK 0x00000080L |
38982 | #define RLC_XT_INT_VEC_FORCE__NUM_8_MASK 0x00000100L |
38983 | #define RLC_XT_INT_VEC_FORCE__NUM_9_MASK 0x00000200L |
38984 | #define RLC_XT_INT_VEC_FORCE__NUM_10_MASK 0x00000400L |
38985 | #define RLC_XT_INT_VEC_FORCE__NUM_11_MASK 0x00000800L |
38986 | #define RLC_XT_INT_VEC_FORCE__NUM_12_MASK 0x00001000L |
38987 | #define RLC_XT_INT_VEC_FORCE__NUM_13_MASK 0x00002000L |
38988 | #define RLC_XT_INT_VEC_FORCE__NUM_14_MASK 0x00004000L |
38989 | #define RLC_XT_INT_VEC_FORCE__NUM_15_MASK 0x00008000L |
38990 | #define RLC_XT_INT_VEC_FORCE__NUM_16_MASK 0x00010000L |
38991 | #define RLC_XT_INT_VEC_FORCE__NUM_17_MASK 0x00020000L |
38992 | #define RLC_XT_INT_VEC_FORCE__NUM_18_MASK 0x00040000L |
38993 | #define RLC_XT_INT_VEC_FORCE__NUM_19_MASK 0x00080000L |
38994 | #define RLC_XT_INT_VEC_FORCE__NUM_20_MASK 0x00100000L |
38995 | #define RLC_XT_INT_VEC_FORCE__NUM_21_MASK 0x00200000L |
38996 | #define RLC_XT_INT_VEC_FORCE__NUM_22_MASK 0x00400000L |
38997 | #define RLC_XT_INT_VEC_FORCE__NUM_23_MASK 0x00800000L |
38998 | #define RLC_XT_INT_VEC_FORCE__NUM_24_MASK 0x01000000L |
38999 | #define RLC_XT_INT_VEC_FORCE__NUM_25_MASK 0x02000000L |
39000 | //RLC_XT_INT_VEC_CLEAR |
39001 | #define RLC_XT_INT_VEC_CLEAR__NUM_0__SHIFT 0x0 |
39002 | #define RLC_XT_INT_VEC_CLEAR__NUM_1__SHIFT 0x1 |
39003 | #define RLC_XT_INT_VEC_CLEAR__NUM_2__SHIFT 0x2 |
39004 | #define RLC_XT_INT_VEC_CLEAR__NUM_3__SHIFT 0x3 |
39005 | #define RLC_XT_INT_VEC_CLEAR__NUM_4__SHIFT 0x4 |
39006 | #define RLC_XT_INT_VEC_CLEAR__NUM_5__SHIFT 0x5 |
39007 | #define RLC_XT_INT_VEC_CLEAR__NUM_6__SHIFT 0x6 |
39008 | #define RLC_XT_INT_VEC_CLEAR__NUM_7__SHIFT 0x7 |
39009 | #define RLC_XT_INT_VEC_CLEAR__NUM_8__SHIFT 0x8 |
39010 | #define RLC_XT_INT_VEC_CLEAR__NUM_9__SHIFT 0x9 |
39011 | #define RLC_XT_INT_VEC_CLEAR__NUM_10__SHIFT 0xa |
39012 | #define RLC_XT_INT_VEC_CLEAR__NUM_11__SHIFT 0xb |
39013 | #define RLC_XT_INT_VEC_CLEAR__NUM_12__SHIFT 0xc |
39014 | #define RLC_XT_INT_VEC_CLEAR__NUM_13__SHIFT 0xd |
39015 | #define RLC_XT_INT_VEC_CLEAR__NUM_14__SHIFT 0xe |
39016 | #define RLC_XT_INT_VEC_CLEAR__NUM_15__SHIFT 0xf |
39017 | #define RLC_XT_INT_VEC_CLEAR__NUM_16__SHIFT 0x10 |
39018 | #define RLC_XT_INT_VEC_CLEAR__NUM_17__SHIFT 0x11 |
39019 | #define RLC_XT_INT_VEC_CLEAR__NUM_18__SHIFT 0x12 |
39020 | #define RLC_XT_INT_VEC_CLEAR__NUM_19__SHIFT 0x13 |
39021 | #define RLC_XT_INT_VEC_CLEAR__NUM_20__SHIFT 0x14 |
39022 | #define RLC_XT_INT_VEC_CLEAR__NUM_21__SHIFT 0x15 |
39023 | #define RLC_XT_INT_VEC_CLEAR__NUM_22__SHIFT 0x16 |
39024 | #define RLC_XT_INT_VEC_CLEAR__NUM_23__SHIFT 0x17 |
39025 | #define RLC_XT_INT_VEC_CLEAR__NUM_24__SHIFT 0x18 |
39026 | #define RLC_XT_INT_VEC_CLEAR__NUM_25__SHIFT 0x19 |
39027 | #define RLC_XT_INT_VEC_CLEAR__NUM_0_MASK 0x00000001L |
39028 | #define RLC_XT_INT_VEC_CLEAR__NUM_1_MASK 0x00000002L |
39029 | #define RLC_XT_INT_VEC_CLEAR__NUM_2_MASK 0x00000004L |
39030 | #define RLC_XT_INT_VEC_CLEAR__NUM_3_MASK 0x00000008L |
39031 | #define RLC_XT_INT_VEC_CLEAR__NUM_4_MASK 0x00000010L |
39032 | #define RLC_XT_INT_VEC_CLEAR__NUM_5_MASK 0x00000020L |
39033 | #define RLC_XT_INT_VEC_CLEAR__NUM_6_MASK 0x00000040L |
39034 | #define RLC_XT_INT_VEC_CLEAR__NUM_7_MASK 0x00000080L |
39035 | #define RLC_XT_INT_VEC_CLEAR__NUM_8_MASK 0x00000100L |
39036 | #define RLC_XT_INT_VEC_CLEAR__NUM_9_MASK 0x00000200L |
39037 | #define RLC_XT_INT_VEC_CLEAR__NUM_10_MASK 0x00000400L |
39038 | #define RLC_XT_INT_VEC_CLEAR__NUM_11_MASK 0x00000800L |
39039 | #define RLC_XT_INT_VEC_CLEAR__NUM_12_MASK 0x00001000L |
39040 | #define RLC_XT_INT_VEC_CLEAR__NUM_13_MASK 0x00002000L |
39041 | #define RLC_XT_INT_VEC_CLEAR__NUM_14_MASK 0x00004000L |
39042 | #define RLC_XT_INT_VEC_CLEAR__NUM_15_MASK 0x00008000L |
39043 | #define RLC_XT_INT_VEC_CLEAR__NUM_16_MASK 0x00010000L |
39044 | #define RLC_XT_INT_VEC_CLEAR__NUM_17_MASK 0x00020000L |
39045 | #define RLC_XT_INT_VEC_CLEAR__NUM_18_MASK 0x00040000L |
39046 | #define RLC_XT_INT_VEC_CLEAR__NUM_19_MASK 0x00080000L |
39047 | #define RLC_XT_INT_VEC_CLEAR__NUM_20_MASK 0x00100000L |
39048 | #define RLC_XT_INT_VEC_CLEAR__NUM_21_MASK 0x00200000L |
39049 | #define RLC_XT_INT_VEC_CLEAR__NUM_22_MASK 0x00400000L |
39050 | #define RLC_XT_INT_VEC_CLEAR__NUM_23_MASK 0x00800000L |
39051 | #define RLC_XT_INT_VEC_CLEAR__NUM_24_MASK 0x01000000L |
39052 | #define RLC_XT_INT_VEC_CLEAR__NUM_25_MASK 0x02000000L |
39053 | //RLC_XT_INT_VEC_MUX_SEL |
39054 | #define RLC_XT_INT_VEC_MUX_SEL__MUX_SEL__SHIFT 0x0 |
39055 | #define RLC_XT_INT_VEC_MUX_SEL__MUX_SEL_MASK 0x0000001FL |
39056 | //RLC_XT_INT_VEC_MUX_INT_SEL |
39057 | #define RLC_XT_INT_VEC_MUX_INT_SEL__INT_SEL__SHIFT 0x0 |
39058 | #define RLC_XT_INT_VEC_MUX_INT_SEL__INT_SEL_MASK 0x0000003FL |
39059 | //RLC_GPU_CLOCK_COUNT_SPM_LSB |
39060 | #define RLC_GPU_CLOCK_COUNT_SPM_LSB__GPU_CLOCKS_LSB__SHIFT 0x0 |
39061 | #define RLC_GPU_CLOCK_COUNT_SPM_LSB__GPU_CLOCKS_LSB_MASK 0xFFFFFFFFL |
39062 | //RLC_GPU_CLOCK_COUNT_SPM_MSB |
39063 | #define RLC_GPU_CLOCK_COUNT_SPM_MSB__GPU_CLOCKS_MSB__SHIFT 0x0 |
39064 | #define RLC_GPU_CLOCK_COUNT_SPM_MSB__GPU_CLOCKS_MSB_MASK 0xFFFFFFFFL |
39065 | //RLC_SPM_THREAD_TRACE_CTRL |
39066 | #define RLC_SPM_THREAD_TRACE_CTRL__THREAD_TRACE_INT_EN__SHIFT 0x0 |
39067 | #define RLC_SPM_THREAD_TRACE_CTRL__THREAD_TRACE_INT_EN_MASK 0x00000001L |
39068 | //RLC_SPP_CAM_ADDR |
39069 | #define RLC_SPP_CAM_ADDR__ADDR__SHIFT 0x0 |
39070 | #define RLC_SPP_CAM_ADDR__ADDR_MASK 0x000000FFL |
39071 | //RLC_SPP_CAM_DATA |
39072 | #define RLC_SPP_CAM_DATA__DATA__SHIFT 0x0 |
39073 | #define RLC_SPP_CAM_DATA__TAG__SHIFT 0x8 |
39074 | #define RLC_SPP_CAM_DATA__DATA_MASK 0x000000FFL |
39075 | #define RLC_SPP_CAM_DATA__TAG_MASK 0xFFFFFF00L |
39076 | //RLC_SPP_CAM_EXT_ADDR |
39077 | #define RLC_SPP_CAM_EXT_ADDR__ADDR__SHIFT 0x0 |
39078 | #define RLC_SPP_CAM_EXT_ADDR__ADDR_MASK 0x000000FFL |
39079 | //RLC_SPP_CAM_EXT_DATA |
39080 | #define RLC_SPP_CAM_EXT_DATA__VALID__SHIFT 0x0 |
39081 | #define RLC_SPP_CAM_EXT_DATA__LOCK__SHIFT 0x1 |
39082 | #define RLC_SPP_CAM_EXT_DATA__VALID_MASK 0x00000001L |
39083 | #define RLC_SPP_CAM_EXT_DATA__LOCK_MASK 0x00000002L |
39084 | //RLC_CPAXI_DOORBELL_MON_CTRL |
39085 | #define RLC_CPAXI_DOORBELL_MON_CTRL__EN__SHIFT 0x0 |
39086 | #define RLC_CPAXI_DOORBELL_MON_CTRL__ID__SHIFT 0x1 |
39087 | #define RLC_CPAXI_DOORBELL_MON_CTRL__EN_MASK 0x00000001L |
39088 | #define RLC_CPAXI_DOORBELL_MON_CTRL__ID_MASK 0x0000003EL |
39089 | //RLC_CPAXI_DOORBELL_MON_STAT |
39090 | #define RLC_CPAXI_DOORBELL_MON_STAT__ID_MATCH__SHIFT 0x0 |
39091 | #define RLC_CPAXI_DOORBELL_MON_STAT__MATCH_CLEAR__SHIFT 0x1 |
39092 | #define RLC_CPAXI_DOORBELL_MON_STAT__ADDR__SHIFT 0x2 |
39093 | #define RLC_CPAXI_DOORBELL_MON_STAT__ID_MATCH_MASK 0x00000001L |
39094 | #define RLC_CPAXI_DOORBELL_MON_STAT__MATCH_CLEAR_MASK 0x00000002L |
39095 | #define RLC_CPAXI_DOORBELL_MON_STAT__ADDR_MASK 0x0FFFFFFCL |
39096 | //RLC_CPAXI_DOORBELL_MON_DATA_LSB |
39097 | #define RLC_CPAXI_DOORBELL_MON_DATA_LSB__DATA__SHIFT 0x0 |
39098 | #define RLC_CPAXI_DOORBELL_MON_DATA_LSB__DATA_MASK 0xFFFFFFFFL |
39099 | //RLC_CPAXI_DOORBELL_MON_DATA_MSB |
39100 | #define RLC_CPAXI_DOORBELL_MON_DATA_MSB__DATA__SHIFT 0x0 |
39101 | #define RLC_CPAXI_DOORBELL_MON_DATA_MSB__DATA_MASK 0xFFFFFFFFL |
39102 | //RLC_XT_DOORBELL_RANGE |
39103 | #define RLC_XT_DOORBELL_RANGE__LOWER_ADDR_RESERVED__SHIFT 0x0 |
39104 | #define RLC_XT_DOORBELL_RANGE__LOWER_ADDR__SHIFT 0x2 |
39105 | #define RLC_XT_DOORBELL_RANGE__UPPER_ADDR_RESERVED__SHIFT 0x10 |
39106 | #define RLC_XT_DOORBELL_RANGE__UPPER_ADDR__SHIFT 0x12 |
39107 | #define RLC_XT_DOORBELL_RANGE__LOWER_ADDR_RESERVED_MASK 0x00000003L |
39108 | #define RLC_XT_DOORBELL_RANGE__LOWER_ADDR_MASK 0x00000FFCL |
39109 | #define RLC_XT_DOORBELL_RANGE__UPPER_ADDR_RESERVED_MASK 0x00030000L |
39110 | #define RLC_XT_DOORBELL_RANGE__UPPER_ADDR_MASK 0x0FFC0000L |
39111 | //RLC_XT_DOORBELL_CNTL |
39112 | #define RLC_XT_DOORBELL_CNTL__DOORBELL_0_MODE__SHIFT 0x0 |
39113 | #define RLC_XT_DOORBELL_CNTL__DOORBELL_1_MODE__SHIFT 0x2 |
39114 | #define RLC_XT_DOORBELL_CNTL__DOORBELL_2_MODE__SHIFT 0x4 |
39115 | #define RLC_XT_DOORBELL_CNTL__DOORBELL_3_MODE__SHIFT 0x6 |
39116 | #define RLC_XT_DOORBELL_CNTL__DOORBELL_ID__SHIFT 0x10 |
39117 | #define RLC_XT_DOORBELL_CNTL__DOORBELL_ID_EN__SHIFT 0x15 |
39118 | #define RLC_XT_DOORBELL_CNTL__DOORBELL_0_MODE_MASK 0x00000003L |
39119 | #define RLC_XT_DOORBELL_CNTL__DOORBELL_1_MODE_MASK 0x0000000CL |
39120 | #define RLC_XT_DOORBELL_CNTL__DOORBELL_2_MODE_MASK 0x00000030L |
39121 | #define RLC_XT_DOORBELL_CNTL__DOORBELL_3_MODE_MASK 0x000000C0L |
39122 | #define RLC_XT_DOORBELL_CNTL__DOORBELL_ID_MASK 0x001F0000L |
39123 | #define RLC_XT_DOORBELL_CNTL__DOORBELL_ID_EN_MASK 0x00200000L |
39124 | //RLC_XT_DOORBELL_STAT |
39125 | #define RLC_XT_DOORBELL_STAT__DOORBELL_0_VALID__SHIFT 0x0 |
39126 | #define RLC_XT_DOORBELL_STAT__DOORBELL_1_VALID__SHIFT 0x1 |
39127 | #define RLC_XT_DOORBELL_STAT__DOORBELL_2_VALID__SHIFT 0x2 |
39128 | #define RLC_XT_DOORBELL_STAT__DOORBELL_3_VALID__SHIFT 0x3 |
39129 | #define RLC_XT_DOORBELL_STAT__DOORBELL_0_VALID_MASK 0x00000001L |
39130 | #define RLC_XT_DOORBELL_STAT__DOORBELL_1_VALID_MASK 0x00000002L |
39131 | #define RLC_XT_DOORBELL_STAT__DOORBELL_2_VALID_MASK 0x00000004L |
39132 | #define RLC_XT_DOORBELL_STAT__DOORBELL_3_VALID_MASK 0x00000008L |
39133 | //RLC_XT_DOORBELL_0_DATA_LO |
39134 | #define RLC_XT_DOORBELL_0_DATA_LO__DATA__SHIFT 0x0 |
39135 | #define RLC_XT_DOORBELL_0_DATA_LO__DATA_MASK 0xFFFFFFFFL |
39136 | //RLC_XT_DOORBELL_0_DATA_HI |
39137 | #define RLC_XT_DOORBELL_0_DATA_HI__DATA__SHIFT 0x0 |
39138 | #define RLC_XT_DOORBELL_0_DATA_HI__DATA_MASK 0xFFFFFFFFL |
39139 | //RLC_XT_DOORBELL_1_DATA_LO |
39140 | #define RLC_XT_DOORBELL_1_DATA_LO__DATA__SHIFT 0x0 |
39141 | #define RLC_XT_DOORBELL_1_DATA_LO__DATA_MASK 0xFFFFFFFFL |
39142 | //RLC_XT_DOORBELL_1_DATA_HI |
39143 | #define RLC_XT_DOORBELL_1_DATA_HI__DATA__SHIFT 0x0 |
39144 | #define RLC_XT_DOORBELL_1_DATA_HI__DATA_MASK 0xFFFFFFFFL |
39145 | //RLC_XT_DOORBELL_2_DATA_LO |
39146 | #define RLC_XT_DOORBELL_2_DATA_LO__DATA__SHIFT 0x0 |
39147 | #define RLC_XT_DOORBELL_2_DATA_LO__DATA_MASK 0xFFFFFFFFL |
39148 | //RLC_XT_DOORBELL_2_DATA_HI |
39149 | #define RLC_XT_DOORBELL_2_DATA_HI__DATA__SHIFT 0x0 |
39150 | #define RLC_XT_DOORBELL_2_DATA_HI__DATA_MASK 0xFFFFFFFFL |
39151 | //RLC_XT_DOORBELL_3_DATA_LO |
39152 | #define RLC_XT_DOORBELL_3_DATA_LO__DATA__SHIFT 0x0 |
39153 | #define RLC_XT_DOORBELL_3_DATA_LO__DATA_MASK 0xFFFFFFFFL |
39154 | //RLC_XT_DOORBELL_3_DATA_HI |
39155 | #define RLC_XT_DOORBELL_3_DATA_HI__DATA__SHIFT 0x0 |
39156 | #define RLC_XT_DOORBELL_3_DATA_HI__DATA_MASK 0xFFFFFFFFL |
39157 | //RLC_MEM_SLP_CNTL |
39158 | #define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN__SHIFT 0x0 |
39159 | #define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN__SHIFT 0x1 |
39160 | #define RLC_MEM_SLP_CNTL__RLC_SRM_MEM_LS_OVERRIDE__SHIFT 0x2 |
39161 | #define RLC_MEM_SLP_CNTL__RLC_SRM_MEM_DS_OVERRIDE__SHIFT 0x3 |
39162 | #define RLC_MEM_SLP_CNTL__RLC_SPM_MEM_LS_OVERRIDE__SHIFT 0x4 |
39163 | #define RLC_MEM_SLP_CNTL__RLC_SPM_MEM_DS_OVERRIDE__SHIFT 0x5 |
39164 | #define RLC_MEM_SLP_CNTL__RESERVED__SHIFT 0x6 |
39165 | #define RLC_MEM_SLP_CNTL__RLC_LS_DS_BUSY_OVERRIDE__SHIFT 0x7 |
39166 | #define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY__SHIFT 0x8 |
39167 | #define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY__SHIFT 0x10 |
39168 | #define RLC_MEM_SLP_CNTL__RLC_SPP_MEM_LS_OVERRIDE__SHIFT 0x18 |
39169 | #define RLC_MEM_SLP_CNTL__RLC_SPP_MEM_DS_OVERRIDE__SHIFT 0x19 |
39170 | #define RLC_MEM_SLP_CNTL__RESERVED1__SHIFT 0x1a |
39171 | #define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK 0x00000001L |
39172 | #define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN_MASK 0x00000002L |
39173 | #define RLC_MEM_SLP_CNTL__RLC_SRM_MEM_LS_OVERRIDE_MASK 0x00000004L |
39174 | #define RLC_MEM_SLP_CNTL__RLC_SRM_MEM_DS_OVERRIDE_MASK 0x00000008L |
39175 | #define RLC_MEM_SLP_CNTL__RLC_SPM_MEM_LS_OVERRIDE_MASK 0x00000010L |
39176 | #define RLC_MEM_SLP_CNTL__RLC_SPM_MEM_DS_OVERRIDE_MASK 0x00000020L |
39177 | #define RLC_MEM_SLP_CNTL__RESERVED_MASK 0x00000040L |
39178 | #define RLC_MEM_SLP_CNTL__RLC_LS_DS_BUSY_OVERRIDE_MASK 0x00000080L |
39179 | #define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY_MASK 0x0000FF00L |
39180 | #define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY_MASK 0x00FF0000L |
39181 | #define RLC_MEM_SLP_CNTL__RLC_SPP_MEM_LS_OVERRIDE_MASK 0x01000000L |
39182 | #define RLC_MEM_SLP_CNTL__RLC_SPP_MEM_DS_OVERRIDE_MASK 0x02000000L |
39183 | #define RLC_MEM_SLP_CNTL__RESERVED1_MASK 0xFC000000L |
39184 | //SMU_RLC_RESPONSE |
39185 | #define SMU_RLC_RESPONSE__RESP__SHIFT 0x0 |
39186 | #define SMU_RLC_RESPONSE__RESP_MASK 0xFFFFFFFFL |
39187 | //RLC_RLCV_SAFE_MODE |
39188 | #define RLC_RLCV_SAFE_MODE__CMD__SHIFT 0x0 |
39189 | #define RLC_RLCV_SAFE_MODE__MESSAGE__SHIFT 0x1 |
39190 | #define RLC_RLCV_SAFE_MODE__RESERVED1__SHIFT 0x5 |
39191 | #define RLC_RLCV_SAFE_MODE__RESPONSE__SHIFT 0x8 |
39192 | #define RLC_RLCV_SAFE_MODE__RESERVED__SHIFT 0xc |
39193 | #define RLC_RLCV_SAFE_MODE__CMD_MASK 0x00000001L |
39194 | #define RLC_RLCV_SAFE_MODE__MESSAGE_MASK 0x0000001EL |
39195 | #define RLC_RLCV_SAFE_MODE__RESERVED1_MASK 0x000000E0L |
39196 | #define RLC_RLCV_SAFE_MODE__RESPONSE_MASK 0x00000F00L |
39197 | #define RLC_RLCV_SAFE_MODE__RESERVED_MASK 0xFFFFF000L |
39198 | //RLC_SMU_SAFE_MODE |
39199 | #define RLC_SMU_SAFE_MODE__CMD__SHIFT 0x0 |
39200 | #define RLC_SMU_SAFE_MODE__MESSAGE__SHIFT 0x1 |
39201 | #define RLC_SMU_SAFE_MODE__RESERVED1__SHIFT 0x5 |
39202 | #define RLC_SMU_SAFE_MODE__RESPONSE__SHIFT 0x8 |
39203 | #define RLC_SMU_SAFE_MODE__RESERVED__SHIFT 0xc |
39204 | #define RLC_SMU_SAFE_MODE__CMD_MASK 0x00000001L |
39205 | #define RLC_SMU_SAFE_MODE__MESSAGE_MASK 0x0000001EL |
39206 | #define RLC_SMU_SAFE_MODE__RESERVED1_MASK 0x000000E0L |
39207 | #define RLC_SMU_SAFE_MODE__RESPONSE_MASK 0x00000F00L |
39208 | #define RLC_SMU_SAFE_MODE__RESERVED_MASK 0xFFFFF000L |
39209 | //RLC_RLCV_COMMAND |
39210 | #define RLC_RLCV_COMMAND__CMD__SHIFT 0x0 |
39211 | #define RLC_RLCV_COMMAND__RESERVED__SHIFT 0x4 |
39212 | #define RLC_RLCV_COMMAND__CMD_MASK 0x0000000FL |
39213 | #define RLC_RLCV_COMMAND__RESERVED_MASK 0xFFFFFFF0L |
39214 | //RLC_SMU_MESSAGE |
39215 | #define RLC_SMU_MESSAGE__CMD__SHIFT 0x0 |
39216 | #define RLC_SMU_MESSAGE__CMD_MASK 0xFFFFFFFFL |
39217 | //RLC_SMU_MESSAGE_1 |
39218 | #define RLC_SMU_MESSAGE_1__CMD__SHIFT 0x0 |
39219 | #define RLC_SMU_MESSAGE_1__CMD_MASK 0xFFFFFFFFL |
39220 | //RLC_SMU_MESSAGE_2 |
39221 | #define RLC_SMU_MESSAGE_2__CMD__SHIFT 0x0 |
39222 | #define RLC_SMU_MESSAGE_2__CMD_MASK 0xFFFFFFFFL |
39223 | //RLC_SRM_GPM_COMMAND |
39224 | #define RLC_SRM_GPM_COMMAND__OP__SHIFT 0x0 |
39225 | #define RLC_SRM_GPM_COMMAND__INDEX_CNTL__SHIFT 0x1 |
39226 | #define RLC_SRM_GPM_COMMAND__INDEX_CNTL_NUM__SHIFT 0x2 |
39227 | #define RLC_SRM_GPM_COMMAND__SIZE__SHIFT 0x5 |
39228 | #define RLC_SRM_GPM_COMMAND__START_OFFSET__SHIFT 0x12 |
39229 | #define RLC_SRM_GPM_COMMAND__DEST_MEMORY__SHIFT 0x1f |
39230 | #define RLC_SRM_GPM_COMMAND__OP_MASK 0x00000001L |
39231 | #define RLC_SRM_GPM_COMMAND__INDEX_CNTL_MASK 0x00000002L |
39232 | #define RLC_SRM_GPM_COMMAND__INDEX_CNTL_NUM_MASK 0x0000001CL |
39233 | #define RLC_SRM_GPM_COMMAND__SIZE_MASK 0x0003FFE0L |
39234 | #define RLC_SRM_GPM_COMMAND__START_OFFSET_MASK 0x7FFC0000L |
39235 | #define RLC_SRM_GPM_COMMAND__DEST_MEMORY_MASK 0x80000000L |
39236 | //RLC_SRM_GPM_ABORT |
39237 | #define RLC_SRM_GPM_ABORT__ABORT__SHIFT 0x0 |
39238 | #define RLC_SRM_GPM_ABORT__RESERVED__SHIFT 0x1 |
39239 | #define RLC_SRM_GPM_ABORT__ABORT_MASK 0x00000001L |
39240 | #define RLC_SRM_GPM_ABORT__RESERVED_MASK 0xFFFFFFFEL |
39241 | //RLC_SMU_COMMAND |
39242 | #define RLC_SMU_COMMAND__CMD__SHIFT 0x0 |
39243 | #define RLC_SMU_COMMAND__CMD_MASK 0xFFFFFFFFL |
39244 | //RLC_SMU_ARGUMENT_1 |
39245 | #define RLC_SMU_ARGUMENT_1__ARG__SHIFT 0x0 |
39246 | #define RLC_SMU_ARGUMENT_1__ARG_MASK 0xFFFFFFFFL |
39247 | //RLC_SMU_ARGUMENT_2 |
39248 | #define RLC_SMU_ARGUMENT_2__ARG__SHIFT 0x0 |
39249 | #define RLC_SMU_ARGUMENT_2__ARG_MASK 0xFFFFFFFFL |
39250 | //RLC_SMU_ARGUMENT_3 |
39251 | #define RLC_SMU_ARGUMENT_3__ARG__SHIFT 0x0 |
39252 | #define RLC_SMU_ARGUMENT_3__ARG_MASK 0xFFFFFFFFL |
39253 | //RLC_SMU_ARGUMENT_4 |
39254 | #define RLC_SMU_ARGUMENT_4__ARG__SHIFT 0x0 |
39255 | #define RLC_SMU_ARGUMENT_4__ARG_MASK 0xFFFFFFFFL |
39256 | //RLC_SMU_ARGUMENT_5 |
39257 | #define RLC_SMU_ARGUMENT_5__ARG__SHIFT 0x0 |
39258 | #define RLC_SMU_ARGUMENT_5__ARG_MASK 0xFFFFFFFFL |
39259 | //RLC_IMU_BOOTLOAD_ADDR_HI |
39260 | #define RLC_IMU_BOOTLOAD_ADDR_HI__ADDR_HI__SHIFT 0x0 |
39261 | #define RLC_IMU_BOOTLOAD_ADDR_HI__ADDR_HI_MASK 0xFFFFFFFFL |
39262 | //RLC_IMU_BOOTLOAD_ADDR_LO |
39263 | #define RLC_IMU_BOOTLOAD_ADDR_LO__ADDR_LO__SHIFT 0x0 |
39264 | #define RLC_IMU_BOOTLOAD_ADDR_LO__ADDR_LO_MASK 0xFFFFFFFFL |
39265 | //RLC_IMU_BOOTLOAD_SIZE |
39266 | #define RLC_IMU_BOOTLOAD_SIZE__SIZE__SHIFT 0x0 |
39267 | #define RLC_IMU_BOOTLOAD_SIZE__RESERVED__SHIFT 0x1a |
39268 | #define RLC_IMU_BOOTLOAD_SIZE__SIZE_MASK 0x03FFFFFFL |
39269 | #define RLC_IMU_BOOTLOAD_SIZE__RESERVED_MASK 0xFC000000L |
39270 | //RLC_IMU_MISC |
39271 | #define RLC_IMU_MISC__THROTTLE_GFX__SHIFT 0x0 |
39272 | #define RLC_IMU_MISC__EARLY_MGCG__SHIFT 0x1 |
39273 | #define RLC_IMU_MISC__RESERVED__SHIFT 0x2 |
39274 | #define RLC_IMU_MISC__THROTTLE_GFX_MASK 0x00000001L |
39275 | #define RLC_IMU_MISC__EARLY_MGCG_MASK 0x00000002L |
39276 | #define RLC_IMU_MISC__RESERVED_MASK 0xFFFFFFFCL |
39277 | //RLC_IMU_RESET_VECTOR |
39278 | #define RLC_IMU_RESET_VECTOR__COLD_BOOT_EXIT__SHIFT 0x0 |
39279 | #define RLC_IMU_RESET_VECTOR__VDDGFX_EXIT__SHIFT 0x1 |
39280 | #define RLC_IMU_RESET_VECTOR__VECTOR__SHIFT 0x2 |
39281 | #define RLC_IMU_RESET_VECTOR__RESERVED__SHIFT 0x8 |
39282 | #define RLC_IMU_RESET_VECTOR__COLD_BOOT_EXIT_MASK 0x00000001L |
39283 | #define RLC_IMU_RESET_VECTOR__VDDGFX_EXIT_MASK 0x00000002L |
39284 | #define RLC_IMU_RESET_VECTOR__VECTOR_MASK 0x000000FCL |
39285 | #define RLC_IMU_RESET_VECTOR__RESERVED_MASK 0xFFFFFF00L |
39286 | |
39287 | |
39288 | // addressBlock: gc_rlcsdec |
39289 | //RLC_RLCS_DEC_START |
39290 | //RLC_RLCS_DEC_DUMP_ADDR |
39291 | //RLC_RLCS_EXCEPTION_REG_1 |
39292 | #define RLC_RLCS_EXCEPTION_REG_1__ADDR__SHIFT 0x0 |
39293 | #define RLC_RLCS_EXCEPTION_REG_1__RESERVED__SHIFT 0x12 |
39294 | #define RLC_RLCS_EXCEPTION_REG_1__ADDR_MASK 0x0003FFFFL |
39295 | #define RLC_RLCS_EXCEPTION_REG_1__RESERVED_MASK 0xFFFC0000L |
39296 | //RLC_RLCS_EXCEPTION_REG_2 |
39297 | #define RLC_RLCS_EXCEPTION_REG_2__ADDR__SHIFT 0x0 |
39298 | #define RLC_RLCS_EXCEPTION_REG_2__RESERVED__SHIFT 0x12 |
39299 | #define RLC_RLCS_EXCEPTION_REG_2__ADDR_MASK 0x0003FFFFL |
39300 | #define RLC_RLCS_EXCEPTION_REG_2__RESERVED_MASK 0xFFFC0000L |
39301 | //RLC_RLCS_EXCEPTION_REG_3 |
39302 | #define RLC_RLCS_EXCEPTION_REG_3__ADDR__SHIFT 0x0 |
39303 | #define RLC_RLCS_EXCEPTION_REG_3__RESERVED__SHIFT 0x12 |
39304 | #define RLC_RLCS_EXCEPTION_REG_3__ADDR_MASK 0x0003FFFFL |
39305 | #define RLC_RLCS_EXCEPTION_REG_3__RESERVED_MASK 0xFFFC0000L |
39306 | //RLC_RLCS_EXCEPTION_REG_4 |
39307 | #define RLC_RLCS_EXCEPTION_REG_4__ADDR__SHIFT 0x0 |
39308 | #define RLC_RLCS_EXCEPTION_REG_4__RESERVED__SHIFT 0x12 |
39309 | #define RLC_RLCS_EXCEPTION_REG_4__ADDR_MASK 0x0003FFFFL |
39310 | #define RLC_RLCS_EXCEPTION_REG_4__RESERVED_MASK 0xFFFC0000L |
39311 | //RLC_RLCS_CGCG_REQUEST |
39312 | #define RLC_RLCS_CGCG_REQUEST__CGCG_REQUEST__SHIFT 0x0 |
39313 | #define RLC_RLCS_CGCG_REQUEST__CGCG_REQUEST_3D__SHIFT 0x1 |
39314 | #define RLC_RLCS_CGCG_REQUEST__RESERVED__SHIFT 0x2 |
39315 | #define RLC_RLCS_CGCG_REQUEST__CGCG_REQUEST_MASK 0x00000001L |
39316 | #define RLC_RLCS_CGCG_REQUEST__CGCG_REQUEST_3D_MASK 0x00000002L |
39317 | #define RLC_RLCS_CGCG_REQUEST__RESERVED_MASK 0xFFFFFFFCL |
39318 | //RLC_RLCS_CGCG_STATUS |
39319 | #define RLC_RLCS_CGCG_STATUS__CGCG_RAMP_STATUS__SHIFT 0x0 |
39320 | #define RLC_RLCS_CGCG_STATUS__GFX_CLK_STATUS__SHIFT 0x2 |
39321 | #define RLC_RLCS_CGCG_STATUS__CGCG_RAMP_STATUS_3D__SHIFT 0x3 |
39322 | #define RLC_RLCS_CGCG_STATUS__GFX_CLK_STATUS_3D__SHIFT 0x5 |
39323 | #define RLC_RLCS_CGCG_STATUS__RESERVED__SHIFT 0x6 |
39324 | #define RLC_RLCS_CGCG_STATUS__CGCG_RAMP_STATUS_MASK 0x00000003L |
39325 | #define RLC_RLCS_CGCG_STATUS__GFX_CLK_STATUS_MASK 0x00000004L |
39326 | #define RLC_RLCS_CGCG_STATUS__CGCG_RAMP_STATUS_3D_MASK 0x00000018L |
39327 | #define RLC_RLCS_CGCG_STATUS__GFX_CLK_STATUS_3D_MASK 0x00000020L |
39328 | #define RLC_RLCS_CGCG_STATUS__RESERVED_MASK 0xFFFFFFC0L |
39329 | //RLC_RLCS_SOC_DS_CNTL |
39330 | #define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_ALLOW__SHIFT 0x0 |
39331 | #define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_RLC_BUSY_MASK__SHIFT 0x1 |
39332 | #define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_CP_BUSY_MASK__SHIFT 0x2 |
39333 | #define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_GFX_PWR_STALLED_MASK__SHIFT 0x6 |
39334 | #define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_NON3D_PWR_STALLED_MASK__SHIFT 0x7 |
39335 | #define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_0_BUSY_MASK__SHIFT 0x10 |
39336 | #define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_1_BUSY_MASK__SHIFT 0x11 |
39337 | #define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_2_BUSY_MASK__SHIFT 0x12 |
39338 | #define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_3_BUSY_MASK__SHIFT 0x13 |
39339 | #define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_4_BUSY_MASK__SHIFT 0x14 |
39340 | #define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_5_BUSY_MASK__SHIFT 0x15 |
39341 | #define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_6_BUSY_MASK__SHIFT 0x16 |
39342 | #define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_7_BUSY_MASK__SHIFT 0x17 |
39343 | #define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_ALLOW_MASK 0x00000001L |
39344 | #define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_RLC_BUSY_MASK_MASK 0x00000002L |
39345 | #define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_CP_BUSY_MASK_MASK 0x00000004L |
39346 | #define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_GFX_PWR_STALLED_MASK_MASK 0x00000040L |
39347 | #define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_NON3D_PWR_STALLED_MASK_MASK 0x00000080L |
39348 | #define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_0_BUSY_MASK_MASK 0x00010000L |
39349 | #define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_1_BUSY_MASK_MASK 0x00020000L |
39350 | #define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_2_BUSY_MASK_MASK 0x00040000L |
39351 | #define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_3_BUSY_MASK_MASK 0x00080000L |
39352 | #define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_4_BUSY_MASK_MASK 0x00100000L |
39353 | #define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_5_BUSY_MASK_MASK 0x00200000L |
39354 | #define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_6_BUSY_MASK_MASK 0x00400000L |
39355 | #define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_7_BUSY_MASK_MASK 0x00800000L |
39356 | //RLC_RLCS_GFX_DS_CNTL |
39357 | #define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_ALLOW__SHIFT 0x0 |
39358 | #define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_RLC_BUSY_MASK__SHIFT 0x1 |
39359 | #define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_CP_BUSY_MASK__SHIFT 0x2 |
39360 | #define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_GFX_PWR_STALLED_MASK__SHIFT 0x6 |
39361 | #define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_NON3D_PWR_STALLED_MASK__SHIFT 0x7 |
39362 | #define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_IMU_DISABLE_MASK__SHIFT 0x8 |
39363 | #define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_0_BUSY_MASK__SHIFT 0x10 |
39364 | #define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_1_BUSY_MASK__SHIFT 0x11 |
39365 | #define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_2_BUSY_MASK__SHIFT 0x12 |
39366 | #define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_3_BUSY_MASK__SHIFT 0x13 |
39367 | #define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_4_BUSY_MASK__SHIFT 0x14 |
39368 | #define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_5_BUSY_MASK__SHIFT 0x15 |
39369 | #define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_6_BUSY_MASK__SHIFT 0x16 |
39370 | #define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_7_BUSY_MASK__SHIFT 0x17 |
39371 | #define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_ALLOW_MASK 0x00000001L |
39372 | #define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_RLC_BUSY_MASK_MASK 0x00000002L |
39373 | #define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_CP_BUSY_MASK_MASK 0x00000004L |
39374 | #define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_GFX_PWR_STALLED_MASK_MASK 0x00000040L |
39375 | #define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_NON3D_PWR_STALLED_MASK_MASK 0x00000080L |
39376 | #define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_IMU_DISABLE_MASK_MASK 0x00000100L |
39377 | #define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_0_BUSY_MASK_MASK 0x00010000L |
39378 | #define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_1_BUSY_MASK_MASK 0x00020000L |
39379 | #define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_2_BUSY_MASK_MASK 0x00040000L |
39380 | #define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_3_BUSY_MASK_MASK 0x00080000L |
39381 | #define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_4_BUSY_MASK_MASK 0x00100000L |
39382 | #define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_5_BUSY_MASK_MASK 0x00200000L |
39383 | #define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_6_BUSY_MASK_MASK 0x00400000L |
39384 | #define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_7_BUSY_MASK_MASK 0x00800000L |
39385 | //RLC_RLCS_GFX_DS_ALLOW_MASK_CNTL |
39386 | #define RLC_RLCS_GFX_DS_ALLOW_MASK_CNTL__GFX_CLK_DS_ALLOW_MASK_GDFLL__SHIFT 0x0 |
39387 | #define RLC_RLCS_GFX_DS_ALLOW_MASK_CNTL__GFX_CLK_DS_ALLOW_MASK_GDFLL_SE0__SHIFT 0x1 |
39388 | #define RLC_RLCS_GFX_DS_ALLOW_MASK_CNTL__GFX_CLK_DS_ALLOW_MASK_GDFLL_SE1__SHIFT 0x2 |
39389 | #define RLC_RLCS_GFX_DS_ALLOW_MASK_CNTL__GFX_CLK_DS_ALLOW_MASK_GDFLL_SE2__SHIFT 0x3 |
39390 | #define RLC_RLCS_GFX_DS_ALLOW_MASK_CNTL__GFX_CLK_DS_ALLOW_MASK_GDFLL_MASK 0x00000001L |
39391 | #define RLC_RLCS_GFX_DS_ALLOW_MASK_CNTL__GFX_CLK_DS_ALLOW_MASK_GDFLL_SE0_MASK 0x00000002L |
39392 | #define RLC_RLCS_GFX_DS_ALLOW_MASK_CNTL__GFX_CLK_DS_ALLOW_MASK_GDFLL_SE1_MASK 0x00000004L |
39393 | #define RLC_RLCS_GFX_DS_ALLOW_MASK_CNTL__GFX_CLK_DS_ALLOW_MASK_GDFLL_SE2_MASK 0x00000008L |
39394 | //RLC_GPM_STAT |
39395 | #define RLC_GPM_STAT__RLC_BUSY__SHIFT 0x0 |
39396 | #define RLC_GPM_STAT__GFX_POWER_STATUS__SHIFT 0x1 |
39397 | #define RLC_GPM_STAT__GFX_CLOCK_STATUS__SHIFT 0x2 |
39398 | #define RLC_GPM_STAT__GFX_LS_STATUS__SHIFT 0x3 |
39399 | #define RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS__SHIFT 0x4 |
39400 | #define RLC_GPM_STAT__CNTX_IDLE_BEING_PROCESSED__SHIFT 0x5 |
39401 | #define RLC_GPM_STAT__CNTX_BUSY_BEING_PROCESSED__SHIFT 0x6 |
39402 | #define RLC_GPM_STAT__GFX_IDLE_BEING_PROCESSED__SHIFT 0x7 |
39403 | #define RLC_GPM_STAT__CMP_BUSY_BEING_PROCESSED__SHIFT 0x8 |
39404 | #define RLC_GPM_STAT__SAVING_REGISTERS__SHIFT 0x9 |
39405 | #define RLC_GPM_STAT__RESTORING_REGISTERS__SHIFT 0xa |
39406 | #define RLC_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE__SHIFT 0xb |
39407 | #define RLC_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE__SHIFT 0xc |
39408 | #define RLC_GPM_STAT__STATIC_WGP_POWERING_UP__SHIFT 0xd |
39409 | #define RLC_GPM_STAT__STATIC_WGP_POWERING_DOWN__SHIFT 0xe |
39410 | #define RLC_GPM_STAT__DYN_WGP_POWERING_UP__SHIFT 0xf |
39411 | #define RLC_GPM_STAT__DYN_WGP_POWERING_DOWN__SHIFT 0x10 |
39412 | #define RLC_GPM_STAT__ABORTED_PD_SEQUENCE__SHIFT 0x11 |
39413 | #define RLC_GPM_STAT__CMP_power_status__SHIFT 0x12 |
39414 | #define RLC_GPM_STAT__GFX_LS_STATUS_3D__SHIFT 0x13 |
39415 | #define RLC_GPM_STAT__GFX_CLOCK_STATUS_3D__SHIFT 0x14 |
39416 | #define RLC_GPM_STAT__MGCG_OVERRIDE_STATUS__SHIFT 0x15 |
39417 | #define RLC_GPM_STAT__RLC_EXEC_ROM_CODE__SHIFT 0x16 |
39418 | #define RLC_GPM_STAT__FGCG_OVERRIDE_STATUS__SHIFT 0x17 |
39419 | #define RLC_GPM_STAT__PG_ERROR_STATUS__SHIFT 0x18 |
39420 | #define RLC_GPM_STAT__RLC_BUSY_MASK 0x00000001L |
39421 | #define RLC_GPM_STAT__GFX_POWER_STATUS_MASK 0x00000002L |
39422 | #define RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK 0x00000004L |
39423 | #define RLC_GPM_STAT__GFX_LS_STATUS_MASK 0x00000008L |
39424 | #define RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS_MASK 0x00000010L |
39425 | #define RLC_GPM_STAT__CNTX_IDLE_BEING_PROCESSED_MASK 0x00000020L |
39426 | #define RLC_GPM_STAT__CNTX_BUSY_BEING_PROCESSED_MASK 0x00000040L |
39427 | #define RLC_GPM_STAT__GFX_IDLE_BEING_PROCESSED_MASK 0x00000080L |
39428 | #define RLC_GPM_STAT__CMP_BUSY_BEING_PROCESSED_MASK 0x00000100L |
39429 | #define RLC_GPM_STAT__SAVING_REGISTERS_MASK 0x00000200L |
39430 | #define RLC_GPM_STAT__RESTORING_REGISTERS_MASK 0x00000400L |
39431 | #define RLC_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE_MASK 0x00000800L |
39432 | #define RLC_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE_MASK 0x00001000L |
39433 | #define RLC_GPM_STAT__STATIC_WGP_POWERING_UP_MASK 0x00002000L |
39434 | #define RLC_GPM_STAT__STATIC_WGP_POWERING_DOWN_MASK 0x00004000L |
39435 | #define RLC_GPM_STAT__DYN_WGP_POWERING_UP_MASK 0x00008000L |
39436 | #define RLC_GPM_STAT__DYN_WGP_POWERING_DOWN_MASK 0x00010000L |
39437 | #define RLC_GPM_STAT__ABORTED_PD_SEQUENCE_MASK 0x00020000L |
39438 | #define RLC_GPM_STAT__CMP_power_status_MASK 0x00040000L |
39439 | #define RLC_GPM_STAT__GFX_LS_STATUS_3D_MASK 0x00080000L |
39440 | #define RLC_GPM_STAT__GFX_CLOCK_STATUS_3D_MASK 0x00100000L |
39441 | #define RLC_GPM_STAT__MGCG_OVERRIDE_STATUS_MASK 0x00200000L |
39442 | #define RLC_GPM_STAT__RLC_EXEC_ROM_CODE_MASK 0x00400000L |
39443 | #define RLC_GPM_STAT__FGCG_OVERRIDE_STATUS_MASK 0x00800000L |
39444 | #define RLC_GPM_STAT__PG_ERROR_STATUS_MASK 0xFF000000L |
39445 | //RLC_RLCS_GPM_STAT |
39446 | #define RLC_RLCS_GPM_STAT__RLC_BUSY__SHIFT 0x0 |
39447 | #define RLC_RLCS_GPM_STAT__GFX_POWER_STATUS__SHIFT 0x1 |
39448 | #define RLC_RLCS_GPM_STAT__GFX_CLOCK_STATUS__SHIFT 0x2 |
39449 | #define RLC_RLCS_GPM_STAT__GFX_LS_STATUS__SHIFT 0x3 |
39450 | #define RLC_RLCS_GPM_STAT__GFX_PIPELINE_POWER_STATUS__SHIFT 0x4 |
39451 | #define RLC_RLCS_GPM_STAT__CNTX_IDLE_BEING_PROCESSED__SHIFT 0x5 |
39452 | #define RLC_RLCS_GPM_STAT__CNTX_BUSY_BEING_PROCESSED__SHIFT 0x6 |
39453 | #define RLC_RLCS_GPM_STAT__GFX_IDLE_BEING_PROCESSED__SHIFT 0x7 |
39454 | #define RLC_RLCS_GPM_STAT__CMP_BUSY_BEING_PROCESSED__SHIFT 0x8 |
39455 | #define RLC_RLCS_GPM_STAT__SAVING_REGISTERS__SHIFT 0x9 |
39456 | #define RLC_RLCS_GPM_STAT__RESTORING_REGISTERS__SHIFT 0xa |
39457 | #define RLC_RLCS_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE__SHIFT 0xb |
39458 | #define RLC_RLCS_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE__SHIFT 0xc |
39459 | #define RLC_RLCS_GPM_STAT__STATIC_WGP_POWERING_UP__SHIFT 0xd |
39460 | #define RLC_RLCS_GPM_STAT__STATIC_WGP_POWERING_DOWN__SHIFT 0xe |
39461 | #define RLC_RLCS_GPM_STAT__DYN_WGP_POWERING_UP__SHIFT 0xf |
39462 | #define RLC_RLCS_GPM_STAT__DYN_WGP_POWERING_DOWN__SHIFT 0x10 |
39463 | #define RLC_RLCS_GPM_STAT__ABORTED_PD_SEQUENCE__SHIFT 0x11 |
39464 | #define RLC_RLCS_GPM_STAT__CMP_POWER_STATUS__SHIFT 0x12 |
39465 | #define RLC_RLCS_GPM_STAT__GFX_LS_STATUS_3D__SHIFT 0x13 |
39466 | #define RLC_RLCS_GPM_STAT__GFX_CLOCK_STATUS_3D__SHIFT 0x14 |
39467 | #define RLC_RLCS_GPM_STAT__MGCG_OVERRIDE_STATUS__SHIFT 0x15 |
39468 | #define RLC_RLCS_GPM_STAT__RLC_EXEC_ROM_CODE__SHIFT 0x16 |
39469 | #define RLC_RLCS_GPM_STAT__FGCG_OVERRIDE_STATUS__SHIFT 0x17 |
39470 | #define RLC_RLCS_GPM_STAT__PG_ERROR_STATUS__SHIFT 0x18 |
39471 | #define RLC_RLCS_GPM_STAT__RLC_BUSY_MASK 0x00000001L |
39472 | #define RLC_RLCS_GPM_STAT__GFX_POWER_STATUS_MASK 0x00000002L |
39473 | #define RLC_RLCS_GPM_STAT__GFX_CLOCK_STATUS_MASK 0x00000004L |
39474 | #define RLC_RLCS_GPM_STAT__GFX_LS_STATUS_MASK 0x00000008L |
39475 | #define RLC_RLCS_GPM_STAT__GFX_PIPELINE_POWER_STATUS_MASK 0x00000010L |
39476 | #define RLC_RLCS_GPM_STAT__CNTX_IDLE_BEING_PROCESSED_MASK 0x00000020L |
39477 | #define RLC_RLCS_GPM_STAT__CNTX_BUSY_BEING_PROCESSED_MASK 0x00000040L |
39478 | #define RLC_RLCS_GPM_STAT__GFX_IDLE_BEING_PROCESSED_MASK 0x00000080L |
39479 | #define RLC_RLCS_GPM_STAT__CMP_BUSY_BEING_PROCESSED_MASK 0x00000100L |
39480 | #define RLC_RLCS_GPM_STAT__SAVING_REGISTERS_MASK 0x00000200L |
39481 | #define RLC_RLCS_GPM_STAT__RESTORING_REGISTERS_MASK 0x00000400L |
39482 | #define RLC_RLCS_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE_MASK 0x00000800L |
39483 | #define RLC_RLCS_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE_MASK 0x00001000L |
39484 | #define RLC_RLCS_GPM_STAT__STATIC_WGP_POWERING_UP_MASK 0x00002000L |
39485 | #define RLC_RLCS_GPM_STAT__STATIC_WGP_POWERING_DOWN_MASK 0x00004000L |
39486 | #define RLC_RLCS_GPM_STAT__DYN_WGP_POWERING_UP_MASK 0x00008000L |
39487 | #define RLC_RLCS_GPM_STAT__DYN_WGP_POWERING_DOWN_MASK 0x00010000L |
39488 | #define RLC_RLCS_GPM_STAT__ABORTED_PD_SEQUENCE_MASK 0x00020000L |
39489 | #define RLC_RLCS_GPM_STAT__CMP_POWER_STATUS_MASK 0x00040000L |
39490 | #define RLC_RLCS_GPM_STAT__GFX_LS_STATUS_3D_MASK 0x00080000L |
39491 | #define RLC_RLCS_GPM_STAT__GFX_CLOCK_STATUS_3D_MASK 0x00100000L |
39492 | #define RLC_RLCS_GPM_STAT__MGCG_OVERRIDE_STATUS_MASK 0x00200000L |
39493 | #define RLC_RLCS_GPM_STAT__RLC_EXEC_ROM_CODE_MASK 0x00400000L |
39494 | #define RLC_RLCS_GPM_STAT__FGCG_OVERRIDE_STATUS_MASK 0x00800000L |
39495 | #define RLC_RLCS_GPM_STAT__PG_ERROR_STATUS_MASK 0xFF000000L |
39496 | //RLC_RLCS_ABORTED_PD_SEQUENCE |
39497 | #define RLC_RLCS_ABORTED_PD_SEQUENCE__APS__SHIFT 0x0 |
39498 | #define RLC_RLCS_ABORTED_PD_SEQUENCE__RESERVED__SHIFT 0x10 |
39499 | #define RLC_RLCS_ABORTED_PD_SEQUENCE__APS_MASK 0x0000FFFFL |
39500 | #define RLC_RLCS_ABORTED_PD_SEQUENCE__RESERVED_MASK 0xFFFF0000L |
39501 | //RLC_RLCS_DIDT_FORCE_STALL |
39502 | #define RLC_RLCS_DIDT_FORCE_STALL__DFS__SHIFT 0x0 |
39503 | #define RLC_RLCS_DIDT_FORCE_STALL__VALID__SHIFT 0x3 |
39504 | #define RLC_RLCS_DIDT_FORCE_STALL__RESERVED__SHIFT 0x4 |
39505 | #define RLC_RLCS_DIDT_FORCE_STALL__DFS_MASK 0x00000007L |
39506 | #define RLC_RLCS_DIDT_FORCE_STALL__VALID_MASK 0x00000008L |
39507 | #define RLC_RLCS_DIDT_FORCE_STALL__RESERVED_MASK 0xFFFFFFF0L |
39508 | //RLC_RLCS_IOV_CMD_STATUS |
39509 | #define RLC_RLCS_IOV_CMD_STATUS__DATA__SHIFT 0x0 |
39510 | #define RLC_RLCS_IOV_CMD_STATUS__DATA_MASK 0xFFFFFFFFL |
39511 | //RLC_RLCS_IOV_CNTX_LOC_SIZE |
39512 | #define RLC_RLCS_IOV_CNTX_LOC_SIZE__DATA__SHIFT 0x0 |
39513 | #define RLC_RLCS_IOV_CNTX_LOC_SIZE__RESERVED__SHIFT 0x8 |
39514 | #define RLC_RLCS_IOV_CNTX_LOC_SIZE__DATA_MASK 0x000000FFL |
39515 | #define RLC_RLCS_IOV_CNTX_LOC_SIZE__RESERVED_MASK 0xFFFFFF00L |
39516 | //RLC_RLCS_IOV_SCH_BLOCK |
39517 | #define RLC_RLCS_IOV_SCH_BLOCK__DATA__SHIFT 0x0 |
39518 | #define RLC_RLCS_IOV_SCH_BLOCK__DATA_MASK 0xFFFFFFFFL |
39519 | //RLC_RLCS_IOV_VM_BUSY_STATUS |
39520 | #define RLC_RLCS_IOV_VM_BUSY_STATUS__DATA__SHIFT 0x0 |
39521 | #define RLC_RLCS_IOV_VM_BUSY_STATUS__DATA_MASK 0xFFFFFFFFL |
39522 | //RLC_RLCS_GPM_STAT_2 |
39523 | #define RLC_RLCS_GPM_STAT_2__TC_TRANS_ERROR__SHIFT 0x0 |
39524 | #define RLC_RLCS_GPM_STAT_2__RLC_PWR_NON3D_STALLED__SHIFT 0x1 |
39525 | #define RLC_RLCS_GPM_STAT_2__GFX_PWR_STALLED_STATUS__SHIFT 0x2 |
39526 | #define RLC_RLCS_GPM_STAT_2__GFX_ULV_STATUS__SHIFT 0x3 |
39527 | #define RLC_RLCS_GPM_STAT_2__GFX_GENERAL_STATUS__SHIFT 0x4 |
39528 | #define RLC_RLCS_GPM_STAT_2__RESERVED__SHIFT 0x5 |
39529 | #define RLC_RLCS_GPM_STAT_2__TC_TRANS_ERROR_MASK 0x00000001L |
39530 | #define RLC_RLCS_GPM_STAT_2__RLC_PWR_NON3D_STALLED_MASK 0x00000002L |
39531 | #define RLC_RLCS_GPM_STAT_2__GFX_PWR_STALLED_STATUS_MASK 0x00000004L |
39532 | #define RLC_RLCS_GPM_STAT_2__GFX_ULV_STATUS_MASK 0x00000008L |
39533 | #define RLC_RLCS_GPM_STAT_2__GFX_GENERAL_STATUS_MASK 0x00000010L |
39534 | #define RLC_RLCS_GPM_STAT_2__RESERVED_MASK 0xFFFFFFE0L |
39535 | //RLC_RLCS_GRBM_SOFT_RESET |
39536 | #define RLC_RLCS_GRBM_SOFT_RESET__RESET__SHIFT 0x0 |
39537 | #define RLC_RLCS_GRBM_SOFT_RESET__RESERVED__SHIFT 0x1 |
39538 | #define RLC_RLCS_GRBM_SOFT_RESET__RESET_MASK 0x00000001L |
39539 | #define RLC_RLCS_GRBM_SOFT_RESET__RESERVED_MASK 0xFFFFFFFEL |
39540 | //RLC_RLCS_PG_CHANGE_STATUS |
39541 | #define RLC_RLCS_PG_CHANGE_STATUS__PG_CNTL_CHANGED__SHIFT 0x0 |
39542 | #define RLC_RLCS_PG_CHANGE_STATUS__PG_REG_CHANGED__SHIFT 0x1 |
39543 | #define RLC_RLCS_PG_CHANGE_STATUS__DYN_PG_STATUS_CHANGED__SHIFT 0x2 |
39544 | #define RLC_RLCS_PG_CHANGE_STATUS__DYN_PG_REQ_CHANGED__SHIFT 0x3 |
39545 | #define RLC_RLCS_PG_CHANGE_STATUS__RESERVED__SHIFT 0x4 |
39546 | #define RLC_RLCS_PG_CHANGE_STATUS__PG_CNTL_CHANGED_MASK 0x00000001L |
39547 | #define RLC_RLCS_PG_CHANGE_STATUS__PG_REG_CHANGED_MASK 0x00000002L |
39548 | #define RLC_RLCS_PG_CHANGE_STATUS__DYN_PG_STATUS_CHANGED_MASK 0x00000004L |
39549 | #define RLC_RLCS_PG_CHANGE_STATUS__DYN_PG_REQ_CHANGED_MASK 0x00000008L |
39550 | #define RLC_RLCS_PG_CHANGE_STATUS__RESERVED_MASK 0xFFFFFFF0L |
39551 | //RLC_RLCS_PG_CHANGE_READ |
39552 | #define RLC_RLCS_PG_CHANGE_READ__RESERVED__SHIFT 0x0 |
39553 | #define RLC_RLCS_PG_CHANGE_READ__PG_REG_CHANGED__SHIFT 0x1 |
39554 | #define RLC_RLCS_PG_CHANGE_READ__DYN_PG_STATUS_CHANGED__SHIFT 0x2 |
39555 | #define RLC_RLCS_PG_CHANGE_READ__DYN_PG_REQ_CHANGED__SHIFT 0x3 |
39556 | #define RLC_RLCS_PG_CHANGE_READ__RESERVED_MASK 0x00000001L |
39557 | #define RLC_RLCS_PG_CHANGE_READ__PG_REG_CHANGED_MASK 0x00000002L |
39558 | #define RLC_RLCS_PG_CHANGE_READ__DYN_PG_STATUS_CHANGED_MASK 0x00000004L |
39559 | #define RLC_RLCS_PG_CHANGE_READ__DYN_PG_REQ_CHANGED_MASK 0x00000008L |
39560 | //RLC_RLCS_IH_SEMAPHORE |
39561 | #define RLC_RLCS_IH_SEMAPHORE__CLIENT_ID__SHIFT 0x0 |
39562 | #define RLC_RLCS_IH_SEMAPHORE__RESERVED__SHIFT 0x5 |
39563 | #define RLC_RLCS_IH_SEMAPHORE__CLIENT_ID_MASK 0x0000001FL |
39564 | #define RLC_RLCS_IH_SEMAPHORE__RESERVED_MASK 0xFFFFFFE0L |
39565 | //RLC_RLCS_IH_COOKIE_SEMAPHORE |
39566 | #define RLC_RLCS_IH_COOKIE_SEMAPHORE__CLIENT_ID__SHIFT 0x0 |
39567 | #define RLC_RLCS_IH_COOKIE_SEMAPHORE__RESERVED__SHIFT 0x5 |
39568 | #define RLC_RLCS_IH_COOKIE_SEMAPHORE__CLIENT_ID_MASK 0x0000001FL |
39569 | #define RLC_RLCS_IH_COOKIE_SEMAPHORE__RESERVED_MASK 0xFFFFFFE0L |
39570 | //RLC_RLCS_WGP_STATUS |
39571 | #define RLC_RLCS_WGP_STATUS__CS_WORK_ACTIVE__SHIFT 0x0 |
39572 | #define RLC_RLCS_WGP_STATUS__STATIC_WGP_STATUS_CHANGED__SHIFT 0x1 |
39573 | #define RLC_RLCS_WGP_STATUS__DYMANIC_WGP_STATUS_CHANGED__SHIFT 0x2 |
39574 | #define RLC_RLCS_WGP_STATUS__STATIC_PERWGP_PD_INCOMPLETE__SHIFT 0x3 |
39575 | #define RLC_RLCS_WGP_STATUS__RESERVED__SHIFT 0x4 |
39576 | #define RLC_RLCS_WGP_STATUS__CS_WORK_ACTIVE_MASK 0x00000001L |
39577 | #define RLC_RLCS_WGP_STATUS__STATIC_WGP_STATUS_CHANGED_MASK 0x00000002L |
39578 | #define RLC_RLCS_WGP_STATUS__DYMANIC_WGP_STATUS_CHANGED_MASK 0x00000004L |
39579 | #define RLC_RLCS_WGP_STATUS__STATIC_PERWGP_PD_INCOMPLETE_MASK 0x00000008L |
39580 | #define RLC_RLCS_WGP_STATUS__RESERVED_MASK 0xFFFFFFF0L |
39581 | //RLC_RLCS_WGP_READ |
39582 | #define RLC_RLCS_WGP_READ__CS_WORK_ACTIVE__SHIFT 0x0 |
39583 | #define RLC_RLCS_WGP_READ__STATIC_WGP_STATUS_CHANGED__SHIFT 0x1 |
39584 | #define RLC_RLCS_WGP_READ__DYMANIC_WGP_STATUS_CHANGED__SHIFT 0x2 |
39585 | #define RLC_RLCS_WGP_READ__RESERVED__SHIFT 0x3 |
39586 | #define RLC_RLCS_WGP_READ__CS_WORK_ACTIVE_MASK 0x00000001L |
39587 | #define RLC_RLCS_WGP_READ__STATIC_WGP_STATUS_CHANGED_MASK 0x00000002L |
39588 | #define RLC_RLCS_WGP_READ__DYMANIC_WGP_STATUS_CHANGED_MASK 0x00000004L |
39589 | #define RLC_RLCS_WGP_READ__RESERVED_MASK 0xFFFFFFF8L |
39590 | //RLC_RLCS_CP_INT_CTRL_1 |
39591 | #define RLC_RLCS_CP_INT_CTRL_1__INTERRUPT_ACK__SHIFT 0x0 |
39592 | #define RLC_RLCS_CP_INT_CTRL_1__RESERVED__SHIFT 0x1 |
39593 | #define RLC_RLCS_CP_INT_CTRL_1__INTERRUPT_ACK_MASK 0x00000001L |
39594 | #define RLC_RLCS_CP_INT_CTRL_1__RESERVED_MASK 0xFFFFFFFEL |
39595 | //RLC_RLCS_CP_INT_CTRL_2 |
39596 | #define RLC_RLCS_CP_INT_CTRL_2__IDLE_AUTO_ACK_EN__SHIFT 0x0 |
39597 | #define RLC_RLCS_CP_INT_CTRL_2__BUSY_AUTO_ACK_EN__SHIFT 0x1 |
39598 | #define RLC_RLCS_CP_INT_CTRL_2__IDLE_AUTO_ACK_ACTIVE__SHIFT 0x2 |
39599 | #define RLC_RLCS_CP_INT_CTRL_2__BUSY_AUTO_ACK_ACTIVE__SHIFT 0x3 |
39600 | #define RLC_RLCS_CP_INT_CTRL_2__INTERRUPT_PENDING__SHIFT 0x4 |
39601 | #define RLC_RLCS_CP_INT_CTRL_2__RESERVED__SHIFT 0x5 |
39602 | #define RLC_RLCS_CP_INT_CTRL_2__IDLE_AUTO_ACK_EN_MASK 0x00000001L |
39603 | #define RLC_RLCS_CP_INT_CTRL_2__BUSY_AUTO_ACK_EN_MASK 0x00000002L |
39604 | #define RLC_RLCS_CP_INT_CTRL_2__IDLE_AUTO_ACK_ACTIVE_MASK 0x00000004L |
39605 | #define RLC_RLCS_CP_INT_CTRL_2__BUSY_AUTO_ACK_ACTIVE_MASK 0x00000008L |
39606 | #define RLC_RLCS_CP_INT_CTRL_2__INTERRUPT_PENDING_MASK 0x00000010L |
39607 | #define RLC_RLCS_CP_INT_CTRL_2__RESERVED_MASK 0xFFFFFFE0L |
39608 | //RLC_RLCS_CP_INT_INFO_1 |
39609 | #define RLC_RLCS_CP_INT_INFO_1__INTERRUPT_INFO_1__SHIFT 0x0 |
39610 | #define RLC_RLCS_CP_INT_INFO_1__INTERRUPT_INFO_1_MASK 0xFFFFFFFFL |
39611 | //RLC_RLCS_CP_INT_INFO_2 |
39612 | #define RLC_RLCS_CP_INT_INFO_2__INTERRUPT_INFO_2__SHIFT 0x0 |
39613 | #define RLC_RLCS_CP_INT_INFO_2__INTERRUPT_ID__SHIFT 0x10 |
39614 | #define RLC_RLCS_CP_INT_INFO_2__RESERVED__SHIFT 0x19 |
39615 | #define RLC_RLCS_CP_INT_INFO_2__INTERRUPT_INFO_2_MASK 0x0000FFFFL |
39616 | #define RLC_RLCS_CP_INT_INFO_2__INTERRUPT_ID_MASK 0x01FF0000L |
39617 | #define RLC_RLCS_CP_INT_INFO_2__RESERVED_MASK 0xFE000000L |
39618 | //RLC_RLCS_SPM_INT_CTRL |
39619 | #define RLC_RLCS_SPM_INT_CTRL__INTERRUPT_ACK__SHIFT 0x0 |
39620 | #define RLC_RLCS_SPM_INT_CTRL__RESERVED__SHIFT 0x1 |
39621 | #define RLC_RLCS_SPM_INT_CTRL__INTERRUPT_ACK_MASK 0x00000001L |
39622 | #define RLC_RLCS_SPM_INT_CTRL__RESERVED_MASK 0xFFFFFFFEL |
39623 | //RLC_RLCS_SPM_INT_INFO_1 |
39624 | #define RLC_RLCS_SPM_INT_INFO_1__INTERRUPT_INFO_1__SHIFT 0x0 |
39625 | #define RLC_RLCS_SPM_INT_INFO_1__INTERRUPT_INFO_1_MASK 0xFFFFFFFFL |
39626 | //RLC_RLCS_SPM_INT_INFO_2 |
39627 | #define RLC_RLCS_SPM_INT_INFO_2__INTERRUPT_INFO_2__SHIFT 0x0 |
39628 | #define RLC_RLCS_SPM_INT_INFO_2__INTERRUPT_ID__SHIFT 0x10 |
39629 | #define RLC_RLCS_SPM_INT_INFO_2__RESERVED__SHIFT 0x19 |
39630 | #define RLC_RLCS_SPM_INT_INFO_2__INTERRUPT_INFO_2_MASK 0x0000FFFFL |
39631 | #define RLC_RLCS_SPM_INT_INFO_2__INTERRUPT_ID_MASK 0x01FF0000L |
39632 | #define RLC_RLCS_SPM_INT_INFO_2__RESERVED_MASK 0xFE000000L |
39633 | //RLC_RLCS_DSM_TRIG |
39634 | #define RLC_RLCS_DSM_TRIG__START__SHIFT 0x0 |
39635 | #define RLC_RLCS_DSM_TRIG__RESERVED__SHIFT 0x1 |
39636 | #define RLC_RLCS_DSM_TRIG__START_MASK 0x00000001L |
39637 | #define RLC_RLCS_DSM_TRIG__RESERVED_MASK 0xFFFFFFFEL |
39638 | //RLC_RLCS_BOOTLOAD_STATUS |
39639 | #define RLC_RLCS_BOOTLOAD_STATUS__GFX_INIT_DONE__SHIFT 0x0 |
39640 | #define RLC_RLCS_BOOTLOAD_STATUS__GFX_SECURITY_POLICY_LOADED__SHIFT 0x1 |
39641 | #define RLC_RLCS_BOOTLOAD_STATUS__GFX_SECURITY_POLICY_DONE__SHIFT 0x2 |
39642 | #define RLC_RLCS_BOOTLOAD_STATUS__RLC_GPM_IRAM_LOADED__SHIFT 0x3 |
39643 | #define RLC_RLCS_BOOTLOAD_STATUS__RLC_GPM_IRAM_DONE__SHIFT 0x4 |
39644 | #define RLC_RLCS_BOOTLOAD_STATUS__RESERVED__SHIFT 0x5 |
39645 | #define RLC_RLCS_BOOTLOAD_STATUS__BOOTLOAD_COMPLETE__SHIFT 0x1f |
39646 | #define RLC_RLCS_BOOTLOAD_STATUS__GFX_INIT_DONE_MASK 0x00000001L |
39647 | #define RLC_RLCS_BOOTLOAD_STATUS__GFX_SECURITY_POLICY_LOADED_MASK 0x00000002L |
39648 | #define RLC_RLCS_BOOTLOAD_STATUS__GFX_SECURITY_POLICY_DONE_MASK 0x00000004L |
39649 | #define RLC_RLCS_BOOTLOAD_STATUS__RLC_GPM_IRAM_LOADED_MASK 0x00000008L |
39650 | #define RLC_RLCS_BOOTLOAD_STATUS__RLC_GPM_IRAM_DONE_MASK 0x00000010L |
39651 | #define RLC_RLCS_BOOTLOAD_STATUS__RESERVED_MASK 0x7FFFFFE0L |
39652 | #define RLC_RLCS_BOOTLOAD_STATUS__BOOTLOAD_COMPLETE_MASK 0x80000000L |
39653 | //RLC_RLCS_POWER_BRAKE_CNTL |
39654 | #define RLC_RLCS_POWER_BRAKE_CNTL__POWER_BRAKE__SHIFT 0x0 |
39655 | #define RLC_RLCS_POWER_BRAKE_CNTL__INT_CLEAR__SHIFT 0x1 |
39656 | #define RLC_RLCS_POWER_BRAKE_CNTL__MAX_HYSTERESIS__SHIFT 0x2 |
39657 | #define RLC_RLCS_POWER_BRAKE_CNTL__HYSTERESIS_CNT__SHIFT 0xa |
39658 | #define RLC_RLCS_POWER_BRAKE_CNTL__RESERVED__SHIFT 0x12 |
39659 | #define RLC_RLCS_POWER_BRAKE_CNTL__POWER_BRAKE_MASK 0x00000001L |
39660 | #define RLC_RLCS_POWER_BRAKE_CNTL__INT_CLEAR_MASK 0x00000002L |
39661 | #define RLC_RLCS_POWER_BRAKE_CNTL__MAX_HYSTERESIS_MASK 0x000003FCL |
39662 | #define RLC_RLCS_POWER_BRAKE_CNTL__HYSTERESIS_CNT_MASK 0x0003FC00L |
39663 | #define RLC_RLCS_POWER_BRAKE_CNTL__RESERVED_MASK 0xFFFC0000L |
39664 | //RLC_RLCS_POWER_BRAKE_CNTL_TH1 |
39665 | #define RLC_RLCS_POWER_BRAKE_CNTL_TH1__POWER_BRAKE__SHIFT 0x0 |
39666 | #define RLC_RLCS_POWER_BRAKE_CNTL_TH1__INT_CLEAR__SHIFT 0x1 |
39667 | #define RLC_RLCS_POWER_BRAKE_CNTL_TH1__MAX_HYSTERESIS__SHIFT 0x2 |
39668 | #define RLC_RLCS_POWER_BRAKE_CNTL_TH1__HYSTERESIS_CNT__SHIFT 0xa |
39669 | #define RLC_RLCS_POWER_BRAKE_CNTL_TH1__RESERVED__SHIFT 0x12 |
39670 | #define RLC_RLCS_POWER_BRAKE_CNTL_TH1__POWER_BRAKE_MASK 0x00000001L |
39671 | #define RLC_RLCS_POWER_BRAKE_CNTL_TH1__INT_CLEAR_MASK 0x00000002L |
39672 | #define RLC_RLCS_POWER_BRAKE_CNTL_TH1__MAX_HYSTERESIS_MASK 0x000003FCL |
39673 | #define RLC_RLCS_POWER_BRAKE_CNTL_TH1__HYSTERESIS_CNT_MASK 0x0003FC00L |
39674 | #define RLC_RLCS_POWER_BRAKE_CNTL_TH1__RESERVED_MASK 0xFFFC0000L |
39675 | //RLC_RLCS_GRBM_IDLE_BUSY_STAT |
39676 | #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__GRBM_RLC_GC_STAT_IDLE__SHIFT 0x0 |
39677 | #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_0_BUSY__SHIFT 0x10 |
39678 | #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_1_BUSY__SHIFT 0x11 |
39679 | #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_2_BUSY__SHIFT 0x12 |
39680 | #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_3_BUSY__SHIFT 0x13 |
39681 | #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_4_BUSY__SHIFT 0x14 |
39682 | #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_5_BUSY__SHIFT 0x15 |
39683 | #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_6_BUSY__SHIFT 0x16 |
39684 | #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_7_BUSY__SHIFT 0x17 |
39685 | #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_0_BUSY_CHANGED__SHIFT 0x18 |
39686 | #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_1_BUSY_CHANGED__SHIFT 0x19 |
39687 | #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_2_BUSY_CHANGED__SHIFT 0x1a |
39688 | #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_3_BUSY_CHANGED__SHIFT 0x1b |
39689 | #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_4_BUSY_CHANGED__SHIFT 0x1c |
39690 | #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_5_BUSY_CHANGED__SHIFT 0x1d |
39691 | #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_6_BUSY_CHANGED__SHIFT 0x1e |
39692 | #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_7_BUSY_CHANGED__SHIFT 0x1f |
39693 | #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__GRBM_RLC_GC_STAT_IDLE_MASK 0x00000003L |
39694 | #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_0_BUSY_MASK 0x00010000L |
39695 | #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_1_BUSY_MASK 0x00020000L |
39696 | #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_2_BUSY_MASK 0x00040000L |
39697 | #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_3_BUSY_MASK 0x00080000L |
39698 | #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_4_BUSY_MASK 0x00100000L |
39699 | #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_5_BUSY_MASK 0x00200000L |
39700 | #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_6_BUSY_MASK 0x00400000L |
39701 | #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_7_BUSY_MASK 0x00800000L |
39702 | #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_0_BUSY_CHANGED_MASK 0x01000000L |
39703 | #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_1_BUSY_CHANGED_MASK 0x02000000L |
39704 | #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_2_BUSY_CHANGED_MASK 0x04000000L |
39705 | #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_3_BUSY_CHANGED_MASK 0x08000000L |
39706 | #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_4_BUSY_CHANGED_MASK 0x10000000L |
39707 | #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_5_BUSY_CHANGED_MASK 0x20000000L |
39708 | #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_6_BUSY_CHANGED_MASK 0x40000000L |
39709 | #define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_7_BUSY_CHANGED_MASK 0x80000000L |
39710 | //RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL |
39711 | #define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA0_BUSY_INT_CLEAR__SHIFT 0x0 |
39712 | #define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA1_BUSY_INT_CLEAR__SHIFT 0x1 |
39713 | #define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA2_BUSY_INT_CLEAR__SHIFT 0x2 |
39714 | #define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA3_BUSY_INT_CLEAR__SHIFT 0x3 |
39715 | #define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA4_BUSY_INT_CLEAR__SHIFT 0x4 |
39716 | #define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA5_BUSY_INT_CLEAR__SHIFT 0x5 |
39717 | #define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA6_BUSY_INT_CLEAR__SHIFT 0x6 |
39718 | #define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA7_BUSY_INT_CLEAR__SHIFT 0x7 |
39719 | #define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA0_BUSY_INT_CLEAR_MASK 0x00000001L |
39720 | #define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA1_BUSY_INT_CLEAR_MASK 0x00000002L |
39721 | #define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA2_BUSY_INT_CLEAR_MASK 0x00000004L |
39722 | #define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA3_BUSY_INT_CLEAR_MASK 0x00000008L |
39723 | #define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA4_BUSY_INT_CLEAR_MASK 0x00000010L |
39724 | #define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA5_BUSY_INT_CLEAR_MASK 0x00000020L |
39725 | #define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA6_BUSY_INT_CLEAR_MASK 0x00000040L |
39726 | #define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA7_BUSY_INT_CLEAR_MASK 0x00000080L |
39727 | //RLC_RLCS_CMP_IDLE_CNTL |
39728 | #define RLC_RLCS_CMP_IDLE_CNTL__INT_CLEAR__SHIFT 0x0 |
39729 | #define RLC_RLCS_CMP_IDLE_CNTL__CMP_IDLE_HYST__SHIFT 0x1 |
39730 | #define RLC_RLCS_CMP_IDLE_CNTL__CMP_IDLE__SHIFT 0x2 |
39731 | #define RLC_RLCS_CMP_IDLE_CNTL__MAX_HYSTERESIS__SHIFT 0x3 |
39732 | #define RLC_RLCS_CMP_IDLE_CNTL__HYSTERESIS_CNT__SHIFT 0xb |
39733 | #define RLC_RLCS_CMP_IDLE_CNTL__RESERVED__SHIFT 0x13 |
39734 | #define RLC_RLCS_CMP_IDLE_CNTL__INT_CLEAR_MASK 0x00000001L |
39735 | #define RLC_RLCS_CMP_IDLE_CNTL__CMP_IDLE_HYST_MASK 0x00000002L |
39736 | #define RLC_RLCS_CMP_IDLE_CNTL__CMP_IDLE_MASK 0x00000004L |
39737 | #define RLC_RLCS_CMP_IDLE_CNTL__MAX_HYSTERESIS_MASK 0x000007F8L |
39738 | #define RLC_RLCS_CMP_IDLE_CNTL__HYSTERESIS_CNT_MASK 0x0007F800L |
39739 | #define RLC_RLCS_CMP_IDLE_CNTL__RESERVED_MASK 0xFFF80000L |
39740 | //RLC_RLCS_GENERAL_0 |
39741 | #define RLC_RLCS_GENERAL_0__DATA__SHIFT 0x0 |
39742 | #define RLC_RLCS_GENERAL_0__DATA_MASK 0xFFFFFFFFL |
39743 | //RLC_RLCS_GENERAL_1 |
39744 | #define RLC_RLCS_GENERAL_1__DATA__SHIFT 0x0 |
39745 | #define RLC_RLCS_GENERAL_1__DATA_MASK 0xFFFFFFFFL |
39746 | //RLC_RLCS_GENERAL_2 |
39747 | #define RLC_RLCS_GENERAL_2__DATA__SHIFT 0x0 |
39748 | #define RLC_RLCS_GENERAL_2__DATA_MASK 0xFFFFFFFFL |
39749 | //RLC_RLCS_GENERAL_3 |
39750 | #define RLC_RLCS_GENERAL_3__DATA__SHIFT 0x0 |
39751 | #define RLC_RLCS_GENERAL_3__DATA_MASK 0xFFFFFFFFL |
39752 | //RLC_RLCS_GENERAL_4 |
39753 | #define RLC_RLCS_GENERAL_4__DATA__SHIFT 0x0 |
39754 | #define RLC_RLCS_GENERAL_4__DATA_MASK 0xFFFFFFFFL |
39755 | //RLC_RLCS_GENERAL_5 |
39756 | #define RLC_RLCS_GENERAL_5__DATA__SHIFT 0x0 |
39757 | #define RLC_RLCS_GENERAL_5__DATA_MASK 0xFFFFFFFFL |
39758 | //RLC_RLCS_GENERAL_6 |
39759 | #define RLC_RLCS_GENERAL_6__DATA__SHIFT 0x0 |
39760 | #define RLC_RLCS_GENERAL_6__DATA_MASK 0xFFFFFFFFL |
39761 | //RLC_RLCS_GENERAL_7 |
39762 | #define RLC_RLCS_GENERAL_7__DATA__SHIFT 0x0 |
39763 | #define RLC_RLCS_GENERAL_7__DATA_MASK 0xFFFFFFFFL |
39764 | //RLC_RLCS_GENERAL_8 |
39765 | #define RLC_RLCS_GENERAL_8__DATA__SHIFT 0x0 |
39766 | #define RLC_RLCS_GENERAL_8__DATA_MASK 0xFFFFFFFFL |
39767 | //RLC_RLCS_GENERAL_9 |
39768 | #define RLC_RLCS_GENERAL_9__DATA__SHIFT 0x0 |
39769 | #define RLC_RLCS_GENERAL_9__DATA_MASK 0xFFFFFFFFL |
39770 | //RLC_RLCS_GENERAL_10 |
39771 | #define RLC_RLCS_GENERAL_10__DATA__SHIFT 0x0 |
39772 | #define RLC_RLCS_GENERAL_10__DATA_MASK 0xFFFFFFFFL |
39773 | //RLC_RLCS_GENERAL_11 |
39774 | #define RLC_RLCS_GENERAL_11__DATA__SHIFT 0x0 |
39775 | #define RLC_RLCS_GENERAL_11__DATA_MASK 0xFFFFFFFFL |
39776 | //RLC_RLCS_GENERAL_12 |
39777 | #define RLC_RLCS_GENERAL_12__DATA__SHIFT 0x0 |
39778 | #define RLC_RLCS_GENERAL_12__DATA_MASK 0xFFFFFFFFL |
39779 | //RLC_RLCS_GENERAL_13 |
39780 | #define RLC_RLCS_GENERAL_13__DATA__SHIFT 0x0 |
39781 | #define RLC_RLCS_GENERAL_13__DATA_MASK 0xFFFFFFFFL |
39782 | //RLC_RLCS_GENERAL_14 |
39783 | #define RLC_RLCS_GENERAL_14__DATA__SHIFT 0x0 |
39784 | #define RLC_RLCS_GENERAL_14__DATA_MASK 0xFFFFFFFFL |
39785 | //RLC_RLCS_GENERAL_15 |
39786 | #define RLC_RLCS_GENERAL_15__DATA__SHIFT 0x0 |
39787 | #define RLC_RLCS_GENERAL_15__DATA_MASK 0xFFFFFFFFL |
39788 | //RLC_RLCS_GENERAL_16 |
39789 | #define RLC_RLCS_GENERAL_16__DATA__SHIFT 0x0 |
39790 | #define RLC_RLCS_GENERAL_16__DATA_MASK 0xFFFFFFFFL |
39791 | //RLC_RLCS_AUXILIARY_REG_1 |
39792 | #define RLC_RLCS_AUXILIARY_REG_1__ADDR__SHIFT 0x0 |
39793 | #define RLC_RLCS_AUXILIARY_REG_1__RESERVED__SHIFT 0x12 |
39794 | #define RLC_RLCS_AUXILIARY_REG_1__ADDR_MASK 0x0003FFFFL |
39795 | #define RLC_RLCS_AUXILIARY_REG_1__RESERVED_MASK 0xFFFC0000L |
39796 | //RLC_RLCS_AUXILIARY_REG_2 |
39797 | #define RLC_RLCS_AUXILIARY_REG_2__ADDR__SHIFT 0x0 |
39798 | #define RLC_RLCS_AUXILIARY_REG_2__RESERVED__SHIFT 0x12 |
39799 | #define RLC_RLCS_AUXILIARY_REG_2__ADDR_MASK 0x0003FFFFL |
39800 | #define RLC_RLCS_AUXILIARY_REG_2__RESERVED_MASK 0xFFFC0000L |
39801 | //RLC_RLCS_AUXILIARY_REG_3 |
39802 | #define RLC_RLCS_AUXILIARY_REG_3__ADDR__SHIFT 0x0 |
39803 | #define RLC_RLCS_AUXILIARY_REG_3__RESERVED__SHIFT 0x12 |
39804 | #define RLC_RLCS_AUXILIARY_REG_3__ADDR_MASK 0x0003FFFFL |
39805 | #define RLC_RLCS_AUXILIARY_REG_3__RESERVED_MASK 0xFFFC0000L |
39806 | //RLC_RLCS_AUXILIARY_REG_4 |
39807 | #define RLC_RLCS_AUXILIARY_REG_4__ADDR__SHIFT 0x0 |
39808 | #define RLC_RLCS_AUXILIARY_REG_4__RESERVED__SHIFT 0x12 |
39809 | #define RLC_RLCS_AUXILIARY_REG_4__ADDR_MASK 0x0003FFFFL |
39810 | #define RLC_RLCS_AUXILIARY_REG_4__RESERVED_MASK 0xFFFC0000L |
39811 | //RLC_RLCS_SPM_SQTT_MODE |
39812 | #define RLC_RLCS_SPM_SQTT_MODE__MODE__SHIFT 0x0 |
39813 | #define RLC_RLCS_SPM_SQTT_MODE__MODE_MASK 0x00000001L |
39814 | //RLC_RLCS_CP_DMA_SRCID_OVER |
39815 | #define RLC_RLCS_CP_DMA_SRCID_OVER__SRCID_OVERRIDE__SHIFT 0x0 |
39816 | #define RLC_RLCS_CP_DMA_SRCID_OVER__SRCID_OVERRIDE_MASK 0x00000001L |
39817 | //RLC_RLCS_BOOTLOAD_ID_STATUS1 |
39818 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_0_LOADED__SHIFT 0x0 |
39819 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_1_LOADED__SHIFT 0x1 |
39820 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_2_LOADED__SHIFT 0x2 |
39821 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_3_LOADED__SHIFT 0x3 |
39822 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_4_LOADED__SHIFT 0x4 |
39823 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_5_LOADED__SHIFT 0x5 |
39824 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_6_LOADED__SHIFT 0x6 |
39825 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_7_LOADED__SHIFT 0x7 |
39826 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_8_LOADED__SHIFT 0x8 |
39827 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_9_LOADED__SHIFT 0x9 |
39828 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_10_LOADED__SHIFT 0xa |
39829 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_11_LOADED__SHIFT 0xb |
39830 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_12_LOADED__SHIFT 0xc |
39831 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_13_LOADED__SHIFT 0xd |
39832 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_14_LOADED__SHIFT 0xe |
39833 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_15_LOADED__SHIFT 0xf |
39834 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_16_LOADED__SHIFT 0x10 |
39835 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_17_LOADED__SHIFT 0x11 |
39836 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_18_LOADED__SHIFT 0x12 |
39837 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_19_LOADED__SHIFT 0x13 |
39838 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_20_LOADED__SHIFT 0x14 |
39839 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_21_LOADED__SHIFT 0x15 |
39840 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_22_LOADED__SHIFT 0x16 |
39841 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_23_LOADED__SHIFT 0x17 |
39842 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_24_LOADED__SHIFT 0x18 |
39843 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_25_LOADED__SHIFT 0x19 |
39844 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_26_LOADED__SHIFT 0x1a |
39845 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_27_LOADED__SHIFT 0x1b |
39846 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_28_LOADED__SHIFT 0x1c |
39847 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_29_LOADED__SHIFT 0x1d |
39848 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_30_LOADED__SHIFT 0x1e |
39849 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_31_LOADED__SHIFT 0x1f |
39850 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_0_LOADED_MASK 0x00000001L |
39851 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_1_LOADED_MASK 0x00000002L |
39852 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_2_LOADED_MASK 0x00000004L |
39853 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_3_LOADED_MASK 0x00000008L |
39854 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_4_LOADED_MASK 0x00000010L |
39855 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_5_LOADED_MASK 0x00000020L |
39856 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_6_LOADED_MASK 0x00000040L |
39857 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_7_LOADED_MASK 0x00000080L |
39858 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_8_LOADED_MASK 0x00000100L |
39859 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_9_LOADED_MASK 0x00000200L |
39860 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_10_LOADED_MASK 0x00000400L |
39861 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_11_LOADED_MASK 0x00000800L |
39862 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_12_LOADED_MASK 0x00001000L |
39863 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_13_LOADED_MASK 0x00002000L |
39864 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_14_LOADED_MASK 0x00004000L |
39865 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_15_LOADED_MASK 0x00008000L |
39866 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_16_LOADED_MASK 0x00010000L |
39867 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_17_LOADED_MASK 0x00020000L |
39868 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_18_LOADED_MASK 0x00040000L |
39869 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_19_LOADED_MASK 0x00080000L |
39870 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_20_LOADED_MASK 0x00100000L |
39871 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_21_LOADED_MASK 0x00200000L |
39872 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_22_LOADED_MASK 0x00400000L |
39873 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_23_LOADED_MASK 0x00800000L |
39874 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_24_LOADED_MASK 0x01000000L |
39875 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_25_LOADED_MASK 0x02000000L |
39876 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_26_LOADED_MASK 0x04000000L |
39877 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_27_LOADED_MASK 0x08000000L |
39878 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_28_LOADED_MASK 0x10000000L |
39879 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_29_LOADED_MASK 0x20000000L |
39880 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_30_LOADED_MASK 0x40000000L |
39881 | #define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_31_LOADED_MASK 0x80000000L |
39882 | //RLC_RLCS_BOOTLOAD_ID_STATUS2 |
39883 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_32_LOADED__SHIFT 0x0 |
39884 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_33_LOADED__SHIFT 0x1 |
39885 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_34_LOADED__SHIFT 0x2 |
39886 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_35_LOADED__SHIFT 0x3 |
39887 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_36_LOADED__SHIFT 0x4 |
39888 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_37_LOADED__SHIFT 0x5 |
39889 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_38_LOADED__SHIFT 0x6 |
39890 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_39_LOADED__SHIFT 0x7 |
39891 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_40_LOADED__SHIFT 0x8 |
39892 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_41_LOADED__SHIFT 0x9 |
39893 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_42_LOADED__SHIFT 0xa |
39894 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_43_LOADED__SHIFT 0xb |
39895 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_44_LOADED__SHIFT 0xc |
39896 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_45_LOADED__SHIFT 0xd |
39897 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_46_LOADED__SHIFT 0xe |
39898 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_47_LOADED__SHIFT 0xf |
39899 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_48_LOADED__SHIFT 0x10 |
39900 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_49_LOADED__SHIFT 0x11 |
39901 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_50_LOADED__SHIFT 0x12 |
39902 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_51_LOADED__SHIFT 0x13 |
39903 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_52_LOADED__SHIFT 0x14 |
39904 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_53_LOADED__SHIFT 0x15 |
39905 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_54_LOADED__SHIFT 0x16 |
39906 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_55_LOADED__SHIFT 0x17 |
39907 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_56_LOADED__SHIFT 0x18 |
39908 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_57_LOADED__SHIFT 0x19 |
39909 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_58_LOADED__SHIFT 0x1a |
39910 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_59_LOADED__SHIFT 0x1b |
39911 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_60_LOADED__SHIFT 0x1c |
39912 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_61_LOADED__SHIFT 0x1d |
39913 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_62_LOADED__SHIFT 0x1e |
39914 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_63_LOADED__SHIFT 0x1f |
39915 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_32_LOADED_MASK 0x00000001L |
39916 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_33_LOADED_MASK 0x00000002L |
39917 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_34_LOADED_MASK 0x00000004L |
39918 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_35_LOADED_MASK 0x00000008L |
39919 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_36_LOADED_MASK 0x00000010L |
39920 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_37_LOADED_MASK 0x00000020L |
39921 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_38_LOADED_MASK 0x00000040L |
39922 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_39_LOADED_MASK 0x00000080L |
39923 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_40_LOADED_MASK 0x00000100L |
39924 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_41_LOADED_MASK 0x00000200L |
39925 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_42_LOADED_MASK 0x00000400L |
39926 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_43_LOADED_MASK 0x00000800L |
39927 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_44_LOADED_MASK 0x00001000L |
39928 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_45_LOADED_MASK 0x00002000L |
39929 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_46_LOADED_MASK 0x00004000L |
39930 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_47_LOADED_MASK 0x00008000L |
39931 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_48_LOADED_MASK 0x00010000L |
39932 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_49_LOADED_MASK 0x00020000L |
39933 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_50_LOADED_MASK 0x00040000L |
39934 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_51_LOADED_MASK 0x00080000L |
39935 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_52_LOADED_MASK 0x00100000L |
39936 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_53_LOADED_MASK 0x00200000L |
39937 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_54_LOADED_MASK 0x00400000L |
39938 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_55_LOADED_MASK 0x00800000L |
39939 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_56_LOADED_MASK 0x01000000L |
39940 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_57_LOADED_MASK 0x02000000L |
39941 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_58_LOADED_MASK 0x04000000L |
39942 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_59_LOADED_MASK 0x08000000L |
39943 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_60_LOADED_MASK 0x10000000L |
39944 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_61_LOADED_MASK 0x20000000L |
39945 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_62_LOADED_MASK 0x40000000L |
39946 | #define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_63_LOADED_MASK 0x80000000L |
39947 | //RLC_RLCS_IMU_VIDCHG_CNTL |
39948 | #define RLC_RLCS_IMU_VIDCHG_CNTL__REQ__SHIFT 0x0 |
39949 | #define RLC_RLCS_IMU_VIDCHG_CNTL__DATA__SHIFT 0x1 |
39950 | #define RLC_RLCS_IMU_VIDCHG_CNTL__PSIEN__SHIFT 0xa |
39951 | #define RLC_RLCS_IMU_VIDCHG_CNTL__ACK__SHIFT 0xb |
39952 | #define RLC_RLCS_IMU_VIDCHG_CNTL__RESERVED__SHIFT 0xc |
39953 | #define RLC_RLCS_IMU_VIDCHG_CNTL__REQ_MASK 0x00000001L |
39954 | #define RLC_RLCS_IMU_VIDCHG_CNTL__DATA_MASK 0x000003FEL |
39955 | #define RLC_RLCS_IMU_VIDCHG_CNTL__PSIEN_MASK 0x00000400L |
39956 | #define RLC_RLCS_IMU_VIDCHG_CNTL__ACK_MASK 0x00000800L |
39957 | #define RLC_RLCS_IMU_VIDCHG_CNTL__RESERVED_MASK 0xFFFFF000L |
39958 | //RLC_RLCS_EDC_INT_CNTL |
39959 | #define RLC_RLCS_EDC_INT_CNTL__EDC_EVENT_INT_CLEAR__SHIFT 0x0 |
39960 | #define RLC_RLCS_EDC_INT_CNTL__EDC_EVENT_INT_CLEAR_MASK 0x00000001L |
39961 | //RLC_RLCS_KMD_LOG_CNTL1 |
39962 | #define RLC_RLCS_KMD_LOG_CNTL1__DATA__SHIFT 0x0 |
39963 | #define RLC_RLCS_KMD_LOG_CNTL1__DATA_MASK 0xFFFFFFFFL |
39964 | //RLC_RLCS_KMD_LOG_CNTL2 |
39965 | #define RLC_RLCS_KMD_LOG_CNTL2__DATA__SHIFT 0x0 |
39966 | #define RLC_RLCS_KMD_LOG_CNTL2__DATA_MASK 0xFFFFFFFFL |
39967 | //RLC_RLCS_GPM_LEGACY_INT_STAT |
39968 | #define RLC_RLCS_GPM_LEGACY_INT_STAT__GC_CAC_EDC_EVENT_CHANGED__SHIFT 0x0 |
39969 | #define RLC_RLCS_GPM_LEGACY_INT_STAT__GFX_POWER_BRAKE_CHANGED__SHIFT 0x1 |
39970 | #define RLC_RLCS_GPM_LEGACY_INT_STAT__GC_CAC_EDC_EVENT_CHANGED_MASK 0x00000001L |
39971 | #define RLC_RLCS_GPM_LEGACY_INT_STAT__GFX_POWER_BRAKE_CHANGED_MASK 0x00000002L |
39972 | //RLC_RLCS_GPM_LEGACY_INT_DISABLE |
39973 | #define RLC_RLCS_GPM_LEGACY_INT_DISABLE__GC_CAC_EDC_EVENT_CHANGED__SHIFT 0x0 |
39974 | #define RLC_RLCS_GPM_LEGACY_INT_DISABLE__GFX_POWER_BRAKE_CHANGED__SHIFT 0x1 |
39975 | #define RLC_RLCS_GPM_LEGACY_INT_DISABLE__GC_CAC_EDC_EVENT_CHANGED_MASK 0x00000001L |
39976 | #define RLC_RLCS_GPM_LEGACY_INT_DISABLE__GFX_POWER_BRAKE_CHANGED_MASK 0x00000002L |
39977 | //RLC_RLCS_SRM_SRCID_CNTL |
39978 | #define RLC_RLCS_SRM_SRCID_CNTL__SRCID__SHIFT 0x0 |
39979 | #define RLC_RLCS_SRM_SRCID_CNTL__SRCID_MASK 0x00000007L |
39980 | //RLC_RLCS_GCR_DATA_0 |
39981 | #define RLC_RLCS_GCR_DATA_0__PHASE_0__SHIFT 0x0 |
39982 | #define RLC_RLCS_GCR_DATA_0__PHASE_1__SHIFT 0x10 |
39983 | #define RLC_RLCS_GCR_DATA_0__PHASE_0_MASK 0x0000FFFFL |
39984 | #define RLC_RLCS_GCR_DATA_0__PHASE_1_MASK 0xFFFF0000L |
39985 | //RLC_RLCS_GCR_DATA_1 |
39986 | #define RLC_RLCS_GCR_DATA_1__PHASE_2__SHIFT 0x0 |
39987 | #define RLC_RLCS_GCR_DATA_1__PHASE_3__SHIFT 0x10 |
39988 | #define RLC_RLCS_GCR_DATA_1__PHASE_2_MASK 0x0000FFFFL |
39989 | #define RLC_RLCS_GCR_DATA_1__PHASE_3_MASK 0xFFFF0000L |
39990 | //RLC_RLCS_GCR_DATA_2 |
39991 | #define RLC_RLCS_GCR_DATA_2__PHASE_4__SHIFT 0x0 |
39992 | #define RLC_RLCS_GCR_DATA_2__PHASE_5__SHIFT 0x10 |
39993 | #define RLC_RLCS_GCR_DATA_2__PHASE_4_MASK 0x0000FFFFL |
39994 | #define RLC_RLCS_GCR_DATA_2__PHASE_5_MASK 0xFFFF0000L |
39995 | //RLC_RLCS_GCR_DATA_3 |
39996 | #define RLC_RLCS_GCR_DATA_3__PHASE_6__SHIFT 0x0 |
39997 | #define RLC_RLCS_GCR_DATA_3__PHASE_7__SHIFT 0x10 |
39998 | #define RLC_RLCS_GCR_DATA_3__PHASE_6_MASK 0x0000FFFFL |
39999 | #define RLC_RLCS_GCR_DATA_3__PHASE_7_MASK 0xFFFF0000L |
40000 | //RLC_RLCS_GCR_STATUS |
40001 | #define RLC_RLCS_GCR_STATUS__GCR_BUSY__SHIFT 0x0 |
40002 | #define RLC_RLCS_GCR_STATUS__GCR_OUT_COUNT__SHIFT 0x1 |
40003 | #define RLC_RLCS_GCR_STATUS__RESERVED_2__SHIFT 0x5 |
40004 | #define RLC_RLCS_GCR_STATUS__GCRIU_CLI_RSP_TAG__SHIFT 0x8 |
40005 | #define RLC_RLCS_GCR_STATUS__RESERVED__SHIFT 0x10 |
40006 | #define RLC_RLCS_GCR_STATUS__GCR_BUSY_MASK 0x00000001L |
40007 | #define RLC_RLCS_GCR_STATUS__GCR_OUT_COUNT_MASK 0x0000001EL |
40008 | #define RLC_RLCS_GCR_STATUS__RESERVED_2_MASK 0x000000E0L |
40009 | #define RLC_RLCS_GCR_STATUS__GCRIU_CLI_RSP_TAG_MASK 0x0000FF00L |
40010 | #define RLC_RLCS_GCR_STATUS__RESERVED_MASK 0xFFFF0000L |
40011 | //RLC_RLCS_PERFMON_CLK_CNTL_UCODE |
40012 | #define RLC_RLCS_PERFMON_CLK_CNTL_UCODE__PERFMON_CLOCK_STATE__SHIFT 0x0 |
40013 | #define RLC_RLCS_PERFMON_CLK_CNTL_UCODE__PERFMON_CLOCK_STATE_MASK 0x00000001L |
40014 | //RLC_RLCS_UTCL2_CNTL |
40015 | #define RLC_RLCS_UTCL2_CNTL__MTYPE_NO_PTE_MODE__SHIFT 0x0 |
40016 | #define RLC_RLCS_UTCL2_CNTL__GPA_OVERRIDE__SHIFT 0x1 |
40017 | #define RLC_RLCS_UTCL2_CNTL__VF_OVERRIDE__SHIFT 0x2 |
40018 | #define RLC_RLCS_UTCL2_CNTL__GPA_OVERRIDE_VALUE__SHIFT 0x3 |
40019 | #define RLC_RLCS_UTCL2_CNTL__VF_OVERRIDE_VALUE__SHIFT 0x5 |
40020 | #define RLC_RLCS_UTCL2_CNTL__IGNORE_PTE_PERMISSION__SHIFT 0x6 |
40021 | #define RLC_RLCS_UTCL2_CNTL__RESERVED__SHIFT 0x7 |
40022 | #define RLC_RLCS_UTCL2_CNTL__MTYPE_NO_PTE_MODE_MASK 0x00000001L |
40023 | #define RLC_RLCS_UTCL2_CNTL__GPA_OVERRIDE_MASK 0x00000002L |
40024 | #define RLC_RLCS_UTCL2_CNTL__VF_OVERRIDE_MASK 0x00000004L |
40025 | #define RLC_RLCS_UTCL2_CNTL__GPA_OVERRIDE_VALUE_MASK 0x00000018L |
40026 | #define RLC_RLCS_UTCL2_CNTL__VF_OVERRIDE_VALUE_MASK 0x00000020L |
40027 | #define RLC_RLCS_UTCL2_CNTL__IGNORE_PTE_PERMISSION_MASK 0x00000040L |
40028 | #define RLC_RLCS_UTCL2_CNTL__RESERVED_MASK 0xFFFFFF80L |
40029 | //RLC_RLCS_IMU_RLC_MSG_DATA0 |
40030 | #define RLC_RLCS_IMU_RLC_MSG_DATA0__DATA__SHIFT 0x0 |
40031 | #define RLC_RLCS_IMU_RLC_MSG_DATA0__DATA_MASK 0xFFFFFFFFL |
40032 | //RLC_RLCS_IMU_RLC_MSG_DATA1 |
40033 | #define RLC_RLCS_IMU_RLC_MSG_DATA1__DATA__SHIFT 0x0 |
40034 | #define RLC_RLCS_IMU_RLC_MSG_DATA1__DATA_MASK 0xFFFFFFFFL |
40035 | //RLC_RLCS_IMU_RLC_MSG_DATA2 |
40036 | #define RLC_RLCS_IMU_RLC_MSG_DATA2__DATA__SHIFT 0x0 |
40037 | #define RLC_RLCS_IMU_RLC_MSG_DATA2__DATA_MASK 0xFFFFFFFFL |
40038 | //RLC_RLCS_IMU_RLC_MSG_DATA3 |
40039 | #define RLC_RLCS_IMU_RLC_MSG_DATA3__DATA__SHIFT 0x0 |
40040 | #define RLC_RLCS_IMU_RLC_MSG_DATA3__DATA_MASK 0xFFFFFFFFL |
40041 | //RLC_RLCS_IMU_RLC_MSG_DATA4 |
40042 | #define RLC_RLCS_IMU_RLC_MSG_DATA4__DATA__SHIFT 0x0 |
40043 | #define RLC_RLCS_IMU_RLC_MSG_DATA4__DATA_MASK 0xFFFFFFFFL |
40044 | //RLC_RLCS_IMU_RLC_MSG_CONTROL |
40045 | #define RLC_RLCS_IMU_RLC_MSG_CONTROL__DATA__SHIFT 0x0 |
40046 | #define RLC_RLCS_IMU_RLC_MSG_CONTROL__DATA_MASK 0xFFFFFFFFL |
40047 | //RLC_RLCS_IMU_RLC_MSG_CNTL |
40048 | #define RLC_RLCS_IMU_RLC_MSG_CNTL__DONETOG__SHIFT 0x0 |
40049 | #define RLC_RLCS_IMU_RLC_MSG_CNTL__CHGTOG__SHIFT 0x1 |
40050 | #define RLC_RLCS_IMU_RLC_MSG_CNTL__RESERVED__SHIFT 0x2 |
40051 | #define RLC_RLCS_IMU_RLC_MSG_CNTL__DONETOG_MASK 0x00000001L |
40052 | #define RLC_RLCS_IMU_RLC_MSG_CNTL__CHGTOG_MASK 0x00000002L |
40053 | #define RLC_RLCS_IMU_RLC_MSG_CNTL__RESERVED_MASK 0xFFFFFFFCL |
40054 | //RLC_RLCS_RLC_IMU_MSG_DATA0 |
40055 | #define RLC_RLCS_RLC_IMU_MSG_DATA0__DATA__SHIFT 0x0 |
40056 | #define RLC_RLCS_RLC_IMU_MSG_DATA0__DATA_MASK 0xFFFFFFFFL |
40057 | //RLC_RLCS_RLC_IMU_MSG_CONTROL |
40058 | #define RLC_RLCS_RLC_IMU_MSG_CONTROL__DATA__SHIFT 0x0 |
40059 | #define RLC_RLCS_RLC_IMU_MSG_CONTROL__DATA_MASK 0xFFFFFFFFL |
40060 | //RLC_RLCS_RLC_IMU_MSG_CNTL |
40061 | #define RLC_RLCS_RLC_IMU_MSG_CNTL__CHGTOG__SHIFT 0x0 |
40062 | #define RLC_RLCS_RLC_IMU_MSG_CNTL__DONETOG__SHIFT 0x1 |
40063 | #define RLC_RLCS_RLC_IMU_MSG_CNTL__RESERVED__SHIFT 0x2 |
40064 | #define RLC_RLCS_RLC_IMU_MSG_CNTL__CHGTOG_MASK 0x00000001L |
40065 | #define RLC_RLCS_RLC_IMU_MSG_CNTL__DONETOG_MASK 0x00000002L |
40066 | #define RLC_RLCS_RLC_IMU_MSG_CNTL__RESERVED_MASK 0xFFFFFFFCL |
40067 | //RLC_RLCS_IMU_RLC_TELEMETRY_DATA_0 |
40068 | #define RLC_RLCS_IMU_RLC_TELEMETRY_DATA_0__CURRENT__SHIFT 0x0 |
40069 | #define RLC_RLCS_IMU_RLC_TELEMETRY_DATA_0__VOLTAGE__SHIFT 0x10 |
40070 | #define RLC_RLCS_IMU_RLC_TELEMETRY_DATA_0__CURRENT_MASK 0x0000FFFFL |
40071 | #define RLC_RLCS_IMU_RLC_TELEMETRY_DATA_0__VOLTAGE_MASK 0xFFFF0000L |
40072 | //RLC_RLCS_IMU_RLC_TELEMETRY_DATA_1 |
40073 | #define RLC_RLCS_IMU_RLC_TELEMETRY_DATA_1__TEMPERATURE1__SHIFT 0x0 |
40074 | #define RLC_RLCS_IMU_RLC_TELEMETRY_DATA_1__RESERVED__SHIFT 0x10 |
40075 | #define RLC_RLCS_IMU_RLC_TELEMETRY_DATA_1__TEMPERATURE1_MASK 0x0000FFFFL |
40076 | #define RLC_RLCS_IMU_RLC_TELEMETRY_DATA_1__RESERVED_MASK 0xFFFF0000L |
40077 | //RLC_RLCS_IMU_RLC_MUTEX_CNTL |
40078 | #define RLC_RLCS_IMU_RLC_MUTEX_CNTL__REQ__SHIFT 0x0 |
40079 | #define RLC_RLCS_IMU_RLC_MUTEX_CNTL__ACQUIRE__SHIFT 0x1 |
40080 | #define RLC_RLCS_IMU_RLC_MUTEX_CNTL__RESERVED__SHIFT 0x2 |
40081 | #define RLC_RLCS_IMU_RLC_MUTEX_CNTL__REQ_MASK 0x00000001L |
40082 | #define RLC_RLCS_IMU_RLC_MUTEX_CNTL__ACQUIRE_MASK 0x00000002L |
40083 | #define RLC_RLCS_IMU_RLC_MUTEX_CNTL__RESERVED_MASK 0xFFFFFFFCL |
40084 | //RLC_RLCS_IMU_RLC_STATUS |
40085 | #define RLC_RLCS_IMU_RLC_STATUS__ALLOW_GFXOFF__SHIFT 0x0 |
40086 | #define RLC_RLCS_IMU_RLC_STATUS__ALLOW_FA_DCS__SHIFT 0x1 |
40087 | #define RLC_RLCS_IMU_RLC_STATUS__RESERVED_14_2__SHIFT 0x2 |
40088 | #define RLC_RLCS_IMU_RLC_STATUS__DISABLE_GFXCLK_DS__SHIFT 0xf |
40089 | #define RLC_RLCS_IMU_RLC_STATUS__RESERVED__SHIFT 0x10 |
40090 | #define RLC_RLCS_IMU_RLC_STATUS__ALLOW_GFXOFF_MASK 0x00000001L |
40091 | #define RLC_RLCS_IMU_RLC_STATUS__ALLOW_FA_DCS_MASK 0x00000002L |
40092 | #define RLC_RLCS_IMU_RLC_STATUS__RESERVED_14_2_MASK 0x00007FFCL |
40093 | #define RLC_RLCS_IMU_RLC_STATUS__DISABLE_GFXCLK_DS_MASK 0x00008000L |
40094 | #define RLC_RLCS_IMU_RLC_STATUS__RESERVED_MASK 0xFFFF0000L |
40095 | //RLC_RLCS_RLC_IMU_STATUS |
40096 | #define RLC_RLCS_RLC_IMU_STATUS__PWR_DOWN_ACTIVE__SHIFT 0x0 |
40097 | #define RLC_RLCS_RLC_IMU_STATUS__RLC_ALIVE__SHIFT 0x1 |
40098 | #define RLC_RLCS_RLC_IMU_STATUS__RESERVED_3_2__SHIFT 0x2 |
40099 | #define RLC_RLCS_RLC_IMU_STATUS__RESERVED__SHIFT 0x4 |
40100 | #define RLC_RLCS_RLC_IMU_STATUS__PWR_DOWN_ACTIVE_MASK 0x00000001L |
40101 | #define RLC_RLCS_RLC_IMU_STATUS__RLC_ALIVE_MASK 0x00000002L |
40102 | #define RLC_RLCS_RLC_IMU_STATUS__RESERVED_3_2_MASK 0x0000000CL |
40103 | #define RLC_RLCS_RLC_IMU_STATUS__RESERVED_MASK 0xFFFFFFF0L |
40104 | //RLC_RLCS_IMU_RAM_DATA_1 |
40105 | #define RLC_RLCS_IMU_RAM_DATA_1__DATA__SHIFT 0x0 |
40106 | #define RLC_RLCS_IMU_RAM_DATA_1__DATA_MASK 0xFFFFFFFFL |
40107 | //RLC_RLCS_IMU_RAM_ADDR_1_LSB |
40108 | #define RLC_RLCS_IMU_RAM_ADDR_1_LSB__DATA__SHIFT 0x0 |
40109 | #define RLC_RLCS_IMU_RAM_ADDR_1_LSB__DATA_MASK 0xFFFFFFFFL |
40110 | //RLC_RLCS_IMU_RAM_ADDR_1_MSB |
40111 | #define RLC_RLCS_IMU_RAM_ADDR_1_MSB__DATA__SHIFT 0x0 |
40112 | #define RLC_RLCS_IMU_RAM_ADDR_1_MSB__RESERVED__SHIFT 0x10 |
40113 | #define RLC_RLCS_IMU_RAM_ADDR_1_MSB__DATA_MASK 0x0000FFFFL |
40114 | #define RLC_RLCS_IMU_RAM_ADDR_1_MSB__RESERVED_MASK 0xFFFF0000L |
40115 | //RLC_RLCS_IMU_RAM_DATA_0 |
40116 | #define RLC_RLCS_IMU_RAM_DATA_0__DATA__SHIFT 0x0 |
40117 | #define RLC_RLCS_IMU_RAM_DATA_0__DATA_MASK 0xFFFFFFFFL |
40118 | //RLC_RLCS_IMU_RAM_ADDR_0_LSB |
40119 | #define RLC_RLCS_IMU_RAM_ADDR_0_LSB__DATA__SHIFT 0x0 |
40120 | #define RLC_RLCS_IMU_RAM_ADDR_0_LSB__DATA_MASK 0xFFFFFFFFL |
40121 | //RLC_RLCS_IMU_RAM_ADDR_0_MSB |
40122 | #define RLC_RLCS_IMU_RAM_ADDR_0_MSB__DATA__SHIFT 0x0 |
40123 | #define RLC_RLCS_IMU_RAM_ADDR_0_MSB__RESERVED__SHIFT 0x10 |
40124 | #define RLC_RLCS_IMU_RAM_ADDR_0_MSB__DATA_MASK 0x0000FFFFL |
40125 | #define RLC_RLCS_IMU_RAM_ADDR_0_MSB__RESERVED_MASK 0xFFFF0000L |
40126 | //RLC_RLCS_IMU_RAM_CNTL |
40127 | #define RLC_RLCS_IMU_RAM_CNTL__REQTOG__SHIFT 0x0 |
40128 | #define RLC_RLCS_IMU_RAM_CNTL__ACKTOG__SHIFT 0x1 |
40129 | #define RLC_RLCS_IMU_RAM_CNTL__RESERVED__SHIFT 0x2 |
40130 | #define RLC_RLCS_IMU_RAM_CNTL__REQTOG_MASK 0x00000001L |
40131 | #define RLC_RLCS_IMU_RAM_CNTL__ACKTOG_MASK 0x00000002L |
40132 | #define RLC_RLCS_IMU_RAM_CNTL__RESERVED_MASK 0xFFFFFFFCL |
40133 | //RLC_RLCS_IMU_GFX_DOORBELL_FENCE |
40134 | #define RLC_RLCS_IMU_GFX_DOORBELL_FENCE__ENABLE__SHIFT 0x0 |
40135 | #define RLC_RLCS_IMU_GFX_DOORBELL_FENCE__ACK__SHIFT 0x1 |
40136 | #define RLC_RLCS_IMU_GFX_DOORBELL_FENCE__RESERVED__SHIFT 0x2 |
40137 | #define RLC_RLCS_IMU_GFX_DOORBELL_FENCE__ENABLE_MASK 0x00000001L |
40138 | #define RLC_RLCS_IMU_GFX_DOORBELL_FENCE__ACK_MASK 0x00000002L |
40139 | #define RLC_RLCS_IMU_GFX_DOORBELL_FENCE__RESERVED_MASK 0xFFFFFFFCL |
40140 | //RLC_RLCS_SDMA_INT_CNTL_1 |
40141 | #define RLC_RLCS_SDMA_INT_CNTL_1__INTERRUPT_ACK__SHIFT 0x0 |
40142 | #define RLC_RLCS_SDMA_INT_CNTL_1__RESP_ID__SHIFT 0x1 |
40143 | #define RLC_RLCS_SDMA_INT_CNTL_1__RESERVED__SHIFT 0x2 |
40144 | #define RLC_RLCS_SDMA_INT_CNTL_1__INTERRUPT_ACK_MASK 0x00000001L |
40145 | #define RLC_RLCS_SDMA_INT_CNTL_1__RESP_ID_MASK 0x00000002L |
40146 | #define RLC_RLCS_SDMA_INT_CNTL_1__RESERVED_MASK 0xFFFFFFFCL |
40147 | //RLC_RLCS_SDMA_INT_CNTL_2 |
40148 | #define RLC_RLCS_SDMA_INT_CNTL_2__AUTO_ACK_EN__SHIFT 0x0 |
40149 | #define RLC_RLCS_SDMA_INT_CNTL_2__AUTO_ACK_ACTIVE__SHIFT 0x1 |
40150 | #define RLC_RLCS_SDMA_INT_CNTL_2__RESERVED__SHIFT 0x2 |
40151 | #define RLC_RLCS_SDMA_INT_CNTL_2__AUTO_ACK_EN_MASK 0x00000001L |
40152 | #define RLC_RLCS_SDMA_INT_CNTL_2__AUTO_ACK_ACTIVE_MASK 0x00000002L |
40153 | #define RLC_RLCS_SDMA_INT_CNTL_2__RESERVED_MASK 0xFFFFFFFCL |
40154 | //RLC_RLCS_SDMA_INT_STAT |
40155 | #define RLC_RLCS_SDMA_INT_STAT__REQ_IDLE_HIST__SHIFT 0x0 |
40156 | #define RLC_RLCS_SDMA_INT_STAT__REQ_BUSY_HIST__SHIFT 0x8 |
40157 | #define RLC_RLCS_SDMA_INT_STAT__LAST_SDMA_RLC_INT_ID__SHIFT 0x10 |
40158 | #define RLC_RLCS_SDMA_INT_STAT__SDMA_RLC_INT_PENDING__SHIFT 0x11 |
40159 | #define RLC_RLCS_SDMA_INT_STAT__RESERVED__SHIFT 0x12 |
40160 | #define RLC_RLCS_SDMA_INT_STAT__REQ_IDLE_HIST_MASK 0x000000FFL |
40161 | #define RLC_RLCS_SDMA_INT_STAT__REQ_BUSY_HIST_MASK 0x0000FF00L |
40162 | #define RLC_RLCS_SDMA_INT_STAT__LAST_SDMA_RLC_INT_ID_MASK 0x00010000L |
40163 | #define RLC_RLCS_SDMA_INT_STAT__SDMA_RLC_INT_PENDING_MASK 0x00020000L |
40164 | #define RLC_RLCS_SDMA_INT_STAT__RESERVED_MASK 0xFFFC0000L |
40165 | //RLC_RLCS_SDMA_INT_INFO |
40166 | #define RLC_RLCS_SDMA_INT_INFO__REQ_IDLE_TO_FW__SHIFT 0x0 |
40167 | #define RLC_RLCS_SDMA_INT_INFO__REQ_BUSY_TO_FW__SHIFT 0x8 |
40168 | #define RLC_RLCS_SDMA_INT_INFO__INTERRUPT_ID__SHIFT 0x10 |
40169 | #define RLC_RLCS_SDMA_INT_INFO__RESERVED__SHIFT 0x11 |
40170 | #define RLC_RLCS_SDMA_INT_INFO__REQ_IDLE_TO_FW_MASK 0x000000FFL |
40171 | #define RLC_RLCS_SDMA_INT_INFO__REQ_BUSY_TO_FW_MASK 0x0000FF00L |
40172 | #define RLC_RLCS_SDMA_INT_INFO__INTERRUPT_ID_MASK 0x00010000L |
40173 | #define RLC_RLCS_SDMA_INT_INFO__RESERVED_MASK 0xFFFE0000L |
40174 | //RLC_RLCS_PMM_CGCG_CNTL |
40175 | #define RLC_RLCS_PMM_CGCG_CNTL__VALID__SHIFT 0x0 |
40176 | #define RLC_RLCS_PMM_CGCG_CNTL__CLEAN__SHIFT 0x1 |
40177 | #define RLC_RLCS_PMM_CGCG_CNTL__RESERVED__SHIFT 0x2 |
40178 | #define RLC_RLCS_PMM_CGCG_CNTL__VALID_MASK 0x00000001L |
40179 | #define RLC_RLCS_PMM_CGCG_CNTL__CLEAN_MASK 0x00000002L |
40180 | #define RLC_RLCS_PMM_CGCG_CNTL__RESERVED_MASK 0xFFFFFFFCL |
40181 | //RLC_RLCS_GFX_MEM_POWER_CTRL_LO |
40182 | #define RLC_RLCS_GFX_MEM_POWER_CTRL_LO__DATA__SHIFT 0x0 |
40183 | #define RLC_RLCS_GFX_MEM_POWER_CTRL_LO__DATA_MASK 0xFFFFFFFFL |
40184 | //RLC_RLCS_GFX_RM_CNTL |
40185 | #define RLC_RLCS_GFX_RM_CNTL__RLC_GFX_RM_VALID__SHIFT 0x0 |
40186 | #define RLC_RLCS_GFX_RM_CNTL__RESERVED__SHIFT 0x1 |
40187 | #define RLC_RLCS_GFX_RM_CNTL__RLC_GFX_RM_VALID_MASK 0x00000001L |
40188 | #define RLC_RLCS_GFX_RM_CNTL__RESERVED_MASK 0xFFFFFFFEL |
40189 | //RLC_RLCS_IH_CTRL_1 |
40190 | #define RLC_RLCS_IH_CTRL_1__IH_CONTEXT_ID_1__SHIFT 0x0 |
40191 | #define RLC_RLCS_IH_CTRL_1__IH_CONTEXT_ID_1_MASK 0xFFFFFFFFL |
40192 | //RLC_RLCS_IH_CTRL_2 |
40193 | #define RLC_RLCS_IH_CTRL_2__IH_CONTEXT_ID_2__SHIFT 0x0 |
40194 | #define RLC_RLCS_IH_CTRL_2__IH_RING_ID__SHIFT 0x8 |
40195 | #define RLC_RLCS_IH_CTRL_2__IH_VM_ID__SHIFT 0x10 |
40196 | #define RLC_RLCS_IH_CTRL_2__RESERVED__SHIFT 0x14 |
40197 | #define RLC_RLCS_IH_CTRL_2__IH_CONTEXT_ID_2_MASK 0x000000FFL |
40198 | #define RLC_RLCS_IH_CTRL_2__IH_RING_ID_MASK 0x0000FF00L |
40199 | #define RLC_RLCS_IH_CTRL_2__IH_VM_ID_MASK 0x000F0000L |
40200 | #define RLC_RLCS_IH_CTRL_2__RESERVED_MASK 0xFFF00000L |
40201 | //RLC_RLCS_IH_CTRL_3 |
40202 | #define RLC_RLCS_IH_CTRL_3__IH_SOURCE_ID__SHIFT 0x0 |
40203 | #define RLC_RLCS_IH_CTRL_3__IH_VF_ID__SHIFT 0x8 |
40204 | #define RLC_RLCS_IH_CTRL_3__IH_VF__SHIFT 0xd |
40205 | #define RLC_RLCS_IH_CTRL_3__RESERVED__SHIFT 0xe |
40206 | #define RLC_RLCS_IH_CTRL_3__IH_SOURCE_ID_MASK 0x000000FFL |
40207 | #define RLC_RLCS_IH_CTRL_3__IH_VF_ID_MASK 0x00001F00L |
40208 | #define RLC_RLCS_IH_CTRL_3__IH_VF_MASK 0x00002000L |
40209 | #define RLC_RLCS_IH_CTRL_3__RESERVED_MASK 0xFFFFC000L |
40210 | //RLC_RLCS_IH_STATUS |
40211 | #define RLC_RLCS_IH_STATUS__IH_CREDIT_COUNT__SHIFT 0x0 |
40212 | #define RLC_RLCS_IH_STATUS__IH_BUSY__SHIFT 0x6 |
40213 | #define RLC_RLCS_IH_STATUS__IH_WRITE_DONE__SHIFT 0x7 |
40214 | #define RLC_RLCS_IH_STATUS__RESERVED__SHIFT 0x8 |
40215 | #define RLC_RLCS_IH_STATUS__IH_CREDIT_COUNT_MASK 0x0000003FL |
40216 | #define RLC_RLCS_IH_STATUS__IH_BUSY_MASK 0x00000040L |
40217 | #define RLC_RLCS_IH_STATUS__IH_WRITE_DONE_MASK 0x00000080L |
40218 | #define RLC_RLCS_IH_STATUS__RESERVED_MASK 0xFFFFFF00L |
40219 | //RLC_RLCS_DEC_END |
40220 | |
40221 | |
40222 | // addressBlock: gc_pfvfdec_rlc |
40223 | //RLC_SAFE_MODE |
40224 | #define RLC_SAFE_MODE__CMD__SHIFT 0x0 |
40225 | #define RLC_SAFE_MODE__MESSAGE__SHIFT 0x1 |
40226 | #define RLC_SAFE_MODE__RESERVED1__SHIFT 0x5 |
40227 | #define RLC_SAFE_MODE__RESPONSE__SHIFT 0x8 |
40228 | #define RLC_SAFE_MODE__RESERVED__SHIFT 0xc |
40229 | #define RLC_SAFE_MODE__CMD_MASK 0x00000001L |
40230 | #define RLC_SAFE_MODE__MESSAGE_MASK 0x0000001EL |
40231 | #define RLC_SAFE_MODE__RESERVED1_MASK 0x000000E0L |
40232 | #define RLC_SAFE_MODE__RESPONSE_MASK 0x00000F00L |
40233 | #define RLC_SAFE_MODE__RESERVED_MASK 0xFFFFF000L |
40234 | //RLC_SPM_SAMPLE_CNT |
40235 | #define RLC_SPM_SAMPLE_CNT__COUNT__SHIFT 0x0 |
40236 | #define RLC_SPM_SAMPLE_CNT__COUNT_MASK 0xFFFFFFFFL |
40237 | //RLC_SPM_MC_CNTL |
40238 | #define RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT 0x0 |
40239 | #define RLC_SPM_MC_CNTL__RLC_SPM_POLICY__SHIFT 0x4 |
40240 | #define RLC_SPM_MC_CNTL__RLC_SPM_PERF_CNTR__SHIFT 0x6 |
40241 | #define RLC_SPM_MC_CNTL__RLC_SPM_FED__SHIFT 0x7 |
40242 | #define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_OVER__SHIFT 0x8 |
40243 | #define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE__SHIFT 0x9 |
40244 | #define RLC_SPM_MC_CNTL__RLC_SPM_BC__SHIFT 0xc |
40245 | #define RLC_SPM_MC_CNTL__RLC_SPM_RO__SHIFT 0xd |
40246 | #define RLC_SPM_MC_CNTL__RLC_SPM_VOL__SHIFT 0xe |
40247 | #define RLC_SPM_MC_CNTL__RLC_SPM_NOFILL__SHIFT 0xf |
40248 | #define RLC_SPM_MC_CNTL__RESERVED_3__SHIFT 0x10 |
40249 | #define RLC_SPM_MC_CNTL__RLC_SPM_LLC_NOALLOC__SHIFT 0x12 |
40250 | #define RLC_SPM_MC_CNTL__RLC_SPM_LLC_NOALLOC_OVER__SHIFT 0x13 |
40251 | #define RLC_SPM_MC_CNTL__RESERVED__SHIFT 0x14 |
40252 | #define RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK 0x0000000FL |
40253 | #define RLC_SPM_MC_CNTL__RLC_SPM_POLICY_MASK 0x00000030L |
40254 | #define RLC_SPM_MC_CNTL__RLC_SPM_PERF_CNTR_MASK 0x00000040L |
40255 | #define RLC_SPM_MC_CNTL__RLC_SPM_FED_MASK 0x00000080L |
40256 | #define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_OVER_MASK 0x00000100L |
40257 | #define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_MASK 0x00000E00L |
40258 | #define RLC_SPM_MC_CNTL__RLC_SPM_BC_MASK 0x00001000L |
40259 | #define RLC_SPM_MC_CNTL__RLC_SPM_RO_MASK 0x00002000L |
40260 | #define RLC_SPM_MC_CNTL__RLC_SPM_VOL_MASK 0x00004000L |
40261 | #define RLC_SPM_MC_CNTL__RLC_SPM_NOFILL_MASK 0x00008000L |
40262 | #define RLC_SPM_MC_CNTL__RESERVED_3_MASK 0x00030000L |
40263 | #define RLC_SPM_MC_CNTL__RLC_SPM_LLC_NOALLOC_MASK 0x00040000L |
40264 | #define RLC_SPM_MC_CNTL__RLC_SPM_LLC_NOALLOC_OVER_MASK 0x00080000L |
40265 | #define RLC_SPM_MC_CNTL__RESERVED_MASK 0xFFF00000L |
40266 | //RLC_SPM_INT_CNTL |
40267 | #define RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL__SHIFT 0x0 |
40268 | #define RLC_SPM_INT_CNTL__RESERVED__SHIFT 0x1 |
40269 | #define RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL_MASK 0x00000001L |
40270 | #define RLC_SPM_INT_CNTL__RESERVED_MASK 0xFFFFFFFEL |
40271 | //RLC_SPM_INT_STATUS |
40272 | #define RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS__SHIFT 0x0 |
40273 | #define RLC_SPM_INT_STATUS__RESERVED__SHIFT 0x1 |
40274 | #define RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS_MASK 0x00000001L |
40275 | #define RLC_SPM_INT_STATUS__RESERVED_MASK 0xFFFFFFFEL |
40276 | //RLC_SPM_INT_INFO_1 |
40277 | #define RLC_SPM_INT_INFO_1__INTERRUPT_INFO_1__SHIFT 0x0 |
40278 | #define RLC_SPM_INT_INFO_1__INTERRUPT_INFO_1_MASK 0xFFFFFFFFL |
40279 | //RLC_SPM_INT_INFO_2 |
40280 | #define RLC_SPM_INT_INFO_2__INTERRUPT_INFO_2__SHIFT 0x0 |
40281 | #define RLC_SPM_INT_INFO_2__INTERRUPT_ID__SHIFT 0x10 |
40282 | #define RLC_SPM_INT_INFO_2__RESERVED__SHIFT 0x18 |
40283 | #define RLC_SPM_INT_INFO_2__INTERRUPT_INFO_2_MASK 0x0000FFFFL |
40284 | #define RLC_SPM_INT_INFO_2__INTERRUPT_ID_MASK 0x00FF0000L |
40285 | #define RLC_SPM_INT_INFO_2__RESERVED_MASK 0xFF000000L |
40286 | //RLC_CSIB_ADDR_LO |
40287 | #define RLC_CSIB_ADDR_LO__ADDRESS__SHIFT 0x0 |
40288 | #define RLC_CSIB_ADDR_LO__ADDRESS_MASK 0xFFFFFFFFL |
40289 | //RLC_CSIB_ADDR_HI |
40290 | #define RLC_CSIB_ADDR_HI__ADDRESS__SHIFT 0x0 |
40291 | #define RLC_CSIB_ADDR_HI__ADDRESS_MASK 0x0000FFFFL |
40292 | //RLC_CSIB_LENGTH |
40293 | #define RLC_CSIB_LENGTH__LENGTH__SHIFT 0x0 |
40294 | #define RLC_CSIB_LENGTH__LENGTH_MASK 0xFFFFFFFFL |
40295 | //RLC_CP_SCHEDULERS |
40296 | #define RLC_CP_SCHEDULERS__scheduler0__SHIFT 0x0 |
40297 | #define RLC_CP_SCHEDULERS__scheduler1__SHIFT 0x8 |
40298 | #define RLC_CP_SCHEDULERS__scheduler0_MASK 0x000000FFL |
40299 | #define RLC_CP_SCHEDULERS__scheduler1_MASK 0x0000FF00L |
40300 | //RLC_CP_EOF_INT |
40301 | #define RLC_CP_EOF_INT__INTERRUPT__SHIFT 0x0 |
40302 | #define RLC_CP_EOF_INT__RESERVED__SHIFT 0x1 |
40303 | #define RLC_CP_EOF_INT__INTERRUPT_MASK 0x00000001L |
40304 | #define RLC_CP_EOF_INT__RESERVED_MASK 0xFFFFFFFEL |
40305 | //RLC_CP_EOF_INT_CNT |
40306 | #define RLC_CP_EOF_INT_CNT__CNT__SHIFT 0x0 |
40307 | #define RLC_CP_EOF_INT_CNT__CNT_MASK 0xFFFFFFFFL |
40308 | //RLC_SPARE_INT_0 |
40309 | #define RLC_SPARE_INT_0__DATA__SHIFT 0x0 |
40310 | #define RLC_SPARE_INT_0__PROCESSING__SHIFT 0x1e |
40311 | #define RLC_SPARE_INT_0__COMPLETE__SHIFT 0x1f |
40312 | #define RLC_SPARE_INT_0__DATA_MASK 0x3FFFFFFFL |
40313 | #define RLC_SPARE_INT_0__PROCESSING_MASK 0x40000000L |
40314 | #define RLC_SPARE_INT_0__COMPLETE_MASK 0x80000000L |
40315 | //RLC_SPARE_INT_1 |
40316 | #define RLC_SPARE_INT_1__DATA__SHIFT 0x0 |
40317 | #define RLC_SPARE_INT_1__PROCESSING__SHIFT 0x1e |
40318 | #define RLC_SPARE_INT_1__COMPLETE__SHIFT 0x1f |
40319 | #define RLC_SPARE_INT_1__DATA_MASK 0x3FFFFFFFL |
40320 | #define RLC_SPARE_INT_1__PROCESSING_MASK 0x40000000L |
40321 | #define RLC_SPARE_INT_1__COMPLETE_MASK 0x80000000L |
40322 | //RLC_SPARE_INT_2 |
40323 | #define RLC_SPARE_INT_2__DATA__SHIFT 0x0 |
40324 | #define RLC_SPARE_INT_2__PROCESSING__SHIFT 0x1e |
40325 | #define RLC_SPARE_INT_2__COMPLETE__SHIFT 0x1f |
40326 | #define RLC_SPARE_INT_2__DATA_MASK 0x3FFFFFFFL |
40327 | #define RLC_SPARE_INT_2__PROCESSING_MASK 0x40000000L |
40328 | #define RLC_SPARE_INT_2__COMPLETE_MASK 0x80000000L |
40329 | //RLC_PACE_SPARE_INT |
40330 | #define RLC_PACE_SPARE_INT__INTERRUPT__SHIFT 0x0 |
40331 | #define RLC_PACE_SPARE_INT__RESERVED__SHIFT 0x1 |
40332 | #define RLC_PACE_SPARE_INT__INTERRUPT_MASK 0x00000001L |
40333 | #define RLC_PACE_SPARE_INT__RESERVED_MASK 0xFFFFFFFEL |
40334 | //RLC_PACE_SPARE_INT_1 |
40335 | #define RLC_PACE_SPARE_INT_1__INTERRUPT__SHIFT 0x0 |
40336 | #define RLC_PACE_SPARE_INT_1__RESERVED__SHIFT 0x1 |
40337 | #define RLC_PACE_SPARE_INT_1__INTERRUPT_MASK 0x00000001L |
40338 | #define RLC_PACE_SPARE_INT_1__RESERVED_MASK 0xFFFFFFFEL |
40339 | //RLC_RLCV_SPARE_INT_1 |
40340 | #define RLC_RLCV_SPARE_INT_1__INTERRUPT__SHIFT 0x0 |
40341 | #define RLC_RLCV_SPARE_INT_1__RESERVED__SHIFT 0x1 |
40342 | #define RLC_RLCV_SPARE_INT_1__INTERRUPT_MASK 0x00000001L |
40343 | #define RLC_RLCV_SPARE_INT_1__RESERVED_MASK 0xFFFFFFFEL |
40344 | |
40345 | |
40346 | // addressBlock: gc_pwrdec |
40347 | //CGTS_TCC_DISABLE |
40348 | #define CGTS_TCC_DISABLE__WRITE_DIS__SHIFT 0x0 |
40349 | #define CGTS_TCC_DISABLE__HI_TCC_DISABLE__SHIFT 0x8 |
40350 | #define CGTS_TCC_DISABLE__TCC_DISABLE__SHIFT 0x10 |
40351 | #define CGTS_TCC_DISABLE__WRITE_DIS_MASK 0x00000001L |
40352 | #define CGTS_TCC_DISABLE__HI_TCC_DISABLE_MASK 0x0000FF00L |
40353 | #define CGTS_TCC_DISABLE__TCC_DISABLE_MASK 0xFFFF0000L |
40354 | //CGTX_SPI_DEBUG_CLK_CTRL |
40355 | #define CGTX_SPI_DEBUG_CLK_CTRL__GRP5_CG_OFF_HYST__SHIFT 0x0 |
40356 | #define CGTX_SPI_DEBUG_CLK_CTRL__GRP5_CG_OVERRIDE__SHIFT 0x6 |
40357 | #define CGTX_SPI_DEBUG_CLK_CTRL__ALL_CLK_ON_OVERRIDE__SHIFT 0x7 |
40358 | #define CGTX_SPI_DEBUG_CLK_CTRL__SPI_SH_CLK_CONTROL__SHIFT 0x8 |
40359 | #define CGTX_SPI_DEBUG_CLK_CTRL__SPI_REPEATER_FGCG_OVERRIDE__SHIFT 0x9 |
40360 | #define CGTX_SPI_DEBUG_CLK_CTRL__GRP5_CG_OFF_HYST_MASK 0x0000003FL |
40361 | #define CGTX_SPI_DEBUG_CLK_CTRL__GRP5_CG_OVERRIDE_MASK 0x00000040L |
40362 | #define CGTX_SPI_DEBUG_CLK_CTRL__ALL_CLK_ON_OVERRIDE_MASK 0x00000080L |
40363 | #define CGTX_SPI_DEBUG_CLK_CTRL__SPI_SH_CLK_CONTROL_MASK 0x00000100L |
40364 | #define CGTX_SPI_DEBUG_CLK_CTRL__SPI_REPEATER_FGCG_OVERRIDE_MASK 0x00000200L |
40365 | //CGTT_VGT_CLK_CTRL |
40366 | #define CGTT_VGT_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
40367 | #define CGTT_VGT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
40368 | #define CGTT_VGT_CLK_CTRL__PERF_ENABLE__SHIFT 0xf |
40369 | #define CGTT_VGT_CLK_CTRL__DBG_ENABLE__SHIFT 0x10 |
40370 | #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
40371 | #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
40372 | #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
40373 | #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
40374 | #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
40375 | #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
40376 | #define CGTT_VGT_CLK_CTRL__PI1_OVERRIDE__SHIFT 0x17 |
40377 | #define CGTT_VGT_CLK_CTRL__PI0_OVERRIDE__SHIFT 0x18 |
40378 | #define CGTT_VGT_CLK_CTRL__HS_OVERRIDE__SHIFT 0x19 |
40379 | #define CGTT_VGT_CLK_CTRL__TESS_OVERRIDE__SHIFT 0x1c |
40380 | #define CGTT_VGT_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1d |
40381 | #define CGTT_VGT_CLK_CTRL__RBIU_INPUT_OVERRIDE__SHIFT 0x1e |
40382 | #define CGTT_VGT_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f |
40383 | #define CGTT_VGT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
40384 | #define CGTT_VGT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
40385 | #define CGTT_VGT_CLK_CTRL__PERF_ENABLE_MASK 0x00008000L |
40386 | #define CGTT_VGT_CLK_CTRL__DBG_ENABLE_MASK 0x00010000L |
40387 | #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
40388 | #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
40389 | #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
40390 | #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
40391 | #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
40392 | #define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
40393 | #define CGTT_VGT_CLK_CTRL__PI1_OVERRIDE_MASK 0x00800000L |
40394 | #define CGTT_VGT_CLK_CTRL__PI0_OVERRIDE_MASK 0x01000000L |
40395 | #define CGTT_VGT_CLK_CTRL__HS_OVERRIDE_MASK 0x02000000L |
40396 | #define CGTT_VGT_CLK_CTRL__TESS_OVERRIDE_MASK 0x10000000L |
40397 | #define CGTT_VGT_CLK_CTRL__CORE_OVERRIDE_MASK 0x20000000L |
40398 | #define CGTT_VGT_CLK_CTRL__RBIU_INPUT_OVERRIDE_MASK 0x40000000L |
40399 | #define CGTT_VGT_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L |
40400 | //CGTT_IA_CLK_CTRL |
40401 | #define CGTT_IA_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
40402 | #define CGTT_IA_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
40403 | #define CGTT_IA_CLK_CTRL__PERF_ENABLE__SHIFT 0xf |
40404 | #define CGTT_IA_CLK_CTRL__DBG_ENABLE__SHIFT 0x10 |
40405 | #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
40406 | #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
40407 | #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
40408 | #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
40409 | #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
40410 | #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
40411 | #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 |
40412 | #define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 |
40413 | #define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 |
40414 | #define CGTT_IA_CLK_CTRL__DIST_OVERRIDE__SHIFT 0x1a |
40415 | #define CGTT_IA_CLK_CTRL__PERF_OVERRIDE__SHIFT 0x1b |
40416 | #define CGTT_IA_CLK_CTRL__PCM_OVERRIDE__SHIFT 0x1c |
40417 | #define CGTT_IA_CLK_CTRL__TESS_DIST_OVERRIDE__SHIFT 0x1d |
40418 | #define CGTT_IA_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e |
40419 | #define CGTT_IA_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f |
40420 | #define CGTT_IA_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
40421 | #define CGTT_IA_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
40422 | #define CGTT_IA_CLK_CTRL__PERF_ENABLE_MASK 0x00008000L |
40423 | #define CGTT_IA_CLK_CTRL__DBG_ENABLE_MASK 0x00010000L |
40424 | #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
40425 | #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
40426 | #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
40427 | #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
40428 | #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
40429 | #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
40430 | #define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L |
40431 | #define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L |
40432 | #define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L |
40433 | #define CGTT_IA_CLK_CTRL__DIST_OVERRIDE_MASK 0x04000000L |
40434 | #define CGTT_IA_CLK_CTRL__PERF_OVERRIDE_MASK 0x08000000L |
40435 | #define CGTT_IA_CLK_CTRL__PCM_OVERRIDE_MASK 0x10000000L |
40436 | #define CGTT_IA_CLK_CTRL__TESS_DIST_OVERRIDE_MASK 0x20000000L |
40437 | #define CGTT_IA_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000L |
40438 | #define CGTT_IA_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L |
40439 | //CGTT_WD_CLK_CTRL |
40440 | #define CGTT_WD_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
40441 | #define CGTT_WD_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
40442 | #define CGTT_WD_CLK_CTRL__PERF_ENABLE__SHIFT 0xf |
40443 | #define CGTT_WD_CLK_CTRL__DBG_ENABLE__SHIFT 0x10 |
40444 | #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
40445 | #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
40446 | #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
40447 | #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
40448 | #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
40449 | #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
40450 | #define CGTT_WD_CLK_CTRL__FE_OUT_OVERRIDE__SHIFT 0x17 |
40451 | #define CGTT_WD_CLK_CTRL__ASSEMBLER_OVERRIDE__SHIFT 0x18 |
40452 | #define CGTT_WD_CLK_CTRL__DMA_PROC0_OVERRIDE__SHIFT 0x19 |
40453 | #define CGTT_WD_CLK_CTRL__DMA_PROC1_OVERRIDE__SHIFT 0x1a |
40454 | #define CGTT_WD_CLK_CTRL__PERF_OVERRIDE__SHIFT 0x1b |
40455 | #define CGTT_WD_CLK_CTRL__DMA_OVERRIDE__SHIFT 0x1c |
40456 | #define CGTT_WD_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1d |
40457 | #define CGTT_WD_CLK_CTRL__RBIU_INPUT_OVERRIDE__SHIFT 0x1e |
40458 | #define CGTT_WD_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f |
40459 | #define CGTT_WD_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
40460 | #define CGTT_WD_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
40461 | #define CGTT_WD_CLK_CTRL__PERF_ENABLE_MASK 0x00008000L |
40462 | #define CGTT_WD_CLK_CTRL__DBG_ENABLE_MASK 0x00010000L |
40463 | #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
40464 | #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
40465 | #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
40466 | #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
40467 | #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
40468 | #define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
40469 | #define CGTT_WD_CLK_CTRL__FE_OUT_OVERRIDE_MASK 0x00800000L |
40470 | #define CGTT_WD_CLK_CTRL__ASSEMBLER_OVERRIDE_MASK 0x01000000L |
40471 | #define CGTT_WD_CLK_CTRL__DMA_PROC0_OVERRIDE_MASK 0x02000000L |
40472 | #define CGTT_WD_CLK_CTRL__DMA_PROC1_OVERRIDE_MASK 0x04000000L |
40473 | #define CGTT_WD_CLK_CTRL__PERF_OVERRIDE_MASK 0x08000000L |
40474 | #define CGTT_WD_CLK_CTRL__DMA_OVERRIDE_MASK 0x10000000L |
40475 | #define CGTT_WD_CLK_CTRL__CORE_OVERRIDE_MASK 0x20000000L |
40476 | #define CGTT_WD_CLK_CTRL__RBIU_INPUT_OVERRIDE_MASK 0x40000000L |
40477 | #define CGTT_WD_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L |
40478 | //CGTT_GS_NGG_CLK_CTRL |
40479 | #define CGTT_GS_NGG_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
40480 | #define CGTT_GS_NGG_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
40481 | #define CGTT_GS_NGG_CLK_CTRL__PERF_ENABLE__SHIFT 0xf |
40482 | #define CGTT_GS_NGG_CLK_CTRL__DBG_ENABLE__SHIFT 0x10 |
40483 | #define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
40484 | #define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
40485 | #define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
40486 | #define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
40487 | #define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
40488 | #define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
40489 | #define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 |
40490 | #define CGTT_GS_NGG_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 |
40491 | #define CGTT_GS_NGG_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 |
40492 | #define CGTT_GS_NGG_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a |
40493 | #define CGTT_GS_NGG_CLK_CTRL__PERF_OVERRIDE__SHIFT 0x1b |
40494 | #define CGTT_GS_NGG_CLK_CTRL__PRIMGEN_OVERRIDE__SHIFT 0x1c |
40495 | #define CGTT_GS_NGG_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f |
40496 | #define CGTT_GS_NGG_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
40497 | #define CGTT_GS_NGG_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
40498 | #define CGTT_GS_NGG_CLK_CTRL__PERF_ENABLE_MASK 0x00008000L |
40499 | #define CGTT_GS_NGG_CLK_CTRL__DBG_ENABLE_MASK 0x00010000L |
40500 | #define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
40501 | #define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
40502 | #define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
40503 | #define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
40504 | #define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
40505 | #define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
40506 | #define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L |
40507 | #define CGTT_GS_NGG_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L |
40508 | #define CGTT_GS_NGG_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L |
40509 | #define CGTT_GS_NGG_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L |
40510 | #define CGTT_GS_NGG_CLK_CTRL__PERF_OVERRIDE_MASK 0x08000000L |
40511 | #define CGTT_GS_NGG_CLK_CTRL__PRIMGEN_OVERRIDE_MASK 0x10000000L |
40512 | #define CGTT_GS_NGG_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L |
40513 | //CGTT_PA_CLK_CTRL |
40514 | #define CGTT_PA_CLK_CTRL__CLIP_SU_PRIM_FIFO_CLK_OVERRIDE__SHIFT 0xc |
40515 | #define CGTT_PA_CLK_CTRL__SXIFCCG_CLK_OVERRIDE__SHIFT 0xd |
40516 | #define CGTT_PA_CLK_CTRL__AG_CLK_OVERRIDE__SHIFT 0xe |
40517 | #define CGTT_PA_CLK_CTRL__VE_VTE_REC_CLK_OVERRIDE__SHIFT 0xf |
40518 | #define CGTT_PA_CLK_CTRL__ENGG_CLK_OVERRIDE__SHIFT 0x10 |
40519 | #define CGTT_PA_CLK_CTRL__CL_VTE_CLK_OVERRIDE__SHIFT 0x11 |
40520 | #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
40521 | #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
40522 | #define CGTT_PA_CLK_CTRL__AG_REG_CLK_OVERRIDE__SHIFT 0x14 |
40523 | #define CGTT_PA_CLK_CTRL__CL_VTE_REG_CLK_OVERRIDE__SHIFT 0x15 |
40524 | #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
40525 | #define CGTT_PA_CLK_CTRL__DEBUG_BUS_EN__SHIFT 0x17 |
40526 | #define CGTT_PA_CLK_CTRL__VTE_REG_CLK_OVERRIDE__SHIFT 0x18 |
40527 | #define CGTT_PA_CLK_CTRL__PERFMON_CLK_OVERRIDE__SHIFT 0x19 |
40528 | #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a |
40529 | #define CGTT_PA_CLK_CTRL__NGG_INDEX_CLK_OVERRIDE__SHIFT 0x1b |
40530 | #define CGTT_PA_CLK_CTRL__NGG_CSB_CLK_OVERRIDE__SHIFT 0x1c |
40531 | #define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE__SHIFT 0x1d |
40532 | #define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE__SHIFT 0x1e |
40533 | #define CGTT_PA_CLK_CTRL__SU_CL_REG_CLK_OVERRIDE__SHIFT 0x1f |
40534 | #define CGTT_PA_CLK_CTRL__CLIP_SU_PRIM_FIFO_CLK_OVERRIDE_MASK 0x00001000L |
40535 | #define CGTT_PA_CLK_CTRL__SXIFCCG_CLK_OVERRIDE_MASK 0x00002000L |
40536 | #define CGTT_PA_CLK_CTRL__AG_CLK_OVERRIDE_MASK 0x00004000L |
40537 | #define CGTT_PA_CLK_CTRL__VE_VTE_REC_CLK_OVERRIDE_MASK 0x00008000L |
40538 | #define CGTT_PA_CLK_CTRL__ENGG_CLK_OVERRIDE_MASK 0x00010000L |
40539 | #define CGTT_PA_CLK_CTRL__CL_VTE_CLK_OVERRIDE_MASK 0x00020000L |
40540 | #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
40541 | #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
40542 | #define CGTT_PA_CLK_CTRL__AG_REG_CLK_OVERRIDE_MASK 0x00100000L |
40543 | #define CGTT_PA_CLK_CTRL__CL_VTE_REG_CLK_OVERRIDE_MASK 0x00200000L |
40544 | #define CGTT_PA_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
40545 | #define CGTT_PA_CLK_CTRL__DEBUG_BUS_EN_MASK 0x00800000L |
40546 | #define CGTT_PA_CLK_CTRL__VTE_REG_CLK_OVERRIDE_MASK 0x01000000L |
40547 | #define CGTT_PA_CLK_CTRL__PERFMON_CLK_OVERRIDE_MASK 0x02000000L |
40548 | #define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L |
40549 | #define CGTT_PA_CLK_CTRL__NGG_INDEX_CLK_OVERRIDE_MASK 0x08000000L |
40550 | #define CGTT_PA_CLK_CTRL__NGG_CSB_CLK_OVERRIDE_MASK 0x10000000L |
40551 | #define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE_MASK 0x20000000L |
40552 | #define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE_MASK 0x40000000L |
40553 | #define CGTT_PA_CLK_CTRL__SU_CL_REG_CLK_OVERRIDE_MASK 0x80000000L |
40554 | //CGTT_SC_CLK_CTRL0 |
40555 | #define CGTT_SC_CLK_CTRL0__ON_DELAY__SHIFT 0x0 |
40556 | #define CGTT_SC_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4 |
40557 | #define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_STALL_OVERRIDE__SHIFT 0x10 |
40558 | #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE5__SHIFT 0x11 |
40559 | #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE4__SHIFT 0x12 |
40560 | #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE3__SHIFT 0x13 |
40561 | #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE2__SHIFT 0x14 |
40562 | #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE1__SHIFT 0x15 |
40563 | #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE0__SHIFT 0x16 |
40564 | #define CGTT_SC_CLK_CTRL0__REG_CLK_STALL_OVERRIDE__SHIFT 0x17 |
40565 | #define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_OVERRIDE__SHIFT 0x18 |
40566 | #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE5__SHIFT 0x19 |
40567 | #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE4__SHIFT 0x1a |
40568 | #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE3__SHIFT 0x1b |
40569 | #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT 0x1c |
40570 | #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1d |
40571 | #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1e |
40572 | #define CGTT_SC_CLK_CTRL0__REG_CLK_OVERRIDE__SHIFT 0x1f |
40573 | #define CGTT_SC_CLK_CTRL0__ON_DELAY_MASK 0x0000000FL |
40574 | #define CGTT_SC_CLK_CTRL0__OFF_HYSTERESIS_MASK 0x00000FF0L |
40575 | #define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_STALL_OVERRIDE_MASK 0x00010000L |
40576 | #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE5_MASK 0x00020000L |
40577 | #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE4_MASK 0x00040000L |
40578 | #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE3_MASK 0x00080000L |
40579 | #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE2_MASK 0x00100000L |
40580 | #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE1_MASK 0x00200000L |
40581 | #define CGTT_SC_CLK_CTRL0__SOFT_STALL_OVERRIDE0_MASK 0x00400000L |
40582 | #define CGTT_SC_CLK_CTRL0__REG_CLK_STALL_OVERRIDE_MASK 0x00800000L |
40583 | #define CGTT_SC_CLK_CTRL0__PFF_ZFF_MEM_CLK_OVERRIDE_MASK 0x01000000L |
40584 | #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE5_MASK 0x02000000L |
40585 | #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE4_MASK 0x04000000L |
40586 | #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE3_MASK 0x08000000L |
40587 | #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE2_MASK 0x10000000L |
40588 | #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x20000000L |
40589 | #define CGTT_SC_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x40000000L |
40590 | #define CGTT_SC_CLK_CTRL0__REG_CLK_OVERRIDE_MASK 0x80000000L |
40591 | //CGTT_SC_CLK_CTRL1 |
40592 | #define CGTT_SC_CLK_CTRL1__ON_DELAY__SHIFT 0x0 |
40593 | #define CGTT_SC_CLK_CTRL1__OFF_HYSTERESIS__SHIFT 0x4 |
40594 | #define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_STALL_OVERRIDE0__SHIFT 0x10 |
40595 | #define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_STALL_OVERRIDE__SHIFT 0x11 |
40596 | #define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_STALL_OVERRIDE__SHIFT 0x12 |
40597 | #define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_STALL_OVERRIDE__SHIFT 0x13 |
40598 | #define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_STALL_OVERRIDE__SHIFT 0x14 |
40599 | #define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_STALL_OVERRIDE__SHIFT 0x15 |
40600 | #define CGTT_SC_CLK_CTRL1__PBB_CLK_STALL_OVERRIDE__SHIFT 0x16 |
40601 | #define CGTT_SC_CLK_CTRL1__PBB_WARP_CLK_STALL_OVERRIDE__SHIFT 0x17 |
40602 | #define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_OVERRIDE0__SHIFT 0x18 |
40603 | #define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_OVERRIDE__SHIFT 0x19 |
40604 | #define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_OVERRIDE__SHIFT 0x1a |
40605 | #define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_OVERRIDE__SHIFT 0x1b |
40606 | #define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_OVERRIDE__SHIFT 0x1c |
40607 | #define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_OVERRIDE__SHIFT 0x1d |
40608 | #define CGTT_SC_CLK_CTRL1__PBB_CLK_OVERRIDE__SHIFT 0x1e |
40609 | #define CGTT_SC_CLK_CTRL1__PBB_WARP_CLK_OVERRIDE__SHIFT 0x1f |
40610 | #define CGTT_SC_CLK_CTRL1__ON_DELAY_MASK 0x0000000FL |
40611 | #define CGTT_SC_CLK_CTRL1__OFF_HYSTERESIS_MASK 0x00000FF0L |
40612 | #define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_STALL_OVERRIDE0_MASK 0x00010000L |
40613 | #define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_STALL_OVERRIDE_MASK 0x00020000L |
40614 | #define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_STALL_OVERRIDE_MASK 0x00040000L |
40615 | #define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_STALL_OVERRIDE_MASK 0x00080000L |
40616 | #define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_STALL_OVERRIDE_MASK 0x00100000L |
40617 | #define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_STALL_OVERRIDE_MASK 0x00200000L |
40618 | #define CGTT_SC_CLK_CTRL1__PBB_CLK_STALL_OVERRIDE_MASK 0x00400000L |
40619 | #define CGTT_SC_CLK_CTRL1__PBB_WARP_CLK_STALL_OVERRIDE_MASK 0x00800000L |
40620 | #define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_OVERRIDE0_MASK 0x01000000L |
40621 | #define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_OVERRIDE_MASK 0x02000000L |
40622 | #define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_OVERRIDE_MASK 0x04000000L |
40623 | #define CGTT_SC_CLK_CTRL1__OTHER_SPECIAL_SC_REG_CLK_OVERRIDE_MASK 0x08000000L |
40624 | #define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_OVERRIDE_MASK 0x10000000L |
40625 | #define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_OVERRIDE_MASK 0x20000000L |
40626 | #define CGTT_SC_CLK_CTRL1__PBB_CLK_OVERRIDE_MASK 0x40000000L |
40627 | #define CGTT_SC_CLK_CTRL1__PBB_WARP_CLK_OVERRIDE_MASK 0x80000000L |
40628 | //CGTT_SC_CLK_CTRL2 |
40629 | #define CGTT_SC_CLK_CTRL2__ON_DELAY__SHIFT 0x0 |
40630 | #define CGTT_SC_CLK_CTRL2__OFF_HYSTERESIS__SHIFT 0x4 |
40631 | #define CGTT_SC_CLK_CTRL2__DISABLE_DEBUG_BUS_FLOP_EN_ON_PERFMON__SHIFT 0xf |
40632 | #define CGTT_SC_CLK_CTRL2__SCF_SCB_VRS_INTF_CLK_OVERRIDE__SHIFT 0x10 |
40633 | #define CGTT_SC_CLK_CTRL2__SC_DB_COURSE_MGCG_BUSY_ENABLE__SHIFT 0x11 |
40634 | #define CGTT_SC_CLK_CTRL2__SC_DB_STAGE_IN_TP_PFFB_WR_OVERRIDE__SHIFT 0x12 |
40635 | #define CGTT_SC_CLK_CTRL2__SC_DB_QUADMASK_OVERRIDE__SHIFT 0x13 |
40636 | #define CGTT_SC_CLK_CTRL2__SC_DB_QUADMASK_Z_OVERRIDE__SHIFT 0x14 |
40637 | #define CGTT_SC_CLK_CTRL2__SC_DB_QUAD_PROC_OVERRIDE__SHIFT 0x15 |
40638 | #define CGTT_SC_CLK_CTRL2__SC_DB_QUAD_ACCUM_OVERRIDE__SHIFT 0x16 |
40639 | #define CGTT_SC_CLK_CTRL2__SC_DB_PFFB_RP_OVERRIDE__SHIFT 0x17 |
40640 | #define CGTT_SC_CLK_CTRL2__SC_DB_PKR_OVERRIDE__SHIFT 0x18 |
40641 | #define CGTT_SC_CLK_CTRL2__SC_DB_SC_FREE_WAVE_CLK_OVERRIDE__SHIFT 0x19 |
40642 | #define CGTT_SC_CLK_CTRL2__SC_DB_SC_WAVE_2_SC_SPI_WAVE_CLK_OVERRIDE__SHIFT 0x1a |
40643 | #define CGTT_SC_CLK_CTRL2__SCF_SCB_INTF_CLK_OVERRIDE__SHIFT 0x1b |
40644 | #define CGTT_SC_CLK_CTRL2__SC_PKR_INTF_CLK_OVERRIDE__SHIFT 0x1c |
40645 | #define CGTT_SC_CLK_CTRL2__SC_DB_INTF_CLK_OVERRIDE__SHIFT 0x1d |
40646 | #define CGTT_SC_CLK_CTRL2__PA_SC_INTF_CLK_OVERRIDE__SHIFT 0x1e |
40647 | #define CGTT_SC_CLK_CTRL2__ON_DELAY_MASK 0x0000000FL |
40648 | #define CGTT_SC_CLK_CTRL2__OFF_HYSTERESIS_MASK 0x00000FF0L |
40649 | #define CGTT_SC_CLK_CTRL2__DISABLE_DEBUG_BUS_FLOP_EN_ON_PERFMON_MASK 0x00008000L |
40650 | #define CGTT_SC_CLK_CTRL2__SCF_SCB_VRS_INTF_CLK_OVERRIDE_MASK 0x00010000L |
40651 | #define CGTT_SC_CLK_CTRL2__SC_DB_COURSE_MGCG_BUSY_ENABLE_MASK 0x00020000L |
40652 | #define CGTT_SC_CLK_CTRL2__SC_DB_STAGE_IN_TP_PFFB_WR_OVERRIDE_MASK 0x00040000L |
40653 | #define CGTT_SC_CLK_CTRL2__SC_DB_QUADMASK_OVERRIDE_MASK 0x00080000L |
40654 | #define CGTT_SC_CLK_CTRL2__SC_DB_QUADMASK_Z_OVERRIDE_MASK 0x00100000L |
40655 | #define CGTT_SC_CLK_CTRL2__SC_DB_QUAD_PROC_OVERRIDE_MASK 0x00200000L |
40656 | #define CGTT_SC_CLK_CTRL2__SC_DB_QUAD_ACCUM_OVERRIDE_MASK 0x00400000L |
40657 | #define CGTT_SC_CLK_CTRL2__SC_DB_PFFB_RP_OVERRIDE_MASK 0x00800000L |
40658 | #define CGTT_SC_CLK_CTRL2__SC_DB_PKR_OVERRIDE_MASK 0x01000000L |
40659 | #define CGTT_SC_CLK_CTRL2__SC_DB_SC_FREE_WAVE_CLK_OVERRIDE_MASK 0x02000000L |
40660 | #define CGTT_SC_CLK_CTRL2__SC_DB_SC_WAVE_2_SC_SPI_WAVE_CLK_OVERRIDE_MASK 0x04000000L |
40661 | #define CGTT_SC_CLK_CTRL2__SCF_SCB_INTF_CLK_OVERRIDE_MASK 0x08000000L |
40662 | #define CGTT_SC_CLK_CTRL2__SC_PKR_INTF_CLK_OVERRIDE_MASK 0x10000000L |
40663 | #define CGTT_SC_CLK_CTRL2__SC_DB_INTF_CLK_OVERRIDE_MASK 0x20000000L |
40664 | #define CGTT_SC_CLK_CTRL2__PA_SC_INTF_CLK_OVERRIDE_MASK 0x40000000L |
40665 | //CGTT_SQG_CLK_CTRL |
40666 | #define CGTT_SQG_CLK_CTRL__ON_DELAY__SHIFT 0x0 |
40667 | #define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
40668 | #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 |
40669 | #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
40670 | #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
40671 | #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
40672 | #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
40673 | #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
40674 | #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
40675 | #define CGTT_SQG_CLK_CTRL__FORCE_GL1H_CLKEN__SHIFT 0x17 |
40676 | #define CGTT_SQG_CLK_CTRL__FORCE_EXPALLOC_FGCG__SHIFT 0x18 |
40677 | #define CGTT_SQG_CLK_CTRL__FORCE_EXPGRANT_FGCG__SHIFT 0x19 |
40678 | #define CGTT_SQG_CLK_CTRL__FORCE_EXPREQ_FGCG__SHIFT 0x1a |
40679 | #define CGTT_SQG_CLK_CTRL__FORCE_CMD_FGCG__SHIFT 0x1b |
40680 | #define CGTT_SQG_CLK_CTRL__TTRACE_OVERRIDE__SHIFT 0x1c |
40681 | #define CGTT_SQG_CLK_CTRL__PERFMON_OVERRIDE__SHIFT 0x1d |
40682 | #define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e |
40683 | #define CGTT_SQG_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f |
40684 | #define CGTT_SQG_CLK_CTRL__ON_DELAY_MASK 0x0000000FL |
40685 | #define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
40686 | #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L |
40687 | #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
40688 | #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
40689 | #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
40690 | #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
40691 | #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
40692 | #define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
40693 | #define CGTT_SQG_CLK_CTRL__FORCE_GL1H_CLKEN_MASK 0x00800000L |
40694 | #define CGTT_SQG_CLK_CTRL__FORCE_EXPALLOC_FGCG_MASK 0x01000000L |
40695 | #define CGTT_SQG_CLK_CTRL__FORCE_EXPGRANT_FGCG_MASK 0x02000000L |
40696 | #define CGTT_SQG_CLK_CTRL__FORCE_EXPREQ_FGCG_MASK 0x04000000L |
40697 | #define CGTT_SQG_CLK_CTRL__FORCE_CMD_FGCG_MASK 0x08000000L |
40698 | #define CGTT_SQG_CLK_CTRL__TTRACE_OVERRIDE_MASK 0x10000000L |
40699 | #define CGTT_SQG_CLK_CTRL__PERFMON_OVERRIDE_MASK 0x20000000L |
40700 | #define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000L |
40701 | #define CGTT_SQG_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L |
40702 | //SQ_ALU_CLK_CTRL |
40703 | #define SQ_ALU_CLK_CTRL__FORCE_WGP_ON_SA0__SHIFT 0x0 |
40704 | #define SQ_ALU_CLK_CTRL__FORCE_WGP_ON_SA1__SHIFT 0x10 |
40705 | #define SQ_ALU_CLK_CTRL__FORCE_WGP_ON_SA0_MASK 0x0000FFFFL |
40706 | #define SQ_ALU_CLK_CTRL__FORCE_WGP_ON_SA1_MASK 0xFFFF0000L |
40707 | //SQ_TEX_CLK_CTRL |
40708 | #define SQ_TEX_CLK_CTRL__FORCE_WGP_ON_SA0__SHIFT 0x0 |
40709 | #define SQ_TEX_CLK_CTRL__FORCE_WGP_ON_SA1__SHIFT 0x10 |
40710 | #define SQ_TEX_CLK_CTRL__FORCE_WGP_ON_SA0_MASK 0x0000FFFFL |
40711 | #define SQ_TEX_CLK_CTRL__FORCE_WGP_ON_SA1_MASK 0xFFFF0000L |
40712 | //SQ_LDS_CLK_CTRL |
40713 | #define SQ_LDS_CLK_CTRL__FORCE_WGP_ON_SA0__SHIFT 0x0 |
40714 | #define SQ_LDS_CLK_CTRL__FORCE_WGP_ON_SA1__SHIFT 0x10 |
40715 | #define SQ_LDS_CLK_CTRL__FORCE_WGP_ON_SA0_MASK 0x0000FFFFL |
40716 | #define SQ_LDS_CLK_CTRL__FORCE_WGP_ON_SA1_MASK 0xFFFF0000L |
40717 | //ICG_SP_CLK_CTRL |
40718 | #define ICG_SP_CLK_CTRL__CLK_OVERRIDE__SHIFT 0x0 |
40719 | #define ICG_SP_CLK_CTRL__CLK_OVERRIDE_MASK 0xFFFFFFFFL |
40720 | //TA_CGTT_CTRL |
40721 | #define TA_CGTT_CTRL__ON_DELAY__SHIFT 0x0 |
40722 | #define TA_CGTT_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
40723 | #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 |
40724 | #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
40725 | #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
40726 | #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
40727 | #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
40728 | #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
40729 | #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
40730 | #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 |
40731 | #define TA_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 |
40732 | #define TA_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 |
40733 | #define TA_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a |
40734 | #define TA_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b |
40735 | #define TA_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c |
40736 | #define TA_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d |
40737 | #define TA_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e |
40738 | #define TA_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f |
40739 | #define TA_CGTT_CTRL__ON_DELAY_MASK 0x0000000FL |
40740 | #define TA_CGTT_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
40741 | #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L |
40742 | #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
40743 | #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
40744 | #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
40745 | #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
40746 | #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
40747 | #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
40748 | #define TA_CGTT_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L |
40749 | #define TA_CGTT_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L |
40750 | #define TA_CGTT_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L |
40751 | #define TA_CGTT_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L |
40752 | #define TA_CGTT_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L |
40753 | #define TA_CGTT_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L |
40754 | #define TA_CGTT_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L |
40755 | #define TA_CGTT_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L |
40756 | #define TA_CGTT_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L |
40757 | //DB_CGTT_CLK_CTRL_0 |
40758 | #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0__SHIFT 0x0 |
40759 | #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1__SHIFT 0x1 |
40760 | #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2__SHIFT 0x2 |
40761 | #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3__SHIFT 0x3 |
40762 | #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4__SHIFT 0x4 |
40763 | #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5__SHIFT 0x5 |
40764 | #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6__SHIFT 0x6 |
40765 | #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7__SHIFT 0x7 |
40766 | #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE8__SHIFT 0x8 |
40767 | #define DB_CGTT_CLK_CTRL_0__RESERVED__SHIFT 0x9 |
40768 | #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0_MASK 0x00000001L |
40769 | #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1_MASK 0x00000002L |
40770 | #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2_MASK 0x00000004L |
40771 | #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3_MASK 0x00000008L |
40772 | #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4_MASK 0x00000010L |
40773 | #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5_MASK 0x00000020L |
40774 | #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6_MASK 0x00000040L |
40775 | #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7_MASK 0x00000080L |
40776 | #define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE8_MASK 0x00000100L |
40777 | #define DB_CGTT_CLK_CTRL_0__RESERVED_MASK 0xFFFFFE00L |
40778 | //CB_CGTT_SCLK_CTRL |
40779 | #define CB_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0 |
40780 | #define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
40781 | #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 |
40782 | #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
40783 | #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
40784 | #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
40785 | #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
40786 | #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
40787 | #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
40788 | #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 |
40789 | #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 |
40790 | #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 |
40791 | #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a |
40792 | #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b |
40793 | #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c |
40794 | #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d |
40795 | #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e |
40796 | #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f |
40797 | #define CB_CGTT_SCLK_CTRL__ON_DELAY_MASK 0x0000000FL |
40798 | #define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
40799 | #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L |
40800 | #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
40801 | #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
40802 | #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
40803 | #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
40804 | #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
40805 | #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
40806 | #define CB_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L |
40807 | #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L |
40808 | #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L |
40809 | #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L |
40810 | #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L |
40811 | #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L |
40812 | #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L |
40813 | #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L |
40814 | #define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L |
40815 | //GFX_ICG_GL2A_CTRL |
40816 | #define GFX_ICG_GL2A_CTRL__REG_OVERRIDE__SHIFT 0x0 |
40817 | #define GFX_ICG_GL2A_CTRL__PERFMON_OVERRIDE__SHIFT 0x1 |
40818 | #define GFX_ICG_GL2A_CTRL__CROSSBAR_OVERRIDE__SHIFT 0x2 |
40819 | #define GFX_ICG_GL2A_CTRL__RTN_ARB_OVERRIDE__SHIFT 0x3 |
40820 | #define GFX_ICG_GL2A_CTRL__GCRD_OVERRIDE__SHIFT 0x4 |
40821 | #define GFX_ICG_GL2A_CTRL__CLIENT0_OVERRIDE__SHIFT 0x8 |
40822 | #define GFX_ICG_GL2A_CTRL__CLIENT1_OVERRIDE__SHIFT 0x9 |
40823 | #define GFX_ICG_GL2A_CTRL__CLIENT2_OVERRIDE__SHIFT 0xa |
40824 | #define GFX_ICG_GL2A_CTRL__CLIENT3_OVERRIDE__SHIFT 0xb |
40825 | #define GFX_ICG_GL2A_CTRL__CLIENT4_OVERRIDE__SHIFT 0xc |
40826 | #define GFX_ICG_GL2A_CTRL__CLIENT5_OVERRIDE__SHIFT 0xd |
40827 | #define GFX_ICG_GL2A_CTRL__CLIENT6_OVERRIDE__SHIFT 0xe |
40828 | #define GFX_ICG_GL2A_CTRL__CLIENT7_OVERRIDE__SHIFT 0xf |
40829 | #define GFX_ICG_GL2A_CTRL__CLIENT8_OVERRIDE__SHIFT 0x10 |
40830 | #define GFX_ICG_GL2A_CTRL__CLIENT9_OVERRIDE__SHIFT 0x11 |
40831 | #define GFX_ICG_GL2A_CTRL__CLIENT10_OVERRIDE__SHIFT 0x12 |
40832 | #define GFX_ICG_GL2A_CTRL__CLIENT11_OVERRIDE__SHIFT 0x13 |
40833 | #define GFX_ICG_GL2A_CTRL__CLIENT12_OVERRIDE__SHIFT 0x14 |
40834 | #define GFX_ICG_GL2A_CTRL__CLIENT13_OVERRIDE__SHIFT 0x15 |
40835 | #define GFX_ICG_GL2A_CTRL__CLIENT14_OVERRIDE__SHIFT 0x16 |
40836 | #define GFX_ICG_GL2A_CTRL__CLIENT15_OVERRIDE__SHIFT 0x17 |
40837 | #define GFX_ICG_GL2A_CTRL__REG_OVERRIDE_MASK 0x00000001L |
40838 | #define GFX_ICG_GL2A_CTRL__PERFMON_OVERRIDE_MASK 0x00000002L |
40839 | #define GFX_ICG_GL2A_CTRL__CROSSBAR_OVERRIDE_MASK 0x00000004L |
40840 | #define GFX_ICG_GL2A_CTRL__RTN_ARB_OVERRIDE_MASK 0x00000008L |
40841 | #define GFX_ICG_GL2A_CTRL__GCRD_OVERRIDE_MASK 0x00000010L |
40842 | #define GFX_ICG_GL2A_CTRL__CLIENT0_OVERRIDE_MASK 0x00000100L |
40843 | #define GFX_ICG_GL2A_CTRL__CLIENT1_OVERRIDE_MASK 0x00000200L |
40844 | #define GFX_ICG_GL2A_CTRL__CLIENT2_OVERRIDE_MASK 0x00000400L |
40845 | #define GFX_ICG_GL2A_CTRL__CLIENT3_OVERRIDE_MASK 0x00000800L |
40846 | #define GFX_ICG_GL2A_CTRL__CLIENT4_OVERRIDE_MASK 0x00001000L |
40847 | #define GFX_ICG_GL2A_CTRL__CLIENT5_OVERRIDE_MASK 0x00002000L |
40848 | #define GFX_ICG_GL2A_CTRL__CLIENT6_OVERRIDE_MASK 0x00004000L |
40849 | #define GFX_ICG_GL2A_CTRL__CLIENT7_OVERRIDE_MASK 0x00008000L |
40850 | #define GFX_ICG_GL2A_CTRL__CLIENT8_OVERRIDE_MASK 0x00010000L |
40851 | #define GFX_ICG_GL2A_CTRL__CLIENT9_OVERRIDE_MASK 0x00020000L |
40852 | #define GFX_ICG_GL2A_CTRL__CLIENT10_OVERRIDE_MASK 0x00040000L |
40853 | #define GFX_ICG_GL2A_CTRL__CLIENT11_OVERRIDE_MASK 0x00080000L |
40854 | #define GFX_ICG_GL2A_CTRL__CLIENT12_OVERRIDE_MASK 0x00100000L |
40855 | #define GFX_ICG_GL2A_CTRL__CLIENT13_OVERRIDE_MASK 0x00200000L |
40856 | #define GFX_ICG_GL2A_CTRL__CLIENT14_OVERRIDE_MASK 0x00400000L |
40857 | #define GFX_ICG_GL2A_CTRL__CLIENT15_OVERRIDE_MASK 0x00800000L |
40858 | //CGTT_CP_CLK_CTRL |
40859 | #define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
40860 | #define CGTT_CP_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf |
40861 | #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 |
40862 | #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
40863 | #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
40864 | #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
40865 | #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
40866 | #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
40867 | #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
40868 | #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 |
40869 | #define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d |
40870 | #define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e |
40871 | #define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f |
40872 | #define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
40873 | #define CGTT_CP_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L |
40874 | #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L |
40875 | #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
40876 | #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
40877 | #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
40878 | #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
40879 | #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
40880 | #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
40881 | #define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L |
40882 | #define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000L |
40883 | #define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L |
40884 | #define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L |
40885 | //CGTT_CPF_CLK_CTRL |
40886 | #define CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
40887 | #define CGTT_CPF_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf |
40888 | #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 |
40889 | #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
40890 | #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
40891 | #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
40892 | #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
40893 | #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
40894 | #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
40895 | #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 |
40896 | #define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1a |
40897 | #define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PRT__SHIFT 0x1b |
40898 | #define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_CMP__SHIFT 0x1c |
40899 | #define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_GFX__SHIFT 0x1d |
40900 | #define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e |
40901 | #define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f |
40902 | #define CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
40903 | #define CGTT_CPF_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L |
40904 | #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L |
40905 | #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
40906 | #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
40907 | #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
40908 | #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
40909 | #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
40910 | #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
40911 | #define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L |
40912 | #define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x04000000L |
40913 | #define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PRT_MASK 0x08000000L |
40914 | #define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_CMP_MASK 0x10000000L |
40915 | #define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_GFX_MASK 0x20000000L |
40916 | #define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L |
40917 | #define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L |
40918 | //CGTT_CPC_CLK_CTRL |
40919 | #define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 |
40920 | #define CGTT_CPC_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf |
40921 | #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 |
40922 | #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 |
40923 | #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 |
40924 | #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 |
40925 | #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 |
40926 | #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 |
40927 | #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 |
40928 | #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 |
40929 | #define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d |
40930 | #define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e |
40931 | #define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f |
40932 | #define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L |
40933 | #define CGTT_CPC_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L |
40934 | #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L |
40935 | #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L |
40936 | #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L |
40937 | #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L |
40938 | #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L |
40939 | #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L |
40940 | #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L |
40941 | #define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L |
40942 | #define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000L |
40943 | #define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L |
40944 | #define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L |
40945 | //CGTT_RLC_CLK_CTRL |
40946 | #define CGTT_RLC_CLK_CTRL__RESERVED__SHIFT 0x0 |
40947 | #define CGTT_RLC_CLK_CTRL__RESERVED_MASK 0xFFFFFFFFL |
40948 | //CGTT_SC_CLK_CTRL3 |
40949 | #define CGTT_SC_CLK_CTRL3__PBB_WARPBINROWWARP_CLK_STALL_OVERRIDE__SHIFT 0x0 |
40950 | #define CGTT_SC_CLK_CTRL3__PBB_WARPBINWARP_CLK_STALL_OVERRIDE__SHIFT 0x1 |
40951 | #define CGTT_SC_CLK_CTRL3__PBB_WARPFBWBINWARP_CLK_STALL_OVERRIDE__SHIFT 0x2 |
40952 | #define CGTT_SC_CLK_CTRL3__PBB_WARPHSPANUNWARP_CLK_STALL_OVERRIDE__SHIFT 0x3 |
40953 | #define CGTT_SC_CLK_CTRL3__PBB_WARPSCISSORUNWARP_CLK_STALL_OVERRIDE__SHIFT 0x4 |
40954 | #define CGTT_SC_CLK_CTRL3__PBB_FBWBACK_CLK_STALL_OVERRIDE__SHIFT 0x5 |
40955 | #define CGTT_SC_CLK_CTRL3__PBB_FBWBACKREPEATER_CLK_STALL_OVERRIDE__SHIFT 0x6 |
40956 | #define CGTT_SC_CLK_CTRL3__PBB_FBWFRONT_CLK_STALL_OVERRIDE__SHIFT 0x7 |
40957 | #define CGTT_SC_CLK_CTRL3__PBB_FBWFRONTREPEATER_CLK_STALL_OVERRIDE__SHIFT 0x8 |
40958 | #define CGTT_SC_CLK_CTRL3__PBB_FBWSCALER_CLK_STALL_OVERRIDE__SHIFT 0x9 |
40959 | #define CGTT_SC_CLK_CTRL3__PBB_FRONT_CLK_STALL_OVERRIDE__SHIFT 0xa |
40960 | #define CGTT_SC_CLK_CTRL3__PBB_BATCHIN_CLK_STALL_OVERRIDE__SHIFT 0xb |
40961 | #define CGTT_SC_CLK_CTRL3__PBB_VRASTER_CLK_STALL_OVERRIDE__SHIFT 0xc |
40962 | #define CGTT_SC_CLK_CTRL3__PBB_VGATHER_CLK_STALL_OVERRIDE__SHIFT 0xd |
40963 | #define CGTT_SC_CLK_CTRL3__PBB_WARPBINROWWARP_CLK_OVERRIDE__SHIFT 0x12 |
40964 | #define CGTT_SC_CLK_CTRL3__PBB_WARPBINWARP_CLK_OVERRIDE__SHIFT 0x13 |
40965 | #define CGTT_SC_CLK_CTRL3__PBB_WARPFBWBINWARP_CLK_OVERRIDE__SHIFT 0x14 |
40966 | #define CGTT_SC_CLK_CTRL3__PBB_WARPHSPANUNWARP_CLK_OVERRIDE__SHIFT 0x15 |
40967 | #define CGTT_SC_CLK_CTRL3__PBB_WARPSCISSORUNWARP_CLK_OVERRIDE__SHIFT 0x16 |
40968 | #define CGTT_SC_CLK_CTRL3__PBB_FBWBACK_CLK_OVERRIDE__SHIFT 0x17 |
40969 | #define CGTT_SC_CLK_CTRL3__PBB_FBWBACKREPEATER_CLK_OVERRIDE__SHIFT 0x18 |
40970 | #define CGTT_SC_CLK_CTRL3__PBB_FBWFRONT_CLK_OVERRIDE__SHIFT 0x19 |
40971 | #define CGTT_SC_CLK_CTRL3__PBB_FBWFRONTREPEATER_CLK_OVERRIDE__SHIFT 0x1a |
40972 | #define CGTT_SC_CLK_CTRL3__PBB_FBWSCALER_CLK_OVERRIDE__SHIFT 0x1b |
40973 | #define CGTT_SC_CLK_CTRL3__PBB_FRONT_CLK_OVERRIDE__SHIFT 0x1c |
40974 | #define CGTT_SC_CLK_CTRL3__PBB_BATCHIN_CLK_OVERRIDE__SHIFT 0x1d |
40975 | #define CGTT_SC_CLK_CTRL3__PBB_VRASTER_CLK_OVERRIDE__SHIFT 0x1e |
40976 | #define CGTT_SC_CLK_CTRL3__PBB_VGATHER_CLK_OVERRIDE__SHIFT 0x1f |
40977 | #define CGTT_SC_CLK_CTRL3__PBB_WARPBINROWWARP_CLK_STALL_OVERRIDE_MASK 0x00000001L |
40978 | #define CGTT_SC_CLK_CTRL3__PBB_WARPBINWARP_CLK_STALL_OVERRIDE_MASK 0x00000002L |
40979 | #define CGTT_SC_CLK_CTRL3__PBB_WARPFBWBINWARP_CLK_STALL_OVERRIDE_MASK 0x00000004L |
40980 | #define CGTT_SC_CLK_CTRL3__PBB_WARPHSPANUNWARP_CLK_STALL_OVERRIDE_MASK 0x00000008L |
40981 | #define CGTT_SC_CLK_CTRL3__PBB_WARPSCISSORUNWARP_CLK_STALL_OVERRIDE_MASK 0x00000010L |
40982 | #define CGTT_SC_CLK_CTRL3__PBB_FBWBACK_CLK_STALL_OVERRIDE_MASK 0x00000020L |
40983 | #define CGTT_SC_CLK_CTRL3__PBB_FBWBACKREPEATER_CLK_STALL_OVERRIDE_MASK 0x00000040L |
40984 | #define CGTT_SC_CLK_CTRL3__PBB_FBWFRONT_CLK_STALL_OVERRIDE_MASK 0x00000080L |
40985 | #define CGTT_SC_CLK_CTRL3__PBB_FBWFRONTREPEATER_CLK_STALL_OVERRIDE_MASK 0x00000100L |
40986 | #define CGTT_SC_CLK_CTRL3__PBB_FBWSCALER_CLK_STALL_OVERRIDE_MASK 0x00000200L |
40987 | #define CGTT_SC_CLK_CTRL3__PBB_FRONT_CLK_STALL_OVERRIDE_MASK 0x00000400L |
40988 | #define CGTT_SC_CLK_CTRL3__PBB_BATCHIN_CLK_STALL_OVERRIDE_MASK 0x00000800L |
40989 | #define CGTT_SC_CLK_CTRL3__PBB_VRASTER_CLK_STALL_OVERRIDE_MASK 0x00001000L |
40990 | #define CGTT_SC_CLK_CTRL3__PBB_VGATHER_CLK_STALL_OVERRIDE_MASK 0x00002000L |
40991 | #define CGTT_SC_CLK_CTRL3__PBB_WARPBINROWWARP_CLK_OVERRIDE_MASK 0x00040000L |
40992 | #define CGTT_SC_CLK_CTRL3__PBB_WARPBINWARP_CLK_OVERRIDE_MASK 0x00080000L |
40993 | #define CGTT_SC_CLK_CTRL3__PBB_WARPFBWBINWARP_CLK_OVERRIDE_MASK 0x00100000L |
40994 | #define CGTT_SC_CLK_CTRL3__PBB_WARPHSPANUNWARP_CLK_OVERRIDE_MASK 0x00200000L |
40995 | #define CGTT_SC_CLK_CTRL3__PBB_WARPSCISSORUNWARP_CLK_OVERRIDE_MASK 0x00400000L |
40996 | #define CGTT_SC_CLK_CTRL3__PBB_FBWBACK_CLK_OVERRIDE_MASK 0x00800000L |
40997 | #define CGTT_SC_CLK_CTRL3__PBB_FBWBACKREPEATER_CLK_OVERRIDE_MASK 0x01000000L |
40998 | #define CGTT_SC_CLK_CTRL3__PBB_FBWFRONT_CLK_OVERRIDE_MASK 0x02000000L |
40999 | #define CGTT_SC_CLK_CTRL3__PBB_FBWFRONTREPEATER_CLK_OVERRIDE_MASK 0x04000000L |
41000 | #define CGTT_SC_CLK_CTRL3__PBB_FBWSCALER_CLK_OVERRIDE_MASK 0x08000000L |
41001 | #define CGTT_SC_CLK_CTRL3__PBB_FRONT_CLK_OVERRIDE_MASK 0x10000000L |
41002 | #define CGTT_SC_CLK_CTRL3__PBB_BATCHIN_CLK_OVERRIDE_MASK 0x20000000L |
41003 | #define CGTT_SC_CLK_CTRL3__PBB_VRASTER_CLK_OVERRIDE_MASK 0x40000000L |
41004 | #define CGTT_SC_CLK_CTRL3__PBB_VGATHER_CLK_OVERRIDE_MASK 0x80000000L |
41005 | //CGTT_SC_CLK_CTRL4 |
41006 | #define CGTT_SC_CLK_CTRL4__PBB_VCOARSE_CLK_STALL_OVERRIDE__SHIFT 0x0 |
41007 | #define CGTT_SC_CLK_CTRL4__PBB_VDETAIL_CLK_STALL_OVERRIDE__SHIFT 0x1 |
41008 | #define CGTT_SC_CLK_CTRL4__PBB_HRASTER_CLK_STALL_OVERRIDE__SHIFT 0x2 |
41009 | #define CGTT_SC_CLK_CTRL4__PBB_HCONFIG_CLK_STALL_OVERRIDE__SHIFT 0x3 |
41010 | #define CGTT_SC_CLK_CTRL4__PBB_HGATHER_CLK_STALL_OVERRIDE__SHIFT 0x4 |
41011 | #define CGTT_SC_CLK_CTRL4__PBB_HCOARSE_CLK_STALL_OVERRIDE__SHIFT 0x5 |
41012 | #define CGTT_SC_CLK_CTRL4__PBB_HDETAIL_CLK_STALL_OVERRIDE__SHIFT 0x6 |
41013 | #define CGTT_SC_CLK_CTRL4__PBB_HREPEAT_CLK_STALL_OVERRIDE__SHIFT 0x7 |
41014 | #define CGTT_SC_CLK_CTRL4__PBB_BATCHOUT_CLK_STALL_OVERRIDE__SHIFT 0x8 |
41015 | #define CGTT_SC_CLK_CTRL4__PBB_OUTPUT_CLK_STALL_OVERRIDE__SHIFT 0x9 |
41016 | #define CGTT_SC_CLK_CTRL4__PBB_OUTMUX_CLK_STALL_OVERRIDE__SHIFT 0xa |
41017 | #define CGTT_SC_CLK_CTRL4__PBB_BATCHINFO_CLK_STALL_OVERRIDE__SHIFT 0xb |
41018 | #define CGTT_SC_CLK_CTRL4__PBB_EVENTINFO_CLK_STALL_OVERRIDE__SHIFT 0xc |
41019 | #define CGTT_SC_CLK_CTRL4__PBB_VCOARSE_CLK_OVERRIDE__SHIFT 0x13 |
41020 | #define CGTT_SC_CLK_CTRL4__PBB_VDETAIL_CLK_OVERRIDE__SHIFT 0x14 |
41021 | #define CGTT_SC_CLK_CTRL4__PBB_HRASTER_CLK_OVERRIDE__SHIFT 0x15 |
41022 | #define CGTT_SC_CLK_CTRL4__PBB_HCONFIG_CLK_OVERRIDE__SHIFT 0x16 |
41023 | #define CGTT_SC_CLK_CTRL4__PBB_HGATHER_CLK_OVERRIDE__SHIFT 0x17 |
41024 | #define CGTT_SC_CLK_CTRL4__PBB_HCOARSE_CLK_OVERRIDE__SHIFT 0x18 |
41025 | #define CGTT_SC_CLK_CTRL4__PBB_HDETAIL_CLK_OVERRIDE__SHIFT 0x19 |
41026 | #define CGTT_SC_CLK_CTRL4__PBB_HREPEAT_CLK_OVERRIDE__SHIFT 0x1a |
41027 | #define CGTT_SC_CLK_CTRL4__PBB_BATCHOUT_CLK_OVERRIDE__SHIFT 0x1b |
41028 | #define CGTT_SC_CLK_CTRL4__PBB_OUTPUT_CLK_OVERRIDE__SHIFT 0x1c |
41029 | #define CGTT_SC_CLK_CTRL4__PBB_OUTMUX_CLK_OVERRIDE__SHIFT 0x1d |
41030 | #define CGTT_SC_CLK_CTRL4__PBB_BATCHINFO_CLK_OVERRIDE__SHIFT 0x1e |
41031 | #define CGTT_SC_CLK_CTRL4__PBB_EVENTINFO_CLK_OVERRIDE__SHIFT 0x1f |
41032 | #define CGTT_SC_CLK_CTRL4__PBB_VCOARSE_CLK_STALL_OVERRIDE_MASK 0x00000001L |
41033 | #define CGTT_SC_CLK_CTRL4__PBB_VDETAIL_CLK_STALL_OVERRIDE_MASK 0x00000002L |
41034 | #define CGTT_SC_CLK_CTRL4__PBB_HRASTER_CLK_STALL_OVERRIDE_MASK 0x00000004L |
41035 | #define CGTT_SC_CLK_CTRL4__PBB_HCONFIG_CLK_STALL_OVERRIDE_MASK 0x00000008L |
41036 | #define CGTT_SC_CLK_CTRL4__PBB_HGATHER_CLK_STALL_OVERRIDE_MASK 0x00000010L |
41037 | #define CGTT_SC_CLK_CTRL4__PBB_HCOARSE_CLK_STALL_OVERRIDE_MASK 0x00000020L |
41038 | #define CGTT_SC_CLK_CTRL4__PBB_HDETAIL_CLK_STALL_OVERRIDE_MASK 0x00000040L |
41039 | #define CGTT_SC_CLK_CTRL4__PBB_HREPEAT_CLK_STALL_OVERRIDE_MASK 0x00000080L |
41040 | #define CGTT_SC_CLK_CTRL4__PBB_BATCHOUT_CLK_STALL_OVERRIDE_MASK 0x00000100L |
41041 | #define CGTT_SC_CLK_CTRL4__PBB_OUTPUT_CLK_STALL_OVERRIDE_MASK 0x00000200L |
41042 | #define CGTT_SC_CLK_CTRL4__PBB_OUTMUX_CLK_STALL_OVERRIDE_MASK 0x00000400L |
41043 | #define CGTT_SC_CLK_CTRL4__PBB_BATCHINFO_CLK_STALL_OVERRIDE_MASK 0x00000800L |
41044 | #define CGTT_SC_CLK_CTRL4__PBB_EVENTINFO_CLK_STALL_OVERRIDE_MASK 0x00001000L |
41045 | #define CGTT_SC_CLK_CTRL4__PBB_VCOARSE_CLK_OVERRIDE_MASK 0x00080000L |
41046 | #define CGTT_SC_CLK_CTRL4__PBB_VDETAIL_CLK_OVERRIDE_MASK 0x00100000L |
41047 | #define CGTT_SC_CLK_CTRL4__PBB_HRASTER_CLK_OVERRIDE_MASK 0x00200000L |
41048 | #define CGTT_SC_CLK_CTRL4__PBB_HCONFIG_CLK_OVERRIDE_MASK 0x00400000L |
41049 | #define CGTT_SC_CLK_CTRL4__PBB_HGATHER_CLK_OVERRIDE_MASK 0x00800000L |
41050 | #define CGTT_SC_CLK_CTRL4__PBB_HCOARSE_CLK_OVERRIDE_MASK 0x01000000L |
41051 | #define CGTT_SC_CLK_CTRL4__PBB_HDETAIL_CLK_OVERRIDE_MASK 0x02000000L |
41052 | #define CGTT_SC_CLK_CTRL4__PBB_HREPEAT_CLK_OVERRIDE_MASK 0x04000000L |
41053 | #define CGTT_SC_CLK_CTRL4__PBB_BATCHOUT_CLK_OVERRIDE_MASK 0x08000000L |
41054 | #define CGTT_SC_CLK_CTRL4__PBB_OUTPUT_CLK_OVERRIDE_MASK 0x10000000L |
41055 | #define CGTT_SC_CLK_CTRL4__PBB_OUTMUX_CLK_OVERRIDE_MASK 0x20000000L |
41056 | #define CGTT_SC_CLK_CTRL4__PBB_BATCHINFO_CLK_OVERRIDE_MASK 0x40000000L |
41057 | #define CGTT_SC_CLK_CTRL4__PBB_EVENTINFO_CLK_OVERRIDE_MASK 0x80000000L |
41058 | //GCEA_ICG_CTRL |
41059 | #define GCEA_ICG_CTRL__SOFT_OVERRIDE_RETURN__SHIFT 0x0 |
41060 | #define GCEA_ICG_CTRL__SOFT_OVERRIDE_READ__SHIFT 0x1 |
41061 | #define GCEA_ICG_CTRL__SOFT_OVERRIDE_WRITE__SHIFT 0x2 |
41062 | #define GCEA_ICG_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT 0x3 |
41063 | #define GCEA_ICG_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x4 |
41064 | #define GCEA_ICG_CTRL__SOFT_OVERRIDE_MAM__SHIFT 0x5 |
41065 | #define GCEA_ICG_CTRL__SOFT_OVERRIDE_RETURN_MASK 0x00000001L |
41066 | #define GCEA_ICG_CTRL__SOFT_OVERRIDE_READ_MASK 0x00000002L |
41067 | #define GCEA_ICG_CTRL__SOFT_OVERRIDE_WRITE_MASK 0x00000004L |
41068 | #define GCEA_ICG_CTRL__SOFT_OVERRIDE_REGISTER_MASK 0x00000008L |
41069 | #define GCEA_ICG_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x00000010L |
41070 | #define GCEA_ICG_CTRL__SOFT_OVERRIDE_MAM_MASK 0x00000020L |
41071 | //GL1I_GL1R_MGCG_OVERRIDE |
41072 | #define GL1I_GL1R_MGCG_OVERRIDE__GL1A_GL1IR_MGCG_SCLK_OVERRIDE__SHIFT 0x0 |
41073 | #define GL1I_GL1R_MGCG_OVERRIDE__GL1A_GL1IR_MGCG_RET_DCLK_OVERRIDE__SHIFT 0x1 |
41074 | #define GL1I_GL1R_MGCG_OVERRIDE__GL1A_GL1IW_MGCG_SCLK_OVERRIDE__SHIFT 0x2 |
41075 | #define GL1I_GL1R_MGCG_OVERRIDE__GL1A_GL1IW_MGCG_RET_DCLK_OVERRIDE__SHIFT 0x3 |
41076 | #define GL1I_GL1R_MGCG_OVERRIDE__GL1A_GL1IW_MGCG_SRC_DCLK_OVERRIDE__SHIFT 0x4 |
41077 | #define GL1I_GL1R_MGCG_OVERRIDE__GL1A_GL1R_SRC_MGCG_SCLK_OVERRIDE__SHIFT 0x5 |
41078 | #define GL1I_GL1R_MGCG_OVERRIDE__GL1A_GL1R_RET_MGCG_SCLK_OVERRIDE__SHIFT 0x6 |
41079 | #define GL1I_GL1R_MGCG_OVERRIDE__GL1A_GL1IR_MGCG_SCLK_OVERRIDE_MASK 0x00000001L |
41080 | #define GL1I_GL1R_MGCG_OVERRIDE__GL1A_GL1IR_MGCG_RET_DCLK_OVERRIDE_MASK 0x00000002L |
41081 | #define GL1I_GL1R_MGCG_OVERRIDE__GL1A_GL1IW_MGCG_SCLK_OVERRIDE_MASK 0x00000004L |
41082 | #define GL1I_GL1R_MGCG_OVERRIDE__GL1A_GL1IW_MGCG_RET_DCLK_OVERRIDE_MASK 0x00000008L |
41083 | #define GL1I_GL1R_MGCG_OVERRIDE__GL1A_GL1IW_MGCG_SRC_DCLK_OVERRIDE_MASK 0x00000010L |
41084 | #define GL1I_GL1R_MGCG_OVERRIDE__GL1A_GL1R_SRC_MGCG_SCLK_OVERRIDE_MASK 0x00000020L |
41085 | #define GL1I_GL1R_MGCG_OVERRIDE__GL1A_GL1R_RET_MGCG_SCLK_OVERRIDE_MASK 0x00000040L |
41086 | //GL1H_ICG_CTRL |
41087 | #define GL1H_ICG_CTRL__REG_DCLK_OVERRIDE__SHIFT 0x0 |
41088 | #define GL1H_ICG_CTRL__REQ_ARB_DCLK_OVERRIDE__SHIFT 0x1 |
41089 | #define GL1H_ICG_CTRL__PERFMON_DCLK_OVERRIDE__SHIFT 0x2 |
41090 | #define GL1H_ICG_CTRL__REQ_ARB_CLI0_DCLK_OVERRIDE__SHIFT 0x3 |
41091 | #define GL1H_ICG_CTRL__REQ_ARB_CLI1_DCLK_OVERRIDE__SHIFT 0x4 |
41092 | #define GL1H_ICG_CTRL__REQ_ARB_CLI2_DCLK_OVERRIDE__SHIFT 0x5 |
41093 | #define GL1H_ICG_CTRL__REQ_ARB_CLI3_DCLK_OVERRIDE__SHIFT 0x6 |
41094 | #define GL1H_ICG_CTRL__SRC_DCLK_OVERRIDE__SHIFT 0x7 |
41095 | #define GL1H_ICG_CTRL__RET_DCLK_OVERRIDE__SHIFT 0x8 |
41096 | #define GL1H_ICG_CTRL__REG_DCLK_OVERRIDE_MASK 0x00000001L |
41097 | #define GL1H_ICG_CTRL__REQ_ARB_DCLK_OVERRIDE_MASK 0x00000002L |
41098 | #define GL1H_ICG_CTRL__PERFMON_DCLK_OVERRIDE_MASK 0x00000004L |
41099 | #define GL1H_ICG_CTRL__REQ_ARB_CLI0_DCLK_OVERRIDE_MASK 0x00000008L |
41100 | #define GL1H_ICG_CTRL__REQ_ARB_CLI1_DCLK_OVERRIDE_MASK 0x00000010L |
41101 | #define GL1H_ICG_CTRL__REQ_ARB_CLI2_DCLK_OVERRIDE_MASK 0x00000020L |
41102 | #define GL1H_ICG_CTRL__REQ_ARB_CLI3_DCLK_OVERRIDE_MASK 0x00000040L |
41103 | #define GL1H_ICG_CTRL__SRC_DCLK_OVERRIDE_MASK 0x00000080L |
41104 | #define GL1H_ICG_CTRL__RET_DCLK_OVERRIDE_MASK 0x00000100L |
41105 | //CHI_CHR_MGCG_OVERRIDE |
41106 | #define CHI_CHR_MGCG_OVERRIDE__CHA_CHIR_MGCG_SCLK_OVERRIDE__SHIFT 0x0 |
41107 | #define CHI_CHR_MGCG_OVERRIDE__CHA_CHIR_MGCG_RET_DCLK_OVERRIDE__SHIFT 0x1 |
41108 | #define CHI_CHR_MGCG_OVERRIDE__CHA_CHIW_MGCG_SCLK_OVERRIDE__SHIFT 0x2 |
41109 | #define CHI_CHR_MGCG_OVERRIDE__CHA_CHIW_MGCG_RET_DCLK_OVERRIDE__SHIFT 0x3 |
41110 | #define CHI_CHR_MGCG_OVERRIDE__CHA_CHIW_MGCG_SRC_DCLK_OVERRIDE__SHIFT 0x4 |
41111 | #define CHI_CHR_MGCG_OVERRIDE__CHA_CHR_RET_MGCG_SCLK_OVERRIDE__SHIFT 0x5 |
41112 | #define CHI_CHR_MGCG_OVERRIDE__CHA_CHR_SRC_MGCG_SCLK_OVERRIDE__SHIFT 0x6 |
41113 | #define CHI_CHR_MGCG_OVERRIDE__CHA_CHIR_MGCG_SCLK_OVERRIDE_MASK 0x00000001L |
41114 | #define CHI_CHR_MGCG_OVERRIDE__CHA_CHIR_MGCG_RET_DCLK_OVERRIDE_MASK 0x00000002L |
41115 | #define CHI_CHR_MGCG_OVERRIDE__CHA_CHIW_MGCG_SCLK_OVERRIDE_MASK 0x00000004L |
41116 | #define CHI_CHR_MGCG_OVERRIDE__CHA_CHIW_MGCG_RET_DCLK_OVERRIDE_MASK 0x00000008L |
41117 | #define CHI_CHR_MGCG_OVERRIDE__CHA_CHIW_MGCG_SRC_DCLK_OVERRIDE_MASK 0x00000010L |
41118 | #define CHI_CHR_MGCG_OVERRIDE__CHA_CHR_RET_MGCG_SCLK_OVERRIDE_MASK 0x00000020L |
41119 | #define CHI_CHR_MGCG_OVERRIDE__CHA_CHR_SRC_MGCG_SCLK_OVERRIDE_MASK 0x00000040L |
41120 | //ICG_GL1C_CLK_CTRL |
41121 | #define ICG_GL1C_CLK_CTRL__GLOBAL_CLK_OVERRIDE__SHIFT 0x0 |
41122 | #define ICG_GL1C_CLK_CTRL__GLOBAL_NONHARVESTABLE_CLK_OVERRIDE__SHIFT 0x1 |
41123 | #define ICG_GL1C_CLK_CTRL__REQUEST_CLK_OVERRIDE__SHIFT 0x2 |
41124 | #define ICG_GL1C_CLK_CTRL__VM_CLK_OVERRIDE__SHIFT 0x3 |
41125 | #define ICG_GL1C_CLK_CTRL__TAG_CLK_OVERRIDE__SHIFT 0x4 |
41126 | #define ICG_GL1C_CLK_CTRL__GCR_CLK_OVERRIDE__SHIFT 0x5 |
41127 | #define ICG_GL1C_CLK_CTRL__SRC_DATA_CLK_OVERRIDE__SHIFT 0x6 |
41128 | #define ICG_GL1C_CLK_CTRL__RETURN_CLK_OVERRIDE__SHIFT 0x7 |
41129 | #define ICG_GL1C_CLK_CTRL__GRBM_CLK_OVERRIDE__SHIFT 0x8 |
41130 | #define ICG_GL1C_CLK_CTRL__PERF_CLK_OVERRIDE__SHIFT 0x9 |
41131 | #define ICG_GL1C_CLK_CTRL__LATENCY_FIFO_CLK_OVERRIDE__SHIFT 0xa |
41132 | #define ICG_GL1C_CLK_CTRL__GLOBAL_CLK_OVERRIDE_MASK 0x00000001L |
41133 | #define ICG_GL1C_CLK_CTRL__GLOBAL_NONHARVESTABLE_CLK_OVERRIDE_MASK 0x00000002L |
41134 | #define ICG_GL1C_CLK_CTRL__REQUEST_CLK_OVERRIDE_MASK 0x00000004L |
41135 | #define ICG_GL1C_CLK_CTRL__VM_CLK_OVERRIDE_MASK 0x00000008L |
41136 | #define ICG_GL1C_CLK_CTRL__TAG_CLK_OVERRIDE_MASK 0x00000010L |
41137 | #define ICG_GL1C_CLK_CTRL__GCR_CLK_OVERRIDE_MASK 0x00000020L |
41138 | #define ICG_GL1C_CLK_CTRL__SRC_DATA_CLK_OVERRIDE_MASK 0x00000040L |
41139 | #define ICG_GL1C_CLK_CTRL__RETURN_CLK_OVERRIDE_MASK 0x00000080L |
41140 | #define ICG_GL1C_CLK_CTRL__GRBM_CLK_OVERRIDE_MASK 0x00000100L |
41141 | #define ICG_GL1C_CLK_CTRL__PERF_CLK_OVERRIDE_MASK 0x00000200L |
41142 | #define ICG_GL1C_CLK_CTRL__LATENCY_FIFO_CLK_OVERRIDE_MASK 0x00000400L |
41143 | //ICG_GL1A_CTRL |
41144 | #define ICG_GL1A_CTRL__REG_CLK_OVERRIDE__SHIFT 0x0 |
41145 | #define ICG_GL1A_CTRL__REQ_CLI_CLK_OVERRIDE__SHIFT 0x1 |
41146 | #define ICG_GL1A_CTRL__REQ_ARB_CLK_OVERRIDE__SHIFT 0x2 |
41147 | #define ICG_GL1A_CTRL__RET_CLK_OVERRIDE__SHIFT 0x3 |
41148 | #define ICG_GL1A_CTRL__REQ_CREDIT_CLK_OVERRIDE__SHIFT 0x4 |
41149 | #define ICG_GL1A_CTRL__PERFMON_CLK_OVERRIDE__SHIFT 0x5 |
41150 | #define ICG_GL1A_CTRL__REG_CLK_OVERRIDE_MASK 0x00000001L |
41151 | #define ICG_GL1A_CTRL__REQ_CLI_CLK_OVERRIDE_MASK 0x00000002L |
41152 | #define ICG_GL1A_CTRL__REQ_ARB_CLK_OVERRIDE_MASK 0x00000004L |
41153 | #define ICG_GL1A_CTRL__RET_CLK_OVERRIDE_MASK 0x00000008L |
41154 | #define ICG_GL1A_CTRL__REQ_CREDIT_CLK_OVERRIDE_MASK 0x00000010L |
41155 | #define ICG_GL1A_CTRL__PERFMON_CLK_OVERRIDE_MASK 0x00000020L |
41156 | //ICG_CHA_CTRL |
41157 | #define ICG_CHA_CTRL__REG_CLK_OVERRIDE__SHIFT 0x0 |
41158 | #define ICG_CHA_CTRL__REQ_CLI_CLK_OVERRIDE__SHIFT 0x1 |
41159 | #define ICG_CHA_CTRL__REQ_ARB_CLK_OVERRIDE__SHIFT 0x2 |
41160 | #define ICG_CHA_CTRL__RET_CLK_OVERRIDE__SHIFT 0x3 |
41161 | #define ICG_CHA_CTRL__REQ_CREDIT_CLK_OVERRIDE__SHIFT 0x4 |
41162 | #define ICG_CHA_CTRL__PERFMON_CLK_OVERRIDE__SHIFT 0x5 |
41163 | #define ICG_CHA_CTRL__REG_CLK_OVERRIDE_MASK 0x00000001L |
41164 | #define ICG_CHA_CTRL__REQ_CLI_CLK_OVERRIDE_MASK 0x00000002L |
41165 | #define ICG_CHA_CTRL__REQ_ARB_CLK_OVERRIDE_MASK 0x00000004L |
41166 | #define ICG_CHA_CTRL__RET_CLK_OVERRIDE_MASK 0x00000008L |
41167 | #define ICG_CHA_CTRL__REQ_CREDIT_CLK_OVERRIDE_MASK 0x00000010L |
41168 | #define ICG_CHA_CTRL__PERFMON_CLK_OVERRIDE_MASK 0x00000020L |
41169 | //GUS_ICG_CTRL |
41170 | #define GUS_ICG_CTRL__SOFT_OVERRIDE_DRAM__SHIFT 0x0 |
41171 | #define GUS_ICG_CTRL__SOFT_OVERRIDE_WRITE__SHIFT 0x1 |
41172 | #define GUS_ICG_CTRL__SOFT_OVERRIDE_READ__SHIFT 0x2 |
41173 | #define GUS_ICG_CTRL__SOFT_OVERRIDE_RETURN_DEMUX__SHIFT 0x3 |
41174 | #define GUS_ICG_CTRL__SOFT_OVERRIDE_RETURN_WRITE__SHIFT 0x4 |
41175 | #define GUS_ICG_CTRL__SOFT_OVERRIDE_RETURN_READ__SHIFT 0x5 |
41176 | #define GUS_ICG_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT 0x6 |
41177 | #define GUS_ICG_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x7 |
41178 | #define GUS_ICG_CTRL__SOFT_OVERRIDE_STATIC__SHIFT 0x8 |
41179 | #define GUS_ICG_CTRL__SPARE1__SHIFT 0x9 |
41180 | #define GUS_ICG_CTRL__SOFT_OVERRIDE_DRAM_MASK 0x00000001L |
41181 | #define GUS_ICG_CTRL__SOFT_OVERRIDE_WRITE_MASK 0x00000002L |
41182 | #define GUS_ICG_CTRL__SOFT_OVERRIDE_READ_MASK 0x00000004L |
41183 | #define GUS_ICG_CTRL__SOFT_OVERRIDE_RETURN_DEMUX_MASK 0x00000008L |
41184 | #define GUS_ICG_CTRL__SOFT_OVERRIDE_RETURN_WRITE_MASK 0x00000010L |
41185 | #define GUS_ICG_CTRL__SOFT_OVERRIDE_RETURN_READ_MASK 0x00000020L |
41186 | #define GUS_ICG_CTRL__SOFT_OVERRIDE_REGISTER_MASK 0x00000040L |
41187 | #define GUS_ICG_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x00000080L |
41188 | #define GUS_ICG_CTRL__SOFT_OVERRIDE_STATIC_MASK 0x00000100L |
41189 | #define GUS_ICG_CTRL__SPARE1_MASK 0x0003FE00L |
41190 | //CGTT_PH_CLK_CTRL0 |
41191 | #define CGTT_PH_CLK_CTRL0__ON_DELAY__SHIFT 0x0 |
41192 | #define CGTT_PH_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4 |
41193 | #define CGTT_PH_CLK_CTRL0__DEBUG_BUS_EN__SHIFT 0x17 |
41194 | #define CGTT_PH_CLK_CTRL0__DISABLE_DEBUG_BUS_FLOP_EN_ON_PERFMON__SHIFT 0x18 |
41195 | #define CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE6__SHIFT 0x19 |
41196 | #define CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE5__SHIFT 0x1a |
41197 | #define CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE4__SHIFT 0x1b |
41198 | #define CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE3__SHIFT 0x1c |
41199 | #define CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT 0x1d |
41200 | #define CGTT_PH_CLK_CTRL0__PERFMON_CLK_OVERRIDE__SHIFT 0x1e |
41201 | #define CGTT_PH_CLK_CTRL0__REG_CLK_OVERRIDE__SHIFT 0x1f |
41202 | #define CGTT_PH_CLK_CTRL0__ON_DELAY_MASK 0x0000000FL |
41203 | #define CGTT_PH_CLK_CTRL0__OFF_HYSTERESIS_MASK 0x00000FF0L |
41204 | #define CGTT_PH_CLK_CTRL0__DEBUG_BUS_EN_MASK 0x00800000L |
41205 | #define CGTT_PH_CLK_CTRL0__DISABLE_DEBUG_BUS_FLOP_EN_ON_PERFMON_MASK 0x01000000L |
41206 | #define CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE6_MASK 0x02000000L |
41207 | #define CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE5_MASK 0x04000000L |
41208 | #define CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE4_MASK 0x08000000L |
41209 | #define CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE3_MASK 0x10000000L |
41210 | #define CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE2_MASK 0x20000000L |
41211 | #define CGTT_PH_CLK_CTRL0__PERFMON_CLK_OVERRIDE_MASK 0x40000000L |
41212 | #define CGTT_PH_CLK_CTRL0__REG_CLK_OVERRIDE_MASK 0x80000000L |
41213 | //CGTT_PH_CLK_CTRL1 |
41214 | #define CGTT_PH_CLK_CTRL1__ON_DELAY__SHIFT 0x0 |
41215 | #define CGTT_PH_CLK_CTRL1__OFF_HYSTERESIS__SHIFT 0x4 |
41216 | #define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE7__SHIFT 0x18 |
41217 | #define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE6__SHIFT 0x19 |
41218 | #define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE5__SHIFT 0x1a |
41219 | #define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE4__SHIFT 0x1b |
41220 | #define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE3__SHIFT 0x1c |
41221 | #define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE2__SHIFT 0x1d |
41222 | #define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE1__SHIFT 0x1e |
41223 | #define CGTT_PH_CLK_CTRL1__ON_DELAY_MASK 0x0000000FL |
41224 | #define CGTT_PH_CLK_CTRL1__OFF_HYSTERESIS_MASK 0x00000FF0L |
41225 | #define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE7_MASK 0x01000000L |
41226 | #define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE6_MASK 0x02000000L |
41227 | #define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE5_MASK 0x04000000L |
41228 | #define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE4_MASK 0x08000000L |
41229 | #define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE3_MASK 0x10000000L |
41230 | #define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE2_MASK 0x20000000L |
41231 | #define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE1_MASK 0x40000000L |
41232 | //CGTT_PH_CLK_CTRL2 |
41233 | #define CGTT_PH_CLK_CTRL2__ON_DELAY__SHIFT 0x0 |
41234 | #define CGTT_PH_CLK_CTRL2__OFF_HYSTERESIS__SHIFT 0x4 |
41235 | #define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE7__SHIFT 0x18 |
41236 | #define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE6__SHIFT 0x19 |
41237 | #define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE5__SHIFT 0x1a |
41238 | #define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE4__SHIFT 0x1b |
41239 | #define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE3__SHIFT 0x1c |
41240 | #define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE2__SHIFT 0x1d |
41241 | #define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE1__SHIFT 0x1e |
41242 | #define CGTT_PH_CLK_CTRL2__ON_DELAY_MASK 0x0000000FL |
41243 | #define CGTT_PH_CLK_CTRL2__OFF_HYSTERESIS_MASK 0x00000FF0L |
41244 | #define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE7_MASK 0x01000000L |
41245 | #define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE6_MASK 0x02000000L |
41246 | #define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE5_MASK 0x04000000L |
41247 | #define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE4_MASK 0x08000000L |
41248 | #define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE3_MASK 0x10000000L |
41249 | #define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE2_MASK 0x20000000L |
41250 | #define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE1_MASK 0x40000000L |
41251 | //CGTT_PH_CLK_CTRL3 |
41252 | #define CGTT_PH_CLK_CTRL3__ON_DELAY__SHIFT 0x0 |
41253 | #define CGTT_PH_CLK_CTRL3__OFF_HYSTERESIS__SHIFT 0x4 |
41254 | #define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE7__SHIFT 0x18 |
41255 | #define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE6__SHIFT 0x19 |
41256 | #define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE5__SHIFT 0x1a |
41257 | #define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE4__SHIFT 0x1b |
41258 | #define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE3__SHIFT 0x1c |
41259 | #define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE2__SHIFT 0x1d |
41260 | #define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE1__SHIFT 0x1e |
41261 | #define CGTT_PH_CLK_CTRL3__ON_DELAY_MASK 0x0000000FL |
41262 | #define CGTT_PH_CLK_CTRL3__OFF_HYSTERESIS_MASK 0x00000FF0L |
41263 | #define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE7_MASK 0x01000000L |
41264 | #define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE6_MASK 0x02000000L |
41265 | #define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE5_MASK 0x04000000L |
41266 | #define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE4_MASK 0x08000000L |
41267 | #define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE3_MASK 0x10000000L |
41268 | #define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE2_MASK 0x20000000L |
41269 | #define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE1_MASK 0x40000000L |
41270 | //GFX_ICG_GL2C_CTRL |
41271 | #define GFX_ICG_GL2C_CTRL__REG_OVERRIDE__SHIFT 0x0 |
41272 | #define GFX_ICG_GL2C_CTRL__PERFMON_OVERRIDE__SHIFT 0x1 |
41273 | #define GFX_ICG_GL2C_CTRL__IB_OVERRIDE__SHIFT 0x2 |
41274 | #define GFX_ICG_GL2C_CTRL__TAG_OVERRIDE__SHIFT 0x3 |
41275 | #define GFX_ICG_GL2C_CTRL__CM_CORE_OVERRIDE__SHIFT 0x4 |
41276 | #define GFX_ICG_GL2C_CTRL__CORE_OVERRIDE__SHIFT 0x5 |
41277 | #define GFX_ICG_GL2C_CTRL__CACHE_RAM_OVERRIDE__SHIFT 0x6 |
41278 | #define GFX_ICG_GL2C_CTRL__GCR_OVERRIDE__SHIFT 0x7 |
41279 | #define GFX_ICG_GL2C_CTRL__EXECUTE_OVERRIDE__SHIFT 0x8 |
41280 | #define GFX_ICG_GL2C_CTRL__RETURN_BUFFER_OVERRIDE__SHIFT 0x9 |
41281 | #define GFX_ICG_GL2C_CTRL__LATENCY_FIFO_OVERRIDE__SHIFT 0xa |
41282 | #define GFX_ICG_GL2C_CTRL__OUTPUT_FIFOS_OVERRIDE__SHIFT 0xb |
41283 | #define GFX_ICG_GL2C_CTRL__MC_WRITE_OVERRIDE__SHIFT 0xc |
41284 | #define GFX_ICG_GL2C_CTRL__EXECUTE_DECOMP_OVERRIDE__SHIFT 0xd |
41285 | #define GFX_ICG_GL2C_CTRL__EXECUTE_WRITE_OVERRIDE__SHIFT 0xe |
41286 | #define GFX_ICG_GL2C_CTRL__TAG_FLOPSET_GROUP0_OVERRIDE__SHIFT 0xf |
41287 | #define GFX_ICG_GL2C_CTRL__TAG_FLOPSET_GROUP1_OVERRIDE__SHIFT 0x10 |
41288 | #define GFX_ICG_GL2C_CTRL__TAG_FLOPSET_GROUP2_OVERRIDE__SHIFT 0x11 |
41289 | #define GFX_ICG_GL2C_CTRL__TAG_FLOPSET_GROUP3_OVERRIDE__SHIFT 0x12 |
41290 | #define GFX_ICG_GL2C_CTRL__CM_RVF_OVERRIDE__SHIFT 0x14 |
41291 | #define GFX_ICG_GL2C_CTRL__CM_SDR_OVERRIDE__SHIFT 0x15 |
41292 | #define GFX_ICG_GL2C_CTRL__CM_RPF_OVERRIDE__SHIFT 0x16 |
41293 | #define GFX_ICG_GL2C_CTRL__CM_STS_OVERRIDE__SHIFT 0x17 |
41294 | #define GFX_ICG_GL2C_CTRL__CM_READ_OVERRIDE__SHIFT 0x18 |
41295 | #define GFX_ICG_GL2C_CTRL__CM_MERGE_OVERRIDE__SHIFT 0x19 |
41296 | #define GFX_ICG_GL2C_CTRL__CM_COMP_OVERRIDE__SHIFT 0x1a |
41297 | #define GFX_ICG_GL2C_CTRL__CM_DCC_OVERRIDE__SHIFT 0x1b |
41298 | #define GFX_ICG_GL2C_CTRL__CM_WRITE_OVERRIDE__SHIFT 0x1c |
41299 | #define GFX_ICG_GL2C_CTRL__CM_NOOP_OVERRIDE__SHIFT 0x1d |
41300 | #define GFX_ICG_GL2C_CTRL__MDC_TAG_OVERRIDE__SHIFT 0x1e |
41301 | #define GFX_ICG_GL2C_CTRL__MDC_DATA_OVERRIDE__SHIFT 0x1f |
41302 | #define GFX_ICG_GL2C_CTRL__REG_OVERRIDE_MASK 0x00000001L |
41303 | #define GFX_ICG_GL2C_CTRL__PERFMON_OVERRIDE_MASK 0x00000002L |
41304 | #define GFX_ICG_GL2C_CTRL__IB_OVERRIDE_MASK 0x00000004L |
41305 | #define GFX_ICG_GL2C_CTRL__TAG_OVERRIDE_MASK 0x00000008L |
41306 | #define GFX_ICG_GL2C_CTRL__CM_CORE_OVERRIDE_MASK 0x00000010L |
41307 | #define GFX_ICG_GL2C_CTRL__CORE_OVERRIDE_MASK 0x00000020L |
41308 | #define GFX_ICG_GL2C_CTRL__CACHE_RAM_OVERRIDE_MASK 0x00000040L |
41309 | #define GFX_ICG_GL2C_CTRL__GCR_OVERRIDE_MASK 0x00000080L |
41310 | #define GFX_ICG_GL2C_CTRL__EXECUTE_OVERRIDE_MASK 0x00000100L |
41311 | #define GFX_ICG_GL2C_CTRL__RETURN_BUFFER_OVERRIDE_MASK 0x00000200L |
41312 | #define GFX_ICG_GL2C_CTRL__LATENCY_FIFO_OVERRIDE_MASK 0x00000400L |
41313 | #define GFX_ICG_GL2C_CTRL__OUTPUT_FIFOS_OVERRIDE_MASK 0x00000800L |
41314 | #define GFX_ICG_GL2C_CTRL__MC_WRITE_OVERRIDE_MASK 0x00001000L |
41315 | #define GFX_ICG_GL2C_CTRL__EXECUTE_DECOMP_OVERRIDE_MASK 0x00002000L |
41316 | #define GFX_ICG_GL2C_CTRL__EXECUTE_WRITE_OVERRIDE_MASK 0x00004000L |
41317 | #define GFX_ICG_GL2C_CTRL__TAG_FLOPSET_GROUP0_OVERRIDE_MASK 0x00008000L |
41318 | #define GFX_ICG_GL2C_CTRL__TAG_FLOPSET_GROUP1_OVERRIDE_MASK 0x00010000L |
41319 | #define GFX_ICG_GL2C_CTRL__TAG_FLOPSET_GROUP2_OVERRIDE_MASK 0x00020000L |
41320 | #define GFX_ICG_GL2C_CTRL__TAG_FLOPSET_GROUP3_OVERRIDE_MASK 0x00040000L |
41321 | #define GFX_ICG_GL2C_CTRL__CM_RVF_OVERRIDE_MASK 0x00100000L |
41322 | #define GFX_ICG_GL2C_CTRL__CM_SDR_OVERRIDE_MASK 0x00200000L |
41323 | #define GFX_ICG_GL2C_CTRL__CM_RPF_OVERRIDE_MASK 0x00400000L |
41324 | #define GFX_ICG_GL2C_CTRL__CM_STS_OVERRIDE_MASK 0x00800000L |
41325 | #define GFX_ICG_GL2C_CTRL__CM_READ_OVERRIDE_MASK 0x01000000L |
41326 | #define GFX_ICG_GL2C_CTRL__CM_MERGE_OVERRIDE_MASK 0x02000000L |
41327 | #define GFX_ICG_GL2C_CTRL__CM_COMP_OVERRIDE_MASK 0x04000000L |
41328 | #define GFX_ICG_GL2C_CTRL__CM_DCC_OVERRIDE_MASK 0x08000000L |
41329 | #define GFX_ICG_GL2C_CTRL__CM_WRITE_OVERRIDE_MASK 0x10000000L |
41330 | #define GFX_ICG_GL2C_CTRL__CM_NOOP_OVERRIDE_MASK 0x20000000L |
41331 | #define GFX_ICG_GL2C_CTRL__MDC_TAG_OVERRIDE_MASK 0x40000000L |
41332 | #define GFX_ICG_GL2C_CTRL__MDC_DATA_OVERRIDE_MASK 0x80000000L |
41333 | //GFX_ICG_GL2C_CTRL1 |
41334 | #define GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT0_OVERRIDE__SHIFT 0x0 |
41335 | #define GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT1_OVERRIDE__SHIFT 0x1 |
41336 | #define GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT2_OVERRIDE__SHIFT 0x2 |
41337 | #define GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT3_OVERRIDE__SHIFT 0x3 |
41338 | #define GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT4_OVERRIDE__SHIFT 0x4 |
41339 | #define GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT5_OVERRIDE__SHIFT 0x5 |
41340 | #define GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT6_OVERRIDE__SHIFT 0x6 |
41341 | #define GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT7_OVERRIDE__SHIFT 0x7 |
41342 | #define GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT8_OVERRIDE__SHIFT 0x8 |
41343 | #define GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT9_OVERRIDE__SHIFT 0x9 |
41344 | #define GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT10_OVERRIDE__SHIFT 0xa |
41345 | #define GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT11_OVERRIDE__SHIFT 0xb |
41346 | #define GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT12_OVERRIDE__SHIFT 0xc |
41347 | #define GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT13_OVERRIDE__SHIFT 0xd |
41348 | #define GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT14_OVERRIDE__SHIFT 0xe |
41349 | #define GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT15_OVERRIDE__SHIFT 0xf |
41350 | #define GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT16_OVERRIDE__SHIFT 0x10 |
41351 | #define GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT17_OVERRIDE__SHIFT 0x11 |
41352 | #define GFX_ICG_GL2C_CTRL1__TAG_PROBE_OVERRIDE__SHIFT 0x18 |
41353 | #define GFX_ICG_GL2C_CTRL1__DCC_UPPER_OVERRIDE__SHIFT 0x19 |
41354 | #define GFX_ICG_GL2C_CTRL1__DCC_LOWER_OVERRIDE__SHIFT 0x1a |
41355 | #define GFX_ICG_GL2C_CTRL1__ZD_UPPER_OVERRIDE__SHIFT 0x1b |
41356 | #define GFX_ICG_GL2C_CTRL1__ZD_LOWER_OVERRIDE__SHIFT 0x1c |
41357 | #define GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT0_OVERRIDE_MASK 0x00000001L |
41358 | #define GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT1_OVERRIDE_MASK 0x00000002L |
41359 | #define GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT2_OVERRIDE_MASK 0x00000004L |
41360 | #define GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT3_OVERRIDE_MASK 0x00000008L |
41361 | #define GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT4_OVERRIDE_MASK 0x00000010L |
41362 | #define GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT5_OVERRIDE_MASK 0x00000020L |
41363 | #define GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT6_OVERRIDE_MASK 0x00000040L |
41364 | #define GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT7_OVERRIDE_MASK 0x00000080L |
41365 | #define GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT8_OVERRIDE_MASK 0x00000100L |
41366 | #define GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT9_OVERRIDE_MASK 0x00000200L |
41367 | #define GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT10_OVERRIDE_MASK 0x00000400L |
41368 | #define GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT11_OVERRIDE_MASK 0x00000800L |
41369 | #define GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT12_OVERRIDE_MASK 0x00001000L |
41370 | #define GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT13_OVERRIDE_MASK 0x00002000L |
41371 | #define GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT14_OVERRIDE_MASK 0x00004000L |
41372 | #define GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT15_OVERRIDE_MASK 0x00008000L |
41373 | #define GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT16_OVERRIDE_MASK 0x00010000L |
41374 | #define GFX_ICG_GL2C_CTRL1__OUTPUT_FIFOS_INTERNAL_CLIENT17_OVERRIDE_MASK 0x00020000L |
41375 | #define GFX_ICG_GL2C_CTRL1__TAG_PROBE_OVERRIDE_MASK 0x01000000L |
41376 | #define GFX_ICG_GL2C_CTRL1__DCC_UPPER_OVERRIDE_MASK 0x02000000L |
41377 | #define GFX_ICG_GL2C_CTRL1__DCC_LOWER_OVERRIDE_MASK 0x04000000L |
41378 | #define GFX_ICG_GL2C_CTRL1__ZD_UPPER_OVERRIDE_MASK 0x08000000L |
41379 | #define GFX_ICG_GL2C_CTRL1__ZD_LOWER_OVERRIDE_MASK 0x10000000L |
41380 | //ICG_LDS_CLK_CTRL |
41381 | #define ICG_LDS_CLK_CTRL__LDS_DLOAD0_OVERRIDE__SHIFT 0x0 |
41382 | #define ICG_LDS_CLK_CTRL__LDS_DLOAD1_OVERRIDE__SHIFT 0x1 |
41383 | #define ICG_LDS_CLK_CTRL__LDS_WGP_ARB_OVERRIDE__SHIFT 0x2 |
41384 | #define ICG_LDS_CLK_CTRL__LDS_TD_OVERRIDE__SHIFT 0x3 |
41385 | #define ICG_LDS_CLK_CTRL__LDS_ATTR_WR_OVERRIDE__SHIFT 0x4 |
41386 | #define ICG_LDS_CLK_CTRL__LDS_CONFIG_REG_OVERRIDE__SHIFT 0x5 |
41387 | #define ICG_LDS_CLK_CTRL__LDS_IDX_PIPE_OVERRIDE__SHIFT 0x6 |
41388 | #define ICG_LDS_CLK_CTRL__LDS_IDX_DIR_OVERRIDE__SHIFT 0x7 |
41389 | #define ICG_LDS_CLK_CTRL__LDS_IDX_WR_OVERRIDE__SHIFT 0x8 |
41390 | #define ICG_LDS_CLK_CTRL__LDS_IDX_INPUT_QUEUE_OVERRIDE__SHIFT 0x9 |
41391 | #define ICG_LDS_CLK_CTRL__LDS_MEM_OVERRIDE__SHIFT 0xa |
41392 | #define ICG_LDS_CLK_CTRL__LDS_IDX_OUTPUT_ALIGNER_OVERRIDE__SHIFT 0xb |
41393 | #define ICG_LDS_CLK_CTRL__LDS_DIR_OUTPUT_ALIGNER_OVERRIDE__SHIFT 0xc |
41394 | #define ICG_LDS_CLK_CTRL__LDS_IDX_BANK_CONFLICT_OVERRIDE__SHIFT 0xd |
41395 | #define ICG_LDS_CLK_CTRL__LDS_IDX_SCHED_INPUT_OVERRIDE__SHIFT 0xe |
41396 | #define ICG_LDS_CLK_CTRL__LDS_IDX_SCHED_OUTPUT_OVERRIDE__SHIFT 0xf |
41397 | #define ICG_LDS_CLK_CTRL__LDS_IDX_SCHED_PIPE_OVERRIDE__SHIFT 0x10 |
41398 | #define ICG_LDS_CLK_CTRL__LDS_IDX_SCHEDULER_OVERRIDE__SHIFT 0x11 |
41399 | #define ICG_LDS_CLK_CTRL__LDS_IDX_RDRTN_OVERRIDE__SHIFT 0x12 |
41400 | #define ICG_LDS_CLK_CTRL__LDS_SP_DONE_OVERRIDE__SHIFT 0x13 |
41401 | #define ICG_LDS_CLK_CTRL__LDS_SQC_PERF_OVERRIDE__SHIFT 0x14 |
41402 | #define ICG_LDS_CLK_CTRL__LDS_SP_READ_OVERRIDE__SHIFT 0x15 |
41403 | #define ICG_LDS_CLK_CTRL__SQ_LDS_VMEMCMD_OVERRIDE__SHIFT 0x16 |
41404 | #define ICG_LDS_CLK_CTRL__SP_LDS_VMEMREQ_OVERRIDE__SHIFT 0x17 |
41405 | #define ICG_LDS_CLK_CTRL__SPI_LDS_STALL_OVERRIDE__SHIFT 0x18 |
41406 | #define ICG_LDS_CLK_CTRL__MEM_WR_OVERRIDE__SHIFT 0x19 |
41407 | #define ICG_LDS_CLK_CTRL__LDS_CLK_OVERRIDE_UNUSED__SHIFT 0x1a |
41408 | #define ICG_LDS_CLK_CTRL__LDS_DLOAD0_OVERRIDE_MASK 0x00000001L |
41409 | #define ICG_LDS_CLK_CTRL__LDS_DLOAD1_OVERRIDE_MASK 0x00000002L |
41410 | #define ICG_LDS_CLK_CTRL__LDS_WGP_ARB_OVERRIDE_MASK 0x00000004L |
41411 | #define ICG_LDS_CLK_CTRL__LDS_TD_OVERRIDE_MASK 0x00000008L |
41412 | #define ICG_LDS_CLK_CTRL__LDS_ATTR_WR_OVERRIDE_MASK 0x00000010L |
41413 | #define ICG_LDS_CLK_CTRL__LDS_CONFIG_REG_OVERRIDE_MASK 0x00000020L |
41414 | #define ICG_LDS_CLK_CTRL__LDS_IDX_PIPE_OVERRIDE_MASK 0x00000040L |
41415 | #define ICG_LDS_CLK_CTRL__LDS_IDX_DIR_OVERRIDE_MASK 0x00000080L |
41416 | #define ICG_LDS_CLK_CTRL__LDS_IDX_WR_OVERRIDE_MASK 0x00000100L |
41417 | #define ICG_LDS_CLK_CTRL__LDS_IDX_INPUT_QUEUE_OVERRIDE_MASK 0x00000200L |
41418 | #define ICG_LDS_CLK_CTRL__LDS_MEM_OVERRIDE_MASK 0x00000400L |
41419 | #define ICG_LDS_CLK_CTRL__LDS_IDX_OUTPUT_ALIGNER_OVERRIDE_MASK 0x00000800L |
41420 | #define ICG_LDS_CLK_CTRL__LDS_DIR_OUTPUT_ALIGNER_OVERRIDE_MASK 0x00001000L |
41421 | #define ICG_LDS_CLK_CTRL__LDS_IDX_BANK_CONFLICT_OVERRIDE_MASK 0x00002000L |
41422 | #define ICG_LDS_CLK_CTRL__LDS_IDX_SCHED_INPUT_OVERRIDE_MASK 0x00004000L |
41423 | #define ICG_LDS_CLK_CTRL__LDS_IDX_SCHED_OUTPUT_OVERRIDE_MASK 0x00008000L |
41424 | #define ICG_LDS_CLK_CTRL__LDS_IDX_SCHED_PIPE_OVERRIDE_MASK 0x00010000L |
41425 | #define ICG_LDS_CLK_CTRL__LDS_IDX_SCHEDULER_OVERRIDE_MASK 0x00020000L |
41426 | #define ICG_LDS_CLK_CTRL__LDS_IDX_RDRTN_OVERRIDE_MASK 0x00040000L |
41427 | #define ICG_LDS_CLK_CTRL__LDS_SP_DONE_OVERRIDE_MASK 0x00080000L |
41428 | #define ICG_LDS_CLK_CTRL__LDS_SQC_PERF_OVERRIDE_MASK 0x00100000L |
41429 | #define ICG_LDS_CLK_CTRL__LDS_SP_READ_OVERRIDE_MASK 0x00200000L |
41430 | #define ICG_LDS_CLK_CTRL__SQ_LDS_VMEMCMD_OVERRIDE_MASK 0x00400000L |
41431 | #define ICG_LDS_CLK_CTRL__SP_LDS_VMEMREQ_OVERRIDE_MASK 0x00800000L |
41432 | #define ICG_LDS_CLK_CTRL__SPI_LDS_STALL_OVERRIDE_MASK 0x01000000L |
41433 | #define ICG_LDS_CLK_CTRL__MEM_WR_OVERRIDE_MASK 0x02000000L |
41434 | #define ICG_LDS_CLK_CTRL__LDS_CLK_OVERRIDE_UNUSED_MASK 0xFC000000L |
41435 | //GFX_ICG_UTCL1_CTRL |
41436 | #define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE0__SHIFT 0x0 |
41437 | #define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE1__SHIFT 0x1 |
41438 | #define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE2__SHIFT 0x2 |
41439 | #define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE3__SHIFT 0x3 |
41440 | #define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE4__SHIFT 0x4 |
41441 | #define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE5__SHIFT 0x5 |
41442 | #define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE6__SHIFT 0x6 |
41443 | #define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE7__SHIFT 0x7 |
41444 | #define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE8__SHIFT 0x8 |
41445 | #define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE9__SHIFT 0x9 |
41446 | #define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE10__SHIFT 0xa |
41447 | #define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE11__SHIFT 0xb |
41448 | #define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE12__SHIFT 0xc |
41449 | #define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE13__SHIFT 0xd |
41450 | #define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE14__SHIFT 0xe |
41451 | #define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE15_31__SHIFT 0xf |
41452 | #define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE0_MASK 0x00000001L |
41453 | #define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE1_MASK 0x00000002L |
41454 | #define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE2_MASK 0x00000004L |
41455 | #define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE3_MASK 0x00000008L |
41456 | #define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE4_MASK 0x00000010L |
41457 | #define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE5_MASK 0x00000020L |
41458 | #define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE6_MASK 0x00000040L |
41459 | #define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE7_MASK 0x00000080L |
41460 | #define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE8_MASK 0x00000100L |
41461 | #define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE9_MASK 0x00000200L |
41462 | #define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE10_MASK 0x00000400L |
41463 | #define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE11_MASK 0x00000800L |
41464 | #define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE12_MASK 0x00001000L |
41465 | #define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE13_MASK 0x00002000L |
41466 | #define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE14_MASK 0x00004000L |
41467 | #define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE15_31_MASK 0xFFFF8000L |
41468 | //ICG_CHC_CLK_CTRL |
41469 | #define ICG_CHC_CLK_CTRL__GLOBAL_CLK_OVERRIDE__SHIFT 0x0 |
41470 | #define ICG_CHC_CLK_CTRL__GLOBAL_NONHARVESTABLE_CLK_OVERRIDE__SHIFT 0x1 |
41471 | #define ICG_CHC_CLK_CTRL__REQUEST_CLK_OVERRIDE__SHIFT 0x2 |
41472 | #define ICG_CHC_CLK_CTRL__SRC_DATA_CLK_OVERRIDE__SHIFT 0x3 |
41473 | #define ICG_CHC_CLK_CTRL__RETURN_CLK_OVERRIDE__SHIFT 0x4 |
41474 | #define ICG_CHC_CLK_CTRL__GRBM_CLK_OVERRIDE__SHIFT 0x5 |
41475 | #define ICG_CHC_CLK_CTRL__PERF_CLK_OVERRIDE__SHIFT 0x6 |
41476 | #define ICG_CHC_CLK_CTRL__GLOBAL_CLK_OVERRIDE_MASK 0x00000001L |
41477 | #define ICG_CHC_CLK_CTRL__GLOBAL_NONHARVESTABLE_CLK_OVERRIDE_MASK 0x00000002L |
41478 | #define ICG_CHC_CLK_CTRL__REQUEST_CLK_OVERRIDE_MASK 0x00000004L |
41479 | #define ICG_CHC_CLK_CTRL__SRC_DATA_CLK_OVERRIDE_MASK 0x00000008L |
41480 | #define ICG_CHC_CLK_CTRL__RETURN_CLK_OVERRIDE_MASK 0x00000010L |
41481 | #define ICG_CHC_CLK_CTRL__GRBM_CLK_OVERRIDE_MASK 0x00000020L |
41482 | #define ICG_CHC_CLK_CTRL__PERF_CLK_OVERRIDE_MASK 0x00000040L |
41483 | //ICG_CHCG_CLK_CTRL |
41484 | #define ICG_CHCG_CLK_CTRL__GLOBAL_CLK_OVERRIDE__SHIFT 0x0 |
41485 | #define ICG_CHCG_CLK_CTRL__GLOBAL_NONHARVESTABLE_CLK_OVERRIDE__SHIFT 0x1 |
41486 | #define ICG_CHCG_CLK_CTRL__REQUEST_CLK_OVERRIDE__SHIFT 0x2 |
41487 | #define ICG_CHCG_CLK_CTRL__SRC_DATA_CLK_OVERRIDE__SHIFT 0x3 |
41488 | #define ICG_CHCG_CLK_CTRL__RETURN_CLK_OVERRIDE__SHIFT 0x4 |
41489 | #define ICG_CHCG_CLK_CTRL__GRBM_CLK_OVERRIDE__SHIFT 0x5 |
41490 | #define ICG_CHCG_CLK_CTRL__PERF_CLK_OVERRIDE__SHIFT 0x6 |
41491 | #define ICG_CHCG_CLK_CTRL__GLOBAL_CLK_OVERRIDE_MASK 0x00000001L |
41492 | #define ICG_CHCG_CLK_CTRL__GLOBAL_NONHARVESTABLE_CLK_OVERRIDE_MASK 0x00000002L |
41493 | #define ICG_CHCG_CLK_CTRL__REQUEST_CLK_OVERRIDE_MASK 0x00000004L |
41494 | #define ICG_CHCG_CLK_CTRL__SRC_DATA_CLK_OVERRIDE_MASK 0x00000008L |
41495 | #define ICG_CHCG_CLK_CTRL__RETURN_CLK_OVERRIDE_MASK 0x00000010L |
41496 | #define ICG_CHCG_CLK_CTRL__GRBM_CLK_OVERRIDE_MASK 0x00000020L |
41497 | #define ICG_CHCG_CLK_CTRL__PERF_CLK_OVERRIDE_MASK 0x00000040L |
41498 | |
41499 | |
41500 | // addressBlock: gc_pspdec |
41501 | //CP_MES_DM_INDEX_ADDR |
41502 | #define CP_MES_DM_INDEX_ADDR__ADDR__SHIFT 0x0 |
41503 | #define CP_MES_DM_INDEX_ADDR__ADDR_MASK 0xFFFFFFFFL |
41504 | //CP_MES_DM_INDEX_DATA |
41505 | #define CP_MES_DM_INDEX_DATA__DATA__SHIFT 0x0 |
41506 | #define CP_MES_DM_INDEX_DATA__DATA_MASK 0xFFFFFFFFL |
41507 | //CP_MEC_DM_INDEX_ADDR |
41508 | #define CP_MEC_DM_INDEX_ADDR__ADDR__SHIFT 0x0 |
41509 | #define CP_MEC_DM_INDEX_ADDR__ADDR_MASK 0xFFFFFFFFL |
41510 | //CP_MEC_DM_INDEX_DATA |
41511 | #define CP_MEC_DM_INDEX_DATA__DATA__SHIFT 0x0 |
41512 | #define CP_MEC_DM_INDEX_DATA__DATA_MASK 0xFFFFFFFFL |
41513 | //CP_GFX_RS64_DM_INDEX_ADDR |
41514 | #define CP_GFX_RS64_DM_INDEX_ADDR__ADDR__SHIFT 0x0 |
41515 | #define CP_GFX_RS64_DM_INDEX_ADDR__ADDR_MASK 0xFFFFFFFFL |
41516 | //CP_GFX_RS64_DM_INDEX_DATA |
41517 | #define CP_GFX_RS64_DM_INDEX_DATA__DATA__SHIFT 0x0 |
41518 | #define CP_GFX_RS64_DM_INDEX_DATA__DATA_MASK 0xFFFFFFFFL |
41519 | //CPG_PSP_DEBUG |
41520 | #define CPG_PSP_DEBUG__PRIV_VIOLATION_CNTL__SHIFT 0x0 |
41521 | #define CPG_PSP_DEBUG__VMID_VIOLATION_CNTL__SHIFT 0x2 |
41522 | #define CPG_PSP_DEBUG__GPA_OVERRIDE__SHIFT 0x3 |
41523 | #define CPG_PSP_DEBUG__UCODE_VF_OVERRIDE__SHIFT 0x4 |
41524 | #define CPG_PSP_DEBUG__MTYPE_TMZ_OVERRIDE__SHIFT 0x5 |
41525 | #define CPG_PSP_DEBUG__SECURE_REG_OVERRIDE__SHIFT 0x6 |
41526 | #define CPG_PSP_DEBUG__PRIV_VIOLATION_CNTL_MASK 0x00000003L |
41527 | #define CPG_PSP_DEBUG__VMID_VIOLATION_CNTL_MASK 0x00000004L |
41528 | #define CPG_PSP_DEBUG__GPA_OVERRIDE_MASK 0x00000008L |
41529 | #define CPG_PSP_DEBUG__UCODE_VF_OVERRIDE_MASK 0x00000010L |
41530 | #define CPG_PSP_DEBUG__MTYPE_TMZ_OVERRIDE_MASK 0x00000020L |
41531 | #define CPG_PSP_DEBUG__SECURE_REG_OVERRIDE_MASK 0x00000040L |
41532 | //CPC_PSP_DEBUG |
41533 | #define CPC_PSP_DEBUG__PRIV_VIOLATION_CNTL__SHIFT 0x0 |
41534 | #define CPC_PSP_DEBUG__GPA_OVERRIDE__SHIFT 0x3 |
41535 | #define CPC_PSP_DEBUG__UCODE_VF_OVERRIDE__SHIFT 0x4 |
41536 | #define CPC_PSP_DEBUG__MTYPE_TMZ_OVERRIDE__SHIFT 0x5 |
41537 | #define CPC_PSP_DEBUG__SECURE_REG_OVERRIDE__SHIFT 0x6 |
41538 | #define CPC_PSP_DEBUG__PRIV_VIOLATION_CNTL_MASK 0x00000003L |
41539 | #define CPC_PSP_DEBUG__GPA_OVERRIDE_MASK 0x00000008L |
41540 | #define CPC_PSP_DEBUG__UCODE_VF_OVERRIDE_MASK 0x00000010L |
41541 | #define CPC_PSP_DEBUG__MTYPE_TMZ_OVERRIDE_MASK 0x00000020L |
41542 | #define CPC_PSP_DEBUG__SECURE_REG_OVERRIDE_MASK 0x00000040L |
41543 | //GRBM_IOV_ERROR_FIFO |
41544 | #define GRBM_IOV_ERROR_FIFO__IOV_ADDR__SHIFT 0x0 |
41545 | #define GRBM_IOV_ERROR_FIFO__IOV_VFID__SHIFT 0x12 |
41546 | #define GRBM_IOV_ERROR_FIFO__IOV_SSRCID__SHIFT 0x18 |
41547 | #define GRBM_IOV_ERROR_FIFO__IOV_OP__SHIFT 0x1c |
41548 | #define GRBM_IOV_ERROR_FIFO__IOV_VF__SHIFT 0x1d |
41549 | #define GRBM_IOV_ERROR_FIFO__FIFO_OVERFLOW__SHIFT 0x1e |
41550 | #define GRBM_IOV_ERROR_FIFO__READ_VALID__SHIFT 0x1f |
41551 | #define GRBM_IOV_ERROR_FIFO__IOV_ADDR_MASK 0x0003FFFFL |
41552 | #define GRBM_IOV_ERROR_FIFO__IOV_VFID_MASK 0x00FC0000L |
41553 | #define GRBM_IOV_ERROR_FIFO__IOV_SSRCID_MASK 0x0F000000L |
41554 | #define GRBM_IOV_ERROR_FIFO__IOV_OP_MASK 0x10000000L |
41555 | #define GRBM_IOV_ERROR_FIFO__IOV_VF_MASK 0x20000000L |
41556 | #define GRBM_IOV_ERROR_FIFO__FIFO_OVERFLOW_MASK 0x40000000L |
41557 | #define GRBM_IOV_ERROR_FIFO__READ_VALID_MASK 0x80000000L |
41558 | //GRBM_SEC_CNTL |
41559 | #define GRBM_SEC_CNTL__DEBUG_ENABLE__SHIFT 0x0 |
41560 | #define GRBM_SEC_CNTL__DEBUG_ENABLE_MASK 0x00000001L |
41561 | //GRBM_CAM_INDEX |
41562 | #define GRBM_CAM_INDEX__CAM_INDEX__SHIFT 0x0 |
41563 | #define GRBM_CAM_INDEX__CAM_INDEX_MASK 0x0000000FL |
41564 | //GRBM_HYP_CAM_INDEX |
41565 | #define GRBM_HYP_CAM_INDEX__CAM_INDEX__SHIFT 0x0 |
41566 | #define GRBM_HYP_CAM_INDEX__CAM_INDEX_MASK 0x0000000FL |
41567 | //GRBM_CAM_DATA |
41568 | #define GRBM_CAM_DATA__CAM_ADDR__SHIFT 0x0 |
41569 | #define GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT 0x10 |
41570 | #define GRBM_CAM_DATA__CAM_ADDR_MASK 0x0000FFFFL |
41571 | #define GRBM_CAM_DATA__CAM_REMAPADDR_MASK 0xFFFF0000L |
41572 | //GRBM_HYP_CAM_DATA |
41573 | #define GRBM_HYP_CAM_DATA__CAM_ADDR__SHIFT 0x0 |
41574 | #define GRBM_HYP_CAM_DATA__CAM_REMAPADDR__SHIFT 0x10 |
41575 | #define GRBM_HYP_CAM_DATA__CAM_ADDR_MASK 0x0000FFFFL |
41576 | #define GRBM_HYP_CAM_DATA__CAM_REMAPADDR_MASK 0xFFFF0000L |
41577 | //GRBM_CAM_DATA_UPPER |
41578 | #define GRBM_CAM_DATA_UPPER__CAM_ADDR__SHIFT 0x0 |
41579 | #define GRBM_CAM_DATA_UPPER__CAM_REMAPADDR__SHIFT 0x10 |
41580 | #define GRBM_CAM_DATA_UPPER__CAM_ADDR_MASK 0x00000003L |
41581 | #define GRBM_CAM_DATA_UPPER__CAM_REMAPADDR_MASK 0x00030000L |
41582 | //GRBM_HYP_CAM_DATA_UPPER |
41583 | #define GRBM_HYP_CAM_DATA_UPPER__CAM_ADDR__SHIFT 0x0 |
41584 | #define GRBM_HYP_CAM_DATA_UPPER__CAM_REMAPADDR__SHIFT 0x10 |
41585 | #define GRBM_HYP_CAM_DATA_UPPER__CAM_ADDR_MASK 0x00000003L |
41586 | #define GRBM_HYP_CAM_DATA_UPPER__CAM_REMAPADDR_MASK 0x00030000L |
41587 | //RLC_FWL_FIRST_VIOL_ADDR |
41588 | #define RLC_FWL_FIRST_VIOL_ADDR__VIOL_ADDR__SHIFT 0x0 |
41589 | #define RLC_FWL_FIRST_VIOL_ADDR__VIOL_APERTURE_ID__SHIFT 0x12 |
41590 | #define RLC_FWL_FIRST_VIOL_ADDR__VIOL_OP__SHIFT 0x1e |
41591 | #define RLC_FWL_FIRST_VIOL_ADDR__RESERVED__SHIFT 0x1f |
41592 | #define RLC_FWL_FIRST_VIOL_ADDR__VIOL_ADDR_MASK 0x0003FFFFL |
41593 | #define RLC_FWL_FIRST_VIOL_ADDR__VIOL_APERTURE_ID_MASK 0x3FFC0000L |
41594 | #define RLC_FWL_FIRST_VIOL_ADDR__VIOL_OP_MASK 0x40000000L |
41595 | #define RLC_FWL_FIRST_VIOL_ADDR__RESERVED_MASK 0x80000000L |
41596 | |
41597 | |
41598 | // addressBlock: gc_gfx_imu_gfx_imudec |
41599 | //GFX_IMU_C2PMSG_0 |
41600 | #define GFX_IMU_C2PMSG_0__DATA__SHIFT 0x0 |
41601 | #define GFX_IMU_C2PMSG_0__DATA_MASK 0xFFFFFFFFL |
41602 | //GFX_IMU_C2PMSG_1 |
41603 | #define GFX_IMU_C2PMSG_1__DATA__SHIFT 0x0 |
41604 | #define GFX_IMU_C2PMSG_1__DATA_MASK 0xFFFFFFFFL |
41605 | //GFX_IMU_C2PMSG_2 |
41606 | #define GFX_IMU_C2PMSG_2__DATA__SHIFT 0x0 |
41607 | #define GFX_IMU_C2PMSG_2__DATA_MASK 0xFFFFFFFFL |
41608 | //GFX_IMU_C2PMSG_3 |
41609 | #define GFX_IMU_C2PMSG_3__DATA__SHIFT 0x0 |
41610 | #define GFX_IMU_C2PMSG_3__DATA_MASK 0xFFFFFFFFL |
41611 | //GFX_IMU_C2PMSG_4 |
41612 | #define GFX_IMU_C2PMSG_4__DATA__SHIFT 0x0 |
41613 | #define GFX_IMU_C2PMSG_4__DATA_MASK 0xFFFFFFFFL |
41614 | //GFX_IMU_C2PMSG_5 |
41615 | #define GFX_IMU_C2PMSG_5__DATA__SHIFT 0x0 |
41616 | #define GFX_IMU_C2PMSG_5__DATA_MASK 0xFFFFFFFFL |
41617 | //GFX_IMU_C2PMSG_6 |
41618 | #define GFX_IMU_C2PMSG_6__DATA__SHIFT 0x0 |
41619 | #define GFX_IMU_C2PMSG_6__DATA_MASK 0xFFFFFFFFL |
41620 | //GFX_IMU_C2PMSG_7 |
41621 | #define GFX_IMU_C2PMSG_7__DATA__SHIFT 0x0 |
41622 | #define GFX_IMU_C2PMSG_7__DATA_MASK 0xFFFFFFFFL |
41623 | //GFX_IMU_C2PMSG_8 |
41624 | #define GFX_IMU_C2PMSG_8__DATA__SHIFT 0x0 |
41625 | #define GFX_IMU_C2PMSG_8__DATA_MASK 0xFFFFFFFFL |
41626 | //GFX_IMU_C2PMSG_9 |
41627 | #define GFX_IMU_C2PMSG_9__DATA__SHIFT 0x0 |
41628 | #define GFX_IMU_C2PMSG_9__DATA_MASK 0xFFFFFFFFL |
41629 | //GFX_IMU_C2PMSG_10 |
41630 | #define GFX_IMU_C2PMSG_10__DATA__SHIFT 0x0 |
41631 | #define GFX_IMU_C2PMSG_10__DATA_MASK 0xFFFFFFFFL |
41632 | //GFX_IMU_C2PMSG_11 |
41633 | #define GFX_IMU_C2PMSG_11__DATA__SHIFT 0x0 |
41634 | #define GFX_IMU_C2PMSG_11__DATA_MASK 0xFFFFFFFFL |
41635 | //GFX_IMU_C2PMSG_12 |
41636 | #define GFX_IMU_C2PMSG_12__DATA__SHIFT 0x0 |
41637 | #define GFX_IMU_C2PMSG_12__DATA_MASK 0xFFFFFFFFL |
41638 | //GFX_IMU_C2PMSG_13 |
41639 | #define GFX_IMU_C2PMSG_13__DATA__SHIFT 0x0 |
41640 | #define GFX_IMU_C2PMSG_13__DATA_MASK 0xFFFFFFFFL |
41641 | //GFX_IMU_C2PMSG_14 |
41642 | #define GFX_IMU_C2PMSG_14__DATA__SHIFT 0x0 |
41643 | #define GFX_IMU_C2PMSG_14__DATA_MASK 0xFFFFFFFFL |
41644 | //GFX_IMU_C2PMSG_15 |
41645 | #define GFX_IMU_C2PMSG_15__DATA__SHIFT 0x0 |
41646 | #define GFX_IMU_C2PMSG_15__DATA_MASK 0xFFFFFFFFL |
41647 | //GFX_IMU_C2PMSG_16 |
41648 | #define GFX_IMU_C2PMSG_16__DATA__SHIFT 0x0 |
41649 | #define GFX_IMU_C2PMSG_16__DATA_MASK 0xFFFFFFFFL |
41650 | //GFX_IMU_C2PMSG_17 |
41651 | #define GFX_IMU_C2PMSG_17__DATA__SHIFT 0x0 |
41652 | #define GFX_IMU_C2PMSG_17__DATA_MASK 0xFFFFFFFFL |
41653 | //GFX_IMU_C2PMSG_18 |
41654 | #define GFX_IMU_C2PMSG_18__DATA__SHIFT 0x0 |
41655 | #define GFX_IMU_C2PMSG_18__DATA_MASK 0xFFFFFFFFL |
41656 | //GFX_IMU_C2PMSG_19 |
41657 | #define GFX_IMU_C2PMSG_19__DATA__SHIFT 0x0 |
41658 | #define GFX_IMU_C2PMSG_19__DATA_MASK 0xFFFFFFFFL |
41659 | //GFX_IMU_C2PMSG_20 |
41660 | #define GFX_IMU_C2PMSG_20__DATA__SHIFT 0x0 |
41661 | #define GFX_IMU_C2PMSG_20__DATA_MASK 0xFFFFFFFFL |
41662 | //GFX_IMU_C2PMSG_21 |
41663 | #define GFX_IMU_C2PMSG_21__DATA__SHIFT 0x0 |
41664 | #define GFX_IMU_C2PMSG_21__DATA_MASK 0xFFFFFFFFL |
41665 | //GFX_IMU_C2PMSG_22 |
41666 | #define GFX_IMU_C2PMSG_22__DATA__SHIFT 0x0 |
41667 | #define GFX_IMU_C2PMSG_22__DATA_MASK 0xFFFFFFFFL |
41668 | //GFX_IMU_C2PMSG_23 |
41669 | #define GFX_IMU_C2PMSG_23__DATA__SHIFT 0x0 |
41670 | #define GFX_IMU_C2PMSG_23__DATA_MASK 0xFFFFFFFFL |
41671 | //GFX_IMU_C2PMSG_24 |
41672 | #define GFX_IMU_C2PMSG_24__DATA__SHIFT 0x0 |
41673 | #define GFX_IMU_C2PMSG_24__DATA_MASK 0xFFFFFFFFL |
41674 | //GFX_IMU_C2PMSG_25 |
41675 | #define GFX_IMU_C2PMSG_25__DATA__SHIFT 0x0 |
41676 | #define GFX_IMU_C2PMSG_25__DATA_MASK 0xFFFFFFFFL |
41677 | //GFX_IMU_C2PMSG_26 |
41678 | #define GFX_IMU_C2PMSG_26__DATA__SHIFT 0x0 |
41679 | #define GFX_IMU_C2PMSG_26__DATA_MASK 0xFFFFFFFFL |
41680 | //GFX_IMU_C2PMSG_27 |
41681 | #define GFX_IMU_C2PMSG_27__DATA__SHIFT 0x0 |
41682 | #define GFX_IMU_C2PMSG_27__DATA_MASK 0xFFFFFFFFL |
41683 | //GFX_IMU_C2PMSG_28 |
41684 | #define GFX_IMU_C2PMSG_28__DATA__SHIFT 0x0 |
41685 | #define GFX_IMU_C2PMSG_28__DATA_MASK 0xFFFFFFFFL |
41686 | //GFX_IMU_C2PMSG_29 |
41687 | #define GFX_IMU_C2PMSG_29__DATA__SHIFT 0x0 |
41688 | #define GFX_IMU_C2PMSG_29__DATA_MASK 0xFFFFFFFFL |
41689 | //GFX_IMU_C2PMSG_30 |
41690 | #define GFX_IMU_C2PMSG_30__DATA__SHIFT 0x0 |
41691 | #define GFX_IMU_C2PMSG_30__DATA_MASK 0xFFFFFFFFL |
41692 | //GFX_IMU_C2PMSG_31 |
41693 | #define GFX_IMU_C2PMSG_31__DATA__SHIFT 0x0 |
41694 | #define GFX_IMU_C2PMSG_31__DATA_MASK 0xFFFFFFFFL |
41695 | //GFX_IMU_C2PMSG_32 |
41696 | #define GFX_IMU_C2PMSG_32__DATA__SHIFT 0x0 |
41697 | #define GFX_IMU_C2PMSG_32__DATA_MASK 0xFFFFFFFFL |
41698 | //GFX_IMU_C2PMSG_33 |
41699 | #define GFX_IMU_C2PMSG_33__DATA__SHIFT 0x0 |
41700 | #define GFX_IMU_C2PMSG_33__DATA_MASK 0xFFFFFFFFL |
41701 | //GFX_IMU_C2PMSG_34 |
41702 | #define GFX_IMU_C2PMSG_34__DATA__SHIFT 0x0 |
41703 | #define GFX_IMU_C2PMSG_34__DATA_MASK 0xFFFFFFFFL |
41704 | //GFX_IMU_C2PMSG_35 |
41705 | #define GFX_IMU_C2PMSG_35__DATA__SHIFT 0x0 |
41706 | #define GFX_IMU_C2PMSG_35__DATA_MASK 0xFFFFFFFFL |
41707 | //GFX_IMU_C2PMSG_36 |
41708 | #define GFX_IMU_C2PMSG_36__DATA__SHIFT 0x0 |
41709 | #define GFX_IMU_C2PMSG_36__DATA_MASK 0xFFFFFFFFL |
41710 | //GFX_IMU_C2PMSG_37 |
41711 | #define GFX_IMU_C2PMSG_37__DATA__SHIFT 0x0 |
41712 | #define GFX_IMU_C2PMSG_37__DATA_MASK 0xFFFFFFFFL |
41713 | //GFX_IMU_C2PMSG_38 |
41714 | #define GFX_IMU_C2PMSG_38__DATA__SHIFT 0x0 |
41715 | #define GFX_IMU_C2PMSG_38__DATA_MASK 0xFFFFFFFFL |
41716 | //GFX_IMU_C2PMSG_39 |
41717 | #define GFX_IMU_C2PMSG_39__DATA__SHIFT 0x0 |
41718 | #define GFX_IMU_C2PMSG_39__DATA_MASK 0xFFFFFFFFL |
41719 | //GFX_IMU_C2PMSG_40 |
41720 | #define GFX_IMU_C2PMSG_40__DATA__SHIFT 0x0 |
41721 | #define GFX_IMU_C2PMSG_40__DATA_MASK 0xFFFFFFFFL |
41722 | //GFX_IMU_C2PMSG_41 |
41723 | #define GFX_IMU_C2PMSG_41__DATA__SHIFT 0x0 |
41724 | #define GFX_IMU_C2PMSG_41__DATA_MASK 0xFFFFFFFFL |
41725 | //GFX_IMU_C2PMSG_42 |
41726 | #define GFX_IMU_C2PMSG_42__DATA__SHIFT 0x0 |
41727 | #define GFX_IMU_C2PMSG_42__DATA_MASK 0xFFFFFFFFL |
41728 | //GFX_IMU_C2PMSG_43 |
41729 | #define GFX_IMU_C2PMSG_43__DATA__SHIFT 0x0 |
41730 | #define GFX_IMU_C2PMSG_43__DATA_MASK 0xFFFFFFFFL |
41731 | //GFX_IMU_C2PMSG_44 |
41732 | #define GFX_IMU_C2PMSG_44__DATA__SHIFT 0x0 |
41733 | #define GFX_IMU_C2PMSG_44__DATA_MASK 0xFFFFFFFFL |
41734 | //GFX_IMU_C2PMSG_45 |
41735 | #define GFX_IMU_C2PMSG_45__DATA__SHIFT 0x0 |
41736 | #define GFX_IMU_C2PMSG_45__DATA_MASK 0xFFFFFFFFL |
41737 | //GFX_IMU_C2PMSG_46 |
41738 | #define GFX_IMU_C2PMSG_46__DATA__SHIFT 0x0 |
41739 | #define GFX_IMU_C2PMSG_46__DATA_MASK 0xFFFFFFFFL |
41740 | //GFX_IMU_C2PMSG_47 |
41741 | #define GFX_IMU_C2PMSG_47__DATA__SHIFT 0x0 |
41742 | #define GFX_IMU_C2PMSG_47__DATA_MASK 0xFFFFFFFFL |
41743 | //GFX_IMU_MSG_FLAGS |
41744 | #define GFX_IMU_MSG_FLAGS__STATUS__SHIFT 0x0 |
41745 | #define GFX_IMU_MSG_FLAGS__STATUS_MASK 0xFFFFFFFFL |
41746 | //GFX_IMU_C2PMSG_ACCESS_CTRL0 |
41747 | #define GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC0__SHIFT 0x0 |
41748 | #define GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC1__SHIFT 0x3 |
41749 | #define GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC2__SHIFT 0x6 |
41750 | #define GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC3__SHIFT 0x9 |
41751 | #define GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC4__SHIFT 0xc |
41752 | #define GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC5__SHIFT 0xf |
41753 | #define GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC6__SHIFT 0x12 |
41754 | #define GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC7__SHIFT 0x15 |
41755 | #define GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC0_MASK 0x00000007L |
41756 | #define GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC1_MASK 0x00000038L |
41757 | #define GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC2_MASK 0x000001C0L |
41758 | #define GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC3_MASK 0x00000E00L |
41759 | #define GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC4_MASK 0x00007000L |
41760 | #define GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC5_MASK 0x00038000L |
41761 | #define GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC6_MASK 0x001C0000L |
41762 | #define GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC7_MASK 0x00E00000L |
41763 | //GFX_IMU_C2PMSG_ACCESS_CTRL1 |
41764 | #define GFX_IMU_C2PMSG_ACCESS_CTRL1__ACC8_15__SHIFT 0x0 |
41765 | #define GFX_IMU_C2PMSG_ACCESS_CTRL1__ACC16_23__SHIFT 0x3 |
41766 | #define GFX_IMU_C2PMSG_ACCESS_CTRL1__ACC24_31__SHIFT 0x6 |
41767 | #define GFX_IMU_C2PMSG_ACCESS_CTRL1__ACC32_39__SHIFT 0x9 |
41768 | #define GFX_IMU_C2PMSG_ACCESS_CTRL1__ACC40_47__SHIFT 0xc |
41769 | #define GFX_IMU_C2PMSG_ACCESS_CTRL1__ACC8_15_MASK 0x00000007L |
41770 | #define GFX_IMU_C2PMSG_ACCESS_CTRL1__ACC16_23_MASK 0x00000038L |
41771 | #define GFX_IMU_C2PMSG_ACCESS_CTRL1__ACC24_31_MASK 0x000001C0L |
41772 | #define GFX_IMU_C2PMSG_ACCESS_CTRL1__ACC32_39_MASK 0x00000E00L |
41773 | #define GFX_IMU_C2PMSG_ACCESS_CTRL1__ACC40_47_MASK 0x00007000L |
41774 | //GFX_IMU_PWRMGT_IRQ_CTRL |
41775 | #define GFX_IMU_PWRMGT_IRQ_CTRL__REQ__SHIFT 0x0 |
41776 | #define GFX_IMU_PWRMGT_IRQ_CTRL__REQ_MASK 0x00000001L |
41777 | //GFX_IMU_MP1_MUTEX |
41778 | #define GFX_IMU_MP1_MUTEX__MUTEX__SHIFT 0x0 |
41779 | #define GFX_IMU_MP1_MUTEX__MUTEX_MASK 0x00000003L |
41780 | //GFX_IMU_RLC_DATA_4 |
41781 | #define GFX_IMU_RLC_DATA_4__DATA__SHIFT 0x0 |
41782 | #define GFX_IMU_RLC_DATA_4__DATA_MASK 0xFFFFFFFFL |
41783 | //GFX_IMU_RLC_DATA_3 |
41784 | #define GFX_IMU_RLC_DATA_3__DATA__SHIFT 0x0 |
41785 | #define GFX_IMU_RLC_DATA_3__DATA_MASK 0xFFFFFFFFL |
41786 | //GFX_IMU_RLC_DATA_2 |
41787 | #define GFX_IMU_RLC_DATA_2__DATA__SHIFT 0x0 |
41788 | #define GFX_IMU_RLC_DATA_2__DATA_MASK 0xFFFFFFFFL |
41789 | //GFX_IMU_RLC_DATA_1 |
41790 | #define GFX_IMU_RLC_DATA_1__DATA__SHIFT 0x0 |
41791 | #define GFX_IMU_RLC_DATA_1__DATA_MASK 0xFFFFFFFFL |
41792 | //GFX_IMU_RLC_DATA_0 |
41793 | #define GFX_IMU_RLC_DATA_0__DATA__SHIFT 0x0 |
41794 | #define GFX_IMU_RLC_DATA_0__DATA_MASK 0xFFFFFFFFL |
41795 | //GFX_IMU_RLC_CMD |
41796 | #define GFX_IMU_RLC_CMD__CMD__SHIFT 0x0 |
41797 | #define GFX_IMU_RLC_CMD__CMD_MASK 0xFFFFFFFFL |
41798 | //GFX_IMU_RLC_MUTEX |
41799 | #define GFX_IMU_RLC_MUTEX__MUTEX__SHIFT 0x0 |
41800 | #define GFX_IMU_RLC_MUTEX__MUTEX_MASK 0x00000003L |
41801 | //GFX_IMU_RLC_MSG_STATUS |
41802 | #define GFX_IMU_RLC_MSG_STATUS__IMU2RLC_BUSY__SHIFT 0x0 |
41803 | #define GFX_IMU_RLC_MSG_STATUS__IMU2RLC_MSG_ERROR__SHIFT 0x1 |
41804 | #define GFX_IMU_RLC_MSG_STATUS__RLC2IMU_MSGDONE__SHIFT 0x10 |
41805 | #define GFX_IMU_RLC_MSG_STATUS__RLC2IMU_CHGTOG__SHIFT 0x1e |
41806 | #define GFX_IMU_RLC_MSG_STATUS__RLC2IMU_DONETOG__SHIFT 0x1f |
41807 | #define GFX_IMU_RLC_MSG_STATUS__IMU2RLC_BUSY_MASK 0x00000001L |
41808 | #define GFX_IMU_RLC_MSG_STATUS__IMU2RLC_MSG_ERROR_MASK 0x00000002L |
41809 | #define GFX_IMU_RLC_MSG_STATUS__RLC2IMU_MSGDONE_MASK 0x00010000L |
41810 | #define GFX_IMU_RLC_MSG_STATUS__RLC2IMU_CHGTOG_MASK 0x40000000L |
41811 | #define GFX_IMU_RLC_MSG_STATUS__RLC2IMU_DONETOG_MASK 0x80000000L |
41812 | //RLC_GFX_IMU_DATA_0 |
41813 | #define RLC_GFX_IMU_DATA_0__DATA__SHIFT 0x0 |
41814 | #define RLC_GFX_IMU_DATA_0__DATA_MASK 0xFFFFFFFFL |
41815 | //RLC_GFX_IMU_CMD |
41816 | #define RLC_GFX_IMU_CMD__CMD__SHIFT 0x0 |
41817 | #define RLC_GFX_IMU_CMD__CMD_MASK 0xFFFFFFFFL |
41818 | //GFX_IMU_RLC_STATUS |
41819 | #define GFX_IMU_RLC_STATUS__PD_ACTIVE__SHIFT 0x0 |
41820 | #define GFX_IMU_RLC_STATUS__RLC_ALIVE__SHIFT 0x1 |
41821 | #define GFX_IMU_RLC_STATUS__TBD2__SHIFT 0x2 |
41822 | #define GFX_IMU_RLC_STATUS__TBD3__SHIFT 0x3 |
41823 | #define GFX_IMU_RLC_STATUS__PD_ACTIVE_MASK 0x00000001L |
41824 | #define GFX_IMU_RLC_STATUS__RLC_ALIVE_MASK 0x00000002L |
41825 | #define GFX_IMU_RLC_STATUS__TBD2_MASK 0x00000004L |
41826 | #define GFX_IMU_RLC_STATUS__TBD3_MASK 0x00000008L |
41827 | //GFX_IMU_STATUS |
41828 | #define GFX_IMU_STATUS__ALLOW_GFXOFF__SHIFT 0x0 |
41829 | #define GFX_IMU_STATUS__ALLOW_FA_DCS__SHIFT 0x1 |
41830 | #define GFX_IMU_STATUS__TBD2__SHIFT 0x2 |
41831 | #define GFX_IMU_STATUS__TBD3__SHIFT 0x3 |
41832 | #define GFX_IMU_STATUS__TBD4__SHIFT 0x4 |
41833 | #define GFX_IMU_STATUS__TBD5__SHIFT 0x5 |
41834 | #define GFX_IMU_STATUS__TBD6__SHIFT 0x6 |
41835 | #define GFX_IMU_STATUS__TBD7__SHIFT 0x7 |
41836 | #define GFX_IMU_STATUS__TBD8__SHIFT 0x8 |
41837 | #define GFX_IMU_STATUS__TBD9__SHIFT 0x9 |
41838 | #define GFX_IMU_STATUS__TBD10__SHIFT 0xa |
41839 | #define GFX_IMU_STATUS__TBD11__SHIFT 0xb |
41840 | #define GFX_IMU_STATUS__TBD12__SHIFT 0xc |
41841 | #define GFX_IMU_STATUS__TBD13__SHIFT 0xd |
41842 | #define GFX_IMU_STATUS__TBD14__SHIFT 0xe |
41843 | #define GFX_IMU_STATUS__DISABLE_GFXCLK_DS__SHIFT 0xf |
41844 | #define GFX_IMU_STATUS__ALLOW_GFXOFF_MASK 0x00000001L |
41845 | #define GFX_IMU_STATUS__ALLOW_FA_DCS_MASK 0x00000002L |
41846 | #define GFX_IMU_STATUS__TBD2_MASK 0x00000004L |
41847 | #define GFX_IMU_STATUS__TBD3_MASK 0x00000008L |
41848 | #define GFX_IMU_STATUS__TBD4_MASK 0x00000010L |
41849 | #define GFX_IMU_STATUS__TBD5_MASK 0x00000020L |
41850 | #define GFX_IMU_STATUS__TBD6_MASK 0x00000040L |
41851 | #define GFX_IMU_STATUS__TBD7_MASK 0x00000080L |
41852 | #define GFX_IMU_STATUS__TBD8_MASK 0x00000100L |
41853 | #define GFX_IMU_STATUS__TBD9_MASK 0x00000200L |
41854 | #define GFX_IMU_STATUS__TBD10_MASK 0x00000400L |
41855 | #define GFX_IMU_STATUS__TBD11_MASK 0x00000800L |
41856 | #define GFX_IMU_STATUS__TBD12_MASK 0x00001000L |
41857 | #define GFX_IMU_STATUS__TBD13_MASK 0x00002000L |
41858 | #define GFX_IMU_STATUS__TBD14_MASK 0x00004000L |
41859 | #define GFX_IMU_STATUS__DISABLE_GFXCLK_DS_MASK 0x00008000L |
41860 | //GFX_IMU_SOC_DATA |
41861 | #define GFX_IMU_SOC_DATA__DATA__SHIFT 0x0 |
41862 | #define GFX_IMU_SOC_DATA__DATA_MASK 0xFFFFFFFFL |
41863 | //GFX_IMU_SOC_ADDR |
41864 | #define GFX_IMU_SOC_ADDR__ADDR__SHIFT 0x0 |
41865 | #define GFX_IMU_SOC_ADDR__ADDR_MASK 0xFFFFFFFFL |
41866 | //GFX_IMU_SOC_REQ |
41867 | #define GFX_IMU_SOC_REQ__REQ_BUSY__SHIFT 0x0 |
41868 | #define GFX_IMU_SOC_REQ__R_W__SHIFT 0x1 |
41869 | #define GFX_IMU_SOC_REQ__ERR__SHIFT 0x1f |
41870 | #define GFX_IMU_SOC_REQ__REQ_BUSY_MASK 0x00000001L |
41871 | #define GFX_IMU_SOC_REQ__R_W_MASK 0x00000002L |
41872 | #define GFX_IMU_SOC_REQ__ERR_MASK 0x80000000L |
41873 | //GFX_IMU_VF_CTRL |
41874 | #define GFX_IMU_VF_CTRL__VF__SHIFT 0x0 |
41875 | #define GFX_IMU_VF_CTRL__VFID__SHIFT 0x1 |
41876 | #define GFX_IMU_VF_CTRL__QOS__SHIFT 0x7 |
41877 | #define GFX_IMU_VF_CTRL__VF_MASK 0x00000001L |
41878 | #define GFX_IMU_VF_CTRL__VFID_MASK 0x0000007EL |
41879 | #define GFX_IMU_VF_CTRL__QOS_MASK 0x00000780L |
41880 | //GFX_IMU_TELEMETRY |
41881 | #define GFX_IMU_TELEMETRY__TELEMETRY_ENTRIES__SHIFT 0x0 |
41882 | #define GFX_IMU_TELEMETRY__TELEMETRY_DATA_SAMPLE_SIZE__SHIFT 0x5 |
41883 | #define GFX_IMU_TELEMETRY__FIFO_OVERFLOW__SHIFT 0x6 |
41884 | #define GFX_IMU_TELEMETRY__FIFO_UNDERFLOW__SHIFT 0x7 |
41885 | #define GFX_IMU_TELEMETRY__FSM_STATE__SHIFT 0x8 |
41886 | #define GFX_IMU_TELEMETRY__SVI_TYPE__SHIFT 0xc |
41887 | #define GFX_IMU_TELEMETRY__ENABLE_FIFO__SHIFT 0x1e |
41888 | #define GFX_IMU_TELEMETRY__ENABLE_IMU_RLC_TELEMETRY__SHIFT 0x1f |
41889 | #define GFX_IMU_TELEMETRY__TELEMETRY_ENTRIES_MASK 0x0000001FL |
41890 | #define GFX_IMU_TELEMETRY__TELEMETRY_DATA_SAMPLE_SIZE_MASK 0x00000020L |
41891 | #define GFX_IMU_TELEMETRY__FIFO_OVERFLOW_MASK 0x00000040L |
41892 | #define GFX_IMU_TELEMETRY__FIFO_UNDERFLOW_MASK 0x00000080L |
41893 | #define GFX_IMU_TELEMETRY__FSM_STATE_MASK 0x00000700L |
41894 | #define GFX_IMU_TELEMETRY__SVI_TYPE_MASK 0x00003000L |
41895 | #define GFX_IMU_TELEMETRY__ENABLE_FIFO_MASK 0x40000000L |
41896 | #define GFX_IMU_TELEMETRY__ENABLE_IMU_RLC_TELEMETRY_MASK 0x80000000L |
41897 | //GFX_IMU_TELEMETRY_DATA |
41898 | #define GFX_IMU_TELEMETRY_DATA__CURRENT__SHIFT 0x0 |
41899 | #define GFX_IMU_TELEMETRY_DATA__VOLTAGE__SHIFT 0x10 |
41900 | #define GFX_IMU_TELEMETRY_DATA__CURRENT_MASK 0x0000FFFFL |
41901 | #define GFX_IMU_TELEMETRY_DATA__VOLTAGE_MASK 0xFFFF0000L |
41902 | //GFX_IMU_TELEMETRY_TEMPERATURE |
41903 | #define GFX_IMU_TELEMETRY_TEMPERATURE__TEMPERATURE__SHIFT 0x0 |
41904 | #define GFX_IMU_TELEMETRY_TEMPERATURE__TEMPERATURE_MASK 0x0000FFFFL |
41905 | //GFX_IMU_SCRATCH_0 |
41906 | #define GFX_IMU_SCRATCH_0__DATA__SHIFT 0x0 |
41907 | #define GFX_IMU_SCRATCH_0__DATA_MASK 0xFFFFFFFFL |
41908 | //GFX_IMU_SCRATCH_1 |
41909 | #define GFX_IMU_SCRATCH_1__DATA__SHIFT 0x0 |
41910 | #define GFX_IMU_SCRATCH_1__DATA_MASK 0xFFFFFFFFL |
41911 | //GFX_IMU_SCRATCH_2 |
41912 | #define GFX_IMU_SCRATCH_2__DATA__SHIFT 0x0 |
41913 | #define GFX_IMU_SCRATCH_2__DATA_MASK 0xFFFFFFFFL |
41914 | //GFX_IMU_SCRATCH_3 |
41915 | #define GFX_IMU_SCRATCH_3__DATA__SHIFT 0x0 |
41916 | #define GFX_IMU_SCRATCH_3__DATA_MASK 0xFFFFFFFFL |
41917 | //GFX_IMU_SCRATCH_4 |
41918 | #define GFX_IMU_SCRATCH_4__DATA__SHIFT 0x0 |
41919 | #define GFX_IMU_SCRATCH_4__DATA_MASK 0xFFFFFFFFL |
41920 | //GFX_IMU_SCRATCH_5 |
41921 | #define GFX_IMU_SCRATCH_5__DATA__SHIFT 0x0 |
41922 | #define GFX_IMU_SCRATCH_5__DATA_MASK 0xFFFFFFFFL |
41923 | //GFX_IMU_SCRATCH_6 |
41924 | #define GFX_IMU_SCRATCH_6__DATA__SHIFT 0x0 |
41925 | #define GFX_IMU_SCRATCH_6__DATA_MASK 0xFFFFFFFFL |
41926 | //GFX_IMU_SCRATCH_7 |
41927 | #define GFX_IMU_SCRATCH_7__DATA__SHIFT 0x0 |
41928 | #define GFX_IMU_SCRATCH_7__DATA_MASK 0xFFFFFFFFL |
41929 | //GFX_IMU_SCRATCH_8 |
41930 | #define GFX_IMU_SCRATCH_8__DATA__SHIFT 0x0 |
41931 | #define GFX_IMU_SCRATCH_8__DATA_MASK 0xFFFFFFFFL |
41932 | //GFX_IMU_SCRATCH_9 |
41933 | #define GFX_IMU_SCRATCH_9__DATA__SHIFT 0x0 |
41934 | #define GFX_IMU_SCRATCH_9__DATA_MASK 0xFFFFFFFFL |
41935 | //GFX_IMU_SCRATCH_10 |
41936 | #define GFX_IMU_SCRATCH_10__DATA__SHIFT 0x0 |
41937 | #define GFX_IMU_SCRATCH_10__DATA_MASK 0xFFFFFFFFL |
41938 | //GFX_IMU_SCRATCH_11 |
41939 | #define GFX_IMU_SCRATCH_11__DATA__SHIFT 0x0 |
41940 | #define GFX_IMU_SCRATCH_11__DATA_MASK 0xFFFFFFFFL |
41941 | //GFX_IMU_SCRATCH_12 |
41942 | #define GFX_IMU_SCRATCH_12__DATA__SHIFT 0x0 |
41943 | #define GFX_IMU_SCRATCH_12__DATA_MASK 0xFFFFFFFFL |
41944 | //GFX_IMU_SCRATCH_13 |
41945 | #define GFX_IMU_SCRATCH_13__DATA__SHIFT 0x0 |
41946 | #define GFX_IMU_SCRATCH_13__DATA_MASK 0xFFFFFFFFL |
41947 | //GFX_IMU_SCRATCH_14 |
41948 | #define GFX_IMU_SCRATCH_14__DATA__SHIFT 0x0 |
41949 | #define GFX_IMU_SCRATCH_14__DATA_MASK 0xFFFFFFFFL |
41950 | //GFX_IMU_SCRATCH_15 |
41951 | #define GFX_IMU_SCRATCH_15__DATA__SHIFT 0x0 |
41952 | #define GFX_IMU_SCRATCH_15__DATA_MASK 0xFFFFFFFFL |
41953 | //GFX_IMU_FW_GTS_LO |
41954 | #define GFX_IMU_FW_GTS_LO__TSTAMP_LO__SHIFT 0x0 |
41955 | #define GFX_IMU_FW_GTS_LO__TSTAMP_LO_MASK 0xFFFFFFFFL |
41956 | //GFX_IMU_FW_GTS_HI |
41957 | #define GFX_IMU_FW_GTS_HI__TSTAMP_HI__SHIFT 0x0 |
41958 | #define GFX_IMU_FW_GTS_HI__TSTAMP_HI_MASK 0x00FFFFFFL |
41959 | //GFX_IMU_GTS_OFFSET_LO |
41960 | #define GFX_IMU_GTS_OFFSET_LO__GTS_OFFSET_LO__SHIFT 0x0 |
41961 | #define GFX_IMU_GTS_OFFSET_LO__GTS_OFFSET_LO_MASK 0xFFFFFFFFL |
41962 | //GFX_IMU_GTS_OFFSET_HI |
41963 | #define GFX_IMU_GTS_OFFSET_HI__GTS_OFFSET_HI__SHIFT 0x0 |
41964 | #define GFX_IMU_GTS_OFFSET_HI__GTS_OFFSET_HI_MASK 0x00FFFFFFL |
41965 | //GFX_IMU_RLC_GTS_OFFSET_LO |
41966 | #define GFX_IMU_RLC_GTS_OFFSET_LO__GTS_OFFSET_LO__SHIFT 0x0 |
41967 | #define GFX_IMU_RLC_GTS_OFFSET_LO__GTS_OFFSET_LO_MASK 0xFFFFFFFFL |
41968 | //GFX_IMU_RLC_GTS_OFFSET_HI |
41969 | #define GFX_IMU_RLC_GTS_OFFSET_HI__GTS_OFFSET_HI__SHIFT 0x0 |
41970 | #define GFX_IMU_RLC_GTS_OFFSET_HI__GTS_OFFSET_HI_MASK 0x00FFFFFFL |
41971 | //GFX_IMU_CORE_INT_STATUS |
41972 | #define GFX_IMU_CORE_INT_STATUS__INTERRUPT_24__SHIFT 0x18 |
41973 | #define GFX_IMU_CORE_INT_STATUS__INTERRUPT_25__SHIFT 0x19 |
41974 | #define GFX_IMU_CORE_INT_STATUS__INTERRUPT_29__SHIFT 0x1d |
41975 | #define GFX_IMU_CORE_INT_STATUS__INTERRUPT_24_MASK 0x01000000L |
41976 | #define GFX_IMU_CORE_INT_STATUS__INTERRUPT_25_MASK 0x02000000L |
41977 | #define GFX_IMU_CORE_INT_STATUS__INTERRUPT_29_MASK 0x20000000L |
41978 | //GFX_IMU_PIC_INT_MASK |
41979 | #define GFX_IMU_PIC_INT_MASK__MASK_0__SHIFT 0x0 |
41980 | #define GFX_IMU_PIC_INT_MASK__MASK_1__SHIFT 0x1 |
41981 | #define GFX_IMU_PIC_INT_MASK__MASK_2__SHIFT 0x2 |
41982 | #define GFX_IMU_PIC_INT_MASK__MASK_3__SHIFT 0x3 |
41983 | #define GFX_IMU_PIC_INT_MASK__MASK_4__SHIFT 0x4 |
41984 | #define GFX_IMU_PIC_INT_MASK__MASK_5__SHIFT 0x5 |
41985 | #define GFX_IMU_PIC_INT_MASK__MASK_6__SHIFT 0x6 |
41986 | #define GFX_IMU_PIC_INT_MASK__MASK_7__SHIFT 0x7 |
41987 | #define GFX_IMU_PIC_INT_MASK__MASK_8__SHIFT 0x8 |
41988 | #define GFX_IMU_PIC_INT_MASK__MASK_9__SHIFT 0x9 |
41989 | #define GFX_IMU_PIC_INT_MASK__MASK_10__SHIFT 0xa |
41990 | #define GFX_IMU_PIC_INT_MASK__MASK_11__SHIFT 0xb |
41991 | #define GFX_IMU_PIC_INT_MASK__MASK_12__SHIFT 0xc |
41992 | #define GFX_IMU_PIC_INT_MASK__MASK_13__SHIFT 0xd |
41993 | #define GFX_IMU_PIC_INT_MASK__MASK_14__SHIFT 0xe |
41994 | #define GFX_IMU_PIC_INT_MASK__MASK_15__SHIFT 0xf |
41995 | #define GFX_IMU_PIC_INT_MASK__MASK_16__SHIFT 0x10 |
41996 | #define GFX_IMU_PIC_INT_MASK__MASK_17__SHIFT 0x11 |
41997 | #define GFX_IMU_PIC_INT_MASK__MASK_18__SHIFT 0x12 |
41998 | #define GFX_IMU_PIC_INT_MASK__MASK_19__SHIFT 0x13 |
41999 | #define GFX_IMU_PIC_INT_MASK__MASK_20__SHIFT 0x14 |
42000 | #define GFX_IMU_PIC_INT_MASK__MASK_21__SHIFT 0x15 |
42001 | #define GFX_IMU_PIC_INT_MASK__MASK_22__SHIFT 0x16 |
42002 | #define GFX_IMU_PIC_INT_MASK__MASK_23__SHIFT 0x17 |
42003 | #define GFX_IMU_PIC_INT_MASK__MASK_24__SHIFT 0x18 |
42004 | #define GFX_IMU_PIC_INT_MASK__MASK_25__SHIFT 0x19 |
42005 | #define GFX_IMU_PIC_INT_MASK__MASK_26__SHIFT 0x1a |
42006 | #define GFX_IMU_PIC_INT_MASK__MASK_27__SHIFT 0x1b |
42007 | #define GFX_IMU_PIC_INT_MASK__MASK_28__SHIFT 0x1c |
42008 | #define GFX_IMU_PIC_INT_MASK__MASK_29__SHIFT 0x1d |
42009 | #define GFX_IMU_PIC_INT_MASK__MASK_30__SHIFT 0x1e |
42010 | #define GFX_IMU_PIC_INT_MASK__MASK_31__SHIFT 0x1f |
42011 | #define GFX_IMU_PIC_INT_MASK__MASK_0_MASK 0x00000001L |
42012 | #define GFX_IMU_PIC_INT_MASK__MASK_1_MASK 0x00000002L |
42013 | #define GFX_IMU_PIC_INT_MASK__MASK_2_MASK 0x00000004L |
42014 | #define GFX_IMU_PIC_INT_MASK__MASK_3_MASK 0x00000008L |
42015 | #define GFX_IMU_PIC_INT_MASK__MASK_4_MASK 0x00000010L |
42016 | #define GFX_IMU_PIC_INT_MASK__MASK_5_MASK 0x00000020L |
42017 | #define GFX_IMU_PIC_INT_MASK__MASK_6_MASK 0x00000040L |
42018 | #define GFX_IMU_PIC_INT_MASK__MASK_7_MASK 0x00000080L |
42019 | #define GFX_IMU_PIC_INT_MASK__MASK_8_MASK 0x00000100L |
42020 | #define GFX_IMU_PIC_INT_MASK__MASK_9_MASK 0x00000200L |
42021 | #define GFX_IMU_PIC_INT_MASK__MASK_10_MASK 0x00000400L |
42022 | #define GFX_IMU_PIC_INT_MASK__MASK_11_MASK 0x00000800L |
42023 | #define GFX_IMU_PIC_INT_MASK__MASK_12_MASK 0x00001000L |
42024 | #define GFX_IMU_PIC_INT_MASK__MASK_13_MASK 0x00002000L |
42025 | #define GFX_IMU_PIC_INT_MASK__MASK_14_MASK 0x00004000L |
42026 | #define GFX_IMU_PIC_INT_MASK__MASK_15_MASK 0x00008000L |
42027 | #define GFX_IMU_PIC_INT_MASK__MASK_16_MASK 0x00010000L |
42028 | #define GFX_IMU_PIC_INT_MASK__MASK_17_MASK 0x00020000L |
42029 | #define GFX_IMU_PIC_INT_MASK__MASK_18_MASK 0x00040000L |
42030 | #define GFX_IMU_PIC_INT_MASK__MASK_19_MASK 0x00080000L |
42031 | #define GFX_IMU_PIC_INT_MASK__MASK_20_MASK 0x00100000L |
42032 | #define GFX_IMU_PIC_INT_MASK__MASK_21_MASK 0x00200000L |
42033 | #define GFX_IMU_PIC_INT_MASK__MASK_22_MASK 0x00400000L |
42034 | #define GFX_IMU_PIC_INT_MASK__MASK_23_MASK 0x00800000L |
42035 | #define GFX_IMU_PIC_INT_MASK__MASK_24_MASK 0x01000000L |
42036 | #define GFX_IMU_PIC_INT_MASK__MASK_25_MASK 0x02000000L |
42037 | #define GFX_IMU_PIC_INT_MASK__MASK_26_MASK 0x04000000L |
42038 | #define GFX_IMU_PIC_INT_MASK__MASK_27_MASK 0x08000000L |
42039 | #define GFX_IMU_PIC_INT_MASK__MASK_28_MASK 0x10000000L |
42040 | #define GFX_IMU_PIC_INT_MASK__MASK_29_MASK 0x20000000L |
42041 | #define GFX_IMU_PIC_INT_MASK__MASK_30_MASK 0x40000000L |
42042 | #define GFX_IMU_PIC_INT_MASK__MASK_31_MASK 0x80000000L |
42043 | //GFX_IMU_PIC_INT_LVL |
42044 | #define GFX_IMU_PIC_INT_LVL__LVL_0__SHIFT 0x0 |
42045 | #define GFX_IMU_PIC_INT_LVL__LVL_1__SHIFT 0x1 |
42046 | #define GFX_IMU_PIC_INT_LVL__LVL_2__SHIFT 0x2 |
42047 | #define GFX_IMU_PIC_INT_LVL__LVL_3__SHIFT 0x3 |
42048 | #define GFX_IMU_PIC_INT_LVL__LVL_4__SHIFT 0x4 |
42049 | #define GFX_IMU_PIC_INT_LVL__LVL_5__SHIFT 0x5 |
42050 | #define GFX_IMU_PIC_INT_LVL__LVL_6__SHIFT 0x6 |
42051 | #define GFX_IMU_PIC_INT_LVL__LVL_7__SHIFT 0x7 |
42052 | #define GFX_IMU_PIC_INT_LVL__LVL_8__SHIFT 0x8 |
42053 | #define GFX_IMU_PIC_INT_LVL__LVL_9__SHIFT 0x9 |
42054 | #define GFX_IMU_PIC_INT_LVL__LVL_10__SHIFT 0xa |
42055 | #define GFX_IMU_PIC_INT_LVL__LVL_11__SHIFT 0xb |
42056 | #define GFX_IMU_PIC_INT_LVL__LVL_12__SHIFT 0xc |
42057 | #define GFX_IMU_PIC_INT_LVL__LVL_13__SHIFT 0xd |
42058 | #define GFX_IMU_PIC_INT_LVL__LVL_14__SHIFT 0xe |
42059 | #define GFX_IMU_PIC_INT_LVL__LVL_15__SHIFT 0xf |
42060 | #define GFX_IMU_PIC_INT_LVL__LVL_16__SHIFT 0x10 |
42061 | #define GFX_IMU_PIC_INT_LVL__LVL_17__SHIFT 0x11 |
42062 | #define GFX_IMU_PIC_INT_LVL__LVL_18__SHIFT 0x12 |
42063 | #define GFX_IMU_PIC_INT_LVL__LVL_19__SHIFT 0x13 |
42064 | #define GFX_IMU_PIC_INT_LVL__LVL_20__SHIFT 0x14 |
42065 | #define GFX_IMU_PIC_INT_LVL__LVL_21__SHIFT 0x15 |
42066 | #define GFX_IMU_PIC_INT_LVL__LVL_22__SHIFT 0x16 |
42067 | #define GFX_IMU_PIC_INT_LVL__LVL_23__SHIFT 0x17 |
42068 | #define GFX_IMU_PIC_INT_LVL__LVL_24__SHIFT 0x18 |
42069 | #define GFX_IMU_PIC_INT_LVL__LVL_25__SHIFT 0x19 |
42070 | #define GFX_IMU_PIC_INT_LVL__LVL_26__SHIFT 0x1a |
42071 | #define GFX_IMU_PIC_INT_LVL__LVL_27__SHIFT 0x1b |
42072 | #define GFX_IMU_PIC_INT_LVL__LVL_28__SHIFT 0x1c |
42073 | #define GFX_IMU_PIC_INT_LVL__LVL_29__SHIFT 0x1d |
42074 | #define GFX_IMU_PIC_INT_LVL__LVL_30__SHIFT 0x1e |
42075 | #define GFX_IMU_PIC_INT_LVL__LVL_31__SHIFT 0x1f |
42076 | #define GFX_IMU_PIC_INT_LVL__LVL_0_MASK 0x00000001L |
42077 | #define GFX_IMU_PIC_INT_LVL__LVL_1_MASK 0x00000002L |
42078 | #define GFX_IMU_PIC_INT_LVL__LVL_2_MASK 0x00000004L |
42079 | #define GFX_IMU_PIC_INT_LVL__LVL_3_MASK 0x00000008L |
42080 | #define GFX_IMU_PIC_INT_LVL__LVL_4_MASK 0x00000010L |
42081 | #define GFX_IMU_PIC_INT_LVL__LVL_5_MASK 0x00000020L |
42082 | #define GFX_IMU_PIC_INT_LVL__LVL_6_MASK 0x00000040L |
42083 | #define GFX_IMU_PIC_INT_LVL__LVL_7_MASK 0x00000080L |
42084 | #define GFX_IMU_PIC_INT_LVL__LVL_8_MASK 0x00000100L |
42085 | #define GFX_IMU_PIC_INT_LVL__LVL_9_MASK 0x00000200L |
42086 | #define GFX_IMU_PIC_INT_LVL__LVL_10_MASK 0x00000400L |
42087 | #define GFX_IMU_PIC_INT_LVL__LVL_11_MASK 0x00000800L |
42088 | #define GFX_IMU_PIC_INT_LVL__LVL_12_MASK 0x00001000L |
42089 | #define GFX_IMU_PIC_INT_LVL__LVL_13_MASK 0x00002000L |
42090 | #define GFX_IMU_PIC_INT_LVL__LVL_14_MASK 0x00004000L |
42091 | #define GFX_IMU_PIC_INT_LVL__LVL_15_MASK 0x00008000L |
42092 | #define GFX_IMU_PIC_INT_LVL__LVL_16_MASK 0x00010000L |
42093 | #define GFX_IMU_PIC_INT_LVL__LVL_17_MASK 0x00020000L |
42094 | #define GFX_IMU_PIC_INT_LVL__LVL_18_MASK 0x00040000L |
42095 | #define GFX_IMU_PIC_INT_LVL__LVL_19_MASK 0x00080000L |
42096 | #define GFX_IMU_PIC_INT_LVL__LVL_20_MASK 0x00100000L |
42097 | #define GFX_IMU_PIC_INT_LVL__LVL_21_MASK 0x00200000L |
42098 | #define GFX_IMU_PIC_INT_LVL__LVL_22_MASK 0x00400000L |
42099 | #define GFX_IMU_PIC_INT_LVL__LVL_23_MASK 0x00800000L |
42100 | #define GFX_IMU_PIC_INT_LVL__LVL_24_MASK 0x01000000L |
42101 | #define GFX_IMU_PIC_INT_LVL__LVL_25_MASK 0x02000000L |
42102 | #define GFX_IMU_PIC_INT_LVL__LVL_26_MASK 0x04000000L |
42103 | #define GFX_IMU_PIC_INT_LVL__LVL_27_MASK 0x08000000L |
42104 | #define GFX_IMU_PIC_INT_LVL__LVL_28_MASK 0x10000000L |
42105 | #define GFX_IMU_PIC_INT_LVL__LVL_29_MASK 0x20000000L |
42106 | #define GFX_IMU_PIC_INT_LVL__LVL_30_MASK 0x40000000L |
42107 | #define GFX_IMU_PIC_INT_LVL__LVL_31_MASK 0x80000000L |
42108 | //GFX_IMU_PIC_INT_EDGE |
42109 | #define GFX_IMU_PIC_INT_EDGE__EDGE_0__SHIFT 0x0 |
42110 | #define GFX_IMU_PIC_INT_EDGE__EDGE_1__SHIFT 0x1 |
42111 | #define GFX_IMU_PIC_INT_EDGE__EDGE_2__SHIFT 0x2 |
42112 | #define GFX_IMU_PIC_INT_EDGE__EDGE_3__SHIFT 0x3 |
42113 | #define GFX_IMU_PIC_INT_EDGE__EDGE_4__SHIFT 0x4 |
42114 | #define GFX_IMU_PIC_INT_EDGE__EDGE_5__SHIFT 0x5 |
42115 | #define GFX_IMU_PIC_INT_EDGE__EDGE_6__SHIFT 0x6 |
42116 | #define GFX_IMU_PIC_INT_EDGE__EDGE_7__SHIFT 0x7 |
42117 | #define GFX_IMU_PIC_INT_EDGE__EDGE_8__SHIFT 0x8 |
42118 | #define GFX_IMU_PIC_INT_EDGE__EDGE_9__SHIFT 0x9 |
42119 | #define GFX_IMU_PIC_INT_EDGE__EDGE_10__SHIFT 0xa |
42120 | #define GFX_IMU_PIC_INT_EDGE__EDGE_11__SHIFT 0xb |
42121 | #define GFX_IMU_PIC_INT_EDGE__EDGE_12__SHIFT 0xc |
42122 | #define GFX_IMU_PIC_INT_EDGE__EDGE_13__SHIFT 0xd |
42123 | #define GFX_IMU_PIC_INT_EDGE__EDGE_14__SHIFT 0xe |
42124 | #define GFX_IMU_PIC_INT_EDGE__EDGE_15__SHIFT 0xf |
42125 | #define GFX_IMU_PIC_INT_EDGE__EDGE_16__SHIFT 0x10 |
42126 | #define GFX_IMU_PIC_INT_EDGE__EDGE_17__SHIFT 0x11 |
42127 | #define GFX_IMU_PIC_INT_EDGE__EDGE_18__SHIFT 0x12 |
42128 | #define GFX_IMU_PIC_INT_EDGE__EDGE_19__SHIFT 0x13 |
42129 | #define GFX_IMU_PIC_INT_EDGE__EDGE_20__SHIFT 0x14 |
42130 | #define GFX_IMU_PIC_INT_EDGE__EDGE_21__SHIFT 0x15 |
42131 | #define GFX_IMU_PIC_INT_EDGE__EDGE_22__SHIFT 0x16 |
42132 | #define GFX_IMU_PIC_INT_EDGE__EDGE_23__SHIFT 0x17 |
42133 | #define GFX_IMU_PIC_INT_EDGE__EDGE_24__SHIFT 0x18 |
42134 | #define GFX_IMU_PIC_INT_EDGE__EDGE_25__SHIFT 0x19 |
42135 | #define GFX_IMU_PIC_INT_EDGE__EDGE_26__SHIFT 0x1a |
42136 | #define GFX_IMU_PIC_INT_EDGE__EDGE_27__SHIFT 0x1b |
42137 | #define GFX_IMU_PIC_INT_EDGE__EDGE_28__SHIFT 0x1c |
42138 | #define GFX_IMU_PIC_INT_EDGE__EDGE_29__SHIFT 0x1d |
42139 | #define GFX_IMU_PIC_INT_EDGE__EDGE_30__SHIFT 0x1e |
42140 | #define GFX_IMU_PIC_INT_EDGE__EDGE_31__SHIFT 0x1f |
42141 | #define GFX_IMU_PIC_INT_EDGE__EDGE_0_MASK 0x00000001L |
42142 | #define GFX_IMU_PIC_INT_EDGE__EDGE_1_MASK 0x00000002L |
42143 | #define GFX_IMU_PIC_INT_EDGE__EDGE_2_MASK 0x00000004L |
42144 | #define GFX_IMU_PIC_INT_EDGE__EDGE_3_MASK 0x00000008L |
42145 | #define GFX_IMU_PIC_INT_EDGE__EDGE_4_MASK 0x00000010L |
42146 | #define GFX_IMU_PIC_INT_EDGE__EDGE_5_MASK 0x00000020L |
42147 | #define GFX_IMU_PIC_INT_EDGE__EDGE_6_MASK 0x00000040L |
42148 | #define GFX_IMU_PIC_INT_EDGE__EDGE_7_MASK 0x00000080L |
42149 | #define GFX_IMU_PIC_INT_EDGE__EDGE_8_MASK 0x00000100L |
42150 | #define GFX_IMU_PIC_INT_EDGE__EDGE_9_MASK 0x00000200L |
42151 | #define GFX_IMU_PIC_INT_EDGE__EDGE_10_MASK 0x00000400L |
42152 | #define GFX_IMU_PIC_INT_EDGE__EDGE_11_MASK 0x00000800L |
42153 | #define GFX_IMU_PIC_INT_EDGE__EDGE_12_MASK 0x00001000L |
42154 | #define GFX_IMU_PIC_INT_EDGE__EDGE_13_MASK 0x00002000L |
42155 | #define GFX_IMU_PIC_INT_EDGE__EDGE_14_MASK 0x00004000L |
42156 | #define GFX_IMU_PIC_INT_EDGE__EDGE_15_MASK 0x00008000L |
42157 | #define GFX_IMU_PIC_INT_EDGE__EDGE_16_MASK 0x00010000L |
42158 | #define GFX_IMU_PIC_INT_EDGE__EDGE_17_MASK 0x00020000L |
42159 | #define GFX_IMU_PIC_INT_EDGE__EDGE_18_MASK 0x00040000L |
42160 | #define GFX_IMU_PIC_INT_EDGE__EDGE_19_MASK 0x00080000L |
42161 | #define GFX_IMU_PIC_INT_EDGE__EDGE_20_MASK 0x00100000L |
42162 | #define GFX_IMU_PIC_INT_EDGE__EDGE_21_MASK 0x00200000L |
42163 | #define GFX_IMU_PIC_INT_EDGE__EDGE_22_MASK 0x00400000L |
42164 | #define GFX_IMU_PIC_INT_EDGE__EDGE_23_MASK 0x00800000L |
42165 | #define GFX_IMU_PIC_INT_EDGE__EDGE_24_MASK 0x01000000L |
42166 | #define GFX_IMU_PIC_INT_EDGE__EDGE_25_MASK 0x02000000L |
42167 | #define GFX_IMU_PIC_INT_EDGE__EDGE_26_MASK 0x04000000L |
42168 | #define GFX_IMU_PIC_INT_EDGE__EDGE_27_MASK 0x08000000L |
42169 | #define GFX_IMU_PIC_INT_EDGE__EDGE_28_MASK 0x10000000L |
42170 | #define GFX_IMU_PIC_INT_EDGE__EDGE_29_MASK 0x20000000L |
42171 | #define GFX_IMU_PIC_INT_EDGE__EDGE_30_MASK 0x40000000L |
42172 | #define GFX_IMU_PIC_INT_EDGE__EDGE_31_MASK 0x80000000L |
42173 | //GFX_IMU_PIC_INT_PRI_0 |
42174 | #define GFX_IMU_PIC_INT_PRI_0__PRI_0__SHIFT 0x0 |
42175 | #define GFX_IMU_PIC_INT_PRI_0__PRI_1__SHIFT 0x8 |
42176 | #define GFX_IMU_PIC_INT_PRI_0__PRI_2__SHIFT 0x10 |
42177 | #define GFX_IMU_PIC_INT_PRI_0__PRI_3__SHIFT 0x18 |
42178 | #define GFX_IMU_PIC_INT_PRI_0__PRI_0_MASK 0x000000FFL |
42179 | #define GFX_IMU_PIC_INT_PRI_0__PRI_1_MASK 0x0000FF00L |
42180 | #define GFX_IMU_PIC_INT_PRI_0__PRI_2_MASK 0x00FF0000L |
42181 | #define GFX_IMU_PIC_INT_PRI_0__PRI_3_MASK 0xFF000000L |
42182 | //GFX_IMU_PIC_INT_PRI_1 |
42183 | #define GFX_IMU_PIC_INT_PRI_1__PRI_4__SHIFT 0x0 |
42184 | #define GFX_IMU_PIC_INT_PRI_1__PRI_5__SHIFT 0x8 |
42185 | #define GFX_IMU_PIC_INT_PRI_1__PRI_6__SHIFT 0x10 |
42186 | #define GFX_IMU_PIC_INT_PRI_1__PRI_7__SHIFT 0x18 |
42187 | #define GFX_IMU_PIC_INT_PRI_1__PRI_4_MASK 0x000000FFL |
42188 | #define GFX_IMU_PIC_INT_PRI_1__PRI_5_MASK 0x0000FF00L |
42189 | #define GFX_IMU_PIC_INT_PRI_1__PRI_6_MASK 0x00FF0000L |
42190 | #define GFX_IMU_PIC_INT_PRI_1__PRI_7_MASK 0xFF000000L |
42191 | //GFX_IMU_PIC_INT_PRI_2 |
42192 | #define GFX_IMU_PIC_INT_PRI_2__PRI_8__SHIFT 0x0 |
42193 | #define GFX_IMU_PIC_INT_PRI_2__PRI_9__SHIFT 0x8 |
42194 | #define GFX_IMU_PIC_INT_PRI_2__PRI_10__SHIFT 0x10 |
42195 | #define GFX_IMU_PIC_INT_PRI_2__PRI_11__SHIFT 0x18 |
42196 | #define GFX_IMU_PIC_INT_PRI_2__PRI_8_MASK 0x000000FFL |
42197 | #define GFX_IMU_PIC_INT_PRI_2__PRI_9_MASK 0x0000FF00L |
42198 | #define GFX_IMU_PIC_INT_PRI_2__PRI_10_MASK 0x00FF0000L |
42199 | #define GFX_IMU_PIC_INT_PRI_2__PRI_11_MASK 0xFF000000L |
42200 | //GFX_IMU_PIC_INT_PRI_3 |
42201 | #define GFX_IMU_PIC_INT_PRI_3__PRI_12__SHIFT 0x0 |
42202 | #define GFX_IMU_PIC_INT_PRI_3__PRI_13__SHIFT 0x8 |
42203 | #define GFX_IMU_PIC_INT_PRI_3__PRI_14__SHIFT 0x10 |
42204 | #define GFX_IMU_PIC_INT_PRI_3__PRI_15__SHIFT 0x18 |
42205 | #define GFX_IMU_PIC_INT_PRI_3__PRI_12_MASK 0x000000FFL |
42206 | #define GFX_IMU_PIC_INT_PRI_3__PRI_13_MASK 0x0000FF00L |
42207 | #define GFX_IMU_PIC_INT_PRI_3__PRI_14_MASK 0x00FF0000L |
42208 | #define GFX_IMU_PIC_INT_PRI_3__PRI_15_MASK 0xFF000000L |
42209 | //GFX_IMU_PIC_INT_PRI_4 |
42210 | #define GFX_IMU_PIC_INT_PRI_4__PRI_16__SHIFT 0x0 |
42211 | #define GFX_IMU_PIC_INT_PRI_4__PRI_17__SHIFT 0x8 |
42212 | #define GFX_IMU_PIC_INT_PRI_4__PRI_18__SHIFT 0x10 |
42213 | #define GFX_IMU_PIC_INT_PRI_4__PRI_19__SHIFT 0x18 |
42214 | #define GFX_IMU_PIC_INT_PRI_4__PRI_16_MASK 0x000000FFL |
42215 | #define GFX_IMU_PIC_INT_PRI_4__PRI_17_MASK 0x0000FF00L |
42216 | #define GFX_IMU_PIC_INT_PRI_4__PRI_18_MASK 0x00FF0000L |
42217 | #define GFX_IMU_PIC_INT_PRI_4__PRI_19_MASK 0xFF000000L |
42218 | //GFX_IMU_PIC_INT_PRI_5 |
42219 | #define GFX_IMU_PIC_INT_PRI_5__PRI_20__SHIFT 0x0 |
42220 | #define GFX_IMU_PIC_INT_PRI_5__PRI_21__SHIFT 0x8 |
42221 | #define GFX_IMU_PIC_INT_PRI_5__PRI_22__SHIFT 0x10 |
42222 | #define GFX_IMU_PIC_INT_PRI_5__PRI_23__SHIFT 0x18 |
42223 | #define GFX_IMU_PIC_INT_PRI_5__PRI_20_MASK 0x000000FFL |
42224 | #define GFX_IMU_PIC_INT_PRI_5__PRI_21_MASK 0x0000FF00L |
42225 | #define GFX_IMU_PIC_INT_PRI_5__PRI_22_MASK 0x00FF0000L |
42226 | #define GFX_IMU_PIC_INT_PRI_5__PRI_23_MASK 0xFF000000L |
42227 | //GFX_IMU_PIC_INT_PRI_6 |
42228 | #define GFX_IMU_PIC_INT_PRI_6__PRI_24__SHIFT 0x0 |
42229 | #define GFX_IMU_PIC_INT_PRI_6__PRI_25__SHIFT 0x8 |
42230 | #define GFX_IMU_PIC_INT_PRI_6__PRI_26__SHIFT 0x10 |
42231 | #define GFX_IMU_PIC_INT_PRI_6__PRI_27__SHIFT 0x18 |
42232 | #define GFX_IMU_PIC_INT_PRI_6__PRI_24_MASK 0x000000FFL |
42233 | #define GFX_IMU_PIC_INT_PRI_6__PRI_25_MASK 0x0000FF00L |
42234 | #define GFX_IMU_PIC_INT_PRI_6__PRI_26_MASK 0x00FF0000L |
42235 | #define GFX_IMU_PIC_INT_PRI_6__PRI_27_MASK 0xFF000000L |
42236 | //GFX_IMU_PIC_INT_PRI_7 |
42237 | #define GFX_IMU_PIC_INT_PRI_7__PRI_28__SHIFT 0x0 |
42238 | #define GFX_IMU_PIC_INT_PRI_7__PRI_29__SHIFT 0x8 |
42239 | #define GFX_IMU_PIC_INT_PRI_7__PRI_30__SHIFT 0x10 |
42240 | #define GFX_IMU_PIC_INT_PRI_7__PRI_31__SHIFT 0x18 |
42241 | #define GFX_IMU_PIC_INT_PRI_7__PRI_28_MASK 0x000000FFL |
42242 | #define GFX_IMU_PIC_INT_PRI_7__PRI_29_MASK 0x0000FF00L |
42243 | #define GFX_IMU_PIC_INT_PRI_7__PRI_30_MASK 0x00FF0000L |
42244 | #define GFX_IMU_PIC_INT_PRI_7__PRI_31_MASK 0xFF000000L |
42245 | //GFX_IMU_PIC_INT_STATUS |
42246 | #define GFX_IMU_PIC_INT_STATUS__INT_STATUS0__SHIFT 0x0 |
42247 | #define GFX_IMU_PIC_INT_STATUS__INT_STATUS1__SHIFT 0x1 |
42248 | #define GFX_IMU_PIC_INT_STATUS__INT_STATUS2__SHIFT 0x2 |
42249 | #define GFX_IMU_PIC_INT_STATUS__INT_STATUS3__SHIFT 0x3 |
42250 | #define GFX_IMU_PIC_INT_STATUS__INT_STATUS4__SHIFT 0x4 |
42251 | #define GFX_IMU_PIC_INT_STATUS__INT_STATUS5__SHIFT 0x5 |
42252 | #define GFX_IMU_PIC_INT_STATUS__INT_STATUS6__SHIFT 0x6 |
42253 | #define GFX_IMU_PIC_INT_STATUS__INT_STATUS7__SHIFT 0x7 |
42254 | #define GFX_IMU_PIC_INT_STATUS__INT_STATUS8__SHIFT 0x8 |
42255 | #define GFX_IMU_PIC_INT_STATUS__INT_STATUS9__SHIFT 0x9 |
42256 | #define GFX_IMU_PIC_INT_STATUS__INT_STATUS10__SHIFT 0xa |
42257 | #define GFX_IMU_PIC_INT_STATUS__INT_STATUS11__SHIFT 0xb |
42258 | #define GFX_IMU_PIC_INT_STATUS__INT_STATUS12__SHIFT 0xc |
42259 | #define GFX_IMU_PIC_INT_STATUS__INT_STATUS13__SHIFT 0xd |
42260 | #define GFX_IMU_PIC_INT_STATUS__INT_STATUS14__SHIFT 0xe |
42261 | #define GFX_IMU_PIC_INT_STATUS__INT_STATUS15__SHIFT 0xf |
42262 | #define GFX_IMU_PIC_INT_STATUS__INT_STATUS16__SHIFT 0x10 |
42263 | #define GFX_IMU_PIC_INT_STATUS__INT_STATUS17__SHIFT 0x11 |
42264 | #define GFX_IMU_PIC_INT_STATUS__INT_STATUS18__SHIFT 0x12 |
42265 | #define GFX_IMU_PIC_INT_STATUS__INT_STATUS19__SHIFT 0x13 |
42266 | #define GFX_IMU_PIC_INT_STATUS__INT_STATUS20__SHIFT 0x14 |
42267 | #define GFX_IMU_PIC_INT_STATUS__INT_STATUS21__SHIFT 0x15 |
42268 | #define GFX_IMU_PIC_INT_STATUS__INT_STATUS22__SHIFT 0x16 |
42269 | #define GFX_IMU_PIC_INT_STATUS__INT_STATUS23__SHIFT 0x17 |
42270 | #define GFX_IMU_PIC_INT_STATUS__INT_STATUS24__SHIFT 0x18 |
42271 | #define GFX_IMU_PIC_INT_STATUS__INT_STATUS25__SHIFT 0x19 |
42272 | #define GFX_IMU_PIC_INT_STATUS__INT_STATUS26__SHIFT 0x1a |
42273 | #define GFX_IMU_PIC_INT_STATUS__INT_STATUS27__SHIFT 0x1b |
42274 | #define GFX_IMU_PIC_INT_STATUS__INT_STATUS28__SHIFT 0x1c |
42275 | #define GFX_IMU_PIC_INT_STATUS__INT_STATUS29__SHIFT 0x1d |
42276 | #define GFX_IMU_PIC_INT_STATUS__INT_STATUS30__SHIFT 0x1e |
42277 | #define GFX_IMU_PIC_INT_STATUS__INT_STATUS31__SHIFT 0x1f |
42278 | #define GFX_IMU_PIC_INT_STATUS__INT_STATUS0_MASK 0x00000001L |
42279 | #define GFX_IMU_PIC_INT_STATUS__INT_STATUS1_MASK 0x00000002L |
42280 | #define GFX_IMU_PIC_INT_STATUS__INT_STATUS2_MASK 0x00000004L |
42281 | #define GFX_IMU_PIC_INT_STATUS__INT_STATUS3_MASK 0x00000008L |
42282 | #define GFX_IMU_PIC_INT_STATUS__INT_STATUS4_MASK 0x00000010L |
42283 | #define GFX_IMU_PIC_INT_STATUS__INT_STATUS5_MASK 0x00000020L |
42284 | #define GFX_IMU_PIC_INT_STATUS__INT_STATUS6_MASK 0x00000040L |
42285 | #define GFX_IMU_PIC_INT_STATUS__INT_STATUS7_MASK 0x00000080L |
42286 | #define GFX_IMU_PIC_INT_STATUS__INT_STATUS8_MASK 0x00000100L |
42287 | #define GFX_IMU_PIC_INT_STATUS__INT_STATUS9_MASK 0x00000200L |
42288 | #define GFX_IMU_PIC_INT_STATUS__INT_STATUS10_MASK 0x00000400L |
42289 | #define GFX_IMU_PIC_INT_STATUS__INT_STATUS11_MASK 0x00000800L |
42290 | #define GFX_IMU_PIC_INT_STATUS__INT_STATUS12_MASK 0x00001000L |
42291 | #define GFX_IMU_PIC_INT_STATUS__INT_STATUS13_MASK 0x00002000L |
42292 | #define GFX_IMU_PIC_INT_STATUS__INT_STATUS14_MASK 0x00004000L |
42293 | #define GFX_IMU_PIC_INT_STATUS__INT_STATUS15_MASK 0x00008000L |
42294 | #define GFX_IMU_PIC_INT_STATUS__INT_STATUS16_MASK 0x00010000L |
42295 | #define GFX_IMU_PIC_INT_STATUS__INT_STATUS17_MASK 0x00020000L |
42296 | #define GFX_IMU_PIC_INT_STATUS__INT_STATUS18_MASK 0x00040000L |
42297 | #define GFX_IMU_PIC_INT_STATUS__INT_STATUS19_MASK 0x00080000L |
42298 | #define GFX_IMU_PIC_INT_STATUS__INT_STATUS20_MASK 0x00100000L |
42299 | #define GFX_IMU_PIC_INT_STATUS__INT_STATUS21_MASK 0x00200000L |
42300 | #define GFX_IMU_PIC_INT_STATUS__INT_STATUS22_MASK 0x00400000L |
42301 | #define GFX_IMU_PIC_INT_STATUS__INT_STATUS23_MASK 0x00800000L |
42302 | #define GFX_IMU_PIC_INT_STATUS__INT_STATUS24_MASK 0x01000000L |
42303 | #define GFX_IMU_PIC_INT_STATUS__INT_STATUS25_MASK 0x02000000L |
42304 | #define GFX_IMU_PIC_INT_STATUS__INT_STATUS26_MASK 0x04000000L |
42305 | #define GFX_IMU_PIC_INT_STATUS__INT_STATUS27_MASK 0x08000000L |
42306 | #define GFX_IMU_PIC_INT_STATUS__INT_STATUS28_MASK 0x10000000L |
42307 | #define GFX_IMU_PIC_INT_STATUS__INT_STATUS29_MASK 0x20000000L |
42308 | #define GFX_IMU_PIC_INT_STATUS__INT_STATUS30_MASK 0x40000000L |
42309 | #define GFX_IMU_PIC_INT_STATUS__INT_STATUS31_MASK 0x80000000L |
42310 | //GFX_IMU_PIC_INTR |
42311 | #define GFX_IMU_PIC_INTR__INTR_n__SHIFT 0x0 |
42312 | #define GFX_IMU_PIC_INTR__INTR_n_MASK 0x00000001L |
42313 | //GFX_IMU_PIC_INTR_ID |
42314 | #define GFX_IMU_PIC_INTR_ID__INTR_n__SHIFT 0x0 |
42315 | #define GFX_IMU_PIC_INTR_ID__INTR_n_MASK 0x000000FFL |
42316 | //GFX_IMU_IH_CTRL_1 |
42317 | #define GFX_IMU_IH_CTRL_1__CONTEXT_ID__SHIFT 0x0 |
42318 | #define GFX_IMU_IH_CTRL_1__CONTEXT_ID_MASK 0xFFFFFFFFL |
42319 | //GFX_IMU_IH_CTRL_2 |
42320 | #define GFX_IMU_IH_CTRL_2__CONTEXT_ID__SHIFT 0x0 |
42321 | #define GFX_IMU_IH_CTRL_2__RING_ID__SHIFT 0x8 |
42322 | #define GFX_IMU_IH_CTRL_2__VM_ID__SHIFT 0x10 |
42323 | #define GFX_IMU_IH_CTRL_2__SRSTB__SHIFT 0x1f |
42324 | #define GFX_IMU_IH_CTRL_2__CONTEXT_ID_MASK 0x000000FFL |
42325 | #define GFX_IMU_IH_CTRL_2__RING_ID_MASK 0x0000FF00L |
42326 | #define GFX_IMU_IH_CTRL_2__VM_ID_MASK 0x000F0000L |
42327 | #define GFX_IMU_IH_CTRL_2__SRSTB_MASK 0x80000000L |
42328 | //GFX_IMU_IH_CTRL_3 |
42329 | #define GFX_IMU_IH_CTRL_3__SOURCE_ID__SHIFT 0x0 |
42330 | #define GFX_IMU_IH_CTRL_3__VF_ID__SHIFT 0x8 |
42331 | #define GFX_IMU_IH_CTRL_3__VF__SHIFT 0xd |
42332 | #define GFX_IMU_IH_CTRL_3__SOURCE_ID_MASK 0x000000FFL |
42333 | #define GFX_IMU_IH_CTRL_3__VF_ID_MASK 0x00001F00L |
42334 | #define GFX_IMU_IH_CTRL_3__VF_MASK 0x00002000L |
42335 | //GFX_IMU_IH_STATUS |
42336 | #define GFX_IMU_IH_STATUS__IH_BUSY__SHIFT 0x0 |
42337 | #define GFX_IMU_IH_STATUS__IH_BUSY_MASK 0x00000001L |
42338 | //GFX_IMU_FUSESTRAP |
42339 | #define GFX_IMU_FUSESTRAP__BOOT_VID__SHIFT 0x0 |
42340 | #define GFX_IMU_FUSESTRAP__BOOT_VID_MASK 0x000001FFL |
42341 | //GFX_IMU_SMUIO_VIDCHG_CTRL |
42342 | #define GFX_IMU_SMUIO_VIDCHG_CTRL__REQ__SHIFT 0x0 |
42343 | #define GFX_IMU_SMUIO_VIDCHG_CTRL__DATA__SHIFT 0x1 |
42344 | #define GFX_IMU_SMUIO_VIDCHG_CTRL__PSIEN__SHIFT 0xa |
42345 | #define GFX_IMU_SMUIO_VIDCHG_CTRL__ACK__SHIFT 0xb |
42346 | #define GFX_IMU_SMUIO_VIDCHG_CTRL__SRC_SEL__SHIFT 0x1f |
42347 | #define GFX_IMU_SMUIO_VIDCHG_CTRL__REQ_MASK 0x00000001L |
42348 | #define GFX_IMU_SMUIO_VIDCHG_CTRL__DATA_MASK 0x000003FEL |
42349 | #define GFX_IMU_SMUIO_VIDCHG_CTRL__PSIEN_MASK 0x00000400L |
42350 | #define GFX_IMU_SMUIO_VIDCHG_CTRL__ACK_MASK 0x00000800L |
42351 | #define GFX_IMU_SMUIO_VIDCHG_CTRL__SRC_SEL_MASK 0x80000000L |
42352 | //GFX_IMU_GFXCLK_BYPASS_CTRL |
42353 | #define GFX_IMU_GFXCLK_BYPASS_CTRL__BYPASS_SEL__SHIFT 0x0 |
42354 | #define GFX_IMU_GFXCLK_BYPASS_CTRL__BYPASS_SEL_MASK 0x00000001L |
42355 | //GFX_IMU_CLK_CTRL |
42356 | #define GFX_IMU_CLK_CTRL__CG_OVR__SHIFT 0x0 |
42357 | #define GFX_IMU_CLK_CTRL__CG_OVR_CORE__SHIFT 0x1 |
42358 | #define GFX_IMU_CLK_CTRL__CLKDIV__SHIFT 0x4 |
42359 | #define GFX_IMU_CLK_CTRL__GFXBYPASSCLK_CHGTOG__SHIFT 0x8 |
42360 | #define GFX_IMU_CLK_CTRL__GFXBYPASSCLK_DONETOG__SHIFT 0x9 |
42361 | #define GFX_IMU_CLK_CTRL__GFXBYPASSCLK_DIV__SHIFT 0x10 |
42362 | #define GFX_IMU_CLK_CTRL__COOLDOWN_PERIOD__SHIFT 0x1c |
42363 | #define GFX_IMU_CLK_CTRL__CG_OVR_MASK 0x00000001L |
42364 | #define GFX_IMU_CLK_CTRL__CG_OVR_CORE_MASK 0x00000002L |
42365 | #define GFX_IMU_CLK_CTRL__CLKDIV_MASK 0x00000010L |
42366 | #define GFX_IMU_CLK_CTRL__GFXBYPASSCLK_CHGTOG_MASK 0x00000100L |
42367 | #define GFX_IMU_CLK_CTRL__GFXBYPASSCLK_DONETOG_MASK 0x00000200L |
42368 | #define GFX_IMU_CLK_CTRL__GFXBYPASSCLK_DIV_MASK 0x007F0000L |
42369 | #define GFX_IMU_CLK_CTRL__COOLDOWN_PERIOD_MASK 0xF0000000L |
42370 | //GFX_IMU_DOORBELL_CONTROL |
42371 | #define GFX_IMU_DOORBELL_CONTROL__OVR_EN__SHIFT 0x0 |
42372 | #define GFX_IMU_DOORBELL_CONTROL__FENCE_EN_OVR__SHIFT 0x1 |
42373 | #define GFX_IMU_DOORBELL_CONTROL__CP_DB_RESP_PEND_COUNT__SHIFT 0x18 |
42374 | #define GFX_IMU_DOORBELL_CONTROL__FENCE_EN_STATUS__SHIFT 0x1f |
42375 | #define GFX_IMU_DOORBELL_CONTROL__OVR_EN_MASK 0x00000001L |
42376 | #define GFX_IMU_DOORBELL_CONTROL__FENCE_EN_OVR_MASK 0x00000002L |
42377 | #define GFX_IMU_DOORBELL_CONTROL__CP_DB_RESP_PEND_COUNT_MASK 0x7F000000L |
42378 | #define GFX_IMU_DOORBELL_CONTROL__FENCE_EN_STATUS_MASK 0x80000000L |
42379 | //GFX_IMU_RLC_CG_CTRL |
42380 | #define GFX_IMU_RLC_CG_CTRL__FORCE_CGCG__SHIFT 0x0 |
42381 | #define GFX_IMU_RLC_CG_CTRL__MGCG_EARLY_EN__SHIFT 0x1 |
42382 | #define GFX_IMU_RLC_CG_CTRL__FORCE_CGCG_MASK 0x00000001L |
42383 | #define GFX_IMU_RLC_CG_CTRL__MGCG_EARLY_EN_MASK 0x00000002L |
42384 | //GFX_IMU_RLC_THROTTLE_GFX |
42385 | #define GFX_IMU_RLC_THROTTLE_GFX__THROTTLE_EN__SHIFT 0x0 |
42386 | #define GFX_IMU_RLC_THROTTLE_GFX__THROTTLE_EN_MASK 0x00000001L |
42387 | //GFX_IMU_RLC_RESET_VECTOR |
42388 | #define GFX_IMU_RLC_RESET_VECTOR__COLD_VS_GFXOFF__SHIFT 0x0 |
42389 | #define GFX_IMU_RLC_RESET_VECTOR__WARM_RESET_EXIT__SHIFT 0x2 |
42390 | #define GFX_IMU_RLC_RESET_VECTOR__VF_FLR_EXIT__SHIFT 0x3 |
42391 | #define GFX_IMU_RLC_RESET_VECTOR__VECTOR__SHIFT 0x4 |
42392 | #define GFX_IMU_RLC_RESET_VECTOR__COLD_VS_GFXOFF_MASK 0x00000001L |
42393 | #define GFX_IMU_RLC_RESET_VECTOR__WARM_RESET_EXIT_MASK 0x00000004L |
42394 | #define GFX_IMU_RLC_RESET_VECTOR__VF_FLR_EXIT_MASK 0x00000008L |
42395 | #define GFX_IMU_RLC_RESET_VECTOR__VECTOR_MASK 0x000000F0L |
42396 | //GFX_IMU_RLC_OVERRIDE |
42397 | #define GFX_IMU_RLC_OVERRIDE__DS_ALLOW__SHIFT 0x0 |
42398 | #define GFX_IMU_RLC_OVERRIDE__DS_ALLOW_MASK 0x00000001L |
42399 | //GFX_IMU_DPM_CONTROL |
42400 | #define GFX_IMU_DPM_CONTROL__ACC_RESET__SHIFT 0x0 |
42401 | #define GFX_IMU_DPM_CONTROL__ACC_START__SHIFT 0x1 |
42402 | #define GFX_IMU_DPM_CONTROL__BUSY_MASK__SHIFT 0x2 |
42403 | #define GFX_IMU_DPM_CONTROL__ACC_RESET_MASK 0x00000001L |
42404 | #define GFX_IMU_DPM_CONTROL__ACC_START_MASK 0x00000002L |
42405 | #define GFX_IMU_DPM_CONTROL__BUSY_MASK_MASK 0x0003FFFCL |
42406 | //GFX_IMU_DPM_ACC |
42407 | #define GFX_IMU_DPM_ACC__COUNT__SHIFT 0x0 |
42408 | #define GFX_IMU_DPM_ACC__COUNT_MASK 0x00FFFFFFL |
42409 | //GFX_IMU_DPM_REF_COUNTER |
42410 | #define GFX_IMU_DPM_REF_COUNTER__COUNT__SHIFT 0x0 |
42411 | #define GFX_IMU_DPM_REF_COUNTER__COUNT_MASK 0x00FFFFFFL |
42412 | //GFX_IMU_RLC_RAM_INDEX |
42413 | #define GFX_IMU_RLC_RAM_INDEX__INDEX__SHIFT 0x0 |
42414 | #define GFX_IMU_RLC_RAM_INDEX__RLC_INDEX__SHIFT 0x10 |
42415 | #define GFX_IMU_RLC_RAM_INDEX__RAM_VALID__SHIFT 0x1f |
42416 | #define GFX_IMU_RLC_RAM_INDEX__INDEX_MASK 0x000000FFL |
42417 | #define GFX_IMU_RLC_RAM_INDEX__RLC_INDEX_MASK 0x00FF0000L |
42418 | #define GFX_IMU_RLC_RAM_INDEX__RAM_VALID_MASK 0x80000000L |
42419 | //GFX_IMU_RLC_RAM_ADDR_HIGH |
42420 | #define GFX_IMU_RLC_RAM_ADDR_HIGH__ADDR_MSB__SHIFT 0x0 |
42421 | #define GFX_IMU_RLC_RAM_ADDR_HIGH__ADDR_MSB_MASK 0x0000FFFFL |
42422 | //GFX_IMU_RLC_RAM_ADDR_LOW |
42423 | #define GFX_IMU_RLC_RAM_ADDR_LOW__ADDR_LSB__SHIFT 0x0 |
42424 | #define GFX_IMU_RLC_RAM_ADDR_LOW__ADDR_LSB_MASK 0xFFFFFFFFL |
42425 | //GFX_IMU_RLC_RAM_DATA |
42426 | #define GFX_IMU_RLC_RAM_DATA__DATA__SHIFT 0x0 |
42427 | #define GFX_IMU_RLC_RAM_DATA__DATA_MASK 0xFFFFFFFFL |
42428 | //GFX_IMU_FENCE_CTRL |
42429 | #define GFX_IMU_FENCE_CTRL__ENABLED__SHIFT 0x0 |
42430 | #define GFX_IMU_FENCE_CTRL__ARM_LOG__SHIFT 0x1 |
42431 | #define GFX_IMU_FENCE_CTRL__GRBM_RSMU_FENCE_ENABLE__SHIFT 0x2 |
42432 | #define GFX_IMU_FENCE_CTRL__FLUSH_ARBITER_CREDITS__SHIFT 0x3 |
42433 | #define GFX_IMU_FENCE_CTRL__GFX_REG_FENCE_OVR_EN__SHIFT 0x8 |
42434 | #define GFX_IMU_FENCE_CTRL__GFX_REG_FENCE_OVR__SHIFT 0x9 |
42435 | #define GFX_IMU_FENCE_CTRL__ENABLED_MASK 0x00000001L |
42436 | #define GFX_IMU_FENCE_CTRL__ARM_LOG_MASK 0x00000002L |
42437 | #define GFX_IMU_FENCE_CTRL__GRBM_RSMU_FENCE_ENABLE_MASK 0x00000004L |
42438 | #define GFX_IMU_FENCE_CTRL__FLUSH_ARBITER_CREDITS_MASK 0x00000008L |
42439 | #define GFX_IMU_FENCE_CTRL__GFX_REG_FENCE_OVR_EN_MASK 0x00000100L |
42440 | #define GFX_IMU_FENCE_CTRL__GFX_REG_FENCE_OVR_MASK 0x00000200L |
42441 | //GFX_IMU_FENCE_LOG_INIT |
42442 | #define GFX_IMU_FENCE_LOG_INIT__UNIT_ID__SHIFT 0x0 |
42443 | #define GFX_IMU_FENCE_LOG_INIT__INITIATOR_ID__SHIFT 0x7 |
42444 | #define GFX_IMU_FENCE_LOG_INIT__UNIT_ID_MASK 0x0000007FL |
42445 | #define GFX_IMU_FENCE_LOG_INIT__INITIATOR_ID_MASK 0x0001FF80L |
42446 | //GFX_IMU_FENCE_LOG_ADDR |
42447 | #define GFX_IMU_FENCE_LOG_ADDR__ADDR__SHIFT 0x2 |
42448 | #define GFX_IMU_FENCE_LOG_ADDR__ADDR_MASK 0x000FFFFCL |
42449 | //GFX_IMU_PROGRAM_CTR |
42450 | #define GFX_IMU_PROGRAM_CTR__PC__SHIFT 0x0 |
42451 | #define GFX_IMU_PROGRAM_CTR__PC_MASK 0xFFFFFFFFL |
42452 | //GFX_IMU_CORE_CTRL |
42453 | #define GFX_IMU_CORE_CTRL__CRESET__SHIFT 0x0 |
42454 | #define GFX_IMU_CORE_CTRL__CSTALL__SHIFT 0x1 |
42455 | #define GFX_IMU_CORE_CTRL__CDBGENABLE__SHIFT 0x2 |
42456 | #define GFX_IMU_CORE_CTRL__DRESET__SHIFT 0x3 |
42457 | #define GFX_IMU_CORE_CTRL__HALT_ON_RESET__SHIFT 0x4 |
42458 | #define GFX_IMU_CORE_CTRL__BREAK_IN__SHIFT 0x8 |
42459 | #define GFX_IMU_CORE_CTRL__BREAK_OUT_ACK__SHIFT 0x9 |
42460 | #define GFX_IMU_CORE_CTRL__CRESET_MASK 0x00000001L |
42461 | #define GFX_IMU_CORE_CTRL__CSTALL_MASK 0x00000002L |
42462 | #define GFX_IMU_CORE_CTRL__CDBGENABLE_MASK 0x00000004L |
42463 | #define GFX_IMU_CORE_CTRL__DRESET_MASK 0x00000008L |
42464 | #define GFX_IMU_CORE_CTRL__HALT_ON_RESET_MASK 0x00000010L |
42465 | #define GFX_IMU_CORE_CTRL__BREAK_IN_MASK 0x00000100L |
42466 | #define GFX_IMU_CORE_CTRL__BREAK_OUT_ACK_MASK 0x00000200L |
42467 | //GFX_IMU_CORE_STATUS |
42468 | #define GFX_IMU_CORE_STATUS__CBUSY__SHIFT 0x0 |
42469 | #define GFX_IMU_CORE_STATUS__PWAIT_MODE__SHIFT 0x1 |
42470 | #define GFX_IMU_CORE_STATUS__PSP_ACC_ERR__SHIFT 0x2 |
42471 | #define GFX_IMU_CORE_STATUS__CINTLEVEL__SHIFT 0x4 |
42472 | #define GFX_IMU_CORE_STATUS__BREAK_IN_ACK__SHIFT 0x8 |
42473 | #define GFX_IMU_CORE_STATUS__BREAK_OUT__SHIFT 0x9 |
42474 | #define GFX_IMU_CORE_STATUS__DEBUG_MODE__SHIFT 0xa |
42475 | #define GFX_IMU_CORE_STATUS__P_FATAL_ERROR__SHIFT 0xb |
42476 | #define GFX_IMU_CORE_STATUS__FAULT_SEVERITY_LEVEL__SHIFT 0x18 |
42477 | #define GFX_IMU_CORE_STATUS__FAULT_TYPE__SHIFT 0x1c |
42478 | #define GFX_IMU_CORE_STATUS__CBUSY_MASK 0x00000001L |
42479 | #define GFX_IMU_CORE_STATUS__PWAIT_MODE_MASK 0x00000002L |
42480 | #define GFX_IMU_CORE_STATUS__PSP_ACC_ERR_MASK 0x00000004L |
42481 | #define GFX_IMU_CORE_STATUS__CINTLEVEL_MASK 0x000000F0L |
42482 | #define GFX_IMU_CORE_STATUS__BREAK_IN_ACK_MASK 0x00000100L |
42483 | #define GFX_IMU_CORE_STATUS__BREAK_OUT_MASK 0x00000200L |
42484 | #define GFX_IMU_CORE_STATUS__DEBUG_MODE_MASK 0x00000400L |
42485 | #define GFX_IMU_CORE_STATUS__P_FATAL_ERROR_MASK 0x00000800L |
42486 | #define GFX_IMU_CORE_STATUS__FAULT_SEVERITY_LEVEL_MASK 0x0F000000L |
42487 | #define GFX_IMU_CORE_STATUS__FAULT_TYPE_MASK 0xF0000000L |
42488 | //GFX_IMU_PWROKRAW |
42489 | #define GFX_IMU_PWROKRAW__PWROKRAW__SHIFT 0x0 |
42490 | #define GFX_IMU_PWROKRAW__PWROKRAW_MASK 0x00000001L |
42491 | //GFX_IMU_PWROK |
42492 | #define GFX_IMU_PWROK__PWROK__SHIFT 0x0 |
42493 | #define GFX_IMU_PWROK__PWROK_MASK 0x00000001L |
42494 | //GFX_IMU_GAP_PWROK |
42495 | #define GFX_IMU_GAP_PWROK__GAP_PWROK__SHIFT 0x0 |
42496 | #define GFX_IMU_GAP_PWROK__GAP_PWROK_MASK 0x00000001L |
42497 | //GFX_IMU_RESETn |
42498 | #define GFX_IMU_RESETn__Cpl_RESETn__SHIFT 0x0 |
42499 | #define GFX_IMU_RESETn__Cpl_RESETn_MASK 0x00000001L |
42500 | //GFX_IMU_GFX_RESET_CTRL |
42501 | #define GFX_IMU_GFX_RESET_CTRL__HARD_RESETB__SHIFT 0x0 |
42502 | #define GFX_IMU_GFX_RESET_CTRL__EA_RESETB__SHIFT 0x1 |
42503 | #define GFX_IMU_GFX_RESET_CTRL__UTCL2_RESETB__SHIFT 0x2 |
42504 | #define GFX_IMU_GFX_RESET_CTRL__SDMA_RESETB__SHIFT 0x3 |
42505 | #define GFX_IMU_GFX_RESET_CTRL__GRBM_RESETB__SHIFT 0x4 |
42506 | #define GFX_IMU_GFX_RESET_CTRL__HARD_RESETB_MASK 0x00000001L |
42507 | #define GFX_IMU_GFX_RESET_CTRL__EA_RESETB_MASK 0x00000002L |
42508 | #define GFX_IMU_GFX_RESET_CTRL__UTCL2_RESETB_MASK 0x00000004L |
42509 | #define GFX_IMU_GFX_RESET_CTRL__SDMA_RESETB_MASK 0x00000008L |
42510 | #define GFX_IMU_GFX_RESET_CTRL__GRBM_RESETB_MASK 0x00000010L |
42511 | //GFX_IMU_AEB_OVERRIDE |
42512 | #define GFX_IMU_AEB_OVERRIDE__AEB_OVERRIDE_CTRL__SHIFT 0x0 |
42513 | #define GFX_IMU_AEB_OVERRIDE__AEB_RESET_VALUE__SHIFT 0x1 |
42514 | #define GFX_IMU_AEB_OVERRIDE__AEB_VALID_VALUE__SHIFT 0x2 |
42515 | #define GFX_IMU_AEB_OVERRIDE__AEB_OVERRIDE_CTRL_MASK 0x00000001L |
42516 | #define GFX_IMU_AEB_OVERRIDE__AEB_RESET_VALUE_MASK 0x00000002L |
42517 | #define GFX_IMU_AEB_OVERRIDE__AEB_VALID_VALUE_MASK 0x00000004L |
42518 | //GFX_IMU_VDCI_RESET_CTRL |
42519 | #define GFX_IMU_VDCI_RESET_CTRL__SOC2GFX_VDCI_RESETn__SHIFT 0x0 |
42520 | #define GFX_IMU_VDCI_RESET_CTRL__SOC_EA_SDF_VDCI_RESET__SHIFT 0x1 |
42521 | #define GFX_IMU_VDCI_RESET_CTRL__SOC_UTCL2_ATHUB_VDCI_RESET__SHIFT 0x2 |
42522 | #define GFX_IMU_VDCI_RESET_CTRL__SOC_IMUAXI_SYSHUB_VDCI_RESET__SHIFT 0x3 |
42523 | #define GFX_IMU_VDCI_RESET_CTRL__IMU2GFX_VDCI_RESETn__SHIFT 0x4 |
42524 | #define GFX_IMU_VDCI_RESET_CTRL__SOC2GFX_VDCI_RESETn_MASK 0x00000001L |
42525 | #define GFX_IMU_VDCI_RESET_CTRL__SOC_EA_SDF_VDCI_RESET_MASK 0x00000002L |
42526 | #define GFX_IMU_VDCI_RESET_CTRL__SOC_UTCL2_ATHUB_VDCI_RESET_MASK 0x00000004L |
42527 | #define GFX_IMU_VDCI_RESET_CTRL__SOC_IMUAXI_SYSHUB_VDCI_RESET_MASK 0x00000008L |
42528 | #define GFX_IMU_VDCI_RESET_CTRL__IMU2GFX_VDCI_RESETn_MASK 0x00000010L |
42529 | //GFX_IMU_GFX_ISO_CTRL |
42530 | #define GFX_IMU_GFX_ISO_CTRL__GFX2IMU_ISOn__SHIFT 0x0 |
42531 | #define GFX_IMU_GFX_ISO_CTRL__SOC_EA_SDF_VDCI_ISOn_EN__SHIFT 0x1 |
42532 | #define GFX_IMU_GFX_ISO_CTRL__SOC_UTCL2_ATHUB_VDCI_ISOn_EN__SHIFT 0x2 |
42533 | #define GFX_IMU_GFX_ISO_CTRL__GFX2SOC_ISOn__SHIFT 0x3 |
42534 | #define GFX_IMU_GFX_ISO_CTRL__GFX2SOC_CLK_ISOn__SHIFT 0x4 |
42535 | #define GFX_IMU_GFX_ISO_CTRL__GFX2IMU_ISOn_MASK 0x00000001L |
42536 | #define GFX_IMU_GFX_ISO_CTRL__SOC_EA_SDF_VDCI_ISOn_EN_MASK 0x00000002L |
42537 | #define GFX_IMU_GFX_ISO_CTRL__SOC_UTCL2_ATHUB_VDCI_ISOn_EN_MASK 0x00000004L |
42538 | #define GFX_IMU_GFX_ISO_CTRL__GFX2SOC_ISOn_MASK 0x00000008L |
42539 | #define GFX_IMU_GFX_ISO_CTRL__GFX2SOC_CLK_ISOn_MASK 0x00000010L |
42540 | //GFX_IMU_TIMER0_CTRL0 |
42541 | #define GFX_IMU_TIMER0_CTRL0__START_STOP__SHIFT 0x0 |
42542 | #define GFX_IMU_TIMER0_CTRL0__CLEAR__SHIFT 0x8 |
42543 | #define GFX_IMU_TIMER0_CTRL0__UP_DOWN__SHIFT 0x10 |
42544 | #define GFX_IMU_TIMER0_CTRL0__PULSE_EN__SHIFT 0x18 |
42545 | #define GFX_IMU_TIMER0_CTRL0__START_STOP_MASK 0x00000001L |
42546 | #define GFX_IMU_TIMER0_CTRL0__CLEAR_MASK 0x00000100L |
42547 | #define GFX_IMU_TIMER0_CTRL0__UP_DOWN_MASK 0x00010000L |
42548 | #define GFX_IMU_TIMER0_CTRL0__PULSE_EN_MASK 0x01000000L |
42549 | //GFX_IMU_TIMER0_CTRL1 |
42550 | #define GFX_IMU_TIMER0_CTRL1__PWM_EN__SHIFT 0x0 |
42551 | #define GFX_IMU_TIMER0_CTRL1__TS_MODE__SHIFT 0x8 |
42552 | #define GFX_IMU_TIMER0_CTRL1__SAT_EN__SHIFT 0x10 |
42553 | #define GFX_IMU_TIMER0_CTRL1__PWM_EN_MASK 0x00000001L |
42554 | #define GFX_IMU_TIMER0_CTRL1__TS_MODE_MASK 0x00000100L |
42555 | #define GFX_IMU_TIMER0_CTRL1__SAT_EN_MASK 0x00010000L |
42556 | //GFX_IMU_TIMER0_CMP_AUTOINC |
42557 | #define GFX_IMU_TIMER0_CMP_AUTOINC__AUTOINC_EN0__SHIFT 0x0 |
42558 | #define GFX_IMU_TIMER0_CMP_AUTOINC__AUTOINC_EN1__SHIFT 0x1 |
42559 | #define GFX_IMU_TIMER0_CMP_AUTOINC__AUTOINC_EN2__SHIFT 0x2 |
42560 | #define GFX_IMU_TIMER0_CMP_AUTOINC__AUTOINC_EN3__SHIFT 0x3 |
42561 | #define GFX_IMU_TIMER0_CMP_AUTOINC__AUTOINC_EN0_MASK 0x00000001L |
42562 | #define GFX_IMU_TIMER0_CMP_AUTOINC__AUTOINC_EN1_MASK 0x00000002L |
42563 | #define GFX_IMU_TIMER0_CMP_AUTOINC__AUTOINC_EN2_MASK 0x00000004L |
42564 | #define GFX_IMU_TIMER0_CMP_AUTOINC__AUTOINC_EN3_MASK 0x00000008L |
42565 | //GFX_IMU_TIMER0_CMP_INTEN |
42566 | #define GFX_IMU_TIMER0_CMP_INTEN__INT_EN0__SHIFT 0x0 |
42567 | #define GFX_IMU_TIMER0_CMP_INTEN__INT_EN1__SHIFT 0x1 |
42568 | #define GFX_IMU_TIMER0_CMP_INTEN__INT_EN2__SHIFT 0x2 |
42569 | #define GFX_IMU_TIMER0_CMP_INTEN__INT_EN3__SHIFT 0x3 |
42570 | #define GFX_IMU_TIMER0_CMP_INTEN__INT_EN0_MASK 0x00000001L |
42571 | #define GFX_IMU_TIMER0_CMP_INTEN__INT_EN1_MASK 0x00000002L |
42572 | #define GFX_IMU_TIMER0_CMP_INTEN__INT_EN2_MASK 0x00000004L |
42573 | #define GFX_IMU_TIMER0_CMP_INTEN__INT_EN3_MASK 0x00000008L |
42574 | //GFX_IMU_TIMER0_CMP0 |
42575 | #define GFX_IMU_TIMER0_CMP0__VALUE__SHIFT 0x0 |
42576 | #define GFX_IMU_TIMER0_CMP0__VALUE_MASK 0xFFFFFFFFL |
42577 | //GFX_IMU_TIMER0_CMP1 |
42578 | #define GFX_IMU_TIMER0_CMP1__VALUE__SHIFT 0x0 |
42579 | #define GFX_IMU_TIMER0_CMP1__VALUE_MASK 0xFFFFFFFFL |
42580 | //GFX_IMU_TIMER0_CMP3 |
42581 | #define GFX_IMU_TIMER0_CMP3__VALUE__SHIFT 0x0 |
42582 | #define GFX_IMU_TIMER0_CMP3__VALUE_MASK 0xFFFFFFFFL |
42583 | //GFX_IMU_TIMER0_VALUE |
42584 | #define GFX_IMU_TIMER0_VALUE__VALUE__SHIFT 0x0 |
42585 | #define GFX_IMU_TIMER0_VALUE__VALUE_MASK 0xFFFFFFFFL |
42586 | //GFX_IMU_TIMER1_CTRL0 |
42587 | #define GFX_IMU_TIMER1_CTRL0__START_STOP__SHIFT 0x0 |
42588 | #define GFX_IMU_TIMER1_CTRL0__CLEAR__SHIFT 0x8 |
42589 | #define GFX_IMU_TIMER1_CTRL0__UP_DOWN__SHIFT 0x10 |
42590 | #define GFX_IMU_TIMER1_CTRL0__PULSE_EN__SHIFT 0x18 |
42591 | #define GFX_IMU_TIMER1_CTRL0__START_STOP_MASK 0x00000001L |
42592 | #define GFX_IMU_TIMER1_CTRL0__CLEAR_MASK 0x00000100L |
42593 | #define GFX_IMU_TIMER1_CTRL0__UP_DOWN_MASK 0x00010000L |
42594 | #define GFX_IMU_TIMER1_CTRL0__PULSE_EN_MASK 0x01000000L |
42595 | //GFX_IMU_TIMER1_CTRL1 |
42596 | #define GFX_IMU_TIMER1_CTRL1__PWM_EN__SHIFT 0x0 |
42597 | #define GFX_IMU_TIMER1_CTRL1__TS_MODE__SHIFT 0x8 |
42598 | #define GFX_IMU_TIMER1_CTRL1__SAT_EN__SHIFT 0x10 |
42599 | #define GFX_IMU_TIMER1_CTRL1__PWM_EN_MASK 0x00000001L |
42600 | #define GFX_IMU_TIMER1_CTRL1__TS_MODE_MASK 0x00000100L |
42601 | #define GFX_IMU_TIMER1_CTRL1__SAT_EN_MASK 0x00010000L |
42602 | //GFX_IMU_TIMER1_CMP_AUTOINC |
42603 | #define GFX_IMU_TIMER1_CMP_AUTOINC__AUTOINC_EN0__SHIFT 0x0 |
42604 | #define GFX_IMU_TIMER1_CMP_AUTOINC__AUTOINC_EN1__SHIFT 0x1 |
42605 | #define GFX_IMU_TIMER1_CMP_AUTOINC__AUTOINC_EN2__SHIFT 0x2 |
42606 | #define GFX_IMU_TIMER1_CMP_AUTOINC__AUTOINC_EN3__SHIFT 0x3 |
42607 | #define GFX_IMU_TIMER1_CMP_AUTOINC__AUTOINC_EN0_MASK 0x00000001L |
42608 | #define GFX_IMU_TIMER1_CMP_AUTOINC__AUTOINC_EN1_MASK 0x00000002L |
42609 | #define GFX_IMU_TIMER1_CMP_AUTOINC__AUTOINC_EN2_MASK 0x00000004L |
42610 | #define GFX_IMU_TIMER1_CMP_AUTOINC__AUTOINC_EN3_MASK 0x00000008L |
42611 | //GFX_IMU_TIMER1_CMP_INTEN |
42612 | #define GFX_IMU_TIMER1_CMP_INTEN__INT_EN0__SHIFT 0x0 |
42613 | #define GFX_IMU_TIMER1_CMP_INTEN__INT_EN1__SHIFT 0x1 |
42614 | #define GFX_IMU_TIMER1_CMP_INTEN__INT_EN2__SHIFT 0x2 |
42615 | #define GFX_IMU_TIMER1_CMP_INTEN__INT_EN3__SHIFT 0x3 |
42616 | #define GFX_IMU_TIMER1_CMP_INTEN__INT_EN0_MASK 0x00000001L |
42617 | #define GFX_IMU_TIMER1_CMP_INTEN__INT_EN1_MASK 0x00000002L |
42618 | #define GFX_IMU_TIMER1_CMP_INTEN__INT_EN2_MASK 0x00000004L |
42619 | #define GFX_IMU_TIMER1_CMP_INTEN__INT_EN3_MASK 0x00000008L |
42620 | //GFX_IMU_TIMER1_CMP0 |
42621 | #define GFX_IMU_TIMER1_CMP0__VALUE__SHIFT 0x0 |
42622 | #define GFX_IMU_TIMER1_CMP0__VALUE_MASK 0xFFFFFFFFL |
42623 | //GFX_IMU_TIMER1_CMP1 |
42624 | #define GFX_IMU_TIMER1_CMP1__VALUE__SHIFT 0x0 |
42625 | #define GFX_IMU_TIMER1_CMP1__VALUE_MASK 0xFFFFFFFFL |
42626 | //GFX_IMU_TIMER1_CMP3 |
42627 | #define GFX_IMU_TIMER1_CMP3__VALUE__SHIFT 0x0 |
42628 | #define GFX_IMU_TIMER1_CMP3__VALUE_MASK 0xFFFFFFFFL |
42629 | //GFX_IMU_TIMER1_VALUE |
42630 | #define GFX_IMU_TIMER1_VALUE__VALUE__SHIFT 0x0 |
42631 | #define GFX_IMU_TIMER1_VALUE__VALUE_MASK 0xFFFFFFFFL |
42632 | //GFX_IMU_TIMER2_CTRL0 |
42633 | #define GFX_IMU_TIMER2_CTRL0__START_STOP__SHIFT 0x0 |
42634 | #define GFX_IMU_TIMER2_CTRL0__CLEAR__SHIFT 0x8 |
42635 | #define GFX_IMU_TIMER2_CTRL0__UP_DOWN__SHIFT 0x10 |
42636 | #define GFX_IMU_TIMER2_CTRL0__PULSE_EN__SHIFT 0x18 |
42637 | #define GFX_IMU_TIMER2_CTRL0__START_STOP_MASK 0x00000001L |
42638 | #define GFX_IMU_TIMER2_CTRL0__CLEAR_MASK 0x00000100L |
42639 | #define GFX_IMU_TIMER2_CTRL0__UP_DOWN_MASK 0x00010000L |
42640 | #define GFX_IMU_TIMER2_CTRL0__PULSE_EN_MASK 0x01000000L |
42641 | //GFX_IMU_TIMER2_CTRL1 |
42642 | #define GFX_IMU_TIMER2_CTRL1__PWM_EN__SHIFT 0x0 |
42643 | #define GFX_IMU_TIMER2_CTRL1__TS_MODE__SHIFT 0x8 |
42644 | #define GFX_IMU_TIMER2_CTRL1__SAT_EN__SHIFT 0x10 |
42645 | #define GFX_IMU_TIMER2_CTRL1__PWM_EN_MASK 0x00000001L |
42646 | #define GFX_IMU_TIMER2_CTRL1__TS_MODE_MASK 0x00000100L |
42647 | #define GFX_IMU_TIMER2_CTRL1__SAT_EN_MASK 0x00010000L |
42648 | //GFX_IMU_TIMER2_CMP_AUTOINC |
42649 | #define GFX_IMU_TIMER2_CMP_AUTOINC__AUTOINC_EN0__SHIFT 0x0 |
42650 | #define GFX_IMU_TIMER2_CMP_AUTOINC__AUTOINC_EN1__SHIFT 0x1 |
42651 | #define GFX_IMU_TIMER2_CMP_AUTOINC__AUTOINC_EN2__SHIFT 0x2 |
42652 | #define GFX_IMU_TIMER2_CMP_AUTOINC__AUTOINC_EN3__SHIFT 0x3 |
42653 | #define GFX_IMU_TIMER2_CMP_AUTOINC__AUTOINC_EN0_MASK 0x00000001L |
42654 | #define GFX_IMU_TIMER2_CMP_AUTOINC__AUTOINC_EN1_MASK 0x00000002L |
42655 | #define GFX_IMU_TIMER2_CMP_AUTOINC__AUTOINC_EN2_MASK 0x00000004L |
42656 | #define GFX_IMU_TIMER2_CMP_AUTOINC__AUTOINC_EN3_MASK 0x00000008L |
42657 | //GFX_IMU_TIMER2_CMP_INTEN |
42658 | #define GFX_IMU_TIMER2_CMP_INTEN__INT_EN0__SHIFT 0x0 |
42659 | #define GFX_IMU_TIMER2_CMP_INTEN__INT_EN1__SHIFT 0x1 |
42660 | #define GFX_IMU_TIMER2_CMP_INTEN__INT_EN2__SHIFT 0x2 |
42661 | #define GFX_IMU_TIMER2_CMP_INTEN__INT_EN3__SHIFT 0x3 |
42662 | #define GFX_IMU_TIMER2_CMP_INTEN__INT_EN0_MASK 0x00000001L |
42663 | #define GFX_IMU_TIMER2_CMP_INTEN__INT_EN1_MASK 0x00000002L |
42664 | #define GFX_IMU_TIMER2_CMP_INTEN__INT_EN2_MASK 0x00000004L |
42665 | #define GFX_IMU_TIMER2_CMP_INTEN__INT_EN3_MASK 0x00000008L |
42666 | //GFX_IMU_TIMER2_CMP0 |
42667 | #define GFX_IMU_TIMER2_CMP0__VALUE__SHIFT 0x0 |
42668 | #define GFX_IMU_TIMER2_CMP0__VALUE_MASK 0xFFFFFFFFL |
42669 | //GFX_IMU_TIMER2_CMP1 |
42670 | #define GFX_IMU_TIMER2_CMP1__VALUE__SHIFT 0x0 |
42671 | #define GFX_IMU_TIMER2_CMP1__VALUE_MASK 0xFFFFFFFFL |
42672 | //GFX_IMU_TIMER2_CMP3 |
42673 | #define GFX_IMU_TIMER2_CMP3__VALUE__SHIFT 0x0 |
42674 | #define GFX_IMU_TIMER2_CMP3__VALUE_MASK 0xFFFFFFFFL |
42675 | //GFX_IMU_TIMER2_VALUE |
42676 | #define GFX_IMU_TIMER2_VALUE__VALUE__SHIFT 0x0 |
42677 | #define GFX_IMU_TIMER2_VALUE__VALUE_MASK 0xFFFFFFFFL |
42678 | //GFX_IMU_FUSE_CTRL |
42679 | #define GFX_IMU_FUSE_CTRL__DIV_OVR__SHIFT 0x0 |
42680 | #define GFX_IMU_FUSE_CTRL__DIV_OVR_EN__SHIFT 0x5 |
42681 | #define GFX_IMU_FUSE_CTRL__FORCE_DONE__SHIFT 0x6 |
42682 | #define GFX_IMU_FUSE_CTRL__DIV_OVR_MASK 0x0000001FL |
42683 | #define GFX_IMU_FUSE_CTRL__DIV_OVR_EN_MASK 0x00000020L |
42684 | #define GFX_IMU_FUSE_CTRL__FORCE_DONE_MASK 0x00000040L |
42685 | //GFX_IMU_D_RAM_ADDR |
42686 | #define GFX_IMU_D_RAM_ADDR__ADDR__SHIFT 0x2 |
42687 | #define GFX_IMU_D_RAM_ADDR__ADDR_MASK 0x0000FFFCL |
42688 | //GFX_IMU_D_RAM_DATA |
42689 | #define GFX_IMU_D_RAM_DATA__DATA__SHIFT 0x0 |
42690 | #define GFX_IMU_D_RAM_DATA__DATA_MASK 0xFFFFFFFFL |
42691 | //GFX_IMU_GFX_IH_GASKET_CTRL |
42692 | #define GFX_IMU_GFX_IH_GASKET_CTRL__SRSTB__SHIFT 0x0 |
42693 | #define GFX_IMU_GFX_IH_GASKET_CTRL__BUFFER_LEVEL__SHIFT 0x10 |
42694 | #define GFX_IMU_GFX_IH_GASKET_CTRL__BUFFER_OVERFLOW__SHIFT 0x14 |
42695 | #define GFX_IMU_GFX_IH_GASKET_CTRL__SRSTB_MASK 0x00000001L |
42696 | #define GFX_IMU_GFX_IH_GASKET_CTRL__BUFFER_LEVEL_MASK 0x000F0000L |
42697 | #define GFX_IMU_GFX_IH_GASKET_CTRL__BUFFER_OVERFLOW_MASK 0x00100000L |
42698 | |
42699 | |
42700 | // addressBlock: gc_gfx_imu_gfx_imu_pspdec |
42701 | //GFX_IMU_RLC_BOOTLOADER_ADDR_HI |
42702 | #define GFX_IMU_RLC_BOOTLOADER_ADDR_HI__ADDR_HI__SHIFT 0x0 |
42703 | #define GFX_IMU_RLC_BOOTLOADER_ADDR_HI__ADDR_HI_MASK 0xFFFFFFFFL |
42704 | //GFX_IMU_RLC_BOOTLOADER_ADDR_LO |
42705 | #define GFX_IMU_RLC_BOOTLOADER_ADDR_LO__ADDR_LO__SHIFT 0x0 |
42706 | #define GFX_IMU_RLC_BOOTLOADER_ADDR_LO__ADDR_LO_MASK 0xFFFFFFFFL |
42707 | //GFX_IMU_RLC_BOOTLOADER_SIZE |
42708 | #define GFX_IMU_RLC_BOOTLOADER_SIZE__SIZE__SHIFT 0x0 |
42709 | #define GFX_IMU_RLC_BOOTLOADER_SIZE__SIZE_MASK 0x03FFFFFFL |
42710 | //GFX_IMU_I_RAM_ADDR |
42711 | #define GFX_IMU_I_RAM_ADDR__ADDR__SHIFT 0x2 |
42712 | #define GFX_IMU_I_RAM_ADDR__ADDR_MASK 0x0000FFFCL |
42713 | //GFX_IMU_I_RAM_DATA |
42714 | #define GFX_IMU_I_RAM_DATA__DATA__SHIFT 0x0 |
42715 | #define GFX_IMU_I_RAM_DATA__DATA_MASK 0xFFFFFFFFL |
42716 | |
42717 | |
42718 | // addressBlock: gccacind |
42719 | //GC_CAC_ID |
42720 | #define GC_CAC_ID__CAC_BLOCK_ID__SHIFT 0x0 |
42721 | #define GC_CAC_ID__CAC_SIGNAL_ID__SHIFT 0x6 |
42722 | #define GC_CAC_ID__CAC_BLOCK_ID_MASK 0x0000003FL |
42723 | #define GC_CAC_ID__CAC_SIGNAL_ID_MASK 0x00003FC0L |
42724 | //GC_CAC_CNTL |
42725 | #define GC_CAC_CNTL__CAC_THRESHOLD__SHIFT 0x0 |
42726 | #define GC_CAC_CNTL__CAC_THRESHOLD_MASK 0x0000FFFFL |
42727 | //GC_CAC_ACC_CP0 |
42728 | #define GC_CAC_ACC_CP0__ACCUMULATOR_31_0__SHIFT 0x0 |
42729 | #define GC_CAC_ACC_CP0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
42730 | //GC_CAC_ACC_CP1 |
42731 | #define GC_CAC_ACC_CP1__ACCUMULATOR_31_0__SHIFT 0x0 |
42732 | #define GC_CAC_ACC_CP1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
42733 | //GC_CAC_ACC_CP2 |
42734 | #define GC_CAC_ACC_CP2__ACCUMULATOR_31_0__SHIFT 0x0 |
42735 | #define GC_CAC_ACC_CP2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
42736 | //GC_CAC_ACC_EA0 |
42737 | #define GC_CAC_ACC_EA0__ACCUMULATOR_31_0__SHIFT 0x0 |
42738 | #define GC_CAC_ACC_EA0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
42739 | //GC_CAC_ACC_EA1 |
42740 | #define GC_CAC_ACC_EA1__ACCUMULATOR_31_0__SHIFT 0x0 |
42741 | #define GC_CAC_ACC_EA1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
42742 | //GC_CAC_ACC_EA2 |
42743 | #define GC_CAC_ACC_EA2__ACCUMULATOR_31_0__SHIFT 0x0 |
42744 | #define GC_CAC_ACC_EA2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
42745 | //GC_CAC_ACC_EA3 |
42746 | #define GC_CAC_ACC_EA3__ACCUMULATOR_31_0__SHIFT 0x0 |
42747 | #define GC_CAC_ACC_EA3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
42748 | //GC_CAC_ACC_EA4 |
42749 | #define GC_CAC_ACC_EA4__ACCUMULATOR_31_0__SHIFT 0x0 |
42750 | #define GC_CAC_ACC_EA4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
42751 | //GC_CAC_ACC_EA5 |
42752 | #define GC_CAC_ACC_EA5__ACCUMULATOR_31_0__SHIFT 0x0 |
42753 | #define GC_CAC_ACC_EA5__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
42754 | //GC_CAC_ACC_UTCL2_ROUTER0 |
42755 | #define GC_CAC_ACC_UTCL2_ROUTER0__ACCUMULATOR_31_0__SHIFT 0x0 |
42756 | #define GC_CAC_ACC_UTCL2_ROUTER0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
42757 | //GC_CAC_ACC_UTCL2_ROUTER1 |
42758 | #define GC_CAC_ACC_UTCL2_ROUTER1__ACCUMULATOR_31_0__SHIFT 0x0 |
42759 | #define GC_CAC_ACC_UTCL2_ROUTER1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
42760 | //GC_CAC_ACC_UTCL2_ROUTER2 |
42761 | #define GC_CAC_ACC_UTCL2_ROUTER2__ACCUMULATOR_31_0__SHIFT 0x0 |
42762 | #define GC_CAC_ACC_UTCL2_ROUTER2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
42763 | //GC_CAC_ACC_UTCL2_ROUTER3 |
42764 | #define GC_CAC_ACC_UTCL2_ROUTER3__ACCUMULATOR_31_0__SHIFT 0x0 |
42765 | #define GC_CAC_ACC_UTCL2_ROUTER3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
42766 | //GC_CAC_ACC_UTCL2_ROUTER4 |
42767 | #define GC_CAC_ACC_UTCL2_ROUTER4__ACCUMULATOR_31_0__SHIFT 0x0 |
42768 | #define GC_CAC_ACC_UTCL2_ROUTER4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
42769 | //GC_CAC_ACC_UTCL2_ROUTER5 |
42770 | #define GC_CAC_ACC_UTCL2_ROUTER5__ACCUMULATOR_31_0__SHIFT 0x0 |
42771 | #define GC_CAC_ACC_UTCL2_ROUTER5__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
42772 | //GC_CAC_ACC_UTCL2_ROUTER6 |
42773 | #define GC_CAC_ACC_UTCL2_ROUTER6__ACCUMULATOR_31_0__SHIFT 0x0 |
42774 | #define GC_CAC_ACC_UTCL2_ROUTER6__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
42775 | //GC_CAC_ACC_UTCL2_ROUTER7 |
42776 | #define GC_CAC_ACC_UTCL2_ROUTER7__ACCUMULATOR_31_0__SHIFT 0x0 |
42777 | #define GC_CAC_ACC_UTCL2_ROUTER7__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
42778 | //GC_CAC_ACC_UTCL2_ROUTER8 |
42779 | #define GC_CAC_ACC_UTCL2_ROUTER8__ACCUMULATOR_31_0__SHIFT 0x0 |
42780 | #define GC_CAC_ACC_UTCL2_ROUTER8__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
42781 | //GC_CAC_ACC_UTCL2_ROUTER9 |
42782 | #define GC_CAC_ACC_UTCL2_ROUTER9__ACCUMULATOR_31_0__SHIFT 0x0 |
42783 | #define GC_CAC_ACC_UTCL2_ROUTER9__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
42784 | //GC_CAC_ACC_UTCL2_VML20 |
42785 | #define GC_CAC_ACC_UTCL2_VML20__ACCUMULATOR_31_0__SHIFT 0x0 |
42786 | #define GC_CAC_ACC_UTCL2_VML20__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
42787 | //GC_CAC_ACC_UTCL2_VML21 |
42788 | #define GC_CAC_ACC_UTCL2_VML21__ACCUMULATOR_31_0__SHIFT 0x0 |
42789 | #define GC_CAC_ACC_UTCL2_VML21__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
42790 | //GC_CAC_ACC_UTCL2_VML22 |
42791 | #define GC_CAC_ACC_UTCL2_VML22__ACCUMULATOR_31_0__SHIFT 0x0 |
42792 | #define GC_CAC_ACC_UTCL2_VML22__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
42793 | //GC_CAC_ACC_UTCL2_VML23 |
42794 | #define GC_CAC_ACC_UTCL2_VML23__ACCUMULATOR_31_0__SHIFT 0x0 |
42795 | #define GC_CAC_ACC_UTCL2_VML23__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
42796 | //GC_CAC_ACC_UTCL2_VML24 |
42797 | #define GC_CAC_ACC_UTCL2_VML24__ACCUMULATOR_31_0__SHIFT 0x0 |
42798 | #define GC_CAC_ACC_UTCL2_VML24__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
42799 | //GC_CAC_ACC_UTCL2_WALKER0 |
42800 | #define GC_CAC_ACC_UTCL2_WALKER0__ACCUMULATOR_31_0__SHIFT 0x0 |
42801 | #define GC_CAC_ACC_UTCL2_WALKER0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
42802 | //GC_CAC_ACC_UTCL2_WALKER1 |
42803 | #define GC_CAC_ACC_UTCL2_WALKER1__ACCUMULATOR_31_0__SHIFT 0x0 |
42804 | #define GC_CAC_ACC_UTCL2_WALKER1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
42805 | //GC_CAC_ACC_UTCL2_WALKER2 |
42806 | #define GC_CAC_ACC_UTCL2_WALKER2__ACCUMULATOR_31_0__SHIFT 0x0 |
42807 | #define GC_CAC_ACC_UTCL2_WALKER2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
42808 | //GC_CAC_ACC_UTCL2_WALKER3 |
42809 | #define GC_CAC_ACC_UTCL2_WALKER3__ACCUMULATOR_31_0__SHIFT 0x0 |
42810 | #define GC_CAC_ACC_UTCL2_WALKER3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
42811 | //GC_CAC_ACC_UTCL2_WALKER4 |
42812 | #define GC_CAC_ACC_UTCL2_WALKER4__ACCUMULATOR_31_0__SHIFT 0x0 |
42813 | #define GC_CAC_ACC_UTCL2_WALKER4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
42814 | //GC_CAC_ACC_GDS0 |
42815 | #define GC_CAC_ACC_GDS0__ACCUMULATOR_31_0__SHIFT 0x0 |
42816 | #define GC_CAC_ACC_GDS0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
42817 | //GC_CAC_ACC_GDS1 |
42818 | #define GC_CAC_ACC_GDS1__ACCUMULATOR_31_0__SHIFT 0x0 |
42819 | #define GC_CAC_ACC_GDS1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
42820 | //GC_CAC_ACC_GDS2 |
42821 | #define GC_CAC_ACC_GDS2__ACCUMULATOR_31_0__SHIFT 0x0 |
42822 | #define GC_CAC_ACC_GDS2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
42823 | //GC_CAC_ACC_GDS3 |
42824 | #define GC_CAC_ACC_GDS3__ACCUMULATOR_31_0__SHIFT 0x0 |
42825 | #define GC_CAC_ACC_GDS3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
42826 | //GC_CAC_ACC_GDS4 |
42827 | #define GC_CAC_ACC_GDS4__ACCUMULATOR_31_0__SHIFT 0x0 |
42828 | #define GC_CAC_ACC_GDS4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
42829 | //GC_CAC_ACC_GE0 |
42830 | #define GC_CAC_ACC_GE0__ACCUMULATOR_31_0__SHIFT 0x0 |
42831 | #define GC_CAC_ACC_GE0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
42832 | //GC_CAC_ACC_GE1 |
42833 | #define GC_CAC_ACC_GE1__ACCUMULATOR_31_0__SHIFT 0x0 |
42834 | #define GC_CAC_ACC_GE1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
42835 | //GC_CAC_ACC_GE2 |
42836 | #define GC_CAC_ACC_GE2__ACCUMULATOR_31_0__SHIFT 0x0 |
42837 | #define GC_CAC_ACC_GE2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
42838 | //GC_CAC_ACC_GE3 |
42839 | #define GC_CAC_ACC_GE3__ACCUMULATOR_31_0__SHIFT 0x0 |
42840 | #define GC_CAC_ACC_GE3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
42841 | //GC_CAC_ACC_GE4 |
42842 | #define GC_CAC_ACC_GE4__ACCUMULATOR_31_0__SHIFT 0x0 |
42843 | #define GC_CAC_ACC_GE4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
42844 | //GC_CAC_ACC_GE5 |
42845 | #define GC_CAC_ACC_GE5__ACCUMULATOR_31_0__SHIFT 0x0 |
42846 | #define GC_CAC_ACC_GE5__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
42847 | //GC_CAC_ACC_GE6 |
42848 | #define GC_CAC_ACC_GE6__ACCUMULATOR_31_0__SHIFT 0x0 |
42849 | #define GC_CAC_ACC_GE6__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
42850 | //GC_CAC_ACC_GE7 |
42851 | #define GC_CAC_ACC_GE7__ACCUMULATOR_31_0__SHIFT 0x0 |
42852 | #define GC_CAC_ACC_GE7__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
42853 | //GC_CAC_ACC_GE8 |
42854 | #define GC_CAC_ACC_GE8__ACCUMULATOR_31_0__SHIFT 0x0 |
42855 | #define GC_CAC_ACC_GE8__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
42856 | //GC_CAC_ACC_GE9 |
42857 | #define GC_CAC_ACC_GE9__ACCUMULATOR_31_0__SHIFT 0x0 |
42858 | #define GC_CAC_ACC_GE9__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
42859 | //GC_CAC_ACC_GE10 |
42860 | #define GC_CAC_ACC_GE10__ACCUMULATOR_31_0__SHIFT 0x0 |
42861 | #define GC_CAC_ACC_GE10__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
42862 | //GC_CAC_ACC_GE11 |
42863 | #define GC_CAC_ACC_GE11__ACCUMULATOR_31_0__SHIFT 0x0 |
42864 | #define GC_CAC_ACC_GE11__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
42865 | //GC_CAC_ACC_GE12 |
42866 | #define GC_CAC_ACC_GE12__ACCUMULATOR_31_0__SHIFT 0x0 |
42867 | #define GC_CAC_ACC_GE12__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
42868 | //GC_CAC_ACC_GE13 |
42869 | #define GC_CAC_ACC_GE13__ACCUMULATOR_31_0__SHIFT 0x0 |
42870 | #define GC_CAC_ACC_GE13__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
42871 | //GC_CAC_ACC_GE14 |
42872 | #define GC_CAC_ACC_GE14__ACCUMULATOR_31_0__SHIFT 0x0 |
42873 | #define GC_CAC_ACC_GE14__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
42874 | //GC_CAC_ACC_GE15 |
42875 | #define GC_CAC_ACC_GE15__ACCUMULATOR_31_0__SHIFT 0x0 |
42876 | #define GC_CAC_ACC_GE15__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
42877 | //GC_CAC_ACC_GE16 |
42878 | #define GC_CAC_ACC_GE16__ACCUMULATOR_31_0__SHIFT 0x0 |
42879 | #define GC_CAC_ACC_GE16__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
42880 | //GC_CAC_ACC_GE17 |
42881 | #define GC_CAC_ACC_GE17__ACCUMULATOR_31_0__SHIFT 0x0 |
42882 | #define GC_CAC_ACC_GE17__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
42883 | //GC_CAC_ACC_GE18 |
42884 | #define GC_CAC_ACC_GE18__ACCUMULATOR_31_0__SHIFT 0x0 |
42885 | #define GC_CAC_ACC_GE18__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
42886 | //GC_CAC_ACC_GE19 |
42887 | #define GC_CAC_ACC_GE19__ACCUMULATOR_31_0__SHIFT 0x0 |
42888 | #define GC_CAC_ACC_GE19__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
42889 | //GC_CAC_ACC_GE20 |
42890 | #define GC_CAC_ACC_GE20__ACCUMULATOR_31_0__SHIFT 0x0 |
42891 | #define GC_CAC_ACC_GE20__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
42892 | //GC_CAC_ACC_PMM0 |
42893 | #define GC_CAC_ACC_PMM0__ACCUMULATOR_31_0__SHIFT 0x0 |
42894 | #define GC_CAC_ACC_PMM0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
42895 | //GC_CAC_ACC_GL2C0 |
42896 | #define GC_CAC_ACC_GL2C0__ACCUMULATOR_31_0__SHIFT 0x0 |
42897 | #define GC_CAC_ACC_GL2C0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
42898 | //GC_CAC_ACC_GL2C1 |
42899 | #define GC_CAC_ACC_GL2C1__ACCUMULATOR_31_0__SHIFT 0x0 |
42900 | #define GC_CAC_ACC_GL2C1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
42901 | //GC_CAC_ACC_GL2C2 |
42902 | #define GC_CAC_ACC_GL2C2__ACCUMULATOR_31_0__SHIFT 0x0 |
42903 | #define GC_CAC_ACC_GL2C2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
42904 | //GC_CAC_ACC_GL2C3 |
42905 | #define GC_CAC_ACC_GL2C3__ACCUMULATOR_31_0__SHIFT 0x0 |
42906 | #define GC_CAC_ACC_GL2C3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
42907 | //GC_CAC_ACC_GL2C4 |
42908 | #define GC_CAC_ACC_GL2C4__ACCUMULATOR_31_0__SHIFT 0x0 |
42909 | #define GC_CAC_ACC_GL2C4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
42910 | //GC_CAC_ACC_PH0 |
42911 | #define GC_CAC_ACC_PH0__ACCUMULATOR_31_0__SHIFT 0x0 |
42912 | #define GC_CAC_ACC_PH0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
42913 | //GC_CAC_ACC_PH1 |
42914 | #define GC_CAC_ACC_PH1__ACCUMULATOR_31_0__SHIFT 0x0 |
42915 | #define GC_CAC_ACC_PH1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
42916 | //GC_CAC_ACC_PH2 |
42917 | #define GC_CAC_ACC_PH2__ACCUMULATOR_31_0__SHIFT 0x0 |
42918 | #define GC_CAC_ACC_PH2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
42919 | //GC_CAC_ACC_PH3 |
42920 | #define GC_CAC_ACC_PH3__ACCUMULATOR_31_0__SHIFT 0x0 |
42921 | #define GC_CAC_ACC_PH3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
42922 | //GC_CAC_ACC_PH4 |
42923 | #define GC_CAC_ACC_PH4__ACCUMULATOR_31_0__SHIFT 0x0 |
42924 | #define GC_CAC_ACC_PH4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
42925 | //GC_CAC_ACC_PH5 |
42926 | #define GC_CAC_ACC_PH5__ACCUMULATOR_31_0__SHIFT 0x0 |
42927 | #define GC_CAC_ACC_PH5__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
42928 | //GC_CAC_ACC_PH6 |
42929 | #define GC_CAC_ACC_PH6__ACCUMULATOR_31_0__SHIFT 0x0 |
42930 | #define GC_CAC_ACC_PH6__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
42931 | //GC_CAC_ACC_PH7 |
42932 | #define GC_CAC_ACC_PH7__ACCUMULATOR_31_0__SHIFT 0x0 |
42933 | #define GC_CAC_ACC_PH7__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
42934 | //GC_CAC_ACC_SDMA0 |
42935 | #define GC_CAC_ACC_SDMA0__ACCUMULATOR_31_0__SHIFT 0x0 |
42936 | #define GC_CAC_ACC_SDMA0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
42937 | //GC_CAC_ACC_SDMA1 |
42938 | #define GC_CAC_ACC_SDMA1__ACCUMULATOR_31_0__SHIFT 0x0 |
42939 | #define GC_CAC_ACC_SDMA1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
42940 | //GC_CAC_ACC_SDMA2 |
42941 | #define GC_CAC_ACC_SDMA2__ACCUMULATOR_31_0__SHIFT 0x0 |
42942 | #define GC_CAC_ACC_SDMA2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
42943 | //GC_CAC_ACC_SDMA3 |
42944 | #define GC_CAC_ACC_SDMA3__ACCUMULATOR_31_0__SHIFT 0x0 |
42945 | #define GC_CAC_ACC_SDMA3__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
42946 | //GC_CAC_ACC_SDMA4 |
42947 | #define GC_CAC_ACC_SDMA4__ACCUMULATOR_31_0__SHIFT 0x0 |
42948 | #define GC_CAC_ACC_SDMA4__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
42949 | //GC_CAC_ACC_SDMA5 |
42950 | #define GC_CAC_ACC_SDMA5__ACCUMULATOR_31_0__SHIFT 0x0 |
42951 | #define GC_CAC_ACC_SDMA5__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
42952 | //GC_CAC_ACC_SDMA6 |
42953 | #define GC_CAC_ACC_SDMA6__ACCUMULATOR_31_0__SHIFT 0x0 |
42954 | #define GC_CAC_ACC_SDMA6__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
42955 | //GC_CAC_ACC_SDMA7 |
42956 | #define GC_CAC_ACC_SDMA7__ACCUMULATOR_31_0__SHIFT 0x0 |
42957 | #define GC_CAC_ACC_SDMA7__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
42958 | //GC_CAC_ACC_SDMA8 |
42959 | #define GC_CAC_ACC_SDMA8__ACCUMULATOR_31_0__SHIFT 0x0 |
42960 | #define GC_CAC_ACC_SDMA8__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
42961 | //GC_CAC_ACC_SDMA9 |
42962 | #define GC_CAC_ACC_SDMA9__ACCUMULATOR_31_0__SHIFT 0x0 |
42963 | #define GC_CAC_ACC_SDMA9__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
42964 | //GC_CAC_ACC_SDMA10 |
42965 | #define GC_CAC_ACC_SDMA10__ACCUMULATOR_31_0__SHIFT 0x0 |
42966 | #define GC_CAC_ACC_SDMA10__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
42967 | //GC_CAC_ACC_SDMA11 |
42968 | #define GC_CAC_ACC_SDMA11__ACCUMULATOR_31_0__SHIFT 0x0 |
42969 | #define GC_CAC_ACC_SDMA11__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
42970 | //GC_CAC_ACC_CHC0 |
42971 | #define GC_CAC_ACC_CHC0__ACCUMULATOR_31_0__SHIFT 0x0 |
42972 | #define GC_CAC_ACC_CHC0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
42973 | //GC_CAC_ACC_CHC1 |
42974 | #define GC_CAC_ACC_CHC1__ACCUMULATOR_31_0__SHIFT 0x0 |
42975 | #define GC_CAC_ACC_CHC1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
42976 | //GC_CAC_ACC_CHC2 |
42977 | #define GC_CAC_ACC_CHC2__ACCUMULATOR_31_0__SHIFT 0x0 |
42978 | #define GC_CAC_ACC_CHC2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
42979 | //GC_CAC_ACC_GUS0 |
42980 | #define GC_CAC_ACC_GUS0__ACCUMULATOR_31_0__SHIFT 0x0 |
42981 | #define GC_CAC_ACC_GUS0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
42982 | //GC_CAC_ACC_GUS1 |
42983 | #define GC_CAC_ACC_GUS1__ACCUMULATOR_31_0__SHIFT 0x0 |
42984 | #define GC_CAC_ACC_GUS1__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
42985 | //GC_CAC_ACC_GUS2 |
42986 | #define GC_CAC_ACC_GUS2__ACCUMULATOR_31_0__SHIFT 0x0 |
42987 | #define GC_CAC_ACC_GUS2__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
42988 | //GC_CAC_ACC_RLC0 |
42989 | #define GC_CAC_ACC_RLC0__ACCUMULATOR_31_0__SHIFT 0x0 |
42990 | #define GC_CAC_ACC_RLC0__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
42991 | //GC_CAC_ACC_UTCL2_ATCL20 |
42992 | #define GC_CAC_ACC_UTCL2_ATCL20__ACCUMULATOR_31_0__SHIFT 0x0 |
42993 | #define GC_CAC_ACC_UTCL2_ATCL20__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
42994 | //GC_CAC_ACC_UTCL2_ATCL21 |
42995 | #define GC_CAC_ACC_UTCL2_ATCL21__ACCUMULATOR_31_0__SHIFT 0x0 |
42996 | #define GC_CAC_ACC_UTCL2_ATCL21__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
42997 | //GC_CAC_ACC_UTCL2_ATCL22 |
42998 | #define GC_CAC_ACC_UTCL2_ATCL22__ACCUMULATOR_31_0__SHIFT 0x0 |
42999 | #define GC_CAC_ACC_UTCL2_ATCL22__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
43000 | //GC_CAC_ACC_UTCL2_ATCL23 |
43001 | #define GC_CAC_ACC_UTCL2_ATCL23__ACCUMULATOR_31_0__SHIFT 0x0 |
43002 | #define GC_CAC_ACC_UTCL2_ATCL23__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
43003 | //GC_CAC_ACC_UTCL2_ATCL24 |
43004 | #define GC_CAC_ACC_UTCL2_ATCL24__ACCUMULATOR_31_0__SHIFT 0x0 |
43005 | #define GC_CAC_ACC_UTCL2_ATCL24__ACCUMULATOR_31_0_MASK 0xFFFFFFFFL |
43006 | //RELEASE_TO_STALL_LUT_1_8 |
43007 | #define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_1__SHIFT 0x0 |
43008 | #define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_2__SHIFT 0x4 |
43009 | #define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_3__SHIFT 0x8 |
43010 | #define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_4__SHIFT 0xc |
43011 | #define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_5__SHIFT 0x10 |
43012 | #define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_6__SHIFT 0x14 |
43013 | #define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_7__SHIFT 0x18 |
43014 | #define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_8__SHIFT 0x1c |
43015 | #define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_1_MASK 0x00000007L |
43016 | #define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_2_MASK 0x00000070L |
43017 | #define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_3_MASK 0x00000700L |
43018 | #define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_4_MASK 0x00007000L |
43019 | #define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_5_MASK 0x00070000L |
43020 | #define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_6_MASK 0x00700000L |
43021 | #define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_7_MASK 0x07000000L |
43022 | #define RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_8_MASK 0x70000000L |
43023 | //RELEASE_TO_STALL_LUT_9_16 |
43024 | #define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_9__SHIFT 0x0 |
43025 | #define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_10__SHIFT 0x4 |
43026 | #define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_11__SHIFT 0x8 |
43027 | #define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_12__SHIFT 0xc |
43028 | #define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_13__SHIFT 0x10 |
43029 | #define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_14__SHIFT 0x14 |
43030 | #define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_15__SHIFT 0x18 |
43031 | #define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_16__SHIFT 0x1c |
43032 | #define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_9_MASK 0x00000007L |
43033 | #define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_10_MASK 0x00000070L |
43034 | #define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_11_MASK 0x00000700L |
43035 | #define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_12_MASK 0x00007000L |
43036 | #define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_13_MASK 0x00070000L |
43037 | #define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_14_MASK 0x00700000L |
43038 | #define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_15_MASK 0x07000000L |
43039 | #define RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_16_MASK 0x70000000L |
43040 | //RELEASE_TO_STALL_LUT_17_20 |
43041 | #define RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_17__SHIFT 0x0 |
43042 | #define RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_18__SHIFT 0x4 |
43043 | #define RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_19__SHIFT 0x8 |
43044 | #define RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_20__SHIFT 0xc |
43045 | #define RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_17_MASK 0x00000007L |
43046 | #define RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_18_MASK 0x00000070L |
43047 | #define RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_19_MASK 0x00000700L |
43048 | #define RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_20_MASK 0x00007000L |
43049 | //STALL_TO_RELEASE_LUT_1_4 |
43050 | #define STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_1__SHIFT 0x0 |
43051 | #define STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_2__SHIFT 0x8 |
43052 | #define STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_3__SHIFT 0x10 |
43053 | #define STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_4__SHIFT 0x18 |
43054 | #define STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_1_MASK 0x0000001FL |
43055 | #define STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_2_MASK 0x00001F00L |
43056 | #define STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_3_MASK 0x001F0000L |
43057 | #define STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_4_MASK 0x1F000000L |
43058 | //STALL_TO_RELEASE_LUT_5_7 |
43059 | #define STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_5__SHIFT 0x0 |
43060 | #define STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_6__SHIFT 0x8 |
43061 | #define STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_7__SHIFT 0x10 |
43062 | #define STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_5_MASK 0x0000001FL |
43063 | #define STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_6_MASK 0x00001F00L |
43064 | #define STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_7_MASK 0x001F0000L |
43065 | //STALL_TO_PWRBRK_LUT_1_4 |
43066 | #define STALL_TO_PWRBRK_LUT_1_4__FIRST_PATTERN_1__SHIFT 0x0 |
43067 | #define STALL_TO_PWRBRK_LUT_1_4__FIRST_PATTERN_2__SHIFT 0x8 |
43068 | #define STALL_TO_PWRBRK_LUT_1_4__FIRST_PATTERN_3__SHIFT 0x10 |
43069 | #define STALL_TO_PWRBRK_LUT_1_4__FIRST_PATTERN_4__SHIFT 0x18 |
43070 | #define STALL_TO_PWRBRK_LUT_1_4__FIRST_PATTERN_1_MASK 0x00000007L |
43071 | #define STALL_TO_PWRBRK_LUT_1_4__FIRST_PATTERN_2_MASK 0x00000700L |
43072 | #define STALL_TO_PWRBRK_LUT_1_4__FIRST_PATTERN_3_MASK 0x00070000L |
43073 | #define STALL_TO_PWRBRK_LUT_1_4__FIRST_PATTERN_4_MASK 0x07000000L |
43074 | //STALL_TO_PWRBRK_LUT_5_7 |
43075 | #define STALL_TO_PWRBRK_LUT_5_7__FIRST_PATTERN_5__SHIFT 0x0 |
43076 | #define STALL_TO_PWRBRK_LUT_5_7__FIRST_PATTERN_6__SHIFT 0x8 |
43077 | #define STALL_TO_PWRBRK_LUT_5_7__FIRST_PATTERN_7__SHIFT 0x10 |
43078 | #define STALL_TO_PWRBRK_LUT_5_7__FIRST_PATTERN_5_MASK 0x00000007L |
43079 | #define STALL_TO_PWRBRK_LUT_5_7__FIRST_PATTERN_6_MASK 0x00000700L |
43080 | #define STALL_TO_PWRBRK_LUT_5_7__FIRST_PATTERN_7_MASK 0x00070000L |
43081 | //PWRBRK_STALL_TO_RELEASE_LUT_1_4 |
43082 | #define PWRBRK_STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_1__SHIFT 0x0 |
43083 | #define PWRBRK_STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_2__SHIFT 0x8 |
43084 | #define PWRBRK_STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_3__SHIFT 0x10 |
43085 | #define PWRBRK_STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_4__SHIFT 0x18 |
43086 | #define PWRBRK_STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_1_MASK 0x0000001FL |
43087 | #define PWRBRK_STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_2_MASK 0x00001F00L |
43088 | #define PWRBRK_STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_3_MASK 0x001F0000L |
43089 | #define PWRBRK_STALL_TO_RELEASE_LUT_1_4__FIRST_PATTERN_4_MASK 0x1F000000L |
43090 | //PWRBRK_STALL_TO_RELEASE_LUT_5_7 |
43091 | #define PWRBRK_STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_5__SHIFT 0x0 |
43092 | #define PWRBRK_STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_6__SHIFT 0x8 |
43093 | #define PWRBRK_STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_7__SHIFT 0x10 |
43094 | #define PWRBRK_STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_5_MASK 0x0000001FL |
43095 | #define PWRBRK_STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_6_MASK 0x00001F00L |
43096 | #define PWRBRK_STALL_TO_RELEASE_LUT_5_7__FIRST_PATTERN_7_MASK 0x001F0000L |
43097 | //PWRBRK_RELEASE_TO_STALL_LUT_1_8 |
43098 | #define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_1__SHIFT 0x0 |
43099 | #define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_2__SHIFT 0x4 |
43100 | #define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_3__SHIFT 0x8 |
43101 | #define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_4__SHIFT 0xc |
43102 | #define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_5__SHIFT 0x10 |
43103 | #define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_6__SHIFT 0x14 |
43104 | #define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_7__SHIFT 0x18 |
43105 | #define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_8__SHIFT 0x1c |
43106 | #define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_1_MASK 0x00000007L |
43107 | #define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_2_MASK 0x00000070L |
43108 | #define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_3_MASK 0x00000700L |
43109 | #define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_4_MASK 0x00007000L |
43110 | #define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_5_MASK 0x00070000L |
43111 | #define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_6_MASK 0x00700000L |
43112 | #define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_7_MASK 0x07000000L |
43113 | #define PWRBRK_RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_8_MASK 0x70000000L |
43114 | //PWRBRK_RELEASE_TO_STALL_LUT_9_16 |
43115 | #define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_9__SHIFT 0x0 |
43116 | #define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_10__SHIFT 0x4 |
43117 | #define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_11__SHIFT 0x8 |
43118 | #define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_12__SHIFT 0xc |
43119 | #define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_13__SHIFT 0x10 |
43120 | #define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_14__SHIFT 0x14 |
43121 | #define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_15__SHIFT 0x18 |
43122 | #define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_16__SHIFT 0x1c |
43123 | #define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_9_MASK 0x00000007L |
43124 | #define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_10_MASK 0x00000070L |
43125 | #define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_11_MASK 0x00000700L |
43126 | #define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_12_MASK 0x00007000L |
43127 | #define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_13_MASK 0x00070000L |
43128 | #define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_14_MASK 0x00700000L |
43129 | #define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_15_MASK 0x07000000L |
43130 | #define PWRBRK_RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_16_MASK 0x70000000L |
43131 | //PWRBRK_RELEASE_TO_STALL_LUT_17_20 |
43132 | #define PWRBRK_RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_17__SHIFT 0x0 |
43133 | #define PWRBRK_RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_18__SHIFT 0x4 |
43134 | #define PWRBRK_RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_19__SHIFT 0x8 |
43135 | #define PWRBRK_RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_20__SHIFT 0xc |
43136 | #define PWRBRK_RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_17_MASK 0x00000007L |
43137 | #define PWRBRK_RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_18_MASK 0x00000070L |
43138 | #define PWRBRK_RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_19_MASK 0x00000700L |
43139 | #define PWRBRK_RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_20_MASK 0x00007000L |
43140 | //FIXED_PATTERN_PERF_COUNTER_1 |
43141 | #define FIXED_PATTERN_PERF_COUNTER_1__PERF_COUNTER__SHIFT 0x0 |
43142 | #define FIXED_PATTERN_PERF_COUNTER_1__PERF_COUNTER_MASK 0x0001FFFFL |
43143 | //FIXED_PATTERN_PERF_COUNTER_2 |
43144 | #define FIXED_PATTERN_PERF_COUNTER_2__PERF_COUNTER__SHIFT 0x0 |
43145 | #define FIXED_PATTERN_PERF_COUNTER_2__PERF_COUNTER_MASK 0x0001FFFFL |
43146 | //FIXED_PATTERN_PERF_COUNTER_3 |
43147 | #define FIXED_PATTERN_PERF_COUNTER_3__PERF_COUNTER__SHIFT 0x0 |
43148 | #define FIXED_PATTERN_PERF_COUNTER_3__PERF_COUNTER_MASK 0x0001FFFFL |
43149 | //FIXED_PATTERN_PERF_COUNTER_4 |
43150 | #define FIXED_PATTERN_PERF_COUNTER_4__PERF_COUNTER__SHIFT 0x0 |
43151 | #define FIXED_PATTERN_PERF_COUNTER_4__PERF_COUNTER_MASK 0x0001FFFFL |
43152 | //FIXED_PATTERN_PERF_COUNTER_5 |
43153 | #define FIXED_PATTERN_PERF_COUNTER_5__PERF_COUNTER__SHIFT 0x0 |
43154 | #define FIXED_PATTERN_PERF_COUNTER_5__PERF_COUNTER_MASK 0x0001FFFFL |
43155 | //FIXED_PATTERN_PERF_COUNTER_6 |
43156 | #define FIXED_PATTERN_PERF_COUNTER_6__PERF_COUNTER__SHIFT 0x0 |
43157 | #define FIXED_PATTERN_PERF_COUNTER_6__PERF_COUNTER_MASK 0x0001FFFFL |
43158 | //FIXED_PATTERN_PERF_COUNTER_7 |
43159 | #define FIXED_PATTERN_PERF_COUNTER_7__PERF_COUNTER__SHIFT 0x0 |
43160 | #define FIXED_PATTERN_PERF_COUNTER_7__PERF_COUNTER_MASK 0x0001FFFFL |
43161 | //FIXED_PATTERN_PERF_COUNTER_8 |
43162 | #define FIXED_PATTERN_PERF_COUNTER_8__PERF_COUNTER__SHIFT 0x0 |
43163 | #define FIXED_PATTERN_PERF_COUNTER_8__PERF_COUNTER_MASK 0x0001FFFFL |
43164 | //FIXED_PATTERN_PERF_COUNTER_9 |
43165 | #define FIXED_PATTERN_PERF_COUNTER_9__PERF_COUNTER__SHIFT 0x0 |
43166 | #define FIXED_PATTERN_PERF_COUNTER_9__PERF_COUNTER_MASK 0x0001FFFFL |
43167 | //FIXED_PATTERN_PERF_COUNTER_10 |
43168 | #define FIXED_PATTERN_PERF_COUNTER_10__PERF_COUNTER__SHIFT 0x0 |
43169 | #define FIXED_PATTERN_PERF_COUNTER_10__PERF_COUNTER_MASK 0x0001FFFFL |
43170 | //HW_LUT_UPDATE_STATUS |
43171 | #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_1_DONE__SHIFT 0x0 |
43172 | #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_1_ERROR__SHIFT 0x1 |
43173 | #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_1_ERROR_STEP__SHIFT 0x2 |
43174 | #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_2_DONE__SHIFT 0x5 |
43175 | #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_2_ERROR__SHIFT 0x6 |
43176 | #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_2_ERROR_STEP__SHIFT 0x7 |
43177 | #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_3_DONE__SHIFT 0xa |
43178 | #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_3_ERROR__SHIFT 0xb |
43179 | #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_3_ERROR_STEP__SHIFT 0xc |
43180 | #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_4_DONE__SHIFT 0x11 |
43181 | #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_4_ERROR__SHIFT 0x12 |
43182 | #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_4_ERROR_STEP__SHIFT 0x13 |
43183 | #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_5_DONE__SHIFT 0x16 |
43184 | #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_5_ERROR__SHIFT 0x17 |
43185 | #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_5_ERROR_STEP__SHIFT 0x18 |
43186 | #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_1_DONE_MASK 0x00000001L |
43187 | #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_1_ERROR_MASK 0x00000002L |
43188 | #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_1_ERROR_STEP_MASK 0x0000001CL |
43189 | #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_2_DONE_MASK 0x00000020L |
43190 | #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_2_ERROR_MASK 0x00000040L |
43191 | #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_2_ERROR_STEP_MASK 0x00000380L |
43192 | #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_3_DONE_MASK 0x00000400L |
43193 | #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_3_ERROR_MASK 0x00000800L |
43194 | #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_3_ERROR_STEP_MASK 0x0001F000L |
43195 | #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_4_DONE_MASK 0x00020000L |
43196 | #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_4_ERROR_MASK 0x00040000L |
43197 | #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_4_ERROR_STEP_MASK 0x00380000L |
43198 | #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_5_DONE_MASK 0x00400000L |
43199 | #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_5_ERROR_MASK 0x00800000L |
43200 | #define HW_LUT_UPDATE_STATUS__UPDATE_TABLE_5_ERROR_STEP_MASK 0x1F000000L |
43201 | |
43202 | |
43203 | // addressBlock: secacind |
43204 | //SE_CAC_ID |
43205 | #define SE_CAC_ID__CAC_BLOCK_ID__SHIFT 0x0 |
43206 | #define SE_CAC_ID__CAC_SIGNAL_ID__SHIFT 0x6 |
43207 | #define SE_CAC_ID__CAC_BLOCK_ID_MASK 0x0000003FL |
43208 | #define SE_CAC_ID__CAC_SIGNAL_ID_MASK 0x00003FC0L |
43209 | //SE_CAC_CNTL |
43210 | #define SE_CAC_CNTL__CAC_THRESHOLD__SHIFT 0x0 |
43211 | #define SE_CAC_CNTL__CAC_THRESHOLD_MASK 0x0000FFFFL |
43212 | |
43213 | |
43214 | // addressBlock: grtavfsind |
43215 | //RTAVFS_REG0 |
43216 | #define RTAVFS_REG0__RTAVFSZONE0STARTCNT__SHIFT 0x0 |
43217 | #define RTAVFS_REG0__RTAVFSZONE0STOPCNT__SHIFT 0x10 |
43218 | #define RTAVFS_REG0__RTAVFSZONE0STARTCNT_MASK 0x0000FFFFL |
43219 | #define RTAVFS_REG0__RTAVFSZONE0STOPCNT_MASK 0xFFFF0000L |
43220 | //RTAVFS_REG1 |
43221 | #define RTAVFS_REG1__RTAVFSZONE1STARTCNT__SHIFT 0x0 |
43222 | #define RTAVFS_REG1__RTAVFSZONE1STOPCNT__SHIFT 0x10 |
43223 | #define RTAVFS_REG1__RTAVFSZONE1STARTCNT_MASK 0x0000FFFFL |
43224 | #define RTAVFS_REG1__RTAVFSZONE1STOPCNT_MASK 0xFFFF0000L |
43225 | //RTAVFS_REG2 |
43226 | #define RTAVFS_REG2__RTAVFSZONE2STARTCNT__SHIFT 0x0 |
43227 | #define RTAVFS_REG2__RTAVFSZONE2STOPCNT__SHIFT 0x10 |
43228 | #define RTAVFS_REG2__RTAVFSZONE2STARTCNT_MASK 0x0000FFFFL |
43229 | #define RTAVFS_REG2__RTAVFSZONE2STOPCNT_MASK 0xFFFF0000L |
43230 | //RTAVFS_REG3 |
43231 | #define RTAVFS_REG3__RTAVFSZONE3STARTCNT__SHIFT 0x0 |
43232 | #define RTAVFS_REG3__RTAVFSZONE3STOPCNT__SHIFT 0x10 |
43233 | #define RTAVFS_REG3__RTAVFSZONE3STARTCNT_MASK 0x0000FFFFL |
43234 | #define RTAVFS_REG3__RTAVFSZONE3STOPCNT_MASK 0xFFFF0000L |
43235 | //RTAVFS_REG4 |
43236 | #define RTAVFS_REG4__RTAVFSZONE4STARTCNT__SHIFT 0x0 |
43237 | #define RTAVFS_REG4__RTAVFSZONE4STOPCNT__SHIFT 0x10 |
43238 | #define RTAVFS_REG4__RTAVFSZONE4STARTCNT_MASK 0x0000FFFFL |
43239 | #define RTAVFS_REG4__RTAVFSZONE4STOPCNT_MASK 0xFFFF0000L |
43240 | //RTAVFS_REG5 |
43241 | #define RTAVFS_REG5__RTAVFSZONE0EN0__SHIFT 0x0 |
43242 | #define RTAVFS_REG5__RTAVFSZONE0EN0_MASK 0xFFFFFFFFL |
43243 | //RTAVFS_REG6 |
43244 | #define RTAVFS_REG6__RTAVFSZONE0EN1__SHIFT 0x0 |
43245 | #define RTAVFS_REG6__RTAVFSZONE0EN1_MASK 0xFFFFFFFFL |
43246 | //RTAVFS_REG7 |
43247 | #define RTAVFS_REG7__RTAVFSZONE1EN0__SHIFT 0x0 |
43248 | #define RTAVFS_REG7__RTAVFSZONE1EN0_MASK 0xFFFFFFFFL |
43249 | //RTAVFS_REG8 |
43250 | #define RTAVFS_REG8__RTAVFSZONE1EN1__SHIFT 0x0 |
43251 | #define RTAVFS_REG8__RTAVFSZONE1EN1_MASK 0xFFFFFFFFL |
43252 | //RTAVFS_REG9 |
43253 | #define RTAVFS_REG9__RTAVFSZONE2EN0__SHIFT 0x0 |
43254 | #define RTAVFS_REG9__RTAVFSZONE2EN0_MASK 0xFFFFFFFFL |
43255 | //RTAVFS_REG10 |
43256 | #define RTAVFS_REG10__RTAVFSZONE2EN1__SHIFT 0x0 |
43257 | #define RTAVFS_REG10__RTAVFSZONE2EN1_MASK 0xFFFFFFFFL |
43258 | //RTAVFS_REG11 |
43259 | #define RTAVFS_REG11__RTAVFSZONE3EN0__SHIFT 0x0 |
43260 | #define RTAVFS_REG11__RTAVFSZONE3EN0_MASK 0xFFFFFFFFL |
43261 | //RTAVFS_REG12 |
43262 | #define RTAVFS_REG12__RTAVFSZONE3EN1__SHIFT 0x0 |
43263 | #define RTAVFS_REG12__RTAVFSZONE3EN1_MASK 0xFFFFFFFFL |
43264 | //RTAVFS_REG13 |
43265 | #define RTAVFS_REG13__RTAVFSZONE4EN0__SHIFT 0x0 |
43266 | #define RTAVFS_REG13__RTAVFSZONE4EN0_MASK 0xFFFFFFFFL |
43267 | //RTAVFS_REG14 |
43268 | #define RTAVFS_REG14__RTAVFSZONE4EN1__SHIFT 0x0 |
43269 | #define RTAVFS_REG14__RTAVFSZONE4EN1_MASK 0xFFFFFFFFL |
43270 | //RTAVFS_REG15 |
43271 | #define RTAVFS_REG15__RTAVFSVF0FREQCOUNT__SHIFT 0x0 |
43272 | #define RTAVFS_REG15__RTAVFSVF0VOLTCODE__SHIFT 0x10 |
43273 | #define RTAVFS_REG15__RTAVFSVF0FREQCOUNT_MASK 0x0000FFFFL |
43274 | #define RTAVFS_REG15__RTAVFSVF0VOLTCODE_MASK 0xFFFF0000L |
43275 | //RTAVFS_REG16 |
43276 | #define RTAVFS_REG16__RTAVFSVF1FREQCOUNT__SHIFT 0x0 |
43277 | #define RTAVFS_REG16__RTAVFSVF1VOLTCODE__SHIFT 0x10 |
43278 | #define RTAVFS_REG16__RTAVFSVF1FREQCOUNT_MASK 0x0000FFFFL |
43279 | #define RTAVFS_REG16__RTAVFSVF1VOLTCODE_MASK 0xFFFF0000L |
43280 | //RTAVFS_REG17 |
43281 | #define RTAVFS_REG17__RTAVFSVF2FREQCOUNT__SHIFT 0x0 |
43282 | #define RTAVFS_REG17__RTAVFSVF2VOLTCODE__SHIFT 0x10 |
43283 | #define RTAVFS_REG17__RTAVFSVF2FREQCOUNT_MASK 0x0000FFFFL |
43284 | #define RTAVFS_REG17__RTAVFSVF2VOLTCODE_MASK 0xFFFF0000L |
43285 | //RTAVFS_REG18 |
43286 | #define RTAVFS_REG18__RTAVFSVF3FREQCOUNT__SHIFT 0x0 |
43287 | #define RTAVFS_REG18__RTAVFSVF3VOLTCODE__SHIFT 0x10 |
43288 | #define RTAVFS_REG18__RTAVFSVF3FREQCOUNT_MASK 0x0000FFFFL |
43289 | #define RTAVFS_REG18__RTAVFSVF3VOLTCODE_MASK 0xFFFF0000L |
43290 | //RTAVFS_REG19 |
43291 | #define RTAVFS_REG19__RTAVFSGB_ZONE0__SHIFT 0x0 |
43292 | #define RTAVFS_REG19__RTAVFSGB_ZONE1__SHIFT 0x6 |
43293 | #define RTAVFS_REG19__RTAVFSGB_ZONE2__SHIFT 0xc |
43294 | #define RTAVFS_REG19__RTAVFSGB_ZONE3__SHIFT 0x12 |
43295 | #define RTAVFS_REG19__RTAVFSGB_ZONE4__SHIFT 0x19 |
43296 | #define RTAVFS_REG19__RTAVFSGB_ZONE0_MASK 0x0000003FL |
43297 | #define RTAVFS_REG19__RTAVFSGB_ZONE1_MASK 0x00000FC0L |
43298 | #define RTAVFS_REG19__RTAVFSGB_ZONE2_MASK 0x0003F000L |
43299 | #define RTAVFS_REG19__RTAVFSGB_ZONE3_MASK 0x01FC0000L |
43300 | #define RTAVFS_REG19__RTAVFSGB_ZONE4_MASK 0xFE000000L |
43301 | //RTAVFS_REG20 |
43302 | #define RTAVFS_REG20__RTAVFSZONE0CPOAVGDIV0__SHIFT 0x0 |
43303 | #define RTAVFS_REG20__RTAVFSZONE0CPOAVGDIV1__SHIFT 0x2 |
43304 | #define RTAVFS_REG20__RTAVFSZONE0CPOAVGDIV2__SHIFT 0x4 |
43305 | #define RTAVFS_REG20__RTAVFSZONE0CPOAVGDIV3__SHIFT 0x6 |
43306 | #define RTAVFS_REG20__RTAVFSZONE0CPOAVGDIV4__SHIFT 0x8 |
43307 | #define RTAVFS_REG20__RTAVFSZONE0CPOAVGDIV5__SHIFT 0xa |
43308 | #define RTAVFS_REG20__RTAVFSZONE0CPOAVGDIV6__SHIFT 0xc |
43309 | #define RTAVFS_REG20__RTAVFSZONE0CPOAVGDIV7__SHIFT 0xe |
43310 | #define RTAVFS_REG20__RTAVFSZONE0CPOAVGDIVFINAL__SHIFT 0x10 |
43311 | #define RTAVFS_REG20__RTAVFSZONE0RESERVED__SHIFT 0x12 |
43312 | #define RTAVFS_REG20__RTAVFSZONE0CPOAVGDIV0_MASK 0x00000003L |
43313 | #define RTAVFS_REG20__RTAVFSZONE0CPOAVGDIV1_MASK 0x0000000CL |
43314 | #define RTAVFS_REG20__RTAVFSZONE0CPOAVGDIV2_MASK 0x00000030L |
43315 | #define RTAVFS_REG20__RTAVFSZONE0CPOAVGDIV3_MASK 0x000000C0L |
43316 | #define RTAVFS_REG20__RTAVFSZONE0CPOAVGDIV4_MASK 0x00000300L |
43317 | #define RTAVFS_REG20__RTAVFSZONE0CPOAVGDIV5_MASK 0x00000C00L |
43318 | #define RTAVFS_REG20__RTAVFSZONE0CPOAVGDIV6_MASK 0x00003000L |
43319 | #define RTAVFS_REG20__RTAVFSZONE0CPOAVGDIV7_MASK 0x0000C000L |
43320 | #define RTAVFS_REG20__RTAVFSZONE0CPOAVGDIVFINAL_MASK 0x00030000L |
43321 | #define RTAVFS_REG20__RTAVFSZONE0RESERVED_MASK 0xFFFC0000L |
43322 | //RTAVFS_REG21 |
43323 | #define RTAVFS_REG21__RTAVFSZONE1CPOAVGDIV0__SHIFT 0x0 |
43324 | #define RTAVFS_REG21__RTAVFSZONE1CPOAVGDIV1__SHIFT 0x2 |
43325 | #define RTAVFS_REG21__RTAVFSZONE1CPOAVGDIV2__SHIFT 0x4 |
43326 | #define RTAVFS_REG21__RTAVFSZONE1CPOAVGDIV3__SHIFT 0x6 |
43327 | #define RTAVFS_REG21__RTAVFSZONE1CPOAVGDIV4__SHIFT 0x8 |
43328 | #define RTAVFS_REG21__RTAVFSZONE1CPOAVGDIV5__SHIFT 0xa |
43329 | #define RTAVFS_REG21__RTAVFSZONE1CPOAVGDIV6__SHIFT 0xc |
43330 | #define RTAVFS_REG21__RTAVFSZONE1CPOAVGDIV7__SHIFT 0xe |
43331 | #define RTAVFS_REG21__RTAVFSZONE1CPOAVGDIVFINAL__SHIFT 0x10 |
43332 | #define RTAVFS_REG21__RTAVFSZONE1RESERVED__SHIFT 0x12 |
43333 | #define RTAVFS_REG21__RTAVFSZONE1CPOAVGDIV0_MASK 0x00000003L |
43334 | #define RTAVFS_REG21__RTAVFSZONE1CPOAVGDIV1_MASK 0x0000000CL |
43335 | #define RTAVFS_REG21__RTAVFSZONE1CPOAVGDIV2_MASK 0x00000030L |
43336 | #define RTAVFS_REG21__RTAVFSZONE1CPOAVGDIV3_MASK 0x000000C0L |
43337 | #define RTAVFS_REG21__RTAVFSZONE1CPOAVGDIV4_MASK 0x00000300L |
43338 | #define RTAVFS_REG21__RTAVFSZONE1CPOAVGDIV5_MASK 0x00000C00L |
43339 | #define RTAVFS_REG21__RTAVFSZONE1CPOAVGDIV6_MASK 0x00003000L |
43340 | #define RTAVFS_REG21__RTAVFSZONE1CPOAVGDIV7_MASK 0x0000C000L |
43341 | #define RTAVFS_REG21__RTAVFSZONE1CPOAVGDIVFINAL_MASK 0x00030000L |
43342 | #define RTAVFS_REG21__RTAVFSZONE1RESERVED_MASK 0xFFFC0000L |
43343 | //RTAVFS_REG22 |
43344 | #define RTAVFS_REG22__RTAVFSZONE2CPOAVGDIV0__SHIFT 0x0 |
43345 | #define RTAVFS_REG22__RTAVFSZONE2CPOAVGDIV1__SHIFT 0x2 |
43346 | #define RTAVFS_REG22__RTAVFSZONE2CPOAVGDIV2__SHIFT 0x4 |
43347 | #define RTAVFS_REG22__RTAVFSZONE2CPOAVGDIV3__SHIFT 0x6 |
43348 | #define RTAVFS_REG22__RTAVFSZONE2CPOAVGDIV4__SHIFT 0x8 |
43349 | #define RTAVFS_REG22__RTAVFSZONE2CPOAVGDIV5__SHIFT 0xa |
43350 | #define RTAVFS_REG22__RTAVFSZONE2CPOAVGDIV6__SHIFT 0xc |
43351 | #define RTAVFS_REG22__RTAVFSZONE2CPOAVGDIV7__SHIFT 0xe |
43352 | #define RTAVFS_REG22__RTAVFSZONE2CPOAVGDIVFINAL__SHIFT 0x10 |
43353 | #define RTAVFS_REG22__RTAVFSZONE2RESERVED__SHIFT 0x12 |
43354 | #define RTAVFS_REG22__RTAVFSZONE2CPOAVGDIV0_MASK 0x00000003L |
43355 | #define RTAVFS_REG22__RTAVFSZONE2CPOAVGDIV1_MASK 0x0000000CL |
43356 | #define RTAVFS_REG22__RTAVFSZONE2CPOAVGDIV2_MASK 0x00000030L |
43357 | #define RTAVFS_REG22__RTAVFSZONE2CPOAVGDIV3_MASK 0x000000C0L |
43358 | #define RTAVFS_REG22__RTAVFSZONE2CPOAVGDIV4_MASK 0x00000300L |
43359 | #define RTAVFS_REG22__RTAVFSZONE2CPOAVGDIV5_MASK 0x00000C00L |
43360 | #define RTAVFS_REG22__RTAVFSZONE2CPOAVGDIV6_MASK 0x00003000L |
43361 | #define RTAVFS_REG22__RTAVFSZONE2CPOAVGDIV7_MASK 0x0000C000L |
43362 | #define RTAVFS_REG22__RTAVFSZONE2CPOAVGDIVFINAL_MASK 0x00030000L |
43363 | #define RTAVFS_REG22__RTAVFSZONE2RESERVED_MASK 0xFFFC0000L |
43364 | //RTAVFS_REG23 |
43365 | #define RTAVFS_REG23__RTAVFSZONE3CPOAVGDIV0__SHIFT 0x0 |
43366 | #define RTAVFS_REG23__RTAVFSZONE3CPOAVGDIV1__SHIFT 0x2 |
43367 | #define RTAVFS_REG23__RTAVFSZONE3CPOAVGDIV2__SHIFT 0x4 |
43368 | #define RTAVFS_REG23__RTAVFSZONE3CPOAVGDIV3__SHIFT 0x6 |
43369 | #define RTAVFS_REG23__RTAVFSZONE3CPOAVGDIV4__SHIFT 0x8 |
43370 | #define RTAVFS_REG23__RTAVFSZONE3CPOAVGDIV5__SHIFT 0xa |
43371 | #define RTAVFS_REG23__RTAVFSZONE3CPOAVGDIV6__SHIFT 0xc |
43372 | #define RTAVFS_REG23__RTAVFSZONE3CPOAVGDIV7__SHIFT 0xe |
43373 | #define RTAVFS_REG23__RTAVFSZONE3CPOAVGDIVFINAL__SHIFT 0x10 |
43374 | #define RTAVFS_REG23__RTAVFSZONE3RESERVED__SHIFT 0x12 |
43375 | #define RTAVFS_REG23__RTAVFSZONE3CPOAVGDIV0_MASK 0x00000003L |
43376 | #define RTAVFS_REG23__RTAVFSZONE3CPOAVGDIV1_MASK 0x0000000CL |
43377 | #define RTAVFS_REG23__RTAVFSZONE3CPOAVGDIV2_MASK 0x00000030L |
43378 | #define RTAVFS_REG23__RTAVFSZONE3CPOAVGDIV3_MASK 0x000000C0L |
43379 | #define RTAVFS_REG23__RTAVFSZONE3CPOAVGDIV4_MASK 0x00000300L |
43380 | #define RTAVFS_REG23__RTAVFSZONE3CPOAVGDIV5_MASK 0x00000C00L |
43381 | #define RTAVFS_REG23__RTAVFSZONE3CPOAVGDIV6_MASK 0x00003000L |
43382 | #define RTAVFS_REG23__RTAVFSZONE3CPOAVGDIV7_MASK 0x0000C000L |
43383 | #define RTAVFS_REG23__RTAVFSZONE3CPOAVGDIVFINAL_MASK 0x00030000L |
43384 | #define RTAVFS_REG23__RTAVFSZONE3RESERVED_MASK 0xFFFC0000L |
43385 | //RTAVFS_REG24 |
43386 | #define RTAVFS_REG24__RTAVFSZONE4CPOAVGDIV0__SHIFT 0x0 |
43387 | #define RTAVFS_REG24__RTAVFSZONE4CPOAVGDIV1__SHIFT 0x2 |
43388 | #define RTAVFS_REG24__RTAVFSZONE4CPOAVGDIV2__SHIFT 0x4 |
43389 | #define RTAVFS_REG24__RTAVFSZONE4CPOAVGDIV3__SHIFT 0x6 |
43390 | #define RTAVFS_REG24__RTAVFSZONE4CPOAVGDIV4__SHIFT 0x8 |
43391 | #define RTAVFS_REG24__RTAVFSZONE4CPOAVGDIV5__SHIFT 0xa |
43392 | #define RTAVFS_REG24__RTAVFSZONE4CPOAVGDIV6__SHIFT 0xc |
43393 | #define RTAVFS_REG24__RTAVFSZONE4CPOAVGDIV7__SHIFT 0xe |
43394 | #define RTAVFS_REG24__RTAVFSZONE4CPOAVGDIVFINAL__SHIFT 0x10 |
43395 | #define RTAVFS_REG24__RTAVFSZONE4RESERVED__SHIFT 0x12 |
43396 | #define RTAVFS_REG24__RTAVFSZONE4CPOAVGDIV0_MASK 0x00000003L |
43397 | #define RTAVFS_REG24__RTAVFSZONE4CPOAVGDIV1_MASK 0x0000000CL |
43398 | #define RTAVFS_REG24__RTAVFSZONE4CPOAVGDIV2_MASK 0x00000030L |
43399 | #define RTAVFS_REG24__RTAVFSZONE4CPOAVGDIV3_MASK 0x000000C0L |
43400 | #define RTAVFS_REG24__RTAVFSZONE4CPOAVGDIV4_MASK 0x00000300L |
43401 | #define RTAVFS_REG24__RTAVFSZONE4CPOAVGDIV5_MASK 0x00000C00L |
43402 | #define RTAVFS_REG24__RTAVFSZONE4CPOAVGDIV6_MASK 0x00003000L |
43403 | #define RTAVFS_REG24__RTAVFSZONE4CPOAVGDIV7_MASK 0x0000C000L |
43404 | #define RTAVFS_REG24__RTAVFSZONE4CPOAVGDIVFINAL_MASK 0x00030000L |
43405 | #define RTAVFS_REG24__RTAVFSZONE4RESERVED_MASK 0xFFFC0000L |
43406 | //RTAVFS_REG25 |
43407 | #define RTAVFS_REG25__RTAVFSRESERVED0__SHIFT 0x0 |
43408 | #define RTAVFS_REG25__RTAVFSRESERVED0_MASK 0xFFFFFFFFL |
43409 | //RTAVFS_REG26 |
43410 | #define RTAVFS_REG26__RTAVFSRESERVED1__SHIFT 0x0 |
43411 | #define RTAVFS_REG26__RTAVFSRESERVED1_MASK 0xFFFFFFFFL |
43412 | //RTAVFS_REG27 |
43413 | #define RTAVFS_REG27__RTAVFSRESERVED2__SHIFT 0x0 |
43414 | #define RTAVFS_REG27__RTAVFSRESERVED2_MASK 0xFFFFFFFFL |
43415 | //RTAVFS_REG28 |
43416 | #define RTAVFS_REG28__RTAVFSZONE0INTERCEPT__SHIFT 0x0 |
43417 | #define RTAVFS_REG28__RTAVFSZONE1INTERCEPT__SHIFT 0x10 |
43418 | #define RTAVFS_REG28__RTAVFSZONE0INTERCEPT_MASK 0x0000FFFFL |
43419 | #define RTAVFS_REG28__RTAVFSZONE1INTERCEPT_MASK 0xFFFF0000L |
43420 | //RTAVFS_REG29 |
43421 | #define RTAVFS_REG29__RTAVFSZONE2INTERCEPT__SHIFT 0x0 |
43422 | #define RTAVFS_REG29__RTAVFSZONE3INTERCEPT__SHIFT 0x10 |
43423 | #define RTAVFS_REG29__RTAVFSZONE2INTERCEPT_MASK 0x0000FFFFL |
43424 | #define RTAVFS_REG29__RTAVFSZONE3INTERCEPT_MASK 0xFFFF0000L |
43425 | //RTAVFS_REG30 |
43426 | #define RTAVFS_REG30__RTAVFSZONE4INTERCEPT__SHIFT 0x0 |
43427 | #define RTAVFS_REG30__RTAVFSRESERVEDINTERCEPT__SHIFT 0x10 |
43428 | #define RTAVFS_REG30__RTAVFSZONE4INTERCEPT_MASK 0x0000FFFFL |
43429 | #define RTAVFS_REG30__RTAVFSRESERVEDINTERCEPT_MASK 0xFFFF0000L |
43430 | //RTAVFS_REG31 |
43431 | #define RTAVFS_REG31__RTAVFSCPOCLKDIV0__SHIFT 0x0 |
43432 | #define RTAVFS_REG31__RTAVFSCPOCLKDIV1__SHIFT 0x2 |
43433 | #define RTAVFS_REG31__RTAVFSCPOCLKDIV2__SHIFT 0x4 |
43434 | #define RTAVFS_REG31__RTAVFSCPOCLKDIV3__SHIFT 0x6 |
43435 | #define RTAVFS_REG31__RTAVFSCPOCLKDIV4__SHIFT 0x8 |
43436 | #define RTAVFS_REG31__RTAVFSCPOCLKDIV5__SHIFT 0xa |
43437 | #define RTAVFS_REG31__RTAVFSCPOCLKDIV6__SHIFT 0xc |
43438 | #define RTAVFS_REG31__RTAVFSCPOCLKDIV7__SHIFT 0xe |
43439 | #define RTAVFS_REG31__RESERVED__SHIFT 0x10 |
43440 | #define RTAVFS_REG31__RTAVFSCPOCLKDIV0_MASK 0x00000003L |
43441 | #define RTAVFS_REG31__RTAVFSCPOCLKDIV1_MASK 0x0000000CL |
43442 | #define RTAVFS_REG31__RTAVFSCPOCLKDIV2_MASK 0x00000030L |
43443 | #define RTAVFS_REG31__RTAVFSCPOCLKDIV3_MASK 0x000000C0L |
43444 | #define RTAVFS_REG31__RTAVFSCPOCLKDIV4_MASK 0x00000300L |
43445 | #define RTAVFS_REG31__RTAVFSCPOCLKDIV5_MASK 0x00000C00L |
43446 | #define RTAVFS_REG31__RTAVFSCPOCLKDIV6_MASK 0x00003000L |
43447 | #define RTAVFS_REG31__RTAVFSCPOCLKDIV7_MASK 0x0000C000L |
43448 | #define RTAVFS_REG31__RESERVED_MASK 0xFFFF0000L |
43449 | //RTAVFS_REG32 |
43450 | #define RTAVFS_REG32__RTAVFSFSMSTARTUPCNT__SHIFT 0x0 |
43451 | #define RTAVFS_REG32__RESERVED__SHIFT 0x10 |
43452 | #define RTAVFS_REG32__RTAVFSFSMSTARTUPCNT_MASK 0x0000FFFFL |
43453 | #define RTAVFS_REG32__RESERVED_MASK 0xFFFF0000L |
43454 | //RTAVFS_REG33 |
43455 | #define RTAVFS_REG33__RTAVFSFSMIDLECNT__SHIFT 0x0 |
43456 | #define RTAVFS_REG33__RESERVED__SHIFT 0x10 |
43457 | #define RTAVFS_REG33__RTAVFSFSMIDLECNT_MASK 0x0000FFFFL |
43458 | #define RTAVFS_REG33__RESERVED_MASK 0xFFFF0000L |
43459 | //RTAVFS_REG34 |
43460 | #define RTAVFS_REG34__RTAVFSFSMRESETCPORIPPLECOUNTERSCNT__SHIFT 0x0 |
43461 | #define RTAVFS_REG34__RESERVED__SHIFT 0x10 |
43462 | #define RTAVFS_REG34__RTAVFSFSMRESETCPORIPPLECOUNTERSCNT_MASK 0x0000FFFFL |
43463 | #define RTAVFS_REG34__RESERVED_MASK 0xFFFF0000L |
43464 | //RTAVFS_REG35 |
43465 | #define RTAVFS_REG35__RTAVFSFSMSTARTCPOSCNT__SHIFT 0x0 |
43466 | #define RTAVFS_REG35__RESERVED__SHIFT 0x10 |
43467 | #define RTAVFS_REG35__RTAVFSFSMSTARTCPOSCNT_MASK 0x0000FFFFL |
43468 | #define RTAVFS_REG35__RESERVED_MASK 0xFFFF0000L |
43469 | //RTAVFS_REG36 |
43470 | #define RTAVFS_REG36__RTAVFSFSMSTARTRIPPLECOUNTERSCNT__SHIFT 0x0 |
43471 | #define RTAVFS_REG36__RESERVED__SHIFT 0x10 |
43472 | #define RTAVFS_REG36__RTAVFSFSMSTARTRIPPLECOUNTERSCNT_MASK 0x0000FFFFL |
43473 | #define RTAVFS_REG36__RESERVED_MASK 0xFFFF0000L |
43474 | //RTAVFS_REG37 |
43475 | #define RTAVFS_REG37__RTAVFSFSMRIPPLECOUNTERSDONECNT__SHIFT 0x0 |
43476 | #define RTAVFS_REG37__RESERVED__SHIFT 0x10 |
43477 | #define RTAVFS_REG37__RTAVFSFSMRIPPLECOUNTERSDONECNT_MASK 0x0000FFFFL |
43478 | #define RTAVFS_REG37__RESERVED_MASK 0xFFFF0000L |
43479 | //RTAVFS_REG38 |
43480 | #define RTAVFS_REG38__RTAVFSFSMCPOFINALRESULTREADYCNT__SHIFT 0x0 |
43481 | #define RTAVFS_REG38__RESERVED__SHIFT 0x10 |
43482 | #define RTAVFS_REG38__RTAVFSFSMCPOFINALRESULTREADYCNT_MASK 0x0000FFFFL |
43483 | #define RTAVFS_REG38__RESERVED_MASK 0xFFFF0000L |
43484 | //RTAVFS_REG39 |
43485 | #define RTAVFS_REG39__RTAVFSFSMVOLTCODEREADYCNT__SHIFT 0x0 |
43486 | #define RTAVFS_REG39__RESERVED__SHIFT 0x10 |
43487 | #define RTAVFS_REG39__RTAVFSFSMVOLTCODEREADYCNT_MASK 0x0000FFFFL |
43488 | #define RTAVFS_REG39__RESERVED_MASK 0xFFFF0000L |
43489 | //RTAVFS_REG40 |
43490 | #define RTAVFS_REG40__RTAVFSFSMTARGETVOLTAGEREADYCNT__SHIFT 0x0 |
43491 | #define RTAVFS_REG40__RESERVED__SHIFT 0x10 |
43492 | #define RTAVFS_REG40__RTAVFSFSMTARGETVOLTAGEREADYCNT_MASK 0x0000FFFFL |
43493 | #define RTAVFS_REG40__RESERVED_MASK 0xFFFF0000L |
43494 | //RTAVFS_REG41 |
43495 | #define RTAVFS_REG41__RTAVFSFSMSTOPCPOSCNT__SHIFT 0x0 |
43496 | #define RTAVFS_REG41__RESERVED__SHIFT 0x10 |
43497 | #define RTAVFS_REG41__RTAVFSFSMSTOPCPOSCNT_MASK 0x0000FFFFL |
43498 | #define RTAVFS_REG41__RESERVED_MASK 0xFFFF0000L |
43499 | //RTAVFS_REG42 |
43500 | #define RTAVFS_REG42__RTAVFSFSMWAITFORACKCNT__SHIFT 0x0 |
43501 | #define RTAVFS_REG42__RESERVED__SHIFT 0x10 |
43502 | #define RTAVFS_REG42__RTAVFSFSMWAITFORACKCNT_MASK 0x0000FFFFL |
43503 | #define RTAVFS_REG42__RESERVED_MASK 0xFFFF0000L |
43504 | //RTAVFS_REG43 |
43505 | #define RTAVFS_REG43__RTAVFSKP0__SHIFT 0x0 |
43506 | #define RTAVFS_REG43__RTAVFSKP1__SHIFT 0x4 |
43507 | #define RTAVFS_REG43__RTAVFSKP2__SHIFT 0x8 |
43508 | #define RTAVFS_REG43__RTAVFSKP3__SHIFT 0xc |
43509 | #define RTAVFS_REG43__RTAVFSKI0__SHIFT 0x10 |
43510 | #define RTAVFS_REG43__RTAVFSKI1__SHIFT 0x14 |
43511 | #define RTAVFS_REG43__RTAVFSKI2__SHIFT 0x18 |
43512 | #define RTAVFS_REG43__RTAVFSKI3__SHIFT 0x1c |
43513 | #define RTAVFS_REG43__RTAVFSKP0_MASK 0x0000000FL |
43514 | #define RTAVFS_REG43__RTAVFSKP1_MASK 0x000000F0L |
43515 | #define RTAVFS_REG43__RTAVFSKP2_MASK 0x00000F00L |
43516 | #define RTAVFS_REG43__RTAVFSKP3_MASK 0x0000F000L |
43517 | #define RTAVFS_REG43__RTAVFSKI0_MASK 0x000F0000L |
43518 | #define RTAVFS_REG43__RTAVFSKI1_MASK 0x00F00000L |
43519 | #define RTAVFS_REG43__RTAVFSKI2_MASK 0x0F000000L |
43520 | #define RTAVFS_REG43__RTAVFSKI3_MASK 0xF0000000L |
43521 | //RTAVFS_REG44 |
43522 | #define RTAVFS_REG44__RTAVFSV1__SHIFT 0x0 |
43523 | #define RTAVFS_REG44__RTAVFSV2__SHIFT 0xa |
43524 | #define RTAVFS_REG44__RTAVFSV3__SHIFT 0x14 |
43525 | #define RTAVFS_REG44__RTAVFSUSEBINARYSEARCH__SHIFT 0x1e |
43526 | #define RTAVFS_REG44__RTAVFSVOLTCODEHWCAL__SHIFT 0x1f |
43527 | #define RTAVFS_REG44__RTAVFSV1_MASK 0x000003FFL |
43528 | #define RTAVFS_REG44__RTAVFSV2_MASK 0x000FFC00L |
43529 | #define RTAVFS_REG44__RTAVFSV3_MASK 0x3FF00000L |
43530 | #define RTAVFS_REG44__RTAVFSUSEBINARYSEARCH_MASK 0x40000000L |
43531 | #define RTAVFS_REG44__RTAVFSVOLTCODEHWCAL_MASK 0x80000000L |
43532 | //RTAVFS_REG45 |
43533 | #define RTAVFS_REG45__RTAVFSVRBLEEDCNTRL__SHIFT 0x0 |
43534 | #define RTAVFS_REG45__RTAVFSVRENABLE__SHIFT 0x1 |
43535 | #define RTAVFS_REG45__RTAVFSVOLTCODEOVERRIDE__SHIFT 0x2 |
43536 | #define RTAVFS_REG45__RTAVFSVOLTCODEOVERRIDESEL__SHIFT 0xc |
43537 | #define RTAVFS_REG45__RTAVFSLOWPWREN__SHIFT 0xd |
43538 | #define RTAVFS_REG45__RTAVFSUREGENABLE__SHIFT 0xe |
43539 | #define RTAVFS_REG45__RTAVFSBGENABLE__SHIFT 0xf |
43540 | #define RTAVFS_REG45__RTAVFSENABLEVDDRETSENSING__SHIFT 0x10 |
43541 | #define RTAVFS_REG45__RESERVED__SHIFT 0x11 |
43542 | #define RTAVFS_REG45__RTAVFSVRBLEEDCNTRL_MASK 0x00000001L |
43543 | #define RTAVFS_REG45__RTAVFSVRENABLE_MASK 0x00000002L |
43544 | #define RTAVFS_REG45__RTAVFSVOLTCODEOVERRIDE_MASK 0x00000FFCL |
43545 | #define RTAVFS_REG45__RTAVFSVOLTCODEOVERRIDESEL_MASK 0x00001000L |
43546 | #define RTAVFS_REG45__RTAVFSLOWPWREN_MASK 0x00002000L |
43547 | #define RTAVFS_REG45__RTAVFSUREGENABLE_MASK 0x00004000L |
43548 | #define RTAVFS_REG45__RTAVFSBGENABLE_MASK 0x00008000L |
43549 | #define RTAVFS_REG45__RTAVFSENABLEVDDRETSENSING_MASK 0x00010000L |
43550 | #define RTAVFS_REG45__RESERVED_MASK 0xFFFE0000L |
43551 | //RTAVFS_REG46 |
43552 | #define RTAVFS_REG46__RTAVFSKP__SHIFT 0x0 |
43553 | #define RTAVFS_REG46__RTAVFSKI__SHIFT 0x4 |
43554 | #define RTAVFS_REG46__RTAVFSPIENABLEANTIWINDUP__SHIFT 0x8 |
43555 | #define RTAVFS_REG46__RTAVFSPISHIFT__SHIFT 0x9 |
43556 | #define RTAVFS_REG46__RTAVFSPIERREN__SHIFT 0xd |
43557 | #define RTAVFS_REG46__RTAVFSPISHIFTOUT__SHIFT 0xe |
43558 | #define RTAVFS_REG46__RTAVFSUSELUTKPKI__SHIFT 0x12 |
43559 | #define RTAVFS_REG46__RESERVED__SHIFT 0x13 |
43560 | #define RTAVFS_REG46__RTAVFSKP_MASK 0x0000000FL |
43561 | #define RTAVFS_REG46__RTAVFSKI_MASK 0x000000F0L |
43562 | #define RTAVFS_REG46__RTAVFSPIENABLEANTIWINDUP_MASK 0x00000100L |
43563 | #define RTAVFS_REG46__RTAVFSPISHIFT_MASK 0x00001E00L |
43564 | #define RTAVFS_REG46__RTAVFSPIERREN_MASK 0x00002000L |
43565 | #define RTAVFS_REG46__RTAVFSPISHIFTOUT_MASK 0x0003C000L |
43566 | #define RTAVFS_REG46__RTAVFSUSELUTKPKI_MASK 0x00040000L |
43567 | #define RTAVFS_REG46__RESERVED_MASK 0xFFF80000L |
43568 | //RTAVFS_REG47 |
43569 | #define RTAVFS_REG47__RTAVFSVOLTCODEPIMIN__SHIFT 0x0 |
43570 | #define RTAVFS_REG47__RTAVFSVOLTCODEPIMAX__SHIFT 0xa |
43571 | #define RTAVFS_REG47__RTAVFSPIERRMASK__SHIFT 0x14 |
43572 | #define RTAVFS_REG47__RTAVFSFORCEDISABLEPI__SHIFT 0x1b |
43573 | #define RTAVFS_REG47__RESERVED__SHIFT 0x1c |
43574 | #define RTAVFS_REG47__RTAVFSVOLTCODEPIMIN_MASK 0x000003FFL |
43575 | #define RTAVFS_REG47__RTAVFSVOLTCODEPIMAX_MASK 0x000FFC00L |
43576 | #define RTAVFS_REG47__RTAVFSPIERRMASK_MASK 0x07F00000L |
43577 | #define RTAVFS_REG47__RTAVFSFORCEDISABLEPI_MASK 0x08000000L |
43578 | #define RTAVFS_REG47__RESERVED_MASK 0xF0000000L |
43579 | //RTAVFS_REG48 |
43580 | #define RTAVFS_REG48__RTAVFSPILOOPNITERATIONS__SHIFT 0x0 |
43581 | #define RTAVFS_REG48__RTAVFSPIERRTHRESHOLD__SHIFT 0x10 |
43582 | #define RTAVFS_REG48__RTAVFSPILOOPNITERATIONS_MASK 0x0000FFFFL |
43583 | #define RTAVFS_REG48__RTAVFSPIERRTHRESHOLD_MASK 0xFFFF0000L |
43584 | //RTAVFS_REG49 |
43585 | #define RTAVFS_REG49__RTAVFSPSMRSTAVGVDD__SHIFT 0x0 |
43586 | #define RTAVFS_REG49__RTAVFSPSMMEASMAXVDD__SHIFT 0x1 |
43587 | #define RTAVFS_REG49__RTAVFSPSMCLKDIVVDD__SHIFT 0x2 |
43588 | #define RTAVFS_REG49__RTAVFSPSMAVGDIVVDD__SHIFT 0x4 |
43589 | #define RTAVFS_REG49__RTAVFSPSMOSCENVDD__SHIFT 0xa |
43590 | #define RTAVFS_REG49__RTAVFSPSMAVGENVDD__SHIFT 0xb |
43591 | #define RTAVFS_REG49__RTAVFSPSMRSTMINMAXVDD__SHIFT 0xc |
43592 | #define RTAVFS_REG49__RESERVED__SHIFT 0xd |
43593 | #define RTAVFS_REG49__RTAVFSPSMRSTAVGVDD_MASK 0x00000001L |
43594 | #define RTAVFS_REG49__RTAVFSPSMMEASMAXVDD_MASK 0x00000002L |
43595 | #define RTAVFS_REG49__RTAVFSPSMCLKDIVVDD_MASK 0x0000000CL |
43596 | #define RTAVFS_REG49__RTAVFSPSMAVGDIVVDD_MASK 0x000003F0L |
43597 | #define RTAVFS_REG49__RTAVFSPSMOSCENVDD_MASK 0x00000400L |
43598 | #define RTAVFS_REG49__RTAVFSPSMAVGENVDD_MASK 0x00000800L |
43599 | #define RTAVFS_REG49__RTAVFSPSMRSTMINMAXVDD_MASK 0x00001000L |
43600 | #define RTAVFS_REG49__RESERVED_MASK 0xFFFFE000L |
43601 | //RTAVFS_REG50 |
43602 | #define RTAVFS_REG50__RTAVFSPSMRSTAVGVREG__SHIFT 0x0 |
43603 | #define RTAVFS_REG50__RTAVFSPSMMEASMAXVREG__SHIFT 0x1 |
43604 | #define RTAVFS_REG50__RTAVFSPSMCLKDIVVREG__SHIFT 0x2 |
43605 | #define RTAVFS_REG50__RTAVFSPSMAVGDIVVREG__SHIFT 0x4 |
43606 | #define RTAVFS_REG50__RTAVFSPSMOSCENVREG__SHIFT 0xa |
43607 | #define RTAVFS_REG50__RTAVFSPSMAVGENVREG__SHIFT 0xb |
43608 | #define RTAVFS_REG50__RTAVFSPSMRSTMINMAXVREG__SHIFT 0xc |
43609 | #define RTAVFS_REG50__RESERVED__SHIFT 0xd |
43610 | #define RTAVFS_REG50__RTAVFSPSMRSTAVGVREG_MASK 0x00000001L |
43611 | #define RTAVFS_REG50__RTAVFSPSMMEASMAXVREG_MASK 0x00000002L |
43612 | #define RTAVFS_REG50__RTAVFSPSMCLKDIVVREG_MASK 0x0000000CL |
43613 | #define RTAVFS_REG50__RTAVFSPSMAVGDIVVREG_MASK 0x000003F0L |
43614 | #define RTAVFS_REG50__RTAVFSPSMOSCENVREG_MASK 0x00000400L |
43615 | #define RTAVFS_REG50__RTAVFSPSMAVGENVREG_MASK 0x00000800L |
43616 | #define RTAVFS_REG50__RTAVFSPSMRSTMINMAXVREG_MASK 0x00001000L |
43617 | #define RTAVFS_REG50__RESERVED_MASK 0xFFFFE000L |
43618 | //RTAVFS_REG51 |
43619 | #define RTAVFS_REG51__RTAVFSAVFSENABLE__SHIFT 0x0 |
43620 | #define RTAVFS_REG51__RTAVFSCPOTURNONDELAY__SHIFT 0x1 |
43621 | #define RTAVFS_REG51__RTAVFSSELECTMINMAX__SHIFT 0x5 |
43622 | #define RTAVFS_REG51__RTAVFSSELECTPERPATHSCALING__SHIFT 0x6 |
43623 | #define RTAVFS_REG51__RTAVFSADDVOLTCODEGUARDBAND__SHIFT 0x7 |
43624 | #define RTAVFS_REG51__RTAVFSSENDAVGPSMTOPSMOUT__SHIFT 0x8 |
43625 | #define RTAVFS_REG51__RTAVFSUPDATEANCHORVOLTAGES__SHIFT 0x9 |
43626 | #define RTAVFS_REG51__RTAVFSSENDVDDTOPSMOUT__SHIFT 0xa |
43627 | #define RTAVFS_REG51__RESERVED__SHIFT 0xb |
43628 | #define RTAVFS_REG51__RTAVFSAVFSENABLE_MASK 0x00000001L |
43629 | #define RTAVFS_REG51__RTAVFSCPOTURNONDELAY_MASK 0x0000001EL |
43630 | #define RTAVFS_REG51__RTAVFSSELECTMINMAX_MASK 0x00000020L |
43631 | #define RTAVFS_REG51__RTAVFSSELECTPERPATHSCALING_MASK 0x00000040L |
43632 | #define RTAVFS_REG51__RTAVFSADDVOLTCODEGUARDBAND_MASK 0x00000080L |
43633 | #define RTAVFS_REG51__RTAVFSSENDAVGPSMTOPSMOUT_MASK 0x00000100L |
43634 | #define RTAVFS_REG51__RTAVFSUPDATEANCHORVOLTAGES_MASK 0x00000200L |
43635 | #define RTAVFS_REG51__RTAVFSSENDVDDTOPSMOUT_MASK 0x00000400L |
43636 | #define RTAVFS_REG51__RESERVED_MASK 0xFFFFF800L |
43637 | //RTAVFS_REG52 |
43638 | #define RTAVFS_REG52__RTAVFSMINMAXPSMVDD__SHIFT 0x0 |
43639 | #define RTAVFS_REG52__RTAVFSAVGPSMVDD__SHIFT 0xe |
43640 | #define RTAVFS_REG52__RESERVED__SHIFT 0x1c |
43641 | #define RTAVFS_REG52__RTAVFSMINMAXPSMVDD_MASK 0x00003FFFL |
43642 | #define RTAVFS_REG52__RTAVFSAVGPSMVDD_MASK 0x0FFFC000L |
43643 | #define RTAVFS_REG52__RESERVED_MASK 0xF0000000L |
43644 | //RTAVFS_REG53 |
43645 | #define RTAVFS_REG53__RTAVFSMINMAXPSMVREG__SHIFT 0x0 |
43646 | #define RTAVFS_REG53__RTAVFSAVGPSMVREG__SHIFT 0xe |
43647 | #define RTAVFS_REG53__RESERVED__SHIFT 0x1c |
43648 | #define RTAVFS_REG53__RTAVFSMINMAXPSMVREG_MASK 0x00003FFFL |
43649 | #define RTAVFS_REG53__RTAVFSAVGPSMVREG_MASK 0x0FFFC000L |
43650 | #define RTAVFS_REG53__RESERVED_MASK 0xF0000000L |
43651 | //RTAVFS_REG54 |
43652 | #define RTAVFS_REG54__RTAVFSCPO0_STARTCNT__SHIFT 0x0 |
43653 | #define RTAVFS_REG54__RTAVFSCPO0_STOPCNT__SHIFT 0x10 |
43654 | #define RTAVFS_REG54__RTAVFSCPO0_STARTCNT_MASK 0x0000FFFFL |
43655 | #define RTAVFS_REG54__RTAVFSCPO0_STOPCNT_MASK 0xFFFF0000L |
43656 | //RTAVFS_REG55 |
43657 | #define RTAVFS_REG55__RTAVFSCPO1_STARTCNT__SHIFT 0x0 |
43658 | #define RTAVFS_REG55__RTAVFSCPO1_STOPCNT__SHIFT 0x10 |
43659 | #define RTAVFS_REG55__RTAVFSCPO1_STARTCNT_MASK 0x0000FFFFL |
43660 | #define RTAVFS_REG55__RTAVFSCPO1_STOPCNT_MASK 0xFFFF0000L |
43661 | //RTAVFS_REG56 |
43662 | #define RTAVFS_REG56__RTAVFSCPO2_STARTCNT__SHIFT 0x0 |
43663 | #define RTAVFS_REG56__RTAVFSCPO2_STOPCNT__SHIFT 0x10 |
43664 | #define RTAVFS_REG56__RTAVFSCPO2_STARTCNT_MASK 0x0000FFFFL |
43665 | #define RTAVFS_REG56__RTAVFSCPO2_STOPCNT_MASK 0xFFFF0000L |
43666 | //RTAVFS_REG57 |
43667 | #define RTAVFS_REG57__RTAVFSCPO3_STARTCNT__SHIFT 0x0 |
43668 | #define RTAVFS_REG57__RTAVFSCPO3_STOPCNT__SHIFT 0x10 |
43669 | #define RTAVFS_REG57__RTAVFSCPO3_STARTCNT_MASK 0x0000FFFFL |
43670 | #define RTAVFS_REG57__RTAVFSCPO3_STOPCNT_MASK 0xFFFF0000L |
43671 | //RTAVFS_REG58 |
43672 | #define RTAVFS_REG58__RTAVFSCPO4_STARTCNT__SHIFT 0x0 |
43673 | #define RTAVFS_REG58__RTAVFSCPO4_STOPCNT__SHIFT 0x10 |
43674 | #define RTAVFS_REG58__RTAVFSCPO4_STARTCNT_MASK 0x0000FFFFL |
43675 | #define RTAVFS_REG58__RTAVFSCPO4_STOPCNT_MASK 0xFFFF0000L |
43676 | //RTAVFS_REG59 |
43677 | #define RTAVFS_REG59__RTAVFSCPO5_STARTCNT__SHIFT 0x0 |
43678 | #define RTAVFS_REG59__RTAVFSCPO5_STOPCNT__SHIFT 0x10 |
43679 | #define RTAVFS_REG59__RTAVFSCPO5_STARTCNT_MASK 0x0000FFFFL |
43680 | #define RTAVFS_REG59__RTAVFSCPO5_STOPCNT_MASK 0xFFFF0000L |
43681 | //RTAVFS_REG60 |
43682 | #define RTAVFS_REG60__RTAVFSCPO6_STARTCNT__SHIFT 0x0 |
43683 | #define RTAVFS_REG60__RTAVFSCPO6_STOPCNT__SHIFT 0x10 |
43684 | #define RTAVFS_REG60__RTAVFSCPO6_STARTCNT_MASK 0x0000FFFFL |
43685 | #define RTAVFS_REG60__RTAVFSCPO6_STOPCNT_MASK 0xFFFF0000L |
43686 | //RTAVFS_REG61 |
43687 | #define RTAVFS_REG61__RTAVFSCPO7_STARTCNT__SHIFT 0x0 |
43688 | #define RTAVFS_REG61__RTAVFSCPO7_STOPCNT__SHIFT 0x10 |
43689 | #define RTAVFS_REG61__RTAVFSCPO7_STARTCNT_MASK 0x0000FFFFL |
43690 | #define RTAVFS_REG61__RTAVFSCPO7_STOPCNT_MASK 0xFFFF0000L |
43691 | //RTAVFS_REG62 |
43692 | #define RTAVFS_REG62__RTAVFSCPO8_STARTCNT__SHIFT 0x0 |
43693 | #define RTAVFS_REG62__RTAVFSCPO8_STOPCNT__SHIFT 0x10 |
43694 | #define RTAVFS_REG62__RTAVFSCPO8_STARTCNT_MASK 0x0000FFFFL |
43695 | #define RTAVFS_REG62__RTAVFSCPO8_STOPCNT_MASK 0xFFFF0000L |
43696 | //RTAVFS_REG63 |
43697 | #define RTAVFS_REG63__RTAVFSCPO9_STARTCNT__SHIFT 0x0 |
43698 | #define RTAVFS_REG63__RTAVFSCPO9_STOPCNT__SHIFT 0x10 |
43699 | #define RTAVFS_REG63__RTAVFSCPO9_STARTCNT_MASK 0x0000FFFFL |
43700 | #define RTAVFS_REG63__RTAVFSCPO9_STOPCNT_MASK 0xFFFF0000L |
43701 | //RTAVFS_REG64 |
43702 | #define RTAVFS_REG64__RTAVFSCPO10_STARTCNT__SHIFT 0x0 |
43703 | #define RTAVFS_REG64__RTAVFSCPO10_STOPCNT__SHIFT 0x10 |
43704 | #define RTAVFS_REG64__RTAVFSCPO10_STARTCNT_MASK 0x0000FFFFL |
43705 | #define RTAVFS_REG64__RTAVFSCPO10_STOPCNT_MASK 0xFFFF0000L |
43706 | //RTAVFS_REG65 |
43707 | #define RTAVFS_REG65__RTAVFSCPO11_STARTCNT__SHIFT 0x0 |
43708 | #define RTAVFS_REG65__RTAVFSCPO11_STOPCNT__SHIFT 0x10 |
43709 | #define RTAVFS_REG65__RTAVFSCPO11_STARTCNT_MASK 0x0000FFFFL |
43710 | #define RTAVFS_REG65__RTAVFSCPO11_STOPCNT_MASK 0xFFFF0000L |
43711 | //RTAVFS_REG66 |
43712 | #define RTAVFS_REG66__RTAVFSCPO12_STARTCNT__SHIFT 0x0 |
43713 | #define RTAVFS_REG66__RTAVFSCPO12_STOPCNT__SHIFT 0x10 |
43714 | #define RTAVFS_REG66__RTAVFSCPO12_STARTCNT_MASK 0x0000FFFFL |
43715 | #define RTAVFS_REG66__RTAVFSCPO12_STOPCNT_MASK 0xFFFF0000L |
43716 | //RTAVFS_REG67 |
43717 | #define RTAVFS_REG67__RTAVFSCPO13_STARTCNT__SHIFT 0x0 |
43718 | #define RTAVFS_REG67__RTAVFSCPO13_STOPCNT__SHIFT 0x10 |
43719 | #define RTAVFS_REG67__RTAVFSCPO13_STARTCNT_MASK 0x0000FFFFL |
43720 | #define RTAVFS_REG67__RTAVFSCPO13_STOPCNT_MASK 0xFFFF0000L |
43721 | //RTAVFS_REG68 |
43722 | #define RTAVFS_REG68__RTAVFSCPO14_STARTCNT__SHIFT 0x0 |
43723 | #define RTAVFS_REG68__RTAVFSCPO14_STOPCNT__SHIFT 0x10 |
43724 | #define RTAVFS_REG68__RTAVFSCPO14_STARTCNT_MASK 0x0000FFFFL |
43725 | #define RTAVFS_REG68__RTAVFSCPO14_STOPCNT_MASK 0xFFFF0000L |
43726 | //RTAVFS_REG69 |
43727 | #define RTAVFS_REG69__RTAVFSCPO15_STARTCNT__SHIFT 0x0 |
43728 | #define RTAVFS_REG69__RTAVFSCPO15_STOPCNT__SHIFT 0x10 |
43729 | #define RTAVFS_REG69__RTAVFSCPO15_STARTCNT_MASK 0x0000FFFFL |
43730 | #define RTAVFS_REG69__RTAVFSCPO15_STOPCNT_MASK 0xFFFF0000L |
43731 | //RTAVFS_REG70 |
43732 | #define RTAVFS_REG70__RTAVFSCPO16_STARTCNT__SHIFT 0x0 |
43733 | #define RTAVFS_REG70__RTAVFSCPO16_STOPCNT__SHIFT 0x10 |
43734 | #define RTAVFS_REG70__RTAVFSCPO16_STARTCNT_MASK 0x0000FFFFL |
43735 | #define RTAVFS_REG70__RTAVFSCPO16_STOPCNT_MASK 0xFFFF0000L |
43736 | //RTAVFS_REG71 |
43737 | #define RTAVFS_REG71__RTAVFSCPO17_STARTCNT__SHIFT 0x0 |
43738 | #define RTAVFS_REG71__RTAVFSCPO17_STOPCNT__SHIFT 0x10 |
43739 | #define RTAVFS_REG71__RTAVFSCPO17_STARTCNT_MASK 0x0000FFFFL |
43740 | #define RTAVFS_REG71__RTAVFSCPO17_STOPCNT_MASK 0xFFFF0000L |
43741 | //RTAVFS_REG72 |
43742 | #define RTAVFS_REG72__RTAVFSCPO18_STARTCNT__SHIFT 0x0 |
43743 | #define RTAVFS_REG72__RTAVFSCPO18_STOPCNT__SHIFT 0x10 |
43744 | #define RTAVFS_REG72__RTAVFSCPO18_STARTCNT_MASK 0x0000FFFFL |
43745 | #define RTAVFS_REG72__RTAVFSCPO18_STOPCNT_MASK 0xFFFF0000L |
43746 | //RTAVFS_REG73 |
43747 | #define RTAVFS_REG73__RTAVFSCPO19_STARTCNT__SHIFT 0x0 |
43748 | #define RTAVFS_REG73__RTAVFSCPO19_STOPCNT__SHIFT 0x10 |
43749 | #define RTAVFS_REG73__RTAVFSCPO19_STARTCNT_MASK 0x0000FFFFL |
43750 | #define RTAVFS_REG73__RTAVFSCPO19_STOPCNT_MASK 0xFFFF0000L |
43751 | //RTAVFS_REG74 |
43752 | #define RTAVFS_REG74__RTAVFSCPO20_STARTCNT__SHIFT 0x0 |
43753 | #define RTAVFS_REG74__RTAVFSCPO20_STOPCNT__SHIFT 0x10 |
43754 | #define RTAVFS_REG74__RTAVFSCPO20_STARTCNT_MASK 0x0000FFFFL |
43755 | #define RTAVFS_REG74__RTAVFSCPO20_STOPCNT_MASK 0xFFFF0000L |
43756 | //RTAVFS_REG75 |
43757 | #define RTAVFS_REG75__RTAVFSCPO21_STARTCNT__SHIFT 0x0 |
43758 | #define RTAVFS_REG75__RTAVFSCPO21_STOPCNT__SHIFT 0x10 |
43759 | #define RTAVFS_REG75__RTAVFSCPO21_STARTCNT_MASK 0x0000FFFFL |
43760 | #define RTAVFS_REG75__RTAVFSCPO21_STOPCNT_MASK 0xFFFF0000L |
43761 | //RTAVFS_REG76 |
43762 | #define RTAVFS_REG76__RTAVFSCPO22_STARTCNT__SHIFT 0x0 |
43763 | #define RTAVFS_REG76__RTAVFSCPO22_STOPCNT__SHIFT 0x10 |
43764 | #define RTAVFS_REG76__RTAVFSCPO22_STARTCNT_MASK 0x0000FFFFL |
43765 | #define RTAVFS_REG76__RTAVFSCPO22_STOPCNT_MASK 0xFFFF0000L |
43766 | //RTAVFS_REG77 |
43767 | #define RTAVFS_REG77__RTAVFSCPO23_STARTCNT__SHIFT 0x0 |
43768 | #define RTAVFS_REG77__RTAVFSCPO23_STOPCNT__SHIFT 0x10 |
43769 | #define RTAVFS_REG77__RTAVFSCPO23_STARTCNT_MASK 0x0000FFFFL |
43770 | #define RTAVFS_REG77__RTAVFSCPO23_STOPCNT_MASK 0xFFFF0000L |
43771 | //RTAVFS_REG78 |
43772 | #define RTAVFS_REG78__RTAVFSCPO24_STARTCNT__SHIFT 0x0 |
43773 | #define RTAVFS_REG78__RTAVFSCPO24_STOPCNT__SHIFT 0x10 |
43774 | #define RTAVFS_REG78__RTAVFSCPO24_STARTCNT_MASK 0x0000FFFFL |
43775 | #define RTAVFS_REG78__RTAVFSCPO24_STOPCNT_MASK 0xFFFF0000L |
43776 | //RTAVFS_REG79 |
43777 | #define RTAVFS_REG79__RTAVFSCPO25_STARTCNT__SHIFT 0x0 |
43778 | #define RTAVFS_REG79__RTAVFSCPO25_STOPCNT__SHIFT 0x10 |
43779 | #define RTAVFS_REG79__RTAVFSCPO25_STARTCNT_MASK 0x0000FFFFL |
43780 | #define RTAVFS_REG79__RTAVFSCPO25_STOPCNT_MASK 0xFFFF0000L |
43781 | //RTAVFS_REG80 |
43782 | #define RTAVFS_REG80__RTAVFSCPO26_STARTCNT__SHIFT 0x0 |
43783 | #define RTAVFS_REG80__RTAVFSCPO26_STOPCNT__SHIFT 0x10 |
43784 | #define RTAVFS_REG80__RTAVFSCPO26_STARTCNT_MASK 0x0000FFFFL |
43785 | #define RTAVFS_REG80__RTAVFSCPO26_STOPCNT_MASK 0xFFFF0000L |
43786 | //RTAVFS_REG81 |
43787 | #define RTAVFS_REG81__RTAVFSCPO27_STARTCNT__SHIFT 0x0 |
43788 | #define RTAVFS_REG81__RTAVFSCPO27_STOPCNT__SHIFT 0x10 |
43789 | #define RTAVFS_REG81__RTAVFSCPO27_STARTCNT_MASK 0x0000FFFFL |
43790 | #define RTAVFS_REG81__RTAVFSCPO27_STOPCNT_MASK 0xFFFF0000L |
43791 | //RTAVFS_REG82 |
43792 | #define RTAVFS_REG82__RTAVFSCPO28_STARTCNT__SHIFT 0x0 |
43793 | #define RTAVFS_REG82__RTAVFSCPO28_STOPCNT__SHIFT 0x10 |
43794 | #define RTAVFS_REG82__RTAVFSCPO28_STARTCNT_MASK 0x0000FFFFL |
43795 | #define RTAVFS_REG82__RTAVFSCPO28_STOPCNT_MASK 0xFFFF0000L |
43796 | //RTAVFS_REG83 |
43797 | #define RTAVFS_REG83__RTAVFSCPO29_STARTCNT__SHIFT 0x0 |
43798 | #define RTAVFS_REG83__RTAVFSCPO29_STOPCNT__SHIFT 0x10 |
43799 | #define RTAVFS_REG83__RTAVFSCPO29_STARTCNT_MASK 0x0000FFFFL |
43800 | #define RTAVFS_REG83__RTAVFSCPO29_STOPCNT_MASK 0xFFFF0000L |
43801 | //RTAVFS_REG84 |
43802 | #define RTAVFS_REG84__RTAVFSCPO30_STARTCNT__SHIFT 0x0 |
43803 | #define RTAVFS_REG84__RTAVFSCPO30_STOPCNT__SHIFT 0x10 |
43804 | #define RTAVFS_REG84__RTAVFSCPO30_STARTCNT_MASK 0x0000FFFFL |
43805 | #define RTAVFS_REG84__RTAVFSCPO30_STOPCNT_MASK 0xFFFF0000L |
43806 | //RTAVFS_REG85 |
43807 | #define RTAVFS_REG85__RTAVFSCPO31_STARTCNT__SHIFT 0x0 |
43808 | #define RTAVFS_REG85__RTAVFSCPO31_STOPCNT__SHIFT 0x10 |
43809 | #define RTAVFS_REG85__RTAVFSCPO31_STARTCNT_MASK 0x0000FFFFL |
43810 | #define RTAVFS_REG85__RTAVFSCPO31_STOPCNT_MASK 0xFFFF0000L |
43811 | //RTAVFS_REG86 |
43812 | #define RTAVFS_REG86__RTAVFSCPO32_STARTCNT__SHIFT 0x0 |
43813 | #define RTAVFS_REG86__RTAVFSCPO32_STOPCNT__SHIFT 0x10 |
43814 | #define RTAVFS_REG86__RTAVFSCPO32_STARTCNT_MASK 0x0000FFFFL |
43815 | #define RTAVFS_REG86__RTAVFSCPO32_STOPCNT_MASK 0xFFFF0000L |
43816 | //RTAVFS_REG87 |
43817 | #define RTAVFS_REG87__RTAVFSCPO33_STARTCNT__SHIFT 0x0 |
43818 | #define RTAVFS_REG87__RTAVFSCPO33_STOPCNT__SHIFT 0x10 |
43819 | #define RTAVFS_REG87__RTAVFSCPO33_STARTCNT_MASK 0x0000FFFFL |
43820 | #define RTAVFS_REG87__RTAVFSCPO33_STOPCNT_MASK 0xFFFF0000L |
43821 | //RTAVFS_REG88 |
43822 | #define RTAVFS_REG88__RTAVFSCPO34_STARTCNT__SHIFT 0x0 |
43823 | #define RTAVFS_REG88__RTAVFSCPO34_STOPCNT__SHIFT 0x10 |
43824 | #define RTAVFS_REG88__RTAVFSCPO34_STARTCNT_MASK 0x0000FFFFL |
43825 | #define RTAVFS_REG88__RTAVFSCPO34_STOPCNT_MASK 0xFFFF0000L |
43826 | //RTAVFS_REG89 |
43827 | #define RTAVFS_REG89__RTAVFSCPO35_STARTCNT__SHIFT 0x0 |
43828 | #define RTAVFS_REG89__RTAVFSCPO35_STOPCNT__SHIFT 0x10 |
43829 | #define RTAVFS_REG89__RTAVFSCPO35_STARTCNT_MASK 0x0000FFFFL |
43830 | #define RTAVFS_REG89__RTAVFSCPO35_STOPCNT_MASK 0xFFFF0000L |
43831 | //RTAVFS_REG90 |
43832 | #define RTAVFS_REG90__RTAVFSCPO36_STARTCNT__SHIFT 0x0 |
43833 | #define RTAVFS_REG90__RTAVFSCPO36_STOPCNT__SHIFT 0x10 |
43834 | #define RTAVFS_REG90__RTAVFSCPO36_STARTCNT_MASK 0x0000FFFFL |
43835 | #define RTAVFS_REG90__RTAVFSCPO36_STOPCNT_MASK 0xFFFF0000L |
43836 | //RTAVFS_REG91 |
43837 | #define RTAVFS_REG91__RTAVFSCPO37_STARTCNT__SHIFT 0x0 |
43838 | #define RTAVFS_REG91__RTAVFSCPO37_STOPCNT__SHIFT 0x10 |
43839 | #define RTAVFS_REG91__RTAVFSCPO37_STARTCNT_MASK 0x0000FFFFL |
43840 | #define RTAVFS_REG91__RTAVFSCPO37_STOPCNT_MASK 0xFFFF0000L |
43841 | //RTAVFS_REG92 |
43842 | #define RTAVFS_REG92__RTAVFSCPO38_STARTCNT__SHIFT 0x0 |
43843 | #define RTAVFS_REG92__RTAVFSCPO38_STOPCNT__SHIFT 0x10 |
43844 | #define RTAVFS_REG92__RTAVFSCPO38_STARTCNT_MASK 0x0000FFFFL |
43845 | #define RTAVFS_REG92__RTAVFSCPO38_STOPCNT_MASK 0xFFFF0000L |
43846 | //RTAVFS_REG93 |
43847 | #define RTAVFS_REG93__RTAVFSCPO39_STARTCNT__SHIFT 0x0 |
43848 | #define RTAVFS_REG93__RTAVFSCPO39_STOPCNT__SHIFT 0x10 |
43849 | #define RTAVFS_REG93__RTAVFSCPO39_STARTCNT_MASK 0x0000FFFFL |
43850 | #define RTAVFS_REG93__RTAVFSCPO39_STOPCNT_MASK 0xFFFF0000L |
43851 | //RTAVFS_REG94 |
43852 | #define RTAVFS_REG94__RTAVFSCPO40_STARTCNT__SHIFT 0x0 |
43853 | #define RTAVFS_REG94__RTAVFSCPO40_STOPCNT__SHIFT 0x10 |
43854 | #define RTAVFS_REG94__RTAVFSCPO40_STARTCNT_MASK 0x0000FFFFL |
43855 | #define RTAVFS_REG94__RTAVFSCPO40_STOPCNT_MASK 0xFFFF0000L |
43856 | //RTAVFS_REG95 |
43857 | #define RTAVFS_REG95__RTAVFSCPO41_STARTCNT__SHIFT 0x0 |
43858 | #define RTAVFS_REG95__RTAVFSCPO41_STOPCNT__SHIFT 0x10 |
43859 | #define RTAVFS_REG95__RTAVFSCPO41_STARTCNT_MASK 0x0000FFFFL |
43860 | #define RTAVFS_REG95__RTAVFSCPO41_STOPCNT_MASK 0xFFFF0000L |
43861 | //RTAVFS_REG96 |
43862 | #define RTAVFS_REG96__RTAVFSCPO42_STARTCNT__SHIFT 0x0 |
43863 | #define RTAVFS_REG96__RTAVFSCPO42_STOPCNT__SHIFT 0x10 |
43864 | #define RTAVFS_REG96__RTAVFSCPO42_STARTCNT_MASK 0x0000FFFFL |
43865 | #define RTAVFS_REG96__RTAVFSCPO42_STOPCNT_MASK 0xFFFF0000L |
43866 | //RTAVFS_REG97 |
43867 | #define RTAVFS_REG97__RTAVFSCPO43_STARTCNT__SHIFT 0x0 |
43868 | #define RTAVFS_REG97__RTAVFSCPO43_STOPCNT__SHIFT 0x10 |
43869 | #define RTAVFS_REG97__RTAVFSCPO43_STARTCNT_MASK 0x0000FFFFL |
43870 | #define RTAVFS_REG97__RTAVFSCPO43_STOPCNT_MASK 0xFFFF0000L |
43871 | //RTAVFS_REG98 |
43872 | #define RTAVFS_REG98__RTAVFSCPO44_STARTCNT__SHIFT 0x0 |
43873 | #define RTAVFS_REG98__RTAVFSCPO44_STOPCNT__SHIFT 0x10 |
43874 | #define RTAVFS_REG98__RTAVFSCPO44_STARTCNT_MASK 0x0000FFFFL |
43875 | #define RTAVFS_REG98__RTAVFSCPO44_STOPCNT_MASK 0xFFFF0000L |
43876 | //RTAVFS_REG99 |
43877 | #define RTAVFS_REG99__RTAVFSCPO45_STARTCNT__SHIFT 0x0 |
43878 | #define RTAVFS_REG99__RTAVFSCPO45_STOPCNT__SHIFT 0x10 |
43879 | #define RTAVFS_REG99__RTAVFSCPO45_STARTCNT_MASK 0x0000FFFFL |
43880 | #define RTAVFS_REG99__RTAVFSCPO45_STOPCNT_MASK 0xFFFF0000L |
43881 | //RTAVFS_REG100 |
43882 | #define RTAVFS_REG100__RTAVFSCPO46_STARTCNT__SHIFT 0x0 |
43883 | #define RTAVFS_REG100__RTAVFSCPO46_STOPCNT__SHIFT 0x10 |
43884 | #define RTAVFS_REG100__RTAVFSCPO46_STARTCNT_MASK 0x0000FFFFL |
43885 | #define RTAVFS_REG100__RTAVFSCPO46_STOPCNT_MASK 0xFFFF0000L |
43886 | //RTAVFS_REG101 |
43887 | #define RTAVFS_REG101__RTAVFSCPO47_STARTCNT__SHIFT 0x0 |
43888 | #define RTAVFS_REG101__RTAVFSCPO47_STOPCNT__SHIFT 0x10 |
43889 | #define RTAVFS_REG101__RTAVFSCPO47_STARTCNT_MASK 0x0000FFFFL |
43890 | #define RTAVFS_REG101__RTAVFSCPO47_STOPCNT_MASK 0xFFFF0000L |
43891 | //RTAVFS_REG102 |
43892 | #define RTAVFS_REG102__RTAVFSCPO48_STARTCNT__SHIFT 0x0 |
43893 | #define RTAVFS_REG102__RTAVFSCPO48_STOPCNT__SHIFT 0x10 |
43894 | #define RTAVFS_REG102__RTAVFSCPO48_STARTCNT_MASK 0x0000FFFFL |
43895 | #define RTAVFS_REG102__RTAVFSCPO48_STOPCNT_MASK 0xFFFF0000L |
43896 | //RTAVFS_REG103 |
43897 | #define RTAVFS_REG103__RTAVFSCPO49_STARTCNT__SHIFT 0x0 |
43898 | #define RTAVFS_REG103__RTAVFSCPO49_STOPCNT__SHIFT 0x10 |
43899 | #define RTAVFS_REG103__RTAVFSCPO49_STARTCNT_MASK 0x0000FFFFL |
43900 | #define RTAVFS_REG103__RTAVFSCPO49_STOPCNT_MASK 0xFFFF0000L |
43901 | //RTAVFS_REG104 |
43902 | #define RTAVFS_REG104__RTAVFSCPO50_STARTCNT__SHIFT 0x0 |
43903 | #define RTAVFS_REG104__RTAVFSCPO50_STOPCNT__SHIFT 0x10 |
43904 | #define RTAVFS_REG104__RTAVFSCPO50_STARTCNT_MASK 0x0000FFFFL |
43905 | #define RTAVFS_REG104__RTAVFSCPO50_STOPCNT_MASK 0xFFFF0000L |
43906 | //RTAVFS_REG105 |
43907 | #define RTAVFS_REG105__RTAVFSCPO51_STARTCNT__SHIFT 0x0 |
43908 | #define RTAVFS_REG105__RTAVFSCPO51_STOPCNT__SHIFT 0x10 |
43909 | #define RTAVFS_REG105__RTAVFSCPO51_STARTCNT_MASK 0x0000FFFFL |
43910 | #define RTAVFS_REG105__RTAVFSCPO51_STOPCNT_MASK 0xFFFF0000L |
43911 | //RTAVFS_REG106 |
43912 | #define RTAVFS_REG106__RTAVFSCPO52_STARTCNT__SHIFT 0x0 |
43913 | #define RTAVFS_REG106__RTAVFSCPO52_STOPCNT__SHIFT 0x10 |
43914 | #define RTAVFS_REG106__RTAVFSCPO52_STARTCNT_MASK 0x0000FFFFL |
43915 | #define RTAVFS_REG106__RTAVFSCPO52_STOPCNT_MASK 0xFFFF0000L |
43916 | //RTAVFS_REG107 |
43917 | #define RTAVFS_REG107__RTAVFSCPO53_STARTCNT__SHIFT 0x0 |
43918 | #define RTAVFS_REG107__RTAVFSCPO53_STOPCNT__SHIFT 0x10 |
43919 | #define RTAVFS_REG107__RTAVFSCPO53_STARTCNT_MASK 0x0000FFFFL |
43920 | #define RTAVFS_REG107__RTAVFSCPO53_STOPCNT_MASK 0xFFFF0000L |
43921 | //RTAVFS_REG108 |
43922 | #define RTAVFS_REG108__RTAVFSCPO54_STARTCNT__SHIFT 0x0 |
43923 | #define RTAVFS_REG108__RTAVFSCPO54_STOPCNT__SHIFT 0x10 |
43924 | #define RTAVFS_REG108__RTAVFSCPO54_STARTCNT_MASK 0x0000FFFFL |
43925 | #define RTAVFS_REG108__RTAVFSCPO54_STOPCNT_MASK 0xFFFF0000L |
43926 | //RTAVFS_REG109 |
43927 | #define RTAVFS_REG109__RTAVFSCPO55_STARTCNT__SHIFT 0x0 |
43928 | #define RTAVFS_REG109__RTAVFSCPO55_STOPCNT__SHIFT 0x10 |
43929 | #define RTAVFS_REG109__RTAVFSCPO55_STARTCNT_MASK 0x0000FFFFL |
43930 | #define RTAVFS_REG109__RTAVFSCPO55_STOPCNT_MASK 0xFFFF0000L |
43931 | //RTAVFS_REG110 |
43932 | #define RTAVFS_REG110__RTAVFSCPO56_STARTCNT__SHIFT 0x0 |
43933 | #define RTAVFS_REG110__RTAVFSCPO56_STOPCNT__SHIFT 0x10 |
43934 | #define RTAVFS_REG110__RTAVFSCPO56_STARTCNT_MASK 0x0000FFFFL |
43935 | #define RTAVFS_REG110__RTAVFSCPO56_STOPCNT_MASK 0xFFFF0000L |
43936 | //RTAVFS_REG111 |
43937 | #define RTAVFS_REG111__RTAVFSCPO57_STARTCNT__SHIFT 0x0 |
43938 | #define RTAVFS_REG111__RTAVFSCPO57_STOPCNT__SHIFT 0x10 |
43939 | #define RTAVFS_REG111__RTAVFSCPO57_STARTCNT_MASK 0x0000FFFFL |
43940 | #define RTAVFS_REG111__RTAVFSCPO57_STOPCNT_MASK 0xFFFF0000L |
43941 | //RTAVFS_REG112 |
43942 | #define RTAVFS_REG112__RTAVFSCPO58_STARTCNT__SHIFT 0x0 |
43943 | #define RTAVFS_REG112__RTAVFSCPO58_STOPCNT__SHIFT 0x10 |
43944 | #define RTAVFS_REG112__RTAVFSCPO58_STARTCNT_MASK 0x0000FFFFL |
43945 | #define RTAVFS_REG112__RTAVFSCPO58_STOPCNT_MASK 0xFFFF0000L |
43946 | //RTAVFS_REG113 |
43947 | #define RTAVFS_REG113__RTAVFSCPO59_STARTCNT__SHIFT 0x0 |
43948 | #define RTAVFS_REG113__RTAVFSCPO59_STOPCNT__SHIFT 0x10 |
43949 | #define RTAVFS_REG113__RTAVFSCPO59_STARTCNT_MASK 0x0000FFFFL |
43950 | #define RTAVFS_REG113__RTAVFSCPO59_STOPCNT_MASK 0xFFFF0000L |
43951 | //RTAVFS_REG114 |
43952 | #define RTAVFS_REG114__RTAVFSCPO60_STARTCNT__SHIFT 0x0 |
43953 | #define RTAVFS_REG114__RTAVFSCPO60_STOPCNT__SHIFT 0x10 |
43954 | #define RTAVFS_REG114__RTAVFSCPO60_STARTCNT_MASK 0x0000FFFFL |
43955 | #define RTAVFS_REG114__RTAVFSCPO60_STOPCNT_MASK 0xFFFF0000L |
43956 | //RTAVFS_REG115 |
43957 | #define RTAVFS_REG115__RTAVFSCPO61_STARTCNT__SHIFT 0x0 |
43958 | #define RTAVFS_REG115__RTAVFSCPO61_STOPCNT__SHIFT 0x10 |
43959 | #define RTAVFS_REG115__RTAVFSCPO61_STARTCNT_MASK 0x0000FFFFL |
43960 | #define RTAVFS_REG115__RTAVFSCPO61_STOPCNT_MASK 0xFFFF0000L |
43961 | //RTAVFS_REG116 |
43962 | #define RTAVFS_REG116__RTAVFSCPO62_STARTCNT__SHIFT 0x0 |
43963 | #define RTAVFS_REG116__RTAVFSCPO62_STOPCNT__SHIFT 0x10 |
43964 | #define RTAVFS_REG116__RTAVFSCPO62_STARTCNT_MASK 0x0000FFFFL |
43965 | #define RTAVFS_REG116__RTAVFSCPO62_STOPCNT_MASK 0xFFFF0000L |
43966 | //RTAVFS_REG117 |
43967 | #define RTAVFS_REG117__RTAVFSCPO63_STARTCNT__SHIFT 0x0 |
43968 | #define RTAVFS_REG117__RTAVFSCPO63_STOPCNT__SHIFT 0x10 |
43969 | #define RTAVFS_REG117__RTAVFSCPO63_STARTCNT_MASK 0x0000FFFFL |
43970 | #define RTAVFS_REG117__RTAVFSCPO63_STOPCNT_MASK 0xFFFF0000L |
43971 | //RTAVFS_REG118 |
43972 | #define RTAVFS_REG118__RTAVFSCPOEN0__SHIFT 0x0 |
43973 | #define RTAVFS_REG118__RTAVFSCPOEN0_MASK 0xFFFFFFFFL |
43974 | //RTAVFS_REG119 |
43975 | #define RTAVFS_REG119__RTAVFSCPOEN1__SHIFT 0x0 |
43976 | #define RTAVFS_REG119__RTAVFSCPOEN1_MASK 0xFFFFFFFFL |
43977 | //RTAVFS_REG120 |
43978 | #define RTAVFS_REG120__RTAVFSCPOAVGDIV0__SHIFT 0x0 |
43979 | #define RTAVFS_REG120__RTAVFSCPOAVGDIV1__SHIFT 0x2 |
43980 | #define RTAVFS_REG120__RTAVFSCPOAVGDIV2__SHIFT 0x4 |
43981 | #define RTAVFS_REG120__RTAVFSCPOAVGDIV3__SHIFT 0x6 |
43982 | #define RTAVFS_REG120__RTAVFSCPOAVGDIV4__SHIFT 0x8 |
43983 | #define RTAVFS_REG120__RTAVFSCPOAVGDIV5__SHIFT 0xa |
43984 | #define RTAVFS_REG120__RTAVFSCPOAVGDIV6__SHIFT 0xc |
43985 | #define RTAVFS_REG120__RTAVFSCPOAVGDIV7__SHIFT 0xe |
43986 | #define RTAVFS_REG120__RTAVFSCPOAVGDIVFINAL__SHIFT 0x10 |
43987 | #define RTAVFS_REG120__RESERVED__SHIFT 0x12 |
43988 | #define RTAVFS_REG120__RTAVFSCPOAVGDIV0_MASK 0x00000003L |
43989 | #define RTAVFS_REG120__RTAVFSCPOAVGDIV1_MASK 0x0000000CL |
43990 | #define RTAVFS_REG120__RTAVFSCPOAVGDIV2_MASK 0x00000030L |
43991 | #define RTAVFS_REG120__RTAVFSCPOAVGDIV3_MASK 0x000000C0L |
43992 | #define RTAVFS_REG120__RTAVFSCPOAVGDIV4_MASK 0x00000300L |
43993 | #define RTAVFS_REG120__RTAVFSCPOAVGDIV5_MASK 0x00000C00L |
43994 | #define RTAVFS_REG120__RTAVFSCPOAVGDIV6_MASK 0x00003000L |
43995 | #define RTAVFS_REG120__RTAVFSCPOAVGDIV7_MASK 0x0000C000L |
43996 | #define RTAVFS_REG120__RTAVFSCPOAVGDIVFINAL_MASK 0x00030000L |
43997 | #define RTAVFS_REG120__RESERVED_MASK 0xFFFC0000L |
43998 | //RTAVFS_REG121 |
43999 | #define RTAVFS_REG121__RTAVFSZONE0INUSE__SHIFT 0x0 |
44000 | #define RTAVFS_REG121__RTAVFSZONE1INUSE__SHIFT 0x1 |
44001 | #define RTAVFS_REG121__RTAVFSZONE2INUSE__SHIFT 0x2 |
44002 | #define RTAVFS_REG121__RTAVFSZONE3INUSE__SHIFT 0x3 |
44003 | #define RTAVFS_REG121__RTAVFSZONE4INUSE__SHIFT 0x4 |
44004 | #define RTAVFS_REG121__RTAVFSRESERVED__SHIFT 0x5 |
44005 | #define RTAVFS_REG121__RTAVFSERRORCODE__SHIFT 0x1c |
44006 | #define RTAVFS_REG121__RTAVFSZONE0INUSE_MASK 0x00000001L |
44007 | #define RTAVFS_REG121__RTAVFSZONE1INUSE_MASK 0x00000002L |
44008 | #define RTAVFS_REG121__RTAVFSZONE2INUSE_MASK 0x00000004L |
44009 | #define RTAVFS_REG121__RTAVFSZONE3INUSE_MASK 0x00000008L |
44010 | #define RTAVFS_REG121__RTAVFSZONE4INUSE_MASK 0x00000010L |
44011 | #define RTAVFS_REG121__RTAVFSRESERVED_MASK 0x0FFFFFE0L |
44012 | #define RTAVFS_REG121__RTAVFSERRORCODE_MASK 0xF0000000L |
44013 | //RTAVFS_REG122 |
44014 | #define RTAVFS_REG122__RTAVFSCPO0_RIPPLECNT__SHIFT 0x0 |
44015 | #define RTAVFS_REG122__RESERVED__SHIFT 0x10 |
44016 | #define RTAVFS_REG122__RTAVFSCPO0_RIPPLECNT_MASK 0x0000FFFFL |
44017 | #define RTAVFS_REG122__RESERVED_MASK 0xFFFF0000L |
44018 | //RTAVFS_REG123 |
44019 | #define RTAVFS_REG123__RTAVFSCPO1_RIPPLECNT__SHIFT 0x0 |
44020 | #define RTAVFS_REG123__RESERVED__SHIFT 0x10 |
44021 | #define RTAVFS_REG123__RTAVFSCPO1_RIPPLECNT_MASK 0x0000FFFFL |
44022 | #define RTAVFS_REG123__RESERVED_MASK 0xFFFF0000L |
44023 | //RTAVFS_REG124 |
44024 | #define RTAVFS_REG124__RTAVFSCPO2_RIPPLECNT__SHIFT 0x0 |
44025 | #define RTAVFS_REG124__RESERVED__SHIFT 0x10 |
44026 | #define RTAVFS_REG124__RTAVFSCPO2_RIPPLECNT_MASK 0x0000FFFFL |
44027 | #define RTAVFS_REG124__RESERVED_MASK 0xFFFF0000L |
44028 | //RTAVFS_REG125 |
44029 | #define RTAVFS_REG125__RTAVFSCPO3_RIPPLECNT__SHIFT 0x0 |
44030 | #define RTAVFS_REG125__RESERVED__SHIFT 0x10 |
44031 | #define RTAVFS_REG125__RTAVFSCPO3_RIPPLECNT_MASK 0x0000FFFFL |
44032 | #define RTAVFS_REG125__RESERVED_MASK 0xFFFF0000L |
44033 | //RTAVFS_REG126 |
44034 | #define RTAVFS_REG126__RTAVFSCPO4_RIPPLECNT__SHIFT 0x0 |
44035 | #define RTAVFS_REG126__RESERVED__SHIFT 0x10 |
44036 | #define RTAVFS_REG126__RTAVFSCPO4_RIPPLECNT_MASK 0x0000FFFFL |
44037 | #define RTAVFS_REG126__RESERVED_MASK 0xFFFF0000L |
44038 | //RTAVFS_REG127 |
44039 | #define RTAVFS_REG127__RTAVFSCPO5_RIPPLECNT__SHIFT 0x0 |
44040 | #define RTAVFS_REG127__RESERVED__SHIFT 0x10 |
44041 | #define RTAVFS_REG127__RTAVFSCPO5_RIPPLECNT_MASK 0x0000FFFFL |
44042 | #define RTAVFS_REG127__RESERVED_MASK 0xFFFF0000L |
44043 | //RTAVFS_REG128 |
44044 | #define RTAVFS_REG128__RTAVFSCPO6_RIPPLECNT__SHIFT 0x0 |
44045 | #define RTAVFS_REG128__RESERVED__SHIFT 0x10 |
44046 | #define RTAVFS_REG128__RTAVFSCPO6_RIPPLECNT_MASK 0x0000FFFFL |
44047 | #define RTAVFS_REG128__RESERVED_MASK 0xFFFF0000L |
44048 | //RTAVFS_REG129 |
44049 | #define RTAVFS_REG129__RTAVFSCPO7_RIPPLECNT__SHIFT 0x0 |
44050 | #define RTAVFS_REG129__RESERVED__SHIFT 0x10 |
44051 | #define RTAVFS_REG129__RTAVFSCPO7_RIPPLECNT_MASK 0x0000FFFFL |
44052 | #define RTAVFS_REG129__RESERVED_MASK 0xFFFF0000L |
44053 | //RTAVFS_REG130 |
44054 | #define RTAVFS_REG130__RTAVFSCPO8_RIPPLECNT__SHIFT 0x0 |
44055 | #define RTAVFS_REG130__RESERVED__SHIFT 0x10 |
44056 | #define RTAVFS_REG130__RTAVFSCPO8_RIPPLECNT_MASK 0x0000FFFFL |
44057 | #define RTAVFS_REG130__RESERVED_MASK 0xFFFF0000L |
44058 | //RTAVFS_REG131 |
44059 | #define RTAVFS_REG131__RTAVFSCPO9_RIPPLECNT__SHIFT 0x0 |
44060 | #define RTAVFS_REG131__RESERVED__SHIFT 0x10 |
44061 | #define RTAVFS_REG131__RTAVFSCPO9_RIPPLECNT_MASK 0x0000FFFFL |
44062 | #define RTAVFS_REG131__RESERVED_MASK 0xFFFF0000L |
44063 | //RTAVFS_REG132 |
44064 | #define RTAVFS_REG132__RTAVFSCPO10_RIPPLECNT__SHIFT 0x0 |
44065 | #define RTAVFS_REG132__RESERVED__SHIFT 0x10 |
44066 | #define RTAVFS_REG132__RTAVFSCPO10_RIPPLECNT_MASK 0x0000FFFFL |
44067 | #define RTAVFS_REG132__RESERVED_MASK 0xFFFF0000L |
44068 | //RTAVFS_REG133 |
44069 | #define RTAVFS_REG133__RTAVFSCPO11_RIPPLECNT__SHIFT 0x0 |
44070 | #define RTAVFS_REG133__RESERVED__SHIFT 0x10 |
44071 | #define RTAVFS_REG133__RTAVFSCPO11_RIPPLECNT_MASK 0x0000FFFFL |
44072 | #define RTAVFS_REG133__RESERVED_MASK 0xFFFF0000L |
44073 | //RTAVFS_REG134 |
44074 | #define RTAVFS_REG134__RTAVFSCPO12_RIPPLECNT__SHIFT 0x0 |
44075 | #define RTAVFS_REG134__RESERVED__SHIFT 0x10 |
44076 | #define RTAVFS_REG134__RTAVFSCPO12_RIPPLECNT_MASK 0x0000FFFFL |
44077 | #define RTAVFS_REG134__RESERVED_MASK 0xFFFF0000L |
44078 | //RTAVFS_REG135 |
44079 | #define RTAVFS_REG135__RTAVFSCPO13_RIPPLECNT__SHIFT 0x0 |
44080 | #define RTAVFS_REG135__RESERVED__SHIFT 0x10 |
44081 | #define RTAVFS_REG135__RTAVFSCPO13_RIPPLECNT_MASK 0x0000FFFFL |
44082 | #define RTAVFS_REG135__RESERVED_MASK 0xFFFF0000L |
44083 | //RTAVFS_REG136 |
44084 | #define RTAVFS_REG136__RTAVFSCPO14_RIPPLECNT__SHIFT 0x0 |
44085 | #define RTAVFS_REG136__RESERVED__SHIFT 0x10 |
44086 | #define RTAVFS_REG136__RTAVFSCPO14_RIPPLECNT_MASK 0x0000FFFFL |
44087 | #define RTAVFS_REG136__RESERVED_MASK 0xFFFF0000L |
44088 | //RTAVFS_REG137 |
44089 | #define RTAVFS_REG137__RTAVFSCPO15_RIPPLECNT__SHIFT 0x0 |
44090 | #define RTAVFS_REG137__RESERVED__SHIFT 0x10 |
44091 | #define RTAVFS_REG137__RTAVFSCPO15_RIPPLECNT_MASK 0x0000FFFFL |
44092 | #define RTAVFS_REG137__RESERVED_MASK 0xFFFF0000L |
44093 | //RTAVFS_REG138 |
44094 | #define RTAVFS_REG138__RTAVFSCPO16_RIPPLECNT__SHIFT 0x0 |
44095 | #define RTAVFS_REG138__RESERVED__SHIFT 0x10 |
44096 | #define RTAVFS_REG138__RTAVFSCPO16_RIPPLECNT_MASK 0x0000FFFFL |
44097 | #define RTAVFS_REG138__RESERVED_MASK 0xFFFF0000L |
44098 | //RTAVFS_REG139 |
44099 | #define RTAVFS_REG139__RTAVFSCPO17_RIPPLECNT__SHIFT 0x0 |
44100 | #define RTAVFS_REG139__RESERVED__SHIFT 0x10 |
44101 | #define RTAVFS_REG139__RTAVFSCPO17_RIPPLECNT_MASK 0x0000FFFFL |
44102 | #define RTAVFS_REG139__RESERVED_MASK 0xFFFF0000L |
44103 | //RTAVFS_REG140 |
44104 | #define RTAVFS_REG140__RTAVFSCPO18_RIPPLECNT__SHIFT 0x0 |
44105 | #define RTAVFS_REG140__RESERVED__SHIFT 0x10 |
44106 | #define RTAVFS_REG140__RTAVFSCPO18_RIPPLECNT_MASK 0x0000FFFFL |
44107 | #define RTAVFS_REG140__RESERVED_MASK 0xFFFF0000L |
44108 | //RTAVFS_REG141 |
44109 | #define RTAVFS_REG141__RTAVFSCPO19_RIPPLECNT__SHIFT 0x0 |
44110 | #define RTAVFS_REG141__RESERVED__SHIFT 0x10 |
44111 | #define RTAVFS_REG141__RTAVFSCPO19_RIPPLECNT_MASK 0x0000FFFFL |
44112 | #define RTAVFS_REG141__RESERVED_MASK 0xFFFF0000L |
44113 | //RTAVFS_REG142 |
44114 | #define RTAVFS_REG142__RTAVFSCPO20_RIPPLECNT__SHIFT 0x0 |
44115 | #define RTAVFS_REG142__RESERVED__SHIFT 0x10 |
44116 | #define RTAVFS_REG142__RTAVFSCPO20_RIPPLECNT_MASK 0x0000FFFFL |
44117 | #define RTAVFS_REG142__RESERVED_MASK 0xFFFF0000L |
44118 | //RTAVFS_REG143 |
44119 | #define RTAVFS_REG143__RTAVFSCPO21_RIPPLECNT__SHIFT 0x0 |
44120 | #define RTAVFS_REG143__RESERVED__SHIFT 0x10 |
44121 | #define RTAVFS_REG143__RTAVFSCPO21_RIPPLECNT_MASK 0x0000FFFFL |
44122 | #define RTAVFS_REG143__RESERVED_MASK 0xFFFF0000L |
44123 | //RTAVFS_REG144 |
44124 | #define RTAVFS_REG144__RTAVFSCPO22_RIPPLECNT__SHIFT 0x0 |
44125 | #define RTAVFS_REG144__RESERVED__SHIFT 0x10 |
44126 | #define RTAVFS_REG144__RTAVFSCPO22_RIPPLECNT_MASK 0x0000FFFFL |
44127 | #define RTAVFS_REG144__RESERVED_MASK 0xFFFF0000L |
44128 | //RTAVFS_REG145 |
44129 | #define RTAVFS_REG145__RTAVFSCPO23_RIPPLECNT__SHIFT 0x0 |
44130 | #define RTAVFS_REG145__RESERVED__SHIFT 0x10 |
44131 | #define RTAVFS_REG145__RTAVFSCPO23_RIPPLECNT_MASK 0x0000FFFFL |
44132 | #define RTAVFS_REG145__RESERVED_MASK 0xFFFF0000L |
44133 | //RTAVFS_REG146 |
44134 | #define RTAVFS_REG146__RTAVFSCPO24_RIPPLECNT__SHIFT 0x0 |
44135 | #define RTAVFS_REG146__RESERVED__SHIFT 0x10 |
44136 | #define RTAVFS_REG146__RTAVFSCPO24_RIPPLECNT_MASK 0x0000FFFFL |
44137 | #define RTAVFS_REG146__RESERVED_MASK 0xFFFF0000L |
44138 | //RTAVFS_REG147 |
44139 | #define RTAVFS_REG147__RTAVFSCPO25_RIPPLECNT__SHIFT 0x0 |
44140 | #define RTAVFS_REG147__RESERVED__SHIFT 0x10 |
44141 | #define RTAVFS_REG147__RTAVFSCPO25_RIPPLECNT_MASK 0x0000FFFFL |
44142 | #define RTAVFS_REG147__RESERVED_MASK 0xFFFF0000L |
44143 | //RTAVFS_REG148 |
44144 | #define RTAVFS_REG148__RTAVFSCPO26_RIPPLECNT__SHIFT 0x0 |
44145 | #define RTAVFS_REG148__RESERVED__SHIFT 0x10 |
44146 | #define RTAVFS_REG148__RTAVFSCPO26_RIPPLECNT_MASK 0x0000FFFFL |
44147 | #define RTAVFS_REG148__RESERVED_MASK 0xFFFF0000L |
44148 | //RTAVFS_REG149 |
44149 | #define RTAVFS_REG149__RTAVFSCPO27_RIPPLECNT__SHIFT 0x0 |
44150 | #define RTAVFS_REG149__RESERVED__SHIFT 0x10 |
44151 | #define RTAVFS_REG149__RTAVFSCPO27_RIPPLECNT_MASK 0x0000FFFFL |
44152 | #define RTAVFS_REG149__RESERVED_MASK 0xFFFF0000L |
44153 | //RTAVFS_REG150 |
44154 | #define RTAVFS_REG150__RTAVFSCPO28_RIPPLECNT__SHIFT 0x0 |
44155 | #define RTAVFS_REG150__RESERVED__SHIFT 0x10 |
44156 | #define RTAVFS_REG150__RTAVFSCPO28_RIPPLECNT_MASK 0x0000FFFFL |
44157 | #define RTAVFS_REG150__RESERVED_MASK 0xFFFF0000L |
44158 | //RTAVFS_REG151 |
44159 | #define RTAVFS_REG151__RTAVFSCPO29_RIPPLECNT__SHIFT 0x0 |
44160 | #define RTAVFS_REG151__RESERVED__SHIFT 0x10 |
44161 | #define RTAVFS_REG151__RTAVFSCPO29_RIPPLECNT_MASK 0x0000FFFFL |
44162 | #define RTAVFS_REG151__RESERVED_MASK 0xFFFF0000L |
44163 | //RTAVFS_REG152 |
44164 | #define RTAVFS_REG152__RTAVFSCPO30_RIPPLECNT__SHIFT 0x0 |
44165 | #define RTAVFS_REG152__RESERVED__SHIFT 0x10 |
44166 | #define RTAVFS_REG152__RTAVFSCPO30_RIPPLECNT_MASK 0x0000FFFFL |
44167 | #define RTAVFS_REG152__RESERVED_MASK 0xFFFF0000L |
44168 | //RTAVFS_REG153 |
44169 | #define RTAVFS_REG153__RTAVFSCPO31_RIPPLECNT__SHIFT 0x0 |
44170 | #define RTAVFS_REG153__RESERVED__SHIFT 0x10 |
44171 | #define RTAVFS_REG153__RTAVFSCPO31_RIPPLECNT_MASK 0x0000FFFFL |
44172 | #define RTAVFS_REG153__RESERVED_MASK 0xFFFF0000L |
44173 | //RTAVFS_REG154 |
44174 | #define RTAVFS_REG154__RTAVFSCPO32_RIPPLECNT__SHIFT 0x0 |
44175 | #define RTAVFS_REG154__RESERVED__SHIFT 0x10 |
44176 | #define RTAVFS_REG154__RTAVFSCPO32_RIPPLECNT_MASK 0x0000FFFFL |
44177 | #define RTAVFS_REG154__RESERVED_MASK 0xFFFF0000L |
44178 | //RTAVFS_REG155 |
44179 | #define RTAVFS_REG155__RTAVFSCPO33_RIPPLECNT__SHIFT 0x0 |
44180 | #define RTAVFS_REG155__RESERVED__SHIFT 0x10 |
44181 | #define RTAVFS_REG155__RTAVFSCPO33_RIPPLECNT_MASK 0x0000FFFFL |
44182 | #define RTAVFS_REG155__RESERVED_MASK 0xFFFF0000L |
44183 | //RTAVFS_REG156 |
44184 | #define RTAVFS_REG156__RTAVFSCPO34_RIPPLECNT__SHIFT 0x0 |
44185 | #define RTAVFS_REG156__RESERVED__SHIFT 0x10 |
44186 | #define RTAVFS_REG156__RTAVFSCPO34_RIPPLECNT_MASK 0x0000FFFFL |
44187 | #define RTAVFS_REG156__RESERVED_MASK 0xFFFF0000L |
44188 | //RTAVFS_REG157 |
44189 | #define RTAVFS_REG157__RTAVFSCPO35_RIPPLECNT__SHIFT 0x0 |
44190 | #define RTAVFS_REG157__RESERVED__SHIFT 0x10 |
44191 | #define RTAVFS_REG157__RTAVFSCPO35_RIPPLECNT_MASK 0x0000FFFFL |
44192 | #define RTAVFS_REG157__RESERVED_MASK 0xFFFF0000L |
44193 | //RTAVFS_REG158 |
44194 | #define RTAVFS_REG158__RTAVFSCPO36_RIPPLECNT__SHIFT 0x0 |
44195 | #define RTAVFS_REG158__RESERVED__SHIFT 0x10 |
44196 | #define RTAVFS_REG158__RTAVFSCPO36_RIPPLECNT_MASK 0x0000FFFFL |
44197 | #define RTAVFS_REG158__RESERVED_MASK 0xFFFF0000L |
44198 | //RTAVFS_REG159 |
44199 | #define RTAVFS_REG159__RTAVFSCPO37_RIPPLECNT__SHIFT 0x0 |
44200 | #define RTAVFS_REG159__RESERVED__SHIFT 0x10 |
44201 | #define RTAVFS_REG159__RTAVFSCPO37_RIPPLECNT_MASK 0x0000FFFFL |
44202 | #define RTAVFS_REG159__RESERVED_MASK 0xFFFF0000L |
44203 | //RTAVFS_REG160 |
44204 | #define RTAVFS_REG160__RTAVFSCPO38_RIPPLECNT__SHIFT 0x0 |
44205 | #define RTAVFS_REG160__RESERVED__SHIFT 0x10 |
44206 | #define RTAVFS_REG160__RTAVFSCPO38_RIPPLECNT_MASK 0x0000FFFFL |
44207 | #define RTAVFS_REG160__RESERVED_MASK 0xFFFF0000L |
44208 | //RTAVFS_REG161 |
44209 | #define RTAVFS_REG161__RTAVFSCPO39_RIPPLECNT__SHIFT 0x0 |
44210 | #define RTAVFS_REG161__RESERVED__SHIFT 0x10 |
44211 | #define RTAVFS_REG161__RTAVFSCPO39_RIPPLECNT_MASK 0x0000FFFFL |
44212 | #define RTAVFS_REG161__RESERVED_MASK 0xFFFF0000L |
44213 | //RTAVFS_REG162 |
44214 | #define RTAVFS_REG162__RTAVFSCPO40_RIPPLECNT__SHIFT 0x0 |
44215 | #define RTAVFS_REG162__RESERVED__SHIFT 0x10 |
44216 | #define RTAVFS_REG162__RTAVFSCPO40_RIPPLECNT_MASK 0x0000FFFFL |
44217 | #define RTAVFS_REG162__RESERVED_MASK 0xFFFF0000L |
44218 | //RTAVFS_REG163 |
44219 | #define RTAVFS_REG163__RTAVFSCPO41_RIPPLECNT__SHIFT 0x0 |
44220 | #define RTAVFS_REG163__RESERVED__SHIFT 0x10 |
44221 | #define RTAVFS_REG163__RTAVFSCPO41_RIPPLECNT_MASK 0x0000FFFFL |
44222 | #define RTAVFS_REG163__RESERVED_MASK 0xFFFF0000L |
44223 | //RTAVFS_REG164 |
44224 | #define RTAVFS_REG164__RTAVFSCPO42_RIPPLECNT__SHIFT 0x0 |
44225 | #define RTAVFS_REG164__RESERVED__SHIFT 0x10 |
44226 | #define RTAVFS_REG164__RTAVFSCPO42_RIPPLECNT_MASK 0x0000FFFFL |
44227 | #define RTAVFS_REG164__RESERVED_MASK 0xFFFF0000L |
44228 | //RTAVFS_REG165 |
44229 | #define RTAVFS_REG165__RTAVFSCPO43_RIPPLECNT__SHIFT 0x0 |
44230 | #define RTAVFS_REG165__RESERVED__SHIFT 0x10 |
44231 | #define RTAVFS_REG165__RTAVFSCPO43_RIPPLECNT_MASK 0x0000FFFFL |
44232 | #define RTAVFS_REG165__RESERVED_MASK 0xFFFF0000L |
44233 | //RTAVFS_REG166 |
44234 | #define RTAVFS_REG166__RTAVFSCPO44_RIPPLECNT__SHIFT 0x0 |
44235 | #define RTAVFS_REG166__RESERVED__SHIFT 0x10 |
44236 | #define RTAVFS_REG166__RTAVFSCPO44_RIPPLECNT_MASK 0x0000FFFFL |
44237 | #define RTAVFS_REG166__RESERVED_MASK 0xFFFF0000L |
44238 | //RTAVFS_REG167 |
44239 | #define RTAVFS_REG167__RTAVFSCPO45_RIPPLECNT__SHIFT 0x0 |
44240 | #define RTAVFS_REG167__RESERVED__SHIFT 0x10 |
44241 | #define RTAVFS_REG167__RTAVFSCPO45_RIPPLECNT_MASK 0x0000FFFFL |
44242 | #define RTAVFS_REG167__RESERVED_MASK 0xFFFF0000L |
44243 | //RTAVFS_REG168 |
44244 | #define RTAVFS_REG168__RTAVFSCPO46_RIPPLECNT__SHIFT 0x0 |
44245 | #define RTAVFS_REG168__RESERVED__SHIFT 0x10 |
44246 | #define RTAVFS_REG168__RTAVFSCPO46_RIPPLECNT_MASK 0x0000FFFFL |
44247 | #define RTAVFS_REG168__RESERVED_MASK 0xFFFF0000L |
44248 | //RTAVFS_REG169 |
44249 | #define RTAVFS_REG169__RTAVFSCPO47_RIPPLECNT__SHIFT 0x0 |
44250 | #define RTAVFS_REG169__RESERVED__SHIFT 0x10 |
44251 | #define RTAVFS_REG169__RTAVFSCPO47_RIPPLECNT_MASK 0x0000FFFFL |
44252 | #define RTAVFS_REG169__RESERVED_MASK 0xFFFF0000L |
44253 | //RTAVFS_REG170 |
44254 | #define RTAVFS_REG170__RTAVFSCPO48_RIPPLECNT__SHIFT 0x0 |
44255 | #define RTAVFS_REG170__RESERVED__SHIFT 0x10 |
44256 | #define RTAVFS_REG170__RTAVFSCPO48_RIPPLECNT_MASK 0x0000FFFFL |
44257 | #define RTAVFS_REG170__RESERVED_MASK 0xFFFF0000L |
44258 | //RTAVFS_REG171 |
44259 | #define RTAVFS_REG171__RTAVFSCPO49_RIPPLECNT__SHIFT 0x0 |
44260 | #define RTAVFS_REG171__RESERVED__SHIFT 0x10 |
44261 | #define RTAVFS_REG171__RTAVFSCPO49_RIPPLECNT_MASK 0x0000FFFFL |
44262 | #define RTAVFS_REG171__RESERVED_MASK 0xFFFF0000L |
44263 | //RTAVFS_REG172 |
44264 | #define RTAVFS_REG172__RTAVFSCPO50_RIPPLECNT__SHIFT 0x0 |
44265 | #define RTAVFS_REG172__RESERVED__SHIFT 0x10 |
44266 | #define RTAVFS_REG172__RTAVFSCPO50_RIPPLECNT_MASK 0x0000FFFFL |
44267 | #define RTAVFS_REG172__RESERVED_MASK 0xFFFF0000L |
44268 | //RTAVFS_REG173 |
44269 | #define RTAVFS_REG173__RTAVFSCPO51_RIPPLECNT__SHIFT 0x0 |
44270 | #define RTAVFS_REG173__RESERVED__SHIFT 0x10 |
44271 | #define RTAVFS_REG173__RTAVFSCPO51_RIPPLECNT_MASK 0x0000FFFFL |
44272 | #define RTAVFS_REG173__RESERVED_MASK 0xFFFF0000L |
44273 | //RTAVFS_REG174 |
44274 | #define RTAVFS_REG174__RTAVFSCPO52_RIPPLECNT__SHIFT 0x0 |
44275 | #define RTAVFS_REG174__RESERVED__SHIFT 0x10 |
44276 | #define RTAVFS_REG174__RTAVFSCPO52_RIPPLECNT_MASK 0x0000FFFFL |
44277 | #define RTAVFS_REG174__RESERVED_MASK 0xFFFF0000L |
44278 | //RTAVFS_REG175 |
44279 | #define RTAVFS_REG175__RTAVFSCPO53_RIPPLECNT__SHIFT 0x0 |
44280 | #define RTAVFS_REG175__RESERVED__SHIFT 0x10 |
44281 | #define RTAVFS_REG175__RTAVFSCPO53_RIPPLECNT_MASK 0x0000FFFFL |
44282 | #define RTAVFS_REG175__RESERVED_MASK 0xFFFF0000L |
44283 | //RTAVFS_REG176 |
44284 | #define RTAVFS_REG176__RTAVFSCPO54_RIPPLECNT__SHIFT 0x0 |
44285 | #define RTAVFS_REG176__RESERVED__SHIFT 0x10 |
44286 | #define RTAVFS_REG176__RTAVFSCPO54_RIPPLECNT_MASK 0x0000FFFFL |
44287 | #define RTAVFS_REG176__RESERVED_MASK 0xFFFF0000L |
44288 | //RTAVFS_REG177 |
44289 | #define RTAVFS_REG177__RTAVFSCPO55_RIPPLECNT__SHIFT 0x0 |
44290 | #define RTAVFS_REG177__RESERVED__SHIFT 0x10 |
44291 | #define RTAVFS_REG177__RTAVFSCPO55_RIPPLECNT_MASK 0x0000FFFFL |
44292 | #define RTAVFS_REG177__RESERVED_MASK 0xFFFF0000L |
44293 | //RTAVFS_REG178 |
44294 | #define RTAVFS_REG178__RTAVFSCPO56_RIPPLECNT__SHIFT 0x0 |
44295 | #define RTAVFS_REG178__RESERVED__SHIFT 0x10 |
44296 | #define RTAVFS_REG178__RTAVFSCPO56_RIPPLECNT_MASK 0x0000FFFFL |
44297 | #define RTAVFS_REG178__RESERVED_MASK 0xFFFF0000L |
44298 | //RTAVFS_REG179 |
44299 | #define RTAVFS_REG179__RTAVFSCPO57_RIPPLECNT__SHIFT 0x0 |
44300 | #define RTAVFS_REG179__RESERVED__SHIFT 0x10 |
44301 | #define RTAVFS_REG179__RTAVFSCPO57_RIPPLECNT_MASK 0x0000FFFFL |
44302 | #define RTAVFS_REG179__RESERVED_MASK 0xFFFF0000L |
44303 | //RTAVFS_REG180 |
44304 | #define RTAVFS_REG180__RTAVFSCPO58_RIPPLECNT__SHIFT 0x0 |
44305 | #define RTAVFS_REG180__RESERVED__SHIFT 0x10 |
44306 | #define RTAVFS_REG180__RTAVFSCPO58_RIPPLECNT_MASK 0x0000FFFFL |
44307 | #define RTAVFS_REG180__RESERVED_MASK 0xFFFF0000L |
44308 | //RTAVFS_REG181 |
44309 | #define RTAVFS_REG181__RTAVFSCPO59_RIPPLECNT__SHIFT 0x0 |
44310 | #define RTAVFS_REG181__RESERVED__SHIFT 0x10 |
44311 | #define RTAVFS_REG181__RTAVFSCPO59_RIPPLECNT_MASK 0x0000FFFFL |
44312 | #define RTAVFS_REG181__RESERVED_MASK 0xFFFF0000L |
44313 | //RTAVFS_REG182 |
44314 | #define RTAVFS_REG182__RTAVFSCPO60_RIPPLECNT__SHIFT 0x0 |
44315 | #define RTAVFS_REG182__RESERVED__SHIFT 0x10 |
44316 | #define RTAVFS_REG182__RTAVFSCPO60_RIPPLECNT_MASK 0x0000FFFFL |
44317 | #define RTAVFS_REG182__RESERVED_MASK 0xFFFF0000L |
44318 | //RTAVFS_REG183 |
44319 | #define RTAVFS_REG183__RTAVFSCPO61_RIPPLECNT__SHIFT 0x0 |
44320 | #define RTAVFS_REG183__RESERVED__SHIFT 0x10 |
44321 | #define RTAVFS_REG183__RTAVFSCPO61_RIPPLECNT_MASK 0x0000FFFFL |
44322 | #define RTAVFS_REG183__RESERVED_MASK 0xFFFF0000L |
44323 | //RTAVFS_REG184 |
44324 | #define RTAVFS_REG184__RTAVFSCPO62_RIPPLECNT__SHIFT 0x0 |
44325 | #define RTAVFS_REG184__RESERVED__SHIFT 0x10 |
44326 | #define RTAVFS_REG184__RTAVFSCPO62_RIPPLECNT_MASK 0x0000FFFFL |
44327 | #define RTAVFS_REG184__RESERVED_MASK 0xFFFF0000L |
44328 | //RTAVFS_REG185 |
44329 | #define RTAVFS_REG185__RTAVFSCPO63_RIPPLECNT__SHIFT 0x0 |
44330 | #define RTAVFS_REG185__RESERVED__SHIFT 0x10 |
44331 | #define RTAVFS_REG185__RTAVFSCPO63_RIPPLECNT_MASK 0x0000FFFFL |
44332 | #define RTAVFS_REG185__RESERVED_MASK 0xFFFF0000L |
44333 | //RTAVFS_REG186 |
44334 | #define RTAVFS_REG186__RTAVFSTARGETFREQCNTOVERRIDE__SHIFT 0x0 |
44335 | #define RTAVFS_REG186__RTAVFSTARGETFREQCNTOVERRIDESEL__SHIFT 0x10 |
44336 | #define RTAVFS_REG186__RESERVED__SHIFT 0x11 |
44337 | #define RTAVFS_REG186__RTAVFSTARGETFREQCNTOVERRIDE_MASK 0x0000FFFFL |
44338 | #define RTAVFS_REG186__RTAVFSTARGETFREQCNTOVERRIDESEL_MASK 0x00010000L |
44339 | #define RTAVFS_REG186__RESERVED_MASK 0xFFFE0000L |
44340 | //RTAVFS_REG187 |
44341 | #define RTAVFS_REG187__RTAVFSCURRENTFREQCNTOVERRIDE__SHIFT 0x0 |
44342 | #define RTAVFS_REG187__RTAVFSCURRENTFREQCNTOVERRIDESEL__SHIFT 0x10 |
44343 | #define RTAVFS_REG187__RESERVED__SHIFT 0x11 |
44344 | #define RTAVFS_REG187__RTAVFSCURRENTFREQCNTOVERRIDE_MASK 0x0000FFFFL |
44345 | #define RTAVFS_REG187__RTAVFSCURRENTFREQCNTOVERRIDESEL_MASK 0x00010000L |
44346 | #define RTAVFS_REG187__RESERVED_MASK 0xFFFE0000L |
44347 | //RTAVFS_REG189 |
44348 | #define RTAVFS_REG189__RTAVFSVOLTCODEFROMPI__SHIFT 0x0 |
44349 | #define RTAVFS_REG189__RTAVFSVOLTCODEFROMBINARYSEARCH__SHIFT 0xa |
44350 | #define RTAVFS_REG189__RTAVFSVDDREGON__SHIFT 0x14 |
44351 | #define RTAVFS_REG189__RTAVFSVDDABOVEVDDRET__SHIFT 0x15 |
44352 | #define RTAVFS_REG189__RESERVED__SHIFT 0x16 |
44353 | #define RTAVFS_REG189__RTAVFSVOLTCODEFROMPI_MASK 0x000003FFL |
44354 | #define RTAVFS_REG189__RTAVFSVOLTCODEFROMBINARYSEARCH_MASK 0x000FFC00L |
44355 | #define RTAVFS_REG189__RTAVFSVDDREGON_MASK 0x00100000L |
44356 | #define RTAVFS_REG189__RTAVFSVDDABOVEVDDRET_MASK 0x00200000L |
44357 | #define RTAVFS_REG189__RESERVED_MASK 0xFFC00000L |
44358 | //RTAVFS_REG190 |
44359 | #define RTAVFS_REG190__RTAVFSIGNORERLCREQ__SHIFT 0x0 |
44360 | #define RTAVFS_REG190__RTAVFSRIPPLECOUNTEROUTSEL__SHIFT 0x1 |
44361 | #define RTAVFS_REG190__RTAVFSRUNLOOP__SHIFT 0x6 |
44362 | #define RTAVFS_REG190__RTAVFSSAVECPOWEIGHTS__SHIFT 0x7 |
44363 | #define RTAVFS_REG190__RTAVFSRESTORECPOWEIGHTS__SHIFT 0x8 |
44364 | #define RTAVFS_REG190__RTAVFSRESETRETENTIONREGS__SHIFT 0x9 |
44365 | #define RTAVFS_REG190__RESERVED__SHIFT 0xa |
44366 | #define RTAVFS_REG190__RTAVFSIGNORERLCREQ_MASK 0x00000001L |
44367 | #define RTAVFS_REG190__RTAVFSRIPPLECOUNTEROUTSEL_MASK 0x0000003EL |
44368 | #define RTAVFS_REG190__RTAVFSRUNLOOP_MASK 0x00000040L |
44369 | #define RTAVFS_REG190__RTAVFSSAVECPOWEIGHTS_MASK 0x00000080L |
44370 | #define RTAVFS_REG190__RTAVFSRESTORECPOWEIGHTS_MASK 0x00000100L |
44371 | #define RTAVFS_REG190__RTAVFSRESETRETENTIONREGS_MASK 0x00000200L |
44372 | #define RTAVFS_REG190__RESERVED_MASK 0xFFFFFC00L |
44373 | //RTAVFS_REG191 |
44374 | #define RTAVFS_REG191__RTAVFSSTOPATSTARTUP__SHIFT 0x0 |
44375 | #define RTAVFS_REG191__RTAVFSSTOPATIDLE__SHIFT 0x1 |
44376 | #define RTAVFS_REG191__RTAVFSSTOPATRESETCPORIPPLECOUNTERS__SHIFT 0x2 |
44377 | #define RTAVFS_REG191__RTAVFSSTOPATSTARTCPOS__SHIFT 0x3 |
44378 | #define RTAVFS_REG191__RTAVFSSTOPATSTARTRIPPLECOUNTERS__SHIFT 0x4 |
44379 | #define RTAVFS_REG191__RTAVFSSTOPATRIPPLECOUNTERSDONE__SHIFT 0x5 |
44380 | #define RTAVFS_REG191__RTAVFSSTOPATCPOFINALRESULTREADY__SHIFT 0x6 |
44381 | #define RTAVFS_REG191__RTAVFSSTOPATVOLTCODEREADY__SHIFT 0x7 |
44382 | #define RTAVFS_REG191__RTAVFSSTOPATTARGETVOLATGEREADY__SHIFT 0x8 |
44383 | #define RTAVFS_REG191__RTAVFSSTOPATSTOPCPOS__SHIFT 0x9 |
44384 | #define RTAVFS_REG191__RTAVFSSTOPATWAITFORACK__SHIFT 0xa |
44385 | #define RTAVFS_REG191__RESERVED__SHIFT 0xb |
44386 | #define RTAVFS_REG191__RTAVFSSTOPATSTARTUP_MASK 0x00000001L |
44387 | #define RTAVFS_REG191__RTAVFSSTOPATIDLE_MASK 0x00000002L |
44388 | #define RTAVFS_REG191__RTAVFSSTOPATRESETCPORIPPLECOUNTERS_MASK 0x00000004L |
44389 | #define RTAVFS_REG191__RTAVFSSTOPATSTARTCPOS_MASK 0x00000008L |
44390 | #define RTAVFS_REG191__RTAVFSSTOPATSTARTRIPPLECOUNTERS_MASK 0x00000010L |
44391 | #define RTAVFS_REG191__RTAVFSSTOPATRIPPLECOUNTERSDONE_MASK 0x00000020L |
44392 | #define RTAVFS_REG191__RTAVFSSTOPATCPOFINALRESULTREADY_MASK 0x00000040L |
44393 | #define RTAVFS_REG191__RTAVFSSTOPATVOLTCODEREADY_MASK 0x00000080L |
44394 | #define RTAVFS_REG191__RTAVFSSTOPATTARGETVOLATGEREADY_MASK 0x00000100L |
44395 | #define RTAVFS_REG191__RTAVFSSTOPATSTOPCPOS_MASK 0x00000200L |
44396 | #define RTAVFS_REG191__RTAVFSSTOPATWAITFORACK_MASK 0x00000400L |
44397 | #define RTAVFS_REG191__RESERVED_MASK 0xFFFFF800L |
44398 | //RTAVFS_REG192 |
44399 | #define RTAVFS_REG192__RTAVFSAVFSSCALEDCPOCOUNT__SHIFT 0x0 |
44400 | #define RTAVFS_REG192__RTAVFSAVFSFINALMINCPOCOUNT__SHIFT 0x10 |
44401 | #define RTAVFS_REG192__RTAVFSAVFSSCALEDCPOCOUNT_MASK 0x0000FFFFL |
44402 | #define RTAVFS_REG192__RTAVFSAVFSFINALMINCPOCOUNT_MASK 0xFFFF0000L |
44403 | //RTAVFS_REG193 |
44404 | #define RTAVFS_REG193__RTAVFSFSMSTATE__SHIFT 0x0 |
44405 | #define RTAVFS_REG193__RESERVED__SHIFT 0x10 |
44406 | #define RTAVFS_REG193__RTAVFSFSMSTATE_MASK 0x0000FFFFL |
44407 | #define RTAVFS_REG193__RESERVED_MASK 0xFFFF0000L |
44408 | //RTAVFS_REG194 |
44409 | #define RTAVFS_REG194__RTAVFSRIPPLECNTREAD__SHIFT 0x0 |
44410 | #define RTAVFS_REG194__RTAVFSRIPPLECNTREAD_MASK 0xFFFFFFFFL |
44411 | |
44412 | |
44413 | // addressBlock: sqind |
44414 | //SQ_DEBUG_STS_LOCAL |
44415 | #define SQ_DEBUG_STS_LOCAL__BUSY__SHIFT 0x0 |
44416 | #define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL__SHIFT 0x4 |
44417 | #define SQ_DEBUG_STS_LOCAL__SQ_BUSY__SHIFT 0xc |
44418 | #define SQ_DEBUG_STS_LOCAL__IS_BUSY__SHIFT 0xd |
44419 | #define SQ_DEBUG_STS_LOCAL__IB_BUSY__SHIFT 0xe |
44420 | #define SQ_DEBUG_STS_LOCAL__ARB_BUSY__SHIFT 0xf |
44421 | #define SQ_DEBUG_STS_LOCAL__EXP_BUSY__SHIFT 0x10 |
44422 | #define SQ_DEBUG_STS_LOCAL__BRMSG_BUSY__SHIFT 0x11 |
44423 | #define SQ_DEBUG_STS_LOCAL__VM_BUSY__SHIFT 0x12 |
44424 | #define SQ_DEBUG_STS_LOCAL__BUSY_MASK 0x00000001L |
44425 | #define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL_MASK 0x000003F0L |
44426 | #define SQ_DEBUG_STS_LOCAL__SQ_BUSY_MASK 0x00001000L |
44427 | #define SQ_DEBUG_STS_LOCAL__IS_BUSY_MASK 0x00002000L |
44428 | #define SQ_DEBUG_STS_LOCAL__IB_BUSY_MASK 0x00004000L |
44429 | #define SQ_DEBUG_STS_LOCAL__ARB_BUSY_MASK 0x00008000L |
44430 | #define SQ_DEBUG_STS_LOCAL__EXP_BUSY_MASK 0x00010000L |
44431 | #define SQ_DEBUG_STS_LOCAL__BRMSG_BUSY_MASK 0x00020000L |
44432 | #define SQ_DEBUG_STS_LOCAL__VM_BUSY_MASK 0x00040000L |
44433 | //SQ_DEBUG_CTRL_LOCAL |
44434 | #define SQ_DEBUG_CTRL_LOCAL__UNUSED__SHIFT 0x0 |
44435 | #define SQ_DEBUG_CTRL_LOCAL__UNUSED_MASK 0x000000FFL |
44436 | //SQ_WAVE_ACTIVE |
44437 | #define SQ_WAVE_ACTIVE__WAVE_SLOT__SHIFT 0x0 |
44438 | #define SQ_WAVE_ACTIVE__WAVE_SLOT_MASK 0x000FFFFFL |
44439 | //SQ_WAVE_VALID_AND_IDLE |
44440 | #define SQ_WAVE_VALID_AND_IDLE__WAVE_SLOT__SHIFT 0x0 |
44441 | #define SQ_WAVE_VALID_AND_IDLE__WAVE_SLOT_MASK 0x000FFFFFL |
44442 | //SQ_WAVE_MODE |
44443 | #define SQ_WAVE_MODE__FP_ROUND__SHIFT 0x0 |
44444 | #define SQ_WAVE_MODE__FP_DENORM__SHIFT 0x4 |
44445 | #define SQ_WAVE_MODE__DX10_CLAMP__SHIFT 0x8 |
44446 | #define SQ_WAVE_MODE__IEEE__SHIFT 0x9 |
44447 | #define SQ_WAVE_MODE__LOD_CLAMPED__SHIFT 0xa |
44448 | #define SQ_WAVE_MODE__TRAP_AFTER_INST_EN__SHIFT 0xb |
44449 | #define SQ_WAVE_MODE__EXCP_EN__SHIFT 0xc |
44450 | #define SQ_WAVE_MODE__WAVE_END__SHIFT 0x15 |
44451 | #define SQ_WAVE_MODE__FP16_OVFL__SHIFT 0x17 |
44452 | #define SQ_WAVE_MODE__DISABLE_PERF__SHIFT 0x1b |
44453 | #define SQ_WAVE_MODE__FP_ROUND_MASK 0x0000000FL |
44454 | #define SQ_WAVE_MODE__FP_DENORM_MASK 0x000000F0L |
44455 | #define SQ_WAVE_MODE__DX10_CLAMP_MASK 0x00000100L |
44456 | #define SQ_WAVE_MODE__IEEE_MASK 0x00000200L |
44457 | #define SQ_WAVE_MODE__LOD_CLAMPED_MASK 0x00000400L |
44458 | #define SQ_WAVE_MODE__TRAP_AFTER_INST_EN_MASK 0x00000800L |
44459 | #define SQ_WAVE_MODE__EXCP_EN_MASK 0x001FF000L |
44460 | #define SQ_WAVE_MODE__WAVE_END_MASK 0x00200000L |
44461 | #define SQ_WAVE_MODE__FP16_OVFL_MASK 0x00800000L |
44462 | #define SQ_WAVE_MODE__DISABLE_PERF_MASK 0x08000000L |
44463 | //SQ_WAVE_STATUS |
44464 | #define SQ_WAVE_STATUS__SCC__SHIFT 0x0 |
44465 | #define SQ_WAVE_STATUS__SPI_PRIO__SHIFT 0x1 |
44466 | #define SQ_WAVE_STATUS__USER_PRIO__SHIFT 0x3 |
44467 | #define SQ_WAVE_STATUS__PRIV__SHIFT 0x5 |
44468 | #define SQ_WAVE_STATUS__TRAP_EN__SHIFT 0x6 |
44469 | #define SQ_WAVE_STATUS__TTRACE_EN__SHIFT 0x7 |
44470 | #define SQ_WAVE_STATUS__EXPORT_RDY__SHIFT 0x8 |
44471 | #define SQ_WAVE_STATUS__EXECZ__SHIFT 0x9 |
44472 | #define SQ_WAVE_STATUS__VCCZ__SHIFT 0xa |
44473 | #define SQ_WAVE_STATUS__IN_TG__SHIFT 0xb |
44474 | #define SQ_WAVE_STATUS__IN_BARRIER__SHIFT 0xc |
44475 | #define SQ_WAVE_STATUS__HALT__SHIFT 0xd |
44476 | #define SQ_WAVE_STATUS__TRAP__SHIFT 0xe |
44477 | #define SQ_WAVE_STATUS__TTRACE_SIMD_EN__SHIFT 0xf |
44478 | #define SQ_WAVE_STATUS__VALID__SHIFT 0x10 |
44479 | #define SQ_WAVE_STATUS__ECC_ERR__SHIFT 0x11 |
44480 | #define SQ_WAVE_STATUS__SKIP_EXPORT__SHIFT 0x12 |
44481 | #define SQ_WAVE_STATUS__PERF_EN__SHIFT 0x13 |
44482 | #define SQ_WAVE_STATUS__COND_DBG_USER__SHIFT 0x14 |
44483 | #define SQ_WAVE_STATUS__COND_DBG_SYS__SHIFT 0x15 |
44484 | #define SQ_WAVE_STATUS__OREO_CONFLICT__SHIFT 0x16 |
44485 | #define SQ_WAVE_STATUS__FATAL_HALT__SHIFT 0x17 |
44486 | #define SQ_WAVE_STATUS__NO_VGPRS__SHIFT 0x18 |
44487 | #define SQ_WAVE_STATUS__LDS_PARAM_READY__SHIFT 0x19 |
44488 | #define SQ_WAVE_STATUS__MUST_GS_ALLOC__SHIFT 0x1a |
44489 | #define SQ_WAVE_STATUS__MUST_EXPORT__SHIFT 0x1b |
44490 | #define SQ_WAVE_STATUS__IDLE__SHIFT 0x1c |
44491 | #define SQ_WAVE_STATUS__SCRATCH_EN__SHIFT 0x1d |
44492 | #define SQ_WAVE_STATUS__SCC_MASK 0x00000001L |
44493 | #define SQ_WAVE_STATUS__SPI_PRIO_MASK 0x00000006L |
44494 | #define SQ_WAVE_STATUS__USER_PRIO_MASK 0x00000018L |
44495 | #define SQ_WAVE_STATUS__PRIV_MASK 0x00000020L |
44496 | #define SQ_WAVE_STATUS__TRAP_EN_MASK 0x00000040L |
44497 | #define SQ_WAVE_STATUS__TTRACE_EN_MASK 0x00000080L |
44498 | #define SQ_WAVE_STATUS__EXPORT_RDY_MASK 0x00000100L |
44499 | #define SQ_WAVE_STATUS__EXECZ_MASK 0x00000200L |
44500 | #define SQ_WAVE_STATUS__VCCZ_MASK 0x00000400L |
44501 | #define SQ_WAVE_STATUS__IN_TG_MASK 0x00000800L |
44502 | #define SQ_WAVE_STATUS__IN_BARRIER_MASK 0x00001000L |
44503 | #define SQ_WAVE_STATUS__HALT_MASK 0x00002000L |
44504 | #define SQ_WAVE_STATUS__TRAP_MASK 0x00004000L |
44505 | #define SQ_WAVE_STATUS__TTRACE_SIMD_EN_MASK 0x00008000L |
44506 | #define SQ_WAVE_STATUS__VALID_MASK 0x00010000L |
44507 | #define SQ_WAVE_STATUS__ECC_ERR_MASK 0x00020000L |
44508 | #define SQ_WAVE_STATUS__SKIP_EXPORT_MASK 0x00040000L |
44509 | #define SQ_WAVE_STATUS__PERF_EN_MASK 0x00080000L |
44510 | #define SQ_WAVE_STATUS__COND_DBG_USER_MASK 0x00100000L |
44511 | #define SQ_WAVE_STATUS__COND_DBG_SYS_MASK 0x00200000L |
44512 | #define SQ_WAVE_STATUS__OREO_CONFLICT_MASK 0x00400000L |
44513 | #define SQ_WAVE_STATUS__FATAL_HALT_MASK 0x00800000L |
44514 | #define SQ_WAVE_STATUS__NO_VGPRS_MASK 0x01000000L |
44515 | #define SQ_WAVE_STATUS__LDS_PARAM_READY_MASK 0x02000000L |
44516 | #define SQ_WAVE_STATUS__MUST_GS_ALLOC_MASK 0x04000000L |
44517 | #define SQ_WAVE_STATUS__MUST_EXPORT_MASK 0x08000000L |
44518 | #define SQ_WAVE_STATUS__IDLE_MASK 0x10000000L |
44519 | #define SQ_WAVE_STATUS__SCRATCH_EN_MASK 0x20000000L |
44520 | //SQ_WAVE_TRAPSTS |
44521 | #define SQ_WAVE_TRAPSTS__EXCP__SHIFT 0x0 |
44522 | #define SQ_WAVE_TRAPSTS__SAVECTX__SHIFT 0xa |
44523 | #define SQ_WAVE_TRAPSTS__ILLEGAL_INST__SHIFT 0xb |
44524 | #define SQ_WAVE_TRAPSTS__EXCP_HI__SHIFT 0xc |
44525 | #define SQ_WAVE_TRAPSTS__BUFFER_OOB__SHIFT 0xf |
44526 | #define SQ_WAVE_TRAPSTS__HOST_TRAP__SHIFT 0x10 |
44527 | #define SQ_WAVE_TRAPSTS__WAVESTART__SHIFT 0x11 |
44528 | #define SQ_WAVE_TRAPSTS__WAVE_END__SHIFT 0x12 |
44529 | #define SQ_WAVE_TRAPSTS__PERF_SNAPSHOT__SHIFT 0x13 |
44530 | #define SQ_WAVE_TRAPSTS__TRAP_AFTER_INST__SHIFT 0x14 |
44531 | #define SQ_WAVE_TRAPSTS__UTC_ERROR__SHIFT 0x1c |
44532 | #define SQ_WAVE_TRAPSTS__EXCP_MASK 0x000001FFL |
44533 | #define SQ_WAVE_TRAPSTS__SAVECTX_MASK 0x00000400L |
44534 | #define SQ_WAVE_TRAPSTS__ILLEGAL_INST_MASK 0x00000800L |
44535 | #define SQ_WAVE_TRAPSTS__EXCP_HI_MASK 0x00007000L |
44536 | #define SQ_WAVE_TRAPSTS__BUFFER_OOB_MASK 0x00008000L |
44537 | #define SQ_WAVE_TRAPSTS__HOST_TRAP_MASK 0x00010000L |
44538 | #define SQ_WAVE_TRAPSTS__WAVESTART_MASK 0x00020000L |
44539 | #define SQ_WAVE_TRAPSTS__WAVE_END_MASK 0x00040000L |
44540 | #define SQ_WAVE_TRAPSTS__PERF_SNAPSHOT_MASK 0x00080000L |
44541 | #define SQ_WAVE_TRAPSTS__TRAP_AFTER_INST_MASK 0x00100000L |
44542 | #define SQ_WAVE_TRAPSTS__UTC_ERROR_MASK 0x10000000L |
44543 | //SQ_WAVE_GPR_ALLOC |
44544 | #define SQ_WAVE_GPR_ALLOC__VGPR_BASE__SHIFT 0x0 |
44545 | #define SQ_WAVE_GPR_ALLOC__VGPR_SIZE__SHIFT 0xc |
44546 | #define SQ_WAVE_GPR_ALLOC__VGPR_BASE_MASK 0x000001FFL |
44547 | #define SQ_WAVE_GPR_ALLOC__VGPR_SIZE_MASK 0x000FF000L |
44548 | //SQ_WAVE_LDS_ALLOC |
44549 | #define SQ_WAVE_LDS_ALLOC__LDS_BASE__SHIFT 0x0 |
44550 | #define SQ_WAVE_LDS_ALLOC__LDS_SIZE__SHIFT 0xc |
44551 | #define SQ_WAVE_LDS_ALLOC__VGPR_SHARED_SIZE__SHIFT 0x18 |
44552 | #define SQ_WAVE_LDS_ALLOC__LDS_BASE_MASK 0x000001FFL |
44553 | #define SQ_WAVE_LDS_ALLOC__LDS_SIZE_MASK 0x001FF000L |
44554 | #define SQ_WAVE_LDS_ALLOC__VGPR_SHARED_SIZE_MASK 0x0F000000L |
44555 | //SQ_WAVE_IB_STS |
44556 | #define SQ_WAVE_IB_STS__EXP_CNT__SHIFT 0x0 |
44557 | #define SQ_WAVE_IB_STS__LGKM_CNT__SHIFT 0x4 |
44558 | #define SQ_WAVE_IB_STS__VM_CNT__SHIFT 0xa |
44559 | #define SQ_WAVE_IB_STS__VS_CNT__SHIFT 0x1a |
44560 | #define SQ_WAVE_IB_STS__EXP_CNT_MASK 0x00000007L |
44561 | #define SQ_WAVE_IB_STS__LGKM_CNT_MASK 0x000003F0L |
44562 | #define SQ_WAVE_IB_STS__VM_CNT_MASK 0x0000FC00L |
44563 | #define SQ_WAVE_IB_STS__VS_CNT_MASK 0xFC000000L |
44564 | //SQ_WAVE_PC_LO |
44565 | #define SQ_WAVE_PC_LO__PC_LO__SHIFT 0x0 |
44566 | #define SQ_WAVE_PC_LO__PC_LO_MASK 0xFFFFFFFFL |
44567 | //SQ_WAVE_PC_HI |
44568 | #define SQ_WAVE_PC_HI__PC_HI__SHIFT 0x0 |
44569 | #define SQ_WAVE_PC_HI__PC_HI_MASK 0x0000FFFFL |
44570 | //SQ_WAVE_IB_DBG1 |
44571 | #define SQ_WAVE_IB_DBG1__WAVE_IDLE__SHIFT 0x18 |
44572 | #define SQ_WAVE_IB_DBG1__MISC_CNT__SHIFT 0x19 |
44573 | #define SQ_WAVE_IB_DBG1__WAVE_IDLE_MASK 0x01000000L |
44574 | #define SQ_WAVE_IB_DBG1__MISC_CNT_MASK 0xFE000000L |
44575 | //SQ_WAVE_FLUSH_IB |
44576 | #define SQ_WAVE_FLUSH_IB__UNUSED__SHIFT 0x0 |
44577 | #define SQ_WAVE_FLUSH_IB__UNUSED_MASK 0xFFFFFFFFL |
44578 | //SQ_WAVE_FLAT_SCRATCH_LO |
44579 | #define SQ_WAVE_FLAT_SCRATCH_LO__DATA__SHIFT 0x0 |
44580 | #define SQ_WAVE_FLAT_SCRATCH_LO__DATA_MASK 0xFFFFFFFFL |
44581 | //SQ_WAVE_FLAT_SCRATCH_HI |
44582 | #define SQ_WAVE_FLAT_SCRATCH_HI__DATA__SHIFT 0x0 |
44583 | #define SQ_WAVE_FLAT_SCRATCH_HI__DATA_MASK 0xFFFFFFFFL |
44584 | //SQ_WAVE_HW_ID1 |
44585 | #define SQ_WAVE_HW_ID1__WAVE_ID__SHIFT 0x0 |
44586 | #define SQ_WAVE_HW_ID1__SIMD_ID__SHIFT 0x8 |
44587 | #define SQ_WAVE_HW_ID1__WGP_ID__SHIFT 0xa |
44588 | #define SQ_WAVE_HW_ID1__SA_ID__SHIFT 0x10 |
44589 | #define SQ_WAVE_HW_ID1__SE_ID__SHIFT 0x12 |
44590 | #define SQ_WAVE_HW_ID1__DP_RATE__SHIFT 0x1d |
44591 | #define SQ_WAVE_HW_ID1__WAVE_ID_MASK 0x0000001FL |
44592 | #define SQ_WAVE_HW_ID1__SIMD_ID_MASK 0x00000300L |
44593 | #define SQ_WAVE_HW_ID1__WGP_ID_MASK 0x00003C00L |
44594 | #define SQ_WAVE_HW_ID1__SA_ID_MASK 0x00010000L |
44595 | #define SQ_WAVE_HW_ID1__SE_ID_MASK 0x001C0000L |
44596 | #define SQ_WAVE_HW_ID1__DP_RATE_MASK 0xE0000000L |
44597 | //SQ_WAVE_HW_ID2 |
44598 | #define SQ_WAVE_HW_ID2__QUEUE_ID__SHIFT 0x0 |
44599 | #define SQ_WAVE_HW_ID2__PIPE_ID__SHIFT 0x4 |
44600 | #define SQ_WAVE_HW_ID2__ME_ID__SHIFT 0x8 |
44601 | #define SQ_WAVE_HW_ID2__STATE_ID__SHIFT 0xc |
44602 | #define SQ_WAVE_HW_ID2__WG_ID__SHIFT 0x10 |
44603 | #define SQ_WAVE_HW_ID2__VM_ID__SHIFT 0x18 |
44604 | #define SQ_WAVE_HW_ID2__QUEUE_ID_MASK 0x0000000FL |
44605 | #define SQ_WAVE_HW_ID2__PIPE_ID_MASK 0x00000030L |
44606 | #define SQ_WAVE_HW_ID2__ME_ID_MASK 0x00000300L |
44607 | #define SQ_WAVE_HW_ID2__STATE_ID_MASK 0x00007000L |
44608 | #define SQ_WAVE_HW_ID2__WG_ID_MASK 0x001F0000L |
44609 | #define SQ_WAVE_HW_ID2__VM_ID_MASK 0x0F000000L |
44610 | //SQ_WAVE_POPS_PACKER |
44611 | #define SQ_WAVE_POPS_PACKER__POPS_EN__SHIFT 0x0 |
44612 | #define SQ_WAVE_POPS_PACKER__POPS_PACKER_ID__SHIFT 0x1 |
44613 | #define SQ_WAVE_POPS_PACKER__POPS_EN_MASK 0x00000001L |
44614 | #define SQ_WAVE_POPS_PACKER__POPS_PACKER_ID_MASK 0x00000006L |
44615 | //SQ_WAVE_SCHED_MODE |
44616 | #define SQ_WAVE_SCHED_MODE__DEP_MODE__SHIFT 0x0 |
44617 | #define SQ_WAVE_SCHED_MODE__DEP_MODE_MASK 0x00000003L |
44618 | //SQ_WAVE_IB_STS2 |
44619 | #define SQ_WAVE_IB_STS2__INST_PREFETCH__SHIFT 0x0 |
44620 | #define SQ_WAVE_IB_STS2__MEM_ORDER__SHIFT 0x8 |
44621 | #define SQ_WAVE_IB_STS2__FWD_PROGRESS__SHIFT 0xa |
44622 | #define SQ_WAVE_IB_STS2__WAVE64__SHIFT 0xb |
44623 | #define SQ_WAVE_IB_STS2__INST_PREFETCH_MASK 0x00000003L |
44624 | #define SQ_WAVE_IB_STS2__MEM_ORDER_MASK 0x00000300L |
44625 | #define SQ_WAVE_IB_STS2__FWD_PROGRESS_MASK 0x00000400L |
44626 | #define SQ_WAVE_IB_STS2__WAVE64_MASK 0x00000800L |
44627 | //SQ_WAVE_SHADER_CYCLES |
44628 | #define SQ_WAVE_SHADER_CYCLES__CYCLES__SHIFT 0x0 |
44629 | #define SQ_WAVE_SHADER_CYCLES__CYCLES_MASK 0x000FFFFFL |
44630 | //SQ_WAVE_TTMP0 |
44631 | #define SQ_WAVE_TTMP0__DATA__SHIFT 0x0 |
44632 | #define SQ_WAVE_TTMP0__DATA_MASK 0xFFFFFFFFL |
44633 | //SQ_WAVE_TTMP1 |
44634 | #define SQ_WAVE_TTMP1__DATA__SHIFT 0x0 |
44635 | #define SQ_WAVE_TTMP1__DATA_MASK 0xFFFFFFFFL |
44636 | //SQ_WAVE_TTMP2 |
44637 | #define SQ_WAVE_TTMP2__DATA__SHIFT 0x0 |
44638 | #define SQ_WAVE_TTMP2__DATA_MASK 0xFFFFFFFFL |
44639 | //SQ_WAVE_TTMP3 |
44640 | #define SQ_WAVE_TTMP3__DATA__SHIFT 0x0 |
44641 | #define SQ_WAVE_TTMP3__DATA_MASK 0xFFFFFFFFL |
44642 | //SQ_WAVE_TTMP4 |
44643 | #define SQ_WAVE_TTMP4__DATA__SHIFT 0x0 |
44644 | #define SQ_WAVE_TTMP4__DATA_MASK 0xFFFFFFFFL |
44645 | //SQ_WAVE_TTMP5 |
44646 | #define SQ_WAVE_TTMP5__DATA__SHIFT 0x0 |
44647 | #define SQ_WAVE_TTMP5__DATA_MASK 0xFFFFFFFFL |
44648 | //SQ_WAVE_TTMP6 |
44649 | #define SQ_WAVE_TTMP6__DATA__SHIFT 0x0 |
44650 | #define SQ_WAVE_TTMP6__DATA_MASK 0xFFFFFFFFL |
44651 | //SQ_WAVE_TTMP7 |
44652 | #define SQ_WAVE_TTMP7__DATA__SHIFT 0x0 |
44653 | #define SQ_WAVE_TTMP7__DATA_MASK 0xFFFFFFFFL |
44654 | //SQ_WAVE_TTMP8 |
44655 | #define SQ_WAVE_TTMP8__DATA__SHIFT 0x0 |
44656 | #define SQ_WAVE_TTMP8__DATA_MASK 0xFFFFFFFFL |
44657 | //SQ_WAVE_TTMP9 |
44658 | #define SQ_WAVE_TTMP9__DATA__SHIFT 0x0 |
44659 | #define SQ_WAVE_TTMP9__DATA_MASK 0xFFFFFFFFL |
44660 | //SQ_WAVE_TTMP10 |
44661 | #define SQ_WAVE_TTMP10__DATA__SHIFT 0x0 |
44662 | #define SQ_WAVE_TTMP10__DATA_MASK 0xFFFFFFFFL |
44663 | //SQ_WAVE_TTMP11 |
44664 | #define SQ_WAVE_TTMP11__DATA__SHIFT 0x0 |
44665 | #define SQ_WAVE_TTMP11__DATA_MASK 0xFFFFFFFFL |
44666 | //SQ_WAVE_TTMP12 |
44667 | #define SQ_WAVE_TTMP12__DATA__SHIFT 0x0 |
44668 | #define SQ_WAVE_TTMP12__DATA_MASK 0xFFFFFFFFL |
44669 | //SQ_WAVE_TTMP13 |
44670 | #define SQ_WAVE_TTMP13__DATA__SHIFT 0x0 |
44671 | #define SQ_WAVE_TTMP13__DATA_MASK 0xFFFFFFFFL |
44672 | //SQ_WAVE_TTMP14 |
44673 | #define SQ_WAVE_TTMP14__DATA__SHIFT 0x0 |
44674 | #define SQ_WAVE_TTMP14__DATA_MASK 0xFFFFFFFFL |
44675 | //SQ_WAVE_TTMP15 |
44676 | #define SQ_WAVE_TTMP15__DATA__SHIFT 0x0 |
44677 | #define SQ_WAVE_TTMP15__DATA_MASK 0xFFFFFFFFL |
44678 | //SQ_WAVE_M0 |
44679 | #define SQ_WAVE_M0__M0__SHIFT 0x0 |
44680 | #define SQ_WAVE_M0__M0_MASK 0xFFFFFFFFL |
44681 | //SQ_WAVE_EXEC_LO |
44682 | #define SQ_WAVE_EXEC_LO__EXEC_LO__SHIFT 0x0 |
44683 | #define SQ_WAVE_EXEC_LO__EXEC_LO_MASK 0xFFFFFFFFL |
44684 | //SQ_WAVE_EXEC_HI |
44685 | #define SQ_WAVE_EXEC_HI__EXEC_HI__SHIFT 0x0 |
44686 | #define SQ_WAVE_EXEC_HI__EXEC_HI_MASK 0xFFFFFFFFL |
44687 | |
44688 | |
44689 | |
44690 | #endif |
44691 | |