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1/*
2 * Copyright (C) 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20 */
21#ifndef _gc_9_0_SH_MASK_HEADER
22#define _gc_9_0_SH_MASK_HEADER
23
24//GCEA_EDC_CNT
25#define GCEA_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0
26#define GCEA_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2
27#define GCEA_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4
28#define GCEA_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6
29#define GCEA_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8
30#define GCEA_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa
31#define GCEA_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc
32#define GCEA_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0xe
33#define GCEA_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10
34#define GCEA_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x12
35#define GCEA_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x14
36#define GCEA_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x16
37#define GCEA_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT 0x18
38#define GCEA_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1a
39#define GCEA_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT 0x1c
40#define GCEA_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L
41#define GCEA_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL
42#define GCEA_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L
43#define GCEA_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L
44#define GCEA_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L
45#define GCEA_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L
46#define GCEA_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L
47#define GCEA_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L
48#define GCEA_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L
49#define GCEA_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L
50#define GCEA_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x00300000L
51#define GCEA_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x00C00000L
52#define GCEA_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK 0x03000000L
53#define GCEA_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK 0x0C000000L
54#define GCEA_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK 0x30000000L
55
56#define GCEA_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0
57#define GCEA_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2
58#define GCEA_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4
59#define GCEA_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6
60#define GCEA_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8
61#define GCEA_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa
62#define GCEA_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc
63#define GCEA_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe
64#define GCEA_EDC_CNT2__MAM_D0MEM_SED_COUNT__SHIFT 0x10
65#define GCEA_EDC_CNT2__MAM_D1MEM_SED_COUNT__SHIFT 0x12
66#define GCEA_EDC_CNT2__MAM_D2MEM_SED_COUNT__SHIFT 0x14
67#define GCEA_EDC_CNT2__MAM_D3MEM_SED_COUNT__SHIFT 0x16
68#define GCEA_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L
69#define GCEA_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL
70#define GCEA_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L
71#define GCEA_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L
72#define GCEA_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L
73#define GCEA_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L
74#define GCEA_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L
75#define GCEA_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L
76#define GCEA_EDC_CNT2__MAM_D0MEM_SED_COUNT_MASK 0x00030000L
77#define GCEA_EDC_CNT2__MAM_D1MEM_SED_COUNT_MASK 0x000C0000L
78#define GCEA_EDC_CNT2__MAM_D2MEM_SED_COUNT_MASK 0x00300000L
79#define GCEA_EDC_CNT2__MAM_D3MEM_SED_COUNT_MASK 0x00C00000L
80
81// addressBlock: gc_cppdec2
82//CPF_EDC_TAG_CNT
83#define CPF_EDC_TAG_CNT__DED_COUNT__SHIFT 0x0
84#define CPF_EDC_TAG_CNT__SEC_COUNT__SHIFT 0x2
85#define CPF_EDC_TAG_CNT__DED_COUNT_MASK 0x00000003L
86#define CPF_EDC_TAG_CNT__SEC_COUNT_MASK 0x0000000CL
87//CPF_EDC_ROQ_CNT
88#define CPF_EDC_ROQ_CNT__COUNT_ME1__SHIFT 0x0
89#define CPF_EDC_ROQ_CNT__COUNT_ME2__SHIFT 0x2
90#define CPF_EDC_ROQ_CNT__COUNT_ME1_MASK 0x00000003L
91#define CPF_EDC_ROQ_CNT__COUNT_ME2_MASK 0x0000000CL
92//CPG_EDC_TAG_CNT
93#define CPG_EDC_TAG_CNT__DED_COUNT__SHIFT 0x0
94#define CPG_EDC_TAG_CNT__SEC_COUNT__SHIFT 0x2
95#define CPG_EDC_TAG_CNT__DED_COUNT_MASK 0x00000003L
96#define CPG_EDC_TAG_CNT__SEC_COUNT_MASK 0x0000000CL
97//CPG_EDC_DMA_CNT
98#define CPG_EDC_DMA_CNT__ROQ_COUNT__SHIFT 0x0
99#define CPG_EDC_DMA_CNT__TAG_DED_COUNT__SHIFT 0x2
100#define CPG_EDC_DMA_CNT__TAG_SEC_COUNT__SHIFT 0x4
101#define CPG_EDC_DMA_CNT__ROQ_COUNT_MASK 0x00000003L
102#define CPG_EDC_DMA_CNT__TAG_DED_COUNT_MASK 0x0000000CL
103#define CPG_EDC_DMA_CNT__TAG_SEC_COUNT_MASK 0x00000030L
104//CPC_EDC_SCRATCH_CNT
105#define CPC_EDC_SCRATCH_CNT__DED_COUNT__SHIFT 0x0
106#define CPC_EDC_SCRATCH_CNT__SEC_COUNT__SHIFT 0x2
107#define CPC_EDC_SCRATCH_CNT__DED_COUNT_MASK 0x00000003L
108#define CPC_EDC_SCRATCH_CNT__SEC_COUNT_MASK 0x0000000CL
109//CPC_EDC_UCODE_CNT
110#define CPC_EDC_UCODE_CNT__DED_COUNT__SHIFT 0x0
111#define CPC_EDC_UCODE_CNT__SEC_COUNT__SHIFT 0x2
112#define CPC_EDC_UCODE_CNT__DED_COUNT_MASK 0x00000003L
113#define CPC_EDC_UCODE_CNT__SEC_COUNT_MASK 0x0000000CL
114//DC_EDC_STATE_CNT
115#define DC_EDC_STATE_CNT__COUNT_ME1__SHIFT 0x0
116#define DC_EDC_STATE_CNT__COUNT_ME1_MASK 0x00000003L
117//DC_EDC_CSINVOC_CNT
118#define DC_EDC_CSINVOC_CNT__COUNT_ME1__SHIFT 0x0
119#define DC_EDC_CSINVOC_CNT__COUNT_ME1_MASK 0x00000003L
120//DC_EDC_RESTORE_CNT
121#define DC_EDC_RESTORE_CNT__COUNT_ME1__SHIFT 0x0
122#define DC_EDC_RESTORE_CNT__COUNT_ME1_MASK 0x00000003L
123
124// addressBlock: gc_grbmdec
125//GRBM_CNTL
126#define GRBM_CNTL__READ_TIMEOUT__SHIFT 0x0
127#define GRBM_CNTL__REPORT_LAST_RDERR__SHIFT 0x1f
128#define GRBM_CNTL__READ_TIMEOUT_MASK 0x000000FFL
129#define GRBM_CNTL__REPORT_LAST_RDERR_MASK 0x80000000L
130//GRBM_SKEW_CNTL
131#define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD__SHIFT 0x0
132#define GRBM_SKEW_CNTL__SKEW_COUNT__SHIFT 0x6
133#define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD_MASK 0x0000003FL
134#define GRBM_SKEW_CNTL__SKEW_COUNT_MASK 0x00000FC0L
135//GRBM_STATUS2
136#define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL__SHIFT 0x0
137#define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING__SHIFT 0x4
138#define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING__SHIFT 0x5
139#define GRBM_STATUS2__ME1PIPE0_RQ_PENDING__SHIFT 0x6
140#define GRBM_STATUS2__ME1PIPE1_RQ_PENDING__SHIFT 0x7
141#define GRBM_STATUS2__ME1PIPE2_RQ_PENDING__SHIFT 0x8
142#define GRBM_STATUS2__ME1PIPE3_RQ_PENDING__SHIFT 0x9
143#define GRBM_STATUS2__ME2PIPE0_RQ_PENDING__SHIFT 0xa
144#define GRBM_STATUS2__ME2PIPE1_RQ_PENDING__SHIFT 0xb
145#define GRBM_STATUS2__ME2PIPE2_RQ_PENDING__SHIFT 0xc
146#define GRBM_STATUS2__ME2PIPE3_RQ_PENDING__SHIFT 0xd
147#define GRBM_STATUS2__RLC_RQ_PENDING__SHIFT 0xe
148#define GRBM_STATUS2__UTCL2_BUSY__SHIFT 0xf
149#define GRBM_STATUS2__EA_BUSY__SHIFT 0x10
150#define GRBM_STATUS2__RMI_BUSY__SHIFT 0x11
151#define GRBM_STATUS2__UTCL2_RQ_PENDING__SHIFT 0x12
152#define GRBM_STATUS2__CPF_RQ_PENDING__SHIFT 0x13
153#define GRBM_STATUS2__EA_LINK_BUSY__SHIFT 0x14
154#define GRBM_STATUS2__RLC_BUSY__SHIFT 0x18
155#define GRBM_STATUS2__TC_BUSY__SHIFT 0x19
156#define GRBM_STATUS2__TCC_CC_RESIDENT__SHIFT 0x1a
157#define GRBM_STATUS2__CPF_BUSY__SHIFT 0x1c
158#define GRBM_STATUS2__CPC_BUSY__SHIFT 0x1d
159#define GRBM_STATUS2__CPG_BUSY__SHIFT 0x1e
160#define GRBM_STATUS2__CPAXI_BUSY__SHIFT 0x1f
161#define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL_MASK 0x0000000FL
162#define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING_MASK 0x00000010L
163#define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING_MASK 0x00000020L
164#define GRBM_STATUS2__ME1PIPE0_RQ_PENDING_MASK 0x00000040L
165#define GRBM_STATUS2__ME1PIPE1_RQ_PENDING_MASK 0x00000080L
166#define GRBM_STATUS2__ME1PIPE2_RQ_PENDING_MASK 0x00000100L
167#define GRBM_STATUS2__ME1PIPE3_RQ_PENDING_MASK 0x00000200L
168#define GRBM_STATUS2__ME2PIPE0_RQ_PENDING_MASK 0x00000400L
169#define GRBM_STATUS2__ME2PIPE1_RQ_PENDING_MASK 0x00000800L
170#define GRBM_STATUS2__ME2PIPE2_RQ_PENDING_MASK 0x00001000L
171#define GRBM_STATUS2__ME2PIPE3_RQ_PENDING_MASK 0x00002000L
172#define GRBM_STATUS2__RLC_RQ_PENDING_MASK 0x00004000L
173#define GRBM_STATUS2__UTCL2_BUSY_MASK 0x00008000L
174#define GRBM_STATUS2__EA_BUSY_MASK 0x00010000L
175#define GRBM_STATUS2__RMI_BUSY_MASK 0x00020000L
176#define GRBM_STATUS2__UTCL2_RQ_PENDING_MASK 0x00040000L
177#define GRBM_STATUS2__CPF_RQ_PENDING_MASK 0x00080000L
178#define GRBM_STATUS2__EA_LINK_BUSY_MASK 0x00100000L
179#define GRBM_STATUS2__RLC_BUSY_MASK 0x01000000L
180#define GRBM_STATUS2__TC_BUSY_MASK 0x02000000L
181#define GRBM_STATUS2__TCC_CC_RESIDENT_MASK 0x04000000L
182#define GRBM_STATUS2__CPF_BUSY_MASK 0x10000000L
183#define GRBM_STATUS2__CPC_BUSY_MASK 0x20000000L
184#define GRBM_STATUS2__CPG_BUSY_MASK 0x40000000L
185#define GRBM_STATUS2__CPAXI_BUSY_MASK 0x80000000L
186//GRBM_PWR_CNTL
187#define GRBM_PWR_CNTL__ALL_REQ_TYPE__SHIFT 0x0
188#define GRBM_PWR_CNTL__GFX_REQ_TYPE__SHIFT 0x2
189#define GRBM_PWR_CNTL__ALL_RSP_TYPE__SHIFT 0x4
190#define GRBM_PWR_CNTL__GFX_RSP_TYPE__SHIFT 0x6
191#define GRBM_PWR_CNTL__GFX_REQ_EN__SHIFT 0xe
192#define GRBM_PWR_CNTL__ALL_REQ_EN__SHIFT 0xf
193#define GRBM_PWR_CNTL__ALL_REQ_TYPE_MASK 0x00000003L
194#define GRBM_PWR_CNTL__GFX_REQ_TYPE_MASK 0x0000000CL
195#define GRBM_PWR_CNTL__ALL_RSP_TYPE_MASK 0x00000030L
196#define GRBM_PWR_CNTL__GFX_RSP_TYPE_MASK 0x000000C0L
197#define GRBM_PWR_CNTL__GFX_REQ_EN_MASK 0x00004000L
198#define GRBM_PWR_CNTL__ALL_REQ_EN_MASK 0x00008000L
199//GRBM_STATUS
200#define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL__SHIFT 0x0
201#define GRBM_STATUS__RSMU_RQ_PENDING__SHIFT 0x5
202#define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING__SHIFT 0x7
203#define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING__SHIFT 0x8
204#define GRBM_STATUS__GDS_DMA_RQ_PENDING__SHIFT 0x9
205#define GRBM_STATUS__DB_CLEAN__SHIFT 0xc
206#define GRBM_STATUS__CB_CLEAN__SHIFT 0xd
207#define GRBM_STATUS__TA_BUSY__SHIFT 0xe
208#define GRBM_STATUS__GDS_BUSY__SHIFT 0xf
209#define GRBM_STATUS__WD_BUSY_NO_DMA__SHIFT 0x10
210#define GRBM_STATUS__VGT_BUSY__SHIFT 0x11
211#define GRBM_STATUS__IA_BUSY_NO_DMA__SHIFT 0x12
212#define GRBM_STATUS__IA_BUSY__SHIFT 0x13
213#define GRBM_STATUS__SX_BUSY__SHIFT 0x14
214#define GRBM_STATUS__WD_BUSY__SHIFT 0x15
215#define GRBM_STATUS__SPI_BUSY__SHIFT 0x16
216#define GRBM_STATUS__BCI_BUSY__SHIFT 0x17
217#define GRBM_STATUS__SC_BUSY__SHIFT 0x18
218#define GRBM_STATUS__PA_BUSY__SHIFT 0x19
219#define GRBM_STATUS__DB_BUSY__SHIFT 0x1a
220#define GRBM_STATUS__CP_COHERENCY_BUSY__SHIFT 0x1c
221#define GRBM_STATUS__CP_BUSY__SHIFT 0x1d
222#define GRBM_STATUS__CB_BUSY__SHIFT 0x1e
223#define GRBM_STATUS__GUI_ACTIVE__SHIFT 0x1f
224#define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL_MASK 0x0000000FL
225#define GRBM_STATUS__RSMU_RQ_PENDING_MASK 0x00000020L
226#define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING_MASK 0x00000080L
227#define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING_MASK 0x00000100L
228#define GRBM_STATUS__GDS_DMA_RQ_PENDING_MASK 0x00000200L
229#define GRBM_STATUS__DB_CLEAN_MASK 0x00001000L
230#define GRBM_STATUS__CB_CLEAN_MASK 0x00002000L
231#define GRBM_STATUS__TA_BUSY_MASK 0x00004000L
232#define GRBM_STATUS__GDS_BUSY_MASK 0x00008000L
233#define GRBM_STATUS__WD_BUSY_NO_DMA_MASK 0x00010000L
234#define GRBM_STATUS__VGT_BUSY_MASK 0x00020000L
235#define GRBM_STATUS__IA_BUSY_NO_DMA_MASK 0x00040000L
236#define GRBM_STATUS__IA_BUSY_MASK 0x00080000L
237#define GRBM_STATUS__SX_BUSY_MASK 0x00100000L
238#define GRBM_STATUS__WD_BUSY_MASK 0x00200000L
239#define GRBM_STATUS__SPI_BUSY_MASK 0x00400000L
240#define GRBM_STATUS__BCI_BUSY_MASK 0x00800000L
241#define GRBM_STATUS__SC_BUSY_MASK 0x01000000L
242#define GRBM_STATUS__PA_BUSY_MASK 0x02000000L
243#define GRBM_STATUS__DB_BUSY_MASK 0x04000000L
244#define GRBM_STATUS__CP_COHERENCY_BUSY_MASK 0x10000000L
245#define GRBM_STATUS__CP_BUSY_MASK 0x20000000L
246#define GRBM_STATUS__CB_BUSY_MASK 0x40000000L
247#define GRBM_STATUS__GUI_ACTIVE_MASK 0x80000000L
248//GRBM_STATUS_SE0
249#define GRBM_STATUS_SE0__DB_CLEAN__SHIFT 0x1
250#define GRBM_STATUS_SE0__CB_CLEAN__SHIFT 0x2
251#define GRBM_STATUS_SE0__RMI_BUSY__SHIFT 0x15
252#define GRBM_STATUS_SE0__BCI_BUSY__SHIFT 0x16
253#define GRBM_STATUS_SE0__VGT_BUSY__SHIFT 0x17
254#define GRBM_STATUS_SE0__PA_BUSY__SHIFT 0x18
255#define GRBM_STATUS_SE0__TA_BUSY__SHIFT 0x19
256#define GRBM_STATUS_SE0__SX_BUSY__SHIFT 0x1a
257#define GRBM_STATUS_SE0__SPI_BUSY__SHIFT 0x1b
258#define GRBM_STATUS_SE0__SC_BUSY__SHIFT 0x1d
259#define GRBM_STATUS_SE0__DB_BUSY__SHIFT 0x1e
260#define GRBM_STATUS_SE0__CB_BUSY__SHIFT 0x1f
261#define GRBM_STATUS_SE0__DB_CLEAN_MASK 0x00000002L
262#define GRBM_STATUS_SE0__CB_CLEAN_MASK 0x00000004L
263#define GRBM_STATUS_SE0__RMI_BUSY_MASK 0x00200000L
264#define GRBM_STATUS_SE0__BCI_BUSY_MASK 0x00400000L
265#define GRBM_STATUS_SE0__VGT_BUSY_MASK 0x00800000L
266#define GRBM_STATUS_SE0__PA_BUSY_MASK 0x01000000L
267#define GRBM_STATUS_SE0__TA_BUSY_MASK 0x02000000L
268#define GRBM_STATUS_SE0__SX_BUSY_MASK 0x04000000L
269#define GRBM_STATUS_SE0__SPI_BUSY_MASK 0x08000000L
270#define GRBM_STATUS_SE0__SC_BUSY_MASK 0x20000000L
271#define GRBM_STATUS_SE0__DB_BUSY_MASK 0x40000000L
272#define GRBM_STATUS_SE0__CB_BUSY_MASK 0x80000000L
273//GRBM_STATUS_SE1
274#define GRBM_STATUS_SE1__DB_CLEAN__SHIFT 0x1
275#define GRBM_STATUS_SE1__CB_CLEAN__SHIFT 0x2
276#define GRBM_STATUS_SE1__RMI_BUSY__SHIFT 0x15
277#define GRBM_STATUS_SE1__BCI_BUSY__SHIFT 0x16
278#define GRBM_STATUS_SE1__VGT_BUSY__SHIFT 0x17
279#define GRBM_STATUS_SE1__PA_BUSY__SHIFT 0x18
280#define GRBM_STATUS_SE1__TA_BUSY__SHIFT 0x19
281#define GRBM_STATUS_SE1__SX_BUSY__SHIFT 0x1a
282#define GRBM_STATUS_SE1__SPI_BUSY__SHIFT 0x1b
283#define GRBM_STATUS_SE1__SC_BUSY__SHIFT 0x1d
284#define GRBM_STATUS_SE1__DB_BUSY__SHIFT 0x1e
285#define GRBM_STATUS_SE1__CB_BUSY__SHIFT 0x1f
286#define GRBM_STATUS_SE1__DB_CLEAN_MASK 0x00000002L
287#define GRBM_STATUS_SE1__CB_CLEAN_MASK 0x00000004L
288#define GRBM_STATUS_SE1__RMI_BUSY_MASK 0x00200000L
289#define GRBM_STATUS_SE1__BCI_BUSY_MASK 0x00400000L
290#define GRBM_STATUS_SE1__VGT_BUSY_MASK 0x00800000L
291#define GRBM_STATUS_SE1__PA_BUSY_MASK 0x01000000L
292#define GRBM_STATUS_SE1__TA_BUSY_MASK 0x02000000L
293#define GRBM_STATUS_SE1__SX_BUSY_MASK 0x04000000L
294#define GRBM_STATUS_SE1__SPI_BUSY_MASK 0x08000000L
295#define GRBM_STATUS_SE1__SC_BUSY_MASK 0x20000000L
296#define GRBM_STATUS_SE1__DB_BUSY_MASK 0x40000000L
297#define GRBM_STATUS_SE1__CB_BUSY_MASK 0x80000000L
298//GRBM_SOFT_RESET
299#define GRBM_SOFT_RESET__SOFT_RESET_CP__SHIFT 0x0
300#define GRBM_SOFT_RESET__SOFT_RESET_RLC__SHIFT 0x2
301#define GRBM_SOFT_RESET__SOFT_RESET_GFX__SHIFT 0x10
302#define GRBM_SOFT_RESET__SOFT_RESET_CPF__SHIFT 0x11
303#define GRBM_SOFT_RESET__SOFT_RESET_CPC__SHIFT 0x12
304#define GRBM_SOFT_RESET__SOFT_RESET_CPG__SHIFT 0x13
305#define GRBM_SOFT_RESET__SOFT_RESET_CAC__SHIFT 0x14
306#define GRBM_SOFT_RESET__SOFT_RESET_CPAXI__SHIFT 0x15
307#define GRBM_SOFT_RESET__SOFT_RESET_EA__SHIFT 0x16
308#define GRBM_SOFT_RESET__SOFT_RESET_CP_MASK 0x00000001L
309#define GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK 0x00000004L
310#define GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK 0x00010000L
311#define GRBM_SOFT_RESET__SOFT_RESET_CPF_MASK 0x00020000L
312#define GRBM_SOFT_RESET__SOFT_RESET_CPC_MASK 0x00040000L
313#define GRBM_SOFT_RESET__SOFT_RESET_CPG_MASK 0x00080000L
314#define GRBM_SOFT_RESET__SOFT_RESET_CAC_MASK 0x00100000L
315#define GRBM_SOFT_RESET__SOFT_RESET_CPAXI_MASK 0x00200000L
316#define GRBM_SOFT_RESET__SOFT_RESET_EA_MASK 0x00400000L
317//GRBM_CGTT_CLK_CNTL
318#define GRBM_CGTT_CLK_CNTL__ON_DELAY__SHIFT 0x0
319#define GRBM_CGTT_CLK_CNTL__OFF_HYSTERESIS__SHIFT 0x4
320#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE7__SHIFT 0x10
321#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE6__SHIFT 0x11
322#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE5__SHIFT 0x12
323#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE4__SHIFT 0x13
324#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE3__SHIFT 0x14
325#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE2__SHIFT 0x15
326#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE1__SHIFT 0x16
327#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE0__SHIFT 0x17
328#define GRBM_CGTT_CLK_CNTL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
329#define GRBM_CGTT_CLK_CNTL__ON_DELAY_MASK 0x0000000FL
330#define GRBM_CGTT_CLK_CNTL__OFF_HYSTERESIS_MASK 0x00000FF0L
331#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L
332#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L
333#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L
334#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L
335#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L
336#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L
337#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L
338#define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L
339#define GRBM_CGTT_CLK_CNTL__SOFT_OVERRIDE_DYN_MASK 0x40000000L
340//GRBM_GFX_CLKEN_CNTL
341#define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0
342#define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8
343#define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0x0000000FL
344#define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x00001F00L
345//GRBM_WAIT_IDLE_CLOCKS
346#define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS__SHIFT 0x0
347#define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_MASK 0x000000FFL
348//GRBM_STATUS_SE2
349#define GRBM_STATUS_SE2__DB_CLEAN__SHIFT 0x1
350#define GRBM_STATUS_SE2__CB_CLEAN__SHIFT 0x2
351#define GRBM_STATUS_SE2__RMI_BUSY__SHIFT 0x15
352#define GRBM_STATUS_SE2__BCI_BUSY__SHIFT 0x16
353#define GRBM_STATUS_SE2__VGT_BUSY__SHIFT 0x17
354#define GRBM_STATUS_SE2__PA_BUSY__SHIFT 0x18
355#define GRBM_STATUS_SE2__TA_BUSY__SHIFT 0x19
356#define GRBM_STATUS_SE2__SX_BUSY__SHIFT 0x1a
357#define GRBM_STATUS_SE2__SPI_BUSY__SHIFT 0x1b
358#define GRBM_STATUS_SE2__SC_BUSY__SHIFT 0x1d
359#define GRBM_STATUS_SE2__DB_BUSY__SHIFT 0x1e
360#define GRBM_STATUS_SE2__CB_BUSY__SHIFT 0x1f
361#define GRBM_STATUS_SE2__DB_CLEAN_MASK 0x00000002L
362#define GRBM_STATUS_SE2__CB_CLEAN_MASK 0x00000004L
363#define GRBM_STATUS_SE2__RMI_BUSY_MASK 0x00200000L
364#define GRBM_STATUS_SE2__BCI_BUSY_MASK 0x00400000L
365#define GRBM_STATUS_SE2__VGT_BUSY_MASK 0x00800000L
366#define GRBM_STATUS_SE2__PA_BUSY_MASK 0x01000000L
367#define GRBM_STATUS_SE2__TA_BUSY_MASK 0x02000000L
368#define GRBM_STATUS_SE2__SX_BUSY_MASK 0x04000000L
369#define GRBM_STATUS_SE2__SPI_BUSY_MASK 0x08000000L
370#define GRBM_STATUS_SE2__SC_BUSY_MASK 0x20000000L
371#define GRBM_STATUS_SE2__DB_BUSY_MASK 0x40000000L
372#define GRBM_STATUS_SE2__CB_BUSY_MASK 0x80000000L
373//GRBM_STATUS_SE3
374#define GRBM_STATUS_SE3__DB_CLEAN__SHIFT 0x1
375#define GRBM_STATUS_SE3__CB_CLEAN__SHIFT 0x2
376#define GRBM_STATUS_SE3__RMI_BUSY__SHIFT 0x15
377#define GRBM_STATUS_SE3__BCI_BUSY__SHIFT 0x16
378#define GRBM_STATUS_SE3__VGT_BUSY__SHIFT 0x17
379#define GRBM_STATUS_SE3__PA_BUSY__SHIFT 0x18
380#define GRBM_STATUS_SE3__TA_BUSY__SHIFT 0x19
381#define GRBM_STATUS_SE3__SX_BUSY__SHIFT 0x1a
382#define GRBM_STATUS_SE3__SPI_BUSY__SHIFT 0x1b
383#define GRBM_STATUS_SE3__SC_BUSY__SHIFT 0x1d
384#define GRBM_STATUS_SE3__DB_BUSY__SHIFT 0x1e
385#define GRBM_STATUS_SE3__CB_BUSY__SHIFT 0x1f
386#define GRBM_STATUS_SE3__DB_CLEAN_MASK 0x00000002L
387#define GRBM_STATUS_SE3__CB_CLEAN_MASK 0x00000004L
388#define GRBM_STATUS_SE3__RMI_BUSY_MASK 0x00200000L
389#define GRBM_STATUS_SE3__BCI_BUSY_MASK 0x00400000L
390#define GRBM_STATUS_SE3__VGT_BUSY_MASK 0x00800000L
391#define GRBM_STATUS_SE3__PA_BUSY_MASK 0x01000000L
392#define GRBM_STATUS_SE3__TA_BUSY_MASK 0x02000000L
393#define GRBM_STATUS_SE3__SX_BUSY_MASK 0x04000000L
394#define GRBM_STATUS_SE3__SPI_BUSY_MASK 0x08000000L
395#define GRBM_STATUS_SE3__SC_BUSY_MASK 0x20000000L
396#define GRBM_STATUS_SE3__DB_BUSY_MASK 0x40000000L
397#define GRBM_STATUS_SE3__CB_BUSY_MASK 0x80000000L
398//GRBM_READ_ERROR
399#define GRBM_READ_ERROR__READ_ADDRESS__SHIFT 0x2
400#define GRBM_READ_ERROR__READ_PIPEID__SHIFT 0x14
401#define GRBM_READ_ERROR__READ_MEID__SHIFT 0x16
402#define GRBM_READ_ERROR__READ_ERROR__SHIFT 0x1f
403#define GRBM_READ_ERROR__READ_ADDRESS_MASK 0x0003FFFCL
404#define GRBM_READ_ERROR__READ_PIPEID_MASK 0x00300000L
405#define GRBM_READ_ERROR__READ_MEID_MASK 0x00C00000L
406#define GRBM_READ_ERROR__READ_ERROR_MASK 0x80000000L
407//GRBM_READ_ERROR2
408#define GRBM_READ_ERROR2__READ_REQUESTER_CPF__SHIFT 0x10
409#define GRBM_READ_ERROR2__READ_REQUESTER_RSMU__SHIFT 0x11
410#define GRBM_READ_ERROR2__READ_REQUESTER_RLC__SHIFT 0x12
411#define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA__SHIFT 0x13
412#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF__SHIFT 0x14
413#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF__SHIFT 0x15
414#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF__SHIFT 0x16
415#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF__SHIFT 0x17
416#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0__SHIFT 0x18
417#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1__SHIFT 0x19
418#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2__SHIFT 0x1a
419#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3__SHIFT 0x1b
420#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0__SHIFT 0x1c
421#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1__SHIFT 0x1d
422#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2__SHIFT 0x1e
423#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3__SHIFT 0x1f
424#define GRBM_READ_ERROR2__READ_REQUESTER_CPF_MASK 0x00010000L
425#define GRBM_READ_ERROR2__READ_REQUESTER_RSMU_MASK 0x00020000L
426#define GRBM_READ_ERROR2__READ_REQUESTER_RLC_MASK 0x00040000L
427#define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA_MASK 0x00080000L
428#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF_MASK 0x00100000L
429#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF_MASK 0x00200000L
430#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF_MASK 0x00400000L
431#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF_MASK 0x00800000L
432#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0_MASK 0x01000000L
433#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1_MASK 0x02000000L
434#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2_MASK 0x04000000L
435#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3_MASK 0x08000000L
436#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0_MASK 0x10000000L
437#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1_MASK 0x20000000L
438#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2_MASK 0x40000000L
439#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3_MASK 0x80000000L
440//GRBM_INT_CNTL
441#define GRBM_INT_CNTL__RDERR_INT_ENABLE__SHIFT 0x0
442#define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE__SHIFT 0x13
443#define GRBM_INT_CNTL__RDERR_INT_ENABLE_MASK 0x00000001L
444#define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE_MASK 0x00080000L
445//GRBM_TRAP_OP
446#define GRBM_TRAP_OP__RW__SHIFT 0x0
447#define GRBM_TRAP_OP__RW_MASK 0x00000001L
448//GRBM_TRAP_ADDR
449#define GRBM_TRAP_ADDR__DATA__SHIFT 0x0
450#define GRBM_TRAP_ADDR__DATA_MASK 0x0003FFFFL
451//GRBM_TRAP_ADDR_MSK
452#define GRBM_TRAP_ADDR_MSK__DATA__SHIFT 0x0
453#define GRBM_TRAP_ADDR_MSK__DATA_MASK 0x0003FFFFL
454//GRBM_TRAP_WD
455#define GRBM_TRAP_WD__DATA__SHIFT 0x0
456#define GRBM_TRAP_WD__DATA_MASK 0xFFFFFFFFL
457//GRBM_TRAP_WD_MSK
458#define GRBM_TRAP_WD_MSK__DATA__SHIFT 0x0
459#define GRBM_TRAP_WD_MSK__DATA_MASK 0xFFFFFFFFL
460//GRBM_DSM_BYPASS
461#define GRBM_DSM_BYPASS__BYPASS_BITS__SHIFT 0x0
462#define GRBM_DSM_BYPASS__BYPASS_EN__SHIFT 0x2
463#define GRBM_DSM_BYPASS__BYPASS_BITS_MASK 0x00000003L
464#define GRBM_DSM_BYPASS__BYPASS_EN_MASK 0x00000004L
465//GRBM_WRITE_ERROR
466#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC__SHIFT 0x0
467#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RSMU__SHIFT 0x1
468#define GRBM_WRITE_ERROR__WRITE_SSRCID__SHIFT 0x2
469#define GRBM_WRITE_ERROR__WRITE_VFID__SHIFT 0x5
470#define GRBM_WRITE_ERROR__WRITE_VF__SHIFT 0xc
471#define GRBM_WRITE_ERROR__WRITE_VMID__SHIFT 0xd
472#define GRBM_WRITE_ERROR__WRITE_PIPEID__SHIFT 0x14
473#define GRBM_WRITE_ERROR__WRITE_MEID__SHIFT 0x16
474#define GRBM_WRITE_ERROR__WRITE_ERROR__SHIFT 0x1f
475#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC_MASK 0x00000001L
476#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RSMU_MASK 0x00000002L
477#define GRBM_WRITE_ERROR__WRITE_SSRCID_MASK 0x0000001CL
478#define GRBM_WRITE_ERROR__WRITE_VFID_MASK 0x000001E0L
479#define GRBM_WRITE_ERROR__WRITE_VF_MASK 0x00001000L
480#define GRBM_WRITE_ERROR__WRITE_VMID_MASK 0x0001E000L
481#define GRBM_WRITE_ERROR__WRITE_PIPEID_MASK 0x00300000L
482#define GRBM_WRITE_ERROR__WRITE_MEID_MASK 0x00C00000L
483#define GRBM_WRITE_ERROR__WRITE_ERROR_MASK 0x80000000L
484//GRBM_IOV_ERROR
485#define GRBM_IOV_ERROR__IOV_ADDR__SHIFT 0x2
486#define GRBM_IOV_ERROR__IOV_VFID__SHIFT 0x14
487#define GRBM_IOV_ERROR__IOV_VF__SHIFT 0x1a
488#define GRBM_IOV_ERROR__IOV_OP__SHIFT 0x1b
489#define GRBM_IOV_ERROR__IOV_ERROR__SHIFT 0x1f
490#define GRBM_IOV_ERROR__IOV_ADDR_MASK 0x000FFFFCL
491#define GRBM_IOV_ERROR__IOV_VFID_MASK 0x03F00000L
492#define GRBM_IOV_ERROR__IOV_VF_MASK 0x04000000L
493#define GRBM_IOV_ERROR__IOV_OP_MASK 0x08000000L
494#define GRBM_IOV_ERROR__IOV_ERROR_MASK 0x80000000L
495//GRBM_CHIP_REVISION
496#define GRBM_CHIP_REVISION__CHIP_REVISION__SHIFT 0x0
497#define GRBM_CHIP_REVISION__CHIP_REVISION_MASK 0x000000FFL
498//GRBM_GFX_CNTL
499#define GRBM_GFX_CNTL__PIPEID__SHIFT 0x0
500#define GRBM_GFX_CNTL__MEID__SHIFT 0x2
501#define GRBM_GFX_CNTL__VMID__SHIFT 0x4
502#define GRBM_GFX_CNTL__QUEUEID__SHIFT 0x8
503#define GRBM_GFX_CNTL__PIPEID_MASK 0x00000003L
504#define GRBM_GFX_CNTL__MEID_MASK 0x0000000CL
505#define GRBM_GFX_CNTL__VMID_MASK 0x000000F0L
506#define GRBM_GFX_CNTL__QUEUEID_MASK 0x00000700L
507//GRBM_RSMU_CFG
508#define GRBM_RSMU_CFG__APERTURE_ID__SHIFT 0x0
509#define GRBM_RSMU_CFG__QOS__SHIFT 0xc
510#define GRBM_RSMU_CFG__POSTED_WR__SHIFT 0x10
511#define GRBM_RSMU_CFG__DEBUG_MASK__SHIFT 0x11
512#define GRBM_RSMU_CFG__APERTURE_ID_MASK 0x00000FFFL
513#define GRBM_RSMU_CFG__QOS_MASK 0x0000F000L
514#define GRBM_RSMU_CFG__POSTED_WR_MASK 0x00010000L
515#define GRBM_RSMU_CFG__DEBUG_MASK_MASK 0x00020000L
516//GRBM_IH_CREDIT
517#define GRBM_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0
518#define GRBM_IH_CREDIT__IH_CLIENT_ID__SHIFT 0x10
519#define GRBM_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L
520#define GRBM_IH_CREDIT__IH_CLIENT_ID_MASK 0x00FF0000L
521//GRBM_PWR_CNTL2
522#define GRBM_PWR_CNTL2__PWR_REQUEST_HALT__SHIFT 0x10
523#define GRBM_PWR_CNTL2__PWR_GFX3D_REQUEST_HALT__SHIFT 0x14
524#define GRBM_PWR_CNTL2__PWR_REQUEST_HALT_MASK 0x00010000L
525#define GRBM_PWR_CNTL2__PWR_GFX3D_REQUEST_HALT_MASK 0x00100000L
526//GRBM_UTCL2_INVAL_RANGE_START
527#define GRBM_UTCL2_INVAL_RANGE_START__DATA__SHIFT 0x0
528#define GRBM_UTCL2_INVAL_RANGE_START__DATA_MASK 0x0003FFFFL
529//GRBM_UTCL2_INVAL_RANGE_END
530#define GRBM_UTCL2_INVAL_RANGE_END__DATA__SHIFT 0x0
531#define GRBM_UTCL2_INVAL_RANGE_END__DATA_MASK 0x0003FFFFL
532//GRBM_RSMU_READ_ERROR
533#define GRBM_RSMU_READ_ERROR__RSMU_READ_ADDRESS__SHIFT 0x2
534#define GRBM_RSMU_READ_ERROR__RSMU_READ_VF__SHIFT 0x14
535#define GRBM_RSMU_READ_ERROR__RSMU_READ_VFID__SHIFT 0x15
536#define GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR_TYPE__SHIFT 0x1b
537#define GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR__SHIFT 0x1f
538#define GRBM_RSMU_READ_ERROR__RSMU_READ_ADDRESS_MASK 0x000FFFFCL
539#define GRBM_RSMU_READ_ERROR__RSMU_READ_VF_MASK 0x00100000L
540#define GRBM_RSMU_READ_ERROR__RSMU_READ_VFID_MASK 0x07E00000L
541#define GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR_TYPE_MASK 0x08000000L
542#define GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR_MASK 0x80000000L
543//GRBM_CHICKEN_BITS
544#define GRBM_CHICKEN_BITS__DISABLE_CP_VMID_RESET_REQ__SHIFT 0x0
545#define GRBM_CHICKEN_BITS__DISABLE_CP_VMID_RESET_REQ_MASK 0x00000001L
546//GRBM_NOWHERE
547#define GRBM_NOWHERE__DATA__SHIFT 0x0
548#define GRBM_NOWHERE__DATA_MASK 0xFFFFFFFFL
549//GRBM_SCRATCH_REG0
550#define GRBM_SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x0
551#define GRBM_SCRATCH_REG0__SCRATCH_REG0_MASK 0xFFFFFFFFL
552//GRBM_SCRATCH_REG1
553#define GRBM_SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x0
554#define GRBM_SCRATCH_REG1__SCRATCH_REG1_MASK 0xFFFFFFFFL
555//GRBM_SCRATCH_REG2
556#define GRBM_SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x0
557#define GRBM_SCRATCH_REG2__SCRATCH_REG2_MASK 0xFFFFFFFFL
558//GRBM_SCRATCH_REG3
559#define GRBM_SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x0
560#define GRBM_SCRATCH_REG3__SCRATCH_REG3_MASK 0xFFFFFFFFL
561//GRBM_SCRATCH_REG4
562#define GRBM_SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x0
563#define GRBM_SCRATCH_REG4__SCRATCH_REG4_MASK 0xFFFFFFFFL
564//GRBM_SCRATCH_REG5
565#define GRBM_SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x0
566#define GRBM_SCRATCH_REG5__SCRATCH_REG5_MASK 0xFFFFFFFFL
567//GRBM_SCRATCH_REG6
568#define GRBM_SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x0
569#define GRBM_SCRATCH_REG6__SCRATCH_REG6_MASK 0xFFFFFFFFL
570//GRBM_SCRATCH_REG7
571#define GRBM_SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x0
572#define GRBM_SCRATCH_REG7__SCRATCH_REG7_MASK 0xFFFFFFFFL
573
574
575// addressBlock: gc_cpdec
576//CP_CPC_STATUS
577#define CP_CPC_STATUS__MEC1_BUSY__SHIFT 0x0
578#define CP_CPC_STATUS__MEC2_BUSY__SHIFT 0x1
579#define CP_CPC_STATUS__DC0_BUSY__SHIFT 0x2
580#define CP_CPC_STATUS__DC1_BUSY__SHIFT 0x3
581#define CP_CPC_STATUS__RCIU1_BUSY__SHIFT 0x4
582#define CP_CPC_STATUS__RCIU2_BUSY__SHIFT 0x5
583#define CP_CPC_STATUS__ROQ1_BUSY__SHIFT 0x6
584#define CP_CPC_STATUS__ROQ2_BUSY__SHIFT 0x7
585#define CP_CPC_STATUS__TCIU_BUSY__SHIFT 0xa
586#define CP_CPC_STATUS__SCRATCH_RAM_BUSY__SHIFT 0xb
587#define CP_CPC_STATUS__QU_BUSY__SHIFT 0xc
588#define CP_CPC_STATUS__UTCL2IU_BUSY__SHIFT 0xd
589#define CP_CPC_STATUS__SAVE_RESTORE_BUSY__SHIFT 0xe
590#define CP_CPC_STATUS__CPG_CPC_BUSY__SHIFT 0x1d
591#define CP_CPC_STATUS__CPF_CPC_BUSY__SHIFT 0x1e
592#define CP_CPC_STATUS__CPC_BUSY__SHIFT 0x1f
593#define CP_CPC_STATUS__MEC1_BUSY_MASK 0x00000001L
594#define CP_CPC_STATUS__MEC2_BUSY_MASK 0x00000002L
595#define CP_CPC_STATUS__DC0_BUSY_MASK 0x00000004L
596#define CP_CPC_STATUS__DC1_BUSY_MASK 0x00000008L
597#define CP_CPC_STATUS__RCIU1_BUSY_MASK 0x00000010L
598#define CP_CPC_STATUS__RCIU2_BUSY_MASK 0x00000020L
599#define CP_CPC_STATUS__ROQ1_BUSY_MASK 0x00000040L
600#define CP_CPC_STATUS__ROQ2_BUSY_MASK 0x00000080L
601#define CP_CPC_STATUS__TCIU_BUSY_MASK 0x00000400L
602#define CP_CPC_STATUS__SCRATCH_RAM_BUSY_MASK 0x00000800L
603#define CP_CPC_STATUS__QU_BUSY_MASK 0x00001000L
604#define CP_CPC_STATUS__UTCL2IU_BUSY_MASK 0x00002000L
605#define CP_CPC_STATUS__SAVE_RESTORE_BUSY_MASK 0x00004000L
606#define CP_CPC_STATUS__CPG_CPC_BUSY_MASK 0x20000000L
607#define CP_CPC_STATUS__CPF_CPC_BUSY_MASK 0x40000000L
608#define CP_CPC_STATUS__CPC_BUSY_MASK 0x80000000L
609//CP_CPC_BUSY_STAT
610#define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY__SHIFT 0x0
611#define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY__SHIFT 0x1
612#define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY__SHIFT 0x2
613#define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY__SHIFT 0x3
614#define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY__SHIFT 0x4
615#define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY__SHIFT 0x5
616#define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY__SHIFT 0x6
617#define CP_CPC_BUSY_STAT__MEC1_TC_BUSY__SHIFT 0x7
618#define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY__SHIFT 0x8
619#define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY__SHIFT 0x9
620#define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY__SHIFT 0xa
621#define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY__SHIFT 0xb
622#define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY__SHIFT 0xc
623#define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY__SHIFT 0xd
624#define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY__SHIFT 0x10
625#define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY__SHIFT 0x11
626#define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY__SHIFT 0x12
627#define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY__SHIFT 0x13
628#define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY__SHIFT 0x14
629#define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY__SHIFT 0x15
630#define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY__SHIFT 0x16
631#define CP_CPC_BUSY_STAT__MEC2_TC_BUSY__SHIFT 0x17
632#define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY__SHIFT 0x18
633#define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY__SHIFT 0x19
634#define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY__SHIFT 0x1a
635#define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY__SHIFT 0x1b
636#define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY__SHIFT 0x1c
637#define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY__SHIFT 0x1d
638#define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY_MASK 0x00000001L
639#define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY_MASK 0x00000002L
640#define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY_MASK 0x00000004L
641#define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY_MASK 0x00000008L
642#define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY_MASK 0x00000010L
643#define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY_MASK 0x00000020L
644#define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY_MASK 0x00000040L
645#define CP_CPC_BUSY_STAT__MEC1_TC_BUSY_MASK 0x00000080L
646#define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY_MASK 0x00000100L
647#define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY_MASK 0x00000200L
648#define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY_MASK 0x00000400L
649#define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY_MASK 0x00000800L
650#define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY_MASK 0x00001000L
651#define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY_MASK 0x00002000L
652#define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY_MASK 0x00010000L
653#define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY_MASK 0x00020000L
654#define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY_MASK 0x00040000L
655#define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY_MASK 0x00080000L
656#define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY_MASK 0x00100000L
657#define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY_MASK 0x00200000L
658#define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY_MASK 0x00400000L
659#define CP_CPC_BUSY_STAT__MEC2_TC_BUSY_MASK 0x00800000L
660#define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY_MASK 0x01000000L
661#define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY_MASK 0x02000000L
662#define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY_MASK 0x04000000L
663#define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY_MASK 0x08000000L
664#define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY_MASK 0x10000000L
665#define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY_MASK 0x20000000L
666//CP_CPC_STALLED_STAT1
667#define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL__SHIFT 0x3
668#define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION__SHIFT 0x4
669#define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL__SHIFT 0x6
670#define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET__SHIFT 0x8
671#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU__SHIFT 0x9
672#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ__SHIFT 0xa
673#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA__SHIFT 0xd
674#define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET__SHIFT 0x10
675#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU__SHIFT 0x11
676#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ__SHIFT 0x12
677#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA__SHIFT 0x15
678#define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE__SHIFT 0x16
679#define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS__SHIFT 0x17
680#define CP_CPC_STALLED_STAT1__UTCL1_WAITING_ON_TRANS__SHIFT 0x18
681#define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL_MASK 0x00000008L
682#define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION_MASK 0x00000010L
683#define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL_MASK 0x00000040L
684#define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET_MASK 0x00000100L
685#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_MASK 0x00000200L
686#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ_MASK 0x00000400L
687#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA_MASK 0x00002000L
688#define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET_MASK 0x00010000L
689#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_MASK 0x00020000L
690#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ_MASK 0x00040000L
691#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA_MASK 0x00200000L
692#define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE_MASK 0x00400000L
693#define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS_MASK 0x00800000L
694#define CP_CPC_STALLED_STAT1__UTCL1_WAITING_ON_TRANS_MASK 0x01000000L
695//CP_CPF_STATUS
696#define CP_CPF_STATUS__POST_WPTR_GFX_BUSY__SHIFT 0x0
697#define CP_CPF_STATUS__CSF_BUSY__SHIFT 0x1
698#define CP_CPF_STATUS__ROQ_ALIGN_BUSY__SHIFT 0x4
699#define CP_CPF_STATUS__ROQ_RING_BUSY__SHIFT 0x5
700#define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY__SHIFT 0x6
701#define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY__SHIFT 0x7
702#define CP_CPF_STATUS__ROQ_STATE_BUSY__SHIFT 0x8
703#define CP_CPF_STATUS__ROQ_CE_RING_BUSY__SHIFT 0x9
704#define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY__SHIFT 0xa
705#define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY__SHIFT 0xb
706#define CP_CPF_STATUS__SEMAPHORE_BUSY__SHIFT 0xc
707#define CP_CPF_STATUS__INTERRUPT_BUSY__SHIFT 0xd
708#define CP_CPF_STATUS__TCIU_BUSY__SHIFT 0xe
709#define CP_CPF_STATUS__HQD_BUSY__SHIFT 0xf
710#define CP_CPF_STATUS__PRT_BUSY__SHIFT 0x10
711#define CP_CPF_STATUS__UTCL2IU_BUSY__SHIFT 0x11
712#define CP_CPF_STATUS__CPF_GFX_BUSY__SHIFT 0x1a
713#define CP_CPF_STATUS__CPF_CMP_BUSY__SHIFT 0x1b
714#define CP_CPF_STATUS__GRBM_CPF_STAT_BUSY__SHIFT 0x1c
715#define CP_CPF_STATUS__CPC_CPF_BUSY__SHIFT 0x1e
716#define CP_CPF_STATUS__CPF_BUSY__SHIFT 0x1f
717#define CP_CPF_STATUS__POST_WPTR_GFX_BUSY_MASK 0x00000001L
718#define CP_CPF_STATUS__CSF_BUSY_MASK 0x00000002L
719#define CP_CPF_STATUS__ROQ_ALIGN_BUSY_MASK 0x00000010L
720#define CP_CPF_STATUS__ROQ_RING_BUSY_MASK 0x00000020L
721#define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY_MASK 0x00000040L
722#define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY_MASK 0x00000080L
723#define CP_CPF_STATUS__ROQ_STATE_BUSY_MASK 0x00000100L
724#define CP_CPF_STATUS__ROQ_CE_RING_BUSY_MASK 0x00000200L
725#define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY_MASK 0x00000400L
726#define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY_MASK 0x00000800L
727#define CP_CPF_STATUS__SEMAPHORE_BUSY_MASK 0x00001000L
728#define CP_CPF_STATUS__INTERRUPT_BUSY_MASK 0x00002000L
729#define CP_CPF_STATUS__TCIU_BUSY_MASK 0x00004000L
730#define CP_CPF_STATUS__HQD_BUSY_MASK 0x00008000L
731#define CP_CPF_STATUS__PRT_BUSY_MASK 0x00010000L
732#define CP_CPF_STATUS__UTCL2IU_BUSY_MASK 0x00020000L
733#define CP_CPF_STATUS__CPF_GFX_BUSY_MASK 0x04000000L
734#define CP_CPF_STATUS__CPF_CMP_BUSY_MASK 0x08000000L
735#define CP_CPF_STATUS__GRBM_CPF_STAT_BUSY_MASK 0x30000000L
736#define CP_CPF_STATUS__CPC_CPF_BUSY_MASK 0x40000000L
737#define CP_CPF_STATUS__CPF_BUSY_MASK 0x80000000L
738//CP_CPF_BUSY_STAT
739#define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x0
740#define CP_CPF_BUSY_STAT__CSF_RING_BUSY__SHIFT 0x1
741#define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY__SHIFT 0x2
742#define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY__SHIFT 0x3
743#define CP_CPF_BUSY_STAT__CSF_STATE_BUSY__SHIFT 0x4
744#define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY__SHIFT 0x5
745#define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY__SHIFT 0x6
746#define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY__SHIFT 0x7
747#define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY__SHIFT 0x8
748#define CP_CPF_BUSY_STAT__OUTSTANDING_READ_TAGS__SHIFT 0x9
749#define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY__SHIFT 0xb
750#define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY__SHIFT 0xc
751#define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY__SHIFT 0xd
752#define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY__SHIFT 0xe
753#define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY__SHIFT 0xf
754#define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY__SHIFT 0x10
755#define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY__SHIFT 0x11
756#define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY__SHIFT 0x12
757#define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY__SHIFT 0x13
758#define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY__SHIFT 0x14
759#define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY__SHIFT 0x15
760#define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY__SHIFT 0x16
761#define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY__SHIFT 0x17
762#define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY__SHIFT 0x18
763#define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY__SHIFT 0x19
764#define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY__SHIFT 0x1a
765#define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY__SHIFT 0x1b
766#define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY__SHIFT 0x1c
767#define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY__SHIFT 0x1d
768#define CP_CPF_BUSY_STAT__HQD_PQ_BUSY__SHIFT 0x1e
769#define CP_CPF_BUSY_STAT__HQD_IB_BUSY__SHIFT 0x1f
770#define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x00000001L
771#define CP_CPF_BUSY_STAT__CSF_RING_BUSY_MASK 0x00000002L
772#define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY_MASK 0x00000004L
773#define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY_MASK 0x00000008L
774#define CP_CPF_BUSY_STAT__CSF_STATE_BUSY_MASK 0x00000010L
775#define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY_MASK 0x00000020L
776#define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY_MASK 0x00000040L
777#define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY_MASK 0x00000080L
778#define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY_MASK 0x00000100L
779#define CP_CPF_BUSY_STAT__OUTSTANDING_READ_TAGS_MASK 0x00000200L
780#define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY_MASK 0x00000800L
781#define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY_MASK 0x00001000L
782#define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY_MASK 0x00002000L
783#define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY_MASK 0x00004000L
784#define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY_MASK 0x00008000L
785#define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY_MASK 0x00010000L
786#define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY_MASK 0x00020000L
787#define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY_MASK 0x00040000L
788#define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY_MASK 0x00080000L
789#define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY_MASK 0x00100000L
790#define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY_MASK 0x00200000L
791#define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY_MASK 0x00400000L
792#define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY_MASK 0x00800000L
793#define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY_MASK 0x01000000L
794#define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY_MASK 0x02000000L
795#define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY_MASK 0x04000000L
796#define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY_MASK 0x08000000L
797#define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY_MASK 0x10000000L
798#define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY_MASK 0x20000000L
799#define CP_CPF_BUSY_STAT__HQD_PQ_BUSY_MASK 0x40000000L
800#define CP_CPF_BUSY_STAT__HQD_IB_BUSY_MASK 0x80000000L
801//CP_CPF_STALLED_STAT1
802#define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA__SHIFT 0x0
803#define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA__SHIFT 0x1
804#define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA__SHIFT 0x2
805#define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA__SHIFT 0x3
806#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE__SHIFT 0x5
807#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS__SHIFT 0x6
808#define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE__SHIFT 0x7
809#define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS__SHIFT 0x8
810#define CP_CPF_STALLED_STAT1__GFX_UTCL1_WAITING_ON_TRANS__SHIFT 0x9
811#define CP_CPF_STALLED_STAT1__CMP_UTCL1_WAITING_ON_TRANS__SHIFT 0xa
812#define CP_CPF_STALLED_STAT1__RCIU_WAITING_ON_FREE__SHIFT 0xb
813#define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA_MASK 0x00000001L
814#define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA_MASK 0x00000002L
815#define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA_MASK 0x00000004L
816#define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA_MASK 0x00000008L
817#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE_MASK 0x00000020L
818#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS_MASK 0x00000040L
819#define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE_MASK 0x00000080L
820#define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS_MASK 0x00000100L
821#define CP_CPF_STALLED_STAT1__GFX_UTCL1_WAITING_ON_TRANS_MASK 0x00000200L
822#define CP_CPF_STALLED_STAT1__CMP_UTCL1_WAITING_ON_TRANS_MASK 0x00000400L
823#define CP_CPF_STALLED_STAT1__RCIU_WAITING_ON_FREE_MASK 0x00000800L
824//CP_CPC_GRBM_FREE_COUNT
825#define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0
826#define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x0000003FL
827//CP_MEC_CNTL
828#define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE__SHIFT 0x4
829#define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET__SHIFT 0x10
830#define CP_MEC_CNTL__MEC_ME1_PIPE1_RESET__SHIFT 0x11
831#define CP_MEC_CNTL__MEC_ME1_PIPE2_RESET__SHIFT 0x12
832#define CP_MEC_CNTL__MEC_ME1_PIPE3_RESET__SHIFT 0x13
833#define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET__SHIFT 0x14
834#define CP_MEC_CNTL__MEC_ME2_PIPE1_RESET__SHIFT 0x15
835#define CP_MEC_CNTL__MEC_ME2_HALT__SHIFT 0x1c
836#define CP_MEC_CNTL__MEC_ME2_STEP__SHIFT 0x1d
837#define CP_MEC_CNTL__MEC_ME1_HALT__SHIFT 0x1e
838#define CP_MEC_CNTL__MEC_ME1_STEP__SHIFT 0x1f
839#define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE_MASK 0x00000010L
840#define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET_MASK 0x00010000L
841#define CP_MEC_CNTL__MEC_ME1_PIPE1_RESET_MASK 0x00020000L
842#define CP_MEC_CNTL__MEC_ME1_PIPE2_RESET_MASK 0x00040000L
843#define CP_MEC_CNTL__MEC_ME1_PIPE3_RESET_MASK 0x00080000L
844#define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET_MASK 0x00100000L
845#define CP_MEC_CNTL__MEC_ME2_PIPE1_RESET_MASK 0x00200000L
846#define CP_MEC_CNTL__MEC_ME2_HALT_MASK 0x10000000L
847#define CP_MEC_CNTL__MEC_ME2_STEP_MASK 0x20000000L
848#define CP_MEC_CNTL__MEC_ME1_HALT_MASK 0x40000000L
849#define CP_MEC_CNTL__MEC_ME1_STEP_MASK 0x80000000L
850//CP_MEC_ME1_HEADER_DUMP
851#define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP__SHIFT 0x0
852#define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP_MASK 0xFFFFFFFFL
853//CP_MEC_ME2_HEADER_DUMP
854#define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP__SHIFT 0x0
855#define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP_MASK 0xFFFFFFFFL
856//CP_CPC_SCRATCH_INDEX
857#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0
858#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0x000001FFL
859//CP_CPC_SCRATCH_DATA
860#define CP_CPC_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0
861#define CP_CPC_SCRATCH_DATA__SCRATCH_DATA_MASK 0xFFFFFFFFL
862//CP_CPF_GRBM_FREE_COUNT
863#define CP_CPF_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0
864#define CP_CPF_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x00000007L
865//CP_CPC_HALT_HYST_COUNT
866#define CP_CPC_HALT_HYST_COUNT__COUNT__SHIFT 0x0
867#define CP_CPC_HALT_HYST_COUNT__COUNT_MASK 0x0000000FL
868//CP_PRT_LOD_STATS_CNTL0
869#define CP_PRT_LOD_STATS_CNTL0__BU_SIZE__SHIFT 0x0
870#define CP_PRT_LOD_STATS_CNTL0__BU_SIZE_MASK 0xFFFFFFFFL
871//CP_PRT_LOD_STATS_CNTL1
872#define CP_PRT_LOD_STATS_CNTL1__BASE_LO__SHIFT 0x0
873#define CP_PRT_LOD_STATS_CNTL1__BASE_LO_MASK 0xFFFFFFFFL
874//CP_PRT_LOD_STATS_CNTL2
875#define CP_PRT_LOD_STATS_CNTL2__BASE_HI__SHIFT 0x0
876#define CP_PRT_LOD_STATS_CNTL2__BASE_HI_MASK 0x000003FFL
877//CP_PRT_LOD_STATS_CNTL3
878#define CP_PRT_LOD_STATS_CNTL3__INTERVAL__SHIFT 0x2
879#define CP_PRT_LOD_STATS_CNTL3__RESET_CNT__SHIFT 0xa
880#define CP_PRT_LOD_STATS_CNTL3__RESET_FORCE__SHIFT 0x12
881#define CP_PRT_LOD_STATS_CNTL3__REPORT_AND_RESET__SHIFT 0x13
882#define CP_PRT_LOD_STATS_CNTL3__MC_VMID__SHIFT 0x17
883#define CP_PRT_LOD_STATS_CNTL3__CACHE_POLICY__SHIFT 0x1c
884#define CP_PRT_LOD_STATS_CNTL3__INTERVAL_MASK 0x000003FCL
885#define CP_PRT_LOD_STATS_CNTL3__RESET_CNT_MASK 0x0003FC00L
886#define CP_PRT_LOD_STATS_CNTL3__RESET_FORCE_MASK 0x00040000L
887#define CP_PRT_LOD_STATS_CNTL3__REPORT_AND_RESET_MASK 0x00080000L
888#define CP_PRT_LOD_STATS_CNTL3__MC_VMID_MASK 0x07800000L
889#define CP_PRT_LOD_STATS_CNTL3__CACHE_POLICY_MASK 0x10000000L
890//CP_CE_COMPARE_COUNT
891#define CP_CE_COMPARE_COUNT__COMPARE_COUNT__SHIFT 0x0
892#define CP_CE_COMPARE_COUNT__COMPARE_COUNT_MASK 0xFFFFFFFFL
893//CP_CE_DE_COUNT
894#define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT 0x0
895#define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT_MASK 0xFFFFFFFFL
896//CP_DE_CE_COUNT
897#define CP_DE_CE_COUNT__CONST_ENGINE_COUNT__SHIFT 0x0
898#define CP_DE_CE_COUNT__CONST_ENGINE_COUNT_MASK 0xFFFFFFFFL
899//CP_DE_LAST_INVAL_COUNT
900#define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT__SHIFT 0x0
901#define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT_MASK 0xFFFFFFFFL
902//CP_DE_DE_COUNT
903#define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT 0x0
904#define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT_MASK 0xFFFFFFFFL
905//CP_STALLED_STAT3
906#define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0
907#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV__SHIFT 0x1
908#define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER__SHIFT 0x2
909#define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY__SHIFT 0x3
910#define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY__SHIFT 0x4
911#define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY__SHIFT 0x5
912#define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV__SHIFT 0x6
913#define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV__SHIFT 0x7
914#define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA__SHIFT 0xa
915#define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG__SHIFT 0xb
916#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER__SHIFT 0xc
917#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW__SHIFT 0xd
918#define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE__SHIFT 0xe
919#define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS__SHIFT 0xf
920#define CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x10
921#define CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x11
922#define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_FREE__SHIFT 0x12
923#define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_TAGS__SHIFT 0x13
924#define CP_STALLED_STAT3__UTCL1_WAITING_ON_TRANS__SHIFT 0x14
925#define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV_MASK 0x00000001L
926#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV_MASK 0x00000002L
927#define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER_MASK 0x00000004L
928#define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY_MASK 0x00000008L
929#define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY_MASK 0x00000010L
930#define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY_MASK 0x00000020L
931#define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV_MASK 0x00000040L
932#define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV_MASK 0x00000080L
933#define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA_MASK 0x00000400L
934#define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG_MASK 0x00000800L
935#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_MASK 0x00001000L
936#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW_MASK 0x00002000L
937#define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE_MASK 0x00004000L
938#define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS_MASK 0x00008000L
939#define CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM_MASK 0x00010000L
940#define CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x00020000L
941#define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_FREE_MASK 0x00040000L
942#define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_TAGS_MASK 0x00080000L
943#define CP_STALLED_STAT3__UTCL1_WAITING_ON_TRANS_MASK 0x00100000L
944//CP_STALLED_STAT1
945#define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV__SHIFT 0x0
946#define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV__SHIFT 0x2
947#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV__SHIFT 0x4
948#define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG__SHIFT 0xa
949#define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG__SHIFT 0xb
950#define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM__SHIFT 0xc
951#define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0xd
952#define CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA__SHIFT 0xe
953#define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA__SHIFT 0xf
954#define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE__SHIFT 0x17
955#define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE__SHIFT 0x18
956#define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE__SHIFT 0x19
957#define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ__SHIFT 0x1a
958#define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ__SHIFT 0x1b
959#define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ__SHIFT 0x1c
960#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION__SHIFT 0x1d
961#define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV_MASK 0x00000001L
962#define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV_MASK 0x00000004L
963#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV_MASK 0x00000010L
964#define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG_MASK 0x00000400L
965#define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG_MASK 0x00000800L
966#define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM_MASK 0x00001000L
967#define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x00002000L
968#define CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA_MASK 0x00004000L
969#define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA_MASK 0x00008000L
970#define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE_MASK 0x00800000L
971#define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE_MASK 0x01000000L
972#define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE_MASK 0x02000000L
973#define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ_MASK 0x04000000L
974#define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ_MASK 0x08000000L
975#define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ_MASK 0x10000000L
976#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION_MASK 0x20000000L
977//CP_STALLED_STAT2
978#define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0
979#define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV__SHIFT 0x1
980#define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV__SHIFT 0x2
981#define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING__SHIFT 0x4
982#define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING__SHIFT 0x5
983#define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA__SHIFT 0x8
984#define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER__SHIFT 0x9
985#define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER__SHIFT 0xa
986#define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME__SHIFT 0xb
987#define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV__SHIFT 0xc
988#define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV__SHIFT 0xd
989#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP__SHIFT 0xe
990#define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH__SHIFT 0xf
991#define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x10
992#define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x11
993#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ__SHIFT 0x12
994#define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x13
995#define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x14
996#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE__SHIFT 0x15
997#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM__SHIFT 0x16
998#define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING__SHIFT 0x17
999#define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING__SHIFT 0x18
1000#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE__SHIFT 0x19
1001#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE__SHIFT 0x1a
1002#define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM__SHIFT 0x1b
1003#define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION__SHIFT 0x1c
1004#define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE__SHIFT 0x1d
1005#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS__SHIFT 0x1e
1006#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN__SHIFT 0x1f
1007#define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV_MASK 0x00000001L
1008#define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV_MASK 0x00000002L
1009#define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV_MASK 0x00000004L
1010#define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING_MASK 0x00000010L
1011#define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING_MASK 0x00000020L
1012#define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA_MASK 0x00000100L
1013#define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER_MASK 0x00000200L
1014#define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER_MASK 0x00000400L
1015#define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME_MASK 0x00000800L
1016#define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV_MASK 0x00001000L
1017#define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV_MASK 0x00002000L
1018#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP_MASK 0x00004000L
1019#define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH_MASK 0x00008000L
1020#define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x00010000L
1021#define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x00020000L
1022#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ_MASK 0x00040000L
1023#define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM_MASK 0x00080000L
1024#define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x00100000L
1025#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE_MASK 0x00200000L
1026#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM_MASK 0x00400000L
1027#define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING_MASK 0x00800000L
1028#define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING_MASK 0x01000000L
1029#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE_MASK 0x02000000L
1030#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE_MASK 0x04000000L
1031#define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM_MASK 0x08000000L
1032#define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION_MASK 0x10000000L
1033#define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE_MASK 0x20000000L
1034#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS_MASK 0x40000000L
1035#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN_MASK 0x80000000L
1036//CP_BUSY_STAT
1037#define CP_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x0
1038#define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO__SHIFT 0x6
1039#define CP_BUSY_STAT__PFP_PARSING_PACKETS__SHIFT 0x7
1040#define CP_BUSY_STAT__ME_PARSING_PACKETS__SHIFT 0x8
1041#define CP_BUSY_STAT__RCIU_PFP_BUSY__SHIFT 0x9
1042#define CP_BUSY_STAT__RCIU_ME_BUSY__SHIFT 0xa
1043#define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY__SHIFT 0xc
1044#define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING__SHIFT 0xd
1045#define CP_BUSY_STAT__SEM_POLLING_FOR_PASS__SHIFT 0xe
1046#define CP_BUSY_STAT__GFX_CONTEXT_BUSY__SHIFT 0xf
1047#define CP_BUSY_STAT__ME_PARSER_BUSY__SHIFT 0x11
1048#define CP_BUSY_STAT__EOP_DONE_BUSY__SHIFT 0x12
1049#define CP_BUSY_STAT__STRM_OUT_BUSY__SHIFT 0x13
1050#define CP_BUSY_STAT__PIPE_STATS_BUSY__SHIFT 0x14
1051#define CP_BUSY_STAT__RCIU_CE_BUSY__SHIFT 0x15
1052#define CP_BUSY_STAT__CE_PARSING_PACKETS__SHIFT 0x16
1053#define CP_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x00000001L
1054#define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO_MASK 0x00000040L
1055#define CP_BUSY_STAT__PFP_PARSING_PACKETS_MASK 0x00000080L
1056#define CP_BUSY_STAT__ME_PARSING_PACKETS_MASK 0x00000100L
1057#define CP_BUSY_STAT__RCIU_PFP_BUSY_MASK 0x00000200L
1058#define CP_BUSY_STAT__RCIU_ME_BUSY_MASK 0x00000400L
1059#define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY_MASK 0x00001000L
1060#define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING_MASK 0x00002000L
1061#define CP_BUSY_STAT__SEM_POLLING_FOR_PASS_MASK 0x00004000L
1062#define CP_BUSY_STAT__GFX_CONTEXT_BUSY_MASK 0x00008000L
1063#define CP_BUSY_STAT__ME_PARSER_BUSY_MASK 0x00020000L
1064#define CP_BUSY_STAT__EOP_DONE_BUSY_MASK 0x00040000L
1065#define CP_BUSY_STAT__STRM_OUT_BUSY_MASK 0x00080000L
1066#define CP_BUSY_STAT__PIPE_STATS_BUSY_MASK 0x00100000L
1067#define CP_BUSY_STAT__RCIU_CE_BUSY_MASK 0x00200000L
1068#define CP_BUSY_STAT__CE_PARSING_PACKETS_MASK 0x00400000L
1069//CP_STAT
1070#define CP_STAT__ROQ_RING_BUSY__SHIFT 0x9
1071#define CP_STAT__ROQ_INDIRECT1_BUSY__SHIFT 0xa
1072#define CP_STAT__ROQ_INDIRECT2_BUSY__SHIFT 0xb
1073#define CP_STAT__ROQ_STATE_BUSY__SHIFT 0xc
1074#define CP_STAT__DC_BUSY__SHIFT 0xd
1075#define CP_STAT__UTCL2IU_BUSY__SHIFT 0xe
1076#define CP_STAT__PFP_BUSY__SHIFT 0xf
1077#define CP_STAT__MEQ_BUSY__SHIFT 0x10
1078#define CP_STAT__ME_BUSY__SHIFT 0x11
1079#define CP_STAT__QUERY_BUSY__SHIFT 0x12
1080#define CP_STAT__SEMAPHORE_BUSY__SHIFT 0x13
1081#define CP_STAT__INTERRUPT_BUSY__SHIFT 0x14
1082#define CP_STAT__SURFACE_SYNC_BUSY__SHIFT 0x15
1083#define CP_STAT__DMA_BUSY__SHIFT 0x16
1084#define CP_STAT__RCIU_BUSY__SHIFT 0x17
1085#define CP_STAT__SCRATCH_RAM_BUSY__SHIFT 0x18
1086#define CP_STAT__CE_BUSY__SHIFT 0x1a
1087#define CP_STAT__TCIU_BUSY__SHIFT 0x1b
1088#define CP_STAT__ROQ_CE_RING_BUSY__SHIFT 0x1c
1089#define CP_STAT__ROQ_CE_INDIRECT1_BUSY__SHIFT 0x1d
1090#define CP_STAT__ROQ_CE_INDIRECT2_BUSY__SHIFT 0x1e
1091#define CP_STAT__CP_BUSY__SHIFT 0x1f
1092#define CP_STAT__ROQ_RING_BUSY_MASK 0x00000200L
1093#define CP_STAT__ROQ_INDIRECT1_BUSY_MASK 0x00000400L
1094#define CP_STAT__ROQ_INDIRECT2_BUSY_MASK 0x00000800L
1095#define CP_STAT__ROQ_STATE_BUSY_MASK 0x00001000L
1096#define CP_STAT__DC_BUSY_MASK 0x00002000L
1097#define CP_STAT__UTCL2IU_BUSY_MASK 0x00004000L
1098#define CP_STAT__PFP_BUSY_MASK 0x00008000L
1099#define CP_STAT__MEQ_BUSY_MASK 0x00010000L
1100#define CP_STAT__ME_BUSY_MASK 0x00020000L
1101#define CP_STAT__QUERY_BUSY_MASK 0x00040000L
1102#define CP_STAT__SEMAPHORE_BUSY_MASK 0x00080000L
1103#define CP_STAT__INTERRUPT_BUSY_MASK 0x00100000L
1104#define CP_STAT__SURFACE_SYNC_BUSY_MASK 0x00200000L
1105#define CP_STAT__DMA_BUSY_MASK 0x00400000L
1106#define CP_STAT__RCIU_BUSY_MASK 0x00800000L
1107#define CP_STAT__SCRATCH_RAM_BUSY_MASK 0x01000000L
1108#define CP_STAT__CE_BUSY_MASK 0x04000000L
1109#define CP_STAT__TCIU_BUSY_MASK 0x08000000L
1110#define CP_STAT__ROQ_CE_RING_BUSY_MASK 0x10000000L
1111#define CP_STAT__ROQ_CE_INDIRECT1_BUSY_MASK 0x20000000L
1112#define CP_STAT__ROQ_CE_INDIRECT2_BUSY_MASK 0x40000000L
1113#define CP_STAT__CP_BUSY_MASK 0x80000000L
1114//CP_ME_HEADER_DUMP
1115#define CP_ME_HEADER_DUMP__ME_HEADER_DUMP__SHIFT 0x0
1116#define CP_ME_HEADER_DUMP__ME_HEADER_DUMP_MASK 0xFFFFFFFFL
1117//CP_PFP_HEADER_DUMP
1118#define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP__SHIFT 0x0
1119#define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP_MASK 0xFFFFFFFFL
1120//CP_GRBM_FREE_COUNT
1121#define CP_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0
1122#define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS__SHIFT 0x8
1123#define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP__SHIFT 0x10
1124#define CP_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x0000003FL
1125#define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS_MASK 0x00003F00L
1126#define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP_MASK 0x003F0000L
1127//CP_CE_HEADER_DUMP
1128#define CP_CE_HEADER_DUMP__CE_HEADER_DUMP__SHIFT 0x0
1129#define CP_CE_HEADER_DUMP__CE_HEADER_DUMP_MASK 0xFFFFFFFFL
1130//CP_PFP_INSTR_PNTR
1131#define CP_PFP_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0
1132#define CP_PFP_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL
1133//CP_ME_INSTR_PNTR
1134#define CP_ME_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0
1135#define CP_ME_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL
1136//CP_CE_INSTR_PNTR
1137#define CP_CE_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0
1138#define CP_CE_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL
1139//CP_MEC1_INSTR_PNTR
1140#define CP_MEC1_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0
1141#define CP_MEC1_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL
1142//CP_MEC2_INSTR_PNTR
1143#define CP_MEC2_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0
1144#define CP_MEC2_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL
1145//CP_CSF_STAT
1146#define CP_CSF_STAT__BUFFER_REQUEST_COUNT__SHIFT 0x8
1147#define CP_CSF_STAT__BUFFER_REQUEST_COUNT_MASK 0x0001FF00L
1148//CP_ME_CNTL
1149#define CP_ME_CNTL__CE_INVALIDATE_ICACHE__SHIFT 0x4
1150#define CP_ME_CNTL__PFP_INVALIDATE_ICACHE__SHIFT 0x6
1151#define CP_ME_CNTL__ME_INVALIDATE_ICACHE__SHIFT 0x8
1152#define CP_ME_CNTL__CE_PIPE0_RESET__SHIFT 0x10
1153#define CP_ME_CNTL__CE_PIPE1_RESET__SHIFT 0x11
1154#define CP_ME_CNTL__PFP_PIPE0_RESET__SHIFT 0x12
1155#define CP_ME_CNTL__PFP_PIPE1_RESET__SHIFT 0x13
1156#define CP_ME_CNTL__ME_PIPE0_RESET__SHIFT 0x14
1157#define CP_ME_CNTL__ME_PIPE1_RESET__SHIFT 0x15
1158#define CP_ME_CNTL__CE_HALT__SHIFT 0x18
1159#define CP_ME_CNTL__CE_STEP__SHIFT 0x19
1160#define CP_ME_CNTL__PFP_HALT__SHIFT 0x1a
1161#define CP_ME_CNTL__PFP_STEP__SHIFT 0x1b
1162#define CP_ME_CNTL__ME_HALT__SHIFT 0x1c
1163#define CP_ME_CNTL__ME_STEP__SHIFT 0x1d
1164#define CP_ME_CNTL__CE_INVALIDATE_ICACHE_MASK 0x00000010L
1165#define CP_ME_CNTL__PFP_INVALIDATE_ICACHE_MASK 0x00000040L
1166#define CP_ME_CNTL__ME_INVALIDATE_ICACHE_MASK 0x00000100L
1167#define CP_ME_CNTL__CE_PIPE0_RESET_MASK 0x00010000L
1168#define CP_ME_CNTL__CE_PIPE1_RESET_MASK 0x00020000L
1169#define CP_ME_CNTL__PFP_PIPE0_RESET_MASK 0x00040000L
1170#define CP_ME_CNTL__PFP_PIPE1_RESET_MASK 0x00080000L
1171#define CP_ME_CNTL__ME_PIPE0_RESET_MASK 0x00100000L
1172#define CP_ME_CNTL__ME_PIPE1_RESET_MASK 0x00200000L
1173#define CP_ME_CNTL__CE_HALT_MASK 0x01000000L
1174#define CP_ME_CNTL__CE_STEP_MASK 0x02000000L
1175#define CP_ME_CNTL__PFP_HALT_MASK 0x04000000L
1176#define CP_ME_CNTL__PFP_STEP_MASK 0x08000000L
1177#define CP_ME_CNTL__ME_HALT_MASK 0x10000000L
1178#define CP_ME_CNTL__ME_STEP_MASK 0x20000000L
1179//CP_CNTX_STAT
1180#define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS__SHIFT 0x0
1181#define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT__SHIFT 0x8
1182#define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS__SHIFT 0x14
1183#define CP_CNTX_STAT__CURRENT_GFX_CONTEXT__SHIFT 0x1c
1184#define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS_MASK 0x000000FFL
1185#define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT_MASK 0x00000700L
1186#define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS_MASK 0x0FF00000L
1187#define CP_CNTX_STAT__CURRENT_GFX_CONTEXT_MASK 0x70000000L
1188//CP_ME_PREEMPTION
1189#define CP_ME_PREEMPTION__OBSOLETE__SHIFT 0x0
1190#define CP_ME_PREEMPTION__OBSOLETE_MASK 0x00000001L
1191//CP_ROQ_THRESHOLDS
1192#define CP_ROQ_THRESHOLDS__IB1_START__SHIFT 0x0
1193#define CP_ROQ_THRESHOLDS__IB2_START__SHIFT 0x8
1194#define CP_ROQ_THRESHOLDS__IB1_START_MASK 0x000000FFL
1195#define CP_ROQ_THRESHOLDS__IB2_START_MASK 0x0000FF00L
1196//CP_MEQ_STQ_THRESHOLD
1197#define CP_MEQ_STQ_THRESHOLD__STQ_START__SHIFT 0x0
1198#define CP_MEQ_STQ_THRESHOLD__STQ_START_MASK 0x000000FFL
1199//CP_RB2_RPTR
1200#define CP_RB2_RPTR__RB_RPTR__SHIFT 0x0
1201#define CP_RB2_RPTR__RB_RPTR_MASK 0x000FFFFFL
1202//CP_RB1_RPTR
1203#define CP_RB1_RPTR__RB_RPTR__SHIFT 0x0
1204#define CP_RB1_RPTR__RB_RPTR_MASK 0x000FFFFFL
1205//CP_RB0_RPTR
1206#define CP_RB0_RPTR__RB_RPTR__SHIFT 0x0
1207#define CP_RB0_RPTR__RB_RPTR_MASK 0x000FFFFFL
1208//CP_RB_RPTR
1209#define CP_RB_RPTR__RB_RPTR__SHIFT 0x0
1210#define CP_RB_RPTR__RB_RPTR_MASK 0x000FFFFFL
1211//CP_RB_WPTR_DELAY
1212#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER__SHIFT 0x0
1213#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT__SHIFT 0x1c
1214#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER_MASK 0x0FFFFFFFL
1215#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT_MASK 0xF0000000L
1216//CP_RB_WPTR_POLL_CNTL
1217#define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT 0x0
1218#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
1219#define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK 0x0000FFFFL
1220#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L
1221//CP_ROQ1_THRESHOLDS
1222#define CP_ROQ1_THRESHOLDS__RB1_START__SHIFT 0x0
1223#define CP_ROQ1_THRESHOLDS__RB2_START__SHIFT 0x8
1224#define CP_ROQ1_THRESHOLDS__R0_IB1_START__SHIFT 0x10
1225#define CP_ROQ1_THRESHOLDS__R1_IB1_START__SHIFT 0x18
1226#define CP_ROQ1_THRESHOLDS__RB1_START_MASK 0x000000FFL
1227#define CP_ROQ1_THRESHOLDS__RB2_START_MASK 0x0000FF00L
1228#define CP_ROQ1_THRESHOLDS__R0_IB1_START_MASK 0x00FF0000L
1229#define CP_ROQ1_THRESHOLDS__R1_IB1_START_MASK 0xFF000000L
1230//CP_ROQ2_THRESHOLDS
1231#define CP_ROQ2_THRESHOLDS__R2_IB1_START__SHIFT 0x0
1232#define CP_ROQ2_THRESHOLDS__R0_IB2_START__SHIFT 0x8
1233#define CP_ROQ2_THRESHOLDS__R1_IB2_START__SHIFT 0x10
1234#define CP_ROQ2_THRESHOLDS__R2_IB2_START__SHIFT 0x18
1235#define CP_ROQ2_THRESHOLDS__R2_IB1_START_MASK 0x000000FFL
1236#define CP_ROQ2_THRESHOLDS__R0_IB2_START_MASK 0x0000FF00L
1237#define CP_ROQ2_THRESHOLDS__R1_IB2_START_MASK 0x00FF0000L
1238#define CP_ROQ2_THRESHOLDS__R2_IB2_START_MASK 0xFF000000L
1239//CP_STQ_THRESHOLDS
1240#define CP_STQ_THRESHOLDS__STQ0_START__SHIFT 0x0
1241#define CP_STQ_THRESHOLDS__STQ1_START__SHIFT 0x8
1242#define CP_STQ_THRESHOLDS__STQ2_START__SHIFT 0x10
1243#define CP_STQ_THRESHOLDS__STQ0_START_MASK 0x000000FFL
1244#define CP_STQ_THRESHOLDS__STQ1_START_MASK 0x0000FF00L
1245#define CP_STQ_THRESHOLDS__STQ2_START_MASK 0x00FF0000L
1246//CP_QUEUE_THRESHOLDS
1247#define CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT 0x0
1248#define CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT 0x8
1249#define CP_QUEUE_THRESHOLDS__ROQ_IB1_START_MASK 0x0000003FL
1250#define CP_QUEUE_THRESHOLDS__ROQ_IB2_START_MASK 0x00003F00L
1251//CP_MEQ_THRESHOLDS
1252#define CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT 0x0
1253#define CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT 0x8
1254#define CP_MEQ_THRESHOLDS__MEQ1_START_MASK 0x000000FFL
1255#define CP_MEQ_THRESHOLDS__MEQ2_START_MASK 0x0000FF00L
1256//CP_ROQ_AVAIL
1257#define CP_ROQ_AVAIL__ROQ_CNT_RING__SHIFT 0x0
1258#define CP_ROQ_AVAIL__ROQ_CNT_IB1__SHIFT 0x10
1259#define CP_ROQ_AVAIL__ROQ_CNT_RING_MASK 0x000007FFL
1260#define CP_ROQ_AVAIL__ROQ_CNT_IB1_MASK 0x07FF0000L
1261//CP_STQ_AVAIL
1262#define CP_STQ_AVAIL__STQ_CNT__SHIFT 0x0
1263#define CP_STQ_AVAIL__STQ_CNT_MASK 0x000001FFL
1264//CP_ROQ2_AVAIL
1265#define CP_ROQ2_AVAIL__ROQ_CNT_IB2__SHIFT 0x0
1266#define CP_ROQ2_AVAIL__ROQ_CNT_IB2_MASK 0x000007FFL
1267//CP_MEQ_AVAIL
1268#define CP_MEQ_AVAIL__MEQ_CNT__SHIFT 0x0
1269#define CP_MEQ_AVAIL__MEQ_CNT_MASK 0x000003FFL
1270//CP_CMD_INDEX
1271#define CP_CMD_INDEX__CMD_INDEX__SHIFT 0x0
1272#define CP_CMD_INDEX__CMD_ME_SEL__SHIFT 0xc
1273#define CP_CMD_INDEX__CMD_QUEUE_SEL__SHIFT 0x10
1274#define CP_CMD_INDEX__CMD_INDEX_MASK 0x000007FFL
1275#define CP_CMD_INDEX__CMD_ME_SEL_MASK 0x00003000L
1276#define CP_CMD_INDEX__CMD_QUEUE_SEL_MASK 0x00070000L
1277//CP_CMD_DATA
1278#define CP_CMD_DATA__CMD_DATA__SHIFT 0x0
1279#define CP_CMD_DATA__CMD_DATA_MASK 0xFFFFFFFFL
1280//CP_ROQ_RB_STAT
1281#define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY__SHIFT 0x0
1282#define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY__SHIFT 0x10
1283#define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY_MASK 0x000003FFL
1284#define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY_MASK 0x03FF0000L
1285//CP_ROQ_IB1_STAT
1286#define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1__SHIFT 0x0
1287#define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1__SHIFT 0x10
1288#define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1_MASK 0x000003FFL
1289#define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1_MASK 0x03FF0000L
1290//CP_ROQ_IB2_STAT
1291#define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2__SHIFT 0x0
1292#define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2__SHIFT 0x10
1293#define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2_MASK 0x000003FFL
1294#define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2_MASK 0x03FF0000L
1295//CP_STQ_STAT
1296#define CP_STQ_STAT__STQ_RPTR__SHIFT 0x0
1297#define CP_STQ_STAT__STQ_RPTR_MASK 0x000003FFL
1298//CP_STQ_WR_STAT
1299#define CP_STQ_WR_STAT__STQ_WPTR__SHIFT 0x0
1300#define CP_STQ_WR_STAT__STQ_WPTR_MASK 0x000003FFL
1301//CP_MEQ_STAT
1302#define CP_MEQ_STAT__MEQ_RPTR__SHIFT 0x0
1303#define CP_MEQ_STAT__MEQ_WPTR__SHIFT 0x10
1304#define CP_MEQ_STAT__MEQ_RPTR_MASK 0x000003FFL
1305#define CP_MEQ_STAT__MEQ_WPTR_MASK 0x03FF0000L
1306//CP_CEQ1_AVAIL
1307#define CP_CEQ1_AVAIL__CEQ_CNT_RING__SHIFT 0x0
1308#define CP_CEQ1_AVAIL__CEQ_CNT_IB1__SHIFT 0x10
1309#define CP_CEQ1_AVAIL__CEQ_CNT_RING_MASK 0x000007FFL
1310#define CP_CEQ1_AVAIL__CEQ_CNT_IB1_MASK 0x07FF0000L
1311//CP_CEQ2_AVAIL
1312#define CP_CEQ2_AVAIL__CEQ_CNT_IB2__SHIFT 0x0
1313#define CP_CEQ2_AVAIL__CEQ_CNT_IB2_MASK 0x000007FFL
1314//CP_CE_ROQ_RB_STAT
1315#define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY__SHIFT 0x0
1316#define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY__SHIFT 0x10
1317#define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY_MASK 0x000003FFL
1318#define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY_MASK 0x03FF0000L
1319//CP_CE_ROQ_IB1_STAT
1320#define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1__SHIFT 0x0
1321#define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1__SHIFT 0x10
1322#define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1_MASK 0x000003FFL
1323#define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1_MASK 0x03FF0000L
1324//CP_CE_ROQ_IB2_STAT
1325#define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2__SHIFT 0x0
1326#define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2__SHIFT 0x10
1327#define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2_MASK 0x000003FFL
1328#define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2_MASK 0x03FF0000L
1329//CP_INT_STAT_DEBUG
1330#define CP_INT_STAT_DEBUG__CP_VM_DOORBELL_WR_INT_ASSERTED__SHIFT 0xb
1331#define CP_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0xe
1332#define CP_INT_STAT_DEBUG__GPF_INT_ASSERTED__SHIFT 0x10
1333#define CP_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x11
1334#define CP_INT_STAT_DEBUG__CMP_BUSY_INT_ASSERTED__SHIFT 0x12
1335#define CP_INT_STAT_DEBUG__CNTX_BUSY_INT_ASSERTED__SHIFT 0x13
1336#define CP_INT_STAT_DEBUG__CNTX_EMPTY_INT_ASSERTED__SHIFT 0x14
1337#define CP_INT_STAT_DEBUG__GFX_IDLE_INT_ASSERTED__SHIFT 0x15
1338#define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED__SHIFT 0x16
1339#define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17
1340#define CP_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x18
1341#define CP_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x1a
1342#define CP_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x1b
1343#define CP_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d
1344#define CP_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x1e
1345#define CP_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x1f
1346#define CP_INT_STAT_DEBUG__CP_VM_DOORBELL_WR_INT_ASSERTED_MASK 0x00000800L
1347#define CP_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x00004000L
1348#define CP_INT_STAT_DEBUG__GPF_INT_ASSERTED_MASK 0x00010000L
1349#define CP_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x00020000L
1350#define CP_INT_STAT_DEBUG__CMP_BUSY_INT_ASSERTED_MASK 0x00040000L
1351#define CP_INT_STAT_DEBUG__CNTX_BUSY_INT_ASSERTED_MASK 0x00080000L
1352#define CP_INT_STAT_DEBUG__CNTX_EMPTY_INT_ASSERTED_MASK 0x00100000L
1353#define CP_INT_STAT_DEBUG__GFX_IDLE_INT_ASSERTED_MASK 0x00200000L
1354#define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED_MASK 0x00400000L
1355#define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x00800000L
1356#define CP_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x01000000L
1357#define CP_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x04000000L
1358#define CP_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x08000000L
1359#define CP_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000L
1360#define CP_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000L
1361#define CP_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000L
1362
1363
1364// addressBlock: gc_padec
1365//VGT_VTX_VECT_EJECT_REG
1366#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT__SHIFT 0x0
1367#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT_MASK 0x0000007FL
1368//VGT_DMA_DATA_FIFO_DEPTH
1369#define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH__SHIFT 0x0
1370#define VGT_DMA_DATA_FIFO_DEPTH__DMA2DRAW_FIFO_DEPTH__SHIFT 0x9
1371#define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH_MASK 0x000001FFL
1372#define VGT_DMA_DATA_FIFO_DEPTH__DMA2DRAW_FIFO_DEPTH_MASK 0x0007FE00L
1373//VGT_DMA_REQ_FIFO_DEPTH
1374#define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH__SHIFT 0x0
1375#define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH_MASK 0x0000003FL
1376//VGT_DRAW_INIT_FIFO_DEPTH
1377#define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH__SHIFT 0x0
1378#define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH_MASK 0x0000003FL
1379//VGT_LAST_COPY_STATE
1380#define VGT_LAST_COPY_STATE__SRC_STATE_ID__SHIFT 0x0
1381#define VGT_LAST_COPY_STATE__DST_STATE_ID__SHIFT 0x10
1382#define VGT_LAST_COPY_STATE__SRC_STATE_ID_MASK 0x00000007L
1383#define VGT_LAST_COPY_STATE__DST_STATE_ID_MASK 0x00070000L
1384//VGT_CACHE_INVALIDATION
1385#define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT 0x0
1386#define VGT_CACHE_INVALIDATION__DIS_INSTANCING_OPT__SHIFT 0x4
1387#define VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER__SHIFT 0x5
1388#define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT 0x6
1389#define VGT_CACHE_INVALIDATION__USE_GS_DONE__SHIFT 0x9
1390#define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD__SHIFT 0xb
1391#define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN__SHIFT 0xc
1392#define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH__SHIFT 0xd
1393#define VGT_CACHE_INVALIDATION__ES_LIMIT__SHIFT 0x10
1394#define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG__SHIFT 0x15
1395#define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_1__SHIFT 0x16
1396#define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_2__SHIFT 0x19
1397#define VGT_CACHE_INVALIDATION__EN_WAVE_MERGE__SHIFT 0x1c
1398#define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG_EOI__SHIFT 0x1d
1399#define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION_MASK 0x00000003L
1400#define VGT_CACHE_INVALIDATION__DIS_INSTANCING_OPT_MASK 0x00000010L
1401#define VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER_MASK 0x00000020L
1402#define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN_MASK 0x000000C0L
1403#define VGT_CACHE_INVALIDATION__USE_GS_DONE_MASK 0x00000200L
1404#define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD_MASK 0x00000800L
1405#define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN_MASK 0x00001000L
1406#define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH_MASK 0x00002000L
1407#define VGT_CACHE_INVALIDATION__ES_LIMIT_MASK 0x001F0000L
1408#define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG_MASK 0x00200000L
1409#define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_1_MASK 0x01C00000L
1410#define VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_2_MASK 0x0E000000L
1411#define VGT_CACHE_INVALIDATION__EN_WAVE_MERGE_MASK 0x10000000L
1412#define VGT_CACHE_INVALIDATION__ENABLE_PING_PONG_EOI_MASK 0x20000000L
1413//VGT_RESET_DEBUG
1414#define VGT_RESET_DEBUG__GS_DISABLE__SHIFT 0x0
1415#define VGT_RESET_DEBUG__TESS_DISABLE__SHIFT 0x1
1416#define VGT_RESET_DEBUG__WD_DISABLE__SHIFT 0x2
1417#define VGT_RESET_DEBUG__GS_DISABLE_MASK 0x00000001L
1418#define VGT_RESET_DEBUG__TESS_DISABLE_MASK 0x00000002L
1419#define VGT_RESET_DEBUG__WD_DISABLE_MASK 0x00000004L
1420//VGT_STRMOUT_DELAY
1421#define VGT_STRMOUT_DELAY__SKIP_DELAY__SHIFT 0x0
1422#define VGT_STRMOUT_DELAY__SE0_WD_DELAY__SHIFT 0x8
1423#define VGT_STRMOUT_DELAY__SE1_WD_DELAY__SHIFT 0xb
1424#define VGT_STRMOUT_DELAY__SE2_WD_DELAY__SHIFT 0xe
1425#define VGT_STRMOUT_DELAY__SE3_WD_DELAY__SHIFT 0x11
1426#define VGT_STRMOUT_DELAY__SKIP_DELAY_MASK 0x000000FFL
1427#define VGT_STRMOUT_DELAY__SE0_WD_DELAY_MASK 0x00000700L
1428#define VGT_STRMOUT_DELAY__SE1_WD_DELAY_MASK 0x00003800L
1429#define VGT_STRMOUT_DELAY__SE2_WD_DELAY_MASK 0x0001C000L
1430#define VGT_STRMOUT_DELAY__SE3_WD_DELAY_MASK 0x000E0000L
1431//VGT_FIFO_DEPTHS
1432#define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH__SHIFT 0x0
1433#define VGT_FIFO_DEPTHS__RESERVED_0__SHIFT 0x7
1434#define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH__SHIFT 0x8
1435#define VGT_FIFO_DEPTHS__HSINPUT_FIFO_DEPTH__SHIFT 0x16
1436#define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH_MASK 0x0000007FL
1437#define VGT_FIFO_DEPTHS__RESERVED_0_MASK 0x00000080L
1438#define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH_MASK 0x003FFF00L
1439#define VGT_FIFO_DEPTHS__HSINPUT_FIFO_DEPTH_MASK 0x0FC00000L
1440//VGT_GS_VERTEX_REUSE
1441#define VGT_GS_VERTEX_REUSE__VERT_REUSE__SHIFT 0x0
1442#define VGT_GS_VERTEX_REUSE__VERT_REUSE_MASK 0x0000001FL
1443//VGT_MC_LAT_CNTL
1444#define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES__SHIFT 0x0
1445#define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES_MASK 0x0000000FL
1446//IA_CNTL_STATUS
1447#define IA_CNTL_STATUS__IA_BUSY__SHIFT 0x0
1448#define IA_CNTL_STATUS__IA_DMA_BUSY__SHIFT 0x1
1449#define IA_CNTL_STATUS__IA_DMA_REQ_BUSY__SHIFT 0x2
1450#define IA_CNTL_STATUS__IA_GRP_BUSY__SHIFT 0x3
1451#define IA_CNTL_STATUS__IA_ADC_BUSY__SHIFT 0x4
1452#define IA_CNTL_STATUS__IA_BUSY_MASK 0x00000001L
1453#define IA_CNTL_STATUS__IA_DMA_BUSY_MASK 0x00000002L
1454#define IA_CNTL_STATUS__IA_DMA_REQ_BUSY_MASK 0x00000004L
1455#define IA_CNTL_STATUS__IA_GRP_BUSY_MASK 0x00000008L
1456#define IA_CNTL_STATUS__IA_ADC_BUSY_MASK 0x00000010L
1457//VGT_CNTL_STATUS
1458#define VGT_CNTL_STATUS__VGT_BUSY__SHIFT 0x0
1459#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY__SHIFT 0x1
1460#define VGT_CNTL_STATUS__VGT_OUT_BUSY__SHIFT 0x2
1461#define VGT_CNTL_STATUS__VGT_PT_BUSY__SHIFT 0x3
1462#define VGT_CNTL_STATUS__VGT_TE_BUSY__SHIFT 0x4
1463#define VGT_CNTL_STATUS__VGT_VR_BUSY__SHIFT 0x5
1464#define VGT_CNTL_STATUS__VGT_PI_BUSY__SHIFT 0x6
1465#define VGT_CNTL_STATUS__VGT_GS_BUSY__SHIFT 0x7
1466#define VGT_CNTL_STATUS__VGT_HS_BUSY__SHIFT 0x8
1467#define VGT_CNTL_STATUS__VGT_TE11_BUSY__SHIFT 0x9
1468#define VGT_CNTL_STATUS__VGT_PRIMGEN_BUSY__SHIFT 0xa
1469#define VGT_CNTL_STATUS__VGT_BUSY_MASK 0x00000001L
1470#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY_MASK 0x00000002L
1471#define VGT_CNTL_STATUS__VGT_OUT_BUSY_MASK 0x00000004L
1472#define VGT_CNTL_STATUS__VGT_PT_BUSY_MASK 0x00000008L
1473#define VGT_CNTL_STATUS__VGT_TE_BUSY_MASK 0x00000010L
1474#define VGT_CNTL_STATUS__VGT_VR_BUSY_MASK 0x00000020L
1475#define VGT_CNTL_STATUS__VGT_PI_BUSY_MASK 0x00000040L
1476#define VGT_CNTL_STATUS__VGT_GS_BUSY_MASK 0x00000080L
1477#define VGT_CNTL_STATUS__VGT_HS_BUSY_MASK 0x00000100L
1478#define VGT_CNTL_STATUS__VGT_TE11_BUSY_MASK 0x00000200L
1479#define VGT_CNTL_STATUS__VGT_PRIMGEN_BUSY_MASK 0x00000400L
1480//WD_CNTL_STATUS
1481#define WD_CNTL_STATUS__WD_BUSY__SHIFT 0x0
1482#define WD_CNTL_STATUS__WD_SPL_DMA_BUSY__SHIFT 0x1
1483#define WD_CNTL_STATUS__WD_SPL_DI_BUSY__SHIFT 0x2
1484#define WD_CNTL_STATUS__WD_ADC_BUSY__SHIFT 0x3
1485#define WD_CNTL_STATUS__WD_BUSY_MASK 0x00000001L
1486#define WD_CNTL_STATUS__WD_SPL_DMA_BUSY_MASK 0x00000002L
1487#define WD_CNTL_STATUS__WD_SPL_DI_BUSY_MASK 0x00000004L
1488#define WD_CNTL_STATUS__WD_ADC_BUSY_MASK 0x00000008L
1489//CC_GC_PRIM_CONFIG
1490#define CC_GC_PRIM_CONFIG__INACTIVE_IA__SHIFT 0x10
1491#define CC_GC_PRIM_CONFIG__INACTIVE_VGT_PA__SHIFT 0x18
1492#define CC_GC_PRIM_CONFIG__INACTIVE_IA_MASK 0x00030000L
1493#define CC_GC_PRIM_CONFIG__INACTIVE_VGT_PA_MASK 0x0F000000L
1494//GC_USER_PRIM_CONFIG
1495#define GC_USER_PRIM_CONFIG__INACTIVE_IA__SHIFT 0x10
1496#define GC_USER_PRIM_CONFIG__INACTIVE_VGT_PA__SHIFT 0x18
1497#define GC_USER_PRIM_CONFIG__INACTIVE_IA_MASK 0x00030000L
1498#define GC_USER_PRIM_CONFIG__INACTIVE_VGT_PA_MASK 0x0F000000L
1499//WD_QOS
1500#define WD_QOS__DRAW_STALL__SHIFT 0x0
1501#define WD_QOS__DRAW_STALL_MASK 0x00000001L
1502//WD_UTCL1_CNTL
1503#define WD_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0
1504#define WD_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x17
1505#define WD_UTCL1_CNTL__DROP_MODE__SHIFT 0x18
1506#define WD_UTCL1_CNTL__BYPASS__SHIFT 0x19
1507#define WD_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a
1508#define WD_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b
1509#define WD_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c
1510#define WD_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d
1511#define WD_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL
1512#define WD_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L
1513#define WD_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L
1514#define WD_UTCL1_CNTL__BYPASS_MASK 0x02000000L
1515#define WD_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L
1516#define WD_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L
1517#define WD_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L
1518#define WD_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L
1519//WD_UTCL1_STATUS
1520#define WD_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0
1521#define WD_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1
1522#define WD_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2
1523#define WD_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8
1524#define WD_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10
1525#define WD_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18
1526#define WD_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L
1527#define WD_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L
1528#define WD_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L
1529#define WD_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L
1530#define WD_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L
1531#define WD_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L
1532//IA_UTCL1_CNTL
1533#define IA_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0
1534#define IA_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x17
1535#define IA_UTCL1_CNTL__DROP_MODE__SHIFT 0x18
1536#define IA_UTCL1_CNTL__BYPASS__SHIFT 0x19
1537#define IA_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a
1538#define IA_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b
1539#define IA_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c
1540#define IA_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT 0x1d
1541#define IA_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL
1542#define IA_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L
1543#define IA_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L
1544#define IA_UTCL1_CNTL__BYPASS_MASK 0x02000000L
1545#define IA_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L
1546#define IA_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L
1547#define IA_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L
1548#define IA_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK 0x20000000L
1549//IA_UTCL1_STATUS
1550#define IA_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0
1551#define IA_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1
1552#define IA_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2
1553#define IA_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8
1554#define IA_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10
1555#define IA_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18
1556#define IA_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L
1557#define IA_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L
1558#define IA_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L
1559#define IA_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L
1560#define IA_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L
1561#define IA_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L
1562//VGT_SYS_CONFIG
1563#define VGT_SYS_CONFIG__DUAL_CORE_EN__SHIFT 0x0
1564#define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP__SHIFT 0x1
1565#define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE__SHIFT 0x7
1566#define VGT_SYS_CONFIG__DUAL_CORE_EN_MASK 0x00000001L
1567#define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP_MASK 0x0000007EL
1568#define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE_MASK 0x00000080L
1569//VGT_VS_MAX_WAVE_ID
1570#define VGT_VS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0
1571#define VGT_VS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000FFFL
1572//VGT_GS_MAX_WAVE_ID
1573#define VGT_GS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0
1574#define VGT_GS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000FFFL
1575//GFX_PIPE_CONTROL
1576#define GFX_PIPE_CONTROL__HYSTERESIS_CNT__SHIFT 0x0
1577#define GFX_PIPE_CONTROL__RESERVED__SHIFT 0xd
1578#define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN__SHIFT 0x10
1579#define GFX_PIPE_CONTROL__HYSTERESIS_CNT_MASK 0x00001FFFL
1580#define GFX_PIPE_CONTROL__RESERVED_MASK 0x0000E000L
1581#define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN_MASK 0x00010000L
1582//CC_GC_SHADER_ARRAY_CONFIG
1583#define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT 0x10
1584#define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK 0xFFFF0000L
1585//GC_USER_SHADER_ARRAY_CONFIG
1586#define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT 0x10
1587#define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK 0xFFFF0000L
1588//VGT_DMA_PRIMITIVE_TYPE
1589#define VGT_DMA_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT 0x0
1590#define VGT_DMA_PRIMITIVE_TYPE__PRIM_TYPE_MASK 0x0000003FL
1591//VGT_DMA_CONTROL
1592#define VGT_DMA_CONTROL__PRIMGROUP_SIZE__SHIFT 0x0
1593#define VGT_DMA_CONTROL__IA_SWITCH_ON_EOP__SHIFT 0x11
1594#define VGT_DMA_CONTROL__SWITCH_ON_EOI__SHIFT 0x13
1595#define VGT_DMA_CONTROL__WD_SWITCH_ON_EOP__SHIFT 0x14
1596#define VGT_DMA_CONTROL__EN_INST_OPT_BASIC__SHIFT 0x15
1597#define VGT_DMA_CONTROL__EN_INST_OPT_ADV__SHIFT 0x16
1598#define VGT_DMA_CONTROL__HW_USE_ONLY__SHIFT 0x17
1599#define VGT_DMA_CONTROL__PRIMGROUP_SIZE_MASK 0x0000FFFFL
1600#define VGT_DMA_CONTROL__IA_SWITCH_ON_EOP_MASK 0x00020000L
1601#define VGT_DMA_CONTROL__SWITCH_ON_EOI_MASK 0x00080000L
1602#define VGT_DMA_CONTROL__WD_SWITCH_ON_EOP_MASK 0x00100000L
1603#define VGT_DMA_CONTROL__EN_INST_OPT_BASIC_MASK 0x00200000L
1604#define VGT_DMA_CONTROL__EN_INST_OPT_ADV_MASK 0x00400000L
1605#define VGT_DMA_CONTROL__HW_USE_ONLY_MASK 0x00800000L
1606//VGT_DMA_LS_HS_CONFIG
1607#define VGT_DMA_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT 0x8
1608#define VGT_DMA_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK 0x00003F00L
1609//WD_BUF_RESOURCE_1
1610#define WD_BUF_RESOURCE_1__POS_BUF_SIZE__SHIFT 0x0
1611#define WD_BUF_RESOURCE_1__INDEX_BUF_SIZE__SHIFT 0x10
1612#define WD_BUF_RESOURCE_1__POS_BUF_SIZE_MASK 0x0000FFFFL
1613#define WD_BUF_RESOURCE_1__INDEX_BUF_SIZE_MASK 0xFFFF0000L
1614//WD_BUF_RESOURCE_2
1615#define WD_BUF_RESOURCE_2__PARAM_BUF_SIZE__SHIFT 0x0
1616#define WD_BUF_RESOURCE_2__ADDR_MODE__SHIFT 0xf
1617#define WD_BUF_RESOURCE_2__CNTL_SB_BUF_SIZE__SHIFT 0x10
1618#define WD_BUF_RESOURCE_2__PARAM_BUF_SIZE_MASK 0x00001FFFL
1619#define WD_BUF_RESOURCE_2__ADDR_MODE_MASK 0x00008000L
1620#define WD_BUF_RESOURCE_2__CNTL_SB_BUF_SIZE_MASK 0xFFFF0000L
1621//PA_CL_CNTL_STATUS
1622#define PA_CL_CNTL_STATUS__UTC_FAULT_DETECTED__SHIFT 0x0
1623#define PA_CL_CNTL_STATUS__UTC_RETRY_DETECTED__SHIFT 0x1
1624#define PA_CL_CNTL_STATUS__UTC_PRT_DETECTED__SHIFT 0x2
1625#define PA_CL_CNTL_STATUS__UTC_FAULT_DETECTED_MASK 0x00000001L
1626#define PA_CL_CNTL_STATUS__UTC_RETRY_DETECTED_MASK 0x00000002L
1627#define PA_CL_CNTL_STATUS__UTC_PRT_DETECTED_MASK 0x00000004L
1628//PA_CL_ENHANCE
1629#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA__SHIFT 0x0
1630#define PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT 0x1
1631#define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL__SHIFT 0x3
1632#define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE__SHIFT 0x4
1633#define PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL__SHIFT 0x5
1634#define PA_CL_ENHANCE__IGNORE_PIPELINE_RESET__SHIFT 0x6
1635#define PA_CL_ENHANCE__KILL_INNER_EDGE_FLAGS__SHIFT 0x7
1636#define PA_CL_ENHANCE__NGG_PA_TO_ALL_SC__SHIFT 0x8
1637#define PA_CL_ENHANCE__TC_LATENCY_TIME_STAMP_RESOLUTION__SHIFT 0x9
1638#define PA_CL_ENHANCE__NGG_BYPASS_PRIM_FILTER__SHIFT 0xb
1639#define PA_CL_ENHANCE__NGG_SIDEBAND_MEMORY_DEPTH__SHIFT 0xc
1640#define PA_CL_ENHANCE__NGG_PRIM_INDICES_FIFO_DEPTH__SHIFT 0xe
1641#define PA_CL_ENHANCE__ECO_SPARE3__SHIFT 0x1c
1642#define PA_CL_ENHANCE__ECO_SPARE2__SHIFT 0x1d
1643#define PA_CL_ENHANCE__ECO_SPARE1__SHIFT 0x1e
1644#define PA_CL_ENHANCE__ECO_SPARE0__SHIFT 0x1f
1645#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK 0x00000001L
1646#define PA_CL_ENHANCE__NUM_CLIP_SEQ_MASK 0x00000006L
1647#define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL_MASK 0x00000008L
1648#define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE_MASK 0x00000010L
1649#define PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL_MASK 0x00000020L
1650#define PA_CL_ENHANCE__IGNORE_PIPELINE_RESET_MASK 0x00000040L
1651#define PA_CL_ENHANCE__KILL_INNER_EDGE_FLAGS_MASK 0x00000080L
1652#define PA_CL_ENHANCE__NGG_PA_TO_ALL_SC_MASK 0x00000100L
1653#define PA_CL_ENHANCE__TC_LATENCY_TIME_STAMP_RESOLUTION_MASK 0x00000600L
1654#define PA_CL_ENHANCE__NGG_BYPASS_PRIM_FILTER_MASK 0x00000800L
1655#define PA_CL_ENHANCE__NGG_SIDEBAND_MEMORY_DEPTH_MASK 0x00003000L
1656#define PA_CL_ENHANCE__NGG_PRIM_INDICES_FIFO_DEPTH_MASK 0x0001C000L
1657#define PA_CL_ENHANCE__ECO_SPARE3_MASK 0x10000000L
1658#define PA_CL_ENHANCE__ECO_SPARE2_MASK 0x20000000L
1659#define PA_CL_ENHANCE__ECO_SPARE1_MASK 0x40000000L
1660#define PA_CL_ENHANCE__ECO_SPARE0_MASK 0x80000000L
1661//PA_CL_RESET_DEBUG
1662#define PA_CL_RESET_DEBUG__CL_TRIV_DISC_DISABLE__SHIFT 0x0
1663#define PA_CL_RESET_DEBUG__CL_TRIV_DISC_DISABLE_MASK 0x00000001L
1664//PA_SU_CNTL_STATUS
1665#define PA_SU_CNTL_STATUS__SU_BUSY__SHIFT 0x1f
1666#define PA_SU_CNTL_STATUS__SU_BUSY_MASK 0x80000000L
1667//PA_SC_FIFO_DEPTH_CNTL
1668#define PA_SC_FIFO_DEPTH_CNTL__DEPTH__SHIFT 0x0
1669#define PA_SC_FIFO_DEPTH_CNTL__DEPTH_MASK 0x000003FFL
1670//PA_SC_P3D_TRAP_SCREEN_HV_LOCK
1671#define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0
1672#define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x00000001L
1673//PA_SC_HP3D_TRAP_SCREEN_HV_LOCK
1674#define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0
1675#define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x00000001L
1676//PA_SC_TRAP_SCREEN_HV_LOCK
1677#define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0
1678#define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x00000001L
1679//PA_SC_FORCE_EOV_MAX_CNTS
1680#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT 0x0
1681#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT 0x10
1682#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT_MASK 0x0000FFFFL
1683#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT_MASK 0xFFFF0000L
1684//PA_SC_BINNER_EVENT_CNTL_0
1685#define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_0__SHIFT 0x0
1686#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS1__SHIFT 0x2
1687#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS2__SHIFT 0x4
1688#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS3__SHIFT 0x6
1689#define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_TS__SHIFT 0x8
1690#define PA_SC_BINNER_EVENT_CNTL_0__CONTEXT_DONE__SHIFT 0xa
1691#define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH__SHIFT 0xc
1692#define PA_SC_BINNER_EVENT_CNTL_0__CS_PARTIAL_FLUSH__SHIFT 0xe
1693#define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_SYNC__SHIFT 0x10
1694#define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_9__SHIFT 0x12
1695#define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_RESET__SHIFT 0x14
1696#define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_INCR_DE__SHIFT 0x16
1697#define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_IB_END__SHIFT 0x18
1698#define PA_SC_BINNER_EVENT_CNTL_0__RST_PIX_CNT__SHIFT 0x1a
1699#define PA_SC_BINNER_EVENT_CNTL_0__BREAK_BATCH__SHIFT 0x1c
1700#define PA_SC_BINNER_EVENT_CNTL_0__VS_PARTIAL_FLUSH__SHIFT 0x1e
1701#define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_0_MASK 0x00000003L
1702#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS1_MASK 0x0000000CL
1703#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS2_MASK 0x00000030L
1704#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS3_MASK 0x000000C0L
1705#define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_TS_MASK 0x00000300L
1706#define PA_SC_BINNER_EVENT_CNTL_0__CONTEXT_DONE_MASK 0x00000C00L
1707#define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_MASK 0x00003000L
1708#define PA_SC_BINNER_EVENT_CNTL_0__CS_PARTIAL_FLUSH_MASK 0x0000C000L
1709#define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_SYNC_MASK 0x00030000L
1710#define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_9_MASK 0x000C0000L
1711#define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_RESET_MASK 0x00300000L
1712#define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_INCR_DE_MASK 0x00C00000L
1713#define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_IB_END_MASK 0x03000000L
1714#define PA_SC_BINNER_EVENT_CNTL_0__RST_PIX_CNT_MASK 0x0C000000L
1715#define PA_SC_BINNER_EVENT_CNTL_0__BREAK_BATCH_MASK 0x30000000L
1716#define PA_SC_BINNER_EVENT_CNTL_0__VS_PARTIAL_FLUSH_MASK 0xC0000000L
1717//PA_SC_BINNER_EVENT_CNTL_1
1718#define PA_SC_BINNER_EVENT_CNTL_1__PS_PARTIAL_FLUSH__SHIFT 0x0
1719#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_HS_OUTPUT__SHIFT 0x2
1720#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_DFSM__SHIFT 0x4
1721#define PA_SC_BINNER_EVENT_CNTL_1__RESET_TO_LOWEST_VGT__SHIFT 0x6
1722#define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_TS_EVENT__SHIFT 0x8
1723#define PA_SC_BINNER_EVENT_CNTL_1__ZPASS_DONE__SHIFT 0xa
1724#define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_EVENT__SHIFT 0xc
1725#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_START__SHIFT 0xe
1726#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_STOP__SHIFT 0x10
1727#define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_START__SHIFT 0x12
1728#define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_STOP__SHIFT 0x14
1729#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_SAMPLE__SHIFT 0x16
1730#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_ES_OUTPUT__SHIFT 0x18
1731#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_GS_OUTPUT__SHIFT 0x1a
1732#define PA_SC_BINNER_EVENT_CNTL_1__SAMPLE_PIPELINESTAT__SHIFT 0x1c
1733#define PA_SC_BINNER_EVENT_CNTL_1__SO_VGTSTREAMOUT_FLUSH__SHIFT 0x1e
1734#define PA_SC_BINNER_EVENT_CNTL_1__PS_PARTIAL_FLUSH_MASK 0x00000003L
1735#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_HS_OUTPUT_MASK 0x0000000CL
1736#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_DFSM_MASK 0x00000030L
1737#define PA_SC_BINNER_EVENT_CNTL_1__RESET_TO_LOWEST_VGT_MASK 0x000000C0L
1738#define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_TS_EVENT_MASK 0x00000300L
1739#define PA_SC_BINNER_EVENT_CNTL_1__ZPASS_DONE_MASK 0x00000C00L
1740#define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_EVENT_MASK 0x00003000L
1741#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_START_MASK 0x0000C000L
1742#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_STOP_MASK 0x00030000L
1743#define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_START_MASK 0x000C0000L
1744#define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_STOP_MASK 0x00300000L
1745#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_SAMPLE_MASK 0x00C00000L
1746#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_ES_OUTPUT_MASK 0x03000000L
1747#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_GS_OUTPUT_MASK 0x0C000000L
1748#define PA_SC_BINNER_EVENT_CNTL_1__SAMPLE_PIPELINESTAT_MASK 0x30000000L
1749#define PA_SC_BINNER_EVENT_CNTL_1__SO_VGTSTREAMOUT_FLUSH_MASK 0xC0000000L
1750//PA_SC_BINNER_EVENT_CNTL_2
1751#define PA_SC_BINNER_EVENT_CNTL_2__SAMPLE_STREAMOUTSTATS__SHIFT 0x0
1752#define PA_SC_BINNER_EVENT_CNTL_2__RESET_VTX_CNT__SHIFT 0x2
1753#define PA_SC_BINNER_EVENT_CNTL_2__BLOCK_CONTEXT_DONE__SHIFT 0x4
1754#define PA_SC_BINNER_EVENT_CNTL_2__CS_CONTEXT_DONE__SHIFT 0x6
1755#define PA_SC_BINNER_EVENT_CNTL_2__VGT_FLUSH__SHIFT 0x8
1756#define PA_SC_BINNER_EVENT_CNTL_2__TGID_ROLLOVER__SHIFT 0xa
1757#define PA_SC_BINNER_EVENT_CNTL_2__SQ_NON_EVENT__SHIFT 0xc
1758#define PA_SC_BINNER_EVENT_CNTL_2__SC_SEND_DB_VPZ__SHIFT 0xe
1759#define PA_SC_BINNER_EVENT_CNTL_2__BOTTOM_OF_PIPE_TS__SHIFT 0x10
1760#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_SX_TS__SHIFT 0x12
1761#define PA_SC_BINNER_EVENT_CNTL_2__DB_CACHE_FLUSH_AND_INV__SHIFT 0x14
1762#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_DATA_TS__SHIFT 0x16
1763#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_META__SHIFT 0x18
1764#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_DATA_TS__SHIFT 0x1a
1765#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_META__SHIFT 0x1c
1766#define PA_SC_BINNER_EVENT_CNTL_2__CS_DONE__SHIFT 0x1e
1767#define PA_SC_BINNER_EVENT_CNTL_2__SAMPLE_STREAMOUTSTATS_MASK 0x00000003L
1768#define PA_SC_BINNER_EVENT_CNTL_2__RESET_VTX_CNT_MASK 0x0000000CL
1769#define PA_SC_BINNER_EVENT_CNTL_2__BLOCK_CONTEXT_DONE_MASK 0x00000030L
1770#define PA_SC_BINNER_EVENT_CNTL_2__CS_CONTEXT_DONE_MASK 0x000000C0L
1771#define PA_SC_BINNER_EVENT_CNTL_2__VGT_FLUSH_MASK 0x00000300L
1772#define PA_SC_BINNER_EVENT_CNTL_2__TGID_ROLLOVER_MASK 0x00000C00L
1773#define PA_SC_BINNER_EVENT_CNTL_2__SQ_NON_EVENT_MASK 0x00003000L
1774#define PA_SC_BINNER_EVENT_CNTL_2__SC_SEND_DB_VPZ_MASK 0x0000C000L
1775#define PA_SC_BINNER_EVENT_CNTL_2__BOTTOM_OF_PIPE_TS_MASK 0x00030000L
1776#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_SX_TS_MASK 0x000C0000L
1777#define PA_SC_BINNER_EVENT_CNTL_2__DB_CACHE_FLUSH_AND_INV_MASK 0x00300000L
1778#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_DATA_TS_MASK 0x00C00000L
1779#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_META_MASK 0x03000000L
1780#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_DATA_TS_MASK 0x0C000000L
1781#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_META_MASK 0x30000000L
1782#define PA_SC_BINNER_EVENT_CNTL_2__CS_DONE_MASK 0xC0000000L
1783//PA_SC_BINNER_EVENT_CNTL_3
1784#define PA_SC_BINNER_EVENT_CNTL_3__PS_DONE__SHIFT 0x0
1785#define PA_SC_BINNER_EVENT_CNTL_3__FLUSH_AND_INV_CB_PIXEL_DATA__SHIFT 0x2
1786#define PA_SC_BINNER_EVENT_CNTL_3__SX_CB_RAT_ACK_REQUEST__SHIFT 0x4
1787#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_START__SHIFT 0x6
1788#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_STOP__SHIFT 0x8
1789#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_MARKER__SHIFT 0xa
1790#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FLUSH__SHIFT 0xc
1791#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FINISH__SHIFT 0xe
1792#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_CONTROL__SHIFT 0x10
1793#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_DUMP__SHIFT 0x12
1794#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_RESET__SHIFT 0x14
1795#define PA_SC_BINNER_EVENT_CNTL_3__CONTEXT_SUSPEND__SHIFT 0x16
1796#define PA_SC_BINNER_EVENT_CNTL_3__OFFCHIP_HS_DEALLOC__SHIFT 0x18
1797#define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_NGG_PIPELINE__SHIFT 0x1a
1798#define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_LEGACY_PIPELINE__SHIFT 0x1c
1799#define PA_SC_BINNER_EVENT_CNTL_3__RESERVED_63__SHIFT 0x1e
1800#define PA_SC_BINNER_EVENT_CNTL_3__PS_DONE_MASK 0x00000003L
1801#define PA_SC_BINNER_EVENT_CNTL_3__FLUSH_AND_INV_CB_PIXEL_DATA_MASK 0x0000000CL
1802#define PA_SC_BINNER_EVENT_CNTL_3__SX_CB_RAT_ACK_REQUEST_MASK 0x00000030L
1803#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_START_MASK 0x000000C0L
1804#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_STOP_MASK 0x00000300L
1805#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_MARKER_MASK 0x00000C00L
1806#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FLUSH_MASK 0x00003000L
1807#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FINISH_MASK 0x0000C000L
1808#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_CONTROL_MASK 0x00030000L
1809#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_DUMP_MASK 0x000C0000L
1810#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_RESET_MASK 0x00300000L
1811#define PA_SC_BINNER_EVENT_CNTL_3__CONTEXT_SUSPEND_MASK 0x00C00000L
1812#define PA_SC_BINNER_EVENT_CNTL_3__OFFCHIP_HS_DEALLOC_MASK 0x03000000L
1813#define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_NGG_PIPELINE_MASK 0x0C000000L
1814#define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_LEGACY_PIPELINE_MASK 0x30000000L
1815#define PA_SC_BINNER_EVENT_CNTL_3__RESERVED_63_MASK 0xC0000000L
1816//PA_SC_BINNER_TIMEOUT_COUNTER
1817#define PA_SC_BINNER_TIMEOUT_COUNTER__THRESHOLD__SHIFT 0x0
1818#define PA_SC_BINNER_TIMEOUT_COUNTER__THRESHOLD_MASK 0xFFFFFFFFL
1819//PA_SC_BINNER_PERF_CNTL_0
1820#define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_PRIMS_THRESHOLD__SHIFT 0x0
1821#define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_PRIMS_THRESHOLD__SHIFT 0xa
1822#define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_CONTEXT_THRESHOLD__SHIFT 0x14
1823#define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_CONTEXT_THRESHOLD__SHIFT 0x17
1824#define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_PRIMS_THRESHOLD_MASK 0x000003FFL
1825#define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_PRIMS_THRESHOLD_MASK 0x000FFC00L
1826#define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_CONTEXT_THRESHOLD_MASK 0x00700000L
1827#define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_CONTEXT_THRESHOLD_MASK 0x03800000L
1828//PA_SC_BINNER_PERF_CNTL_1
1829#define PA_SC_BINNER_PERF_CNTL_1__BIN_HIST_NUM_PERSISTENT_STATE_THRESHOLD__SHIFT 0x0
1830#define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_PERSISTENT_STATE_THRESHOLD__SHIFT 0x5
1831#define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_TRIV_REJECTED_PRIMS_THRESHOLD__SHIFT 0xa
1832#define PA_SC_BINNER_PERF_CNTL_1__BIN_HIST_NUM_PERSISTENT_STATE_THRESHOLD_MASK 0x0000001FL
1833#define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_PERSISTENT_STATE_THRESHOLD_MASK 0x000003E0L
1834#define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_TRIV_REJECTED_PRIMS_THRESHOLD_MASK 0x03FFFC00L
1835//PA_SC_BINNER_PERF_CNTL_2
1836#define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_ROWS_PER_PRIM_THRESHOLD__SHIFT 0x0
1837#define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_COLUMNS_PER_ROW_THRESHOLD__SHIFT 0xb
1838#define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_ROWS_PER_PRIM_THRESHOLD_MASK 0x000007FFL
1839#define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_COLUMNS_PER_ROW_THRESHOLD_MASK 0x003FF800L
1840//PA_SC_BINNER_PERF_CNTL_3
1841#define PA_SC_BINNER_PERF_CNTL_3__BATCH_HIST_NUM_PS_WAVE_BREAKS_THRESHOLD__SHIFT 0x0
1842#define PA_SC_BINNER_PERF_CNTL_3__BATCH_HIST_NUM_PS_WAVE_BREAKS_THRESHOLD_MASK 0xFFFFFFFFL
1843//PA_SC_FIFO_SIZE
1844#define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT 0x0
1845#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT 0x6
1846#define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT 0xf
1847#define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT 0x15
1848#define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE_MASK 0x0000003FL
1849#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE_MASK 0x00007FC0L
1850#define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE_MASK 0x001F8000L
1851#define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE_MASK 0xFFE00000L
1852//PA_SC_IF_FIFO_SIZE
1853#define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE__SHIFT 0x0
1854#define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE__SHIFT 0x6
1855#define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE__SHIFT 0xc
1856#define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE__SHIFT 0x12
1857#define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE_MASK 0x0000003FL
1858#define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE_MASK 0x00000FC0L
1859#define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE_MASK 0x0003F000L
1860#define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE_MASK 0x00FC0000L
1861//PA_SC_PKR_WAVE_TABLE_CNTL
1862#define PA_SC_PKR_WAVE_TABLE_CNTL__SIZE__SHIFT 0x0
1863#define PA_SC_PKR_WAVE_TABLE_CNTL__SIZE_MASK 0x0000003FL
1864//PA_UTCL1_CNTL1
1865#define PA_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0
1866#define PA_UTCL1_CNTL1__GPUVM_64K_DEFAULT__SHIFT 0x1
1867#define PA_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2
1868#define PA_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3
1869#define PA_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5
1870#define PA_UTCL1_CNTL1__CLIENTID__SHIFT 0x7
1871#define PA_UTCL1_CNTL1__SPARE__SHIFT 0x10
1872#define PA_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11
1873#define PA_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12
1874#define PA_UTCL1_CNTL1__REG_INV_VMID__SHIFT 0x13
1875#define PA_UTCL1_CNTL1__REG_INV_ALL_VMID__SHIFT 0x17
1876#define PA_UTCL1_CNTL1__REG_INV_TOGGLE__SHIFT 0x18
1877#define PA_UTCL1_CNTL1__INVALIDATE_ALL_VMID__SHIFT 0x19
1878#define PA_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a
1879#define PA_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b
1880#define PA_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c
1881#define PA_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e
1882#define PA_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L
1883#define PA_UTCL1_CNTL1__GPUVM_64K_DEFAULT_MASK 0x00000002L
1884#define PA_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L
1885#define PA_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L
1886#define PA_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L
1887#define PA_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L
1888#define PA_UTCL1_CNTL1__SPARE_MASK 0x00010000L
1889#define PA_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L
1890#define PA_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L
1891#define PA_UTCL1_CNTL1__REG_INV_VMID_MASK 0x00780000L
1892#define PA_UTCL1_CNTL1__REG_INV_ALL_VMID_MASK 0x00800000L
1893#define PA_UTCL1_CNTL1__REG_INV_TOGGLE_MASK 0x01000000L
1894#define PA_UTCL1_CNTL1__INVALIDATE_ALL_VMID_MASK 0x02000000L
1895#define PA_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L
1896#define PA_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L
1897#define PA_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L
1898#define PA_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L
1899//PA_UTCL1_CNTL2
1900#define PA_UTCL1_CNTL2__SPARE1__SHIFT 0x0
1901#define PA_UTCL1_CNTL2__SPARE2__SHIFT 0x8
1902#define PA_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9
1903#define PA_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa
1904#define PA_UTCL1_CNTL2__SPARE3__SHIFT 0xb
1905#define PA_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc
1906#define PA_UTCL1_CNTL2__ENABLE_SHOOTDOWN_OPT__SHIFT 0xd
1907#define PA_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe
1908#define PA_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf
1909#define PA_UTCL1_CNTL2__SPARE4__SHIFT 0x10
1910#define PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT 0x12
1911#define PA_UTCL1_CNTL2__PERF_EVENT_RD_WR__SHIFT 0x13
1912#define PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT 0x14
1913#define PA_UTCL1_CNTL2__PERF_EVENT_VMID__SHIFT 0x15
1914#define PA_UTCL1_CNTL2__SPARE5__SHIFT 0x19
1915#define PA_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a
1916#define PA_UTCL1_CNTL2__RESERVED__SHIFT 0x1b
1917#define PA_UTCL1_CNTL2__SPARE1_MASK 0x000000FFL
1918#define PA_UTCL1_CNTL2__SPARE2_MASK 0x00000100L
1919#define PA_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L
1920#define PA_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L
1921#define PA_UTCL1_CNTL2__SPARE3_MASK 0x00000800L
1922#define PA_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L
1923#define PA_UTCL1_CNTL2__ENABLE_SHOOTDOWN_OPT_MASK 0x00002000L
1924#define PA_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L
1925#define PA_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L
1926#define PA_UTCL1_CNTL2__SPARE4_MASK 0x00030000L
1927#define PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L
1928#define PA_UTCL1_CNTL2__PERF_EVENT_RD_WR_MASK 0x00080000L
1929#define PA_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID_MASK 0x00100000L
1930#define PA_UTCL1_CNTL2__PERF_EVENT_VMID_MASK 0x01E00000L
1931#define PA_UTCL1_CNTL2__SPARE5_MASK 0x02000000L
1932#define PA_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L
1933#define PA_UTCL1_CNTL2__RESERVED_MASK 0xF8000000L
1934//PA_SIDEBAND_REQUEST_DELAYS
1935#define PA_SIDEBAND_REQUEST_DELAYS__RETRY_DELAY__SHIFT 0x0
1936#define PA_SIDEBAND_REQUEST_DELAYS__INITIAL_DELAY__SHIFT 0x10
1937#define PA_SIDEBAND_REQUEST_DELAYS__RETRY_DELAY_MASK 0x0000FFFFL
1938#define PA_SIDEBAND_REQUEST_DELAYS__INITIAL_DELAY_MASK 0xFFFF0000L
1939//PA_SC_ENHANCE
1940#define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER__SHIFT 0x0
1941#define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX__SHIFT 0x1
1942#define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX__SHIFT 0x2
1943#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS__SHIFT 0x3
1944#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID__SHIFT 0x4
1945#define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX__SHIFT 0x5
1946#define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER__SHIFT 0x6
1947#define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION__SHIFT 0x7
1948#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM__SHIFT 0x8
1949#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE__SHIFT 0x9
1950#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE__SHIFT 0xa
1951#define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE__SHIFT 0xb
1952#define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS__SHIFT 0xc
1953#define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE__SHIFT 0xd
1954#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE__SHIFT 0xe
1955#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE__SHIFT 0xf
1956#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST__SHIFT 0x10
1957#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING__SHIFT 0x11
1958#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY__SHIFT 0x12
1959#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING__SHIFT 0x13
1960#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING__SHIFT 0x14
1961#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS__SHIFT 0x15
1962#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID__SHIFT 0x16
1963#define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO__SHIFT 0x17
1964#define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT__SHIFT 0x18
1965#define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING__SHIFT 0x19
1966#define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET__SHIFT 0x1a
1967#define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET__SHIFT 0x1b
1968#define PA_SC_ENHANCE__IOO_DISABLE_SCAN_UNSELECTED_FIFOS_FOR_DUAL_GFX_RING_CHANGE__SHIFT 0x1c
1969#define PA_SC_ENHANCE__OOO_USE_ABSOLUTE_FIFO_COUNT_IN_THRESHOLD_SWITCHING__SHIFT 0x1d
1970#define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK 0x00000001L
1971#define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX_MASK 0x00000002L
1972#define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX_MASK 0x00000004L
1973#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS_MASK 0x00000008L
1974#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID_MASK 0x00000010L
1975#define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX_MASK 0x00000020L
1976#define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER_MASK 0x00000040L
1977#define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION_MASK 0x00000080L
1978#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM_MASK 0x00000100L
1979#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE_MASK 0x00000200L
1980#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE_MASK 0x00000400L
1981#define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE_MASK 0x00000800L
1982#define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS_MASK 0x00001000L
1983#define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE_MASK 0x00002000L
1984#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE_MASK 0x00004000L
1985#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE_MASK 0x00008000L
1986#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST_MASK 0x00010000L
1987#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING_MASK 0x00020000L
1988#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY_MASK 0x00040000L
1989#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING_MASK 0x00080000L
1990#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING_MASK 0x00100000L
1991#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS_MASK 0x00200000L
1992#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID_MASK 0x00400000L
1993#define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO_MASK 0x00800000L
1994#define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT_MASK 0x01000000L
1995#define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING_MASK 0x02000000L
1996#define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET_MASK 0x04000000L
1997#define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET_MASK 0x08000000L
1998#define PA_SC_ENHANCE__IOO_DISABLE_SCAN_UNSELECTED_FIFOS_FOR_DUAL_GFX_RING_CHANGE_MASK 0x10000000L
1999#define PA_SC_ENHANCE__OOO_USE_ABSOLUTE_FIFO_COUNT_IN_THRESHOLD_SWITCHING_MASK 0x20000000L
2000//PA_SC_ENHANCE_1
2001#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_ENABLE__SHIFT 0x0
2002#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE__SHIFT 0x1
2003#define PA_SC_ENHANCE_1__DISABLE_SC_BINNING__SHIFT 0x3
2004#define PA_SC_ENHANCE_1__BYPASS_PBB__SHIFT 0x4
2005#define PA_SC_ENHANCE_1__ECO_SPARE0__SHIFT 0x5
2006#define PA_SC_ENHANCE_1__ECO_SPARE1__SHIFT 0x6
2007#define PA_SC_ENHANCE_1__ECO_SPARE2__SHIFT 0x7
2008#define PA_SC_ENHANCE_1__ECO_SPARE3__SHIFT 0x8
2009#define PA_SC_ENHANCE_1__DISABLE_SC_PROCESS_RESET_PBB__SHIFT 0x9
2010#define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_OPT__SHIFT 0xa
2011#define PA_SC_ENHANCE_1__ENABLE_DFSM_FLUSH_EVENT_TO_FLUSH_POPS_CAM__SHIFT 0xb
2012#define PA_SC_ENHANCE_1__DEBUG_PIXEL_PICKER_XY_UNPACK__SHIFT 0xc
2013#define PA_SC_ENHANCE_1__DISABLE_PACKER_GRAD_FDCE_ENHANCE__SHIFT 0xd
2014#define PA_SC_ENHANCE_1__DISABLE_SC_DB_TILE_INTF_FINE_CLOCK_GATE__SHIFT 0xe
2015#define PA_SC_ENHANCE_1__DISABLE_SC_PIPELINE_RESET_LEGACY_MODE_TRANSITION__SHIFT 0xf
2016#define PA_SC_ENHANCE_1__DISABLE_PACKER_ODC_ENHANCE__SHIFT 0x10
2017#define PA_SC_ENHANCE_1__ALLOW_SCALE_LINE_WIDTH_PAD_WITH_BINNING__SHIFT 0x11
2018#define PA_SC_ENHANCE_1__OPTIMAL_BIN_SELECTION__SHIFT 0x12
2019#define PA_SC_ENHANCE_1__DISABLE_FORCE_SOP_ALL_EVENTS__SHIFT 0x13
2020#define PA_SC_ENHANCE_1__DISABLE_PBB_CLK_OPTIMIZATION__SHIFT 0x14
2021#define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_CLK_OPTIMIZATION__SHIFT 0x15
2022#define PA_SC_ENHANCE_1__DISABLE_PBB_BINNING_CLK_OPTIMIZATION__SHIFT 0x16
2023#define PA_SC_ENHANCE_1__RSVD__SHIFT 0x17
2024#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_ENABLE_MASK 0x00000001L
2025#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_MASK 0x00000006L
2026#define PA_SC_ENHANCE_1__DISABLE_SC_BINNING_MASK 0x00000008L
2027#define PA_SC_ENHANCE_1__BYPASS_PBB_MASK 0x00000010L
2028#define PA_SC_ENHANCE_1__ECO_SPARE0_MASK 0x00000020L
2029#define PA_SC_ENHANCE_1__ECO_SPARE1_MASK 0x00000040L
2030#define PA_SC_ENHANCE_1__ECO_SPARE2_MASK 0x00000080L
2031#define PA_SC_ENHANCE_1__ECO_SPARE3_MASK 0x00000100L
2032#define PA_SC_ENHANCE_1__DISABLE_SC_PROCESS_RESET_PBB_MASK 0x00000200L
2033#define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_OPT_MASK 0x00000400L
2034#define PA_SC_ENHANCE_1__ENABLE_DFSM_FLUSH_EVENT_TO_FLUSH_POPS_CAM_MASK 0x00000800L
2035#define PA_SC_ENHANCE_1__DEBUG_PIXEL_PICKER_XY_UNPACK_MASK 0x00001000L
2036#define PA_SC_ENHANCE_1__DISABLE_PACKER_GRAD_FDCE_ENHANCE_MASK 0x00002000L
2037#define PA_SC_ENHANCE_1__DISABLE_SC_DB_TILE_INTF_FINE_CLOCK_GATE_MASK 0x00004000L
2038#define PA_SC_ENHANCE_1__DISABLE_SC_PIPELINE_RESET_LEGACY_MODE_TRANSITION_MASK 0x00008000L
2039#define PA_SC_ENHANCE_1__DISABLE_PACKER_ODC_ENHANCE_MASK 0x00010000L
2040#define PA_SC_ENHANCE_1__ALLOW_SCALE_LINE_WIDTH_PAD_WITH_BINNING_MASK 0x00020000L
2041#define PA_SC_ENHANCE_1__OPTIMAL_BIN_SELECTION_MASK 0x00040000L
2042#define PA_SC_ENHANCE_1__DISABLE_FORCE_SOP_ALL_EVENTS_MASK 0x00080000L
2043#define PA_SC_ENHANCE_1__DISABLE_PBB_CLK_OPTIMIZATION_MASK 0x00100000L
2044#define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_CLK_OPTIMIZATION_MASK 0x00200000L
2045#define PA_SC_ENHANCE_1__DISABLE_PBB_BINNING_CLK_OPTIMIZATION_MASK 0x00400000L
2046#define PA_SC_ENHANCE_1__RSVD_MASK 0xFF800000L
2047//PA_SC_DSM_CNTL
2048#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0__SHIFT 0x0
2049#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_1__SHIFT 0x1
2050#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0_MASK 0x00000001L
2051#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_1_MASK 0x00000002L
2052//PA_SC_TILE_STEERING_CREST_OVERRIDE
2053#define PA_SC_TILE_STEERING_CREST_OVERRIDE__ONE_RB_MODE_ENABLE__SHIFT 0x0
2054#define PA_SC_TILE_STEERING_CREST_OVERRIDE__SE_SELECT__SHIFT 0x1
2055#define PA_SC_TILE_STEERING_CREST_OVERRIDE__RB_SELECT__SHIFT 0x5
2056#define PA_SC_TILE_STEERING_CREST_OVERRIDE__ONE_RB_MODE_ENABLE_MASK 0x00000001L
2057#define PA_SC_TILE_STEERING_CREST_OVERRIDE__SE_SELECT_MASK 0x00000006L
2058#define PA_SC_TILE_STEERING_CREST_OVERRIDE__RB_SELECT_MASK 0x00000060L
2059
2060
2061// addressBlock: gc_sqdec
2062//SQ_CONFIG
2063#define SQ_CONFIG__DISABLE_BARRIER_WAITCNT__SHIFT 0x0
2064#define SQ_CONFIG__UNUSED__SHIFT 0x1
2065#define SQ_CONFIG__OVERRIDE_ALU_BUSY__SHIFT 0x7
2066#define SQ_CONFIG__DEBUG_EN__SHIFT 0x8
2067#define SQ_CONFIG__DEBUG_SINGLE_MEMOP__SHIFT 0x9
2068#define SQ_CONFIG__DEBUG_ONE_INST_CLAUSE__SHIFT 0xa
2069#define SQ_CONFIG__OVERRIDE_LDS_IDX_BUSY__SHIFT 0xb
2070#define SQ_CONFIG__EARLY_TA_DONE_DISABLE__SHIFT 0xc
2071#define SQ_CONFIG__DUA_FLAT_LOCK_ENABLE__SHIFT 0xd
2072#define SQ_CONFIG__DUA_LDS_BYPASS_DISABLE__SHIFT 0xe
2073#define SQ_CONFIG__DUA_FLAT_LDS_PINGPONG_DISABLE__SHIFT 0xf
2074#define SQ_CONFIG__DISABLE_VMEM_SOFT_CLAUSE__SHIFT 0x10
2075#define SQ_CONFIG__DISABLE_SMEM_SOFT_CLAUSE__SHIFT 0x11
2076#define SQ_CONFIG__ENABLE_HIPRIO_ON_EXP_RDY_VS__SHIFT 0x12
2077#define SQ_CONFIG__PRIO_VAL_ON_EXP_RDY_VS__SHIFT 0x13
2078#define SQ_CONFIG__REPLAY_SLEEP_CNT__SHIFT 0x15
2079#define SQ_CONFIG__DISABLE_SP_VGPR_WRITE_SKIP__SHIFT 0x1c
2080#define SQ_CONFIG__DISABLE_SP_REDUNDANT_THREAD_GATING__SHIFT 0x1d
2081#define SQ_CONFIG__DISABLE_FLAT_SOFT_CLAUSE__SHIFT 0x1e
2082#define SQ_CONFIG__DISABLE_MIMG_SOFT_CLAUSE__SHIFT 0x1f
2083#define SQ_CONFIG__DISABLE_BARRIER_WAITCNT_MASK 0x00000001L
2084#define SQ_CONFIG__UNUSED_MASK 0x0000007EL
2085#define SQ_CONFIG__OVERRIDE_ALU_BUSY_MASK 0x00000080L
2086#define SQ_CONFIG__DEBUG_EN_MASK 0x00000100L
2087#define SQ_CONFIG__DEBUG_SINGLE_MEMOP_MASK 0x00000200L
2088#define SQ_CONFIG__DEBUG_ONE_INST_CLAUSE_MASK 0x00000400L
2089#define SQ_CONFIG__OVERRIDE_LDS_IDX_BUSY_MASK 0x00000800L
2090#define SQ_CONFIG__EARLY_TA_DONE_DISABLE_MASK 0x00001000L
2091#define SQ_CONFIG__DUA_FLAT_LOCK_ENABLE_MASK 0x00002000L
2092#define SQ_CONFIG__DUA_LDS_BYPASS_DISABLE_MASK 0x00004000L
2093#define SQ_CONFIG__DUA_FLAT_LDS_PINGPONG_DISABLE_MASK 0x00008000L
2094#define SQ_CONFIG__DISABLE_VMEM_SOFT_CLAUSE_MASK 0x00010000L
2095#define SQ_CONFIG__DISABLE_SMEM_SOFT_CLAUSE_MASK 0x00020000L
2096#define SQ_CONFIG__ENABLE_HIPRIO_ON_EXP_RDY_VS_MASK 0x00040000L
2097#define SQ_CONFIG__PRIO_VAL_ON_EXP_RDY_VS_MASK 0x00180000L
2098#define SQ_CONFIG__REPLAY_SLEEP_CNT_MASK 0x0FE00000L
2099#define SQ_CONFIG__DISABLE_SP_VGPR_WRITE_SKIP_MASK 0x10000000L
2100#define SQ_CONFIG__DISABLE_SP_REDUNDANT_THREAD_GATING_MASK 0x20000000L
2101#define SQ_CONFIG__DISABLE_FLAT_SOFT_CLAUSE_MASK 0x40000000L
2102#define SQ_CONFIG__DISABLE_MIMG_SOFT_CLAUSE_MASK 0x80000000L
2103//SQC_CONFIG
2104#define SQC_CONFIG__INST_CACHE_SIZE__SHIFT 0x0
2105#define SQC_CONFIG__DATA_CACHE_SIZE__SHIFT 0x2
2106#define SQC_CONFIG__MISS_FIFO_DEPTH__SHIFT 0x4
2107#define SQC_CONFIG__HIT_FIFO_DEPTH__SHIFT 0x6
2108#define SQC_CONFIG__FORCE_ALWAYS_MISS__SHIFT 0x7
2109#define SQC_CONFIG__FORCE_IN_ORDER__SHIFT 0x8
2110#define SQC_CONFIG__IDENTITY_HASH_BANK__SHIFT 0x9
2111#define SQC_CONFIG__IDENTITY_HASH_SET__SHIFT 0xa
2112#define SQC_CONFIG__PER_VMID_INV_DISABLE__SHIFT 0xb
2113#define SQC_CONFIG__EVICT_LRU__SHIFT 0xc
2114#define SQC_CONFIG__FORCE_2_BANK__SHIFT 0xe
2115#define SQC_CONFIG__FORCE_1_BANK__SHIFT 0xf
2116#define SQC_CONFIG__LS_DISABLE_CLOCKS__SHIFT 0x10
2117#define SQC_CONFIG__INST_PRF_COUNT__SHIFT 0x18
2118#define SQC_CONFIG__INST_PRF_FILTER_DIS__SHIFT 0x1a
2119#define SQC_CONFIG__INST_CACHE_SIZE_MASK 0x00000003L
2120#define SQC_CONFIG__DATA_CACHE_SIZE_MASK 0x0000000CL
2121#define SQC_CONFIG__MISS_FIFO_DEPTH_MASK 0x00000030L
2122#define SQC_CONFIG__HIT_FIFO_DEPTH_MASK 0x00000040L
2123#define SQC_CONFIG__FORCE_ALWAYS_MISS_MASK 0x00000080L
2124#define SQC_CONFIG__FORCE_IN_ORDER_MASK 0x00000100L
2125#define SQC_CONFIG__IDENTITY_HASH_BANK_MASK 0x00000200L
2126#define SQC_CONFIG__IDENTITY_HASH_SET_MASK 0x00000400L
2127#define SQC_CONFIG__PER_VMID_INV_DISABLE_MASK 0x00000800L
2128#define SQC_CONFIG__EVICT_LRU_MASK 0x00003000L
2129#define SQC_CONFIG__FORCE_2_BANK_MASK 0x00004000L
2130#define SQC_CONFIG__FORCE_1_BANK_MASK 0x00008000L
2131#define SQC_CONFIG__LS_DISABLE_CLOCKS_MASK 0x00FF0000L
2132#define SQC_CONFIG__INST_PRF_COUNT_MASK 0x03000000L
2133#define SQC_CONFIG__INST_PRF_FILTER_DIS_MASK 0x04000000L
2134//LDS_CONFIG
2135#define LDS_CONFIG__ADDR_OUT_OF_RANGE_REPORTING__SHIFT 0x0
2136#define LDS_CONFIG__ADDR_OUT_OF_RANGE_REPORTING_MASK 0x00000001L
2137//SQ_RANDOM_WAVE_PRI
2138#define SQ_RANDOM_WAVE_PRI__RET__SHIFT 0x0
2139#define SQ_RANDOM_WAVE_PRI__RUI__SHIFT 0x7
2140#define SQ_RANDOM_WAVE_PRI__RNG__SHIFT 0xa
2141#define SQ_RANDOM_WAVE_PRI__RET_MASK 0x0000007FL
2142#define SQ_RANDOM_WAVE_PRI__RUI_MASK 0x00000380L
2143#define SQ_RANDOM_WAVE_PRI__RNG_MASK 0x007FFC00L
2144//SQ_REG_CREDITS
2145#define SQ_REG_CREDITS__SRBM_CREDITS__SHIFT 0x0
2146#define SQ_REG_CREDITS__CMD_CREDITS__SHIFT 0x8
2147#define SQ_REG_CREDITS__REG_BUSY__SHIFT 0x1c
2148#define SQ_REG_CREDITS__SRBM_OVERFLOW__SHIFT 0x1d
2149#define SQ_REG_CREDITS__IMMED_OVERFLOW__SHIFT 0x1e
2150#define SQ_REG_CREDITS__CMD_OVERFLOW__SHIFT 0x1f
2151#define SQ_REG_CREDITS__SRBM_CREDITS_MASK 0x0000003FL
2152#define SQ_REG_CREDITS__CMD_CREDITS_MASK 0x00000F00L
2153#define SQ_REG_CREDITS__REG_BUSY_MASK 0x10000000L
2154#define SQ_REG_CREDITS__SRBM_OVERFLOW_MASK 0x20000000L
2155#define SQ_REG_CREDITS__IMMED_OVERFLOW_MASK 0x40000000L
2156#define SQ_REG_CREDITS__CMD_OVERFLOW_MASK 0x80000000L
2157//SQ_FIFO_SIZES
2158#define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE__SHIFT 0x0
2159#define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE__SHIFT 0x8
2160#define SQ_FIFO_SIZES__EXPORT_BUF_SIZE__SHIFT 0x10
2161#define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE__SHIFT 0x12
2162#define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE_MASK 0x0000000FL
2163#define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE_MASK 0x00000F00L
2164#define SQ_FIFO_SIZES__EXPORT_BUF_SIZE_MASK 0x00030000L
2165#define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE_MASK 0x000C0000L
2166//SQ_DSM_CNTL
2167#define SQ_DSM_CNTL__WAVEFRONT_STALL_0__SHIFT 0x0
2168#define SQ_DSM_CNTL__WAVEFRONT_STALL_1__SHIFT 0x1
2169#define SQ_DSM_CNTL__SPI_BACKPRESSURE_0__SHIFT 0x2
2170#define SQ_DSM_CNTL__SPI_BACKPRESSURE_1__SHIFT 0x3
2171#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA0__SHIFT 0x8
2172#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA1__SHIFT 0x9
2173#define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE__SHIFT 0xa
2174#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA0__SHIFT 0x10
2175#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA1__SHIFT 0x11
2176#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE01__SHIFT 0x12
2177#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA2__SHIFT 0x13
2178#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA3__SHIFT 0x14
2179#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE23__SHIFT 0x15
2180#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA0__SHIFT 0x18
2181#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA1__SHIFT 0x19
2182#define SQ_DSM_CNTL__SP_ENABLE_SINGLE_WRITE__SHIFT 0x1a
2183#define SQ_DSM_CNTL__WAVEFRONT_STALL_0_MASK 0x00000001L
2184#define SQ_DSM_CNTL__WAVEFRONT_STALL_1_MASK 0x00000002L
2185#define SQ_DSM_CNTL__SPI_BACKPRESSURE_0_MASK 0x00000004L
2186#define SQ_DSM_CNTL__SPI_BACKPRESSURE_1_MASK 0x00000008L
2187#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA0_MASK 0x00000100L
2188#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA1_MASK 0x00000200L
2189#define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE_MASK 0x00000400L
2190#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA0_MASK 0x00010000L
2191#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA1_MASK 0x00020000L
2192#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE01_MASK 0x00040000L
2193#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA2_MASK 0x00080000L
2194#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA3_MASK 0x00100000L
2195#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE23_MASK 0x00200000L
2196#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA0_MASK 0x01000000L
2197#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA1_MASK 0x02000000L
2198#define SQ_DSM_CNTL__SP_ENABLE_SINGLE_WRITE_MASK 0x04000000L
2199//SQ_DSM_CNTL2
2200#define SQ_DSM_CNTL2__SGPR_ENABLE_ERROR_INJECT__SHIFT 0x0
2201#define SQ_DSM_CNTL2__SGPR_SELECT_INJECT_DELAY__SHIFT 0x2
2202#define SQ_DSM_CNTL2__LDS_D_ENABLE_ERROR_INJECT__SHIFT 0x3
2203#define SQ_DSM_CNTL2__LDS_D_SELECT_INJECT_DELAY__SHIFT 0x5
2204#define SQ_DSM_CNTL2__LDS_I_ENABLE_ERROR_INJECT__SHIFT 0x6
2205#define SQ_DSM_CNTL2__LDS_I_SELECT_INJECT_DELAY__SHIFT 0x8
2206#define SQ_DSM_CNTL2__SP_ENABLE_ERROR_INJECT__SHIFT 0x9
2207#define SQ_DSM_CNTL2__SP_SELECT_INJECT_DELAY__SHIFT 0xb
2208#define SQ_DSM_CNTL2__LDS_INJECT_DELAY__SHIFT 0xe
2209#define SQ_DSM_CNTL2__SP_INJECT_DELAY__SHIFT 0x14
2210#define SQ_DSM_CNTL2__SQ_INJECT_DELAY__SHIFT 0x1a
2211#define SQ_DSM_CNTL2__SGPR_ENABLE_ERROR_INJECT_MASK 0x00000003L
2212#define SQ_DSM_CNTL2__SGPR_SELECT_INJECT_DELAY_MASK 0x00000004L
2213#define SQ_DSM_CNTL2__LDS_D_ENABLE_ERROR_INJECT_MASK 0x00000018L
2214#define SQ_DSM_CNTL2__LDS_D_SELECT_INJECT_DELAY_MASK 0x00000020L
2215#define SQ_DSM_CNTL2__LDS_I_ENABLE_ERROR_INJECT_MASK 0x000000C0L
2216#define SQ_DSM_CNTL2__LDS_I_SELECT_INJECT_DELAY_MASK 0x00000100L
2217#define SQ_DSM_CNTL2__SP_ENABLE_ERROR_INJECT_MASK 0x00000600L
2218#define SQ_DSM_CNTL2__SP_SELECT_INJECT_DELAY_MASK 0x00000800L
2219#define SQ_DSM_CNTL2__LDS_INJECT_DELAY_MASK 0x000FC000L
2220#define SQ_DSM_CNTL2__SP_INJECT_DELAY_MASK 0x03F00000L
2221#define SQ_DSM_CNTL2__SQ_INJECT_DELAY_MASK 0xFC000000L
2222//SQ_RUNTIME_CONFIG
2223#define SQ_RUNTIME_CONFIG__ENABLE_TEX_ARB_OLDEST__SHIFT 0x0
2224#define SQ_RUNTIME_CONFIG__ENABLE_TEX_ARB_OLDEST_MASK 0x00000001L
2225//SH_MEM_BASES
2226#define SH_MEM_BASES__PRIVATE_BASE__SHIFT 0x0
2227#define SH_MEM_BASES__SHARED_BASE__SHIFT 0x10
2228#define SH_MEM_BASES__PRIVATE_BASE_MASK 0x0000FFFFL
2229#define SH_MEM_BASES__SHARED_BASE_MASK 0xFFFF0000L
2230//SH_MEM_CONFIG
2231#define SH_MEM_CONFIG__ADDRESS_MODE__SHIFT 0x0
2232#define SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT 0x3
2233#define SH_MEM_CONFIG__RETRY_DISABLE__SHIFT 0xc
2234#define SH_MEM_CONFIG__PRIVATE_NV__SHIFT 0xd
2235#define SH_MEM_CONFIG__ADDRESS_MODE_MASK 0x00000001L
2236#define SH_MEM_CONFIG__ALIGNMENT_MODE_MASK 0x00000018L
2237#define SH_MEM_CONFIG__RETRY_DISABLE_MASK 0x00001000L
2238#define SH_MEM_CONFIG__PRIVATE_NV_MASK 0x00002000L
2239//CC_GC_SHADER_RATE_CONFIG
2240#define CC_GC_SHADER_RATE_CONFIG__DPFP_RATE__SHIFT 0x1
2241#define CC_GC_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE__SHIFT 0x3
2242#define CC_GC_SHADER_RATE_CONFIG__HALF_LDS__SHIFT 0x4
2243#define CC_GC_SHADER_RATE_CONFIG__DPFP_RATE_MASK 0x00000006L
2244#define CC_GC_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE_MASK 0x00000008L
2245#define CC_GC_SHADER_RATE_CONFIG__HALF_LDS_MASK 0x00000010L
2246//GC_USER_SHADER_RATE_CONFIG
2247#define GC_USER_SHADER_RATE_CONFIG__DPFP_RATE__SHIFT 0x1
2248#define GC_USER_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE__SHIFT 0x3
2249#define GC_USER_SHADER_RATE_CONFIG__HALF_LDS__SHIFT 0x4
2250#define GC_USER_SHADER_RATE_CONFIG__DPFP_RATE_MASK 0x00000006L
2251#define GC_USER_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE_MASK 0x00000008L
2252#define GC_USER_SHADER_RATE_CONFIG__HALF_LDS_MASK 0x00000010L
2253//SQ_INTERRUPT_AUTO_MASK
2254#define SQ_INTERRUPT_AUTO_MASK__MASK__SHIFT 0x0
2255#define SQ_INTERRUPT_AUTO_MASK__MASK_MASK 0x00FFFFFFL
2256//SQ_INTERRUPT_MSG_CTRL
2257#define SQ_INTERRUPT_MSG_CTRL__STALL__SHIFT 0x0
2258#define SQ_INTERRUPT_MSG_CTRL__STALL_MASK 0x00000001L
2259//SQ_UTCL1_CNTL1
2260#define SQ_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0
2261#define SQ_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT 0x1
2262#define SQ_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2
2263#define SQ_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3
2264#define SQ_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5
2265#define SQ_UTCL1_CNTL1__CLIENTID__SHIFT 0x7
2266#define SQ_UTCL1_CNTL1__USERVM_DIS__SHIFT 0x10
2267#define SQ_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11
2268#define SQ_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12
2269#define SQ_UTCL1_CNTL1__REG_INVALIDATE_VMID__SHIFT 0x13
2270#define SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID__SHIFT 0x17
2271#define SQ_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE__SHIFT 0x18
2272#define SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL__SHIFT 0x19
2273#define SQ_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a
2274#define SQ_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b
2275#define SQ_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c
2276#define SQ_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e
2277#define SQ_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L
2278#define SQ_UTCL1_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L
2279#define SQ_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L
2280#define SQ_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L
2281#define SQ_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L
2282#define SQ_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L
2283#define SQ_UTCL1_CNTL1__USERVM_DIS_MASK 0x00010000L
2284#define SQ_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L
2285#define SQ_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L
2286#define SQ_UTCL1_CNTL1__REG_INVALIDATE_VMID_MASK 0x00780000L
2287#define SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID_MASK 0x00800000L
2288#define SQ_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE_MASK 0x01000000L
2289#define SQ_UTCL1_CNTL1__REG_INVALIDATE_ALL_MASK 0x02000000L
2290#define SQ_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L
2291#define SQ_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L
2292#define SQ_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L
2293#define SQ_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L
2294//SQ_UTCL1_CNTL2
2295#define SQ_UTCL1_CNTL2__SPARE__SHIFT 0x0
2296#define SQ_UTCL1_CNTL2__LFIFO_SCAN_DISABLE__SHIFT 0x8
2297#define SQ_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9
2298#define SQ_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa
2299#define SQ_UTCL1_CNTL2__DIS_EDC__SHIFT 0xb
2300#define SQ_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc
2301#define SQ_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT 0xd
2302#define SQ_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe
2303#define SQ_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf
2304#define SQ_UTCL1_CNTL2__RETRY_TIMER__SHIFT 0x10
2305#define SQ_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a
2306#define SQ_UTCL1_CNTL2__PREFETCH_PAGE__SHIFT 0x1c
2307#define SQ_UTCL1_CNTL2__SPARE_MASK 0x000000FFL
2308#define SQ_UTCL1_CNTL2__LFIFO_SCAN_DISABLE_MASK 0x00000100L
2309#define SQ_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L
2310#define SQ_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L
2311#define SQ_UTCL1_CNTL2__DIS_EDC_MASK 0x00000800L
2312#define SQ_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L
2313#define SQ_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK 0x00002000L
2314#define SQ_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L
2315#define SQ_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L
2316#define SQ_UTCL1_CNTL2__RETRY_TIMER_MASK 0x007F0000L
2317#define SQ_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L
2318#define SQ_UTCL1_CNTL2__PREFETCH_PAGE_MASK 0xF0000000L
2319//SQ_UTCL1_STATUS
2320#define SQ_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0
2321#define SQ_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1
2322#define SQ_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2
2323#define SQ_UTCL1_STATUS__RESERVED__SHIFT 0x3
2324#define SQ_UTCL1_STATUS__UNUSED__SHIFT 0x10
2325#define SQ_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L
2326#define SQ_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L
2327#define SQ_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L
2328#define SQ_UTCL1_STATUS__RESERVED_MASK 0x0000FFF8L
2329#define SQ_UTCL1_STATUS__UNUSED_MASK 0xFFFF0000L
2330//SQ_SHADER_TBA_LO
2331#define SQ_SHADER_TBA_LO__ADDR_LO__SHIFT 0x0
2332#define SQ_SHADER_TBA_LO__ADDR_LO_MASK 0xFFFFFFFFL
2333//SQ_SHADER_TBA_HI
2334#define SQ_SHADER_TBA_HI__ADDR_HI__SHIFT 0x0
2335#define SQ_SHADER_TBA_HI__ADDR_HI_MASK 0x000000FFL
2336//SQ_SHADER_TMA_LO
2337#define SQ_SHADER_TMA_LO__ADDR_LO__SHIFT 0x0
2338#define SQ_SHADER_TMA_LO__ADDR_LO_MASK 0xFFFFFFFFL
2339//SQ_SHADER_TMA_HI
2340#define SQ_SHADER_TMA_HI__ADDR_HI__SHIFT 0x0
2341#define SQ_SHADER_TMA_HI__ADDR_HI_MASK 0x000000FFL
2342//SQC_DSM_CNTL
2343#define SQC_DSM_CNTL__INST_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT 0x0
2344#define SQC_DSM_CNTL__INST_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT 0x2
2345#define SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_DSM_IRRITATOR_DATA__SHIFT 0x3
2346#define SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE__SHIFT 0x5
2347#define SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT 0x6
2348#define SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT 0x8
2349#define SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_DSM_IRRITATOR_DATA__SHIFT 0x9
2350#define SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE__SHIFT 0xb
2351#define SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT 0xc
2352#define SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT 0xe
2353#define SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_DSM_IRRITATOR_DATA__SHIFT 0xf
2354#define SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE__SHIFT 0x11
2355#define SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_DSM_IRRITATOR_DATA__SHIFT 0x12
2356#define SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_ENABLE_SINGLE_WRITE__SHIFT 0x14
2357#define SQC_DSM_CNTL__INST_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK 0x00000003L
2358#define SQC_DSM_CNTL__INST_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK 0x00000004L
2359#define SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_DSM_IRRITATOR_DATA_MASK 0x00000018L
2360#define SQC_DSM_CNTL__DATA_CU0_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE_MASK 0x00000020L
2361#define SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK 0x000000C0L
2362#define SQC_DSM_CNTL__DATA_CU0_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK 0x00000100L
2363#define SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_DSM_IRRITATOR_DATA_MASK 0x00000600L
2364#define SQC_DSM_CNTL__DATA_CU1_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE_MASK 0x00000800L
2365#define SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK 0x00003000L
2366#define SQC_DSM_CNTL__DATA_CU1_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK 0x00004000L
2367#define SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_DSM_IRRITATOR_DATA_MASK 0x00018000L
2368#define SQC_DSM_CNTL__DATA_CU2_WRITE_DATA_BUF_ENABLE_SINGLE_WRITE_MASK 0x00020000L
2369#define SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_DSM_IRRITATOR_DATA_MASK 0x000C0000L
2370#define SQC_DSM_CNTL__DATA_CU2_UTCL1_LFIFO_ENABLE_SINGLE_WRITE_MASK 0x00100000L
2371//SQC_DSM_CNTLA
2372#define SQC_DSM_CNTLA__INST_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT 0x0
2373#define SQC_DSM_CNTLA__INST_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x2
2374#define SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x3
2375#define SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x5
2376#define SQC_DSM_CNTLA__INST_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x6
2377#define SQC_DSM_CNTLA__INST_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x8
2378#define SQC_DSM_CNTLA__INST_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT 0x9
2379#define SQC_DSM_CNTLA__INST_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT 0xb
2380#define SQC_DSM_CNTLA__DATA_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT 0xc
2381#define SQC_DSM_CNTLA__DATA_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT 0xe
2382#define SQC_DSM_CNTLA__DATA_HIT_FIFO_DSM_IRRITATOR_DATA__SHIFT 0xf
2383#define SQC_DSM_CNTLA__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x11
2384#define SQC_DSM_CNTLA__DATA_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x12
2385#define SQC_DSM_CNTLA__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x14
2386#define SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA__SHIFT 0x15
2387#define SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x17
2388#define SQC_DSM_CNTLA__DATA_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT 0x18
2389#define SQC_DSM_CNTLA__DATA_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x1a
2390#define SQC_DSM_CNTLA__INST_TAG_RAM_DSM_IRRITATOR_DATA_MASK 0x00000003L
2391#define SQC_DSM_CNTLA__INST_TAG_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000004L
2392#define SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x00000018L
2393#define SQC_DSM_CNTLA__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000020L
2394#define SQC_DSM_CNTLA__INST_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000000C0L
2395#define SQC_DSM_CNTLA__INST_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000100L
2396#define SQC_DSM_CNTLA__INST_BANK_RAM_DSM_IRRITATOR_DATA_MASK 0x00000600L
2397#define SQC_DSM_CNTLA__INST_BANK_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000800L
2398#define SQC_DSM_CNTLA__DATA_TAG_RAM_DSM_IRRITATOR_DATA_MASK 0x00003000L
2399#define SQC_DSM_CNTLA__DATA_TAG_RAM_ENABLE_SINGLE_WRITE_MASK 0x00004000L
2400#define SQC_DSM_CNTLA__DATA_HIT_FIFO_DSM_IRRITATOR_DATA_MASK 0x00018000L
2401#define SQC_DSM_CNTLA__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00020000L
2402#define SQC_DSM_CNTLA__DATA_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000C0000L
2403#define SQC_DSM_CNTLA__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00100000L
2404#define SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA_MASK 0x00600000L
2405#define SQC_DSM_CNTLA__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE_MASK 0x00800000L
2406#define SQC_DSM_CNTLA__DATA_BANK_RAM_DSM_IRRITATOR_DATA_MASK 0x03000000L
2407#define SQC_DSM_CNTLA__DATA_BANK_RAM_ENABLE_SINGLE_WRITE_MASK 0x04000000L
2408//SQC_DSM_CNTLB
2409#define SQC_DSM_CNTLB__INST_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT 0x0
2410#define SQC_DSM_CNTLB__INST_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x2
2411#define SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x3
2412#define SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x5
2413#define SQC_DSM_CNTLB__INST_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x6
2414#define SQC_DSM_CNTLB__INST_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x8
2415#define SQC_DSM_CNTLB__INST_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT 0x9
2416#define SQC_DSM_CNTLB__INST_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT 0xb
2417#define SQC_DSM_CNTLB__DATA_TAG_RAM_DSM_IRRITATOR_DATA__SHIFT 0xc
2418#define SQC_DSM_CNTLB__DATA_TAG_RAM_ENABLE_SINGLE_WRITE__SHIFT 0xe
2419#define SQC_DSM_CNTLB__DATA_HIT_FIFO_DSM_IRRITATOR_DATA__SHIFT 0xf
2420#define SQC_DSM_CNTLB__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x11
2421#define SQC_DSM_CNTLB__DATA_MISS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x12
2422#define SQC_DSM_CNTLB__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x14
2423#define SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA__SHIFT 0x15
2424#define SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x17
2425#define SQC_DSM_CNTLB__DATA_BANK_RAM_DSM_IRRITATOR_DATA__SHIFT 0x18
2426#define SQC_DSM_CNTLB__DATA_BANK_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x1a
2427#define SQC_DSM_CNTLB__INST_TAG_RAM_DSM_IRRITATOR_DATA_MASK 0x00000003L
2428#define SQC_DSM_CNTLB__INST_TAG_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000004L
2429#define SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x00000018L
2430#define SQC_DSM_CNTLB__INST_UTCL1_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000020L
2431#define SQC_DSM_CNTLB__INST_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000000C0L
2432#define SQC_DSM_CNTLB__INST_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000100L
2433#define SQC_DSM_CNTLB__INST_BANK_RAM_DSM_IRRITATOR_DATA_MASK 0x00000600L
2434#define SQC_DSM_CNTLB__INST_BANK_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000800L
2435#define SQC_DSM_CNTLB__DATA_TAG_RAM_DSM_IRRITATOR_DATA_MASK 0x00003000L
2436#define SQC_DSM_CNTLB__DATA_TAG_RAM_ENABLE_SINGLE_WRITE_MASK 0x00004000L
2437#define SQC_DSM_CNTLB__DATA_HIT_FIFO_DSM_IRRITATOR_DATA_MASK 0x00018000L
2438#define SQC_DSM_CNTLB__DATA_HIT_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00020000L
2439#define SQC_DSM_CNTLB__DATA_MISS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000C0000L
2440#define SQC_DSM_CNTLB__DATA_MISS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00100000L
2441#define SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_DSM_IRRITATOR_DATA_MASK 0x00600000L
2442#define SQC_DSM_CNTLB__DATA_DIRTY_BIT_RAM_ENABLE_SINGLE_WRITE_MASK 0x00800000L
2443#define SQC_DSM_CNTLB__DATA_BANK_RAM_DSM_IRRITATOR_DATA_MASK 0x03000000L
2444#define SQC_DSM_CNTLB__DATA_BANK_RAM_ENABLE_SINGLE_WRITE_MASK 0x04000000L
2445//SQC_DSM_CNTL2
2446#define SQC_DSM_CNTL2__INST_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT 0x0
2447#define SQC_DSM_CNTL2__INST_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT 0x2
2448#define SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_ENABLE_ERROR_INJECT__SHIFT 0x3
2449#define SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_SELECT_INJECT_DELAY__SHIFT 0x5
2450#define SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT 0x6
2451#define SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT 0x8
2452#define SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_ENABLE_ERROR_INJECT__SHIFT 0x9
2453#define SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_SELECT_INJECT_DELAY__SHIFT 0xb
2454#define SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT 0xc
2455#define SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT 0xe
2456#define SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_ENABLE_ERROR_INJECT__SHIFT 0xf
2457#define SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_SELECT_INJECT_DELAY__SHIFT 0x11
2458#define SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_ENABLE_ERROR_INJECT__SHIFT 0x12
2459#define SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_SELECT_INJECT_DELAY__SHIFT 0x14
2460#define SQC_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a
2461#define SQC_DSM_CNTL2__INST_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK 0x00000003L
2462#define SQC_DSM_CNTL2__INST_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK 0x00000004L
2463#define SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_ENABLE_ERROR_INJECT_MASK 0x00000018L
2464#define SQC_DSM_CNTL2__DATA_CU0_WRITE_DATA_BUF_SELECT_INJECT_DELAY_MASK 0x00000020L
2465#define SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK 0x000000C0L
2466#define SQC_DSM_CNTL2__DATA_CU0_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK 0x00000100L
2467#define SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_ENABLE_ERROR_INJECT_MASK 0x00000600L
2468#define SQC_DSM_CNTL2__DATA_CU1_WRITE_DATA_BUF_SELECT_INJECT_DELAY_MASK 0x00000800L
2469#define SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK 0x00003000L
2470#define SQC_DSM_CNTL2__DATA_CU1_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK 0x00004000L
2471#define SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_ENABLE_ERROR_INJECT_MASK 0x00018000L
2472#define SQC_DSM_CNTL2__DATA_CU2_WRITE_DATA_BUF_SELECT_INJECT_DELAY_MASK 0x00020000L
2473#define SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_ENABLE_ERROR_INJECT_MASK 0x000C0000L
2474#define SQC_DSM_CNTL2__DATA_CU2_UTCL1_LFIFO_SELECT_INJECT_DELAY_MASK 0x00100000L
2475#define SQC_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L
2476//SQC_DSM_CNTL2A
2477#define SQC_DSM_CNTL2A__INST_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT 0x0
2478#define SQC_DSM_CNTL2A__INST_TAG_RAM_SELECT_INJECT_DELAY__SHIFT 0x2
2479#define SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x3
2480#define SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x5
2481#define SQC_DSM_CNTL2A__INST_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x6
2482#define SQC_DSM_CNTL2A__INST_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x8
2483#define SQC_DSM_CNTL2A__INST_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT 0x9
2484#define SQC_DSM_CNTL2A__INST_BANK_RAM_SELECT_INJECT_DELAY__SHIFT 0xb
2485#define SQC_DSM_CNTL2A__DATA_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT 0xc
2486#define SQC_DSM_CNTL2A__DATA_TAG_RAM_SELECT_INJECT_DELAY__SHIFT 0xe
2487#define SQC_DSM_CNTL2A__DATA_HIT_FIFO_ENABLE_ERROR_INJECT__SHIFT 0xf
2488#define SQC_DSM_CNTL2A__DATA_HIT_FIFO_SELECT_INJECT_DELAY__SHIFT 0x11
2489#define SQC_DSM_CNTL2A__DATA_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x12
2490#define SQC_DSM_CNTL2A__DATA_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x14
2491#define SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT__SHIFT 0x15
2492#define SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY__SHIFT 0x17
2493#define SQC_DSM_CNTL2A__DATA_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT 0x18
2494#define SQC_DSM_CNTL2A__DATA_BANK_RAM_SELECT_INJECT_DELAY__SHIFT 0x1a
2495#define SQC_DSM_CNTL2A__INST_TAG_RAM_ENABLE_ERROR_INJECT_MASK 0x00000003L
2496#define SQC_DSM_CNTL2A__INST_TAG_RAM_SELECT_INJECT_DELAY_MASK 0x00000004L
2497#define SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x00000018L
2498#define SQC_DSM_CNTL2A__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000020L
2499#define SQC_DSM_CNTL2A__INST_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000000C0L
2500#define SQC_DSM_CNTL2A__INST_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000100L
2501#define SQC_DSM_CNTL2A__INST_BANK_RAM_ENABLE_ERROR_INJECT_MASK 0x00000600L
2502#define SQC_DSM_CNTL2A__INST_BANK_RAM_SELECT_INJECT_DELAY_MASK 0x00000800L
2503#define SQC_DSM_CNTL2A__DATA_TAG_RAM_ENABLE_ERROR_INJECT_MASK 0x00003000L
2504#define SQC_DSM_CNTL2A__DATA_TAG_RAM_SELECT_INJECT_DELAY_MASK 0x00004000L
2505#define SQC_DSM_CNTL2A__DATA_HIT_FIFO_ENABLE_ERROR_INJECT_MASK 0x00018000L
2506#define SQC_DSM_CNTL2A__DATA_HIT_FIFO_SELECT_INJECT_DELAY_MASK 0x00020000L
2507#define SQC_DSM_CNTL2A__DATA_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000C0000L
2508#define SQC_DSM_CNTL2A__DATA_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00100000L
2509#define SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT_MASK 0x00600000L
2510#define SQC_DSM_CNTL2A__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY_MASK 0x00800000L
2511#define SQC_DSM_CNTL2A__DATA_BANK_RAM_ENABLE_ERROR_INJECT_MASK 0x03000000L
2512#define SQC_DSM_CNTL2A__DATA_BANK_RAM_SELECT_INJECT_DELAY_MASK 0x04000000L
2513//SQC_DSM_CNTL2B
2514#define SQC_DSM_CNTL2B__INST_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT 0x0
2515#define SQC_DSM_CNTL2B__INST_TAG_RAM_SELECT_INJECT_DELAY__SHIFT 0x2
2516#define SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x3
2517#define SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x5
2518#define SQC_DSM_CNTL2B__INST_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x6
2519#define SQC_DSM_CNTL2B__INST_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x8
2520#define SQC_DSM_CNTL2B__INST_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT 0x9
2521#define SQC_DSM_CNTL2B__INST_BANK_RAM_SELECT_INJECT_DELAY__SHIFT 0xb
2522#define SQC_DSM_CNTL2B__DATA_TAG_RAM_ENABLE_ERROR_INJECT__SHIFT 0xc
2523#define SQC_DSM_CNTL2B__DATA_TAG_RAM_SELECT_INJECT_DELAY__SHIFT 0xe
2524#define SQC_DSM_CNTL2B__DATA_HIT_FIFO_ENABLE_ERROR_INJECT__SHIFT 0xf
2525#define SQC_DSM_CNTL2B__DATA_HIT_FIFO_SELECT_INJECT_DELAY__SHIFT 0x11
2526#define SQC_DSM_CNTL2B__DATA_MISS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x12
2527#define SQC_DSM_CNTL2B__DATA_MISS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x14
2528#define SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT__SHIFT 0x15
2529#define SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY__SHIFT 0x17
2530#define SQC_DSM_CNTL2B__DATA_BANK_RAM_ENABLE_ERROR_INJECT__SHIFT 0x18
2531#define SQC_DSM_CNTL2B__DATA_BANK_RAM_SELECT_INJECT_DELAY__SHIFT 0x1a
2532#define SQC_DSM_CNTL2B__INST_TAG_RAM_ENABLE_ERROR_INJECT_MASK 0x00000003L
2533#define SQC_DSM_CNTL2B__INST_TAG_RAM_SELECT_INJECT_DELAY_MASK 0x00000004L
2534#define SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x00000018L
2535#define SQC_DSM_CNTL2B__INST_UTCL1_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000020L
2536#define SQC_DSM_CNTL2B__INST_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000000C0L
2537#define SQC_DSM_CNTL2B__INST_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000100L
2538#define SQC_DSM_CNTL2B__INST_BANK_RAM_ENABLE_ERROR_INJECT_MASK 0x00000600L
2539#define SQC_DSM_CNTL2B__INST_BANK_RAM_SELECT_INJECT_DELAY_MASK 0x00000800L
2540#define SQC_DSM_CNTL2B__DATA_TAG_RAM_ENABLE_ERROR_INJECT_MASK 0x00003000L
2541#define SQC_DSM_CNTL2B__DATA_TAG_RAM_SELECT_INJECT_DELAY_MASK 0x00004000L
2542#define SQC_DSM_CNTL2B__DATA_HIT_FIFO_ENABLE_ERROR_INJECT_MASK 0x00018000L
2543#define SQC_DSM_CNTL2B__DATA_HIT_FIFO_SELECT_INJECT_DELAY_MASK 0x00020000L
2544#define SQC_DSM_CNTL2B__DATA_MISS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000C0000L
2545#define SQC_DSM_CNTL2B__DATA_MISS_FIFO_SELECT_INJECT_DELAY_MASK 0x00100000L
2546#define SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_ENABLE_ERROR_INJECT_MASK 0x00600000L
2547#define SQC_DSM_CNTL2B__DATA_DIRTY_BIT_RAM_SELECT_INJECT_DELAY_MASK 0x00800000L
2548#define SQC_DSM_CNTL2B__DATA_BANK_RAM_ENABLE_ERROR_INJECT_MASK 0x03000000L
2549#define SQC_DSM_CNTL2B__DATA_BANK_RAM_SELECT_INJECT_DELAY_MASK 0x04000000L
2550//SQC_EDC_FUE_CNTL
2551#define SQC_EDC_FUE_CNTL__BLOCK_FUE_FLAGS__SHIFT 0x0
2552#define SQC_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES__SHIFT 0x10
2553#define SQC_EDC_FUE_CNTL__BLOCK_FUE_FLAGS_MASK 0x0000FFFFL
2554#define SQC_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES_MASK 0xFFFF0000L
2555//SQC_EDC_CNT2
2556#define SQC_EDC_CNT2__INST_BANKA_TAG_RAM_SEC_COUNT__SHIFT 0x0
2557#define SQC_EDC_CNT2__INST_BANKA_TAG_RAM_DED_COUNT__SHIFT 0x2
2558#define SQC_EDC_CNT2__INST_BANKA_BANK_RAM_SEC_COUNT__SHIFT 0x4
2559#define SQC_EDC_CNT2__INST_BANKA_BANK_RAM_DED_COUNT__SHIFT 0x6
2560#define SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_SEC_COUNT__SHIFT 0x8
2561#define SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_DED_COUNT__SHIFT 0xa
2562#define SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_SEC_COUNT__SHIFT 0xc
2563#define SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_DED_COUNT__SHIFT 0xe
2564#define SQC_EDC_CNT2__INST_BANKA_UTCL1_MISS_FIFO_SED_COUNT__SHIFT 0x10
2565#define SQC_EDC_CNT2__INST_BANKA_MISS_FIFO_SED_COUNT__SHIFT 0x12
2566#define SQC_EDC_CNT2__DATA_BANKA_HIT_FIFO_SED_COUNT__SHIFT 0x14
2567#define SQC_EDC_CNT2__DATA_BANKA_MISS_FIFO_SED_COUNT__SHIFT 0x16
2568#define SQC_EDC_CNT2__DATA_BANKA_DIRTY_BIT_RAM_SED_COUNT__SHIFT 0x18
2569#define SQC_EDC_CNT2__INST_UTCL1_LFIFO_SEC_COUNT__SHIFT 0x1a
2570#define SQC_EDC_CNT2__INST_UTCL1_LFIFO_DED_COUNT__SHIFT 0x1c
2571#define SQC_EDC_CNT2__INST_BANKA_TAG_RAM_SEC_COUNT_MASK 0x00000003L
2572#define SQC_EDC_CNT2__INST_BANKA_TAG_RAM_DED_COUNT_MASK 0x0000000CL
2573#define SQC_EDC_CNT2__INST_BANKA_BANK_RAM_SEC_COUNT_MASK 0x00000030L
2574#define SQC_EDC_CNT2__INST_BANKA_BANK_RAM_DED_COUNT_MASK 0x000000C0L
2575#define SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_SEC_COUNT_MASK 0x00000300L
2576#define SQC_EDC_CNT2__DATA_BANKA_TAG_RAM_DED_COUNT_MASK 0x00000C00L
2577#define SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_SEC_COUNT_MASK 0x00003000L
2578#define SQC_EDC_CNT2__DATA_BANKA_BANK_RAM_DED_COUNT_MASK 0x0000C000L
2579#define SQC_EDC_CNT2__INST_BANKA_UTCL1_MISS_FIFO_SED_COUNT_MASK 0x00030000L
2580#define SQC_EDC_CNT2__INST_BANKA_MISS_FIFO_SED_COUNT_MASK 0x000C0000L
2581#define SQC_EDC_CNT2__DATA_BANKA_HIT_FIFO_SED_COUNT_MASK 0x00300000L
2582#define SQC_EDC_CNT2__DATA_BANKA_MISS_FIFO_SED_COUNT_MASK 0x00C00000L
2583#define SQC_EDC_CNT2__DATA_BANKA_DIRTY_BIT_RAM_SED_COUNT_MASK 0x03000000L
2584#define SQC_EDC_CNT2__INST_UTCL1_LFIFO_SEC_COUNT_MASK 0x0C000000L
2585#define SQC_EDC_CNT2__INST_UTCL1_LFIFO_DED_COUNT_MASK 0x30000000L
2586//SQC_EDC_CNT3
2587#define SQC_EDC_CNT3__INST_BANKB_TAG_RAM_SEC_COUNT__SHIFT 0x0
2588#define SQC_EDC_CNT3__INST_BANKB_TAG_RAM_DED_COUNT__SHIFT 0x2
2589#define SQC_EDC_CNT3__INST_BANKB_BANK_RAM_SEC_COUNT__SHIFT 0x4
2590#define SQC_EDC_CNT3__INST_BANKB_BANK_RAM_DED_COUNT__SHIFT 0x6
2591#define SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_SEC_COUNT__SHIFT 0x8
2592#define SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_DED_COUNT__SHIFT 0xa
2593#define SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_SEC_COUNT__SHIFT 0xc
2594#define SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_DED_COUNT__SHIFT 0xe
2595#define SQC_EDC_CNT3__INST_BANKB_UTCL1_MISS_FIFO_SED_COUNT__SHIFT 0x10
2596#define SQC_EDC_CNT3__INST_BANKB_MISS_FIFO_SED_COUNT__SHIFT 0x12
2597#define SQC_EDC_CNT3__DATA_BANKB_HIT_FIFO_SED_COUNT__SHIFT 0x14
2598#define SQC_EDC_CNT3__DATA_BANKB_MISS_FIFO_SED_COUNT__SHIFT 0x16
2599#define SQC_EDC_CNT3__DATA_BANKB_DIRTY_BIT_RAM_SED_COUNT__SHIFT 0x18
2600#define SQC_EDC_CNT3__INST_BANKB_TAG_RAM_SEC_COUNT_MASK 0x00000003L
2601#define SQC_EDC_CNT3__INST_BANKB_TAG_RAM_DED_COUNT_MASK 0x0000000CL
2602#define SQC_EDC_CNT3__INST_BANKB_BANK_RAM_SEC_COUNT_MASK 0x00000030L
2603#define SQC_EDC_CNT3__INST_BANKB_BANK_RAM_DED_COUNT_MASK 0x000000C0L
2604#define SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_SEC_COUNT_MASK 0x00000300L
2605#define SQC_EDC_CNT3__DATA_BANKB_TAG_RAM_DED_COUNT_MASK 0x00000C00L
2606#define SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_SEC_COUNT_MASK 0x00003000L
2607#define SQC_EDC_CNT3__DATA_BANKB_BANK_RAM_DED_COUNT_MASK 0x0000C000L
2608#define SQC_EDC_CNT3__INST_BANKB_UTCL1_MISS_FIFO_SED_COUNT_MASK 0x00030000L
2609#define SQC_EDC_CNT3__INST_BANKB_MISS_FIFO_SED_COUNT_MASK 0x000C0000L
2610#define SQC_EDC_CNT3__DATA_BANKB_HIT_FIFO_SED_COUNT_MASK 0x00300000L
2611#define SQC_EDC_CNT3__DATA_BANKB_MISS_FIFO_SED_COUNT_MASK 0x00C00000L
2612#define SQC_EDC_CNT3__DATA_BANKB_DIRTY_BIT_RAM_SED_COUNT_MASK 0x03000000L
2613//SQ_REG_TIMESTAMP
2614#define SQ_REG_TIMESTAMP__TIMESTAMP__SHIFT 0x0
2615#define SQ_REG_TIMESTAMP__TIMESTAMP_MASK 0x000000FFL
2616//SQ_CMD_TIMESTAMP
2617#define SQ_CMD_TIMESTAMP__TIMESTAMP__SHIFT 0x0
2618#define SQ_CMD_TIMESTAMP__TIMESTAMP_MASK 0x000000FFL
2619//SQ_IND_INDEX
2620#define SQ_IND_INDEX__WAVE_ID__SHIFT 0x0
2621#define SQ_IND_INDEX__SIMD_ID__SHIFT 0x4
2622#define SQ_IND_INDEX__THREAD_ID__SHIFT 0x6
2623#define SQ_IND_INDEX__AUTO_INCR__SHIFT 0xc
2624#define SQ_IND_INDEX__FORCE_READ__SHIFT 0xd
2625#define SQ_IND_INDEX__READ_TIMEOUT__SHIFT 0xe
2626#define SQ_IND_INDEX__UNINDEXED__SHIFT 0xf
2627#define SQ_IND_INDEX__INDEX__SHIFT 0x10
2628#define SQ_IND_INDEX__WAVE_ID_MASK 0x0000000FL
2629#define SQ_IND_INDEX__SIMD_ID_MASK 0x00000030L
2630#define SQ_IND_INDEX__THREAD_ID_MASK 0x00000FC0L
2631#define SQ_IND_INDEX__AUTO_INCR_MASK 0x00001000L
2632#define SQ_IND_INDEX__FORCE_READ_MASK 0x00002000L
2633#define SQ_IND_INDEX__READ_TIMEOUT_MASK 0x00004000L
2634#define SQ_IND_INDEX__UNINDEXED_MASK 0x00008000L
2635#define SQ_IND_INDEX__INDEX_MASK 0xFFFF0000L
2636//SQ_IND_DATA
2637#define SQ_IND_DATA__DATA__SHIFT 0x0
2638#define SQ_IND_DATA__DATA_MASK 0xFFFFFFFFL
2639//SQ_CMD
2640#define SQ_CMD__CMD__SHIFT 0x0
2641#define SQ_CMD__MODE__SHIFT 0x4
2642#define SQ_CMD__CHECK_VMID__SHIFT 0x7
2643#define SQ_CMD__DATA__SHIFT 0x8
2644#define SQ_CMD__WAVE_ID__SHIFT 0x10
2645#define SQ_CMD__SIMD_ID__SHIFT 0x14
2646#define SQ_CMD__QUEUE_ID__SHIFT 0x18
2647#define SQ_CMD__VM_ID__SHIFT 0x1c
2648#define SQ_CMD__CMD_MASK 0x00000007L
2649#define SQ_CMD__MODE_MASK 0x00000070L
2650#define SQ_CMD__CHECK_VMID_MASK 0x00000080L
2651#define SQ_CMD__DATA_MASK 0x00000F00L
2652#define SQ_CMD__WAVE_ID_MASK 0x000F0000L
2653#define SQ_CMD__SIMD_ID_MASK 0x00300000L
2654#define SQ_CMD__QUEUE_ID_MASK 0x07000000L
2655#define SQ_CMD__VM_ID_MASK 0xF0000000L
2656//SQ_TIME_HI
2657#define SQ_TIME_HI__TIME__SHIFT 0x0
2658#define SQ_TIME_HI__TIME_MASK 0xFFFFFFFFL
2659//SQ_TIME_LO
2660#define SQ_TIME_LO__TIME__SHIFT 0x0
2661#define SQ_TIME_LO__TIME_MASK 0xFFFFFFFFL
2662//SQ_DS_0
2663#define SQ_DS_0__OFFSET0__SHIFT 0x0
2664#define SQ_DS_0__OFFSET1__SHIFT 0x8
2665#define SQ_DS_0__GDS__SHIFT 0x10
2666#define SQ_DS_0__OP__SHIFT 0x11
2667#define SQ_DS_0__ENCODING__SHIFT 0x1a
2668#define SQ_DS_0__OFFSET0_MASK 0x000000FFL
2669#define SQ_DS_0__OFFSET1_MASK 0x0000FF00L
2670#define SQ_DS_0__GDS_MASK 0x00010000L
2671#define SQ_DS_0__OP_MASK 0x01FE0000L
2672#define SQ_DS_0__ENCODING_MASK 0xFC000000L
2673//SQ_DS_1
2674#define SQ_DS_1__ADDR__SHIFT 0x0
2675#define SQ_DS_1__DATA0__SHIFT 0x8
2676#define SQ_DS_1__DATA1__SHIFT 0x10
2677#define SQ_DS_1__VDST__SHIFT 0x18
2678#define SQ_DS_1__ADDR_MASK 0x000000FFL
2679#define SQ_DS_1__DATA0_MASK 0x0000FF00L
2680#define SQ_DS_1__DATA1_MASK 0x00FF0000L
2681#define SQ_DS_1__VDST_MASK 0xFF000000L
2682//SQ_EXP_0
2683#define SQ_EXP_0__EN__SHIFT 0x0
2684#define SQ_EXP_0__TGT__SHIFT 0x4
2685#define SQ_EXP_0__COMPR__SHIFT 0xa
2686#define SQ_EXP_0__DONE__SHIFT 0xb
2687#define SQ_EXP_0__VM__SHIFT 0xc
2688#define SQ_EXP_0__ENCODING__SHIFT 0x1a
2689#define SQ_EXP_0__EN_MASK 0x0000000FL
2690#define SQ_EXP_0__TGT_MASK 0x000003F0L
2691#define SQ_EXP_0__COMPR_MASK 0x00000400L
2692#define SQ_EXP_0__DONE_MASK 0x00000800L
2693#define SQ_EXP_0__VM_MASK 0x00001000L
2694#define SQ_EXP_0__ENCODING_MASK 0xFC000000L
2695//SQ_EXP_1
2696#define SQ_EXP_1__VSRC0__SHIFT 0x0
2697#define SQ_EXP_1__VSRC1__SHIFT 0x8
2698#define SQ_EXP_1__VSRC2__SHIFT 0x10
2699#define SQ_EXP_1__VSRC3__SHIFT 0x18
2700#define SQ_EXP_1__VSRC0_MASK 0x000000FFL
2701#define SQ_EXP_1__VSRC1_MASK 0x0000FF00L
2702#define SQ_EXP_1__VSRC2_MASK 0x00FF0000L
2703#define SQ_EXP_1__VSRC3_MASK 0xFF000000L
2704//SQ_FLAT_0
2705#define SQ_FLAT_0__OFFSET__SHIFT 0x0
2706#define SQ_FLAT_0__LDS__SHIFT 0xd
2707#define SQ_FLAT_0__SEG__SHIFT 0xe
2708#define SQ_FLAT_0__GLC__SHIFT 0x10
2709#define SQ_FLAT_0__SLC__SHIFT 0x11
2710#define SQ_FLAT_0__OP__SHIFT 0x12
2711#define SQ_FLAT_0__ENCODING__SHIFT 0x1a
2712#define SQ_FLAT_0__OFFSET_MASK 0x00000FFFL
2713#define SQ_FLAT_0__LDS_MASK 0x00002000L
2714#define SQ_FLAT_0__SEG_MASK 0x0000C000L
2715#define SQ_FLAT_0__GLC_MASK 0x00010000L
2716#define SQ_FLAT_0__SLC_MASK 0x00020000L
2717#define SQ_FLAT_0__OP_MASK 0x01FC0000L
2718#define SQ_FLAT_0__ENCODING_MASK 0xFC000000L
2719//SQ_FLAT_1
2720#define SQ_FLAT_1__ADDR__SHIFT 0x0
2721#define SQ_FLAT_1__DATA__SHIFT 0x8
2722#define SQ_FLAT_1__SADDR__SHIFT 0x10
2723#define SQ_FLAT_1__NV__SHIFT 0x17
2724#define SQ_FLAT_1__VDST__SHIFT 0x18
2725#define SQ_FLAT_1__ADDR_MASK 0x000000FFL
2726#define SQ_FLAT_1__DATA_MASK 0x0000FF00L
2727#define SQ_FLAT_1__SADDR_MASK 0x007F0000L
2728#define SQ_FLAT_1__NV_MASK 0x00800000L
2729#define SQ_FLAT_1__VDST_MASK 0xFF000000L
2730//SQ_GLBL_0
2731#define SQ_GLBL_0__OFFSET__SHIFT 0x0
2732#define SQ_GLBL_0__LDS__SHIFT 0xd
2733#define SQ_GLBL_0__SEG__SHIFT 0xe
2734#define SQ_GLBL_0__GLC__SHIFT 0x10
2735#define SQ_GLBL_0__SLC__SHIFT 0x11
2736#define SQ_GLBL_0__OP__SHIFT 0x12
2737#define SQ_GLBL_0__ENCODING__SHIFT 0x1a
2738#define SQ_GLBL_0__OFFSET_MASK 0x00001FFFL
2739#define SQ_GLBL_0__LDS_MASK 0x00002000L
2740#define SQ_GLBL_0__SEG_MASK 0x0000C000L
2741#define SQ_GLBL_0__GLC_MASK 0x00010000L
2742#define SQ_GLBL_0__SLC_MASK 0x00020000L
2743#define SQ_GLBL_0__OP_MASK 0x01FC0000L
2744#define SQ_GLBL_0__ENCODING_MASK 0xFC000000L
2745//SQ_GLBL_1
2746#define SQ_GLBL_1__ADDR__SHIFT 0x0
2747#define SQ_GLBL_1__DATA__SHIFT 0x8
2748#define SQ_GLBL_1__SADDR__SHIFT 0x10
2749#define SQ_GLBL_1__NV__SHIFT 0x17
2750#define SQ_GLBL_1__VDST__SHIFT 0x18
2751#define SQ_GLBL_1__ADDR_MASK 0x000000FFL
2752#define SQ_GLBL_1__DATA_MASK 0x0000FF00L
2753#define SQ_GLBL_1__SADDR_MASK 0x007F0000L
2754#define SQ_GLBL_1__NV_MASK 0x00800000L
2755#define SQ_GLBL_1__VDST_MASK 0xFF000000L
2756//SQ_INST
2757#define SQ_INST__ENCODING__SHIFT 0x0
2758#define SQ_INST__ENCODING_MASK 0xFFFFFFFFL
2759//SQ_MIMG_0
2760#define SQ_MIMG_0__OPM__SHIFT 0x0
2761#define SQ_MIMG_0__DMASK__SHIFT 0x8
2762#define SQ_MIMG_0__UNORM__SHIFT 0xc
2763#define SQ_MIMG_0__GLC__SHIFT 0xd
2764#define SQ_MIMG_0__DA__SHIFT 0xe
2765#define SQ_MIMG_0__A16__SHIFT 0xf
2766#define SQ_MIMG_0__TFE__SHIFT 0x10
2767#define SQ_MIMG_0__LWE__SHIFT 0x11
2768#define SQ_MIMG_0__OP__SHIFT 0x12
2769#define SQ_MIMG_0__SLC__SHIFT 0x19
2770#define SQ_MIMG_0__ENCODING__SHIFT 0x1a
2771#define SQ_MIMG_0__OPM_MASK 0x00000001L
2772#define SQ_MIMG_0__DMASK_MASK 0x00000F00L
2773#define SQ_MIMG_0__UNORM_MASK 0x00001000L
2774#define SQ_MIMG_0__GLC_MASK 0x00002000L
2775#define SQ_MIMG_0__DA_MASK 0x00004000L
2776#define SQ_MIMG_0__A16_MASK 0x00008000L
2777#define SQ_MIMG_0__TFE_MASK 0x00010000L
2778#define SQ_MIMG_0__LWE_MASK 0x00020000L
2779#define SQ_MIMG_0__OP_MASK 0x01FC0000L
2780#define SQ_MIMG_0__SLC_MASK 0x02000000L
2781#define SQ_MIMG_0__ENCODING_MASK 0xFC000000L
2782//SQ_MIMG_1
2783#define SQ_MIMG_1__VADDR__SHIFT 0x0
2784#define SQ_MIMG_1__VDATA__SHIFT 0x8
2785#define SQ_MIMG_1__SRSRC__SHIFT 0x10
2786#define SQ_MIMG_1__SSAMP__SHIFT 0x15
2787#define SQ_MIMG_1__D16__SHIFT 0x1f
2788#define SQ_MIMG_1__VADDR_MASK 0x000000FFL
2789#define SQ_MIMG_1__VDATA_MASK 0x0000FF00L
2790#define SQ_MIMG_1__SRSRC_MASK 0x001F0000L
2791#define SQ_MIMG_1__SSAMP_MASK 0x03E00000L
2792#define SQ_MIMG_1__D16_MASK 0x80000000L
2793//SQ_MTBUF_0
2794#define SQ_MTBUF_0__OFFSET__SHIFT 0x0
2795#define SQ_MTBUF_0__OFFEN__SHIFT 0xc
2796#define SQ_MTBUF_0__IDXEN__SHIFT 0xd
2797#define SQ_MTBUF_0__GLC__SHIFT 0xe
2798#define SQ_MTBUF_0__OP__SHIFT 0xf
2799#define SQ_MTBUF_0__DFMT__SHIFT 0x13
2800#define SQ_MTBUF_0__NFMT__SHIFT 0x17
2801#define SQ_MTBUF_0__ENCODING__SHIFT 0x1a
2802#define SQ_MTBUF_0__OFFSET_MASK 0x00000FFFL
2803#define SQ_MTBUF_0__OFFEN_MASK 0x00001000L
2804#define SQ_MTBUF_0__IDXEN_MASK 0x00002000L
2805#define SQ_MTBUF_0__GLC_MASK 0x00004000L
2806#define SQ_MTBUF_0__OP_MASK 0x00078000L
2807#define SQ_MTBUF_0__DFMT_MASK 0x00780000L
2808#define SQ_MTBUF_0__NFMT_MASK 0x03800000L
2809#define SQ_MTBUF_0__ENCODING_MASK 0xFC000000L
2810//SQ_MTBUF_1
2811#define SQ_MTBUF_1__VADDR__SHIFT 0x0
2812#define SQ_MTBUF_1__VDATA__SHIFT 0x8
2813#define SQ_MTBUF_1__SRSRC__SHIFT 0x10
2814#define SQ_MTBUF_1__SLC__SHIFT 0x16
2815#define SQ_MTBUF_1__TFE__SHIFT 0x17
2816#define SQ_MTBUF_1__SOFFSET__SHIFT 0x18
2817#define SQ_MTBUF_1__VADDR_MASK 0x000000FFL
2818#define SQ_MTBUF_1__VDATA_MASK 0x0000FF00L
2819#define SQ_MTBUF_1__SRSRC_MASK 0x001F0000L
2820#define SQ_MTBUF_1__SLC_MASK 0x00400000L
2821#define SQ_MTBUF_1__TFE_MASK 0x00800000L
2822#define SQ_MTBUF_1__SOFFSET_MASK 0xFF000000L
2823//SQ_MUBUF_0
2824#define SQ_MUBUF_0__OFFSET__SHIFT 0x0
2825#define SQ_MUBUF_0__OFFEN__SHIFT 0xc
2826#define SQ_MUBUF_0__IDXEN__SHIFT 0xd
2827#define SQ_MUBUF_0__GLC__SHIFT 0xe
2828#define SQ_MUBUF_0__LDS__SHIFT 0x10
2829#define SQ_MUBUF_0__SLC__SHIFT 0x11
2830#define SQ_MUBUF_0__OP__SHIFT 0x12
2831#define SQ_MUBUF_0__ENCODING__SHIFT 0x1a
2832#define SQ_MUBUF_0__OFFSET_MASK 0x00000FFFL
2833#define SQ_MUBUF_0__OFFEN_MASK 0x00001000L
2834#define SQ_MUBUF_0__IDXEN_MASK 0x00002000L
2835#define SQ_MUBUF_0__GLC_MASK 0x00004000L
2836#define SQ_MUBUF_0__LDS_MASK 0x00010000L
2837#define SQ_MUBUF_0__SLC_MASK 0x00020000L
2838#define SQ_MUBUF_0__OP_MASK 0x01FC0000L
2839#define SQ_MUBUF_0__ENCODING_MASK 0xFC000000L
2840//SQ_MUBUF_1
2841#define SQ_MUBUF_1__VADDR__SHIFT 0x0
2842#define SQ_MUBUF_1__VDATA__SHIFT 0x8
2843#define SQ_MUBUF_1__SRSRC__SHIFT 0x10
2844#define SQ_MUBUF_1__TFE__SHIFT 0x17
2845#define SQ_MUBUF_1__SOFFSET__SHIFT 0x18
2846#define SQ_MUBUF_1__VADDR_MASK 0x000000FFL
2847#define SQ_MUBUF_1__VDATA_MASK 0x0000FF00L
2848#define SQ_MUBUF_1__SRSRC_MASK 0x001F0000L
2849#define SQ_MUBUF_1__TFE_MASK 0x00800000L
2850#define SQ_MUBUF_1__SOFFSET_MASK 0xFF000000L
2851//SQ_SCRATCH_0
2852#define SQ_SCRATCH_0__OFFSET__SHIFT 0x0
2853#define SQ_SCRATCH_0__LDS__SHIFT 0xd
2854#define SQ_SCRATCH_0__SEG__SHIFT 0xe
2855#define SQ_SCRATCH_0__GLC__SHIFT 0x10
2856#define SQ_SCRATCH_0__SLC__SHIFT 0x11
2857#define SQ_SCRATCH_0__OP__SHIFT 0x12
2858#define SQ_SCRATCH_0__ENCODING__SHIFT 0x1a
2859#define SQ_SCRATCH_0__OFFSET_MASK 0x00001FFFL
2860#define SQ_SCRATCH_0__LDS_MASK 0x00002000L
2861#define SQ_SCRATCH_0__SEG_MASK 0x0000C000L
2862#define SQ_SCRATCH_0__GLC_MASK 0x00010000L
2863#define SQ_SCRATCH_0__SLC_MASK 0x00020000L
2864#define SQ_SCRATCH_0__OP_MASK 0x01FC0000L
2865#define SQ_SCRATCH_0__ENCODING_MASK 0xFC000000L
2866//SQ_SCRATCH_1
2867#define SQ_SCRATCH_1__ADDR__SHIFT 0x0
2868#define SQ_SCRATCH_1__DATA__SHIFT 0x8
2869#define SQ_SCRATCH_1__SADDR__SHIFT 0x10
2870#define SQ_SCRATCH_1__NV__SHIFT 0x17
2871#define SQ_SCRATCH_1__VDST__SHIFT 0x18
2872#define SQ_SCRATCH_1__ADDR_MASK 0x000000FFL
2873#define SQ_SCRATCH_1__DATA_MASK 0x0000FF00L
2874#define SQ_SCRATCH_1__SADDR_MASK 0x007F0000L
2875#define SQ_SCRATCH_1__NV_MASK 0x00800000L
2876#define SQ_SCRATCH_1__VDST_MASK 0xFF000000L
2877//SQ_SMEM_0
2878#define SQ_SMEM_0__SBASE__SHIFT 0x0
2879#define SQ_SMEM_0__SDATA__SHIFT 0x6
2880#define SQ_SMEM_0__SOFFSET_EN__SHIFT 0xe
2881#define SQ_SMEM_0__NV__SHIFT 0xf
2882#define SQ_SMEM_0__GLC__SHIFT 0x10
2883#define SQ_SMEM_0__IMM__SHIFT 0x11
2884#define SQ_SMEM_0__OP__SHIFT 0x12
2885#define SQ_SMEM_0__ENCODING__SHIFT 0x1a
2886#define SQ_SMEM_0__SBASE_MASK 0x0000003FL
2887#define SQ_SMEM_0__SDATA_MASK 0x00001FC0L
2888#define SQ_SMEM_0__SOFFSET_EN_MASK 0x00004000L
2889#define SQ_SMEM_0__NV_MASK 0x00008000L
2890#define SQ_SMEM_0__GLC_MASK 0x00010000L
2891#define SQ_SMEM_0__IMM_MASK 0x00020000L
2892#define SQ_SMEM_0__OP_MASK 0x03FC0000L
2893#define SQ_SMEM_0__ENCODING_MASK 0xFC000000L
2894//SQ_SMEM_1
2895#define SQ_SMEM_1__OFFSET__SHIFT 0x0
2896#define SQ_SMEM_1__SOFFSET__SHIFT 0x19
2897#define SQ_SMEM_1__OFFSET_MASK 0x001FFFFFL
2898#define SQ_SMEM_1__SOFFSET_MASK 0xFE000000L
2899//SQ_SOP1
2900#define SQ_SOP1__SSRC0__SHIFT 0x0
2901#define SQ_SOP1__OP__SHIFT 0x8
2902#define SQ_SOP1__SDST__SHIFT 0x10
2903#define SQ_SOP1__ENCODING__SHIFT 0x17
2904#define SQ_SOP1__SSRC0_MASK 0x000000FFL
2905#define SQ_SOP1__OP_MASK 0x0000FF00L
2906#define SQ_SOP1__SDST_MASK 0x007F0000L
2907#define SQ_SOP1__ENCODING_MASK 0xFF800000L
2908//SQ_SOP2
2909#define SQ_SOP2__SSRC0__SHIFT 0x0
2910#define SQ_SOP2__SSRC1__SHIFT 0x8
2911#define SQ_SOP2__SDST__SHIFT 0x10
2912#define SQ_SOP2__OP__SHIFT 0x17
2913#define SQ_SOP2__ENCODING__SHIFT 0x1e
2914#define SQ_SOP2__SSRC0_MASK 0x000000FFL
2915#define SQ_SOP2__SSRC1_MASK 0x0000FF00L
2916#define SQ_SOP2__SDST_MASK 0x007F0000L
2917#define SQ_SOP2__OP_MASK 0x3F800000L
2918#define SQ_SOP2__ENCODING_MASK 0xC0000000L
2919//SQ_SOPC
2920#define SQ_SOPC__SSRC0__SHIFT 0x0
2921#define SQ_SOPC__SSRC1__SHIFT 0x8
2922#define SQ_SOPC__OP__SHIFT 0x10
2923#define SQ_SOPC__ENCODING__SHIFT 0x17
2924#define SQ_SOPC__SSRC0_MASK 0x000000FFL
2925#define SQ_SOPC__SSRC1_MASK 0x0000FF00L
2926#define SQ_SOPC__OP_MASK 0x007F0000L
2927#define SQ_SOPC__ENCODING_MASK 0xFF800000L
2928//SQ_SOPK
2929#define SQ_SOPK__SIMM16__SHIFT 0x0
2930#define SQ_SOPK__SDST__SHIFT 0x10
2931#define SQ_SOPK__OP__SHIFT 0x17
2932#define SQ_SOPK__ENCODING__SHIFT 0x1c
2933#define SQ_SOPK__SIMM16_MASK 0x0000FFFFL
2934#define SQ_SOPK__SDST_MASK 0x007F0000L
2935#define SQ_SOPK__OP_MASK 0x0F800000L
2936#define SQ_SOPK__ENCODING_MASK 0xF0000000L
2937//SQ_SOPP
2938#define SQ_SOPP__SIMM16__SHIFT 0x0
2939#define SQ_SOPP__OP__SHIFT 0x10
2940#define SQ_SOPP__ENCODING__SHIFT 0x17
2941#define SQ_SOPP__SIMM16_MASK 0x0000FFFFL
2942#define SQ_SOPP__OP_MASK 0x007F0000L
2943#define SQ_SOPP__ENCODING_MASK 0xFF800000L
2944//SQ_VINTRP
2945#define SQ_VINTRP__VSRC__SHIFT 0x0
2946#define SQ_VINTRP__ATTRCHAN__SHIFT 0x8
2947#define SQ_VINTRP__ATTR__SHIFT 0xa
2948#define SQ_VINTRP__OP__SHIFT 0x10
2949#define SQ_VINTRP__VDST__SHIFT 0x12
2950#define SQ_VINTRP__ENCODING__SHIFT 0x1a
2951#define SQ_VINTRP__VSRC_MASK 0x000000FFL
2952#define SQ_VINTRP__ATTRCHAN_MASK 0x00000300L
2953#define SQ_VINTRP__ATTR_MASK 0x0000FC00L
2954#define SQ_VINTRP__OP_MASK 0x00030000L
2955#define SQ_VINTRP__VDST_MASK 0x03FC0000L
2956#define SQ_VINTRP__ENCODING_MASK 0xFC000000L
2957//SQ_VOP1
2958#define SQ_VOP1__SRC0__SHIFT 0x0
2959#define SQ_VOP1__OP__SHIFT 0x9
2960#define SQ_VOP1__VDST__SHIFT 0x11
2961#define SQ_VOP1__ENCODING__SHIFT 0x19
2962#define SQ_VOP1__SRC0_MASK 0x000001FFL
2963#define SQ_VOP1__OP_MASK 0x0001FE00L
2964#define SQ_VOP1__VDST_MASK 0x01FE0000L
2965#define SQ_VOP1__ENCODING_MASK 0xFE000000L
2966//SQ_VOP2
2967#define SQ_VOP2__SRC0__SHIFT 0x0
2968#define SQ_VOP2__VSRC1__SHIFT 0x9
2969#define SQ_VOP2__VDST__SHIFT 0x11
2970#define SQ_VOP2__OP__SHIFT 0x19
2971#define SQ_VOP2__ENCODING__SHIFT 0x1f
2972#define SQ_VOP2__SRC0_MASK 0x000001FFL
2973#define SQ_VOP2__VSRC1_MASK 0x0001FE00L
2974#define SQ_VOP2__VDST_MASK 0x01FE0000L
2975#define SQ_VOP2__OP_MASK 0x7E000000L
2976#define SQ_VOP2__ENCODING_MASK 0x80000000L
2977//SQ_VOP3P_0
2978#define SQ_VOP3P_0__VDST__SHIFT 0x0
2979#define SQ_VOP3P_0__NEG_HI__SHIFT 0x8
2980#define SQ_VOP3P_0__OP_SEL__SHIFT 0xb
2981#define SQ_VOP3P_0__OP_SEL_HI_2__SHIFT 0xe
2982#define SQ_VOP3P_0__CLAMP__SHIFT 0xf
2983#define SQ_VOP3P_0__OP__SHIFT 0x10
2984#define SQ_VOP3P_0__ENCODING__SHIFT 0x17
2985#define SQ_VOP3P_0__VDST_MASK 0x000000FFL
2986#define SQ_VOP3P_0__NEG_HI_MASK 0x00000700L
2987#define SQ_VOP3P_0__OP_SEL_MASK 0x00003800L
2988#define SQ_VOP3P_0__OP_SEL_HI_2_MASK 0x00004000L
2989#define SQ_VOP3P_0__CLAMP_MASK 0x00008000L
2990#define SQ_VOP3P_0__OP_MASK 0x007F0000L
2991#define SQ_VOP3P_0__ENCODING_MASK 0xFF800000L
2992//SQ_VOP3P_1
2993#define SQ_VOP3P_1__SRC0__SHIFT 0x0
2994#define SQ_VOP3P_1__SRC1__SHIFT 0x9
2995#define SQ_VOP3P_1__SRC2__SHIFT 0x12
2996#define SQ_VOP3P_1__OP_SEL_HI__SHIFT 0x1b
2997#define SQ_VOP3P_1__NEG__SHIFT 0x1d
2998#define SQ_VOP3P_1__SRC0_MASK 0x000001FFL
2999#define SQ_VOP3P_1__SRC1_MASK 0x0003FE00L
3000#define SQ_VOP3P_1__SRC2_MASK 0x07FC0000L
3001#define SQ_VOP3P_1__OP_SEL_HI_MASK 0x18000000L
3002#define SQ_VOP3P_1__NEG_MASK 0xE0000000L
3003//SQ_VOP3_0
3004#define SQ_VOP3_0__VDST__SHIFT 0x0
3005#define SQ_VOP3_0__ABS__SHIFT 0x8
3006#define SQ_VOP3_0__OP_SEL__SHIFT 0xb
3007#define SQ_VOP3_0__CLAMP__SHIFT 0xf
3008#define SQ_VOP3_0__OP__SHIFT 0x10
3009#define SQ_VOP3_0__ENCODING__SHIFT 0x1a
3010#define SQ_VOP3_0__VDST_MASK 0x000000FFL
3011#define SQ_VOP3_0__ABS_MASK 0x00000700L
3012#define SQ_VOP3_0__OP_SEL_MASK 0x00007800L
3013#define SQ_VOP3_0__CLAMP_MASK 0x00008000L
3014#define SQ_VOP3_0__OP_MASK 0x03FF0000L
3015#define SQ_VOP3_0__ENCODING_MASK 0xFC000000L
3016//SQ_VOP3_0_SDST_ENC
3017#define SQ_VOP3_0_SDST_ENC__VDST__SHIFT 0x0
3018#define SQ_VOP3_0_SDST_ENC__SDST__SHIFT 0x8
3019#define SQ_VOP3_0_SDST_ENC__CLAMP__SHIFT 0xf
3020#define SQ_VOP3_0_SDST_ENC__OP__SHIFT 0x10
3021#define SQ_VOP3_0_SDST_ENC__ENCODING__SHIFT 0x1a
3022#define SQ_VOP3_0_SDST_ENC__VDST_MASK 0x000000FFL
3023#define SQ_VOP3_0_SDST_ENC__SDST_MASK 0x00007F00L
3024#define SQ_VOP3_0_SDST_ENC__CLAMP_MASK 0x00008000L
3025#define SQ_VOP3_0_SDST_ENC__OP_MASK 0x03FF0000L
3026#define SQ_VOP3_0_SDST_ENC__ENCODING_MASK 0xFC000000L
3027//SQ_VOP3_1
3028#define SQ_VOP3_1__SRC0__SHIFT 0x0
3029#define SQ_VOP3_1__SRC1__SHIFT 0x9
3030#define SQ_VOP3_1__SRC2__SHIFT 0x12
3031#define SQ_VOP3_1__OMOD__SHIFT 0x1b
3032#define SQ_VOP3_1__NEG__SHIFT 0x1d
3033#define SQ_VOP3_1__SRC0_MASK 0x000001FFL
3034#define SQ_VOP3_1__SRC1_MASK 0x0003FE00L
3035#define SQ_VOP3_1__SRC2_MASK 0x07FC0000L
3036#define SQ_VOP3_1__OMOD_MASK 0x18000000L
3037#define SQ_VOP3_1__NEG_MASK 0xE0000000L
3038//SQ_VOPC
3039#define SQ_VOPC__SRC0__SHIFT 0x0
3040#define SQ_VOPC__VSRC1__SHIFT 0x9
3041#define SQ_VOPC__OP__SHIFT 0x11
3042#define SQ_VOPC__ENCODING__SHIFT 0x19
3043#define SQ_VOPC__SRC0_MASK 0x000001FFL
3044#define SQ_VOPC__VSRC1_MASK 0x0001FE00L
3045#define SQ_VOPC__OP_MASK 0x01FE0000L
3046#define SQ_VOPC__ENCODING_MASK 0xFE000000L
3047//SQ_VOP_DPP
3048#define SQ_VOP_DPP__SRC0__SHIFT 0x0
3049#define SQ_VOP_DPP__DPP_CTRL__SHIFT 0x8
3050#define SQ_VOP_DPP__BOUND_CTRL__SHIFT 0x13
3051#define SQ_VOP_DPP__SRC0_NEG__SHIFT 0x14
3052#define SQ_VOP_DPP__SRC0_ABS__SHIFT 0x15
3053#define SQ_VOP_DPP__SRC1_NEG__SHIFT 0x16
3054#define SQ_VOP_DPP__SRC1_ABS__SHIFT 0x17
3055#define SQ_VOP_DPP__BANK_MASK__SHIFT 0x18
3056#define SQ_VOP_DPP__ROW_MASK__SHIFT 0x1c
3057#define SQ_VOP_DPP__SRC0_MASK 0x000000FFL
3058#define SQ_VOP_DPP__DPP_CTRL_MASK 0x0001FF00L
3059#define SQ_VOP_DPP__BOUND_CTRL_MASK 0x00080000L
3060#define SQ_VOP_DPP__SRC0_NEG_MASK 0x00100000L
3061#define SQ_VOP_DPP__SRC0_ABS_MASK 0x00200000L
3062#define SQ_VOP_DPP__SRC1_NEG_MASK 0x00400000L
3063#define SQ_VOP_DPP__SRC1_ABS_MASK 0x00800000L
3064#define SQ_VOP_DPP__BANK_MASK_MASK 0x0F000000L
3065#define SQ_VOP_DPP__ROW_MASK_MASK 0xF0000000L
3066//SQ_VOP_SDWA
3067#define SQ_VOP_SDWA__SRC0__SHIFT 0x0
3068#define SQ_VOP_SDWA__DST_SEL__SHIFT 0x8
3069#define SQ_VOP_SDWA__DST_UNUSED__SHIFT 0xb
3070#define SQ_VOP_SDWA__CLAMP__SHIFT 0xd
3071#define SQ_VOP_SDWA__OMOD__SHIFT 0xe
3072#define SQ_VOP_SDWA__SRC0_SEL__SHIFT 0x10
3073#define SQ_VOP_SDWA__SRC0_SEXT__SHIFT 0x13
3074#define SQ_VOP_SDWA__SRC0_NEG__SHIFT 0x14
3075#define SQ_VOP_SDWA__SRC0_ABS__SHIFT 0x15
3076#define SQ_VOP_SDWA__S0__SHIFT 0x17
3077#define SQ_VOP_SDWA__SRC1_SEL__SHIFT 0x18
3078#define SQ_VOP_SDWA__SRC1_SEXT__SHIFT 0x1b
3079#define SQ_VOP_SDWA__SRC1_NEG__SHIFT 0x1c
3080#define SQ_VOP_SDWA__SRC1_ABS__SHIFT 0x1d
3081#define SQ_VOP_SDWA__S1__SHIFT 0x1f
3082#define SQ_VOP_SDWA__SRC0_MASK 0x000000FFL
3083#define SQ_VOP_SDWA__DST_SEL_MASK 0x00000700L
3084#define SQ_VOP_SDWA__DST_UNUSED_MASK 0x00001800L
3085#define SQ_VOP_SDWA__CLAMP_MASK 0x00002000L
3086#define SQ_VOP_SDWA__OMOD_MASK 0x0000C000L
3087#define SQ_VOP_SDWA__SRC0_SEL_MASK 0x00070000L
3088#define SQ_VOP_SDWA__SRC0_SEXT_MASK 0x00080000L
3089#define SQ_VOP_SDWA__SRC0_NEG_MASK 0x00100000L
3090#define SQ_VOP_SDWA__SRC0_ABS_MASK 0x00200000L
3091#define SQ_VOP_SDWA__S0_MASK 0x00800000L
3092#define SQ_VOP_SDWA__SRC1_SEL_MASK 0x07000000L
3093#define SQ_VOP_SDWA__SRC1_SEXT_MASK 0x08000000L
3094#define SQ_VOP_SDWA__SRC1_NEG_MASK 0x10000000L
3095#define SQ_VOP_SDWA__SRC1_ABS_MASK 0x20000000L
3096#define SQ_VOP_SDWA__S1_MASK 0x80000000L
3097//SQ_VOP_SDWA_SDST_ENC
3098#define SQ_VOP_SDWA_SDST_ENC__SRC0__SHIFT 0x0
3099#define SQ_VOP_SDWA_SDST_ENC__SDST__SHIFT 0x8
3100#define SQ_VOP_SDWA_SDST_ENC__SD__SHIFT 0xf
3101#define SQ_VOP_SDWA_SDST_ENC__SRC0_SEL__SHIFT 0x10
3102#define SQ_VOP_SDWA_SDST_ENC__SRC0_SEXT__SHIFT 0x13
3103#define SQ_VOP_SDWA_SDST_ENC__SRC0_NEG__SHIFT 0x14
3104#define SQ_VOP_SDWA_SDST_ENC__SRC0_ABS__SHIFT 0x15
3105#define SQ_VOP_SDWA_SDST_ENC__S0__SHIFT 0x17
3106#define SQ_VOP_SDWA_SDST_ENC__SRC1_SEL__SHIFT 0x18
3107#define SQ_VOP_SDWA_SDST_ENC__SRC1_SEXT__SHIFT 0x1b
3108#define SQ_VOP_SDWA_SDST_ENC__SRC1_NEG__SHIFT 0x1c
3109#define SQ_VOP_SDWA_SDST_ENC__SRC1_ABS__SHIFT 0x1d
3110#define SQ_VOP_SDWA_SDST_ENC__S1__SHIFT 0x1f
3111#define SQ_VOP_SDWA_SDST_ENC__SRC0_MASK 0x000000FFL
3112#define SQ_VOP_SDWA_SDST_ENC__SDST_MASK 0x00007F00L
3113#define SQ_VOP_SDWA_SDST_ENC__SD_MASK 0x00008000L
3114#define SQ_VOP_SDWA_SDST_ENC__SRC0_SEL_MASK 0x00070000L
3115#define SQ_VOP_SDWA_SDST_ENC__SRC0_SEXT_MASK 0x00080000L
3116#define SQ_VOP_SDWA_SDST_ENC__SRC0_NEG_MASK 0x00100000L
3117#define SQ_VOP_SDWA_SDST_ENC__SRC0_ABS_MASK 0x00200000L
3118#define SQ_VOP_SDWA_SDST_ENC__S0_MASK 0x00800000L
3119#define SQ_VOP_SDWA_SDST_ENC__SRC1_SEL_MASK 0x07000000L
3120#define SQ_VOP_SDWA_SDST_ENC__SRC1_SEXT_MASK 0x08000000L
3121#define SQ_VOP_SDWA_SDST_ENC__SRC1_NEG_MASK 0x10000000L
3122#define SQ_VOP_SDWA_SDST_ENC__SRC1_ABS_MASK 0x20000000L
3123#define SQ_VOP_SDWA_SDST_ENC__S1_MASK 0x80000000L
3124//SQ_LB_CTR_CTRL
3125#define SQ_LB_CTR_CTRL__START__SHIFT 0x0
3126#define SQ_LB_CTR_CTRL__LOAD__SHIFT 0x1
3127#define SQ_LB_CTR_CTRL__CLEAR__SHIFT 0x2
3128#define SQ_LB_CTR_CTRL__START_MASK 0x00000001L
3129#define SQ_LB_CTR_CTRL__LOAD_MASK 0x00000002L
3130#define SQ_LB_CTR_CTRL__CLEAR_MASK 0x00000004L
3131//SQ_LB_DATA0
3132#define SQ_LB_DATA0__DATA__SHIFT 0x0
3133#define SQ_LB_DATA0__DATA_MASK 0xFFFFFFFFL
3134//SQ_LB_DATA1
3135#define SQ_LB_DATA1__DATA__SHIFT 0x0
3136#define SQ_LB_DATA1__DATA_MASK 0xFFFFFFFFL
3137//SQ_LB_DATA2
3138#define SQ_LB_DATA2__DATA__SHIFT 0x0
3139#define SQ_LB_DATA2__DATA_MASK 0xFFFFFFFFL
3140//SQ_LB_DATA3
3141#define SQ_LB_DATA3__DATA__SHIFT 0x0
3142#define SQ_LB_DATA3__DATA_MASK 0xFFFFFFFFL
3143//SQ_LB_CTR_SEL
3144#define SQ_LB_CTR_SEL__SEL0__SHIFT 0x0
3145#define SQ_LB_CTR_SEL__SEL1__SHIFT 0x4
3146#define SQ_LB_CTR_SEL__SEL2__SHIFT 0x8
3147#define SQ_LB_CTR_SEL__SEL3__SHIFT 0xc
3148#define SQ_LB_CTR_SEL__SEL0_MASK 0x0000000FL
3149#define SQ_LB_CTR_SEL__SEL1_MASK 0x000000F0L
3150#define SQ_LB_CTR_SEL__SEL2_MASK 0x00000F00L
3151#define SQ_LB_CTR_SEL__SEL3_MASK 0x0000F000L
3152//SQ_LB_CTR0_CU
3153#define SQ_LB_CTR0_CU__SH0_MASK__SHIFT 0x0
3154#define SQ_LB_CTR0_CU__SH1_MASK__SHIFT 0x10
3155#define SQ_LB_CTR0_CU__SH0_MASK_MASK 0x0000FFFFL
3156#define SQ_LB_CTR0_CU__SH1_MASK_MASK 0xFFFF0000L
3157//SQ_LB_CTR1_CU
3158#define SQ_LB_CTR1_CU__SH0_MASK__SHIFT 0x0
3159#define SQ_LB_CTR1_CU__SH1_MASK__SHIFT 0x10
3160#define SQ_LB_CTR1_CU__SH0_MASK_MASK 0x0000FFFFL
3161#define SQ_LB_CTR1_CU__SH1_MASK_MASK 0xFFFF0000L
3162//SQ_LB_CTR2_CU
3163#define SQ_LB_CTR2_CU__SH0_MASK__SHIFT 0x0
3164#define SQ_LB_CTR2_CU__SH1_MASK__SHIFT 0x10
3165#define SQ_LB_CTR2_CU__SH0_MASK_MASK 0x0000FFFFL
3166#define SQ_LB_CTR2_CU__SH1_MASK_MASK 0xFFFF0000L
3167//SQ_LB_CTR3_CU
3168#define SQ_LB_CTR3_CU__SH0_MASK__SHIFT 0x0
3169#define SQ_LB_CTR3_CU__SH1_MASK__SHIFT 0x10
3170#define SQ_LB_CTR3_CU__SH0_MASK_MASK 0x0000FFFFL
3171#define SQ_LB_CTR3_CU__SH1_MASK_MASK 0xFFFF0000L
3172//SQC_EDC_CNT
3173#define SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_SEC_COUNT__SHIFT 0x0
3174#define SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_DED_COUNT__SHIFT 0x2
3175#define SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_SEC_COUNT__SHIFT 0x4
3176#define SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_DED_COUNT__SHIFT 0x6
3177#define SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_SEC_COUNT__SHIFT 0x8
3178#define SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_DED_COUNT__SHIFT 0xa
3179#define SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_SEC_COUNT__SHIFT 0xc
3180#define SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_DED_COUNT__SHIFT 0xe
3181#define SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_SEC_COUNT__SHIFT 0x10
3182#define SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_DED_COUNT__SHIFT 0x12
3183#define SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_SEC_COUNT__SHIFT 0x14
3184#define SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_DED_COUNT__SHIFT 0x16
3185#define SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_SEC_COUNT__SHIFT 0x18
3186#define SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_DED_COUNT__SHIFT 0x1a
3187#define SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_SEC_COUNT__SHIFT 0x1c
3188#define SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_DED_COUNT__SHIFT 0x1e
3189#define SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_SEC_COUNT_MASK 0x00000003L
3190#define SQC_EDC_CNT__DATA_CU0_WRITE_DATA_BUF_DED_COUNT_MASK 0x0000000CL
3191#define SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_SEC_COUNT_MASK 0x00000030L
3192#define SQC_EDC_CNT__DATA_CU0_UTCL1_LFIFO_DED_COUNT_MASK 0x000000C0L
3193#define SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_SEC_COUNT_MASK 0x00000300L
3194#define SQC_EDC_CNT__DATA_CU1_WRITE_DATA_BUF_DED_COUNT_MASK 0x00000C00L
3195#define SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_SEC_COUNT_MASK 0x00003000L
3196#define SQC_EDC_CNT__DATA_CU1_UTCL1_LFIFO_DED_COUNT_MASK 0x0000C000L
3197#define SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_SEC_COUNT_MASK 0x00030000L
3198#define SQC_EDC_CNT__DATA_CU2_WRITE_DATA_BUF_DED_COUNT_MASK 0x000C0000L
3199#define SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_SEC_COUNT_MASK 0x00300000L
3200#define SQC_EDC_CNT__DATA_CU2_UTCL1_LFIFO_DED_COUNT_MASK 0x00C00000L
3201#define SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_SEC_COUNT_MASK 0x03000000L
3202#define SQC_EDC_CNT__DATA_CU3_WRITE_DATA_BUF_DED_COUNT_MASK 0x0C000000L
3203#define SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_SEC_COUNT_MASK 0x30000000L
3204#define SQC_EDC_CNT__DATA_CU3_UTCL1_LFIFO_DED_COUNT_MASK 0xC0000000L
3205//SQ_EDC_SEC_CNT
3206#define SQ_EDC_SEC_CNT__LDS_SEC__SHIFT 0x0
3207#define SQ_EDC_SEC_CNT__SGPR_SEC__SHIFT 0x8
3208#define SQ_EDC_SEC_CNT__VGPR_SEC__SHIFT 0x10
3209#define SQ_EDC_SEC_CNT__LDS_SEC_MASK 0x000000FFL
3210#define SQ_EDC_SEC_CNT__SGPR_SEC_MASK 0x0000FF00L
3211#define SQ_EDC_SEC_CNT__VGPR_SEC_MASK 0x00FF0000L
3212//SQ_EDC_DED_CNT
3213#define SQ_EDC_DED_CNT__LDS_DED__SHIFT 0x0
3214#define SQ_EDC_DED_CNT__SGPR_DED__SHIFT 0x8
3215#define SQ_EDC_DED_CNT__VGPR_DED__SHIFT 0x10
3216#define SQ_EDC_DED_CNT__LDS_DED_MASK 0x000000FFL
3217#define SQ_EDC_DED_CNT__SGPR_DED_MASK 0x0000FF00L
3218#define SQ_EDC_DED_CNT__VGPR_DED_MASK 0x00FF0000L
3219//SQ_EDC_INFO
3220#define SQ_EDC_INFO__WAVE_ID__SHIFT 0x0
3221#define SQ_EDC_INFO__SIMD_ID__SHIFT 0x4
3222#define SQ_EDC_INFO__SOURCE__SHIFT 0x6
3223#define SQ_EDC_INFO__VM_ID__SHIFT 0x9
3224#define SQ_EDC_INFO__WAVE_ID_MASK 0x0000000FL
3225#define SQ_EDC_INFO__SIMD_ID_MASK 0x00000030L
3226#define SQ_EDC_INFO__SOURCE_MASK 0x000001C0L
3227#define SQ_EDC_INFO__VM_ID_MASK 0x00001E00L
3228//SQ_EDC_CNT
3229#define SQ_EDC_CNT__LDS_D_SEC_COUNT__SHIFT 0x0
3230#define SQ_EDC_CNT__LDS_D_DED_COUNT__SHIFT 0x2
3231#define SQ_EDC_CNT__LDS_I_SEC_COUNT__SHIFT 0x4
3232#define SQ_EDC_CNT__LDS_I_DED_COUNT__SHIFT 0x6
3233#define SQ_EDC_CNT__SGPR_SEC_COUNT__SHIFT 0x8
3234#define SQ_EDC_CNT__SGPR_DED_COUNT__SHIFT 0xa
3235#define SQ_EDC_CNT__VGPR0_SEC_COUNT__SHIFT 0xc
3236#define SQ_EDC_CNT__VGPR0_DED_COUNT__SHIFT 0xe
3237#define SQ_EDC_CNT__VGPR1_SEC_COUNT__SHIFT 0x10
3238#define SQ_EDC_CNT__VGPR1_DED_COUNT__SHIFT 0x12
3239#define SQ_EDC_CNT__VGPR2_SEC_COUNT__SHIFT 0x14
3240#define SQ_EDC_CNT__VGPR2_DED_COUNT__SHIFT 0x16
3241#define SQ_EDC_CNT__VGPR3_SEC_COUNT__SHIFT 0x18
3242#define SQ_EDC_CNT__VGPR3_DED_COUNT__SHIFT 0x1a
3243#define SQ_EDC_CNT__LDS_D_SEC_COUNT_MASK 0x00000003L
3244#define SQ_EDC_CNT__LDS_D_DED_COUNT_MASK 0x0000000CL
3245#define SQ_EDC_CNT__LDS_I_SEC_COUNT_MASK 0x00000030L
3246#define SQ_EDC_CNT__LDS_I_DED_COUNT_MASK 0x000000C0L
3247#define SQ_EDC_CNT__SGPR_SEC_COUNT_MASK 0x00000300L
3248#define SQ_EDC_CNT__SGPR_DED_COUNT_MASK 0x00000C00L
3249#define SQ_EDC_CNT__VGPR0_SEC_COUNT_MASK 0x00003000L
3250#define SQ_EDC_CNT__VGPR0_DED_COUNT_MASK 0x0000C000L
3251#define SQ_EDC_CNT__VGPR1_SEC_COUNT_MASK 0x00030000L
3252#define SQ_EDC_CNT__VGPR1_DED_COUNT_MASK 0x000C0000L
3253#define SQ_EDC_CNT__VGPR2_SEC_COUNT_MASK 0x00300000L
3254#define SQ_EDC_CNT__VGPR2_DED_COUNT_MASK 0x00C00000L
3255#define SQ_EDC_CNT__VGPR3_SEC_COUNT_MASK 0x03000000L
3256#define SQ_EDC_CNT__VGPR3_DED_COUNT_MASK 0x0C000000L
3257//SQ_EDC_FUE_CNTL
3258#define SQ_EDC_FUE_CNTL__BLOCK_FUE_FLAGS__SHIFT 0x0
3259#define SQ_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES__SHIFT 0x10
3260#define SQ_EDC_FUE_CNTL__BLOCK_FUE_FLAGS_MASK 0x0000FFFFL
3261#define SQ_EDC_FUE_CNTL__FUE_INTERRUPT_ENABLES_MASK 0xFFFF0000L
3262//SQ_THREAD_TRACE_WORD_CMN
3263#define SQ_THREAD_TRACE_WORD_CMN__TOKEN_TYPE__SHIFT 0x0
3264#define SQ_THREAD_TRACE_WORD_CMN__TIME_DELTA__SHIFT 0x4
3265#define SQ_THREAD_TRACE_WORD_CMN__TOKEN_TYPE_MASK 0x000FL
3266#define SQ_THREAD_TRACE_WORD_CMN__TIME_DELTA_MASK 0x0010L
3267//SQ_THREAD_TRACE_WORD_EVENT
3268#define SQ_THREAD_TRACE_WORD_EVENT__TOKEN_TYPE__SHIFT 0x0
3269#define SQ_THREAD_TRACE_WORD_EVENT__TIME_DELTA__SHIFT 0x4
3270#define SQ_THREAD_TRACE_WORD_EVENT__SH_ID__SHIFT 0x5
3271#define SQ_THREAD_TRACE_WORD_EVENT__STAGE__SHIFT 0x6
3272#define SQ_THREAD_TRACE_WORD_EVENT__EVENT_TYPE__SHIFT 0xa
3273#define SQ_THREAD_TRACE_WORD_EVENT__TOKEN_TYPE_MASK 0x000FL
3274#define SQ_THREAD_TRACE_WORD_EVENT__TIME_DELTA_MASK 0x0010L
3275#define SQ_THREAD_TRACE_WORD_EVENT__SH_ID_MASK 0x0020L
3276#define SQ_THREAD_TRACE_WORD_EVENT__STAGE_MASK 0x01C0L
3277#define SQ_THREAD_TRACE_WORD_EVENT__EVENT_TYPE_MASK 0xFC00L
3278//SQ_THREAD_TRACE_WORD_INST
3279#define SQ_THREAD_TRACE_WORD_INST__TOKEN_TYPE__SHIFT 0x0
3280#define SQ_THREAD_TRACE_WORD_INST__TIME_DELTA__SHIFT 0x4
3281#define SQ_THREAD_TRACE_WORD_INST__WAVE_ID__SHIFT 0x5
3282#define SQ_THREAD_TRACE_WORD_INST__SIMD_ID__SHIFT 0x9
3283#define SQ_THREAD_TRACE_WORD_INST__INST_TYPE__SHIFT 0xb
3284#define SQ_THREAD_TRACE_WORD_INST__TOKEN_TYPE_MASK 0x000FL
3285#define SQ_THREAD_TRACE_WORD_INST__TIME_DELTA_MASK 0x0010L
3286#define SQ_THREAD_TRACE_WORD_INST__WAVE_ID_MASK 0x01E0L
3287#define SQ_THREAD_TRACE_WORD_INST__SIMD_ID_MASK 0x0600L
3288#define SQ_THREAD_TRACE_WORD_INST__INST_TYPE_MASK 0xF800L
3289//SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2
3290#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TOKEN_TYPE__SHIFT 0x0
3291#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TIME_DELTA__SHIFT 0x4
3292#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__WAVE_ID__SHIFT 0x5
3293#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__SIMD_ID__SHIFT 0x9
3294#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TRAP_ERROR__SHIFT 0xf
3295#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__PC_LO__SHIFT 0x10
3296#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL
3297#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TIME_DELTA_MASK 0x00000010L
3298#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__WAVE_ID_MASK 0x000001E0L
3299#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__SIMD_ID_MASK 0x00000600L
3300#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TRAP_ERROR_MASK 0x00008000L
3301#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__PC_LO_MASK 0xFFFF0000L
3302//SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2
3303#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TOKEN_TYPE__SHIFT 0x0
3304#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TIME_DELTA__SHIFT 0x4
3305#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SH_ID__SHIFT 0x5
3306#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__CU_ID__SHIFT 0x6
3307#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__WAVE_ID__SHIFT 0xa
3308#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SIMD_ID__SHIFT 0xe
3309#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__DATA_LO__SHIFT 0x10
3310#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL
3311#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TIME_DELTA_MASK 0x00000010L
3312#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SH_ID_MASK 0x00000020L
3313#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__CU_ID_MASK 0x000003C0L
3314#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__WAVE_ID_MASK 0x00003C00L
3315#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SIMD_ID_MASK 0x0000C000L
3316#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__DATA_LO_MASK 0xFFFF0000L
3317//SQ_THREAD_TRACE_WORD_ISSUE
3318#define SQ_THREAD_TRACE_WORD_ISSUE__TOKEN_TYPE__SHIFT 0x0
3319#define SQ_THREAD_TRACE_WORD_ISSUE__TIME_DELTA__SHIFT 0x4
3320#define SQ_THREAD_TRACE_WORD_ISSUE__SIMD_ID__SHIFT 0x5
3321#define SQ_THREAD_TRACE_WORD_ISSUE__INST0__SHIFT 0x8
3322#define SQ_THREAD_TRACE_WORD_ISSUE__INST1__SHIFT 0xa
3323#define SQ_THREAD_TRACE_WORD_ISSUE__INST2__SHIFT 0xc
3324#define SQ_THREAD_TRACE_WORD_ISSUE__INST3__SHIFT 0xe
3325#define SQ_THREAD_TRACE_WORD_ISSUE__INST4__SHIFT 0x10
3326#define SQ_THREAD_TRACE_WORD_ISSUE__INST5__SHIFT 0x12
3327#define SQ_THREAD_TRACE_WORD_ISSUE__INST6__SHIFT 0x14
3328#define SQ_THREAD_TRACE_WORD_ISSUE__INST7__SHIFT 0x16
3329#define SQ_THREAD_TRACE_WORD_ISSUE__INST8__SHIFT 0x18
3330#define SQ_THREAD_TRACE_WORD_ISSUE__INST9__SHIFT 0x1a
3331#define SQ_THREAD_TRACE_WORD_ISSUE__TOKEN_TYPE_MASK 0x0000000FL
3332#define SQ_THREAD_TRACE_WORD_ISSUE__TIME_DELTA_MASK 0x00000010L
3333#define SQ_THREAD_TRACE_WORD_ISSUE__SIMD_ID_MASK 0x00000060L
3334#define SQ_THREAD_TRACE_WORD_ISSUE__INST0_MASK 0x00000300L
3335#define SQ_THREAD_TRACE_WORD_ISSUE__INST1_MASK 0x00000C00L
3336#define SQ_THREAD_TRACE_WORD_ISSUE__INST2_MASK 0x00003000L
3337#define SQ_THREAD_TRACE_WORD_ISSUE__INST3_MASK 0x0000C000L
3338#define SQ_THREAD_TRACE_WORD_ISSUE__INST4_MASK 0x00030000L
3339#define SQ_THREAD_TRACE_WORD_ISSUE__INST5_MASK 0x000C0000L
3340#define SQ_THREAD_TRACE_WORD_ISSUE__INST6_MASK 0x00300000L
3341#define SQ_THREAD_TRACE_WORD_ISSUE__INST7_MASK 0x00C00000L
3342#define SQ_THREAD_TRACE_WORD_ISSUE__INST8_MASK 0x03000000L
3343#define SQ_THREAD_TRACE_WORD_ISSUE__INST9_MASK 0x0C000000L
3344//SQ_THREAD_TRACE_WORD_MISC
3345#define SQ_THREAD_TRACE_WORD_MISC__TOKEN_TYPE__SHIFT 0x0
3346#define SQ_THREAD_TRACE_WORD_MISC__TIME_DELTA__SHIFT 0x4
3347#define SQ_THREAD_TRACE_WORD_MISC__SH_ID__SHIFT 0xc
3348#define SQ_THREAD_TRACE_WORD_MISC__MISC_TOKEN_TYPE__SHIFT 0xd
3349#define SQ_THREAD_TRACE_WORD_MISC__TOKEN_TYPE_MASK 0x000FL
3350#define SQ_THREAD_TRACE_WORD_MISC__TIME_DELTA_MASK 0x0FF0L
3351#define SQ_THREAD_TRACE_WORD_MISC__SH_ID_MASK 0x1000L
3352#define SQ_THREAD_TRACE_WORD_MISC__MISC_TOKEN_TYPE_MASK 0xE000L
3353//SQ_THREAD_TRACE_WORD_PERF_1_OF_2
3354#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TOKEN_TYPE__SHIFT 0x0
3355#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TIME_DELTA__SHIFT 0x4
3356#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__SH_ID__SHIFT 0x5
3357#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CU_ID__SHIFT 0x6
3358#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR_BANK__SHIFT 0xa
3359#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR0__SHIFT 0xc
3360#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR1_LO__SHIFT 0x19
3361#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL
3362#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TIME_DELTA_MASK 0x00000010L
3363#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__SH_ID_MASK 0x00000020L
3364#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CU_ID_MASK 0x000003C0L
3365#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR_BANK_MASK 0x00000C00L
3366#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR0_MASK 0x01FFF000L
3367#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR1_LO_MASK 0xFE000000L
3368//SQ_THREAD_TRACE_WORD_REG_1_OF_2
3369#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TOKEN_TYPE__SHIFT 0x0
3370#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TIME_DELTA__SHIFT 0x4
3371#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__PIPE_ID__SHIFT 0x5
3372#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__ME_ID__SHIFT 0x7
3373#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_DROPPED_PREV__SHIFT 0x9
3374#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_TYPE__SHIFT 0xa
3375#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_PRIV__SHIFT 0xe
3376#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_OP__SHIFT 0xf
3377#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_ADDR__SHIFT 0x10
3378#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL
3379#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TIME_DELTA_MASK 0x00000010L
3380#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__PIPE_ID_MASK 0x00000060L
3381#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__ME_ID_MASK 0x00000180L
3382#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_DROPPED_PREV_MASK 0x00000200L
3383#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_TYPE_MASK 0x00001C00L
3384#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_PRIV_MASK 0x00004000L
3385#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_OP_MASK 0x00008000L
3386#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_ADDR_MASK 0xFFFF0000L
3387//SQ_THREAD_TRACE_WORD_REG_2_OF_2
3388#define SQ_THREAD_TRACE_WORD_REG_2_OF_2__DATA__SHIFT 0x0
3389#define SQ_THREAD_TRACE_WORD_REG_2_OF_2__DATA_MASK 0xFFFFFFFFL
3390//SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2
3391#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TOKEN_TYPE__SHIFT 0x0
3392#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TIME_DELTA__SHIFT 0x4
3393#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__PIPE_ID__SHIFT 0x5
3394#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__ME_ID__SHIFT 0x7
3395#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__REG_ADDR__SHIFT 0x9
3396#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__DATA_LO__SHIFT 0x10
3397#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL
3398#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TIME_DELTA_MASK 0x00000010L
3399#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__PIPE_ID_MASK 0x00000060L
3400#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__ME_ID_MASK 0x00000180L
3401#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__REG_ADDR_MASK 0x0000FE00L
3402#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__DATA_LO_MASK 0xFFFF0000L
3403//SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2
3404#define SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2__DATA_HI__SHIFT 0x0
3405#define SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2__DATA_HI_MASK 0x0000FFFFL
3406//SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2
3407#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TOKEN_TYPE__SHIFT 0x0
3408#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TIME_LO__SHIFT 0x10
3409#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TOKEN_TYPE_MASK 0x0000000FL
3410#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TIME_LO_MASK 0xFFFF0000L
3411//SQ_THREAD_TRACE_WORD_WAVE
3412#define SQ_THREAD_TRACE_WORD_WAVE__TOKEN_TYPE__SHIFT 0x0
3413#define SQ_THREAD_TRACE_WORD_WAVE__TIME_DELTA__SHIFT 0x4
3414#define SQ_THREAD_TRACE_WORD_WAVE__SH_ID__SHIFT 0x5
3415#define SQ_THREAD_TRACE_WORD_WAVE__CU_ID__SHIFT 0x6
3416#define SQ_THREAD_TRACE_WORD_WAVE__WAVE_ID__SHIFT 0xa
3417#define SQ_THREAD_TRACE_WORD_WAVE__SIMD_ID__SHIFT 0xe
3418#define SQ_THREAD_TRACE_WORD_WAVE__TOKEN_TYPE_MASK 0x000FL
3419#define SQ_THREAD_TRACE_WORD_WAVE__TIME_DELTA_MASK 0x0010L
3420#define SQ_THREAD_TRACE_WORD_WAVE__SH_ID_MASK 0x0020L
3421#define SQ_THREAD_TRACE_WORD_WAVE__CU_ID_MASK 0x03C0L
3422#define SQ_THREAD_TRACE_WORD_WAVE__WAVE_ID_MASK 0x3C00L
3423#define SQ_THREAD_TRACE_WORD_WAVE__SIMD_ID_MASK 0xC000L
3424//SQ_THREAD_TRACE_WORD_WAVE_START
3425#define SQ_THREAD_TRACE_WORD_WAVE_START__TOKEN_TYPE__SHIFT 0x0
3426#define SQ_THREAD_TRACE_WORD_WAVE_START__TIME_DELTA__SHIFT 0x4
3427#define SQ_THREAD_TRACE_WORD_WAVE_START__SH_ID__SHIFT 0x5
3428#define SQ_THREAD_TRACE_WORD_WAVE_START__CU_ID__SHIFT 0x6
3429#define SQ_THREAD_TRACE_WORD_WAVE_START__WAVE_ID__SHIFT 0xa
3430#define SQ_THREAD_TRACE_WORD_WAVE_START__SIMD_ID__SHIFT 0xe
3431#define SQ_THREAD_TRACE_WORD_WAVE_START__DISPATCHER__SHIFT 0x10
3432#define SQ_THREAD_TRACE_WORD_WAVE_START__VS_NO_ALLOC_OR_GROUPED__SHIFT 0x15
3433#define SQ_THREAD_TRACE_WORD_WAVE_START__COUNT__SHIFT 0x16
3434#define SQ_THREAD_TRACE_WORD_WAVE_START__TG_ID__SHIFT 0x1d
3435#define SQ_THREAD_TRACE_WORD_WAVE_START__TOKEN_TYPE_MASK 0x0000000FL
3436#define SQ_THREAD_TRACE_WORD_WAVE_START__TIME_DELTA_MASK 0x00000010L
3437#define SQ_THREAD_TRACE_WORD_WAVE_START__SH_ID_MASK 0x00000020L
3438#define SQ_THREAD_TRACE_WORD_WAVE_START__CU_ID_MASK 0x000003C0L
3439#define SQ_THREAD_TRACE_WORD_WAVE_START__WAVE_ID_MASK 0x00003C00L
3440#define SQ_THREAD_TRACE_WORD_WAVE_START__SIMD_ID_MASK 0x0000C000L
3441#define SQ_THREAD_TRACE_WORD_WAVE_START__DISPATCHER_MASK 0x001F0000L
3442#define SQ_THREAD_TRACE_WORD_WAVE_START__VS_NO_ALLOC_OR_GROUPED_MASK 0x00200000L
3443#define SQ_THREAD_TRACE_WORD_WAVE_START__COUNT_MASK 0x1FC00000L
3444#define SQ_THREAD_TRACE_WORD_WAVE_START__TG_ID_MASK 0xE0000000L
3445//SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2
3446#define SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2__PC_HI__SHIFT 0x0
3447#define SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2__PC_HI_MASK 0x00FFFFFFL
3448//SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2
3449#define SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2__DATA_HI__SHIFT 0x0
3450#define SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2__DATA_HI_MASK 0xFFFFL
3451//SQ_THREAD_TRACE_WORD_PERF_2_OF_2
3452#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR1_HI__SHIFT 0x0
3453#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR2__SHIFT 0x6
3454#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR3__SHIFT 0x13
3455#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR1_HI_MASK 0x0000003FL
3456#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR2_MASK 0x0007FFC0L
3457#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR3_MASK 0xFFF80000L
3458//SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2
3459#define SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2__TIME_HI__SHIFT 0x0
3460#define SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2__TIME_HI_MASK 0xFFFFFFFFL
3461//SQ_WREXEC_EXEC_HI
3462#define SQ_WREXEC_EXEC_HI__ADDR_HI__SHIFT 0x0
3463#define SQ_WREXEC_EXEC_HI__FIRST_WAVE__SHIFT 0x1a
3464#define SQ_WREXEC_EXEC_HI__ATC__SHIFT 0x1b
3465#define SQ_WREXEC_EXEC_HI__MTYPE__SHIFT 0x1c
3466#define SQ_WREXEC_EXEC_HI__MSB__SHIFT 0x1f
3467#define SQ_WREXEC_EXEC_HI__ADDR_HI_MASK 0x0000FFFFL
3468#define SQ_WREXEC_EXEC_HI__FIRST_WAVE_MASK 0x04000000L
3469#define SQ_WREXEC_EXEC_HI__ATC_MASK 0x08000000L
3470#define SQ_WREXEC_EXEC_HI__MTYPE_MASK 0x70000000L
3471#define SQ_WREXEC_EXEC_HI__MSB_MASK 0x80000000L
3472//SQ_WREXEC_EXEC_LO
3473#define SQ_WREXEC_EXEC_LO__ADDR_LO__SHIFT 0x0
3474#define SQ_WREXEC_EXEC_LO__ADDR_LO_MASK 0xFFFFFFFFL
3475//SQ_BUF_RSRC_WORD0
3476#define SQ_BUF_RSRC_WORD0__BASE_ADDRESS__SHIFT 0x0
3477#define SQ_BUF_RSRC_WORD0__BASE_ADDRESS_MASK 0xFFFFFFFFL
3478//SQ_BUF_RSRC_WORD1
3479#define SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT 0x0
3480#define SQ_BUF_RSRC_WORD1__STRIDE__SHIFT 0x10
3481#define SQ_BUF_RSRC_WORD1__CACHE_SWIZZLE__SHIFT 0x1e
3482#define SQ_BUF_RSRC_WORD1__SWIZZLE_ENABLE__SHIFT 0x1f
3483#define SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI_MASK 0x0000FFFFL
3484#define SQ_BUF_RSRC_WORD1__STRIDE_MASK 0x3FFF0000L
3485#define SQ_BUF_RSRC_WORD1__CACHE_SWIZZLE_MASK 0x40000000L
3486#define SQ_BUF_RSRC_WORD1__SWIZZLE_ENABLE_MASK 0x80000000L
3487//SQ_BUF_RSRC_WORD2
3488#define SQ_BUF_RSRC_WORD2__NUM_RECORDS__SHIFT 0x0
3489#define SQ_BUF_RSRC_WORD2__NUM_RECORDS_MASK 0xFFFFFFFFL
3490//SQ_BUF_RSRC_WORD3
3491#define SQ_BUF_RSRC_WORD3__DST_SEL_X__SHIFT 0x0
3492#define SQ_BUF_RSRC_WORD3__DST_SEL_Y__SHIFT 0x3
3493#define SQ_BUF_RSRC_WORD3__DST_SEL_Z__SHIFT 0x6
3494#define SQ_BUF_RSRC_WORD3__DST_SEL_W__SHIFT 0x9
3495#define SQ_BUF_RSRC_WORD3__NUM_FORMAT__SHIFT 0xc
3496#define SQ_BUF_RSRC_WORD3__DATA_FORMAT__SHIFT 0xf
3497#define SQ_BUF_RSRC_WORD3__USER_VM_ENABLE__SHIFT 0x13
3498#define SQ_BUF_RSRC_WORD3__USER_VM_MODE__SHIFT 0x14
3499#define SQ_BUF_RSRC_WORD3__INDEX_STRIDE__SHIFT 0x15
3500#define SQ_BUF_RSRC_WORD3__ADD_TID_ENABLE__SHIFT 0x17
3501#define SQ_BUF_RSRC_WORD3__NV__SHIFT 0x1b
3502#define SQ_BUF_RSRC_WORD3__TYPE__SHIFT 0x1e
3503#define SQ_BUF_RSRC_WORD3__DST_SEL_X_MASK 0x00000007L
3504#define SQ_BUF_RSRC_WORD3__DST_SEL_Y_MASK 0x00000038L
3505#define SQ_BUF_RSRC_WORD3__DST_SEL_Z_MASK 0x000001C0L
3506#define SQ_BUF_RSRC_WORD3__DST_SEL_W_MASK 0x00000E00L
3507#define SQ_BUF_RSRC_WORD3__NUM_FORMAT_MASK 0x00007000L
3508#define SQ_BUF_RSRC_WORD3__DATA_FORMAT_MASK 0x00078000L
3509#define SQ_BUF_RSRC_WORD3__USER_VM_ENABLE_MASK 0x00080000L
3510#define SQ_BUF_RSRC_WORD3__USER_VM_MODE_MASK 0x00100000L
3511#define SQ_BUF_RSRC_WORD3__INDEX_STRIDE_MASK 0x00600000L
3512#define SQ_BUF_RSRC_WORD3__ADD_TID_ENABLE_MASK 0x00800000L
3513#define SQ_BUF_RSRC_WORD3__NV_MASK 0x08000000L
3514#define SQ_BUF_RSRC_WORD3__TYPE_MASK 0xC0000000L
3515//SQ_IMG_RSRC_WORD0
3516#define SQ_IMG_RSRC_WORD0__BASE_ADDRESS__SHIFT 0x0
3517#define SQ_IMG_RSRC_WORD0__BASE_ADDRESS_MASK 0xFFFFFFFFL
3518//SQ_IMG_RSRC_WORD1
3519#define SQ_IMG_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT 0x0
3520#define SQ_IMG_RSRC_WORD1__MIN_LOD__SHIFT 0x8
3521#define SQ_IMG_RSRC_WORD1__DATA_FORMAT__SHIFT 0x14
3522#define SQ_IMG_RSRC_WORD1__NUM_FORMAT__SHIFT 0x1a
3523#define SQ_IMG_RSRC_WORD1__NV__SHIFT 0x1e
3524#define SQ_IMG_RSRC_WORD1__META_DIRECT__SHIFT 0x1f
3525#define SQ_IMG_RSRC_WORD1__BASE_ADDRESS_HI_MASK 0x000000FFL
3526#define SQ_IMG_RSRC_WORD1__MIN_LOD_MASK 0x000FFF00L
3527#define SQ_IMG_RSRC_WORD1__DATA_FORMAT_MASK 0x03F00000L
3528#define SQ_IMG_RSRC_WORD1__NUM_FORMAT_MASK 0x3C000000L
3529#define SQ_IMG_RSRC_WORD1__NV_MASK 0x40000000L
3530#define SQ_IMG_RSRC_WORD1__META_DIRECT_MASK 0x80000000L
3531//SQ_IMG_RSRC_WORD2
3532#define SQ_IMG_RSRC_WORD2__WIDTH__SHIFT 0x0
3533#define SQ_IMG_RSRC_WORD2__HEIGHT__SHIFT 0xe
3534#define SQ_IMG_RSRC_WORD2__PERF_MOD__SHIFT 0x1c
3535#define SQ_IMG_RSRC_WORD2__WIDTH_MASK 0x00003FFFL
3536#define SQ_IMG_RSRC_WORD2__HEIGHT_MASK 0x0FFFC000L
3537#define SQ_IMG_RSRC_WORD2__PERF_MOD_MASK 0x70000000L
3538//SQ_IMG_RSRC_WORD3
3539#define SQ_IMG_RSRC_WORD3__DST_SEL_X__SHIFT 0x0
3540#define SQ_IMG_RSRC_WORD3__DST_SEL_Y__SHIFT 0x3
3541#define SQ_IMG_RSRC_WORD3__DST_SEL_Z__SHIFT 0x6
3542#define SQ_IMG_RSRC_WORD3__DST_SEL_W__SHIFT 0x9
3543#define SQ_IMG_RSRC_WORD3__BASE_LEVEL__SHIFT 0xc
3544#define SQ_IMG_RSRC_WORD3__LAST_LEVEL__SHIFT 0x10
3545#define SQ_IMG_RSRC_WORD3__SW_MODE__SHIFT 0x14
3546#define SQ_IMG_RSRC_WORD3__TYPE__SHIFT 0x1c
3547#define SQ_IMG_RSRC_WORD3__DST_SEL_X_MASK 0x00000007L
3548#define SQ_IMG_RSRC_WORD3__DST_SEL_Y_MASK 0x00000038L
3549#define SQ_IMG_RSRC_WORD3__DST_SEL_Z_MASK 0x000001C0L
3550#define SQ_IMG_RSRC_WORD3__DST_SEL_W_MASK 0x00000E00L
3551#define SQ_IMG_RSRC_WORD3__BASE_LEVEL_MASK 0x0000F000L
3552#define SQ_IMG_RSRC_WORD3__LAST_LEVEL_MASK 0x000F0000L
3553#define SQ_IMG_RSRC_WORD3__SW_MODE_MASK 0x01F00000L
3554#define SQ_IMG_RSRC_WORD3__TYPE_MASK 0xF0000000L
3555//SQ_IMG_RSRC_WORD4
3556#define SQ_IMG_RSRC_WORD4__DEPTH__SHIFT 0x0
3557#define SQ_IMG_RSRC_WORD4__PITCH__SHIFT 0xd
3558#define SQ_IMG_RSRC_WORD4__BC_SWIZZLE__SHIFT 0x1d
3559#define SQ_IMG_RSRC_WORD4__DEPTH_MASK 0x00001FFFL
3560#define SQ_IMG_RSRC_WORD4__PITCH_MASK 0x1FFFE000L
3561#define SQ_IMG_RSRC_WORD4__BC_SWIZZLE_MASK 0xE0000000L
3562//SQ_IMG_RSRC_WORD5
3563#define SQ_IMG_RSRC_WORD5__BASE_ARRAY__SHIFT 0x0
3564#define SQ_IMG_RSRC_WORD5__ARRAY_PITCH__SHIFT 0xd
3565#define SQ_IMG_RSRC_WORD5__META_DATA_ADDRESS__SHIFT 0x11
3566#define SQ_IMG_RSRC_WORD5__META_LINEAR__SHIFT 0x19
3567#define SQ_IMG_RSRC_WORD5__META_PIPE_ALIGNED__SHIFT 0x1a
3568#define SQ_IMG_RSRC_WORD5__META_RB_ALIGNED__SHIFT 0x1b
3569#define SQ_IMG_RSRC_WORD5__MAX_MIP__SHIFT 0x1c
3570#define SQ_IMG_RSRC_WORD5__BASE_ARRAY_MASK 0x00001FFFL
3571#define SQ_IMG_RSRC_WORD5__ARRAY_PITCH_MASK 0x0001E000L
3572#define SQ_IMG_RSRC_WORD5__META_DATA_ADDRESS_MASK 0x01FE0000L
3573#define SQ_IMG_RSRC_WORD5__META_LINEAR_MASK 0x02000000L
3574#define SQ_IMG_RSRC_WORD5__META_PIPE_ALIGNED_MASK 0x04000000L
3575#define SQ_IMG_RSRC_WORD5__META_RB_ALIGNED_MASK 0x08000000L
3576#define SQ_IMG_RSRC_WORD5__MAX_MIP_MASK 0xF0000000L
3577//SQ_IMG_RSRC_WORD6
3578#define SQ_IMG_RSRC_WORD6__MIN_LOD_WARN__SHIFT 0x0
3579#define SQ_IMG_RSRC_WORD6__COUNTER_BANK_ID__SHIFT 0xc
3580#define SQ_IMG_RSRC_WORD6__LOD_HDW_CNT_EN__SHIFT 0x14
3581#define SQ_IMG_RSRC_WORD6__COMPRESSION_EN__SHIFT 0x15
3582#define SQ_IMG_RSRC_WORD6__ALPHA_IS_ON_MSB__SHIFT 0x16
3583#define SQ_IMG_RSRC_WORD6__COLOR_TRANSFORM__SHIFT 0x17
3584#define SQ_IMG_RSRC_WORD6__LOST_ALPHA_BITS__SHIFT 0x18
3585#define SQ_IMG_RSRC_WORD6__LOST_COLOR_BITS__SHIFT 0x1c
3586#define SQ_IMG_RSRC_WORD6__MIN_LOD_WARN_MASK 0x00000FFFL
3587#define SQ_IMG_RSRC_WORD6__COUNTER_BANK_ID_MASK 0x000FF000L
3588#define SQ_IMG_RSRC_WORD6__LOD_HDW_CNT_EN_MASK 0x00100000L
3589#define SQ_IMG_RSRC_WORD6__COMPRESSION_EN_MASK 0x00200000L
3590#define SQ_IMG_RSRC_WORD6__ALPHA_IS_ON_MSB_MASK 0x00400000L
3591#define SQ_IMG_RSRC_WORD6__COLOR_TRANSFORM_MASK 0x00800000L
3592#define SQ_IMG_RSRC_WORD6__LOST_ALPHA_BITS_MASK 0x0F000000L
3593#define SQ_IMG_RSRC_WORD6__LOST_COLOR_BITS_MASK 0xF0000000L
3594//SQ_IMG_RSRC_WORD7
3595#define SQ_IMG_RSRC_WORD7__META_DATA_ADDRESS__SHIFT 0x0
3596#define SQ_IMG_RSRC_WORD7__META_DATA_ADDRESS_MASK 0xFFFFFFFFL
3597//SQ_IMG_SAMP_WORD0
3598#define SQ_IMG_SAMP_WORD0__CLAMP_X__SHIFT 0x0
3599#define SQ_IMG_SAMP_WORD0__CLAMP_Y__SHIFT 0x3
3600#define SQ_IMG_SAMP_WORD0__CLAMP_Z__SHIFT 0x6
3601#define SQ_IMG_SAMP_WORD0__MAX_ANISO_RATIO__SHIFT 0x9
3602#define SQ_IMG_SAMP_WORD0__DEPTH_COMPARE_FUNC__SHIFT 0xc
3603#define SQ_IMG_SAMP_WORD0__FORCE_UNNORMALIZED__SHIFT 0xf
3604#define SQ_IMG_SAMP_WORD0__ANISO_THRESHOLD__SHIFT 0x10
3605#define SQ_IMG_SAMP_WORD0__MC_COORD_TRUNC__SHIFT 0x13
3606#define SQ_IMG_SAMP_WORD0__FORCE_DEGAMMA__SHIFT 0x14
3607#define SQ_IMG_SAMP_WORD0__ANISO_BIAS__SHIFT 0x15
3608#define SQ_IMG_SAMP_WORD0__TRUNC_COORD__SHIFT 0x1b
3609#define SQ_IMG_SAMP_WORD0__DISABLE_CUBE_WRAP__SHIFT 0x1c
3610#define SQ_IMG_SAMP_WORD0__FILTER_MODE__SHIFT 0x1d
3611#define SQ_IMG_SAMP_WORD0__COMPAT_MODE__SHIFT 0x1f
3612#define SQ_IMG_SAMP_WORD0__CLAMP_X_MASK 0x00000007L
3613#define SQ_IMG_SAMP_WORD0__CLAMP_Y_MASK 0x00000038L
3614#define SQ_IMG_SAMP_WORD0__CLAMP_Z_MASK 0x000001C0L
3615#define SQ_IMG_SAMP_WORD0__MAX_ANISO_RATIO_MASK 0x00000E00L
3616#define SQ_IMG_SAMP_WORD0__DEPTH_COMPARE_FUNC_MASK 0x00007000L
3617#define SQ_IMG_SAMP_WORD0__FORCE_UNNORMALIZED_MASK 0x00008000L
3618#define SQ_IMG_SAMP_WORD0__ANISO_THRESHOLD_MASK 0x00070000L
3619#define SQ_IMG_SAMP_WORD0__MC_COORD_TRUNC_MASK 0x00080000L
3620#define SQ_IMG_SAMP_WORD0__FORCE_DEGAMMA_MASK 0x00100000L
3621#define SQ_IMG_SAMP_WORD0__ANISO_BIAS_MASK 0x07E00000L
3622#define SQ_IMG_SAMP_WORD0__TRUNC_COORD_MASK 0x08000000L
3623#define SQ_IMG_SAMP_WORD0__DISABLE_CUBE_WRAP_MASK 0x10000000L
3624#define SQ_IMG_SAMP_WORD0__FILTER_MODE_MASK 0x60000000L
3625#define SQ_IMG_SAMP_WORD0__COMPAT_MODE_MASK 0x80000000L
3626//SQ_IMG_SAMP_WORD1
3627#define SQ_IMG_SAMP_WORD1__MIN_LOD__SHIFT 0x0
3628#define SQ_IMG_SAMP_WORD1__MAX_LOD__SHIFT 0xc
3629#define SQ_IMG_SAMP_WORD1__PERF_MIP__SHIFT 0x18
3630#define SQ_IMG_SAMP_WORD1__PERF_Z__SHIFT 0x1c
3631#define SQ_IMG_SAMP_WORD1__MIN_LOD_MASK 0x00000FFFL
3632#define SQ_IMG_SAMP_WORD1__MAX_LOD_MASK 0x00FFF000L
3633#define SQ_IMG_SAMP_WORD1__PERF_MIP_MASK 0x0F000000L
3634#define SQ_IMG_SAMP_WORD1__PERF_Z_MASK 0xF0000000L
3635//SQ_IMG_SAMP_WORD2
3636#define SQ_IMG_SAMP_WORD2__LOD_BIAS__SHIFT 0x0
3637#define SQ_IMG_SAMP_WORD2__LOD_BIAS_SEC__SHIFT 0xe
3638#define SQ_IMG_SAMP_WORD2__XY_MAG_FILTER__SHIFT 0x14
3639#define SQ_IMG_SAMP_WORD2__XY_MIN_FILTER__SHIFT 0x16
3640#define SQ_IMG_SAMP_WORD2__Z_FILTER__SHIFT 0x18
3641#define SQ_IMG_SAMP_WORD2__MIP_FILTER__SHIFT 0x1a
3642#define SQ_IMG_SAMP_WORD2__MIP_POINT_PRECLAMP__SHIFT 0x1c
3643#define SQ_IMG_SAMP_WORD2__BLEND_ZERO_PRT__SHIFT 0x1d
3644#define SQ_IMG_SAMP_WORD2__FILTER_PREC_FIX__SHIFT 0x1e
3645#define SQ_IMG_SAMP_WORD2__ANISO_OVERRIDE__SHIFT 0x1f
3646#define SQ_IMG_SAMP_WORD2__LOD_BIAS_MASK 0x00003FFFL
3647#define SQ_IMG_SAMP_WORD2__LOD_BIAS_SEC_MASK 0x000FC000L
3648#define SQ_IMG_SAMP_WORD2__XY_MAG_FILTER_MASK 0x00300000L
3649#define SQ_IMG_SAMP_WORD2__XY_MIN_FILTER_MASK 0x00C00000L
3650#define SQ_IMG_SAMP_WORD2__Z_FILTER_MASK 0x03000000L
3651#define SQ_IMG_SAMP_WORD2__MIP_FILTER_MASK 0x0C000000L
3652#define SQ_IMG_SAMP_WORD2__MIP_POINT_PRECLAMP_MASK 0x10000000L
3653#define SQ_IMG_SAMP_WORD2__BLEND_ZERO_PRT_MASK 0x20000000L
3654#define SQ_IMG_SAMP_WORD2__FILTER_PREC_FIX_MASK 0x40000000L
3655#define SQ_IMG_SAMP_WORD2__ANISO_OVERRIDE_MASK 0x80000000L
3656//SQ_IMG_SAMP_WORD3
3657#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_PTR__SHIFT 0x0
3658#define SQ_IMG_SAMP_WORD3__SKIP_DEGAMMA__SHIFT 0xc
3659#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_TYPE__SHIFT 0x1e
3660#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_PTR_MASK 0x00000FFFL
3661#define SQ_IMG_SAMP_WORD3__SKIP_DEGAMMA_MASK 0x00001000L
3662#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_TYPE_MASK 0xC0000000L
3663//SQ_FLAT_SCRATCH_WORD0
3664#define SQ_FLAT_SCRATCH_WORD0__SIZE__SHIFT 0x0
3665#define SQ_FLAT_SCRATCH_WORD0__SIZE_MASK 0x0007FFFFL
3666//SQ_FLAT_SCRATCH_WORD1
3667#define SQ_FLAT_SCRATCH_WORD1__OFFSET__SHIFT 0x0
3668#define SQ_FLAT_SCRATCH_WORD1__OFFSET_MASK 0x00FFFFFFL
3669//SQ_M0_GPR_IDX_WORD
3670#define SQ_M0_GPR_IDX_WORD__INDEX__SHIFT 0x0
3671#define SQ_M0_GPR_IDX_WORD__VSRC0_REL__SHIFT 0xc
3672#define SQ_M0_GPR_IDX_WORD__VSRC1_REL__SHIFT 0xd
3673#define SQ_M0_GPR_IDX_WORD__VSRC2_REL__SHIFT 0xe
3674#define SQ_M0_GPR_IDX_WORD__VDST_REL__SHIFT 0xf
3675#define SQ_M0_GPR_IDX_WORD__INDEX_MASK 0x000000FFL
3676#define SQ_M0_GPR_IDX_WORD__VSRC0_REL_MASK 0x00001000L
3677#define SQ_M0_GPR_IDX_WORD__VSRC1_REL_MASK 0x00002000L
3678#define SQ_M0_GPR_IDX_WORD__VSRC2_REL_MASK 0x00004000L
3679#define SQ_M0_GPR_IDX_WORD__VDST_REL_MASK 0x00008000L
3680//SQC_ICACHE_UTCL1_CNTL1
3681#define SQC_ICACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0
3682#define SQC_ICACHE_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT 0x1
3683#define SQC_ICACHE_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2
3684#define SQC_ICACHE_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3
3685#define SQC_ICACHE_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5
3686#define SQC_ICACHE_UTCL1_CNTL1__CLIENTID__SHIFT 0x7
3687#define SQC_ICACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11
3688#define SQC_ICACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12
3689#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID__SHIFT 0x13
3690#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID__SHIFT 0x17
3691#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE__SHIFT 0x18
3692#define SQC_ICACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT 0x19
3693#define SQC_ICACHE_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a
3694#define SQC_ICACHE_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b
3695#define SQC_ICACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c
3696#define SQC_ICACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e
3697#define SQC_ICACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L
3698#define SQC_ICACHE_UTCL1_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L
3699#define SQC_ICACHE_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L
3700#define SQC_ICACHE_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L
3701#define SQC_ICACHE_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L
3702#define SQC_ICACHE_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L
3703#define SQC_ICACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L
3704#define SQC_ICACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L
3705#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID_MASK 0x00780000L
3706#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID_MASK 0x00800000L
3707#define SQC_ICACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE_MASK 0x01000000L
3708#define SQC_ICACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK 0x02000000L
3709#define SQC_ICACHE_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L
3710#define SQC_ICACHE_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L
3711#define SQC_ICACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L
3712#define SQC_ICACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L
3713//SQC_ICACHE_UTCL1_CNTL2
3714#define SQC_ICACHE_UTCL1_CNTL2__SPARE__SHIFT 0x0
3715#define SQC_ICACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE__SHIFT 0x8
3716#define SQC_ICACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9
3717#define SQC_ICACHE_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa
3718#define SQC_ICACHE_UTCL1_CNTL2__DIS_EDC__SHIFT 0xb
3719#define SQC_ICACHE_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc
3720#define SQC_ICACHE_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT 0xd
3721#define SQC_ICACHE_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe
3722#define SQC_ICACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf
3723#define SQC_ICACHE_UTCL1_CNTL2__ARB_BURST_MODE__SHIFT 0x10
3724#define SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT 0x12
3725#define SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR__SHIFT 0x13
3726#define SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT 0x14
3727#define SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_VMID__SHIFT 0x15
3728#define SQC_ICACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a
3729#define SQC_ICACHE_UTCL1_CNTL2__SPARE_MASK 0x000000FFL
3730#define SQC_ICACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE_MASK 0x00000100L
3731#define SQC_ICACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L
3732#define SQC_ICACHE_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L
3733#define SQC_ICACHE_UTCL1_CNTL2__DIS_EDC_MASK 0x00000800L
3734#define SQC_ICACHE_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L
3735#define SQC_ICACHE_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK 0x00002000L
3736#define SQC_ICACHE_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L
3737#define SQC_ICACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L
3738#define SQC_ICACHE_UTCL1_CNTL2__ARB_BURST_MODE_MASK 0x00030000L
3739#define SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L
3740#define SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR_MASK 0x00080000L
3741#define SQC_ICACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID_MASK 0x00100000L
3742#define SQC_ICACHE_UTCL1_CNTL2__PERF_EVENT_VMID_MASK 0x01E00000L
3743#define SQC_ICACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L
3744//SQC_DCACHE_UTCL1_CNTL1
3745#define SQC_DCACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0
3746#define SQC_DCACHE_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT 0x1
3747#define SQC_DCACHE_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2
3748#define SQC_DCACHE_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3
3749#define SQC_DCACHE_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5
3750#define SQC_DCACHE_UTCL1_CNTL1__CLIENTID__SHIFT 0x7
3751#define SQC_DCACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11
3752#define SQC_DCACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12
3753#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID__SHIFT 0x13
3754#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID__SHIFT 0x17
3755#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE__SHIFT 0x18
3756#define SQC_DCACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT 0x19
3757#define SQC_DCACHE_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a
3758#define SQC_DCACHE_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b
3759#define SQC_DCACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c
3760#define SQC_DCACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e
3761#define SQC_DCACHE_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L
3762#define SQC_DCACHE_UTCL1_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L
3763#define SQC_DCACHE_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L
3764#define SQC_DCACHE_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L
3765#define SQC_DCACHE_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L
3766#define SQC_DCACHE_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L
3767#define SQC_DCACHE_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L
3768#define SQC_DCACHE_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L
3769#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_VMID_MASK 0x00780000L
3770#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_ALL_VMID_MASK 0x00800000L
3771#define SQC_DCACHE_UTCL1_CNTL1__REG_INVALIDATE_TOGGLE_MASK 0x01000000L
3772#define SQC_DCACHE_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK 0x02000000L
3773#define SQC_DCACHE_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L
3774#define SQC_DCACHE_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L
3775#define SQC_DCACHE_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L
3776#define SQC_DCACHE_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L
3777//SQC_DCACHE_UTCL1_CNTL2
3778#define SQC_DCACHE_UTCL1_CNTL2__SPARE__SHIFT 0x0
3779#define SQC_DCACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE__SHIFT 0x8
3780#define SQC_DCACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9
3781#define SQC_DCACHE_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa
3782#define SQC_DCACHE_UTCL1_CNTL2__DIS_EDC__SHIFT 0xb
3783#define SQC_DCACHE_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc
3784#define SQC_DCACHE_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT 0xd
3785#define SQC_DCACHE_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe
3786#define SQC_DCACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf
3787#define SQC_DCACHE_UTCL1_CNTL2__ARB_BURST_MODE__SHIFT 0x10
3788#define SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT 0x12
3789#define SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR__SHIFT 0x13
3790#define SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT 0x14
3791#define SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_VMID__SHIFT 0x15
3792#define SQC_DCACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a
3793#define SQC_DCACHE_UTCL1_CNTL2__SPARE_MASK 0x000000FFL
3794#define SQC_DCACHE_UTCL1_CNTL2__LFIFO_SCAN_DISABLE_MASK 0x00000100L
3795#define SQC_DCACHE_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L
3796#define SQC_DCACHE_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L
3797#define SQC_DCACHE_UTCL1_CNTL2__DIS_EDC_MASK 0x00000800L
3798#define SQC_DCACHE_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L
3799#define SQC_DCACHE_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK 0x00002000L
3800#define SQC_DCACHE_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L
3801#define SQC_DCACHE_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L
3802#define SQC_DCACHE_UTCL1_CNTL2__ARB_BURST_MODE_MASK 0x00030000L
3803#define SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L
3804#define SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_RD_WR_MASK 0x00080000L
3805#define SQC_DCACHE_UTCL1_CNTL2__ENABLE_PERF_EVENT_VMID_MASK 0x00100000L
3806#define SQC_DCACHE_UTCL1_CNTL2__PERF_EVENT_VMID_MASK 0x01E00000L
3807#define SQC_DCACHE_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L
3808//SQC_ICACHE_UTCL1_STATUS
3809#define SQC_ICACHE_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0
3810#define SQC_ICACHE_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1
3811#define SQC_ICACHE_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2
3812#define SQC_ICACHE_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L
3813#define SQC_ICACHE_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L
3814#define SQC_ICACHE_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L
3815//SQC_DCACHE_UTCL1_STATUS
3816#define SQC_DCACHE_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0
3817#define SQC_DCACHE_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1
3818#define SQC_DCACHE_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2
3819#define SQC_DCACHE_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L
3820#define SQC_DCACHE_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L
3821#define SQC_DCACHE_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L
3822
3823
3824// addressBlock: gc_shsdec
3825//SX_DEBUG_BUSY
3826#define SX_DEBUG_BUSY__POS_FREE_OR_VALIDS__SHIFT 0x0
3827#define SX_DEBUG_BUSY__POS_REQUESTER_BUSY__SHIFT 0x1
3828#define SX_DEBUG_BUSY__PA_SX_BUSY__SHIFT 0x2
3829#define SX_DEBUG_BUSY__POS_SCBD_BUSY__SHIFT 0x3
3830#define SX_DEBUG_BUSY__POS_BANK3VAL3_BUSY__SHIFT 0x4
3831#define SX_DEBUG_BUSY__POS_BANK3VAL2_BUSY__SHIFT 0x5
3832#define SX_DEBUG_BUSY__POS_BANK3VAL1_BUSY__SHIFT 0x6
3833#define SX_DEBUG_BUSY__POS_BANK3VAL0_BUSY__SHIFT 0x7
3834#define SX_DEBUG_BUSY__POS_BANK2VAL3_BUSY__SHIFT 0x8
3835#define SX_DEBUG_BUSY__POS_BANK2VAL2_BUSY__SHIFT 0x9
3836#define SX_DEBUG_BUSY__POS_BANK2VAL1_BUSY__SHIFT 0xa
3837#define SX_DEBUG_BUSY__POS_BANK2VAL0_BUSY__SHIFT 0xb
3838#define SX_DEBUG_BUSY__POS_BANK1VAL3_BUSY__SHIFT 0xc
3839#define SX_DEBUG_BUSY__POS_BANK1VAL2_BUSY__SHIFT 0xd
3840#define SX_DEBUG_BUSY__POS_BANK1VAL1_BUSY__SHIFT 0xe
3841#define SX_DEBUG_BUSY__POS_BANK1VAL0_BUSY__SHIFT 0xf
3842#define SX_DEBUG_BUSY__POS_BANK0VAL3_BUSY__SHIFT 0x10
3843#define SX_DEBUG_BUSY__POS_BANK0VAL2_BUSY__SHIFT 0x11
3844#define SX_DEBUG_BUSY__POS_BANK0VAL1_BUSY__SHIFT 0x12
3845#define SX_DEBUG_BUSY__POS_BANK0VAL0_BUSY__SHIFT 0x13
3846#define SX_DEBUG_BUSY__POS_INMUX_VALID__SHIFT 0x14
3847#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ3__SHIFT 0x15
3848#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ2__SHIFT 0x16
3849#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ1__SHIFT 0x17
3850#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ3__SHIFT 0x18
3851#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ2__SHIFT 0x19
3852#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ1__SHIFT 0x1a
3853#define SX_DEBUG_BUSY__PCCMD_VALID__SHIFT 0x1b
3854#define SX_DEBUG_BUSY__VDATA1_VALID__SHIFT 0x1c
3855#define SX_DEBUG_BUSY__VDATA0_VALID__SHIFT 0x1d
3856#define SX_DEBUG_BUSY__CMD_BUSYORVAL__SHIFT 0x1e
3857#define SX_DEBUG_BUSY__ADDR_BUSYORVAL__SHIFT 0x1f
3858#define SX_DEBUG_BUSY__POS_FREE_OR_VALIDS_MASK 0x00000001L
3859#define SX_DEBUG_BUSY__POS_REQUESTER_BUSY_MASK 0x00000002L
3860#define SX_DEBUG_BUSY__PA_SX_BUSY_MASK 0x00000004L
3861#define SX_DEBUG_BUSY__POS_SCBD_BUSY_MASK 0x00000008L
3862#define SX_DEBUG_BUSY__POS_BANK3VAL3_BUSY_MASK 0x00000010L
3863#define SX_DEBUG_BUSY__POS_BANK3VAL2_BUSY_MASK 0x00000020L
3864#define SX_DEBUG_BUSY__POS_BANK3VAL1_BUSY_MASK 0x00000040L
3865#define SX_DEBUG_BUSY__POS_BANK3VAL0_BUSY_MASK 0x00000080L
3866#define SX_DEBUG_BUSY__POS_BANK2VAL3_BUSY_MASK 0x00000100L
3867#define SX_DEBUG_BUSY__POS_BANK2VAL2_BUSY_MASK 0x00000200L
3868#define SX_DEBUG_BUSY__POS_BANK2VAL1_BUSY_MASK 0x00000400L
3869#define SX_DEBUG_BUSY__POS_BANK2VAL0_BUSY_MASK 0x00000800L
3870#define SX_DEBUG_BUSY__POS_BANK1VAL3_BUSY_MASK 0x00001000L
3871#define SX_DEBUG_BUSY__POS_BANK1VAL2_BUSY_MASK 0x00002000L
3872#define SX_DEBUG_BUSY__POS_BANK1VAL1_BUSY_MASK 0x00004000L
3873#define SX_DEBUG_BUSY__POS_BANK1VAL0_BUSY_MASK 0x00008000L
3874#define SX_DEBUG_BUSY__POS_BANK0VAL3_BUSY_MASK 0x00010000L
3875#define SX_DEBUG_BUSY__POS_BANK0VAL2_BUSY_MASK 0x00020000L
3876#define SX_DEBUG_BUSY__POS_BANK0VAL1_BUSY_MASK 0x00040000L
3877#define SX_DEBUG_BUSY__POS_BANK0VAL0_BUSY_MASK 0x00080000L
3878#define SX_DEBUG_BUSY__POS_INMUX_VALID_MASK 0x00100000L
3879#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ3_MASK 0x00200000L
3880#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ2_MASK 0x00400000L
3881#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ1_MASK 0x00800000L
3882#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ3_MASK 0x01000000L
3883#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ2_MASK 0x02000000L
3884#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ1_MASK 0x04000000L
3885#define SX_DEBUG_BUSY__PCCMD_VALID_MASK 0x08000000L
3886#define SX_DEBUG_BUSY__VDATA1_VALID_MASK 0x10000000L
3887#define SX_DEBUG_BUSY__VDATA0_VALID_MASK 0x20000000L
3888#define SX_DEBUG_BUSY__CMD_BUSYORVAL_MASK 0x40000000L
3889#define SX_DEBUG_BUSY__ADDR_BUSYORVAL_MASK 0x80000000L
3890//SX_DEBUG_BUSY_2
3891#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL3_BUSY__SHIFT 0x0
3892#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL2_BUSY__SHIFT 0x1
3893#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL1_BUSY__SHIFT 0x2
3894#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL0_BUSY__SHIFT 0x3
3895#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL3_BUSY__SHIFT 0x4
3896#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL2_BUSY__SHIFT 0x5
3897#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL1_BUSY__SHIFT 0x6
3898#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL0_BUSY__SHIFT 0x7
3899#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK1_VAL3_BUSY__SHIFT 0x8
3900#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK1_VAL2_BUSY__SHIFT 0x9
3901#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK1_VAL1_BUSY__SHIFT 0xa
3902#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK1_VAL0_BUSY__SHIFT 0xb
3903#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK0_VAL3_BUSY__SHIFT 0xc
3904#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK0_VAL2_BUSY__SHIFT 0xd
3905#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK0_VAL1_BUSY__SHIFT 0xe
3906#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK0_VAL0_BUSY__SHIFT 0xf
3907#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK3_VAL3_BUSY__SHIFT 0x10
3908#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK3_VAL2_BUSY__SHIFT 0x11
3909#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK3_VAL1_BUSY__SHIFT 0x12
3910#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK3_VAL0_BUSY__SHIFT 0x13
3911#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK2_VAL3_BUSY__SHIFT 0x14
3912#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK2_VAL2_BUSY__SHIFT 0x15
3913#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK2_VAL1_BUSY__SHIFT 0x16
3914#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK2_VAL0_BUSY__SHIFT 0x17
3915#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK1_VAL3_BUSY__SHIFT 0x18
3916#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK1_VAL2_BUSY__SHIFT 0x19
3917#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK1_VAL1_BUSY__SHIFT 0x1a
3918#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK1_VAL0_BUSY__SHIFT 0x1b
3919#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK0_VAL3_BUSY__SHIFT 0x1c
3920#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK0_VAL2_BUSY__SHIFT 0x1d
3921#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK0_VAL1_BUSY__SHIFT 0x1e
3922#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK0_VAL0_BUSY__SHIFT 0x1f
3923#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL3_BUSY_MASK 0x00000001L
3924#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL2_BUSY_MASK 0x00000002L
3925#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL1_BUSY_MASK 0x00000004L
3926#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL0_BUSY_MASK 0x00000008L
3927#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL3_BUSY_MASK 0x00000010L
3928#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL2_BUSY_MASK 0x00000020L
3929#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL1_BUSY_MASK 0x00000040L
3930#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL0_BUSY_MASK 0x00000080L
3931#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK1_VAL3_BUSY_MASK 0x00000100L
3932#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK1_VAL2_BUSY_MASK 0x00000200L
3933#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK1_VAL1_BUSY_MASK 0x00000400L
3934#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK1_VAL0_BUSY_MASK 0x00000800L
3935#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK0_VAL3_BUSY_MASK 0x00001000L
3936#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK0_VAL2_BUSY_MASK 0x00002000L
3937#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK0_VAL1_BUSY_MASK 0x00004000L
3938#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK0_VAL0_BUSY_MASK 0x00008000L
3939#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK3_VAL3_BUSY_MASK 0x00010000L
3940#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK3_VAL2_BUSY_MASK 0x00020000L
3941#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK3_VAL1_BUSY_MASK 0x00040000L
3942#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK3_VAL0_BUSY_MASK 0x00080000L
3943#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK2_VAL3_BUSY_MASK 0x00100000L
3944#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK2_VAL2_BUSY_MASK 0x00200000L
3945#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK2_VAL1_BUSY_MASK 0x00400000L
3946#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK2_VAL0_BUSY_MASK 0x00800000L
3947#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK1_VAL3_BUSY_MASK 0x01000000L
3948#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK1_VAL2_BUSY_MASK 0x02000000L
3949#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK1_VAL1_BUSY_MASK 0x04000000L
3950#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK1_VAL0_BUSY_MASK 0x08000000L
3951#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK0_VAL3_BUSY_MASK 0x10000000L
3952#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK0_VAL2_BUSY_MASK 0x20000000L
3953#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK0_VAL1_BUSY_MASK 0x40000000L
3954#define SX_DEBUG_BUSY_2__COL_BUFF2_BANK0_VAL0_BUSY_MASK 0x80000000L
3955//SX_DEBUG_BUSY_3
3956#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL3_BUSY__SHIFT 0x0
3957#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL2_BUSY__SHIFT 0x1
3958#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL1_BUSY__SHIFT 0x2
3959#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL0_BUSY__SHIFT 0x3
3960#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL3_BUSY__SHIFT 0x4
3961#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL2_BUSY__SHIFT 0x5
3962#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL1_BUSY__SHIFT 0x6
3963#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL0_BUSY__SHIFT 0x7
3964#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK1_VAL3_BUSY__SHIFT 0x8
3965#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK1_VAL2_BUSY__SHIFT 0x9
3966#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK1_VAL1_BUSY__SHIFT 0xa
3967#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK1_VAL0_BUSY__SHIFT 0xb
3968#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK0_VAL3_BUSY__SHIFT 0xc
3969#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK0_VAL2_BUSY__SHIFT 0xd
3970#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK0_VAL1_BUSY__SHIFT 0xe
3971#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK0_VAL0_BUSY__SHIFT 0xf
3972#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK3_VAL3_BUSY__SHIFT 0x10
3973#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK3_VAL2_BUSY__SHIFT 0x11
3974#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK3_VAL1_BUSY__SHIFT 0x12
3975#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK3_VAL0_BUSY__SHIFT 0x13
3976#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK2_VAL3_BUSY__SHIFT 0x14
3977#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK2_VAL2_BUSY__SHIFT 0x15
3978#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK2_VAL1_BUSY__SHIFT 0x16
3979#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK2_VAL0_BUSY__SHIFT 0x17
3980#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK1_VAL3_BUSY__SHIFT 0x18
3981#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK1_VAL2_BUSY__SHIFT 0x19
3982#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK1_VAL1_BUSY__SHIFT 0x1a
3983#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK1_VAL0_BUSY__SHIFT 0x1b
3984#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK0_VAL3_BUSY__SHIFT 0x1c
3985#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK0_VAL2_BUSY__SHIFT 0x1d
3986#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK0_VAL1_BUSY__SHIFT 0x1e
3987#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK0_VAL0_BUSY__SHIFT 0x1f
3988#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL3_BUSY_MASK 0x00000001L
3989#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL2_BUSY_MASK 0x00000002L
3990#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL1_BUSY_MASK 0x00000004L
3991#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL0_BUSY_MASK 0x00000008L
3992#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL3_BUSY_MASK 0x00000010L
3993#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL2_BUSY_MASK 0x00000020L
3994#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL1_BUSY_MASK 0x00000040L
3995#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL0_BUSY_MASK 0x00000080L
3996#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK1_VAL3_BUSY_MASK 0x00000100L
3997#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK1_VAL2_BUSY_MASK 0x00000200L
3998#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK1_VAL1_BUSY_MASK 0x00000400L
3999#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK1_VAL0_BUSY_MASK 0x00000800L
4000#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK0_VAL3_BUSY_MASK 0x00001000L
4001#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK0_VAL2_BUSY_MASK 0x00002000L
4002#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK0_VAL1_BUSY_MASK 0x00004000L
4003#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK0_VAL0_BUSY_MASK 0x00008000L
4004#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK3_VAL3_BUSY_MASK 0x00010000L
4005#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK3_VAL2_BUSY_MASK 0x00020000L
4006#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK3_VAL1_BUSY_MASK 0x00040000L
4007#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK3_VAL0_BUSY_MASK 0x00080000L
4008#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK2_VAL3_BUSY_MASK 0x00100000L
4009#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK2_VAL2_BUSY_MASK 0x00200000L
4010#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK2_VAL1_BUSY_MASK 0x00400000L
4011#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK2_VAL0_BUSY_MASK 0x00800000L
4012#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK1_VAL3_BUSY_MASK 0x01000000L
4013#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK1_VAL2_BUSY_MASK 0x02000000L
4014#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK1_VAL1_BUSY_MASK 0x04000000L
4015#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK1_VAL0_BUSY_MASK 0x08000000L
4016#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK0_VAL3_BUSY_MASK 0x10000000L
4017#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK0_VAL2_BUSY_MASK 0x20000000L
4018#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK0_VAL1_BUSY_MASK 0x40000000L
4019#define SX_DEBUG_BUSY_3__COL_BUFF0_BANK0_VAL0_BUSY_MASK 0x80000000L
4020//SX_DEBUG_BUSY_4
4021#define SX_DEBUG_BUSY_4__COL_SCBD_BUSY__SHIFT 0x0
4022#define SX_DEBUG_BUSY_4__COL_REQ3_FREECNT_NE0__SHIFT 0x1
4023#define SX_DEBUG_BUSY_4__COL_REQ3_IDLE__SHIFT 0x2
4024#define SX_DEBUG_BUSY_4__COL_REQ3_BUSY__SHIFT 0x3
4025#define SX_DEBUG_BUSY_4__COL_REQ3_CREDIT_BUSY__SHIFT 0x4
4026#define SX_DEBUG_BUSY_4__COL_REQ2_FREECNT_NE0__SHIFT 0x5
4027#define SX_DEBUG_BUSY_4__COL_REQ2_IDLE__SHIFT 0x6
4028#define SX_DEBUG_BUSY_4__COL_REQ2_BUSY__SHIFT 0x7
4029#define SX_DEBUG_BUSY_4__COL_REQ2_CREDIT_BUSY__SHIFT 0x8
4030#define SX_DEBUG_BUSY_4__COL_REQ1_FREECNT_NE0__SHIFT 0x9
4031#define SX_DEBUG_BUSY_4__COL_REQ1_IDLE__SHIFT 0xa
4032#define SX_DEBUG_BUSY_4__COL_REQ1_BUSY__SHIFT 0xb
4033#define SX_DEBUG_BUSY_4__COL_REQ1_CREDIT_BUSY__SHIFT 0xc
4034#define SX_DEBUG_BUSY_4__COL_REQ0_FREECNT_NE0__SHIFT 0xd
4035#define SX_DEBUG_BUSY_4__COL_REQ0_IDLE__SHIFT 0xe
4036#define SX_DEBUG_BUSY_4__COL_REQ0_BUSY__SHIFT 0xf
4037#define SX_DEBUG_BUSY_4__COL_REQ0_CREDIT_BUSY__SHIFT 0x10
4038#define SX_DEBUG_BUSY_4__COL_DBIF3_SENDFREE_BUSY__SHIFT 0x11
4039#define SX_DEBUG_BUSY_4__COL_DBIF3_FIFO_BUSY__SHIFT 0x12
4040#define SX_DEBUG_BUSY_4__COL_DBIF3_QUAD_FREE__SHIFT 0x13
4041#define SX_DEBUG_BUSY_4__COL_DBIF2_SENDFREE_BUSY__SHIFT 0x14
4042#define SX_DEBUG_BUSY_4__COL_DBIF2_FIFO_BUSY__SHIFT 0x15
4043#define SX_DEBUG_BUSY_4__COL_DBIF2_QUAD_FREE__SHIFT 0x16
4044#define SX_DEBUG_BUSY_4__COL_DBIF1_SENDFREE_BUSY__SHIFT 0x17
4045#define SX_DEBUG_BUSY_4__COL_DBIF1_FIFO_BUSY__SHIFT 0x18
4046#define SX_DEBUG_BUSY_4__COL_DBIF1_QUAD_FREE__SHIFT 0x19
4047#define SX_DEBUG_BUSY_4__COL_DBIF0_SENDFREE_BUSY__SHIFT 0x1a
4048#define SX_DEBUG_BUSY_4__COL_DBIF0_FIFO_BUSY__SHIFT 0x1b
4049#define SX_DEBUG_BUSY_4__COL_DBIF0_QUAD_FREE__SHIFT 0x1c
4050#define SX_DEBUG_BUSY_4__COL_BLEND3_DATA_VALIDQ1__SHIFT 0x1d
4051#define SX_DEBUG_BUSY_4__COL_BLEND3_DATA_VALIDQ1_ADJ__SHIFT 0x1e
4052#define SX_DEBUG_BUSY_4__COL_BLEND3_DATA_VALIDQ2__SHIFT 0x1f
4053#define SX_DEBUG_BUSY_4__COL_SCBD_BUSY_MASK 0x00000001L
4054#define SX_DEBUG_BUSY_4__COL_REQ3_FREECNT_NE0_MASK 0x00000002L
4055#define SX_DEBUG_BUSY_4__COL_REQ3_IDLE_MASK 0x00000004L
4056#define SX_DEBUG_BUSY_4__COL_REQ3_BUSY_MASK 0x00000008L
4057#define SX_DEBUG_BUSY_4__COL_REQ3_CREDIT_BUSY_MASK 0x00000010L
4058#define SX_DEBUG_BUSY_4__COL_REQ2_FREECNT_NE0_MASK 0x00000020L
4059#define SX_DEBUG_BUSY_4__COL_REQ2_IDLE_MASK 0x00000040L
4060#define SX_DEBUG_BUSY_4__COL_REQ2_BUSY_MASK 0x00000080L
4061#define SX_DEBUG_BUSY_4__COL_REQ2_CREDIT_BUSY_MASK 0x00000100L
4062#define SX_DEBUG_BUSY_4__COL_REQ1_FREECNT_NE0_MASK 0x00000200L
4063#define SX_DEBUG_BUSY_4__COL_REQ1_IDLE_MASK 0x00000400L
4064#define SX_DEBUG_BUSY_4__COL_REQ1_BUSY_MASK 0x00000800L
4065#define SX_DEBUG_BUSY_4__COL_REQ1_CREDIT_BUSY_MASK 0x00001000L
4066#define SX_DEBUG_BUSY_4__COL_REQ0_FREECNT_NE0_MASK 0x00002000L
4067#define SX_DEBUG_BUSY_4__COL_REQ0_IDLE_MASK 0x00004000L
4068#define SX_DEBUG_BUSY_4__COL_REQ0_BUSY_MASK 0x00008000L
4069#define SX_DEBUG_BUSY_4__COL_REQ0_CREDIT_BUSY_MASK 0x00010000L
4070#define SX_DEBUG_BUSY_4__COL_DBIF3_SENDFREE_BUSY_MASK 0x00020000L
4071#define SX_DEBUG_BUSY_4__COL_DBIF3_FIFO_BUSY_MASK 0x00040000L
4072#define SX_DEBUG_BUSY_4__COL_DBIF3_QUAD_FREE_MASK 0x00080000L
4073#define SX_DEBUG_BUSY_4__COL_DBIF2_SENDFREE_BUSY_MASK 0x00100000L
4074#define SX_DEBUG_BUSY_4__COL_DBIF2_FIFO_BUSY_MASK 0x00200000L
4075#define SX_DEBUG_BUSY_4__COL_DBIF2_QUAD_FREE_MASK 0x00400000L
4076#define SX_DEBUG_BUSY_4__COL_DBIF1_SENDFREE_BUSY_MASK 0x00800000L
4077#define SX_DEBUG_BUSY_4__COL_DBIF1_FIFO_BUSY_MASK 0x01000000L
4078#define SX_DEBUG_BUSY_4__COL_DBIF1_QUAD_FREE_MASK 0x02000000L
4079#define SX_DEBUG_BUSY_4__COL_DBIF0_SENDFREE_BUSY_MASK 0x04000000L
4080#define SX_DEBUG_BUSY_4__COL_DBIF0_FIFO_BUSY_MASK 0x08000000L
4081#define SX_DEBUG_BUSY_4__COL_DBIF0_QUAD_FREE_MASK 0x10000000L
4082#define SX_DEBUG_BUSY_4__COL_BLEND3_DATA_VALIDQ1_MASK 0x20000000L
4083#define SX_DEBUG_BUSY_4__COL_BLEND3_DATA_VALIDQ1_ADJ_MASK 0x40000000L
4084#define SX_DEBUG_BUSY_4__COL_BLEND3_DATA_VALIDQ2_MASK 0x80000000L
4085//SX_DEBUG_BUSY_5
4086#define SX_DEBUG_BUSY_5__COL_BLEND3_DATA_VALIDQ3__SHIFT 0x0
4087#define SX_DEBUG_BUSY_5__COL_BLEND3_DATA_VALIDQ4__SHIFT 0x1
4088#define SX_DEBUG_BUSY_5__COL_BLEND3_DATA_VALIDQ5__SHIFT 0x2
4089#define SX_DEBUG_BUSY_5__COL_BLEND3_DATA_VALID_O__SHIFT 0x3
4090#define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALIDQ1__SHIFT 0x4
4091#define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALIDQ1_ADJ__SHIFT 0x5
4092#define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALIDQ2__SHIFT 0x6
4093#define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALIDQ3__SHIFT 0x7
4094#define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALIDQ4__SHIFT 0x8
4095#define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALIDQ5__SHIFT 0x9
4096#define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALID_O__SHIFT 0xa
4097#define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALIDQ1__SHIFT 0xb
4098#define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALIDQ1_ADJ__SHIFT 0xc
4099#define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALIDQ2__SHIFT 0xd
4100#define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALIDQ3__SHIFT 0xe
4101#define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALIDQ4__SHIFT 0xf
4102#define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALIDQ5__SHIFT 0x10
4103#define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALID_O__SHIFT 0x11
4104#define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALIDQ1__SHIFT 0x12
4105#define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALIDQ1_ADJ__SHIFT 0x13
4106#define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALIDQ2__SHIFT 0x14
4107#define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALIDQ3__SHIFT 0x15
4108#define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALIDQ4__SHIFT 0x16
4109#define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALIDQ5__SHIFT 0x17
4110#define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALID_O__SHIFT 0x18
4111#define SX_DEBUG_BUSY_5__RESERVED__SHIFT 0x19
4112#define SX_DEBUG_BUSY_5__COL_BLEND3_DATA_VALIDQ3_MASK 0x00000001L
4113#define SX_DEBUG_BUSY_5__COL_BLEND3_DATA_VALIDQ4_MASK 0x00000002L
4114#define SX_DEBUG_BUSY_5__COL_BLEND3_DATA_VALIDQ5_MASK 0x00000004L
4115#define SX_DEBUG_BUSY_5__COL_BLEND3_DATA_VALID_O_MASK 0x00000008L
4116#define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALIDQ1_MASK 0x00000010L
4117#define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALIDQ1_ADJ_MASK 0x00000020L
4118#define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALIDQ2_MASK 0x00000040L
4119#define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALIDQ3_MASK 0x00000080L
4120#define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALIDQ4_MASK 0x00000100L
4121#define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALIDQ5_MASK 0x00000200L
4122#define SX_DEBUG_BUSY_5__COL_BLEND2_DATA_VALID_O_MASK 0x00000400L
4123#define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALIDQ1_MASK 0x00000800L
4124#define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALIDQ1_ADJ_MASK 0x00001000L
4125#define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALIDQ2_MASK 0x00002000L
4126#define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALIDQ3_MASK 0x00004000L
4127#define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALIDQ4_MASK 0x00008000L
4128#define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALIDQ5_MASK 0x00010000L
4129#define SX_DEBUG_BUSY_5__COL_BLEND1_DATA_VALID_O_MASK 0x00020000L
4130#define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALIDQ1_MASK 0x00040000L
4131#define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALIDQ1_ADJ_MASK 0x00080000L
4132#define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALIDQ2_MASK 0x00100000L
4133#define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALIDQ3_MASK 0x00200000L
4134#define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALIDQ4_MASK 0x00400000L
4135#define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALIDQ5_MASK 0x00800000L
4136#define SX_DEBUG_BUSY_5__COL_BLEND0_DATA_VALID_O_MASK 0x01000000L
4137#define SX_DEBUG_BUSY_5__RESERVED_MASK 0xFE000000L
4138//SX_DEBUG_1
4139#define SX_DEBUG_1__SX_DB_QUAD_CREDIT__SHIFT 0x0
4140#define SX_DEBUG_1__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT 0x8
4141#define SX_DEBUG_1__DISABLE_BLEND_OPT_BYPASS__SHIFT 0x9
4142#define SX_DEBUG_1__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT 0xa
4143#define SX_DEBUG_1__DISABLE_QUAD_PAIR_OPT__SHIFT 0xb
4144#define SX_DEBUG_1__DISABLE_PIX_EN_ZERO_OPT__SHIFT 0xc
4145#define SX_DEBUG_1__PC_CFG__SHIFT 0xd
4146#define SX_DEBUG_1__DEBUG_DATA__SHIFT 0xe
4147#define SX_DEBUG_1__SX_DB_QUAD_CREDIT_MASK 0x0000007FL
4148#define SX_DEBUG_1__DISABLE_BLEND_OPT_DONT_RD_DST_MASK 0x00000100L
4149#define SX_DEBUG_1__DISABLE_BLEND_OPT_BYPASS_MASK 0x00000200L
4150#define SX_DEBUG_1__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK 0x00000400L
4151#define SX_DEBUG_1__DISABLE_QUAD_PAIR_OPT_MASK 0x00000800L
4152#define SX_DEBUG_1__DISABLE_PIX_EN_ZERO_OPT_MASK 0x00001000L
4153#define SX_DEBUG_1__PC_CFG_MASK 0x00002000L
4154#define SX_DEBUG_1__DEBUG_DATA_MASK 0xFFFFC000L
4155//SPI_PS_MAX_WAVE_ID
4156#define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0
4157#define SPI_PS_MAX_WAVE_ID__MAX_COLLISION_WAVE_ID__SHIFT 0x10
4158#define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000FFFL
4159#define SPI_PS_MAX_WAVE_ID__MAX_COLLISION_WAVE_ID_MASK 0x03FF0000L
4160//SPI_START_PHASE
4161#define SPI_START_PHASE__VGPR_START_PHASE__SHIFT 0x0
4162#define SPI_START_PHASE__SGPR_START_PHASE__SHIFT 0x2
4163#define SPI_START_PHASE__WAVE_START_PHASE__SHIFT 0x4
4164#define SPI_START_PHASE__VGPR_START_PHASE_MASK 0x00000003L
4165#define SPI_START_PHASE__SGPR_START_PHASE_MASK 0x0000000CL
4166#define SPI_START_PHASE__WAVE_START_PHASE_MASK 0x00000030L
4167//SPI_GFX_CNTL
4168#define SPI_GFX_CNTL__RESET_COUNTS__SHIFT 0x0
4169#define SPI_GFX_CNTL__RESET_COUNTS_MASK 0x00000001L
4170//SPI_DEBUG_READ
4171#define SPI_DEBUG_READ__DATA__SHIFT 0x0
4172#define SPI_DEBUG_READ__DATA_MASK 0xFFFFFFFFL
4173//SPI_DSM_CNTL
4174#define SPI_DSM_CNTL__SPI_SR_MEM_DSM_IRRITATOR_DATA__SHIFT 0x0
4175#define SPI_DSM_CNTL__SPI_SR_MEM_ENABLE_SINGLE_WRITE__SHIFT 0x2
4176#define SPI_DSM_CNTL__UNUSED__SHIFT 0x3
4177#define SPI_DSM_CNTL__SPI_SR_MEM_DSM_IRRITATOR_DATA_MASK 0x00000003L
4178#define SPI_DSM_CNTL__SPI_SR_MEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L
4179#define SPI_DSM_CNTL__UNUSED_MASK 0xFFFFFFF8L
4180//SPI_DSM_CNTL2
4181#define SPI_DSM_CNTL2__SPI_SR_MEM_ENABLE_ERROR_INJECT__SHIFT 0x0
4182#define SPI_DSM_CNTL2__SPI_SR_MEM_SELECT_INJECT_DELAY__SHIFT 0x2
4183#define SPI_DSM_CNTL2__SPI_SR_MEM_INJECT_DELAY__SHIFT 0x4
4184#define SPI_DSM_CNTL2__UNUSED__SHIFT 0xa
4185#define SPI_DSM_CNTL2__SPI_SR_MEM_ENABLE_ERROR_INJECT_MASK 0x00000003L
4186#define SPI_DSM_CNTL2__SPI_SR_MEM_SELECT_INJECT_DELAY_MASK 0x00000004L
4187#define SPI_DSM_CNTL2__SPI_SR_MEM_INJECT_DELAY_MASK 0x000003F0L
4188#define SPI_DSM_CNTL2__UNUSED_MASK 0xFFFFFC00L
4189//SPI_EDC_CNT
4190#define SPI_EDC_CNT__SPI_SR_MEM_SED_COUNT__SHIFT 0x0
4191#define SPI_EDC_CNT__SPI_SR_MEM_SED_COUNT_MASK 0x00000003L
4192//SPI_DEBUG_BUSY
4193#define SPI_DEBUG_BUSY__LS_BUSY__SHIFT 0x0
4194#define SPI_DEBUG_BUSY__HS_BUSY__SHIFT 0x1
4195#define SPI_DEBUG_BUSY__ES_BUSY__SHIFT 0x2
4196#define SPI_DEBUG_BUSY__GS_BUSY__SHIFT 0x3
4197#define SPI_DEBUG_BUSY__VS_BUSY__SHIFT 0x4
4198#define SPI_DEBUG_BUSY__PS0_BUSY__SHIFT 0x5
4199#define SPI_DEBUG_BUSY__PS1_BUSY__SHIFT 0x6
4200#define SPI_DEBUG_BUSY__CSG_BUSY__SHIFT 0x7
4201#define SPI_DEBUG_BUSY__CS0_BUSY__SHIFT 0x8
4202#define SPI_DEBUG_BUSY__CS1_BUSY__SHIFT 0x9
4203#define SPI_DEBUG_BUSY__CS2_BUSY__SHIFT 0xa
4204#define SPI_DEBUG_BUSY__CS3_BUSY__SHIFT 0xb
4205#define SPI_DEBUG_BUSY__CS4_BUSY__SHIFT 0xc
4206#define SPI_DEBUG_BUSY__CS5_BUSY__SHIFT 0xd
4207#define SPI_DEBUG_BUSY__CS6_BUSY__SHIFT 0xe
4208#define SPI_DEBUG_BUSY__CS7_BUSY__SHIFT 0xf
4209#define SPI_DEBUG_BUSY__LDS_WR_CTL0_BUSY__SHIFT 0x10
4210#define SPI_DEBUG_BUSY__LDS_WR_CTL1_BUSY__SHIFT 0x11
4211#define SPI_DEBUG_BUSY__RSRC_ALLOC0_BUSY__SHIFT 0x12
4212#define SPI_DEBUG_BUSY__RSRC_ALLOC1_BUSY__SHIFT 0x13
4213#define SPI_DEBUG_BUSY__PC_DEALLOC_BUSY__SHIFT 0x14
4214#define SPI_DEBUG_BUSY__EVENT_CLCTR_BUSY__SHIFT 0x15
4215#define SPI_DEBUG_BUSY__GRBM_BUSY__SHIFT 0x16
4216#define SPI_DEBUG_BUSY__SPIS_BUSY__SHIFT 0x17
4217#define SPI_DEBUG_BUSY__LS_BUSY_MASK 0x00000001L
4218#define SPI_DEBUG_BUSY__HS_BUSY_MASK 0x00000002L
4219#define SPI_DEBUG_BUSY__ES_BUSY_MASK 0x00000004L
4220#define SPI_DEBUG_BUSY__GS_BUSY_MASK 0x00000008L
4221#define SPI_DEBUG_BUSY__VS_BUSY_MASK 0x00000010L
4222#define SPI_DEBUG_BUSY__PS0_BUSY_MASK 0x00000020L
4223#define SPI_DEBUG_BUSY__PS1_BUSY_MASK 0x00000040L
4224#define SPI_DEBUG_BUSY__CSG_BUSY_MASK 0x00000080L
4225#define SPI_DEBUG_BUSY__CS0_BUSY_MASK 0x00000100L
4226#define SPI_DEBUG_BUSY__CS1_BUSY_MASK 0x00000200L
4227#define SPI_DEBUG_BUSY__CS2_BUSY_MASK 0x00000400L
4228#define SPI_DEBUG_BUSY__CS3_BUSY_MASK 0x00000800L
4229#define SPI_DEBUG_BUSY__CS4_BUSY_MASK 0x00001000L
4230#define SPI_DEBUG_BUSY__CS5_BUSY_MASK 0x00002000L
4231#define SPI_DEBUG_BUSY__CS6_BUSY_MASK 0x00004000L
4232#define SPI_DEBUG_BUSY__CS7_BUSY_MASK 0x00008000L
4233#define SPI_DEBUG_BUSY__LDS_WR_CTL0_BUSY_MASK 0x00010000L
4234#define SPI_DEBUG_BUSY__LDS_WR_CTL1_BUSY_MASK 0x00020000L
4235#define SPI_DEBUG_BUSY__RSRC_ALLOC0_BUSY_MASK 0x00040000L
4236#define SPI_DEBUG_BUSY__RSRC_ALLOC1_BUSY_MASK 0x00080000L
4237#define SPI_DEBUG_BUSY__PC_DEALLOC_BUSY_MASK 0x00100000L
4238#define SPI_DEBUG_BUSY__EVENT_CLCTR_BUSY_MASK 0x00200000L
4239#define SPI_DEBUG_BUSY__GRBM_BUSY_MASK 0x00400000L
4240#define SPI_DEBUG_BUSY__SPIS_BUSY_MASK 0x00800000L
4241//SPI_CONFIG_PS_CU_EN
4242#define SPI_CONFIG_PS_CU_EN__ENABLE__SHIFT 0x0
4243#define SPI_CONFIG_PS_CU_EN__PKR0_CU_EN__SHIFT 0x1
4244#define SPI_CONFIG_PS_CU_EN__PKR1_CU_EN__SHIFT 0x10
4245#define SPI_CONFIG_PS_CU_EN__ENABLE_MASK 0x00000001L
4246#define SPI_CONFIG_PS_CU_EN__PKR0_CU_EN_MASK 0x0000FFFEL
4247#define SPI_CONFIG_PS_CU_EN__PKR1_CU_EN_MASK 0xFFFF0000L
4248//SPI_WF_LIFETIME_CNTL
4249#define SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD__SHIFT 0x0
4250#define SPI_WF_LIFETIME_CNTL__EN__SHIFT 0x4
4251#define SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD_MASK 0x0000000FL
4252#define SPI_WF_LIFETIME_CNTL__EN_MASK 0x00000010L
4253//SPI_WF_LIFETIME_LIMIT_0
4254#define SPI_WF_LIFETIME_LIMIT_0__MAX_CNT__SHIFT 0x0
4255#define SPI_WF_LIFETIME_LIMIT_0__EN_WARN__SHIFT 0x1f
4256#define SPI_WF_LIFETIME_LIMIT_0__MAX_CNT_MASK 0x7FFFFFFFL
4257#define SPI_WF_LIFETIME_LIMIT_0__EN_WARN_MASK 0x80000000L
4258//SPI_WF_LIFETIME_LIMIT_1
4259#define SPI_WF_LIFETIME_LIMIT_1__MAX_CNT__SHIFT 0x0
4260#define SPI_WF_LIFETIME_LIMIT_1__EN_WARN__SHIFT 0x1f
4261#define SPI_WF_LIFETIME_LIMIT_1__MAX_CNT_MASK 0x7FFFFFFFL
4262#define SPI_WF_LIFETIME_LIMIT_1__EN_WARN_MASK 0x80000000L
4263//SPI_WF_LIFETIME_LIMIT_2
4264#define SPI_WF_LIFETIME_LIMIT_2__MAX_CNT__SHIFT 0x0
4265#define SPI_WF_LIFETIME_LIMIT_2__EN_WARN__SHIFT 0x1f
4266#define SPI_WF_LIFETIME_LIMIT_2__MAX_CNT_MASK 0x7FFFFFFFL
4267#define SPI_WF_LIFETIME_LIMIT_2__EN_WARN_MASK 0x80000000L
4268//SPI_WF_LIFETIME_LIMIT_3
4269#define SPI_WF_LIFETIME_LIMIT_3__MAX_CNT__SHIFT 0x0
4270#define SPI_WF_LIFETIME_LIMIT_3__EN_WARN__SHIFT 0x1f
4271#define SPI_WF_LIFETIME_LIMIT_3__MAX_CNT_MASK 0x7FFFFFFFL
4272#define SPI_WF_LIFETIME_LIMIT_3__EN_WARN_MASK 0x80000000L
4273//SPI_WF_LIFETIME_LIMIT_4
4274#define SPI_WF_LIFETIME_LIMIT_4__MAX_CNT__SHIFT 0x0
4275#define SPI_WF_LIFETIME_LIMIT_4__EN_WARN__SHIFT 0x1f
4276#define SPI_WF_LIFETIME_LIMIT_4__MAX_CNT_MASK 0x7FFFFFFFL
4277#define SPI_WF_LIFETIME_LIMIT_4__EN_WARN_MASK 0x80000000L
4278//SPI_WF_LIFETIME_LIMIT_5
4279#define SPI_WF_LIFETIME_LIMIT_5__MAX_CNT__SHIFT 0x0
4280#define SPI_WF_LIFETIME_LIMIT_5__EN_WARN__SHIFT 0x1f
4281#define SPI_WF_LIFETIME_LIMIT_5__MAX_CNT_MASK 0x7FFFFFFFL
4282#define SPI_WF_LIFETIME_LIMIT_5__EN_WARN_MASK 0x80000000L
4283//SPI_WF_LIFETIME_LIMIT_6
4284#define SPI_WF_LIFETIME_LIMIT_6__MAX_CNT__SHIFT 0x0
4285#define SPI_WF_LIFETIME_LIMIT_6__EN_WARN__SHIFT 0x1f
4286#define SPI_WF_LIFETIME_LIMIT_6__MAX_CNT_MASK 0x7FFFFFFFL
4287#define SPI_WF_LIFETIME_LIMIT_6__EN_WARN_MASK 0x80000000L
4288//SPI_WF_LIFETIME_LIMIT_7
4289#define SPI_WF_LIFETIME_LIMIT_7__MAX_CNT__SHIFT 0x0
4290#define SPI_WF_LIFETIME_LIMIT_7__EN_WARN__SHIFT 0x1f
4291#define SPI_WF_LIFETIME_LIMIT_7__MAX_CNT_MASK 0x7FFFFFFFL
4292#define SPI_WF_LIFETIME_LIMIT_7__EN_WARN_MASK 0x80000000L
4293//SPI_WF_LIFETIME_LIMIT_8
4294#define SPI_WF_LIFETIME_LIMIT_8__MAX_CNT__SHIFT 0x0
4295#define SPI_WF_LIFETIME_LIMIT_8__EN_WARN__SHIFT 0x1f
4296#define SPI_WF_LIFETIME_LIMIT_8__MAX_CNT_MASK 0x7FFFFFFFL
4297#define SPI_WF_LIFETIME_LIMIT_8__EN_WARN_MASK 0x80000000L
4298//SPI_WF_LIFETIME_LIMIT_9
4299#define SPI_WF_LIFETIME_LIMIT_9__MAX_CNT__SHIFT 0x0
4300#define SPI_WF_LIFETIME_LIMIT_9__EN_WARN__SHIFT 0x1f
4301#define SPI_WF_LIFETIME_LIMIT_9__MAX_CNT_MASK 0x7FFFFFFFL
4302#define SPI_WF_LIFETIME_LIMIT_9__EN_WARN_MASK 0x80000000L
4303//SPI_WF_LIFETIME_STATUS_0
4304#define SPI_WF_LIFETIME_STATUS_0__MAX_CNT__SHIFT 0x0
4305#define SPI_WF_LIFETIME_STATUS_0__INT_SENT__SHIFT 0x1f
4306#define SPI_WF_LIFETIME_STATUS_0__MAX_CNT_MASK 0x7FFFFFFFL
4307#define SPI_WF_LIFETIME_STATUS_0__INT_SENT_MASK 0x80000000L
4308//SPI_WF_LIFETIME_STATUS_1
4309#define SPI_WF_LIFETIME_STATUS_1__MAX_CNT__SHIFT 0x0
4310#define SPI_WF_LIFETIME_STATUS_1__INT_SENT__SHIFT 0x1f
4311#define SPI_WF_LIFETIME_STATUS_1__MAX_CNT_MASK 0x7FFFFFFFL
4312#define SPI_WF_LIFETIME_STATUS_1__INT_SENT_MASK 0x80000000L
4313//SPI_WF_LIFETIME_STATUS_2
4314#define SPI_WF_LIFETIME_STATUS_2__MAX_CNT__SHIFT 0x0
4315#define SPI_WF_LIFETIME_STATUS_2__INT_SENT__SHIFT 0x1f
4316#define SPI_WF_LIFETIME_STATUS_2__MAX_CNT_MASK 0x7FFFFFFFL
4317#define SPI_WF_LIFETIME_STATUS_2__INT_SENT_MASK 0x80000000L
4318//SPI_WF_LIFETIME_STATUS_3
4319#define SPI_WF_LIFETIME_STATUS_3__MAX_CNT__SHIFT 0x0
4320#define SPI_WF_LIFETIME_STATUS_3__INT_SENT__SHIFT 0x1f
4321#define SPI_WF_LIFETIME_STATUS_3__MAX_CNT_MASK 0x7FFFFFFFL
4322#define SPI_WF_LIFETIME_STATUS_3__INT_SENT_MASK 0x80000000L
4323//SPI_WF_LIFETIME_STATUS_4
4324#define SPI_WF_LIFETIME_STATUS_4__MAX_CNT__SHIFT 0x0
4325#define SPI_WF_LIFETIME_STATUS_4__INT_SENT__SHIFT 0x1f
4326#define SPI_WF_LIFETIME_STATUS_4__MAX_CNT_MASK 0x7FFFFFFFL
4327#define SPI_WF_LIFETIME_STATUS_4__INT_SENT_MASK 0x80000000L
4328//SPI_WF_LIFETIME_STATUS_5
4329#define SPI_WF_LIFETIME_STATUS_5__MAX_CNT__SHIFT 0x0
4330#define SPI_WF_LIFETIME_STATUS_5__INT_SENT__SHIFT 0x1f
4331#define SPI_WF_LIFETIME_STATUS_5__MAX_CNT_MASK 0x7FFFFFFFL
4332#define SPI_WF_LIFETIME_STATUS_5__INT_SENT_MASK 0x80000000L
4333//SPI_WF_LIFETIME_STATUS_6
4334#define SPI_WF_LIFETIME_STATUS_6__MAX_CNT__SHIFT 0x0
4335#define SPI_WF_LIFETIME_STATUS_6__INT_SENT__SHIFT 0x1f
4336#define SPI_WF_LIFETIME_STATUS_6__MAX_CNT_MASK 0x7FFFFFFFL
4337#define SPI_WF_LIFETIME_STATUS_6__INT_SENT_MASK 0x80000000L
4338//SPI_WF_LIFETIME_STATUS_7
4339#define SPI_WF_LIFETIME_STATUS_7__MAX_CNT__SHIFT 0x0
4340#define SPI_WF_LIFETIME_STATUS_7__INT_SENT__SHIFT 0x1f
4341#define SPI_WF_LIFETIME_STATUS_7__MAX_CNT_MASK 0x7FFFFFFFL
4342#define SPI_WF_LIFETIME_STATUS_7__INT_SENT_MASK 0x80000000L
4343//SPI_WF_LIFETIME_STATUS_8
4344#define SPI_WF_LIFETIME_STATUS_8__MAX_CNT__SHIFT 0x0
4345#define SPI_WF_LIFETIME_STATUS_8__INT_SENT__SHIFT 0x1f
4346#define SPI_WF_LIFETIME_STATUS_8__MAX_CNT_MASK 0x7FFFFFFFL
4347#define SPI_WF_LIFETIME_STATUS_8__INT_SENT_MASK 0x80000000L
4348//SPI_WF_LIFETIME_STATUS_9
4349#define SPI_WF_LIFETIME_STATUS_9__MAX_CNT__SHIFT 0x0
4350#define SPI_WF_LIFETIME_STATUS_9__INT_SENT__SHIFT 0x1f
4351#define SPI_WF_LIFETIME_STATUS_9__MAX_CNT_MASK 0x7FFFFFFFL
4352#define SPI_WF_LIFETIME_STATUS_9__INT_SENT_MASK 0x80000000L
4353//SPI_WF_LIFETIME_STATUS_10
4354#define SPI_WF_LIFETIME_STATUS_10__MAX_CNT__SHIFT 0x0
4355#define SPI_WF_LIFETIME_STATUS_10__INT_SENT__SHIFT 0x1f
4356#define SPI_WF_LIFETIME_STATUS_10__MAX_CNT_MASK 0x7FFFFFFFL
4357#define SPI_WF_LIFETIME_STATUS_10__INT_SENT_MASK 0x80000000L
4358//SPI_WF_LIFETIME_STATUS_11
4359#define SPI_WF_LIFETIME_STATUS_11__MAX_CNT__SHIFT 0x0
4360#define SPI_WF_LIFETIME_STATUS_11__INT_SENT__SHIFT 0x1f
4361#define SPI_WF_LIFETIME_STATUS_11__MAX_CNT_MASK 0x7FFFFFFFL
4362#define SPI_WF_LIFETIME_STATUS_11__INT_SENT_MASK 0x80000000L
4363//SPI_WF_LIFETIME_STATUS_12
4364#define SPI_WF_LIFETIME_STATUS_12__MAX_CNT__SHIFT 0x0
4365#define SPI_WF_LIFETIME_STATUS_12__INT_SENT__SHIFT 0x1f
4366#define SPI_WF_LIFETIME_STATUS_12__MAX_CNT_MASK 0x7FFFFFFFL
4367#define SPI_WF_LIFETIME_STATUS_12__INT_SENT_MASK 0x80000000L
4368//SPI_WF_LIFETIME_STATUS_13
4369#define SPI_WF_LIFETIME_STATUS_13__MAX_CNT__SHIFT 0x0
4370#define SPI_WF_LIFETIME_STATUS_13__INT_SENT__SHIFT 0x1f
4371#define SPI_WF_LIFETIME_STATUS_13__MAX_CNT_MASK 0x7FFFFFFFL
4372#define SPI_WF_LIFETIME_STATUS_13__INT_SENT_MASK 0x80000000L
4373//SPI_WF_LIFETIME_STATUS_14
4374#define SPI_WF_LIFETIME_STATUS_14__MAX_CNT__SHIFT 0x0
4375#define SPI_WF_LIFETIME_STATUS_14__INT_SENT__SHIFT 0x1f
4376#define SPI_WF_LIFETIME_STATUS_14__MAX_CNT_MASK 0x7FFFFFFFL
4377#define SPI_WF_LIFETIME_STATUS_14__INT_SENT_MASK 0x80000000L
4378//SPI_WF_LIFETIME_STATUS_15
4379#define SPI_WF_LIFETIME_STATUS_15__MAX_CNT__SHIFT 0x0
4380#define SPI_WF_LIFETIME_STATUS_15__INT_SENT__SHIFT 0x1f
4381#define SPI_WF_LIFETIME_STATUS_15__MAX_CNT_MASK 0x7FFFFFFFL
4382#define SPI_WF_LIFETIME_STATUS_15__INT_SENT_MASK 0x80000000L
4383//SPI_WF_LIFETIME_STATUS_16
4384#define SPI_WF_LIFETIME_STATUS_16__MAX_CNT__SHIFT 0x0
4385#define SPI_WF_LIFETIME_STATUS_16__INT_SENT__SHIFT 0x1f
4386#define SPI_WF_LIFETIME_STATUS_16__MAX_CNT_MASK 0x7FFFFFFFL
4387#define SPI_WF_LIFETIME_STATUS_16__INT_SENT_MASK 0x80000000L
4388//SPI_WF_LIFETIME_STATUS_17
4389#define SPI_WF_LIFETIME_STATUS_17__MAX_CNT__SHIFT 0x0
4390#define SPI_WF_LIFETIME_STATUS_17__INT_SENT__SHIFT 0x1f
4391#define SPI_WF_LIFETIME_STATUS_17__MAX_CNT_MASK 0x7FFFFFFFL
4392#define SPI_WF_LIFETIME_STATUS_17__INT_SENT_MASK 0x80000000L
4393//SPI_WF_LIFETIME_STATUS_18
4394#define SPI_WF_LIFETIME_STATUS_18__MAX_CNT__SHIFT 0x0
4395#define SPI_WF_LIFETIME_STATUS_18__INT_SENT__SHIFT 0x1f
4396#define SPI_WF_LIFETIME_STATUS_18__MAX_CNT_MASK 0x7FFFFFFFL
4397#define SPI_WF_LIFETIME_STATUS_18__INT_SENT_MASK 0x80000000L
4398//SPI_WF_LIFETIME_STATUS_19
4399#define SPI_WF_LIFETIME_STATUS_19__MAX_CNT__SHIFT 0x0
4400#define SPI_WF_LIFETIME_STATUS_19__INT_SENT__SHIFT 0x1f
4401#define SPI_WF_LIFETIME_STATUS_19__MAX_CNT_MASK 0x7FFFFFFFL
4402#define SPI_WF_LIFETIME_STATUS_19__INT_SENT_MASK 0x80000000L
4403//SPI_WF_LIFETIME_STATUS_20
4404#define SPI_WF_LIFETIME_STATUS_20__MAX_CNT__SHIFT 0x0
4405#define SPI_WF_LIFETIME_STATUS_20__INT_SENT__SHIFT 0x1f
4406#define SPI_WF_LIFETIME_STATUS_20__MAX_CNT_MASK 0x7FFFFFFFL
4407#define SPI_WF_LIFETIME_STATUS_20__INT_SENT_MASK 0x80000000L
4408//SPI_WF_LIFETIME_DEBUG
4409#define SPI_WF_LIFETIME_DEBUG__START_VALUE__SHIFT 0x0
4410#define SPI_WF_LIFETIME_DEBUG__OVERRIDE_EN__SHIFT 0x1f
4411#define SPI_WF_LIFETIME_DEBUG__START_VALUE_MASK 0x7FFFFFFFL
4412#define SPI_WF_LIFETIME_DEBUG__OVERRIDE_EN_MASK 0x80000000L
4413//SPI_LB_CTR_CTRL
4414#define SPI_LB_CTR_CTRL__LOAD__SHIFT 0x0
4415#define SPI_LB_CTR_CTRL__WAVES_SELECT__SHIFT 0x1
4416#define SPI_LB_CTR_CTRL__CLEAR_ON_READ__SHIFT 0x3
4417#define SPI_LB_CTR_CTRL__RESET_COUNTS__SHIFT 0x4
4418#define SPI_LB_CTR_CTRL__LOAD_MASK 0x00000001L
4419#define SPI_LB_CTR_CTRL__WAVES_SELECT_MASK 0x00000006L
4420#define SPI_LB_CTR_CTRL__CLEAR_ON_READ_MASK 0x00000008L
4421#define SPI_LB_CTR_CTRL__RESET_COUNTS_MASK 0x00000010L
4422//SPI_LB_CU_MASK
4423#define SPI_LB_CU_MASK__CU_MASK__SHIFT 0x0
4424#define SPI_LB_CU_MASK__CU_MASK_MASK 0xFFFFL
4425//SPI_LB_DATA_REG
4426#define SPI_LB_DATA_REG__CNT_DATA__SHIFT 0x0
4427#define SPI_LB_DATA_REG__CNT_DATA_MASK 0xFFFFFFFFL
4428//SPI_PG_ENABLE_STATIC_CU_MASK
4429#define SPI_PG_ENABLE_STATIC_CU_MASK__CU_MASK__SHIFT 0x0
4430#define SPI_PG_ENABLE_STATIC_CU_MASK__CU_MASK_MASK 0xFFFFL
4431//SPI_GDS_CREDITS
4432#define SPI_GDS_CREDITS__DS_DATA_CREDITS__SHIFT 0x0
4433#define SPI_GDS_CREDITS__DS_CMD_CREDITS__SHIFT 0x8
4434#define SPI_GDS_CREDITS__UNUSED__SHIFT 0x10
4435#define SPI_GDS_CREDITS__DS_DATA_CREDITS_MASK 0x000000FFL
4436#define SPI_GDS_CREDITS__DS_CMD_CREDITS_MASK 0x0000FF00L
4437#define SPI_GDS_CREDITS__UNUSED_MASK 0xFFFF0000L
4438//SPI_SX_EXPORT_BUFFER_SIZES
4439#define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE__SHIFT 0x0
4440#define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE__SHIFT 0x10
4441#define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE_MASK 0x0000FFFFL
4442#define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE_MASK 0xFFFF0000L
4443//SPI_SX_SCOREBOARD_BUFFER_SIZES
4444#define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE__SHIFT 0x0
4445#define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE__SHIFT 0x10
4446#define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE_MASK 0x0000FFFFL
4447#define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE_MASK 0xFFFF0000L
4448//SPI_CSQ_WF_ACTIVE_STATUS
4449#define SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE__SHIFT 0x0
4450#define SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE_MASK 0xFFFFFFFFL
4451//SPI_CSQ_WF_ACTIVE_COUNT_0
4452#define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT__SHIFT 0x0
4453#define SPI_CSQ_WF_ACTIVE_COUNT_0__EVENTS__SHIFT 0x10
4454#define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK 0x000007FFL
4455#define SPI_CSQ_WF_ACTIVE_COUNT_0__EVENTS_MASK 0x07FF0000L
4456//SPI_CSQ_WF_ACTIVE_COUNT_1
4457#define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT__SHIFT 0x0
4458#define SPI_CSQ_WF_ACTIVE_COUNT_1__EVENTS__SHIFT 0x10
4459#define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT_MASK 0x000007FFL
4460#define SPI_CSQ_WF_ACTIVE_COUNT_1__EVENTS_MASK 0x07FF0000L
4461//SPI_CSQ_WF_ACTIVE_COUNT_2
4462#define SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT__SHIFT 0x0
4463#define SPI_CSQ_WF_ACTIVE_COUNT_2__EVENTS__SHIFT 0x10
4464#define SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT_MASK 0x000007FFL
4465#define SPI_CSQ_WF_ACTIVE_COUNT_2__EVENTS_MASK 0x07FF0000L
4466//SPI_CSQ_WF_ACTIVE_COUNT_3
4467#define SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT__SHIFT 0x0
4468#define SPI_CSQ_WF_ACTIVE_COUNT_3__EVENTS__SHIFT 0x10
4469#define SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT_MASK 0x000007FFL
4470#define SPI_CSQ_WF_ACTIVE_COUNT_3__EVENTS_MASK 0x07FF0000L
4471//SPI_CSQ_WF_ACTIVE_COUNT_4
4472#define SPI_CSQ_WF_ACTIVE_COUNT_4__COUNT__SHIFT 0x0
4473#define SPI_CSQ_WF_ACTIVE_COUNT_4__EVENTS__SHIFT 0x10
4474#define SPI_CSQ_WF_ACTIVE_COUNT_4__COUNT_MASK 0x000007FFL
4475#define SPI_CSQ_WF_ACTIVE_COUNT_4__EVENTS_MASK 0x07FF0000L
4476//SPI_CSQ_WF_ACTIVE_COUNT_5
4477#define SPI_CSQ_WF_ACTIVE_COUNT_5__COUNT__SHIFT 0x0
4478#define SPI_CSQ_WF_ACTIVE_COUNT_5__EVENTS__SHIFT 0x10
4479#define SPI_CSQ_WF_ACTIVE_COUNT_5__COUNT_MASK 0x000007FFL
4480#define SPI_CSQ_WF_ACTIVE_COUNT_5__EVENTS_MASK 0x07FF0000L
4481//SPI_CSQ_WF_ACTIVE_COUNT_6
4482#define SPI_CSQ_WF_ACTIVE_COUNT_6__COUNT__SHIFT 0x0
4483#define SPI_CSQ_WF_ACTIVE_COUNT_6__EVENTS__SHIFT 0x10
4484#define SPI_CSQ_WF_ACTIVE_COUNT_6__COUNT_MASK 0x000007FFL
4485#define SPI_CSQ_WF_ACTIVE_COUNT_6__EVENTS_MASK 0x07FF0000L
4486//SPI_CSQ_WF_ACTIVE_COUNT_7
4487#define SPI_CSQ_WF_ACTIVE_COUNT_7__COUNT__SHIFT 0x0
4488#define SPI_CSQ_WF_ACTIVE_COUNT_7__EVENTS__SHIFT 0x10
4489#define SPI_CSQ_WF_ACTIVE_COUNT_7__COUNT_MASK 0x000007FFL
4490#define SPI_CSQ_WF_ACTIVE_COUNT_7__EVENTS_MASK 0x07FF0000L
4491//SPI_LB_DATA_WAVES
4492#define SPI_LB_DATA_WAVES__COUNT0__SHIFT 0x0
4493#define SPI_LB_DATA_WAVES__COUNT1__SHIFT 0x10
4494#define SPI_LB_DATA_WAVES__COUNT0_MASK 0x0000FFFFL
4495#define SPI_LB_DATA_WAVES__COUNT1_MASK 0xFFFF0000L
4496//SPI_LB_DATA_PERCU_WAVE_HSGS
4497#define SPI_LB_DATA_PERCU_WAVE_HSGS__CU_USED_HS__SHIFT 0x0
4498#define SPI_LB_DATA_PERCU_WAVE_HSGS__CU_USED_GS__SHIFT 0x10
4499#define SPI_LB_DATA_PERCU_WAVE_HSGS__CU_USED_HS_MASK 0x0000FFFFL
4500#define SPI_LB_DATA_PERCU_WAVE_HSGS__CU_USED_GS_MASK 0xFFFF0000L
4501//SPI_LB_DATA_PERCU_WAVE_VSPS
4502#define SPI_LB_DATA_PERCU_WAVE_VSPS__CU_USED_VS__SHIFT 0x0
4503#define SPI_LB_DATA_PERCU_WAVE_VSPS__CU_USED_PS__SHIFT 0x10
4504#define SPI_LB_DATA_PERCU_WAVE_VSPS__CU_USED_VS_MASK 0x0000FFFFL
4505#define SPI_LB_DATA_PERCU_WAVE_VSPS__CU_USED_PS_MASK 0xFFFF0000L
4506//SPI_LB_DATA_PERCU_WAVE_CS
4507#define SPI_LB_DATA_PERCU_WAVE_CS__ACTIVE__SHIFT 0x0
4508#define SPI_LB_DATA_PERCU_WAVE_CS__ACTIVE_MASK 0xFFFFL
4509//SPIS_DEBUG_READ
4510#define SPIS_DEBUG_READ__DATA__SHIFT 0x0
4511#define SPIS_DEBUG_READ__DATA_MASK 0xFFFFFFFFL
4512//BCI_DEBUG_READ
4513#define BCI_DEBUG_READ__DATA__SHIFT 0x0
4514#define BCI_DEBUG_READ__DATA_MASK 0xFFFFFFL
4515//SPI_P0_TRAP_SCREEN_PSBA_LO
4516#define SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT 0x0
4517#define SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK 0xFFFFFFFFL
4518//SPI_P0_TRAP_SCREEN_PSBA_HI
4519#define SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT 0x0
4520#define SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK 0xFFL
4521//SPI_P0_TRAP_SCREEN_PSMA_LO
4522#define SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT 0x0
4523#define SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK 0xFFFFFFFFL
4524//SPI_P0_TRAP_SCREEN_PSMA_HI
4525#define SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT 0x0
4526#define SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK 0xFFL
4527//SPI_P0_TRAP_SCREEN_GPR_MIN
4528#define SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT 0x0
4529#define SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT 0x6
4530#define SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK 0x003FL
4531#define SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK 0x03C0L
4532//SPI_P1_TRAP_SCREEN_PSBA_LO
4533#define SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT 0x0
4534#define SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK 0xFFFFFFFFL
4535//SPI_P1_TRAP_SCREEN_PSBA_HI
4536#define SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT 0x0
4537#define SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK 0xFFL
4538//SPI_P1_TRAP_SCREEN_PSMA_LO
4539#define SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT 0x0
4540#define SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK 0xFFFFFFFFL
4541//SPI_P1_TRAP_SCREEN_PSMA_HI
4542#define SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT 0x0
4543#define SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK 0xFFL
4544//SPI_P1_TRAP_SCREEN_GPR_MIN
4545#define SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT 0x0
4546#define SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT 0x6
4547#define SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK 0x003FL
4548#define SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK 0x03C0L
4549
4550
4551// addressBlock: gc_tpdec
4552//TD_CNTL
4553#define TD_CNTL__SYNC_PHASE_SH__SHIFT 0x0
4554#define TD_CNTL__SYNC_PHASE_VC_SMX__SHIFT 0x4
4555#define TD_CNTL__PAD_STALL_EN__SHIFT 0x8
4556#define TD_CNTL__EXTEND_LDS_STALL__SHIFT 0x9
4557#define TD_CNTL__LDS_STALL_PHASE_ADJUST__SHIFT 0xb
4558#define TD_CNTL__PRECISION_COMPATIBILITY__SHIFT 0xf
4559#define TD_CNTL__GATHER4_FLOAT_MODE__SHIFT 0x10
4560#define TD_CNTL__LD_FLOAT_MODE__SHIFT 0x12
4561#define TD_CNTL__GATHER4_DX9_MODE__SHIFT 0x13
4562#define TD_CNTL__DISABLE_POWER_THROTTLE__SHIFT 0x14
4563#define TD_CNTL__ENABLE_ROUND_TO_ZERO__SHIFT 0x15
4564#define TD_CNTL__DISABLE_2BIT_SIGNED_FORMAT__SHIFT 0x17
4565#define TD_CNTL__DISABLE_MM_QNAN_COMPARE_RESULT__SHIFT 0x18
4566#define TD_CNTL__SYNC_PHASE_SH_MASK 0x00000003L
4567#define TD_CNTL__SYNC_PHASE_VC_SMX_MASK 0x00000030L
4568#define TD_CNTL__PAD_STALL_EN_MASK 0x00000100L
4569#define TD_CNTL__EXTEND_LDS_STALL_MASK 0x00000600L
4570#define TD_CNTL__LDS_STALL_PHASE_ADJUST_MASK 0x00001800L
4571#define TD_CNTL__PRECISION_COMPATIBILITY_MASK 0x00008000L
4572#define TD_CNTL__GATHER4_FLOAT_MODE_MASK 0x00010000L
4573#define TD_CNTL__LD_FLOAT_MODE_MASK 0x00040000L
4574#define TD_CNTL__GATHER4_DX9_MODE_MASK 0x00080000L
4575#define TD_CNTL__DISABLE_POWER_THROTTLE_MASK 0x00100000L
4576#define TD_CNTL__ENABLE_ROUND_TO_ZERO_MASK 0x00200000L
4577#define TD_CNTL__DISABLE_2BIT_SIGNED_FORMAT_MASK 0x00800000L
4578#define TD_CNTL__DISABLE_MM_QNAN_COMPARE_RESULT_MASK 0x01000000L
4579//TD_STATUS
4580#define TD_STATUS__BUSY__SHIFT 0x1f
4581#define TD_STATUS__BUSY_MASK 0x80000000L
4582//TD_DSM_CNTL
4583#define TD_DSM_CNTL__TD_SS_FIFO_LO_DSM_IRRITATOR_DATA__SHIFT 0x0
4584#define TD_DSM_CNTL__TD_SS_FIFO_LO_ENABLE_SINGLE_WRITE__SHIFT 0x2
4585#define TD_DSM_CNTL__TD_SS_FIFO_HI_DSM_IRRITATOR_DATA__SHIFT 0x3
4586#define TD_DSM_CNTL__TD_SS_FIFO_HI_ENABLE_SINGLE_WRITE__SHIFT 0x5
4587#define TD_DSM_CNTL__TD_CS_FIFO_DSM_IRRITATOR_DATA__SHIFT 0x6
4588#define TD_DSM_CNTL__TD_CS_FIFO_ENABLE_SINGLE_WRITE__SHIFT 0x8
4589#define TD_DSM_CNTL__TD_SS_FIFO_LO_DSM_IRRITATOR_DATA_MASK 0x00000003L
4590#define TD_DSM_CNTL__TD_SS_FIFO_LO_ENABLE_SINGLE_WRITE_MASK 0x00000004L
4591#define TD_DSM_CNTL__TD_SS_FIFO_HI_DSM_IRRITATOR_DATA_MASK 0x00000018L
4592#define TD_DSM_CNTL__TD_SS_FIFO_HI_ENABLE_SINGLE_WRITE_MASK 0x00000020L
4593#define TD_DSM_CNTL__TD_CS_FIFO_DSM_IRRITATOR_DATA_MASK 0x000000C0L
4594#define TD_DSM_CNTL__TD_CS_FIFO_ENABLE_SINGLE_WRITE_MASK 0x00000100L
4595//TD_DSM_CNTL2
4596#define TD_DSM_CNTL2__TD_SS_FIFO_LO_ENABLE_ERROR_INJECT__SHIFT 0x0
4597#define TD_DSM_CNTL2__TD_SS_FIFO_LO_SELECT_INJECT_DELAY__SHIFT 0x2
4598#define TD_DSM_CNTL2__TD_SS_FIFO_HI_ENABLE_ERROR_INJECT__SHIFT 0x3
4599#define TD_DSM_CNTL2__TD_SS_FIFO_HI_SELECT_INJECT_DELAY__SHIFT 0x5
4600#define TD_DSM_CNTL2__TD_CS_FIFO_ENABLE_ERROR_INJECT__SHIFT 0x6
4601#define TD_DSM_CNTL2__TD_CS_FIFO_SELECT_INJECT_DELAY__SHIFT 0x8
4602#define TD_DSM_CNTL2__TD_INJECT_DELAY__SHIFT 0x1a
4603#define TD_DSM_CNTL2__TD_SS_FIFO_LO_ENABLE_ERROR_INJECT_MASK 0x00000003L
4604#define TD_DSM_CNTL2__TD_SS_FIFO_LO_SELECT_INJECT_DELAY_MASK 0x00000004L
4605#define TD_DSM_CNTL2__TD_SS_FIFO_HI_ENABLE_ERROR_INJECT_MASK 0x00000018L
4606#define TD_DSM_CNTL2__TD_SS_FIFO_HI_SELECT_INJECT_DELAY_MASK 0x00000020L
4607#define TD_DSM_CNTL2__TD_CS_FIFO_ENABLE_ERROR_INJECT_MASK 0x000000C0L
4608#define TD_DSM_CNTL2__TD_CS_FIFO_SELECT_INJECT_DELAY_MASK 0x00000100L
4609#define TD_DSM_CNTL2__TD_INJECT_DELAY_MASK 0xFC000000L
4610//TD_SCRATCH
4611#define TD_SCRATCH__SCRATCH__SHIFT 0x0
4612#define TD_SCRATCH__SCRATCH_MASK 0xFFFFFFFFL
4613//TA_CNTL
4614#define TA_CNTL__FX_XNACK_CREDIT__SHIFT 0x0
4615#define TA_CNTL__SQ_XNACK_CREDIT__SHIFT 0x9
4616#define TA_CNTL__TC_DATA_CREDIT__SHIFT 0xd
4617#define TA_CNTL__ALIGNER_CREDIT__SHIFT 0x10
4618#define TA_CNTL__TD_FIFO_CREDIT__SHIFT 0x16
4619#define TA_CNTL__FX_XNACK_CREDIT_MASK 0x0000007FL
4620#define TA_CNTL__SQ_XNACK_CREDIT_MASK 0x00001E00L
4621#define TA_CNTL__TC_DATA_CREDIT_MASK 0x0000E000L
4622#define TA_CNTL__ALIGNER_CREDIT_MASK 0x001F0000L
4623#define TA_CNTL__TD_FIFO_CREDIT_MASK 0xFFC00000L
4624//TA_CNTL_AUX
4625#define TA_CNTL_AUX__SCOAL_DSWIZZLE_N__SHIFT 0x0
4626#define TA_CNTL_AUX__RESERVED__SHIFT 0x1
4627#define TA_CNTL_AUX__TFAULT_EN_OVERRIDE__SHIFT 0x5
4628#define TA_CNTL_AUX__GATHERH_DST_SEL__SHIFT 0x6
4629#define TA_CNTL_AUX__DISABLE_GATHER4_BC_SWIZZLE__SHIFT 0x7
4630#define TA_CNTL_AUX__NONIMG_ANISO_BYPASS__SHIFT 0x9
4631#define TA_CNTL_AUX__ANISO_HALF_THRESH__SHIFT 0xa
4632#define TA_CNTL_AUX__ANISO_ERROR_FP_VBIAS__SHIFT 0xc
4633#define TA_CNTL_AUX__ANISO_STEP_ORDER__SHIFT 0xd
4634#define TA_CNTL_AUX__ANISO_STEP__SHIFT 0xe
4635#define TA_CNTL_AUX__MINMAG_UNNORM__SHIFT 0xf
4636#define TA_CNTL_AUX__ANISO_WEIGHT_MODE__SHIFT 0x10
4637#define TA_CNTL_AUX__ANISO_RATIO_LUT__SHIFT 0x11
4638#define TA_CNTL_AUX__ANISO_TAP__SHIFT 0x12
4639#define TA_CNTL_AUX__ANISO_MIP_ADJ_MODE__SHIFT 0x13
4640#define TA_CNTL_AUX__DETERMINISM_RESERVED_DISABLE__SHIFT 0x14
4641#define TA_CNTL_AUX__DETERMINISM_OPCODE_STRICT_DISABLE__SHIFT 0x15
4642#define TA_CNTL_AUX__DETERMINISM_MISC_DISABLE__SHIFT 0x16
4643#define TA_CNTL_AUX__DETERMINISM_SAMPLE_C_DFMT_DISABLE__SHIFT 0x17
4644#define TA_CNTL_AUX__DETERMINISM_SAMPLER_MSAA_DISABLE__SHIFT 0x18
4645#define TA_CNTL_AUX__DETERMINISM_WRITEOP_READFMT_DISABLE__SHIFT 0x19
4646#define TA_CNTL_AUX__DETERMINISM_DFMT_NFMT_DISABLE__SHIFT 0x1a
4647#define TA_CNTL_AUX__DISABLE_DWORD_X2_COALESCE__SHIFT 0x1b
4648#define TA_CNTL_AUX__CUBEMAP_SLICE_CLAMP__SHIFT 0x1c
4649#define TA_CNTL_AUX__TRUNC_SMALL_NEG__SHIFT 0x1d
4650#define TA_CNTL_AUX__ARRAY_ROUND_MODE__SHIFT 0x1e
4651#define TA_CNTL_AUX__SCOAL_DSWIZZLE_N_MASK 0x00000001L
4652#define TA_CNTL_AUX__RESERVED_MASK 0x0000000EL
4653#define TA_CNTL_AUX__TFAULT_EN_OVERRIDE_MASK 0x00000020L
4654#define TA_CNTL_AUX__GATHERH_DST_SEL_MASK 0x00000040L
4655#define TA_CNTL_AUX__DISABLE_GATHER4_BC_SWIZZLE_MASK 0x00000080L
4656#define TA_CNTL_AUX__NONIMG_ANISO_BYPASS_MASK 0x00000200L
4657#define TA_CNTL_AUX__ANISO_HALF_THRESH_MASK 0x00000C00L
4658#define TA_CNTL_AUX__ANISO_ERROR_FP_VBIAS_MASK 0x00001000L
4659#define TA_CNTL_AUX__ANISO_STEP_ORDER_MASK 0x00002000L
4660#define TA_CNTL_AUX__ANISO_STEP_MASK 0x00004000L
4661#define TA_CNTL_AUX__MINMAG_UNNORM_MASK 0x00008000L
4662#define TA_CNTL_AUX__ANISO_WEIGHT_MODE_MASK 0x00010000L
4663#define TA_CNTL_AUX__ANISO_RATIO_LUT_MASK 0x00020000L
4664#define TA_CNTL_AUX__ANISO_TAP_MASK 0x00040000L
4665#define TA_CNTL_AUX__ANISO_MIP_ADJ_MODE_MASK 0x00080000L
4666#define TA_CNTL_AUX__DETERMINISM_RESERVED_DISABLE_MASK 0x00100000L
4667#define TA_CNTL_AUX__DETERMINISM_OPCODE_STRICT_DISABLE_MASK 0x00200000L
4668#define TA_CNTL_AUX__DETERMINISM_MISC_DISABLE_MASK 0x00400000L
4669#define TA_CNTL_AUX__DETERMINISM_SAMPLE_C_DFMT_DISABLE_MASK 0x00800000L
4670#define TA_CNTL_AUX__DETERMINISM_SAMPLER_MSAA_DISABLE_MASK 0x01000000L
4671#define TA_CNTL_AUX__DETERMINISM_WRITEOP_READFMT_DISABLE_MASK 0x02000000L
4672#define TA_CNTL_AUX__DETERMINISM_DFMT_NFMT_DISABLE_MASK 0x04000000L
4673#define TA_CNTL_AUX__DISABLE_DWORD_X2_COALESCE_MASK 0x08000000L
4674#define TA_CNTL_AUX__CUBEMAP_SLICE_CLAMP_MASK 0x10000000L
4675#define TA_CNTL_AUX__TRUNC_SMALL_NEG_MASK 0x20000000L
4676#define TA_CNTL_AUX__ARRAY_ROUND_MODE_MASK 0xC0000000L
4677//TA_RESERVED_010C
4678#define TA_RESERVED_010C__Unused__SHIFT 0x0
4679#define TA_RESERVED_010C__Unused_MASK 0xFFFFFFFFL
4680//TA_STATUS
4681#define TA_STATUS__FG_PFIFO_EMPTYB__SHIFT 0xc
4682#define TA_STATUS__FG_LFIFO_EMPTYB__SHIFT 0xd
4683#define TA_STATUS__FG_SFIFO_EMPTYB__SHIFT 0xe
4684#define TA_STATUS__FL_PFIFO_EMPTYB__SHIFT 0x10
4685#define TA_STATUS__FL_LFIFO_EMPTYB__SHIFT 0x11
4686#define TA_STATUS__FL_SFIFO_EMPTYB__SHIFT 0x12
4687#define TA_STATUS__FA_PFIFO_EMPTYB__SHIFT 0x14
4688#define TA_STATUS__FA_LFIFO_EMPTYB__SHIFT 0x15
4689#define TA_STATUS__FA_SFIFO_EMPTYB__SHIFT 0x16
4690#define TA_STATUS__IN_BUSY__SHIFT 0x18
4691#define TA_STATUS__FG_BUSY__SHIFT 0x19
4692#define TA_STATUS__LA_BUSY__SHIFT 0x1a
4693#define TA_STATUS__FL_BUSY__SHIFT 0x1b
4694#define TA_STATUS__TA_BUSY__SHIFT 0x1c
4695#define TA_STATUS__FA_BUSY__SHIFT 0x1d
4696#define TA_STATUS__AL_BUSY__SHIFT 0x1e
4697#define TA_STATUS__BUSY__SHIFT 0x1f
4698#define TA_STATUS__FG_PFIFO_EMPTYB_MASK 0x00001000L
4699#define TA_STATUS__FG_LFIFO_EMPTYB_MASK 0x00002000L
4700#define TA_STATUS__FG_SFIFO_EMPTYB_MASK 0x00004000L
4701#define TA_STATUS__FL_PFIFO_EMPTYB_MASK 0x00010000L
4702#define TA_STATUS__FL_LFIFO_EMPTYB_MASK 0x00020000L
4703#define TA_STATUS__FL_SFIFO_EMPTYB_MASK 0x00040000L
4704#define TA_STATUS__FA_PFIFO_EMPTYB_MASK 0x00100000L
4705#define TA_STATUS__FA_LFIFO_EMPTYB_MASK 0x00200000L
4706#define TA_STATUS__FA_SFIFO_EMPTYB_MASK 0x00400000L
4707#define TA_STATUS__IN_BUSY_MASK 0x01000000L
4708#define TA_STATUS__FG_BUSY_MASK 0x02000000L
4709#define TA_STATUS__LA_BUSY_MASK 0x04000000L
4710#define TA_STATUS__FL_BUSY_MASK 0x08000000L
4711#define TA_STATUS__TA_BUSY_MASK 0x10000000L
4712#define TA_STATUS__FA_BUSY_MASK 0x20000000L
4713#define TA_STATUS__AL_BUSY_MASK 0x40000000L
4714#define TA_STATUS__BUSY_MASK 0x80000000L
4715//TA_SCRATCH
4716#define TA_SCRATCH__SCRATCH__SHIFT 0x0
4717#define TA_SCRATCH__SCRATCH_MASK 0xFFFFFFFFL
4718
4719
4720// addressBlock: gc_gdsdec
4721//GDS_CONFIG
4722#define GDS_CONFIG__SH0_GPR_PHASE_SEL__SHIFT 0x1
4723#define GDS_CONFIG__SH1_GPR_PHASE_SEL__SHIFT 0x3
4724#define GDS_CONFIG__SH2_GPR_PHASE_SEL__SHIFT 0x5
4725#define GDS_CONFIG__SH3_GPR_PHASE_SEL__SHIFT 0x7
4726#define GDS_CONFIG__SH0_GPR_PHASE_SEL_MASK 0x00000006L
4727#define GDS_CONFIG__SH1_GPR_PHASE_SEL_MASK 0x00000018L
4728#define GDS_CONFIG__SH2_GPR_PHASE_SEL_MASK 0x00000060L
4729#define GDS_CONFIG__SH3_GPR_PHASE_SEL_MASK 0x00000180L
4730//GDS_CNTL_STATUS
4731#define GDS_CNTL_STATUS__GDS_BUSY__SHIFT 0x0
4732#define GDS_CNTL_STATUS__GRBM_WBUF_BUSY__SHIFT 0x1
4733#define GDS_CNTL_STATUS__ORD_APP_BUSY__SHIFT 0x2
4734#define GDS_CNTL_STATUS__DS_BANK_CONFLICT__SHIFT 0x3
4735#define GDS_CNTL_STATUS__DS_ADDR_CONFLICT__SHIFT 0x4
4736#define GDS_CNTL_STATUS__DS_WR_CLAMP__SHIFT 0x5
4737#define GDS_CNTL_STATUS__DS_RD_CLAMP__SHIFT 0x6
4738#define GDS_CNTL_STATUS__GRBM_RBUF_BUSY__SHIFT 0x7
4739#define GDS_CNTL_STATUS__DS_BUSY__SHIFT 0x8
4740#define GDS_CNTL_STATUS__GWS_BUSY__SHIFT 0x9
4741#define GDS_CNTL_STATUS__ORD_FIFO_BUSY__SHIFT 0xa
4742#define GDS_CNTL_STATUS__CREDIT_BUSY0__SHIFT 0xb
4743#define GDS_CNTL_STATUS__CREDIT_BUSY1__SHIFT 0xc
4744#define GDS_CNTL_STATUS__CREDIT_BUSY2__SHIFT 0xd
4745#define GDS_CNTL_STATUS__CREDIT_BUSY3__SHIFT 0xe
4746#define GDS_CNTL_STATUS__GDS_BUSY_MASK 0x00000001L
4747#define GDS_CNTL_STATUS__GRBM_WBUF_BUSY_MASK 0x00000002L
4748#define GDS_CNTL_STATUS__ORD_APP_BUSY_MASK 0x00000004L
4749#define GDS_CNTL_STATUS__DS_BANK_CONFLICT_MASK 0x00000008L
4750#define GDS_CNTL_STATUS__DS_ADDR_CONFLICT_MASK 0x00000010L
4751#define GDS_CNTL_STATUS__DS_WR_CLAMP_MASK 0x00000020L
4752#define GDS_CNTL_STATUS__DS_RD_CLAMP_MASK 0x00000040L
4753#define GDS_CNTL_STATUS__GRBM_RBUF_BUSY_MASK 0x00000080L
4754#define GDS_CNTL_STATUS__DS_BUSY_MASK 0x00000100L
4755#define GDS_CNTL_STATUS__GWS_BUSY_MASK 0x00000200L
4756#define GDS_CNTL_STATUS__ORD_FIFO_BUSY_MASK 0x00000400L
4757#define GDS_CNTL_STATUS__CREDIT_BUSY0_MASK 0x00000800L
4758#define GDS_CNTL_STATUS__CREDIT_BUSY1_MASK 0x00001000L
4759#define GDS_CNTL_STATUS__CREDIT_BUSY2_MASK 0x00002000L
4760#define GDS_CNTL_STATUS__CREDIT_BUSY3_MASK 0x00004000L
4761//GDS_ENHANCE2
4762#define GDS_ENHANCE2__MISC__SHIFT 0x0
4763#define GDS_ENHANCE2__UNUSED__SHIFT 0x10
4764#define GDS_ENHANCE2__MISC_MASK 0x0000FFFFL
4765#define GDS_ENHANCE2__UNUSED_MASK 0xFFFF0000L
4766//GDS_PROTECTION_FAULT
4767#define GDS_PROTECTION_FAULT__WRITE_DIS__SHIFT 0x0
4768#define GDS_PROTECTION_FAULT__FAULT_DETECTED__SHIFT 0x1
4769#define GDS_PROTECTION_FAULT__GRBM__SHIFT 0x2
4770#define GDS_PROTECTION_FAULT__SH_ID__SHIFT 0x3
4771#define GDS_PROTECTION_FAULT__CU_ID__SHIFT 0x6
4772#define GDS_PROTECTION_FAULT__SIMD_ID__SHIFT 0xa
4773#define GDS_PROTECTION_FAULT__WAVE_ID__SHIFT 0xc
4774#define GDS_PROTECTION_FAULT__ADDRESS__SHIFT 0x10
4775#define GDS_PROTECTION_FAULT__WRITE_DIS_MASK 0x00000001L
4776#define GDS_PROTECTION_FAULT__FAULT_DETECTED_MASK 0x00000002L
4777#define GDS_PROTECTION_FAULT__GRBM_MASK 0x00000004L
4778#define GDS_PROTECTION_FAULT__SH_ID_MASK 0x00000038L
4779#define GDS_PROTECTION_FAULT__CU_ID_MASK 0x000003C0L
4780#define GDS_PROTECTION_FAULT__SIMD_ID_MASK 0x00000C00L
4781#define GDS_PROTECTION_FAULT__WAVE_ID_MASK 0x0000F000L
4782#define GDS_PROTECTION_FAULT__ADDRESS_MASK 0xFFFF0000L
4783//GDS_VM_PROTECTION_FAULT
4784#define GDS_VM_PROTECTION_FAULT__WRITE_DIS__SHIFT 0x0
4785#define GDS_VM_PROTECTION_FAULT__FAULT_DETECTED__SHIFT 0x1
4786#define GDS_VM_PROTECTION_FAULT__GWS__SHIFT 0x2
4787#define GDS_VM_PROTECTION_FAULT__OA__SHIFT 0x3
4788#define GDS_VM_PROTECTION_FAULT__GRBM__SHIFT 0x4
4789#define GDS_VM_PROTECTION_FAULT__TMZ__SHIFT 0x5
4790#define GDS_VM_PROTECTION_FAULT__VMID__SHIFT 0x8
4791#define GDS_VM_PROTECTION_FAULT__ADDRESS__SHIFT 0x10
4792#define GDS_VM_PROTECTION_FAULT__WRITE_DIS_MASK 0x00000001L
4793#define GDS_VM_PROTECTION_FAULT__FAULT_DETECTED_MASK 0x00000002L
4794#define GDS_VM_PROTECTION_FAULT__GWS_MASK 0x00000004L
4795#define GDS_VM_PROTECTION_FAULT__OA_MASK 0x00000008L
4796#define GDS_VM_PROTECTION_FAULT__GRBM_MASK 0x00000010L
4797#define GDS_VM_PROTECTION_FAULT__TMZ_MASK 0x00000020L
4798#define GDS_VM_PROTECTION_FAULT__VMID_MASK 0x00000F00L
4799#define GDS_VM_PROTECTION_FAULT__ADDRESS_MASK 0xFFFF0000L
4800//GDS_EDC_CNT
4801#define GDS_EDC_CNT__GDS_MEM_DED__SHIFT 0x0
4802#define GDS_EDC_CNT__GDS_INPUT_QUEUE_SED__SHIFT 0x2
4803#define GDS_EDC_CNT__GDS_MEM_SEC__SHIFT 0x4
4804#define GDS_EDC_CNT__UNUSED__SHIFT 0x6
4805#define GDS_EDC_CNT__GDS_MEM_DED_MASK 0x00000003L
4806#define GDS_EDC_CNT__GDS_INPUT_QUEUE_SED_MASK 0x0000000CL
4807#define GDS_EDC_CNT__GDS_MEM_SEC_MASK 0x00000030L
4808#define GDS_EDC_CNT__UNUSED_MASK 0xFFFFFFC0L
4809//GDS_EDC_GRBM_CNT
4810#define GDS_EDC_GRBM_CNT__DED__SHIFT 0x0
4811#define GDS_EDC_GRBM_CNT__SEC__SHIFT 0x2
4812#define GDS_EDC_GRBM_CNT__UNUSED__SHIFT 0x4
4813#define GDS_EDC_GRBM_CNT__DED_MASK 0x00000003L
4814#define GDS_EDC_GRBM_CNT__SEC_MASK 0x0000000CL
4815#define GDS_EDC_GRBM_CNT__UNUSED_MASK 0xFFFFFFF0L
4816//GDS_EDC_OA_DED
4817#define GDS_EDC_OA_DED__ME0_GFXHP3D_PIX_DED__SHIFT 0x0
4818#define GDS_EDC_OA_DED__ME0_GFXHP3D_VTX_DED__SHIFT 0x1
4819#define GDS_EDC_OA_DED__ME0_CS_DED__SHIFT 0x2
4820#define GDS_EDC_OA_DED__ME0_GFXHP3D_GS_DED__SHIFT 0x3
4821#define GDS_EDC_OA_DED__ME1_PIPE0_DED__SHIFT 0x4
4822#define GDS_EDC_OA_DED__ME1_PIPE1_DED__SHIFT 0x5
4823#define GDS_EDC_OA_DED__ME1_PIPE2_DED__SHIFT 0x6
4824#define GDS_EDC_OA_DED__ME1_PIPE3_DED__SHIFT 0x7
4825#define GDS_EDC_OA_DED__ME2_PIPE0_DED__SHIFT 0x8
4826#define GDS_EDC_OA_DED__ME2_PIPE1_DED__SHIFT 0x9
4827#define GDS_EDC_OA_DED__ME2_PIPE2_DED__SHIFT 0xa
4828#define GDS_EDC_OA_DED__ME2_PIPE3_DED__SHIFT 0xb
4829#define GDS_EDC_OA_DED__UNUSED1__SHIFT 0xc
4830#define GDS_EDC_OA_DED__ME0_GFXHP3D_PIX_DED_MASK 0x00000001L
4831#define GDS_EDC_OA_DED__ME0_GFXHP3D_VTX_DED_MASK 0x00000002L
4832#define GDS_EDC_OA_DED__ME0_CS_DED_MASK 0x00000004L
4833#define GDS_EDC_OA_DED__ME0_GFXHP3D_GS_DED_MASK 0x00000008L
4834#define GDS_EDC_OA_DED__ME1_PIPE0_DED_MASK 0x00000010L
4835#define GDS_EDC_OA_DED__ME1_PIPE1_DED_MASK 0x00000020L
4836#define GDS_EDC_OA_DED__ME1_PIPE2_DED_MASK 0x00000040L
4837#define GDS_EDC_OA_DED__ME1_PIPE3_DED_MASK 0x00000080L
4838#define GDS_EDC_OA_DED__ME2_PIPE0_DED_MASK 0x00000100L
4839#define GDS_EDC_OA_DED__ME2_PIPE1_DED_MASK 0x00000200L
4840#define GDS_EDC_OA_DED__ME2_PIPE2_DED_MASK 0x00000400L
4841#define GDS_EDC_OA_DED__ME2_PIPE3_DED_MASK 0x00000800L
4842#define GDS_EDC_OA_DED__UNUSED1_MASK 0xFFFFF000L
4843//GDS_DSM_CNTL
4844#define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_0__SHIFT 0x0
4845#define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_1__SHIFT 0x1
4846#define GDS_DSM_CNTL__GDS_MEM_ENABLE_SINGLE_WRITE__SHIFT 0x2
4847#define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_0__SHIFT 0x3
4848#define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_1__SHIFT 0x4
4849#define GDS_DSM_CNTL__GDS_INPUT_QUEUE_ENABLE_SINGLE_WRITE__SHIFT 0x5
4850#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_0__SHIFT 0x6
4851#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_1__SHIFT 0x7
4852#define GDS_DSM_CNTL__GDS_PHY_CMD_RAM_ENABLE_SINGLE_WRITE__SHIFT 0x8
4853#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_0__SHIFT 0x9
4854#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_1__SHIFT 0xa
4855#define GDS_DSM_CNTL__GDS_PHY_DATA_RAM_ENABLE_SINGLE_WRITE__SHIFT 0xb
4856#define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_0__SHIFT 0xc
4857#define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_1__SHIFT 0xd
4858#define GDS_DSM_CNTL__GDS_PIPE_MEM_ENABLE_SINGLE_WRITE__SHIFT 0xe
4859#define GDS_DSM_CNTL__UNUSED__SHIFT 0xf
4860#define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_0_MASK 0x00000001L
4861#define GDS_DSM_CNTL__SEL_DSM_GDS_MEM_IRRITATOR_DATA_1_MASK 0x00000002L
4862#define GDS_DSM_CNTL__GDS_MEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L
4863#define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_0_MASK 0x00000008L
4864#define GDS_DSM_CNTL__SEL_DSM_GDS_INPUT_QUEUE_IRRITATOR_DATA_1_MASK 0x00000010L
4865#define GDS_DSM_CNTL__GDS_INPUT_QUEUE_ENABLE_SINGLE_WRITE_MASK 0x00000020L
4866#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_0_MASK 0x00000040L
4867#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_CMD_RAM_IRRITATOR_DATA_1_MASK 0x00000080L
4868#define GDS_DSM_CNTL__GDS_PHY_CMD_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000100L
4869#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_0_MASK 0x00000200L
4870#define GDS_DSM_CNTL__SEL_DSM_GDS_PHY_DATA_RAM_IRRITATOR_DATA_1_MASK 0x00000400L
4871#define GDS_DSM_CNTL__GDS_PHY_DATA_RAM_ENABLE_SINGLE_WRITE_MASK 0x00000800L
4872#define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_0_MASK 0x00001000L
4873#define GDS_DSM_CNTL__SEL_DSM_GDS_PIPE_MEM_IRRITATOR_DATA_1_MASK 0x00002000L
4874#define GDS_DSM_CNTL__GDS_PIPE_MEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L
4875#define GDS_DSM_CNTL__UNUSED_MASK 0xFFFF8000L
4876//GDS_EDC_OA_PHY_CNT
4877#define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_SEC__SHIFT 0x0
4878#define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_DED__SHIFT 0x2
4879#define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_SEC__SHIFT 0x4
4880#define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_DED__SHIFT 0x6
4881#define GDS_EDC_OA_PHY_CNT__PHY_DATA_RAM_MEM_SED__SHIFT 0x8
4882#define GDS_EDC_OA_PHY_CNT__UNUSED1__SHIFT 0xa
4883#define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_SEC_MASK 0x00000003L
4884#define GDS_EDC_OA_PHY_CNT__ME0_CS_PIPE_MEM_DED_MASK 0x0000000CL
4885#define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_SEC_MASK 0x00000030L
4886#define GDS_EDC_OA_PHY_CNT__PHY_CMD_RAM_MEM_DED_MASK 0x000000C0L
4887#define GDS_EDC_OA_PHY_CNT__PHY_DATA_RAM_MEM_SED_MASK 0x00000300L
4888#define GDS_EDC_OA_PHY_CNT__UNUSED1_MASK 0xFFFFFC00L
4889//GDS_EDC_OA_PIPE_CNT
4890#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_SEC__SHIFT 0x0
4891#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_DED__SHIFT 0x2
4892#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_SEC__SHIFT 0x4
4893#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_DED__SHIFT 0x6
4894#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_SEC__SHIFT 0x8
4895#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_DED__SHIFT 0xa
4896#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_SEC__SHIFT 0xc
4897#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_DED__SHIFT 0xe
4898#define GDS_EDC_OA_PIPE_CNT__UNUSED__SHIFT 0x10
4899#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_SEC_MASK 0x00000003L
4900#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE0_PIPE_MEM_DED_MASK 0x0000000CL
4901#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_SEC_MASK 0x00000030L
4902#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE1_PIPE_MEM_DED_MASK 0x000000C0L
4903#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_SEC_MASK 0x00000300L
4904#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE2_PIPE_MEM_DED_MASK 0x00000C00L
4905#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_SEC_MASK 0x00003000L
4906#define GDS_EDC_OA_PIPE_CNT__ME1_PIPE3_PIPE_MEM_DED_MASK 0x0000C000L
4907#define GDS_EDC_OA_PIPE_CNT__UNUSED_MASK 0xFFFF0000L
4908//GDS_DSM_CNTL2
4909#define GDS_DSM_CNTL2__GDS_MEM_ENABLE_ERROR_INJECT__SHIFT 0x0
4910#define GDS_DSM_CNTL2__GDS_MEM_SELECT_INJECT_DELAY__SHIFT 0x2
4911#define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_ENABLE_ERROR_INJECT__SHIFT 0x3
4912#define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_SELECT_INJECT_DELAY__SHIFT 0x5
4913#define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_ENABLE_ERROR_INJECT__SHIFT 0x6
4914#define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_SELECT_INJECT_DELAY__SHIFT 0x8
4915#define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_ENABLE_ERROR_INJECT__SHIFT 0x9
4916#define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_SELECT_INJECT_DELAY__SHIFT 0xb
4917#define GDS_DSM_CNTL2__GDS_PIPE_MEM_ENABLE_ERROR_INJECT__SHIFT 0xc
4918#define GDS_DSM_CNTL2__GDS_PIPE_MEM_SELECT_INJECT_DELAY__SHIFT 0xe
4919#define GDS_DSM_CNTL2__UNUSED__SHIFT 0xf
4920#define GDS_DSM_CNTL2__GDS_INJECT_DELAY__SHIFT 0x1a
4921#define GDS_DSM_CNTL2__GDS_MEM_ENABLE_ERROR_INJECT_MASK 0x00000003L
4922#define GDS_DSM_CNTL2__GDS_MEM_SELECT_INJECT_DELAY_MASK 0x00000004L
4923#define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_ENABLE_ERROR_INJECT_MASK 0x00000018L
4924#define GDS_DSM_CNTL2__GDS_INPUT_QUEUE_SELECT_INJECT_DELAY_MASK 0x00000020L
4925#define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_ENABLE_ERROR_INJECT_MASK 0x000000C0L
4926#define GDS_DSM_CNTL2__GDS_PHY_CMD_RAM_SELECT_INJECT_DELAY_MASK 0x00000100L
4927#define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_ENABLE_ERROR_INJECT_MASK 0x00000600L
4928#define GDS_DSM_CNTL2__GDS_PHY_DATA_RAM_SELECT_INJECT_DELAY_MASK 0x00000800L
4929#define GDS_DSM_CNTL2__GDS_PIPE_MEM_ENABLE_ERROR_INJECT_MASK 0x00003000L
4930#define GDS_DSM_CNTL2__GDS_PIPE_MEM_SELECT_INJECT_DELAY_MASK 0x00004000L
4931#define GDS_DSM_CNTL2__UNUSED_MASK 0x03FF8000L
4932#define GDS_DSM_CNTL2__GDS_INJECT_DELAY_MASK 0xFC000000L
4933//GDS_WD_GDS_CSB
4934#define GDS_WD_GDS_CSB__COUNTER__SHIFT 0x0
4935#define GDS_WD_GDS_CSB__UNUSED__SHIFT 0xd
4936#define GDS_WD_GDS_CSB__COUNTER_MASK 0x00001FFFL
4937#define GDS_WD_GDS_CSB__UNUSED_MASK 0xFFFFE000L
4938
4939
4940// addressBlock: gc_rbdec
4941//DB_DEBUG
4942#define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE__SHIFT 0x0
4943#define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE__SHIFT 0x1
4944#define DB_DEBUG__FETCH_FULL_Z_TILE__SHIFT 0x2
4945#define DB_DEBUG__FETCH_FULL_STENCIL_TILE__SHIFT 0x3
4946#define DB_DEBUG__FORCE_Z_MODE__SHIFT 0x4
4947#define DB_DEBUG__DEBUG_FORCE_DEPTH_READ__SHIFT 0x6
4948#define DB_DEBUG__DEBUG_FORCE_STENCIL_READ__SHIFT 0x7
4949#define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE__SHIFT 0x8
4950#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0__SHIFT 0xa
4951#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1__SHIFT 0xc
4952#define DB_DEBUG__DEBUG_FAST_Z_DISABLE__SHIFT 0xe
4953#define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE__SHIFT 0xf
4954#define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE__SHIFT 0x10
4955#define DB_DEBUG__DISABLE_SUMM_SQUADS__SHIFT 0x11
4956#define DB_DEBUG__DEPTH_CACHE_FORCE_MISS__SHIFT 0x12
4957#define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE__SHIFT 0x13
4958#define DB_DEBUG__NEVER_FREE_Z_ONLY__SHIFT 0x15
4959#define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS__SHIFT 0x16
4960#define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION__SHIFT 0x17
4961#define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES__SHIFT 0x18
4962#define DB_DEBUG__ONE_FREE_IN_FLIGHT__SHIFT 0x1c
4963#define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT__SHIFT 0x1d
4964#define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC__SHIFT 0x1e
4965#define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC__SHIFT 0x1f
4966#define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE_MASK 0x00000001L
4967#define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE_MASK 0x00000002L
4968#define DB_DEBUG__FETCH_FULL_Z_TILE_MASK 0x00000004L
4969#define DB_DEBUG__FETCH_FULL_STENCIL_TILE_MASK 0x00000008L
4970#define DB_DEBUG__FORCE_Z_MODE_MASK 0x00000030L
4971#define DB_DEBUG__DEBUG_FORCE_DEPTH_READ_MASK 0x00000040L
4972#define DB_DEBUG__DEBUG_FORCE_STENCIL_READ_MASK 0x00000080L
4973#define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE_MASK 0x00000300L
4974#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0_MASK 0x00000C00L
4975#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1_MASK 0x00003000L
4976#define DB_DEBUG__DEBUG_FAST_Z_DISABLE_MASK 0x00004000L
4977#define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE_MASK 0x00008000L
4978#define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE_MASK 0x00010000L
4979#define DB_DEBUG__DISABLE_SUMM_SQUADS_MASK 0x00020000L
4980#define DB_DEBUG__DEPTH_CACHE_FORCE_MISS_MASK 0x00040000L
4981#define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE_MASK 0x00180000L
4982#define DB_DEBUG__NEVER_FREE_Z_ONLY_MASK 0x00200000L
4983#define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS_MASK 0x00400000L
4984#define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION_MASK 0x00800000L
4985#define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES_MASK 0x0F000000L
4986#define DB_DEBUG__ONE_FREE_IN_FLIGHT_MASK 0x10000000L
4987#define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT_MASK 0x20000000L
4988#define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC_MASK 0x40000000L
4989#define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC_MASK 0x80000000L
4990//DB_DEBUG2
4991#define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING__SHIFT 0x0
4992#define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE__SHIFT 0x1
4993#define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE__SHIFT 0x2
4994#define DB_DEBUG2__DTR_ROUND_ROBIN_ARB__SHIFT 0x3
4995#define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM__SHIFT 0x4
4996#define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL__SHIFT 0x5
4997#define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_REZ__SHIFT 0x6
4998#define DB_DEBUG2__ENABLE_VIEWPORT_STALL_ON_ALL__SHIFT 0x7
4999#define DB_DEBUG2__OPTIMIZE_HIZ_MATCHES_FB_DISABLE__SHIFT 0x8
5000#define DB_DEBUG2__CLK_OFF_DELAY__SHIFT 0x9
5001#define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER__SHIFT 0xe
5002#define DB_DEBUG2__ENABLE_SUBTILE_GROUPING__SHIFT 0xf
5003#define DB_DEBUG2__RESERVED__SHIFT 0x10
5004#define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING__SHIFT 0x11
5005#define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING__SHIFT 0x12
5006#define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL__SHIFT 0x13
5007#define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM__SHIFT 0x1c
5008#define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL__SHIFT 0x1d
5009#define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM__SHIFT 0x1e
5010#define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT__SHIFT 0x1f
5011#define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING_MASK 0x00000001L
5012#define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE_MASK 0x00000002L
5013#define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE_MASK 0x00000004L
5014#define DB_DEBUG2__DTR_ROUND_ROBIN_ARB_MASK 0x00000008L
5015#define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM_MASK 0x00000010L
5016#define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_MASK 0x00000020L
5017#define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_REZ_MASK 0x00000040L
5018#define DB_DEBUG2__ENABLE_VIEWPORT_STALL_ON_ALL_MASK 0x00000080L
5019#define DB_DEBUG2__OPTIMIZE_HIZ_MATCHES_FB_DISABLE_MASK 0x00000100L
5020#define DB_DEBUG2__CLK_OFF_DELAY_MASK 0x00003E00L
5021#define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER_MASK 0x00004000L
5022#define DB_DEBUG2__ENABLE_SUBTILE_GROUPING_MASK 0x00008000L
5023#define DB_DEBUG2__RESERVED_MASK 0x00010000L
5024#define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING_MASK 0x00020000L
5025#define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING_MASK 0x00040000L
5026#define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL_MASK 0x00080000L
5027#define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM_MASK 0x10000000L
5028#define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL_MASK 0x20000000L
5029#define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM_MASK 0x40000000L
5030#define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT_MASK 0x80000000L
5031//DB_DEBUG3
5032#define DB_DEBUG3__DISABLE_CLEAR_ZRANGE_CORRECTION__SHIFT 0x0
5033#define DB_DEBUG3__ROUND_ZRANGE_CORRECTION__SHIFT 0x1
5034#define DB_DEBUG3__FORCE_DB_IS_GOOD__SHIFT 0x2
5035#define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION__SHIFT 0x3
5036#define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP__SHIFT 0x4
5037#define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z__SHIFT 0x5
5038#define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z__SHIFT 0x6
5039#define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS__SHIFT 0x7
5040#define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION__SHIFT 0x8
5041#define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT__SHIFT 0x9
5042#define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP__SHIFT 0xa
5043#define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS__SHIFT 0xb
5044#define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING__SHIFT 0xc
5045#define DB_DEBUG3__DISABLE_OP_DF_BYPASS__SHIFT 0xd
5046#define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE__SHIFT 0xe
5047#define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK__SHIFT 0xf
5048#define DB_DEBUG3__ALLOW_RF2P_RW_COLLISION__SHIFT 0x10
5049#define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE__SHIFT 0x11
5050#define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING__SHIFT 0x12
5051#define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE__SHIFT 0x13
5052#define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE__SHIFT 0x14
5053#define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT__SHIFT 0x15
5054#define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB__SHIFT 0x16
5055#define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD__SHIFT 0x17
5056#define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT__SHIFT 0x18
5057#define DB_DEBUG3__DISABLE_DI_DT_STALL__SHIFT 0x19
5058#define DB_DEBUG3__ENABLE_DB_PROCESS_RESET__SHIFT 0x1a
5059#define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX__SHIFT 0x1b
5060#define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND__SHIFT 0x1c
5061#define DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND__SHIFT 0x1d
5062#define DB_DEBUG3__DISABLE_4XAA_2P_DELAYED_WRITE__SHIFT 0x1e
5063#define DB_DEBUG3__DISABLE_4XAA_2P_INTERLEAVED_PMASK__SHIFT 0x1f
5064#define DB_DEBUG3__DISABLE_CLEAR_ZRANGE_CORRECTION_MASK 0x00000001L
5065#define DB_DEBUG3__ROUND_ZRANGE_CORRECTION_MASK 0x00000002L
5066#define DB_DEBUG3__FORCE_DB_IS_GOOD_MASK 0x00000004L
5067#define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION_MASK 0x00000008L
5068#define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP_MASK 0x00000010L
5069#define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z_MASK 0x00000020L
5070#define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z_MASK 0x00000040L
5071#define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS_MASK 0x00000080L
5072#define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION_MASK 0x00000100L
5073#define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT_MASK 0x00000200L
5074#define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP_MASK 0x00000400L
5075#define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS_MASK 0x00000800L
5076#define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING_MASK 0x00001000L
5077#define DB_DEBUG3__DISABLE_OP_DF_BYPASS_MASK 0x00002000L
5078#define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE_MASK 0x00004000L
5079#define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK_MASK 0x00008000L
5080#define DB_DEBUG3__ALLOW_RF2P_RW_COLLISION_MASK 0x00010000L
5081#define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE_MASK 0x00020000L
5082#define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING_MASK 0x00040000L
5083#define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE_MASK 0x00080000L
5084#define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE_MASK 0x00100000L
5085#define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT_MASK 0x00200000L
5086#define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB_MASK 0x00400000L
5087#define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD_MASK 0x00800000L
5088#define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT_MASK 0x01000000L
5089#define DB_DEBUG3__DISABLE_DI_DT_STALL_MASK 0x02000000L
5090#define DB_DEBUG3__ENABLE_DB_PROCESS_RESET_MASK 0x04000000L
5091#define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX_MASK 0x08000000L
5092#define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND_MASK 0x10000000L
5093#define DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND_MASK 0x20000000L
5094#define DB_DEBUG3__DISABLE_4XAA_2P_DELAYED_WRITE_MASK 0x40000000L
5095#define DB_DEBUG3__DISABLE_4XAA_2P_INTERLEAVED_PMASK_MASK 0x80000000L
5096//DB_DEBUG4
5097#define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION__SHIFT 0x0
5098#define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION__SHIFT 0x1
5099#define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL__SHIFT 0x2
5100#define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL__SHIFT 0x3
5101#define DB_DEBUG4__DISABLE_4XAA_2P_ZD_HOLDOFF__SHIFT 0x4
5102#define DB_DEBUG4__ENABLE_A2M_DQUAD_OPTIMIZATION__SHIFT 0x5
5103#define DB_DEBUG4__ENABLE_DBCB_SLOW_FORMAT_COLLAPSE__SHIFT 0x6
5104#define DB_DEBUG4__ALWAYS_ON_RMI_CLK_EN__SHIFT 0x7
5105#define DB_DEBUG4__DFSM_CONVERT_PASSTHROUGH_TO_BYPASS__SHIFT 0x8
5106#define DB_DEBUG4__DISABLE_UNMAPPED_Z_INDICATOR__SHIFT 0x9
5107#define DB_DEBUG4__DISABLE_UNMAPPED_S_INDICATOR__SHIFT 0xa
5108#define DB_DEBUG4__DISABLE_UNMAPPED_H_INDICATOR__SHIFT 0xb
5109#define DB_DEBUG4__DISABLE_SEPARATE_DFSM_CLK__SHIFT 0xc
5110#define DB_DEBUG4__DISABLE_DTT_FAST_HTILENACK_LOOKUP__SHIFT 0xd
5111#define DB_DEBUG4__DISABLE_RESCHECK_MEMCOHER_OPTIMIZATION__SHIFT 0xe
5112#define DB_DEBUG4__DISABLE_TS_WRITE_L0__SHIFT 0xf
5113#define DB_DEBUG4__DISABLE_DYNAMIC_RAM_LIGHT_SLEEP_MODE__SHIFT 0x10
5114#define DB_DEBUG4__DISABLE_HIZ_Q1_TS_COLLISION_DETECT__SHIFT 0x11
5115#define DB_DEBUG4__DISABLE_HIZ_Q2_TS_COLLISION_DETECT__SHIFT 0x12
5116#define DB_DEBUG4__DB_EXTRA_DEBUG4__SHIFT 0x13
5117#define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION_MASK 0x00000001L
5118#define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION_MASK 0x00000002L
5119#define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL_MASK 0x00000004L
5120#define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL_MASK 0x00000008L
5121#define DB_DEBUG4__DISABLE_4XAA_2P_ZD_HOLDOFF_MASK 0x00000010L
5122#define DB_DEBUG4__ENABLE_A2M_DQUAD_OPTIMIZATION_MASK 0x00000020L
5123#define DB_DEBUG4__ENABLE_DBCB_SLOW_FORMAT_COLLAPSE_MASK 0x00000040L
5124#define DB_DEBUG4__ALWAYS_ON_RMI_CLK_EN_MASK 0x00000080L
5125#define DB_DEBUG4__DFSM_CONVERT_PASSTHROUGH_TO_BYPASS_MASK 0x00000100L
5126#define DB_DEBUG4__DISABLE_UNMAPPED_Z_INDICATOR_MASK 0x00000200L
5127#define DB_DEBUG4__DISABLE_UNMAPPED_S_INDICATOR_MASK 0x00000400L
5128#define DB_DEBUG4__DISABLE_UNMAPPED_H_INDICATOR_MASK 0x00000800L
5129#define DB_DEBUG4__DISABLE_SEPARATE_DFSM_CLK_MASK 0x00001000L
5130#define DB_DEBUG4__DISABLE_DTT_FAST_HTILENACK_LOOKUP_MASK 0x00002000L
5131#define DB_DEBUG4__DISABLE_RESCHECK_MEMCOHER_OPTIMIZATION_MASK 0x00004000L
5132#define DB_DEBUG4__DISABLE_TS_WRITE_L0_MASK 0x00008000L
5133#define DB_DEBUG4__DISABLE_DYNAMIC_RAM_LIGHT_SLEEP_MODE_MASK 0x00010000L
5134#define DB_DEBUG4__DISABLE_HIZ_Q1_TS_COLLISION_DETECT_MASK 0x00020000L
5135#define DB_DEBUG4__DISABLE_HIZ_Q2_TS_COLLISION_DETECT_MASK 0x00040000L
5136#define DB_DEBUG4__DB_EXTRA_DEBUG4_MASK 0xFFF80000L
5137//DB_CREDIT_LIMIT
5138#define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS__SHIFT 0x0
5139#define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS__SHIFT 0x5
5140#define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS__SHIFT 0xa
5141#define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS__SHIFT 0x18
5142#define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS_MASK 0x0000001FL
5143#define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS_MASK 0x000003E0L
5144#define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS_MASK 0x00001C00L
5145#define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS_MASK 0x7F000000L
5146//DB_WATERMARKS
5147#define DB_WATERMARKS__DEPTH_FREE__SHIFT 0x0
5148#define DB_WATERMARKS__DEPTH_FLUSH__SHIFT 0x5
5149#define DB_WATERMARKS__FORCE_SUMMARIZE__SHIFT 0xb
5150#define DB_WATERMARKS__DEPTH_PENDING_FREE__SHIFT 0xf
5151#define DB_WATERMARKS__DEPTH_CACHELINE_FREE__SHIFT 0x14
5152#define DB_WATERMARKS__AUTO_FLUSH_HTILE__SHIFT 0x1e
5153#define DB_WATERMARKS__AUTO_FLUSH_QUAD__SHIFT 0x1f
5154#define DB_WATERMARKS__DEPTH_FREE_MASK 0x0000001FL
5155#define DB_WATERMARKS__DEPTH_FLUSH_MASK 0x000007E0L
5156#define DB_WATERMARKS__FORCE_SUMMARIZE_MASK 0x00007800L
5157#define DB_WATERMARKS__DEPTH_PENDING_FREE_MASK 0x000F8000L
5158#define DB_WATERMARKS__DEPTH_CACHELINE_FREE_MASK 0x0FF00000L
5159#define DB_WATERMARKS__AUTO_FLUSH_HTILE_MASK 0x40000000L
5160#define DB_WATERMARKS__AUTO_FLUSH_QUAD_MASK 0x80000000L
5161//DB_SUBTILE_CONTROL
5162#define DB_SUBTILE_CONTROL__MSAA1_X__SHIFT 0x0
5163#define DB_SUBTILE_CONTROL__MSAA1_Y__SHIFT 0x2
5164#define DB_SUBTILE_CONTROL__MSAA2_X__SHIFT 0x4
5165#define DB_SUBTILE_CONTROL__MSAA2_Y__SHIFT 0x6
5166#define DB_SUBTILE_CONTROL__MSAA4_X__SHIFT 0x8
5167#define DB_SUBTILE_CONTROL__MSAA4_Y__SHIFT 0xa
5168#define DB_SUBTILE_CONTROL__MSAA8_X__SHIFT 0xc
5169#define DB_SUBTILE_CONTROL__MSAA8_Y__SHIFT 0xe
5170#define DB_SUBTILE_CONTROL__MSAA16_X__SHIFT 0x10
5171#define DB_SUBTILE_CONTROL__MSAA16_Y__SHIFT 0x12
5172#define DB_SUBTILE_CONTROL__MSAA1_X_MASK 0x00000003L
5173#define DB_SUBTILE_CONTROL__MSAA1_Y_MASK 0x0000000CL
5174#define DB_SUBTILE_CONTROL__MSAA2_X_MASK 0x00000030L
5175#define DB_SUBTILE_CONTROL__MSAA2_Y_MASK 0x000000C0L
5176#define DB_SUBTILE_CONTROL__MSAA4_X_MASK 0x00000300L
5177#define DB_SUBTILE_CONTROL__MSAA4_Y_MASK 0x00000C00L
5178#define DB_SUBTILE_CONTROL__MSAA8_X_MASK 0x00003000L
5179#define DB_SUBTILE_CONTROL__MSAA8_Y_MASK 0x0000C000L
5180#define DB_SUBTILE_CONTROL__MSAA16_X_MASK 0x00030000L
5181#define DB_SUBTILE_CONTROL__MSAA16_Y_MASK 0x000C0000L
5182//DB_FREE_CACHELINES
5183#define DB_FREE_CACHELINES__FREE_DTILE_DEPTH__SHIFT 0x0
5184#define DB_FREE_CACHELINES__FREE_PLANE_DEPTH__SHIFT 0x7
5185#define DB_FREE_CACHELINES__FREE_Z_DEPTH__SHIFT 0xe
5186#define DB_FREE_CACHELINES__FREE_HTILE_DEPTH__SHIFT 0x14
5187#define DB_FREE_CACHELINES__QUAD_READ_REQS__SHIFT 0x18
5188#define DB_FREE_CACHELINES__FREE_DTILE_DEPTH_MASK 0x0000007FL
5189#define DB_FREE_CACHELINES__FREE_PLANE_DEPTH_MASK 0x00003F80L
5190#define DB_FREE_CACHELINES__FREE_Z_DEPTH_MASK 0x000FC000L
5191#define DB_FREE_CACHELINES__FREE_HTILE_DEPTH_MASK 0x00F00000L
5192#define DB_FREE_CACHELINES__QUAD_READ_REQS_MASK 0xFF000000L
5193//DB_FIFO_DEPTH1
5194#define DB_FIFO_DEPTH1__DB_RMI_RDREQ_CREDITS__SHIFT 0x0
5195#define DB_FIFO_DEPTH1__DB_RMI_WRREQ_CREDITS__SHIFT 0x5
5196#define DB_FIFO_DEPTH1__MCC_DEPTH__SHIFT 0xa
5197#define DB_FIFO_DEPTH1__QC_DEPTH__SHIFT 0x10
5198#define DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH__SHIFT 0x15
5199#define DB_FIFO_DEPTH1__DB_RMI_RDREQ_CREDITS_MASK 0x0000001FL
5200#define DB_FIFO_DEPTH1__DB_RMI_WRREQ_CREDITS_MASK 0x000003E0L
5201#define DB_FIFO_DEPTH1__MCC_DEPTH_MASK 0x0000FC00L
5202#define DB_FIFO_DEPTH1__QC_DEPTH_MASK 0x001F0000L
5203#define DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH_MASK 0x1FE00000L
5204//DB_FIFO_DEPTH2
5205#define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH__SHIFT 0x0
5206#define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH__SHIFT 0x8
5207#define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH__SHIFT 0xf
5208#define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH__SHIFT 0x19
5209#define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH_MASK 0x000000FFL
5210#define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH_MASK 0x00007F00L
5211#define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH_MASK 0x01FF8000L
5212#define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH_MASK 0xFE000000L
5213//DB_EXCEPTION_CONTROL
5214#define DB_EXCEPTION_CONTROL__EARLY_Z_PANIC_DISABLE__SHIFT 0x0
5215#define DB_EXCEPTION_CONTROL__LATE_Z_PANIC_DISABLE__SHIFT 0x1
5216#define DB_EXCEPTION_CONTROL__RE_Z_PANIC_DISABLE__SHIFT 0x2
5217#define DB_EXCEPTION_CONTROL__EARLY_Z_PANIC_DISABLE_MASK 0x00000001L
5218#define DB_EXCEPTION_CONTROL__LATE_Z_PANIC_DISABLE_MASK 0x00000002L
5219#define DB_EXCEPTION_CONTROL__RE_Z_PANIC_DISABLE_MASK 0x00000004L
5220//DB_RING_CONTROL
5221#define DB_RING_CONTROL__COUNTER_CONTROL__SHIFT 0x0
5222#define DB_RING_CONTROL__COUNTER_CONTROL_MASK 0x00000003L
5223//DB_MEM_ARB_WATERMARKS
5224#define DB_MEM_ARB_WATERMARKS__CLIENT0_WATERMARK__SHIFT 0x0
5225#define DB_MEM_ARB_WATERMARKS__CLIENT1_WATERMARK__SHIFT 0x8
5226#define DB_MEM_ARB_WATERMARKS__CLIENT2_WATERMARK__SHIFT 0x10
5227#define DB_MEM_ARB_WATERMARKS__CLIENT3_WATERMARK__SHIFT 0x18
5228#define DB_MEM_ARB_WATERMARKS__CLIENT0_WATERMARK_MASK 0x00000007L
5229#define DB_MEM_ARB_WATERMARKS__CLIENT1_WATERMARK_MASK 0x00000700L
5230#define DB_MEM_ARB_WATERMARKS__CLIENT2_WATERMARK_MASK 0x00070000L
5231#define DB_MEM_ARB_WATERMARKS__CLIENT3_WATERMARK_MASK 0x07000000L
5232//DB_RMI_CACHE_POLICY
5233#define DB_RMI_CACHE_POLICY__Z_RD__SHIFT 0x0
5234#define DB_RMI_CACHE_POLICY__S_RD__SHIFT 0x1
5235#define DB_RMI_CACHE_POLICY__HTILE_RD__SHIFT 0x2
5236#define DB_RMI_CACHE_POLICY__Z_WR__SHIFT 0x8
5237#define DB_RMI_CACHE_POLICY__S_WR__SHIFT 0x9
5238#define DB_RMI_CACHE_POLICY__HTILE_WR__SHIFT 0xa
5239#define DB_RMI_CACHE_POLICY__ZPCPSD_WR__SHIFT 0xb
5240#define DB_RMI_CACHE_POLICY__CC_RD__SHIFT 0x10
5241#define DB_RMI_CACHE_POLICY__FMASK_RD__SHIFT 0x11
5242#define DB_RMI_CACHE_POLICY__CMASK_RD__SHIFT 0x12
5243#define DB_RMI_CACHE_POLICY__DCC_RD__SHIFT 0x13
5244#define DB_RMI_CACHE_POLICY__CC_WR__SHIFT 0x18
5245#define DB_RMI_CACHE_POLICY__FMASK_WR__SHIFT 0x19
5246#define DB_RMI_CACHE_POLICY__CMASK_WR__SHIFT 0x1a
5247#define DB_RMI_CACHE_POLICY__DCC_WR__SHIFT 0x1b
5248#define DB_RMI_CACHE_POLICY__Z_RD_MASK 0x00000001L
5249#define DB_RMI_CACHE_POLICY__S_RD_MASK 0x00000002L
5250#define DB_RMI_CACHE_POLICY__HTILE_RD_MASK 0x00000004L
5251#define DB_RMI_CACHE_POLICY__Z_WR_MASK 0x00000100L
5252#define DB_RMI_CACHE_POLICY__S_WR_MASK 0x00000200L
5253#define DB_RMI_CACHE_POLICY__HTILE_WR_MASK 0x00000400L
5254#define DB_RMI_CACHE_POLICY__ZPCPSD_WR_MASK 0x00000800L
5255#define DB_RMI_CACHE_POLICY__CC_RD_MASK 0x00010000L
5256#define DB_RMI_CACHE_POLICY__FMASK_RD_MASK 0x00020000L
5257#define DB_RMI_CACHE_POLICY__CMASK_RD_MASK 0x00040000L
5258#define DB_RMI_CACHE_POLICY__DCC_RD_MASK 0x00080000L
5259#define DB_RMI_CACHE_POLICY__CC_WR_MASK 0x01000000L
5260#define DB_RMI_CACHE_POLICY__FMASK_WR_MASK 0x02000000L
5261#define DB_RMI_CACHE_POLICY__CMASK_WR_MASK 0x04000000L
5262#define DB_RMI_CACHE_POLICY__DCC_WR_MASK 0x08000000L
5263//DB_DFSM_CONFIG
5264#define DB_DFSM_CONFIG__BYPASS_DFSM__SHIFT 0x0
5265#define DB_DFSM_CONFIG__DISABLE_PUNCHOUT__SHIFT 0x1
5266#define DB_DFSM_CONFIG__DISABLE_POPS__SHIFT 0x2
5267#define DB_DFSM_CONFIG__FORCE_FLUSH__SHIFT 0x3
5268#define DB_DFSM_CONFIG__MIDDLE_PIPE_MAX_DEPTH__SHIFT 0x8
5269#define DB_DFSM_CONFIG__BYPASS_DFSM_MASK 0x00000001L
5270#define DB_DFSM_CONFIG__DISABLE_PUNCHOUT_MASK 0x00000002L
5271#define DB_DFSM_CONFIG__DISABLE_POPS_MASK 0x00000004L
5272#define DB_DFSM_CONFIG__FORCE_FLUSH_MASK 0x00000008L
5273#define DB_DFSM_CONFIG__MIDDLE_PIPE_MAX_DEPTH_MASK 0x00007F00L
5274//DB_DFSM_WATERMARK
5275#define DB_DFSM_WATERMARK__DFSM_HIGH_WATERMARK__SHIFT 0x0
5276#define DB_DFSM_WATERMARK__POPS_HIGH_WATERMARK__SHIFT 0x10
5277#define DB_DFSM_WATERMARK__DFSM_HIGH_WATERMARK_MASK 0x0000FFFFL
5278#define DB_DFSM_WATERMARK__POPS_HIGH_WATERMARK_MASK 0xFFFF0000L
5279//DB_DFSM_TILES_IN_FLIGHT
5280#define DB_DFSM_TILES_IN_FLIGHT__HIGH_WATERMARK__SHIFT 0x0
5281#define DB_DFSM_TILES_IN_FLIGHT__HARD_LIMIT__SHIFT 0x10
5282#define DB_DFSM_TILES_IN_FLIGHT__HIGH_WATERMARK_MASK 0x0000FFFFL
5283#define DB_DFSM_TILES_IN_FLIGHT__HARD_LIMIT_MASK 0xFFFF0000L
5284//DB_DFSM_PRIMS_IN_FLIGHT
5285#define DB_DFSM_PRIMS_IN_FLIGHT__HIGH_WATERMARK__SHIFT 0x0
5286#define DB_DFSM_PRIMS_IN_FLIGHT__HARD_LIMIT__SHIFT 0x10
5287#define DB_DFSM_PRIMS_IN_FLIGHT__HIGH_WATERMARK_MASK 0x0000FFFFL
5288#define DB_DFSM_PRIMS_IN_FLIGHT__HARD_LIMIT_MASK 0xFFFF0000L
5289//DB_DFSM_WATCHDOG
5290#define DB_DFSM_WATCHDOG__TIMER_TARGET__SHIFT 0x0
5291#define DB_DFSM_WATCHDOG__TIMER_TARGET_MASK 0xFFFFFFFFL
5292//DB_DFSM_FLUSH_ENABLE
5293#define DB_DFSM_FLUSH_ENABLE__PRIMARY_EVENTS__SHIFT 0x0
5294#define DB_DFSM_FLUSH_ENABLE__AUX_FORCE_PASSTHRU__SHIFT 0x18
5295#define DB_DFSM_FLUSH_ENABLE__AUX_EVENTS__SHIFT 0x1c
5296#define DB_DFSM_FLUSH_ENABLE__PRIMARY_EVENTS_MASK 0x000003FFL
5297#define DB_DFSM_FLUSH_ENABLE__AUX_FORCE_PASSTHRU_MASK 0x0F000000L
5298#define DB_DFSM_FLUSH_ENABLE__AUX_EVENTS_MASK 0xF0000000L
5299//DB_DFSM_FLUSH_AUX_EVENT
5300#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_A__SHIFT 0x0
5301#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_B__SHIFT 0x8
5302#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_C__SHIFT 0x10
5303#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_D__SHIFT 0x18
5304#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_A_MASK 0x000000FFL
5305#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_B_MASK 0x0000FF00L
5306#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_C_MASK 0x00FF0000L
5307#define DB_DFSM_FLUSH_AUX_EVENT__EVENT_D_MASK 0xFF000000L
5308//CC_RB_REDUNDANCY
5309#define CC_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8
5310#define CC_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc
5311#define CC_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10
5312#define CC_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14
5313#define CC_RB_REDUNDANCY__FAILED_RB0_MASK 0x00000F00L
5314#define CC_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x00001000L
5315#define CC_RB_REDUNDANCY__FAILED_RB1_MASK 0x000F0000L
5316#define CC_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x00100000L
5317//CC_RB_BACKEND_DISABLE
5318#define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10
5319#define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0x00FF0000L
5320//GB_ADDR_CONFIG
5321#define GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
5322#define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3
5323#define GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0x6
5324#define GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
5325#define GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc
5326#define GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
5327#define GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13
5328#define GB_ADDR_CONFIG__NUM_GPUS__SHIFT 0x15
5329#define GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
5330#define GB_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT 0x1a
5331#define GB_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
5332#define GB_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
5333#define GB_ADDR_CONFIG__SE_ENABLE__SHIFT 0x1f
5334#define GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L
5335#define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L
5336#define GB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L
5337#define GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L
5338#define GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L
5339#define GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L
5340#define GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L
5341#define GB_ADDR_CONFIG__NUM_GPUS_MASK 0x00E00000L
5342#define GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x03000000L
5343#define GB_ADDR_CONFIG__NUM_RB_PER_SE_MASK 0x0C000000L
5344#define GB_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L
5345#define GB_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000L
5346#define GB_ADDR_CONFIG__SE_ENABLE_MASK 0x80000000L
5347//GB_BACKEND_MAP
5348#define GB_BACKEND_MAP__BACKEND_MAP__SHIFT 0x0
5349#define GB_BACKEND_MAP__BACKEND_MAP_MASK 0xFFFFFFFFL
5350//GB_GPU_ID
5351#define GB_GPU_ID__GPU_ID__SHIFT 0x0
5352#define GB_GPU_ID__GPU_ID_MASK 0x0000000FL
5353//CC_RB_DAISY_CHAIN
5354#define CC_RB_DAISY_CHAIN__RB_0__SHIFT 0x0
5355#define CC_RB_DAISY_CHAIN__RB_1__SHIFT 0x4
5356#define CC_RB_DAISY_CHAIN__RB_2__SHIFT 0x8
5357#define CC_RB_DAISY_CHAIN__RB_3__SHIFT 0xc
5358#define CC_RB_DAISY_CHAIN__RB_4__SHIFT 0x10
5359#define CC_RB_DAISY_CHAIN__RB_5__SHIFT 0x14
5360#define CC_RB_DAISY_CHAIN__RB_6__SHIFT 0x18
5361#define CC_RB_DAISY_CHAIN__RB_7__SHIFT 0x1c
5362#define CC_RB_DAISY_CHAIN__RB_0_MASK 0x0000000FL
5363#define CC_RB_DAISY_CHAIN__RB_1_MASK 0x000000F0L
5364#define CC_RB_DAISY_CHAIN__RB_2_MASK 0x00000F00L
5365#define CC_RB_DAISY_CHAIN__RB_3_MASK 0x0000F000L
5366#define CC_RB_DAISY_CHAIN__RB_4_MASK 0x000F0000L
5367#define CC_RB_DAISY_CHAIN__RB_5_MASK 0x00F00000L
5368#define CC_RB_DAISY_CHAIN__RB_6_MASK 0x0F000000L
5369#define CC_RB_DAISY_CHAIN__RB_7_MASK 0xF0000000L
5370//GB_ADDR_CONFIG_READ
5371#define GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0
5372#define GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3
5373#define GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS__SHIFT 0x6
5374#define GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8
5375#define GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc
5376#define GB_ADDR_CONFIG_READ__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
5377#define GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13
5378#define GB_ADDR_CONFIG_READ__NUM_GPUS__SHIFT 0x15
5379#define GB_ADDR_CONFIG_READ__MULTI_GPU_TILE_SIZE__SHIFT 0x18
5380#define GB_ADDR_CONFIG_READ__NUM_RB_PER_SE__SHIFT 0x1a
5381#define GB_ADDR_CONFIG_READ__ROW_SIZE__SHIFT 0x1c
5382#define GB_ADDR_CONFIG_READ__NUM_LOWER_PIPES__SHIFT 0x1e
5383#define GB_ADDR_CONFIG_READ__SE_ENABLE__SHIFT 0x1f
5384#define GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L
5385#define GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L
5386#define GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L
5387#define GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L
5388#define GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L
5389#define GB_ADDR_CONFIG_READ__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L
5390#define GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L
5391#define GB_ADDR_CONFIG_READ__NUM_GPUS_MASK 0x00E00000L
5392#define GB_ADDR_CONFIG_READ__MULTI_GPU_TILE_SIZE_MASK 0x03000000L
5393#define GB_ADDR_CONFIG_READ__NUM_RB_PER_SE_MASK 0x0C000000L
5394#define GB_ADDR_CONFIG_READ__ROW_SIZE_MASK 0x30000000L
5395#define GB_ADDR_CONFIG_READ__NUM_LOWER_PIPES_MASK 0x40000000L
5396#define GB_ADDR_CONFIG_READ__SE_ENABLE_MASK 0x80000000L
5397//GB_TILE_MODE0
5398#define GB_TILE_MODE0__ARRAY_MODE__SHIFT 0x2
5399#define GB_TILE_MODE0__PIPE_CONFIG__SHIFT 0x6
5400#define GB_TILE_MODE0__TILE_SPLIT__SHIFT 0xb
5401#define GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT 0x16
5402#define GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT 0x19
5403#define GB_TILE_MODE0__ARRAY_MODE_MASK 0x0000003CL
5404#define GB_TILE_MODE0__PIPE_CONFIG_MASK 0x000007C0L
5405#define GB_TILE_MODE0__TILE_SPLIT_MASK 0x00003800L
5406#define GB_TILE_MODE0__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
5407#define GB_TILE_MODE0__SAMPLE_SPLIT_MASK 0x06000000L
5408//GB_TILE_MODE1
5409#define GB_TILE_MODE1__ARRAY_MODE__SHIFT 0x2
5410#define GB_TILE_MODE1__PIPE_CONFIG__SHIFT 0x6
5411#define GB_TILE_MODE1__TILE_SPLIT__SHIFT 0xb
5412#define GB_TILE_MODE1__MICRO_TILE_MODE_NEW__SHIFT 0x16
5413#define GB_TILE_MODE1__SAMPLE_SPLIT__SHIFT 0x19
5414#define GB_TILE_MODE1__ARRAY_MODE_MASK 0x0000003CL
5415#define GB_TILE_MODE1__PIPE_CONFIG_MASK 0x000007C0L
5416#define GB_TILE_MODE1__TILE_SPLIT_MASK 0x00003800L
5417#define GB_TILE_MODE1__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
5418#define GB_TILE_MODE1__SAMPLE_SPLIT_MASK 0x06000000L
5419//GB_TILE_MODE2
5420#define GB_TILE_MODE2__ARRAY_MODE__SHIFT 0x2
5421#define GB_TILE_MODE2__PIPE_CONFIG__SHIFT 0x6
5422#define GB_TILE_MODE2__TILE_SPLIT__SHIFT 0xb
5423#define GB_TILE_MODE2__MICRO_TILE_MODE_NEW__SHIFT 0x16
5424#define GB_TILE_MODE2__SAMPLE_SPLIT__SHIFT 0x19
5425#define GB_TILE_MODE2__ARRAY_MODE_MASK 0x0000003CL
5426#define GB_TILE_MODE2__PIPE_CONFIG_MASK 0x000007C0L
5427#define GB_TILE_MODE2__TILE_SPLIT_MASK 0x00003800L
5428#define GB_TILE_MODE2__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
5429#define GB_TILE_MODE2__SAMPLE_SPLIT_MASK 0x06000000L
5430//GB_TILE_MODE3
5431#define GB_TILE_MODE3__ARRAY_MODE__SHIFT 0x2
5432#define GB_TILE_MODE3__PIPE_CONFIG__SHIFT 0x6
5433#define GB_TILE_MODE3__TILE_SPLIT__SHIFT 0xb
5434#define GB_TILE_MODE3__MICRO_TILE_MODE_NEW__SHIFT 0x16
5435#define GB_TILE_MODE3__SAMPLE_SPLIT__SHIFT 0x19
5436#define GB_TILE_MODE3__ARRAY_MODE_MASK 0x0000003CL
5437#define GB_TILE_MODE3__PIPE_CONFIG_MASK 0x000007C0L
5438#define GB_TILE_MODE3__TILE_SPLIT_MASK 0x00003800L
5439#define GB_TILE_MODE3__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
5440#define GB_TILE_MODE3__SAMPLE_SPLIT_MASK 0x06000000L
5441//GB_TILE_MODE4
5442#define GB_TILE_MODE4__ARRAY_MODE__SHIFT 0x2
5443#define GB_TILE_MODE4__PIPE_CONFIG__SHIFT 0x6
5444#define GB_TILE_MODE4__TILE_SPLIT__SHIFT 0xb
5445#define GB_TILE_MODE4__MICRO_TILE_MODE_NEW__SHIFT 0x16
5446#define GB_TILE_MODE4__SAMPLE_SPLIT__SHIFT 0x19
5447#define GB_TILE_MODE4__ARRAY_MODE_MASK 0x0000003CL
5448#define GB_TILE_MODE4__PIPE_CONFIG_MASK 0x000007C0L
5449#define GB_TILE_MODE4__TILE_SPLIT_MASK 0x00003800L
5450#define GB_TILE_MODE4__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
5451#define GB_TILE_MODE4__SAMPLE_SPLIT_MASK 0x06000000L
5452//GB_TILE_MODE5
5453#define GB_TILE_MODE5__ARRAY_MODE__SHIFT 0x2
5454#define GB_TILE_MODE5__PIPE_CONFIG__SHIFT 0x6
5455#define GB_TILE_MODE5__TILE_SPLIT__SHIFT 0xb
5456#define GB_TILE_MODE5__MICRO_TILE_MODE_NEW__SHIFT 0x16
5457#define GB_TILE_MODE5__SAMPLE_SPLIT__SHIFT 0x19
5458#define GB_TILE_MODE5__ARRAY_MODE_MASK 0x0000003CL
5459#define GB_TILE_MODE5__PIPE_CONFIG_MASK 0x000007C0L
5460#define GB_TILE_MODE5__TILE_SPLIT_MASK 0x00003800L
5461#define GB_TILE_MODE5__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
5462#define GB_TILE_MODE5__SAMPLE_SPLIT_MASK 0x06000000L
5463//GB_TILE_MODE6
5464#define GB_TILE_MODE6__ARRAY_MODE__SHIFT 0x2
5465#define GB_TILE_MODE6__PIPE_CONFIG__SHIFT 0x6
5466#define GB_TILE_MODE6__TILE_SPLIT__SHIFT 0xb
5467#define GB_TILE_MODE6__MICRO_TILE_MODE_NEW__SHIFT 0x16
5468#define GB_TILE_MODE6__SAMPLE_SPLIT__SHIFT 0x19
5469#define GB_TILE_MODE6__ARRAY_MODE_MASK 0x0000003CL
5470#define GB_TILE_MODE6__PIPE_CONFIG_MASK 0x000007C0L
5471#define GB_TILE_MODE6__TILE_SPLIT_MASK 0x00003800L
5472#define GB_TILE_MODE6__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
5473#define GB_TILE_MODE6__SAMPLE_SPLIT_MASK 0x06000000L
5474//GB_TILE_MODE7
5475#define GB_TILE_MODE7__ARRAY_MODE__SHIFT 0x2
5476#define GB_TILE_MODE7__PIPE_CONFIG__SHIFT 0x6
5477#define GB_TILE_MODE7__TILE_SPLIT__SHIFT 0xb
5478#define GB_TILE_MODE7__MICRO_TILE_MODE_NEW__SHIFT 0x16
5479#define GB_TILE_MODE7__SAMPLE_SPLIT__SHIFT 0x19
5480#define GB_TILE_MODE7__ARRAY_MODE_MASK 0x0000003CL
5481#define GB_TILE_MODE7__PIPE_CONFIG_MASK 0x000007C0L
5482#define GB_TILE_MODE7__TILE_SPLIT_MASK 0x00003800L
5483#define GB_TILE_MODE7__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
5484#define GB_TILE_MODE7__SAMPLE_SPLIT_MASK 0x06000000L
5485//GB_TILE_MODE8
5486#define GB_TILE_MODE8__ARRAY_MODE__SHIFT 0x2
5487#define GB_TILE_MODE8__PIPE_CONFIG__SHIFT 0x6
5488#define GB_TILE_MODE8__TILE_SPLIT__SHIFT 0xb
5489#define GB_TILE_MODE8__MICRO_TILE_MODE_NEW__SHIFT 0x16
5490#define GB_TILE_MODE8__SAMPLE_SPLIT__SHIFT 0x19
5491#define GB_TILE_MODE8__ARRAY_MODE_MASK 0x0000003CL
5492#define GB_TILE_MODE8__PIPE_CONFIG_MASK 0x000007C0L
5493#define GB_TILE_MODE8__TILE_SPLIT_MASK 0x00003800L
5494#define GB_TILE_MODE8__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
5495#define GB_TILE_MODE8__SAMPLE_SPLIT_MASK 0x06000000L
5496//GB_TILE_MODE9
5497#define GB_TILE_MODE9__ARRAY_MODE__SHIFT 0x2
5498#define GB_TILE_MODE9__PIPE_CONFIG__SHIFT 0x6
5499#define GB_TILE_MODE9__TILE_SPLIT__SHIFT 0xb
5500#define GB_TILE_MODE9__MICRO_TILE_MODE_NEW__SHIFT 0x16
5501#define GB_TILE_MODE9__SAMPLE_SPLIT__SHIFT 0x19
5502#define GB_TILE_MODE9__ARRAY_MODE_MASK 0x0000003CL
5503#define GB_TILE_MODE9__PIPE_CONFIG_MASK 0x000007C0L
5504#define GB_TILE_MODE9__TILE_SPLIT_MASK 0x00003800L
5505#define GB_TILE_MODE9__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
5506#define GB_TILE_MODE9__SAMPLE_SPLIT_MASK 0x06000000L
5507//GB_TILE_MODE10
5508#define GB_TILE_MODE10__ARRAY_MODE__SHIFT 0x2
5509#define GB_TILE_MODE10__PIPE_CONFIG__SHIFT 0x6
5510#define GB_TILE_MODE10__TILE_SPLIT__SHIFT 0xb
5511#define GB_TILE_MODE10__MICRO_TILE_MODE_NEW__SHIFT 0x16
5512#define GB_TILE_MODE10__SAMPLE_SPLIT__SHIFT 0x19
5513#define GB_TILE_MODE10__ARRAY_MODE_MASK 0x0000003CL
5514#define GB_TILE_MODE10__PIPE_CONFIG_MASK 0x000007C0L
5515#define GB_TILE_MODE10__TILE_SPLIT_MASK 0x00003800L
5516#define GB_TILE_MODE10__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
5517#define GB_TILE_MODE10__SAMPLE_SPLIT_MASK 0x06000000L
5518//GB_TILE_MODE11
5519#define GB_TILE_MODE11__ARRAY_MODE__SHIFT 0x2
5520#define GB_TILE_MODE11__PIPE_CONFIG__SHIFT 0x6
5521#define GB_TILE_MODE11__TILE_SPLIT__SHIFT 0xb
5522#define GB_TILE_MODE11__MICRO_TILE_MODE_NEW__SHIFT 0x16
5523#define GB_TILE_MODE11__SAMPLE_SPLIT__SHIFT 0x19
5524#define GB_TILE_MODE11__ARRAY_MODE_MASK 0x0000003CL
5525#define GB_TILE_MODE11__PIPE_CONFIG_MASK 0x000007C0L
5526#define GB_TILE_MODE11__TILE_SPLIT_MASK 0x00003800L
5527#define GB_TILE_MODE11__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
5528#define GB_TILE_MODE11__SAMPLE_SPLIT_MASK 0x06000000L
5529//GB_TILE_MODE12
5530#define GB_TILE_MODE12__ARRAY_MODE__SHIFT 0x2
5531#define GB_TILE_MODE12__PIPE_CONFIG__SHIFT 0x6
5532#define GB_TILE_MODE12__TILE_SPLIT__SHIFT 0xb
5533#define GB_TILE_MODE12__MICRO_TILE_MODE_NEW__SHIFT 0x16
5534#define GB_TILE_MODE12__SAMPLE_SPLIT__SHIFT 0x19
5535#define GB_TILE_MODE12__ARRAY_MODE_MASK 0x0000003CL
5536#define GB_TILE_MODE12__PIPE_CONFIG_MASK 0x000007C0L
5537#define GB_TILE_MODE12__TILE_SPLIT_MASK 0x00003800L
5538#define GB_TILE_MODE12__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
5539#define GB_TILE_MODE12__SAMPLE_SPLIT_MASK 0x06000000L
5540//GB_TILE_MODE13
5541#define GB_TILE_MODE13__ARRAY_MODE__SHIFT 0x2
5542#define GB_TILE_MODE13__PIPE_CONFIG__SHIFT 0x6
5543#define GB_TILE_MODE13__TILE_SPLIT__SHIFT 0xb
5544#define GB_TILE_MODE13__MICRO_TILE_MODE_NEW__SHIFT 0x16
5545#define GB_TILE_MODE13__SAMPLE_SPLIT__SHIFT 0x19
5546#define GB_TILE_MODE13__ARRAY_MODE_MASK 0x0000003CL
5547#define GB_TILE_MODE13__PIPE_CONFIG_MASK 0x000007C0L
5548#define GB_TILE_MODE13__TILE_SPLIT_MASK 0x00003800L
5549#define GB_TILE_MODE13__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
5550#define GB_TILE_MODE13__SAMPLE_SPLIT_MASK 0x06000000L
5551//GB_TILE_MODE14
5552#define GB_TILE_MODE14__ARRAY_MODE__SHIFT 0x2
5553#define GB_TILE_MODE14__PIPE_CONFIG__SHIFT 0x6
5554#define GB_TILE_MODE14__TILE_SPLIT__SHIFT 0xb
5555#define GB_TILE_MODE14__MICRO_TILE_MODE_NEW__SHIFT 0x16
5556#define GB_TILE_MODE14__SAMPLE_SPLIT__SHIFT 0x19
5557#define GB_TILE_MODE14__ARRAY_MODE_MASK 0x0000003CL
5558#define GB_TILE_MODE14__PIPE_CONFIG_MASK 0x000007C0L
5559#define GB_TILE_MODE14__TILE_SPLIT_MASK 0x00003800L
5560#define GB_TILE_MODE14__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
5561#define GB_TILE_MODE14__SAMPLE_SPLIT_MASK 0x06000000L
5562//GB_TILE_MODE15
5563#define GB_TILE_MODE15__ARRAY_MODE__SHIFT 0x2
5564#define GB_TILE_MODE15__PIPE_CONFIG__SHIFT 0x6
5565#define GB_TILE_MODE15__TILE_SPLIT__SHIFT 0xb
5566#define GB_TILE_MODE15__MICRO_TILE_MODE_NEW__SHIFT 0x16
5567#define GB_TILE_MODE15__SAMPLE_SPLIT__SHIFT 0x19
5568#define GB_TILE_MODE15__ARRAY_MODE_MASK 0x0000003CL
5569#define GB_TILE_MODE15__PIPE_CONFIG_MASK 0x000007C0L
5570#define GB_TILE_MODE15__TILE_SPLIT_MASK 0x00003800L
5571#define GB_TILE_MODE15__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
5572#define GB_TILE_MODE15__SAMPLE_SPLIT_MASK 0x06000000L
5573//GB_TILE_MODE16
5574#define GB_TILE_MODE16__ARRAY_MODE__SHIFT 0x2
5575#define GB_TILE_MODE16__PIPE_CONFIG__SHIFT 0x6
5576#define GB_TILE_MODE16__TILE_SPLIT__SHIFT 0xb
5577#define GB_TILE_MODE16__MICRO_TILE_MODE_NEW__SHIFT 0x16
5578#define GB_TILE_MODE16__SAMPLE_SPLIT__SHIFT 0x19
5579#define GB_TILE_MODE16__ARRAY_MODE_MASK 0x0000003CL
5580#define GB_TILE_MODE16__PIPE_CONFIG_MASK 0x000007C0L
5581#define GB_TILE_MODE16__TILE_SPLIT_MASK 0x00003800L
5582#define GB_TILE_MODE16__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
5583#define GB_TILE_MODE16__SAMPLE_SPLIT_MASK 0x06000000L
5584//GB_TILE_MODE17
5585#define GB_TILE_MODE17__ARRAY_MODE__SHIFT 0x2
5586#define GB_TILE_MODE17__PIPE_CONFIG__SHIFT 0x6
5587#define GB_TILE_MODE17__TILE_SPLIT__SHIFT 0xb
5588#define GB_TILE_MODE17__MICRO_TILE_MODE_NEW__SHIFT 0x16
5589#define GB_TILE_MODE17__SAMPLE_SPLIT__SHIFT 0x19
5590#define GB_TILE_MODE17__ARRAY_MODE_MASK 0x0000003CL
5591#define GB_TILE_MODE17__PIPE_CONFIG_MASK 0x000007C0L
5592#define GB_TILE_MODE17__TILE_SPLIT_MASK 0x00003800L
5593#define GB_TILE_MODE17__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
5594#define GB_TILE_MODE17__SAMPLE_SPLIT_MASK 0x06000000L
5595//GB_TILE_MODE18
5596#define GB_TILE_MODE18__ARRAY_MODE__SHIFT 0x2
5597#define GB_TILE_MODE18__PIPE_CONFIG__SHIFT 0x6
5598#define GB_TILE_MODE18__TILE_SPLIT__SHIFT 0xb
5599#define GB_TILE_MODE18__MICRO_TILE_MODE_NEW__SHIFT 0x16
5600#define GB_TILE_MODE18__SAMPLE_SPLIT__SHIFT 0x19
5601#define GB_TILE_MODE18__ARRAY_MODE_MASK 0x0000003CL
5602#define GB_TILE_MODE18__PIPE_CONFIG_MASK 0x000007C0L
5603#define GB_TILE_MODE18__TILE_SPLIT_MASK 0x00003800L
5604#define GB_TILE_MODE18__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
5605#define GB_TILE_MODE18__SAMPLE_SPLIT_MASK 0x06000000L
5606//GB_TILE_MODE19
5607#define GB_TILE_MODE19__ARRAY_MODE__SHIFT 0x2
5608#define GB_TILE_MODE19__PIPE_CONFIG__SHIFT 0x6
5609#define GB_TILE_MODE19__TILE_SPLIT__SHIFT 0xb
5610#define GB_TILE_MODE19__MICRO_TILE_MODE_NEW__SHIFT 0x16
5611#define GB_TILE_MODE19__SAMPLE_SPLIT__SHIFT 0x19
5612#define GB_TILE_MODE19__ARRAY_MODE_MASK 0x0000003CL
5613#define GB_TILE_MODE19__PIPE_CONFIG_MASK 0x000007C0L
5614#define GB_TILE_MODE19__TILE_SPLIT_MASK 0x00003800L
5615#define GB_TILE_MODE19__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
5616#define GB_TILE_MODE19__SAMPLE_SPLIT_MASK 0x06000000L
5617//GB_TILE_MODE20
5618#define GB_TILE_MODE20__ARRAY_MODE__SHIFT 0x2
5619#define GB_TILE_MODE20__PIPE_CONFIG__SHIFT 0x6
5620#define GB_TILE_MODE20__TILE_SPLIT__SHIFT 0xb
5621#define GB_TILE_MODE20__MICRO_TILE_MODE_NEW__SHIFT 0x16
5622#define GB_TILE_MODE20__SAMPLE_SPLIT__SHIFT 0x19
5623#define GB_TILE_MODE20__ARRAY_MODE_MASK 0x0000003CL
5624#define GB_TILE_MODE20__PIPE_CONFIG_MASK 0x000007C0L
5625#define GB_TILE_MODE20__TILE_SPLIT_MASK 0x00003800L
5626#define GB_TILE_MODE20__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
5627#define GB_TILE_MODE20__SAMPLE_SPLIT_MASK 0x06000000L
5628//GB_TILE_MODE21
5629#define GB_TILE_MODE21__ARRAY_MODE__SHIFT 0x2
5630#define GB_TILE_MODE21__PIPE_CONFIG__SHIFT 0x6
5631#define GB_TILE_MODE21__TILE_SPLIT__SHIFT 0xb
5632#define GB_TILE_MODE21__MICRO_TILE_MODE_NEW__SHIFT 0x16
5633#define GB_TILE_MODE21__SAMPLE_SPLIT__SHIFT 0x19
5634#define GB_TILE_MODE21__ARRAY_MODE_MASK 0x0000003CL
5635#define GB_TILE_MODE21__PIPE_CONFIG_MASK 0x000007C0L
5636#define GB_TILE_MODE21__TILE_SPLIT_MASK 0x00003800L
5637#define GB_TILE_MODE21__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
5638#define GB_TILE_MODE21__SAMPLE_SPLIT_MASK 0x06000000L
5639//GB_TILE_MODE22
5640#define GB_TILE_MODE22__ARRAY_MODE__SHIFT 0x2
5641#define GB_TILE_MODE22__PIPE_CONFIG__SHIFT 0x6
5642#define GB_TILE_MODE22__TILE_SPLIT__SHIFT 0xb
5643#define GB_TILE_MODE22__MICRO_TILE_MODE_NEW__SHIFT 0x16
5644#define GB_TILE_MODE22__SAMPLE_SPLIT__SHIFT 0x19
5645#define GB_TILE_MODE22__ARRAY_MODE_MASK 0x0000003CL
5646#define GB_TILE_MODE22__PIPE_CONFIG_MASK 0x000007C0L
5647#define GB_TILE_MODE22__TILE_SPLIT_MASK 0x00003800L
5648#define GB_TILE_MODE22__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
5649#define GB_TILE_MODE22__SAMPLE_SPLIT_MASK 0x06000000L
5650//GB_TILE_MODE23
5651#define GB_TILE_MODE23__ARRAY_MODE__SHIFT 0x2
5652#define GB_TILE_MODE23__PIPE_CONFIG__SHIFT 0x6
5653#define GB_TILE_MODE23__TILE_SPLIT__SHIFT 0xb
5654#define GB_TILE_MODE23__MICRO_TILE_MODE_NEW__SHIFT 0x16
5655#define GB_TILE_MODE23__SAMPLE_SPLIT__SHIFT 0x19
5656#define GB_TILE_MODE23__ARRAY_MODE_MASK 0x0000003CL
5657#define GB_TILE_MODE23__PIPE_CONFIG_MASK 0x000007C0L
5658#define GB_TILE_MODE23__TILE_SPLIT_MASK 0x00003800L
5659#define GB_TILE_MODE23__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
5660#define GB_TILE_MODE23__SAMPLE_SPLIT_MASK 0x06000000L
5661//GB_TILE_MODE24
5662#define GB_TILE_MODE24__ARRAY_MODE__SHIFT 0x2
5663#define GB_TILE_MODE24__PIPE_CONFIG__SHIFT 0x6
5664#define GB_TILE_MODE24__TILE_SPLIT__SHIFT 0xb
5665#define GB_TILE_MODE24__MICRO_TILE_MODE_NEW__SHIFT 0x16
5666#define GB_TILE_MODE24__SAMPLE_SPLIT__SHIFT 0x19
5667#define GB_TILE_MODE24__ARRAY_MODE_MASK 0x0000003CL
5668#define GB_TILE_MODE24__PIPE_CONFIG_MASK 0x000007C0L
5669#define GB_TILE_MODE24__TILE_SPLIT_MASK 0x00003800L
5670#define GB_TILE_MODE24__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
5671#define GB_TILE_MODE24__SAMPLE_SPLIT_MASK 0x06000000L
5672//GB_TILE_MODE25
5673#define GB_TILE_MODE25__ARRAY_MODE__SHIFT 0x2
5674#define GB_TILE_MODE25__PIPE_CONFIG__SHIFT 0x6
5675#define GB_TILE_MODE25__TILE_SPLIT__SHIFT 0xb
5676#define GB_TILE_MODE25__MICRO_TILE_MODE_NEW__SHIFT 0x16
5677#define GB_TILE_MODE25__SAMPLE_SPLIT__SHIFT 0x19
5678#define GB_TILE_MODE25__ARRAY_MODE_MASK 0x0000003CL
5679#define GB_TILE_MODE25__PIPE_CONFIG_MASK 0x000007C0L
5680#define GB_TILE_MODE25__TILE_SPLIT_MASK 0x00003800L
5681#define GB_TILE_MODE25__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
5682#define GB_TILE_MODE25__SAMPLE_SPLIT_MASK 0x06000000L
5683//GB_TILE_MODE26
5684#define GB_TILE_MODE26__ARRAY_MODE__SHIFT 0x2
5685#define GB_TILE_MODE26__PIPE_CONFIG__SHIFT 0x6
5686#define GB_TILE_MODE26__TILE_SPLIT__SHIFT 0xb
5687#define GB_TILE_MODE26__MICRO_TILE_MODE_NEW__SHIFT 0x16
5688#define GB_TILE_MODE26__SAMPLE_SPLIT__SHIFT 0x19
5689#define GB_TILE_MODE26__ARRAY_MODE_MASK 0x0000003CL
5690#define GB_TILE_MODE26__PIPE_CONFIG_MASK 0x000007C0L
5691#define GB_TILE_MODE26__TILE_SPLIT_MASK 0x00003800L
5692#define GB_TILE_MODE26__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
5693#define GB_TILE_MODE26__SAMPLE_SPLIT_MASK 0x06000000L
5694//GB_TILE_MODE27
5695#define GB_TILE_MODE27__ARRAY_MODE__SHIFT 0x2
5696#define GB_TILE_MODE27__PIPE_CONFIG__SHIFT 0x6
5697#define GB_TILE_MODE27__TILE_SPLIT__SHIFT 0xb
5698#define GB_TILE_MODE27__MICRO_TILE_MODE_NEW__SHIFT 0x16
5699#define GB_TILE_MODE27__SAMPLE_SPLIT__SHIFT 0x19
5700#define GB_TILE_MODE27__ARRAY_MODE_MASK 0x0000003CL
5701#define GB_TILE_MODE27__PIPE_CONFIG_MASK 0x000007C0L
5702#define GB_TILE_MODE27__TILE_SPLIT_MASK 0x00003800L
5703#define GB_TILE_MODE27__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
5704#define GB_TILE_MODE27__SAMPLE_SPLIT_MASK 0x06000000L
5705//GB_TILE_MODE28
5706#define GB_TILE_MODE28__ARRAY_MODE__SHIFT 0x2
5707#define GB_TILE_MODE28__PIPE_CONFIG__SHIFT 0x6
5708#define GB_TILE_MODE28__TILE_SPLIT__SHIFT 0xb
5709#define GB_TILE_MODE28__MICRO_TILE_MODE_NEW__SHIFT 0x16
5710#define GB_TILE_MODE28__SAMPLE_SPLIT__SHIFT 0x19
5711#define GB_TILE_MODE28__ARRAY_MODE_MASK 0x0000003CL
5712#define GB_TILE_MODE28__PIPE_CONFIG_MASK 0x000007C0L
5713#define GB_TILE_MODE28__TILE_SPLIT_MASK 0x00003800L
5714#define GB_TILE_MODE28__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
5715#define GB_TILE_MODE28__SAMPLE_SPLIT_MASK 0x06000000L
5716//GB_TILE_MODE29
5717#define GB_TILE_MODE29__ARRAY_MODE__SHIFT 0x2
5718#define GB_TILE_MODE29__PIPE_CONFIG__SHIFT 0x6
5719#define GB_TILE_MODE29__TILE_SPLIT__SHIFT 0xb
5720#define GB_TILE_MODE29__MICRO_TILE_MODE_NEW__SHIFT 0x16
5721#define GB_TILE_MODE29__SAMPLE_SPLIT__SHIFT 0x19
5722#define GB_TILE_MODE29__ARRAY_MODE_MASK 0x0000003CL
5723#define GB_TILE_MODE29__PIPE_CONFIG_MASK 0x000007C0L
5724#define GB_TILE_MODE29__TILE_SPLIT_MASK 0x00003800L
5725#define GB_TILE_MODE29__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
5726#define GB_TILE_MODE29__SAMPLE_SPLIT_MASK 0x06000000L
5727//GB_TILE_MODE30
5728#define GB_TILE_MODE30__ARRAY_MODE__SHIFT 0x2
5729#define GB_TILE_MODE30__PIPE_CONFIG__SHIFT 0x6
5730#define GB_TILE_MODE30__TILE_SPLIT__SHIFT 0xb
5731#define GB_TILE_MODE30__MICRO_TILE_MODE_NEW__SHIFT 0x16
5732#define GB_TILE_MODE30__SAMPLE_SPLIT__SHIFT 0x19
5733#define GB_TILE_MODE30__ARRAY_MODE_MASK 0x0000003CL
5734#define GB_TILE_MODE30__PIPE_CONFIG_MASK 0x000007C0L
5735#define GB_TILE_MODE30__TILE_SPLIT_MASK 0x00003800L
5736#define GB_TILE_MODE30__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
5737#define GB_TILE_MODE30__SAMPLE_SPLIT_MASK 0x06000000L
5738//GB_TILE_MODE31
5739#define GB_TILE_MODE31__ARRAY_MODE__SHIFT 0x2
5740#define GB_TILE_MODE31__PIPE_CONFIG__SHIFT 0x6
5741#define GB_TILE_MODE31__TILE_SPLIT__SHIFT 0xb
5742#define GB_TILE_MODE31__MICRO_TILE_MODE_NEW__SHIFT 0x16
5743#define GB_TILE_MODE31__SAMPLE_SPLIT__SHIFT 0x19
5744#define GB_TILE_MODE31__ARRAY_MODE_MASK 0x0000003CL
5745#define GB_TILE_MODE31__PIPE_CONFIG_MASK 0x000007C0L
5746#define GB_TILE_MODE31__TILE_SPLIT_MASK 0x00003800L
5747#define GB_TILE_MODE31__MICRO_TILE_MODE_NEW_MASK 0x01C00000L
5748#define GB_TILE_MODE31__SAMPLE_SPLIT_MASK 0x06000000L
5749//GB_MACROTILE_MODE0
5750#define GB_MACROTILE_MODE0__BANK_WIDTH__SHIFT 0x0
5751#define GB_MACROTILE_MODE0__BANK_HEIGHT__SHIFT 0x2
5752#define GB_MACROTILE_MODE0__MACRO_TILE_ASPECT__SHIFT 0x4
5753#define GB_MACROTILE_MODE0__NUM_BANKS__SHIFT 0x6
5754#define GB_MACROTILE_MODE0__BANK_WIDTH_MASK 0x00000003L
5755#define GB_MACROTILE_MODE0__BANK_HEIGHT_MASK 0x0000000CL
5756#define GB_MACROTILE_MODE0__MACRO_TILE_ASPECT_MASK 0x00000030L
5757#define GB_MACROTILE_MODE0__NUM_BANKS_MASK 0x000000C0L
5758//GB_MACROTILE_MODE1
5759#define GB_MACROTILE_MODE1__BANK_WIDTH__SHIFT 0x0
5760#define GB_MACROTILE_MODE1__BANK_HEIGHT__SHIFT 0x2
5761#define GB_MACROTILE_MODE1__MACRO_TILE_ASPECT__SHIFT 0x4
5762#define GB_MACROTILE_MODE1__NUM_BANKS__SHIFT 0x6
5763#define GB_MACROTILE_MODE1__BANK_WIDTH_MASK 0x00000003L
5764#define GB_MACROTILE_MODE1__BANK_HEIGHT_MASK 0x0000000CL
5765#define GB_MACROTILE_MODE1__MACRO_TILE_ASPECT_MASK 0x00000030L
5766#define GB_MACROTILE_MODE1__NUM_BANKS_MASK 0x000000C0L
5767//GB_MACROTILE_MODE2
5768#define GB_MACROTILE_MODE2__BANK_WIDTH__SHIFT 0x0
5769#define GB_MACROTILE_MODE2__BANK_HEIGHT__SHIFT 0x2
5770#define GB_MACROTILE_MODE2__MACRO_TILE_ASPECT__SHIFT 0x4
5771#define GB_MACROTILE_MODE2__NUM_BANKS__SHIFT 0x6
5772#define GB_MACROTILE_MODE2__BANK_WIDTH_MASK 0x00000003L
5773#define GB_MACROTILE_MODE2__BANK_HEIGHT_MASK 0x0000000CL
5774#define GB_MACROTILE_MODE2__MACRO_TILE_ASPECT_MASK 0x00000030L
5775#define GB_MACROTILE_MODE2__NUM_BANKS_MASK 0x000000C0L
5776//GB_MACROTILE_MODE3
5777#define GB_MACROTILE_MODE3__BANK_WIDTH__SHIFT 0x0
5778#define GB_MACROTILE_MODE3__BANK_HEIGHT__SHIFT 0x2
5779#define GB_MACROTILE_MODE3__MACRO_TILE_ASPECT__SHIFT 0x4
5780#define GB_MACROTILE_MODE3__NUM_BANKS__SHIFT 0x6
5781#define GB_MACROTILE_MODE3__BANK_WIDTH_MASK 0x00000003L
5782#define GB_MACROTILE_MODE3__BANK_HEIGHT_MASK 0x0000000CL
5783#define GB_MACROTILE_MODE3__MACRO_TILE_ASPECT_MASK 0x00000030L
5784#define GB_MACROTILE_MODE3__NUM_BANKS_MASK 0x000000C0L
5785//GB_MACROTILE_MODE4
5786#define GB_MACROTILE_MODE4__BANK_WIDTH__SHIFT 0x0
5787#define GB_MACROTILE_MODE4__BANK_HEIGHT__SHIFT 0x2
5788#define GB_MACROTILE_MODE4__MACRO_TILE_ASPECT__SHIFT 0x4
5789#define GB_MACROTILE_MODE4__NUM_BANKS__SHIFT 0x6
5790#define GB_MACROTILE_MODE4__BANK_WIDTH_MASK 0x00000003L
5791#define GB_MACROTILE_MODE4__BANK_HEIGHT_MASK 0x0000000CL
5792#define GB_MACROTILE_MODE4__MACRO_TILE_ASPECT_MASK 0x00000030L
5793#define GB_MACROTILE_MODE4__NUM_BANKS_MASK 0x000000C0L
5794//GB_MACROTILE_MODE5
5795#define GB_MACROTILE_MODE5__BANK_WIDTH__SHIFT 0x0
5796#define GB_MACROTILE_MODE5__BANK_HEIGHT__SHIFT 0x2
5797#define GB_MACROTILE_MODE5__MACRO_TILE_ASPECT__SHIFT 0x4
5798#define GB_MACROTILE_MODE5__NUM_BANKS__SHIFT 0x6
5799#define GB_MACROTILE_MODE5__BANK_WIDTH_MASK 0x00000003L
5800#define GB_MACROTILE_MODE5__BANK_HEIGHT_MASK 0x0000000CL
5801#define GB_MACROTILE_MODE5__MACRO_TILE_ASPECT_MASK 0x00000030L
5802#define GB_MACROTILE_MODE5__NUM_BANKS_MASK 0x000000C0L
5803//GB_MACROTILE_MODE6
5804#define GB_MACROTILE_MODE6__BANK_WIDTH__SHIFT 0x0
5805#define GB_MACROTILE_MODE6__BANK_HEIGHT__SHIFT 0x2
5806#define GB_MACROTILE_MODE6__MACRO_TILE_ASPECT__SHIFT 0x4
5807#define GB_MACROTILE_MODE6__NUM_BANKS__SHIFT 0x6
5808#define GB_MACROTILE_MODE6__BANK_WIDTH_MASK 0x00000003L
5809#define GB_MACROTILE_MODE6__BANK_HEIGHT_MASK 0x0000000CL
5810#define GB_MACROTILE_MODE6__MACRO_TILE_ASPECT_MASK 0x00000030L
5811#define GB_MACROTILE_MODE6__NUM_BANKS_MASK 0x000000C0L
5812//GB_MACROTILE_MODE7
5813#define GB_MACROTILE_MODE7__BANK_WIDTH__SHIFT 0x0
5814#define GB_MACROTILE_MODE7__BANK_HEIGHT__SHIFT 0x2
5815#define GB_MACROTILE_MODE7__MACRO_TILE_ASPECT__SHIFT 0x4
5816#define GB_MACROTILE_MODE7__NUM_BANKS__SHIFT 0x6
5817#define GB_MACROTILE_MODE7__BANK_WIDTH_MASK 0x00000003L
5818#define GB_MACROTILE_MODE7__BANK_HEIGHT_MASK 0x0000000CL
5819#define GB_MACROTILE_MODE7__MACRO_TILE_ASPECT_MASK 0x00000030L
5820#define GB_MACROTILE_MODE7__NUM_BANKS_MASK 0x000000C0L
5821//GB_MACROTILE_MODE8
5822#define GB_MACROTILE_MODE8__BANK_WIDTH__SHIFT 0x0
5823#define GB_MACROTILE_MODE8__BANK_HEIGHT__SHIFT 0x2
5824#define GB_MACROTILE_MODE8__MACRO_TILE_ASPECT__SHIFT 0x4
5825#define GB_MACROTILE_MODE8__NUM_BANKS__SHIFT 0x6
5826#define GB_MACROTILE_MODE8__BANK_WIDTH_MASK 0x00000003L
5827#define GB_MACROTILE_MODE8__BANK_HEIGHT_MASK 0x0000000CL
5828#define GB_MACROTILE_MODE8__MACRO_TILE_ASPECT_MASK 0x00000030L
5829#define GB_MACROTILE_MODE8__NUM_BANKS_MASK 0x000000C0L
5830//GB_MACROTILE_MODE9
5831#define GB_MACROTILE_MODE9__BANK_WIDTH__SHIFT 0x0
5832#define GB_MACROTILE_MODE9__BANK_HEIGHT__SHIFT 0x2
5833#define GB_MACROTILE_MODE9__MACRO_TILE_ASPECT__SHIFT 0x4
5834#define GB_MACROTILE_MODE9__NUM_BANKS__SHIFT 0x6
5835#define GB_MACROTILE_MODE9__BANK_WIDTH_MASK 0x00000003L
5836#define GB_MACROTILE_MODE9__BANK_HEIGHT_MASK 0x0000000CL
5837#define GB_MACROTILE_MODE9__MACRO_TILE_ASPECT_MASK 0x00000030L
5838#define GB_MACROTILE_MODE9__NUM_BANKS_MASK 0x000000C0L
5839//GB_MACROTILE_MODE10
5840#define GB_MACROTILE_MODE10__BANK_WIDTH__SHIFT 0x0
5841#define GB_MACROTILE_MODE10__BANK_HEIGHT__SHIFT 0x2
5842#define GB_MACROTILE_MODE10__MACRO_TILE_ASPECT__SHIFT 0x4
5843#define GB_MACROTILE_MODE10__NUM_BANKS__SHIFT 0x6
5844#define GB_MACROTILE_MODE10__BANK_WIDTH_MASK 0x00000003L
5845#define GB_MACROTILE_MODE10__BANK_HEIGHT_MASK 0x0000000CL
5846#define GB_MACROTILE_MODE10__MACRO_TILE_ASPECT_MASK 0x00000030L
5847#define GB_MACROTILE_MODE10__NUM_BANKS_MASK 0x000000C0L
5848//GB_MACROTILE_MODE11
5849#define GB_MACROTILE_MODE11__BANK_WIDTH__SHIFT 0x0
5850#define GB_MACROTILE_MODE11__BANK_HEIGHT__SHIFT 0x2
5851#define GB_MACROTILE_MODE11__MACRO_TILE_ASPECT__SHIFT 0x4
5852#define GB_MACROTILE_MODE11__NUM_BANKS__SHIFT 0x6
5853#define GB_MACROTILE_MODE11__BANK_WIDTH_MASK 0x00000003L
5854#define GB_MACROTILE_MODE11__BANK_HEIGHT_MASK 0x0000000CL
5855#define GB_MACROTILE_MODE11__MACRO_TILE_ASPECT_MASK 0x00000030L
5856#define GB_MACROTILE_MODE11__NUM_BANKS_MASK 0x000000C0L
5857//GB_MACROTILE_MODE12
5858#define GB_MACROTILE_MODE12__BANK_WIDTH__SHIFT 0x0
5859#define GB_MACROTILE_MODE12__BANK_HEIGHT__SHIFT 0x2
5860#define GB_MACROTILE_MODE12__MACRO_TILE_ASPECT__SHIFT 0x4
5861#define GB_MACROTILE_MODE12__NUM_BANKS__SHIFT 0x6
5862#define GB_MACROTILE_MODE12__BANK_WIDTH_MASK 0x00000003L
5863#define GB_MACROTILE_MODE12__BANK_HEIGHT_MASK 0x0000000CL
5864#define GB_MACROTILE_MODE12__MACRO_TILE_ASPECT_MASK 0x00000030L
5865#define GB_MACROTILE_MODE12__NUM_BANKS_MASK 0x000000C0L
5866//GB_MACROTILE_MODE13
5867#define GB_MACROTILE_MODE13__BANK_WIDTH__SHIFT 0x0
5868#define GB_MACROTILE_MODE13__BANK_HEIGHT__SHIFT 0x2
5869#define GB_MACROTILE_MODE13__MACRO_TILE_ASPECT__SHIFT 0x4
5870#define GB_MACROTILE_MODE13__NUM_BANKS__SHIFT 0x6
5871#define GB_MACROTILE_MODE13__BANK_WIDTH_MASK 0x00000003L
5872#define GB_MACROTILE_MODE13__BANK_HEIGHT_MASK 0x0000000CL
5873#define GB_MACROTILE_MODE13__MACRO_TILE_ASPECT_MASK 0x00000030L
5874#define GB_MACROTILE_MODE13__NUM_BANKS_MASK 0x000000C0L
5875//GB_MACROTILE_MODE14
5876#define GB_MACROTILE_MODE14__BANK_WIDTH__SHIFT 0x0
5877#define GB_MACROTILE_MODE14__BANK_HEIGHT__SHIFT 0x2
5878#define GB_MACROTILE_MODE14__MACRO_TILE_ASPECT__SHIFT 0x4
5879#define GB_MACROTILE_MODE14__NUM_BANKS__SHIFT 0x6
5880#define GB_MACROTILE_MODE14__BANK_WIDTH_MASK 0x00000003L
5881#define GB_MACROTILE_MODE14__BANK_HEIGHT_MASK 0x0000000CL
5882#define GB_MACROTILE_MODE14__MACRO_TILE_ASPECT_MASK 0x00000030L
5883#define GB_MACROTILE_MODE14__NUM_BANKS_MASK 0x000000C0L
5884//GB_MACROTILE_MODE15
5885#define GB_MACROTILE_MODE15__BANK_WIDTH__SHIFT 0x0
5886#define GB_MACROTILE_MODE15__BANK_HEIGHT__SHIFT 0x2
5887#define GB_MACROTILE_MODE15__MACRO_TILE_ASPECT__SHIFT 0x4
5888#define GB_MACROTILE_MODE15__NUM_BANKS__SHIFT 0x6
5889#define GB_MACROTILE_MODE15__BANK_WIDTH_MASK 0x00000003L
5890#define GB_MACROTILE_MODE15__BANK_HEIGHT_MASK 0x0000000CL
5891#define GB_MACROTILE_MODE15__MACRO_TILE_ASPECT_MASK 0x00000030L
5892#define GB_MACROTILE_MODE15__NUM_BANKS_MASK 0x000000C0L
5893//CB_HW_CONTROL
5894#define CB_HW_CONTROL__CM_CACHE_EVICT_POINT__SHIFT 0x0
5895#define CB_HW_CONTROL__FC_CACHE_EVICT_POINT__SHIFT 0x6
5896#define CB_HW_CONTROL__CC_CACHE_EVICT_POINT__SHIFT 0xc
5897#define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE__SHIFT 0x10
5898#define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING__SHIFT 0x12
5899#define CB_HW_CONTROL__FORCE_NEEDS_DST__SHIFT 0x13
5900#define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE__SHIFT 0x14
5901#define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST__SHIFT 0x15
5902#define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK__SHIFT 0x16
5903#define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG__SHIFT 0x17
5904#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT 0x18
5905#define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS__SHIFT 0x19
5906#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT 0x1a
5907#define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED__SHIFT 0x1b
5908#define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT__SHIFT 0x1c
5909#define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT__SHIFT 0x1d
5910#define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT__SHIFT 0x1e
5911#define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE__SHIFT 0x1f
5912#define CB_HW_CONTROL__CM_CACHE_EVICT_POINT_MASK 0x0000000FL
5913#define CB_HW_CONTROL__FC_CACHE_EVICT_POINT_MASK 0x000003C0L
5914#define CB_HW_CONTROL__CC_CACHE_EVICT_POINT_MASK 0x0000F000L
5915#define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE_MASK 0x00010000L
5916#define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING_MASK 0x00040000L
5917#define CB_HW_CONTROL__FORCE_NEEDS_DST_MASK 0x00080000L
5918#define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE_MASK 0x00100000L
5919#define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST_MASK 0x00200000L
5920#define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK_MASK 0x00400000L
5921#define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG_MASK 0x00800000L
5922#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST_MASK 0x01000000L
5923#define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS_MASK 0x02000000L
5924#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK 0x04000000L
5925#define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED_MASK 0x08000000L
5926#define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT_MASK 0x10000000L
5927#define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT_MASK 0x20000000L
5928#define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT_MASK 0x40000000L
5929#define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE_MASK 0x80000000L
5930//CB_HW_CONTROL_1
5931#define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS__SHIFT 0x0
5932#define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS__SHIFT 0x5
5933#define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS__SHIFT 0xb
5934#define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH__SHIFT 0x11
5935#define CB_HW_CONTROL_1__RMI_CREDITS__SHIFT 0x1a
5936#define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS_MASK 0x0000001FL
5937#define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS_MASK 0x000007E0L
5938#define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS_MASK 0x0001F800L
5939#define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH_MASK 0x03FE0000L
5940#define CB_HW_CONTROL_1__RMI_CREDITS_MASK 0xFC000000L
5941//CB_HW_CONTROL_2
5942#define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH__SHIFT 0x0
5943#define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH__SHIFT 0x8
5944#define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH__SHIFT 0xf
5945#define CB_HW_CONTROL_2__DRR_ASSUMED_FIFO_DEPTH_DIV8__SHIFT 0x18
5946#define CB_HW_CONTROL_2__CHICKEN_BITS__SHIFT 0x1c
5947#define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH_MASK 0x000000FFL
5948#define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH_MASK 0x00007F00L
5949#define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH_MASK 0x007F8000L
5950#define CB_HW_CONTROL_2__DRR_ASSUMED_FIFO_DEPTH_DIV8_MASK 0x0F000000L
5951#define CB_HW_CONTROL_2__CHICKEN_BITS_MASK 0xF0000000L
5952//CB_HW_CONTROL_3
5953#define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL__SHIFT 0x0
5954#define CB_HW_CONTROL_3__RAM_ADDRESS_CONFLICTS_DISALLOWED__SHIFT 0x1
5955#define CB_HW_CONTROL_3__DISABLE_FAST_CLEAR_FETCH_OPT__SHIFT 0x2
5956#define CB_HW_CONTROL_3__DISABLE_QUAD_MARKER_DROP_STOP__SHIFT 0x3
5957#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_CAM_CLR__SHIFT 0x4
5958#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_STATUS_ACCUM__SHIFT 0x5
5959#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_KEY_MOD__SHIFT 0x6
5960#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_PANIC_GATING__SHIFT 0x7
5961#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_TARGET_MASK_VALIDATION__SHIFT 0x8
5962#define CB_HW_CONTROL_3__SPLIT_ALL_FAST_MODE_TRANSFERS__SHIFT 0x9
5963#define CB_HW_CONTROL_3__DISABLE_SHADER_BLEND_OPTS__SHIFT 0xa
5964#define CB_HW_CONTROL_3__DISABLE_CMASK_LAST_QUAD_INSERTION__SHIFT 0xb
5965#define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_511967__SHIFT 0xc
5966#define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_520657__SHIFT 0xd
5967#define CB_HW_CONTROL_3__DISABLE_OC_FIXES_OF_BUG_522542__SHIFT 0xe
5968#define CB_HW_CONTROL_3__FORCE_RMI_LAST_HIGH__SHIFT 0xf
5969#define CB_HW_CONTROL_3__FORCE_RMI_CLKEN_HIGH__SHIFT 0x10
5970#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CC__SHIFT 0x11
5971#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_FC__SHIFT 0x12
5972#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_DC__SHIFT 0x13
5973#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CM__SHIFT 0x14
5974#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CC__SHIFT 0x15
5975#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_FC__SHIFT 0x16
5976#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_DC__SHIFT 0x17
5977#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CM__SHIFT 0x18
5978#define CB_HW_CONTROL_3__DISABLE_NACK_COLOR_RD_WR_OPT__SHIFT 0x19
5979#define CB_HW_CONTROL_3__DISABLE_BLENDER_CLOCK_GATING__SHIFT 0x1a
5980#define CB_HW_CONTROL_3__DISABLE_DUALSRC_WITH_OBJPRIMID_FIX__SHIFT 0x1b
5981#define CB_HW_CONTROL_3__COLOR_CACHE_PREFETCH_NUM_CLS__SHIFT 0x1c
5982#define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL_MASK 0x00000001L
5983#define CB_HW_CONTROL_3__RAM_ADDRESS_CONFLICTS_DISALLOWED_MASK 0x00000002L
5984#define CB_HW_CONTROL_3__DISABLE_FAST_CLEAR_FETCH_OPT_MASK 0x00000004L
5985#define CB_HW_CONTROL_3__DISABLE_QUAD_MARKER_DROP_STOP_MASK 0x00000008L
5986#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_CAM_CLR_MASK 0x00000010L
5987#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_STATUS_ACCUM_MASK 0x00000020L
5988#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_KEY_MOD_MASK 0x00000040L
5989#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_PANIC_GATING_MASK 0x00000080L
5990#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_TARGET_MASK_VALIDATION_MASK 0x00000100L
5991#define CB_HW_CONTROL_3__SPLIT_ALL_FAST_MODE_TRANSFERS_MASK 0x00000200L
5992#define CB_HW_CONTROL_3__DISABLE_SHADER_BLEND_OPTS_MASK 0x00000400L
5993#define CB_HW_CONTROL_3__DISABLE_CMASK_LAST_QUAD_INSERTION_MASK 0x00000800L
5994#define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_511967_MASK 0x00001000L
5995#define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_520657_MASK 0x00002000L
5996#define CB_HW_CONTROL_3__DISABLE_OC_FIXES_OF_BUG_522542_MASK 0x00004000L
5997#define CB_HW_CONTROL_3__FORCE_RMI_LAST_HIGH_MASK 0x00008000L
5998#define CB_HW_CONTROL_3__FORCE_RMI_CLKEN_HIGH_MASK 0x00010000L
5999#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CC_MASK 0x00020000L
6000#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_FC_MASK 0x00040000L
6001#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_DC_MASK 0x00080000L
6002#define CB_HW_CONTROL_3__DISABLE_EARLY_WRACKS_CM_MASK 0x00100000L
6003#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CC_MASK 0x00200000L
6004#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_FC_MASK 0x00400000L
6005#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_DC_MASK 0x00800000L
6006#define CB_HW_CONTROL_3__DISABLE_NACK_PROCESSING_CM_MASK 0x01000000L
6007#define CB_HW_CONTROL_3__DISABLE_NACK_COLOR_RD_WR_OPT_MASK 0x02000000L
6008#define CB_HW_CONTROL_3__DISABLE_BLENDER_CLOCK_GATING_MASK 0x04000000L
6009#define CB_HW_CONTROL_3__DISABLE_DUALSRC_WITH_OBJPRIMID_FIX_MASK 0x08000000L
6010#define CB_HW_CONTROL_3__COLOR_CACHE_PREFETCH_NUM_CLS_MASK 0x30000000L
6011//CB_HW_MEM_ARBITER_RD
6012#define CB_HW_MEM_ARBITER_RD__MODE__SHIFT 0x0
6013#define CB_HW_MEM_ARBITER_RD__IGNORE_URGENT_AGE__SHIFT 0x2
6014#define CB_HW_MEM_ARBITER_RD__BREAK_GROUP_AGE__SHIFT 0x6
6015#define CB_HW_MEM_ARBITER_RD__WEIGHT_CC__SHIFT 0xa
6016#define CB_HW_MEM_ARBITER_RD__WEIGHT_FC__SHIFT 0xc
6017#define CB_HW_MEM_ARBITER_RD__WEIGHT_CM__SHIFT 0xe
6018#define CB_HW_MEM_ARBITER_RD__WEIGHT_DC__SHIFT 0x10
6019#define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_REQS__SHIFT 0x12
6020#define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_NOREQS__SHIFT 0x14
6021#define CB_HW_MEM_ARBITER_RD__WEIGHT_IGNORE_NUM_TIDS__SHIFT 0x16
6022#define CB_HW_MEM_ARBITER_RD__SCALE_AGE__SHIFT 0x17
6023#define CB_HW_MEM_ARBITER_RD__SCALE_WEIGHT__SHIFT 0x1a
6024#define CB_HW_MEM_ARBITER_RD__SEND_LASTS_WITHIN_GROUPS__SHIFT 0x1d
6025#define CB_HW_MEM_ARBITER_RD__MODE_MASK 0x00000003L
6026#define CB_HW_MEM_ARBITER_RD__IGNORE_URGENT_AGE_MASK 0x0000003CL
6027#define CB_HW_MEM_ARBITER_RD__BREAK_GROUP_AGE_MASK 0x000003C0L
6028#define CB_HW_MEM_ARBITER_RD__WEIGHT_CC_MASK 0x00000C00L
6029#define CB_HW_MEM_ARBITER_RD__WEIGHT_FC_MASK 0x00003000L
6030#define CB_HW_MEM_ARBITER_RD__WEIGHT_CM_MASK 0x0000C000L
6031#define CB_HW_MEM_ARBITER_RD__WEIGHT_DC_MASK 0x00030000L
6032#define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_REQS_MASK 0x000C0000L
6033#define CB_HW_MEM_ARBITER_RD__WEIGHT_DECAY_NOREQS_MASK 0x00300000L
6034#define CB_HW_MEM_ARBITER_RD__WEIGHT_IGNORE_NUM_TIDS_MASK 0x00400000L
6035#define CB_HW_MEM_ARBITER_RD__SCALE_AGE_MASK 0x03800000L
6036#define CB_HW_MEM_ARBITER_RD__SCALE_WEIGHT_MASK 0x1C000000L
6037#define CB_HW_MEM_ARBITER_RD__SEND_LASTS_WITHIN_GROUPS_MASK 0x20000000L
6038//CB_HW_MEM_ARBITER_WR
6039#define CB_HW_MEM_ARBITER_WR__MODE__SHIFT 0x0
6040#define CB_HW_MEM_ARBITER_WR__IGNORE_URGENT_AGE__SHIFT 0x2
6041#define CB_HW_MEM_ARBITER_WR__BREAK_GROUP_AGE__SHIFT 0x6
6042#define CB_HW_MEM_ARBITER_WR__WEIGHT_CC__SHIFT 0xa
6043#define CB_HW_MEM_ARBITER_WR__WEIGHT_FC__SHIFT 0xc
6044#define CB_HW_MEM_ARBITER_WR__WEIGHT_CM__SHIFT 0xe
6045#define CB_HW_MEM_ARBITER_WR__WEIGHT_DC__SHIFT 0x10
6046#define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_REQS__SHIFT 0x12
6047#define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_NOREQS__SHIFT 0x14
6048#define CB_HW_MEM_ARBITER_WR__WEIGHT_IGNORE_BYTE_MASK__SHIFT 0x16
6049#define CB_HW_MEM_ARBITER_WR__SCALE_AGE__SHIFT 0x17
6050#define CB_HW_MEM_ARBITER_WR__SCALE_WEIGHT__SHIFT 0x1a
6051#define CB_HW_MEM_ARBITER_WR__SEND_LASTS_WITHIN_GROUPS__SHIFT 0x1d
6052#define CB_HW_MEM_ARBITER_WR__MODE_MASK 0x00000003L
6053#define CB_HW_MEM_ARBITER_WR__IGNORE_URGENT_AGE_MASK 0x0000003CL
6054#define CB_HW_MEM_ARBITER_WR__BREAK_GROUP_AGE_MASK 0x000003C0L
6055#define CB_HW_MEM_ARBITER_WR__WEIGHT_CC_MASK 0x00000C00L
6056#define CB_HW_MEM_ARBITER_WR__WEIGHT_FC_MASK 0x00003000L
6057#define CB_HW_MEM_ARBITER_WR__WEIGHT_CM_MASK 0x0000C000L
6058#define CB_HW_MEM_ARBITER_WR__WEIGHT_DC_MASK 0x00030000L
6059#define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_REQS_MASK 0x000C0000L
6060#define CB_HW_MEM_ARBITER_WR__WEIGHT_DECAY_NOREQS_MASK 0x00300000L
6061#define CB_HW_MEM_ARBITER_WR__WEIGHT_IGNORE_BYTE_MASK_MASK 0x00400000L
6062#define CB_HW_MEM_ARBITER_WR__SCALE_AGE_MASK 0x03800000L
6063#define CB_HW_MEM_ARBITER_WR__SCALE_WEIGHT_MASK 0x1C000000L
6064#define CB_HW_MEM_ARBITER_WR__SEND_LASTS_WITHIN_GROUPS_MASK 0x20000000L
6065//CB_DCC_CONFIG
6066#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DEPTH__SHIFT 0x0
6067#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DISABLE__SHIFT 0x5
6068#define CB_DCC_CONFIG__OVERWRITE_COMBINER_CC_POP_DISABLE__SHIFT 0x6
6069#define CB_DCC_CONFIG__FC_RDLAT_KEYID_FIFO_DEPTH__SHIFT 0x8
6070#define CB_DCC_CONFIG__READ_RETURN_SKID_FIFO_DEPTH__SHIFT 0x10
6071#define CB_DCC_CONFIG__DCC_CACHE_EVICT_POINT__SHIFT 0x18
6072#define CB_DCC_CONFIG__DCC_CACHE_NUM_TAGS__SHIFT 0x1c
6073#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DEPTH_MASK 0x0000001FL
6074#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DISABLE_MASK 0x00000020L
6075#define CB_DCC_CONFIG__OVERWRITE_COMBINER_CC_POP_DISABLE_MASK 0x00000040L
6076#define CB_DCC_CONFIG__FC_RDLAT_KEYID_FIFO_DEPTH_MASK 0x0000FF00L
6077#define CB_DCC_CONFIG__READ_RETURN_SKID_FIFO_DEPTH_MASK 0x007F0000L
6078#define CB_DCC_CONFIG__DCC_CACHE_EVICT_POINT_MASK 0x0F000000L
6079#define CB_DCC_CONFIG__DCC_CACHE_NUM_TAGS_MASK 0xF0000000L
6080//GC_USER_RB_REDUNDANCY
6081#define GC_USER_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8
6082#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc
6083#define GC_USER_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10
6084#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14
6085#define GC_USER_RB_REDUNDANCY__FAILED_RB0_MASK 0x00000F00L
6086#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x00001000L
6087#define GC_USER_RB_REDUNDANCY__FAILED_RB1_MASK 0x000F0000L
6088#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x00100000L
6089//GC_USER_RB_BACKEND_DISABLE
6090#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10
6091#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0x00FF0000L
6092
6093
6094// addressBlock: gc_rmi_rmidec
6095//RMI_GENERAL_CNTL
6096#define RMI_GENERAL_CNTL__BURST_DISABLE__SHIFT 0x0
6097#define RMI_GENERAL_CNTL__VMID_BYPASS_ENABLE__SHIFT 0x1
6098#define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG__SHIFT 0x11
6099#define RMI_GENERAL_CNTL__RB0_HARVEST_EN__SHIFT 0x13
6100#define RMI_GENERAL_CNTL__RB1_HARVEST_EN__SHIFT 0x14
6101#define RMI_GENERAL_CNTL__LOOPBACK_DIS_BY_REQ_TYPE__SHIFT 0x15
6102#define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG_UPDATE__SHIFT 0x19
6103#define RMI_GENERAL_CNTL__SKID_FIFO_0_OVERFLOW_ERROR_MASK__SHIFT 0x1a
6104#define RMI_GENERAL_CNTL__SKID_FIFO_0_UNDERFLOW_ERROR_MASK__SHIFT 0x1b
6105#define RMI_GENERAL_CNTL__SKID_FIFO_1_OVERFLOW_ERROR_MASK__SHIFT 0x1c
6106#define RMI_GENERAL_CNTL__SKID_FIFO_1_UNDERFLOW_ERROR_MASK__SHIFT 0x1d
6107#define RMI_GENERAL_CNTL__SKID_FIFO_FREESPACE_IS_ZERO_ERROR_MASK__SHIFT 0x1e
6108#define RMI_GENERAL_CNTL__BURST_DISABLE_MASK 0x00000001L
6109#define RMI_GENERAL_CNTL__VMID_BYPASS_ENABLE_MASK 0x0001FFFEL
6110#define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG_MASK 0x00060000L
6111#define RMI_GENERAL_CNTL__RB0_HARVEST_EN_MASK 0x00080000L
6112#define RMI_GENERAL_CNTL__RB1_HARVEST_EN_MASK 0x00100000L
6113#define RMI_GENERAL_CNTL__LOOPBACK_DIS_BY_REQ_TYPE_MASK 0x01E00000L
6114#define RMI_GENERAL_CNTL__XBAR_MUX_CONFIG_UPDATE_MASK 0x02000000L
6115#define RMI_GENERAL_CNTL__SKID_FIFO_0_OVERFLOW_ERROR_MASK_MASK 0x04000000L
6116#define RMI_GENERAL_CNTL__SKID_FIFO_0_UNDERFLOW_ERROR_MASK_MASK 0x08000000L
6117#define RMI_GENERAL_CNTL__SKID_FIFO_1_OVERFLOW_ERROR_MASK_MASK 0x10000000L
6118#define RMI_GENERAL_CNTL__SKID_FIFO_1_UNDERFLOW_ERROR_MASK_MASK 0x20000000L
6119#define RMI_GENERAL_CNTL__SKID_FIFO_FREESPACE_IS_ZERO_ERROR_MASK_MASK 0x40000000L
6120//RMI_GENERAL_CNTL1
6121#define RMI_GENERAL_CNTL1__EARLY_WRACK_ENABLE_PER_MTYPE__SHIFT 0x0
6122#define RMI_GENERAL_CNTL1__TCIW0_64B_RD_STALL_MODE__SHIFT 0x4
6123#define RMI_GENERAL_CNTL1__TCIW1_64B_RD_STALL_MODE__SHIFT 0x6
6124#define RMI_GENERAL_CNTL1__EARLY_WRACK_DISABLE_FOR_LOOPBACK__SHIFT 0x8
6125#define RMI_GENERAL_CNTL1__POLICY_OVERRIDE_VALUE__SHIFT 0x9
6126#define RMI_GENERAL_CNTL1__POLICY_OVERRIDE__SHIFT 0xa
6127#define RMI_GENERAL_CNTL1__UTCL1_PROBE0_RR_ARB_BURST_HINT_EN__SHIFT 0xb
6128#define RMI_GENERAL_CNTL1__UTCL1_PROBE1_RR_ARB_BURST_HINT_EN__SHIFT 0xc
6129#define RMI_GENERAL_CNTL1__EARLY_WRACK_ENABLE_PER_MTYPE_MASK 0x0000000FL
6130#define RMI_GENERAL_CNTL1__TCIW0_64B_RD_STALL_MODE_MASK 0x00000030L
6131#define RMI_GENERAL_CNTL1__TCIW1_64B_RD_STALL_MODE_MASK 0x000000C0L
6132#define RMI_GENERAL_CNTL1__EARLY_WRACK_DISABLE_FOR_LOOPBACK_MASK 0x00000100L
6133#define RMI_GENERAL_CNTL1__POLICY_OVERRIDE_VALUE_MASK 0x00000200L
6134#define RMI_GENERAL_CNTL1__POLICY_OVERRIDE_MASK 0x00000400L
6135#define RMI_GENERAL_CNTL1__UTCL1_PROBE0_RR_ARB_BURST_HINT_EN_MASK 0x00000800L
6136#define RMI_GENERAL_CNTL1__UTCL1_PROBE1_RR_ARB_BURST_HINT_EN_MASK 0x00001000L
6137//RMI_GENERAL_STATUS
6138#define RMI_GENERAL_STATUS__GENERAL_RMI_ERRORS_COMBINED__SHIFT 0x0
6139#define RMI_GENERAL_STATUS__SKID_FIFO_0_OVERFLOW_ERROR__SHIFT 0x1
6140#define RMI_GENERAL_STATUS__SKID_FIFO_0_UNDERFLOW_ERROR__SHIFT 0x2
6141#define RMI_GENERAL_STATUS__SKID_FIFO_1_OVERFLOW_ERROR__SHIFT 0x3
6142#define RMI_GENERAL_STATUS__SKID_FIFO_1_UNDERFLOW_ERROR__SHIFT 0x4
6143#define RMI_GENERAL_STATUS__RMI_XBAR_BUSY__SHIFT 0x5
6144#define RMI_GENERAL_STATUS__RMI_UTCL1_BUSY__SHIFT 0x6
6145#define RMI_GENERAL_STATUS__RMI_SCOREBOARD_BUSY__SHIFT 0x7
6146#define RMI_GENERAL_STATUS__TCIW0_PRT_FIFO_BUSY__SHIFT 0x8
6147#define RMI_GENERAL_STATUS__TCIW_FRMTR0_BUSY__SHIFT 0x9
6148#define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR0_BUSY__SHIFT 0xa
6149#define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_0_BUSY__SHIFT 0xb
6150#define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_0_BUSY__SHIFT 0xc
6151#define RMI_GENERAL_STATUS__TCIW1_PRT_FIFO_BUSY__SHIFT 0xd
6152#define RMI_GENERAL_STATUS__TCIW_FRMTR1_BUSY__SHIFT 0xe
6153#define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR1_BUSY__SHIFT 0xf
6154#define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_1_BUSY__SHIFT 0x10
6155#define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_1_BUSY__SHIFT 0x11
6156#define RMI_GENERAL_STATUS__UTC_PROBE1_BUSY__SHIFT 0x12
6157#define RMI_GENERAL_STATUS__UTC_PROBE0_BUSY__SHIFT 0x13
6158#define RMI_GENERAL_STATUS__RMI_XNACK_BUSY__SHIFT 0x14
6159#define RMI_GENERAL_STATUS__XNACK_FIFO_NUM_USED__SHIFT 0x15
6160#define RMI_GENERAL_STATUS__XNACK_FIFO_EMPTY__SHIFT 0x1d
6161#define RMI_GENERAL_STATUS__XNACK_FIFO_FULL__SHIFT 0x1e
6162#define RMI_GENERAL_STATUS__SKID_FIFO_FREESPACE_IS_ZERO_ERROR__SHIFT 0x1f
6163#define RMI_GENERAL_STATUS__GENERAL_RMI_ERRORS_COMBINED_MASK 0x00000001L
6164#define RMI_GENERAL_STATUS__SKID_FIFO_0_OVERFLOW_ERROR_MASK 0x00000002L
6165#define RMI_GENERAL_STATUS__SKID_FIFO_0_UNDERFLOW_ERROR_MASK 0x00000004L
6166#define RMI_GENERAL_STATUS__SKID_FIFO_1_OVERFLOW_ERROR_MASK 0x00000008L
6167#define RMI_GENERAL_STATUS__SKID_FIFO_1_UNDERFLOW_ERROR_MASK 0x00000010L
6168#define RMI_GENERAL_STATUS__RMI_XBAR_BUSY_MASK 0x00000020L
6169#define RMI_GENERAL_STATUS__RMI_UTCL1_BUSY_MASK 0x00000040L
6170#define RMI_GENERAL_STATUS__RMI_SCOREBOARD_BUSY_MASK 0x00000080L
6171#define RMI_GENERAL_STATUS__TCIW0_PRT_FIFO_BUSY_MASK 0x00000100L
6172#define RMI_GENERAL_STATUS__TCIW_FRMTR0_BUSY_MASK 0x00000200L
6173#define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR0_BUSY_MASK 0x00000400L
6174#define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_0_BUSY_MASK 0x00000800L
6175#define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_0_BUSY_MASK 0x00001000L
6176#define RMI_GENERAL_STATUS__TCIW1_PRT_FIFO_BUSY_MASK 0x00002000L
6177#define RMI_GENERAL_STATUS__TCIW_FRMTR1_BUSY_MASK 0x00004000L
6178#define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR1_BUSY_MASK 0x00008000L
6179#define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_1_BUSY_MASK 0x00010000L
6180#define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_1_BUSY_MASK 0x00020000L
6181#define RMI_GENERAL_STATUS__UTC_PROBE1_BUSY_MASK 0x00040000L
6182#define RMI_GENERAL_STATUS__UTC_PROBE0_BUSY_MASK 0x00080000L
6183#define RMI_GENERAL_STATUS__RMI_XNACK_BUSY_MASK 0x00100000L
6184#define RMI_GENERAL_STATUS__XNACK_FIFO_NUM_USED_MASK 0x1FE00000L
6185#define RMI_GENERAL_STATUS__XNACK_FIFO_EMPTY_MASK 0x20000000L
6186#define RMI_GENERAL_STATUS__XNACK_FIFO_FULL_MASK 0x40000000L
6187#define RMI_GENERAL_STATUS__SKID_FIFO_FREESPACE_IS_ZERO_ERROR_MASK 0x80000000L
6188//RMI_SUBBLOCK_STATUS0
6189#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE0__SHIFT 0x0
6190#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE0__SHIFT 0x7
6191#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE0__SHIFT 0x8
6192#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE1__SHIFT 0x9
6193#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE1__SHIFT 0x10
6194#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE1__SHIFT 0x11
6195#define RMI_SUBBLOCK_STATUS0__TCIW0_INFLIGHT_CNT__SHIFT 0x12
6196#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE0_MASK 0x0000007FL
6197#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE0_MASK 0x00000080L
6198#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE0_MASK 0x00000100L
6199#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE1_MASK 0x0000FE00L
6200#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE1_MASK 0x00010000L
6201#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE1_MASK 0x00020000L
6202#define RMI_SUBBLOCK_STATUS0__TCIW0_INFLIGHT_CNT_MASK 0x0FFC0000L
6203//RMI_SUBBLOCK_STATUS1
6204#define RMI_SUBBLOCK_STATUS1__SKID_FIFO_0_FREE_SPACE__SHIFT 0x0
6205#define RMI_SUBBLOCK_STATUS1__SKID_FIFO_1_FREE_SPACE__SHIFT 0xa
6206#define RMI_SUBBLOCK_STATUS1__TCIW1_INFLIGHT_CNT__SHIFT 0x14
6207#define RMI_SUBBLOCK_STATUS1__SKID_FIFO_0_FREE_SPACE_MASK 0x000003FFL
6208#define RMI_SUBBLOCK_STATUS1__SKID_FIFO_1_FREE_SPACE_MASK 0x000FFC00L
6209#define RMI_SUBBLOCK_STATUS1__TCIW1_INFLIGHT_CNT_MASK 0x3FF00000L
6210//RMI_SUBBLOCK_STATUS2
6211#define RMI_SUBBLOCK_STATUS2__PRT_FIFO_0_NUM_USED__SHIFT 0x0
6212#define RMI_SUBBLOCK_STATUS2__PRT_FIFO_1_NUM_USED__SHIFT 0x9
6213#define RMI_SUBBLOCK_STATUS2__PRT_FIFO_0_NUM_USED_MASK 0x000001FFL
6214#define RMI_SUBBLOCK_STATUS2__PRT_FIFO_1_NUM_USED_MASK 0x0003FE00L
6215//RMI_SUBBLOCK_STATUS3
6216#define RMI_SUBBLOCK_STATUS3__SKID_FIFO_0_FREE_SPACE_TOTAL__SHIFT 0x0
6217#define RMI_SUBBLOCK_STATUS3__SKID_FIFO_1_FREE_SPACE_TOTAL__SHIFT 0xa
6218#define RMI_SUBBLOCK_STATUS3__SKID_FIFO_0_FREE_SPACE_TOTAL_MASK 0x000003FFL
6219#define RMI_SUBBLOCK_STATUS3__SKID_FIFO_1_FREE_SPACE_TOTAL_MASK 0x000FFC00L
6220//RMI_XBAR_CONFIG
6221#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_OVERRIDE__SHIFT 0x0
6222#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_REQ_TYPE_OVERRIDE__SHIFT 0x2
6223#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_CB_DB_OVERRIDE__SHIFT 0x6
6224#define RMI_XBAR_CONFIG__ARBITER_DIS__SHIFT 0x7
6225#define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ__SHIFT 0x8
6226#define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_OVERRIDE__SHIFT 0xc
6227#define RMI_XBAR_CONFIG__XBAR_EN_IN_RB0__SHIFT 0xd
6228#define RMI_XBAR_CONFIG__XBAR_EN_IN_RB1__SHIFT 0xe
6229#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_OVERRIDE_MASK 0x00000003L
6230#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_REQ_TYPE_OVERRIDE_MASK 0x0000003CL
6231#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_CB_DB_OVERRIDE_MASK 0x00000040L
6232#define RMI_XBAR_CONFIG__ARBITER_DIS_MASK 0x00000080L
6233#define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_MASK 0x00000F00L
6234#define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_OVERRIDE_MASK 0x00001000L
6235#define RMI_XBAR_CONFIG__XBAR_EN_IN_RB0_MASK 0x00002000L
6236#define RMI_XBAR_CONFIG__XBAR_EN_IN_RB1_MASK 0x00004000L
6237//RMI_PROBE_POP_LOGIC_CNTL
6238#define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_0_MAX_DEPTH__SHIFT 0x0
6239#define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE0_DIS__SHIFT 0x7
6240#define RMI_PROBE_POP_LOGIC_CNTL__REDUCE_MAX_XLAT_CHAIN_SIZE_BY_2__SHIFT 0x8
6241#define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_1_MAX_DEPTH__SHIFT 0xa
6242#define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE1_DIS__SHIFT 0x11
6243#define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_0_MAX_DEPTH_MASK 0x0000007FL
6244#define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE0_DIS_MASK 0x00000080L
6245#define RMI_PROBE_POP_LOGIC_CNTL__REDUCE_MAX_XLAT_CHAIN_SIZE_BY_2_MASK 0x00000300L
6246#define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_1_MAX_DEPTH_MASK 0x0001FC00L
6247#define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE1_DIS_MASK 0x00020000L
6248//RMI_UTC_XNACK_N_MISC_CNTL
6249#define RMI_UTC_XNACK_N_MISC_CNTL__MASTER_XNACK_TIMER_INC__SHIFT 0x0
6250#define RMI_UTC_XNACK_N_MISC_CNTL__IND_XNACK_TIMER_START_VALUE__SHIFT 0x8
6251#define RMI_UTC_XNACK_N_MISC_CNTL__UTCL1_PERM_MODE__SHIFT 0xc
6252#define RMI_UTC_XNACK_N_MISC_CNTL__CP_VMID_RESET_REQUEST_DISABLE__SHIFT 0xd
6253#define RMI_UTC_XNACK_N_MISC_CNTL__MASTER_XNACK_TIMER_INC_MASK 0x000000FFL
6254#define RMI_UTC_XNACK_N_MISC_CNTL__IND_XNACK_TIMER_START_VALUE_MASK 0x00000F00L
6255#define RMI_UTC_XNACK_N_MISC_CNTL__UTCL1_PERM_MODE_MASK 0x00001000L
6256#define RMI_UTC_XNACK_N_MISC_CNTL__CP_VMID_RESET_REQUEST_DISABLE_MASK 0x00002000L
6257//RMI_DEMUX_CNTL
6258#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL__SHIFT 0x0
6259#define RMI_DEMUX_CNTL__DEMUX_ARB0_BREAK_LOB_ON_IDLEIN__SHIFT 0x1
6260#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_OVERRIDE__SHIFT 0x4
6261#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_START_VALUE__SHIFT 0x6
6262#define RMI_DEMUX_CNTL__DEMUX_ARB0_MODE__SHIFT 0xe
6263#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL__SHIFT 0x10
6264#define RMI_DEMUX_CNTL__DEMUX_ARB1_BREAK_LOB_ON_IDLEIN__SHIFT 0x11
6265#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_OVERRIDE__SHIFT 0x14
6266#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_START_VALUE__SHIFT 0x16
6267#define RMI_DEMUX_CNTL__DEMUX_ARB1_MODE__SHIFT 0x1e
6268#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_MASK 0x00000001L
6269#define RMI_DEMUX_CNTL__DEMUX_ARB0_BREAK_LOB_ON_IDLEIN_MASK 0x00000002L
6270#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_OVERRIDE_MASK 0x00000030L
6271#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_START_VALUE_MASK 0x00003FC0L
6272#define RMI_DEMUX_CNTL__DEMUX_ARB0_MODE_MASK 0x0000C000L
6273#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_MASK 0x00010000L
6274#define RMI_DEMUX_CNTL__DEMUX_ARB1_BREAK_LOB_ON_IDLEIN_MASK 0x00020000L
6275#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_OVERRIDE_MASK 0x00300000L
6276#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_START_VALUE_MASK 0x3FC00000L
6277#define RMI_DEMUX_CNTL__DEMUX_ARB1_MODE_MASK 0xC0000000L
6278//RMI_UTCL1_CNTL1
6279#define RMI_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0
6280#define RMI_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT 0x1
6281#define RMI_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2
6282#define RMI_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3
6283#define RMI_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5
6284#define RMI_UTCL1_CNTL1__CLIENTID__SHIFT 0x7
6285#define RMI_UTCL1_CNTL1__USERVM_DIS__SHIFT 0x10
6286#define RMI_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11
6287#define RMI_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12
6288#define RMI_UTCL1_CNTL1__REG_INV_VMID__SHIFT 0x13
6289#define RMI_UTCL1_CNTL1__REG_INV_ALL_VMID__SHIFT 0x17
6290#define RMI_UTCL1_CNTL1__REG_INV_TOGGLE__SHIFT 0x18
6291#define RMI_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT 0x19
6292#define RMI_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a
6293#define RMI_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b
6294#define RMI_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c
6295#define RMI_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e
6296#define RMI_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L
6297#define RMI_UTCL1_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L
6298#define RMI_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L
6299#define RMI_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L
6300#define RMI_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L
6301#define RMI_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L
6302#define RMI_UTCL1_CNTL1__USERVM_DIS_MASK 0x00010000L
6303#define RMI_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L
6304#define RMI_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L
6305#define RMI_UTCL1_CNTL1__REG_INV_VMID_MASK 0x00780000L
6306#define RMI_UTCL1_CNTL1__REG_INV_ALL_VMID_MASK 0x00800000L
6307#define RMI_UTCL1_CNTL1__REG_INV_TOGGLE_MASK 0x01000000L
6308#define RMI_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK 0x02000000L
6309#define RMI_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L
6310#define RMI_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L
6311#define RMI_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L
6312#define RMI_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L
6313//RMI_UTCL1_CNTL2
6314#define RMI_UTCL1_CNTL2__UTC_SPARE__SHIFT 0x0
6315#define RMI_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9
6316#define RMI_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa
6317#define RMI_UTCL1_CNTL2__DIS_EDC__SHIFT 0xb
6318#define RMI_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc
6319#define RMI_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT 0xd
6320#define RMI_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe
6321#define RMI_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf
6322#define RMI_UTCL1_CNTL2__UTCL1_ARB_BURST_MODE__SHIFT 0x10
6323#define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_RD_WR__SHIFT 0x12
6324#define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_RD_WR__SHIFT 0x13
6325#define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_VMID__SHIFT 0x14
6326#define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_VMID__SHIFT 0x15
6327#define RMI_UTCL1_CNTL2__UTCL1_DIS_DUAL_L2_REQ__SHIFT 0x19
6328#define RMI_UTCL1_CNTL2__UTCL1_FORCE_FRAG_2M_TO_64K__SHIFT 0x1a
6329#define RMI_UTCL1_CNTL2__UTC_SPARE_MASK 0x000000FFL
6330#define RMI_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L
6331#define RMI_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L
6332#define RMI_UTCL1_CNTL2__DIS_EDC_MASK 0x00000800L
6333#define RMI_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L
6334#define RMI_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK 0x00002000L
6335#define RMI_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L
6336#define RMI_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L
6337#define RMI_UTCL1_CNTL2__UTCL1_ARB_BURST_MODE_MASK 0x00030000L
6338#define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L
6339#define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_RD_WR_MASK 0x00080000L
6340#define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_VMID_MASK 0x00100000L
6341#define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_VMID_MASK 0x01E00000L
6342#define RMI_UTCL1_CNTL2__UTCL1_DIS_DUAL_L2_REQ_MASK 0x02000000L
6343#define RMI_UTCL1_CNTL2__UTCL1_FORCE_FRAG_2M_TO_64K_MASK 0x04000000L
6344//RMI_UTC_UNIT_CONFIG
6345//RMI_TCIW_FORMATTER0_CNTL
6346#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_OVERRIDE__SHIFT 0x0
6347#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_TIME_OUT_WINDOW__SHIFT 0x1
6348#define RMI_TCIW_FORMATTER0_CNTL__TCIW0_MAX_ALLOWED_INFLIGHT_REQ__SHIFT 0x9
6349#define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA__SHIFT 0x13
6350#define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA_UPDATE__SHIFT 0x1b
6351#define RMI_TCIW_FORMATTER0_CNTL__TCIW0_REQ_SAFE_MODE__SHIFT 0x1c
6352#define RMI_TCIW_FORMATTER0_CNTL__RMI_IN0_REORDER_DIS__SHIFT 0x1d
6353#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_AT_LAST_OF_BURST__SHIFT 0x1e
6354#define RMI_TCIW_FORMATTER0_CNTL__ALL_FAULT_RET0_DATA__SHIFT 0x1f
6355#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_OVERRIDE_MASK 0x00000001L
6356#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_TIME_OUT_WINDOW_MASK 0x000001FEL
6357#define RMI_TCIW_FORMATTER0_CNTL__TCIW0_MAX_ALLOWED_INFLIGHT_REQ_MASK 0x0007FE00L
6358#define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA_MASK 0x07F80000L
6359#define RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA_UPDATE_MASK 0x08000000L
6360#define RMI_TCIW_FORMATTER0_CNTL__TCIW0_REQ_SAFE_MODE_MASK 0x10000000L
6361#define RMI_TCIW_FORMATTER0_CNTL__RMI_IN0_REORDER_DIS_MASK 0x20000000L
6362#define RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_AT_LAST_OF_BURST_MASK 0x40000000L
6363#define RMI_TCIW_FORMATTER0_CNTL__ALL_FAULT_RET0_DATA_MASK 0x80000000L
6364//RMI_TCIW_FORMATTER1_CNTL
6365#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_OVERRIDE__SHIFT 0x0
6366#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_TIME_OUT_WINDOW__SHIFT 0x1
6367#define RMI_TCIW_FORMATTER1_CNTL__TCIW1_MAX_ALLOWED_INFLIGHT_REQ__SHIFT 0x9
6368#define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA__SHIFT 0x13
6369#define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA_UPDATE__SHIFT 0x1b
6370#define RMI_TCIW_FORMATTER1_CNTL__TCIW1_REQ_SAFE_MODE__SHIFT 0x1c
6371#define RMI_TCIW_FORMATTER1_CNTL__RMI_IN1_REORDER_DIS__SHIFT 0x1d
6372#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_AT_LAST_OF_BURST__SHIFT 0x1e
6373#define RMI_TCIW_FORMATTER1_CNTL__ALL_FAULT_RET1_DATA__SHIFT 0x1f
6374#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_OVERRIDE_MASK 0x00000001L
6375#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_TIME_OUT_WINDOW_MASK 0x000001FEL
6376#define RMI_TCIW_FORMATTER1_CNTL__TCIW1_MAX_ALLOWED_INFLIGHT_REQ_MASK 0x0007FE00L
6377#define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA_MASK 0x07F80000L
6378#define RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA_UPDATE_MASK 0x08000000L
6379#define RMI_TCIW_FORMATTER1_CNTL__TCIW1_REQ_SAFE_MODE_MASK 0x10000000L
6380#define RMI_TCIW_FORMATTER1_CNTL__RMI_IN1_REORDER_DIS_MASK 0x20000000L
6381#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_AT_LAST_OF_BURST_MASK 0x40000000L
6382#define RMI_TCIW_FORMATTER1_CNTL__ALL_FAULT_RET1_DATA_MASK 0x80000000L
6383//RMI_SCOREBOARD_CNTL
6384#define RMI_SCOREBOARD_CNTL__COMPLETE_RB0_FLUSH__SHIFT 0x0
6385#define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB0__SHIFT 0x1
6386#define RMI_SCOREBOARD_CNTL__COMPLETE_RB1_FLUSH__SHIFT 0x2
6387#define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB1__SHIFT 0x3
6388#define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB1__SHIFT 0x4
6389#define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_EN__SHIFT 0x5
6390#define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_VALUE__SHIFT 0x6
6391#define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB0__SHIFT 0x7
6392#define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_EN__SHIFT 0x8
6393#define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_TIMER_START_VALUE__SHIFT 0x9
6394#define RMI_SCOREBOARD_CNTL__COMPLETE_RB0_FLUSH_MASK 0x00000001L
6395#define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB0_MASK 0x00000002L
6396#define RMI_SCOREBOARD_CNTL__COMPLETE_RB1_FLUSH_MASK 0x00000004L
6397#define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB1_MASK 0x00000008L
6398#define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB1_MASK 0x00000010L
6399#define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_EN_MASK 0x00000020L
6400#define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_VALUE_MASK 0x00000040L
6401#define RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB0_MASK 0x00000080L
6402#define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_EN_MASK 0x00000100L
6403#define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_TIMER_START_VALUE_MASK 0x001FFE00L
6404//RMI_SCOREBOARD_STATUS0
6405#define RMI_SCOREBOARD_STATUS0__CURRENT_SESSION_ID__SHIFT 0x0
6406#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_IN_PROG__SHIFT 0x1
6407#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_REQ_VMID__SHIFT 0x2
6408#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_UTC_DONE__SHIFT 0x12
6409#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_DONE__SHIFT 0x13
6410#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_FLUSH_TYPE__SHIFT 0x14
6411#define RMI_SCOREBOARD_STATUS0__FORCE_VMID_INV_DONE__SHIFT 0x15
6412#define RMI_SCOREBOARD_STATUS0__CURRENT_SESSION_ID_MASK 0x00000001L
6413#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_IN_PROG_MASK 0x00000002L
6414#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_REQ_VMID_MASK 0x0003FFFCL
6415#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_UTC_DONE_MASK 0x00040000L
6416#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_DONE_MASK 0x00080000L
6417#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_FLUSH_TYPE_MASK 0x00100000L
6418#define RMI_SCOREBOARD_STATUS0__FORCE_VMID_INV_DONE_MASK 0x00200000L
6419//RMI_SCOREBOARD_STATUS1
6420#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB0__SHIFT 0x0
6421#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB0__SHIFT 0xc
6422#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB0__SHIFT 0xd
6423#define RMI_SCOREBOARD_STATUS1__MULTI_VMID_INVAL_FROM_CP_DETECTED__SHIFT 0xe
6424#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB1__SHIFT 0xf
6425#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB1__SHIFT 0x1b
6426#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB1__SHIFT 0x1c
6427#define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB1__SHIFT 0x1d
6428#define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB0__SHIFT 0x1e
6429#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB0_MASK 0x00000FFFL
6430#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB0_MASK 0x00001000L
6431#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB0_MASK 0x00002000L
6432#define RMI_SCOREBOARD_STATUS1__MULTI_VMID_INVAL_FROM_CP_DETECTED_MASK 0x00004000L
6433#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB1_MASK 0x07FF8000L
6434#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB1_MASK 0x08000000L
6435#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB1_MASK 0x10000000L
6436#define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB1_MASK 0x20000000L
6437#define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB0_MASK 0x40000000L
6438//RMI_SCOREBOARD_STATUS2
6439#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB0__SHIFT 0x0
6440#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB0__SHIFT 0xc
6441#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB1__SHIFT 0xd
6442#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB1__SHIFT 0x19
6443#define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB1__SHIFT 0x1a
6444#define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB0__SHIFT 0x1b
6445#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB0__SHIFT 0x1c
6446#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB1__SHIFT 0x1d
6447#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB0__SHIFT 0x1e
6448#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB1__SHIFT 0x1f
6449#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB0_MASK 0x00000FFFL
6450#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB0_MASK 0x00001000L
6451#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB1_MASK 0x01FFE000L
6452#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB1_MASK 0x02000000L
6453#define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB1_MASK 0x04000000L
6454#define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB0_MASK 0x08000000L
6455#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB0_MASK 0x10000000L
6456#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB1_MASK 0x20000000L
6457#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB0_MASK 0x40000000L
6458#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB1_MASK 0x80000000L
6459//RMI_XBAR_ARBITER_CONFIG
6460#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_MODE__SHIFT 0x0
6461#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_WEIGHTEDRR__SHIFT 0x2
6462#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL__SHIFT 0x3
6463#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_IDLEIN__SHIFT 0x4
6464#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_OVERRIDE__SHIFT 0x6
6465#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_START_VALUE__SHIFT 0x8
6466#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_MODE__SHIFT 0x10
6467#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_WEIGHTEDRR__SHIFT 0x12
6468#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL__SHIFT 0x13
6469#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_IDLEIN__SHIFT 0x14
6470#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_OVERRIDE__SHIFT 0x16
6471#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_START_VALUE__SHIFT 0x18
6472#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_MODE_MASK 0x00000003L
6473#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_WEIGHTEDRR_MASK 0x00000004L
6474#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_MASK 0x00000008L
6475#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_IDLEIN_MASK 0x00000010L
6476#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_OVERRIDE_MASK 0x000000C0L
6477#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_START_VALUE_MASK 0x0000FF00L
6478#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_MODE_MASK 0x00030000L
6479#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_WEIGHTEDRR_MASK 0x00040000L
6480#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_MASK 0x00080000L
6481#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_IDLEIN_MASK 0x00100000L
6482#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_OVERRIDE_MASK 0x00C00000L
6483#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_START_VALUE_MASK 0xFF000000L
6484//RMI_XBAR_ARBITER_CONFIG_1
6485#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_RD__SHIFT 0x0
6486#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_WR__SHIFT 0x8
6487#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_RD__SHIFT 0x10
6488#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_WR__SHIFT 0x18
6489#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_RD_MASK 0x000000FFL
6490#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_WR_MASK 0x0000FF00L
6491#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_RD_MASK 0x00FF0000L
6492#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_WR_MASK 0xFF000000L
6493//RMI_CLOCK_CNTRL
6494#define RMI_CLOCK_CNTRL__DYN_CLK_RB0_BUSY_MASK__SHIFT 0x0
6495#define RMI_CLOCK_CNTRL__DYN_CLK_CMN_BUSY_MASK__SHIFT 0x5
6496#define RMI_CLOCK_CNTRL__DYN_CLK_RB0_WAKEUP_MASK__SHIFT 0xa
6497#define RMI_CLOCK_CNTRL__DYN_CLK_CMN_WAKEUP_MASK__SHIFT 0xf
6498#define RMI_CLOCK_CNTRL__DYN_CLK_RB1_BUSY_MASK__SHIFT 0x14
6499#define RMI_CLOCK_CNTRL__DYN_CLK_RB1_WAKEUP_MASK__SHIFT 0x19
6500#define RMI_CLOCK_CNTRL__DYN_CLK_RB0_BUSY_MASK_MASK 0x0000001FL
6501#define RMI_CLOCK_CNTRL__DYN_CLK_CMN_BUSY_MASK_MASK 0x000003E0L
6502#define RMI_CLOCK_CNTRL__DYN_CLK_RB0_WAKEUP_MASK_MASK 0x00007C00L
6503#define RMI_CLOCK_CNTRL__DYN_CLK_CMN_WAKEUP_MASK_MASK 0x000F8000L
6504#define RMI_CLOCK_CNTRL__DYN_CLK_RB1_BUSY_MASK_MASK 0x01F00000L
6505#define RMI_CLOCK_CNTRL__DYN_CLK_RB1_WAKEUP_MASK_MASK 0x3E000000L
6506//RMI_UTCL1_STATUS
6507#define RMI_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0
6508#define RMI_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1
6509#define RMI_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2
6510#define RMI_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L
6511#define RMI_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L
6512#define RMI_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L
6513//RMI_XNACK_DEBUG
6514#define RMI_XNACK_DEBUG__XNACK_PER_VMID__SHIFT 0x0
6515#define RMI_XNACK_DEBUG__XNACK_PER_VMID_MASK 0x0000FFFFL
6516//RMI_SPARE
6517#define RMI_SPARE__RMI_ARBITER_STALL_TIMER_ENABLED_ALLOW_STREAMING__SHIFT 0x0
6518#define RMI_SPARE__SPARE_BIT_1__SHIFT 0x1
6519#define RMI_SPARE__SPARE_BIT_2__SHIFT 0x2
6520#define RMI_SPARE__SPARE_BIT_3__SHIFT 0x3
6521#define RMI_SPARE__SPARE_BIT_4__SHIFT 0x4
6522#define RMI_SPARE__SPARE_BIT_5__SHIFT 0x5
6523#define RMI_SPARE__SPARE_BIT_6__SHIFT 0x6
6524#define RMI_SPARE__SPARE_BIT_7__SHIFT 0x7
6525#define RMI_SPARE__SPARE_BIT_8_0__SHIFT 0x8
6526#define RMI_SPARE__SPARE_BIT_16_0__SHIFT 0x10
6527#define RMI_SPARE__RMI_ARBITER_STALL_TIMER_ENABLED_ALLOW_STREAMING_MASK 0x00000001L
6528#define RMI_SPARE__SPARE_BIT_1_MASK 0x00000002L
6529#define RMI_SPARE__SPARE_BIT_2_MASK 0x00000004L
6530#define RMI_SPARE__SPARE_BIT_3_MASK 0x00000008L
6531#define RMI_SPARE__SPARE_BIT_4_MASK 0x00000010L
6532#define RMI_SPARE__SPARE_BIT_5_MASK 0x00000020L
6533#define RMI_SPARE__SPARE_BIT_6_MASK 0x00000040L
6534#define RMI_SPARE__SPARE_BIT_7_MASK 0x00000080L
6535#define RMI_SPARE__SPARE_BIT_8_0_MASK 0x0000FF00L
6536#define RMI_SPARE__SPARE_BIT_16_0_MASK 0xFFFF0000L
6537//RMI_SPARE_1
6538#define RMI_SPARE_1__SPARE_BIT_8__SHIFT 0x0
6539#define RMI_SPARE_1__SPARE_BIT_9__SHIFT 0x1
6540#define RMI_SPARE_1__SPARE_BIT_10__SHIFT 0x2
6541#define RMI_SPARE_1__SPARE_BIT_11__SHIFT 0x3
6542#define RMI_SPARE_1__SPARE_BIT_12__SHIFT 0x4
6543#define RMI_SPARE_1__SPARE_BIT_13__SHIFT 0x5
6544#define RMI_SPARE_1__SPARE_BIT_14__SHIFT 0x6
6545#define RMI_SPARE_1__SPARE_BIT_15__SHIFT 0x7
6546#define RMI_SPARE_1__SPARE_BIT_8_1__SHIFT 0x8
6547#define RMI_SPARE_1__SPARE_BIT_16_1__SHIFT 0x10
6548#define RMI_SPARE_1__SPARE_BIT_8_MASK 0x00000001L
6549#define RMI_SPARE_1__SPARE_BIT_9_MASK 0x00000002L
6550#define RMI_SPARE_1__SPARE_BIT_10_MASK 0x00000004L
6551#define RMI_SPARE_1__SPARE_BIT_11_MASK 0x00000008L
6552#define RMI_SPARE_1__SPARE_BIT_12_MASK 0x00000010L
6553#define RMI_SPARE_1__SPARE_BIT_13_MASK 0x00000020L
6554#define RMI_SPARE_1__SPARE_BIT_14_MASK 0x00000040L
6555#define RMI_SPARE_1__SPARE_BIT_15_MASK 0x00000080L
6556#define RMI_SPARE_1__SPARE_BIT_8_1_MASK 0x0000FF00L
6557#define RMI_SPARE_1__SPARE_BIT_16_1_MASK 0xFFFF0000L
6558//RMI_SPARE_2
6559#define RMI_SPARE_2__SPARE_BIT_16__SHIFT 0x0
6560#define RMI_SPARE_2__SPARE_BIT_17__SHIFT 0x1
6561#define RMI_SPARE_2__SPARE_BIT_18__SHIFT 0x2
6562#define RMI_SPARE_2__SPARE_BIT_19__SHIFT 0x3
6563#define RMI_SPARE_2__SPARE_BIT_20__SHIFT 0x4
6564#define RMI_SPARE_2__SPARE_BIT_21__SHIFT 0x5
6565#define RMI_SPARE_2__SPARE_BIT_22__SHIFT 0x6
6566#define RMI_SPARE_2__SPARE_BIT_23__SHIFT 0x7
6567#define RMI_SPARE_2__SPARE_BIT_4_0__SHIFT 0x8
6568#define RMI_SPARE_2__SPARE_BIT_4_1__SHIFT 0xc
6569#define RMI_SPARE_2__SPARE_BIT_8_2__SHIFT 0x10
6570#define RMI_SPARE_2__SPARE_BIT_8_3__SHIFT 0x18
6571#define RMI_SPARE_2__SPARE_BIT_16_MASK 0x00000001L
6572#define RMI_SPARE_2__SPARE_BIT_17_MASK 0x00000002L
6573#define RMI_SPARE_2__SPARE_BIT_18_MASK 0x00000004L
6574#define RMI_SPARE_2__SPARE_BIT_19_MASK 0x00000008L
6575#define RMI_SPARE_2__SPARE_BIT_20_MASK 0x00000010L
6576#define RMI_SPARE_2__SPARE_BIT_21_MASK 0x00000020L
6577#define RMI_SPARE_2__SPARE_BIT_22_MASK 0x00000040L
6578#define RMI_SPARE_2__SPARE_BIT_23_MASK 0x00000080L
6579#define RMI_SPARE_2__SPARE_BIT_4_0_MASK 0x00000F00L
6580#define RMI_SPARE_2__SPARE_BIT_4_1_MASK 0x0000F000L
6581#define RMI_SPARE_2__SPARE_BIT_8_2_MASK 0x00FF0000L
6582#define RMI_SPARE_2__SPARE_BIT_8_3_MASK 0xFF000000L
6583
6584
6585// addressBlock: gc_utcl2_atcl2dec
6586//ATC_L2_CNTL
6587#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT 0x0
6588#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT 0x3
6589#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0x6
6590#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0x7
6591#define ATC_L2_CNTL__CACHE_INVALIDATE_MODE__SHIFT 0x8
6592#define ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb
6593#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK 0x00000003L
6594#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK 0x00000018L
6595#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x00000040L
6596#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x00000080L
6597#define ATC_L2_CNTL__CACHE_INVALIDATE_MODE_MASK 0x00000700L
6598#define ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L
6599//ATC_L2_CNTL2
6600#define ATC_L2_CNTL2__BANK_SELECT__SHIFT 0x0
6601#define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE__SHIFT 0x6
6602#define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x8
6603#define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS__SHIFT 0x9
6604#define ATC_L2_CNTL2__L2_CACHE_VMID_MODE__SHIFT 0xc
6605#define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0xf
6606#define ATC_L2_CNTL2__BANK_SELECT_MASK 0x0000003FL
6607#define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L
6608#define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000100L
6609#define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS_MASK 0x00000E00L
6610#define ATC_L2_CNTL2__L2_CACHE_VMID_MODE_MASK 0x00007000L
6611#define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x001F8000L
6612//ATC_L2_CACHE_DATA0
6613#define ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID__SHIFT 0x0
6614#define ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID__SHIFT 0x1
6615#define ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES__SHIFT 0x2
6616#define ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH__SHIFT 0x17
6617#define ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID_MASK 0x00000001L
6618#define ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID_MASK 0x00000002L
6619#define ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES_MASK 0x007FFFFCL
6620#define ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH_MASK 0x07800000L
6621//ATC_L2_CACHE_DATA1
6622#define ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW__SHIFT 0x0
6623#define ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW_MASK 0xFFFFFFFFL
6624//ATC_L2_CACHE_DATA2
6625#define ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS__SHIFT 0x0
6626#define ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_MASK 0xFFFFFFFFL
6627//ATC_L2_CNTL3
6628#define ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST__SHIFT 0x0
6629#define ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1__SHIFT 0x3
6630#define ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST_MASK 0x00000007L
6631#define ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1_MASK 0x000001F8L
6632//ATC_L2_STATUS
6633#define ATC_L2_STATUS__BUSY__SHIFT 0x0
6634#define ATC_L2_STATUS__PARITY_ERROR_INFO__SHIFT 0x1
6635#define ATC_L2_STATUS__BUSY_MASK 0x00000001L
6636#define ATC_L2_STATUS__PARITY_ERROR_INFO_MASK 0x3FFFFFFEL
6637//ATC_L2_STATUS2
6638#define ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO__SHIFT 0x0
6639#define ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO__SHIFT 0x8
6640#define ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO_MASK 0x000000FFL
6641#define ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO_MASK 0x0000FF00L
6642//ATC_L2_MISC_CG
6643#define ATC_L2_MISC_CG__OFFDLY__SHIFT 0x6
6644#define ATC_L2_MISC_CG__ENABLE__SHIFT 0x12
6645#define ATC_L2_MISC_CG__MEM_LS_ENABLE__SHIFT 0x13
6646#define ATC_L2_MISC_CG__OFFDLY_MASK 0x00000FC0L
6647#define ATC_L2_MISC_CG__ENABLE_MASK 0x00040000L
6648#define ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK 0x00080000L
6649//ATC_L2_MEM_POWER_LS
6650#define ATC_L2_MEM_POWER_LS__LS_SETUP__SHIFT 0x0
6651#define ATC_L2_MEM_POWER_LS__LS_HOLD__SHIFT 0x6
6652#define ATC_L2_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL
6653#define ATC_L2_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L
6654//ATC_L2_CGTT_CLK_CTRL
6655#define ATC_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0
6656#define ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
6657#define ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf
6658#define ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10
6659#define ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18
6660#define ATC_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL
6661#define ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L
6662#define ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L
6663#define ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L
6664#define ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L
6665
6666// addressBlock: gc_utcl2_vml2pfdec
6667//VM_L2_CNTL
6668#define VM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x0
6669#define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT 0x1
6670#define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT 0x2
6671#define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT 0x4
6672#define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT 0x8
6673#define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x9
6674#define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa
6675#define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb
6676#define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT 0xc
6677#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf
6678#define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT 0x12
6679#define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT 0x13
6680#define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT 0x15
6681#define VM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE__SHIFT 0x1a
6682#define VM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x00000001L
6683#define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK 0x00000002L
6684#define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK 0x0000000CL
6685#define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK 0x00000030L
6686#define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK 0x00000100L
6687#define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000200L
6688#define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000400L
6689#define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L
6690#define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK 0x00007000L
6691#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x00038000L
6692#define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK 0x00040000L
6693#define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK 0x00180000L
6694#define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK 0x03E00000L
6695#define VM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE_MASK 0x0C000000L
6696//VM_L2_CNTL2
6697#define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT 0x0
6698#define VM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT 0x1
6699#define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x15
6700#define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT 0x16
6701#define VM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE__SHIFT 0x17
6702#define VM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT 0x1a
6703#define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 0x1c
6704#define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK 0x00000001L
6705#define VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK 0x00000002L
6706#define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x00200000L
6707#define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK 0x00400000L
6708#define VM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE_MASK 0x03800000L
6709#define VM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK 0x0C000000L
6710#define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK 0x70000000L
6711//VM_L2_CNTL3
6712#define VM_L2_CNTL3__BANK_SELECT__SHIFT 0x0
6713#define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT 0x6
6714#define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x8
6715#define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0xf
6716#define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT 0x14
6717#define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 0x15
6718#define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT 0x18
6719#define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT 0x1c
6720#define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT 0x1d
6721#define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT 0x1e
6722#define VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT 0x1f
6723#define VM_L2_CNTL3__BANK_SELECT_MASK 0x0000003FL
6724#define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L
6725#define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x00001F00L
6726#define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000F8000L
6727#define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK 0x00100000L
6728#define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 0x00E00000L
6729#define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 0x0F000000L
6730#define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK 0x10000000L
6731#define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK 0x20000000L
6732#define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK 0x40000000L
6733#define VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK 0x80000000L
6734//VM_L2_STATUS
6735#define VM_L2_STATUS__L2_BUSY__SHIFT 0x0
6736#define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT 0x1
6737#define VM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS__SHIFT 0x11
6738#define VM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS__SHIFT 0x12
6739#define VM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS__SHIFT 0x13
6740#define VM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS__SHIFT 0x14
6741#define VM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS__SHIFT 0x15
6742#define VM_L2_STATUS__L2_BUSY_MASK 0x00000001L
6743#define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK 0x0001FFFEL
6744#define VM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS_MASK 0x00020000L
6745#define VM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS_MASK 0x00040000L
6746#define VM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS_MASK 0x00080000L
6747#define VM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS_MASK 0x00100000L
6748#define VM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS_MASK 0x00200000L
6749//VM_DUMMY_PAGE_FAULT_CNTL
6750#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT 0x0
6751#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT 0x1
6752#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS__SHIFT 0x2
6753#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK 0x00000001L
6754#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK 0x00000002L
6755#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS_MASK 0x000000FCL
6756//VM_DUMMY_PAGE_FAULT_ADDR_LO32
6757#define VM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32__SHIFT 0x0
6758#define VM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL
6759//VM_DUMMY_PAGE_FAULT_ADDR_HI32
6760#define VM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4__SHIFT 0x0
6761#define VM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4_MASK 0x0000000FL
6762//VM_L2_PROTECTION_FAULT_CNTL
6763#define VM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0
6764#define VM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x1
6765#define VM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x2
6766#define VM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x3
6767#define VM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4
6768#define VM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x5
6769#define VM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x6
6770#define VM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7
6771#define VM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x8
6772#define VM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x9
6773#define VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
6774#define VM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb
6775#define VM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc
6776#define VM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0xd
6777#define VM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x1d
6778#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT__SHIFT 0x1e
6779#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT__SHIFT 0x1f
6780#define VM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00000001L
6781#define VM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x00000002L
6782#define VM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000004L
6783#define VM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000008L
6784#define VM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000010L
6785#define VM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000020L
6786#define VM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000040L
6787#define VM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000080L
6788#define VM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000100L
6789#define VM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000200L
6790#define VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L
6791#define VM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L
6792#define VM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L
6793#define VM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x1FFFE000L
6794#define VM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x20000000L
6795#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT_MASK 0x40000000L
6796#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT_MASK 0x80000000L
6797//VM_L2_PROTECTION_FAULT_CNTL2
6798#define VM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x0
6799#define VM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x10
6800#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE__SHIFT 0x11
6801#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY__SHIFT 0x12
6802#define VM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT__SHIFT 0x13
6803#define VM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x0000FFFFL
6804#define VM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x00010000L
6805#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_MASK 0x00020000L
6806#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY_MASK 0x00040000L
6807#define VM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT_MASK 0x00080000L
6808//VM_L2_PROTECTION_FAULT_MM_CNTL3
6809#define VM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0
6810#define VM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL
6811//VM_L2_PROTECTION_FAULT_MM_CNTL4
6812#define VM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0
6813#define VM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL
6814//VM_L2_PROTECTION_FAULT_STATUS
6815#define VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS__SHIFT 0x0
6816#define VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR__SHIFT 0x1
6817#define VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS__SHIFT 0x4
6818#define VM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR__SHIFT 0x8
6819#define VM_L2_PROTECTION_FAULT_STATUS__CID__SHIFT 0x9
6820#define VM_L2_PROTECTION_FAULT_STATUS__RW__SHIFT 0x12
6821#define VM_L2_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT 0x13
6822#define VM_L2_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x14
6823#define VM_L2_PROTECTION_FAULT_STATUS__VF__SHIFT 0x18
6824#define VM_L2_PROTECTION_FAULT_STATUS__VFID__SHIFT 0x19
6825#define VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS_MASK 0x00000001L
6826#define VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR_MASK 0x0000000EL
6827#define VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS_MASK 0x000000F0L
6828#define VM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR_MASK 0x00000100L
6829#define VM_L2_PROTECTION_FAULT_STATUS__CID_MASK 0x0003FE00L
6830#define VM_L2_PROTECTION_FAULT_STATUS__RW_MASK 0x00040000L
6831#define VM_L2_PROTECTION_FAULT_STATUS__ATOMIC_MASK 0x00080000L
6832#define VM_L2_PROTECTION_FAULT_STATUS__VMID_MASK 0x00F00000L
6833#define VM_L2_PROTECTION_FAULT_STATUS__VF_MASK 0x01000000L
6834#define VM_L2_PROTECTION_FAULT_STATUS__VFID_MASK 0x1E000000L
6835//VM_L2_PROTECTION_FAULT_ADDR_LO32
6836#define VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT 0x0
6837#define VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL
6838//VM_L2_PROTECTION_FAULT_ADDR_HI32
6839#define VM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT 0x0
6840#define VM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK 0x0000000FL
6841//VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32
6842#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32__SHIFT 0x0
6843#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL
6844//VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32
6845#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4__SHIFT 0x0
6846#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4_MASK 0x0000000FL
6847//VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32
6848#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
6849#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
6850//VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32
6851#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
6852#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
6853//VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32
6854#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0
6855#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL
6856//VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32
6857#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0
6858#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL
6859//VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32
6860#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32__SHIFT 0x0
6861#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32_MASK 0xFFFFFFFFL
6862//VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32
6863#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4__SHIFT 0x0
6864#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4_MASK 0x0000000FL
6865//VM_L2_CNTL4
6866#define VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT 0x0
6867#define VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL__SHIFT 0x6
6868#define VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL__SHIFT 0x7
6869#define VM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x8
6870#define VM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x12
6871#define VM_L2_CNTL4__BPM_CGCGLS_OVERRIDE__SHIFT 0x1c
6872#define VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK 0x0000003FL
6873#define VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL_MASK 0x00000040L
6874#define VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL_MASK 0x00000080L
6875#define VM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0003FF00L
6876#define VM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0FFC0000L
6877#define VM_L2_CNTL4__BPM_CGCGLS_OVERRIDE_MASK 0x10000000L
6878//VM_L2_MM_GROUP_RT_CLASSES
6879#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS__SHIFT 0x0
6880#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS__SHIFT 0x1
6881#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS__SHIFT 0x2
6882#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS__SHIFT 0x3
6883#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS__SHIFT 0x4
6884#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS__SHIFT 0x5
6885#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS__SHIFT 0x6
6886#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS__SHIFT 0x7
6887#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS__SHIFT 0x8
6888#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS__SHIFT 0x9
6889#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS__SHIFT 0xa
6890#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS__SHIFT 0xb
6891#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS__SHIFT 0xc
6892#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS__SHIFT 0xd
6893#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS__SHIFT 0xe
6894#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS__SHIFT 0xf
6895#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS__SHIFT 0x10
6896#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS__SHIFT 0x11
6897#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS__SHIFT 0x12
6898#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS__SHIFT 0x13
6899#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS__SHIFT 0x14
6900#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS__SHIFT 0x15
6901#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS__SHIFT 0x16
6902#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS__SHIFT 0x17
6903#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS__SHIFT 0x18
6904#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS__SHIFT 0x19
6905#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS__SHIFT 0x1a
6906#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS__SHIFT 0x1b
6907#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS__SHIFT 0x1c
6908#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS__SHIFT 0x1d
6909#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS__SHIFT 0x1e
6910#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS__SHIFT 0x1f
6911#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS_MASK 0x00000001L
6912#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS_MASK 0x00000002L
6913#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS_MASK 0x00000004L
6914#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS_MASK 0x00000008L
6915#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS_MASK 0x00000010L
6916#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS_MASK 0x00000020L
6917#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS_MASK 0x00000040L
6918#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS_MASK 0x00000080L
6919#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS_MASK 0x00000100L
6920#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS_MASK 0x00000200L
6921#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS_MASK 0x00000400L
6922#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS_MASK 0x00000800L
6923#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS_MASK 0x00001000L
6924#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS_MASK 0x00002000L
6925#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS_MASK 0x00004000L
6926#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS_MASK 0x00008000L
6927#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS_MASK 0x00010000L
6928#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS_MASK 0x00020000L
6929#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS_MASK 0x00040000L
6930#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS_MASK 0x00080000L
6931#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS_MASK 0x00100000L
6932#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS_MASK 0x00200000L
6933#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS_MASK 0x00400000L
6934#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS_MASK 0x00800000L
6935#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS_MASK 0x01000000L
6936#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS_MASK 0x02000000L
6937#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS_MASK 0x04000000L
6938#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS_MASK 0x08000000L
6939#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS_MASK 0x10000000L
6940#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS_MASK 0x20000000L
6941#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS_MASK 0x40000000L
6942#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS_MASK 0x80000000L
6943//VM_L2_BANK_SELECT_RESERVED_CID
6944#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID__SHIFT 0x0
6945#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa
6946#define VM_L2_BANK_SELECT_RESERVED_CID__ENABLE__SHIFT 0x14
6947#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18
6948#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19
6949#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL
6950#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L
6951#define VM_L2_BANK_SELECT_RESERVED_CID__ENABLE_MASK 0x00100000L
6952#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L
6953#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L
6954//VM_L2_BANK_SELECT_RESERVED_CID2
6955#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID__SHIFT 0x0
6956#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa
6957#define VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE__SHIFT 0x14
6958#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18
6959#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19
6960#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL
6961#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L
6962#define VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE_MASK 0x00100000L
6963#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L
6964#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L
6965//VM_L2_CACHE_PARITY_CNTL
6966#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES__SHIFT 0x0
6967#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES__SHIFT 0x1
6968#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES__SHIFT 0x2
6969#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE__SHIFT 0x3