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1/*
2 * GFX_7_2 Register documentation
3 *
4 * Copyright (C) 2014 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24#ifndef GFX_7_2_SH_MASK_H
25#define GFX_7_2_SH_MASK_H
26
27#define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28#define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29#define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30#define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31#define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32#define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33#define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34#define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35#define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x8
36#define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x3
37#define CB_COLOR_CONTROL__MODE_MASK 0x70
38#define CB_COLOR_CONTROL__MODE__SHIFT 0x4
39#define CB_COLOR_CONTROL__ROP3_MASK 0xff0000
40#define CB_COLOR_CONTROL__ROP3__SHIFT 0x10
41#define CB_BLEND0_CONTROL__COLOR_SRCBLEND_MASK 0x1f
42#define CB_BLEND0_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
43#define CB_BLEND0_CONTROL__COLOR_COMB_FCN_MASK 0xe0
44#define CB_BLEND0_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
45#define CB_BLEND0_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
46#define CB_BLEND0_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
47#define CB_BLEND0_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
48#define CB_BLEND0_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
49#define CB_BLEND0_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
50#define CB_BLEND0_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
51#define CB_BLEND0_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
52#define CB_BLEND0_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
53#define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
54#define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
55#define CB_BLEND0_CONTROL__ENABLE_MASK 0x40000000
56#define CB_BLEND0_CONTROL__ENABLE__SHIFT 0x1e
57#define CB_BLEND0_CONTROL__DISABLE_ROP3_MASK 0x80000000
58#define CB_BLEND0_CONTROL__DISABLE_ROP3__SHIFT 0x1f
59#define CB_BLEND1_CONTROL__COLOR_SRCBLEND_MASK 0x1f
60#define CB_BLEND1_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
61#define CB_BLEND1_CONTROL__COLOR_COMB_FCN_MASK 0xe0
62#define CB_BLEND1_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
63#define CB_BLEND1_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
64#define CB_BLEND1_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
65#define CB_BLEND1_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
66#define CB_BLEND1_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
67#define CB_BLEND1_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
68#define CB_BLEND1_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
69#define CB_BLEND1_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
70#define CB_BLEND1_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
71#define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
72#define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
73#define CB_BLEND1_CONTROL__ENABLE_MASK 0x40000000
74#define CB_BLEND1_CONTROL__ENABLE__SHIFT 0x1e
75#define CB_BLEND1_CONTROL__DISABLE_ROP3_MASK 0x80000000
76#define CB_BLEND1_CONTROL__DISABLE_ROP3__SHIFT 0x1f
77#define CB_BLEND2_CONTROL__COLOR_SRCBLEND_MASK 0x1f
78#define CB_BLEND2_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
79#define CB_BLEND2_CONTROL__COLOR_COMB_FCN_MASK 0xe0
80#define CB_BLEND2_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
81#define CB_BLEND2_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
82#define CB_BLEND2_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
83#define CB_BLEND2_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
84#define CB_BLEND2_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
85#define CB_BLEND2_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
86#define CB_BLEND2_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
87#define CB_BLEND2_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
88#define CB_BLEND2_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
89#define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
90#define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
91#define CB_BLEND2_CONTROL__ENABLE_MASK 0x40000000
92#define CB_BLEND2_CONTROL__ENABLE__SHIFT 0x1e
93#define CB_BLEND2_CONTROL__DISABLE_ROP3_MASK 0x80000000
94#define CB_BLEND2_CONTROL__DISABLE_ROP3__SHIFT 0x1f
95#define CB_BLEND3_CONTROL__COLOR_SRCBLEND_MASK 0x1f
96#define CB_BLEND3_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
97#define CB_BLEND3_CONTROL__COLOR_COMB_FCN_MASK 0xe0
98#define CB_BLEND3_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
99#define CB_BLEND3_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
100#define CB_BLEND3_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
101#define CB_BLEND3_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
102#define CB_BLEND3_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
103#define CB_BLEND3_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
104#define CB_BLEND3_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
105#define CB_BLEND3_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
106#define CB_BLEND3_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
107#define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
108#define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
109#define CB_BLEND3_CONTROL__ENABLE_MASK 0x40000000
110#define CB_BLEND3_CONTROL__ENABLE__SHIFT 0x1e
111#define CB_BLEND3_CONTROL__DISABLE_ROP3_MASK 0x80000000
112#define CB_BLEND3_CONTROL__DISABLE_ROP3__SHIFT 0x1f
113#define CB_BLEND4_CONTROL__COLOR_SRCBLEND_MASK 0x1f
114#define CB_BLEND4_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
115#define CB_BLEND4_CONTROL__COLOR_COMB_FCN_MASK 0xe0
116#define CB_BLEND4_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
117#define CB_BLEND4_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
118#define CB_BLEND4_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
119#define CB_BLEND4_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
120#define CB_BLEND4_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
121#define CB_BLEND4_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
122#define CB_BLEND4_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
123#define CB_BLEND4_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
124#define CB_BLEND4_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
125#define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
126#define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
127#define CB_BLEND4_CONTROL__ENABLE_MASK 0x40000000
128#define CB_BLEND4_CONTROL__ENABLE__SHIFT 0x1e
129#define CB_BLEND4_CONTROL__DISABLE_ROP3_MASK 0x80000000
130#define CB_BLEND4_CONTROL__DISABLE_ROP3__SHIFT 0x1f
131#define CB_BLEND5_CONTROL__COLOR_SRCBLEND_MASK 0x1f
132#define CB_BLEND5_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
133#define CB_BLEND5_CONTROL__COLOR_COMB_FCN_MASK 0xe0
134#define CB_BLEND5_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
135#define CB_BLEND5_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
136#define CB_BLEND5_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
137#define CB_BLEND5_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
138#define CB_BLEND5_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
139#define CB_BLEND5_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
140#define CB_BLEND5_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
141#define CB_BLEND5_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
142#define CB_BLEND5_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
143#define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
144#define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
145#define CB_BLEND5_CONTROL__ENABLE_MASK 0x40000000
146#define CB_BLEND5_CONTROL__ENABLE__SHIFT 0x1e
147#define CB_BLEND5_CONTROL__DISABLE_ROP3_MASK 0x80000000
148#define CB_BLEND5_CONTROL__DISABLE_ROP3__SHIFT 0x1f
149#define CB_BLEND6_CONTROL__COLOR_SRCBLEND_MASK 0x1f
150#define CB_BLEND6_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
151#define CB_BLEND6_CONTROL__COLOR_COMB_FCN_MASK 0xe0
152#define CB_BLEND6_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
153#define CB_BLEND6_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
154#define CB_BLEND6_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
155#define CB_BLEND6_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
156#define CB_BLEND6_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
157#define CB_BLEND6_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
158#define CB_BLEND6_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
159#define CB_BLEND6_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
160#define CB_BLEND6_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
161#define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
162#define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
163#define CB_BLEND6_CONTROL__ENABLE_MASK 0x40000000
164#define CB_BLEND6_CONTROL__ENABLE__SHIFT 0x1e
165#define CB_BLEND6_CONTROL__DISABLE_ROP3_MASK 0x80000000
166#define CB_BLEND6_CONTROL__DISABLE_ROP3__SHIFT 0x1f
167#define CB_BLEND7_CONTROL__COLOR_SRCBLEND_MASK 0x1f
168#define CB_BLEND7_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
169#define CB_BLEND7_CONTROL__COLOR_COMB_FCN_MASK 0xe0
170#define CB_BLEND7_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
171#define CB_BLEND7_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
172#define CB_BLEND7_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
173#define CB_BLEND7_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
174#define CB_BLEND7_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
175#define CB_BLEND7_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
176#define CB_BLEND7_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
177#define CB_BLEND7_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
178#define CB_BLEND7_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
179#define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
180#define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
181#define CB_BLEND7_CONTROL__ENABLE_MASK 0x40000000
182#define CB_BLEND7_CONTROL__ENABLE__SHIFT 0x1e
183#define CB_BLEND7_CONTROL__DISABLE_ROP3_MASK 0x80000000
184#define CB_BLEND7_CONTROL__DISABLE_ROP3__SHIFT 0x1f
185#define CB_COLOR0_BASE__BASE_256B_MASK 0xffffffff
186#define CB_COLOR0_BASE__BASE_256B__SHIFT 0x0
187#define CB_COLOR1_BASE__BASE_256B_MASK 0xffffffff
188#define CB_COLOR1_BASE__BASE_256B__SHIFT 0x0
189#define CB_COLOR2_BASE__BASE_256B_MASK 0xffffffff
190#define CB_COLOR2_BASE__BASE_256B__SHIFT 0x0
191#define CB_COLOR3_BASE__BASE_256B_MASK 0xffffffff
192#define CB_COLOR3_BASE__BASE_256B__SHIFT 0x0
193#define CB_COLOR4_BASE__BASE_256B_MASK 0xffffffff
194#define CB_COLOR4_BASE__BASE_256B__SHIFT 0x0
195#define CB_COLOR5_BASE__BASE_256B_MASK 0xffffffff
196#define CB_COLOR5_BASE__BASE_256B__SHIFT 0x0
197#define CB_COLOR6_BASE__BASE_256B_MASK 0xffffffff
198#define CB_COLOR6_BASE__BASE_256B__SHIFT 0x0
199#define CB_COLOR7_BASE__BASE_256B_MASK 0xffffffff
200#define CB_COLOR7_BASE__BASE_256B__SHIFT 0x0
201#define CB_COLOR0_PITCH__TILE_MAX_MASK 0x7ff
202#define CB_COLOR0_PITCH__TILE_MAX__SHIFT 0x0
203#define CB_COLOR0_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
204#define CB_COLOR0_PITCH__FMASK_TILE_MAX__SHIFT 0x14
205#define CB_COLOR1_PITCH__TILE_MAX_MASK 0x7ff
206#define CB_COLOR1_PITCH__TILE_MAX__SHIFT 0x0
207#define CB_COLOR1_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
208#define CB_COLOR1_PITCH__FMASK_TILE_MAX__SHIFT 0x14
209#define CB_COLOR2_PITCH__TILE_MAX_MASK 0x7ff
210#define CB_COLOR2_PITCH__TILE_MAX__SHIFT 0x0
211#define CB_COLOR2_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
212#define CB_COLOR2_PITCH__FMASK_TILE_MAX__SHIFT 0x14
213#define CB_COLOR3_PITCH__TILE_MAX_MASK 0x7ff
214#define CB_COLOR3_PITCH__TILE_MAX__SHIFT 0x0
215#define CB_COLOR3_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
216#define CB_COLOR3_PITCH__FMASK_TILE_MAX__SHIFT 0x14
217#define CB_COLOR4_PITCH__TILE_MAX_MASK 0x7ff
218#define CB_COLOR4_PITCH__TILE_MAX__SHIFT 0x0
219#define CB_COLOR4_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
220#define CB_COLOR4_PITCH__FMASK_TILE_MAX__SHIFT 0x14
221#define CB_COLOR5_PITCH__TILE_MAX_MASK 0x7ff
222#define CB_COLOR5_PITCH__TILE_MAX__SHIFT 0x0
223#define CB_COLOR5_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
224#define CB_COLOR5_PITCH__FMASK_TILE_MAX__SHIFT 0x14
225#define CB_COLOR6_PITCH__TILE_MAX_MASK 0x7ff
226#define CB_COLOR6_PITCH__TILE_MAX__SHIFT 0x0
227#define CB_COLOR6_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
228#define CB_COLOR6_PITCH__FMASK_TILE_MAX__SHIFT 0x14
229#define CB_COLOR7_PITCH__TILE_MAX_MASK 0x7ff
230#define CB_COLOR7_PITCH__TILE_MAX__SHIFT 0x0
231#define CB_COLOR7_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
232#define CB_COLOR7_PITCH__FMASK_TILE_MAX__SHIFT 0x14
233#define CB_COLOR0_SLICE__TILE_MAX_MASK 0x3fffff
234#define CB_COLOR0_SLICE__TILE_MAX__SHIFT 0x0
235#define CB_COLOR1_SLICE__TILE_MAX_MASK 0x3fffff
236#define CB_COLOR1_SLICE__TILE_MAX__SHIFT 0x0
237#define CB_COLOR2_SLICE__TILE_MAX_MASK 0x3fffff
238#define CB_COLOR2_SLICE__TILE_MAX__SHIFT 0x0
239#define CB_COLOR3_SLICE__TILE_MAX_MASK 0x3fffff
240#define CB_COLOR3_SLICE__TILE_MAX__SHIFT 0x0
241#define CB_COLOR4_SLICE__TILE_MAX_MASK 0x3fffff
242#define CB_COLOR4_SLICE__TILE_MAX__SHIFT 0x0
243#define CB_COLOR5_SLICE__TILE_MAX_MASK 0x3fffff
244#define CB_COLOR5_SLICE__TILE_MAX__SHIFT 0x0
245#define CB_COLOR6_SLICE__TILE_MAX_MASK 0x3fffff
246#define CB_COLOR6_SLICE__TILE_MAX__SHIFT 0x0
247#define CB_COLOR7_SLICE__TILE_MAX_MASK 0x3fffff
248#define CB_COLOR7_SLICE__TILE_MAX__SHIFT 0x0
249#define CB_COLOR0_VIEW__SLICE_START_MASK 0x7ff
250#define CB_COLOR0_VIEW__SLICE_START__SHIFT 0x0
251#define CB_COLOR0_VIEW__SLICE_MAX_MASK 0xffe000
252#define CB_COLOR0_VIEW__SLICE_MAX__SHIFT 0xd
253#define CB_COLOR1_VIEW__SLICE_START_MASK 0x7ff
254#define CB_COLOR1_VIEW__SLICE_START__SHIFT 0x0
255#define CB_COLOR1_VIEW__SLICE_MAX_MASK 0xffe000
256#define CB_COLOR1_VIEW__SLICE_MAX__SHIFT 0xd
257#define CB_COLOR2_VIEW__SLICE_START_MASK 0x7ff
258#define CB_COLOR2_VIEW__SLICE_START__SHIFT 0x0
259#define CB_COLOR2_VIEW__SLICE_MAX_MASK 0xffe000
260#define CB_COLOR2_VIEW__SLICE_MAX__SHIFT 0xd
261#define CB_COLOR3_VIEW__SLICE_START_MASK 0x7ff
262#define CB_COLOR3_VIEW__SLICE_START__SHIFT 0x0
263#define CB_COLOR3_VIEW__SLICE_MAX_MASK 0xffe000
264#define CB_COLOR3_VIEW__SLICE_MAX__SHIFT 0xd
265#define CB_COLOR4_VIEW__SLICE_START_MASK 0x7ff
266#define CB_COLOR4_VIEW__SLICE_START__SHIFT 0x0
267#define CB_COLOR4_VIEW__SLICE_MAX_MASK 0xffe000
268#define CB_COLOR4_VIEW__SLICE_MAX__SHIFT 0xd
269#define CB_COLOR5_VIEW__SLICE_START_MASK 0x7ff
270#define CB_COLOR5_VIEW__SLICE_START__SHIFT 0x0
271#define CB_COLOR5_VIEW__SLICE_MAX_MASK 0xffe000
272#define CB_COLOR5_VIEW__SLICE_MAX__SHIFT 0xd
273#define CB_COLOR6_VIEW__SLICE_START_MASK 0x7ff
274#define CB_COLOR6_VIEW__SLICE_START__SHIFT 0x0
275#define CB_COLOR6_VIEW__SLICE_MAX_MASK 0xffe000
276#define CB_COLOR6_VIEW__SLICE_MAX__SHIFT 0xd
277#define CB_COLOR7_VIEW__SLICE_START_MASK 0x7ff
278#define CB_COLOR7_VIEW__SLICE_START__SHIFT 0x0
279#define CB_COLOR7_VIEW__SLICE_MAX_MASK 0xffe000
280#define CB_COLOR7_VIEW__SLICE_MAX__SHIFT 0xd
281#define CB_COLOR0_INFO__ENDIAN_MASK 0x3
282#define CB_COLOR0_INFO__ENDIAN__SHIFT 0x0
283#define CB_COLOR0_INFO__FORMAT_MASK 0x7c
284#define CB_COLOR0_INFO__FORMAT__SHIFT 0x2
285#define CB_COLOR0_INFO__LINEAR_GENERAL_MASK 0x80
286#define CB_COLOR0_INFO__LINEAR_GENERAL__SHIFT 0x7
287#define CB_COLOR0_INFO__NUMBER_TYPE_MASK 0x700
288#define CB_COLOR0_INFO__NUMBER_TYPE__SHIFT 0x8
289#define CB_COLOR0_INFO__COMP_SWAP_MASK 0x1800
290#define CB_COLOR0_INFO__COMP_SWAP__SHIFT 0xb
291#define CB_COLOR0_INFO__FAST_CLEAR_MASK 0x2000
292#define CB_COLOR0_INFO__FAST_CLEAR__SHIFT 0xd
293#define CB_COLOR0_INFO__COMPRESSION_MASK 0x4000
294#define CB_COLOR0_INFO__COMPRESSION__SHIFT 0xe
295#define CB_COLOR0_INFO__BLEND_CLAMP_MASK 0x8000
296#define CB_COLOR0_INFO__BLEND_CLAMP__SHIFT 0xf
297#define CB_COLOR0_INFO__BLEND_BYPASS_MASK 0x10000
298#define CB_COLOR0_INFO__BLEND_BYPASS__SHIFT 0x10
299#define CB_COLOR0_INFO__SIMPLE_FLOAT_MASK 0x20000
300#define CB_COLOR0_INFO__SIMPLE_FLOAT__SHIFT 0x11
301#define CB_COLOR0_INFO__ROUND_MODE_MASK 0x40000
302#define CB_COLOR0_INFO__ROUND_MODE__SHIFT 0x12
303#define CB_COLOR0_INFO__CMASK_IS_LINEAR_MASK 0x80000
304#define CB_COLOR0_INFO__CMASK_IS_LINEAR__SHIFT 0x13
305#define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
306#define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
307#define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
308#define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
309#define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
310#define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
311#define CB_COLOR1_INFO__ENDIAN_MASK 0x3
312#define CB_COLOR1_INFO__ENDIAN__SHIFT 0x0
313#define CB_COLOR1_INFO__FORMAT_MASK 0x7c
314#define CB_COLOR1_INFO__FORMAT__SHIFT 0x2
315#define CB_COLOR1_INFO__LINEAR_GENERAL_MASK 0x80
316#define CB_COLOR1_INFO__LINEAR_GENERAL__SHIFT 0x7
317#define CB_COLOR1_INFO__NUMBER_TYPE_MASK 0x700
318#define CB_COLOR1_INFO__NUMBER_TYPE__SHIFT 0x8
319#define CB_COLOR1_INFO__COMP_SWAP_MASK 0x1800
320#define CB_COLOR1_INFO__COMP_SWAP__SHIFT 0xb
321#define CB_COLOR1_INFO__FAST_CLEAR_MASK 0x2000
322#define CB_COLOR1_INFO__FAST_CLEAR__SHIFT 0xd
323#define CB_COLOR1_INFO__COMPRESSION_MASK 0x4000
324#define CB_COLOR1_INFO__COMPRESSION__SHIFT 0xe
325#define CB_COLOR1_INFO__BLEND_CLAMP_MASK 0x8000
326#define CB_COLOR1_INFO__BLEND_CLAMP__SHIFT 0xf
327#define CB_COLOR1_INFO__BLEND_BYPASS_MASK 0x10000
328#define CB_COLOR1_INFO__BLEND_BYPASS__SHIFT 0x10
329#define CB_COLOR1_INFO__SIMPLE_FLOAT_MASK 0x20000
330#define CB_COLOR1_INFO__SIMPLE_FLOAT__SHIFT 0x11
331#define CB_COLOR1_INFO__ROUND_MODE_MASK 0x40000
332#define CB_COLOR1_INFO__ROUND_MODE__SHIFT 0x12
333#define CB_COLOR1_INFO__CMASK_IS_LINEAR_MASK 0x80000
334#define CB_COLOR1_INFO__CMASK_IS_LINEAR__SHIFT 0x13
335#define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
336#define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
337#define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
338#define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
339#define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
340#define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
341#define CB_COLOR2_INFO__ENDIAN_MASK 0x3
342#define CB_COLOR2_INFO__ENDIAN__SHIFT 0x0
343#define CB_COLOR2_INFO__FORMAT_MASK 0x7c
344#define CB_COLOR2_INFO__FORMAT__SHIFT 0x2
345#define CB_COLOR2_INFO__LINEAR_GENERAL_MASK 0x80
346#define CB_COLOR2_INFO__LINEAR_GENERAL__SHIFT 0x7
347#define CB_COLOR2_INFO__NUMBER_TYPE_MASK 0x700
348#define CB_COLOR2_INFO__NUMBER_TYPE__SHIFT 0x8
349#define CB_COLOR2_INFO__COMP_SWAP_MASK 0x1800
350#define CB_COLOR2_INFO__COMP_SWAP__SHIFT 0xb
351#define CB_COLOR2_INFO__FAST_CLEAR_MASK 0x2000
352#define CB_COLOR2_INFO__FAST_CLEAR__SHIFT 0xd
353#define CB_COLOR2_INFO__COMPRESSION_MASK 0x4000
354#define CB_COLOR2_INFO__COMPRESSION__SHIFT 0xe
355#define CB_COLOR2_INFO__BLEND_CLAMP_MASK 0x8000
356#define CB_COLOR2_INFO__BLEND_CLAMP__SHIFT 0xf
357#define CB_COLOR2_INFO__BLEND_BYPASS_MASK 0x10000
358#define CB_COLOR2_INFO__BLEND_BYPASS__SHIFT 0x10
359#define CB_COLOR2_INFO__SIMPLE_FLOAT_MASK 0x20000
360#define CB_COLOR2_INFO__SIMPLE_FLOAT__SHIFT 0x11
361#define CB_COLOR2_INFO__ROUND_MODE_MASK 0x40000
362#define CB_COLOR2_INFO__ROUND_MODE__SHIFT 0x12
363#define CB_COLOR2_INFO__CMASK_IS_LINEAR_MASK 0x80000
364#define CB_COLOR2_INFO__CMASK_IS_LINEAR__SHIFT 0x13
365#define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
366#define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
367#define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
368#define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
369#define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
370#define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
371#define CB_COLOR3_INFO__ENDIAN_MASK 0x3
372#define CB_COLOR3_INFO__ENDIAN__SHIFT 0x0
373#define CB_COLOR3_INFO__FORMAT_MASK 0x7c
374#define CB_COLOR3_INFO__FORMAT__SHIFT 0x2
375#define CB_COLOR3_INFO__LINEAR_GENERAL_MASK 0x80
376#define CB_COLOR3_INFO__LINEAR_GENERAL__SHIFT 0x7
377#define CB_COLOR3_INFO__NUMBER_TYPE_MASK 0x700
378#define CB_COLOR3_INFO__NUMBER_TYPE__SHIFT 0x8
379#define CB_COLOR3_INFO__COMP_SWAP_MASK 0x1800
380#define CB_COLOR3_INFO__COMP_SWAP__SHIFT 0xb
381#define CB_COLOR3_INFO__FAST_CLEAR_MASK 0x2000
382#define CB_COLOR3_INFO__FAST_CLEAR__SHIFT 0xd
383#define CB_COLOR3_INFO__COMPRESSION_MASK 0x4000
384#define CB_COLOR3_INFO__COMPRESSION__SHIFT 0xe
385#define CB_COLOR3_INFO__BLEND_CLAMP_MASK 0x8000
386#define CB_COLOR3_INFO__BLEND_CLAMP__SHIFT 0xf
387#define CB_COLOR3_INFO__BLEND_BYPASS_MASK 0x10000
388#define CB_COLOR3_INFO__BLEND_BYPASS__SHIFT 0x10
389#define CB_COLOR3_INFO__SIMPLE_FLOAT_MASK 0x20000
390#define CB_COLOR3_INFO__SIMPLE_FLOAT__SHIFT 0x11
391#define CB_COLOR3_INFO__ROUND_MODE_MASK 0x40000
392#define CB_COLOR3_INFO__ROUND_MODE__SHIFT 0x12
393#define CB_COLOR3_INFO__CMASK_IS_LINEAR_MASK 0x80000
394#define CB_COLOR3_INFO__CMASK_IS_LINEAR__SHIFT 0x13
395#define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
396#define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
397#define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
398#define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
399#define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
400#define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
401#define CB_COLOR4_INFO__ENDIAN_MASK 0x3
402#define CB_COLOR4_INFO__ENDIAN__SHIFT 0x0
403#define CB_COLOR4_INFO__FORMAT_MASK 0x7c
404#define CB_COLOR4_INFO__FORMAT__SHIFT 0x2
405#define CB_COLOR4_INFO__LINEAR_GENERAL_MASK 0x80
406#define CB_COLOR4_INFO__LINEAR_GENERAL__SHIFT 0x7
407#define CB_COLOR4_INFO__NUMBER_TYPE_MASK 0x700
408#define CB_COLOR4_INFO__NUMBER_TYPE__SHIFT 0x8
409#define CB_COLOR4_INFO__COMP_SWAP_MASK 0x1800
410#define CB_COLOR4_INFO__COMP_SWAP__SHIFT 0xb
411#define CB_COLOR4_INFO__FAST_CLEAR_MASK 0x2000
412#define CB_COLOR4_INFO__FAST_CLEAR__SHIFT 0xd
413#define CB_COLOR4_INFO__COMPRESSION_MASK 0x4000
414#define CB_COLOR4_INFO__COMPRESSION__SHIFT 0xe
415#define CB_COLOR4_INFO__BLEND_CLAMP_MASK 0x8000
416#define CB_COLOR4_INFO__BLEND_CLAMP__SHIFT 0xf
417#define CB_COLOR4_INFO__BLEND_BYPASS_MASK 0x10000
418#define CB_COLOR4_INFO__BLEND_BYPASS__SHIFT 0x10
419#define CB_COLOR4_INFO__SIMPLE_FLOAT_MASK 0x20000
420#define CB_COLOR4_INFO__SIMPLE_FLOAT__SHIFT 0x11
421#define CB_COLOR4_INFO__ROUND_MODE_MASK 0x40000
422#define CB_COLOR4_INFO__ROUND_MODE__SHIFT 0x12
423#define CB_COLOR4_INFO__CMASK_IS_LINEAR_MASK 0x80000
424#define CB_COLOR4_INFO__CMASK_IS_LINEAR__SHIFT 0x13
425#define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
426#define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
427#define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
428#define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
429#define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
430#define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
431#define CB_COLOR5_INFO__ENDIAN_MASK 0x3
432#define CB_COLOR5_INFO__ENDIAN__SHIFT 0x0
433#define CB_COLOR5_INFO__FORMAT_MASK 0x7c
434#define CB_COLOR5_INFO__FORMAT__SHIFT 0x2
435#define CB_COLOR5_INFO__LINEAR_GENERAL_MASK 0x80
436#define CB_COLOR5_INFO__LINEAR_GENERAL__SHIFT 0x7
437#define CB_COLOR5_INFO__NUMBER_TYPE_MASK 0x700
438#define CB_COLOR5_INFO__NUMBER_TYPE__SHIFT 0x8
439#define CB_COLOR5_INFO__COMP_SWAP_MASK 0x1800
440#define CB_COLOR5_INFO__COMP_SWAP__SHIFT 0xb
441#define CB_COLOR5_INFO__FAST_CLEAR_MASK 0x2000
442#define CB_COLOR5_INFO__FAST_CLEAR__SHIFT 0xd
443#define CB_COLOR5_INFO__COMPRESSION_MASK 0x4000
444#define CB_COLOR5_INFO__COMPRESSION__SHIFT 0xe
445#define CB_COLOR5_INFO__BLEND_CLAMP_MASK 0x8000
446#define CB_COLOR5_INFO__BLEND_CLAMP__SHIFT 0xf
447#define CB_COLOR5_INFO__BLEND_BYPASS_MASK 0x10000
448#define CB_COLOR5_INFO__BLEND_BYPASS__SHIFT 0x10
449#define CB_COLOR5_INFO__SIMPLE_FLOAT_MASK 0x20000
450#define CB_COLOR5_INFO__SIMPLE_FLOAT__SHIFT 0x11
451#define CB_COLOR5_INFO__ROUND_MODE_MASK 0x40000
452#define CB_COLOR5_INFO__ROUND_MODE__SHIFT 0x12
453#define CB_COLOR5_INFO__CMASK_IS_LINEAR_MASK 0x80000
454#define CB_COLOR5_INFO__CMASK_IS_LINEAR__SHIFT 0x13
455#define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
456#define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
457#define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
458#define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
459#define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
460#define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
461#define CB_COLOR6_INFO__ENDIAN_MASK 0x3
462#define CB_COLOR6_INFO__ENDIAN__SHIFT 0x0
463#define CB_COLOR6_INFO__FORMAT_MASK 0x7c
464#define CB_COLOR6_INFO__FORMAT__SHIFT 0x2
465#define CB_COLOR6_INFO__LINEAR_GENERAL_MASK 0x80
466#define CB_COLOR6_INFO__LINEAR_GENERAL__SHIFT 0x7
467#define CB_COLOR6_INFO__NUMBER_TYPE_MASK 0x700
468#define CB_COLOR6_INFO__NUMBER_TYPE__SHIFT 0x8
469#define CB_COLOR6_INFO__COMP_SWAP_MASK 0x1800
470#define CB_COLOR6_INFO__COMP_SWAP__SHIFT 0xb
471#define CB_COLOR6_INFO__FAST_CLEAR_MASK 0x2000
472#define CB_COLOR6_INFO__FAST_CLEAR__SHIFT 0xd
473#define CB_COLOR6_INFO__COMPRESSION_MASK 0x4000
474#define CB_COLOR6_INFO__COMPRESSION__SHIFT 0xe
475#define CB_COLOR6_INFO__BLEND_CLAMP_MASK 0x8000
476#define CB_COLOR6_INFO__BLEND_CLAMP__SHIFT 0xf
477#define CB_COLOR6_INFO__BLEND_BYPASS_MASK 0x10000
478#define CB_COLOR6_INFO__BLEND_BYPASS__SHIFT 0x10
479#define CB_COLOR6_INFO__SIMPLE_FLOAT_MASK 0x20000
480#define CB_COLOR6_INFO__SIMPLE_FLOAT__SHIFT 0x11
481#define CB_COLOR6_INFO__ROUND_MODE_MASK 0x40000
482#define CB_COLOR6_INFO__ROUND_MODE__SHIFT 0x12
483#define CB_COLOR6_INFO__CMASK_IS_LINEAR_MASK 0x80000
484#define CB_COLOR6_INFO__CMASK_IS_LINEAR__SHIFT 0x13
485#define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
486#define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
487#define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
488#define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
489#define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
490#define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
491#define CB_COLOR7_INFO__ENDIAN_MASK 0x3
492#define CB_COLOR7_INFO__ENDIAN__SHIFT 0x0
493#define CB_COLOR7_INFO__FORMAT_MASK 0x7c
494#define CB_COLOR7_INFO__FORMAT__SHIFT 0x2
495#define CB_COLOR7_INFO__LINEAR_GENERAL_MASK 0x80
496#define CB_COLOR7_INFO__LINEAR_GENERAL__SHIFT 0x7
497#define CB_COLOR7_INFO__NUMBER_TYPE_MASK 0x700
498#define CB_COLOR7_INFO__NUMBER_TYPE__SHIFT 0x8
499#define CB_COLOR7_INFO__COMP_SWAP_MASK 0x1800
500#define CB_COLOR7_INFO__COMP_SWAP__SHIFT 0xb
501#define CB_COLOR7_INFO__FAST_CLEAR_MASK 0x2000
502#define CB_COLOR7_INFO__FAST_CLEAR__SHIFT 0xd
503#define CB_COLOR7_INFO__COMPRESSION_MASK 0x4000
504#define CB_COLOR7_INFO__COMPRESSION__SHIFT 0xe
505#define CB_COLOR7_INFO__BLEND_CLAMP_MASK 0x8000
506#define CB_COLOR7_INFO__BLEND_CLAMP__SHIFT 0xf
507#define CB_COLOR7_INFO__BLEND_BYPASS_MASK 0x10000
508#define CB_COLOR7_INFO__BLEND_BYPASS__SHIFT 0x10
509#define CB_COLOR7_INFO__SIMPLE_FLOAT_MASK 0x20000
510#define CB_COLOR7_INFO__SIMPLE_FLOAT__SHIFT 0x11
511#define CB_COLOR7_INFO__ROUND_MODE_MASK 0x40000
512#define CB_COLOR7_INFO__ROUND_MODE__SHIFT 0x12
513#define CB_COLOR7_INFO__CMASK_IS_LINEAR_MASK 0x80000
514#define CB_COLOR7_INFO__CMASK_IS_LINEAR__SHIFT 0x13
515#define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
516#define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
517#define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
518#define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
519#define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
520#define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
521#define CB_COLOR0_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
522#define CB_COLOR0_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
523#define CB_COLOR0_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
524#define CB_COLOR0_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
525#define CB_COLOR0_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
526#define CB_COLOR0_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
527#define CB_COLOR0_ATTRIB__NUM_SAMPLES_MASK 0x7000
528#define CB_COLOR0_ATTRIB__NUM_SAMPLES__SHIFT 0xc
529#define CB_COLOR0_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
530#define CB_COLOR0_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
531#define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
532#define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
533#define CB_COLOR1_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
534#define CB_COLOR1_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
535#define CB_COLOR1_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
536#define CB_COLOR1_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
537#define CB_COLOR1_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
538#define CB_COLOR1_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
539#define CB_COLOR1_ATTRIB__NUM_SAMPLES_MASK 0x7000
540#define CB_COLOR1_ATTRIB__NUM_SAMPLES__SHIFT 0xc
541#define CB_COLOR1_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
542#define CB_COLOR1_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
543#define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
544#define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
545#define CB_COLOR2_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
546#define CB_COLOR2_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
547#define CB_COLOR2_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
548#define CB_COLOR2_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
549#define CB_COLOR2_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
550#define CB_COLOR2_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
551#define CB_COLOR2_ATTRIB__NUM_SAMPLES_MASK 0x7000
552#define CB_COLOR2_ATTRIB__NUM_SAMPLES__SHIFT 0xc
553#define CB_COLOR2_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
554#define CB_COLOR2_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
555#define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
556#define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
557#define CB_COLOR3_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
558#define CB_COLOR3_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
559#define CB_COLOR3_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
560#define CB_COLOR3_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
561#define CB_COLOR3_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
562#define CB_COLOR3_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
563#define CB_COLOR3_ATTRIB__NUM_SAMPLES_MASK 0x7000
564#define CB_COLOR3_ATTRIB__NUM_SAMPLES__SHIFT 0xc
565#define CB_COLOR3_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
566#define CB_COLOR3_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
567#define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
568#define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
569#define CB_COLOR4_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
570#define CB_COLOR4_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
571#define CB_COLOR4_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
572#define CB_COLOR4_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
573#define CB_COLOR4_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
574#define CB_COLOR4_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
575#define CB_COLOR4_ATTRIB__NUM_SAMPLES_MASK 0x7000
576#define CB_COLOR4_ATTRIB__NUM_SAMPLES__SHIFT 0xc
577#define CB_COLOR4_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
578#define CB_COLOR4_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
579#define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
580#define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
581#define CB_COLOR5_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
582#define CB_COLOR5_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
583#define CB_COLOR5_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
584#define CB_COLOR5_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
585#define CB_COLOR5_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
586#define CB_COLOR5_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
587#define CB_COLOR5_ATTRIB__NUM_SAMPLES_MASK 0x7000
588#define CB_COLOR5_ATTRIB__NUM_SAMPLES__SHIFT 0xc
589#define CB_COLOR5_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
590#define CB_COLOR5_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
591#define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
592#define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
593#define CB_COLOR6_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
594#define CB_COLOR6_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
595#define CB_COLOR6_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
596#define CB_COLOR6_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
597#define CB_COLOR6_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
598#define CB_COLOR6_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
599#define CB_COLOR6_ATTRIB__NUM_SAMPLES_MASK 0x7000
600#define CB_COLOR6_ATTRIB__NUM_SAMPLES__SHIFT 0xc
601#define CB_COLOR6_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
602#define CB_COLOR6_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
603#define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
604#define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
605#define CB_COLOR7_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
606#define CB_COLOR7_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
607#define CB_COLOR7_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
608#define CB_COLOR7_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
609#define CB_COLOR7_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
610#define CB_COLOR7_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
611#define CB_COLOR7_ATTRIB__NUM_SAMPLES_MASK 0x7000
612#define CB_COLOR7_ATTRIB__NUM_SAMPLES__SHIFT 0xc
613#define CB_COLOR7_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
614#define CB_COLOR7_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
615#define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
616#define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
617#define CB_COLOR0_CMASK__BASE_256B_MASK 0xffffffff
618#define CB_COLOR0_CMASK__BASE_256B__SHIFT 0x0
619#define CB_COLOR1_CMASK__BASE_256B_MASK 0xffffffff
620#define CB_COLOR1_CMASK__BASE_256B__SHIFT 0x0
621#define CB_COLOR2_CMASK__BASE_256B_MASK 0xffffffff
622#define CB_COLOR2_CMASK__BASE_256B__SHIFT 0x0
623#define CB_COLOR3_CMASK__BASE_256B_MASK 0xffffffff
624#define CB_COLOR3_CMASK__BASE_256B__SHIFT 0x0
625#define CB_COLOR4_CMASK__BASE_256B_MASK 0xffffffff
626#define CB_COLOR4_CMASK__BASE_256B__SHIFT 0x0
627#define CB_COLOR5_CMASK__BASE_256B_MASK 0xffffffff
628#define CB_COLOR5_CMASK__BASE_256B__SHIFT 0x0
629#define CB_COLOR6_CMASK__BASE_256B_MASK 0xffffffff
630#define CB_COLOR6_CMASK__BASE_256B__SHIFT 0x0
631#define CB_COLOR7_CMASK__BASE_256B_MASK 0xffffffff
632#define CB_COLOR7_CMASK__BASE_256B__SHIFT 0x0
633#define CB_COLOR0_CMASK_SLICE__TILE_MAX_MASK 0x3fff
634#define CB_COLOR0_CMASK_SLICE__TILE_MAX__SHIFT 0x0
635#define CB_COLOR1_CMASK_SLICE__TILE_MAX_MASK 0x3fff
636#define CB_COLOR1_CMASK_SLICE__TILE_MAX__SHIFT 0x0
637#define CB_COLOR2_CMASK_SLICE__TILE_MAX_MASK 0x3fff
638#define CB_COLOR2_CMASK_SLICE__TILE_MAX__SHIFT 0x0
639#define CB_COLOR3_CMASK_SLICE__TILE_MAX_MASK 0x3fff
640#define CB_COLOR3_CMASK_SLICE__TILE_MAX__SHIFT 0x0
641#define CB_COLOR4_CMASK_SLICE__TILE_MAX_MASK 0x3fff
642#define CB_COLOR4_CMASK_SLICE__TILE_MAX__SHIFT 0x0
643#define CB_COLOR5_CMASK_SLICE__TILE_MAX_MASK 0x3fff
644#define CB_COLOR5_CMASK_SLICE__TILE_MAX__SHIFT 0x0
645#define CB_COLOR6_CMASK_SLICE__TILE_MAX_MASK 0x3fff
646#define CB_COLOR6_CMASK_SLICE__TILE_MAX__SHIFT 0x0
647#define CB_COLOR7_CMASK_SLICE__TILE_MAX_MASK 0x3fff
648#define CB_COLOR7_CMASK_SLICE__TILE_MAX__SHIFT 0x0
649#define CB_COLOR0_FMASK__BASE_256B_MASK 0xffffffff
650#define CB_COLOR0_FMASK__BASE_256B__SHIFT 0x0
651#define CB_COLOR1_FMASK__BASE_256B_MASK 0xffffffff
652#define CB_COLOR1_FMASK__BASE_256B__SHIFT 0x0
653#define CB_COLOR2_FMASK__BASE_256B_MASK 0xffffffff
654#define CB_COLOR2_FMASK__BASE_256B__SHIFT 0x0
655#define CB_COLOR3_FMASK__BASE_256B_MASK 0xffffffff
656#define CB_COLOR3_FMASK__BASE_256B__SHIFT 0x0
657#define CB_COLOR4_FMASK__BASE_256B_MASK 0xffffffff
658#define CB_COLOR4_FMASK__BASE_256B__SHIFT 0x0
659#define CB_COLOR5_FMASK__BASE_256B_MASK 0xffffffff
660#define CB_COLOR5_FMASK__BASE_256B__SHIFT 0x0
661#define CB_COLOR6_FMASK__BASE_256B_MASK 0xffffffff
662#define CB_COLOR6_FMASK__BASE_256B__SHIFT 0x0
663#define CB_COLOR7_FMASK__BASE_256B_MASK 0xffffffff
664#define CB_COLOR7_FMASK__BASE_256B__SHIFT 0x0
665#define CB_COLOR0_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
666#define CB_COLOR0_FMASK_SLICE__TILE_MAX__SHIFT 0x0
667#define CB_COLOR1_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
668#define CB_COLOR1_FMASK_SLICE__TILE_MAX__SHIFT 0x0
669#define CB_COLOR2_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
670#define CB_COLOR2_FMASK_SLICE__TILE_MAX__SHIFT 0x0
671#define CB_COLOR3_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
672#define CB_COLOR3_FMASK_SLICE__TILE_MAX__SHIFT 0x0
673#define CB_COLOR4_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
674#define CB_COLOR4_FMASK_SLICE__TILE_MAX__SHIFT 0x0
675#define CB_COLOR5_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
676#define CB_COLOR5_FMASK_SLICE__TILE_MAX__SHIFT 0x0
677#define CB_COLOR6_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
678#define CB_COLOR6_FMASK_SLICE__TILE_MAX__SHIFT 0x0
679#define CB_COLOR7_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
680#define CB_COLOR7_FMASK_SLICE__TILE_MAX__SHIFT 0x0
681#define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
682#define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
683#define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
684#define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
685#define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
686#define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
687#define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
688#define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
689#define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
690#define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
691#define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
692#define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
693#define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
694#define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
695#define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
696#define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
697#define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
698#define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
699#define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
700#define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
701#define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
702#define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
703#define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
704#define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
705#define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
706#define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
707#define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
708#define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
709#define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
710#define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
711#define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
712#define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
713#define CB_TARGET_MASK__TARGET0_ENABLE_MASK 0xf
714#define CB_TARGET_MASK__TARGET0_ENABLE__SHIFT 0x0
715#define CB_TARGET_MASK__TARGET1_ENABLE_MASK 0xf0
716#define CB_TARGET_MASK__TARGET1_ENABLE__SHIFT 0x4
717#define CB_TARGET_MASK__TARGET2_ENABLE_MASK 0xf00
718#define CB_TARGET_MASK__TARGET2_ENABLE__SHIFT 0x8
719#define CB_TARGET_MASK__TARGET3_ENABLE_MASK 0xf000
720#define CB_TARGET_MASK__TARGET3_ENABLE__SHIFT 0xc
721#define CB_TARGET_MASK__TARGET4_ENABLE_MASK 0xf0000
722#define CB_TARGET_MASK__TARGET4_ENABLE__SHIFT 0x10
723#define CB_TARGET_MASK__TARGET5_ENABLE_MASK 0xf00000
724#define CB_TARGET_MASK__TARGET5_ENABLE__SHIFT 0x14
725#define CB_TARGET_MASK__TARGET6_ENABLE_MASK 0xf000000
726#define CB_TARGET_MASK__TARGET6_ENABLE__SHIFT 0x18
727#define CB_TARGET_MASK__TARGET7_ENABLE_MASK 0xf0000000
728#define CB_TARGET_MASK__TARGET7_ENABLE__SHIFT 0x1c
729#define CB_SHADER_MASK__OUTPUT0_ENABLE_MASK 0xf
730#define CB_SHADER_MASK__OUTPUT0_ENABLE__SHIFT 0x0
731#define CB_SHADER_MASK__OUTPUT1_ENABLE_MASK 0xf0
732#define CB_SHADER_MASK__OUTPUT1_ENABLE__SHIFT 0x4
733#define CB_SHADER_MASK__OUTPUT2_ENABLE_MASK 0xf00
734#define CB_SHADER_MASK__OUTPUT2_ENABLE__SHIFT 0x8
735#define CB_SHADER_MASK__OUTPUT3_ENABLE_MASK 0xf000
736#define CB_SHADER_MASK__OUTPUT3_ENABLE__SHIFT 0xc
737#define CB_SHADER_MASK__OUTPUT4_ENABLE_MASK 0xf0000
738#define CB_SHADER_MASK__OUTPUT4_ENABLE__SHIFT 0x10
739#define CB_SHADER_MASK__OUTPUT5_ENABLE_MASK 0xf00000
740#define CB_SHADER_MASK__OUTPUT5_ENABLE__SHIFT 0x14
741#define CB_SHADER_MASK__OUTPUT6_ENABLE_MASK 0xf000000
742#define CB_SHADER_MASK__OUTPUT6_ENABLE__SHIFT 0x18
743#define CB_SHADER_MASK__OUTPUT7_ENABLE_MASK 0xf0000000
744#define CB_SHADER_MASK__OUTPUT7_ENABLE__SHIFT 0x1c
745#define CB_HW_CONTROL__CM_CACHE_EVICT_POINT_MASK 0xf
746#define CB_HW_CONTROL__CM_CACHE_EVICT_POINT__SHIFT 0x0
747#define CB_HW_CONTROL__FC_CACHE_EVICT_POINT_MASK 0x3c0
748#define CB_HW_CONTROL__FC_CACHE_EVICT_POINT__SHIFT 0x6
749#define CB_HW_CONTROL__CC_CACHE_EVICT_POINT_MASK 0xf000
750#define CB_HW_CONTROL__CC_CACHE_EVICT_POINT__SHIFT 0xc
751#define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE_MASK 0x10000
752#define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE__SHIFT 0x10
753#define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING_MASK 0x40000
754#define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING__SHIFT 0x12
755#define CB_HW_CONTROL__FORCE_NEEDS_DST_MASK 0x80000
756#define CB_HW_CONTROL__FORCE_NEEDS_DST__SHIFT 0x13
757#define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE_MASK 0x100000
758#define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE__SHIFT 0x14
759#define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST_MASK 0x200000
760#define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST__SHIFT 0x15
761#define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK_MASK 0x400000
762#define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK__SHIFT 0x16
763#define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG_MASK 0x800000
764#define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG__SHIFT 0x17
765#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST_MASK 0x1000000
766#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT 0x18
767#define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS_MASK 0x2000000
768#define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS__SHIFT 0x19
769#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK 0x4000000
770#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT 0x1a
771#define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED_MASK 0x8000000
772#define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED__SHIFT 0x1b
773#define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT_MASK 0x10000000
774#define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT__SHIFT 0x1c
775#define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT_MASK 0x20000000
776#define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT__SHIFT 0x1d
777#define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT_MASK 0x40000000
778#define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT__SHIFT 0x1e
779#define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE_MASK 0x80000000
780#define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE__SHIFT 0x1f
781#define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS_MASK 0x1f
782#define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS__SHIFT 0x0
783#define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS_MASK 0x7e0
784#define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS__SHIFT 0x5
785#define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS_MASK 0x1f800
786#define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS__SHIFT 0xb
787#define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH_MASK 0x3fe0000
788#define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH__SHIFT 0x11
789#define CB_HW_CONTROL_1__CHICKEN_BITS_MASK 0xfc000000
790#define CB_HW_CONTROL_1__CHICKEN_BITS__SHIFT 0x1a
791#define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH_MASK 0xff
792#define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH__SHIFT 0x0
793#define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH_MASK 0x7f00
794#define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH__SHIFT 0x8
795#define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH_MASK 0x7f8000
796#define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH__SHIFT 0xf
797#define CB_HW_CONTROL_2__CHICKEN_BITS_MASK 0xff000000
798#define CB_HW_CONTROL_2__CHICKEN_BITS__SHIFT 0x18
799#define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL_MASK 0x1
800#define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL__SHIFT 0x0
801#define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE_MASK 0x1
802#define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE__SHIFT 0x0
803#define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL_MASK 0xe
804#define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL__SHIFT 0x1
805#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE_MASK 0x10
806#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE__SHIFT 0x4
807#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL_MASK 0x3e0
808#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL__SHIFT 0x5
809#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE_MASK 0x400
810#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE__SHIFT 0xa
811#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL_MASK 0x800
812#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL__SHIFT 0xb
813#define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE_MASK 0x1000
814#define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE__SHIFT 0xc
815#define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL_MASK 0xe000
816#define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL__SHIFT 0xd
817#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE_MASK 0x20000
818#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE__SHIFT 0x11
819#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL_MASK 0x1c0000
820#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL__SHIFT 0x12
821#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE_MASK 0x200000
822#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE__SHIFT 0x15
823#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL_MASK 0xc00000
824#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL__SHIFT 0x16
825#define CB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x1ff
826#define CB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
827#define CB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x7fc00
828#define CB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
829#define CB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
830#define CB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
831#define CB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000
832#define CB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
833#define CB_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
834#define CB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
835#define CB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x1ff
836#define CB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
837#define CB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x7fc00
838#define CB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
839#define CB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000
840#define CB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
841#define CB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000
842#define CB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
843#define CB_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x1ff
844#define CB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
845#define CB_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
846#define CB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
847#define CB_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x1ff
848#define CB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
849#define CB_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000
850#define CB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
851#define CB_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x1ff
852#define CB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
853#define CB_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000
854#define CB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
855#define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
856#define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
857#define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
858#define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
859#define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
860#define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
861#define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
862#define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
863#define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
864#define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
865#define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
866#define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
867#define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
868#define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
869#define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
870#define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
871#define CB_CGTT_SCLK_CTRL__ON_DELAY_MASK 0xf
872#define CB_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0
873#define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
874#define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
875#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
876#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
877#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
878#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
879#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
880#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
881#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
882#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
883#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
884#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
885#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
886#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
887#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
888#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
889#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
890#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
891#define CB_DEBUG_BUS_13__TILE_INTFC_BUSY_MASK 0x1
892#define CB_DEBUG_BUS_13__TILE_INTFC_BUSY__SHIFT 0x0
893#define CB_DEBUG_BUS_13__MU_BUSY_MASK 0x2
894#define CB_DEBUG_BUS_13__MU_BUSY__SHIFT 0x1
895#define CB_DEBUG_BUS_13__TQ_BUSY_MASK 0x4
896#define CB_DEBUG_BUS_13__TQ_BUSY__SHIFT 0x2
897#define CB_DEBUG_BUS_13__AC_BUSY_MASK 0x8
898#define CB_DEBUG_BUS_13__AC_BUSY__SHIFT 0x3
899#define CB_DEBUG_BUS_13__CRW_BUSY_MASK 0x10
900#define CB_DEBUG_BUS_13__CRW_BUSY__SHIFT 0x4
901#define CB_DEBUG_BUS_13__CACHE_CTRL_BUSY_MASK 0x20
902#define CB_DEBUG_BUS_13__CACHE_CTRL_BUSY__SHIFT 0x5
903#define CB_DEBUG_BUS_13__MC_WR_PENDING_MASK 0x40
904#define CB_DEBUG_BUS_13__MC_WR_PENDING__SHIFT 0x6
905#define CB_DEBUG_BUS_13__FC_WR_PENDING_MASK 0x80
906#define CB_DEBUG_BUS_13__FC_WR_PENDING__SHIFT 0x7
907#define CB_DEBUG_BUS_13__FC_RD_PENDING_MASK 0x100
908#define CB_DEBUG_BUS_13__FC_RD_PENDING__SHIFT 0x8
909#define CB_DEBUG_BUS_13__EVICT_PENDING_MASK 0x200
910#define CB_DEBUG_BUS_13__EVICT_PENDING__SHIFT 0x9
911#define CB_DEBUG_BUS_13__LAST_RD_ARB_WINNER_MASK 0x400
912#define CB_DEBUG_BUS_13__LAST_RD_ARB_WINNER__SHIFT 0xa
913#define CB_DEBUG_BUS_13__MU_STATE_MASK 0x7f800
914#define CB_DEBUG_BUS_13__MU_STATE__SHIFT 0xb
915#define CB_DEBUG_BUS_14__TILE_RETIREMENT_BUSY_MASK 0x1
916#define CB_DEBUG_BUS_14__TILE_RETIREMENT_BUSY__SHIFT 0x0
917#define CB_DEBUG_BUS_14__FOP_BUSY_MASK 0x2
918#define CB_DEBUG_BUS_14__FOP_BUSY__SHIFT 0x1
919#define CB_DEBUG_BUS_14__LAT_BUSY_MASK 0x4
920#define CB_DEBUG_BUS_14__LAT_BUSY__SHIFT 0x2
921#define CB_DEBUG_BUS_14__CACHE_CTL_BUSY_MASK 0x8
922#define CB_DEBUG_BUS_14__CACHE_CTL_BUSY__SHIFT 0x3
923#define CB_DEBUG_BUS_14__ADDR_BUSY_MASK 0x10
924#define CB_DEBUG_BUS_14__ADDR_BUSY__SHIFT 0x4
925#define CB_DEBUG_BUS_14__MERGE_BUSY_MASK 0x20
926#define CB_DEBUG_BUS_14__MERGE_BUSY__SHIFT 0x5
927#define CB_DEBUG_BUS_14__QUAD_BUSY_MASK 0x40
928#define CB_DEBUG_BUS_14__QUAD_BUSY__SHIFT 0x6
929#define CB_DEBUG_BUS_14__TILE_BUSY_MASK 0x80
930#define CB_DEBUG_BUS_14__TILE_BUSY__SHIFT 0x7
931#define CB_DEBUG_BUS_14__CLEAR_BUSY_MASK 0x100
932#define CB_DEBUG_BUS_14__CLEAR_BUSY__SHIFT 0x8
933#define CB_DEBUG_BUS_15__SURF_SYNC_STATE_MASK 0x3
934#define CB_DEBUG_BUS_15__SURF_SYNC_STATE__SHIFT 0x0
935#define CB_DEBUG_BUS_15__SURF_SYNC_START_MASK 0x4
936#define CB_DEBUG_BUS_15__SURF_SYNC_START__SHIFT 0x2
937#define CB_DEBUG_BUS_15__SF_BUSY_MASK 0x8
938#define CB_DEBUG_BUS_15__SF_BUSY__SHIFT 0x3
939#define CB_DEBUG_BUS_15__CS_BUSY_MASK 0x10
940#define CB_DEBUG_BUS_15__CS_BUSY__SHIFT 0x4
941#define CB_DEBUG_BUS_15__RB_BUSY_MASK 0x20
942#define CB_DEBUG_BUS_15__RB_BUSY__SHIFT 0x5
943#define CB_DEBUG_BUS_15__DS_BUSY_MASK 0x40
944#define CB_DEBUG_BUS_15__DS_BUSY__SHIFT 0x6
945#define CB_DEBUG_BUS_15__TB_BUSY_MASK 0x80
946#define CB_DEBUG_BUS_15__TB_BUSY__SHIFT 0x7
947#define CB_DEBUG_BUS_15__IB_BUSY_MASK 0x100
948#define CB_DEBUG_BUS_15__IB_BUSY__SHIFT 0x8
949#define CB_DEBUG_BUS_16__MC_RDREQ_CREDITS_MASK 0x3f
950#define CB_DEBUG_BUS_16__MC_RDREQ_CREDITS__SHIFT 0x0
951#define CB_DEBUG_BUS_16__LAST_RD_GRANT_VEC_MASK 0x3c0
952#define CB_DEBUG_BUS_16__LAST_RD_GRANT_VEC__SHIFT 0x6
953#define CB_DEBUG_BUS_16__MC_WRREQ_CREDITS_MASK 0xfc00
954#define CB_DEBUG_BUS_16__MC_WRREQ_CREDITS__SHIFT 0xa
955#define CB_DEBUG_BUS_16__LAST_WR_GRANT_VEC_MASK 0xf0000
956#define CB_DEBUG_BUS_16__LAST_WR_GRANT_VEC__SHIFT 0x10
957#define CB_DEBUG_BUS_16__CC_WRREQ_FIFO_EMPTY_MASK 0x100000
958#define CB_DEBUG_BUS_16__CC_WRREQ_FIFO_EMPTY__SHIFT 0x14
959#define CB_DEBUG_BUS_16__FC_WRREQ_FIFO_EMPTY_MASK 0x200000
960#define CB_DEBUG_BUS_16__FC_WRREQ_FIFO_EMPTY__SHIFT 0x15
961#define CB_DEBUG_BUS_16__CM_WRREQ_FIFO_EMPTY_MASK 0x400000
962#define CB_DEBUG_BUS_16__CM_WRREQ_FIFO_EMPTY__SHIFT 0x16
963#define CB_DEBUG_BUS_17__CM_BUSY_MASK 0x1
964#define CB_DEBUG_BUS_17__CM_BUSY__SHIFT 0x0
965#define CB_DEBUG_BUS_17__FC_BUSY_MASK 0x2
966#define CB_DEBUG_BUS_17__FC_BUSY__SHIFT 0x1
967#define CB_DEBUG_BUS_17__CC_BUSY_MASK 0x4
968#define CB_DEBUG_BUS_17__CC_BUSY__SHIFT 0x2
969#define CB_DEBUG_BUS_17__BB_BUSY_MASK 0x8
970#define CB_DEBUG_BUS_17__BB_BUSY__SHIFT 0x3
971#define CB_DEBUG_BUS_17__MA_BUSY_MASK 0x10
972#define CB_DEBUG_BUS_17__MA_BUSY__SHIFT 0x4
973#define CB_DEBUG_BUS_17__CORE_SCLK_VLD_MASK 0x20
974#define CB_DEBUG_BUS_17__CORE_SCLK_VLD__SHIFT 0x5
975#define CB_DEBUG_BUS_17__REG_SCLK1_VLD_MASK 0x40
976#define CB_DEBUG_BUS_17__REG_SCLK1_VLD__SHIFT 0x6
977#define CB_DEBUG_BUS_17__REG_SCLK0_VLD_MASK 0x80
978#define CB_DEBUG_BUS_17__REG_SCLK0_VLD__SHIFT 0x7
979#define CB_DEBUG_BUS_18__NOT_USED_MASK 0xffffff
980#define CB_DEBUG_BUS_18__NOT_USED__SHIFT 0x0
981#define CP_DFY_CNTL__POLICY_MASK 0x300
982#define CP_DFY_CNTL__POLICY__SHIFT 0x8
983#define CP_DFY_CNTL__VOL_MASK 0x400
984#define CP_DFY_CNTL__VOL__SHIFT 0xa
985#define CP_DFY_CNTL__ATC_MASK 0x800
986#define CP_DFY_CNTL__ATC__SHIFT 0xb
987#define CP_DFY_STAT__BURST_COUNT_MASK 0xffff
988#define CP_DFY_STAT__BURST_COUNT__SHIFT 0x0
989#define CP_DFY_STAT__TAGS_PENDING_MASK 0xff0000
990#define CP_DFY_STAT__TAGS_PENDING__SHIFT 0x10
991#define CP_DFY_STAT__BUSY_MASK 0x80000000
992#define CP_DFY_STAT__BUSY__SHIFT 0x1f
993#define CP_DFY_ADDR_HI__ADDR_HI_MASK 0xffffffff
994#define CP_DFY_ADDR_HI__ADDR_HI__SHIFT 0x0
995#define CP_DFY_ADDR_LO__ADDR_LO_MASK 0xffffffe0
996#define CP_DFY_ADDR_LO__ADDR_LO__SHIFT 0x5
997#define CP_DFY_DATA_0__DATA_MASK 0xffffffff
998#define CP_DFY_DATA_0__DATA__SHIFT 0x0
999#define CP_DFY_DATA_1__DATA_MASK 0xffffffff
1000#define CP_DFY_DATA_1__DATA__SHIFT 0x0
1001#define CP_DFY_DATA_2__DATA_MASK 0xffffffff
1002#define CP_DFY_DATA_2__DATA__SHIFT 0x0
1003#define CP_DFY_DATA_3__DATA_MASK 0xffffffff
1004#define CP_DFY_DATA_3__DATA__SHIFT 0x0
1005#define CP_DFY_DATA_4__DATA_MASK 0xffffffff
1006#define CP_DFY_DATA_4__DATA__SHIFT 0x0
1007#define CP_DFY_DATA_5__DATA_MASK 0xffffffff
1008#define CP_DFY_DATA_5__DATA__SHIFT 0x0
1009#define CP_DFY_DATA_6__DATA_MASK 0xffffffff
1010#define CP_DFY_DATA_6__DATA__SHIFT 0x0
1011#define CP_DFY_DATA_7__DATA_MASK 0xffffffff
1012#define CP_DFY_DATA_7__DATA__SHIFT 0x0
1013#define CP_DFY_DATA_8__DATA_MASK 0xffffffff
1014#define CP_DFY_DATA_8__DATA__SHIFT 0x0
1015#define CP_DFY_DATA_9__DATA_MASK 0xffffffff
1016#define CP_DFY_DATA_9__DATA__SHIFT 0x0
1017#define CP_DFY_DATA_10__DATA_MASK 0xffffffff
1018#define CP_DFY_DATA_10__DATA__SHIFT 0x0
1019#define CP_DFY_DATA_11__DATA_MASK 0xffffffff
1020#define CP_DFY_DATA_11__DATA__SHIFT 0x0
1021#define CP_DFY_DATA_12__DATA_MASK 0xffffffff
1022#define CP_DFY_DATA_12__DATA__SHIFT 0x0
1023#define CP_DFY_DATA_13__DATA_MASK 0xffffffff
1024#define CP_DFY_DATA_13__DATA__SHIFT 0x0
1025#define CP_DFY_DATA_14__DATA_MASK 0xffffffff
1026#define CP_DFY_DATA_14__DATA__SHIFT 0x0
1027#define CP_DFY_DATA_15__DATA_MASK 0xffffffff
1028#define CP_DFY_DATA_15__DATA__SHIFT 0x0
1029#define CP_RB0_BASE__RB_BASE_MASK 0xffffffff
1030#define CP_RB0_BASE__RB_BASE__SHIFT 0x0
1031#define CP_RB0_BASE_HI__RB_BASE_HI_MASK 0xff
1032#define CP_RB0_BASE_HI__RB_BASE_HI__SHIFT 0x0
1033#define CP_RB_BASE__RB_BASE_MASK 0xffffffff
1034#define CP_RB_BASE__RB_BASE__SHIFT 0x0
1035#define CP_RB1_BASE__RB_BASE_MASK 0xffffffff
1036#define CP_RB1_BASE__RB_BASE__SHIFT 0x0
1037#define CP_RB1_BASE_HI__RB_BASE_HI_MASK 0xff
1038#define CP_RB1_BASE_HI__RB_BASE_HI__SHIFT 0x0
1039#define CP_RB2_BASE__RB_BASE_MASK 0xffffffff
1040#define CP_RB2_BASE__RB_BASE__SHIFT 0x0
1041#define CP_RB0_CNTL__RB_BUFSZ_MASK 0x3f
1042#define CP_RB0_CNTL__RB_BUFSZ__SHIFT 0x0
1043#define CP_RB0_CNTL__RB_BLKSZ_MASK 0x3f00
1044#define CP_RB0_CNTL__RB_BLKSZ__SHIFT 0x8
1045#define CP_RB0_CNTL__BUF_SWAP_MASK 0x30000
1046#define CP_RB0_CNTL__BUF_SWAP__SHIFT 0x10
1047#define CP_RB0_CNTL__MIN_AVAILSZ_MASK 0x300000
1048#define CP_RB0_CNTL__MIN_AVAILSZ__SHIFT 0x14
1049#define CP_RB0_CNTL__MIN_IB_AVAILSZ_MASK 0xc00000
1050#define CP_RB0_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16
1051#define CP_RB0_CNTL__CACHE_POLICY_MASK 0x3000000
1052#define CP_RB0_CNTL__CACHE_POLICY__SHIFT 0x18
1053#define CP_RB0_CNTL__RB_VOLATILE_MASK 0x4000000
1054#define CP_RB0_CNTL__RB_VOLATILE__SHIFT 0x1a
1055#define CP_RB0_CNTL__RB_NO_UPDATE_MASK 0x8000000
1056#define CP_RB0_CNTL__RB_NO_UPDATE__SHIFT 0x1b
1057#define CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000
1058#define CP_RB0_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f
1059#define CP_RB_CNTL__RB_BUFSZ_MASK 0x3f
1060#define CP_RB_CNTL__RB_BUFSZ__SHIFT 0x0
1061#define CP_RB_CNTL__RB_BLKSZ_MASK 0x3f00
1062#define CP_RB_CNTL__RB_BLKSZ__SHIFT 0x8
1063#define CP_RB_CNTL__BUF_SWAP_MASK 0x30000
1064#define CP_RB_CNTL__BUF_SWAP__SHIFT 0x10
1065#define CP_RB_CNTL__MIN_AVAILSZ_MASK 0x300000
1066#define CP_RB_CNTL__MIN_AVAILSZ__SHIFT 0x14
1067#define CP_RB_CNTL__MIN_IB_AVAILSZ_MASK 0xc00000
1068#define CP_RB_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16
1069#define CP_RB_CNTL__CACHE_POLICY_MASK 0x3000000
1070#define CP_RB_CNTL__CACHE_POLICY__SHIFT 0x18
1071#define CP_RB_CNTL__RB_VOLATILE_MASK 0x4000000
1072#define CP_RB_CNTL__RB_VOLATILE__SHIFT 0x1a
1073#define CP_RB_CNTL__RB_NO_UPDATE_MASK 0x8000000
1074#define CP_RB_CNTL__RB_NO_UPDATE__SHIFT 0x1b
1075#define CP_RB_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000
1076#define CP_RB_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f
1077#define CP_RB1_CNTL__RB_BUFSZ_MASK 0x3f
1078#define CP_RB1_CNTL__RB_BUFSZ__SHIFT 0x0
1079#define CP_RB1_CNTL__RB_BLKSZ_MASK 0x3f00
1080#define CP_RB1_CNTL__RB_BLKSZ__SHIFT 0x8
1081#define CP_RB1_CNTL__MIN_AVAILSZ_MASK 0x300000
1082#define CP_RB1_CNTL__MIN_AVAILSZ__SHIFT 0x14
1083#define CP_RB1_CNTL__MIN_IB_AVAILSZ_MASK 0xc00000
1084#define CP_RB1_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16
1085#define CP_RB1_CNTL__CACHE_POLICY_MASK 0x3000000
1086#define CP_RB1_CNTL__CACHE_POLICY__SHIFT 0x18
1087#define CP_RB1_CNTL__RB_VOLATILE_MASK 0x4000000
1088#define CP_RB1_CNTL__RB_VOLATILE__SHIFT 0x1a
1089#define CP_RB1_CNTL__RB_NO_UPDATE_MASK 0x8000000
1090#define CP_RB1_CNTL__RB_NO_UPDATE__SHIFT 0x1b
1091#define CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000
1092#define CP_RB1_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f
1093#define CP_RB2_CNTL__RB_BUFSZ_MASK 0x3f
1094#define CP_RB2_CNTL__RB_BUFSZ__SHIFT 0x0
1095#define CP_RB2_CNTL__RB_BLKSZ_MASK 0x3f00
1096#define CP_RB2_CNTL__RB_BLKSZ__SHIFT 0x8
1097#define CP_RB2_CNTL__MIN_AVAILSZ_MASK 0x300000
1098#define CP_RB2_CNTL__MIN_AVAILSZ__SHIFT 0x14
1099#define CP_RB2_CNTL__MIN_IB_AVAILSZ_MASK 0xc00000
1100#define CP_RB2_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16
1101#define CP_RB2_CNTL__CACHE_POLICY_MASK 0x3000000
1102#define CP_RB2_CNTL__CACHE_POLICY__SHIFT 0x18
1103#define CP_RB2_CNTL__RB_VOLATILE_MASK 0x4000000
1104#define CP_RB2_CNTL__RB_VOLATILE__SHIFT 0x1a
1105#define CP_RB2_CNTL__RB_NO_UPDATE_MASK 0x8000000
1106#define CP_RB2_CNTL__RB_NO_UPDATE__SHIFT 0x1b
1107#define CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000
1108#define CP_RB2_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f
1109#define CP_RB_RPTR_WR__RB_RPTR_WR_MASK 0xfffff
1110#define CP_RB_RPTR_WR__RB_RPTR_WR__SHIFT 0x0
1111#define CP_RB0_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x3
1112#define CP_RB0_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x0
1113#define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffc
1114#define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2
1115#define CP_RB_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x3
1116#define CP_RB_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x0
1117#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffc
1118#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2
1119#define CP_RB1_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x3
1120#define CP_RB1_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x0
1121#define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffc
1122#define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2
1123#define CP_RB2_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x3
1124#define CP_RB2_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x0
1125#define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffc
1126#define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2
1127#define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0xffff
1128#define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0
1129#define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0xffff
1130#define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0
1131#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0xffff
1132#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0
1133#define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0xffff
1134#define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0
1135#define CP_RB0_WPTR__RB_WPTR_MASK 0xfffff
1136#define CP_RB0_WPTR__RB_WPTR__SHIFT 0x0
1137#define CP_RB_WPTR__RB_WPTR_MASK 0xfffff
1138#define CP_RB_WPTR__RB_WPTR__SHIFT 0x0
1139#define CP_RB1_WPTR__RB_WPTR_MASK 0xfffff
1140#define CP_RB1_WPTR__RB_WPTR__SHIFT 0x0
1141#define CP_RB2_WPTR__RB_WPTR_MASK 0xfffff
1142#define CP_RB2_WPTR__RB_WPTR__SHIFT 0x0
1143#define CP_RB_WPTR_POLL_ADDR_LO__OBSOLETE_MASK 0xfffffffc
1144#define CP_RB_WPTR_POLL_ADDR_LO__OBSOLETE__SHIFT 0x2
1145#define CP_RB_WPTR_POLL_ADDR_HI__OBSOLETE_MASK 0xff
1146#define CP_RB_WPTR_POLL_ADDR_HI__OBSOLETE__SHIFT 0x0
1147#define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
1148#define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
1149#define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
1150#define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
1151#define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK 0x80000
1152#define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE__SHIFT 0x13
1153#define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK 0x100000
1154#define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14
1155#define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE_MASK 0x400000
1156#define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE__SHIFT 0x16
1157#define CP_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
1158#define CP_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
1159#define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
1160#define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
1161#define CP_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
1162#define CP_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
1163#define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
1164#define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
1165#define CP_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
1166#define CP_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
1167#define CP_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
1168#define CP_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
1169#define CP_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
1170#define CP_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
1171#define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
1172#define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
1173#define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
1174#define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
1175#define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK 0x80000
1176#define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE__SHIFT 0x13
1177#define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK 0x100000
1178#define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14
1179#define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK 0x400000
1180#define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE__SHIFT 0x16
1181#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK 0x800000
1182#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE__SHIFT 0x17
1183#define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
1184#define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
1185#define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK 0x4000000
1186#define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
1187#define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
1188#define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
1189#define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE_MASK 0x20000000
1190#define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE__SHIFT 0x1d
1191#define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE_MASK 0x40000000
1192#define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE__SHIFT 0x1e
1193#define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE_MASK 0x80000000
1194#define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE__SHIFT 0x1f
1195#define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
1196#define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
1197#define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
1198#define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
1199#define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE_MASK 0x80000
1200#define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE__SHIFT 0x13
1201#define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE_MASK 0x100000
1202#define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14
1203#define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE_MASK 0x400000
1204#define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE__SHIFT 0x16
1205#define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE_MASK 0x800000
1206#define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE__SHIFT 0x17
1207#define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
1208#define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
1209#define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK 0x4000000
1210#define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
1211#define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
1212#define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
1213#define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE_MASK 0x20000000
1214#define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE__SHIFT 0x1d
1215#define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE_MASK 0x40000000
1216#define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE__SHIFT 0x1e
1217#define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE_MASK 0x80000000
1218#define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE__SHIFT 0x1f
1219#define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
1220#define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
1221#define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
1222#define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
1223#define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE_MASK 0x80000
1224#define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE__SHIFT 0x13
1225#define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE_MASK 0x100000
1226#define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14
1227#define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE_MASK 0x400000
1228#define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE__SHIFT 0x16
1229#define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE_MASK 0x800000
1230#define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE__SHIFT 0x17
1231#define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
1232#define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
1233#define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK 0x4000000
1234#define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
1235#define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
1236#define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
1237#define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE_MASK 0x20000000
1238#define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE__SHIFT 0x1d
1239#define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE_MASK 0x40000000
1240#define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE__SHIFT 0x1e
1241#define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE_MASK 0x80000000
1242#define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE__SHIFT 0x1f
1243#define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT_MASK 0x4000
1244#define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT__SHIFT 0xe
1245#define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x20000
1246#define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11
1247#define CP_INT_STATUS__CNTX_BUSY_INT_STAT_MASK 0x80000
1248#define CP_INT_STATUS__CNTX_BUSY_INT_STAT__SHIFT 0x13
1249#define CP_INT_STATUS__CNTX_EMPTY_INT_STAT_MASK 0x100000
1250#define CP_INT_STATUS__CNTX_EMPTY_INT_STAT__SHIFT 0x14
1251#define CP_INT_STATUS__PRIV_INSTR_INT_STAT_MASK 0x400000
1252#define CP_INT_STATUS__PRIV_INSTR_INT_STAT__SHIFT 0x16
1253#define CP_INT_STATUS__PRIV_REG_INT_STAT_MASK 0x800000
1254#define CP_INT_STATUS__PRIV_REG_INT_STAT__SHIFT 0x17
1255#define CP_INT_STATUS__OPCODE_ERROR_INT_STAT_MASK 0x1000000
1256#define CP_INT_STATUS__OPCODE_ERROR_INT_STAT__SHIFT 0x18
1257#define CP_INT_STATUS__TIME_STAMP_INT_STAT_MASK 0x4000000
1258#define CP_INT_STATUS__TIME_STAMP_INT_STAT__SHIFT 0x1a
1259#define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT_MASK 0x8000000
1260#define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b
1261#define CP_INT_STATUS__GENERIC2_INT_STAT_MASK 0x20000000
1262#define CP_INT_STATUS__GENERIC2_INT_STAT__SHIFT 0x1d
1263#define CP_INT_STATUS__GENERIC1_INT_STAT_MASK 0x40000000
1264#define CP_INT_STATUS__GENERIC1_INT_STAT__SHIFT 0x1e
1265#define CP_INT_STATUS__GENERIC0_INT_STAT_MASK 0x80000000
1266#define CP_INT_STATUS__GENERIC0_INT_STAT__SHIFT 0x1f
1267#define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT_MASK 0x4000
1268#define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT__SHIFT 0xe
1269#define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x20000
1270#define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11
1271#define CP_INT_STATUS_RING0__CNTX_BUSY_INT_STAT_MASK 0x80000
1272#define CP_INT_STATUS_RING0__CNTX_BUSY_INT_STAT__SHIFT 0x13
1273#define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT_MASK 0x100000
1274#define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT__SHIFT 0x14
1275#define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT_MASK 0x400000
1276#define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT__SHIFT 0x16
1277#define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT_MASK 0x800000
1278#define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT__SHIFT 0x17
1279#define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT_MASK 0x1000000
1280#define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT__SHIFT 0x18
1281#define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT_MASK 0x4000000
1282#define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT__SHIFT 0x1a
1283#define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT_MASK 0x8000000
1284#define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b
1285#define CP_INT_STATUS_RING0__GENERIC2_INT_STAT_MASK 0x20000000
1286#define CP_INT_STATUS_RING0__GENERIC2_INT_STAT__SHIFT 0x1d
1287#define CP_INT_STATUS_RING0__GENERIC1_INT_STAT_MASK 0x40000000
1288#define CP_INT_STATUS_RING0__GENERIC1_INT_STAT__SHIFT 0x1e
1289#define CP_INT_STATUS_RING0__GENERIC0_INT_STAT_MASK 0x80000000
1290#define CP_INT_STATUS_RING0__GENERIC0_INT_STAT__SHIFT 0x1f
1291#define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT_MASK 0x4000
1292#define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT__SHIFT 0xe
1293#define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x20000
1294#define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11
1295#define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT_MASK 0x80000
1296#define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT__SHIFT 0x13
1297#define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT_MASK 0x100000
1298#define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT__SHIFT 0x14
1299#define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT_MASK 0x400000
1300#define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT__SHIFT 0x16
1301#define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT_MASK 0x800000
1302#define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT__SHIFT 0x17
1303#define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT_MASK 0x1000000
1304#define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT__SHIFT 0x18
1305#define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT_MASK 0x4000000
1306#define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT__SHIFT 0x1a
1307#define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT_MASK 0x8000000
1308#define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b
1309#define CP_INT_STATUS_RING1__GENERIC2_INT_STAT_MASK 0x20000000
1310#define CP_INT_STATUS_RING1__GENERIC2_INT_STAT__SHIFT 0x1d
1311#define CP_INT_STATUS_RING1__GENERIC1_INT_STAT_MASK 0x40000000
1312#define CP_INT_STATUS_RING1__GENERIC1_INT_STAT__SHIFT 0x1e
1313#define CP_INT_STATUS_RING1__GENERIC0_INT_STAT_MASK 0x80000000
1314#define CP_INT_STATUS_RING1__GENERIC0_INT_STAT__SHIFT 0x1f
1315#define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT_MASK 0x4000
1316#define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT__SHIFT 0xe
1317#define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x20000
1318#define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11
1319#define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT_MASK 0x80000
1320#define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT__SHIFT 0x13
1321#define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT_MASK 0x100000
1322#define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT__SHIFT 0x14
1323#define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT_MASK 0x400000
1324#define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT__SHIFT 0x16
1325#define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT_MASK 0x800000
1326#define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT__SHIFT 0x17
1327#define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT_MASK 0x1000000
1328#define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT__SHIFT 0x18
1329#define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT_MASK 0x4000000
1330#define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT__SHIFT 0x1a
1331#define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT_MASK 0x8000000
1332#define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b
1333#define CP_INT_STATUS_RING2__GENERIC2_INT_STAT_MASK 0x20000000
1334#define CP_INT_STATUS_RING2__GENERIC2_INT_STAT__SHIFT 0x1d
1335#define CP_INT_STATUS_RING2__GENERIC1_INT_STAT_MASK 0x40000000
1336#define CP_INT_STATUS_RING2__GENERIC1_INT_STAT__SHIFT 0x1e
1337#define CP_INT_STATUS_RING2__GENERIC0_INT_STAT_MASK 0x80000000
1338#define CP_INT_STATUS_RING2__GENERIC0_INT_STAT__SHIFT 0x1f
1339#define CP_DEVICE_ID__DEVICE_ID_MASK 0xff
1340#define CP_DEVICE_ID__DEVICE_ID__SHIFT 0x0
1341#define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0xff
1342#define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0
1343#define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0xff00
1344#define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8
1345#define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0xff0000
1346#define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10
1347#define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000
1348#define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18
1349#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0xff
1350#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0
1351#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0xff00
1352#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8
1353#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0xff0000
1354#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10
1355#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000
1356#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18
1357#define CP_RING0_PRIORITY__PRIORITY_MASK 0x3
1358#define CP_RING0_PRIORITY__PRIORITY__SHIFT 0x0
1359#define CP_ME0_PIPE0_PRIORITY__PRIORITY_MASK 0x3
1360#define CP_ME0_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0
1361#define CP_RING1_PRIORITY__PRIORITY_MASK 0x3
1362#define CP_RING1_PRIORITY__PRIORITY__SHIFT 0x0
1363#define CP_ME0_PIPE1_PRIORITY__PRIORITY_MASK 0x3
1364#define CP_ME0_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0
1365#define CP_RING2_PRIORITY__PRIORITY_MASK 0x3
1366#define CP_RING2_PRIORITY__PRIORITY__SHIFT 0x0
1367#define CP_ME0_PIPE2_PRIORITY__PRIORITY_MASK 0x3
1368#define CP_ME0_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0
1369#define CP_ENDIAN_SWAP__ENDIAN_SWAP_MASK 0x3
1370#define CP_ENDIAN_SWAP__ENDIAN_SWAP__SHIFT 0x0
1371#define CP_RB_VMID__RB0_VMID_MASK 0xf
1372#define CP_RB_VMID__RB0_VMID__SHIFT 0x0
1373#define CP_RB_VMID__RB1_VMID_MASK 0xf00
1374#define CP_RB_VMID__RB1_VMID__SHIFT 0x8
1375#define CP_RB_VMID__RB2_VMID_MASK 0xf0000
1376#define CP_RB_VMID__RB2_VMID__SHIFT 0x10
1377#define CP_ME0_PIPE0_VMID__VMID_MASK 0xf
1378#define CP_ME0_PIPE0_VMID__VMID__SHIFT 0x0
1379#define CP_ME0_PIPE1_VMID__VMID_MASK 0xf
1380#define CP_ME0_PIPE1_VMID__VMID__SHIFT 0x0
1381#define CP_PFP_UCODE_ADDR__UCODE_ADDR_MASK 0xfff
1382#define CP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
1383#define CP_PFP_UCODE_DATA__UCODE_DATA_MASK 0xffffffff
1384#define CP_PFP_UCODE_DATA__UCODE_DATA__SHIFT 0x0
1385#define CP_ME_RAM_RADDR__ME_RAM_RADDR_MASK 0xfff
1386#define CP_ME_RAM_RADDR__ME_RAM_RADDR__SHIFT 0x0
1387#define CP_ME_RAM_WADDR__ME_RAM_WADDR_MASK 0xfff
1388#define CP_ME_RAM_WADDR__ME_RAM_WADDR__SHIFT 0x0
1389#define CP_ME_RAM_DATA__ME_RAM_DATA_MASK 0xffffffff
1390#define CP_ME_RAM_DATA__ME_RAM_DATA__SHIFT 0x0
1391#define CGTT_CPC_CLK_CTRL__ON_DELAY_MASK 0xf
1392#define CGTT_CPC_CLK_CTRL__ON_DELAY__SHIFT 0x0
1393#define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
1394#define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
1395#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000
1396#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
1397#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000
1398#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
1399#define CGTT_CPF_CLK_CTRL__ON_DELAY_MASK 0xf
1400#define CGTT_CPF_CLK_CTRL__ON_DELAY__SHIFT 0x0
1401#define CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
1402#define CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
1403#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000
1404#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
1405#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000
1406#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
1407#define CGTT_CP_CLK_CTRL__ON_DELAY_MASK 0xf
1408#define CGTT_CP_CLK_CTRL__ON_DELAY__SHIFT 0x0
1409#define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
1410#define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
1411#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000
1412#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
1413#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000
1414#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
1415#define CP_CE_UCODE_ADDR__UCODE_ADDR_MASK 0xfff
1416#define CP_CE_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
1417#define CP_CE_UCODE_DATA__UCODE_DATA_MASK 0xffffffff
1418#define CP_CE_UCODE_DATA__UCODE_DATA__SHIFT 0x0
1419#define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR_MASK 0x1fff
1420#define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
1421#define CP_MEC_ME1_UCODE_DATA__UCODE_DATA_MASK 0xffffffff
1422#define CP_MEC_ME1_UCODE_DATA__UCODE_DATA__SHIFT 0x0
1423#define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR_MASK 0x1fff
1424#define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
1425#define CP_MEC_ME2_UCODE_DATA__UCODE_DATA_MASK 0xffffffff
1426#define CP_MEC_ME2_UCODE_DATA__UCODE_DATA__SHIFT 0x0
1427#define CP_PFP_F32_INTERRUPT__PRIV_REG_INT_MASK 0x2
1428#define CP_PFP_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1
1429#define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT_MASK 0x2
1430#define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1
1431#define CP_MEC2_F32_INTERRUPT__PRIV_REG_INT_MASK 0x2
1432#define CP_MEC2_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1
1433#define CP_PWR_CNTL__GFX_CLK_HALT_MASK 0x1
1434#define CP_PWR_CNTL__GFX_CLK_HALT__SHIFT 0x0
1435#define CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK 0x1
1436#define CP_MEM_SLP_CNTL__CP_MEM_LS_EN__SHIFT 0x0
1437#define CP_MEM_SLP_CNTL__CP_MEM_DS_EN_MASK 0x2
1438#define CP_MEM_SLP_CNTL__CP_MEM_DS_EN__SHIFT 0x1
1439#define CP_MEM_SLP_CNTL__RESERVED_MASK 0xfc
1440#define CP_MEM_SLP_CNTL__RESERVED__SHIFT 0x2
1441#define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY_MASK 0xff00
1442#define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY__SHIFT 0x8
1443#define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY_MASK 0xff0000
1444#define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY__SHIFT 0x10
1445#define CP_MEM_SLP_CNTL__RESERVED1_MASK 0xff000000
1446#define CP_MEM_SLP_CNTL__RESERVED1__SHIFT 0x18
1447#define CP_ECC_FIRSTOCCURRENCE__INTERFACE_MASK 0x3
1448#define CP_ECC_FIRSTOCCURRENCE__INTERFACE__SHIFT 0x0
1449#define CP_ECC_FIRSTOCCURRENCE__REQUEST_CLIENT_MASK 0xf0
1450#define CP_ECC_FIRSTOCCURRENCE__REQUEST_CLIENT__SHIFT 0x4
1451#define CP_ECC_FIRSTOCCURRENCE__RING_ID_MASK 0x3c00
1452#define CP_ECC_FIRSTOCCURRENCE__RING_ID__SHIFT 0xa
1453#define CP_ECC_FIRSTOCCURRENCE__VMID_MASK 0xf0000
1454#define CP_ECC_FIRSTOCCURRENCE__VMID__SHIFT 0x10
1455#define CP_ECC_FIRSTOCCURRENCE_RING0__INTERFACE_MASK 0x3
1456#define CP_ECC_FIRSTOCCURRENCE_RING0__INTERFACE__SHIFT 0x0
1457#define CP_ECC_FIRSTOCCURRENCE_RING0__REQUEST_CLIENT_MASK 0xf0
1458#define CP_ECC_FIRSTOCCURRENCE_RING0__REQUEST_CLIENT__SHIFT 0x4
1459#define CP_ECC_FIRSTOCCURRENCE_RING0__RING_ID_MASK 0x3c00
1460#define CP_ECC_FIRSTOCCURRENCE_RING0__RING_ID__SHIFT 0xa
1461#define CP_ECC_FIRSTOCCURRENCE_RING0__VMID_MASK 0xf0000
1462#define CP_ECC_FIRSTOCCURRENCE_RING0__VMID__SHIFT 0x10
1463#define CP_ECC_FIRSTOCCURRENCE_RING1__INTERFACE_MASK 0x3
1464#define CP_ECC_FIRSTOCCURRENCE_RING1__INTERFACE__SHIFT 0x0
1465#define CP_ECC_FIRSTOCCURRENCE_RING1__REQUEST_CLIENT_MASK 0xf0
1466#define CP_ECC_FIRSTOCCURRENCE_RING1__REQUEST_CLIENT__SHIFT 0x4
1467#define CP_ECC_FIRSTOCCURRENCE_RING1__RING_ID_MASK 0x3c00
1468#define CP_ECC_FIRSTOCCURRENCE_RING1__RING_ID__SHIFT 0xa
1469#define CP_ECC_FIRSTOCCURRENCE_RING1__VMID_MASK 0xf0000
1470#define CP_ECC_FIRSTOCCURRENCE_RING1__VMID__SHIFT 0x10
1471#define CP_ECC_FIRSTOCCURRENCE_RING2__INTERFACE_MASK 0x3
1472#define CP_ECC_FIRSTOCCURRENCE_RING2__INTERFACE__SHIFT 0x0
1473#define CP_ECC_FIRSTOCCURRENCE_RING2__REQUEST_CLIENT_MASK 0xf0
1474#define CP_ECC_FIRSTOCCURRENCE_RING2__REQUEST_CLIENT__SHIFT 0x4
1475#define CP_ECC_FIRSTOCCURRENCE_RING2__RING_ID_MASK 0x3c00
1476#define CP_ECC_FIRSTOCCURRENCE_RING2__RING_ID__SHIFT 0xa
1477#define CP_ECC_FIRSTOCCURRENCE_RING2__VMID_MASK 0xf0000
1478#define CP_ECC_FIRSTOCCURRENCE_RING2__VMID__SHIFT 0x10
1479#define CP_FETCHER_SOURCE__ME_SRC_MASK 0x1
1480#define CP_FETCHER_SOURCE__ME_SRC__SHIFT 0x0
1481#define CP_PQ_WPTR_POLL_CNTL__PERIOD_MASK 0xff
1482#define CP_PQ_WPTR_POLL_CNTL__PERIOD__SHIFT 0x0
1483#define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE_MASK 0x40000000
1484#define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE__SHIFT 0x1e
1485#define CP_PQ_WPTR_POLL_CNTL__EN_MASK 0x80000000
1486#define CP_PQ_WPTR_POLL_CNTL__EN__SHIFT 0x1f
1487#define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK_MASK 0xffffffff
1488#define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK__SHIFT 0x0
1489#define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
1490#define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
1491#define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
1492#define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
1493#define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
1494#define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
1495#define CPC_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
1496#define CPC_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
1497#define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
1498#define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
1499#define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
1500#define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
1501#define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
1502#define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
1503#define CPC_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
1504#define CPC_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
1505#define CPC_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
1506#define CPC_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
1507#define CPC_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
1508#define CPC_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
1509#define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
1510#define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
1511#define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
1512#define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
1513#define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
1514#define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
1515#define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
1516#define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
1517#define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
1518#define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
1519#define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
1520#define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
1521#define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
1522#define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
1523#define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
1524#define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
1525#define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
1526#define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
1527#define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
1528#define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
1529#define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
1530#define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
1531#define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
1532#define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
1533#define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
1534#define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
1535#define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
1536#define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
1537#define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
1538#define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
1539#define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
1540#define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
1541#define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
1542#define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
1543#define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
1544#define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
1545#define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
1546#define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
1547#define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
1548#define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
1549#define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
1550#define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
1551#define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
1552#define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
1553#define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
1554#define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
1555#define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
1556#define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
1557#define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
1558#define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
1559#define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
1560#define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
1561#define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
1562#define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
1563#define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
1564#define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
1565#define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
1566#define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
1567#define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
1568#define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
1569#define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
1570#define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
1571#define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
1572#define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
1573#define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
1574#define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
1575#define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
1576#define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
1577#define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
1578#define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
1579#define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
1580#define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
1581#define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
1582#define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
1583#define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
1584#define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
1585#define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
1586#define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
1587#define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
1588#define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
1589#define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
1590#define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
1591#define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
1592#define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
1593#define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
1594#define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
1595#define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
1596#define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
1597#define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
1598#define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
1599#define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
1600#define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
1601#define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
1602#define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
1603#define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
1604#define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
1605#define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
1606#define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
1607#define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
1608#define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
1609#define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
1610#define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
1611#define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
1612#define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
1613#define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
1614#define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
1615#define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
1616#define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
1617#define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
1618#define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
1619#define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
1620#define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
1621#define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
1622#define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
1623#define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
1624#define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
1625#define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
1626#define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
1627#define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
1628#define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
1629#define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
1630#define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
1631#define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
1632#define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
1633#define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
1634#define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
1635#define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
1636#define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
1637#define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
1638#define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
1639#define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
1640#define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
1641#define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
1642#define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
1643#define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
1644#define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
1645#define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
1646#define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
1647#define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
1648#define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
1649#define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
1650#define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
1651#define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
1652#define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
1653#define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
1654#define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
1655#define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
1656#define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
1657#define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
1658#define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
1659#define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
1660#define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
1661#define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
1662#define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
1663#define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
1664#define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
1665#define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
1666#define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
1667#define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
1668#define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
1669#define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
1670#define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
1671#define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
1672#define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
1673#define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
1674#define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
1675#define CPC_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
1676#define CPC_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
1677#define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
1678#define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
1679#define CPC_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
1680#define CPC_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
1681#define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
1682#define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
1683#define CPC_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
1684#define CPC_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
1685#define CPC_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
1686#define CPC_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
1687#define CPC_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
1688#define CPC_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
1689#define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
1690#define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
1691#define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
1692#define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
1693#define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
1694#define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
1695#define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
1696#define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
1697#define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
1698#define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
1699#define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
1700#define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
1701#define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
1702#define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
1703#define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
1704#define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
1705#define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
1706#define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
1707#define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
1708#define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
1709#define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
1710#define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
1711#define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
1712#define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
1713#define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
1714#define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
1715#define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
1716#define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
1717#define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
1718#define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
1719#define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
1720#define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
1721#define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
1722#define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
1723#define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
1724#define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
1725#define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
1726#define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
1727#define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
1728#define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
1729#define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
1730#define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
1731#define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
1732#define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
1733#define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
1734#define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
1735#define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
1736#define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
1737#define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
1738#define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
1739#define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
1740#define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
1741#define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
1742#define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
1743#define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
1744#define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
1745#define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
1746#define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
1747#define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
1748#define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
1749#define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
1750#define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
1751#define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
1752#define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
1753#define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
1754#define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
1755#define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
1756#define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
1757#define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
1758#define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
1759#define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
1760#define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
1761#define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
1762#define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
1763#define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
1764#define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
1765#define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
1766#define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
1767#define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
1768#define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
1769#define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
1770#define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
1771#define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
1772#define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
1773#define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
1774#define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
1775#define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
1776#define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
1777#define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
1778#define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
1779#define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
1780#define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
1781#define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
1782#define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
1783#define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
1784#define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
1785#define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
1786#define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
1787#define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
1788#define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
1789#define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
1790#define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
1791#define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
1792#define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
1793#define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
1794#define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
1795#define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
1796#define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
1797#define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
1798#define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
1799#define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
1800#define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
1801#define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
1802#define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
1803#define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
1804#define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
1805#define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
1806#define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
1807#define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
1808#define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
1809#define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
1810#define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
1811#define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
1812#define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
1813#define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
1814#define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
1815#define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
1816#define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
1817#define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
1818#define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
1819#define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
1820#define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
1821#define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
1822#define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
1823#define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
1824#define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
1825#define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
1826#define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
1827#define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
1828#define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
1829#define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
1830#define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
1831#define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
1832#define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
1833#define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
1834#define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
1835#define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
1836#define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
1837#define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
1838#define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
1839#define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
1840#define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
1841#define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
1842#define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
1843#define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
1844#define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
1845#define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
1846#define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
1847#define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
1848#define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
1849#define CP_ME1_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED_MASK 0x2000
1850#define CP_ME1_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED__SHIFT 0xd
1851#define CP_ME1_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x4000
1852#define CP_ME1_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0xe
1853#define CP_ME1_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x20000
1854#define CP_ME1_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x11
1855#define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x800000
1856#define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17
1857#define CP_ME1_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x1000000
1858#define CP_ME1_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x18
1859#define CP_ME1_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x4000000
1860#define CP_ME1_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x1a
1861#define CP_ME1_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x8000000
1862#define CP_ME1_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x1b
1863#define CP_ME1_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000
1864#define CP_ME1_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d
1865#define CP_ME1_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000
1866#define CP_ME1_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x1e
1867#define CP_ME1_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000
1868#define CP_ME1_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x1f
1869#define CP_ME2_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED_MASK 0x2000
1870#define CP_ME2_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED__SHIFT 0xd
1871#define CP_ME2_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x4000
1872#define CP_ME2_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0xe
1873#define CP_ME2_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x20000
1874#define CP_ME2_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x11
1875#define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x800000
1876#define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17
1877#define CP_ME2_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x1000000
1878#define CP_ME2_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x18
1879#define CP_ME2_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x4000000
1880#define CP_ME2_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x1a
1881#define CP_ME2_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x8000000
1882#define CP_ME2_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x1b
1883#define CP_ME2_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000
1884#define CP_ME2_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d
1885#define CP_ME2_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000
1886#define CP_ME2_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x1e
1887#define CP_ME2_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000
1888#define CP_ME2_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x1f
1889#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0xff
1890#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0
1891#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0xff00
1892#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8
1893#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0xff0000
1894#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10
1895#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000
1896#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18
1897#define CP_ME1_PIPE0_PRIORITY__PRIORITY_MASK 0x3
1898#define CP_ME1_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0
1899#define CP_ME1_PIPE1_PRIORITY__PRIORITY_MASK 0x3
1900#define CP_ME1_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0
1901#define CP_ME1_PIPE2_PRIORITY__PRIORITY_MASK 0x3
1902#define CP_ME1_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0
1903#define CP_ME1_PIPE3_PRIORITY__PRIORITY_MASK 0x3
1904#define CP_ME1_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0
1905#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0xff
1906#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0
1907#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0xff00
1908#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8
1909#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0xff0000
1910#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10
1911#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000
1912#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18
1913#define CP_ME2_PIPE0_PRIORITY__PRIORITY_MASK 0x3
1914#define CP_ME2_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0
1915#define CP_ME2_PIPE1_PRIORITY__PRIORITY_MASK 0x3
1916#define CP_ME2_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0
1917#define CP_ME2_PIPE2_PRIORITY__PRIORITY_MASK 0x3
1918#define CP_ME2_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0
1919#define CP_ME2_PIPE3_PRIORITY__PRIORITY_MASK 0x3
1920#define CP_ME2_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0
1921#define CP_CE_PRGRM_CNTR_START__IP_START_MASK 0x7ff
1922#define CP_CE_PRGRM_CNTR_START__IP_START__SHIFT 0x0
1923#define CP_PFP_PRGRM_CNTR_START__IP_START_MASK 0x7ff
1924#define CP_PFP_PRGRM_CNTR_START__IP_START__SHIFT 0x0
1925#define CP_ME_PRGRM_CNTR_START__IP_START_MASK 0x7ff
1926#define CP_ME_PRGRM_CNTR_START__IP_START__SHIFT 0x0
1927#define CP_MEC1_PRGRM_CNTR_START__IP_START_MASK 0xfff
1928#define CP_MEC1_PRGRM_CNTR_START__IP_START__SHIFT 0x0
1929#define CP_MEC2_PRGRM_CNTR_START__IP_START_MASK 0xfff
1930#define CP_MEC2_PRGRM_CNTR_START__IP_START__SHIFT 0x0
1931#define CP_CE_INTR_ROUTINE_START__IR_START_MASK 0x7ff
1932#define CP_CE_INTR_ROUTINE_START__IR_START__SHIFT 0x0
1933#define CP_PFP_INTR_ROUTINE_START__IR_START_MASK 0x7ff
1934#define CP_PFP_INTR_ROUTINE_START__IR_START__SHIFT 0x0
1935#define CP_ME_INTR_ROUTINE_START__IR_START_MASK 0x7ff
1936#define CP_ME_INTR_ROUTINE_START__IR_START__SHIFT 0x0
1937#define CP_MEC1_INTR_ROUTINE_START__IR_START_MASK 0xfff
1938#define CP_MEC1_INTR_ROUTINE_START__IR_START__SHIFT 0x0
1939#define CP_MEC2_INTR_ROUTINE_START__IR_START_MASK 0xfff
1940#define CP_MEC2_INTR_ROUTINE_START__IR_START__SHIFT 0x0
1941#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_WD_CNTX_MASK 0x7
1942#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_WD_CNTX__SHIFT 0x0
1943#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX_MASK 0x70
1944#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX__SHIFT 0x4
1945#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_WD_CNTX_MASK 0x70000
1946#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_WD_CNTX__SHIFT 0x10
1947#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX_MASK 0x700000
1948#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX__SHIFT 0x14
1949#define CP_MAX_CONTEXT__MAX_CONTEXT_MASK 0x7
1950#define CP_MAX_CONTEXT__MAX_CONTEXT__SHIFT 0x0
1951#define CP_IQ_WAIT_TIME1__IB_OFFLOAD_MASK 0xff
1952#define CP_IQ_WAIT_TIME1__IB_OFFLOAD__SHIFT 0x0
1953#define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD_MASK 0xff00
1954#define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD__SHIFT 0x8
1955#define CP_IQ_WAIT_TIME1__WRM_OFFLOAD_MASK 0xff0000
1956#define CP_IQ_WAIT_TIME1__WRM_OFFLOAD__SHIFT 0x10
1957#define CP_IQ_WAIT_TIME1__GWS_MASK 0xff000000
1958#define CP_IQ_WAIT_TIME1__GWS__SHIFT 0x18
1959#define CP_IQ_WAIT_TIME2__QUE_SLEEP_MASK 0xff
1960#define CP_IQ_WAIT_TIME2__QUE_SLEEP__SHIFT 0x0
1961#define CP_IQ_WAIT_TIME2__SCH_WAVE_MASK 0xff00
1962#define CP_IQ_WAIT_TIME2__SCH_WAVE__SHIFT 0x8
1963#define CP_IQ_WAIT_TIME2__SEM_REARM_MASK 0xff0000
1964#define CP_IQ_WAIT_TIME2__SEM_REARM__SHIFT 0x10
1965#define CP_IQ_WAIT_TIME2__DEQ_RETRY_MASK 0xff000000
1966#define CP_IQ_WAIT_TIME2__DEQ_RETRY__SHIFT 0x18
1967#define CP_VMID_RESET__RESET_REQUEST_MASK 0xffff
1968#define CP_VMID_RESET__RESET_REQUEST__SHIFT 0x0
1969#define CP_VMID_RESET__RESET_STATUS_MASK 0xffff0000
1970#define CP_VMID_RESET__RESET_STATUS__SHIFT 0x10
1971#define CP_VMID_PREEMPT__PREEMPT_REQUEST_MASK 0xffff
1972#define CP_VMID_PREEMPT__PREEMPT_REQUEST__SHIFT 0x0
1973#define CP_VMID_PREEMPT__PREEMPT_STATUS_MASK 0xffff0000
1974#define CP_VMID_PREEMPT__PREEMPT_STATUS__SHIFT 0x10
1975#define CPC_INT_CNTX_ID__CNTX_ID_MASK 0xffff
1976#define CPC_INT_CNTX_ID__CNTX_ID__SHIFT 0x0
1977#define CP_PQ_STATUS__DOORBELL_UPDATED_MASK 0x1
1978#define CP_PQ_STATUS__DOORBELL_UPDATED__SHIFT 0x0
1979#define CP_PQ_STATUS__DOORBELL_ENABLE_MASK 0x2
1980#define CP_PQ_STATUS__DOORBELL_ENABLE__SHIFT 0x1
1981#define CP_CPC_STATUS__MEC1_BUSY_MASK 0x1
1982#define CP_CPC_STATUS__MEC1_BUSY__SHIFT 0x0
1983#define CP_CPC_STATUS__MEC2_BUSY_MASK 0x2
1984#define CP_CPC_STATUS__MEC2_BUSY__SHIFT 0x1
1985#define CP_CPC_STATUS__DC0_BUSY_MASK 0x4
1986#define CP_CPC_STATUS__DC0_BUSY__SHIFT 0x2
1987#define CP_CPC_STATUS__DC1_BUSY_MASK 0x8
1988#define CP_CPC_STATUS__DC1_BUSY__SHIFT 0x3
1989#define CP_CPC_STATUS__RCIU1_BUSY_MASK 0x10
1990#define CP_CPC_STATUS__RCIU1_BUSY__SHIFT 0x4
1991#define CP_CPC_STATUS__RCIU2_BUSY_MASK 0x20
1992#define CP_CPC_STATUS__RCIU2_BUSY__SHIFT 0x5
1993#define CP_CPC_STATUS__ROQ1_BUSY_MASK 0x40
1994#define CP_CPC_STATUS__ROQ1_BUSY__SHIFT 0x6
1995#define CP_CPC_STATUS__ROQ2_BUSY_MASK 0x80
1996#define CP_CPC_STATUS__ROQ2_BUSY__SHIFT 0x7
1997#define CP_CPC_STATUS__MIU_RDREQ_BUSY_MASK 0x100
1998#define CP_CPC_STATUS__MIU_RDREQ_BUSY__SHIFT 0x8
1999#define CP_CPC_STATUS__MIU_WRREQ_BUSY_MASK 0x200
2000#define CP_CPC_STATUS__MIU_WRREQ_BUSY__SHIFT 0x9
2001#define CP_CPC_STATUS__TCIU_BUSY_MASK 0x400
2002#define CP_CPC_STATUS__TCIU_BUSY__SHIFT 0xa
2003#define CP_CPC_STATUS__SCRATCH_RAM_BUSY_MASK 0x800
2004#define CP_CPC_STATUS__SCRATCH_RAM_BUSY__SHIFT 0xb
2005#define CP_CPC_STATUS__QU_BUSY_MASK 0x1000
2006#define CP_CPC_STATUS__QU_BUSY__SHIFT 0xc
2007#define CP_CPC_STATUS__CPG_CPC_BUSY_MASK 0x20000000
2008#define CP_CPC_STATUS__CPG_CPC_BUSY__SHIFT 0x1d
2009#define CP_CPC_STATUS__CPF_CPC_BUSY_MASK 0x40000000
2010#define CP_CPC_STATUS__CPF_CPC_BUSY__SHIFT 0x1e
2011#define CP_CPC_STATUS__CPC_BUSY_MASK 0x80000000
2012#define CP_CPC_STATUS__CPC_BUSY__SHIFT 0x1f
2013#define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY_MASK 0x1
2014#define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY__SHIFT 0x0
2015#define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY_MASK 0x2
2016#define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY__SHIFT 0x1
2017#define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY_MASK 0x4
2018#define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY__SHIFT 0x2
2019#define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY_MASK 0x8
2020#define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY__SHIFT 0x3
2021#define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY_MASK 0x10
2022#define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY__SHIFT 0x4
2023#define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY_MASK 0x20
2024#define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY__SHIFT 0x5
2025#define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY_MASK 0x40
2026#define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY__SHIFT 0x6
2027#define CP_CPC_BUSY_STAT__MEC1_TC_BUSY_MASK 0x80
2028#define CP_CPC_BUSY_STAT__MEC1_TC_BUSY__SHIFT 0x7
2029#define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY_MASK 0x100
2030#define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY__SHIFT 0x8
2031#define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY_MASK 0x200
2032#define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY__SHIFT 0x9
2033#define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY_MASK 0x400
2034#define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY__SHIFT 0xa
2035#define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY_MASK 0x800
2036#define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY__SHIFT 0xb
2037#define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY_MASK 0x1000
2038#define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY__SHIFT 0xc
2039#define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY_MASK 0x2000
2040#define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY__SHIFT 0xd
2041#define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY_MASK 0x10000
2042#define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY__SHIFT 0x10
2043#define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY_MASK 0x20000
2044#define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY__SHIFT 0x11
2045#define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY_MASK 0x40000
2046#define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY__SHIFT 0x12
2047#define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY_MASK 0x80000
2048#define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY__SHIFT 0x13
2049#define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY_MASK 0x100000
2050#define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY__SHIFT 0x14
2051#define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY_MASK 0x200000
2052#define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY__SHIFT 0x15
2053#define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY_MASK 0x400000
2054#define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY__SHIFT 0x16
2055#define CP_CPC_BUSY_STAT__MEC2_TC_BUSY_MASK 0x800000
2056#define CP_CPC_BUSY_STAT__MEC2_TC_BUSY__SHIFT 0x17
2057#define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY_MASK 0x1000000
2058#define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY__SHIFT 0x18
2059#define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY_MASK 0x2000000
2060#define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY__SHIFT 0x19
2061#define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY_MASK 0x4000000
2062#define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY__SHIFT 0x1a
2063#define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY_MASK 0x8000000
2064#define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY__SHIFT 0x1b
2065#define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY_MASK 0x10000000
2066#define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY__SHIFT 0x1c
2067#define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY_MASK 0x20000000
2068#define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY__SHIFT 0x1d
2069#define CP_CPC_STALLED_STAT1__MIU_RDREQ_FREE_STALL_MASK 0x1
2070#define CP_CPC_STALLED_STAT1__MIU_RDREQ_FREE_STALL__SHIFT 0x0
2071#define CP_CPC_STALLED_STAT1__MIU_WRREQ_FREE_STALL_MASK 0x2
2072#define CP_CPC_STALLED_STAT1__MIU_WRREQ_FREE_STALL__SHIFT 0x1
2073#define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL_MASK 0x8
2074#define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL__SHIFT 0x3
2075#define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION_MASK 0x10
2076#define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION__SHIFT 0x4
2077#define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL_MASK 0x40
2078#define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL__SHIFT 0x6
2079#define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET_MASK 0x100
2080#define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET__SHIFT 0x8
2081#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_MASK 0x200
2082#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU__SHIFT 0x9
2083#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ_MASK 0x400
2084#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ__SHIFT 0xa
2085#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_MC_READ_MASK 0x800
2086#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_MC_READ__SHIFT 0xb
2087#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_MC_WR_ACK_MASK 0x1000
2088#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_MC_WR_ACK__SHIFT 0xc
2089#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA_MASK 0x2000
2090#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA__SHIFT 0xd
2091#define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET_MASK 0x10000
2092#define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET__SHIFT 0x10
2093#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_MASK 0x20000
2094#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU__SHIFT 0x11
2095#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ_MASK 0x40000
2096#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ__SHIFT 0x12
2097#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_MC_READ_MASK 0x80000
2098#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_MC_READ__SHIFT 0x13
2099#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_MC_WR_ACK_MASK 0x100000
2100#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_MC_WR_ACK__SHIFT 0x14
2101#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA_MASK 0x200000
2102#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA__SHIFT 0x15
2103#define CP_CPF_STATUS__POST_WPTR_GFX_BUSY_MASK 0x1
2104#define CP_CPF_STATUS__POST_WPTR_GFX_BUSY__SHIFT 0x0
2105#define CP_CPF_STATUS__CSF_BUSY_MASK 0x2
2106#define CP_CPF_STATUS__CSF_BUSY__SHIFT 0x1
2107#define CP_CPF_STATUS__MIU_RDREQ_BUSY_MASK 0x4
2108#define CP_CPF_STATUS__MIU_RDREQ_BUSY__SHIFT 0x2
2109#define CP_CPF_STATUS__MIU_WRREQ_BUSY_MASK 0x8
2110#define CP_CPF_STATUS__MIU_WRREQ_BUSY__SHIFT 0x3
2111#define CP_CPF_STATUS__ROQ_ALIGN_BUSY_MASK 0x10
2112#define CP_CPF_STATUS__ROQ_ALIGN_BUSY__SHIFT 0x4
2113#define CP_CPF_STATUS__ROQ_RING_BUSY_MASK 0x20
2114#define CP_CPF_STATUS__ROQ_RING_BUSY__SHIFT 0x5
2115#define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY_MASK 0x40
2116#define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY__SHIFT 0x6
2117#define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY_MASK 0x80
2118#define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY__SHIFT 0x7
2119#define CP_CPF_STATUS__ROQ_STATE_BUSY_MASK 0x100
2120#define CP_CPF_STATUS__ROQ_STATE_BUSY__SHIFT 0x8
2121#define CP_CPF_STATUS__ROQ_CE_RING_BUSY_MASK 0x200
2122#define CP_CPF_STATUS__ROQ_CE_RING_BUSY__SHIFT 0x9
2123#define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY_MASK 0x400
2124#define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY__SHIFT 0xa
2125#define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY_MASK 0x800
2126#define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY__SHIFT 0xb
2127#define CP_CPF_STATUS__SEMAPHORE_BUSY_MASK 0x1000
2128#define CP_CPF_STATUS__SEMAPHORE_BUSY__SHIFT 0xc
2129#define CP_CPF_STATUS__INTERRUPT_BUSY_MASK 0x2000
2130#define CP_CPF_STATUS__INTERRUPT_BUSY__SHIFT 0xd
2131#define CP_CPF_STATUS__TCIU_BUSY_MASK 0x4000
2132#define CP_CPF_STATUS__TCIU_BUSY__SHIFT 0xe
2133#define CP_CPF_STATUS__HQD_BUSY_MASK 0x8000
2134#define CP_CPF_STATUS__HQD_BUSY__SHIFT 0xf
2135#define CP_CPF_STATUS__CPC_CPF_BUSY_MASK 0x40000000
2136#define CP_CPF_STATUS__CPC_CPF_BUSY__SHIFT 0x1e
2137#define CP_CPF_STATUS__CPF_BUSY_MASK 0x80000000
2138#define CP_CPF_STATUS__CPF_BUSY__SHIFT 0x1f
2139#define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x1
2140#define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x0
2141#define CP_CPF_BUSY_STAT__CSF_RING_BUSY_MASK 0x2
2142#define CP_CPF_BUSY_STAT__CSF_RING_BUSY__SHIFT 0x1
2143#define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY_MASK 0x4
2144#define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY__SHIFT 0x2
2145#define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY_MASK 0x8
2146#define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY__SHIFT 0x3
2147#define CP_CPF_BUSY_STAT__CSF_STATE_BUSY_MASK 0x10
2148#define CP_CPF_BUSY_STAT__CSF_STATE_BUSY__SHIFT 0x4
2149#define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY_MASK 0x20
2150#define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY__SHIFT 0x5
2151#define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY_MASK 0x40
2152#define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY__SHIFT 0x6
2153#define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY_MASK 0x80
2154#define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY__SHIFT 0x7
2155#define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY_MASK 0x100
2156#define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY__SHIFT 0x8
2157#define CP_CPF_BUSY_STAT__OUTSTANDING_READ_TAGS_MASK 0x200
2158#define CP_CPF_BUSY_STAT__OUTSTANDING_READ_TAGS__SHIFT 0x9
2159#define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY_MASK 0x800
2160#define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY__SHIFT 0xb
2161#define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY_MASK 0x1000
2162#define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY__SHIFT 0xc
2163#define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY_MASK 0x2000
2164#define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY__SHIFT 0xd
2165#define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY_MASK 0x4000
2166#define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY__SHIFT 0xe
2167#define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY_MASK 0x8000
2168#define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY__SHIFT 0xf
2169#define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY_MASK 0x10000
2170#define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY__SHIFT 0x10
2171#define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY_MASK 0x20000
2172#define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY__SHIFT 0x11
2173#define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY_MASK 0x40000
2174#define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY__SHIFT 0x12
2175#define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY_MASK 0x80000
2176#define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY__SHIFT 0x13
2177#define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY_MASK 0x100000
2178#define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY__SHIFT 0x14
2179#define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY_MASK 0x200000
2180#define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY__SHIFT 0x15
2181#define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY_MASK 0x400000
2182#define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY__SHIFT 0x16
2183#define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY_MASK 0x800000
2184#define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY__SHIFT 0x17
2185#define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY_MASK 0x1000000
2186#define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY__SHIFT 0x18
2187#define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY_MASK 0x2000000
2188#define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY__SHIFT 0x19
2189#define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY_MASK 0x4000000
2190#define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY__SHIFT 0x1a
2191#define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY_MASK 0x8000000
2192#define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY__SHIFT 0x1b
2193#define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY_MASK 0x10000000
2194#define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY__SHIFT 0x1c
2195#define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY_MASK 0x20000000
2196#define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY__SHIFT 0x1d
2197#define CP_CPF_BUSY_STAT__HQD_PQ_BUSY_MASK 0x40000000
2198#define CP_CPF_BUSY_STAT__HQD_PQ_BUSY__SHIFT 0x1e
2199#define CP_CPF_BUSY_STAT__HQD_IB_BUSY_MASK 0x80000000
2200#define CP_CPF_BUSY_STAT__HQD_IB_BUSY__SHIFT 0x1f
2201#define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA_MASK 0x1
2202#define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA__SHIFT 0x0
2203#define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA_MASK 0x2
2204#define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA__SHIFT 0x1
2205#define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA_MASK 0x4
2206#define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA__SHIFT 0x2
2207#define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA_MASK 0x8
2208#define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA__SHIFT 0x3
2209#define CP_CPF_STALLED_STAT1__MIU_WAITING_ON_RDREQ_FREE_MASK 0x10
2210#define CP_CPF_STALLED_STAT1__MIU_WAITING_ON_RDREQ_FREE__SHIFT 0x4
2211#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE_MASK 0x20
2212#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE__SHIFT 0x5
2213#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS_MASK 0x40
2214#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS__SHIFT 0x6
2215#define CP_CPC_MC_CNTL__PACK_DELAY_CNT_MASK 0x1f
2216#define CP_CPC_MC_CNTL__PACK_DELAY_CNT__SHIFT 0x0
2217#define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x3f
2218#define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0
2219#define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE_MASK 0x10
2220#define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE__SHIFT 0x4
2221#define CP_MEC_CNTL__MEC_ME2_HALT_MASK 0x10000000
2222#define CP_MEC_CNTL__MEC_ME2_HALT__SHIFT 0x1c
2223#define CP_MEC_CNTL__MEC_ME2_STEP_MASK 0x20000000
2224#define CP_MEC_CNTL__MEC_ME2_STEP__SHIFT 0x1d
2225#define CP_MEC_CNTL__MEC_ME1_HALT_MASK 0x40000000
2226#define CP_MEC_CNTL__MEC_ME1_HALT__SHIFT 0x1e
2227#define CP_MEC_CNTL__MEC_ME1_STEP_MASK 0x80000000
2228#define CP_MEC_CNTL__MEC_ME1_STEP__SHIFT 0x1f
2229#define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP_MASK 0xffffffff
2230#define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP__SHIFT 0x0
2231#define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP_MASK 0xffffffff
2232#define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP__SHIFT 0x0
2233#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0xff
2234#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0
2235#define CP_CPC_SCRATCH_DATA__SCRATCH_DATA_MASK 0xffffffff
2236#define CP_CPC_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0
2237#define CPG_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f
2238#define CPG_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
2239#define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
2240#define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
2241#define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
2242#define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
2243#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3f
2244#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
2245#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xfc00
2246#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
2247#define CPG_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f
2248#define CPG_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
2249#define CPG_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xfc00
2250#define CPG_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
2251#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
2252#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
2253#define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
2254#define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
2255#define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
2256#define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
2257#define CPC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f
2258#define CPC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
2259#define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
2260#define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
2261#define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
2262#define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
2263#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3f
2264#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
2265#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xfc00
2266#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
2267#define CPC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f
2268#define CPC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
2269#define CPC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xfc00
2270#define CPC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
2271#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
2272#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
2273#define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
2274#define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
2275#define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
2276#define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
2277#define CPF_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f
2278#define CPF_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
2279#define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
2280#define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
2281#define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
2282#define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
2283#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3f
2284#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
2285#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xfc00
2286#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
2287#define CPF_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f
2288#define CPF_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
2289#define CPF_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xfc00
2290#define CPF_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
2291#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
2292#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
2293#define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
2294#define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
2295#define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
2296#define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
2297#define CP_CPC_HALT_HYST_COUNT__COUNT_MASK 0xf
2298#define CP_CPC_HALT_HYST_COUNT__COUNT__SHIFT 0x0
2299#define CP_DRAW_OBJECT__OBJECT_MASK 0xffffffff
2300#define CP_DRAW_OBJECT__OBJECT__SHIFT 0x0
2301#define CP_DRAW_OBJECT_COUNTER__COUNT_MASK 0xffff
2302#define CP_DRAW_OBJECT_COUNTER__COUNT__SHIFT 0x0
2303#define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI_MASK 0xffffffff
2304#define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI__SHIFT 0x0
2305#define CP_DRAW_WINDOW_HI__WINDOW_HI_MASK 0xffffffff
2306#define CP_DRAW_WINDOW_HI__WINDOW_HI__SHIFT 0x0
2307#define CP_DRAW_WINDOW_LO__MIN_MASK 0xffff
2308#define CP_DRAW_WINDOW_LO__MIN__SHIFT 0x0
2309#define CP_DRAW_WINDOW_LO__MAX_MASK 0xffff0000
2310#define CP_DRAW_WINDOW_LO__MAX__SHIFT 0x10
2311#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX_MASK 0x1
2312#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX__SHIFT 0x0
2313#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN_MASK 0x2
2314#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN__SHIFT 0x1
2315#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI_MASK 0x4
2316#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI__SHIFT 0x2
2317#define CP_DRAW_WINDOW_CNTL__MODE_MASK 0x100
2318#define CP_DRAW_WINDOW_CNTL__MODE__SHIFT 0x8
2319#define CP_PRT_LOD_STATS_CNTL0__BU_SIZE_MASK 0xffffffff
2320#define CP_PRT_LOD_STATS_CNTL0__BU_SIZE__SHIFT 0x0
2321#define CP_PRT_LOD_STATS_CNTL1__BASE_LO_MASK 0xffffffff
2322#define CP_PRT_LOD_STATS_CNTL1__BASE_LO__SHIFT 0x0
2323#define CP_PRT_LOD_STATS_CNTL2__BASE_HI_MASK 0x3
2324#define CP_PRT_LOD_STATS_CNTL2__BASE_HI__SHIFT 0x0
2325#define CP_PRT_LOD_STATS_CNTL2__INTERVAL_MASK 0x3fc
2326#define CP_PRT_LOD_STATS_CNTL2__INTERVAL__SHIFT 0x2
2327#define CP_PRT_LOD_STATS_CNTL2__RESET_CNT_MASK 0x3fc00
2328#define CP_PRT_LOD_STATS_CNTL2__RESET_CNT__SHIFT 0xa
2329#define CP_PRT_LOD_STATS_CNTL2__RESET_FORCE_MASK 0x40000
2330#define CP_PRT_LOD_STATS_CNTL2__RESET_FORCE__SHIFT 0x12
2331#define CP_PRT_LOD_STATS_CNTL2__REPORT_AND_RESET_MASK 0x80000
2332#define CP_PRT_LOD_STATS_CNTL2__REPORT_AND_RESET__SHIFT 0x13
2333#define CP_PRT_LOD_STATS_CNTL2__MC_ENDIAN_SWAP_MASK 0x300000
2334#define CP_PRT_LOD_STATS_CNTL2__MC_ENDIAN_SWAP__SHIFT 0x14
2335#define CP_PRT_LOD_STATS_CNTL2__MC_VMID_MASK 0x7800000
2336#define CP_PRT_LOD_STATS_CNTL2__MC_VMID__SHIFT 0x17
2337#define CP_CE_COMPARE_COUNT__COMPARE_COUNT_MASK 0xffffffff
2338#define CP_CE_COMPARE_COUNT__COMPARE_COUNT__SHIFT 0x0
2339#define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT_MASK 0xffffffff
2340#define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT 0x0
2341#define CP_DE_CE_COUNT__CONST_ENGINE_COUNT_MASK 0xffffffff
2342#define CP_DE_CE_COUNT__CONST_ENGINE_COUNT__SHIFT 0x0
2343#define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT_MASK 0xffffffff
2344#define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT__SHIFT 0x0
2345#define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT_MASK 0xffffffff
2346#define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT 0x0
2347#define CP_EOP_DONE_EVENT_CNTL__WBINV_TC_OP_MASK 0x7f
2348#define CP_EOP_DONE_EVENT_CNTL__WBINV_TC_OP__SHIFT 0x0
2349#define CP_EOP_DONE_EVENT_CNTL__WBINV_ACTION_ENA_MASK 0x3f000
2350#define CP_EOP_DONE_EVENT_CNTL__WBINV_ACTION_ENA__SHIFT 0xc
2351#define CP_EOP_DONE_EVENT_CNTL__CACHE_CONTROL_MASK 0x6000000
2352#define CP_EOP_DONE_EVENT_CNTL__CACHE_CONTROL__SHIFT 0x19
2353#define CP_EOP_DONE_EVENT_CNTL__EOP_VOLATILE_MASK 0x8000000
2354#define CP_EOP_DONE_EVENT_CNTL__EOP_VOLATILE__SHIFT 0x1b
2355#define CP_EOP_DONE_DATA_CNTL__CNTX_ID_MASK 0xffff
2356#define CP_EOP_DONE_DATA_CNTL__CNTX_ID__SHIFT 0x0
2357#define CP_EOP_DONE_DATA_CNTL__DST_SEL_MASK 0x30000
2358#define CP_EOP_DONE_DATA_CNTL__DST_SEL__SHIFT 0x10
2359#define CP_EOP_DONE_DATA_CNTL__INT_SEL_MASK 0x7000000
2360#define CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT 0x18
2361#define CP_EOP_DONE_DATA_CNTL__DATA_SEL_MASK 0xe0000000
2362#define CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT 0x1d
2363#define CP_EOP_DONE_ADDR_LO__ADDR_SWAP_MASK 0x3
2364#define CP_EOP_DONE_ADDR_LO__ADDR_SWAP__SHIFT 0x0
2365#define CP_EOP_DONE_ADDR_LO__ADDR_LO_MASK 0xfffffffc
2366#define CP_EOP_DONE_ADDR_LO__ADDR_LO__SHIFT 0x2
2367#define CP_EOP_DONE_ADDR_HI__ADDR_HI_MASK 0xffff
2368#define CP_EOP_DONE_ADDR_HI__ADDR_HI__SHIFT 0x0
2369#define CP_EOP_DONE_DATA_LO__DATA_LO_MASK 0xffffffff
2370#define CP_EOP_DONE_DATA_LO__DATA_LO__SHIFT 0x0
2371#define CP_EOP_DONE_DATA_HI__DATA_HI_MASK 0xffffffff
2372#define CP_EOP_DONE_DATA_HI__DATA_HI__SHIFT 0x0
2373#define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO_MASK 0xffffffff
2374#define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO__SHIFT 0x0
2375#define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI_MASK 0xffffffff
2376#define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI__SHIFT 0x0
2377#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_SWAP_MASK 0x3
2378#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_SWAP__SHIFT 0x0
2379#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO_MASK 0xfffffffc
2380#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO__SHIFT 0x2
2381#define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI_MASK 0xffff
2382#define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI__SHIFT 0x0
2383#define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO_MASK 0xffffffff
2384#define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO__SHIFT 0x0
2385#define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI_MASK 0xffffffff
2386#define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI__SHIFT 0x0
2387#define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO_MASK 0xffffffff
2388#define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO__SHIFT 0x0
2389#define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI_MASK 0xffffffff
2390#define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI__SHIFT 0x0
2391#define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO_MASK 0xffffffff
2392#define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO__SHIFT 0x0
2393#define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI_MASK 0xffffffff
2394#define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI__SHIFT 0x0
2395#define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO_MASK 0xffffffff
2396#define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO__SHIFT 0x0
2397#define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI_MASK 0xffffffff
2398#define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI__SHIFT 0x0
2399#define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO_MASK 0xffffffff
2400#define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO__SHIFT 0x0
2401#define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI_MASK 0xffffffff
2402#define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI__SHIFT 0x0
2403#define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO_MASK 0xffffffff
2404#define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO__SHIFT 0x0
2405#define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI_MASK 0xffffffff
2406#define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI__SHIFT 0x0
2407#define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO_MASK 0xffffffff
2408#define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO__SHIFT 0x0
2409#define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI_MASK 0xffffffff
2410#define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI__SHIFT 0x0
2411#define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO_MASK 0xffffffff
2412#define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO__SHIFT 0x0
2413#define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI_MASK 0xffffffff
2414#define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI__SHIFT 0x0
2415#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_SWAP_MASK 0x3
2416#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_SWAP__SHIFT 0x0
2417#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO_MASK 0xfffffffc
2418#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO__SHIFT 0x2
2419#define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI_MASK 0xffff
2420#define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI__SHIFT 0x0
2421#define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO_MASK 0xffffffff
2422#define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO__SHIFT 0x0
2423#define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI_MASK 0xffffffff
2424#define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI__SHIFT 0x0
2425#define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO_MASK 0xffffffff
2426#define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO__SHIFT 0x0
2427#define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI_MASK 0xffffffff
2428#define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI__SHIFT 0x0
2429#define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO_MASK 0xffffffff
2430#define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO__SHIFT 0x0
2431#define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI_MASK 0xffffffff
2432#define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI__SHIFT 0x0
2433#define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO_MASK 0xffffffff
2434#define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO__SHIFT 0x0
2435#define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI_MASK 0xffffffff
2436#define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI__SHIFT 0x0
2437#define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO_MASK 0xffffffff
2438#define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO__SHIFT 0x0
2439#define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI_MASK 0xffffffff
2440#define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI__SHIFT 0x0
2441#define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO_MASK 0xffffffff
2442#define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO__SHIFT 0x0
2443#define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI_MASK 0xffffffff
2444#define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI__SHIFT 0x0
2445#define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO_MASK 0xffffffff
2446#define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO__SHIFT 0x0
2447#define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI_MASK 0xffffffff
2448#define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI__SHIFT 0x0
2449#define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO_MASK 0xffffffff
2450#define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO__SHIFT 0x0
2451#define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI_MASK 0xffffffff
2452#define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI__SHIFT 0x0
2453#define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO_MASK 0xffffffff
2454#define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO__SHIFT 0x0
2455#define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI_MASK 0xffffffff
2456#define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI__SHIFT 0x0
2457#define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO_MASK 0xffffffff
2458#define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO__SHIFT 0x0
2459#define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI_MASK 0xffffffff
2460#define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI__SHIFT 0x0
2461#define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE_MASK 0xffffffff
2462#define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE__SHIFT 0x0
2463#define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE_MASK 0xffffffff
2464#define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE__SHIFT 0x0
2465#define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO_MASK 0xffffffff
2466#define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO__SHIFT 0x0
2467#define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI_MASK 0xffffffff
2468#define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI__SHIFT 0x0
2469#define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE_MASK 0x1
2470#define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE__SHIFT 0x0
2471#define SCRATCH_REG0__SCRATCH_REG0_MASK 0xffffffff
2472#define SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x0
2473#define SCRATCH_REG1__SCRATCH_REG1_MASK 0xffffffff
2474#define SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x0
2475#define SCRATCH_REG2__SCRATCH_REG2_MASK 0xffffffff
2476#define SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x0
2477#define SCRATCH_REG3__SCRATCH_REG3_MASK 0xffffffff
2478#define SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x0
2479#define SCRATCH_REG4__SCRATCH_REG4_MASK 0xffffffff
2480#define SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x0
2481#define SCRATCH_REG5__SCRATCH_REG5_MASK 0xffffffff
2482#define SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x0
2483#define SCRATCH_REG6__SCRATCH_REG6_MASK 0xffffffff
2484#define SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x0
2485#define SCRATCH_REG7__SCRATCH_REG7_MASK 0xffffffff
2486#define SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x0
2487#define SCRATCH_UMSK__OBSOLETE_UMSK_MASK 0xff
2488#define SCRATCH_UMSK__OBSOLETE_UMSK__SHIFT 0x0
2489#define SCRATCH_UMSK__OBSOLETE_SWAP_MASK 0x30000
2490#define SCRATCH_UMSK__OBSOLETE_SWAP__SHIFT 0x10
2491#define SCRATCH_ADDR__OBSOLETE_ADDR_MASK 0xffffffff
2492#define SCRATCH_ADDR__OBSOLETE_ADDR__SHIFT 0x0
2493#define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xffffffff
2494#define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0
2495#define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xffffffff
2496#define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0
2497#define CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xffffffff
2498#define CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0
2499#define CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xffffffff
2500#define CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0
2501#define CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xffffffff
2502#define CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0
2503#define CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xffffffff
2504#define CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0
2505#define CP_APPEND_ADDR_LO__MEM_ADDR_LO_MASK 0xfffffffc
2506#define CP_APPEND_ADDR_LO__MEM_ADDR_LO__SHIFT 0x2
2507#define CP_APPEND_ADDR_HI__MEM_ADDR_HI_MASK 0xffff
2508#define CP_APPEND_ADDR_HI__MEM_ADDR_HI__SHIFT 0x0
2509#define CP_APPEND_ADDR_HI__CS_PS_SEL_MASK 0x10000
2510#define CP_APPEND_ADDR_HI__CS_PS_SEL__SHIFT 0x10
2511#define CP_APPEND_ADDR_HI__COMMAND_MASK 0xe0000000
2512#define CP_APPEND_ADDR_HI__COMMAND__SHIFT 0x1d
2513#define CP_APPEND_DATA__DATA_MASK 0xffffffff
2514#define CP_APPEND_DATA__DATA__SHIFT 0x0
2515#define CP_APPEND_LAST_CS_FENCE__LAST_FENCE_MASK 0xffffffff
2516#define CP_APPEND_LAST_CS_FENCE__LAST_FENCE__SHIFT 0x0
2517#define CP_APPEND_LAST_PS_FENCE__LAST_FENCE_MASK 0xffffffff
2518#define CP_APPEND_LAST_PS_FENCE__LAST_FENCE__SHIFT 0x0
2519#define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xffffffff
2520#define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0
2521#define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xffffffff
2522#define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0
2523#define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xffffffff
2524#define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0
2525#define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xffffffff
2526#define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0
2527#define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xffffffff
2528#define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0
2529#define CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xffffffff
2530#define CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0
2531#define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xffffffff
2532#define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0
2533#define CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xffffffff
2534#define CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0
2535#define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xffffffff
2536#define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0
2537#define CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xffffffff
2538#define CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0
2539#define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xffffffff
2540#define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0
2541#define CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xffffffff
2542#define CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0
2543#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_SWAP_MASK 0x3
2544#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_SWAP__SHIFT 0x0
2545#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO_MASK 0xfffffffc
2546#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO__SHIFT 0x2
2547#define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI_MASK 0xffff
2548#define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI__SHIFT 0x0
2549#define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO_MASK 0xffffffff
2550#define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO__SHIFT 0x0
2551#define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI_MASK 0xffffffff
2552#define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI__SHIFT 0x0
2553#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_SWAP_MASK 0x3
2554#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_SWAP__SHIFT 0x0
2555#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO_MASK 0xfffffffc
2556#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO__SHIFT 0x2
2557#define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI_MASK 0xffff
2558#define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI__SHIFT 0x0
2559#define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER_MASK 0xffffffff
2560#define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER__SHIFT 0x0
2561#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK 0x3
2562#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT 0x0
2563#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO_MASK 0xfffffff8
2564#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT 0x3
2565#define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI_MASK 0xffff
2566#define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT 0x0
2567#define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK 0x10000
2568#define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x10
2569#define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK 0x100000
2570#define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x14
2571#define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x3000000
2572#define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x18
2573#define CP_SIG_SEM_ADDR_HI__SEM_SELECT_MASK 0xe0000000
2574#define CP_SIG_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x1d
2575#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK 0x3
2576#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT 0x0
2577#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO_MASK 0xfffffff8
2578#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT 0x3
2579#define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI_MASK 0xffff
2580#define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT 0x0
2581#define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK 0x10000
2582#define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x10
2583#define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK 0x100000
2584#define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x14
2585#define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x3000000
2586#define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x18
2587#define CP_WAIT_SEM_ADDR_HI__SEM_SELECT_MASK 0xe0000000
2588#define CP_WAIT_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x1d
2589#define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT_MASK 0xffffffff
2590#define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT__SHIFT 0x0
2591#define CP_COHER_START_DELAY__START_DELAY_COUNT_MASK 0x3f
2592#define CP_COHER_START_DELAY__START_DELAY_COUNT__SHIFT 0x0
2593#define CP_COHER_CNTL__DEST_BASE_0_ENA_MASK 0x1
2594#define CP_COHER_CNTL__DEST_BASE_0_ENA__SHIFT 0x0
2595#define CP_COHER_CNTL__DEST_BASE_1_ENA_MASK 0x2
2596#define CP_COHER_CNTL__DEST_BASE_1_ENA__SHIFT 0x1
2597#define CP_COHER_CNTL__CB0_DEST_BASE_ENA_MASK 0x40
2598#define CP_COHER_CNTL__CB0_DEST_BASE_ENA__SHIFT 0x6
2599#define CP_COHER_CNTL__CB1_DEST_BASE_ENA_MASK 0x80
2600#define CP_COHER_CNTL__CB1_DEST_BASE_ENA__SHIFT 0x7
2601#define CP_COHER_CNTL__CB2_DEST_BASE_ENA_MASK 0x100
2602#define CP_COHER_CNTL__CB2_DEST_BASE_ENA__SHIFT 0x8
2603#define CP_COHER_CNTL__CB3_DEST_BASE_ENA_MASK 0x200
2604#define CP_COHER_CNTL__CB3_DEST_BASE_ENA__SHIFT 0x9
2605#define CP_COHER_CNTL__CB4_DEST_BASE_ENA_MASK 0x400
2606#define CP_COHER_CNTL__CB4_DEST_BASE_ENA__SHIFT 0xa
2607#define CP_COHER_CNTL__CB5_DEST_BASE_ENA_MASK 0x800
2608#define CP_COHER_CNTL__CB5_DEST_BASE_ENA__SHIFT 0xb
2609#define CP_COHER_CNTL__CB6_DEST_BASE_ENA_MASK 0x1000
2610#define CP_COHER_CNTL__CB6_DEST_BASE_ENA__SHIFT 0xc
2611#define CP_COHER_CNTL__CB7_DEST_BASE_ENA_MASK 0x2000
2612#define CP_COHER_CNTL__CB7_DEST_BASE_ENA__SHIFT 0xd
2613#define CP_COHER_CNTL__DB_DEST_BASE_ENA_MASK 0x4000
2614#define CP_COHER_CNTL__DB_DEST_BASE_ENA__SHIFT 0xe
2615#define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA_MASK 0x8000
2616#define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA__SHIFT 0xf
2617#define CP_COHER_CNTL__TC_VOL_ACTION_ENA_MASK 0x10000
2618#define CP_COHER_CNTL__TC_VOL_ACTION_ENA__SHIFT 0x10
2619#define CP_COHER_CNTL__TC_WB_ACTION_ENA_MASK 0x40000
2620#define CP_COHER_CNTL__TC_WB_ACTION_ENA__SHIFT 0x12
2621#define CP_COHER_CNTL__DEST_BASE_2_ENA_MASK 0x80000
2622#define CP_COHER_CNTL__DEST_BASE_2_ENA__SHIFT 0x13
2623#define CP_COHER_CNTL__DEST_BASE_3_ENA_MASK 0x200000
2624#define CP_COHER_CNTL__DEST_BASE_3_ENA__SHIFT 0x15
2625#define CP_COHER_CNTL__TCL1_ACTION_ENA_MASK 0x400000
2626#define CP_COHER_CNTL__TCL1_ACTION_ENA__SHIFT 0x16
2627#define CP_COHER_CNTL__TC_ACTION_ENA_MASK 0x800000
2628#define CP_COHER_CNTL__TC_ACTION_ENA__SHIFT 0x17
2629#define CP_COHER_CNTL__CB_ACTION_ENA_MASK 0x2000000
2630#define CP_COHER_CNTL__CB_ACTION_ENA__SHIFT 0x19
2631#define CP_COHER_CNTL__DB_ACTION_ENA_MASK 0x4000000
2632#define CP_COHER_CNTL__DB_ACTION_ENA__SHIFT 0x1a
2633#define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA_MASK 0x8000000
2634#define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA__SHIFT 0x1b
2635#define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA_MASK 0x10000000
2636#define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA__SHIFT 0x1c
2637#define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA_MASK 0x20000000
2638#define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA__SHIFT 0x1d
2639#define CP_COHER_SIZE__COHER_SIZE_256B_MASK 0xffffffff
2640#define CP_COHER_SIZE__COHER_SIZE_256B__SHIFT 0x0
2641#define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B_MASK 0xff
2642#define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B__SHIFT 0x0
2643#define CP_COHER_BASE__COHER_BASE_256B_MASK 0xffffffff
2644#define CP_COHER_BASE__COHER_BASE_256B__SHIFT 0x0
2645#define CP_COHER_BASE_HI__COHER_BASE_HI_256B_MASK 0xff
2646#define CP_COHER_BASE_HI__COHER_BASE_HI_256B__SHIFT 0x0
2647#define CP_COHER_STATUS__MATCHING_GFX_CNTX_MASK 0xff
2648#define CP_COHER_STATUS__MATCHING_GFX_CNTX__SHIFT 0x0
2649#define CP_COHER_STATUS__MEID_MASK 0x3000000
2650#define CP_COHER_STATUS__MEID__SHIFT 0x18
2651#define CP_COHER_STATUS__PHASE1_STATUS_MASK 0x40000000
2652#define CP_COHER_STATUS__PHASE1_STATUS__SHIFT 0x1e
2653#define CP_COHER_STATUS__STATUS_MASK 0x80000000
2654#define CP_COHER_STATUS__STATUS__SHIFT 0x1f
2655#define COHER_DEST_BASE_0__DEST_BASE_256B_MASK 0xffffffff
2656#define COHER_DEST_BASE_0__DEST_BASE_256B__SHIFT 0x0
2657#define COHER_DEST_BASE_1__DEST_BASE_256B_MASK 0xffffffff
2658#define COHER_DEST_BASE_1__DEST_BASE_256B__SHIFT 0x0
2659#define COHER_DEST_BASE_2__DEST_BASE_256B_MASK 0xffffffff
2660#define COHER_DEST_BASE_2__DEST_BASE_256B__SHIFT 0x0
2661#define COHER_DEST_BASE_3__DEST_BASE_256B_MASK 0xffffffff
2662#define COHER_DEST_BASE_3__DEST_BASE_256B__SHIFT 0x0
2663#define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B_MASK 0xffffffff
2664#define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B__SHIFT 0x0
2665#define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B_MASK 0xffffffff
2666#define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B__SHIFT 0x0
2667#define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B_MASK 0xffffffff
2668#define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B__SHIFT 0x0
2669#define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B_MASK 0xffffffff
2670#define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B__SHIFT 0x0
2671#define CP_DMA_ME_SRC_ADDR__SRC_ADDR_MASK 0xffffffff
2672#define CP_DMA_ME_SRC_ADDR__SRC_ADDR__SHIFT 0x0
2673#define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0xffff
2674#define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x0
2675#define CP_DMA_ME_DST_ADDR__DST_ADDR_MASK 0xffffffff
2676#define CP_DMA_ME_DST_ADDR__DST_ADDR__SHIFT 0x0
2677#define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI_MASK 0xffff
2678#define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x0
2679#define CP_DMA_ME_CONTROL__SRC_ATC_MASK 0x1000
2680#define CP_DMA_ME_CONTROL__SRC_ATC__SHIFT 0xc
2681#define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY_MASK 0x6000
2682#define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY__SHIFT 0xd
2683#define CP_DMA_ME_CONTROL__SRC_VOLATILE_MASK 0x8000
2684#define CP_DMA_ME_CONTROL__SRC_VOLATILE__SHIFT 0xf
2685#define CP_DMA_ME_CONTROL__DST_SELECT_MASK 0x300000
2686#define CP_DMA_ME_CONTROL__DST_SELECT__SHIFT 0x14
2687#define CP_DMA_ME_CONTROL__DST_ATC_MASK 0x1000000
2688#define CP_DMA_ME_CONTROL__DST_ATC__SHIFT 0x18
2689#define CP_DMA_ME_CONTROL__DST_CACHE_POLICY_MASK 0x6000000
2690#define CP_DMA_ME_CONTROL__DST_CACHE_POLICY__SHIFT 0x19
2691#define CP_DMA_ME_CONTROL__DST_VOLATILE_MASK 0x8000000
2692#define CP_DMA_ME_CONTROL__DST_VOLATILE__SHIFT 0x1b
2693#define CP_DMA_ME_CONTROL__SRC_SELECT_MASK 0x60000000
2694#define CP_DMA_ME_CONTROL__SRC_SELECT__SHIFT 0x1d
2695#define CP_DMA_ME_COMMAND__BYTE_COUNT_MASK 0x1fffff
2696#define CP_DMA_ME_COMMAND__BYTE_COUNT__SHIFT 0x0
2697#define CP_DMA_ME_COMMAND__DIS_WC_MASK 0x200000
2698#define CP_DMA_ME_COMMAND__DIS_WC__SHIFT 0x15
2699#define CP_DMA_ME_COMMAND__SRC_SWAP_MASK 0xc00000
2700#define CP_DMA_ME_COMMAND__SRC_SWAP__SHIFT 0x16
2701#define CP_DMA_ME_COMMAND__DST_SWAP_MASK 0x3000000
2702#define CP_DMA_ME_COMMAND__DST_SWAP__SHIFT 0x18
2703#define CP_DMA_ME_COMMAND__SAS_MASK 0x4000000
2704#define CP_DMA_ME_COMMAND__SAS__SHIFT 0x1a
2705#define CP_DMA_ME_COMMAND__DAS_MASK 0x8000000
2706#define CP_DMA_ME_COMMAND__DAS__SHIFT 0x1b
2707#define CP_DMA_ME_COMMAND__SAIC_MASK 0x10000000
2708#define CP_DMA_ME_COMMAND__SAIC__SHIFT 0x1c
2709#define CP_DMA_ME_COMMAND__DAIC_MASK 0x20000000
2710#define CP_DMA_ME_COMMAND__DAIC__SHIFT 0x1d
2711#define CP_DMA_ME_COMMAND__RAW_WAIT_MASK 0x40000000
2712#define CP_DMA_ME_COMMAND__RAW_WAIT__SHIFT 0x1e
2713#define CP_DMA_PFP_SRC_ADDR__SRC_ADDR_MASK 0xffffffff
2714#define CP_DMA_PFP_SRC_ADDR__SRC_ADDR__SHIFT 0x0
2715#define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0xffff
2716#define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x0
2717#define CP_DMA_PFP_DST_ADDR__DST_ADDR_MASK 0xffffffff
2718#define CP_DMA_PFP_DST_ADDR__DST_ADDR__SHIFT 0x0
2719#define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI_MASK 0xffff
2720#define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x0
2721#define CP_DMA_PFP_CONTROL__SRC_ATC_MASK 0x1000
2722#define CP_DMA_PFP_CONTROL__SRC_ATC__SHIFT 0xc
2723#define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY_MASK 0x6000
2724#define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY__SHIFT 0xd
2725#define CP_DMA_PFP_CONTROL__SRC_VOLATILE_MASK 0x8000
2726#define CP_DMA_PFP_CONTROL__SRC_VOLATILE__SHIFT 0xf
2727#define CP_DMA_PFP_CONTROL__DST_SELECT_MASK 0x300000
2728#define CP_DMA_PFP_CONTROL__DST_SELECT__SHIFT 0x14
2729#define CP_DMA_PFP_CONTROL__DST_ATC_MASK 0x1000000
2730#define CP_DMA_PFP_CONTROL__DST_ATC__SHIFT 0x18
2731#define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY_MASK 0x6000000
2732#define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY__SHIFT 0x19
2733#define CP_DMA_PFP_CONTROL__DST_VOLATILE_MASK 0x8000000
2734#define CP_DMA_PFP_CONTROL__DST_VOLATILE__SHIFT 0x1b
2735#define CP_DMA_PFP_CONTROL__SRC_SELECT_MASK 0x60000000
2736#define CP_DMA_PFP_CONTROL__SRC_SELECT__SHIFT 0x1d
2737#define CP_DMA_PFP_COMMAND__BYTE_COUNT_MASK 0x1fffff
2738#define CP_DMA_PFP_COMMAND__BYTE_COUNT__SHIFT 0x0
2739#define CP_DMA_PFP_COMMAND__DIS_WC_MASK 0x200000
2740#define CP_DMA_PFP_COMMAND__DIS_WC__SHIFT 0x15
2741#define CP_DMA_PFP_COMMAND__SRC_SWAP_MASK 0xc00000
2742#define CP_DMA_PFP_COMMAND__SRC_SWAP__SHIFT 0x16
2743#define CP_DMA_PFP_COMMAND__DST_SWAP_MASK 0x3000000
2744#define CP_DMA_PFP_COMMAND__DST_SWAP__SHIFT 0x18
2745#define CP_DMA_PFP_COMMAND__SAS_MASK 0x4000000
2746#define CP_DMA_PFP_COMMAND__SAS__SHIFT 0x1a
2747#define CP_DMA_PFP_COMMAND__DAS_MASK 0x8000000
2748#define CP_DMA_PFP_COMMAND__DAS__SHIFT 0x1b
2749#define CP_DMA_PFP_COMMAND__SAIC_MASK 0x10000000
2750#define CP_DMA_PFP_COMMAND__SAIC__SHIFT 0x1c
2751#define CP_DMA_PFP_COMMAND__DAIC_MASK 0x20000000
2752#define CP_DMA_PFP_COMMAND__DAIC__SHIFT 0x1d
2753#define CP_DMA_PFP_COMMAND__RAW_WAIT_MASK 0x40000000
2754#define CP_DMA_PFP_COMMAND__RAW_WAIT__SHIFT 0x1e
2755#define CP_DMA_CNTL__MIN_AVAILSZ_MASK 0x30
2756#define CP_DMA_CNTL__MIN_AVAILSZ__SHIFT 0x4
2757#define CP_DMA_CNTL__BUFFER_DEPTH_MASK 0xf0000
2758#define CP_DMA_CNTL__BUFFER_DEPTH__SHIFT 0x10
2759#define CP_DMA_CNTL__PIO_FIFO_EMPTY_MASK 0x10000000
2760#define CP_DMA_CNTL__PIO_FIFO_EMPTY__SHIFT 0x1c
2761#define CP_DMA_CNTL__PIO_FIFO_FULL_MASK 0x20000000
2762#define CP_DMA_CNTL__PIO_FIFO_FULL__SHIFT 0x1d
2763#define CP_DMA_CNTL__PIO_COUNT_MASK 0xc0000000
2764#define CP_DMA_CNTL__PIO_COUNT__SHIFT 0x1e
2765#define CP_DMA_READ_TAGS__DMA_READ_TAG_MASK 0x3ffffff
2766#define CP_DMA_READ_TAGS__DMA_READ_TAG__SHIFT 0x0
2767#define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID_MASK 0x10000000
2768#define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID__SHIFT 0x1c
2769#define CP_PFP_IB_CONTROL__IB_EN_MASK 0xff
2770#define CP_PFP_IB_CONTROL__IB_EN__SHIFT 0x0
2771#define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN_MASK 0x1
2772#define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN__SHIFT 0x0
2773#define CP_PFP_LOAD_CONTROL__CNTX_REG_EN_MASK 0x2
2774#define CP_PFP_LOAD_CONTROL__CNTX_REG_EN__SHIFT 0x1
2775#define CP_PFP_LOAD_CONTROL__UCONFIG_REG_EN_MASK 0x8000
2776#define CP_PFP_LOAD_CONTROL__UCONFIG_REG_EN__SHIFT 0xf
2777#define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN_MASK 0x10000
2778#define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN__SHIFT 0x10
2779#define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN_MASK 0x1000000
2780#define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN__SHIFT 0x18
2781#define CP_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0xff
2782#define CP_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0
2783#define CP_SCRATCH_DATA__SCRATCH_DATA_MASK 0xffffffff
2784#define CP_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0
2785#define CP_RB_OFFSET__RB_OFFSET_MASK 0xfffff
2786#define CP_RB_OFFSET__RB_OFFSET__SHIFT 0x0
2787#define CP_IB1_OFFSET__IB1_OFFSET_MASK 0xfffff
2788#define CP_IB1_OFFSET__IB1_OFFSET__SHIFT 0x0
2789#define CP_IB2_OFFSET__IB2_OFFSET_MASK 0xfffff
2790#define CP_IB2_OFFSET__IB2_OFFSET__SHIFT 0x0
2791#define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN_MASK 0xfffff
2792#define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN__SHIFT 0x0
2793#define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END_MASK 0xfffff
2794#define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END__SHIFT 0x0
2795#define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN_MASK 0xfffff
2796#define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN__SHIFT 0x0
2797#define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END_MASK 0xfffff
2798#define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END__SHIFT 0x0
2799#define CP_CE_IB1_OFFSET__IB1_OFFSET_MASK 0xfffff
2800#define CP_CE_IB1_OFFSET__IB1_OFFSET__SHIFT 0x0
2801#define CP_CE_IB2_OFFSET__IB2_OFFSET_MASK 0xfffff
2802#define CP_CE_IB2_OFFSET__IB2_OFFSET__SHIFT 0x0
2803#define CP_CE_COUNTER__CONST_ENGINE_COUNT_MASK 0xffffffff
2804#define CP_CE_COUNTER__CONST_ENGINE_COUNT__SHIFT 0x0
2805#define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV_MASK 0x1
2806#define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV__SHIFT 0x0
2807#define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV_MASK 0x4
2808#define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV__SHIFT 0x2
2809#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV_MASK 0x10
2810#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV__SHIFT 0x4
2811#define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG_MASK 0x400
2812#define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG__SHIFT 0xa
2813#define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG_MASK 0x800
2814#define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG__SHIFT 0xb
2815#define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM_MASK 0x1000
2816#define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM__SHIFT 0xc
2817#define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x2000
2818#define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0xd
2819#define CP_STALLED_STAT1__ME_WAITING_ON_MC_READ_DATA_MASK 0x4000
2820#define CP_STALLED_STAT1__ME_WAITING_ON_MC_READ_DATA__SHIFT 0xe
2821#define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA_MASK 0x8000
2822#define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA__SHIFT 0xf
2823#define CP_STALLED_STAT1__MIU_WAITING_ON_RDREQ_FREE_MASK 0x10000
2824#define CP_STALLED_STAT1__MIU_WAITING_ON_RDREQ_FREE__SHIFT 0x10
2825#define CP_STALLED_STAT1__MIU_WAITING_ON_WRREQ_FREE_MASK 0x20000
2826#define CP_STALLED_STAT1__MIU_WAITING_ON_WRREQ_FREE__SHIFT 0x11
2827#define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE_MASK 0x800000
2828#define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE__SHIFT 0x17
2829#define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE_MASK 0x1000000
2830#define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE__SHIFT 0x18
2831#define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE_MASK 0x2000000
2832#define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE__SHIFT 0x19
2833#define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ_MASK 0x4000000
2834#define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ__SHIFT 0x1a
2835#define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ_MASK 0x8000000
2836#define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ__SHIFT 0x1b
2837#define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ_MASK 0x10000000
2838#define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ__SHIFT 0x1c
2839#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION_MASK 0x20000000
2840#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION__SHIFT 0x1d
2841#define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV_MASK 0x1
2842#define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0
2843#define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV_MASK 0x2
2844#define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV__SHIFT 0x1
2845#define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV_MASK 0x4
2846#define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV__SHIFT 0x2
2847#define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING_MASK 0x10
2848#define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING__SHIFT 0x4
2849#define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING_MASK 0x20
2850#define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING__SHIFT 0x5
2851#define CP_STALLED_STAT2__PFP_MIU_READ_PENDING_MASK 0x40
2852#define CP_STALLED_STAT2__PFP_MIU_READ_PENDING__SHIFT 0x6
2853#define CP_STALLED_STAT2__PFP_TO_MIU_WRITE_NOT_RDY_TO_RCV_MASK 0x80
2854#define CP_STALLED_STAT2__PFP_TO_MIU_WRITE_NOT_RDY_TO_RCV__SHIFT 0x7
2855#define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA_MASK 0x100
2856#define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA__SHIFT 0x8
2857#define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER_MASK 0x200
2858#define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER__SHIFT 0x9
2859#define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER_MASK 0x400
2860#define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER__SHIFT 0xa
2861#define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME_MASK 0x800
2862#define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME__SHIFT 0xb
2863#define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV_MASK 0x1000
2864#define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV__SHIFT 0xc
2865#define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV_MASK 0x2000
2866#define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV__SHIFT 0xd
2867#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP_MASK 0x4000
2868#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP__SHIFT 0xe
2869#define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH_MASK 0x8000
2870#define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH__SHIFT 0xf
2871#define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x10000
2872#define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x10
2873#define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x20000
2874#define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x11
2875#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ_MASK 0x40000
2876#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ__SHIFT 0x12
2877#define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM_MASK 0x80000
2878#define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x13
2879#define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x100000
2880#define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x14
2881#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE_MASK 0x200000
2882#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE__SHIFT 0x15
2883#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM_MASK 0x400000
2884#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM__SHIFT 0x16
2885#define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING_MASK 0x800000
2886#define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING__SHIFT 0x17
2887#define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING_MASK 0x1000000
2888#define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING__SHIFT 0x18
2889#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE_MASK 0x2000000
2890#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE__SHIFT 0x19
2891#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE_MASK 0x4000000
2892#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE__SHIFT 0x1a
2893#define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM_MASK 0x8000000
2894#define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM__SHIFT 0x1b
2895#define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION_MASK 0x10000000
2896#define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION__SHIFT 0x1c
2897#define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE_MASK 0x20000000
2898#define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE__SHIFT 0x1d
2899#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS_MASK 0x40000000
2900#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS__SHIFT 0x1e
2901#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN_MASK 0x80000000
2902#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN__SHIFT 0x1f
2903#define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV_MASK 0x1
2904#define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0
2905#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV_MASK 0x2
2906#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV__SHIFT 0x1
2907#define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER_MASK 0x4
2908#define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER__SHIFT 0x2
2909#define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY_MASK 0x8
2910#define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY__SHIFT 0x3
2911#define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY_MASK 0x10
2912#define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY__SHIFT 0x4
2913#define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY_MASK 0x20
2914#define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY__SHIFT 0x5
2915#define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV_MASK 0x40
2916#define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV__SHIFT 0x6
2917#define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV_MASK 0x80
2918#define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV__SHIFT 0x7
2919#define CP_STALLED_STAT3__CE_TO_MIU_WRITE_NOT_RDY_TO_RCV_MASK 0x100
2920#define CP_STALLED_STAT3__CE_TO_MIU_WRITE_NOT_RDY_TO_RCV__SHIFT 0x8
2921#define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA_MASK 0x400
2922#define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA__SHIFT 0xa
2923#define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG_MASK 0x800
2924#define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG__SHIFT 0xb
2925#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_MASK 0x1000
2926#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER__SHIFT 0xc
2927#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW_MASK 0x2000
2928#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW__SHIFT 0xd
2929#define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE_MASK 0x4000
2930#define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE__SHIFT 0xe
2931#define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS_MASK 0x8000
2932#define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS__SHIFT 0xf
2933#define CP_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x1
2934#define CP_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x0
2935#define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO_MASK 0x40
2936#define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO__SHIFT 0x6
2937#define CP_BUSY_STAT__PFP_PARSING_PACKETS_MASK 0x80
2938#define CP_BUSY_STAT__PFP_PARSING_PACKETS__SHIFT 0x7
2939#define CP_BUSY_STAT__ME_PARSING_PACKETS_MASK 0x100
2940#define CP_BUSY_STAT__ME_PARSING_PACKETS__SHIFT 0x8
2941#define CP_BUSY_STAT__RCIU_PFP_BUSY_MASK 0x200
2942#define CP_BUSY_STAT__RCIU_PFP_BUSY__SHIFT 0x9
2943#define CP_BUSY_STAT__RCIU_ME_BUSY_MASK 0x400
2944#define CP_BUSY_STAT__RCIU_ME_BUSY__SHIFT 0xa
2945#define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY_MASK 0x1000
2946#define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY__SHIFT 0xc
2947#define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING_MASK 0x2000
2948#define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING__SHIFT 0xd
2949#define CP_BUSY_STAT__SEM_POLLING_FOR_PASS_MASK 0x4000
2950#define CP_BUSY_STAT__SEM_POLLING_FOR_PASS__SHIFT 0xe
2951#define CP_BUSY_STAT__GFX_CONTEXT_BUSY_MASK 0x8000
2952#define CP_BUSY_STAT__GFX_CONTEXT_BUSY__SHIFT 0xf
2953#define CP_BUSY_STAT__ME_PARSER_BUSY_MASK 0x20000
2954#define CP_BUSY_STAT__ME_PARSER_BUSY__SHIFT 0x11
2955#define CP_BUSY_STAT__EOP_DONE_BUSY_MASK 0x40000
2956#define CP_BUSY_STAT__EOP_DONE_BUSY__SHIFT 0x12
2957#define CP_BUSY_STAT__STRM_OUT_BUSY_MASK 0x80000
2958#define CP_BUSY_STAT__STRM_OUT_BUSY__SHIFT 0x13
2959#define CP_BUSY_STAT__PIPE_STATS_BUSY_MASK 0x100000
2960#define CP_BUSY_STAT__PIPE_STATS_BUSY__SHIFT 0x14
2961#define CP_BUSY_STAT__RCIU_CE_BUSY_MASK 0x200000
2962#define CP_BUSY_STAT__RCIU_CE_BUSY__SHIFT 0x15
2963#define CP_BUSY_STAT__CE_PARSING_PACKETS_MASK 0x400000
2964#define CP_BUSY_STAT__CE_PARSING_PACKETS__SHIFT 0x16
2965#define CP_STAT__MIU_RDREQ_BUSY_MASK 0x80
2966#define CP_STAT__MIU_RDREQ_BUSY__SHIFT 0x7
2967#define CP_STAT__MIU_WRREQ_BUSY_MASK 0x100
2968#define CP_STAT__MIU_WRREQ_BUSY__SHIFT 0x8
2969#define CP_STAT__ROQ_RING_BUSY_MASK 0x200
2970#define CP_STAT__ROQ_RING_BUSY__SHIFT 0x9
2971#define CP_STAT__ROQ_INDIRECT1_BUSY_MASK 0x400
2972#define CP_STAT__ROQ_INDIRECT1_BUSY__SHIFT 0xa
2973#define CP_STAT__ROQ_INDIRECT2_BUSY_MASK 0x800
2974#define CP_STAT__ROQ_INDIRECT2_BUSY__SHIFT 0xb
2975#define CP_STAT__ROQ_STATE_BUSY_MASK 0x1000
2976#define CP_STAT__ROQ_STATE_BUSY__SHIFT 0xc
2977#define CP_STAT__DC_BUSY_MASK 0x2000
2978#define CP_STAT__DC_BUSY__SHIFT 0xd
2979#define CP_STAT__PFP_BUSY_MASK 0x8000
2980#define CP_STAT__PFP_BUSY__SHIFT 0xf
2981#define CP_STAT__MEQ_BUSY_MASK 0x10000
2982#define CP_STAT__MEQ_BUSY__SHIFT 0x10
2983#define CP_STAT__ME_BUSY_MASK 0x20000
2984#define CP_STAT__ME_BUSY__SHIFT 0x11
2985#define CP_STAT__QUERY_BUSY_MASK 0x40000
2986#define CP_STAT__QUERY_BUSY__SHIFT 0x12
2987#define CP_STAT__SEMAPHORE_BUSY_MASK 0x80000
2988#define CP_STAT__SEMAPHORE_BUSY__SHIFT 0x13
2989#define CP_STAT__INTERRUPT_BUSY_MASK 0x100000
2990#define CP_STAT__INTERRUPT_BUSY__SHIFT 0x14
2991#define CP_STAT__SURFACE_SYNC_BUSY_MASK 0x200000
2992#define CP_STAT__SURFACE_SYNC_BUSY__SHIFT 0x15
2993#define CP_STAT__DMA_BUSY_MASK 0x400000
2994#define CP_STAT__DMA_BUSY__SHIFT 0x16
2995#define CP_STAT__RCIU_BUSY_MASK 0x800000
2996#define CP_STAT__RCIU_BUSY__SHIFT 0x17
2997#define CP_STAT__SCRATCH_RAM_BUSY_MASK 0x1000000
2998#define CP_STAT__SCRATCH_RAM_BUSY__SHIFT 0x18
2999#define CP_STAT__CPC_CPG_BUSY_MASK 0x2000000
3000#define CP_STAT__CPC_CPG_BUSY__SHIFT 0x19
3001#define CP_STAT__CE_BUSY_MASK 0x4000000
3002#define CP_STAT__CE_BUSY__SHIFT 0x1a
3003#define CP_STAT__TCIU_BUSY_MASK 0x8000000
3004#define CP_STAT__TCIU_BUSY__SHIFT 0x1b
3005#define CP_STAT__ROQ_CE_RING_BUSY_MASK 0x10000000
3006#define CP_STAT__ROQ_CE_RING_BUSY__SHIFT 0x1c
3007#define CP_STAT__ROQ_CE_INDIRECT1_BUSY_MASK 0x20000000
3008#define CP_STAT__ROQ_CE_INDIRECT1_BUSY__SHIFT 0x1d
3009#define CP_STAT__ROQ_CE_INDIRECT2_BUSY_MASK 0x40000000
3010#define CP_STAT__ROQ_CE_INDIRECT2_BUSY__SHIFT 0x1e
3011#define CP_STAT__CP_BUSY_MASK 0x80000000
3012#define CP_STAT__CP_BUSY__SHIFT 0x1f
3013#define CP_ME_HEADER_DUMP__ME_HEADER_DUMP_MASK 0xffffffff
3014#define CP_ME_HEADER_DUMP__ME_HEADER_DUMP__SHIFT 0x0
3015#define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP_MASK 0xffffffff
3016#define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP__SHIFT 0x0
3017#define CP_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x3f
3018#define CP_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0
3019#define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS_MASK 0x3f00
3020#define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS__SHIFT 0x8
3021#define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP_MASK 0x3f0000
3022#define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP__SHIFT 0x10
3023#define CP_CE_HEADER_DUMP__CE_HEADER_DUMP_MASK 0xffffffff
3024#define CP_CE_HEADER_DUMP__CE_HEADER_DUMP__SHIFT 0x0
3025#define CP_MC_PACK_DELAY_CNT__PACK_DELAY_CNT_MASK 0x1f
3026#define CP_MC_PACK_DELAY_CNT__PACK_DELAY_CNT__SHIFT 0x0
3027#define CP_MC_TAG_CNTL__TAG_RAM_INDEX_MASK 0x3f
3028#define CP_MC_TAG_CNTL__TAG_RAM_INDEX__SHIFT 0x0
3029#define CP_MC_TAG_CNTL__TAG_RAM_SEL_MASK 0x30000
3030#define CP_MC_TAG_CNTL__TAG_RAM_SEL__SHIFT 0x10
3031#define CP_MC_TAG_DATA__TAG_RAM_DATA_MASK 0xffffffff
3032#define CP_MC_TAG_DATA__TAG_RAM_DATA__SHIFT 0x0
3033#define CP_CSF_STAT__BUFFER_SLOTS_ALLOCATED_MASK 0xf
3034#define CP_CSF_STAT__BUFFER_SLOTS_ALLOCATED__SHIFT 0x0
3035#define CP_CSF_STAT__BUFFER_REQUEST_COUNT_MASK 0x3f00
3036#define CP_CSF_STAT__BUFFER_REQUEST_COUNT__SHIFT 0x8
3037#define CP_CSF_CNTL__FETCH_BUFFER_DEPTH_MASK 0xf
3038#define CP_CSF_CNTL__FETCH_BUFFER_DEPTH__SHIFT 0x0
3039#define CP_ME_CNTL__CE_INVALIDATE_ICACHE_MASK 0x10
3040#define CP_ME_CNTL__CE_INVALIDATE_ICACHE__SHIFT 0x4
3041#define CP_ME_CNTL__PFP_INVALIDATE_ICACHE_MASK 0x40
3042#define CP_ME_CNTL__PFP_INVALIDATE_ICACHE__SHIFT 0x6
3043#define CP_ME_CNTL__ME_INVALIDATE_ICACHE_MASK 0x100
3044#define CP_ME_CNTL__ME_INVALIDATE_ICACHE__SHIFT 0x8
3045#define CP_ME_CNTL__CE_HALT_MASK 0x1000000
3046#define CP_ME_CNTL__CE_HALT__SHIFT 0x18
3047#define CP_ME_CNTL__CE_STEP_MASK 0x2000000
3048#define CP_ME_CNTL__CE_STEP__SHIFT 0x19
3049#define CP_ME_CNTL__PFP_HALT_MASK 0x4000000
3050#define CP_ME_CNTL__PFP_HALT__SHIFT 0x1a
3051#define CP_ME_CNTL__PFP_STEP_MASK 0x8000000
3052#define CP_ME_CNTL__PFP_STEP__SHIFT 0x1b
3053#define CP_ME_CNTL__ME_HALT_MASK 0x10000000
3054#define CP_ME_CNTL__ME_HALT__SHIFT 0x1c
3055#define CP_ME_CNTL__ME_STEP_MASK 0x20000000
3056#define CP_ME_CNTL__ME_STEP__SHIFT 0x1d
3057#define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS_MASK 0xff
3058#define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS__SHIFT 0x0
3059#define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT_MASK 0x700
3060#define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT__SHIFT 0x8
3061#define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS_MASK 0xff00000
3062#define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS__SHIFT 0x14
3063#define CP_CNTX_STAT__CURRENT_GFX_CONTEXT_MASK 0x70000000
3064#define CP_CNTX_STAT__CURRENT_GFX_CONTEXT__SHIFT 0x1c
3065#define CP_ME_PREEMPTION__ME_CNTXSW_PREEMPTION_MASK 0x1
3066#define CP_ME_PREEMPTION__ME_CNTXSW_PREEMPTION__SHIFT 0x0
3067#define CP_RB0_RPTR__RB_RPTR_MASK 0xfffff
3068#define CP_RB0_RPTR__RB_RPTR__SHIFT 0x0
3069#define CP_RB_RPTR__RB_RPTR_MASK 0xfffff
3070#define CP_RB_RPTR__RB_RPTR__SHIFT 0x0
3071#define CP_RB1_RPTR__RB_RPTR_MASK 0xfffff
3072#define CP_RB1_RPTR__RB_RPTR__SHIFT 0x0
3073#define CP_RB2_RPTR__RB_RPTR_MASK 0xfffff
3074#define CP_RB2_RPTR__RB_RPTR__SHIFT 0x0
3075#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER_MASK 0xfffffff
3076#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER__SHIFT 0x0
3077#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT_MASK 0xf0000000
3078#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT__SHIFT 0x1c
3079#define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK 0xffff
3080#define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT 0x0
3081#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000
3082#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
3083#define CP_CE_INIT_BASE_LO__INIT_BASE_LO_MASK 0xffffffe0
3084#define CP_CE_INIT_BASE_LO__INIT_BASE_LO__SHIFT 0x5
3085#define CP_CE_INIT_BASE_HI__INIT_BASE_HI_MASK 0xffff
3086#define CP_CE_INIT_BASE_HI__INIT_BASE_HI__SHIFT 0x0
3087#define CP_CE_INIT_BUFSZ__INIT_BUFSZ_MASK 0xfff
3088#define CP_CE_INIT_BUFSZ__INIT_BUFSZ__SHIFT 0x0
3089#define CP_CE_IB1_BASE_LO__IB1_BASE_LO_MASK 0xfffffffc
3090#define CP_CE_IB1_BASE_LO__IB1_BASE_LO__SHIFT 0x2
3091#define CP_CE_IB1_BASE_HI__IB1_BASE_HI_MASK 0xffff
3092#define CP_CE_IB1_BASE_HI__IB1_BASE_HI__SHIFT 0x0
3093#define CP_CE_IB1_BUFSZ__IB1_BUFSZ_MASK 0xfffff
3094#define CP_CE_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x0
3095#define CP_CE_IB2_BASE_LO__IB2_BASE_LO_MASK 0xfffffffc
3096#define CP_CE_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x2
3097#define CP_CE_IB2_BASE_HI__IB2_BASE_HI_MASK 0xffff
3098#define CP_CE_IB2_BASE_HI__IB2_BASE_HI__SHIFT 0x0
3099#define CP_CE_IB2_BUFSZ__IB2_BUFSZ_MASK 0xfffff
3100#define CP_CE_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x0
3101#define CP_IB1_BASE_LO__IB1_BASE_LO_MASK 0xfffffffc
3102#define CP_IB1_BASE_LO__IB1_BASE_LO__SHIFT 0x2
3103#define CP_IB1_BASE_HI__IB1_BASE_HI_MASK 0xffff
3104#define CP_IB1_BASE_HI__IB1_BASE_HI__SHIFT 0x0
3105#define CP_IB1_BUFSZ__IB1_BUFSZ_MASK 0xfffff
3106#define CP_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x0
3107#define CP_IB2_BASE_LO__IB2_BASE_LO_MASK 0xfffffffc
3108#define CP_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x2
3109#define CP_IB2_BASE_HI__IB2_BASE_HI_MASK 0xffff
3110#define CP_IB2_BASE_HI__IB2_BASE_HI__SHIFT 0x0
3111#define CP_IB2_BUFSZ__IB2_BUFSZ_MASK 0xfffff
3112#define CP_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x0
3113#define CP_ST_BASE_LO__ST_BASE_LO_MASK 0xfffffffc
3114#define CP_ST_BASE_LO__ST_BASE_LO__SHIFT 0x2
3115#define CP_ST_BASE_HI__ST_BASE_HI_MASK 0xffff
3116#define CP_ST_BASE_HI__ST_BASE_HI__SHIFT 0x0
3117#define CP_ST_BUFSZ__ST_BUFSZ_MASK 0xfffff
3118#define CP_ST_BUFSZ__ST_BUFSZ__SHIFT 0x0
3119#define CP_ROQ_THRESHOLDS__IB1_START_MASK 0xff
3120#define CP_ROQ_THRESHOLDS__IB1_START__SHIFT 0x0
3121#define CP_ROQ_THRESHOLDS__IB2_START_MASK 0xff00
3122#define CP_ROQ_THRESHOLDS__IB2_START__SHIFT 0x8
3123#define CP_MEQ_STQ_THRESHOLD__STQ_START_MASK 0xff
3124#define CP_MEQ_STQ_THRESHOLD__STQ_START__SHIFT 0x0
3125#define CP_ROQ1_THRESHOLDS__RB1_START_MASK 0xff
3126#define CP_ROQ1_THRESHOLDS__RB1_START__SHIFT 0x0
3127#define CP_ROQ1_THRESHOLDS__RB2_START_MASK 0xff00
3128#define CP_ROQ1_THRESHOLDS__RB2_START__SHIFT 0x8
3129#define CP_ROQ1_THRESHOLDS__R0_IB1_START_MASK 0xff0000
3130#define CP_ROQ1_THRESHOLDS__R0_IB1_START__SHIFT 0x10
3131#define CP_ROQ1_THRESHOLDS__R1_IB1_START_MASK 0xff000000
3132#define CP_ROQ1_THRESHOLDS__R1_IB1_START__SHIFT 0x18
3133#define CP_ROQ2_THRESHOLDS__R2_IB1_START_MASK 0xff
3134#define CP_ROQ2_THRESHOLDS__R2_IB1_START__SHIFT 0x0
3135#define CP_ROQ2_THRESHOLDS__R0_IB2_START_MASK 0xff00
3136#define CP_ROQ2_THRESHOLDS__R0_IB2_START__SHIFT 0x8
3137#define CP_ROQ2_THRESHOLDS__R1_IB2_START_MASK 0xff0000
3138#define CP_ROQ2_THRESHOLDS__R1_IB2_START__SHIFT 0x10
3139#define CP_ROQ2_THRESHOLDS__R2_IB2_START_MASK 0xff000000
3140#define CP_ROQ2_THRESHOLDS__R2_IB2_START__SHIFT 0x18
3141#define CP_STQ_THRESHOLDS__STQ0_START_MASK 0xff
3142#define CP_STQ_THRESHOLDS__STQ0_START__SHIFT 0x0
3143#define CP_STQ_THRESHOLDS__STQ1_START_MASK 0xff00
3144#define CP_STQ_THRESHOLDS__STQ1_START__SHIFT 0x8
3145#define CP_STQ_THRESHOLDS__STQ2_START_MASK 0xff0000
3146#define CP_STQ_THRESHOLDS__STQ2_START__SHIFT 0x10
3147#define CP_QUEUE_THRESHOLDS__ROQ_IB1_START_MASK 0x3f
3148#define CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT 0x0
3149#define CP_QUEUE_THRESHOLDS__ROQ_IB2_START_MASK 0x3f00
3150#define CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT 0x8
3151#define CP_MEQ_THRESHOLDS__MEQ1_START_MASK 0xff
3152#define CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT 0x0
3153#define CP_MEQ_THRESHOLDS__MEQ2_START_MASK 0xff00
3154#define CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT 0x8
3155#define CP_ROQ_AVAIL__ROQ_CNT_RING_MASK 0x7ff
3156#define CP_ROQ_AVAIL__ROQ_CNT_RING__SHIFT 0x0
3157#define CP_ROQ_AVAIL__ROQ_CNT_IB1_MASK 0x7ff0000
3158#define CP_ROQ_AVAIL__ROQ_CNT_IB1__SHIFT 0x10
3159#define CP_STQ_AVAIL__STQ_CNT_MASK 0x1ff
3160#define CP_STQ_AVAIL__STQ_CNT__SHIFT 0x0
3161#define CP_ROQ2_AVAIL__ROQ_CNT_IB2_MASK 0x7ff
3162#define CP_ROQ2_AVAIL__ROQ_CNT_IB2__SHIFT 0x0
3163#define CP_MEQ_AVAIL__MEQ_CNT_MASK 0x3ff
3164#define CP_MEQ_AVAIL__MEQ_CNT__SHIFT 0x0
3165#define CP_CMD_INDEX__CMD_INDEX_MASK 0x7ff
3166#define CP_CMD_INDEX__CMD_INDEX__SHIFT 0x0
3167#define CP_CMD_INDEX__CMD_ME_SEL_MASK 0x3000
3168#define CP_CMD_INDEX__CMD_ME_SEL__SHIFT 0xc
3169#define CP_CMD_INDEX__CMD_QUEUE_SEL_MASK 0x30000
3170#define CP_CMD_INDEX__CMD_QUEUE_SEL__SHIFT 0x10
3171#define CP_CMD_DATA__CMD_DATA_MASK 0xffffffff
3172#define CP_CMD_DATA__CMD_DATA__SHIFT 0x0
3173#define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY_MASK 0x3ff
3174#define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY__SHIFT 0x0
3175#define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY_MASK 0x3ff0000
3176#define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY__SHIFT 0x10
3177#define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1_MASK 0x3ff
3178#define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1__SHIFT 0x0
3179#define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1_MASK 0x3ff0000
3180#define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1__SHIFT 0x10
3181#define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2_MASK 0x3ff
3182#define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2__SHIFT 0x0
3183#define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2_MASK 0x3ff0000
3184#define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2__SHIFT 0x10
3185#define CP_STQ_STAT__STQ_RPTR_MASK 0x3ff
3186#define CP_STQ_STAT__STQ_RPTR__SHIFT 0x0
3187#define CP_STQ_WR_STAT__STQ_WPTR_MASK 0x3ff
3188#define CP_STQ_WR_STAT__STQ_WPTR__SHIFT 0x0
3189#define CP_MEQ_STAT__MEQ_RPTR_MASK 0x3ff
3190#define CP_MEQ_STAT__MEQ_RPTR__SHIFT 0x0
3191#define CP_MEQ_STAT__MEQ_WPTR_MASK 0x3ff0000
3192#define CP_MEQ_STAT__MEQ_WPTR__SHIFT 0x10
3193#define CP_CEQ1_AVAIL__CEQ_CNT_RING_MASK 0x7ff
3194#define CP_CEQ1_AVAIL__CEQ_CNT_RING__SHIFT 0x0
3195#define CP_CEQ1_AVAIL__CEQ_CNT_IB1_MASK 0x7ff0000
3196#define CP_CEQ1_AVAIL__CEQ_CNT_IB1__SHIFT 0x10
3197#define CP_CEQ2_AVAIL__CEQ_CNT_IB2_MASK 0x7ff
3198#define CP_CEQ2_AVAIL__CEQ_CNT_IB2__SHIFT 0x0
3199#define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY_MASK 0x3ff
3200#define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY__SHIFT 0x0
3201#define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY_MASK 0x3ff0000
3202#define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY__SHIFT 0x10
3203#define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1_MASK 0x3ff
3204#define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1__SHIFT 0x0
3205#define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1_MASK 0x3ff0000
3206#define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1__SHIFT 0x10
3207#define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2_MASK 0x3ff
3208#define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2__SHIFT 0x0
3209#define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2_MASK 0x3ff0000
3210#define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2__SHIFT 0x10
3211#define CP_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x4000
3212#define CP_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0xe
3213#define CP_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x20000
3214#define CP_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x11
3215#define CP_INT_STAT_DEBUG__CNTX_BUSY_INT_ASSERTED_MASK 0x80000
3216#define CP_INT_STAT_DEBUG__CNTX_BUSY_INT_ASSERTED__SHIFT 0x13
3217#define CP_INT_STAT_DEBUG__CNTX_EMPTY_INT_ASSERTED_MASK 0x100000
3218#define CP_INT_STAT_DEBUG__CNTX_EMPTY_INT_ASSERTED__SHIFT 0x14
3219#define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED_MASK 0x400000
3220#define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED__SHIFT 0x16
3221#define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x800000
3222#define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17
3223#define CP_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x1000000
3224#define CP_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x18
3225#define CP_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x4000000
3226#define CP_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x1a
3227#define CP_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x8000000
3228#define CP_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x1b
3229#define CP_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000
3230#define CP_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d
3231#define CP_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000
3232#define CP_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x1e
3233#define CP_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000
3234#define CP_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x1f
3235#define CP_PERFMON_CNTL__PERFMON_STATE_MASK 0xf
3236#define CP_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
3237#define CP_PERFMON_CNTL__SPM_PERFMON_STATE_MASK 0xf0
3238#define CP_PERFMON_CNTL__SPM_PERFMON_STATE__SHIFT 0x4
3239#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK 0x300
3240#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT 0x8
3241#define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x400
3242#define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa
3243#define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE_MASK 0x80000000
3244#define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE__SHIFT 0x1f
3245#define CP_RINGID__RINGID_MASK 0x3
3246#define CP_RINGID__RINGID__SHIFT 0x0
3247#define CP_PIPEID__PIPE_ID_MASK 0x3
3248#define CP_PIPEID__PIPE_ID__SHIFT 0x0
3249#define CP_VMID__VMID_MASK 0xf
3250#define CP_VMID__VMID__SHIFT 0x0
3251#define CP_HPD_ROQ_OFFSETS__IQ_OFFSET_MASK 0x7
3252#define CP_HPD_ROQ_OFFSETS__IQ_OFFSET__SHIFT 0x0
3253#define CP_HPD_ROQ_OFFSETS__PQ_OFFSET_MASK 0x3f00
3254#define CP_HPD_ROQ_OFFSETS__PQ_OFFSET__SHIFT 0x8
3255#define CP_HPD_ROQ_OFFSETS__IB_OFFSET_MASK 0x3f0000
3256#define CP_HPD_ROQ_OFFSETS__IB_OFFSET__SHIFT 0x10
3257#define CP_HPD_EOP_BASE_ADDR__BASE_ADDR_MASK 0xffffffff
3258#define CP_HPD_EOP_BASE_ADDR__BASE_ADDR__SHIFT 0x0
3259#define CP_HPD_EOP_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0xff
3260#define CP_HPD_EOP_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0
3261#define CP_HPD_EOP_VMID__VMID_MASK 0xf
3262#define CP_HPD_EOP_VMID__VMID__SHIFT 0x0
3263#define CP_HPD_EOP_CONTROL__EOP_SIZE_MASK 0x3f
3264#define CP_HPD_EOP_CONTROL__EOP_SIZE__SHIFT 0x0
3265#define CP_HPD_EOP_CONTROL__PROCESSING_EOP_MASK 0x100
3266#define CP_HPD_EOP_CONTROL__PROCESSING_EOP__SHIFT 0x8
3267#define CP_HPD_EOP_CONTROL__PROCESSING_QID_MASK 0xe00
3268#define CP_HPD_EOP_CONTROL__PROCESSING_QID__SHIFT 0x9
3269#define CP_HPD_EOP_CONTROL__PROCESS_EOP_EN_MASK 0x1000
3270#define CP_HPD_EOP_CONTROL__PROCESS_EOP_EN__SHIFT 0xc
3271#define CP_HPD_EOP_CONTROL__PROCESSING_EOPIB_MASK 0x2000
3272#define CP_HPD_EOP_CONTROL__PROCESSING_EOPIB__SHIFT 0xd
3273#define CP_HPD_EOP_CONTROL__PROCESS_EOPIB_EN_MASK 0x4000
3274#define CP_HPD_EOP_CONTROL__PROCESS_EOPIB_EN__SHIFT 0xe
3275#define CP_HPD_EOP_CONTROL__EOP_ATC_MASK 0x800000
3276#define CP_HPD_EOP_CONTROL__EOP_ATC__SHIFT 0x17
3277#define CP_HPD_EOP_CONTROL__CACHE_POLICY_MASK 0x3000000
3278#define CP_HPD_EOP_CONTROL__CACHE_POLICY__SHIFT 0x18
3279#define CP_HPD_EOP_CONTROL__EOP_VOLATILE_MASK 0x4000000
3280#define CP_HPD_EOP_CONTROL__EOP_VOLATILE__SHIFT 0x1a
3281#define CP_HPD_EOP_CONTROL__PEND_Q_SEM_MASK 0x70000000
3282#define CP_HPD_EOP_CONTROL__PEND_Q_SEM__SHIFT 0x1c
3283#define CP_HPD_EOP_CONTROL__PEND_SIG_SEM_MASK 0x80000000
3284#define CP_HPD_EOP_CONTROL__PEND_SIG_SEM__SHIFT 0x1f
3285#define CP_MQD_BASE_ADDR__BASE_ADDR_MASK 0xfffffffc
3286#define CP_MQD_BASE_ADDR__BASE_ADDR__SHIFT 0x2
3287#define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0xffff
3288#define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0
3289#define CP_HQD_ACTIVE__ACTIVE_MASK 0x1
3290#define CP_HQD_ACTIVE__ACTIVE__SHIFT 0x0
3291#define CP_HQD_VMID__VMID_MASK 0xf
3292#define CP_HQD_VMID__VMID__SHIFT 0x0
3293#define CP_HQD_VMID__IB_VMID_MASK 0xf00
3294#define CP_HQD_VMID__IB_VMID__SHIFT 0x8
3295#define CP_HQD_VMID__VQID_MASK 0x3ff0000
3296#define CP_HQD_VMID__VQID__SHIFT 0x10
3297#define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK 0x1
3298#define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ__SHIFT 0x0
3299#define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE_MASK 0x3ff00
3300#define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT 0x8
3301#define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE_MASK 0x80000000
3302#define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE__SHIFT 0x1f
3303#define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY_MASK 0x3
3304#define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY__SHIFT 0x0
3305#define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL_MASK 0xf
3306#define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL__SHIFT 0x0
3307#define CP_HQD_QUANTUM__QUANTUM_EN_MASK 0x1
3308#define CP_HQD_QUANTUM__QUANTUM_EN__SHIFT 0x0
3309#define CP_HQD_QUANTUM__QUANTUM_SCALE_MASK 0x10
3310#define CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT 0x4
3311#define CP_HQD_QUANTUM__QUANTUM_DURATION_MASK 0x3f00
3312#define CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT 0x8
3313#define CP_HQD_PQ_BASE__ADDR_MASK 0xffffffff
3314#define CP_HQD_PQ_BASE__ADDR__SHIFT 0x0
3315#define CP_HQD_PQ_BASE_HI__ADDR_HI_MASK 0xff
3316#define CP_HQD_PQ_BASE_HI__ADDR_HI__SHIFT 0x0
3317#define CP_HQD_PQ_RPTR__CONSUMED_OFFSET_MASK 0xffffffff
3318#define CP_HQD_PQ_RPTR__CONSUMED_OFFSET__SHIFT 0x0
3319#define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR_MASK 0xfffffffc
3320#define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR__SHIFT 0x2
3321#define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI_MASK 0xffff
3322#define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI__SHIFT 0x0
3323#define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR_MASK 0xfffffffc
3324#define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR__SHIFT 0x2
3325#define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI_MASK 0xffff
3326#define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI__SHIFT 0x0
3327#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x7ffffc
3328#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x2
3329#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE_MASK 0x10000000
3330#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE__SHIFT 0x1c
3331#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT_MASK 0x20000000
3332#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT__SHIFT 0x1d
3333#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK 0x40000000
3334#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN__SHIFT 0x1e
3335#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT_MASK 0x80000000
3336#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT 0x1f
3337#define CP_HQD_PQ_WPTR__OFFSET_MASK 0xffffffff
3338#define CP_HQD_PQ_WPTR__OFFSET__SHIFT 0x0
3339#define CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK 0x3f
3340#define CP_HQD_PQ_CONTROL__QUEUE_SIZE__SHIFT 0x0
3341#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK 0x3f00
3342#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT 0x8
3343#define CP_HQD_PQ_CONTROL__ENDIAN_SWAP_MASK 0x30000
3344#define CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT 0x10
3345#define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE_MASK 0x300000
3346#define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE__SHIFT 0x14
3347#define CP_HQD_PQ_CONTROL__PQ_ATC_MASK 0x800000
3348#define CP_HQD_PQ_CONTROL__PQ_ATC__SHIFT 0x17
3349#define CP_HQD_PQ_CONTROL__CACHE_POLICY_MASK 0x3000000
3350#define CP_HQD_PQ_CONTROL__CACHE_POLICY__SHIFT 0x18
3351#define CP_HQD_PQ_CONTROL__PQ_VOLATILE_MASK 0x4000000
3352#define CP_HQD_PQ_CONTROL__PQ_VOLATILE__SHIFT 0x1a
3353#define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK 0x8000000
3354#define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR__SHIFT 0x1b
3355#define CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK 0x10000000
3356#define CP_HQD_PQ_CONTROL__UNORD_DISPATCH__SHIFT 0x1c
3357#define CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP_MASK 0x20000000
3358#define CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP__SHIFT 0x1d
3359#define CP_HQD_PQ_CONTROL__PRIV_STATE_MASK 0x40000000
3360#define CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT 0x1e
3361#define CP_HQD_PQ_CONTROL__KMD_QUEUE_MASK 0x80000000
3362#define CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT 0x1f
3363#define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR_MASK 0xfffffffc
3364#define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR__SHIFT 0x2
3365#define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI_MASK 0xffff
3366#define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI__SHIFT 0x0
3367#define CP_HQD_IB_RPTR__CONSUMED_OFFSET_MASK 0xfffff
3368#define CP_HQD_IB_RPTR__CONSUMED_OFFSET__SHIFT 0x0
3369#define CP_HQD_IB_CONTROL__IB_SIZE_MASK 0xfffff
3370#define CP_HQD_IB_CONTROL__IB_SIZE__SHIFT 0x0
3371#define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE_MASK 0x300000
3372#define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT 0x14
3373#define CP_HQD_IB_CONTROL__IB_ATC_MASK 0x800000
3374#define CP_HQD_IB_CONTROL__IB_ATC__SHIFT 0x17
3375#define CP_HQD_IB_CONTROL__IB_CACHE_POLICY_MASK 0x3000000
3376#define CP_HQD_IB_CONTROL__IB_CACHE_POLICY__SHIFT 0x18
3377#define CP_HQD_IB_CONTROL__IB_VOLATILE_MASK 0x4000000
3378#define CP_HQD_IB_CONTROL__IB_VOLATILE__SHIFT 0x1a
3379#define CP_HQD_IB_CONTROL__PROCESSING_IB_MASK 0x80000000
3380#define CP_HQD_IB_CONTROL__PROCESSING_IB__SHIFT 0x1f
3381#define CP_HQD_IQ_TIMER__WAIT_TIME_MASK 0xff
3382#define CP_HQD_IQ_TIMER__WAIT_TIME__SHIFT 0x0
3383#define CP_HQD_IQ_TIMER__RETRY_TYPE_MASK 0x700
3384#define CP_HQD_IQ_TIMER__RETRY_TYPE__SHIFT 0x8
3385#define CP_HQD_IQ_TIMER__INTERRUPT_TYPE_MASK 0x3000
3386#define CP_HQD_IQ_TIMER__INTERRUPT_TYPE__SHIFT 0xc
3387#define CP_HQD_IQ_TIMER__INTERRUPT_SIZE_MASK 0x3f0000
3388#define CP_HQD_IQ_TIMER__INTERRUPT_SIZE__SHIFT 0x10
3389#define CP_HQD_IQ_TIMER__IQ_ATC_MASK 0x800000
3390#define CP_HQD_IQ_TIMER__IQ_ATC__SHIFT 0x17
3391#define CP_HQD_IQ_TIMER__CACHE_POLICY_MASK 0x3000000
3392#define CP_HQD_IQ_TIMER__CACHE_POLICY__SHIFT 0x18
3393#define CP_HQD_IQ_TIMER__IQ_VOLATILE_MASK 0x4000000
3394#define CP_HQD_IQ_TIMER__IQ_VOLATILE__SHIFT 0x1a
3395#define CP_HQD_IQ_TIMER__PROCESS_IQ_EN_MASK 0x20000000
3396#define CP_HQD_IQ_TIMER__PROCESS_IQ_EN__SHIFT 0x1d
3397#define CP_HQD_IQ_TIMER__PROCESSING_IQ_MASK 0x40000000
3398#define CP_HQD_IQ_TIMER__PROCESSING_IQ__SHIFT 0x1e
3399#define CP_HQD_IQ_TIMER__ACTIVE_MASK 0x80000000
3400#define CP_HQD_IQ_TIMER__ACTIVE__SHIFT 0x1f
3401#define CP_HQD_IQ_RPTR__OFFSET_MASK 0x3f
3402#define CP_HQD_IQ_RPTR__OFFSET__SHIFT 0x0
3403#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_MASK 0x3
3404#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ__SHIFT 0x0
3405#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK 0x10
3406#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND__SHIFT 0x4
3407#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT_MASK 0x100
3408#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT__SHIFT 0x8
3409#define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD_MASK 0x1
3410#define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD__SHIFT 0x0
3411#define CP_HQD_SEMA_CMD__RETRY_MASK 0x1
3412#define CP_HQD_SEMA_CMD__RETRY__SHIFT 0x0
3413#define CP_HQD_SEMA_CMD__RESULT_MASK 0x6
3414#define CP_HQD_SEMA_CMD__RESULT__SHIFT 0x1
3415#define CP_HQD_MSG_TYPE__ACTION_MASK 0x3
3416#define CP_HQD_MSG_TYPE__ACTION__SHIFT 0x0
3417#define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO_MASK 0xffffffff
3418#define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO__SHIFT 0x0
3419#define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI_MASK 0xffffffff
3420#define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI__SHIFT 0x0
3421#define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO_MASK 0xffffffff
3422#define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO__SHIFT 0x0
3423#define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI_MASK 0xffffffff
3424#define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI__SHIFT 0x0
3425#define CP_HQD_HQ_SCHEDULER0__DEQUEUE_STATUS_MASK 0x3
3426#define CP_HQD_HQ_SCHEDULER0__DEQUEUE_STATUS__SHIFT 0x0
3427#define CP_HQD_HQ_SCHEDULER0__DEQUEUE_RETRY_CNT_MASK 0xc
3428#define CP_HQD_HQ_SCHEDULER0__DEQUEUE_RETRY_CNT__SHIFT 0x2
3429#define CP_HQD_HQ_SCHEDULER0__RSV_5_4_MASK 0x30
3430#define CP_HQD_HQ_SCHEDULER0__RSV_5_4__SHIFT 0x4
3431#define CP_HQD_HQ_SCHEDULER0__QUEUE_RUN_ONCE_MASK 0x40
3432#define CP_HQD_HQ_SCHEDULER0__QUEUE_RUN_ONCE__SHIFT 0x6
3433#define CP_HQD_HQ_SCHEDULER0__SCRATCH_RAM_INIT_MASK 0x80
3434#define CP_HQD_HQ_SCHEDULER0__SCRATCH_RAM_INIT__SHIFT 0x7
3435#define CP_HQD_HQ_SCHEDULER0__TCL2_DIRTY_MASK 0x100
3436#define CP_HQD_HQ_SCHEDULER0__TCL2_DIRTY__SHIFT 0x8
3437#define CP_HQD_HQ_SCHEDULER0__PG_ACTIVATED_MASK 0x200
3438#define CP_HQD_HQ_SCHEDULER0__PG_ACTIVATED__SHIFT 0x9
3439#define CP_HQD_HQ_SCHEDULER0__CG_ACTIVATED_MASK 0x400
3440#define CP_HQD_HQ_SCHEDULER0__CG_ACTIVATED__SHIFT 0xa
3441#define CP_HQD_HQ_SCHEDULER0__RSVR_31_11_MASK 0xfffff800
3442#define CP_HQD_HQ_SCHEDULER0__RSVR_31_11__SHIFT 0xb
3443#define CP_HQD_HQ_SCHEDULER1__SCHEDULER_MASK 0xffffffff
3444#define CP_HQD_HQ_SCHEDULER1__SCHEDULER__SHIFT 0x0
3445#define CP_MQD_CONTROL__VMID_MASK 0xf
3446#define CP_MQD_CONTROL__VMID__SHIFT 0x0
3447#define CP_MQD_CONTROL__MQD_ATC_MASK 0x800000
3448#define CP_MQD_CONTROL__MQD_ATC__SHIFT 0x17
3449#define CP_MQD_CONTROL__CACHE_POLICY_MASK 0x3000000
3450#define CP_MQD_CONTROL__CACHE_POLICY__SHIFT 0x18
3451#define CP_MQD_CONTROL__MQD_VOLATILE_MASK 0x4000000
3452#define CP_MQD_CONTROL__MQD_VOLATILE__SHIFT 0x1a
3453#define DB_Z_READ_BASE__BASE_256B_MASK 0xffffffff
3454#define DB_Z_READ_BASE__BASE_256B__SHIFT 0x0
3455#define DB_STENCIL_READ_BASE__BASE_256B_MASK 0xffffffff
3456#define DB_STENCIL_READ_BASE__BASE_256B__SHIFT 0x0
3457#define DB_Z_WRITE_BASE__BASE_256B_MASK 0xffffffff
3458#define DB_Z_WRITE_BASE__BASE_256B__SHIFT 0x0
3459#define DB_STENCIL_WRITE_BASE__BASE_256B_MASK 0xffffffff
3460#define DB_STENCIL_WRITE_BASE__BASE_256B__SHIFT 0x0
3461#define DB_DEPTH_INFO__ADDR5_SWIZZLE_MASK_MASK 0xf
3462#define DB_DEPTH_INFO__ADDR5_SWIZZLE_MASK__SHIFT 0x0
3463#define DB_DEPTH_INFO__ARRAY_MODE_MASK 0xf0
3464#define DB_DEPTH_INFO__ARRAY_MODE__SHIFT 0x4
3465#define DB_DEPTH_INFO__PIPE_CONFIG_MASK 0x1f00
3466#define DB_DEPTH_INFO__PIPE_CONFIG__SHIFT 0x8
3467#define DB_DEPTH_INFO__BANK_WIDTH_MASK 0x6000
3468#define DB_DEPTH_INFO__BANK_WIDTH__SHIFT 0xd
3469#define DB_DEPTH_INFO__BANK_HEIGHT_MASK 0x18000
3470#define DB_DEPTH_INFO__BANK_HEIGHT__SHIFT 0xf
3471#define DB_DEPTH_INFO__MACRO_TILE_ASPECT_MASK 0x60000
3472#define DB_DEPTH_INFO__MACRO_TILE_ASPECT__SHIFT 0x11
3473#define DB_DEPTH_INFO__NUM_BANKS_MASK 0x180000
3474#define DB_DEPTH_INFO__NUM_BANKS__SHIFT 0x13
3475#define DB_Z_INFO__FORMAT_MASK 0x3
3476#define DB_Z_INFO__FORMAT__SHIFT 0x0
3477#define DB_Z_INFO__NUM_SAMPLES_MASK 0xc
3478#define DB_Z_INFO__NUM_SAMPLES__SHIFT 0x2
3479#define DB_Z_INFO__TILE_SPLIT_MASK 0xe000
3480#define DB_Z_INFO__TILE_SPLIT__SHIFT 0xd
3481#define DB_Z_INFO__TILE_MODE_INDEX_MASK 0x700000
3482#define DB_Z_INFO__TILE_MODE_INDEX__SHIFT 0x14
3483#define DB_Z_INFO__ALLOW_EXPCLEAR_MASK 0x8000000
3484#define DB_Z_INFO__ALLOW_EXPCLEAR__SHIFT 0x1b
3485#define DB_Z_INFO__READ_SIZE_MASK 0x10000000
3486#define DB_Z_INFO__READ_SIZE__SHIFT 0x1c
3487#define DB_Z_INFO__TILE_SURFACE_ENABLE_MASK 0x20000000
3488#define DB_Z_INFO__TILE_SURFACE_ENABLE__SHIFT 0x1d
3489#define DB_Z_INFO__ZRANGE_PRECISION_MASK 0x80000000
3490#define DB_Z_INFO__ZRANGE_PRECISION__SHIFT 0x1f
3491#define DB_STENCIL_INFO__FORMAT_MASK 0x1
3492#define DB_STENCIL_INFO__FORMAT__SHIFT 0x0
3493#define DB_STENCIL_INFO__TILE_SPLIT_MASK 0xe000
3494#define DB_STENCIL_INFO__TILE_SPLIT__SHIFT 0xd
3495#define DB_STENCIL_INFO__TILE_MODE_INDEX_MASK 0x700000
3496#define DB_STENCIL_INFO__TILE_MODE_INDEX__SHIFT 0x14
3497#define DB_STENCIL_INFO__ALLOW_EXPCLEAR_MASK 0x8000000
3498#define DB_STENCIL_INFO__ALLOW_EXPCLEAR__SHIFT 0x1b
3499#define DB_STENCIL_INFO__TILE_STENCIL_DISABLE_MASK 0x20000000
3500#define DB_STENCIL_INFO__TILE_STENCIL_DISABLE__SHIFT 0x1d
3501#define DB_DEPTH_SIZE__PITCH_TILE_MAX_MASK 0x7ff
3502#define DB_DEPTH_SIZE__PITCH_TILE_MAX__SHIFT 0x0
3503#define DB_DEPTH_SIZE__HEIGHT_TILE_MAX_MASK 0x3ff800
3504#define DB_DEPTH_SIZE__HEIGHT_TILE_MAX__SHIFT 0xb
3505#define DB_DEPTH_SLICE__SLICE_TILE_MAX_MASK 0x3fffff
3506#define DB_DEPTH_SLICE__SLICE_TILE_MAX__SHIFT 0x0
3507#define DB_DEPTH_VIEW__SLICE_START_MASK 0x7ff
3508#define DB_DEPTH_VIEW__SLICE_START__SHIFT 0x0
3509#define DB_DEPTH_VIEW__SLICE_MAX_MASK 0xffe000
3510#define DB_DEPTH_VIEW__SLICE_MAX__SHIFT 0xd
3511#define DB_DEPTH_VIEW__Z_READ_ONLY_MASK 0x1000000
3512#define DB_DEPTH_VIEW__Z_READ_ONLY__SHIFT 0x18
3513#define DB_DEPTH_VIEW__STENCIL_READ_ONLY_MASK 0x2000000
3514#define DB_DEPTH_VIEW__STENCIL_READ_ONLY__SHIFT 0x19
3515#define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE_MASK 0x1
3516#define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE__SHIFT 0x0
3517#define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE_MASK 0x2
3518#define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE__SHIFT 0x1
3519#define DB_RENDER_CONTROL__DEPTH_COPY_MASK 0x4
3520#define DB_RENDER_CONTROL__DEPTH_COPY__SHIFT 0x2
3521#define DB_RENDER_CONTROL__STENCIL_COPY_MASK 0x8
3522#define DB_RENDER_CONTROL__STENCIL_COPY__SHIFT 0x3
3523#define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE_MASK 0x10
3524#define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE__SHIFT 0x4
3525#define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE_MASK 0x20
3526#define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE__SHIFT 0x5
3527#define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE_MASK 0x40
3528#define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE__SHIFT 0x6
3529#define DB_RENDER_CONTROL__COPY_CENTROID_MASK 0x80
3530#define DB_RENDER_CONTROL__COPY_CENTROID__SHIFT 0x7
3531#define DB_RENDER_CONTROL__COPY_SAMPLE_MASK 0xf00
3532#define DB_RENDER_CONTROL__COPY_SAMPLE__SHIFT 0x8
3533#define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE_MASK 0x1
3534#define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE__SHIFT 0x0
3535#define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS_MASK 0x2
3536#define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS__SHIFT 0x1
3537#define DB_COUNT_CONTROL__SAMPLE_RATE_MASK 0x70
3538#define DB_COUNT_CONTROL__SAMPLE_RATE__SHIFT 0x4
3539#define DB_COUNT_CONTROL__ZPASS_ENABLE_MASK 0xf00
3540#define DB_COUNT_CONTROL__ZPASS_ENABLE__SHIFT 0x8
3541#define DB_COUNT_CONTROL__ZFAIL_ENABLE_MASK 0xf000
3542#define DB_COUNT_CONTROL__ZFAIL_ENABLE__SHIFT 0xc
3543#define DB_COUNT_CONTROL__SFAIL_ENABLE_MASK 0xf0000
3544#define DB_COUNT_CONTROL__SFAIL_ENABLE__SHIFT 0x10
3545#define DB_COUNT_CONTROL__DBFAIL_ENABLE_MASK 0xf00000
3546#define DB_COUNT_CONTROL__DBFAIL_ENABLE__SHIFT 0x14
3547#define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE_MASK 0xf000000
3548#define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE__SHIFT 0x18
3549#define DB_COUNT_CONTROL__SLICE_ODD_ENABLE_MASK 0xf0000000
3550#define DB_COUNT_CONTROL__SLICE_ODD_ENABLE__SHIFT 0x1c
3551#define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE_MASK 0x3
3552#define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE__SHIFT 0x0
3553#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0_MASK 0xc
3554#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0__SHIFT 0x2
3555#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1_MASK 0x30
3556#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1__SHIFT 0x4
3557#define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER_MASK 0x40
3558#define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER__SHIFT 0x6
3559#define DB_RENDER_OVERRIDE__FAST_Z_DISABLE_MASK 0x80
3560#define DB_RENDER_OVERRIDE__FAST_Z_DISABLE__SHIFT 0x7
3561#define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE_MASK 0x100
3562#define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE__SHIFT 0x8
3563#define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE_MASK 0x200
3564#define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE__SHIFT 0x9
3565#define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL_MASK 0x400
3566#define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL__SHIFT 0xa
3567#define DB_RENDER_OVERRIDE__FORCE_Z_READ_MASK 0x800
3568#define DB_RENDER_OVERRIDE__FORCE_Z_READ__SHIFT 0xb
3569#define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ_MASK 0x1000
3570#define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ__SHIFT 0xc
3571#define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE_MASK 0x6000
3572#define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE__SHIFT 0xd
3573#define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT_MASK 0x8000
3574#define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT__SHIFT 0xf
3575#define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP_MASK 0x10000
3576#define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP__SHIFT 0x10
3577#define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE_MASK 0x20000
3578#define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE__SHIFT 0x11
3579#define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED_MASK 0x40000
3580#define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED__SHIFT 0x12
3581#define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM_MASK 0x180000
3582#define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM__SHIFT 0x13
3583#define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT_MASK 0x3e00000
3584#define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT__SHIFT 0x15
3585#define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES_MASK 0x4000000
3586#define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES__SHIFT 0x1a
3587#define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY_MASK 0x8000000
3588#define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY__SHIFT 0x1b
3589#define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY_MASK 0x10000000
3590#define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY__SHIFT 0x1c
3591#define DB_RENDER_OVERRIDE__FORCE_Z_VALID_MASK 0x20000000
3592#define DB_RENDER_OVERRIDE__FORCE_Z_VALID__SHIFT 0x1d
3593#define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID_MASK 0x40000000
3594#define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID__SHIFT 0x1e
3595#define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION_MASK 0x80000000
3596#define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION__SHIFT 0x1f
3597#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL_MASK 0x3
3598#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL__SHIFT 0x0
3599#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN_MASK 0x1c
3600#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN__SHIFT 0x2
3601#define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION_MASK 0x20
3602#define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION__SHIFT 0x5
3603#define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION_MASK 0x40
3604#define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION__SHIFT 0x6
3605#define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION_MASK 0x80
3606#define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION__SHIFT 0x7
3607#define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH_MASK 0x100
3608#define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH__SHIFT 0x8
3609#define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP_MASK 0x200
3610#define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP__SHIFT 0x9
3611#define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE_MASK 0x400
3612#define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE__SHIFT 0xa
3613#define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE_MASK 0x800
3614#define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE__SHIFT 0xb
3615#define DB_RENDER_OVERRIDE2__HIZ_ZFUNC_MASK 0x7000
3616#define DB_RENDER_OVERRIDE2__HIZ_ZFUNC__SHIFT 0xc
3617#define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF_MASK 0x38000
3618#define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF__SHIFT 0xf
3619#define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF_MASK 0x1c0000
3620#define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF__SHIFT 0x12
3621#define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE_MASK 0x200000
3622#define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE__SHIFT 0x15
3623#define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS_MASK 0x400000
3624#define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS__SHIFT 0x16
3625#define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS_MASK 0x800000
3626#define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS__SHIFT 0x17
3627#define DB_EQAA__MAX_ANCHOR_SAMPLES_MASK 0x7
3628#define DB_EQAA__MAX_ANCHOR_SAMPLES__SHIFT 0x0
3629#define DB_EQAA__PS_ITER_SAMPLES_MASK 0x70
3630#define DB_EQAA__PS_ITER_SAMPLES__SHIFT 0x4
3631#define DB_EQAA__MASK_EXPORT_NUM_SAMPLES_MASK 0x700
3632#define DB_EQAA__MASK_EXPORT_NUM_SAMPLES__SHIFT 0x8
3633#define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES_MASK 0x7000
3634#define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES__SHIFT 0xc
3635#define DB_EQAA__HIGH_QUALITY_INTERSECTIONS_MASK 0x10000
3636#define DB_EQAA__HIGH_QUALITY_INTERSECTIONS__SHIFT 0x10
3637#define DB_EQAA__INCOHERENT_EQAA_READS_MASK 0x20000
3638#define DB_EQAA__INCOHERENT_EQAA_READS__SHIFT 0x11
3639#define DB_EQAA__INTERPOLATE_COMP_Z_MASK 0x40000
3640#define DB_EQAA__INTERPOLATE_COMP_Z__SHIFT 0x12
3641#define DB_EQAA__INTERPOLATE_SRC_Z_MASK 0x80000
3642#define DB_EQAA__INTERPOLATE_SRC_Z__SHIFT 0x13
3643#define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS_MASK 0x100000
3644#define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS__SHIFT 0x14
3645#define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE_MASK 0x200000
3646#define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE__SHIFT 0x15
3647#define DB_EQAA__OVERRASTERIZATION_AMOUNT_MASK 0x7000000
3648#define DB_EQAA__OVERRASTERIZATION_AMOUNT__SHIFT 0x18
3649#define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION_MASK 0x8000000
3650#define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION__SHIFT 0x1b
3651#define DB_SHADER_CONTROL__Z_EXPORT_ENABLE_MASK 0x1
3652#define DB_SHADER_CONTROL__Z_EXPORT_ENABLE__SHIFT 0x0
3653#define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE_MASK 0x2
3654#define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE__SHIFT 0x1
3655#define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE_MASK 0x4
3656#define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE__SHIFT 0x2
3657#define DB_SHADER_CONTROL__Z_ORDER_MASK 0x30
3658#define DB_SHADER_CONTROL__Z_ORDER__SHIFT 0x4
3659#define DB_SHADER_CONTROL__KILL_ENABLE_MASK 0x40
3660#define DB_SHADER_CONTROL__KILL_ENABLE__SHIFT 0x6
3661#define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE_MASK 0x80
3662#define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE__SHIFT 0x7
3663#define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE_MASK 0x100
3664#define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE__SHIFT 0x8
3665#define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL_MASK 0x200
3666#define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL__SHIFT 0x9
3667#define DB_SHADER_CONTROL__EXEC_ON_NOOP_MASK 0x400
3668#define DB_SHADER_CONTROL__EXEC_ON_NOOP__SHIFT 0xa
3669#define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE_MASK 0x800
3670#define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE__SHIFT 0xb
3671#define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER_MASK 0x1000
3672#define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER__SHIFT 0xc
3673#define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT_MASK 0x6000
3674#define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT__SHIFT 0xd
3675#define DB_DEPTH_BOUNDS_MIN__MIN_MASK 0xffffffff
3676#define DB_DEPTH_BOUNDS_MIN__MIN__SHIFT 0x0
3677#define DB_DEPTH_BOUNDS_MAX__MAX_MASK 0xffffffff
3678#define DB_DEPTH_BOUNDS_MAX__MAX__SHIFT 0x0
3679#define DB_STENCIL_CLEAR__CLEAR_MASK 0xff
3680#define DB_STENCIL_CLEAR__CLEAR__SHIFT 0x0
3681#define DB_DEPTH_CLEAR__DEPTH_CLEAR_MASK 0xffffffff
3682#define DB_DEPTH_CLEAR__DEPTH_CLEAR__SHIFT 0x0
3683#define DB_HTILE_DATA_BASE__BASE_256B_MASK 0xffffffff
3684#define DB_HTILE_DATA_BASE__BASE_256B__SHIFT 0x0
3685#define DB_HTILE_SURFACE__LINEAR_MASK 0x1
3686#define DB_HTILE_SURFACE__LINEAR__SHIFT 0x0
3687#define DB_HTILE_SURFACE__FULL_CACHE_MASK 0x2
3688#define DB_HTILE_SURFACE__FULL_CACHE__SHIFT 0x1
3689#define DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN_MASK 0x4
3690#define DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN__SHIFT 0x2
3691#define DB_HTILE_SURFACE__PRELOAD_MASK 0x8
3692#define DB_HTILE_SURFACE__PRELOAD__SHIFT 0x3
3693#define DB_HTILE_SURFACE__PREFETCH_WIDTH_MASK 0x3f0
3694#define DB_HTILE_SURFACE__PREFETCH_WIDTH__SHIFT 0x4
3695#define DB_HTILE_SURFACE__PREFETCH_HEIGHT_MASK 0xfc00
3696#define DB_HTILE_SURFACE__PREFETCH_HEIGHT__SHIFT 0xa
3697#define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE_MASK 0x10000
3698#define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE__SHIFT 0x10
3699#define DB_PRELOAD_CONTROL__START_X_MASK 0xff
3700#define DB_PRELOAD_CONTROL__START_X__SHIFT 0x0
3701#define DB_PRELOAD_CONTROL__START_Y_MASK 0xff00
3702#define DB_PRELOAD_CONTROL__START_Y__SHIFT 0x8
3703#define DB_PRELOAD_CONTROL__MAX_X_MASK 0xff0000
3704#define DB_PRELOAD_CONTROL__MAX_X__SHIFT 0x10
3705#define DB_PRELOAD_CONTROL__MAX_Y_MASK 0xff000000
3706#define DB_PRELOAD_CONTROL__MAX_Y__SHIFT 0x18
3707#define DB_STENCILREFMASK__STENCILTESTVAL_MASK 0xff
3708#define DB_STENCILREFMASK__STENCILTESTVAL__SHIFT 0x0
3709#define DB_STENCILREFMASK__STENCILMASK_MASK 0xff00
3710#define DB_STENCILREFMASK__STENCILMASK__SHIFT 0x8
3711#define DB_STENCILREFMASK__STENCILWRITEMASK_MASK 0xff0000
3712#define DB_STENCILREFMASK__STENCILWRITEMASK__SHIFT 0x10
3713#define DB_STENCILREFMASK__STENCILOPVAL_MASK 0xff000000
3714#define DB_STENCILREFMASK__STENCILOPVAL__SHIFT 0x18
3715#define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF_MASK 0xff
3716#define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF__SHIFT 0x0
3717#define DB_STENCILREFMASK_BF__STENCILMASK_BF_MASK 0xff00
3718#define DB_STENCILREFMASK_BF__STENCILMASK_BF__SHIFT 0x8
3719#define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF_MASK 0xff0000
3720#define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF__SHIFT 0x10
3721#define DB_STENCILREFMASK_BF__STENCILOPVAL_BF_MASK 0xff000000
3722#define DB_STENCILREFMASK_BF__STENCILOPVAL_BF__SHIFT 0x18
3723#define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0_MASK 0x7
3724#define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0__SHIFT 0x0
3725#define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0_MASK 0xff0
3726#define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0__SHIFT 0x4
3727#define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0_MASK 0xff000
3728#define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0__SHIFT 0xc
3729#define DB_SRESULTS_COMPARE_STATE0__ENABLE0_MASK 0x1000000
3730#define DB_SRESULTS_COMPARE_STATE0__ENABLE0__SHIFT 0x18
3731#define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1_MASK 0x7
3732#define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1__SHIFT 0x0
3733#define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1_MASK 0xff0
3734#define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1__SHIFT 0x4
3735#define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1_MASK 0xff000
3736#define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1__SHIFT 0xc
3737#define DB_SRESULTS_COMPARE_STATE1__ENABLE1_MASK 0x1000000
3738#define DB_SRESULTS_COMPARE_STATE1__ENABLE1__SHIFT 0x18
3739#define DB_DEPTH_CONTROL__STENCIL_ENABLE_MASK 0x1
3740#define DB_DEPTH_CONTROL__STENCIL_ENABLE__SHIFT 0x0
3741#define DB_DEPTH_CONTROL__Z_ENABLE_MASK 0x2
3742#define DB_DEPTH_CONTROL__Z_ENABLE__SHIFT 0x1
3743#define DB_DEPTH_CONTROL__Z_WRITE_ENABLE_MASK 0x4
3744#define DB_DEPTH_CONTROL__Z_WRITE_ENABLE__SHIFT 0x2
3745#define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE_MASK 0x8
3746#define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE__SHIFT 0x3
3747#define DB_DEPTH_CONTROL__ZFUNC_MASK 0x70
3748#define DB_DEPTH_CONTROL__ZFUNC__SHIFT 0x4
3749#define DB_DEPTH_CONTROL__BACKFACE_ENABLE_MASK 0x80
3750#define DB_DEPTH_CONTROL__BACKFACE_ENABLE__SHIFT 0x7
3751#define DB_DEPTH_CONTROL__STENCILFUNC_MASK 0x700
3752#define DB_DEPTH_CONTROL__STENCILFUNC__SHIFT 0x8
3753#define DB_DEPTH_CONTROL__STENCILFUNC_BF_MASK 0x700000
3754#define DB_DEPTH_CONTROL__STENCILFUNC_BF__SHIFT 0x14
3755#define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL_MASK 0x40000000
3756#define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL__SHIFT 0x1e
3757#define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS_MASK 0x80000000
3758#define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS__SHIFT 0x1f
3759#define DB_STENCIL_CONTROL__STENCILFAIL_MASK 0xf
3760#define DB_STENCIL_CONTROL__STENCILFAIL__SHIFT 0x0
3761#define DB_STENCIL_CONTROL__STENCILZPASS_MASK 0xf0
3762#define DB_STENCIL_CONTROL__STENCILZPASS__SHIFT 0x4
3763#define DB_STENCIL_CONTROL__STENCILZFAIL_MASK 0xf00
3764#define DB_STENCIL_CONTROL__STENCILZFAIL__SHIFT 0x8
3765#define DB_STENCIL_CONTROL__STENCILFAIL_BF_MASK 0xf000
3766#define DB_STENCIL_CONTROL__STENCILFAIL_BF__SHIFT 0xc
3767#define DB_STENCIL_CONTROL__STENCILZPASS_BF_MASK 0xf0000
3768#define DB_STENCIL_CONTROL__STENCILZPASS_BF__SHIFT 0x10
3769#define DB_STENCIL_CONTROL__STENCILZFAIL_BF_MASK 0xf00000
3770#define DB_STENCIL_CONTROL__STENCILZFAIL_BF__SHIFT 0x14
3771#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE_MASK 0x1
3772#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE__SHIFT 0x0
3773#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0_MASK 0x300
3774#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0__SHIFT 0x8
3775#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1_MASK 0xc00
3776#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1__SHIFT 0xa
3777#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2_MASK 0x3000
3778#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2__SHIFT 0xc
3779#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3_MASK 0xc000
3780#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3__SHIFT 0xe
3781#define DB_ALPHA_TO_MASK__OFFSET_ROUND_MASK 0x10000
3782#define DB_ALPHA_TO_MASK__OFFSET_ROUND__SHIFT 0x10
3783#define DB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff
3784#define DB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
3785#define DB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00
3786#define DB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
3787#define DB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
3788#define DB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
3789#define DB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000
3790#define DB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
3791#define DB_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
3792#define DB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
3793#define DB_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff
3794#define DB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
3795#define DB_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00
3796#define DB_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
3797#define DB_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
3798#define DB_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
3799#define DB_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000
3800#define DB_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
3801#define DB_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
3802#define DB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
3803#define DB_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff
3804#define DB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
3805#define DB_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0xffc00
3806#define DB_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa
3807#define DB_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000
3808#define DB_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
3809#define DB_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0xf000000
3810#define DB_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18
3811#define DB_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000
3812#define DB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
3813#define DB_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff
3814#define DB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
3815#define DB_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0xffc00
3816#define DB_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa
3817#define DB_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000
3818#define DB_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
3819#define DB_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0xf000000
3820#define DB_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18
3821#define DB_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000
3822#define DB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
3823#define DB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff
3824#define DB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
3825#define DB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00
3826#define DB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
3827#define DB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000
3828#define DB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
3829#define DB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000
3830#define DB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
3831#define DB_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff
3832#define DB_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
3833#define DB_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00
3834#define DB_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
3835#define DB_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xf000000
3836#define DB_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18
3837#define DB_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf0000000
3838#define DB_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c
3839#define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
3840#define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
3841#define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
3842#define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
3843#define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
3844#define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
3845#define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
3846#define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
3847#define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
3848#define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
3849#define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
3850#define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
3851#define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
3852#define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
3853#define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
3854#define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
3855#define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE_MASK 0x1
3856#define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE__SHIFT 0x0
3857#define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE_MASK 0x2
3858#define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE__SHIFT 0x1
3859#define DB_DEBUG__FETCH_FULL_Z_TILE_MASK 0x4
3860#define DB_DEBUG__FETCH_FULL_Z_TILE__SHIFT 0x2
3861#define DB_DEBUG__FETCH_FULL_STENCIL_TILE_MASK 0x8
3862#define DB_DEBUG__FETCH_FULL_STENCIL_TILE__SHIFT 0x3
3863#define DB_DEBUG__FORCE_Z_MODE_MASK 0x30
3864#define DB_DEBUG__FORCE_Z_MODE__SHIFT 0x4
3865#define DB_DEBUG__DEBUG_FORCE_DEPTH_READ_MASK 0x40
3866#define DB_DEBUG__DEBUG_FORCE_DEPTH_READ__SHIFT 0x6
3867#define DB_DEBUG__DEBUG_FORCE_STENCIL_READ_MASK 0x80
3868#define DB_DEBUG__DEBUG_FORCE_STENCIL_READ__SHIFT 0x7
3869#define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE_MASK 0x300
3870#define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE__SHIFT 0x8
3871#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0_MASK 0xc00
3872#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0__SHIFT 0xa
3873#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1_MASK 0x3000
3874#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1__SHIFT 0xc
3875#define DB_DEBUG__DEBUG_FAST_Z_DISABLE_MASK 0x4000
3876#define DB_DEBUG__DEBUG_FAST_Z_DISABLE__SHIFT 0xe
3877#define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE_MASK 0x8000
3878#define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE__SHIFT 0xf
3879#define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE_MASK 0x10000
3880#define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE__SHIFT 0x10
3881#define DB_DEBUG__DISABLE_SUMM_SQUADS_MASK 0x20000
3882#define DB_DEBUG__DISABLE_SUMM_SQUADS__SHIFT 0x11
3883#define DB_DEBUG__DEPTH_CACHE_FORCE_MISS_MASK 0x40000
3884#define DB_DEBUG__DEPTH_CACHE_FORCE_MISS__SHIFT 0x12
3885#define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE_MASK 0x180000
3886#define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE__SHIFT 0x13
3887#define DB_DEBUG__NEVER_FREE_Z_ONLY_MASK 0x200000
3888#define DB_DEBUG__NEVER_FREE_Z_ONLY__SHIFT 0x15
3889#define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS_MASK 0x400000
3890#define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS__SHIFT 0x16
3891#define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION_MASK 0x800000
3892#define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION__SHIFT 0x17
3893#define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES_MASK 0xf000000
3894#define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES__SHIFT 0x18
3895#define DB_DEBUG__ONE_FREE_IN_FLIGHT_MASK 0x10000000
3896#define DB_DEBUG__ONE_FREE_IN_FLIGHT__SHIFT 0x1c
3897#define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT_MASK 0x20000000
3898#define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT__SHIFT 0x1d
3899#define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC_MASK 0x40000000
3900#define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC__SHIFT 0x1e
3901#define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC_MASK 0x80000000
3902#define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC__SHIFT 0x1f
3903#define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING_MASK 0x1
3904#define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING__SHIFT 0x0
3905#define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE_MASK 0x2
3906#define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE__SHIFT 0x1
3907#define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE_MASK 0x4
3908#define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE__SHIFT 0x2
3909#define DB_DEBUG2__DTR_ROUND_ROBIN_ARB_MASK 0x8
3910#define DB_DEBUG2__DTR_ROUND_ROBIN_ARB__SHIFT 0x3
3911#define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM_MASK 0x10
3912#define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM__SHIFT 0x4
3913#define DB_DEBUG2__DISABLE_PREZL_LPF_STALL_MASK 0x20
3914#define DB_DEBUG2__DISABLE_PREZL_LPF_STALL__SHIFT 0x5
3915#define DB_DEBUG2__ENABLE_PREZL_CB_STALL_MASK 0x40
3916#define DB_DEBUG2__ENABLE_PREZL_CB_STALL__SHIFT 0x6
3917#define DB_DEBUG2__DISABLE_PREZL_LPF_STALL_REZ_MASK 0x80
3918#define DB_DEBUG2__DISABLE_PREZL_LPF_STALL_REZ__SHIFT 0x7
3919#define DB_DEBUG2__DISABLE_PREZL_CB_STALL_REZ_MASK 0x100
3920#define DB_DEBUG2__DISABLE_PREZL_CB_STALL_REZ__SHIFT 0x8
3921#define DB_DEBUG2__CLK_OFF_DELAY_MASK 0x3e00
3922#define DB_DEBUG2__CLK_OFF_DELAY__SHIFT 0x9
3923#define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER_MASK 0x4000
3924#define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER__SHIFT 0xe
3925#define DB_DEBUG2__ENABLE_SUBTILE_GROUPING_MASK 0x8000
3926#define DB_DEBUG2__ENABLE_SUBTILE_GROUPING__SHIFT 0xf
3927#define DB_DEBUG2__DISABLE_HTILE_PAIRED_PIPES_MASK 0x10000
3928#define DB_DEBUG2__DISABLE_HTILE_PAIRED_PIPES__SHIFT 0x10
3929#define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING_MASK 0x20000
3930#define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING__SHIFT 0x11
3931#define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING_MASK 0x40000
3932#define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING__SHIFT 0x12
3933#define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL_MASK 0x80000
3934#define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL__SHIFT 0x13
3935#define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM_MASK 0x10000000
3936#define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM__SHIFT 0x1c
3937#define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL_MASK 0x20000000
3938#define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL__SHIFT 0x1d
3939#define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM_MASK 0x40000000
3940#define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM__SHIFT 0x1e
3941#define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT_MASK 0x80000000
3942#define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT__SHIFT 0x1f
3943#define DB_DEBUG3__FORCE_DB_IS_GOOD_MASK 0x4
3944#define DB_DEBUG3__FORCE_DB_IS_GOOD__SHIFT 0x2
3945#define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION_MASK 0x8
3946#define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION__SHIFT 0x3
3947#define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP_MASK 0x10
3948#define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP__SHIFT 0x4
3949#define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z_MASK 0x20
3950#define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z__SHIFT 0x5
3951#define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z_MASK 0x40
3952#define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z__SHIFT 0x6
3953#define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS_MASK 0x80
3954#define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS__SHIFT 0x7
3955#define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION_MASK 0x100
3956#define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION__SHIFT 0x8
3957#define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT_MASK 0x200
3958#define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT__SHIFT 0x9
3959#define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP_MASK 0x400
3960#define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP__SHIFT 0xa
3961#define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS_MASK 0x800
3962#define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS__SHIFT 0xb
3963#define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING_MASK 0x1000
3964#define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING__SHIFT 0xc
3965#define DB_DEBUG3__DISABLE_OP_DF_BYPASS_MASK 0x2000
3966#define DB_DEBUG3__DISABLE_OP_DF_BYPASS__SHIFT 0xd
3967#define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE_MASK 0x4000
3968#define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE__SHIFT 0xe
3969#define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK_MASK 0x8000
3970#define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK__SHIFT 0xf
3971#define DB_DEBUG3__ALLOW_RF2P_RW_COLLISION_MASK 0x10000
3972#define DB_DEBUG3__ALLOW_RF2P_RW_COLLISION__SHIFT 0x10
3973#define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE_MASK 0x20000
3974#define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE__SHIFT 0x11
3975#define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING_MASK 0x40000
3976#define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING__SHIFT 0x12
3977#define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE_MASK 0x80000
3978#define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE__SHIFT 0x13
3979#define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE_MASK 0x100000
3980#define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE__SHIFT 0x14
3981#define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT_MASK 0x200000
3982#define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT__SHIFT 0x15
3983#define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB_MASK 0x400000
3984#define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB__SHIFT 0x16
3985#define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD_MASK 0x800000
3986#define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD__SHIFT 0x17
3987#define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT_MASK 0x1000000
3988#define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT__SHIFT 0x18
3989#define DB_DEBUG3__DISABLE_DI_DT_STALL_MASK 0x2000000
3990#define DB_DEBUG3__DISABLE_DI_DT_STALL__SHIFT 0x19
3991#define DB_DEBUG3__ENABLE_DB_PROCESS_RESET_MASK 0x4000000
3992#define DB_DEBUG3__ENABLE_DB_PROCESS_RESET__SHIFT 0x1a
3993#define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX_MASK 0x8000000
3994#define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX__SHIFT 0x1b
3995#define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND_MASK 0x10000000
3996#define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND__SHIFT 0x1c
3997#define DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND_MASK 0x20000000
3998#define DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND__SHIFT 0x1d
3999#define DB_DEBUG3__DB_EXTRA_DEBUG3_MASK 0xc0000000
4000#define DB_DEBUG3__DB_EXTRA_DEBUG3__SHIFT 0x1e
4001#define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION_MASK 0x1
4002#define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION__SHIFT 0x0
4003#define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION_MASK 0x2
4004#define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION__SHIFT 0x1
4005#define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL_MASK 0x4
4006#define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL__SHIFT 0x2
4007#define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL_MASK 0x8
4008#define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL__SHIFT 0x3
4009#define DB_DEBUG4__DB_EXTRA_DEBUG4_MASK 0xfffffff0
4010#define DB_DEBUG4__DB_EXTRA_DEBUG4__SHIFT 0x4
4011#define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS_MASK 0x1f
4012#define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS__SHIFT 0x0
4013#define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS_MASK 0x3e0
4014#define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS__SHIFT 0x5
4015#define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS_MASK 0x1c00
4016#define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS__SHIFT 0xa
4017#define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS_MASK 0x7f000000
4018#define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS__SHIFT 0x18
4019#define DB_WATERMARKS__DEPTH_FREE_MASK 0x1f
4020#define DB_WATERMARKS__DEPTH_FREE__SHIFT 0x0
4021#define DB_WATERMARKS__DEPTH_FLUSH_MASK 0x7e0
4022#define DB_WATERMARKS__DEPTH_FLUSH__SHIFT 0x5
4023#define DB_WATERMARKS__FORCE_SUMMARIZE_MASK 0x7800
4024#define DB_WATERMARKS__FORCE_SUMMARIZE__SHIFT 0xb
4025#define DB_WATERMARKS__DEPTH_PENDING_FREE_MASK 0xf8000
4026#define DB_WATERMARKS__DEPTH_PENDING_FREE__SHIFT 0xf
4027#define DB_WATERMARKS__DEPTH_CACHELINE_FREE_MASK 0x7f00000
4028#define DB_WATERMARKS__DEPTH_CACHELINE_FREE__SHIFT 0x14
4029#define DB_WATERMARKS__EARLY_Z_PANIC_DISABLE_MASK 0x8000000
4030#define DB_WATERMARKS__EARLY_Z_PANIC_DISABLE__SHIFT 0x1b
4031#define DB_WATERMARKS__LATE_Z_PANIC_DISABLE_MASK 0x10000000
4032#define DB_WATERMARKS__LATE_Z_PANIC_DISABLE__SHIFT 0x1c
4033#define DB_WATERMARKS__RE_Z_PANIC_DISABLE_MASK 0x20000000
4034#define DB_WATERMARKS__RE_Z_PANIC_DISABLE__SHIFT 0x1d
4035#define DB_WATERMARKS__AUTO_FLUSH_HTILE_MASK 0x40000000
4036#define DB_WATERMARKS__AUTO_FLUSH_HTILE__SHIFT 0x1e
4037#define DB_WATERMARKS__AUTO_FLUSH_QUAD_MASK 0x80000000
4038#define DB_WATERMARKS__AUTO_FLUSH_QUAD__SHIFT 0x1f
4039#define DB_SUBTILE_CONTROL__MSAA1_X_MASK 0x3
4040#define DB_SUBTILE_CONTROL__MSAA1_X__SHIFT 0x0
4041#define DB_SUBTILE_CONTROL__MSAA1_Y_MASK 0xc
4042#define DB_SUBTILE_CONTROL__MSAA1_Y__SHIFT 0x2
4043#define DB_SUBTILE_CONTROL__MSAA2_X_MASK 0x30
4044#define DB_SUBTILE_CONTROL__MSAA2_X__SHIFT 0x4
4045#define DB_SUBTILE_CONTROL__MSAA2_Y_MASK 0xc0
4046#define DB_SUBTILE_CONTROL__MSAA2_Y__SHIFT 0x6
4047#define DB_SUBTILE_CONTROL__MSAA4_X_MASK 0x300
4048#define DB_SUBTILE_CONTROL__MSAA4_X__SHIFT 0x8
4049#define DB_SUBTILE_CONTROL__MSAA4_Y_MASK 0xc00
4050#define DB_SUBTILE_CONTROL__MSAA4_Y__SHIFT 0xa
4051#define DB_SUBTILE_CONTROL__MSAA8_X_MASK 0x3000
4052#define DB_SUBTILE_CONTROL__MSAA8_X__SHIFT 0xc
4053#define DB_SUBTILE_CONTROL__MSAA8_Y_MASK 0xc000
4054#define DB_SUBTILE_CONTROL__MSAA8_Y__SHIFT 0xe
4055#define DB_SUBTILE_CONTROL__MSAA16_X_MASK 0x30000
4056#define DB_SUBTILE_CONTROL__MSAA16_X__SHIFT 0x10
4057#define DB_SUBTILE_CONTROL__MSAA16_Y_MASK 0xc0000
4058#define DB_SUBTILE_CONTROL__MSAA16_Y__SHIFT 0x12
4059#define DB_FREE_CACHELINES__FREE_DTILE_DEPTH_MASK 0x7f
4060#define DB_FREE_CACHELINES__FREE_DTILE_DEPTH__SHIFT 0x0
4061#define DB_FREE_CACHELINES__FREE_PLANE_DEPTH_MASK 0x3f80
4062#define DB_FREE_CACHELINES__FREE_PLANE_DEPTH__SHIFT 0x7
4063#define DB_FREE_CACHELINES__FREE_Z_DEPTH_MASK 0x1fc000
4064#define DB_FREE_CACHELINES__FREE_Z_DEPTH__SHIFT 0xe
4065#define DB_FREE_CACHELINES__FREE_HTILE_DEPTH_MASK 0x1e00000
4066#define DB_FREE_CACHELINES__FREE_HTILE_DEPTH__SHIFT 0x15
4067#define DB_FREE_CACHELINES__QUAD_READ_REQS_MASK 0xfe000000
4068#define DB_FREE_CACHELINES__QUAD_READ_REQS__SHIFT 0x19
4069#define DB_FIFO_DEPTH1__MI_RDREQ_FIFO_DEPTH_MASK 0x1f
4070#define DB_FIFO_DEPTH1__MI_RDREQ_FIFO_DEPTH__SHIFT 0x0
4071#define DB_FIFO_DEPTH1__MI_WRREQ_FIFO_DEPTH_MASK 0x3e0
4072#define DB_FIFO_DEPTH1__MI_WRREQ_FIFO_DEPTH__SHIFT 0x5
4073#define DB_FIFO_DEPTH1__MCC_DEPTH_MASK 0xfc00
4074#define DB_FIFO_DEPTH1__MCC_DEPTH__SHIFT 0xa
4075#define DB_FIFO_DEPTH1__QC_DEPTH_MASK 0x1f0000
4076#define DB_FIFO_DEPTH1__QC_DEPTH__SHIFT 0x10
4077#define DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH_MASK 0x1fe00000
4078#define DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH__SHIFT 0x15
4079#define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH_MASK 0xff
4080#define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH__SHIFT 0x0
4081#define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH_MASK 0x7f00
4082#define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH__SHIFT 0x8
4083#define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH_MASK 0x1ff8000
4084#define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH__SHIFT 0xf
4085#define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH_MASK 0xfe000000
4086#define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH__SHIFT 0x19
4087#define DB_CGTT_CLK_CTRL_0__ON_DELAY_MASK 0xf
4088#define DB_CGTT_CLK_CTRL_0__ON_DELAY__SHIFT 0x0
4089#define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS_MASK 0xff0
4090#define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS__SHIFT 0x4
4091#define DB_CGTT_CLK_CTRL_0__RESERVED_MASK 0xfff000
4092#define DB_CGTT_CLK_CTRL_0__RESERVED__SHIFT 0xc
4093#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7_MASK 0x1000000
4094#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7__SHIFT 0x18
4095#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6_MASK 0x2000000
4096#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6__SHIFT 0x19
4097#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5_MASK 0x4000000
4098#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5__SHIFT 0x1a
4099#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4_MASK 0x8000000
4100#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4__SHIFT 0x1b
4101#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3_MASK 0x10000000
4102#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3__SHIFT 0x1c
4103#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2_MASK 0x20000000
4104#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2__SHIFT 0x1d
4105#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1_MASK 0x40000000
4106#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1__SHIFT 0x1e
4107#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0_MASK 0x80000000
4108#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0__SHIFT 0x1f
4109#define DB_ZPASS_COUNT_LOW__COUNT_LOW_MASK 0xffffffff
4110#define DB_ZPASS_COUNT_LOW__COUNT_LOW__SHIFT 0x0
4111#define DB_ZPASS_COUNT_HI__COUNT_HI_MASK 0x7fffffff
4112#define DB_ZPASS_COUNT_HI__COUNT_HI__SHIFT 0x0
4113#define DB_RING_CONTROL__COUNTER_CONTROL_MASK 0x3
4114#define DB_RING_CONTROL__COUNTER_CONTROL__SHIFT 0x0
4115#define DB_READ_DEBUG_0__BUSY_DATA0_MASK 0xffffffff
4116#define DB_READ_DEBUG_0__BUSY_DATA0__SHIFT 0x0
4117#define DB_READ_DEBUG_1__BUSY_DATA1_MASK 0xffffffff
4118#define DB_READ_DEBUG_1__BUSY_DATA1__SHIFT 0x0
4119#define DB_READ_DEBUG_2__BUSY_DATA2_MASK 0xffffffff
4120#define DB_READ_DEBUG_2__BUSY_DATA2__SHIFT 0x0
4121#define DB_READ_DEBUG_3__DEBUG_DATA_MASK 0xffffffff
4122#define DB_READ_DEBUG_3__DEBUG_DATA__SHIFT 0x0
4123#define DB_READ_DEBUG_4__DEBUG_DATA_MASK 0xffffffff
4124#define DB_READ_DEBUG_4__DEBUG_DATA__SHIFT 0x0
4125#define DB_READ_DEBUG_5__DEBUG_DATA_MASK 0xffffffff
4126#define DB_READ_DEBUG_5__DEBUG_DATA__SHIFT 0x0
4127#define DB_READ_DEBUG_6__DEBUG_DATA_MASK 0xffffffff
4128#define DB_READ_DEBUG_6__DEBUG_DATA__SHIFT 0x0
4129#define DB_READ_DEBUG_7__DEBUG_DATA_MASK 0xffffffff
4130#define DB_READ_DEBUG_7__DEBUG_DATA__SHIFT 0x0
4131#define DB_READ_DEBUG_8__DEBUG_DATA_MASK 0xffffffff
4132#define DB_READ_DEBUG_8__DEBUG_DATA__SHIFT 0x0
4133#define DB_READ_DEBUG_9__DEBUG_DATA_MASK 0xffffffff
4134#define DB_READ_DEBUG_9__DEBUG_DATA__SHIFT 0x0
4135#define DB_READ_DEBUG_A__DEBUG_DATA_MASK 0xffffffff
4136#define DB_READ_DEBUG_A__DEBUG_DATA__SHIFT 0x0
4137#define DB_READ_DEBUG_B__DEBUG_DATA_MASK 0xffffffff
4138#define DB_READ_DEBUG_B__DEBUG_DATA__SHIFT 0x0
4139#define DB_READ_DEBUG_C__DEBUG_DATA_MASK 0xffffffff
4140#define DB_READ_DEBUG_C__DEBUG_DATA__SHIFT 0x0
4141#define DB_READ_DEBUG_D__DEBUG_DATA_MASK 0xffffffff
4142#define DB_READ_DEBUG_D__DEBUG_DATA__SHIFT 0x0
4143#define DB_READ_DEBUG_E__DEBUG_DATA_MASK 0xffffffff
4144#define DB_READ_DEBUG_E__DEBUG_DATA__SHIFT 0x0
4145#define DB_READ_DEBUG_F__DEBUG_DATA_MASK 0xffffffff
4146#define DB_READ_DEBUG_F__DEBUG_DATA__SHIFT 0x0
4147#define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW_MASK 0xffffffff
4148#define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW__SHIFT 0x0
4149#define DB_OCCLUSION_COUNT0_HI__COUNT_HI_MASK 0x7fffffff
4150#define DB_OCCLUSION_COUNT0_HI__COUNT_HI__SHIFT 0x0
4151#define DB_OCCLUSION_COUNT1_LOW__COUNT_LOW_MASK 0xffffffff
4152#define DB_OCCLUSION_COUNT1_LOW__COUNT_LOW__SHIFT 0x0
4153#define DB_OCCLUSION_COUNT1_HI__COUNT_HI_MASK 0x7fffffff
4154#define DB_OCCLUSION_COUNT1_HI__COUNT_HI__SHIFT 0x0
4155#define DB_OCCLUSION_COUNT2_LOW__COUNT_LOW_MASK 0xffffffff
4156#define DB_OCCLUSION_COUNT2_LOW__COUNT_LOW__SHIFT 0x0
4157#define DB_OCCLUSION_COUNT2_HI__COUNT_HI_MASK 0x7fffffff
4158#define DB_OCCLUSION_COUNT2_HI__COUNT_HI__SHIFT 0x0
4159#define DB_OCCLUSION_COUNT3_LOW__COUNT_LOW_MASK 0xffffffff
4160#define DB_OCCLUSION_COUNT3_LOW__COUNT_LOW__SHIFT 0x0
4161#define DB_OCCLUSION_COUNT3_HI__COUNT_HI_MASK 0x7fffffff
4162#define DB_OCCLUSION_COUNT3_HI__COUNT_HI__SHIFT 0x0
4163#define CC_RB_REDUNDANCY__FAILED_RB0_MASK 0xf00
4164#define CC_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8
4165#define CC_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x1000
4166#define CC_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc
4167#define CC_RB_REDUNDANCY__FAILED_RB1_MASK 0xf0000
4168#define CC_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10
4169#define CC_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x100000
4170#define CC_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14
4171#define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0xff0000
4172#define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10
4173#define GC_USER_RB_REDUNDANCY__FAILED_RB0_MASK 0xf00
4174#define GC_USER_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8
4175#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x1000
4176#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc
4177#define GC_USER_RB_REDUNDANCY__FAILED_RB1_MASK 0xf0000
4178#define GC_USER_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10
4179#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x100000
4180#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14
4181#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0xff0000
4182#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10
4183#define GB_ADDR_CONFIG__NUM_PIPES_MASK 0x7
4184#define GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
4185#define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
4186#define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
4187#define GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700
4188#define GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
4189#define GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000
4190#define GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc
4191#define GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000
4192#define GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
4193#define GB_ADDR_CONFIG__NUM_GPUS_MASK 0x700000
4194#define GB_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
4195#define GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000
4196#define GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
4197#define GB_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000
4198#define GB_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
4199#define GB_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000
4200#define GB_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
4201#define GB_BACKEND_MAP__BACKEND_MAP_MASK 0xffffffff
4202#define GB_BACKEND_MAP__BACKEND_MAP__SHIFT 0x0
4203#define GB_GPU_ID__GPU_ID_MASK 0xf
4204#define GB_GPU_ID__GPU_ID__SHIFT 0x0
4205#define CC_RB_DAISY_CHAIN__RB_0_MASK 0xf
4206#define CC_RB_DAISY_CHAIN__RB_0__SHIFT 0x0
4207#define CC_RB_DAISY_CHAIN__RB_1_MASK 0xf0
4208#define CC_RB_DAISY_CHAIN__RB_1__SHIFT 0x4
4209#define CC_RB_DAISY_CHAIN__RB_2_MASK 0xf00
4210#define CC_RB_DAISY_CHAIN__RB_2__SHIFT 0x8
4211#define CC_RB_DAISY_CHAIN__RB_3_MASK 0xf000
4212#define CC_RB_DAISY_CHAIN__RB_3__SHIFT 0xc
4213#define CC_RB_DAISY_CHAIN__RB_4_MASK 0xf0000
4214#define CC_RB_DAISY_CHAIN__RB_4__SHIFT 0x10
4215#define CC_RB_DAISY_CHAIN__RB_5_MASK 0xf00000
4216#define CC_RB_DAISY_CHAIN__RB_5__SHIFT 0x14
4217#define CC_RB_DAISY_CHAIN__RB_6_MASK 0xf000000
4218#define CC_RB_DAISY_CHAIN__RB_6__SHIFT 0x18
4219#define CC_RB_DAISY_CHAIN__RB_7_MASK 0xf0000000
4220#define CC_RB_DAISY_CHAIN__RB_7__SHIFT 0x1c
4221#define GB_TILE_MODE0__ARRAY_MODE_MASK 0x3c
4222#define GB_TILE_MODE0__ARRAY_MODE__SHIFT 0x2
4223#define GB_TILE_MODE0__PIPE_CONFIG_MASK 0x7c0
4224#define GB_TILE_MODE0__PIPE_CONFIG__SHIFT 0x6
4225#define GB_TILE_MODE0__TILE_SPLIT_MASK 0x3800
4226#define GB_TILE_MODE0__TILE_SPLIT__SHIFT 0xb
4227#define GB_TILE_MODE0__MICRO_TILE_MODE_NEW_MASK 0x1c00000
4228#define GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT 0x16
4229#define GB_TILE_MODE0__SAMPLE_SPLIT_MASK 0x6000000
4230#define GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT 0x19
4231#define GB_TILE_MODE1__ARRAY_MODE_MASK 0x3c
4232#define GB_TILE_MODE1__ARRAY_MODE__SHIFT 0x2
4233#define GB_TILE_MODE1__PIPE_CONFIG_MASK 0x7c0
4234#define GB_TILE_MODE1__PIPE_CONFIG__SHIFT 0x6
4235#define GB_TILE_MODE1__TILE_SPLIT_MASK 0x3800
4236#define GB_TILE_MODE1__TILE_SPLIT__SHIFT 0xb
4237#define GB_TILE_MODE1__MICRO_TILE_MODE_NEW_MASK 0x1c00000
4238#define GB_TILE_MODE1__MICRO_TILE_MODE_NEW__SHIFT 0x16
4239#define GB_TILE_MODE1__SAMPLE_SPLIT_MASK 0x6000000
4240#define GB_TILE_MODE1__SAMPLE_SPLIT__SHIFT 0x19
4241#define GB_TILE_MODE2__ARRAY_MODE_MASK 0x3c
4242#define GB_TILE_MODE2__ARRAY_MODE__SHIFT 0x2
4243#define GB_TILE_MODE2__PIPE_CONFIG_MASK 0x7c0
4244#define GB_TILE_MODE2__PIPE_CONFIG__SHIFT 0x6
4245#define GB_TILE_MODE2__TILE_SPLIT_MASK 0x3800
4246#define GB_TILE_MODE2__TILE_SPLIT__SHIFT 0xb
4247#define GB_TILE_MODE2__MICRO_TILE_MODE_NEW_MASK 0x1c00000
4248#define GB_TILE_MODE2__MICRO_TILE_MODE_NEW__SHIFT 0x16
4249#define GB_TILE_MODE2__SAMPLE_SPLIT_MASK 0x6000000
4250#define GB_TILE_MODE2__SAMPLE_SPLIT__SHIFT 0x19
4251#define GB_TILE_MODE3__ARRAY_MODE_MASK 0x3c
4252#define GB_TILE_MODE3__ARRAY_MODE__SHIFT 0x2
4253#define GB_TILE_MODE3__PIPE_CONFIG_MASK 0x7c0
4254#define GB_TILE_MODE3__PIPE_CONFIG__SHIFT 0x6
4255#define GB_TILE_MODE3__TILE_SPLIT_MASK 0x3800
4256#define GB_TILE_MODE3__TILE_SPLIT__SHIFT 0xb
4257#define GB_TILE_MODE3__MICRO_TILE_MODE_NEW_MASK 0x1c00000
4258#define GB_TILE_MODE3__MICRO_TILE_MODE_NEW__SHIFT 0x16
4259#define GB_TILE_MODE3__SAMPLE_SPLIT_MASK 0x6000000
4260#define GB_TILE_MODE3__SAMPLE_SPLIT__SHIFT 0x19
4261#define GB_TILE_MODE4__ARRAY_MODE_MASK 0x3c
4262#define GB_TILE_MODE4__ARRAY_MODE__SHIFT 0x2
4263#define GB_TILE_MODE4__PIPE_CONFIG_MASK 0x7c0
4264#define GB_TILE_MODE4__PIPE_CONFIG__SHIFT 0x6
4265#define GB_TILE_MODE4__TILE_SPLIT_MASK 0x3800
4266#define GB_TILE_MODE4__TILE_SPLIT__SHIFT 0xb
4267#define GB_TILE_MODE4__MICRO_TILE_MODE_NEW_MASK 0x1c00000
4268#define GB_TILE_MODE4__MICRO_TILE_MODE_NEW__SHIFT 0x16
4269#define GB_TILE_MODE4__SAMPLE_SPLIT_MASK 0x6000000
4270#define GB_TILE_MODE4__SAMPLE_SPLIT__SHIFT 0x19
4271#define GB_TILE_MODE5__ARRAY_MODE_MASK 0x3c
4272#define GB_TILE_MODE5__ARRAY_MODE__SHIFT 0x2
4273#define GB_TILE_MODE5__PIPE_CONFIG_MASK 0x7c0
4274#define GB_TILE_MODE5__PIPE_CONFIG__SHIFT 0x6
4275#define GB_TILE_MODE5__TILE_SPLIT_MASK 0x3800
4276#define GB_TILE_MODE5__TILE_SPLIT__SHIFT 0xb
4277#define GB_TILE_MODE5__MICRO_TILE_MODE_NEW_MASK 0x1c00000
4278#define GB_TILE_MODE5__MICRO_TILE_MODE_NEW__SHIFT 0x16
4279#define GB_TILE_MODE5__SAMPLE_SPLIT_MASK 0x6000000
4280#define GB_TILE_MODE5__SAMPLE_SPLIT__SHIFT 0x19
4281#define GB_TILE_MODE6__ARRAY_MODE_MASK 0x3c
4282#define GB_TILE_MODE6__ARRAY_MODE__SHIFT 0x2
4283#define GB_TILE_MODE6__PIPE_CONFIG_MASK 0x7c0
4284#define GB_TILE_MODE6__PIPE_CONFIG__SHIFT 0x6
4285#define GB_TILE_MODE6__TILE_SPLIT_MASK 0x3800
4286#define GB_TILE_MODE6__TILE_SPLIT__SHIFT 0xb
4287#define GB_TILE_MODE6__MICRO_TILE_MODE_NEW_MASK 0x1c00000
4288#define GB_TILE_MODE6__MICRO_TILE_MODE_NEW__SHIFT 0x16
4289#define GB_TILE_MODE6__SAMPLE_SPLIT_MASK 0x6000000
4290#define GB_TILE_MODE6__SAMPLE_SPLIT__SHIFT 0x19
4291#define GB_TILE_MODE7__ARRAY_MODE_MASK 0x3c
4292#define GB_TILE_MODE7__ARRAY_MODE__SHIFT 0x2
4293#define GB_TILE_MODE7__PIPE_CONFIG_MASK 0x7c0
4294#define GB_TILE_MODE7__PIPE_CONFIG__SHIFT 0x6
4295#define GB_TILE_MODE7__TILE_SPLIT_MASK 0x3800
4296#define GB_TILE_MODE7__TILE_SPLIT__SHIFT 0xb
4297#define GB_TILE_MODE7__MICRO_TILE_MODE_NEW_MASK 0x1c00000
4298#define GB_TILE_MODE7__MICRO_TILE_MODE_NEW__SHIFT 0x16
4299#define GB_TILE_MODE7__SAMPLE_SPLIT_MASK 0x6000000
4300#define GB_TILE_MODE7__SAMPLE_SPLIT__SHIFT 0x19
4301#define GB_TILE_MODE8__ARRAY_MODE_MASK 0x3c
4302#define GB_TILE_MODE8__ARRAY_MODE__SHIFT 0x2
4303#define GB_TILE_MODE8__PIPE_CONFIG_MASK 0x7c0
4304#define GB_TILE_MODE8__PIPE_CONFIG__SHIFT 0x6
4305#define GB_TILE_MODE8__TILE_SPLIT_MASK 0x3800
4306#define GB_TILE_MODE8__TILE_SPLIT__SHIFT 0xb
4307#define GB_TILE_MODE8__MICRO_TILE_MODE_NEW_MASK 0x1c00000
4308#define GB_TILE_MODE8__MICRO_TILE_MODE_NEW__SHIFT 0x16
4309#define GB_TILE_MODE8__SAMPLE_SPLIT_MASK 0x6000000
4310#define GB_TILE_MODE8__SAMPLE_SPLIT__SHIFT 0x19
4311#define GB_TILE_MODE9__ARRAY_MODE_MASK 0x3c
4312#define GB_TILE_MODE9__ARRAY_MODE__SHIFT 0x2
4313#define GB_TILE_MODE9__PIPE_CONFIG_MASK 0x7c0
4314#define GB_TILE_MODE9__PIPE_CONFIG__SHIFT 0x6
4315#define GB_TILE_MODE9__TILE_SPLIT_MASK 0x3800
4316#define GB_TILE_MODE9__TILE_SPLIT__SHIFT 0xb
4317#define GB_TILE_MODE9__MICRO_TILE_MODE_NEW_MASK 0x1c00000
4318#define GB_TILE_MODE9__MICRO_TILE_MODE_NEW__SHIFT 0x16
4319#define GB_TILE_MODE9__SAMPLE_SPLIT_MASK 0x6000000
4320#define GB_TILE_MODE9__SAMPLE_SPLIT__SHIFT 0x19
4321#define GB_TILE_MODE10__ARRAY_MODE_MASK 0x3c
4322#define GB_TILE_MODE10__ARRAY_MODE__SHIFT 0x2
4323#define GB_TILE_MODE10__PIPE_CONFIG_MASK 0x7c0
4324#define GB_TILE_MODE10__PIPE_CONFIG__SHIFT 0x6
4325#define GB_TILE_MODE10__TILE_SPLIT_MASK 0x3800
4326#define GB_TILE_MODE10__TILE_SPLIT__SHIFT 0xb
4327#define GB_TILE_MODE10__MICRO_TILE_MODE_NEW_MASK 0x1c00000
4328#define GB_TILE_MODE10__MICRO_TILE_MODE_NEW__SHIFT 0x16
4329#define GB_TILE_MODE10__SAMPLE_SPLIT_MASK 0x6000000
4330#define GB_TILE_MODE10__SAMPLE_SPLIT__SHIFT 0x19
4331#define GB_TILE_MODE11__ARRAY_MODE_MASK 0x3c
4332#define GB_TILE_MODE11__ARRAY_MODE__SHIFT 0x2
4333#define GB_TILE_MODE11__PIPE_CONFIG_MASK 0x7c0
4334#define GB_TILE_MODE11__PIPE_CONFIG__SHIFT 0x6
4335#define GB_TILE_MODE11__TILE_SPLIT_MASK 0x3800
4336#define GB_TILE_MODE11__TILE_SPLIT__SHIFT 0xb
4337#define GB_TILE_MODE11__MICRO_TILE_MODE_NEW_MASK 0x1c00000
4338#define GB_TILE_MODE11__MICRO_TILE_MODE_NEW__SHIFT 0x16
4339#define GB_TILE_MODE11__SAMPLE_SPLIT_MASK 0x6000000
4340#define GB_TILE_MODE11__SAMPLE_SPLIT__SHIFT 0x19
4341#define GB_TILE_MODE12__ARRAY_MODE_MASK 0x3c
4342#define GB_TILE_MODE12__ARRAY_MODE__SHIFT 0x2
4343#define GB_TILE_MODE12__PIPE_CONFIG_MASK 0x7c0
4344#define GB_TILE_MODE12__PIPE_CONFIG__SHIFT 0x6
4345#define GB_TILE_MODE12__TILE_SPLIT_MASK 0x3800
4346#define GB_TILE_MODE12__TILE_SPLIT__SHIFT 0xb
4347#define GB_TILE_MODE12__MICRO_TILE_MODE_NEW_MASK 0x1c00000
4348#define GB_TILE_MODE12__MICRO_TILE_MODE_NEW__SHIFT 0x16
4349#define GB_TILE_MODE12__SAMPLE_SPLIT_MASK 0x6000000
4350#define GB_TILE_MODE12__SAMPLE_SPLIT__SHIFT 0x19
4351#define GB_TILE_MODE13__ARRAY_MODE_MASK 0x3c
4352#define GB_TILE_MODE13__ARRAY_MODE__SHIFT 0x2
4353#define GB_TILE_MODE13__PIPE_CONFIG_MASK 0x7c0
4354#define GB_TILE_MODE13__PIPE_CONFIG__SHIFT 0x6
4355#define GB_TILE_MODE13__TILE_SPLIT_MASK 0x3800
4356#define GB_TILE_MODE13__TILE_SPLIT__SHIFT 0xb
4357#define GB_TILE_MODE13__MICRO_TILE_MODE_NEW_MASK 0x1c00000
4358#define GB_TILE_MODE13__MICRO_TILE_MODE_NEW__SHIFT 0x16
4359#define GB_TILE_MODE13__SAMPLE_SPLIT_MASK 0x6000000
4360#define GB_TILE_MODE13__SAMPLE_SPLIT__SHIFT 0x19
4361#define GB_TILE_MODE14__ARRAY_MODE_MASK 0x3c
4362#define GB_TILE_MODE14__ARRAY_MODE__SHIFT 0x2
4363#define GB_TILE_MODE14__PIPE_CONFIG_MASK 0x7c0
4364#define GB_TILE_MODE14__PIPE_CONFIG__SHIFT 0x6
4365#define GB_TILE_MODE14__TILE_SPLIT_MASK 0x3800
4366#define GB_TILE_MODE14__TILE_SPLIT__SHIFT 0xb
4367#define GB_TILE_MODE14__MICRO_TILE_MODE_NEW_MASK 0x1c00000
4368#define GB_TILE_MODE14__MICRO_TILE_MODE_NEW__SHIFT 0x16
4369#define GB_TILE_MODE14__SAMPLE_SPLIT_MASK 0x6000000
4370#define GB_TILE_MODE14__SAMPLE_SPLIT__SHIFT 0x19
4371#define GB_TILE_MODE15__ARRAY_MODE_MASK 0x3c
4372#define GB_TILE_MODE15__ARRAY_MODE__SHIFT 0x2
4373#define GB_TILE_MODE15__PIPE_CONFIG_MASK 0x7c0
4374#define GB_TILE_MODE15__PIPE_CONFIG__SHIFT 0x6
4375#define GB_TILE_MODE15__TILE_SPLIT_MASK 0x3800
4376#define GB_TILE_MODE15__TILE_SPLIT__SHIFT 0xb
4377#define GB_TILE_MODE15__MICRO_TILE_MODE_NEW_MASK 0x1c00000
4378#define GB_TILE_MODE15__MICRO_TILE_MODE_NEW__SHIFT 0x16
4379#define GB_TILE_MODE15__SAMPLE_SPLIT_MASK 0x6000000
4380#define GB_TILE_MODE15__SAMPLE_SPLIT__SHIFT 0x19
4381#define GB_TILE_MODE16__ARRAY_MODE_MASK 0x3c
4382#define GB_TILE_MODE16__ARRAY_MODE__SHIFT 0x2
4383#define GB_TILE_MODE16__PIPE_CONFIG_MASK 0x7c0
4384#define GB_TILE_MODE16__PIPE_CONFIG__SHIFT 0x6
4385#define GB_TILE_MODE16__TILE_SPLIT_MASK 0x3800
4386#define GB_TILE_MODE16__TILE_SPLIT__SHIFT 0xb
4387#define GB_TILE_MODE16__MICRO_TILE_MODE_NEW_MASK 0x1c00000
4388#define GB_TILE_MODE16__MICRO_TILE_MODE_NEW__SHIFT 0x16
4389#define GB_TILE_MODE16__SAMPLE_SPLIT_MASK 0x6000000
4390#define GB_TILE_MODE16__SAMPLE_SPLIT__SHIFT 0x19
4391#define GB_TILE_MODE17__ARRAY_MODE_MASK 0x3c
4392#define GB_TILE_MODE17__ARRAY_MODE__SHIFT 0x2
4393#define GB_TILE_MODE17__PIPE_CONFIG_MASK 0x7c0
4394#define GB_TILE_MODE17__PIPE_CONFIG__SHIFT 0x6
4395#define GB_TILE_MODE17__TILE_SPLIT_MASK 0x3800
4396#define GB_TILE_MODE17__TILE_SPLIT__SHIFT 0xb
4397#define GB_TILE_MODE17__MICRO_TILE_MODE_NEW_MASK 0x1c00000
4398#define GB_TILE_MODE17__MICRO_TILE_MODE_NEW__SHIFT 0x16
4399#define GB_TILE_MODE17__SAMPLE_SPLIT_MASK 0x6000000
4400#define GB_TILE_MODE17__SAMPLE_SPLIT__SHIFT 0x19
4401#define GB_TILE_MODE18__ARRAY_MODE_MASK 0x3c
4402#define GB_TILE_MODE18__ARRAY_MODE__SHIFT 0x2
4403#define GB_TILE_MODE18__PIPE_CONFIG_MASK 0x7c0
4404#define GB_TILE_MODE18__PIPE_CONFIG__SHIFT 0x6
4405#define GB_TILE_MODE18__TILE_SPLIT_MASK 0x3800
4406#define GB_TILE_MODE18__TILE_SPLIT__SHIFT 0xb
4407#define GB_TILE_MODE18__MICRO_TILE_MODE_NEW_MASK 0x1c00000
4408#define GB_TILE_MODE18__MICRO_TILE_MODE_NEW__SHIFT 0x16
4409#define GB_TILE_MODE18__SAMPLE_SPLIT_MASK 0x6000000
4410#define GB_TILE_MODE18__SAMPLE_SPLIT__SHIFT 0x19
4411#define GB_TILE_MODE19__ARRAY_MODE_MASK 0x3c
4412#define GB_TILE_MODE19__ARRAY_MODE__SHIFT 0x2
4413#define GB_TILE_MODE19__PIPE_CONFIG_MASK 0x7c0
4414#define GB_TILE_MODE19__PIPE_CONFIG__SHIFT 0x6
4415#define GB_TILE_MODE19__TILE_SPLIT_MASK 0x3800
4416#define GB_TILE_MODE19__TILE_SPLIT__SHIFT 0xb
4417#define GB_TILE_MODE19__MICRO_TILE_MODE_NEW_MASK 0x1c00000
4418#define GB_TILE_MODE19__MICRO_TILE_MODE_NEW__SHIFT 0x16
4419#define GB_TILE_MODE19__SAMPLE_SPLIT_MASK 0x6000000
4420#define GB_TILE_MODE19__SAMPLE_SPLIT__SHIFT 0x19
4421#define GB_TILE_MODE20__ARRAY_MODE_MASK 0x3c
4422#define GB_TILE_MODE20__ARRAY_MODE__SHIFT 0x2
4423#define GB_TILE_MODE20__PIPE_CONFIG_MASK 0x7c0
4424#define GB_TILE_MODE20__PIPE_CONFIG__SHIFT 0x6
4425#define GB_TILE_MODE20__TILE_SPLIT_MASK 0x3800
4426#define GB_TILE_MODE20__TILE_SPLIT__SHIFT 0xb
4427#define GB_TILE_MODE20__MICRO_TILE_MODE_NEW_MASK 0x1c00000
4428#define GB_TILE_MODE20__MICRO_TILE_MODE_NEW__SHIFT 0x16
4429#define GB_TILE_MODE20__SAMPLE_SPLIT_MASK 0x6000000
4430#define GB_TILE_MODE20__SAMPLE_SPLIT__SHIFT 0x19
4431#define GB_TILE_MODE21__ARRAY_MODE_MASK 0x3c
4432#define GB_TILE_MODE21__ARRAY_MODE__SHIFT 0x2
4433#define GB_TILE_MODE21__PIPE_CONFIG_MASK 0x7c0
4434#define GB_TILE_MODE21__PIPE_CONFIG__SHIFT 0x6
4435#define GB_TILE_MODE21__TILE_SPLIT_MASK 0x3800
4436#define GB_TILE_MODE21__TILE_SPLIT__SHIFT 0xb
4437#define GB_TILE_MODE21__MICRO_TILE_MODE_NEW_MASK 0x1c00000
4438#define GB_TILE_MODE21__MICRO_TILE_MODE_NEW__SHIFT 0x16
4439#define GB_TILE_MODE21__SAMPLE_SPLIT_MASK 0x6000000
4440#define GB_TILE_MODE21__SAMPLE_SPLIT__SHIFT 0x19
4441#define GB_TILE_MODE22__ARRAY_MODE_MASK 0x3c
4442#define GB_TILE_MODE22__ARRAY_MODE__SHIFT 0x2
4443#define GB_TILE_MODE22__PIPE_CONFIG_MASK 0x7c0
4444#define GB_TILE_MODE22__PIPE_CONFIG__SHIFT 0x6
4445#define GB_TILE_MODE22__TILE_SPLIT_MASK 0x3800
4446#define GB_TILE_MODE22__TILE_SPLIT__SHIFT 0xb
4447#define GB_TILE_MODE22__MICRO_TILE_MODE_NEW_MASK 0x1c00000
4448#define GB_TILE_MODE22__MICRO_TILE_MODE_NEW__SHIFT 0x16
4449#define GB_TILE_MODE22__SAMPLE_SPLIT_MASK 0x6000000
4450#define GB_TILE_MODE22__SAMPLE_SPLIT__SHIFT 0x19
4451#define GB_TILE_MODE23__ARRAY_MODE_MASK 0x3c
4452#define GB_TILE_MODE23__ARRAY_MODE__SHIFT 0x2
4453#define GB_TILE_MODE23__PIPE_CONFIG_MASK 0x7c0
4454#define GB_TILE_MODE23__PIPE_CONFIG__SHIFT 0x6
4455#define GB_TILE_MODE23__TILE_SPLIT_MASK 0x3800
4456#define GB_TILE_MODE23__TILE_SPLIT__SHIFT 0xb
4457#define GB_TILE_MODE23__MICRO_TILE_MODE_NEW_MASK 0x1c00000
4458#define GB_TILE_MODE23__MICRO_TILE_MODE_NEW__SHIFT 0x16
4459#define GB_TILE_MODE23__SAMPLE_SPLIT_MASK 0x6000000
4460#define GB_TILE_MODE23__SAMPLE_SPLIT__SHIFT 0x19
4461#define GB_TILE_MODE24__ARRAY_MODE_MASK 0x3c
4462#define GB_TILE_MODE24__ARRAY_MODE__SHIFT 0x2
4463#define GB_TILE_MODE24__PIPE_CONFIG_MASK 0x7c0
4464#define GB_TILE_MODE24__PIPE_CONFIG__SHIFT 0x6
4465#define GB_TILE_MODE24__TILE_SPLIT_MASK 0x3800
4466#define GB_TILE_MODE24__TILE_SPLIT__SHIFT 0xb
4467#define GB_TILE_MODE24__MICRO_TILE_MODE_NEW_MASK 0x1c00000
4468#define GB_TILE_MODE24__MICRO_TILE_MODE_NEW__SHIFT 0x16
4469#define GB_TILE_MODE24__SAMPLE_SPLIT_MASK 0x6000000
4470#define GB_TILE_MODE24__SAMPLE_SPLIT__SHIFT 0x19
4471#define GB_TILE_MODE25__ARRAY_MODE_MASK 0x3c
4472#define GB_TILE_MODE25__ARRAY_MODE__SHIFT 0x2
4473#define GB_TILE_MODE25__PIPE_CONFIG_MASK 0x7c0
4474#define GB_TILE_MODE25__PIPE_CONFIG__SHIFT 0x6
4475#define GB_TILE_MODE25__TILE_SPLIT_MASK 0x3800
4476#define GB_TILE_MODE25__TILE_SPLIT__SHIFT 0xb
4477#define GB_TILE_MODE25__MICRO_TILE_MODE_NEW_MASK 0x1c00000
4478#define GB_TILE_MODE25__MICRO_TILE_MODE_NEW__SHIFT 0x16
4479#define GB_TILE_MODE25__SAMPLE_SPLIT_MASK 0x6000000
4480#define GB_TILE_MODE25__SAMPLE_SPLIT__SHIFT 0x19
4481#define GB_TILE_MODE26__ARRAY_MODE_MASK 0x3c
4482#define GB_TILE_MODE26__ARRAY_MODE__SHIFT 0x2
4483#define GB_TILE_MODE26__PIPE_CONFIG_MASK 0x7c0
4484#define GB_TILE_MODE26__PIPE_CONFIG__SHIFT 0x6
4485#define GB_TILE_MODE26__TILE_SPLIT_MASK 0x3800
4486#define GB_TILE_MODE26__TILE_SPLIT__SHIFT 0xb
4487#define GB_TILE_MODE26__MICRO_TILE_MODE_NEW_MASK 0x1c00000
4488#define GB_TILE_MODE26__MICRO_TILE_MODE_NEW__SHIFT 0x16
4489#define GB_TILE_MODE26__SAMPLE_SPLIT_MASK 0x6000000
4490#define GB_TILE_MODE26__SAMPLE_SPLIT__SHIFT 0x19
4491#define GB_TILE_MODE27__ARRAY_MODE_MASK 0x3c
4492#define GB_TILE_MODE27__ARRAY_MODE__SHIFT 0x2
4493#define GB_TILE_MODE27__PIPE_CONFIG_MASK 0x7c0
4494#define GB_TILE_MODE27__PIPE_CONFIG__SHIFT 0x6
4495#define GB_TILE_MODE27__TILE_SPLIT_MASK 0x3800
4496#define GB_TILE_MODE27__TILE_SPLIT__SHIFT 0xb
4497#define GB_TILE_MODE27__MICRO_TILE_MODE_NEW_MASK 0x1c00000
4498#define GB_TILE_MODE27__MICRO_TILE_MODE_NEW__SHIFT 0x16
4499#define GB_TILE_MODE27__SAMPLE_SPLIT_MASK 0x6000000
4500#define GB_TILE_MODE27__SAMPLE_SPLIT__SHIFT 0x19
4501#define GB_TILE_MODE28__ARRAY_MODE_MASK 0x3c
4502#define GB_TILE_MODE28__ARRAY_MODE__SHIFT 0x2
4503#define GB_TILE_MODE28__PIPE_CONFIG_MASK 0x7c0
4504#define GB_TILE_MODE28__PIPE_CONFIG__SHIFT 0x6
4505#define GB_TILE_MODE28__TILE_SPLIT_MASK 0x3800
4506#define GB_TILE_MODE28__TILE_SPLIT__SHIFT 0xb
4507#define GB_TILE_MODE28__MICRO_TILE_MODE_NEW_MASK 0x1c00000
4508#define GB_TILE_MODE28__MICRO_TILE_MODE_NEW__SHIFT 0x16
4509#define GB_TILE_MODE28__SAMPLE_SPLIT_MASK 0x6000000
4510#define GB_TILE_MODE28__SAMPLE_SPLIT__SHIFT 0x19
4511#define GB_TILE_MODE29__ARRAY_MODE_MASK 0x3c
4512#define GB_TILE_MODE29__ARRAY_MODE__SHIFT 0x2
4513#define GB_TILE_MODE29__PIPE_CONFIG_MASK 0x7c0
4514#define GB_TILE_MODE29__PIPE_CONFIG__SHIFT 0x6
4515#define GB_TILE_MODE29__TILE_SPLIT_MASK 0x3800
4516#define GB_TILE_MODE29__TILE_SPLIT__SHIFT 0xb
4517#define GB_TILE_MODE29__MICRO_TILE_MODE_NEW_MASK 0x1c00000
4518#define GB_TILE_MODE29__MICRO_TILE_MODE_NEW__SHIFT 0x16
4519#define GB_TILE_MODE29__SAMPLE_SPLIT_MASK 0x6000000
4520#define GB_TILE_MODE29__SAMPLE_SPLIT__SHIFT 0x19
4521#define GB_TILE_MODE30__ARRAY_MODE_MASK 0x3c
4522#define GB_TILE_MODE30__ARRAY_MODE__SHIFT 0x2
4523#define GB_TILE_MODE30__PIPE_CONFIG_MASK 0x7c0
4524#define GB_TILE_MODE30__PIPE_CONFIG__SHIFT 0x6
4525#define GB_TILE_MODE30__TILE_SPLIT_MASK 0x3800
4526#define GB_TILE_MODE30__TILE_SPLIT__SHIFT 0xb
4527#define GB_TILE_MODE30__MICRO_TILE_MODE_NEW_MASK 0x1c00000
4528#define GB_TILE_MODE30__MICRO_TILE_MODE_NEW__SHIFT 0x16
4529#define GB_TILE_MODE30__SAMPLE_SPLIT_MASK 0x6000000
4530#define GB_TILE_MODE30__SAMPLE_SPLIT__SHIFT 0x19
4531#define GB_TILE_MODE31__ARRAY_MODE_MASK 0x3c
4532#define GB_TILE_MODE31__ARRAY_MODE__SHIFT 0x2
4533#define GB_TILE_MODE31__PIPE_CONFIG_MASK 0x7c0
4534#define GB_TILE_MODE31__PIPE_CONFIG__SHIFT 0x6
4535#define GB_TILE_MODE31__TILE_SPLIT_MASK 0x3800
4536#define GB_TILE_MODE31__TILE_SPLIT__SHIFT 0xb
4537#define GB_TILE_MODE31__MICRO_TILE_MODE_NEW_MASK 0x1c00000
4538#define GB_TILE_MODE31__MICRO_TILE_MODE_NEW__SHIFT 0x16
4539#define GB_TILE_MODE31__SAMPLE_SPLIT_MASK 0x6000000
4540#define GB_TILE_MODE31__SAMPLE_SPLIT__SHIFT 0x19
4541#define GB_MACROTILE_MODE0__BANK_WIDTH_MASK 0x3
4542#define GB_MACROTILE_MODE0__BANK_WIDTH__SHIFT 0x0
4543#define GB_MACROTILE_MODE0__BANK_HEIGHT_MASK 0xc
4544#define GB_MACROTILE_MODE0__BANK_HEIGHT__SHIFT 0x2
4545#define GB_MACROTILE_MODE0__MACRO_TILE_ASPECT_MASK 0x30
4546#define GB_MACROTILE_MODE0__MACRO_TILE_ASPECT__SHIFT 0x4
4547#define GB_MACROTILE_MODE0__NUM_BANKS_MASK 0xc0
4548#define GB_MACROTILE_MODE0__NUM_BANKS__SHIFT 0x6
4549#define GB_MACROTILE_MODE1__BANK_WIDTH_MASK 0x3
4550#define GB_MACROTILE_MODE1__BANK_WIDTH__SHIFT 0x0
4551#define GB_MACROTILE_MODE1__BANK_HEIGHT_MASK 0xc
4552#define GB_MACROTILE_MODE1__BANK_HEIGHT__SHIFT 0x2
4553#define GB_MACROTILE_MODE1__MACRO_TILE_ASPECT_MASK 0x30
4554#define GB_MACROTILE_MODE1__MACRO_TILE_ASPECT__SHIFT 0x4
4555#define GB_MACROTILE_MODE1__NUM_BANKS_MASK 0xc0
4556#define GB_MACROTILE_MODE1__NUM_BANKS__SHIFT 0x6
4557#define GB_MACROTILE_MODE2__BANK_WIDTH_MASK 0x3
4558#define GB_MACROTILE_MODE2__BANK_WIDTH__SHIFT 0x0
4559#define GB_MACROTILE_MODE2__BANK_HEIGHT_MASK 0xc
4560#define GB_MACROTILE_MODE2__BANK_HEIGHT__SHIFT 0x2
4561#define GB_MACROTILE_MODE2__MACRO_TILE_ASPECT_MASK 0x30
4562#define GB_MACROTILE_MODE2__MACRO_TILE_ASPECT__SHIFT 0x4
4563#define GB_MACROTILE_MODE2__NUM_BANKS_MASK 0xc0
4564#define GB_MACROTILE_MODE2__NUM_BANKS__SHIFT 0x6
4565#define GB_MACROTILE_MODE3__BANK_WIDTH_MASK 0x3
4566#define GB_MACROTILE_MODE3__BANK_WIDTH__SHIFT 0x0
4567#define GB_MACROTILE_MODE3__BANK_HEIGHT_MASK 0xc
4568#define GB_MACROTILE_MODE3__BANK_HEIGHT__SHIFT 0x2
4569#define GB_MACROTILE_MODE3__MACRO_TILE_ASPECT_MASK 0x30
4570#define GB_MACROTILE_MODE3__MACRO_TILE_ASPECT__SHIFT 0x4
4571#define GB_MACROTILE_MODE3__NUM_BANKS_MASK 0xc0
4572#define GB_MACROTILE_MODE3__NUM_BANKS__SHIFT 0x6
4573#define GB_MACROTILE_MODE4__BANK_WIDTH_MASK 0x3
4574#define GB_MACROTILE_MODE4__BANK_WIDTH__SHIFT 0x0
4575#define GB_MACROTILE_MODE4__BANK_HEIGHT_MASK 0xc
4576#define GB_MACROTILE_MODE4__BANK_HEIGHT__SHIFT 0x2
4577#define GB_MACROTILE_MODE4__MACRO_TILE_ASPECT_MASK 0x30
4578#define GB_MACROTILE_MODE4__MACRO_TILE_ASPECT__SHIFT 0x4
4579#define GB_MACROTILE_MODE4__NUM_BANKS_MASK 0xc0
4580#define GB_MACROTILE_MODE4__NUM_BANKS__SHIFT 0x6
4581#define GB_MACROTILE_MODE5__BANK_WIDTH_MASK 0x3
4582#define GB_MACROTILE_MODE5__BANK_WIDTH__SHIFT 0x0
4583#define GB_MACROTILE_MODE5__BANK_HEIGHT_MASK 0xc
4584#define GB_MACROTILE_MODE5__BANK_HEIGHT__SHIFT 0x2
4585#define GB_MACROTILE_MODE5__MACRO_TILE_ASPECT_MASK 0x30
4586#define GB_MACROTILE_MODE5__MACRO_TILE_ASPECT__SHIFT 0x4
4587#define GB_MACROTILE_MODE5__NUM_BANKS_MASK 0xc0
4588#define GB_MACROTILE_MODE5__NUM_BANKS__SHIFT 0x6
4589#define GB_MACROTILE_MODE6__BANK_WIDTH_MASK 0x3
4590#define GB_MACROTILE_MODE6__BANK_WIDTH__SHIFT 0x0
4591#define GB_MACROTILE_MODE6__BANK_HEIGHT_MASK 0xc
4592#define GB_MACROTILE_MODE6__BANK_HEIGHT__SHIFT 0x2
4593#define GB_MACROTILE_MODE6__MACRO_TILE_ASPECT_MASK 0x30
4594#define GB_MACROTILE_MODE6__MACRO_TILE_ASPECT__SHIFT 0x4
4595#define GB_MACROTILE_MODE6__NUM_BANKS_MASK 0xc0
4596#define GB_MACROTILE_MODE6__NUM_BANKS__SHIFT 0x6
4597#define GB_MACROTILE_MODE7__BANK_WIDTH_MASK 0x3
4598#define GB_MACROTILE_MODE7__BANK_WIDTH__SHIFT 0x0
4599#define GB_MACROTILE_MODE7__BANK_HEIGHT_MASK 0xc
4600#define GB_MACROTILE_MODE7__BANK_HEIGHT__SHIFT 0x2
4601#define GB_MACROTILE_MODE7__MACRO_TILE_ASPECT_MASK 0x30
4602#define GB_MACROTILE_MODE7__MACRO_TILE_ASPECT__SHIFT 0x4
4603#define GB_MACROTILE_MODE7__NUM_BANKS_MASK 0xc0
4604#define GB_MACROTILE_MODE7__NUM_BANKS__SHIFT 0x6
4605#define GB_MACROTILE_MODE8__BANK_WIDTH_MASK 0x3
4606#define GB_MACROTILE_MODE8__BANK_WIDTH__SHIFT 0x0
4607#define GB_MACROTILE_MODE8__BANK_HEIGHT_MASK 0xc
4608#define GB_MACROTILE_MODE8__BANK_HEIGHT__SHIFT 0x2
4609#define GB_MACROTILE_MODE8__MACRO_TILE_ASPECT_MASK 0x30
4610#define GB_MACROTILE_MODE8__MACRO_TILE_ASPECT__SHIFT 0x4
4611#define GB_MACROTILE_MODE8__NUM_BANKS_MASK 0xc0
4612#define GB_MACROTILE_MODE8__NUM_BANKS__SHIFT 0x6
4613#define GB_MACROTILE_MODE9__BANK_WIDTH_MASK 0x3
4614#define GB_MACROTILE_MODE9__BANK_WIDTH__SHIFT 0x0
4615#define GB_MACROTILE_MODE9__BANK_HEIGHT_MASK 0xc
4616#define GB_MACROTILE_MODE9__BANK_HEIGHT__SHIFT 0x2
4617#define GB_MACROTILE_MODE9__MACRO_TILE_ASPECT_MASK 0x30
4618#define GB_MACROTILE_MODE9__MACRO_TILE_ASPECT__SHIFT 0x4
4619#define GB_MACROTILE_MODE9__NUM_BANKS_MASK 0xc0
4620#define GB_MACROTILE_MODE9__NUM_BANKS__SHIFT 0x6
4621#define GB_MACROTILE_MODE10__BANK_WIDTH_MASK 0x3
4622#define GB_MACROTILE_MODE10__BANK_WIDTH__SHIFT 0x0
4623#define GB_MACROTILE_MODE10__BANK_HEIGHT_MASK 0xc
4624#define GB_MACROTILE_MODE10__BANK_HEIGHT__SHIFT 0x2
4625#define GB_MACROTILE_MODE10__MACRO_TILE_ASPECT_MASK 0x30
4626#define GB_MACROTILE_MODE10__MACRO_TILE_ASPECT__SHIFT 0x4
4627#define GB_MACROTILE_MODE10__NUM_BANKS_MASK 0xc0
4628#define GB_MACROTILE_MODE10__NUM_BANKS__SHIFT 0x6
4629#define GB_MACROTILE_MODE11__BANK_WIDTH_MASK 0x3
4630#define GB_MACROTILE_MODE11__BANK_WIDTH__SHIFT 0x0
4631#define GB_MACROTILE_MODE11__BANK_HEIGHT_MASK 0xc
4632#define GB_MACROTILE_MODE11__BANK_HEIGHT__SHIFT 0x2
4633#define GB_MACROTILE_MODE11__MACRO_TILE_ASPECT_MASK 0x30
4634#define GB_MACROTILE_MODE11__MACRO_TILE_ASPECT__SHIFT 0x4
4635#define GB_MACROTILE_MODE11__NUM_BANKS_MASK 0xc0
4636#define GB_MACROTILE_MODE11__NUM_BANKS__SHIFT 0x6
4637#define GB_MACROTILE_MODE12__BANK_WIDTH_MASK 0x3
4638#define GB_MACROTILE_MODE12__BANK_WIDTH__SHIFT 0x0
4639#define GB_MACROTILE_MODE12__BANK_HEIGHT_MASK 0xc
4640#define GB_MACROTILE_MODE12__BANK_HEIGHT__SHIFT 0x2
4641#define GB_MACROTILE_MODE12__MACRO_TILE_ASPECT_MASK 0x30
4642#define GB_MACROTILE_MODE12__MACRO_TILE_ASPECT__SHIFT 0x4
4643#define GB_MACROTILE_MODE12__NUM_BANKS_MASK 0xc0
4644#define GB_MACROTILE_MODE12__NUM_BANKS__SHIFT 0x6
4645#define GB_MACROTILE_MODE13__BANK_WIDTH_MASK 0x3
4646#define GB_MACROTILE_MODE13__BANK_WIDTH__SHIFT 0x0
4647#define GB_MACROTILE_MODE13__BANK_HEIGHT_MASK 0xc
4648#define GB_MACROTILE_MODE13__BANK_HEIGHT__SHIFT 0x2
4649#define GB_MACROTILE_MODE13__MACRO_TILE_ASPECT_MASK 0x30
4650#define GB_MACROTILE_MODE13__MACRO_TILE_ASPECT__SHIFT 0x4
4651#define GB_MACROTILE_MODE13__NUM_BANKS_MASK 0xc0
4652#define GB_MACROTILE_MODE13__NUM_BANKS__SHIFT 0x6
4653#define GB_MACROTILE_MODE14__BANK_WIDTH_MASK 0x3
4654#define GB_MACROTILE_MODE14__BANK_WIDTH__SHIFT 0x0
4655#define GB_MACROTILE_MODE14__BANK_HEIGHT_MASK 0xc
4656#define GB_MACROTILE_MODE14__BANK_HEIGHT__SHIFT 0x2
4657#define GB_MACROTILE_MODE14__MACRO_TILE_ASPECT_MASK 0x30
4658#define GB_MACROTILE_MODE14__MACRO_TILE_ASPECT__SHIFT 0x4
4659#define GB_MACROTILE_MODE14__NUM_BANKS_MASK 0xc0
4660#define GB_MACROTILE_MODE14__NUM_BANKS__SHIFT 0x6
4661#define GB_MACROTILE_MODE15__BANK_WIDTH_MASK 0x3
4662#define GB_MACROTILE_MODE15__BANK_WIDTH__SHIFT 0x0
4663#define GB_MACROTILE_MODE15__BANK_HEIGHT_MASK 0xc
4664#define GB_MACROTILE_MODE15__BANK_HEIGHT__SHIFT 0x2
4665#define GB_MACROTILE_MODE15__MACRO_TILE_ASPECT_MASK 0x30
4666#define GB_MACROTILE_MODE15__MACRO_TILE_ASPECT__SHIFT 0x4
4667#define GB_MACROTILE_MODE15__NUM_BANKS_MASK 0xc0
4668#define GB_MACROTILE_MODE15__NUM_BANKS__SHIFT 0x6
4669#define GB_EDC_MODE__FORCE_SEC_ON_DED_MASK 0x10000
4670#define GB_EDC_MODE__FORCE_SEC_ON_DED__SHIFT 0x10
4671#define GB_EDC_MODE__DED_MODE_MASK 0x300000
4672#define GB_EDC_MODE__DED_MODE__SHIFT 0x14
4673#define GB_EDC_MODE__PROP_FED_MASK 0x20000000
4674#define GB_EDC_MODE__PROP_FED__SHIFT 0x1d
4675#define GB_EDC_MODE__BYPASS_MASK 0x80000000
4676#define GB_EDC_MODE__BYPASS__SHIFT 0x1f
4677#define CC_GC_EDC_CONFIG__DIS_EDC_MASK 0x2
4678#define CC_GC_EDC_CONFIG__DIS_EDC__SHIFT 0x1
4679#define RAS_SIGNATURE_CONTROL__ENABLE_MASK 0x1
4680#define RAS_SIGNATURE_CONTROL__ENABLE__SHIFT 0x0
4681#define RAS_SIGNATURE_MASK__INPUT_BUS_MASK_MASK 0xffffffff
4682#define RAS_SIGNATURE_MASK__INPUT_BUS_MASK__SHIFT 0x0
4683#define RAS_SX_SIGNATURE0__SIGNATURE_MASK 0xffffffff
4684#define RAS_SX_SIGNATURE0__SIGNATURE__SHIFT 0x0
4685#define RAS_SX_SIGNATURE1__SIGNATURE_MASK 0xffffffff
4686#define RAS_SX_SIGNATURE1__SIGNATURE__SHIFT 0x0
4687#define RAS_SX_SIGNATURE2__SIGNATURE_MASK 0xffffffff
4688#define RAS_SX_SIGNATURE2__SIGNATURE__SHIFT 0x0
4689#define RAS_SX_SIGNATURE3__SIGNATURE_MASK 0xffffffff
4690#define RAS_SX_SIGNATURE3__SIGNATURE__SHIFT 0x0
4691#define RAS_DB_SIGNATURE0__SIGNATURE_MASK 0xffffffff
4692#define RAS_DB_SIGNATURE0__SIGNATURE__SHIFT 0x0
4693#define RAS_PA_SIGNATURE0__SIGNATURE_MASK 0xffffffff
4694#define RAS_PA_SIGNATURE0__SIGNATURE__SHIFT 0x0
4695#define RAS_VGT_SIGNATURE0__SIGNATURE_MASK 0xffffffff
4696#define RAS_VGT_SIGNATURE0__SIGNATURE__SHIFT 0x0
4697#define RAS_SQ_SIGNATURE0__SIGNATURE_MASK 0xffffffff
4698#define RAS_SQ_SIGNATURE0__SIGNATURE__SHIFT 0x0
4699#define RAS_SC_SIGNATURE0__SIGNATURE_MASK 0xffffffff
4700#define RAS_SC_SIGNATURE0__SIGNATURE__SHIFT 0x0
4701#define RAS_SC_SIGNATURE1__SIGNATURE_MASK 0xffffffff
4702#define RAS_SC_SIGNATURE1__SIGNATURE__SHIFT 0x0
4703#define RAS_SC_SIGNATURE2__SIGNATURE_MASK 0xffffffff
4704#define RAS_SC_SIGNATURE2__SIGNATURE__SHIFT 0x0
4705#define RAS_SC_SIGNATURE3__SIGNATURE_MASK 0xffffffff
4706#define RAS_SC_SIGNATURE3__SIGNATURE__SHIFT 0x0
4707#define RAS_SC_SIGNATURE4__SIGNATURE_MASK 0xffffffff
4708#define RAS_SC_SIGNATURE4__SIGNATURE__SHIFT 0x0
4709#define RAS_SC_SIGNATURE5__SIGNATURE_MASK 0xffffffff
4710#define RAS_SC_SIGNATURE5__SIGNATURE__SHIFT 0x0
4711#define RAS_SC_SIGNATURE6__SIGNATURE_MASK 0xffffffff
4712#define RAS_SC_SIGNATURE6__SIGNATURE__SHIFT 0x0
4713#define RAS_SC_SIGNATURE7__SIGNATURE_MASK 0xffffffff
4714#define RAS_SC_SIGNATURE7__SIGNATURE__SHIFT 0x0
4715#define RAS_IA_SIGNATURE0__SIGNATURE_MASK 0xffffffff
4716#define RAS_IA_SIGNATURE0__SIGNATURE__SHIFT 0x0
4717#define RAS_IA_SIGNATURE1__SIGNATURE_MASK 0xffffffff
4718#define RAS_IA_SIGNATURE1__SIGNATURE__SHIFT 0x0
4719#define RAS_SPI_SIGNATURE0__SIGNATURE_MASK 0xffffffff
4720#define RAS_SPI_SIGNATURE0__SIGNATURE__SHIFT 0x0
4721#define RAS_SPI_SIGNATURE1__SIGNATURE_MASK 0xffffffff
4722#define RAS_SPI_SIGNATURE1__SIGNATURE__SHIFT 0x0
4723#define RAS_TA_SIGNATURE0__SIGNATURE_MASK 0xffffffff
4724#define RAS_TA_SIGNATURE0__SIGNATURE__SHIFT 0x0
4725#define RAS_TD_SIGNATURE0__SIGNATURE_MASK 0xffffffff
4726#define RAS_TD_SIGNATURE0__SIGNATURE__SHIFT 0x0
4727#define RAS_CB_SIGNATURE0__SIGNATURE_MASK 0xffffffff
4728#define RAS_CB_SIGNATURE0__SIGNATURE__SHIFT 0x0
4729#define RAS_BCI_SIGNATURE0__SIGNATURE_MASK 0xffffffff
4730#define RAS_BCI_SIGNATURE0__SIGNATURE__SHIFT 0x0
4731#define RAS_BCI_SIGNATURE1__SIGNATURE_MASK 0xffffffff
4732#define RAS_BCI_SIGNATURE1__SIGNATURE__SHIFT 0x0
4733#define GRBM_CAM_INDEX__CAM_INDEX_MASK 0x7
4734#define GRBM_CAM_INDEX__CAM_INDEX__SHIFT 0x0
4735#define GRBM_CAM_DATA__CAM_ADDR_MASK 0xffff
4736#define GRBM_CAM_DATA__CAM_ADDR__SHIFT 0x0
4737#define GRBM_CAM_DATA__CAM_REMAPADDR_MASK 0xffff0000
4738#define GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT 0x10
4739#define GRBM_CNTL__READ_TIMEOUT_MASK 0xff
4740#define GRBM_CNTL__READ_TIMEOUT__SHIFT 0x0
4741#define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD_MASK 0x3f
4742#define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD__SHIFT 0x0
4743#define GRBM_SKEW_CNTL__SKEW_COUNT_MASK 0xfc0
4744#define GRBM_SKEW_CNTL__SKEW_COUNT__SHIFT 0x6
4745#define GRBM_PWR_CNTL__REQ_TYPE_MASK 0xf
4746#define GRBM_PWR_CNTL__REQ_TYPE__SHIFT 0x0
4747#define GRBM_PWR_CNTL__RSP_TYPE_MASK 0xf0
4748#define GRBM_PWR_CNTL__RSP_TYPE__SHIFT 0x4
4749#define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL_MASK 0xf
4750#define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL__SHIFT 0x0
4751#define GRBM_STATUS__SRBM_RQ_PENDING_MASK 0x20
4752#define GRBM_STATUS__SRBM_RQ_PENDING__SHIFT 0x5
4753#define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING_MASK 0x80
4754#define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING__SHIFT 0x7
4755#define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING_MASK 0x100
4756#define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING__SHIFT 0x8
4757#define GRBM_STATUS__GDS_DMA_RQ_PENDING_MASK 0x200
4758#define GRBM_STATUS__GDS_DMA_RQ_PENDING__SHIFT 0x9
4759#define GRBM_STATUS__DB_CLEAN_MASK 0x1000
4760#define GRBM_STATUS__DB_CLEAN__SHIFT 0xc
4761#define GRBM_STATUS__CB_CLEAN_MASK 0x2000
4762#define GRBM_STATUS__CB_CLEAN__SHIFT 0xd
4763#define GRBM_STATUS__TA_BUSY_MASK 0x4000
4764#define GRBM_STATUS__TA_BUSY__SHIFT 0xe
4765#define GRBM_STATUS__GDS_BUSY_MASK 0x8000
4766#define GRBM_STATUS__GDS_BUSY__SHIFT 0xf
4767#define GRBM_STATUS__WD_BUSY_NO_DMA_MASK 0x10000
4768#define GRBM_STATUS__WD_BUSY_NO_DMA__SHIFT 0x10
4769#define GRBM_STATUS__VGT_BUSY_MASK 0x20000
4770#define GRBM_STATUS__VGT_BUSY__SHIFT 0x11
4771#define GRBM_STATUS__IA_BUSY_NO_DMA_MASK 0x40000
4772#define GRBM_STATUS__IA_BUSY_NO_DMA__SHIFT 0x12
4773#define GRBM_STATUS__IA_BUSY_MASK 0x80000
4774#define GRBM_STATUS__IA_BUSY__SHIFT 0x13
4775#define GRBM_STATUS__SX_BUSY_MASK 0x100000
4776#define GRBM_STATUS__SX_BUSY__SHIFT 0x14
4777#define GRBM_STATUS__WD_BUSY_MASK 0x200000
4778#define GRBM_STATUS__WD_BUSY__SHIFT 0x15
4779#define GRBM_STATUS__SPI_BUSY_MASK 0x400000
4780#define GRBM_STATUS__SPI_BUSY__SHIFT 0x16
4781#define GRBM_STATUS__BCI_BUSY_MASK 0x800000
4782#define GRBM_STATUS__BCI_BUSY__SHIFT 0x17
4783#define GRBM_STATUS__SC_BUSY_MASK 0x1000000
4784#define GRBM_STATUS__SC_BUSY__SHIFT 0x18
4785#define GRBM_STATUS__PA_BUSY_MASK 0x2000000
4786#define GRBM_STATUS__PA_BUSY__SHIFT 0x19
4787#define GRBM_STATUS__DB_BUSY_MASK 0x4000000
4788#define GRBM_STATUS__DB_BUSY__SHIFT 0x1a
4789#define GRBM_STATUS__CP_COHERENCY_BUSY_MASK 0x10000000
4790#define GRBM_STATUS__CP_COHERENCY_BUSY__SHIFT 0x1c
4791#define GRBM_STATUS__CP_BUSY_MASK 0x20000000
4792#define GRBM_STATUS__CP_BUSY__SHIFT 0x1d
4793#define GRBM_STATUS__CB_BUSY_MASK 0x40000000
4794#define GRBM_STATUS__CB_BUSY__SHIFT 0x1e
4795#define GRBM_STATUS__GUI_ACTIVE_MASK 0x80000000
4796#define GRBM_STATUS__GUI_ACTIVE__SHIFT 0x1f
4797#define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL_MASK 0xf
4798#define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL__SHIFT 0x0
4799#define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING_MASK 0x10
4800#define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING__SHIFT 0x4
4801#define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING_MASK 0x20
4802#define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING__SHIFT 0x5
4803#define GRBM_STATUS2__ME1PIPE0_RQ_PENDING_MASK 0x40
4804#define GRBM_STATUS2__ME1PIPE0_RQ_PENDING__SHIFT 0x6
4805#define GRBM_STATUS2__ME1PIPE1_RQ_PENDING_MASK 0x80
4806#define GRBM_STATUS2__ME1PIPE1_RQ_PENDING__SHIFT 0x7
4807#define GRBM_STATUS2__ME1PIPE2_RQ_PENDING_MASK 0x100
4808#define GRBM_STATUS2__ME1PIPE2_RQ_PENDING__SHIFT 0x8
4809#define GRBM_STATUS2__ME1PIPE3_RQ_PENDING_MASK 0x200
4810#define GRBM_STATUS2__ME1PIPE3_RQ_PENDING__SHIFT 0x9
4811#define GRBM_STATUS2__ME2PIPE0_RQ_PENDING_MASK 0x400
4812#define GRBM_STATUS2__ME2PIPE0_RQ_PENDING__SHIFT 0xa
4813#define GRBM_STATUS2__ME2PIPE1_RQ_PENDING_MASK 0x800
4814#define GRBM_STATUS2__ME2PIPE1_RQ_PENDING__SHIFT 0xb
4815#define GRBM_STATUS2__ME2PIPE2_RQ_PENDING_MASK 0x1000
4816#define GRBM_STATUS2__ME2PIPE2_RQ_PENDING__SHIFT 0xc
4817#define GRBM_STATUS2__ME2PIPE3_RQ_PENDING_MASK 0x2000
4818#define GRBM_STATUS2__ME2PIPE3_RQ_PENDING__SHIFT 0xd
4819#define GRBM_STATUS2__RLC_RQ_PENDING_MASK 0x4000
4820#define GRBM_STATUS2__RLC_RQ_PENDING__SHIFT 0xe
4821#define GRBM_STATUS2__RLC_BUSY_MASK 0x1000000
4822#define GRBM_STATUS2__RLC_BUSY__SHIFT 0x18
4823#define GRBM_STATUS2__TC_BUSY_MASK 0x2000000
4824#define GRBM_STATUS2__TC_BUSY__SHIFT 0x19
4825#define GRBM_STATUS2__CPF_BUSY_MASK 0x10000000
4826#define GRBM_STATUS2__CPF_BUSY__SHIFT 0x1c
4827#define GRBM_STATUS2__CPC_BUSY_MASK 0x20000000
4828#define GRBM_STATUS2__CPC_BUSY__SHIFT 0x1d
4829#define GRBM_STATUS2__CPG_BUSY_MASK 0x40000000
4830#define GRBM_STATUS2__CPG_BUSY__SHIFT 0x1e
4831#define GRBM_STATUS_SE0__DB_CLEAN_MASK 0x2
4832#define GRBM_STATUS_SE0__DB_CLEAN__SHIFT 0x1
4833#define GRBM_STATUS_SE0__CB_CLEAN_MASK 0x4
4834#define GRBM_STATUS_SE0__CB_CLEAN__SHIFT 0x2
4835#define GRBM_STATUS_SE0__BCI_BUSY_MASK 0x400000
4836#define GRBM_STATUS_SE0__BCI_BUSY__SHIFT 0x16
4837#define GRBM_STATUS_SE0__VGT_BUSY_MASK 0x800000
4838#define GRBM_STATUS_SE0__VGT_BUSY__SHIFT 0x17
4839#define GRBM_STATUS_SE0__PA_BUSY_MASK 0x1000000
4840#define GRBM_STATUS_SE0__PA_BUSY__SHIFT 0x18
4841#define GRBM_STATUS_SE0__TA_BUSY_MASK 0x2000000
4842#define GRBM_STATUS_SE0__TA_BUSY__SHIFT 0x19
4843#define GRBM_STATUS_SE0__SX_BUSY_MASK 0x4000000
4844#define GRBM_STATUS_SE0__SX_BUSY__SHIFT 0x1a
4845#define GRBM_STATUS_SE0__SPI_BUSY_MASK 0x8000000
4846#define GRBM_STATUS_SE0__SPI_BUSY__SHIFT 0x1b
4847#define GRBM_STATUS_SE0__SC_BUSY_MASK 0x20000000
4848#define GRBM_STATUS_SE0__SC_BUSY__SHIFT 0x1d
4849#define GRBM_STATUS_SE0__DB_BUSY_MASK 0x40000000
4850#define GRBM_STATUS_SE0__DB_BUSY__SHIFT 0x1e
4851#define GRBM_STATUS_SE0__CB_BUSY_MASK 0x80000000
4852#define GRBM_STATUS_SE0__CB_BUSY__SHIFT 0x1f
4853#define GRBM_STATUS_SE1__DB_CLEAN_MASK 0x2
4854#define GRBM_STATUS_SE1__DB_CLEAN__SHIFT 0x1
4855#define GRBM_STATUS_SE1__CB_CLEAN_MASK 0x4
4856#define GRBM_STATUS_SE1__CB_CLEAN__SHIFT 0x2
4857#define GRBM_STATUS_SE1__BCI_BUSY_MASK 0x400000
4858#define GRBM_STATUS_SE1__BCI_BUSY__SHIFT 0x16
4859#define GRBM_STATUS_SE1__VGT_BUSY_MASK 0x800000
4860#define GRBM_STATUS_SE1__VGT_BUSY__SHIFT 0x17
4861#define GRBM_STATUS_SE1__PA_BUSY_MASK 0x1000000
4862#define GRBM_STATUS_SE1__PA_BUSY__SHIFT 0x18
4863#define GRBM_STATUS_SE1__TA_BUSY_MASK 0x2000000
4864#define GRBM_STATUS_SE1__TA_BUSY__SHIFT 0x19
4865#define GRBM_STATUS_SE1__SX_BUSY_MASK 0x4000000
4866#define GRBM_STATUS_SE1__SX_BUSY__SHIFT 0x1a
4867#define GRBM_STATUS_SE1__SPI_BUSY_MASK 0x8000000
4868#define GRBM_STATUS_SE1__SPI_BUSY__SHIFT 0x1b
4869#define GRBM_STATUS_SE1__SC_BUSY_MASK 0x20000000
4870#define GRBM_STATUS_SE1__SC_BUSY__SHIFT 0x1d
4871#define GRBM_STATUS_SE1__DB_BUSY_MASK 0x40000000
4872#define GRBM_STATUS_SE1__DB_BUSY__SHIFT 0x1e
4873#define GRBM_STATUS_SE1__CB_BUSY_MASK 0x80000000
4874#define GRBM_STATUS_SE1__CB_BUSY__SHIFT 0x1f
4875#define GRBM_STATUS_SE2__DB_CLEAN_MASK 0x2
4876#define GRBM_STATUS_SE2__DB_CLEAN__SHIFT 0x1
4877#define GRBM_STATUS_SE2__CB_CLEAN_MASK 0x4
4878#define GRBM_STATUS_SE2__CB_CLEAN__SHIFT 0x2
4879#define GRBM_STATUS_SE2__BCI_BUSY_MASK 0x400000
4880#define GRBM_STATUS_SE2__BCI_BUSY__SHIFT 0x16
4881#define GRBM_STATUS_SE2__VGT_BUSY_MASK 0x800000
4882#define GRBM_STATUS_SE2__VGT_BUSY__SHIFT 0x17
4883#define GRBM_STATUS_SE2__PA_BUSY_MASK 0x1000000
4884#define GRBM_STATUS_SE2__PA_BUSY__SHIFT 0x18
4885#define GRBM_STATUS_SE2__TA_BUSY_MASK 0x2000000
4886#define GRBM_STATUS_SE2__TA_BUSY__SHIFT 0x19
4887#define GRBM_STATUS_SE2__SX_BUSY_MASK 0x4000000
4888#define GRBM_STATUS_SE2__SX_BUSY__SHIFT 0x1a
4889#define GRBM_STATUS_SE2__SPI_BUSY_MASK 0x8000000
4890#define GRBM_STATUS_SE2__SPI_BUSY__SHIFT 0x1b
4891#define GRBM_STATUS_SE2__SC_BUSY_MASK 0x20000000
4892#define GRBM_STATUS_SE2__SC_BUSY__SHIFT 0x1d
4893#define GRBM_STATUS_SE2__DB_BUSY_MASK 0x40000000
4894#define GRBM_STATUS_SE2__DB_BUSY__SHIFT 0x1e
4895#define GRBM_STATUS_SE2__CB_BUSY_MASK 0x80000000
4896#define GRBM_STATUS_SE2__CB_BUSY__SHIFT 0x1f
4897#define GRBM_STATUS_SE3__DB_CLEAN_MASK 0x2
4898#define GRBM_STATUS_SE3__DB_CLEAN__SHIFT 0x1
4899#define GRBM_STATUS_SE3__CB_CLEAN_MASK 0x4
4900#define GRBM_STATUS_SE3__CB_CLEAN__SHIFT 0x2
4901#define GRBM_STATUS_SE3__BCI_BUSY_MASK 0x400000
4902#define GRBM_STATUS_SE3__BCI_BUSY__SHIFT 0x16
4903#define GRBM_STATUS_SE3__VGT_BUSY_MASK 0x800000
4904#define GRBM_STATUS_SE3__VGT_BUSY__SHIFT 0x17
4905#define GRBM_STATUS_SE3__PA_BUSY_MASK 0x1000000
4906#define GRBM_STATUS_SE3__PA_BUSY__SHIFT 0x18
4907#define GRBM_STATUS_SE3__TA_BUSY_MASK 0x2000000
4908#define GRBM_STATUS_SE3__TA_BUSY__SHIFT 0x19
4909#define GRBM_STATUS_SE3__SX_BUSY_MASK 0x4000000
4910#define GRBM_STATUS_SE3__SX_BUSY__SHIFT 0x1a
4911#define GRBM_STATUS_SE3__SPI_BUSY_MASK 0x8000000
4912#define GRBM_STATUS_SE3__SPI_BUSY__SHIFT 0x1b
4913#define GRBM_STATUS_SE3__SC_BUSY_MASK 0x20000000
4914#define GRBM_STATUS_SE3__SC_BUSY__SHIFT 0x1d
4915#define GRBM_STATUS_SE3__DB_BUSY_MASK 0x40000000
4916#define GRBM_STATUS_SE3__DB_BUSY__SHIFT 0x1e
4917#define GRBM_STATUS_SE3__CB_BUSY_MASK 0x80000000
4918#define GRBM_STATUS_SE3__CB_BUSY__SHIFT 0x1f
4919#define GRBM_SOFT_RESET__SOFT_RESET_CP_MASK 0x1
4920#define GRBM_SOFT_RESET__SOFT_RESET_CP__SHIFT 0x0
4921#define GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK 0x4
4922#define GRBM_SOFT_RESET__SOFT_RESET_RLC__SHIFT 0x2
4923#define GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK 0x10000
4924#define GRBM_SOFT_RESET__SOFT_RESET_GFX__SHIFT 0x10
4925#define GRBM_SOFT_RESET__SOFT_RESET_CPF_MASK 0x20000
4926#define GRBM_SOFT_RESET__SOFT_RESET_CPF__SHIFT 0x11
4927#define GRBM_SOFT_RESET__SOFT_RESET_CPC_MASK 0x40000
4928#define GRBM_SOFT_RESET__SOFT_RESET_CPC__SHIFT 0x12
4929#define GRBM_SOFT_RESET__SOFT_RESET_CPG_MASK 0x80000
4930#define GRBM_SOFT_RESET__SOFT_RESET_CPG__SHIFT 0x13
4931#define GRBM_DEBUG_CNTL__GRBM_DEBUG_INDEX_MASK 0x3f
4932#define GRBM_DEBUG_CNTL__GRBM_DEBUG_INDEX__SHIFT 0x0
4933#define GRBM_DEBUG_DATA__DATA_MASK 0xffffffff
4934#define GRBM_DEBUG_DATA__DATA__SHIFT 0x0
4935#define GRBM_GFX_INDEX__INSTANCE_INDEX_MASK 0xff
4936#define GRBM_GFX_INDEX__INSTANCE_INDEX__SHIFT 0x0
4937#define GRBM_GFX_INDEX__SH_INDEX_MASK 0xff00
4938#define GRBM_GFX_INDEX__SH_INDEX__SHIFT 0x8
4939#define GRBM_GFX_INDEX__SE_INDEX_MASK 0xff0000
4940#define GRBM_GFX_INDEX__SE_INDEX__SHIFT 0x10
4941#define GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK 0x20000000
4942#define GRBM_GFX_INDEX__SH_BROADCAST_WRITES__SHIFT 0x1d
4943#define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK 0x40000000
4944#define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT 0x1e
4945#define GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK 0x80000000
4946#define GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT 0x1f
4947#define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf
4948#define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0
4949#define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00
4950#define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8
4951#define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_MASK 0xff
4952#define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS__SHIFT 0x0
4953#define GRBM_DEBUG__IGNORE_RDY_MASK 0x2
4954#define GRBM_DEBUG__IGNORE_RDY__SHIFT 0x1
4955#define GRBM_DEBUG__IGNORE_FAO_MASK 0x20
4956#define GRBM_DEBUG__IGNORE_FAO__SHIFT 0x5
4957#define GRBM_DEBUG__DISABLE_READ_TIMEOUT_MASK 0x40
4958#define GRBM_DEBUG__DISABLE_READ_TIMEOUT__SHIFT 0x6
4959#define GRBM_DEBUG__SNAPSHOT_FREE_CNTRS_MASK 0x80
4960#define GRBM_DEBUG__SNAPSHOT_FREE_CNTRS__SHIFT 0x7
4961#define GRBM_DEBUG__HYSTERESIS_GUI_ACTIVE_MASK 0xf00
4962#define GRBM_DEBUG__HYSTERESIS_GUI_ACTIVE__SHIFT 0x8
4963#define GRBM_DEBUG__GFX_CLOCK_DOMAIN_OVERRIDE_MASK 0x1000
4964#define GRBM_DEBUG__GFX_CLOCK_DOMAIN_OVERRIDE__SHIFT 0xc
4965#define GRBM_DEBUG_SNAPSHOT__CPF_RDY_MASK 0x1
4966#define GRBM_DEBUG_SNAPSHOT__CPF_RDY__SHIFT 0x0
4967#define GRBM_DEBUG_SNAPSHOT__CPG_RDY_MASK 0x2
4968#define GRBM_DEBUG_SNAPSHOT__CPG_RDY__SHIFT 0x1
4969#define GRBM_DEBUG_SNAPSHOT__SRBM_RDY_MASK 0x4
4970#define GRBM_DEBUG_SNAPSHOT__SRBM_RDY__SHIFT 0x2
4971#define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE0_RDY_MASK 0x8
4972#define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE0_RDY__SHIFT 0x3
4973#define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE1_RDY_MASK 0x10
4974#define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE1_RDY__SHIFT 0x4
4975#define GRBM_DEBUG_SNAPSHOT__GDS_RDY_MASK 0x20
4976#define GRBM_DEBUG_SNAPSHOT__GDS_RDY__SHIFT 0x5
4977#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY0_MASK 0x40
4978#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY0__SHIFT 0x6
4979#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY0_MASK 0x80
4980#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY0__SHIFT 0x7
4981#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY0_MASK 0x100
4982#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY0__SHIFT 0x8
4983#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY0_MASK 0x200
4984#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY0__SHIFT 0x9
4985#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY0_MASK 0x400
4986#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY0__SHIFT 0xa
4987#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY0_MASK 0x800
4988#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY0__SHIFT 0xb
4989#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY0_MASK 0x1000
4990#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY0__SHIFT 0xc
4991#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY0_MASK 0x2000
4992#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY0__SHIFT 0xd
4993#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY1_MASK 0x4000
4994#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY1__SHIFT 0xe
4995#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY1_MASK 0x8000
4996#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY1__SHIFT 0xf
4997#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY1_MASK 0x10000
4998#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY1__SHIFT 0x10
4999#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY1_MASK 0x20000
5000#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY1__SHIFT 0x11
5001#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY1_MASK 0x40000
5002#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY1__SHIFT 0x12
5003#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY1_MASK 0x80000
5004#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY1__SHIFT 0x13
5005#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY1_MASK 0x100000
5006#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY1__SHIFT 0x14
5007#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY1_MASK 0x200000
5008#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY1__SHIFT 0x15
5009#define GRBM_READ_ERROR__READ_ADDRESS_MASK 0x3fffc
5010#define GRBM_READ_ERROR__READ_ADDRESS__SHIFT 0x2
5011#define GRBM_READ_ERROR__READ_PIPEID_MASK 0x300000
5012#define GRBM_READ_ERROR__READ_PIPEID__SHIFT 0x14
5013#define GRBM_READ_ERROR__READ_MEID_MASK 0xc00000
5014#define GRBM_READ_ERROR__READ_MEID__SHIFT 0x16
5015#define GRBM_READ_ERROR__READ_ERROR_MASK 0x80000000
5016#define GRBM_READ_ERROR__READ_ERROR__SHIFT 0x1f
5017#define GRBM_READ_ERROR2__READ_REQUESTER_SRBM_MASK 0x20000
5018#define GRBM_READ_ERROR2__READ_REQUESTER_SRBM__SHIFT 0x11
5019#define GRBM_READ_ERROR2__READ_REQUESTER_RLC_MASK 0x40000
5020#define GRBM_READ_ERROR2__READ_REQUESTER_RLC__SHIFT 0x12
5021#define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA_MASK 0x80000
5022#define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA__SHIFT 0x13
5023#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF_MASK 0x100000
5024#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF__SHIFT 0x14
5025#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF_MASK 0x200000
5026#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF__SHIFT 0x15
5027#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF_MASK 0x400000
5028#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF__SHIFT 0x16
5029#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF_MASK 0x800000
5030#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF__SHIFT 0x17
5031#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0_MASK 0x1000000
5032#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0__SHIFT 0x18
5033#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1_MASK 0x2000000
5034#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1__SHIFT 0x19
5035#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2_MASK 0x4000000
5036#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2__SHIFT 0x1a
5037#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3_MASK 0x8000000
5038#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3__SHIFT 0x1b
5039#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0_MASK 0x10000000
5040#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0__SHIFT 0x1c
5041#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1_MASK 0x20000000
5042#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1__SHIFT 0x1d
5043#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2_MASK 0x40000000
5044#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2__SHIFT 0x1e
5045#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3_MASK 0x80000000
5046#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3__SHIFT 0x1f
5047#define GRBM_INT_CNTL__RDERR_INT_ENABLE_MASK 0x1
5048#define GRBM_INT_CNTL__RDERR_INT_ENABLE__SHIFT 0x0
5049#define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE_MASK 0x80000
5050#define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE__SHIFT 0x13
5051#define GRBM_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f
5052#define GRBM_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
5053#define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400
5054#define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
5055#define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800
5056#define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
5057#define GRBM_PERFCOUNTER0_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x1000
5058#define GRBM_PERFCOUNTER0_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0xc
5059#define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x2000
5060#define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xd
5061#define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x4000
5062#define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xe
5063#define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x10000
5064#define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x10
5065#define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x20000
5066#define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x11
5067#define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x40000
5068#define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x12
5069#define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK 0x80000
5070#define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT 0x13
5071#define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x100000
5072#define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x14
5073#define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x200000
5074#define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x15
5075#define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK 0x400000
5076#define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT 0x16
5077#define GRBM_PERFCOUNTER0_SELECT__IA_BUSY_USER_DEFINED_MASK_MASK 0x800000
5078#define GRBM_PERFCOUNTER0_SELECT__IA_BUSY_USER_DEFINED_MASK__SHIFT 0x17
5079#define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK 0x1000000
5080#define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT 0x18
5081#define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x2000000
5082#define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x19
5083#define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x4000000
5084#define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x1a
5085#define GRBM_PERFCOUNTER0_SELECT__TC_BUSY_USER_DEFINED_MASK_MASK 0x8000000
5086#define GRBM_PERFCOUNTER0_SELECT__TC_BUSY_USER_DEFINED_MASK__SHIFT 0x1b
5087#define GRBM_PERFCOUNTER0_SELECT__WD_BUSY_USER_DEFINED_MASK_MASK 0x10000000
5088#define GRBM_PERFCOUNTER0_SELECT__WD_BUSY_USER_DEFINED_MASK__SHIFT 0x1c
5089#define GRBM_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f
5090#define GRBM_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
5091#define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400
5092#define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
5093#define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800
5094#define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
5095#define GRBM_PERFCOUNTER1_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x1000
5096#define GRBM_PERFCOUNTER1_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0xc
5097#define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x2000
5098#define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xd
5099#define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x4000
5100#define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xe
5101#define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x10000
5102#define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x10
5103#define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x20000
5104#define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x11
5105#define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x40000
5106#define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x12
5107#define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK 0x80000
5108#define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT 0x13
5109#define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x100000
5110#define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x14
5111#define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x200000
5112#define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x15
5113#define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK 0x400000
5114#define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT 0x16
5115#define GRBM_PERFCOUNTER1_SELECT__IA_BUSY_USER_DEFINED_MASK_MASK 0x800000
5116#define GRBM_PERFCOUNTER1_SELECT__IA_BUSY_USER_DEFINED_MASK__SHIFT 0x17
5117#define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK 0x1000000
5118#define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT 0x18
5119#define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x2000000
5120#define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x19
5121#define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x4000000
5122#define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x1a
5123#define GRBM_PERFCOUNTER1_SELECT__TC_BUSY_USER_DEFINED_MASK_MASK 0x8000000
5124#define GRBM_PERFCOUNTER1_SELECT__TC_BUSY_USER_DEFINED_MASK__SHIFT 0x1b
5125#define GRBM_PERFCOUNTER1_SELECT__WD_BUSY_USER_DEFINED_MASK_MASK 0x10000000
5126#define GRBM_PERFCOUNTER1_SELECT__WD_BUSY_USER_DEFINED_MASK__SHIFT 0x1c
5127#define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x3f
5128#define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0
5129#define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400
5130#define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
5131#define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800
5132#define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
5133#define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x1000
5134#define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc
5135#define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x2000
5136#define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd
5137#define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x8000
5138#define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf
5139#define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x10000
5140#define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10
5141#define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x20000
5142#define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11
5143#define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x40000
5144#define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12
5145#define GRBM_SE0_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x80000
5146#define GRBM_SE0_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13
5147#define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x100000
5148#define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14
5149#define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x200000
5150#define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15
5151#define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x3f
5152#define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0
5153#define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400
5154#define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
5155#define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800
5156#define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
5157#define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x1000
5158#define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc
5159#define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x2000
5160#define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd
5161#define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x8000
5162#define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf
5163#define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x10000
5164#define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10
5165#define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x20000
5166#define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11
5167#define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x40000
5168#define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12
5169#define GRBM_SE1_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x80000
5170#define GRBM_SE1_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13
5171#define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x100000
5172#define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14
5173#define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x200000
5174#define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15
5175#define GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x3f
5176#define GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0
5177#define GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400
5178#define GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
5179#define GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800
5180#define GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
5181#define GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x1000
5182#define GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc
5183#define GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x2000
5184#define GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd
5185#define GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x8000
5186#define GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf
5187#define GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x10000
5188#define GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10
5189#define GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x20000
5190#define GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11
5191#define GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x40000
5192#define GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12
5193#define GRBM_SE2_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x80000
5194#define GRBM_SE2_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13
5195#define GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x100000
5196#define GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14
5197#define GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x200000
5198#define GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15
5199#define GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x3f
5200#define GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0
5201#define GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400
5202#define GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
5203#define GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800
5204#define GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
5205#define GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x1000
5206#define GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc
5207#define GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x2000
5208#define GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd
5209#define GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x8000
5210#define GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf
5211#define GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x10000
5212#define GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10
5213#define GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x20000
5214#define GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11
5215#define GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x40000
5216#define GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12
5217#define GRBM_SE3_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x80000
5218#define GRBM_SE3_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13
5219#define GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x100000
5220#define GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14
5221#define GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x200000
5222#define GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15
5223#define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
5224#define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
5225#define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
5226#define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
5227#define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
5228#define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
5229#define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
5230#define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
5231#define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xffffffff
5232#define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0
5233#define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xffffffff
5234#define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0
5235#define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xffffffff
5236#define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0
5237#define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xffffffff
5238#define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0
5239#define GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xffffffff
5240#define GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0
5241#define GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xffffffff
5242#define GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0
5243#define GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xffffffff
5244#define GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0
5245#define GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xffffffff
5246#define GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0
5247#define GRBM_SCRATCH_REG0__SCRATCH_REG0_MASK 0xffffffff
5248#define GRBM_SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x0
5249#define GRBM_SCRATCH_REG1__SCRATCH_REG1_MASK 0xffffffff
5250#define GRBM_SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x0
5251#define GRBM_SCRATCH_REG2__SCRATCH_REG2_MASK 0xffffffff
5252#define GRBM_SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x0
5253#define GRBM_SCRATCH_REG3__SCRATCH_REG3_MASK 0xffffffff
5254#define GRBM_SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x0
5255#define GRBM_SCRATCH_REG4__SCRATCH_REG4_MASK 0xffffffff
5256#define GRBM_SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x0
5257#define GRBM_SCRATCH_REG5__SCRATCH_REG5_MASK 0xffffffff
5258#define GRBM_SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x0
5259#define GRBM_SCRATCH_REG6__SCRATCH_REG6_MASK 0xffffffff
5260#define GRBM_SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x0
5261#define GRBM_SCRATCH_REG7__SCRATCH_REG7_MASK 0xffffffff
5262#define GRBM_SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x0
5263#define DEBUG_INDEX__DEBUG_INDEX_MASK 0x3ffff
5264#define DEBUG_INDEX__DEBUG_INDEX__SHIFT 0x0
5265#define DEBUG_DATA__DEBUG_DATA_MASK 0xffffffff
5266#define DEBUG_DATA__DEBUG_DATA__SHIFT 0x0
5267#define GRBM_NOWHERE__DATA_MASK 0xffffffff
5268#define GRBM_NOWHERE__DATA__SHIFT 0x0
5269#define PA_CL_VPORT_XSCALE__VPORT_XSCALE_MASK 0xffffffff
5270#define PA_CL_VPORT_XSCALE__VPORT_XSCALE__SHIFT 0x0
5271#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET_MASK 0xffffffff
5272#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET__SHIFT 0x0
5273#define PA_CL_VPORT_YSCALE__VPORT_YSCALE_MASK 0xffffffff
5274#define PA_CL_VPORT_YSCALE__VPORT_YSCALE__SHIFT 0x0
5275#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET_MASK 0xffffffff
5276#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET__SHIFT 0x0
5277#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE_MASK 0xffffffff
5278#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE__SHIFT 0x0
5279#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET_MASK 0xffffffff
5280#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET__SHIFT 0x0
5281#define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE_MASK 0xffffffff
5282#define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE__SHIFT 0x0
5283#define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE_MASK 0xffffffff
5284#define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE__SHIFT 0x0
5285#define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE_MASK 0xffffffff
5286#define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE__SHIFT 0x0
5287#define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE_MASK 0xffffffff
5288#define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE__SHIFT 0x0
5289#define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE_MASK 0xffffffff
5290#define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE__SHIFT 0x0
5291#define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE_MASK 0xffffffff
5292#define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE__SHIFT 0x0
5293#define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE_MASK 0xffffffff
5294#define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE__SHIFT 0x0
5295#define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE_MASK 0xffffffff
5296#define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE__SHIFT 0x0
5297#define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE_MASK 0xffffffff
5298#define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE__SHIFT 0x0
5299#define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE_MASK 0xffffffff
5300#define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE__SHIFT 0x0
5301#define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE_MASK 0xffffffff
5302#define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE__SHIFT 0x0
5303#define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE_MASK 0xffffffff
5304#define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE__SHIFT 0x0
5305#define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE_MASK 0xffffffff
5306#define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE__SHIFT 0x0
5307#define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE_MASK 0xffffffff
5308#define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE__SHIFT 0x0
5309#define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE_MASK 0xffffffff
5310#define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE__SHIFT 0x0
5311#define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET_MASK 0xffffffff
5312#define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET__SHIFT 0x0
5313#define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET_MASK 0xffffffff
5314#define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET__SHIFT 0x0
5315#define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET_MASK 0xffffffff
5316#define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET__SHIFT 0x0
5317#define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET_MASK 0xffffffff
5318#define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET__SHIFT 0x0
5319#define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET_MASK 0xffffffff
5320#define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET__SHIFT 0x0
5321#define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET_MASK 0xffffffff
5322#define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET__SHIFT 0x0
5323#define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET_MASK 0xffffffff
5324#define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET__SHIFT 0x0
5325#define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET_MASK 0xffffffff
5326#define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET__SHIFT 0x0
5327#define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET_MASK 0xffffffff
5328#define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET__SHIFT 0x0
5329#define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET_MASK 0xffffffff
5330#define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET__SHIFT 0x0
5331#define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET_MASK 0xffffffff
5332#define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET__SHIFT 0x0
5333#define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET_MASK 0xffffffff
5334#define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET__SHIFT 0x0
5335#define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET_MASK 0xffffffff
5336#define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET__SHIFT 0x0
5337#define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET_MASK 0xffffffff
5338#define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET__SHIFT 0x0
5339#define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET_MASK 0xffffffff
5340#define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET__SHIFT 0x0
5341#define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE_MASK 0xffffffff
5342#define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE__SHIFT 0x0
5343#define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE_MASK 0xffffffff
5344#define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE__SHIFT 0x0
5345#define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE_MASK 0xffffffff
5346#define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE__SHIFT 0x0
5347#define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE_MASK 0xffffffff
5348#define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE__SHIFT 0x0
5349#define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE_MASK 0xffffffff
5350#define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE__SHIFT 0x0
5351#define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE_MASK 0xffffffff
5352#define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE__SHIFT 0x0
5353#define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE_MASK 0xffffffff
5354#define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE__SHIFT 0x0
5355#define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE_MASK 0xffffffff
5356#define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE__SHIFT 0x0
5357#define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE_MASK 0xffffffff
5358#define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE__SHIFT 0x0
5359#define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE_MASK 0xffffffff
5360#define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE__SHIFT 0x0
5361#define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE_MASK 0xffffffff
5362#define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE__SHIFT 0x0
5363#define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE_MASK 0xffffffff
5364#define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE__SHIFT 0x0
5365#define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE_MASK 0xffffffff
5366#define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE__SHIFT 0x0
5367#define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE_MASK 0xffffffff
5368#define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE__SHIFT 0x0
5369#define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE_MASK 0xffffffff
5370#define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE__SHIFT 0x0
5371#define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET_MASK 0xffffffff
5372#define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET__SHIFT 0x0
5373#define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET_MASK 0xffffffff
5374#define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET__SHIFT 0x0
5375#define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET_MASK 0xffffffff
5376#define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET__SHIFT 0x0
5377#define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET_MASK 0xffffffff
5378#define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET__SHIFT 0x0
5379#define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET_MASK 0xffffffff
5380#define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET__SHIFT 0x0
5381#define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET_MASK 0xffffffff
5382#define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET__SHIFT 0x0
5383#define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET_MASK 0xffffffff
5384#define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET__SHIFT 0x0
5385#define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET_MASK 0xffffffff
5386#define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET__SHIFT 0x0
5387#define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET_MASK 0xffffffff
5388#define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET__SHIFT 0x0
5389#define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET_MASK 0xffffffff
5390#define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET__SHIFT 0x0
5391#define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET_MASK 0xffffffff
5392#define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET__SHIFT 0x0
5393#define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET_MASK 0xffffffff
5394#define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET__SHIFT 0x0
5395#define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET_MASK 0xffffffff
5396#define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET__SHIFT 0x0
5397#define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET_MASK 0xffffffff
5398#define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET__SHIFT 0x0
5399#define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET_MASK 0xffffffff
5400#define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET__SHIFT 0x0
5401#define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE_MASK 0xffffffff
5402#define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE__SHIFT 0x0
5403#define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE_MASK 0xffffffff
5404#define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE__SHIFT 0x0
5405#define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE_MASK 0xffffffff
5406#define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE__SHIFT 0x0
5407#define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE_MASK 0xffffffff
5408#define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE__SHIFT 0x0
5409#define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE_MASK 0xffffffff
5410#define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE__SHIFT 0x0
5411#define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE_MASK 0xffffffff
5412#define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE__SHIFT 0x0
5413#define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE_MASK 0xffffffff
5414#define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE__SHIFT 0x0
5415#define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE_MASK 0xffffffff
5416#define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE__SHIFT 0x0
5417#define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE_MASK 0xffffffff
5418#define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE__SHIFT 0x0
5419#define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE_MASK 0xffffffff
5420#define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE__SHIFT 0x0
5421#define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE_MASK 0xffffffff
5422#define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE__SHIFT 0x0
5423#define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE_MASK 0xffffffff
5424#define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE__SHIFT 0x0
5425#define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE_MASK 0xffffffff
5426#define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE__SHIFT 0x0
5427#define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE_MASK 0xffffffff
5428#define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE__SHIFT 0x0
5429#define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE_MASK 0xffffffff
5430#define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE__SHIFT 0x0
5431#define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET_MASK 0xffffffff
5432#define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET__SHIFT 0x0
5433#define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET_MASK 0xffffffff
5434#define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET__SHIFT 0x0
5435#define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET_MASK 0xffffffff
5436#define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET__SHIFT 0x0
5437#define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET_MASK 0xffffffff
5438#define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET__SHIFT 0x0
5439#define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET_MASK 0xffffffff
5440#define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET__SHIFT 0x0
5441#define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET_MASK 0xffffffff
5442#define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET__SHIFT 0x0
5443#define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET_MASK 0xffffffff
5444#define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET__SHIFT 0x0
5445#define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET_MASK 0xffffffff
5446#define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET__SHIFT 0x0
5447#define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET_MASK 0xffffffff
5448#define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET__SHIFT 0x0
5449#define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET_MASK 0xffffffff
5450#define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET__SHIFT 0x0
5451#define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET_MASK 0xffffffff
5452#define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET__SHIFT 0x0
5453#define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET_MASK 0xffffffff
5454#define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET__SHIFT 0x0
5455#define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET_MASK 0xffffffff
5456#define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET__SHIFT 0x0
5457#define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET_MASK 0xffffffff
5458#define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET__SHIFT 0x0
5459#define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET_MASK 0xffffffff
5460#define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET__SHIFT 0x0
5461#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA_MASK 0x1
5462#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA__SHIFT 0x0
5463#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA_MASK 0x2
5464#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA__SHIFT 0x1
5465#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA_MASK 0x4
5466#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA__SHIFT 0x2
5467#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA_MASK 0x8
5468#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA__SHIFT 0x3
5469#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA_MASK 0x10
5470#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA__SHIFT 0x4
5471#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA_MASK 0x20
5472#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA__SHIFT 0x5
5473#define PA_CL_VTE_CNTL__VTX_XY_FMT_MASK 0x100
5474#define PA_CL_VTE_CNTL__VTX_XY_FMT__SHIFT 0x8
5475#define PA_CL_VTE_CNTL__VTX_Z_FMT_MASK 0x200
5476#define PA_CL_VTE_CNTL__VTX_Z_FMT__SHIFT 0x9
5477#define PA_CL_VTE_CNTL__VTX_W0_FMT_MASK 0x400
5478#define PA_CL_VTE_CNTL__VTX_W0_FMT__SHIFT 0xa
5479#define PA_CL_VTE_CNTL__PERFCOUNTER_REF_MASK 0x800
5480#define PA_CL_VTE_CNTL__PERFCOUNTER_REF__SHIFT 0xb
5481#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0_MASK 0x1
5482#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0__SHIFT 0x0
5483#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1_MASK 0x2
5484#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1__SHIFT 0x1
5485#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2_MASK 0x4
5486#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2__SHIFT 0x2
5487#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3_MASK 0x8
5488#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3__SHIFT 0x3
5489#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4_MASK 0x10
5490#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4__SHIFT 0x4
5491#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5_MASK 0x20
5492#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5__SHIFT 0x5
5493#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6_MASK 0x40
5494#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6__SHIFT 0x6
5495#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7_MASK 0x80
5496#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7__SHIFT 0x7
5497#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0_MASK 0x100
5498#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0__SHIFT 0x8
5499#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1_MASK 0x200
5500#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1__SHIFT 0x9
5501#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2_MASK 0x400
5502#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2__SHIFT 0xa
5503#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3_MASK 0x800
5504#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3__SHIFT 0xb
5505#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4_MASK 0x1000
5506#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4__SHIFT 0xc
5507#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5_MASK 0x2000
5508#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5__SHIFT 0xd
5509#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6_MASK 0x4000
5510#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6__SHIFT 0xe
5511#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7_MASK 0x8000
5512#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7__SHIFT 0xf
5513#define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE_MASK 0x10000
5514#define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE__SHIFT 0x10
5515#define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG_MASK 0x20000
5516#define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG__SHIFT 0x11
5517#define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX_MASK 0x40000
5518#define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX__SHIFT 0x12
5519#define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX_MASK 0x80000
5520#define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX__SHIFT 0x13
5521#define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG_MASK 0x100000
5522#define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG__SHIFT 0x14
5523#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA_MASK 0x200000
5524#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA__SHIFT 0x15
5525#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA_MASK 0x400000
5526#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA__SHIFT 0x16
5527#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA_MASK 0x800000
5528#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA__SHIFT 0x17
5529#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA_MASK 0x1000000
5530#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA__SHIFT 0x18
5531#define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG_MASK 0x2000000
5532#define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG__SHIFT 0x19
5533#define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD_MASK 0x1
5534#define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD__SHIFT 0x0
5535#define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD_MASK 0x2
5536#define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD__SHIFT 0x1
5537#define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD_MASK 0x4
5538#define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD__SHIFT 0x2
5539#define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0_MASK 0x8
5540#define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0__SHIFT 0x3
5541#define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN_MASK 0x10
5542#define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN__SHIFT 0x4
5543#define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN_MASK 0x20
5544#define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN__SHIFT 0x5
5545#define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN_MASK 0x40
5546#define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN__SHIFT 0x6
5547#define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0_MASK 0x80
5548#define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0__SHIFT 0x7
5549#define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF_MASK 0x100
5550#define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF__SHIFT 0x8
5551#define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN_MASK 0x200
5552#define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN__SHIFT 0x9
5553#define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF_MASK 0x400
5554#define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF__SHIFT 0xa
5555#define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN_MASK 0x800
5556#define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN__SHIFT 0xb
5557#define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF_MASK 0x1000
5558#define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF__SHIFT 0xc
5559#define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN_MASK 0x2000
5560#define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN__SHIFT 0xd
5561#define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD_MASK 0x4000
5562#define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD__SHIFT 0xe
5563#define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0_MASK 0x100000
5564#define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0__SHIFT 0x14
5565#define PA_CL_CLIP_CNTL__UCP_ENA_0_MASK 0x1
5566#define PA_CL_CLIP_CNTL__UCP_ENA_0__SHIFT 0x0
5567#define PA_CL_CLIP_CNTL__UCP_ENA_1_MASK 0x2
5568#define PA_CL_CLIP_CNTL__UCP_ENA_1__SHIFT 0x1
5569#define PA_CL_CLIP_CNTL__UCP_ENA_2_MASK 0x4
5570#define PA_CL_CLIP_CNTL__UCP_ENA_2__SHIFT 0x2
5571#define PA_CL_CLIP_CNTL__UCP_ENA_3_MASK 0x8
5572#define PA_CL_CLIP_CNTL__UCP_ENA_3__SHIFT 0x3
5573#define PA_CL_CLIP_CNTL__UCP_ENA_4_MASK 0x10
5574#define PA_CL_CLIP_CNTL__UCP_ENA_4__SHIFT 0x4
5575#define PA_CL_CLIP_CNTL__UCP_ENA_5_MASK 0x20
5576#define PA_CL_CLIP_CNTL__UCP_ENA_5__SHIFT 0x5
5577#define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG_MASK 0x2000
5578#define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG__SHIFT 0xd
5579#define PA_CL_CLIP_CNTL__PS_UCP_MODE_MASK 0xc000
5580#define PA_CL_CLIP_CNTL__PS_UCP_MODE__SHIFT 0xe
5581#define PA_CL_CLIP_CNTL__CLIP_DISABLE_MASK 0x10000
5582#define PA_CL_CLIP_CNTL__CLIP_DISABLE__SHIFT 0x10
5583#define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA_MASK 0x20000
5584#define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA__SHIFT 0x11
5585#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA_MASK 0x40000
5586#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA__SHIFT 0x12
5587#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF_MASK 0x80000
5588#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF__SHIFT 0x13
5589#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT_MASK 0x100000
5590#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT__SHIFT 0x14
5591#define PA_CL_CLIP_CNTL__VTX_KILL_OR_MASK 0x200000
5592#define PA_CL_CLIP_CNTL__VTX_KILL_OR__SHIFT 0x15
5593#define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL_MASK 0x400000
5594#define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL__SHIFT 0x16
5595#define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA_MASK 0x1000000
5596#define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA__SHIFT 0x18
5597#define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE_MASK 0x2000000
5598#define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE__SHIFT 0x19
5599#define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE_MASK 0x4000000
5600#define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE__SHIFT 0x1a
5601#define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE_MASK 0x8000000
5602#define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE__SHIFT 0x1b
5603#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER_MASK 0xffffffff
5604#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER__SHIFT 0x0
5605#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER_MASK 0xffffffff
5606#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER__SHIFT 0x0
5607#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER_MASK 0xffffffff
5608#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER__SHIFT 0x0
5609#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER_MASK 0xffffffff
5610#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER__SHIFT 0x0
5611#define PA_CL_UCP_0_X__DATA_REGISTER_MASK 0xffffffff
5612#define PA_CL_UCP_0_X__DATA_REGISTER__SHIFT 0x0
5613#define PA_CL_UCP_0_Y__DATA_REGISTER_MASK 0xffffffff
5614#define PA_CL_UCP_0_Y__DATA_REGISTER__SHIFT 0x0
5615#define PA_CL_UCP_0_Z__DATA_REGISTER_MASK 0xffffffff
5616#define PA_CL_UCP_0_Z__DATA_REGISTER__SHIFT 0x0
5617#define PA_CL_UCP_0_W__DATA_REGISTER_MASK 0xffffffff
5618#define PA_CL_UCP_0_W__DATA_REGISTER__SHIFT 0x0
5619#define PA_CL_UCP_1_X__DATA_REGISTER_MASK 0xffffffff
5620#define PA_CL_UCP_1_X__DATA_REGISTER__SHIFT 0x0
5621#define PA_CL_UCP_1_Y__DATA_REGISTER_MASK 0xffffffff
5622#define PA_CL_UCP_1_Y__DATA_REGISTER__SHIFT 0x0
5623#define PA_CL_UCP_1_Z__DATA_REGISTER_MASK 0xffffffff
5624#define PA_CL_UCP_1_Z__DATA_REGISTER__SHIFT 0x0
5625#define PA_CL_UCP_1_W__DATA_REGISTER_MASK 0xffffffff
5626#define PA_CL_UCP_1_W__DATA_REGISTER__SHIFT 0x0
5627#define PA_CL_UCP_2_X__DATA_REGISTER_MASK 0xffffffff
5628#define PA_CL_UCP_2_X__DATA_REGISTER__SHIFT 0x0
5629#define PA_CL_UCP_2_Y__DATA_REGISTER_MASK 0xffffffff
5630#define PA_CL_UCP_2_Y__DATA_REGISTER__SHIFT 0x0
5631#define PA_CL_UCP_2_Z__DATA_REGISTER_MASK 0xffffffff
5632#define PA_CL_UCP_2_Z__DATA_REGISTER__SHIFT 0x0
5633#define PA_CL_UCP_2_W__DATA_REGISTER_MASK 0xffffffff
5634#define PA_CL_UCP_2_W__DATA_REGISTER__SHIFT 0x0
5635#define PA_CL_UCP_3_X__DATA_REGISTER_MASK 0xffffffff
5636#define PA_CL_UCP_3_X__DATA_REGISTER__SHIFT 0x0
5637#define PA_CL_UCP_3_Y__DATA_REGISTER_MASK 0xffffffff
5638#define PA_CL_UCP_3_Y__DATA_REGISTER__SHIFT 0x0
5639#define PA_CL_UCP_3_Z__DATA_REGISTER_MASK 0xffffffff
5640#define PA_CL_UCP_3_Z__DATA_REGISTER__SHIFT 0x0
5641#define PA_CL_UCP_3_W__DATA_REGISTER_MASK 0xffffffff
5642#define PA_CL_UCP_3_W__DATA_REGISTER__SHIFT 0x0
5643#define PA_CL_UCP_4_X__DATA_REGISTER_MASK 0xffffffff
5644#define PA_CL_UCP_4_X__DATA_REGISTER__SHIFT 0x0
5645#define PA_CL_UCP_4_Y__DATA_REGISTER_MASK 0xffffffff
5646#define PA_CL_UCP_4_Y__DATA_REGISTER__SHIFT 0x0
5647#define PA_CL_UCP_4_Z__DATA_REGISTER_MASK 0xffffffff
5648#define PA_CL_UCP_4_Z__DATA_REGISTER__SHIFT 0x0
5649#define PA_CL_UCP_4_W__DATA_REGISTER_MASK 0xffffffff
5650#define PA_CL_UCP_4_W__DATA_REGISTER__SHIFT 0x0
5651#define PA_CL_UCP_5_X__DATA_REGISTER_MASK 0xffffffff
5652#define PA_CL_UCP_5_X__DATA_REGISTER__SHIFT 0x0
5653#define PA_CL_UCP_5_Y__DATA_REGISTER_MASK 0xffffffff
5654#define PA_CL_UCP_5_Y__DATA_REGISTER__SHIFT 0x0
5655#define PA_CL_UCP_5_Z__DATA_REGISTER_MASK 0xffffffff
5656#define PA_CL_UCP_5_Z__DATA_REGISTER__SHIFT 0x0
5657#define PA_CL_UCP_5_W__DATA_REGISTER_MASK 0xffffffff
5658#define PA_CL_UCP_5_W__DATA_REGISTER__SHIFT 0x0
5659#define PA_CL_POINT_X_RAD__DATA_REGISTER_MASK 0xffffffff
5660#define PA_CL_POINT_X_RAD__DATA_REGISTER__SHIFT 0x0
5661#define PA_CL_POINT_Y_RAD__DATA_REGISTER_MASK 0xffffffff
5662#define PA_CL_POINT_Y_RAD__DATA_REGISTER__SHIFT 0x0
5663#define PA_CL_POINT_SIZE__DATA_REGISTER_MASK 0xffffffff
5664#define PA_CL_POINT_SIZE__DATA_REGISTER__SHIFT 0x0
5665#define PA_CL_POINT_CULL_RAD__DATA_REGISTER_MASK 0xffffffff
5666#define PA_CL_POINT_CULL_RAD__DATA_REGISTER__SHIFT 0x0
5667#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK 0x1
5668#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA__SHIFT 0x0
5669#define PA_CL_ENHANCE__NUM_CLIP_SEQ_MASK 0x6
5670#define PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT 0x1
5671#define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL_MASK 0x8
5672#define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL__SHIFT 0x3
5673#define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE_MASK 0x10
5674#define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE__SHIFT 0x4
5675#define PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL_MASK 0x20
5676#define PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL__SHIFT 0x5
5677#define PA_CL_ENHANCE__ECO_SPARE3_MASK 0x10000000
5678#define PA_CL_ENHANCE__ECO_SPARE3__SHIFT 0x1c
5679#define PA_CL_ENHANCE__ECO_SPARE2_MASK 0x20000000
5680#define PA_CL_ENHANCE__ECO_SPARE2__SHIFT 0x1d
5681#define PA_CL_ENHANCE__ECO_SPARE1_MASK 0x40000000
5682#define PA_CL_ENHANCE__ECO_SPARE1__SHIFT 0x1e
5683#define PA_CL_ENHANCE__ECO_SPARE0_MASK 0x80000000
5684#define PA_CL_ENHANCE__ECO_SPARE0__SHIFT 0x1f
5685#define PA_CL_RESET_DEBUG__CL_TRIV_DISC_DISABLE_MASK 0x1
5686#define PA_CL_RESET_DEBUG__CL_TRIV_DISC_DISABLE__SHIFT 0x0
5687#define PA_SU_VTX_CNTL__PIX_CENTER_MASK 0x1
5688#define PA_SU_VTX_CNTL__PIX_CENTER__SHIFT 0x0
5689#define PA_SU_VTX_CNTL__ROUND_MODE_MASK 0x6
5690#define PA_SU_VTX_CNTL__ROUND_MODE__SHIFT 0x1
5691#define PA_SU_VTX_CNTL__QUANT_MODE_MASK 0x38
5692#define PA_SU_VTX_CNTL__QUANT_MODE__SHIFT 0x3
5693#define PA_SU_POINT_SIZE__HEIGHT_MASK 0xffff
5694#define PA_SU_POINT_SIZE__HEIGHT__SHIFT 0x0
5695#define PA_SU_POINT_SIZE__WIDTH_MASK 0xffff0000
5696#define PA_SU_POINT_SIZE__WIDTH__SHIFT 0x10
5697#define PA_SU_POINT_MINMAX__MIN_SIZE_MASK 0xffff
5698#define PA_SU_POINT_MINMAX__MIN_SIZE__SHIFT 0x0
5699#define PA_SU_POINT_MINMAX__MAX_SIZE_MASK 0xffff0000
5700#define PA_SU_POINT_MINMAX__MAX_SIZE__SHIFT 0x10
5701#define PA_SU_LINE_CNTL__WIDTH_MASK 0xffff
5702#define PA_SU_LINE_CNTL__WIDTH__SHIFT 0x0
5703#define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET_MASK 0x3
5704#define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET__SHIFT 0x0
5705#define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH_MASK 0x4
5706#define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH__SHIFT 0x2
5707#define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM_MASK 0x8
5708#define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM__SHIFT 0x3
5709#define PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST_MASK 0x10
5710#define PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST__SHIFT 0x4
5711#define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE_MASK 0xffffffff
5712#define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE__SHIFT 0x0
5713#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE_MASK 0x1
5714#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE__SHIFT 0x0
5715#define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE_MASK 0x2
5716#define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE__SHIFT 0x1
5717#define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE_MASK 0x4
5718#define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE__SHIFT 0x2
5719#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE_MASK 0x8
5720#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE__SHIFT 0x3
5721#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA_MASK 0x10
5722#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA__SHIFT 0x4
5723#define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA_MASK 0x20
5724#define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA__SHIFT 0x5
5725#define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA_MASK 0x40
5726#define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA__SHIFT 0x6
5727#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA_MASK 0x80
5728#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA__SHIFT 0x7
5729#define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT_MASK 0xff00
5730#define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT__SHIFT 0x8
5731#define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION_MASK 0x40000000
5732#define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION__SHIFT 0x1e
5733#define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION_MASK 0x80000000
5734#define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION__SHIFT 0x1f
5735#define PA_SU_SC_MODE_CNTL__CULL_FRONT_MASK 0x1
5736#define PA_SU_SC_MODE_CNTL__CULL_FRONT__SHIFT 0x0
5737#define PA_SU_SC_MODE_CNTL__CULL_BACK_MASK 0x2
5738#define PA_SU_SC_MODE_CNTL__CULL_BACK__SHIFT 0x1
5739#define PA_SU_SC_MODE_CNTL__FACE_MASK 0x4
5740#define PA_SU_SC_MODE_CNTL__FACE__SHIFT 0x2
5741#define PA_SU_SC_MODE_CNTL__POLY_MODE_MASK 0x18
5742#define PA_SU_SC_MODE_CNTL__POLY_MODE__SHIFT 0x3
5743#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE_MASK 0xe0
5744#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE__SHIFT 0x5
5745#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE_MASK 0x700
5746#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE__SHIFT 0x8
5747#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE_MASK 0x800
5748#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE__SHIFT 0xb
5749#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE_MASK 0x1000
5750#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE__SHIFT 0xc
5751#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE_MASK 0x2000
5752#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE__SHIFT 0xd
5753#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE_MASK 0x10000
5754#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE__SHIFT 0x10
5755#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST_MASK 0x80000
5756#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST__SHIFT 0x13
5757#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS_MASK 0x100000
5758#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS__SHIFT 0x14
5759#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA_MASK 0x200000
5760#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT 0x15
5761#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS_MASK 0xff
5762#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS__SHIFT 0x0
5763#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT_MASK 0x100
5764#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT__SHIFT 0x8
5765#define PA_SU_POLY_OFFSET_CLAMP__CLAMP_MASK 0xffffffff
5766#define PA_SU_POLY_OFFSET_CLAMP__CLAMP__SHIFT 0x0
5767#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE_MASK 0xffffffff
5768#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE__SHIFT 0x0
5769#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET_MASK 0xffffffff
5770#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET__SHIFT 0x0
5771#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE_MASK 0xffffffff
5772#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE__SHIFT 0x0
5773#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET_MASK 0xffffffff
5774#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET__SHIFT 0x0
5775#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X_MASK 0x1ff
5776#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X__SHIFT 0x0
5777#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y_MASK 0x1ff0000
5778#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y__SHIFT 0x10
5779#define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE_MASK 0xffffff
5780#define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE__SHIFT 0x0
5781#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff
5782#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
5783#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00
5784#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
5785#define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
5786#define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
5787#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff
5788#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
5789#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00
5790#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
5791#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff
5792#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
5793#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00
5794#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
5795#define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
5796#define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
5797#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff
5798#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
5799#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00
5800#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
5801#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff
5802#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
5803#define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000
5804#define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
5805#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff
5806#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
5807#define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000
5808#define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
5809#define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
5810#define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
5811#define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffff
5812#define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
5813#define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
5814#define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
5815#define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffff
5816#define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
5817#define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
5818#define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
5819#define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffff
5820#define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
5821#define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
5822#define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
5823#define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffff
5824#define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
5825#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES_MASK 0x7
5826#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES__SHIFT 0x0
5827#define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN_MASK 0x10
5828#define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN__SHIFT 0x4
5829#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST_MASK 0x1e000
5830#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST__SHIFT 0xd
5831#define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES_MASK 0x700000
5832#define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES__SHIFT 0x14
5833#define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE_MASK 0x3000000
5834#define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE__SHIFT 0x18
5835#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0_MASK 0xffff
5836#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0__SHIFT 0x0
5837#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0_MASK 0xffff0000
5838#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0__SHIFT 0x10
5839#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1_MASK 0xffff
5840#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1__SHIFT 0x0
5841#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1_MASK 0xffff0000
5842#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1__SHIFT 0x10
5843#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X_MASK 0xf
5844#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X__SHIFT 0x0
5845#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y_MASK 0xf0
5846#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y__SHIFT 0x4
5847#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X_MASK 0xf00
5848#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X__SHIFT 0x8
5849#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y_MASK 0xf000
5850#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y__SHIFT 0xc
5851#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X_MASK 0xf0000
5852#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X__SHIFT 0x10
5853#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y_MASK 0xf00000
5854#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y__SHIFT 0x14
5855#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X_MASK 0xf000000
5856#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X__SHIFT 0x18
5857#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y_MASK 0xf0000000
5858#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y__SHIFT 0x1c
5859#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X_MASK 0xf
5860#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X__SHIFT 0x0
5861#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y_MASK 0xf0
5862#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y__SHIFT 0x4
5863#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X_MASK 0xf00
5864#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X__SHIFT 0x8
5865#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y_MASK 0xf000
5866#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y__SHIFT 0xc
5867#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X_MASK 0xf0000
5868#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X__SHIFT 0x10
5869#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y_MASK 0xf00000
5870#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y__SHIFT 0x14
5871#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X_MASK 0xf000000
5872#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X__SHIFT 0x18
5873#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y_MASK 0xf0000000
5874#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y__SHIFT 0x1c
5875#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X_MASK 0xf
5876#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X__SHIFT 0x0
5877#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y_MASK 0xf0
5878#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y__SHIFT 0x4
5879#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X_MASK 0xf00
5880#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X__SHIFT 0x8
5881#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y_MASK 0xf000
5882#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y__SHIFT 0xc
5883#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X_MASK 0xf0000
5884#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X__SHIFT 0x10
5885#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y_MASK 0xf00000
5886#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y__SHIFT 0x14
5887#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X_MASK 0xf000000
5888#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X__SHIFT 0x18
5889#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y_MASK 0xf0000000
5890#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y__SHIFT 0x1c
5891#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X_MASK 0xf
5892#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X__SHIFT 0x0
5893#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y_MASK 0xf0
5894#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y__SHIFT 0x4
5895#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X_MASK 0xf00
5896#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X__SHIFT 0x8
5897#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y_MASK 0xf000
5898#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y__SHIFT 0xc
5899#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X_MASK 0xf0000
5900#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X__SHIFT 0x10
5901#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y_MASK 0xf00000
5902#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y__SHIFT 0x14
5903#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X_MASK 0xf000000
5904#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X__SHIFT 0x18
5905#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y_MASK 0xf0000000
5906#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y__SHIFT 0x1c
5907#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X_MASK 0xf
5908#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X__SHIFT 0x0
5909#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y_MASK 0xf0
5910#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y__SHIFT 0x4
5911#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X_MASK 0xf00
5912#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X__SHIFT 0x8
5913#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y_MASK 0xf000
5914#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y__SHIFT 0xc
5915#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X_MASK 0xf0000
5916#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X__SHIFT 0x10
5917#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y_MASK 0xf00000
5918#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y__SHIFT 0x14
5919#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X_MASK 0xf000000
5920#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X__SHIFT 0x18
5921#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y_MASK 0xf0000000
5922#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y__SHIFT 0x1c
5923#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X_MASK 0xf
5924#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X__SHIFT 0x0
5925#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y_MASK 0xf0
5926#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y__SHIFT 0x4
5927#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X_MASK 0xf00
5928#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X__SHIFT 0x8
5929#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y_MASK 0xf000
5930#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y__SHIFT 0xc
5931#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X_MASK 0xf0000
5932#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X__SHIFT 0x10
5933#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y_MASK 0xf00000
5934#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y__SHIFT 0x14
5935#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X_MASK 0xf000000
5936#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X__SHIFT 0x18
5937#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y_MASK 0xf0000000
5938#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y__SHIFT 0x1c
5939#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X_MASK 0xf
5940#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X__SHIFT 0x0
5941#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y_MASK 0xf0
5942#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y__SHIFT 0x4
5943#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X_MASK 0xf00
5944#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X__SHIFT 0x8
5945#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y_MASK 0xf000
5946#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y__SHIFT 0xc
5947#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X_MASK 0xf0000
5948#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X__SHIFT 0x10
5949#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y_MASK 0xf00000
5950#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y__SHIFT 0x14
5951#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X_MASK 0xf000000
5952#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X__SHIFT 0x18
5953#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y_MASK 0xf0000000
5954#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y__SHIFT 0x1c
5955#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X_MASK 0xf
5956#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X__SHIFT 0x0
5957#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y_MASK 0xf0
5958#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y__SHIFT 0x4
5959#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X_MASK 0xf00
5960#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X__SHIFT 0x8
5961#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y_MASK 0xf000
5962#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y__SHIFT 0xc
5963#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X_MASK 0xf0000
5964#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X__SHIFT 0x10
5965#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y_MASK 0xf00000
5966#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y__SHIFT 0x14
5967#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X_MASK 0xf000000
5968#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X__SHIFT 0x18
5969#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y_MASK 0xf0000000
5970#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y__SHIFT 0x1c
5971#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X_MASK 0xf
5972#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X__SHIFT 0x0
5973#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y_MASK 0xf0
5974#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y__SHIFT 0x4
5975#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X_MASK 0xf00
5976#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X__SHIFT 0x8
5977#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y_MASK 0xf000
5978#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y__SHIFT 0xc
5979#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X_MASK 0xf0000
5980#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X__SHIFT 0x10
5981#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y_MASK 0xf00000
5982#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y__SHIFT 0x14
5983#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X_MASK 0xf000000
5984#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X__SHIFT 0x18
5985#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y_MASK 0xf0000000
5986#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y__SHIFT 0x1c
5987#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X_MASK 0xf
5988#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X__SHIFT 0x0
5989#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y_MASK 0xf0
5990#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y__SHIFT 0x4
5991#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X_MASK 0xf00
5992#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X__SHIFT 0x8
5993#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y_MASK 0xf000
5994#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y__SHIFT 0xc
5995#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X_MASK 0xf0000
5996#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X__SHIFT 0x10
5997#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y_MASK 0xf00000
5998#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y__SHIFT 0x14
5999#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X_MASK 0xf000000
6000#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X__SHIFT 0x18
6001#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y_MASK 0xf0000000
6002#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y__SHIFT 0x1c
6003#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X_MASK 0xf
6004#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X__SHIFT 0x0
6005#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y_MASK 0xf0
6006#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y__SHIFT 0x4
6007#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X_MASK 0xf00
6008#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X__SHIFT 0x8
6009#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y_MASK 0xf000
6010#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y__SHIFT 0xc
6011#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X_MASK 0xf0000
6012#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X__SHIFT 0x10
6013#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y_MASK 0xf00000
6014#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y__SHIFT 0x14
6015#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X_MASK 0xf000000
6016#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X__SHIFT 0x18
6017#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y_MASK 0xf0000000
6018#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y__SHIFT 0x1c
6019#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X_MASK 0xf
6020#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X__SHIFT 0x0
6021#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y_MASK 0xf0
6022#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y__SHIFT 0x4
6023#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X_MASK 0xf00
6024#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X__SHIFT 0x8
6025#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y_MASK 0xf000
6026#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y__SHIFT 0xc
6027#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X_MASK 0xf0000
6028#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X__SHIFT 0x10
6029#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y_MASK 0xf00000
6030#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y__SHIFT 0x14
6031#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X_MASK 0xf000000
6032#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X__SHIFT 0x18
6033#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y_MASK 0xf0000000
6034#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y__SHIFT 0x1c
6035#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X_MASK 0xf
6036#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X__SHIFT 0x0
6037#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y_MASK 0xf0
6038#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y__SHIFT 0x4
6039#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X_MASK 0xf00
6040#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X__SHIFT 0x8
6041#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y_MASK 0xf000
6042#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y__SHIFT 0xc
6043#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X_MASK 0xf0000
6044#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X__SHIFT 0x10
6045#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y_MASK 0xf00000
6046#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y__SHIFT 0x14
6047#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X_MASK 0xf000000
6048#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X__SHIFT 0x18
6049#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y_MASK 0xf0000000
6050#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y__SHIFT 0x1c
6051#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X_MASK 0xf
6052#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X__SHIFT 0x0
6053#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y_MASK 0xf0
6054#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y__SHIFT 0x4
6055#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X_MASK 0xf00
6056#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X__SHIFT 0x8
6057#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y_MASK 0xf000
6058#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y__SHIFT 0xc
6059#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X_MASK 0xf0000
6060#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X__SHIFT 0x10
6061#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y_MASK 0xf00000
6062#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y__SHIFT 0x14
6063#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X_MASK 0xf000000
6064#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X__SHIFT 0x18
6065#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y_MASK 0xf0000000
6066#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y__SHIFT 0x1c
6067#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X_MASK 0xf
6068#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X__SHIFT 0x0
6069#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y_MASK 0xf0
6070#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y__SHIFT 0x4
6071#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X_MASK 0xf00
6072#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X__SHIFT 0x8
6073#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y_MASK 0xf000
6074#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y__SHIFT 0xc
6075#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X_MASK 0xf0000
6076#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X__SHIFT 0x10
6077#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y_MASK 0xf00000
6078#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y__SHIFT 0x14
6079#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X_MASK 0xf000000
6080#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X__SHIFT 0x18
6081#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y_MASK 0xf0000000
6082#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y__SHIFT 0x1c
6083#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X_MASK 0xf
6084#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X__SHIFT 0x0
6085#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y_MASK 0xf0
6086#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y__SHIFT 0x4
6087#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X_MASK 0xf00
6088#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X__SHIFT 0x8
6089#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y_MASK 0xf000
6090#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y__SHIFT 0xc
6091#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X_MASK 0xf0000
6092#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X__SHIFT 0x10
6093#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y_MASK 0xf00000
6094#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y__SHIFT 0x14
6095#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X_MASK 0xf000000
6096#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X__SHIFT 0x18
6097#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y_MASK 0xf0000000
6098#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y__SHIFT 0x1c
6099#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0_MASK 0xf
6100#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0__SHIFT 0x0
6101#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1_MASK 0xf0
6102#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1__SHIFT 0x4
6103#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2_MASK 0xf00
6104#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2__SHIFT 0x8
6105#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3_MASK 0xf000
6106#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3__SHIFT 0xc
6107#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4_MASK 0xf0000
6108#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4__SHIFT 0x10
6109#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5_MASK 0xf00000
6110#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5__SHIFT 0x14
6111#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6_MASK 0xf000000
6112#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6__SHIFT 0x18
6113#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7_MASK 0xf0000000
6114#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7__SHIFT 0x1c
6115#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8_MASK 0xf
6116#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8__SHIFT 0x0
6117#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9_MASK 0xf0
6118#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9__SHIFT 0x4
6119#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10_MASK 0xf00
6120#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10__SHIFT 0x8
6121#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11_MASK 0xf000
6122#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11__SHIFT 0xc
6123#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12_MASK 0xf0000
6124#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12__SHIFT 0x10
6125#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13_MASK 0xf00000
6126#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13__SHIFT 0x14
6127#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14_MASK 0xf000000
6128#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14__SHIFT 0x18
6129#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15_MASK 0xf0000000
6130#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15__SHIFT 0x1c
6131#define PA_SC_CLIPRECT_0_TL__TL_X_MASK 0x7fff
6132#define PA_SC_CLIPRECT_0_TL__TL_X__SHIFT 0x0
6133#define PA_SC_CLIPRECT_0_TL__TL_Y_MASK 0x7fff0000
6134#define PA_SC_CLIPRECT_0_TL__TL_Y__SHIFT 0x10
6135#define PA_SC_CLIPRECT_0_BR__BR_X_MASK 0x7fff
6136#define PA_SC_CLIPRECT_0_BR__BR_X__SHIFT 0x0
6137#define PA_SC_CLIPRECT_0_BR__BR_Y_MASK 0x7fff0000
6138#define PA_SC_CLIPRECT_0_BR__BR_Y__SHIFT 0x10
6139#define PA_SC_CLIPRECT_1_TL__TL_X_MASK 0x7fff
6140#define PA_SC_CLIPRECT_1_TL__TL_X__SHIFT 0x0
6141#define PA_SC_CLIPRECT_1_TL__TL_Y_MASK 0x7fff0000
6142#define PA_SC_CLIPRECT_1_TL__TL_Y__SHIFT 0x10
6143#define PA_SC_CLIPRECT_1_BR__BR_X_MASK 0x7fff
6144#define PA_SC_CLIPRECT_1_BR__BR_X__SHIFT 0x0
6145#define PA_SC_CLIPRECT_1_BR__BR_Y_MASK 0x7fff0000
6146#define PA_SC_CLIPRECT_1_BR__BR_Y__SHIFT 0x10
6147#define PA_SC_CLIPRECT_2_TL__TL_X_MASK 0x7fff
6148#define PA_SC_CLIPRECT_2_TL__TL_X__SHIFT 0x0
6149#define PA_SC_CLIPRECT_2_TL__TL_Y_MASK 0x7fff0000
6150#define PA_SC_CLIPRECT_2_TL__TL_Y__SHIFT 0x10
6151#define PA_SC_CLIPRECT_2_BR__BR_X_MASK 0x7fff
6152#define PA_SC_CLIPRECT_2_BR__BR_X__SHIFT 0x0
6153#define PA_SC_CLIPRECT_2_BR__BR_Y_MASK 0x7fff0000
6154#define PA_SC_CLIPRECT_2_BR__BR_Y__SHIFT 0x10
6155#define PA_SC_CLIPRECT_3_TL__TL_X_MASK 0x7fff
6156#define PA_SC_CLIPRECT_3_TL__TL_X__SHIFT 0x0
6157#define PA_SC_CLIPRECT_3_TL__TL_Y_MASK 0x7fff0000
6158#define PA_SC_CLIPRECT_3_TL__TL_Y__SHIFT 0x10
6159#define PA_SC_CLIPRECT_3_BR__BR_X_MASK 0x7fff
6160#define PA_SC_CLIPRECT_3_BR__BR_X__SHIFT 0x0
6161#define PA_SC_CLIPRECT_3_BR__BR_Y_MASK 0x7fff0000
6162#define PA_SC_CLIPRECT_3_BR__BR_Y__SHIFT 0x10
6163#define PA_SC_CLIPRECT_RULE__CLIP_RULE_MASK 0xffff
6164#define PA_SC_CLIPRECT_RULE__CLIP_RULE__SHIFT 0x0
6165#define PA_SC_EDGERULE__ER_TRI_MASK 0xf
6166#define PA_SC_EDGERULE__ER_TRI__SHIFT 0x0
6167#define PA_SC_EDGERULE__ER_POINT_MASK 0xf0
6168#define PA_SC_EDGERULE__ER_POINT__SHIFT 0x4
6169#define PA_SC_EDGERULE__ER_RECT_MASK 0xf00
6170#define PA_SC_EDGERULE__ER_RECT__SHIFT 0x8
6171#define PA_SC_EDGERULE__ER_LINE_LR_MASK 0x3f000
6172#define PA_SC_EDGERULE__ER_LINE_LR__SHIFT 0xc
6173#define PA_SC_EDGERULE__ER_LINE_RL_MASK 0xfc0000
6174#define PA_SC_EDGERULE__ER_LINE_RL__SHIFT 0x12
6175#define PA_SC_EDGERULE__ER_LINE_TB_MASK 0xf000000
6176#define PA_SC_EDGERULE__ER_LINE_TB__SHIFT 0x18
6177#define PA_SC_EDGERULE__ER_LINE_BT_MASK 0xf0000000
6178#define PA_SC_EDGERULE__ER_LINE_BT__SHIFT 0x1c
6179#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH_MASK 0x200
6180#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH__SHIFT 0x9
6181#define PA_SC_LINE_CNTL__LAST_PIXEL_MASK 0x400
6182#define PA_SC_LINE_CNTL__LAST_PIXEL__SHIFT 0xa
6183#define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA_MASK 0x800
6184#define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA__SHIFT 0xb
6185#define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA_MASK 0x1000
6186#define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA__SHIFT 0xc
6187#define PA_SC_LINE_STIPPLE__LINE_PATTERN_MASK 0xffff
6188#define PA_SC_LINE_STIPPLE__LINE_PATTERN__SHIFT 0x0
6189#define PA_SC_LINE_STIPPLE__REPEAT_COUNT_MASK 0xff0000
6190#define PA_SC_LINE_STIPPLE__REPEAT_COUNT__SHIFT 0x10
6191#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER_MASK 0x10000000
6192#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER__SHIFT 0x1c
6193#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL_MASK 0x60000000
6194#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL__SHIFT 0x1d
6195#define PA_SC_MODE_CNTL_0__MSAA_ENABLE_MASK 0x1
6196#define PA_SC_MODE_CNTL_0__MSAA_ENABLE__SHIFT 0x0
6197#define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE_MASK 0x2
6198#define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE__SHIFT 0x1
6199#define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE_MASK 0x4
6200#define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE__SHIFT 0x2
6201#define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR_MASK 0x8
6202#define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR__SHIFT 0x3
6203#define PA_SC_MODE_CNTL_1__WALK_SIZE_MASK 0x1
6204#define PA_SC_MODE_CNTL_1__WALK_SIZE__SHIFT 0x0
6205#define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT_MASK 0x2
6206#define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT__SHIFT 0x1
6207#define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST_MASK 0x4
6208#define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST__SHIFT 0x2
6209#define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE_MASK 0x8
6210#define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE__SHIFT 0x3
6211#define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE_MASK 0x70
6212#define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE__SHIFT 0x4
6213#define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE_MASK 0x80
6214#define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE__SHIFT 0x7
6215#define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE_MASK 0x100
6216#define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE__SHIFT 0x8
6217#define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE_MASK 0x200
6218#define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE__SHIFT 0x9
6219#define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR_MASK 0x400
6220#define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR__SHIFT 0xa
6221#define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT_MASK 0x800
6222#define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT__SHIFT 0xb
6223#define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET_MASK 0x1000
6224#define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET__SHIFT 0xc
6225#define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT_MASK 0x2000
6226#define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT__SHIFT 0xd
6227#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z_MASK 0x4000
6228#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z__SHIFT 0xe
6229#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK_MASK 0x8000
6230#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK__SHIFT 0xf
6231#define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE_MASK 0x10000
6232#define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE__SHIFT 0x10
6233#define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE_MASK 0x20000
6234#define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE__SHIFT 0x11
6235#define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE_MASK 0x40000
6236#define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE__SHIFT 0x12
6237#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE_MASK 0x80000
6238#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE__SHIFT 0x13
6239#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_MASK 0xf00000
6240#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE__SHIFT 0x14
6241#define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE_MASK 0x1000000
6242#define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE__SHIFT 0x18
6243#define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE_MASK 0x2000000
6244#define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE__SHIFT 0x19
6245#define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE_MASK 0x4000000
6246#define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE__SHIFT 0x1a
6247#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE_MASK 0x8000000
6248#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE__SHIFT 0x1b
6249#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK_MASK 0x70000000
6250#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK__SHIFT 0x1c
6251#define PA_SC_RASTER_CONFIG__RB_MAP_PKR0_MASK 0x3
6252#define PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT 0x0
6253#define PA_SC_RASTER_CONFIG__RB_MAP_PKR1_MASK 0xc
6254#define PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT 0x2
6255#define PA_SC_RASTER_CONFIG__RB_XSEL2_MASK 0x30
6256#define PA_SC_RASTER_CONFIG__RB_XSEL2__SHIFT 0x4
6257#define PA_SC_RASTER_CONFIG__RB_XSEL_MASK 0x40
6258#define PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT 0x6
6259#define PA_SC_RASTER_CONFIG__RB_YSEL_MASK 0x80
6260#define PA_SC_RASTER_CONFIG__RB_YSEL__SHIFT 0x7
6261#define PA_SC_RASTER_CONFIG__PKR_MAP_MASK 0x300
6262#define PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT 0x8
6263#define PA_SC_RASTER_CONFIG__PKR_XSEL_MASK 0xc00
6264#define PA_SC_RASTER_CONFIG__PKR_XSEL__SHIFT 0xa
6265#define PA_SC_RASTER_CONFIG__PKR_YSEL_MASK 0x3000
6266#define PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT 0xc
6267#define PA_SC_RASTER_CONFIG__PKR_XSEL2_MASK 0xc000
6268#define PA_SC_RASTER_CONFIG__PKR_XSEL2__SHIFT 0xe
6269#define PA_SC_RASTER_CONFIG__SC_MAP_MASK 0x30000
6270#define PA_SC_RASTER_CONFIG__SC_MAP__SHIFT 0x10
6271#define PA_SC_RASTER_CONFIG__SC_XSEL_MASK 0xc0000
6272#define PA_SC_RASTER_CONFIG__SC_XSEL__SHIFT 0x12
6273#define PA_SC_RASTER_CONFIG__SC_YSEL_MASK 0x300000
6274#define PA_SC_RASTER_CONFIG__SC_YSEL__SHIFT 0x14
6275#define PA_SC_RASTER_CONFIG__SE_MAP_MASK 0x3000000
6276#define PA_SC_RASTER_CONFIG__SE_MAP__SHIFT 0x18
6277#define PA_SC_RASTER_CONFIG__SE_XSEL_MASK 0xc000000
6278#define PA_SC_RASTER_CONFIG__SE_XSEL__SHIFT 0x1a
6279#define PA_SC_RASTER_CONFIG__SE_YSEL_MASK 0x30000000
6280#define PA_SC_RASTER_CONFIG__SE_YSEL__SHIFT 0x1c
6281#define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP_MASK 0x3
6282#define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP__SHIFT 0x0
6283#define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL_MASK 0xc
6284#define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL__SHIFT 0x2
6285#define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL_MASK 0x30
6286#define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL__SHIFT 0x4
6287#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE_MASK 0x3
6288#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE__SHIFT 0x0
6289#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE_MASK 0xc
6290#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE__SHIFT 0x2
6291#define PA_SC_GENERIC_SCISSOR_TL__TL_X_MASK 0x7fff
6292#define PA_SC_GENERIC_SCISSOR_TL__TL_X__SHIFT 0x0
6293#define PA_SC_GENERIC_SCISSOR_TL__TL_Y_MASK 0x7fff0000
6294#define PA_SC_GENERIC_SCISSOR_TL__TL_Y__SHIFT 0x10
6295#define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
6296#define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
6297#define PA_SC_GENERIC_SCISSOR_BR__BR_X_MASK 0x7fff
6298#define PA_SC_GENERIC_SCISSOR_BR__BR_X__SHIFT 0x0
6299#define PA_SC_GENERIC_SCISSOR_BR__BR_Y_MASK 0x7fff0000
6300#define PA_SC_GENERIC_SCISSOR_BR__BR_Y__SHIFT 0x10
6301#define PA_SC_SCREEN_SCISSOR_TL__TL_X_MASK 0xffff
6302#define PA_SC_SCREEN_SCISSOR_TL__TL_X__SHIFT 0x0
6303#define PA_SC_SCREEN_SCISSOR_TL__TL_Y_MASK 0xffff0000
6304#define PA_SC_SCREEN_SCISSOR_TL__TL_Y__SHIFT 0x10
6305#define PA_SC_SCREEN_SCISSOR_BR__BR_X_MASK 0xffff
6306#define PA_SC_SCREEN_SCISSOR_BR__BR_X__SHIFT 0x0
6307#define PA_SC_SCREEN_SCISSOR_BR__BR_Y_MASK 0xffff0000
6308#define PA_SC_SCREEN_SCISSOR_BR__BR_Y__SHIFT 0x10
6309#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET_MASK 0xffff
6310#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET__SHIFT 0x0
6311#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET_MASK 0xffff0000
6312#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET__SHIFT 0x10
6313#define PA_SC_WINDOW_SCISSOR_TL__TL_X_MASK 0x7fff
6314#define PA_SC_WINDOW_SCISSOR_TL__TL_X__SHIFT 0x0
6315#define PA_SC_WINDOW_SCISSOR_TL__TL_Y_MASK 0x7fff0000
6316#define PA_SC_WINDOW_SCISSOR_TL__TL_Y__SHIFT 0x10
6317#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
6318#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
6319#define PA_SC_WINDOW_SCISSOR_BR__BR_X_MASK 0x7fff
6320#define PA_SC_WINDOW_SCISSOR_BR__BR_X__SHIFT 0x0
6321#define PA_SC_WINDOW_SCISSOR_BR__BR_Y_MASK 0x7fff0000
6322#define PA_SC_WINDOW_SCISSOR_BR__BR_Y__SHIFT 0x10
6323#define PA_SC_VPORT_SCISSOR_0_TL__TL_X_MASK 0x7fff
6324#define PA_SC_VPORT_SCISSOR_0_TL__TL_X__SHIFT 0x0
6325#define PA_SC_VPORT_SCISSOR_0_TL__TL_Y_MASK 0x7fff0000
6326#define PA_SC_VPORT_SCISSOR_0_TL__TL_Y__SHIFT 0x10
6327#define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
6328#define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
6329#define PA_SC_VPORT_SCISSOR_1_TL__TL_X_MASK 0x7fff
6330#define PA_SC_VPORT_SCISSOR_1_TL__TL_X__SHIFT 0x0
6331#define PA_SC_VPORT_SCISSOR_1_TL__TL_Y_MASK 0x7fff0000
6332#define PA_SC_VPORT_SCISSOR_1_TL__TL_Y__SHIFT 0x10
6333#define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
6334#define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
6335#define PA_SC_VPORT_SCISSOR_2_TL__TL_X_MASK 0x7fff
6336#define PA_SC_VPORT_SCISSOR_2_TL__TL_X__SHIFT 0x0
6337#define PA_SC_VPORT_SCISSOR_2_TL__TL_Y_MASK 0x7fff0000
6338#define PA_SC_VPORT_SCISSOR_2_TL__TL_Y__SHIFT 0x10
6339#define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
6340#define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
6341#define PA_SC_VPORT_SCISSOR_3_TL__TL_X_MASK 0x7fff
6342#define PA_SC_VPORT_SCISSOR_3_TL__TL_X__SHIFT 0x0
6343#define PA_SC_VPORT_SCISSOR_3_TL__TL_Y_MASK 0x7fff0000
6344#define PA_SC_VPORT_SCISSOR_3_TL__TL_Y__SHIFT 0x10
6345#define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
6346#define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
6347#define PA_SC_VPORT_SCISSOR_4_TL__TL_X_MASK 0x7fff
6348#define PA_SC_VPORT_SCISSOR_4_TL__TL_X__SHIFT 0x0
6349#define PA_SC_VPORT_SCISSOR_4_TL__TL_Y_MASK 0x7fff0000
6350#define PA_SC_VPORT_SCISSOR_4_TL__TL_Y__SHIFT 0x10
6351#define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
6352#define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
6353#define PA_SC_VPORT_SCISSOR_5_TL__TL_X_MASK 0x7fff
6354#define PA_SC_VPORT_SCISSOR_5_TL__TL_X__SHIFT 0x0
6355#define PA_SC_VPORT_SCISSOR_5_TL__TL_Y_MASK 0x7fff0000
6356#define PA_SC_VPORT_SCISSOR_5_TL__TL_Y__SHIFT 0x10
6357#define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
6358#define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
6359#define PA_SC_VPORT_SCISSOR_6_TL__TL_X_MASK 0x7fff
6360#define PA_SC_VPORT_SCISSOR_6_TL__TL_X__SHIFT 0x0
6361#define PA_SC_VPORT_SCISSOR_6_TL__TL_Y_MASK 0x7fff0000
6362#define PA_SC_VPORT_SCISSOR_6_TL__TL_Y__SHIFT 0x10
6363#define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
6364#define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
6365#define PA_SC_VPORT_SCISSOR_7_TL__TL_X_MASK 0x7fff
6366#define PA_SC_VPORT_SCISSOR_7_TL__TL_X__SHIFT 0x0
6367#define PA_SC_VPORT_SCISSOR_7_TL__TL_Y_MASK 0x7fff0000
6368#define PA_SC_VPORT_SCISSOR_7_TL__TL_Y__SHIFT 0x10
6369#define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
6370#define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
6371#define PA_SC_VPORT_SCISSOR_8_TL__TL_X_MASK 0x7fff
6372#define PA_SC_VPORT_SCISSOR_8_TL__TL_X__SHIFT 0x0
6373#define PA_SC_VPORT_SCISSOR_8_TL__TL_Y_MASK 0x7fff0000
6374#define PA_SC_VPORT_SCISSOR_8_TL__TL_Y__SHIFT 0x10
6375#define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
6376#define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
6377#define PA_SC_VPORT_SCISSOR_9_TL__TL_X_MASK 0x7fff
6378#define PA_SC_VPORT_SCISSOR_9_TL__TL_X__SHIFT 0x0
6379#define PA_SC_VPORT_SCISSOR_9_TL__TL_Y_MASK 0x7fff0000
6380#define PA_SC_VPORT_SCISSOR_9_TL__TL_Y__SHIFT 0x10
6381#define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
6382#define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
6383#define PA_SC_VPORT_SCISSOR_10_TL__TL_X_MASK 0x7fff
6384#define PA_SC_VPORT_SCISSOR_10_TL__TL_X__SHIFT 0x0
6385#define PA_SC_VPORT_SCISSOR_10_TL__TL_Y_MASK 0x7fff0000
6386#define PA_SC_VPORT_SCISSOR_10_TL__TL_Y__SHIFT 0x10
6387#define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
6388#define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
6389#define PA_SC_VPORT_SCISSOR_11_TL__TL_X_MASK 0x7fff
6390#define PA_SC_VPORT_SCISSOR_11_TL__TL_X__SHIFT 0x0
6391#define PA_SC_VPORT_SCISSOR_11_TL__TL_Y_MASK 0x7fff0000
6392#define PA_SC_VPORT_SCISSOR_11_TL__TL_Y__SHIFT 0x10
6393#define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
6394#define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
6395#define PA_SC_VPORT_SCISSOR_12_TL__TL_X_MASK 0x7fff
6396#define PA_SC_VPORT_SCISSOR_12_TL__TL_X__SHIFT 0x0
6397#define PA_SC_VPORT_SCISSOR_12_TL__TL_Y_MASK 0x7fff0000
6398#define PA_SC_VPORT_SCISSOR_12_TL__TL_Y__SHIFT 0x10
6399#define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
6400#define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
6401#define PA_SC_VPORT_SCISSOR_13_TL__TL_X_MASK 0x7fff
6402#define PA_SC_VPORT_SCISSOR_13_TL__TL_X__SHIFT 0x0
6403#define PA_SC_VPORT_SCISSOR_13_TL__TL_Y_MASK 0x7fff0000
6404#define PA_SC_VPORT_SCISSOR_13_TL__TL_Y__SHIFT 0x10
6405#define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
6406#define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
6407#define PA_SC_VPORT_SCISSOR_14_TL__TL_X_MASK 0x7fff
6408#define PA_SC_VPORT_SCISSOR_14_TL__TL_X__SHIFT 0x0
6409#define PA_SC_VPORT_SCISSOR_14_TL__TL_Y_MASK 0x7fff0000
6410#define PA_SC_VPORT_SCISSOR_14_TL__TL_Y__SHIFT 0x10
6411#define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
6412#define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
6413#define PA_SC_VPORT_SCISSOR_15_TL__TL_X_MASK 0x7fff
6414#define PA_SC_VPORT_SCISSOR_15_TL__TL_X__SHIFT 0x0
6415#define PA_SC_VPORT_SCISSOR_15_TL__TL_Y_MASK 0x7fff0000
6416#define PA_SC_VPORT_SCISSOR_15_TL__TL_Y__SHIFT 0x10
6417#define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
6418#define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
6419#define PA_SC_VPORT_SCISSOR_0_BR__BR_X_MASK 0x7fff
6420#define PA_SC_VPORT_SCISSOR_0_BR__BR_X__SHIFT 0x0
6421#define PA_SC_VPORT_SCISSOR_0_BR__BR_Y_MASK 0x7fff0000
6422#define PA_SC_VPORT_SCISSOR_0_BR__BR_Y__SHIFT 0x10
6423#define PA_SC_VPORT_SCISSOR_1_BR__BR_X_MASK 0x7fff
6424#define PA_SC_VPORT_SCISSOR_1_BR__BR_X__SHIFT 0x0
6425#define PA_SC_VPORT_SCISSOR_1_BR__BR_Y_MASK 0x7fff0000
6426#define PA_SC_VPORT_SCISSOR_1_BR__BR_Y__SHIFT 0x10
6427#define PA_SC_VPORT_SCISSOR_2_BR__BR_X_MASK 0x7fff
6428#define PA_SC_VPORT_SCISSOR_2_BR__BR_X__SHIFT 0x0
6429#define PA_SC_VPORT_SCISSOR_2_BR__BR_Y_MASK 0x7fff0000
6430#define PA_SC_VPORT_SCISSOR_2_BR__BR_Y__SHIFT 0x10
6431#define PA_SC_VPORT_SCISSOR_3_BR__BR_X_MASK 0x7fff
6432#define PA_SC_VPORT_SCISSOR_3_BR__BR_X__SHIFT 0x0
6433#define PA_SC_VPORT_SCISSOR_3_BR__BR_Y_MASK 0x7fff0000
6434#define PA_SC_VPORT_SCISSOR_3_BR__BR_Y__SHIFT 0x10
6435#define PA_SC_VPORT_SCISSOR_4_BR__BR_X_MASK 0x7fff
6436#define PA_SC_VPORT_SCISSOR_4_BR__BR_X__SHIFT 0x0
6437#define PA_SC_VPORT_SCISSOR_4_BR__BR_Y_MASK 0x7fff0000
6438#define PA_SC_VPORT_SCISSOR_4_BR__BR_Y__SHIFT 0x10
6439#define PA_SC_VPORT_SCISSOR_5_BR__BR_X_MASK 0x7fff
6440#define PA_SC_VPORT_SCISSOR_5_BR__BR_X__SHIFT 0x0
6441#define PA_SC_VPORT_SCISSOR_5_BR__BR_Y_MASK 0x7fff0000
6442#define PA_SC_VPORT_SCISSOR_5_BR__BR_Y__SHIFT 0x10
6443#define PA_SC_VPORT_SCISSOR_6_BR__BR_X_MASK 0x7fff
6444#define PA_SC_VPORT_SCISSOR_6_BR__BR_X__SHIFT 0x0
6445#define PA_SC_VPORT_SCISSOR_6_BR__BR_Y_MASK 0x7fff0000
6446#define PA_SC_VPORT_SCISSOR_6_BR__BR_Y__SHIFT 0x10
6447#define PA_SC_VPORT_SCISSOR_7_BR__BR_X_MASK 0x7fff
6448#define PA_SC_VPORT_SCISSOR_7_BR__BR_X__SHIFT 0x0
6449#define PA_SC_VPORT_SCISSOR_7_BR__BR_Y_MASK 0x7fff0000
6450#define PA_SC_VPORT_SCISSOR_7_BR__BR_Y__SHIFT 0x10
6451#define PA_SC_VPORT_SCISSOR_8_BR__BR_X_MASK 0x7fff
6452#define PA_SC_VPORT_SCISSOR_8_BR__BR_X__SHIFT 0x0
6453#define PA_SC_VPORT_SCISSOR_8_BR__BR_Y_MASK 0x7fff0000
6454#define PA_SC_VPORT_SCISSOR_8_BR__BR_Y__SHIFT 0x10
6455#define PA_SC_VPORT_SCISSOR_9_BR__BR_X_MASK 0x7fff
6456#define PA_SC_VPORT_SCISSOR_9_BR__BR_X__SHIFT 0x0
6457#define PA_SC_VPORT_SCISSOR_9_BR__BR_Y_MASK 0x7fff0000
6458#define PA_SC_VPORT_SCISSOR_9_BR__BR_Y__SHIFT 0x10
6459#define PA_SC_VPORT_SCISSOR_10_BR__BR_X_MASK 0x7fff
6460#define PA_SC_VPORT_SCISSOR_10_BR__BR_X__SHIFT 0x0
6461#define PA_SC_VPORT_SCISSOR_10_BR__BR_Y_MASK 0x7fff0000
6462#define PA_SC_VPORT_SCISSOR_10_BR__BR_Y__SHIFT 0x10
6463#define PA_SC_VPORT_SCISSOR_11_BR__BR_X_MASK 0x7fff
6464#define PA_SC_VPORT_SCISSOR_11_BR__BR_X__SHIFT 0x0
6465#define PA_SC_VPORT_SCISSOR_11_BR__BR_Y_MASK 0x7fff0000
6466#define PA_SC_VPORT_SCISSOR_11_BR__BR_Y__SHIFT 0x10
6467#define PA_SC_VPORT_SCISSOR_12_BR__BR_X_MASK 0x7fff
6468#define PA_SC_VPORT_SCISSOR_12_BR__BR_X__SHIFT 0x0
6469#define PA_SC_VPORT_SCISSOR_12_BR__BR_Y_MASK 0x7fff0000
6470#define PA_SC_VPORT_SCISSOR_12_BR__BR_Y__SHIFT 0x10
6471#define PA_SC_VPORT_SCISSOR_13_BR__BR_X_MASK 0x7fff
6472#define PA_SC_VPORT_SCISSOR_13_BR__BR_X__SHIFT 0x0
6473#define PA_SC_VPORT_SCISSOR_13_BR__BR_Y_MASK 0x7fff0000
6474#define PA_SC_VPORT_SCISSOR_13_BR__BR_Y__SHIFT 0x10
6475#define PA_SC_VPORT_SCISSOR_14_BR__BR_X_MASK 0x7fff
6476#define PA_SC_VPORT_SCISSOR_14_BR__BR_X__SHIFT 0x0
6477#define PA_SC_VPORT_SCISSOR_14_BR__BR_Y_MASK 0x7fff0000
6478#define PA_SC_VPORT_SCISSOR_14_BR__BR_Y__SHIFT 0x10
6479#define PA_SC_VPORT_SCISSOR_15_BR__BR_X_MASK 0x7fff
6480#define PA_SC_VPORT_SCISSOR_15_BR__BR_X__SHIFT 0x0
6481#define PA_SC_VPORT_SCISSOR_15_BR__BR_Y_MASK 0x7fff0000
6482#define PA_SC_VPORT_SCISSOR_15_BR__BR_Y__SHIFT 0x10
6483#define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN_MASK 0xffffffff
6484#define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN__SHIFT 0x0
6485#define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN_MASK 0xffffffff
6486#define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN__SHIFT 0x0
6487#define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN_MASK 0xffffffff
6488#define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN__SHIFT 0x0
6489#define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN_MASK 0xffffffff
6490#define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN__SHIFT 0x0
6491#define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN_MASK 0xffffffff
6492#define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN__SHIFT 0x0
6493#define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN_MASK 0xffffffff
6494#define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN__SHIFT 0x0
6495#define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN_MASK 0xffffffff
6496#define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN__SHIFT 0x0
6497#define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN_MASK 0xffffffff
6498#define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN__SHIFT 0x0
6499#define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN_MASK 0xffffffff
6500#define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN__SHIFT 0x0
6501#define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN_MASK 0xffffffff
6502#define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN__SHIFT 0x0
6503#define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN_MASK 0xffffffff
6504#define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN__SHIFT 0x0
6505#define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN_MASK 0xffffffff
6506#define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN__SHIFT 0x0
6507#define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN_MASK 0xffffffff
6508#define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN__SHIFT 0x0
6509#define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN_MASK 0xffffffff
6510#define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN__SHIFT 0x0
6511#define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN_MASK 0xffffffff
6512#define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN__SHIFT 0x0
6513#define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN_MASK 0xffffffff
6514#define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN__SHIFT 0x0
6515#define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX_MASK 0xffffffff
6516#define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX__SHIFT 0x0
6517#define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX_MASK 0xffffffff
6518#define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX__SHIFT 0x0
6519#define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX_MASK 0xffffffff
6520#define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX__SHIFT 0x0
6521#define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX_MASK 0xffffffff
6522#define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX__SHIFT 0x0
6523#define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX_MASK 0xffffffff
6524#define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX__SHIFT 0x0
6525#define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX_MASK 0xffffffff
6526#define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX__SHIFT 0x0
6527#define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX_MASK 0xffffffff
6528#define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX__SHIFT 0x0
6529#define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX_MASK 0xffffffff
6530#define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX__SHIFT 0x0
6531#define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX_MASK 0xffffffff
6532#define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX__SHIFT 0x0
6533#define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX_MASK 0xffffffff
6534#define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX__SHIFT 0x0
6535#define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX_MASK 0xffffffff
6536#define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX__SHIFT 0x0
6537#define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX_MASK 0xffffffff
6538#define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX__SHIFT 0x0
6539#define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX_MASK 0xffffffff
6540#define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX__SHIFT 0x0
6541#define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX_MASK 0xffffffff
6542#define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX__SHIFT 0x0
6543#define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX_MASK 0xffffffff
6544#define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX__SHIFT 0x0
6545#define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX_MASK 0xffffffff
6546#define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX__SHIFT 0x0
6547#define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK 0x1
6548#define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER__SHIFT 0x0
6549#define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX_MASK 0x2
6550#define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX__SHIFT 0x1
6551#define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX_MASK 0x4
6552#define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX__SHIFT 0x2
6553#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS_MASK 0x8
6554#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS__SHIFT 0x3
6555#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID_MASK 0x10
6556#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID__SHIFT 0x4
6557#define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX_MASK 0x20
6558#define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX__SHIFT 0x5
6559#define PA_SC_ENHANCE__DISABLE_PW_BUBBLE_COLLAPSE_MASK 0xc0
6560#define PA_SC_ENHANCE__DISABLE_PW_BUBBLE_COLLAPSE__SHIFT 0x6
6561#define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER_MASK 0x100
6562#define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER__SHIFT 0x8
6563#define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION_MASK 0x200
6564#define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION__SHIFT 0x9
6565#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM_MASK 0x400
6566#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM__SHIFT 0xa
6567#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE_MASK 0x800
6568#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE__SHIFT 0xb
6569#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE_MASK 0x1000
6570#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE__SHIFT 0xc
6571#define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE_MASK 0x2000
6572#define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE__SHIFT 0xd
6573#define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS_MASK 0x4000
6574#define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS__SHIFT 0xe
6575#define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE_MASK 0x8000
6576#define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE__SHIFT 0xf
6577#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE_MASK 0x10000
6578#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE__SHIFT 0x10
6579#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE_MASK 0x20000
6580#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE__SHIFT 0x11
6581#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST_MASK 0x40000
6582#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST__SHIFT 0x12
6583#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING_MASK 0x80000
6584#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING__SHIFT 0x13
6585#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY_MASK 0x100000
6586#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY__SHIFT 0x14
6587#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING_MASK 0x200000
6588#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING__SHIFT 0x15
6589#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING_MASK 0x400000
6590#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING__SHIFT 0x16
6591#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS_MASK 0x800000
6592#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS__SHIFT 0x17
6593#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID_MASK 0x1000000
6594#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID__SHIFT 0x18
6595#define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO_MASK 0x2000000
6596#define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO__SHIFT 0x19
6597#define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT_MASK 0x4000000
6598#define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT__SHIFT 0x1a
6599#define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING_MASK 0x8000000
6600#define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING__SHIFT 0x1b
6601#define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET_MASK 0x10000000
6602#define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET__SHIFT 0x1c
6603#define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET_MASK 0x20000000
6604#define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET__SHIFT 0x1d
6605#define PA_SC_ENHANCE__ECO_SPARE1_MASK 0x40000000
6606#define PA_SC_ENHANCE__ECO_SPARE1__SHIFT 0x1e
6607#define PA_SC_ENHANCE__ECO_SPARE0_MASK 0x80000000
6608#define PA_SC_ENHANCE__ECO_SPARE0__SHIFT 0x1f
6609#define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE_MASK 0x3f
6610#define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT 0x0
6611#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE_MASK 0x7fc0
6612#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT 0x6
6613#define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE_MASK 0x1f8000
6614#define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT 0xf
6615#define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE_MASK 0xff800000
6616#define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT 0x17
6617#define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE_MASK 0x3f
6618#define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE__SHIFT 0x0
6619#define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE_MASK 0xfc0
6620#define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE__SHIFT 0x6
6621#define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE_MASK 0x3f000
6622#define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE__SHIFT 0xc
6623#define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE_MASK 0xfc0000
6624#define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE__SHIFT 0x12
6625#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT_MASK 0xffff
6626#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT 0x0
6627#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT_MASK 0xffff0000
6628#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT 0x10
6629#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR_MASK 0xf
6630#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR__SHIFT 0x0
6631#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT_MASK 0xff00
6632#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT__SHIFT 0x8
6633#define PA_SC_SCREEN_EXTENT_MIN_0__X_MASK 0xffff
6634#define PA_SC_SCREEN_EXTENT_MIN_0__X__SHIFT 0x0
6635#define PA_SC_SCREEN_EXTENT_MIN_0__Y_MASK 0xffff0000
6636#define PA_SC_SCREEN_EXTENT_MIN_0__Y__SHIFT 0x10
6637#define PA_SC_SCREEN_EXTENT_MAX_0__X_MASK 0xffff
6638#define PA_SC_SCREEN_EXTENT_MAX_0__X__SHIFT 0x0
6639#define PA_SC_SCREEN_EXTENT_MAX_0__Y_MASK 0xffff0000
6640#define PA_SC_SCREEN_EXTENT_MAX_0__Y__SHIFT 0x10
6641#define PA_SC_SCREEN_EXTENT_MIN_1__X_MASK 0xffff
6642#define PA_SC_SCREEN_EXTENT_MIN_1__X__SHIFT 0x0
6643#define PA_SC_SCREEN_EXTENT_MIN_1__Y_MASK 0xffff0000
6644#define PA_SC_SCREEN_EXTENT_MIN_1__Y__SHIFT 0x10
6645#define PA_SC_SCREEN_EXTENT_MAX_1__X_MASK 0xffff
6646#define PA_SC_SCREEN_EXTENT_MAX_1__X__SHIFT 0x0
6647#define PA_SC_SCREEN_EXTENT_MAX_1__Y_MASK 0xffff0000
6648#define PA_SC_SCREEN_EXTENT_MAX_1__Y__SHIFT 0x10
6649#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff
6650#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
6651#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00
6652#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
6653#define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
6654#define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
6655#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff
6656#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
6657#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00
6658#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
6659#define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff
6660#define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
6661#define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff
6662#define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
6663#define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff
6664#define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
6665#define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x3ff
6666#define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0
6667#define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x3ff
6668#define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0
6669#define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0x3ff
6670#define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x0
6671#define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0x3ff
6672#define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x0
6673#define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
6674#define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
6675#define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
6676#define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
6677#define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
6678#define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
6679#define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
6680#define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
6681#define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
6682#define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
6683#define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
6684#define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
6685#define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
6686#define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
6687#define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
6688#define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
6689#define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xffffffff
6690#define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0
6691#define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xffffffff
6692#define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0
6693#define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xffffffff
6694#define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0
6695#define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xffffffff
6696#define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0
6697#define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xffffffff
6698#define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x0
6699#define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xffffffff
6700#define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x0
6701#define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xffffffff
6702#define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x0
6703#define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xffffffff
6704#define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x0
6705#define PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x1
6706#define PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0
6707#define PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x2
6708#define PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1
6709#define PA_SC_P3D_TRAP_SCREEN_H__X_COORD_MASK 0x3fff
6710#define PA_SC_P3D_TRAP_SCREEN_H__X_COORD__SHIFT 0x0
6711#define PA_SC_P3D_TRAP_SCREEN_V__Y_COORD_MASK 0x3fff
6712#define PA_SC_P3D_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0
6713#define PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0xffff
6714#define PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0
6715#define PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT_MASK 0xffff
6716#define PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0
6717#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x1
6718#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0
6719#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x2
6720#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1
6721#define PA_SC_HP3D_TRAP_SCREEN_H__X_COORD_MASK 0x3fff
6722#define PA_SC_HP3D_TRAP_SCREEN_H__X_COORD__SHIFT 0x0
6723#define PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD_MASK 0x3fff
6724#define PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0
6725#define PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0xffff
6726#define PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0
6727#define PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT_MASK 0xffff
6728#define PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0
6729#define PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x1
6730#define PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0
6731#define PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x2
6732#define PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1
6733#define PA_SC_TRAP_SCREEN_H__X_COORD_MASK 0x3fff
6734#define PA_SC_TRAP_SCREEN_H__X_COORD__SHIFT 0x0
6735#define PA_SC_TRAP_SCREEN_V__Y_COORD_MASK 0x3fff
6736#define PA_SC_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0
6737#define PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0xffff
6738#define PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0
6739#define PA_SC_TRAP_SCREEN_COUNT__COUNT_MASK 0xffff
6740#define PA_SC_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0
6741#define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x1
6742#define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0
6743#define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x1
6744#define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0
6745#define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x1
6746#define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0
6747#define PA_CL_CNTL_STATUS__CL_BUSY_MASK 0x80000000
6748#define PA_CL_CNTL_STATUS__CL_BUSY__SHIFT 0x1f
6749#define PA_SU_CNTL_STATUS__SU_BUSY_MASK 0x80000000
6750#define PA_SU_CNTL_STATUS__SU_BUSY__SHIFT 0x1f
6751#define PA_SC_FIFO_DEPTH_CNTL__DEPTH_MASK 0x3ff
6752#define PA_SC_FIFO_DEPTH_CNTL__DEPTH__SHIFT 0x0
6753#define CGTT_PA_CLK_CTRL__ON_DELAY_MASK 0xf
6754#define CGTT_PA_CLK_CTRL__ON_DELAY__SHIFT 0x0
6755#define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
6756#define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
6757#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
6758#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
6759#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
6760#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
6761#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
6762#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
6763#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
6764#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
6765#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
6766#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
6767#define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE_MASK 0x20000000
6768#define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE__SHIFT 0x1d
6769#define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE_MASK 0x40000000
6770#define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE__SHIFT 0x1e
6771#define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE_MASK 0x80000000
6772#define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE__SHIFT 0x1f
6773#define CGTT_SC_CLK_CTRL__ON_DELAY_MASK 0xf
6774#define CGTT_SC_CLK_CTRL__ON_DELAY__SHIFT 0x0
6775#define CGTT_SC_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
6776#define CGTT_SC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
6777#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
6778#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
6779#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
6780#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
6781#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
6782#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
6783#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
6784#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
6785#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
6786#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
6787#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
6788#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
6789#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
6790#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
6791#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
6792#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
6793#define PA_SU_DEBUG_CNTL__SU_DEBUG_INDX_MASK 0x1f
6794#define PA_SU_DEBUG_CNTL__SU_DEBUG_INDX__SHIFT 0x0
6795#define PA_SU_DEBUG_DATA__DATA_MASK 0xffffffff
6796#define PA_SU_DEBUG_DATA__DATA__SHIFT 0x0
6797#define PA_SC_DEBUG_CNTL__SC_DEBUG_INDX_MASK 0x3f
6798#define PA_SC_DEBUG_CNTL__SC_DEBUG_INDX__SHIFT 0x0
6799#define PA_SC_DEBUG_DATA__DATA_MASK 0xffffffff
6800#define PA_SC_DEBUG_DATA__DATA__SHIFT 0x0
6801#define CLIPPER_DEBUG_REG00__ALWAYS_ZERO_MASK 0xff
6802#define CLIPPER_DEBUG_REG00__ALWAYS_ZERO__SHIFT 0x0
6803#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write_MASK 0x100
6804#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write__SHIFT 0x8
6805#define CLIPPER_DEBUG_REG00__su_clip_baryc_free_MASK 0x600
6806#define CLIPPER_DEBUG_REG00__su_clip_baryc_free__SHIFT 0x9
6807#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write_MASK 0x800
6808#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write__SHIFT 0xb
6809#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full_MASK 0x1000
6810#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full__SHIFT 0xc
6811#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty_MASK 0x2000
6812#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty__SHIFT 0xd
6813#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full_MASK 0x4000
6814#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full__SHIFT 0xe
6815#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty_MASK 0x8000
6816#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty__SHIFT 0xf
6817#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full_MASK 0x10000
6818#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full__SHIFT 0x10
6819#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty_MASK 0x20000
6820#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty__SHIFT 0x11
6821#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full_MASK 0x40000
6822#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full__SHIFT 0x12
6823#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty_MASK 0x80000
6824#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty__SHIFT 0x13
6825#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full_MASK 0x100000
6826#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full__SHIFT 0x14
6827#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty_MASK 0x200000
6828#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty__SHIFT 0x15
6829#define CLIPPER_DEBUG_REG00__clipcode_fifo_full_MASK 0x400000
6830#define CLIPPER_DEBUG_REG00__clipcode_fifo_full__SHIFT 0x16
6831#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty_MASK 0x800000
6832#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty__SHIFT 0x17
6833#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full_MASK 0x1000000
6834#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full__SHIFT 0x18
6835#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty_MASK 0x2000000
6836#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty__SHIFT 0x19
6837#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full_MASK 0x4000000
6838#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full__SHIFT 0x1a
6839#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty_MASK 0x8000000
6840#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty__SHIFT 0x1b
6841#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full_MASK 0x10000000
6842#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full__SHIFT 0x1c
6843#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_write_MASK 0x20000000
6844#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_write__SHIFT 0x1d
6845#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_write_MASK 0x40000000
6846#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_write__SHIFT 0x1e
6847#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_write_MASK 0x80000000
6848#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_write__SHIFT 0x1f
6849#define CLIPPER_DEBUG_REG01__ALWAYS_ZERO_MASK 0xff
6850#define CLIPPER_DEBUG_REG01__ALWAYS_ZERO__SHIFT 0x0
6851#define CLIPPER_DEBUG_REG01__clip_extra_bc_valid_MASK 0x700
6852#define CLIPPER_DEBUG_REG01__clip_extra_bc_valid__SHIFT 0x8
6853#define CLIPPER_DEBUG_REG01__clip_vert_vte_valid_MASK 0x3800
6854#define CLIPPER_DEBUG_REG01__clip_vert_vte_valid__SHIFT 0xb
6855#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_deallocate_MASK 0x1c000
6856#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_deallocate__SHIFT 0xe
6857#define CLIPPER_DEBUG_REG01__clip_to_outsm_deallocate_slot_MASK 0xe0000
6858#define CLIPPER_DEBUG_REG01__clip_to_outsm_deallocate_slot__SHIFT 0x11
6859#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive_MASK 0x100000
6860#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive__SHIFT 0x14
6861#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_2_MASK 0x200000
6862#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_2__SHIFT 0x15
6863#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_1_MASK 0x400000
6864#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_1__SHIFT 0x16
6865#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_0_MASK 0x800000
6866#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_0__SHIFT 0x17
6867#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_extra_bc_valid_MASK 0x1000000
6868#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_extra_bc_valid__SHIFT 0x18
6869#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vte_naninf_kill_MASK 0x2000000
6870#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vte_naninf_kill__SHIFT 0x19
6871#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vertex_store_indx_MASK 0xc000000
6872#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vertex_store_indx__SHIFT 0x1a
6873#define CLIPPER_DEBUG_REG01__clip_ga_bc_fifo_write_MASK 0x10000000
6874#define CLIPPER_DEBUG_REG01__clip_ga_bc_fifo_write__SHIFT 0x1c
6875#define CLIPPER_DEBUG_REG01__clip_to_ga_fifo_write_MASK 0x20000000
6876#define CLIPPER_DEBUG_REG01__clip_to_ga_fifo_write__SHIFT 0x1d
6877#define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_advanceread_MASK 0x40000000
6878#define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_advanceread__SHIFT 0x1e
6879#define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_empty_MASK 0x80000000
6880#define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_empty__SHIFT 0x1f
6881#define CLIPPER_DEBUG_REG02__clip_extra_bc_valid_MASK 0x7
6882#define CLIPPER_DEBUG_REG02__clip_extra_bc_valid__SHIFT 0x0
6883#define CLIPPER_DEBUG_REG02__clip_vert_vte_valid_MASK 0x38
6884#define CLIPPER_DEBUG_REG02__clip_vert_vte_valid__SHIFT 0x3
6885#define CLIPPER_DEBUG_REG02__clip_to_outsm_clip_seq_indx_MASK 0xc0
6886#define CLIPPER_DEBUG_REG02__clip_to_outsm_clip_seq_indx__SHIFT 0x6
6887#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_2_MASK 0xf00
6888#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_2__SHIFT 0x8
6889#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_1_MASK 0xf000
6890#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_1__SHIFT 0xc
6891#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_0_MASK 0xf0000
6892#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_0__SHIFT 0x10
6893#define CLIPPER_DEBUG_REG02__clip_to_clipga_extra_bc_coords_MASK 0x100000
6894#define CLIPPER_DEBUG_REG02__clip_to_clipga_extra_bc_coords__SHIFT 0x14
6895#define CLIPPER_DEBUG_REG02__clip_to_clipga_vte_naninf_kill_MASK 0x200000
6896#define CLIPPER_DEBUG_REG02__clip_to_clipga_vte_naninf_kill__SHIFT 0x15
6897#define CLIPPER_DEBUG_REG02__clip_to_outsm_end_of_packet_MASK 0x400000
6898#define CLIPPER_DEBUG_REG02__clip_to_outsm_end_of_packet__SHIFT 0x16
6899#define CLIPPER_DEBUG_REG02__clip_to_outsm_first_prim_of_slot_MASK 0x800000
6900#define CLIPPER_DEBUG_REG02__clip_to_outsm_first_prim_of_slot__SHIFT 0x17
6901#define CLIPPER_DEBUG_REG02__clip_to_outsm_clipped_prim_MASK 0x1000000
6902#define CLIPPER_DEBUG_REG02__clip_to_outsm_clipped_prim__SHIFT 0x18
6903#define CLIPPER_DEBUG_REG02__clip_to_outsm_null_primitive_MASK 0x2000000
6904#define CLIPPER_DEBUG_REG02__clip_to_outsm_null_primitive__SHIFT 0x19
6905#define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_full_MASK 0x4000000
6906#define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_full__SHIFT 0x1a
6907#define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_full_MASK 0x8000000
6908#define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_full__SHIFT 0x1b
6909#define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_write_MASK 0x10000000
6910#define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_write__SHIFT 0x1c
6911#define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_write_MASK 0x20000000
6912#define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_write__SHIFT 0x1d
6913#define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_advanceread_MASK 0x40000000
6914#define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_advanceread__SHIFT 0x1e
6915#define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_empty_MASK 0x80000000
6916#define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_empty__SHIFT 0x1f
6917#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_code_or_MASK 0x3fff
6918#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_code_or__SHIFT 0x0
6919#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event_id_MASK 0xfc000
6920#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event_id__SHIFT 0xe
6921#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_state_var_indx_MASK 0x700000
6922#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_state_var_indx__SHIFT 0x14
6923#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive_MASK 0x800000
6924#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive__SHIFT 0x17
6925#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_deallocate_slot_MASK 0x7000000
6926#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_deallocate_slot__SHIFT 0x18
6927#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_first_prim_of_slot_MASK 0x8000000
6928#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_first_prim_of_slot__SHIFT 0x1b
6929#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_end_of_packet_MASK 0x10000000
6930#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_end_of_packet__SHIFT 0x1c
6931#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event_MASK 0x20000000
6932#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event__SHIFT 0x1d
6933#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive_MASK 0x40000000
6934#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive__SHIFT 0x1e
6935#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000
6936#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x1f
6937#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_param_cache_indx_0_MASK 0x7fe
6938#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_param_cache_indx_0__SHIFT 0x1
6939#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_2_MASK 0x1f800
6940#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_2__SHIFT 0xb
6941#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_1_MASK 0x7e0000
6942#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_1__SHIFT 0x11
6943#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000
6944#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_0__SHIFT 0x17
6945#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event_MASK 0x20000000
6946#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event__SHIFT 0x1d
6947#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_null_primitive_MASK 0x40000000
6948#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_null_primitive__SHIFT 0x1e
6949#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000
6950#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x1f
6951#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_code_or_MASK 0x3fff
6952#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_code_or__SHIFT 0x0
6953#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event_id_MASK 0xfc000
6954#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event_id__SHIFT 0xe
6955#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_state_var_indx_MASK 0x700000
6956#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_state_var_indx__SHIFT 0x14
6957#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_primitive_MASK 0x800000
6958#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_primitive__SHIFT 0x17
6959#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_deallocate_slot_MASK 0x7000000
6960#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_deallocate_slot__SHIFT 0x18
6961#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_first_prim_of_slot_MASK 0x8000000
6962#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_first_prim_of_slot__SHIFT 0x1b
6963#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_end_of_packet_MASK 0x10000000
6964#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_end_of_packet__SHIFT 0x1c
6965#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event_MASK 0x20000000
6966#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event__SHIFT 0x1d
6967#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_null_primitive_MASK 0x40000000
6968#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_null_primitive__SHIFT 0x1e
6969#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_prim_valid_MASK 0x80000000
6970#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_prim_valid__SHIFT 0x1f
6971#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_param_cache_indx_0_MASK 0x7fe
6972#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_param_cache_indx_0__SHIFT 0x1
6973#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_2_MASK 0x1f800
6974#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_2__SHIFT 0xb
6975#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_1_MASK 0x7e0000
6976#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_1__SHIFT 0x11
6977#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000
6978#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_0__SHIFT 0x17
6979#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_event_MASK 0x20000000
6980#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_event__SHIFT 0x1d
6981#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_null_primitive_MASK 0x40000000
6982#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_null_primitive__SHIFT 0x1e
6983#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_prim_valid_MASK 0x80000000
6984#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_prim_valid__SHIFT 0x1f
6985#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_code_or_MASK 0x3fff
6986#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_code_or__SHIFT 0x0
6987#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event_id_MASK 0xfc000
6988#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event_id__SHIFT 0xe
6989#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_state_var_indx_MASK 0x700000
6990#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_state_var_indx__SHIFT 0x14
6991#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_primitive_MASK 0x800000
6992#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_primitive__SHIFT 0x17
6993#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_deallocate_slot_MASK 0x7000000
6994#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_deallocate_slot__SHIFT 0x18
6995#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_first_prim_of_slot_MASK 0x8000000
6996#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_first_prim_of_slot__SHIFT 0x1b
6997#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_end_of_packet_MASK 0x10000000
6998#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_end_of_packet__SHIFT 0x1c
6999#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event_MASK 0x20000000
7000#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event__SHIFT 0x1d
7001#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_null_primitive_MASK 0x40000000
7002#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_null_primitive__SHIFT 0x1e
7003#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_prim_valid_MASK 0x80000000
7004#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_prim_valid__SHIFT 0x1f
7005#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_param_cache_indx_0_MASK 0x7fe
7006#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_param_cache_indx_0__SHIFT 0x1
7007#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_2_MASK 0x1f800
7008#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_2__SHIFT 0xb
7009#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_1_MASK 0x7e0000
7010#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_1__SHIFT 0x11
7011#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000
7012#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_0__SHIFT 0x17
7013#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_event_MASK 0x20000000
7014#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_event__SHIFT 0x1d
7015#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_null_primitive_MASK 0x40000000
7016#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_null_primitive__SHIFT 0x1e
7017#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_prim_valid_MASK 0x80000000
7018#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_prim_valid__SHIFT 0x1f
7019#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_code_or_MASK 0x3fff
7020#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_code_or__SHIFT 0x0
7021#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event_id_MASK 0xfc000
7022#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event_id__SHIFT 0xe
7023#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_state_var_indx_MASK 0x700000
7024#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_state_var_indx__SHIFT 0x14
7025#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_primitive_MASK 0x800000
7026#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_primitive__SHIFT 0x17
7027#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_deallocate_slot_MASK 0x7000000
7028#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_deallocate_slot__SHIFT 0x18
7029#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_first_prim_of_slot_MASK 0x8000000
7030#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_first_prim_of_slot__SHIFT 0x1b
7031#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_end_of_packet_MASK 0x10000000
7032#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_end_of_packet__SHIFT 0x1c
7033#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event_MASK 0x20000000
7034#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event__SHIFT 0x1d
7035#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_null_primitive_MASK 0x40000000
7036#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_null_primitive__SHIFT 0x1e
7037#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_prim_valid_MASK 0x80000000
7038#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_prim_valid__SHIFT 0x1f
7039#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_param_cache_indx_0_MASK 0x7fe
7040#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_param_cache_indx_0__SHIFT 0x1
7041#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_2_MASK 0x1f800
7042#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_2__SHIFT 0xb
7043#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_1_MASK 0x7e0000
7044#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_1__SHIFT 0x11
7045#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000
7046#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_0__SHIFT 0x17
7047#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_event_MASK 0x20000000
7048#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_event__SHIFT 0x1d
7049#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_null_primitive_MASK 0x40000000
7050#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_null_primitive__SHIFT 0x1e
7051#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_prim_valid_MASK 0x80000000
7052#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_prim_valid__SHIFT 0x1f
7053#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_event_MASK 0x1
7054#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_event__SHIFT 0x0
7055#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_event_MASK 0x2
7056#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_event__SHIFT 0x1
7057#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_event_MASK 0x4
7058#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_event__SHIFT 0x2
7059#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_event_MASK 0x8
7060#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_event__SHIFT 0x3
7061#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_primitive_MASK 0x10
7062#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_primitive__SHIFT 0x4
7063#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_primitive_MASK 0x20
7064#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_primitive__SHIFT 0x5
7065#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_primitive_MASK 0x40
7066#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_primitive__SHIFT 0x6
7067#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_primitive_MASK 0x80
7068#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_primitive__SHIFT 0x7
7069#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_to_outsm_cnt_MASK 0xf00
7070#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x8
7071#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_to_outsm_cnt_MASK 0xf000
7072#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0xc
7073#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_to_outsm_cnt_MASK 0xf0000
7074#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x10
7075#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK 0xf00000
7076#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x14
7077#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_prim_valid_MASK 0x1000000
7078#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_prim_valid__SHIFT 0x18
7079#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_prim_valid_MASK 0x2000000
7080#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_prim_valid__SHIFT 0x19
7081#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_prim_valid_MASK 0x4000000
7082#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_prim_valid__SHIFT 0x1a
7083#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_prim_valid_MASK 0x8000000
7084#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_prim_valid__SHIFT 0x1b
7085#define CLIPPER_DEBUG_REG11__clipsm3_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x10000000
7086#define CLIPPER_DEBUG_REG11__clipsm3_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x1c
7087#define CLIPPER_DEBUG_REG11__clipsm2_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x20000000
7088#define CLIPPER_DEBUG_REG11__clipsm2_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x1d
7089#define CLIPPER_DEBUG_REG11__clipsm1_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x40000000
7090#define CLIPPER_DEBUG_REG11__clipsm1_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x1e
7091#define CLIPPER_DEBUG_REG11__clipsm0_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x80000000
7092#define CLIPPER_DEBUG_REG11__clipsm0_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x1f
7093#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO_MASK 0xff
7094#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO__SHIFT 0x0
7095#define CLIPPER_DEBUG_REG12__clip_priority_available_vte_out_clip_MASK 0x1f00
7096#define CLIPPER_DEBUG_REG12__clip_priority_available_vte_out_clip__SHIFT 0x8
7097#define CLIPPER_DEBUG_REG12__clip_priority_available_clip_verts_MASK 0x3e000
7098#define CLIPPER_DEBUG_REG12__clip_priority_available_clip_verts__SHIFT 0xd
7099#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_out_MASK 0xc0000
7100#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_out__SHIFT 0x12
7101#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_vert_MASK 0x300000
7102#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_vert__SHIFT 0x14
7103#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_load_MASK 0xc00000
7104#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_load__SHIFT 0x16
7105#define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_clip_primitive_MASK 0x1000000
7106#define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_clip_primitive__SHIFT 0x18
7107#define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_prim_valid_MASK 0x2000000
7108#define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_prim_valid__SHIFT 0x19
7109#define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_clip_primitive_MASK 0x4000000
7110#define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_clip_primitive__SHIFT 0x1a
7111#define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_prim_valid_MASK 0x8000000
7112#define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_prim_valid__SHIFT 0x1b
7113#define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_clip_primitive_MASK 0x10000000
7114#define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_clip_primitive__SHIFT 0x1c
7115#define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_prim_valid_MASK 0x20000000
7116#define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_prim_valid__SHIFT 0x1d
7117#define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_clip_primitive_MASK 0x40000000
7118#define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_clip_primitive__SHIFT 0x1e
7119#define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000
7120#define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x1f
7121#define CLIPPER_DEBUG_REG13__clprim_in_back_state_var_indx_MASK 0x7
7122#define CLIPPER_DEBUG_REG13__clprim_in_back_state_var_indx__SHIFT 0x0
7123#define CLIPPER_DEBUG_REG13__point_clip_candidate_MASK 0x8
7124#define CLIPPER_DEBUG_REG13__point_clip_candidate__SHIFT 0x3
7125#define CLIPPER_DEBUG_REG13__prim_nan_kill_MASK 0x10
7126#define CLIPPER_DEBUG_REG13__prim_nan_kill__SHIFT 0x4
7127#define CLIPPER_DEBUG_REG13__clprim_clip_primitive_MASK 0x20
7128#define CLIPPER_DEBUG_REG13__clprim_clip_primitive__SHIFT 0x5
7129#define CLIPPER_DEBUG_REG13__clprim_cull_primitive_MASK 0x40
7130#define CLIPPER_DEBUG_REG13__clprim_cull_primitive__SHIFT 0x6
7131#define CLIPPER_DEBUG_REG13__prim_back_valid_MASK 0x80
7132#define CLIPPER_DEBUG_REG13__prim_back_valid__SHIFT 0x7
7133#define CLIPPER_DEBUG_REG13__vertval_bits_vertex_cc_next_valid_MASK 0xf00
7134#define CLIPPER_DEBUG_REG13__vertval_bits_vertex_cc_next_valid__SHIFT 0x8
7135#define CLIPPER_DEBUG_REG13__clipcc_vertex_store_indx_MASK 0x3000
7136#define CLIPPER_DEBUG_REG13__clipcc_vertex_store_indx__SHIFT 0xc
7137#define CLIPPER_DEBUG_REG13__vte_out_orig_fifo_fifo_empty_MASK 0x4000
7138#define CLIPPER_DEBUG_REG13__vte_out_orig_fifo_fifo_empty__SHIFT 0xe
7139#define CLIPPER_DEBUG_REG13__clipcode_fifo_fifo_empty_MASK 0x8000
7140#define CLIPPER_DEBUG_REG13__clipcode_fifo_fifo_empty__SHIFT 0xf
7141#define CLIPPER_DEBUG_REG13__ccgen_to_clipcc_fifo_empty_MASK 0x10000
7142#define CLIPPER_DEBUG_REG13__ccgen_to_clipcc_fifo_empty__SHIFT 0x10
7143#define CLIPPER_DEBUG_REG13__clip_priority_seq_indx_out_cnt_MASK 0x1e0000
7144#define CLIPPER_DEBUG_REG13__clip_priority_seq_indx_out_cnt__SHIFT 0x11
7145#define CLIPPER_DEBUG_REG13__outsm_clr_rd_orig_vertices_MASK 0x600000
7146#define CLIPPER_DEBUG_REG13__outsm_clr_rd_orig_vertices__SHIFT 0x15
7147#define CLIPPER_DEBUG_REG13__outsm_clr_rd_clipsm_wait_MASK 0x800000
7148#define CLIPPER_DEBUG_REG13__outsm_clr_rd_clipsm_wait__SHIFT 0x17
7149#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_contents_MASK 0x1f000000
7150#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_contents__SHIFT 0x18
7151#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_full_MASK 0x20000000
7152#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_full__SHIFT 0x1d
7153#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_advanceread_MASK 0x40000000
7154#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_advanceread__SHIFT 0x1e
7155#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_write_MASK 0x80000000
7156#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_write__SHIFT 0x1f
7157#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_2_MASK 0x3f
7158#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_2__SHIFT 0x0
7159#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_1_MASK 0xfc0
7160#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_1__SHIFT 0x6
7161#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_0_MASK 0x3f000
7162#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_0__SHIFT 0xc
7163#define CLIPPER_DEBUG_REG14__outputclprimtoclip_null_primitive_MASK 0x40000
7164#define CLIPPER_DEBUG_REG14__outputclprimtoclip_null_primitive__SHIFT 0x12
7165#define CLIPPER_DEBUG_REG14__clprim_in_back_end_of_packet_MASK 0x80000
7166#define CLIPPER_DEBUG_REG14__clprim_in_back_end_of_packet__SHIFT 0x13
7167#define CLIPPER_DEBUG_REG14__clprim_in_back_first_prim_of_slot_MASK 0x100000
7168#define CLIPPER_DEBUG_REG14__clprim_in_back_first_prim_of_slot__SHIFT 0x14
7169#define CLIPPER_DEBUG_REG14__clprim_in_back_deallocate_slot_MASK 0xe00000
7170#define CLIPPER_DEBUG_REG14__clprim_in_back_deallocate_slot__SHIFT 0x15
7171#define CLIPPER_DEBUG_REG14__clprim_in_back_event_id_MASK 0x3f000000
7172#define CLIPPER_DEBUG_REG14__clprim_in_back_event_id__SHIFT 0x18
7173#define CLIPPER_DEBUG_REG14__clprim_in_back_event_MASK 0x40000000
7174#define CLIPPER_DEBUG_REG14__clprim_in_back_event__SHIFT 0x1e
7175#define CLIPPER_DEBUG_REG14__prim_back_valid_MASK 0x80000000
7176#define CLIPPER_DEBUG_REG14__prim_back_valid__SHIFT 0x1f
7177#define CLIPPER_DEBUG_REG15__vertval_bits_vertex_vertex_store_msb_MASK 0xffff
7178#define CLIPPER_DEBUG_REG15__vertval_bits_vertex_vertex_store_msb__SHIFT 0x0
7179#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_2_MASK 0x1f0000
7180#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_2__SHIFT 0x10
7181#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_1_MASK 0x3e00000
7182#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_1__SHIFT 0x15
7183#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_0_MASK 0x7c000000
7184#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_0__SHIFT 0x1a
7185#define CLIPPER_DEBUG_REG15__primic_to_clprim_valid_MASK 0x80000000
7186#define CLIPPER_DEBUG_REG15__primic_to_clprim_valid__SHIFT 0x1f
7187#define CLIPPER_DEBUG_REG16__sm0_prim_end_state_MASK 0x7f
7188#define CLIPPER_DEBUG_REG16__sm0_prim_end_state__SHIFT 0x0
7189#define CLIPPER_DEBUG_REG16__sm0_ps_expand_MASK 0x80
7190#define CLIPPER_DEBUG_REG16__sm0_ps_expand__SHIFT 0x7
7191#define CLIPPER_DEBUG_REG16__sm0_clip_vert_cnt_MASK 0x1f00
7192#define CLIPPER_DEBUG_REG16__sm0_clip_vert_cnt__SHIFT 0x8
7193#define CLIPPER_DEBUG_REG16__sm0_vertex_clip_cnt_MASK 0x3e000
7194#define CLIPPER_DEBUG_REG16__sm0_vertex_clip_cnt__SHIFT 0xd
7195#define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_1_MASK 0x40000
7196#define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_1__SHIFT 0x12
7197#define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_0_MASK 0x80000
7198#define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_0__SHIFT 0x13
7199#define CLIPPER_DEBUG_REG16__sm0_current_state_MASK 0x7f00000
7200#define CLIPPER_DEBUG_REG16__sm0_current_state__SHIFT 0x14
7201#define CLIPPER_DEBUG_REG16__sm0_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x8000000
7202#define CLIPPER_DEBUG_REG16__sm0_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x1b
7203#define CLIPPER_DEBUG_REG16__sm0_clip_to_outsm_fifo_full_MASK 0x10000000
7204#define CLIPPER_DEBUG_REG16__sm0_clip_to_outsm_fifo_full__SHIFT 0x1c
7205#define CLIPPER_DEBUG_REG16__sm0_highest_priority_seq_MASK 0x20000000
7206#define CLIPPER_DEBUG_REG16__sm0_highest_priority_seq__SHIFT 0x1d
7207#define CLIPPER_DEBUG_REG16__sm0_outputcliptoclipga_0_MASK 0x40000000
7208#define CLIPPER_DEBUG_REG16__sm0_outputcliptoclipga_0__SHIFT 0x1e
7209#define CLIPPER_DEBUG_REG16__sm0_clprim_to_clip_prim_valid_MASK 0x80000000
7210#define CLIPPER_DEBUG_REG16__sm0_clprim_to_clip_prim_valid__SHIFT 0x1f
7211#define CLIPPER_DEBUG_REG17__sm1_prim_end_state_MASK 0x7f
7212#define CLIPPER_DEBUG_REG17__sm1_prim_end_state__SHIFT 0x0
7213#define CLIPPER_DEBUG_REG17__sm1_ps_expand_MASK 0x80
7214#define CLIPPER_DEBUG_REG17__sm1_ps_expand__SHIFT 0x7
7215#define CLIPPER_DEBUG_REG17__sm1_clip_vert_cnt_MASK 0x1f00
7216#define CLIPPER_DEBUG_REG17__sm1_clip_vert_cnt__SHIFT 0x8
7217#define CLIPPER_DEBUG_REG17__sm1_vertex_clip_cnt_MASK 0x3e000
7218#define CLIPPER_DEBUG_REG17__sm1_vertex_clip_cnt__SHIFT 0xd
7219#define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_1_MASK 0x40000
7220#define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_1__SHIFT 0x12
7221#define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_0_MASK 0x80000
7222#define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_0__SHIFT 0x13
7223#define CLIPPER_DEBUG_REG17__sm1_current_state_MASK 0x7f00000
7224#define CLIPPER_DEBUG_REG17__sm1_current_state__SHIFT 0x14
7225#define CLIPPER_DEBUG_REG17__sm1_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x8000000
7226#define CLIPPER_DEBUG_REG17__sm1_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x1b
7227#define CLIPPER_DEBUG_REG17__sm1_clip_to_outsm_fifo_full_MASK 0x10000000
7228#define CLIPPER_DEBUG_REG17__sm1_clip_to_outsm_fifo_full__SHIFT 0x1c
7229#define CLIPPER_DEBUG_REG17__sm1_highest_priority_seq_MASK 0x20000000
7230#define CLIPPER_DEBUG_REG17__sm1_highest_priority_seq__SHIFT 0x1d
7231#define CLIPPER_DEBUG_REG17__sm1_outputcliptoclipga_0_MASK 0x40000000
7232#define CLIPPER_DEBUG_REG17__sm1_outputcliptoclipga_0__SHIFT 0x1e
7233#define CLIPPER_DEBUG_REG17__sm1_clprim_to_clip_prim_valid_MASK 0x80000000
7234#define CLIPPER_DEBUG_REG17__sm1_clprim_to_clip_prim_valid__SHIFT 0x1f
7235#define CLIPPER_DEBUG_REG18__sm2_prim_end_state_MASK 0x7f
7236#define CLIPPER_DEBUG_REG18__sm2_prim_end_state__SHIFT 0x0
7237#define CLIPPER_DEBUG_REG18__sm2_ps_expand_MASK 0x80
7238#define CLIPPER_DEBUG_REG18__sm2_ps_expand__SHIFT 0x7
7239#define CLIPPER_DEBUG_REG18__sm2_clip_vert_cnt_MASK 0x1f00
7240#define CLIPPER_DEBUG_REG18__sm2_clip_vert_cnt__SHIFT 0x8
7241#define CLIPPER_DEBUG_REG18__sm2_vertex_clip_cnt_MASK 0x3e000
7242#define CLIPPER_DEBUG_REG18__sm2_vertex_clip_cnt__SHIFT 0xd
7243#define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_1_MASK 0x40000
7244#define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_1__SHIFT 0x12
7245#define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_0_MASK 0x80000
7246#define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_0__SHIFT 0x13
7247#define CLIPPER_DEBUG_REG18__sm2_current_state_MASK 0x7f00000
7248#define CLIPPER_DEBUG_REG18__sm2_current_state__SHIFT 0x14
7249#define CLIPPER_DEBUG_REG18__sm2_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x8000000
7250#define CLIPPER_DEBUG_REG18__sm2_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x1b
7251#define CLIPPER_DEBUG_REG18__sm2_clip_to_outsm_fifo_full_MASK 0x10000000
7252#define CLIPPER_DEBUG_REG18__sm2_clip_to_outsm_fifo_full__SHIFT 0x1c
7253#define CLIPPER_DEBUG_REG18__sm2_highest_priority_seq_MASK 0x20000000
7254#define CLIPPER_DEBUG_REG18__sm2_highest_priority_seq__SHIFT 0x1d
7255#define CLIPPER_DEBUG_REG18__sm2_outputcliptoclipga_0_MASK 0x40000000
7256#define CLIPPER_DEBUG_REG18__sm2_outputcliptoclipga_0__SHIFT 0x1e
7257#define CLIPPER_DEBUG_REG18__sm2_clprim_to_clip_prim_valid_MASK 0x80000000
7258#define CLIPPER_DEBUG_REG18__sm2_clprim_to_clip_prim_valid__SHIFT 0x1f
7259#define CLIPPER_DEBUG_REG19__sm3_prim_end_state_MASK 0x7f
7260#define CLIPPER_DEBUG_REG19__sm3_prim_end_state__SHIFT 0x0
7261#define CLIPPER_DEBUG_REG19__sm3_ps_expand_MASK 0x80
7262#define CLIPPER_DEBUG_REG19__sm3_ps_expand__SHIFT 0x7
7263#define CLIPPER_DEBUG_REG19__sm3_clip_vert_cnt_MASK 0x1f00
7264#define CLIPPER_DEBUG_REG19__sm3_clip_vert_cnt__SHIFT 0x8
7265#define CLIPPER_DEBUG_REG19__sm3_vertex_clip_cnt_MASK 0x3e000
7266#define CLIPPER_DEBUG_REG19__sm3_vertex_clip_cnt__SHIFT 0xd
7267#define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_1_MASK 0x40000
7268#define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_1__SHIFT 0x12
7269#define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_0_MASK 0x80000
7270#define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_0__SHIFT 0x13
7271#define CLIPPER_DEBUG_REG19__sm3_current_state_MASK 0x7f00000
7272#define CLIPPER_DEBUG_REG19__sm3_current_state__SHIFT 0x14
7273#define CLIPPER_DEBUG_REG19__sm3_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x8000000
7274#define CLIPPER_DEBUG_REG19__sm3_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x1b
7275#define CLIPPER_DEBUG_REG19__sm3_clip_to_outsm_fifo_full_MASK 0x10000000
7276#define CLIPPER_DEBUG_REG19__sm3_clip_to_outsm_fifo_full__SHIFT 0x1c
7277#define CLIPPER_DEBUG_REG19__sm3_highest_priority_seq_MASK 0x20000000
7278#define CLIPPER_DEBUG_REG19__sm3_highest_priority_seq__SHIFT 0x1d
7279#define CLIPPER_DEBUG_REG19__sm3_outputcliptoclipga_0_MASK 0x40000000
7280#define CLIPPER_DEBUG_REG19__sm3_outputcliptoclipga_0__SHIFT 0x1e
7281#define CLIPPER_DEBUG_REG19__sm3_clprim_to_clip_prim_valid_MASK 0x80000000
7282#define CLIPPER_DEBUG_REG19__sm3_clprim_to_clip_prim_valid__SHIFT 0x1f
7283#define SXIFCCG_DEBUG_REG0__position_address_MASK 0x3f
7284#define SXIFCCG_DEBUG_REG0__position_address__SHIFT 0x0
7285#define SXIFCCG_DEBUG_REG0__point_address_MASK 0x1c0
7286#define SXIFCCG_DEBUG_REG0__point_address__SHIFT 0x6
7287#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx_MASK 0xe00
7288#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx__SHIFT 0x9
7289#define SXIFCCG_DEBUG_REG0__sx_pending_rd_req_mask_MASK 0xf000
7290#define SXIFCCG_DEBUG_REG0__sx_pending_rd_req_mask__SHIFT 0xc
7291#define SXIFCCG_DEBUG_REG0__sx_pending_rd_pci_MASK 0x3ff0000
7292#define SXIFCCG_DEBUG_REG0__sx_pending_rd_pci__SHIFT 0x10
7293#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel_MASK 0xc000000
7294#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel__SHIFT 0x1a
7295#define SXIFCCG_DEBUG_REG0__sx_pending_rd_sp_id_MASK 0x30000000
7296#define SXIFCCG_DEBUG_REG0__sx_pending_rd_sp_id__SHIFT 0x1c
7297#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc_MASK 0x40000000
7298#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc__SHIFT 0x1e
7299#define SXIFCCG_DEBUG_REG0__sx_pending_rd_advance_MASK 0x80000000
7300#define SXIFCCG_DEBUG_REG0__sx_pending_rd_advance__SHIFT 0x1f
7301#define SXIFCCG_DEBUG_REG1__available_positions_MASK 0x7f
7302#define SXIFCCG_DEBUG_REG1__available_positions__SHIFT 0x0
7303#define SXIFCCG_DEBUG_REG1__sx_receive_indx_MASK 0x380
7304#define SXIFCCG_DEBUG_REG1__sx_receive_indx__SHIFT 0x7
7305#define SXIFCCG_DEBUG_REG1__sx_pending_fifo_contents_MASK 0x7c00
7306#define SXIFCCG_DEBUG_REG1__sx_pending_fifo_contents__SHIFT 0xa
7307#define SXIFCCG_DEBUG_REG1__statevar_bits_vs_out_misc_vec_ena_MASK 0x8000
7308#define SXIFCCG_DEBUG_REG1__statevar_bits_vs_out_misc_vec_ena__SHIFT 0xf
7309#define SXIFCCG_DEBUG_REG1__statevar_bits_disable_sp_MASK 0xf0000
7310#define SXIFCCG_DEBUG_REG1__statevar_bits_disable_sp__SHIFT 0x10
7311#define SXIFCCG_DEBUG_REG1__aux_sel_MASK 0x300000
7312#define SXIFCCG_DEBUG_REG1__aux_sel__SHIFT 0x14
7313#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_1_MASK 0x400000
7314#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_1__SHIFT 0x16
7315#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_0_MASK 0x800000
7316#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_0__SHIFT 0x17
7317#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_1_MASK 0xf000000
7318#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_1__SHIFT 0x18
7319#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_0_MASK 0xf0000000
7320#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_0__SHIFT 0x1c
7321#define SXIFCCG_DEBUG_REG2__param_cache_base_MASK 0x7f
7322#define SXIFCCG_DEBUG_REG2__param_cache_base__SHIFT 0x0
7323#define SXIFCCG_DEBUG_REG2__sx_aux_MASK 0x180
7324#define SXIFCCG_DEBUG_REG2__sx_aux__SHIFT 0x7
7325#define SXIFCCG_DEBUG_REG2__sx_request_indx_MASK 0x7e00
7326#define SXIFCCG_DEBUG_REG2__sx_request_indx__SHIFT 0x9
7327#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded_MASK 0x8000
7328#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded__SHIFT 0xf
7329#define SXIFCCG_DEBUG_REG2__req_active_verts_MASK 0x7f0000
7330#define SXIFCCG_DEBUG_REG2__req_active_verts__SHIFT 0x10
7331#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx_MASK 0x3800000
7332#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx__SHIFT 0x17
7333#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_active_verts_MASK 0xfc000000
7334#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_active_verts__SHIFT 0x1a
7335#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO_MASK 0xff
7336#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO__SHIFT 0x0
7337#define SXIFCCG_DEBUG_REG3__vertex_fifo_entriesavailable_MASK 0xf00
7338#define SXIFCCG_DEBUG_REG3__vertex_fifo_entriesavailable__SHIFT 0x8
7339#define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist1_vec_ena_MASK 0x1000
7340#define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist1_vec_ena__SHIFT 0xc
7341#define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist0_vec_ena_MASK 0x2000
7342#define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist0_vec_ena__SHIFT 0xd
7343#define SXIFCCG_DEBUG_REG3__available_positions_MASK 0x1fc000
7344#define SXIFCCG_DEBUG_REG3__available_positions__SHIFT 0xe
7345#define SXIFCCG_DEBUG_REG3__current_state_MASK 0x600000
7346#define SXIFCCG_DEBUG_REG3__current_state__SHIFT 0x15
7347#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty_MASK 0x800000
7348#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty__SHIFT 0x17
7349#define SXIFCCG_DEBUG_REG3__vertex_fifo_full_MASK 0x1000000
7350#define SXIFCCG_DEBUG_REG3__vertex_fifo_full__SHIFT 0x18
7351#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty_MASK 0x2000000
7352#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty__SHIFT 0x19
7353#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full_MASK 0x4000000
7354#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full__SHIFT 0x1a
7355#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty_MASK 0x8000000
7356#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty__SHIFT 0x1b
7357#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full_MASK 0x10000000
7358#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full__SHIFT 0x1c
7359#define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_fifo_full_MASK 0x20000000
7360#define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_fifo_full__SHIFT 0x1d
7361#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_write_MASK 0x40000000
7362#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_write__SHIFT 0x1e
7363#define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_write_MASK 0x80000000
7364#define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_write__SHIFT 0x1f
7365#define SETUP_DEBUG_REG0__su_baryc_cntl_state_MASK 0x3
7366#define SETUP_DEBUG_REG0__su_baryc_cntl_state__SHIFT 0x0
7367#define SETUP_DEBUG_REG0__su_cntl_state_MASK 0x3c
7368#define SETUP_DEBUG_REG0__su_cntl_state__SHIFT 0x2
7369#define SETUP_DEBUG_REG0__pmode_state_MASK 0x3f00
7370#define SETUP_DEBUG_REG0__pmode_state__SHIFT 0x8
7371#define SETUP_DEBUG_REG0__ge_stallb_MASK 0x4000
7372#define SETUP_DEBUG_REG0__ge_stallb__SHIFT 0xe
7373#define SETUP_DEBUG_REG0__geom_enable_MASK 0x8000
7374#define SETUP_DEBUG_REG0__geom_enable__SHIFT 0xf
7375#define SETUP_DEBUG_REG0__su_clip_baryc_free_MASK 0x30000
7376#define SETUP_DEBUG_REG0__su_clip_baryc_free__SHIFT 0x10
7377#define SETUP_DEBUG_REG0__su_clip_rtr_MASK 0x40000
7378#define SETUP_DEBUG_REG0__su_clip_rtr__SHIFT 0x12
7379#define SETUP_DEBUG_REG0__pfifo_busy_MASK 0x80000
7380#define SETUP_DEBUG_REG0__pfifo_busy__SHIFT 0x13
7381#define SETUP_DEBUG_REG0__su_cntl_busy_MASK 0x100000
7382#define SETUP_DEBUG_REG0__su_cntl_busy__SHIFT 0x14
7383#define SETUP_DEBUG_REG0__geom_busy_MASK 0x200000
7384#define SETUP_DEBUG_REG0__geom_busy__SHIFT 0x15
7385#define SETUP_DEBUG_REG0__event_id_gated_MASK 0xfc00000
7386#define SETUP_DEBUG_REG0__event_id_gated__SHIFT 0x16
7387#define SETUP_DEBUG_REG0__event_gated_MASK 0x10000000
7388#define SETUP_DEBUG_REG0__event_gated__SHIFT 0x1c
7389#define SETUP_DEBUG_REG0__pmode_prim_gated_MASK 0x20000000
7390#define SETUP_DEBUG_REG0__pmode_prim_gated__SHIFT 0x1d
7391#define SETUP_DEBUG_REG0__su_dyn_sclk_vld_MASK 0x40000000
7392#define SETUP_DEBUG_REG0__su_dyn_sclk_vld__SHIFT 0x1e
7393#define SETUP_DEBUG_REG0__cl_dyn_sclk_vld_MASK 0x80000000
7394#define SETUP_DEBUG_REG0__cl_dyn_sclk_vld__SHIFT 0x1f
7395#define SETUP_DEBUG_REG1__y_sort0_gated_23_8_MASK 0xffff
7396#define SETUP_DEBUG_REG1__y_sort0_gated_23_8__SHIFT 0x0
7397#define SETUP_DEBUG_REG1__x_sort0_gated_23_8_MASK 0xffff0000
7398#define SETUP_DEBUG_REG1__x_sort0_gated_23_8__SHIFT 0x10
7399#define SETUP_DEBUG_REG2__y_sort1_gated_23_8_MASK 0xffff
7400#define SETUP_DEBUG_REG2__y_sort1_gated_23_8__SHIFT 0x0
7401#define SETUP_DEBUG_REG2__x_sort1_gated_23_8_MASK 0xffff0000
7402#define SETUP_DEBUG_REG2__x_sort1_gated_23_8__SHIFT 0x10
7403#define SETUP_DEBUG_REG3__y_sort2_gated_23_8_MASK 0xffff
7404#define SETUP_DEBUG_REG3__y_sort2_gated_23_8__SHIFT 0x0
7405#define SETUP_DEBUG_REG3__x_sort2_gated_23_8_MASK 0xffff0000
7406#define SETUP_DEBUG_REG3__x_sort2_gated_23_8__SHIFT 0x10
7407#define SETUP_DEBUG_REG4__attr_indx_sort0_gated_MASK 0x3fff
7408#define SETUP_DEBUG_REG4__attr_indx_sort0_gated__SHIFT 0x0
7409#define SETUP_DEBUG_REG4__null_prim_gated_MASK 0x4000
7410#define SETUP_DEBUG_REG4__null_prim_gated__SHIFT 0xe
7411#define SETUP_DEBUG_REG4__backfacing_gated_MASK 0x8000
7412#define SETUP_DEBUG_REG4__backfacing_gated__SHIFT 0xf
7413#define SETUP_DEBUG_REG4__st_indx_gated_MASK 0x70000
7414#define SETUP_DEBUG_REG4__st_indx_gated__SHIFT 0x10
7415#define SETUP_DEBUG_REG4__clipped_gated_MASK 0x80000
7416#define SETUP_DEBUG_REG4__clipped_gated__SHIFT 0x13
7417#define SETUP_DEBUG_REG4__dealloc_slot_gated_MASK 0x700000
7418#define SETUP_DEBUG_REG4__dealloc_slot_gated__SHIFT 0x14
7419#define SETUP_DEBUG_REG4__xmajor_gated_MASK 0x800000
7420#define SETUP_DEBUG_REG4__xmajor_gated__SHIFT 0x17
7421#define SETUP_DEBUG_REG4__diamond_rule_gated_MASK 0x3000000
7422#define SETUP_DEBUG_REG4__diamond_rule_gated__SHIFT 0x18
7423#define SETUP_DEBUG_REG4__type_gated_MASK 0x1c000000
7424#define SETUP_DEBUG_REG4__type_gated__SHIFT 0x1a
7425#define SETUP_DEBUG_REG4__fpov_gated_MASK 0x60000000
7426#define SETUP_DEBUG_REG4__fpov_gated__SHIFT 0x1d
7427#define SETUP_DEBUG_REG4__eop_gated_MASK 0x80000000
7428#define SETUP_DEBUG_REG4__eop_gated__SHIFT 0x1f
7429#define SETUP_DEBUG_REG5__attr_indx_sort2_gated_MASK 0x3fff
7430#define SETUP_DEBUG_REG5__attr_indx_sort2_gated__SHIFT 0x0
7431#define SETUP_DEBUG_REG5__attr_indx_sort1_gated_MASK 0xfffc000
7432#define SETUP_DEBUG_REG5__attr_indx_sort1_gated__SHIFT 0xe
7433#define SETUP_DEBUG_REG5__provoking_vtx_gated_MASK 0x30000000
7434#define SETUP_DEBUG_REG5__provoking_vtx_gated__SHIFT 0x1c
7435#define SETUP_DEBUG_REG5__valid_prim_gated_MASK 0x40000000
7436#define SETUP_DEBUG_REG5__valid_prim_gated__SHIFT 0x1e
7437#define SETUP_DEBUG_REG5__pa_reg_sclk_vld_MASK 0x80000000
7438#define SETUP_DEBUG_REG5__pa_reg_sclk_vld__SHIFT 0x1f
7439#define PA_SC_DEBUG_REG0__REG0_FIELD0_MASK 0x3
7440#define PA_SC_DEBUG_REG0__REG0_FIELD0__SHIFT 0x0
7441#define PA_SC_DEBUG_REG0__REG0_FIELD1_MASK 0xc
7442#define PA_SC_DEBUG_REG0__REG0_FIELD1__SHIFT 0x2
7443#define PA_SC_DEBUG_REG1__REG1_FIELD0_MASK 0x3
7444#define PA_SC_DEBUG_REG1__REG1_FIELD0__SHIFT 0x0
7445#define PA_SC_DEBUG_REG1__REG1_FIELD1_MASK 0xc
7446#define PA_SC_DEBUG_REG1__REG1_FIELD1__SHIFT 0x2
7447#define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN_MASK 0x1
7448#define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN__SHIFT 0x0
7449#define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN_MASK 0x2
7450#define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN__SHIFT 0x1
7451#define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000_MASK 0x4
7452#define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000__SHIFT 0x2
7453#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL_MASK 0x8
7454#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL__SHIFT 0x3
7455#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE_MASK 0x10
7456#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE__SHIFT 0x4
7457#define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS_MASK 0x20
7458#define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS__SHIFT 0x5
7459#define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE_MASK 0x40
7460#define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE__SHIFT 0x6
7461#define COMPUTE_DISPATCH_INITIATOR__DISPATCH_CACHE_CNTL_MASK 0x380
7462#define COMPUTE_DISPATCH_INITIATOR__DISPATCH_CACHE_CNTL__SHIFT 0x7
7463#define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL_MASK 0x400
7464#define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL__SHIFT 0xa
7465#define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL_MASK 0x800
7466#define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL__SHIFT 0xb
7467#define COMPUTE_DISPATCH_INITIATOR__DATA_ATC_MASK 0x1000
7468#define COMPUTE_DISPATCH_INITIATOR__DATA_ATC__SHIFT 0xc
7469#define COMPUTE_DISPATCH_INITIATOR__RESTORE_MASK 0x4000
7470#define COMPUTE_DISPATCH_INITIATOR__RESTORE__SHIFT 0xe
7471#define COMPUTE_DIM_X__SIZE_MASK 0xffffffff
7472#define COMPUTE_DIM_X__SIZE__SHIFT 0x0
7473#define COMPUTE_DIM_Y__SIZE_MASK 0xffffffff
7474#define COMPUTE_DIM_Y__SIZE__SHIFT 0x0
7475#define COMPUTE_DIM_Z__SIZE_MASK 0xffffffff
7476#define COMPUTE_DIM_Z__SIZE__SHIFT 0x0
7477#define COMPUTE_START_X__START_MASK 0xffffffff
7478#define COMPUTE_START_X__START__SHIFT 0x0
7479#define COMPUTE_START_Y__START_MASK 0xffffffff
7480#define COMPUTE_START_Y__START__SHIFT 0x0
7481#define COMPUTE_START_Z__START_MASK 0xffffffff
7482#define COMPUTE_START_Z__START__SHIFT 0x0
7483#define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL_MASK 0xffff
7484#define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL__SHIFT 0x0
7485#define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL_MASK 0xffff0000
7486#define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL__SHIFT 0x10
7487#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL_MASK 0xffff
7488#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL__SHIFT 0x0
7489#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL_MASK 0xffff0000
7490#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL__SHIFT 0x10
7491#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL_MASK 0xffff
7492#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL__SHIFT 0x0
7493#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL_MASK 0xffff0000
7494#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL__SHIFT 0x10
7495#define COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE_MASK 0x1
7496#define COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE__SHIFT 0x0
7497#define COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE_MASK 0x1
7498#define COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE__SHIFT 0x0
7499#define COMPUTE_PGM_LO__DATA_MASK 0xffffffff
7500#define COMPUTE_PGM_LO__DATA__SHIFT 0x0
7501#define COMPUTE_PGM_HI__DATA_MASK 0xff
7502#define COMPUTE_PGM_HI__DATA__SHIFT 0x0
7503#define COMPUTE_PGM_HI__INST_ATC_MASK 0x100
7504#define COMPUTE_PGM_HI__INST_ATC__SHIFT 0x8
7505#define COMPUTE_TBA_LO__DATA_MASK 0xffffffff
7506#define COMPUTE_TBA_LO__DATA__SHIFT 0x0
7507#define COMPUTE_TBA_HI__DATA_MASK 0xff
7508#define COMPUTE_TBA_HI__DATA__SHIFT 0x0
7509#define COMPUTE_TMA_LO__DATA_MASK 0xffffffff
7510#define COMPUTE_TMA_LO__DATA__SHIFT 0x0
7511#define COMPUTE_TMA_HI__DATA_MASK 0xff
7512#define COMPUTE_TMA_HI__DATA__SHIFT 0x0
7513#define COMPUTE_PGM_RSRC1__VGPRS_MASK 0x3f
7514#define COMPUTE_PGM_RSRC1__VGPRS__SHIFT 0x0
7515#define COMPUTE_PGM_RSRC1__SGPRS_MASK 0x3c0
7516#define COMPUTE_PGM_RSRC1__SGPRS__SHIFT 0x6
7517#define COMPUTE_PGM_RSRC1__PRIORITY_MASK 0xc00
7518#define COMPUTE_PGM_RSRC1__PRIORITY__SHIFT 0xa
7519#define COMPUTE_PGM_RSRC1__FLOAT_MODE_MASK 0xff000
7520#define COMPUTE_PGM_RSRC1__FLOAT_MODE__SHIFT 0xc
7521#define COMPUTE_PGM_RSRC1__PRIV_MASK 0x100000
7522#define COMPUTE_PGM_RSRC1__PRIV__SHIFT 0x14
7523#define COMPUTE_PGM_RSRC1__DX10_CLAMP_MASK 0x200000
7524#define COMPUTE_PGM_RSRC1__DX10_CLAMP__SHIFT 0x15
7525#define COMPUTE_PGM_RSRC1__DEBUG_MODE_MASK 0x400000
7526#define COMPUTE_PGM_RSRC1__DEBUG_MODE__SHIFT 0x16
7527#define COMPUTE_PGM_RSRC1__IEEE_MODE_MASK 0x800000
7528#define COMPUTE_PGM_RSRC1__IEEE_MODE__SHIFT 0x17
7529#define COMPUTE_PGM_RSRC1__BULKY_MASK 0x1000000
7530#define COMPUTE_PGM_RSRC1__BULKY__SHIFT 0x18
7531#define COMPUTE_PGM_RSRC1__CDBG_USER_MASK 0x2000000
7532#define COMPUTE_PGM_RSRC1__CDBG_USER__SHIFT 0x19
7533#define COMPUTE_PGM_RSRC2__SCRATCH_EN_MASK 0x1
7534#define COMPUTE_PGM_RSRC2__SCRATCH_EN__SHIFT 0x0
7535#define COMPUTE_PGM_RSRC2__USER_SGPR_MASK 0x3e
7536#define COMPUTE_PGM_RSRC2__USER_SGPR__SHIFT 0x1
7537#define COMPUTE_PGM_RSRC2__TRAP_PRESENT_MASK 0x40
7538#define COMPUTE_PGM_RSRC2__TRAP_PRESENT__SHIFT 0x6
7539#define COMPUTE_PGM_RSRC2__TGID_X_EN_MASK 0x80
7540#define COMPUTE_PGM_RSRC2__TGID_X_EN__SHIFT 0x7
7541#define COMPUTE_PGM_RSRC2__TGID_Y_EN_MASK 0x100
7542#define COMPUTE_PGM_RSRC2__TGID_Y_EN__SHIFT 0x8
7543#define COMPUTE_PGM_RSRC2__TGID_Z_EN_MASK 0x200
7544#define COMPUTE_PGM_RSRC2__TGID_Z_EN__SHIFT 0x9
7545#define COMPUTE_PGM_RSRC2__TG_SIZE_EN_MASK 0x400
7546#define COMPUTE_PGM_RSRC2__TG_SIZE_EN__SHIFT 0xa
7547#define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT_MASK 0x1800
7548#define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT__SHIFT 0xb
7549#define COMPUTE_PGM_RSRC2__EXCP_EN_MSB_MASK 0x6000
7550#define COMPUTE_PGM_RSRC2__EXCP_EN_MSB__SHIFT 0xd
7551#define COMPUTE_PGM_RSRC2__LDS_SIZE_MASK 0xff8000
7552#define COMPUTE_PGM_RSRC2__LDS_SIZE__SHIFT 0xf
7553#define COMPUTE_PGM_RSRC2__EXCP_EN_MASK 0x7f000000
7554#define COMPUTE_PGM_RSRC2__EXCP_EN__SHIFT 0x18
7555#define COMPUTE_VMID__DATA_MASK 0xf
7556#define COMPUTE_VMID__DATA__SHIFT 0x0
7557#define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH_MASK 0x3ff
7558#define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH__SHIFT 0x0
7559#define COMPUTE_RESOURCE_LIMITS__TG_PER_CU_MASK 0xf000
7560#define COMPUTE_RESOURCE_LIMITS__TG_PER_CU__SHIFT 0xc
7561#define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD_MASK 0x3f0000
7562#define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD__SHIFT 0x10
7563#define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL_MASK 0x400000
7564#define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL__SHIFT 0x16
7565#define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST_MASK 0x800000
7566#define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST__SHIFT 0x17
7567#define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT_MASK 0x7000000
7568#define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT__SHIFT 0x18
7569#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH0_CU_EN_MASK 0xffff
7570#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH0_CU_EN__SHIFT 0x0
7571#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH1_CU_EN_MASK 0xffff0000
7572#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH1_CU_EN__SHIFT 0x10
7573#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH0_CU_EN_MASK 0xffff
7574#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH0_CU_EN__SHIFT 0x0
7575#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH1_CU_EN_MASK 0xffff0000
7576#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH1_CU_EN__SHIFT 0x10
7577#define COMPUTE_TMPRING_SIZE__WAVES_MASK 0xfff
7578#define COMPUTE_TMPRING_SIZE__WAVES__SHIFT 0x0
7579#define COMPUTE_TMPRING_SIZE__WAVESIZE_MASK 0x1fff000
7580#define COMPUTE_TMPRING_SIZE__WAVESIZE__SHIFT 0xc
7581#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH0_CU_EN_MASK 0xffff
7582#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH0_CU_EN__SHIFT 0x0
7583#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH1_CU_EN_MASK 0xffff0000
7584#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH1_CU_EN__SHIFT 0x10
7585#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH0_CU_EN_MASK 0xffff
7586#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH0_CU_EN__SHIFT 0x0
7587#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH1_CU_EN_MASK 0xffff0000
7588#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH1_CU_EN__SHIFT 0x10
7589#define COMPUTE_RESTART_X__RESTART_MASK 0xffffffff
7590#define COMPUTE_RESTART_X__RESTART__SHIFT 0x0
7591#define COMPUTE_RESTART_Y__RESTART_MASK 0xffffffff
7592#define COMPUTE_RESTART_Y__RESTART__SHIFT 0x0
7593#define COMPUTE_RESTART_Z__RESTART_MASK 0xffffffff
7594#define COMPUTE_RESTART_Z__RESTART__SHIFT 0x0
7595#define COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE_MASK 0x1
7596#define COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE__SHIFT 0x0
7597#define COMPUTE_MISC_RESERVED__SEND_SEID_MASK 0x3
7598#define COMPUTE_MISC_RESERVED__SEND_SEID__SHIFT 0x0
7599#define COMPUTE_MISC_RESERVED__RESERVED2_MASK 0x4
7600#define COMPUTE_MISC_RESERVED__RESERVED2__SHIFT 0x2
7601#define COMPUTE_MISC_RESERVED__RESERVED3_MASK 0x8
7602#define COMPUTE_MISC_RESERVED__RESERVED3__SHIFT 0x3
7603#define COMPUTE_MISC_RESERVED__RESERVED4_MASK 0x10
7604#define COMPUTE_MISC_RESERVED__RESERVED4__SHIFT 0x4
7605#define COMPUTE_USER_DATA_0__DATA_MASK 0xffffffff
7606#define COMPUTE_USER_DATA_0__DATA__SHIFT 0x0
7607#define COMPUTE_USER_DATA_1__DATA_MASK 0xffffffff
7608#define COMPUTE_USER_DATA_1__DATA__SHIFT 0x0
7609#define COMPUTE_USER_DATA_2__DATA_MASK 0xffffffff
7610#define COMPUTE_USER_DATA_2__DATA__SHIFT 0x0
7611#define COMPUTE_USER_DATA_3__DATA_MASK 0xffffffff
7612#define COMPUTE_USER_DATA_3__DATA__SHIFT 0x0
7613#define COMPUTE_USER_DATA_4__DATA_MASK 0xffffffff
7614#define COMPUTE_USER_DATA_4__DATA__SHIFT 0x0
7615#define COMPUTE_USER_DATA_5__DATA_MASK 0xffffffff
7616#define COMPUTE_USER_DATA_5__DATA__SHIFT 0x0
7617#define COMPUTE_USER_DATA_6__DATA_MASK 0xffffffff
7618#define COMPUTE_USER_DATA_6__DATA__SHIFT 0x0
7619#define COMPUTE_USER_DATA_7__DATA_MASK 0xffffffff
7620#define COMPUTE_USER_DATA_7__DATA__SHIFT 0x0
7621#define COMPUTE_USER_DATA_8__DATA_MASK 0xffffffff
7622#define COMPUTE_USER_DATA_8__DATA__SHIFT 0x0
7623#define COMPUTE_USER_DATA_9__DATA_MASK 0xffffffff
7624#define COMPUTE_USER_DATA_9__DATA__SHIFT 0x0
7625#define COMPUTE_USER_DATA_10__DATA_MASK 0xffffffff
7626#define COMPUTE_USER_DATA_10__DATA__SHIFT 0x0
7627#define COMPUTE_USER_DATA_11__DATA_MASK 0xffffffff
7628#define COMPUTE_USER_DATA_11__DATA__SHIFT 0x0
7629#define COMPUTE_USER_DATA_12__DATA_MASK 0xffffffff
7630#define COMPUTE_USER_DATA_12__DATA__SHIFT 0x0
7631#define COMPUTE_USER_DATA_13__DATA_MASK 0xffffffff
7632#define COMPUTE_USER_DATA_13__DATA__SHIFT 0x0
7633#define COMPUTE_USER_DATA_14__DATA_MASK 0xffffffff
7634#define COMPUTE_USER_DATA_14__DATA__SHIFT 0x0
7635#define COMPUTE_USER_DATA_15__DATA_MASK 0xffffffff
7636#define COMPUTE_USER_DATA_15__DATA__SHIFT 0x0
7637#define CSPRIV_CONNECT__DOORBELL_OFFSET_MASK 0x1fffff
7638#define CSPRIV_CONNECT__DOORBELL_OFFSET__SHIFT 0x0
7639#define CSPRIV_CONNECT__QUEUE_ID_MASK 0xe00000
7640#define CSPRIV_CONNECT__QUEUE_ID__SHIFT 0x15
7641#define CSPRIV_CONNECT__VMID_MASK 0x3c000000
7642#define CSPRIV_CONNECT__VMID__SHIFT 0x1a
7643#define CSPRIV_CONNECT__UNORD_DISP_MASK 0x80000000
7644#define CSPRIV_CONNECT__UNORD_DISP__SHIFT 0x1f
7645#define CSPRIV_THREAD_TRACE_TG0__TGID_X_MASK 0xffffffff
7646#define CSPRIV_THREAD_TRACE_TG0__TGID_X__SHIFT 0x0
7647#define CSPRIV_THREAD_TRACE_TG1__TGID_Y_MASK 0xffffffff
7648#define CSPRIV_THREAD_TRACE_TG1__TGID_Y__SHIFT 0x0
7649#define CSPRIV_THREAD_TRACE_TG2__TGID_Z_MASK 0xffffffff
7650#define CSPRIV_THREAD_TRACE_TG2__TGID_Z__SHIFT 0x0
7651#define CSPRIV_THREAD_TRACE_TG3__WAVE_ID_BASE_MASK 0xfff
7652#define CSPRIV_THREAD_TRACE_TG3__WAVE_ID_BASE__SHIFT 0x0
7653#define CSPRIV_THREAD_TRACE_TG3__THREADS_IN_GROUP_MASK 0xfff000
7654#define CSPRIV_THREAD_TRACE_TG3__THREADS_IN_GROUP__SHIFT 0xc
7655#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_X_FLAG_MASK 0x1000000
7656#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_X_FLAG__SHIFT 0x18
7657#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_Y_FLAG_MASK 0x2000000
7658#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_Y_FLAG__SHIFT 0x19
7659#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_Z_FLAG_MASK 0x4000000
7660#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_Z_FLAG__SHIFT 0x1a
7661#define CSPRIV_THREAD_TRACE_TG3__LAST_TG_MASK 0x8000000
7662#define CSPRIV_THREAD_TRACE_TG3__LAST_TG__SHIFT 0x1b
7663#define CSPRIV_THREAD_TRACE_TG3__FIRST_TG_MASK 0x10000000
7664#define CSPRIV_THREAD_TRACE_TG3__FIRST_TG__SHIFT 0x1c
7665#define CSPRIV_THREAD_TRACE_EVENT__EVENT_ID_MASK 0x1f
7666#define CSPRIV_THREAD_TRACE_EVENT__EVENT_ID__SHIFT 0x0
7667#define RLC_CNTL__RLC_ENABLE_F32_MASK 0x1
7668#define RLC_CNTL__RLC_ENABLE_F32__SHIFT 0x0
7669#define RLC_CNTL__FORCE_RETRY_MASK 0x2
7670#define RLC_CNTL__FORCE_RETRY__SHIFT 0x1
7671#define RLC_CNTL__READ_CACHE_DISABLE_MASK 0x4
7672#define RLC_CNTL__READ_CACHE_DISABLE__SHIFT 0x2
7673#define RLC_CNTL__RLC_STEP_F32_MASK 0x8
7674#define RLC_CNTL__RLC_STEP_F32__SHIFT 0x3
7675#define RLC_CNTL__SOFT_RESET_DEBUG_MODE_MASK 0x10
7676#define RLC_CNTL__SOFT_RESET_DEBUG_MODE__SHIFT 0x4
7677#define RLC_CNTL__RESERVED_MASK 0xffffff00
7678#define RLC_CNTL__RESERVED__SHIFT 0x8
7679#define RLC_DEBUG_SELECT__SELECT_MASK 0xff
7680#define RLC_DEBUG_SELECT__SELECT__SHIFT 0x0
7681#define RLC_DEBUG_SELECT__RESERVED_MASK 0xffffff00
7682#define RLC_DEBUG_SELECT__RESERVED__SHIFT 0x8
7683#define RLC_DEBUG__DATA_MASK 0xffffffff
7684#define RLC_DEBUG__DATA__SHIFT 0x0
7685#define RLC_MC_CNTL__WRREQ_SWAP_MASK 0x3
7686#define RLC_MC_CNTL__WRREQ_SWAP__SHIFT 0x0
7687#define RLC_MC_CNTL__WRREQ_TRAN_MASK 0x4
7688#define RLC_MC_CNTL__WRREQ_TRAN__SHIFT 0x2
7689#define RLC_MC_CNTL__WRREQ_PRIV_MASK 0x8
7690#define RLC_MC_CNTL__WRREQ_PRIV__SHIFT 0x3
7691#define RLC_MC_CNTL__WRNFO_STALL_MASK 0x10
7692#define RLC_MC_CNTL__WRNFO_STALL__SHIFT 0x4
7693#define RLC_MC_CNTL__WRNFO_URG_MASK 0x1e0
7694#define RLC_MC_CNTL__WRNFO_URG__SHIFT 0x5
7695#define RLC_MC_CNTL__WRREQ_DW_IMASK_MASK 0x1e00
7696#define RLC_MC_CNTL__WRREQ_DW_IMASK__SHIFT 0x9
7697#define RLC_MC_CNTL__RESERVED_B_MASK 0xfe000
7698#define RLC_MC_CNTL__RESERVED_B__SHIFT 0xd
7699#define RLC_MC_CNTL__RDNFO_URG_MASK 0xf00000
7700#define RLC_MC_CNTL__RDNFO_URG__SHIFT 0x14
7701#define RLC_MC_CNTL__RDREQ_SWAP_MASK 0x3000000
7702#define RLC_MC_CNTL__RDREQ_SWAP__SHIFT 0x18
7703#define RLC_MC_CNTL__RDREQ_TRAN_MASK 0x4000000
7704#define RLC_MC_CNTL__RDREQ_TRAN__SHIFT 0x1a
7705#define RLC_MC_CNTL__RDREQ_PRIV_MASK 0x8000000
7706#define RLC_MC_CNTL__RDREQ_PRIV__SHIFT 0x1b
7707#define RLC_MC_CNTL__RDNFO_STALL_MASK 0x10000000
7708#define RLC_MC_CNTL__RDNFO_STALL__SHIFT 0x1c
7709#define RLC_MC_CNTL__RESERVED_MASK 0xe0000000
7710#define RLC_MC_CNTL__RESERVED__SHIFT 0x1d
7711#define RLC_STAT__RLC_BUSY_MASK 0x1
7712#define RLC_STAT__RLC_BUSY__SHIFT 0x0
7713#define RLC_STAT__RLC_GPM_BUSY_MASK 0x2
7714#define RLC_STAT__RLC_GPM_BUSY__SHIFT 0x1
7715#define RLC_STAT__RLC_SPM_BUSY_MASK 0x4
7716#define RLC_STAT__RLC_SPM_BUSY__SHIFT 0x2
7717#define RLC_STAT__RESERVED_MASK 0xfffffff8
7718#define RLC_STAT__RESERVED__SHIFT 0x3
7719#define RLC_SAFE_MODE__REQ_MASK 0x1
7720#define RLC_SAFE_MODE__REQ__SHIFT 0x0
7721#define RLC_SAFE_MODE__MESSAGE_MASK 0x1e
7722#define RLC_SAFE_MODE__MESSAGE__SHIFT 0x1
7723#define RLC_SAFE_MODE__RESERVED_MASK 0xffffffe0
7724#define RLC_SAFE_MODE__RESERVED__SHIFT 0x5
7725#define RLC_SOFT_RESET_GPU__SOFT_RESET_GPU_MASK 0x1
7726#define RLC_SOFT_RESET_GPU__SOFT_RESET_GPU__SHIFT 0x0
7727#define RLC_SOFT_RESET_GPU__RESERVED_MASK 0xfffffffe
7728#define RLC_SOFT_RESET_GPU__RESERVED__SHIFT 0x1
7729#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK 0x1
7730#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN__SHIFT 0x0
7731#define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN_MASK 0x2
7732#define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN__SHIFT 0x1
7733#define RLC_MEM_SLP_CNTL__RESERVED_MASK 0xfc
7734#define RLC_MEM_SLP_CNTL__RESERVED__SHIFT 0x2
7735#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY_MASK 0xff00
7736#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY__SHIFT 0x8
7737#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY_MASK 0xff0000
7738#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY__SHIFT 0x10
7739#define RLC_MEM_SLP_CNTL__RESERVED1_MASK 0xff000000
7740#define RLC_MEM_SLP_CNTL__RESERVED1__SHIFT 0x18
7741#define RLC_PERFMON_CNTL__PERFMON_STATE_MASK 0x7
7742#define RLC_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
7743#define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x400
7744#define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa
7745#define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0xff
7746#define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
7747#define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0xff
7748#define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
7749#define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
7750#define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
7751#define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
7752#define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
7753#define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
7754#define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
7755#define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
7756#define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
7757#define CGTT_RLC_CLK_CTRL__ON_DELAY_MASK 0xf
7758#define CGTT_RLC_CLK_CTRL__ON_DELAY__SHIFT 0x0
7759#define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
7760#define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
7761#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000
7762#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
7763#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000
7764#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
7765#define RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK 0x1
7766#define RLC_LB_CNTL__LOAD_BALANCE_ENABLE__SHIFT 0x0
7767#define RLC_LB_CNTL__LB_CNT_CP_BUSY_MASK 0x2
7768#define RLC_LB_CNTL__LB_CNT_CP_BUSY__SHIFT 0x1
7769#define RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK 0x4
7770#define RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE__SHIFT 0x2
7771#define RLC_LB_CNTL__LB_CNT_REG_INC_MASK 0x8
7772#define RLC_LB_CNTL__LB_CNT_REG_INC__SHIFT 0x3
7773#define RLC_LB_CNTL__CU_MASK_USED_OFF_HYST_MASK 0xff0
7774#define RLC_LB_CNTL__CU_MASK_USED_OFF_HYST__SHIFT 0x4
7775#define RLC_LB_CNTL__RESERVED_MASK 0xfffff000
7776#define RLC_LB_CNTL__RESERVED__SHIFT 0xc
7777#define RLC_LB_CNTR_MAX__LB_CNTR_MAX_MASK 0xffffffff
7778#define RLC_LB_CNTR_MAX__LB_CNTR_MAX__SHIFT 0x0
7779#define RLC_LB_CNTR_INIT__LB_CNTR_INIT_MASK 0xffffffff
7780#define RLC_LB_CNTR_INIT__LB_CNTR_INIT__SHIFT 0x0
7781#define RLC_LOAD_BALANCE_CNTR__RLC_LOAD_BALANCE_CNTR_MASK 0xffffffff
7782#define RLC_LOAD_BALANCE_CNTR__RLC_LOAD_BALANCE_CNTR__SHIFT 0x0
7783#define RLC_SAVE_AND_RESTORE_BASE__BASE_MASK 0xffffffff
7784#define RLC_SAVE_AND_RESTORE_BASE__BASE__SHIFT 0x0
7785#define RLC_JUMP_TABLE_RESTORE__ADDR_MASK 0xffffffff
7786#define RLC_JUMP_TABLE_RESTORE__ADDR__SHIFT 0x0
7787#define RLC_DRIVER_CPDMA_STATUS__DRIVER_REQUEST_MASK 0x1
7788#define RLC_DRIVER_CPDMA_STATUS__DRIVER_REQUEST__SHIFT 0x0
7789#define RLC_DRIVER_CPDMA_STATUS__RESERVED1_MASK 0xe
7790#define RLC_DRIVER_CPDMA_STATUS__RESERVED1__SHIFT 0x1
7791#define RLC_DRIVER_CPDMA_STATUS__DRIVER_ACK_MASK 0x10
7792#define RLC_DRIVER_CPDMA_STATUS__DRIVER_ACK__SHIFT 0x4
7793#define RLC_DRIVER_CPDMA_STATUS__RESERVED_MASK 0xffffffe0
7794#define RLC_DRIVER_CPDMA_STATUS__RESERVED__SHIFT 0x5
7795#define RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE_MASK 0xff
7796#define RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE__SHIFT 0x0
7797#define RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK 0xff00
7798#define RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT 0x8
7799#define RLC_PG_DELAY_2__PERCU_TIMEOUT_VALUE_MASK 0xffff0000
7800#define RLC_PG_DELAY_2__PERCU_TIMEOUT_VALUE__SHIFT 0x10
7801#define RLC_GPM_DEBUG_SELECT__SELECT_MASK 0xff
7802#define RLC_GPM_DEBUG_SELECT__SELECT__SHIFT 0x0
7803#define RLC_GPM_DEBUG_SELECT__RESERVED_MASK 0xffffff00
7804#define RLC_GPM_DEBUG_SELECT__RESERVED__SHIFT 0x8
7805#define RLC_GPM_DEBUG__DATA_MASK 0xffffffff
7806#define RLC_GPM_DEBUG__DATA__SHIFT 0x0
7807#define RLC_GPM_UCODE_ADDR__UCODE_ADDR_MASK 0xfff
7808#define RLC_GPM_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
7809#define RLC_GPM_UCODE_ADDR__RESERVED_MASK 0xfffff000
7810#define RLC_GPM_UCODE_ADDR__RESERVED__SHIFT 0xc
7811#define RLC_GPM_UCODE_DATA__UCODE_DATA_MASK 0xffffffff
7812#define RLC_GPM_UCODE_DATA__UCODE_DATA__SHIFT 0x0
7813#define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB_MASK 0xffffffff
7814#define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB__SHIFT 0x0
7815#define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB_MASK 0xffffffff
7816#define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB__SHIFT 0x0
7817#define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE_MASK 0x1
7818#define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE__SHIFT 0x0
7819#define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED_MASK 0xfffffffe
7820#define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED__SHIFT 0x1
7821#define RLC_UCODE_CNTL__RLC_UCODE_FLAGS_MASK 0xffffffff
7822#define RLC_UCODE_CNTL__RLC_UCODE_FLAGS__SHIFT 0x0
7823#define RLC_GPM_STAT__RLC_BUSY_MASK 0x1
7824#define RLC_GPM_STAT__RLC_BUSY__SHIFT 0x0
7825#define RLC_GPM_STAT__GFX_POWER_STATUS_MASK 0x2
7826#define RLC_GPM_STAT__GFX_POWER_STATUS__SHIFT 0x1
7827#define RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK 0x4
7828#define RLC_GPM_STAT__GFX_CLOCK_STATUS__SHIFT 0x2
7829#define RLC_GPM_STAT__GFX_LS_STATUS_MASK 0x8
7830#define RLC_GPM_STAT__GFX_LS_STATUS__SHIFT 0x3
7831#define RLC_GPM_STAT__RESERVED_MASK 0xfffffff0
7832#define RLC_GPM_STAT__RESERVED__SHIFT 0x4
7833#define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL_MASK 0x3f
7834#define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL__SHIFT 0x0
7835#define RLC_GPU_CLOCK_32_RES_SEL__RESERVED_MASK 0xffffffc0
7836#define RLC_GPU_CLOCK_32_RES_SEL__RESERVED__SHIFT 0x6
7837#define RLC_GPU_CLOCK_32__GPU_CLOCK_32_MASK 0xffffffff
7838#define RLC_GPU_CLOCK_32__GPU_CLOCK_32__SHIFT 0x0
7839#define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK 0x1
7840#define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE__SHIFT 0x0
7841#define RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK 0x2
7842#define RLC_PG_CNTL__GFX_POWER_GATING_SRC__SHIFT 0x1
7843#define RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK 0x4
7844#define RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE__SHIFT 0x2
7845#define RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK 0x8
7846#define RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE__SHIFT 0x3
7847#define RLC_PG_CNTL__RESERVED_MASK 0xfff0
7848#define RLC_PG_CNTL__RESERVED__SHIFT 0x4
7849#define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE_MASK 0x10000
7850#define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE__SHIFT 0x10
7851#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK 0x20000
7852#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE__SHIFT 0x11
7853#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK 0x40000
7854#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE__SHIFT 0x12
7855#define RLC_PG_CNTL__RESERVED1_MASK 0xf80000
7856#define RLC_PG_CNTL__RESERVED1__SHIFT 0x13
7857#define RLC_PG_CNTL__PG_ERROR_STATUS_MASK 0xff000000
7858#define RLC_PG_CNTL__PG_ERROR_STATUS__SHIFT 0x18
7859#define RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY_MASK 0xff
7860#define RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY__SHIFT 0x0
7861#define RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY_MASK 0xff00
7862#define RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY__SHIFT 0x8
7863#define RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY_MASK 0xff0000
7864#define RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY__SHIFT 0x10
7865#define RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY_MASK 0xff000000
7866#define RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY__SHIFT 0x18
7867#define RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE_MASK 0x1
7868#define RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE__SHIFT 0x0
7869#define RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE_MASK 0x2
7870#define RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE__SHIFT 0x1
7871#define RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE_MASK 0x4
7872#define RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE__SHIFT 0x2
7873#define RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE_MASK 0x8
7874#define RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE__SHIFT 0x3
7875#define RLC_GPM_THREAD_ENABLE__RESERVED_MASK 0xfffffff0
7876#define RLC_GPM_THREAD_ENABLE__RESERVED__SHIFT 0x4
7877#define RLC_GPM_VMID_THREAD0__RLC_VMID_MASK 0xf
7878#define RLC_GPM_VMID_THREAD0__RLC_VMID__SHIFT 0x0
7879#define RLC_GPM_VMID_THREAD0__RESERVED_MASK 0xfffffff0
7880#define RLC_GPM_VMID_THREAD0__RESERVED__SHIFT 0x4
7881#define RLC_GPM_VMID_THREAD1__RLC_VMID_MASK 0xf
7882#define RLC_GPM_VMID_THREAD1__RLC_VMID__SHIFT 0x0
7883#define RLC_GPM_VMID_THREAD1__RESERVED_MASK 0xfffffff0
7884#define RLC_GPM_VMID_THREAD1__RESERVED__SHIFT 0x4
7885#define RLC_CGTT_MGCG_OVERRIDE__OVERRIDE_MASK 0xffffffff
7886#define RLC_CGTT_MGCG_OVERRIDE__OVERRIDE__SHIFT 0x0
7887#define RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK 0x1
7888#define RLC_CGCG_CGLS_CTRL__CGCG_EN__SHIFT 0x0
7889#define RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK 0x2
7890#define RLC_CGCG_CGLS_CTRL__CGLS_EN__SHIFT 0x1
7891#define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK 0xfc
7892#define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT 0x2
7893#define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK 0x7ffff00
7894#define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT 0x8
7895#define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER_MASK 0x8000000
7896#define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER__SHIFT 0x1b
7897#define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL_MASK 0x10000000
7898#define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL__SHIFT 0x1c
7899#define RLC_CGCG_CGLS_CTRL__SLEEP_MODE_MASK 0x60000000
7900#define RLC_CGCG_CGLS_CTRL__SLEEP_MODE__SHIFT 0x1d
7901#define RLC_CGCG_CGLS_CTRL__SPARE_MASK 0x80000000
7902#define RLC_CGCG_CGLS_CTRL__SPARE__SHIFT 0x1f
7903#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT_MASK 0xf
7904#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT__SHIFT 0x0
7905#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT_MASK 0xf0
7906#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT__SHIFT 0x4
7907#define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT_MASK 0xf00
7908#define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT__SHIFT 0x8
7909#define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT_MASK 0xf000
7910#define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT__SHIFT 0xc
7911#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT_MASK 0xfff0000
7912#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT__SHIFT 0x10
7913#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT_MASK 0xf0000000
7914#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT__SHIFT 0x1c
7915#define RLC_DYN_PG_STATUS__PG_STATUS_CU_MASK_MASK 0xffffffff
7916#define RLC_DYN_PG_STATUS__PG_STATUS_CU_MASK__SHIFT 0x0
7917#define RLC_DYN_PG_REQUEST__PG_REQUEST_CU_MASK_MASK 0xffffffff
7918#define RLC_DYN_PG_REQUEST__PG_REQUEST_CU_MASK__SHIFT 0x0
7919#define RLC_PG_DELAY__POWER_UP_DELAY_MASK 0xff
7920#define RLC_PG_DELAY__POWER_UP_DELAY__SHIFT 0x0
7921#define RLC_PG_DELAY__POWER_DOWN_DELAY_MASK 0xff00
7922#define RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT 0x8
7923#define RLC_PG_DELAY__CMD_PROPAGATE_DELAY_MASK 0xff0000
7924#define RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT 0x10
7925#define RLC_PG_DELAY__MEM_SLEEP_DELAY_MASK 0xff000000
7926#define RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT 0x18
7927#define RLC_CU_STATUS__WORK_PENDING_MASK 0xffffffff
7928#define RLC_CU_STATUS__WORK_PENDING__SHIFT 0x0
7929#define RLC_LB_INIT_CU_MASK__INIT_CU_MASK_MASK 0xffffffff
7930#define RLC_LB_INIT_CU_MASK__INIT_CU_MASK__SHIFT 0x0
7931#define RLC_LB_ALWAYS_ACTIVE_CU_MASK__ALWAYS_ACTIVE_CU_MASK_MASK 0xffffffff
7932#define RLC_LB_ALWAYS_ACTIVE_CU_MASK__ALWAYS_ACTIVE_CU_MASK__SHIFT 0x0
7933#define RLC_LB_PARAMS__SKIP_L2_CHECK_MASK 0x1
7934#define RLC_LB_PARAMS__SKIP_L2_CHECK__SHIFT 0x0
7935#define RLC_LB_PARAMS__FIFO_SAMPLES_MASK 0xfe
7936#define RLC_LB_PARAMS__FIFO_SAMPLES__SHIFT 0x1
7937#define RLC_LB_PARAMS__PG_IDLE_SAMPLES_MASK 0xff00
7938#define RLC_LB_PARAMS__PG_IDLE_SAMPLES__SHIFT 0x8
7939#define RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL_MASK 0xffff0000
7940#define RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL__SHIFT 0x10
7941#define RLC_THREAD1_DELAY__CU_IDEL_DELAY_MASK 0xff
7942#define RLC_THREAD1_DELAY__CU_IDEL_DELAY__SHIFT 0x0
7943#define RLC_THREAD1_DELAY__LBPW_INNER_LOOP_DELAY_MASK 0xff00
7944#define RLC_THREAD1_DELAY__LBPW_INNER_LOOP_DELAY__SHIFT 0x8
7945#define RLC_THREAD1_DELAY__LBPW_OUTER_LOOP_DELAY_MASK 0xff0000
7946#define RLC_THREAD1_DELAY__LBPW_OUTER_LOOP_DELAY__SHIFT 0x10
7947#define RLC_THREAD1_DELAY__SPARE_MASK 0xff000000
7948#define RLC_THREAD1_DELAY__SPARE__SHIFT 0x18
7949#define RLC_PG_ALWAYS_ON_CU_MASK__AON_CU_MASK_MASK 0xffffffff
7950#define RLC_PG_ALWAYS_ON_CU_MASK__AON_CU_MASK__SHIFT 0x0
7951#define RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK 0xff
7952#define RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT 0x0
7953#define RLC_MAX_PG_CU__SPARE_MASK 0xffffff00
7954#define RLC_MAX_PG_CU__SPARE__SHIFT 0x8
7955#define RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK 0x1
7956#define RLC_AUTO_PG_CTRL__AUTO_PG_EN__SHIFT 0x0
7957#define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN_MASK 0x2
7958#define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN__SHIFT 0x1
7959#define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN_MASK 0x4
7960#define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN__SHIFT 0x2
7961#define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK 0x7fff8
7962#define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT 0x3
7963#define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK 0xfff80000
7964#define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD__SHIFT 0x13
7965#define RLC_SMU_GRBM_REG_SAVE_CTRL__START_GRBM_REG_SAVE_MASK 0x1
7966#define RLC_SMU_GRBM_REG_SAVE_CTRL__START_GRBM_REG_SAVE__SHIFT 0x0
7967#define RLC_SMU_GRBM_REG_SAVE_CTRL__SPARE_MASK 0xfffffffe
7968#define RLC_SMU_GRBM_REG_SAVE_CTRL__SPARE__SHIFT 0x1
7969#define RLC_SMU_PG_CTRL__START_PG_MASK 0x1
7970#define RLC_SMU_PG_CTRL__START_PG__SHIFT 0x0
7971#define RLC_SMU_PG_CTRL__SPARE_MASK 0xfffffffe
7972#define RLC_SMU_PG_CTRL__SPARE__SHIFT 0x1
7973#define RLC_SMU_PG_WAKE_UP_CTRL__START_PG_WAKE_UP_MASK 0x1
7974#define RLC_SMU_PG_WAKE_UP_CTRL__START_PG_WAKE_UP__SHIFT 0x0
7975#define RLC_SMU_PG_WAKE_UP_CTRL__SPARE_MASK 0xfffffffe
7976#define RLC_SMU_PG_WAKE_UP_CTRL__SPARE__SHIFT 0x1
7977#define RLC_SERDES_RD_MASTER_INDEX__CU_ID_MASK 0xf
7978#define RLC_SERDES_RD_MASTER_INDEX__CU_ID__SHIFT 0x0
7979#define RLC_SERDES_RD_MASTER_INDEX__SH_ID_MASK 0x30
7980#define RLC_SERDES_RD_MASTER_INDEX__SH_ID__SHIFT 0x4
7981#define RLC_SERDES_RD_MASTER_INDEX__SE_ID_MASK 0x1c0
7982#define RLC_SERDES_RD_MASTER_INDEX__SE_ID__SHIFT 0x6
7983#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_ID_MASK 0x200
7984#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_ID__SHIFT 0x9
7985#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_MASK 0x400
7986#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU__SHIFT 0xa
7987#define RLC_SERDES_RD_MASTER_INDEX__NON_SE_MASK 0x3800
7988#define RLC_SERDES_RD_MASTER_INDEX__NON_SE__SHIFT 0xb
7989#define RLC_SERDES_RD_MASTER_INDEX__DATA_REG_ID_MASK 0xc000
7990#define RLC_SERDES_RD_MASTER_INDEX__DATA_REG_ID__SHIFT 0xe
7991#define RLC_SERDES_RD_MASTER_INDEX__SPARE_MASK 0xffff0000
7992#define RLC_SERDES_RD_MASTER_INDEX__SPARE__SHIFT 0x10
7993#define RLC_SERDES_RD_DATA_0__DATA_MASK 0xffffffff
7994#define RLC_SERDES_RD_DATA_0__DATA__SHIFT 0x0
7995#define RLC_SERDES_RD_DATA_1__DATA_MASK 0xffffffff
7996#define RLC_SERDES_RD_DATA_1__DATA__SHIFT 0x0
7997#define RLC_SERDES_RD_DATA_2__DATA_MASK 0xffffffff
7998#define RLC_SERDES_RD_DATA_2__DATA__SHIFT 0x0
7999#define RLC_SERDES_WR_CU_MASTER_MASK__MASTER_MASK_MASK 0xffffffff
8000#define RLC_SERDES_WR_CU_MASTER_MASK__MASTER_MASK__SHIFT 0x0
8001#define RLC_SERDES_WR_NONCU_MASTER_MASK__SE_MASTER_MASK_MASK 0xffff
8002#define RLC_SERDES_WR_NONCU_MASTER_MASK__SE_MASTER_MASK__SHIFT 0x0
8003#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_MASTER_MASK_MASK 0x10000
8004#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_MASTER_MASK__SHIFT 0x10
8005#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC0_MASTER_MASK_MASK 0x20000
8006#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC0_MASTER_MASK__SHIFT 0x11
8007#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC1_MASTER_MASK_MASK 0x40000
8008#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC1_MASTER_MASK__SHIFT 0x12
8009#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE0_MASTER_MASK_MASK 0x80000
8010#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE0_MASTER_MASK__SHIFT 0x13
8011#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE1_MASTER_MASK_MASK 0x100000
8012#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE1_MASTER_MASK__SHIFT 0x14
8013#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE2_MASTER_MASK_MASK 0x200000
8014#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE2_MASTER_MASK__SHIFT 0x15
8015#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE3_MASTER_MASK_MASK 0x400000
8016#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE3_MASTER_MASK__SHIFT 0x16
8017#define RLC_SERDES_WR_NONCU_MASTER_MASK__RESERVED_MASK 0xff800000
8018#define RLC_SERDES_WR_NONCU_MASTER_MASK__RESERVED__SHIFT 0x17
8019#define RLC_SERDES_WR_CTRL__BPM_ADDR_MASK 0xff
8020#define RLC_SERDES_WR_CTRL__BPM_ADDR__SHIFT 0x0
8021#define RLC_SERDES_WR_CTRL__POWER_DOWN_MASK 0x100
8022#define RLC_SERDES_WR_CTRL__POWER_DOWN__SHIFT 0x8
8023#define RLC_SERDES_WR_CTRL__POWER_UP_MASK 0x200
8024#define RLC_SERDES_WR_CTRL__POWER_UP__SHIFT 0x9
8025#define RLC_SERDES_WR_CTRL__P1_SELECT_MASK 0x400
8026#define RLC_SERDES_WR_CTRL__P1_SELECT__SHIFT 0xa
8027#define RLC_SERDES_WR_CTRL__P2_SELECT_MASK 0x800
8028#define RLC_SERDES_WR_CTRL__P2_SELECT__SHIFT 0xb
8029#define RLC_SERDES_WR_CTRL__WRITE_COMMAND_MASK 0x1000
8030#define RLC_SERDES_WR_CTRL__WRITE_COMMAND__SHIFT 0xc
8031#define RLC_SERDES_WR_CTRL__READ_COMMAND_MASK 0x2000
8032#define RLC_SERDES_WR_CTRL__READ_COMMAND__SHIFT 0xd
8033#define RLC_SERDES_WR_CTRL__RESERVED_1_MASK 0xc000
8034#define RLC_SERDES_WR_CTRL__RESERVED_1__SHIFT 0xe
8035#define RLC_SERDES_WR_CTRL__CGLS_ENABLE_MASK 0x10000
8036#define RLC_SERDES_WR_CTRL__CGLS_ENABLE__SHIFT 0x10
8037#define RLC_SERDES_WR_CTRL__CGLS_DISABLE_MASK 0x20000
8038#define RLC_SERDES_WR_CTRL__CGLS_DISABLE__SHIFT 0x11
8039#define RLC_SERDES_WR_CTRL__CGLS_ON_MASK 0x40000
8040#define RLC_SERDES_WR_CTRL__CGLS_ON__SHIFT 0x12
8041#define RLC_SERDES_WR_CTRL__CGLS_OFF_MASK 0x80000
8042#define RLC_SERDES_WR_CTRL__CGLS_OFF__SHIFT 0x13
8043#define RLC_SERDES_WR_CTRL__CGCG_OVERRIDE_0_MASK 0x100000
8044#define RLC_SERDES_WR_CTRL__CGCG_OVERRIDE_0__SHIFT 0x14
8045#define RLC_SERDES_WR_CTRL__CGCG_OVERRIDE_1_MASK 0x200000
8046#define RLC_SERDES_WR_CTRL__CGCG_OVERRIDE_1__SHIFT 0x15
8047#define RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_0_MASK 0x400000
8048#define RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_0__SHIFT 0x16
8049#define RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_1_MASK 0x800000
8050#define RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_1__SHIFT 0x17
8051#define RLC_SERDES_WR_CTRL__RESERVED_2_MASK 0xf000000
8052#define RLC_SERDES_WR_CTRL__RESERVED_2__SHIFT 0x18
8053#define RLC_SERDES_WR_CTRL__REG_ADDR_MASK 0xf0000000
8054#define RLC_SERDES_WR_CTRL__REG_ADDR__SHIFT 0x1c
8055#define RLC_SERDES_WR_DATA__DATA_MASK 0xffffffff
8056#define RLC_SERDES_WR_DATA__DATA__SHIFT 0x0
8057#define RLC_SERDES_CU_MASTER_BUSY__BUSY_BUSY_MASK 0xffffffff
8058#define RLC_SERDES_CU_MASTER_BUSY__BUSY_BUSY__SHIFT 0x0
8059#define RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK 0xffff
8060#define RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY__SHIFT 0x0
8061#define RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK 0x10000
8062#define RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY__SHIFT 0x10
8063#define RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK 0x20000
8064#define RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY__SHIFT 0x11
8065#define RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK 0x40000
8066#define RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY__SHIFT 0x12
8067#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE0_MASTER_BUSY_MASK 0x80000
8068#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE0_MASTER_BUSY__SHIFT 0x13
8069#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE1_MASTER_BUSY_MASK 0x100000
8070#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE1_MASTER_BUSY__SHIFT 0x14
8071#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE2_MASTER_BUSY_MASK 0x200000
8072#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE2_MASTER_BUSY__SHIFT 0x15
8073#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE3_MASTER_BUSY_MASK 0x400000
8074#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE3_MASTER_BUSY__SHIFT 0x16
8075#define RLC_SERDES_NONCU_MASTER_BUSY__RESERVED_MASK 0xff800000
8076#define RLC_SERDES_NONCU_MASTER_BUSY__RESERVED__SHIFT 0x17
8077#define RLC_GPM_GENERAL_0__DATA_MASK 0xffffffff
8078#define RLC_GPM_GENERAL_0__DATA__SHIFT 0x0
8079#define RLC_GPM_GENERAL_1__DATA_MASK 0xffffffff
8080#define RLC_GPM_GENERAL_1__DATA__SHIFT 0x0
8081#define RLC_GPM_GENERAL_2__DATA_MASK 0xffffffff
8082#define RLC_GPM_GENERAL_2__DATA__SHIFT 0x0
8083#define RLC_GPM_GENERAL_3__DATA_MASK 0xffffffff
8084#define RLC_GPM_GENERAL_3__DATA__SHIFT 0x0
8085#define RLC_GPM_GENERAL_4__DATA_MASK 0xffffffff
8086#define RLC_GPM_GENERAL_4__DATA__SHIFT 0x0
8087#define RLC_GPM_GENERAL_5__DATA_MASK 0xffffffff
8088#define RLC_GPM_GENERAL_5__DATA__SHIFT 0x0
8089#define RLC_GPM_GENERAL_6__DATA_MASK 0xffffffff
8090#define RLC_GPM_GENERAL_6__DATA__SHIFT 0x0
8091#define RLC_GPM_GENERAL_7__DATA_MASK 0xffffffff
8092#define RLC_GPM_GENERAL_7__DATA__SHIFT 0x0
8093#define RLC_GPM_CU_PD_TIMEOUT__TIMEOUT_MASK 0xffffffff
8094#define RLC_GPM_CU_PD_TIMEOUT__TIMEOUT__SHIFT 0x0
8095#define RLC_GPM_SCRATCH_ADDR__ADDR_MASK 0x1ff
8096#define RLC_GPM_SCRATCH_ADDR__ADDR__SHIFT 0x0
8097#define RLC_GPM_SCRATCH_ADDR__RESERVED_MASK 0xfffffe00
8098#define RLC_GPM_SCRATCH_ADDR__RESERVED__SHIFT 0x9
8099#define RLC_GPM_SCRATCH_DATA__DATA_MASK 0xffffffff
8100#define RLC_GPM_SCRATCH_DATA__DATA__SHIFT 0x0
8101#define RLC_STATIC_PG_STATUS__PG_STATUS_CU_MASK_MASK 0xffffffff
8102#define RLC_STATIC_PG_STATUS__PG_STATUS_CU_MASK__SHIFT 0x0
8103#define RLC_GPM_PERF_COUNT_0__FEATURE_SEL_MASK 0xf
8104#define RLC_GPM_PERF_COUNT_0__FEATURE_SEL__SHIFT 0x0
8105#define RLC_GPM_PERF_COUNT_0__SE_INDEX_MASK 0xf0
8106#define RLC_GPM_PERF_COUNT_0__SE_INDEX__SHIFT 0x4
8107#define RLC_GPM_PERF_COUNT_0__SH_INDEX_MASK 0xf00
8108#define RLC_GPM_PERF_COUNT_0__SH_INDEX__SHIFT 0x8
8109#define RLC_GPM_PERF_COUNT_0__CU_INDEX_MASK 0xf000
8110#define RLC_GPM_PERF_COUNT_0__CU_INDEX__SHIFT 0xc
8111#define RLC_GPM_PERF_COUNT_0__EVENT_SEL_MASK 0x30000
8112#define RLC_GPM_PERF_COUNT_0__EVENT_SEL__SHIFT 0x10
8113#define RLC_GPM_PERF_COUNT_0__UNUSED_MASK 0xc0000
8114#define RLC_GPM_PERF_COUNT_0__UNUSED__SHIFT 0x12
8115#define RLC_GPM_PERF_COUNT_0__ENABLE_MASK 0x100000
8116#define RLC_GPM_PERF_COUNT_0__ENABLE__SHIFT 0x14
8117#define RLC_GPM_PERF_COUNT_0__RESERVED_MASK 0xffe00000
8118#define RLC_GPM_PERF_COUNT_0__RESERVED__SHIFT 0x15
8119#define RLC_GPM_PERF_COUNT_1__FEATURE_SEL_MASK 0xf
8120#define RLC_GPM_PERF_COUNT_1__FEATURE_SEL__SHIFT 0x0
8121#define RLC_GPM_PERF_COUNT_1__SE_INDEX_MASK 0xf0
8122#define RLC_GPM_PERF_COUNT_1__SE_INDEX__SHIFT 0x4
8123#define RLC_GPM_PERF_COUNT_1__SH_INDEX_MASK 0xf00
8124#define RLC_GPM_PERF_COUNT_1__SH_INDEX__SHIFT 0x8
8125#define RLC_GPM_PERF_COUNT_1__CU_INDEX_MASK 0xf000
8126#define RLC_GPM_PERF_COUNT_1__CU_INDEX__SHIFT 0xc
8127#define RLC_GPM_PERF_COUNT_1__EVENT_SEL_MASK 0x30000
8128#define RLC_GPM_PERF_COUNT_1__EVENT_SEL__SHIFT 0x10
8129#define RLC_GPM_PERF_COUNT_1__UNUSED_MASK 0xc0000
8130#define RLC_GPM_PERF_COUNT_1__UNUSED__SHIFT 0x12
8131#define RLC_GPM_PERF_COUNT_1__ENABLE_MASK 0x100000
8132#define RLC_GPM_PERF_COUNT_1__ENABLE__SHIFT 0x14
8133#define RLC_GPM_PERF_COUNT_1__RESERVED_MASK 0xffe00000
8134#define RLC_GPM_PERF_COUNT_1__RESERVED__SHIFT 0x15
8135#define RLC_GPR_REG1__DATA_MASK 0xffffffff
8136#define RLC_GPR_REG1__DATA__SHIFT 0x0
8137#define RLC_GPR_REG2__DATA_MASK 0xffffffff
8138#define RLC_GPR_REG2__DATA__SHIFT 0x0
8139#define RLC_SPM_VMID__RLC_SPM_VMID_MASK 0xf
8140#define RLC_SPM_VMID__RLC_SPM_VMID__SHIFT 0x0
8141#define RLC_SPM_VMID__RESERVED_MASK 0xfffffff0
8142#define RLC_SPM_VMID__RESERVED__SHIFT 0x4
8143#define RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL_MASK 0x1
8144#define RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL__SHIFT 0x0
8145#define RLC_SPM_INT_CNTL__RESERVED_MASK 0xfffffffe
8146#define RLC_SPM_INT_CNTL__RESERVED__SHIFT 0x1
8147#define RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS_MASK 0x1
8148#define RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS__SHIFT 0x0
8149#define RLC_SPM_INT_STATUS__RESERVED_MASK 0xfffffffe
8150#define RLC_SPM_INT_STATUS__RESERVED__SHIFT 0x1
8151#define RLC_SPM_DEBUG_SELECT__SELECT_MASK 0xff
8152#define RLC_SPM_DEBUG_SELECT__SELECT__SHIFT 0x0
8153#define RLC_SPM_DEBUG_SELECT__RESERVED_MASK 0x7f00
8154#define RLC_SPM_DEBUG_SELECT__RESERVED__SHIFT 0x8
8155#define RLC_SPM_DEBUG_SELECT__RLC_SPM_DEBUG_MODE_MASK 0x8000
8156#define RLC_SPM_DEBUG_SELECT__RLC_SPM_DEBUG_MODE__SHIFT 0xf
8157#define RLC_SPM_DEBUG_SELECT__RLC_SPM_NUM_SAMPLE_MASK 0xffff0000
8158#define RLC_SPM_DEBUG_SELECT__RLC_SPM_NUM_SAMPLE__SHIFT 0x10
8159#define RLC_SPM_DEBUG__DATA_MASK 0xffffffff
8160#define RLC_SPM_DEBUG__DATA__SHIFT 0x0
8161#define RLC_GPM_LOG_ADDR__ADDR_MASK 0xffffffff
8162#define RLC_GPM_LOG_ADDR__ADDR__SHIFT 0x0
8163#define RLC_GPM_LOG_SIZE__SIZE_MASK 0xffffffff
8164#define RLC_GPM_LOG_SIZE__SIZE__SHIFT 0x0
8165#define RLC_GPM_LOG_CONT__CONT_MASK 0xffffffff
8166#define RLC_GPM_LOG_CONT__CONT__SHIFT 0x0
8167#define RLC_SPM_PERFMON_CNTL__RESERVED1_MASK 0xfff
8168#define RLC_SPM_PERFMON_CNTL__RESERVED1__SHIFT 0x0
8169#define RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE_MASK 0x3000
8170#define RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE__SHIFT 0xc
8171#define RLC_SPM_PERFMON_CNTL__RESERVED_MASK 0xc000
8172#define RLC_SPM_PERFMON_CNTL__RESERVED__SHIFT 0xe
8173#define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL_MASK 0xffff0000
8174#define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL__SHIFT 0x10
8175#define RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO_MASK 0xffffffff
8176#define RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO__SHIFT 0x0
8177#define RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI_MASK 0xffff
8178#define RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI__SHIFT 0x0
8179#define RLC_SPM_PERFMON_RING_BASE_HI__RESERVED_MASK 0xffff0000
8180#define RLC_SPM_PERFMON_RING_BASE_HI__RESERVED__SHIFT 0x10
8181#define RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE_MASK 0xffffffff
8182#define RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE__SHIFT 0x0
8183#define RLC_SPM_PERFMON_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE_MASK 0xff
8184#define RLC_SPM_PERFMON_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE__SHIFT 0x0
8185#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED1_MASK 0x700
8186#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED1__SHIFT 0x8
8187#define RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_LINE_MASK 0xf800
8188#define RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_LINE__SHIFT 0xb
8189#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE0_NUM_LINE_MASK 0x1f0000
8190#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE0_NUM_LINE__SHIFT 0x10
8191#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE1_NUM_LINE_MASK 0x3e00000
8192#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE1_NUM_LINE__SHIFT 0x15
8193#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE2_NUM_LINE_MASK 0x7c000000
8194#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE2_NUM_LINE__SHIFT 0x1a
8195#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED_MASK 0x80000000
8196#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED__SHIFT 0x1f
8197#define RLC_SPM_SE_MUXSEL_ADDR__PERFMON_SEL_ADDR_MASK 0xffffffff
8198#define RLC_SPM_SE_MUXSEL_ADDR__PERFMON_SEL_ADDR__SHIFT 0x0
8199#define RLC_SPM_SE_MUXSEL_DATA__PERFMON_SEL_DATA_MASK 0xffffffff
8200#define RLC_SPM_SE_MUXSEL_DATA__PERFMON_SEL_DATA__SHIFT 0x0
8201#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
8202#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
8203#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
8204#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
8205#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
8206#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
8207#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
8208#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
8209#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
8210#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
8211#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
8212#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
8213#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
8214#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
8215#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
8216#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
8217#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
8218#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
8219#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
8220#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
8221#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
8222#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
8223#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
8224#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
8225#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
8226#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
8227#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
8228#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
8229#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
8230#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
8231#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
8232#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
8233#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
8234#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
8235#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
8236#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
8237#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
8238#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
8239#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
8240#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
8241#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
8242#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
8243#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
8244#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
8245#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
8246#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
8247#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
8248#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
8249#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
8250#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
8251#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
8252#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
8253#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
8254#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
8255#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
8256#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
8257#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
8258#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
8259#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
8260#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
8261#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
8262#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
8263#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
8264#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
8265#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
8266#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
8267#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
8268#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
8269#define RLC_SPM_TCS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
8270#define RLC_SPM_TCS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
8271#define RLC_SPM_TCS_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
8272#define RLC_SPM_TCS_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
8273#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
8274#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
8275#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
8276#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
8277#define RLC_SPM_GLOBAL_MUXSEL_ADDR__PERFMON_SEL_ADDR_MASK 0xffffffff
8278#define RLC_SPM_GLOBAL_MUXSEL_ADDR__PERFMON_SEL_ADDR__SHIFT 0x0
8279#define RLC_SPM_GLOBAL_MUXSEL_DATA__PERFMON_SEL_DATA_MASK 0xffffffff
8280#define RLC_SPM_GLOBAL_MUXSEL_DATA__PERFMON_SEL_DATA__SHIFT 0x0
8281#define RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR_MASK 0xffffffff
8282#define RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR__SHIFT 0x0
8283#define RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD_MASK 0xffffffff
8284#define RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD__SHIFT 0x0
8285#define RLC_SPM_DBR0_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
8286#define RLC_SPM_DBR0_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
8287#define RLC_SPM_DBR0_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
8288#define RLC_SPM_DBR0_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
8289#define RLC_SPM_DBR1_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
8290#define RLC_SPM_DBR1_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
8291#define RLC_SPM_DBR1_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
8292#define RLC_SPM_DBR1_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
8293#define RLC_SPM_CBR0_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
8294#define RLC_SPM_CBR0_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
8295#define RLC_SPM_CBR0_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
8296#define RLC_SPM_CBR0_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
8297#define RLC_SPM_CBR1_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
8298#define RLC_SPM_CBR1_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
8299#define RLC_SPM_CBR1_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
8300#define RLC_SPM_CBR1_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
8301#define SPI_PS_INPUT_CNTL_0__OFFSET_MASK 0x3f
8302#define SPI_PS_INPUT_CNTL_0__OFFSET__SHIFT 0x0
8303#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_MASK 0x300
8304#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL__SHIFT 0x8
8305#define SPI_PS_INPUT_CNTL_0__FLAT_SHADE_MASK 0x400
8306#define SPI_PS_INPUT_CNTL_0__FLAT_SHADE__SHIFT 0xa
8307#define SPI_PS_INPUT_CNTL_0__CYL_WRAP_MASK 0x1e000
8308#define SPI_PS_INPUT_CNTL_0__CYL_WRAP__SHIFT 0xd
8309#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_MASK 0x20000
8310#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX__SHIFT 0x11
8311#define SPI_PS_INPUT_CNTL_0__DUP_MASK 0x40000
8312#define SPI_PS_INPUT_CNTL_0__DUP__SHIFT 0x12
8313#define SPI_PS_INPUT_CNTL_1__OFFSET_MASK 0x3f
8314#define SPI_PS_INPUT_CNTL_1__OFFSET__SHIFT 0x0
8315#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_MASK 0x300
8316#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL__SHIFT 0x8
8317#define SPI_PS_INPUT_CNTL_1__FLAT_SHADE_MASK 0x400
8318#define SPI_PS_INPUT_CNTL_1__FLAT_SHADE__SHIFT 0xa
8319#define SPI_PS_INPUT_CNTL_1__CYL_WRAP_MASK 0x1e000
8320#define SPI_PS_INPUT_CNTL_1__CYL_WRAP__SHIFT 0xd
8321#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_MASK 0x20000
8322#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX__SHIFT 0x11
8323#define SPI_PS_INPUT_CNTL_1__DUP_MASK 0x40000
8324#define SPI_PS_INPUT_CNTL_1__DUP__SHIFT 0x12
8325#define SPI_PS_INPUT_CNTL_2__OFFSET_MASK 0x3f
8326#define SPI_PS_INPUT_CNTL_2__OFFSET__SHIFT 0x0
8327#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_MASK 0x300
8328#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL__SHIFT 0x8
8329#define SPI_PS_INPUT_CNTL_2__FLAT_SHADE_MASK 0x400
8330#define SPI_PS_INPUT_CNTL_2__FLAT_SHADE__SHIFT 0xa
8331#define SPI_PS_INPUT_CNTL_2__CYL_WRAP_MASK 0x1e000
8332#define SPI_PS_INPUT_CNTL_2__CYL_WRAP__SHIFT 0xd
8333#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_MASK 0x20000
8334#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX__SHIFT 0x11
8335#define SPI_PS_INPUT_CNTL_2__DUP_MASK 0x40000
8336#define SPI_PS_INPUT_CNTL_2__DUP__SHIFT 0x12
8337#define SPI_PS_INPUT_CNTL_3__OFFSET_MASK 0x3f
8338#define SPI_PS_INPUT_CNTL_3__OFFSET__SHIFT 0x0
8339#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_MASK 0x300
8340#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL__SHIFT 0x8
8341#define SPI_PS_INPUT_CNTL_3__FLAT_SHADE_MASK 0x400
8342#define SPI_PS_INPUT_CNTL_3__FLAT_SHADE__SHIFT 0xa
8343#define SPI_PS_INPUT_CNTL_3__CYL_WRAP_MASK 0x1e000
8344#define SPI_PS_INPUT_CNTL_3__CYL_WRAP__SHIFT 0xd
8345#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_MASK 0x20000
8346#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX__SHIFT 0x11
8347#define SPI_PS_INPUT_CNTL_3__DUP_MASK 0x40000
8348#define SPI_PS_INPUT_CNTL_3__DUP__SHIFT 0x12
8349#define SPI_PS_INPUT_CNTL_4__OFFSET_MASK 0x3f
8350#define SPI_PS_INPUT_CNTL_4__OFFSET__SHIFT 0x0
8351#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_MASK 0x300
8352#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL__SHIFT 0x8
8353#define SPI_PS_INPUT_CNTL_4__FLAT_SHADE_MASK 0x400
8354#define SPI_PS_INPUT_CNTL_4__FLAT_SHADE__SHIFT 0xa
8355#define SPI_PS_INPUT_CNTL_4__CYL_WRAP_MASK 0x1e000
8356#define SPI_PS_INPUT_CNTL_4__CYL_WRAP__SHIFT 0xd
8357#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_MASK 0x20000
8358#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX__SHIFT 0x11
8359#define SPI_PS_INPUT_CNTL_4__DUP_MASK 0x40000
8360#define SPI_PS_INPUT_CNTL_4__DUP__SHIFT 0x12
8361#define SPI_PS_INPUT_CNTL_5__OFFSET_MASK 0x3f
8362#define SPI_PS_INPUT_CNTL_5__OFFSET__SHIFT 0x0
8363#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_MASK 0x300
8364#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL__SHIFT 0x8
8365#define SPI_PS_INPUT_CNTL_5__FLAT_SHADE_MASK 0x400
8366#define SPI_PS_INPUT_CNTL_5__FLAT_SHADE__SHIFT 0xa
8367#define SPI_PS_INPUT_CNTL_5__CYL_WRAP_MASK 0x1e000
8368#define SPI_PS_INPUT_CNTL_5__CYL_WRAP__SHIFT 0xd
8369#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_MASK 0x20000
8370#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX__SHIFT 0x11
8371#define SPI_PS_INPUT_CNTL_5__DUP_MASK 0x40000
8372#define SPI_PS_INPUT_CNTL_5__DUP__SHIFT 0x12
8373#define SPI_PS_INPUT_CNTL_6__OFFSET_MASK 0x3f
8374#define SPI_PS_INPUT_CNTL_6__OFFSET__SHIFT 0x0
8375#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_MASK 0x300
8376#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL__SHIFT 0x8
8377#define SPI_PS_INPUT_CNTL_6__FLAT_SHADE_MASK 0x400
8378#define SPI_PS_INPUT_CNTL_6__FLAT_SHADE__SHIFT 0xa
8379#define SPI_PS_INPUT_CNTL_6__CYL_WRAP_MASK 0x1e000
8380#define SPI_PS_INPUT_CNTL_6__CYL_WRAP__SHIFT 0xd
8381#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_MASK 0x20000
8382#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX__SHIFT 0x11
8383#define SPI_PS_INPUT_CNTL_6__DUP_MASK 0x40000
8384#define SPI_PS_INPUT_CNTL_6__DUP__SHIFT 0x12
8385#define SPI_PS_INPUT_CNTL_7__OFFSET_MASK 0x3f
8386#define SPI_PS_INPUT_CNTL_7__OFFSET__SHIFT 0x0
8387#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_MASK 0x300
8388#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL__SHIFT 0x8
8389#define SPI_PS_INPUT_CNTL_7__FLAT_SHADE_MASK 0x400
8390#define SPI_PS_INPUT_CNTL_7__FLAT_SHADE__SHIFT 0xa
8391#define SPI_PS_INPUT_CNTL_7__CYL_WRAP_MASK 0x1e000
8392#define SPI_PS_INPUT_CNTL_7__CYL_WRAP__SHIFT 0xd
8393#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_MASK 0x20000
8394#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX__SHIFT 0x11
8395#define SPI_PS_INPUT_CNTL_7__DUP_MASK 0x40000
8396#define SPI_PS_INPUT_CNTL_7__DUP__SHIFT 0x12
8397#define SPI_PS_INPUT_CNTL_8__OFFSET_MASK 0x3f
8398#define SPI_PS_INPUT_CNTL_8__OFFSET__SHIFT 0x0
8399#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_MASK 0x300
8400#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL__SHIFT 0x8
8401#define SPI_PS_INPUT_CNTL_8__FLAT_SHADE_MASK 0x400
8402#define SPI_PS_INPUT_CNTL_8__FLAT_SHADE__SHIFT 0xa
8403#define SPI_PS_INPUT_CNTL_8__CYL_WRAP_MASK 0x1e000
8404#define SPI_PS_INPUT_CNTL_8__CYL_WRAP__SHIFT 0xd
8405#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_MASK 0x20000
8406#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX__SHIFT 0x11
8407#define SPI_PS_INPUT_CNTL_8__DUP_MASK 0x40000
8408#define SPI_PS_INPUT_CNTL_8__DUP__SHIFT 0x12
8409#define SPI_PS_INPUT_CNTL_9__OFFSET_MASK 0x3f
8410#define SPI_PS_INPUT_CNTL_9__OFFSET__SHIFT 0x0
8411#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_MASK 0x300
8412#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL__SHIFT 0x8
8413#define SPI_PS_INPUT_CNTL_9__FLAT_SHADE_MASK 0x400
8414#define SPI_PS_INPUT_CNTL_9__FLAT_SHADE__SHIFT 0xa
8415#define SPI_PS_INPUT_CNTL_9__CYL_WRAP_MASK 0x1e000
8416#define SPI_PS_INPUT_CNTL_9__CYL_WRAP__SHIFT 0xd
8417#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_MASK 0x20000
8418#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX__SHIFT 0x11
8419#define SPI_PS_INPUT_CNTL_9__DUP_MASK 0x40000
8420#define SPI_PS_INPUT_CNTL_9__DUP__SHIFT 0x12
8421#define SPI_PS_INPUT_CNTL_10__OFFSET_MASK 0x3f
8422#define SPI_PS_INPUT_CNTL_10__OFFSET__SHIFT 0x0
8423#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_MASK 0x300
8424#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL__SHIFT 0x8
8425#define SPI_PS_INPUT_CNTL_10__FLAT_SHADE_MASK 0x400
8426#define SPI_PS_INPUT_CNTL_10__FLAT_SHADE__SHIFT 0xa
8427#define SPI_PS_INPUT_CNTL_10__CYL_WRAP_MASK 0x1e000
8428#define SPI_PS_INPUT_CNTL_10__CYL_WRAP__SHIFT 0xd
8429#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_MASK 0x20000
8430#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX__SHIFT 0x11
8431#define SPI_PS_INPUT_CNTL_10__DUP_MASK 0x40000
8432#define SPI_PS_INPUT_CNTL_10__DUP__SHIFT 0x12
8433#define SPI_PS_INPUT_CNTL_11__OFFSET_MASK 0x3f
8434#define SPI_PS_INPUT_CNTL_11__OFFSET__SHIFT 0x0
8435#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_MASK 0x300
8436#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL__SHIFT 0x8
8437#define SPI_PS_INPUT_CNTL_11__FLAT_SHADE_MASK 0x400
8438#define SPI_PS_INPUT_CNTL_11__FLAT_SHADE__SHIFT 0xa
8439#define SPI_PS_INPUT_CNTL_11__CYL_WRAP_MASK 0x1e000
8440#define SPI_PS_INPUT_CNTL_11__CYL_WRAP__SHIFT 0xd
8441#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_MASK 0x20000
8442#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX__SHIFT 0x11
8443#define SPI_PS_INPUT_CNTL_11__DUP_MASK 0x40000
8444#define SPI_PS_INPUT_CNTL_11__DUP__SHIFT 0x12
8445#define SPI_PS_INPUT_CNTL_12__OFFSET_MASK 0x3f
8446#define SPI_PS_INPUT_CNTL_12__OFFSET__SHIFT 0x0
8447#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_MASK 0x300
8448#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL__SHIFT 0x8
8449#define SPI_PS_INPUT_CNTL_12__FLAT_SHADE_MASK 0x400
8450#define SPI_PS_INPUT_CNTL_12__FLAT_SHADE__SHIFT 0xa
8451#define SPI_PS_INPUT_CNTL_12__CYL_WRAP_MASK 0x1e000
8452#define SPI_PS_INPUT_CNTL_12__CYL_WRAP__SHIFT 0xd
8453#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_MASK 0x20000
8454#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX__SHIFT 0x11
8455#define SPI_PS_INPUT_CNTL_12__DUP_MASK 0x40000
8456#define SPI_PS_INPUT_CNTL_12__DUP__SHIFT 0x12
8457#define SPI_PS_INPUT_CNTL_13__OFFSET_MASK 0x3f
8458#define SPI_PS_INPUT_CNTL_13__OFFSET__SHIFT 0x0
8459#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_MASK 0x300
8460#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL__SHIFT 0x8
8461#define SPI_PS_INPUT_CNTL_13__FLAT_SHADE_MASK 0x400
8462#define SPI_PS_INPUT_CNTL_13__FLAT_SHADE__SHIFT 0xa
8463#define SPI_PS_INPUT_CNTL_13__CYL_WRAP_MASK 0x1e000
8464#define SPI_PS_INPUT_CNTL_13__CYL_WRAP__SHIFT 0xd
8465#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_MASK 0x20000
8466#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX__SHIFT 0x11
8467#define SPI_PS_INPUT_CNTL_13__DUP_MASK 0x40000
8468#define SPI_PS_INPUT_CNTL_13__DUP__SHIFT 0x12
8469#define SPI_PS_INPUT_CNTL_14__OFFSET_MASK 0x3f
8470#define SPI_PS_INPUT_CNTL_14__OFFSET__SHIFT 0x0
8471#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_MASK 0x300
8472#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL__SHIFT 0x8
8473#define SPI_PS_INPUT_CNTL_14__FLAT_SHADE_MASK 0x400
8474#define SPI_PS_INPUT_CNTL_14__FLAT_SHADE__SHIFT 0xa
8475#define SPI_PS_INPUT_CNTL_14__CYL_WRAP_MASK 0x1e000
8476#define SPI_PS_INPUT_CNTL_14__CYL_WRAP__SHIFT 0xd
8477#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_MASK 0x20000
8478#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX__SHIFT 0x11
8479#define SPI_PS_INPUT_CNTL_14__DUP_MASK 0x40000
8480#define SPI_PS_INPUT_CNTL_14__DUP__SHIFT 0x12
8481#define SPI_PS_INPUT_CNTL_15__OFFSET_MASK 0x3f
8482#define SPI_PS_INPUT_CNTL_15__OFFSET__SHIFT 0x0
8483#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_MASK 0x300
8484#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL__SHIFT 0x8
8485#define SPI_PS_INPUT_CNTL_15__FLAT_SHADE_MASK 0x400
8486#define SPI_PS_INPUT_CNTL_15__FLAT_SHADE__SHIFT 0xa
8487#define SPI_PS_INPUT_CNTL_15__CYL_WRAP_MASK 0x1e000
8488#define SPI_PS_INPUT_CNTL_15__CYL_WRAP__SHIFT 0xd
8489#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_MASK 0x20000
8490#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX__SHIFT 0x11
8491#define SPI_PS_INPUT_CNTL_15__DUP_MASK 0x40000
8492#define SPI_PS_INPUT_CNTL_15__DUP__SHIFT 0x12
8493#define SPI_PS_INPUT_CNTL_16__OFFSET_MASK 0x3f
8494#define SPI_PS_INPUT_CNTL_16__OFFSET__SHIFT 0x0
8495#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_MASK 0x300
8496#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL__SHIFT 0x8
8497#define SPI_PS_INPUT_CNTL_16__FLAT_SHADE_MASK 0x400
8498#define SPI_PS_INPUT_CNTL_16__FLAT_SHADE__SHIFT 0xa
8499#define SPI_PS_INPUT_CNTL_16__CYL_WRAP_MASK 0x1e000
8500#define SPI_PS_INPUT_CNTL_16__CYL_WRAP__SHIFT 0xd
8501#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_MASK 0x20000
8502#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX__SHIFT 0x11
8503#define SPI_PS_INPUT_CNTL_16__DUP_MASK 0x40000
8504#define SPI_PS_INPUT_CNTL_16__DUP__SHIFT 0x12
8505#define SPI_PS_INPUT_CNTL_17__OFFSET_MASK 0x3f
8506#define SPI_PS_INPUT_CNTL_17__OFFSET__SHIFT 0x0
8507#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_MASK 0x300
8508#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL__SHIFT 0x8
8509#define SPI_PS_INPUT_CNTL_17__FLAT_SHADE_MASK 0x400
8510#define SPI_PS_INPUT_CNTL_17__FLAT_SHADE__SHIFT 0xa
8511#define SPI_PS_INPUT_CNTL_17__CYL_WRAP_MASK 0x1e000
8512#define SPI_PS_INPUT_CNTL_17__CYL_WRAP__SHIFT 0xd
8513#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_MASK 0x20000
8514#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX__SHIFT 0x11
8515#define SPI_PS_INPUT_CNTL_17__DUP_MASK 0x40000
8516#define SPI_PS_INPUT_CNTL_17__DUP__SHIFT 0x12
8517#define SPI_PS_INPUT_CNTL_18__OFFSET_MASK 0x3f
8518#define SPI_PS_INPUT_CNTL_18__OFFSET__SHIFT 0x0
8519#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_MASK 0x300
8520#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL__SHIFT 0x8
8521#define SPI_PS_INPUT_CNTL_18__FLAT_SHADE_MASK 0x400
8522#define SPI_PS_INPUT_CNTL_18__FLAT_SHADE__SHIFT 0xa
8523#define SPI_PS_INPUT_CNTL_18__CYL_WRAP_MASK 0x1e000
8524#define SPI_PS_INPUT_CNTL_18__CYL_WRAP__SHIFT 0xd
8525#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_MASK 0x20000
8526#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX__SHIFT 0x11
8527#define SPI_PS_INPUT_CNTL_18__DUP_MASK 0x40000
8528#define SPI_PS_INPUT_CNTL_18__DUP__SHIFT 0x12
8529#define SPI_PS_INPUT_CNTL_19__OFFSET_MASK 0x3f
8530#define SPI_PS_INPUT_CNTL_19__OFFSET__SHIFT 0x0
8531#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_MASK 0x300
8532#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL__SHIFT 0x8
8533#define SPI_PS_INPUT_CNTL_19__FLAT_SHADE_MASK 0x400
8534#define SPI_PS_INPUT_CNTL_19__FLAT_SHADE__SHIFT 0xa
8535#define SPI_PS_INPUT_CNTL_19__CYL_WRAP_MASK 0x1e000
8536#define SPI_PS_INPUT_CNTL_19__CYL_WRAP__SHIFT 0xd
8537#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_MASK 0x20000
8538#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX__SHIFT 0x11
8539#define SPI_PS_INPUT_CNTL_19__DUP_MASK 0x40000
8540#define SPI_PS_INPUT_CNTL_19__DUP__SHIFT 0x12
8541#define SPI_PS_INPUT_CNTL_20__OFFSET_MASK 0x3f
8542#define SPI_PS_INPUT_CNTL_20__OFFSET__SHIFT 0x0
8543#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_MASK 0x300
8544#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL__SHIFT 0x8
8545#define SPI_PS_INPUT_CNTL_20__FLAT_SHADE_MASK 0x400
8546#define SPI_PS_INPUT_CNTL_20__FLAT_SHADE__SHIFT 0xa
8547#define SPI_PS_INPUT_CNTL_20__DUP_MASK 0x40000
8548#define SPI_PS_INPUT_CNTL_20__DUP__SHIFT 0x12
8549#define SPI_PS_INPUT_CNTL_21__OFFSET_MASK 0x3f
8550#define SPI_PS_INPUT_CNTL_21__OFFSET__SHIFT 0x0
8551#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_MASK 0x300
8552#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL__SHIFT 0x8
8553#define SPI_PS_INPUT_CNTL_21__FLAT_SHADE_MASK 0x400
8554#define SPI_PS_INPUT_CNTL_21__FLAT_SHADE__SHIFT 0xa
8555#define SPI_PS_INPUT_CNTL_21__DUP_MASK 0x40000
8556#define SPI_PS_INPUT_CNTL_21__DUP__SHIFT 0x12
8557#define SPI_PS_INPUT_CNTL_22__OFFSET_MASK 0x3f
8558#define SPI_PS_INPUT_CNTL_22__OFFSET__SHIFT 0x0
8559#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_MASK 0x300
8560#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL__SHIFT 0x8
8561#define SPI_PS_INPUT_CNTL_22__FLAT_SHADE_MASK 0x400
8562#define SPI_PS_INPUT_CNTL_22__FLAT_SHADE__SHIFT 0xa
8563#define SPI_PS_INPUT_CNTL_22__DUP_MASK 0x40000
8564#define SPI_PS_INPUT_CNTL_22__DUP__SHIFT 0x12
8565#define SPI_PS_INPUT_CNTL_23__OFFSET_MASK 0x3f
8566#define SPI_PS_INPUT_CNTL_23__OFFSET__SHIFT 0x0
8567#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_MASK 0x300
8568#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL__SHIFT 0x8
8569#define SPI_PS_INPUT_CNTL_23__FLAT_SHADE_MASK 0x400
8570#define SPI_PS_INPUT_CNTL_23__FLAT_SHADE__SHIFT 0xa
8571#define SPI_PS_INPUT_CNTL_23__DUP_MASK 0x40000
8572#define SPI_PS_INPUT_CNTL_23__DUP__SHIFT 0x12
8573#define SPI_PS_INPUT_CNTL_24__OFFSET_MASK 0x3f
8574#define SPI_PS_INPUT_CNTL_24__OFFSET__SHIFT 0x0
8575#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_MASK 0x300
8576#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL__SHIFT 0x8
8577#define SPI_PS_INPUT_CNTL_24__FLAT_SHADE_MASK 0x400
8578#define SPI_PS_INPUT_CNTL_24__FLAT_SHADE__SHIFT 0xa
8579#define SPI_PS_INPUT_CNTL_24__DUP_MASK 0x40000
8580#define SPI_PS_INPUT_CNTL_24__DUP__SHIFT 0x12
8581#define SPI_PS_INPUT_CNTL_25__OFFSET_MASK 0x3f
8582#define SPI_PS_INPUT_CNTL_25__OFFSET__SHIFT 0x0
8583#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_MASK 0x300
8584#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL__SHIFT 0x8
8585#define SPI_PS_INPUT_CNTL_25__FLAT_SHADE_MASK 0x400
8586#define SPI_PS_INPUT_CNTL_25__FLAT_SHADE__SHIFT 0xa
8587#define SPI_PS_INPUT_CNTL_25__DUP_MASK 0x40000
8588#define SPI_PS_INPUT_CNTL_25__DUP__SHIFT 0x12
8589#define SPI_PS_INPUT_CNTL_26__OFFSET_MASK 0x3f
8590#define SPI_PS_INPUT_CNTL_26__OFFSET__SHIFT 0x0
8591#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_MASK 0x300
8592#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL__SHIFT 0x8
8593#define SPI_PS_INPUT_CNTL_26__FLAT_SHADE_MASK 0x400
8594#define SPI_PS_INPUT_CNTL_26__FLAT_SHADE__SHIFT 0xa
8595#define SPI_PS_INPUT_CNTL_26__DUP_MASK 0x40000
8596#define SPI_PS_INPUT_CNTL_26__DUP__SHIFT 0x12
8597#define SPI_PS_INPUT_CNTL_27__OFFSET_MASK 0x3f
8598#define SPI_PS_INPUT_CNTL_27__OFFSET__SHIFT 0x0
8599#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_MASK 0x300
8600#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL__SHIFT 0x8
8601#define SPI_PS_INPUT_CNTL_27__FLAT_SHADE_MASK 0x400
8602#define SPI_PS_INPUT_CNTL_27__FLAT_SHADE__SHIFT 0xa
8603#define SPI_PS_INPUT_CNTL_27__DUP_MASK 0x40000
8604#define SPI_PS_INPUT_CNTL_27__DUP__SHIFT 0x12
8605#define SPI_PS_INPUT_CNTL_28__OFFSET_MASK 0x3f
8606#define SPI_PS_INPUT_CNTL_28__OFFSET__SHIFT 0x0
8607#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_MASK 0x300
8608#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL__SHIFT 0x8
8609#define SPI_PS_INPUT_CNTL_28__FLAT_SHADE_MASK 0x400
8610#define SPI_PS_INPUT_CNTL_28__FLAT_SHADE__SHIFT 0xa
8611#define SPI_PS_INPUT_CNTL_28__DUP_MASK 0x40000
8612#define SPI_PS_INPUT_CNTL_28__DUP__SHIFT 0x12
8613#define SPI_PS_INPUT_CNTL_29__OFFSET_MASK 0x3f
8614#define SPI_PS_INPUT_CNTL_29__OFFSET__SHIFT 0x0
8615#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_MASK 0x300
8616#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL__SHIFT 0x8
8617#define SPI_PS_INPUT_CNTL_29__FLAT_SHADE_MASK 0x400
8618#define SPI_PS_INPUT_CNTL_29__FLAT_SHADE__SHIFT 0xa
8619#define SPI_PS_INPUT_CNTL_29__DUP_MASK 0x40000
8620#define SPI_PS_INPUT_CNTL_29__DUP__SHIFT 0x12
8621#define SPI_PS_INPUT_CNTL_30__OFFSET_MASK 0x3f
8622#define SPI_PS_INPUT_CNTL_30__OFFSET__SHIFT 0x0
8623#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_MASK 0x300
8624#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL__SHIFT 0x8
8625#define SPI_PS_INPUT_CNTL_30__FLAT_SHADE_MASK 0x400
8626#define SPI_PS_INPUT_CNTL_30__FLAT_SHADE__SHIFT 0xa
8627#define SPI_PS_INPUT_CNTL_30__DUP_MASK 0x40000
8628#define SPI_PS_INPUT_CNTL_30__DUP__SHIFT 0x12
8629#define SPI_PS_INPUT_CNTL_31__OFFSET_MASK 0x3f
8630#define SPI_PS_INPUT_CNTL_31__OFFSET__SHIFT 0x0
8631#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_MASK 0x300
8632#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL__SHIFT 0x8
8633#define SPI_PS_INPUT_CNTL_31__FLAT_SHADE_MASK 0x400
8634#define SPI_PS_INPUT_CNTL_31__FLAT_SHADE__SHIFT 0xa
8635#define SPI_PS_INPUT_CNTL_31__DUP_MASK 0x40000
8636#define SPI_PS_INPUT_CNTL_31__DUP__SHIFT 0x12
8637#define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT_MASK 0x3e
8638#define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT__SHIFT 0x1
8639#define SPI_VS_OUT_CONFIG__VS_HALF_PACK_MASK 0x40
8640#define SPI_VS_OUT_CONFIG__VS_HALF_PACK__SHIFT 0x6
8641#define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA_MASK 0x1
8642#define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA__SHIFT 0x0
8643#define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA_MASK 0x2
8644#define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA__SHIFT 0x1
8645#define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA_MASK 0x4
8646#define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA__SHIFT 0x2
8647#define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA_MASK 0x8
8648#define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA__SHIFT 0x3
8649#define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA_MASK 0x10
8650#define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA__SHIFT 0x4
8651#define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA_MASK 0x20
8652#define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA__SHIFT 0x5
8653#define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA_MASK 0x40
8654#define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA__SHIFT 0x6
8655#define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA_MASK 0x80
8656#define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA__SHIFT 0x7
8657#define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA_MASK 0x100
8658#define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA__SHIFT 0x8
8659#define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA_MASK 0x200
8660#define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA__SHIFT 0x9
8661#define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA_MASK 0x400
8662#define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA__SHIFT 0xa
8663#define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA_MASK 0x800
8664#define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA__SHIFT 0xb
8665#define SPI_PS_INPUT_ENA__FRONT_FACE_ENA_MASK 0x1000
8666#define SPI_PS_INPUT_ENA__FRONT_FACE_ENA__SHIFT 0xc
8667#define SPI_PS_INPUT_ENA__ANCILLARY_ENA_MASK 0x2000
8668#define SPI_PS_INPUT_ENA__ANCILLARY_ENA__SHIFT 0xd
8669#define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA_MASK 0x4000
8670#define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA__SHIFT 0xe
8671#define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA_MASK 0x8000
8672#define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA__SHIFT 0xf
8673#define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA_MASK 0x1
8674#define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA__SHIFT 0x0
8675#define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA_MASK 0x2
8676#define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA__SHIFT 0x1
8677#define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA_MASK 0x4
8678#define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA__SHIFT 0x2
8679#define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA_MASK 0x8
8680#define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA__SHIFT 0x3
8681#define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA_MASK 0x10
8682#define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA__SHIFT 0x4
8683#define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA_MASK 0x20
8684#define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA__SHIFT 0x5
8685#define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA_MASK 0x40
8686#define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA__SHIFT 0x6
8687#define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA_MASK 0x80
8688#define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA__SHIFT 0x7
8689#define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA_MASK 0x100
8690#define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA__SHIFT 0x8
8691#define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA_MASK 0x200
8692#define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA__SHIFT 0x9
8693#define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA_MASK 0x400
8694#define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA__SHIFT 0xa
8695#define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA_MASK 0x800
8696#define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA__SHIFT 0xb
8697#define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA_MASK 0x1000
8698#define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA__SHIFT 0xc
8699#define SPI_PS_INPUT_ADDR__ANCILLARY_ENA_MASK 0x2000
8700#define SPI_PS_INPUT_ADDR__ANCILLARY_ENA__SHIFT 0xd
8701#define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA_MASK 0x4000
8702#define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA__SHIFT 0xe
8703#define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA_MASK 0x8000
8704#define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA__SHIFT 0xf
8705#define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA_MASK 0x1
8706#define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA__SHIFT 0x0
8707#define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA_MASK 0x2
8708#define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA__SHIFT 0x1
8709#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X_MASK 0x1c
8710#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X__SHIFT 0x2
8711#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y_MASK 0xe0
8712#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y__SHIFT 0x5
8713#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z_MASK 0x700
8714#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z__SHIFT 0x8
8715#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W_MASK 0x3800
8716#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W__SHIFT 0xb
8717#define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1_MASK 0x4000
8718#define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1__SHIFT 0xe
8719#define SPI_PS_IN_CONTROL__NUM_INTERP_MASK 0x3f
8720#define SPI_PS_IN_CONTROL__NUM_INTERP__SHIFT 0x0
8721#define SPI_PS_IN_CONTROL__PARAM_GEN_MASK 0x40
8722#define SPI_PS_IN_CONTROL__PARAM_GEN__SHIFT 0x6
8723#define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE_MASK 0x4000
8724#define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE__SHIFT 0xe
8725#define SPI_BARYC_CNTL__PERSP_CENTER_CNTL_MASK 0x1
8726#define SPI_BARYC_CNTL__PERSP_CENTER_CNTL__SHIFT 0x0
8727#define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL_MASK 0x10
8728#define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL__SHIFT 0x4
8729#define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL_MASK 0x100
8730#define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL__SHIFT 0x8
8731#define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL_MASK 0x1000
8732#define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL__SHIFT 0xc
8733#define SPI_BARYC_CNTL__POS_FLOAT_LOCATION_MASK 0x30000
8734#define SPI_BARYC_CNTL__POS_FLOAT_LOCATION__SHIFT 0x10
8735#define SPI_BARYC_CNTL__POS_FLOAT_ULC_MASK 0x100000
8736#define SPI_BARYC_CNTL__POS_FLOAT_ULC__SHIFT 0x14
8737#define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS_MASK 0x1000000
8738#define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS__SHIFT 0x18
8739#define SPI_TMPRING_SIZE__WAVES_MASK 0xfff
8740#define SPI_TMPRING_SIZE__WAVES__SHIFT 0x0
8741#define SPI_TMPRING_SIZE__WAVESIZE_MASK 0x1fff000
8742#define SPI_TMPRING_SIZE__WAVESIZE__SHIFT 0xc
8743#define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT_MASK 0xf
8744#define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT__SHIFT 0x0
8745#define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT_MASK 0xf0
8746#define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT__SHIFT 0x4
8747#define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT_MASK 0xf00
8748#define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT__SHIFT 0x8
8749#define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT_MASK 0xf000
8750#define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT__SHIFT 0xc
8751#define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT_MASK 0xf
8752#define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT__SHIFT 0x0
8753#define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT_MASK 0xf
8754#define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT__SHIFT 0x0
8755#define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT_MASK 0xf0
8756#define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT__SHIFT 0x4
8757#define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT_MASK 0xf00
8758#define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT__SHIFT 0x8
8759#define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT_MASK 0xf000
8760#define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT__SHIFT 0xc
8761#define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT_MASK 0xf0000
8762#define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT__SHIFT 0x10
8763#define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT_MASK 0xf00000
8764#define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT__SHIFT 0x14
8765#define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT_MASK 0xf000000
8766#define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT__SHIFT 0x18
8767#define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT_MASK 0xf0000000
8768#define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT__SHIFT 0x1c
8769#define SPI_ARB_PRIORITY__PIPE_ORDER_TS0_MASK 0x7
8770#define SPI_ARB_PRIORITY__PIPE_ORDER_TS0__SHIFT 0x0
8771#define SPI_ARB_PRIORITY__PIPE_ORDER_TS1_MASK 0x38
8772#define SPI_ARB_PRIORITY__PIPE_ORDER_TS1__SHIFT 0x3
8773#define SPI_ARB_PRIORITY__PIPE_ORDER_TS2_MASK 0x1c0
8774#define SPI_ARB_PRIORITY__PIPE_ORDER_TS2__SHIFT 0x6
8775#define SPI_ARB_PRIORITY__PIPE_ORDER_TS3_MASK 0xe00
8776#define SPI_ARB_PRIORITY__PIPE_ORDER_TS3__SHIFT 0x9
8777#define SPI_ARB_PRIORITY__TS0_DUR_MULT_MASK 0x3000
8778#define SPI_ARB_PRIORITY__TS0_DUR_MULT__SHIFT 0xc
8779#define SPI_ARB_PRIORITY__TS1_DUR_MULT_MASK 0xc000
8780#define SPI_ARB_PRIORITY__TS1_DUR_MULT__SHIFT 0xe
8781#define SPI_ARB_PRIORITY__TS2_DUR_MULT_MASK 0x30000
8782#define SPI_ARB_PRIORITY__TS2_DUR_MULT__SHIFT 0x10
8783#define SPI_ARB_PRIORITY__TS3_DUR_MULT_MASK 0xc0000
8784#define SPI_ARB_PRIORITY__TS3_DUR_MULT__SHIFT 0x12
8785#define SPI_ARB_CYCLES_0__TS0_DURATION_MASK 0xffff
8786#define SPI_ARB_CYCLES_0__TS0_DURATION__SHIFT 0x0
8787#define SPI_ARB_CYCLES_0__TS1_DURATION_MASK 0xffff0000
8788#define SPI_ARB_CYCLES_0__TS1_DURATION__SHIFT 0x10
8789#define SPI_ARB_CYCLES_1__TS2_DURATION_MASK 0xffff
8790#define SPI_ARB_CYCLES_1__TS2_DURATION__SHIFT 0x0
8791#define SPI_ARB_CYCLES_1__TS3_DURATION_MASK 0xffff0000
8792#define SPI_ARB_CYCLES_1__TS3_DURATION__SHIFT 0x10
8793#define SPI_CDBG_SYS_GFX__PS_EN_MASK 0x1
8794#define SPI_CDBG_SYS_GFX__PS_EN__SHIFT 0x0
8795#define SPI_CDBG_SYS_GFX__VS_EN_MASK 0x2
8796#define SPI_CDBG_SYS_GFX__VS_EN__SHIFT 0x1
8797#define SPI_CDBG_SYS_GFX__GS_EN_MASK 0x4
8798#define SPI_CDBG_SYS_GFX__GS_EN__SHIFT 0x2
8799#define SPI_CDBG_SYS_GFX__ES_EN_MASK 0x8
8800#define SPI_CDBG_SYS_GFX__ES_EN__SHIFT 0x3
8801#define SPI_CDBG_SYS_GFX__HS_EN_MASK 0x10
8802#define SPI_CDBG_SYS_GFX__HS_EN__SHIFT 0x4
8803#define SPI_CDBG_SYS_GFX__LS_EN_MASK 0x20
8804#define SPI_CDBG_SYS_GFX__LS_EN__SHIFT 0x5
8805#define SPI_CDBG_SYS_GFX__CS_EN_MASK 0x40
8806#define SPI_CDBG_SYS_GFX__CS_EN__SHIFT 0x6
8807#define SPI_CDBG_SYS_HP3D__PS_EN_MASK 0x1
8808#define SPI_CDBG_SYS_HP3D__PS_EN__SHIFT 0x0
8809#define SPI_CDBG_SYS_HP3D__VS_EN_MASK 0x2
8810#define SPI_CDBG_SYS_HP3D__VS_EN__SHIFT 0x1
8811#define SPI_CDBG_SYS_HP3D__GS_EN_MASK 0x4
8812#define SPI_CDBG_SYS_HP3D__GS_EN__SHIFT 0x2
8813#define SPI_CDBG_SYS_HP3D__ES_EN_MASK 0x8
8814#define SPI_CDBG_SYS_HP3D__ES_EN__SHIFT 0x3
8815#define SPI_CDBG_SYS_HP3D__HS_EN_MASK 0x10
8816#define SPI_CDBG_SYS_HP3D__HS_EN__SHIFT 0x4
8817#define SPI_CDBG_SYS_HP3D__LS_EN_MASK 0x20
8818#define SPI_CDBG_SYS_HP3D__LS_EN__SHIFT 0x5
8819#define SPI_CDBG_SYS_CS0__PIPE0_MASK 0xff
8820#define SPI_CDBG_SYS_CS0__PIPE0__SHIFT 0x0
8821#define SPI_CDBG_SYS_CS0__PIPE1_MASK 0xff00
8822#define SPI_CDBG_SYS_CS0__PIPE1__SHIFT 0x8
8823#define SPI_CDBG_SYS_CS0__PIPE2_MASK 0xff0000
8824#define SPI_CDBG_SYS_CS0__PIPE2__SHIFT 0x10
8825#define SPI_CDBG_SYS_CS0__PIPE3_MASK 0xff000000
8826#define SPI_CDBG_SYS_CS0__PIPE3__SHIFT 0x18
8827#define SPI_CDBG_SYS_CS1__PIPE0_MASK 0xff
8828#define SPI_CDBG_SYS_CS1__PIPE0__SHIFT 0x0
8829#define SPI_CDBG_SYS_CS1__PIPE1_MASK 0xff00
8830#define SPI_CDBG_SYS_CS1__PIPE1__SHIFT 0x8
8831#define SPI_CDBG_SYS_CS1__PIPE2_MASK 0xff0000
8832#define SPI_CDBG_SYS_CS1__PIPE2__SHIFT 0x10
8833#define SPI_CDBG_SYS_CS1__PIPE3_MASK 0xff000000
8834#define SPI_CDBG_SYS_CS1__PIPE3__SHIFT 0x18
8835#define SPI_WCL_PIPE_PERCENT_GFX__VALUE_MASK 0x1f
8836#define SPI_WCL_PIPE_PERCENT_GFX__VALUE__SHIFT 0x0
8837#define SPI_WCL_PIPE_PERCENT_HP3D__VALUE_MASK 0x1f
8838#define SPI_WCL_PIPE_PERCENT_HP3D__VALUE__SHIFT 0x0
8839#define SPI_WCL_PIPE_PERCENT_CS0__VALUE_MASK 0x1f
8840#define SPI_WCL_PIPE_PERCENT_CS0__VALUE__SHIFT 0x0
8841#define SPI_WCL_PIPE_PERCENT_CS1__VALUE_MASK 0x1f
8842#define SPI_WCL_PIPE_PERCENT_CS1__VALUE__SHIFT 0x0
8843#define SPI_WCL_PIPE_PERCENT_CS2__VALUE_MASK 0x1f
8844#define SPI_WCL_PIPE_PERCENT_CS2__VALUE__SHIFT 0x0
8845#define SPI_WCL_PIPE_PERCENT_CS3__VALUE_MASK 0x1f
8846#define SPI_WCL_PIPE_PERCENT_CS3__VALUE__SHIFT 0x0
8847#define SPI_WCL_PIPE_PERCENT_CS4__VALUE_MASK 0x1f
8848#define SPI_WCL_PIPE_PERCENT_CS4__VALUE__SHIFT 0x0
8849#define SPI_WCL_PIPE_PERCENT_CS5__VALUE_MASK 0x1f
8850#define SPI_WCL_PIPE_PERCENT_CS5__VALUE__SHIFT 0x0
8851#define SPI_WCL_PIPE_PERCENT_CS6__VALUE_MASK 0x1f
8852#define SPI_WCL_PIPE_PERCENT_CS6__VALUE__SHIFT 0x0
8853#define SPI_WCL_PIPE_PERCENT_CS7__VALUE_MASK 0x1f
8854#define SPI_WCL_PIPE_PERCENT_CS7__VALUE__SHIFT 0x0
8855#define SPI_GDBG_WAVE_CNTL__STALL_RA_MASK 0x1
8856#define SPI_GDBG_WAVE_CNTL__STALL_RA__SHIFT 0x0
8857#define SPI_GDBG_TRAP_CONFIG__ME_SEL_MASK 0x3
8858#define SPI_GDBG_TRAP_CONFIG__ME_SEL__SHIFT 0x0
8859#define SPI_GDBG_TRAP_CONFIG__PIPE_SEL_MASK 0xc
8860#define SPI_GDBG_TRAP_CONFIG__PIPE_SEL__SHIFT 0x2
8861#define SPI_GDBG_TRAP_CONFIG__QUEUE_SEL_MASK 0x70
8862#define SPI_GDBG_TRAP_CONFIG__QUEUE_SEL__SHIFT 0x4
8863#define SPI_GDBG_TRAP_CONFIG__ME_MATCH_MASK 0x80
8864#define SPI_GDBG_TRAP_CONFIG__ME_MATCH__SHIFT 0x7
8865#define SPI_GDBG_TRAP_CONFIG__PIPE_MATCH_MASK 0x100
8866#define SPI_GDBG_TRAP_CONFIG__PIPE_MATCH__SHIFT 0x8
8867#define SPI_GDBG_TRAP_CONFIG__QUEUE_MATCH_MASK 0x200
8868#define SPI_GDBG_TRAP_CONFIG__QUEUE_MATCH__SHIFT 0x9
8869#define SPI_GDBG_TRAP_CONFIG__TRAP_EN_MASK 0x8000
8870#define SPI_GDBG_TRAP_CONFIG__TRAP_EN__SHIFT 0xf
8871#define SPI_GDBG_TRAP_CONFIG__VMID_SEL_MASK 0xffff0000
8872#define SPI_GDBG_TRAP_CONFIG__VMID_SEL__SHIFT 0x10
8873#define SPI_GDBG_TRAP_MASK__EXCP_EN_MASK 0x1ff
8874#define SPI_GDBG_TRAP_MASK__EXCP_EN__SHIFT 0x0
8875#define SPI_GDBG_TRAP_MASK__REPLACE_MASK 0x200
8876#define SPI_GDBG_TRAP_MASK__REPLACE__SHIFT 0x9
8877#define SPI_GDBG_TBA_LO__MEM_BASE_MASK 0xffffffff
8878#define SPI_GDBG_TBA_LO__MEM_BASE__SHIFT 0x0
8879#define SPI_GDBG_TBA_HI__MEM_BASE_MASK 0xff
8880#define SPI_GDBG_TBA_HI__MEM_BASE__SHIFT 0x0
8881#define SPI_GDBG_TMA_LO__MEM_BASE_MASK 0xffffffff
8882#define SPI_GDBG_TMA_LO__MEM_BASE__SHIFT 0x0
8883#define SPI_GDBG_TMA_HI__MEM_BASE_MASK 0xff
8884#define SPI_GDBG_TMA_HI__MEM_BASE__SHIFT 0x0
8885#define SPI_GDBG_TRAP_DATA0__DATA_MASK 0xffffffff
8886#define SPI_GDBG_TRAP_DATA0__DATA__SHIFT 0x0
8887#define SPI_GDBG_TRAP_DATA1__DATA_MASK 0xffffffff
8888#define SPI_GDBG_TRAP_DATA1__DATA__SHIFT 0x0
8889#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_MASK 0x1
8890#define SPI_RESET_DEBUG__DISABLE_GFX_RESET__SHIFT 0x0
8891#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PER_VMID_MASK 0x2
8892#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PER_VMID__SHIFT 0x1
8893#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_ALL_VMID_MASK 0x4
8894#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_ALL_VMID__SHIFT 0x2
8895#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_RESOURCE_MASK 0x8
8896#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_RESOURCE__SHIFT 0x3
8897#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PRIORITY_MASK 0x10
8898#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PRIORITY__SHIFT 0x4
8899#define SPI_COMPUTE_QUEUE_RESET__RESET_MASK 0x1
8900#define SPI_COMPUTE_QUEUE_RESET__RESET__SHIFT 0x0
8901#define SPI_RESOURCE_RESERVE_CU_0__VGPR_MASK 0xf
8902#define SPI_RESOURCE_RESERVE_CU_0__VGPR__SHIFT 0x0
8903#define SPI_RESOURCE_RESERVE_CU_0__SGPR_MASK 0xf0
8904#define SPI_RESOURCE_RESERVE_CU_0__SGPR__SHIFT 0x4
8905#define SPI_RESOURCE_RESERVE_CU_0__LDS_MASK 0xf00
8906#define SPI_RESOURCE_RESERVE_CU_0__LDS__SHIFT 0x8
8907#define SPI_RESOURCE_RESERVE_CU_0__WAVES_MASK 0x7000
8908#define SPI_RESOURCE_RESERVE_CU_0__WAVES__SHIFT 0xc
8909#define SPI_RESOURCE_RESERVE_CU_0__BARRIERS_MASK 0x78000
8910#define SPI_RESOURCE_RESERVE_CU_0__BARRIERS__SHIFT 0xf
8911#define SPI_RESOURCE_RESERVE_CU_1__VGPR_MASK 0xf
8912#define SPI_RESOURCE_RESERVE_CU_1__VGPR__SHIFT 0x0
8913#define SPI_RESOURCE_RESERVE_CU_1__SGPR_MASK 0xf0
8914#define SPI_RESOURCE_RESERVE_CU_1__SGPR__SHIFT 0x4
8915#define SPI_RESOURCE_RESERVE_CU_1__LDS_MASK 0xf00
8916#define SPI_RESOURCE_RESERVE_CU_1__LDS__SHIFT 0x8
8917#define SPI_RESOURCE_RESERVE_CU_1__WAVES_MASK 0x7000
8918#define SPI_RESOURCE_RESERVE_CU_1__WAVES__SHIFT 0xc
8919#define SPI_RESOURCE_RESERVE_CU_1__BARRIERS_MASK 0x78000
8920#define SPI_RESOURCE_RESERVE_CU_1__BARRIERS__SHIFT 0xf
8921#define SPI_RESOURCE_RESERVE_CU_2__VGPR_MASK 0xf
8922#define SPI_RESOURCE_RESERVE_CU_2__VGPR__SHIFT 0x0
8923#define SPI_RESOURCE_RESERVE_CU_2__SGPR_MASK 0xf0
8924#define SPI_RESOURCE_RESERVE_CU_2__SGPR__SHIFT 0x4
8925#define SPI_RESOURCE_RESERVE_CU_2__LDS_MASK 0xf00
8926#define SPI_RESOURCE_RESERVE_CU_2__LDS__SHIFT 0x8
8927#define SPI_RESOURCE_RESERVE_CU_2__WAVES_MASK 0x7000
8928#define SPI_RESOURCE_RESERVE_CU_2__WAVES__SHIFT 0xc
8929#define SPI_RESOURCE_RESERVE_CU_2__BARRIERS_MASK 0x78000
8930#define SPI_RESOURCE_RESERVE_CU_2__BARRIERS__SHIFT 0xf
8931#define SPI_RESOURCE_RESERVE_CU_3__VGPR_MASK 0xf
8932#define SPI_RESOURCE_RESERVE_CU_3__VGPR__SHIFT 0x0
8933#define SPI_RESOURCE_RESERVE_CU_3__SGPR_MASK 0xf0
8934#define SPI_RESOURCE_RESERVE_CU_3__SGPR__SHIFT 0x4
8935#define SPI_RESOURCE_RESERVE_CU_3__LDS_MASK 0xf00
8936#define SPI_RESOURCE_RESERVE_CU_3__LDS__SHIFT 0x8
8937#define SPI_RESOURCE_RESERVE_CU_3__WAVES_MASK 0x7000
8938#define SPI_RESOURCE_RESERVE_CU_3__WAVES__SHIFT 0xc
8939#define SPI_RESOURCE_RESERVE_CU_3__BARRIERS_MASK 0x78000
8940#define SPI_RESOURCE_RESERVE_CU_3__BARRIERS__SHIFT 0xf
8941#define SPI_RESOURCE_RESERVE_CU_4__VGPR_MASK 0xf
8942#define SPI_RESOURCE_RESERVE_CU_4__VGPR__SHIFT 0x0
8943#define SPI_RESOURCE_RESERVE_CU_4__SGPR_MASK 0xf0
8944#define SPI_RESOURCE_RESERVE_CU_4__SGPR__SHIFT 0x4
8945#define SPI_RESOURCE_RESERVE_CU_4__LDS_MASK 0xf00
8946#define SPI_RESOURCE_RESERVE_CU_4__LDS__SHIFT 0x8
8947#define SPI_RESOURCE_RESERVE_CU_4__WAVES_MASK 0x7000
8948#define SPI_RESOURCE_RESERVE_CU_4__WAVES__SHIFT 0xc
8949#define SPI_RESOURCE_RESERVE_CU_4__BARRIERS_MASK 0x78000
8950#define SPI_RESOURCE_RESERVE_CU_4__BARRIERS__SHIFT 0xf
8951#define SPI_RESOURCE_RESERVE_CU_5__VGPR_MASK 0xf
8952#define SPI_RESOURCE_RESERVE_CU_5__VGPR__SHIFT 0x0
8953#define SPI_RESOURCE_RESERVE_CU_5__SGPR_MASK 0xf0
8954#define SPI_RESOURCE_RESERVE_CU_5__SGPR__SHIFT 0x4
8955#define SPI_RESOURCE_RESERVE_CU_5__LDS_MASK 0xf00
8956#define SPI_RESOURCE_RESERVE_CU_5__LDS__SHIFT 0x8
8957#define SPI_RESOURCE_RESERVE_CU_5__WAVES_MASK 0x7000
8958#define SPI_RESOURCE_RESERVE_CU_5__WAVES__SHIFT 0xc
8959#define SPI_RESOURCE_RESERVE_CU_5__BARRIERS_MASK 0x78000
8960#define SPI_RESOURCE_RESERVE_CU_5__BARRIERS__SHIFT 0xf
8961#define SPI_RESOURCE_RESERVE_CU_6__VGPR_MASK 0xf
8962#define SPI_RESOURCE_RESERVE_CU_6__VGPR__SHIFT 0x0
8963#define SPI_RESOURCE_RESERVE_CU_6__SGPR_MASK 0xf0
8964#define SPI_RESOURCE_RESERVE_CU_6__SGPR__SHIFT 0x4
8965#define SPI_RESOURCE_RESERVE_CU_6__LDS_MASK 0xf00
8966#define SPI_RESOURCE_RESERVE_CU_6__LDS__SHIFT 0x8
8967#define SPI_RESOURCE_RESERVE_CU_6__WAVES_MASK 0x7000
8968#define SPI_RESOURCE_RESERVE_CU_6__WAVES__SHIFT 0xc
8969#define SPI_RESOURCE_RESERVE_CU_6__BARRIERS_MASK 0x78000
8970#define SPI_RESOURCE_RESERVE_CU_6__BARRIERS__SHIFT 0xf
8971#define SPI_RESOURCE_RESERVE_CU_7__VGPR_MASK 0xf
8972#define SPI_RESOURCE_RESERVE_CU_7__VGPR__SHIFT 0x0
8973#define SPI_RESOURCE_RESERVE_CU_7__SGPR_MASK 0xf0
8974#define SPI_RESOURCE_RESERVE_CU_7__SGPR__SHIFT 0x4
8975#define SPI_RESOURCE_RESERVE_CU_7__LDS_MASK 0xf00
8976#define SPI_RESOURCE_RESERVE_CU_7__LDS__SHIFT 0x8
8977#define SPI_RESOURCE_RESERVE_CU_7__WAVES_MASK 0x7000
8978#define SPI_RESOURCE_RESERVE_CU_7__WAVES__SHIFT 0xc
8979#define SPI_RESOURCE_RESERVE_CU_7__BARRIERS_MASK 0x78000
8980#define SPI_RESOURCE_RESERVE_CU_7__BARRIERS__SHIFT 0xf
8981#define SPI_RESOURCE_RESERVE_CU_8__VGPR_MASK 0xf
8982#define SPI_RESOURCE_RESERVE_CU_8__VGPR__SHIFT 0x0
8983#define SPI_RESOURCE_RESERVE_CU_8__SGPR_MASK 0xf0
8984#define SPI_RESOURCE_RESERVE_CU_8__SGPR__SHIFT 0x4
8985#define SPI_RESOURCE_RESERVE_CU_8__LDS_MASK 0xf00
8986#define SPI_RESOURCE_RESERVE_CU_8__LDS__SHIFT 0x8
8987#define SPI_RESOURCE_RESERVE_CU_8__WAVES_MASK 0x7000
8988#define SPI_RESOURCE_RESERVE_CU_8__WAVES__SHIFT 0xc
8989#define SPI_RESOURCE_RESERVE_CU_8__BARRIERS_MASK 0x78000
8990#define SPI_RESOURCE_RESERVE_CU_8__BARRIERS__SHIFT 0xf
8991#define SPI_RESOURCE_RESERVE_CU_9__VGPR_MASK 0xf
8992#define SPI_RESOURCE_RESERVE_CU_9__VGPR__SHIFT 0x0
8993#define SPI_RESOURCE_RESERVE_CU_9__SGPR_MASK 0xf0
8994#define SPI_RESOURCE_RESERVE_CU_9__SGPR__SHIFT 0x4
8995#define SPI_RESOURCE_RESERVE_CU_9__LDS_MASK 0xf00
8996#define SPI_RESOURCE_RESERVE_CU_9__LDS__SHIFT 0x8
8997#define SPI_RESOURCE_RESERVE_CU_9__WAVES_MASK 0x7000
8998#define SPI_RESOURCE_RESERVE_CU_9__WAVES__SHIFT 0xc
8999#define SPI_RESOURCE_RESERVE_CU_9__BARRIERS_MASK 0x78000
9000#define SPI_RESOURCE_RESERVE_CU_9__BARRIERS__SHIFT 0xf
9001#define SPI_RESOURCE_RESERVE_CU_10__VGPR_MASK 0xf
9002#define SPI_RESOURCE_RESERVE_CU_10__VGPR__SHIFT 0x0
9003#define SPI_RESOURCE_RESERVE_CU_10__SGPR_MASK 0xf0
9004#define SPI_RESOURCE_RESERVE_CU_10__SGPR__SHIFT 0x4
9005#define SPI_RESOURCE_RESERVE_CU_10__LDS_MASK 0xf00
9006#define SPI_RESOURCE_RESERVE_CU_10__LDS__SHIFT 0x8
9007#define SPI_RESOURCE_RESERVE_CU_10__WAVES_MASK 0x7000
9008#define SPI_RESOURCE_RESERVE_CU_10__WAVES__SHIFT 0xc
9009#define SPI_RESOURCE_RESERVE_CU_10__BARRIERS_MASK 0x78000
9010#define SPI_RESOURCE_RESERVE_CU_10__BARRIERS__SHIFT 0xf
9011#define SPI_RESOURCE_RESERVE_CU_11__VGPR_MASK 0xf
9012#define SPI_RESOURCE_RESERVE_CU_11__VGPR__SHIFT 0x0
9013#define SPI_RESOURCE_RESERVE_CU_11__SGPR_MASK 0xf0
9014#define SPI_RESOURCE_RESERVE_CU_11__SGPR__SHIFT 0x4
9015#define SPI_RESOURCE_RESERVE_CU_11__LDS_MASK 0xf00
9016#define SPI_RESOURCE_RESERVE_CU_11__LDS__SHIFT 0x8
9017#define SPI_RESOURCE_RESERVE_CU_11__WAVES_MASK 0x7000
9018#define SPI_RESOURCE_RESERVE_CU_11__WAVES__SHIFT 0xc
9019#define SPI_RESOURCE_RESERVE_CU_11__BARRIERS_MASK 0x78000
9020#define SPI_RESOURCE_RESERVE_CU_11__BARRIERS__SHIFT 0xf
9021#define SPI_RESOURCE_RESERVE_EN_CU_0__EN_MASK 0x1
9022#define SPI_RESOURCE_RESERVE_EN_CU_0__EN__SHIFT 0x0
9023#define SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK_MASK 0xfffe
9024#define SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK__SHIFT 0x1
9025#define SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK_MASK 0xff0000
9026#define SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK__SHIFT 0x10
9027#define SPI_RESOURCE_RESERVE_EN_CU_0__RESERVE_SPACE_ONLY_MASK 0x1000000
9028#define SPI_RESOURCE_RESERVE_EN_CU_0__RESERVE_SPACE_ONLY__SHIFT 0x18
9029#define SPI_RESOURCE_RESERVE_EN_CU_1__EN_MASK 0x1
9030#define SPI_RESOURCE_RESERVE_EN_CU_1__EN__SHIFT 0x0
9031#define SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK_MASK 0xfffe
9032#define SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK__SHIFT 0x1
9033#define SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK_MASK 0xff0000
9034#define SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK__SHIFT 0x10
9035#define SPI_RESOURCE_RESERVE_EN_CU_1__RESERVE_SPACE_ONLY_MASK 0x1000000
9036#define SPI_RESOURCE_RESERVE_EN_CU_1__RESERVE_SPACE_ONLY__SHIFT 0x18
9037#define SPI_RESOURCE_RESERVE_EN_CU_2__EN_MASK 0x1
9038#define SPI_RESOURCE_RESERVE_EN_CU_2__EN__SHIFT 0x0
9039#define SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK_MASK 0xfffe
9040#define SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK__SHIFT 0x1
9041#define SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK_MASK 0xff0000
9042#define SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK__SHIFT 0x10
9043#define SPI_RESOURCE_RESERVE_EN_CU_2__RESERVE_SPACE_ONLY_MASK 0x1000000
9044#define SPI_RESOURCE_RESERVE_EN_CU_2__RESERVE_SPACE_ONLY__SHIFT 0x18
9045#define SPI_RESOURCE_RESERVE_EN_CU_3__EN_MASK 0x1
9046#define SPI_RESOURCE_RESERVE_EN_CU_3__EN__SHIFT 0x0
9047#define SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK_MASK 0xfffe
9048#define SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK__SHIFT 0x1
9049#define SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK_MASK 0xff0000
9050#define SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK__SHIFT 0x10
9051#define SPI_RESOURCE_RESERVE_EN_CU_3__RESERVE_SPACE_ONLY_MASK 0x1000000
9052#define SPI_RESOURCE_RESERVE_EN_CU_3__RESERVE_SPACE_ONLY__SHIFT 0x18
9053#define SPI_RESOURCE_RESERVE_EN_CU_4__EN_MASK 0x1
9054#define SPI_RESOURCE_RESERVE_EN_CU_4__EN__SHIFT 0x0
9055#define SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK_MASK 0xfffe
9056#define SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK__SHIFT 0x1
9057#define SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK_MASK 0xff0000
9058#define SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK__SHIFT 0x10
9059#define SPI_RESOURCE_RESERVE_EN_CU_4__RESERVE_SPACE_ONLY_MASK 0x1000000
9060#define SPI_RESOURCE_RESERVE_EN_CU_4__RESERVE_SPACE_ONLY__SHIFT 0x18
9061#define SPI_RESOURCE_RESERVE_EN_CU_5__EN_MASK 0x1
9062#define SPI_RESOURCE_RESERVE_EN_CU_5__EN__SHIFT 0x0
9063#define SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK_MASK 0xfffe
9064#define SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK__SHIFT 0x1
9065#define SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK_MASK 0xff0000
9066#define SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK__SHIFT 0x10
9067#define SPI_RESOURCE_RESERVE_EN_CU_5__RESERVE_SPACE_ONLY_MASK 0x1000000
9068#define SPI_RESOURCE_RESERVE_EN_CU_5__RESERVE_SPACE_ONLY__SHIFT 0x18
9069#define SPI_RESOURCE_RESERVE_EN_CU_6__EN_MASK 0x1
9070#define SPI_RESOURCE_RESERVE_EN_CU_6__EN__SHIFT 0x0
9071#define SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK_MASK 0xfffe
9072#define SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK__SHIFT 0x1
9073#define SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK_MASK 0xff0000
9074#define SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK__SHIFT 0x10
9075#define SPI_RESOURCE_RESERVE_EN_CU_6__RESERVE_SPACE_ONLY_MASK 0x1000000
9076#define SPI_RESOURCE_RESERVE_EN_CU_6__RESERVE_SPACE_ONLY__SHIFT 0x18
9077#define SPI_RESOURCE_RESERVE_EN_CU_7__EN_MASK 0x1
9078#define SPI_RESOURCE_RESERVE_EN_CU_7__EN__SHIFT 0x0
9079#define SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK_MASK 0xfffe
9080#define SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK__SHIFT 0x1
9081#define SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK_MASK 0xff0000
9082#define SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK__SHIFT 0x10
9083#define SPI_RESOURCE_RESERVE_EN_CU_7__RESERVE_SPACE_ONLY_MASK 0x1000000
9084#define SPI_RESOURCE_RESERVE_EN_CU_7__RESERVE_SPACE_ONLY__SHIFT 0x18
9085#define SPI_RESOURCE_RESERVE_EN_CU_8__EN_MASK 0x1
9086#define SPI_RESOURCE_RESERVE_EN_CU_8__EN__SHIFT 0x0
9087#define SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK_MASK 0xfffe
9088#define SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK__SHIFT 0x1
9089#define SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK_MASK 0xff0000
9090#define SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK__SHIFT 0x10
9091#define SPI_RESOURCE_RESERVE_EN_CU_8__RESERVE_SPACE_ONLY_MASK 0x1000000
9092#define SPI_RESOURCE_RESERVE_EN_CU_8__RESERVE_SPACE_ONLY__SHIFT 0x18
9093#define SPI_RESOURCE_RESERVE_EN_CU_9__EN_MASK 0x1
9094#define SPI_RESOURCE_RESERVE_EN_CU_9__EN__SHIFT 0x0
9095#define SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK_MASK 0xfffe
9096#define SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK__SHIFT 0x1
9097#define SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK_MASK 0xff0000
9098#define SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK__SHIFT 0x10
9099#define SPI_RESOURCE_RESERVE_EN_CU_9__RESERVE_SPACE_ONLY_MASK 0x1000000
9100#define SPI_RESOURCE_RESERVE_EN_CU_9__RESERVE_SPACE_ONLY__SHIFT 0x18
9101#define SPI_RESOURCE_RESERVE_EN_CU_10__EN_MASK 0x1
9102#define SPI_RESOURCE_RESERVE_EN_CU_10__EN__SHIFT 0x0
9103#define SPI_RESOURCE_RESERVE_EN_CU_10__TYPE_MASK_MASK 0xfffe
9104#define SPI_RESOURCE_RESERVE_EN_CU_10__TYPE_MASK__SHIFT 0x1
9105#define SPI_RESOURCE_RESERVE_EN_CU_10__QUEUE_MASK_MASK 0xff0000
9106#define SPI_RESOURCE_RESERVE_EN_CU_10__QUEUE_MASK__SHIFT 0x10
9107#define SPI_RESOURCE_RESERVE_EN_CU_10__RESERVE_SPACE_ONLY_MASK 0x1000000
9108#define SPI_RESOURCE_RESERVE_EN_CU_10__RESERVE_SPACE_ONLY__SHIFT 0x18
9109#define SPI_RESOURCE_RESERVE_EN_CU_11__EN_MASK 0x1
9110#define SPI_RESOURCE_RESERVE_EN_CU_11__EN__SHIFT 0x0
9111#define SPI_RESOURCE_RESERVE_EN_CU_11__TYPE_MASK_MASK 0xfffe
9112#define SPI_RESOURCE_RESERVE_EN_CU_11__TYPE_MASK__SHIFT 0x1
9113#define SPI_RESOURCE_RESERVE_EN_CU_11__QUEUE_MASK_MASK 0xff0000
9114#define SPI_RESOURCE_RESERVE_EN_CU_11__QUEUE_MASK__SHIFT 0x10
9115#define SPI_RESOURCE_RESERVE_EN_CU_11__RESERVE_SPACE_ONLY_MASK 0x1000000
9116#define SPI_RESOURCE_RESERVE_EN_CU_11__RESERVE_SPACE_ONLY__SHIFT 0x18
9117#define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0xfff
9118#define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0
9119#define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY_MASK 0x1fffff
9120#define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY__SHIFT 0x0
9121#define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER_MASK 0xe00000
9122#define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER__SHIFT 0x15
9123#define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS_MASK 0x1000000
9124#define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS__SHIFT 0x18
9125#define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS_MASK 0x2000000
9126#define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS__SHIFT 0x19
9127#define SPI_CONFIG_CNTL__RSRC_MGMT_RESET_MASK 0x4000000
9128#define SPI_CONFIG_CNTL__RSRC_MGMT_RESET__SHIFT 0x1a
9129#define SPI_CONFIG_CNTL__TTRACE_STALL_ALL_MASK 0x8000000
9130#define SPI_CONFIG_CNTL__TTRACE_STALL_ALL__SHIFT 0x1b
9131#define SPI_DEBUG_CNTL__DEBUG_GRBM_OVERRIDE_MASK 0x1
9132#define SPI_DEBUG_CNTL__DEBUG_GRBM_OVERRIDE__SHIFT 0x0
9133#define SPI_DEBUG_CNTL__DEBUG_THREAD_TYPE_SEL_MASK 0xe
9134#define SPI_DEBUG_CNTL__DEBUG_THREAD_TYPE_SEL__SHIFT 0x1
9135#define SPI_DEBUG_CNTL__DEBUG_GROUP_SEL_MASK 0x3f0
9136#define SPI_DEBUG_CNTL__DEBUG_GROUP_SEL__SHIFT 0x4
9137#define SPI_DEBUG_CNTL__DEBUG_SIMD_SEL_MASK 0xfc00
9138#define SPI_DEBUG_CNTL__DEBUG_SIMD_SEL__SHIFT 0xa
9139#define SPI_DEBUG_CNTL__DEBUG_SH_SEL_MASK 0x10000
9140#define SPI_DEBUG_CNTL__DEBUG_SH_SEL__SHIFT 0x10
9141#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_0_MASK 0x20000
9142#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_0__SHIFT 0x11
9143#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_1_MASK 0x40000
9144#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_1__SHIFT 0x12
9145#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_2_MASK 0x80000
9146#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_2__SHIFT 0x13
9147#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_3_MASK 0x100000
9148#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_3__SHIFT 0x14
9149#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_4_MASK 0x200000
9150#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_4__SHIFT 0x15
9151#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_5_MASK 0x400000
9152#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_5__SHIFT 0x16
9153#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_6_MASK 0x800000
9154#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_6__SHIFT 0x17
9155#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_7_MASK 0x1000000
9156#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_7__SHIFT 0x18
9157#define SPI_DEBUG_CNTL__DEBUG_PIPE_SEL_MASK 0xe000000
9158#define SPI_DEBUG_CNTL__DEBUG_PIPE_SEL__SHIFT 0x19
9159#define SPI_DEBUG_CNTL__DEBUG_REG_EN_MASK 0x80000000
9160#define SPI_DEBUG_CNTL__DEBUG_REG_EN__SHIFT 0x1f
9161#define SPI_DEBUG_READ__DATA_MASK 0xffffff
9162#define SPI_DEBUG_READ__DATA__SHIFT 0x0
9163#define SPI_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff
9164#define SPI_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
9165#define SPI_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00
9166#define SPI_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
9167#define SPI_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
9168#define SPI_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
9169#define SPI_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff
9170#define SPI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
9171#define SPI_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00
9172#define SPI_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
9173#define SPI_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
9174#define SPI_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
9175#define SPI_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff
9176#define SPI_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
9177#define SPI_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0xffc00
9178#define SPI_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa
9179#define SPI_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000
9180#define SPI_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
9181#define SPI_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff
9182#define SPI_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
9183#define SPI_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0xffc00
9184#define SPI_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa
9185#define SPI_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000
9186#define SPI_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
9187#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff
9188#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
9189#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00
9190#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
9191#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff
9192#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
9193#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00
9194#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
9195#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x3ff
9196#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0
9197#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0xffc00
9198#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa
9199#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x3ff
9200#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0
9201#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0xffc00
9202#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa
9203#define SPI_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0xff
9204#define SPI_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0
9205#define SPI_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0xff
9206#define SPI_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0
9207#define SPI_PERFCOUNTER_BINS__BIN0_MIN_MASK 0xf
9208#define SPI_PERFCOUNTER_BINS__BIN0_MIN__SHIFT 0x0
9209#define SPI_PERFCOUNTER_BINS__BIN0_MAX_MASK 0xf0
9210#define SPI_PERFCOUNTER_BINS__BIN0_MAX__SHIFT 0x4
9211#define SPI_PERFCOUNTER_BINS__BIN1_MIN_MASK 0xf00
9212#define SPI_PERFCOUNTER_BINS__BIN1_MIN__SHIFT 0x8
9213#define SPI_PERFCOUNTER_BINS__BIN1_MAX_MASK 0xf000
9214#define SPI_PERFCOUNTER_BINS__BIN1_MAX__SHIFT 0xc
9215#define SPI_PERFCOUNTER_BINS__BIN2_MIN_MASK 0xf0000
9216#define SPI_PERFCOUNTER_BINS__BIN2_MIN__SHIFT 0x10
9217#define SPI_PERFCOUNTER_BINS__BIN2_MAX_MASK 0xf00000
9218#define SPI_PERFCOUNTER_BINS__BIN2_MAX__SHIFT 0x14
9219#define SPI_PERFCOUNTER_BINS__BIN3_MIN_MASK 0xf000000
9220#define SPI_PERFCOUNTER_BINS__BIN3_MIN__SHIFT 0x18
9221#define SPI_PERFCOUNTER_BINS__BIN3_MAX_MASK 0xf0000000
9222#define SPI_PERFCOUNTER_BINS__BIN3_MAX__SHIFT 0x1c
9223#define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
9224#define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
9225#define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
9226#define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
9227#define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
9228#define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
9229#define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
9230#define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
9231#define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
9232#define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
9233#define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
9234#define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
9235#define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
9236#define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
9237#define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
9238#define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
9239#define SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xffffffff
9240#define SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0
9241#define SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xffffffff
9242#define SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0
9243#define SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xffffffff
9244#define SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0
9245#define SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xffffffff
9246#define SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0
9247#define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY_MASK 0xf
9248#define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT 0x0
9249#define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW_MASK 0x10
9250#define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW__SHIFT 0x4
9251#define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE_MASK 0x40
9252#define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE__SHIFT 0x6
9253#define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT_MASK 0x80
9254#define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT__SHIFT 0x7
9255#define SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE_MASK 0x100
9256#define SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE__SHIFT 0x8
9257#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE_MASK 0x200
9258#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE__SHIFT 0x9
9259#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT_MASK 0x3c00
9260#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT__SHIFT 0xa
9261#define SPI_CONFIG_CNTL_1__PC_LIMIT_SIZE_MASK 0xffff0000
9262#define SPI_CONFIG_CNTL_1__PC_LIMIT_SIZE__SHIFT 0x10
9263#define SPI_DEBUG_BUSY__LS_BUSY_MASK 0x1
9264#define SPI_DEBUG_BUSY__LS_BUSY__SHIFT 0x0
9265#define SPI_DEBUG_BUSY__HS_BUSY_MASK 0x2
9266#define SPI_DEBUG_BUSY__HS_BUSY__SHIFT 0x1
9267#define SPI_DEBUG_BUSY__ES_BUSY_MASK 0x4
9268#define SPI_DEBUG_BUSY__ES_BUSY__SHIFT 0x2
9269#define SPI_DEBUG_BUSY__GS_BUSY_MASK 0x8
9270#define SPI_DEBUG_BUSY__GS_BUSY__SHIFT 0x3
9271#define SPI_DEBUG_BUSY__VS_BUSY_MASK 0x10
9272#define SPI_DEBUG_BUSY__VS_BUSY__SHIFT 0x4
9273#define SPI_DEBUG_BUSY__PS0_BUSY_MASK 0x20
9274#define SPI_DEBUG_BUSY__PS0_BUSY__SHIFT 0x5
9275#define SPI_DEBUG_BUSY__PS1_BUSY_MASK 0x40
9276#define SPI_DEBUG_BUSY__PS1_BUSY__SHIFT 0x6
9277#define SPI_DEBUG_BUSY__CSG_BUSY_MASK 0x80
9278#define SPI_DEBUG_BUSY__CSG_BUSY__SHIFT 0x7
9279#define SPI_DEBUG_BUSY__CS0_BUSY_MASK 0x100
9280#define SPI_DEBUG_BUSY__CS0_BUSY__SHIFT 0x8
9281#define SPI_DEBUG_BUSY__CS1_BUSY_MASK 0x200
9282#define SPI_DEBUG_BUSY__CS1_BUSY__SHIFT 0x9
9283#define SPI_DEBUG_BUSY__CS2_BUSY_MASK 0x400
9284#define SPI_DEBUG_BUSY__CS2_BUSY__SHIFT 0xa
9285#define SPI_DEBUG_BUSY__CS3_BUSY_MASK 0x800
9286#define SPI_DEBUG_BUSY__CS3_BUSY__SHIFT 0xb
9287#define SPI_DEBUG_BUSY__CS4_BUSY_MASK 0x1000
9288#define SPI_DEBUG_BUSY__CS4_BUSY__SHIFT 0xc
9289#define SPI_DEBUG_BUSY__CS5_BUSY_MASK 0x2000
9290#define SPI_DEBUG_BUSY__CS5_BUSY__SHIFT 0xd
9291#define SPI_DEBUG_BUSY__CS6_BUSY_MASK 0x4000
9292#define SPI_DEBUG_BUSY__CS6_BUSY__SHIFT 0xe
9293#define SPI_DEBUG_BUSY__CS7_BUSY_MASK 0x8000
9294#define SPI_DEBUG_BUSY__CS7_BUSY__SHIFT 0xf
9295#define SPI_DEBUG_BUSY__LDS_WR_CTL0_BUSY_MASK 0x10000
9296#define SPI_DEBUG_BUSY__LDS_WR_CTL0_BUSY__SHIFT 0x10
9297#define SPI_DEBUG_BUSY__LDS_WR_CTL1_BUSY_MASK 0x20000
9298#define SPI_DEBUG_BUSY__LDS_WR_CTL1_BUSY__SHIFT 0x11
9299#define SPI_DEBUG_BUSY__RSRC_ALLOC0_BUSY_MASK 0x40000
9300#define SPI_DEBUG_BUSY__RSRC_ALLOC0_BUSY__SHIFT 0x12
9301#define SPI_DEBUG_BUSY__RSRC_ALLOC1_BUSY_MASK 0x80000
9302#define SPI_DEBUG_BUSY__RSRC_ALLOC1_BUSY__SHIFT 0x13
9303#define SPI_DEBUG_BUSY__PC_DEALLOC_BUSY_MASK 0x100000
9304#define SPI_DEBUG_BUSY__PC_DEALLOC_BUSY__SHIFT 0x14
9305#define SPI_DEBUG_BUSY__EVENT_CLCTR_BUSY_MASK 0x200000
9306#define SPI_DEBUG_BUSY__EVENT_CLCTR_BUSY__SHIFT 0x15
9307#define SPI_DEBUG_BUSY__GRBM_BUSY_MASK 0x400000
9308#define SPI_DEBUG_BUSY__GRBM_BUSY__SHIFT 0x16
9309#define SPI_DEBUG_BUSY__SPIS_BUSY_MASK 0x800000
9310#define SPI_DEBUG_BUSY__SPIS_BUSY__SHIFT 0x17
9311#define CGTS_SM_CTRL_REG__ON_SEQ_DELAY_MASK 0xf
9312#define CGTS_SM_CTRL_REG__ON_SEQ_DELAY__SHIFT 0x0
9313#define CGTS_SM_CTRL_REG__OFF_SEQ_DELAY_MASK 0xff0
9314#define CGTS_SM_CTRL_REG__OFF_SEQ_DELAY__SHIFT 0x4
9315#define CGTS_SM_CTRL_REG__MGCG_ENABLED_MASK 0x1000
9316#define CGTS_SM_CTRL_REG__MGCG_ENABLED__SHIFT 0xc
9317#define CGTS_SM_CTRL_REG__BASE_MODE_MASK 0x10000
9318#define CGTS_SM_CTRL_REG__BASE_MODE__SHIFT 0x10
9319#define CGTS_SM_CTRL_REG__SM_MODE_MASK 0xe0000
9320#define CGTS_SM_CTRL_REG__SM_MODE__SHIFT 0x11
9321#define CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK 0x100000
9322#define CGTS_SM_CTRL_REG__SM_MODE_ENABLE__SHIFT 0x14
9323#define CGTS_SM_CTRL_REG__OVERRIDE_MASK 0x200000
9324#define CGTS_SM_CTRL_REG__OVERRIDE__SHIFT 0x15
9325#define CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK 0x400000
9326#define CGTS_SM_CTRL_REG__LS_OVERRIDE__SHIFT 0x16
9327#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK 0x800000
9328#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN__SHIFT 0x17
9329#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK 0xff000000
9330#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT 0x18
9331#define CGTS_RD_CTRL_REG__ROW_MUX_SEL_MASK 0x1f
9332#define CGTS_RD_CTRL_REG__ROW_MUX_SEL__SHIFT 0x0
9333#define CGTS_RD_CTRL_REG__REG_MUX_SEL_MASK 0x1f00
9334#define CGTS_RD_CTRL_REG__REG_MUX_SEL__SHIFT 0x8
9335#define CGTS_RD_REG__READ_DATA_MASK 0x3fff
9336#define CGTS_RD_REG__READ_DATA__SHIFT 0x0
9337#define CGTS_TCC_DISABLE__TCC_DISABLE_MASK 0xffff0000
9338#define CGTS_TCC_DISABLE__TCC_DISABLE__SHIFT 0x10
9339#define CGTS_USER_TCC_DISABLE__TCC_DISABLE_MASK 0xffff0000
9340#define CGTS_USER_TCC_DISABLE__TCC_DISABLE__SHIFT 0x10
9341#define CGTS_CU0_SP0_CTRL_REG__SP00_MASK 0x7f
9342#define CGTS_CU0_SP0_CTRL_REG__SP00__SHIFT 0x0
9343#define CGTS_CU0_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
9344#define CGTS_CU0_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
9345#define CGTS_CU0_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
9346#define CGTS_CU0_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
9347#define CGTS_CU0_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
9348#define CGTS_CU0_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
9349#define CGTS_CU0_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
9350#define CGTS_CU0_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
9351#define CGTS_CU0_SP0_CTRL_REG__SP01_MASK 0x7f0000
9352#define CGTS_CU0_SP0_CTRL_REG__SP01__SHIFT 0x10
9353#define CGTS_CU0_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
9354#define CGTS_CU0_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
9355#define CGTS_CU0_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
9356#define CGTS_CU0_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
9357#define CGTS_CU0_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
9358#define CGTS_CU0_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
9359#define CGTS_CU0_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
9360#define CGTS_CU0_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
9361#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
9362#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
9363#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
9364#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
9365#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
9366#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
9367#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
9368#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
9369#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
9370#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
9371#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
9372#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
9373#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
9374#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
9375#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
9376#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
9377#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
9378#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
9379#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
9380#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
9381#define CGTS_CU0_TA_SQC_CTRL_REG__TA_MASK 0x7f
9382#define CGTS_CU0_TA_SQC_CTRL_REG__TA__SHIFT 0x0
9383#define CGTS_CU0_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x80
9384#define CGTS_CU0_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
9385#define CGTS_CU0_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
9386#define CGTS_CU0_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
9387#define CGTS_CU0_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
9388#define CGTS_CU0_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
9389#define CGTS_CU0_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
9390#define CGTS_CU0_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
9391#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_MASK 0x7f0000
9392#define CGTS_CU0_TA_SQC_CTRL_REG__SQC__SHIFT 0x10
9393#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x800000
9394#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17
9395#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x3000000
9396#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18
9397#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x4000000
9398#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a
9399#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x8000000
9400#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b
9401#define CGTS_CU0_SP1_CTRL_REG__SP10_MASK 0x7f
9402#define CGTS_CU0_SP1_CTRL_REG__SP10__SHIFT 0x0
9403#define CGTS_CU0_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
9404#define CGTS_CU0_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
9405#define CGTS_CU0_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
9406#define CGTS_CU0_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
9407#define CGTS_CU0_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
9408#define CGTS_CU0_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
9409#define CGTS_CU0_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
9410#define CGTS_CU0_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
9411#define CGTS_CU0_SP1_CTRL_REG__SP11_MASK 0x7f0000
9412#define CGTS_CU0_SP1_CTRL_REG__SP11__SHIFT 0x10
9413#define CGTS_CU0_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
9414#define CGTS_CU0_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
9415#define CGTS_CU0_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
9416#define CGTS_CU0_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
9417#define CGTS_CU0_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
9418#define CGTS_CU0_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
9419#define CGTS_CU0_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
9420#define CGTS_CU0_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
9421#define CGTS_CU0_TD_TCP_CTRL_REG__TD_MASK 0x7f
9422#define CGTS_CU0_TD_TCP_CTRL_REG__TD__SHIFT 0x0
9423#define CGTS_CU0_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
9424#define CGTS_CU0_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
9425#define CGTS_CU0_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
9426#define CGTS_CU0_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
9427#define CGTS_CU0_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
9428#define CGTS_CU0_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
9429#define CGTS_CU0_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
9430#define CGTS_CU0_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
9431#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
9432#define CGTS_CU0_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
9433#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
9434#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
9435#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
9436#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
9437#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
9438#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
9439#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
9440#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
9441#define CGTS_CU1_SP0_CTRL_REG__SP00_MASK 0x7f
9442#define CGTS_CU1_SP0_CTRL_REG__SP00__SHIFT 0x0
9443#define CGTS_CU1_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
9444#define CGTS_CU1_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
9445#define CGTS_CU1_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
9446#define CGTS_CU1_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
9447#define CGTS_CU1_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
9448#define CGTS_CU1_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
9449#define CGTS_CU1_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
9450#define CGTS_CU1_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
9451#define CGTS_CU1_SP0_CTRL_REG__SP01_MASK 0x7f0000
9452#define CGTS_CU1_SP0_CTRL_REG__SP01__SHIFT 0x10
9453#define CGTS_CU1_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
9454#define CGTS_CU1_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
9455#define CGTS_CU1_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
9456#define CGTS_CU1_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
9457#define CGTS_CU1_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
9458#define CGTS_CU1_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
9459#define CGTS_CU1_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
9460#define CGTS_CU1_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
9461#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
9462#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
9463#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
9464#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
9465#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
9466#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
9467#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
9468#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
9469#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
9470#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
9471#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
9472#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
9473#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
9474#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
9475#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
9476#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
9477#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
9478#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
9479#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
9480#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
9481#define CGTS_CU1_TA_CTRL_REG__TA_MASK 0x7f
9482#define CGTS_CU1_TA_CTRL_REG__TA__SHIFT 0x0
9483#define CGTS_CU1_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
9484#define CGTS_CU1_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
9485#define CGTS_CU1_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
9486#define CGTS_CU1_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
9487#define CGTS_CU1_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
9488#define CGTS_CU1_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
9489#define CGTS_CU1_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
9490#define CGTS_CU1_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
9491#define CGTS_CU1_SP1_CTRL_REG__SP10_MASK 0x7f
9492#define CGTS_CU1_SP1_CTRL_REG__SP10__SHIFT 0x0
9493#define CGTS_CU1_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
9494#define CGTS_CU1_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
9495#define CGTS_CU1_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
9496#define CGTS_CU1_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
9497#define CGTS_CU1_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
9498#define CGTS_CU1_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
9499#define CGTS_CU1_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
9500#define CGTS_CU1_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
9501#define CGTS_CU1_SP1_CTRL_REG__SP11_MASK 0x7f0000
9502#define CGTS_CU1_SP1_CTRL_REG__SP11__SHIFT 0x10
9503#define CGTS_CU1_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
9504#define CGTS_CU1_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
9505#define CGTS_CU1_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
9506#define CGTS_CU1_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
9507#define CGTS_CU1_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
9508#define CGTS_CU1_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
9509#define CGTS_CU1_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
9510#define CGTS_CU1_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
9511#define CGTS_CU1_TD_TCP_CTRL_REG__TD_MASK 0x7f
9512#define CGTS_CU1_TD_TCP_CTRL_REG__TD__SHIFT 0x0
9513#define CGTS_CU1_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
9514#define CGTS_CU1_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
9515#define CGTS_CU1_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
9516#define CGTS_CU1_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
9517#define CGTS_CU1_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
9518#define CGTS_CU1_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
9519#define CGTS_CU1_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
9520#define CGTS_CU1_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
9521#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
9522#define CGTS_CU1_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
9523#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
9524#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
9525#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
9526#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
9527#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
9528#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
9529#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
9530#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
9531#define CGTS_CU2_SP0_CTRL_REG__SP00_MASK 0x7f
9532#define CGTS_CU2_SP0_CTRL_REG__SP00__SHIFT 0x0
9533#define CGTS_CU2_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
9534#define CGTS_CU2_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
9535#define CGTS_CU2_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
9536#define CGTS_CU2_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
9537#define CGTS_CU2_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
9538#define CGTS_CU2_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
9539#define CGTS_CU2_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
9540#define CGTS_CU2_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
9541#define CGTS_CU2_SP0_CTRL_REG__SP01_MASK 0x7f0000
9542#define CGTS_CU2_SP0_CTRL_REG__SP01__SHIFT 0x10
9543#define CGTS_CU2_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
9544#define CGTS_CU2_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
9545#define CGTS_CU2_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
9546#define CGTS_CU2_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
9547#define CGTS_CU2_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
9548#define CGTS_CU2_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
9549#define CGTS_CU2_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
9550#define CGTS_CU2_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
9551#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
9552#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
9553#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
9554#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
9555#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
9556#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
9557#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
9558#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
9559#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
9560#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
9561#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
9562#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
9563#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
9564#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
9565#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
9566#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
9567#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
9568#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
9569#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
9570#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
9571#define CGTS_CU2_TA_CTRL_REG__TA_MASK 0x7f
9572#define CGTS_CU2_TA_CTRL_REG__TA__SHIFT 0x0
9573#define CGTS_CU2_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
9574#define CGTS_CU2_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
9575#define CGTS_CU2_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
9576#define CGTS_CU2_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
9577#define CGTS_CU2_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
9578#define CGTS_CU2_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
9579#define CGTS_CU2_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
9580#define CGTS_CU2_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
9581#define CGTS_CU2_SP1_CTRL_REG__SP10_MASK 0x7f
9582#define CGTS_CU2_SP1_CTRL_REG__SP10__SHIFT 0x0
9583#define CGTS_CU2_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
9584#define CGTS_CU2_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
9585#define CGTS_CU2_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
9586#define CGTS_CU2_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
9587#define CGTS_CU2_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
9588#define CGTS_CU2_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
9589#define CGTS_CU2_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
9590#define CGTS_CU2_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
9591#define CGTS_CU2_SP1_CTRL_REG__SP11_MASK 0x7f0000
9592#define CGTS_CU2_SP1_CTRL_REG__SP11__SHIFT 0x10
9593#define CGTS_CU2_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
9594#define CGTS_CU2_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
9595#define CGTS_CU2_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
9596#define CGTS_CU2_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
9597#define CGTS_CU2_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
9598#define CGTS_CU2_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
9599#define CGTS_CU2_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
9600#define CGTS_CU2_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
9601#define CGTS_CU2_TD_TCP_CTRL_REG__TD_MASK 0x7f
9602#define CGTS_CU2_TD_TCP_CTRL_REG__TD__SHIFT 0x0
9603#define CGTS_CU2_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
9604#define CGTS_CU2_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
9605#define CGTS_CU2_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
9606#define CGTS_CU2_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
9607#define CGTS_CU2_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
9608#define CGTS_CU2_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
9609#define CGTS_CU2_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
9610#define CGTS_CU2_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
9611#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
9612#define CGTS_CU2_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
9613#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
9614#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
9615#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
9616#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
9617#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
9618#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
9619#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
9620#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
9621#define CGTS_CU3_SP0_CTRL_REG__SP00_MASK 0x7f
9622#define CGTS_CU3_SP0_CTRL_REG__SP00__SHIFT 0x0
9623#define CGTS_CU3_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
9624#define CGTS_CU3_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
9625#define CGTS_CU3_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
9626#define CGTS_CU3_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
9627#define CGTS_CU3_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
9628#define CGTS_CU3_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
9629#define CGTS_CU3_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
9630#define CGTS_CU3_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
9631#define CGTS_CU3_SP0_CTRL_REG__SP01_MASK 0x7f0000
9632#define CGTS_CU3_SP0_CTRL_REG__SP01__SHIFT 0x10
9633#define CGTS_CU3_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
9634#define CGTS_CU3_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
9635#define CGTS_CU3_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
9636#define CGTS_CU3_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
9637#define CGTS_CU3_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
9638#define CGTS_CU3_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
9639#define CGTS_CU3_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
9640#define CGTS_CU3_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
9641#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
9642#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
9643#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
9644#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
9645#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
9646#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
9647#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
9648#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
9649#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
9650#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
9651#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
9652#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
9653#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
9654#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
9655#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
9656#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
9657#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
9658#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
9659#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
9660#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
9661#define CGTS_CU3_TA_CTRL_REG__TA_MASK 0x7f
9662#define CGTS_CU3_TA_CTRL_REG__TA__SHIFT 0x0
9663#define CGTS_CU3_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
9664#define CGTS_CU3_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
9665#define CGTS_CU3_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
9666#define CGTS_CU3_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
9667#define CGTS_CU3_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
9668#define CGTS_CU3_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
9669#define CGTS_CU3_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
9670#define CGTS_CU3_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
9671#define CGTS_CU3_SP1_CTRL_REG__SP10_MASK 0x7f
9672#define CGTS_CU3_SP1_CTRL_REG__SP10__SHIFT 0x0
9673#define CGTS_CU3_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
9674#define CGTS_CU3_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
9675#define CGTS_CU3_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
9676#define CGTS_CU3_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
9677#define CGTS_CU3_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
9678#define CGTS_CU3_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
9679#define CGTS_CU3_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
9680#define CGTS_CU3_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
9681#define CGTS_CU3_SP1_CTRL_REG__SP11_MASK 0x7f0000
9682#define CGTS_CU3_SP1_CTRL_REG__SP11__SHIFT 0x10
9683#define CGTS_CU3_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
9684#define CGTS_CU3_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
9685#define CGTS_CU3_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
9686#define CGTS_CU3_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
9687#define CGTS_CU3_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
9688#define CGTS_CU3_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
9689#define CGTS_CU3_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
9690#define CGTS_CU3_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
9691#define CGTS_CU3_TD_TCP_CTRL_REG__TD_MASK 0x7f
9692#define CGTS_CU3_TD_TCP_CTRL_REG__TD__SHIFT 0x0
9693#define CGTS_CU3_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
9694#define CGTS_CU3_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
9695#define CGTS_CU3_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
9696#define CGTS_CU3_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
9697#define CGTS_CU3_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
9698#define CGTS_CU3_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
9699#define CGTS_CU3_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
9700#define CGTS_CU3_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
9701#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
9702#define CGTS_CU3_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
9703#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
9704#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
9705#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
9706#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
9707#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
9708#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
9709#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
9710#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
9711#define CGTS_CU4_SP0_CTRL_REG__SP00_MASK 0x7f
9712#define CGTS_CU4_SP0_CTRL_REG__SP00__SHIFT 0x0
9713#define CGTS_CU4_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
9714#define CGTS_CU4_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
9715#define CGTS_CU4_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
9716#define CGTS_CU4_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
9717#define CGTS_CU4_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
9718#define CGTS_CU4_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
9719#define CGTS_CU4_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
9720#define CGTS_CU4_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
9721#define CGTS_CU4_SP0_CTRL_REG__SP01_MASK 0x7f0000
9722#define CGTS_CU4_SP0_CTRL_REG__SP01__SHIFT 0x10
9723#define CGTS_CU4_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
9724#define CGTS_CU4_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
9725#define CGTS_CU4_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
9726#define CGTS_CU4_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
9727#define CGTS_CU4_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
9728#define CGTS_CU4_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
9729#define CGTS_CU4_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
9730#define CGTS_CU4_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
9731#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
9732#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
9733#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
9734#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
9735#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
9736#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
9737#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
9738#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
9739#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
9740#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
9741#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
9742#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
9743#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
9744#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
9745#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
9746#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
9747#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
9748#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
9749#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
9750#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
9751#define CGTS_CU4_TA_SQC_CTRL_REG__TA_MASK 0x7f
9752#define CGTS_CU4_TA_SQC_CTRL_REG__TA__SHIFT 0x0
9753#define CGTS_CU4_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x80
9754#define CGTS_CU4_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
9755#define CGTS_CU4_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
9756#define CGTS_CU4_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
9757#define CGTS_CU4_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
9758#define CGTS_CU4_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
9759#define CGTS_CU4_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
9760#define CGTS_CU4_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
9761#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_MASK 0x7f0000
9762#define CGTS_CU4_TA_SQC_CTRL_REG__SQC__SHIFT 0x10
9763#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x800000
9764#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17
9765#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x3000000
9766#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18
9767#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x4000000
9768#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a
9769#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x8000000
9770#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b
9771#define CGTS_CU4_SP1_CTRL_REG__SP10_MASK 0x7f
9772#define CGTS_CU4_SP1_CTRL_REG__SP10__SHIFT 0x0
9773#define CGTS_CU4_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
9774#define CGTS_CU4_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
9775#define CGTS_CU4_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
9776#define CGTS_CU4_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
9777#define CGTS_CU4_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
9778#define CGTS_CU4_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
9779#define CGTS_CU4_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
9780#define CGTS_CU4_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
9781#define CGTS_CU4_SP1_CTRL_REG__SP11_MASK 0x7f0000
9782#define CGTS_CU4_SP1_CTRL_REG__SP11__SHIFT 0x10
9783#define CGTS_CU4_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
9784#define CGTS_CU4_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
9785#define CGTS_CU4_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
9786#define CGTS_CU4_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
9787#define CGTS_CU4_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
9788#define CGTS_CU4_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
9789#define CGTS_CU4_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
9790#define CGTS_CU4_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
9791#define CGTS_CU4_TD_TCP_CTRL_REG__TD_MASK 0x7f
9792#define CGTS_CU4_TD_TCP_CTRL_REG__TD__SHIFT 0x0
9793#define CGTS_CU4_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
9794#define CGTS_CU4_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
9795#define CGTS_CU4_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
9796#define CGTS_CU4_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
9797#define CGTS_CU4_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
9798#define CGTS_CU4_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
9799#define CGTS_CU4_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
9800#define CGTS_CU4_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
9801#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
9802#define CGTS_CU4_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
9803#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
9804#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
9805#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
9806#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
9807#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
9808#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
9809#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
9810#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
9811#define CGTS_CU5_SP0_CTRL_REG__SP00_MASK 0x7f
9812#define CGTS_CU5_SP0_CTRL_REG__SP00__SHIFT 0x0
9813#define CGTS_CU5_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
9814#define CGTS_CU5_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
9815#define CGTS_CU5_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
9816#define CGTS_CU5_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
9817#define CGTS_CU5_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
9818#define CGTS_CU5_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
9819#define CGTS_CU5_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
9820#define CGTS_CU5_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
9821#define CGTS_CU5_SP0_CTRL_REG__SP01_MASK 0x7f0000
9822#define CGTS_CU5_SP0_CTRL_REG__SP01__SHIFT 0x10
9823#define CGTS_CU5_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
9824#define CGTS_CU5_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
9825#define CGTS_CU5_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
9826#define CGTS_CU5_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
9827#define CGTS_CU5_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
9828#define CGTS_CU5_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
9829#define CGTS_CU5_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
9830#define CGTS_CU5_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
9831#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
9832#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
9833#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
9834#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
9835#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
9836#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
9837#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
9838#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
9839#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
9840#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
9841#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
9842#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
9843#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
9844#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
9845#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
9846#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
9847#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
9848#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
9849#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
9850#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
9851#define CGTS_CU5_TA_CTRL_REG__TA_MASK 0x7f
9852#define CGTS_CU5_TA_CTRL_REG__TA__SHIFT 0x0
9853#define CGTS_CU5_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
9854#define CGTS_CU5_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
9855#define CGTS_CU5_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
9856#define CGTS_CU5_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
9857#define CGTS_CU5_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
9858#define CGTS_CU5_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
9859#define CGTS_CU5_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
9860#define CGTS_CU5_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
9861#define CGTS_CU5_SP1_CTRL_REG__SP10_MASK 0x7f
9862#define CGTS_CU5_SP1_CTRL_REG__SP10__SHIFT 0x0
9863#define CGTS_CU5_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
9864#define CGTS_CU5_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
9865#define CGTS_CU5_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
9866#define CGTS_CU5_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
9867#define CGTS_CU5_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
9868#define CGTS_CU5_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
9869#define CGTS_CU5_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
9870#define CGTS_CU5_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
9871#define CGTS_CU5_SP1_CTRL_REG__SP11_MASK 0x7f0000
9872#define CGTS_CU5_SP1_CTRL_REG__SP11__SHIFT 0x10
9873#define CGTS_CU5_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
9874#define CGTS_CU5_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
9875#define CGTS_CU5_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
9876#define CGTS_CU5_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
9877#define CGTS_CU5_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
9878#define CGTS_CU5_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
9879#define CGTS_CU5_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
9880#define CGTS_CU5_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
9881#define CGTS_CU5_TD_TCP_CTRL_REG__TD_MASK 0x7f
9882#define CGTS_CU5_TD_TCP_CTRL_REG__TD__SHIFT 0x0
9883#define CGTS_CU5_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
9884#define CGTS_CU5_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
9885#define CGTS_CU5_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
9886#define CGTS_CU5_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
9887#define CGTS_CU5_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
9888#define CGTS_CU5_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
9889#define CGTS_CU5_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
9890#define CGTS_CU5_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
9891#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
9892#define CGTS_CU5_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
9893#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
9894#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
9895#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
9896#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
9897#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
9898#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
9899#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
9900#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
9901#define CGTS_CU6_SP0_CTRL_REG__SP00_MASK 0x7f
9902#define CGTS_CU6_SP0_CTRL_REG__SP00__SHIFT 0x0
9903#define CGTS_CU6_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
9904#define CGTS_CU6_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
9905#define CGTS_CU6_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
9906#define CGTS_CU6_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
9907#define CGTS_CU6_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
9908#define CGTS_CU6_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
9909#define CGTS_CU6_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
9910#define CGTS_CU6_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
9911#define CGTS_CU6_SP0_CTRL_REG__SP01_MASK 0x7f0000
9912#define CGTS_CU6_SP0_CTRL_REG__SP01__SHIFT 0x10
9913#define CGTS_CU6_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
9914#define CGTS_CU6_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
9915#define CGTS_CU6_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
9916#define CGTS_CU6_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
9917#define CGTS_CU6_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
9918#define CGTS_CU6_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
9919#define CGTS_CU6_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
9920#define CGTS_CU6_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
9921#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
9922#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
9923#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
9924#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
9925#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
9926#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
9927#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
9928#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
9929#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
9930#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
9931#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
9932#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
9933#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
9934#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
9935#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
9936#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
9937#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
9938#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
9939#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
9940#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
9941#define CGTS_CU6_TA_CTRL_REG__TA_MASK 0x7f
9942#define CGTS_CU6_TA_CTRL_REG__TA__SHIFT 0x0
9943#define CGTS_CU6_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
9944#define CGTS_CU6_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
9945#define CGTS_CU6_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
9946#define CGTS_CU6_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
9947#define CGTS_CU6_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
9948#define CGTS_CU6_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
9949#define CGTS_CU6_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
9950#define CGTS_CU6_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
9951#define CGTS_CU6_SP1_CTRL_REG__SP10_MASK 0x7f
9952#define CGTS_CU6_SP1_CTRL_REG__SP10__SHIFT 0x0
9953#define CGTS_CU6_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
9954#define CGTS_CU6_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
9955#define CGTS_CU6_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
9956#define CGTS_CU6_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
9957#define CGTS_CU6_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
9958#define CGTS_CU6_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
9959#define CGTS_CU6_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
9960#define CGTS_CU6_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
9961#define CGTS_CU6_SP1_CTRL_REG__SP11_MASK 0x7f0000
9962#define CGTS_CU6_SP1_CTRL_REG__SP11__SHIFT 0x10
9963#define CGTS_CU6_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
9964#define CGTS_CU6_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
9965#define CGTS_CU6_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
9966#define CGTS_CU6_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
9967#define CGTS_CU6_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
9968#define CGTS_CU6_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
9969#define CGTS_CU6_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
9970#define CGTS_CU6_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
9971#define CGTS_CU6_TD_TCP_CTRL_REG__TD_MASK 0x7f
9972#define CGTS_CU6_TD_TCP_CTRL_REG__TD__SHIFT 0x0
9973#define CGTS_CU6_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
9974#define CGTS_CU6_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
9975#define CGTS_CU6_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
9976#define CGTS_CU6_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
9977#define CGTS_CU6_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
9978#define CGTS_CU6_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
9979#define CGTS_CU6_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
9980#define CGTS_CU6_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
9981#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
9982#define CGTS_CU6_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
9983#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
9984#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
9985#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
9986#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
9987#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
9988#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
9989#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
9990#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
9991#define CGTS_CU7_SP0_CTRL_REG__SP00_MASK 0x7f
9992#define CGTS_CU7_SP0_CTRL_REG__SP00__SHIFT 0x0
9993#define CGTS_CU7_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
9994#define CGTS_CU7_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
9995#define CGTS_CU7_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
9996#define CGTS_CU7_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
9997#define CGTS_CU7_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
9998#define CGTS_CU7_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
9999#define CGTS_CU7_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
10000#define CGTS_CU7_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
10001#define CGTS_CU7_SP0_CTRL_REG__SP01_MASK 0x7f0000
10002#define CGTS_CU7_SP0_CTRL_REG__SP01__SHIFT 0x10
10003#define CGTS_CU7_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
10004#define CGTS_CU7_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
10005#define CGTS_CU7_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
10006#define CGTS_CU7_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
10007#define CGTS_CU7_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
10008#define CGTS_CU7_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
10009#define CGTS_CU7_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
10010#define CGTS_CU7_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
10011#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
10012#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
10013#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
10014#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
10015#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
10016#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
10017#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
10018#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
10019#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
10020#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
10021#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
10022#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
10023#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
10024#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
10025#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
10026#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
10027#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
10028#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
10029#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
10030#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
10031#define CGTS_CU7_TA_CTRL_REG__TA_MASK 0x7f
10032#define CGTS_CU7_TA_CTRL_REG__TA__SHIFT 0x0
10033#define CGTS_CU7_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
10034#define CGTS_CU7_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
10035#define CGTS_CU7_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
10036#define CGTS_CU7_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
10037#define CGTS_CU7_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
10038#define CGTS_CU7_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
10039#define CGTS_CU7_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
10040#define CGTS_CU7_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
10041#define CGTS_CU7_SP1_CTRL_REG__SP10_MASK 0x7f
10042#define CGTS_CU7_SP1_CTRL_REG__SP10__SHIFT 0x0
10043#define CGTS_CU7_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
10044#define CGTS_CU7_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
10045#define CGTS_CU7_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
10046#define CGTS_CU7_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
10047#define CGTS_CU7_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
10048#define CGTS_CU7_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
10049#define CGTS_CU7_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
10050#define CGTS_CU7_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
10051#define CGTS_CU7_SP1_CTRL_REG__SP11_MASK 0x7f0000
10052#define CGTS_CU7_SP1_CTRL_REG__SP11__SHIFT 0x10
10053#define CGTS_CU7_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
10054#define CGTS_CU7_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
10055#define CGTS_CU7_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
10056#define CGTS_CU7_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
10057#define CGTS_CU7_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
10058#define CGTS_CU7_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
10059#define CGTS_CU7_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
10060#define CGTS_CU7_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
10061#define CGTS_CU7_TD_TCP_CTRL_REG__TD_MASK 0x7f
10062#define CGTS_CU7_TD_TCP_CTRL_REG__TD__SHIFT 0x0
10063#define CGTS_CU7_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
10064#define CGTS_CU7_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
10065#define CGTS_CU7_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
10066#define CGTS_CU7_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
10067#define CGTS_CU7_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
10068#define CGTS_CU7_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
10069#define CGTS_CU7_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
10070#define CGTS_CU7_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
10071#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
10072#define CGTS_CU7_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
10073#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
10074#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
10075#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
10076#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
10077#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
10078#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
10079#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
10080#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
10081#define CGTS_CU8_SP0_CTRL_REG__SP00_MASK 0x7f
10082#define CGTS_CU8_SP0_CTRL_REG__SP00__SHIFT 0x0
10083#define CGTS_CU8_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
10084#define CGTS_CU8_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
10085#define CGTS_CU8_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
10086#define CGTS_CU8_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
10087#define CGTS_CU8_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
10088#define CGTS_CU8_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
10089#define CGTS_CU8_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
10090#define CGTS_CU8_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
10091#define CGTS_CU8_SP0_CTRL_REG__SP01_MASK 0x7f0000
10092#define CGTS_CU8_SP0_CTRL_REG__SP01__SHIFT 0x10
10093#define CGTS_CU8_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
10094#define CGTS_CU8_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
10095#define CGTS_CU8_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
10096#define CGTS_CU8_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
10097#define CGTS_CU8_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
10098#define CGTS_CU8_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
10099#define CGTS_CU8_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
10100#define CGTS_CU8_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
10101#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
10102#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
10103#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
10104#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
10105#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
10106#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
10107#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
10108#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
10109#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
10110#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
10111#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
10112#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
10113#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
10114#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
10115#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
10116#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
10117#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
10118#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
10119#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
10120#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
10121#define CGTS_CU8_TA_SQC_CTRL_REG__TA_MASK 0x7f
10122#define CGTS_CU8_TA_SQC_CTRL_REG__TA__SHIFT 0x0
10123#define CGTS_CU8_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x80
10124#define CGTS_CU8_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
10125#define CGTS_CU8_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
10126#define CGTS_CU8_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
10127#define CGTS_CU8_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
10128#define CGTS_CU8_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
10129#define CGTS_CU8_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
10130#define CGTS_CU8_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
10131#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_MASK 0x7f0000
10132#define CGTS_CU8_TA_SQC_CTRL_REG__SQC__SHIFT 0x10
10133#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x800000
10134#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17
10135#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x3000000
10136#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18
10137#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x4000000
10138#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a
10139#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x8000000
10140#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b
10141#define CGTS_CU8_SP1_CTRL_REG__SP10_MASK 0x7f
10142#define CGTS_CU8_SP1_CTRL_REG__SP10__SHIFT 0x0
10143#define CGTS_CU8_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
10144#define CGTS_CU8_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
10145#define CGTS_CU8_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
10146#define CGTS_CU8_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
10147#define CGTS_CU8_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
10148#define CGTS_CU8_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
10149#define CGTS_CU8_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
10150#define CGTS_CU8_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
10151#define CGTS_CU8_SP1_CTRL_REG__SP11_MASK 0x7f0000
10152#define CGTS_CU8_SP1_CTRL_REG__SP11__SHIFT 0x10
10153#define CGTS_CU8_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
10154#define CGTS_CU8_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
10155#define CGTS_CU8_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
10156#define CGTS_CU8_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
10157#define CGTS_CU8_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
10158#define CGTS_CU8_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
10159#define CGTS_CU8_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
10160#define CGTS_CU8_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
10161#define CGTS_CU8_TD_TCP_CTRL_REG__TD_MASK 0x7f
10162#define CGTS_CU8_TD_TCP_CTRL_REG__TD__SHIFT 0x0
10163#define CGTS_CU8_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
10164#define CGTS_CU8_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
10165#define CGTS_CU8_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
10166#define CGTS_CU8_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
10167#define CGTS_CU8_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
10168#define CGTS_CU8_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
10169#define CGTS_CU8_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
10170#define CGTS_CU8_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
10171#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
10172#define CGTS_CU8_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
10173#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
10174#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
10175#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
10176#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
10177#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
10178#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
10179#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
10180#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
10181#define CGTS_CU9_SP0_CTRL_REG__SP00_MASK 0x7f
10182#define CGTS_CU9_SP0_CTRL_REG__SP00__SHIFT 0x0
10183#define CGTS_CU9_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
10184#define CGTS_CU9_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
10185#define CGTS_CU9_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
10186#define CGTS_CU9_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
10187#define CGTS_CU9_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
10188#define CGTS_CU9_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
10189#define CGTS_CU9_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
10190#define CGTS_CU9_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
10191#define CGTS_CU9_SP0_CTRL_REG__SP01_MASK 0x7f0000
10192#define CGTS_CU9_SP0_CTRL_REG__SP01__SHIFT 0x10
10193#define CGTS_CU9_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
10194#define CGTS_CU9_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
10195#define CGTS_CU9_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
10196#define CGTS_CU9_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
10197#define CGTS_CU9_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
10198#define CGTS_CU9_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
10199#define CGTS_CU9_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
10200#define CGTS_CU9_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
10201#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
10202#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
10203#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
10204#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
10205#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
10206#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
10207#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
10208#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
10209#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
10210#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
10211#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
10212#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
10213#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
10214#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
10215#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
10216#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
10217#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
10218#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
10219#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
10220#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
10221#define CGTS_CU9_TA_CTRL_REG__TA_MASK 0x7f
10222#define CGTS_CU9_TA_CTRL_REG__TA__SHIFT 0x0
10223#define CGTS_CU9_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
10224#define CGTS_CU9_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
10225#define CGTS_CU9_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
10226#define CGTS_CU9_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
10227#define CGTS_CU9_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
10228#define CGTS_CU9_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
10229#define CGTS_CU9_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
10230#define CGTS_CU9_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
10231#define CGTS_CU9_SP1_CTRL_REG__SP10_MASK 0x7f
10232#define CGTS_CU9_SP1_CTRL_REG__SP10__SHIFT 0x0
10233#define CGTS_CU9_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
10234#define CGTS_CU9_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
10235#define CGTS_CU9_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
10236#define CGTS_CU9_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
10237#define CGTS_CU9_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
10238#define CGTS_CU9_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
10239#define CGTS_CU9_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
10240#define CGTS_CU9_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
10241#define CGTS_CU9_SP1_CTRL_REG__SP11_MASK 0x7f0000
10242#define CGTS_CU9_SP1_CTRL_REG__SP11__SHIFT 0x10
10243#define CGTS_CU9_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
10244#define CGTS_CU9_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
10245#define CGTS_CU9_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
10246#define CGTS_CU9_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
10247#define CGTS_CU9_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
10248#define CGTS_CU9_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
10249#define CGTS_CU9_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
10250#define CGTS_CU9_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
10251#define CGTS_CU9_TD_TCP_CTRL_REG__TD_MASK 0x7f
10252#define CGTS_CU9_TD_TCP_CTRL_REG__TD__SHIFT 0x0
10253#define CGTS_CU9_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
10254#define CGTS_CU9_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
10255#define CGTS_CU9_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
10256#define CGTS_CU9_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
10257#define CGTS_CU9_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
10258#define CGTS_CU9_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
10259#define CGTS_CU9_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
10260#define CGTS_CU9_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
10261#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
10262#define CGTS_CU9_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
10263#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
10264#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
10265#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
10266#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
10267#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
10268#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
10269#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
10270#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
10271#define CGTS_CU10_SP0_CTRL_REG__SP00_MASK 0x7f
10272#define CGTS_CU10_SP0_CTRL_REG__SP00__SHIFT 0x0
10273#define CGTS_CU10_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
10274#define CGTS_CU10_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
10275#define CGTS_CU10_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
10276#define CGTS_CU10_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
10277#define CGTS_CU10_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
10278#define CGTS_CU10_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
10279#define CGTS_CU10_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
10280#define CGTS_CU10_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
10281#define CGTS_CU10_SP0_CTRL_REG__SP01_MASK 0x7f0000
10282#define CGTS_CU10_SP0_CTRL_REG__SP01__SHIFT 0x10
10283#define CGTS_CU10_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
10284#define CGTS_CU10_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
10285#define CGTS_CU10_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
10286#define CGTS_CU10_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
10287#define CGTS_CU10_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
10288#define CGTS_CU10_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
10289#define CGTS_CU10_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
10290#define CGTS_CU10_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
10291#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
10292#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
10293#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
10294#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
10295#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
10296#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
10297#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
10298#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
10299#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
10300#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
10301#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
10302#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
10303#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
10304#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
10305#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
10306#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
10307#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
10308#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
10309#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
10310#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
10311#define CGTS_CU10_TA_CTRL_REG__TA_MASK 0x7f
10312#define CGTS_CU10_TA_CTRL_REG__TA__SHIFT 0x0
10313#define CGTS_CU10_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
10314#define CGTS_CU10_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
10315#define CGTS_CU10_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
10316#define CGTS_CU10_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
10317#define CGTS_CU10_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
10318#define CGTS_CU10_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
10319#define CGTS_CU10_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
10320#define CGTS_CU10_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
10321#define CGTS_CU10_SP1_CTRL_REG__SP10_MASK 0x7f
10322#define CGTS_CU10_SP1_CTRL_REG__SP10__SHIFT 0x0
10323#define CGTS_CU10_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
10324#define CGTS_CU10_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
10325#define CGTS_CU10_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
10326#define CGTS_CU10_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
10327#define CGTS_CU10_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
10328#define CGTS_CU10_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
10329#define CGTS_CU10_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
10330#define CGTS_CU10_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
10331#define CGTS_CU10_SP1_CTRL_REG__SP11_MASK 0x7f0000
10332#define CGTS_CU10_SP1_CTRL_REG__SP11__SHIFT 0x10
10333#define CGTS_CU10_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
10334#define CGTS_CU10_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
10335#define CGTS_CU10_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
10336#define CGTS_CU10_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
10337#define CGTS_CU10_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
10338#define CGTS_CU10_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
10339#define CGTS_CU10_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
10340#define CGTS_CU10_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
10341#define CGTS_CU10_TD_TCP_CTRL_REG__TD_MASK 0x7f
10342#define CGTS_CU10_TD_TCP_CTRL_REG__TD__SHIFT 0x0
10343#define CGTS_CU10_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
10344#define CGTS_CU10_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
10345#define CGTS_CU10_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
10346#define CGTS_CU10_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
10347#define CGTS_CU10_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
10348#define CGTS_CU10_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
10349#define CGTS_CU10_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
10350#define CGTS_CU10_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
10351#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
10352#define CGTS_CU10_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
10353#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
10354#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
10355#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
10356#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
10357#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
10358#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
10359#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
10360#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
10361#define CGTS_CU11_SP0_CTRL_REG__SP00_MASK 0x7f
10362#define CGTS_CU11_SP0_CTRL_REG__SP00__SHIFT 0x0
10363#define CGTS_CU11_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
10364#define CGTS_CU11_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
10365#define CGTS_CU11_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
10366#define CGTS_CU11_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
10367#define CGTS_CU11_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
10368#define CGTS_CU11_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
10369#define CGTS_CU11_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
10370#define CGTS_CU11_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
10371#define CGTS_CU11_SP0_CTRL_REG__SP01_MASK 0x7f0000
10372#define CGTS_CU11_SP0_CTRL_REG__SP01__SHIFT 0x10
10373#define CGTS_CU11_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
10374#define CGTS_CU11_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
10375#define CGTS_CU11_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
10376#define CGTS_CU11_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
10377#define CGTS_CU11_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
10378#define CGTS_CU11_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
10379#define CGTS_CU11_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
10380#define CGTS_CU11_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
10381#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
10382#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
10383#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
10384#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
10385#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
10386#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
10387#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
10388#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
10389#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
10390#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
10391#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
10392#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
10393#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
10394#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
10395#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
10396#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
10397#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
10398#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
10399#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
10400#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
10401#define CGTS_CU11_TA_CTRL_REG__TA_MASK 0x7f
10402#define CGTS_CU11_TA_CTRL_REG__TA__SHIFT 0x0
10403#define CGTS_CU11_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
10404#define CGTS_CU11_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
10405#define CGTS_CU11_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
10406#define CGTS_CU11_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
10407#define CGTS_CU11_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
10408#define CGTS_CU11_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
10409#define CGTS_CU11_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
10410#define CGTS_CU11_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
10411#define CGTS_CU11_SP1_CTRL_REG__SP10_MASK 0x7f
10412#define CGTS_CU11_SP1_CTRL_REG__SP10__SHIFT 0x0
10413#define CGTS_CU11_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
10414#define CGTS_CU11_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
10415#define CGTS_CU11_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
10416#define CGTS_CU11_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
10417#define CGTS_CU11_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
10418#define CGTS_CU11_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
10419#define CGTS_CU11_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
10420#define CGTS_CU11_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
10421#define CGTS_CU11_SP1_CTRL_REG__SP11_MASK 0x7f0000
10422#define CGTS_CU11_SP1_CTRL_REG__SP11__SHIFT 0x10
10423#define CGTS_CU11_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
10424#define CGTS_CU11_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
10425#define CGTS_CU11_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
10426#define CGTS_CU11_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
10427#define CGTS_CU11_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
10428#define CGTS_CU11_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
10429#define CGTS_CU11_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
10430#define CGTS_CU11_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
10431#define CGTS_CU11_TD_TCP_CTRL_REG__TD_MASK 0x7f
10432#define CGTS_CU11_TD_TCP_CTRL_REG__TD__SHIFT 0x0
10433#define CGTS_CU11_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
10434#define CGTS_CU11_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
10435#define CGTS_CU11_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
10436#define CGTS_CU11_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
10437#define CGTS_CU11_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
10438#define CGTS_CU11_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
10439#define CGTS_CU11_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
10440#define CGTS_CU11_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
10441#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
10442#define CGTS_CU11_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
10443#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
10444#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
10445#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
10446#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
10447#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
10448#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
10449#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
10450#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
10451#define CGTS_CU12_SP0_CTRL_REG__SP00_MASK 0x7f
10452#define CGTS_CU12_SP0_CTRL_REG__SP00__SHIFT 0x0
10453#define CGTS_CU12_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
10454#define CGTS_CU12_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
10455#define CGTS_CU12_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
10456#define CGTS_CU12_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
10457#define CGTS_CU12_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
10458#define CGTS_CU12_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
10459#define CGTS_CU12_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
10460#define CGTS_CU12_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
10461#define CGTS_CU12_SP0_CTRL_REG__SP01_MASK 0x7f0000
10462#define CGTS_CU12_SP0_CTRL_REG__SP01__SHIFT 0x10
10463#define CGTS_CU12_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
10464#define CGTS_CU12_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
10465#define CGTS_CU12_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
10466#define CGTS_CU12_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
10467#define CGTS_CU12_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
10468#define CGTS_CU12_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
10469#define CGTS_CU12_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
10470#define CGTS_CU12_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
10471#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
10472#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
10473#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
10474#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
10475#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
10476#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
10477#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
10478#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
10479#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
10480#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
10481#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
10482#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
10483#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
10484#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
10485#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
10486#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
10487#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
10488#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
10489#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
10490#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
10491#define CGTS_CU12_TA_SQC_CTRL_REG__TA_MASK 0x7f
10492#define CGTS_CU12_TA_SQC_CTRL_REG__TA__SHIFT 0x0
10493#define CGTS_CU12_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x80
10494#define CGTS_CU12_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
10495#define CGTS_CU12_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
10496#define CGTS_CU12_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
10497#define CGTS_CU12_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
10498#define CGTS_CU12_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
10499#define CGTS_CU12_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
10500#define CGTS_CU12_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
10501#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_MASK 0x7f0000
10502#define CGTS_CU12_TA_SQC_CTRL_REG__SQC__SHIFT 0x10
10503#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x800000
10504#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17
10505#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x3000000
10506#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18
10507#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x4000000
10508#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a
10509#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x8000000
10510#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b
10511#define CGTS_CU12_SP1_CTRL_REG__SP10_MASK 0x7f
10512#define CGTS_CU12_SP1_CTRL_REG__SP10__SHIFT 0x0
10513#define CGTS_CU12_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
10514#define CGTS_CU12_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
10515#define CGTS_CU12_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
10516#define CGTS_CU12_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
10517#define CGTS_CU12_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
10518#define CGTS_CU12_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
10519#define CGTS_CU12_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
10520#define CGTS_CU12_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
10521#define CGTS_CU12_SP1_CTRL_REG__SP11_MASK 0x7f0000
10522#define CGTS_CU12_SP1_CTRL_REG__SP11__SHIFT 0x10
10523#define CGTS_CU12_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
10524#define CGTS_CU12_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
10525#define CGTS_CU12_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
10526#define CGTS_CU12_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
10527#define CGTS_CU12_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
10528#define CGTS_CU12_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
10529#define CGTS_CU12_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
10530#define CGTS_CU12_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
10531#define CGTS_CU12_TD_TCP_CTRL_REG__TD_MASK 0x7f
10532#define CGTS_CU12_TD_TCP_CTRL_REG__TD__SHIFT 0x0
10533#define CGTS_CU12_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
10534#define CGTS_CU12_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
10535#define CGTS_CU12_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
10536#define CGTS_CU12_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
10537#define CGTS_CU12_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
10538#define CGTS_CU12_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
10539#define CGTS_CU12_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
10540#define CGTS_CU12_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
10541#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
10542#define CGTS_CU12_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
10543#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
10544#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
10545#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
10546#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
10547#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
10548#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
10549#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
10550#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
10551#define CGTS_CU13_SP0_CTRL_REG__SP00_MASK 0x7f
10552#define CGTS_CU13_SP0_CTRL_REG__SP00__SHIFT 0x0
10553#define CGTS_CU13_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
10554#define CGTS_CU13_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
10555#define CGTS_CU13_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
10556#define CGTS_CU13_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
10557#define CGTS_CU13_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
10558#define CGTS_CU13_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
10559#define CGTS_CU13_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
10560#define CGTS_CU13_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
10561#define CGTS_CU13_SP0_CTRL_REG__SP01_MASK 0x7f0000
10562#define CGTS_CU13_SP0_CTRL_REG__SP01__SHIFT 0x10
10563#define CGTS_CU13_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
10564#define CGTS_CU13_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
10565#define CGTS_CU13_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
10566#define CGTS_CU13_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
10567#define CGTS_CU13_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
10568#define CGTS_CU13_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
10569#define CGTS_CU13_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
10570#define CGTS_CU13_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
10571#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
10572#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
10573#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
10574#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
10575#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
10576#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
10577#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
10578#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
10579#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
10580#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
10581#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
10582#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
10583#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
10584#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
10585#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
10586#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
10587#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
10588#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
10589#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
10590#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
10591#define CGTS_CU13_TA_CTRL_REG__TA_MASK 0x7f
10592#define CGTS_CU13_TA_CTRL_REG__TA__SHIFT 0x0
10593#define CGTS_CU13_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
10594#define CGTS_CU13_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
10595#define CGTS_CU13_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
10596#define CGTS_CU13_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
10597#define CGTS_CU13_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
10598#define CGTS_CU13_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
10599#define CGTS_CU13_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
10600#define CGTS_CU13_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
10601#define CGTS_CU13_SP1_CTRL_REG__SP10_MASK 0x7f
10602#define CGTS_CU13_SP1_CTRL_REG__SP10__SHIFT 0x0
10603#define CGTS_CU13_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
10604#define CGTS_CU13_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
10605#define CGTS_CU13_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
10606#define CGTS_CU13_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
10607#define CGTS_CU13_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
10608#define CGTS_CU13_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
10609#define CGTS_CU13_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
10610#define CGTS_CU13_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
10611#define CGTS_CU13_SP1_CTRL_REG__SP11_MASK 0x7f0000
10612#define CGTS_CU13_SP1_CTRL_REG__SP11__SHIFT 0x10
10613#define CGTS_CU13_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
10614#define CGTS_CU13_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
10615#define CGTS_CU13_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
10616#define CGTS_CU13_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
10617#define CGTS_CU13_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
10618#define CGTS_CU13_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
10619#define CGTS_CU13_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
10620#define CGTS_CU13_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
10621#define CGTS_CU13_TD_TCP_CTRL_REG__TD_MASK 0x7f
10622#define CGTS_CU13_TD_TCP_CTRL_REG__TD__SHIFT 0x0
10623#define CGTS_CU13_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
10624#define CGTS_CU13_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
10625#define CGTS_CU13_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
10626#define CGTS_CU13_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
10627#define CGTS_CU13_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
10628#define CGTS_CU13_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
10629#define CGTS_CU13_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
10630#define CGTS_CU13_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
10631#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
10632#define CGTS_CU13_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
10633#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
10634#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
10635#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
10636#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
10637#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
10638#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
10639#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
10640#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
10641#define CGTS_CU14_SP0_CTRL_REG__SP00_MASK 0x7f
10642#define CGTS_CU14_SP0_CTRL_REG__SP00__SHIFT 0x0
10643#define CGTS_CU14_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
10644#define CGTS_CU14_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
10645#define CGTS_CU14_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
10646#define CGTS_CU14_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
10647#define CGTS_CU14_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
10648#define CGTS_CU14_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
10649#define CGTS_CU14_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
10650#define CGTS_CU14_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
10651#define CGTS_CU14_SP0_CTRL_REG__SP01_MASK 0x7f0000
10652#define CGTS_CU14_SP0_CTRL_REG__SP01__SHIFT 0x10
10653#define CGTS_CU14_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
10654#define CGTS_CU14_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
10655#define CGTS_CU14_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
10656#define CGTS_CU14_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
10657#define CGTS_CU14_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
10658#define CGTS_CU14_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
10659#define CGTS_CU14_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
10660#define CGTS_CU14_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
10661#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
10662#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
10663#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
10664#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
10665#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
10666#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
10667#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
10668#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
10669#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
10670#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
10671#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
10672#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
10673#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
10674#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
10675#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
10676#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
10677#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
10678#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
10679#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
10680#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
10681#define CGTS_CU14_TA_CTRL_REG__TA_MASK 0x7f
10682#define CGTS_CU14_TA_CTRL_REG__TA__SHIFT 0x0
10683#define CGTS_CU14_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
10684#define CGTS_CU14_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
10685#define CGTS_CU14_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
10686#define CGTS_CU14_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
10687#define CGTS_CU14_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
10688#define CGTS_CU14_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
10689#define CGTS_CU14_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
10690#define CGTS_CU14_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
10691#define CGTS_CU14_SP1_CTRL_REG__SP10_MASK 0x7f
10692#define CGTS_CU14_SP1_CTRL_REG__SP10__SHIFT 0x0
10693#define CGTS_CU14_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
10694#define CGTS_CU14_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
10695#define CGTS_CU14_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
10696#define CGTS_CU14_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
10697#define CGTS_CU14_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
10698#define CGTS_CU14_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
10699#define CGTS_CU14_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
10700#define CGTS_CU14_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
10701#define CGTS_CU14_SP1_CTRL_REG__SP11_MASK 0x7f0000
10702#define CGTS_CU14_SP1_CTRL_REG__SP11__SHIFT 0x10
10703#define CGTS_CU14_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
10704#define CGTS_CU14_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
10705#define CGTS_CU14_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
10706#define CGTS_CU14_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
10707#define CGTS_CU14_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
10708#define CGTS_CU14_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
10709#define CGTS_CU14_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
10710#define CGTS_CU14_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
10711#define CGTS_CU14_TD_TCP_CTRL_REG__TD_MASK 0x7f
10712#define CGTS_CU14_TD_TCP_CTRL_REG__TD__SHIFT 0x0
10713#define CGTS_CU14_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
10714#define CGTS_CU14_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
10715#define CGTS_CU14_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
10716#define CGTS_CU14_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
10717#define CGTS_CU14_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
10718#define CGTS_CU14_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
10719#define CGTS_CU14_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
10720#define CGTS_CU14_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
10721#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
10722#define CGTS_CU14_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
10723#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
10724#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
10725#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
10726#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
10727#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
10728#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
10729#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
10730#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
10731#define CGTS_CU15_SP0_CTRL_REG__SP00_MASK 0x7f
10732#define CGTS_CU15_SP0_CTRL_REG__SP00__SHIFT 0x0
10733#define CGTS_CU15_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
10734#define CGTS_CU15_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
10735#define CGTS_CU15_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
10736#define CGTS_CU15_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
10737#define CGTS_CU15_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
10738#define CGTS_CU15_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
10739#define CGTS_CU15_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
10740#define CGTS_CU15_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
10741#define CGTS_CU15_SP0_CTRL_REG__SP01_MASK 0x7f0000
10742#define CGTS_CU15_SP0_CTRL_REG__SP01__SHIFT 0x10