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1/*
2 * GFX_8_0 Register documentation
3 *
4 * Copyright (C) 2014 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24#ifndef GFX_8_0_SH_MASK_H
25#define GFX_8_0_SH_MASK_H
26
27#define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28#define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29#define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30#define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31#define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32#define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33#define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34#define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35#define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
36#define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
37#define CB_DCC_CONTROL__OVERWRITE_COMBINER_MRT_SHARING_DISABLE_MASK 0x2
38#define CB_DCC_CONTROL__OVERWRITE_COMBINER_MRT_SHARING_DISABLE__SHIFT 0x1
39#define CB_DCC_CONTROL__OVERWRITE_COMBINER_WATERMARK_MASK 0x7c
40#define CB_DCC_CONTROL__OVERWRITE_COMBINER_WATERMARK__SHIFT 0x2
41#define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x8
42#define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x3
43#define CB_COLOR_CONTROL__MODE_MASK 0x70
44#define CB_COLOR_CONTROL__MODE__SHIFT 0x4
45#define CB_COLOR_CONTROL__ROP3_MASK 0xff0000
46#define CB_COLOR_CONTROL__ROP3__SHIFT 0x10
47#define CB_BLEND0_CONTROL__COLOR_SRCBLEND_MASK 0x1f
48#define CB_BLEND0_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
49#define CB_BLEND0_CONTROL__COLOR_COMB_FCN_MASK 0xe0
50#define CB_BLEND0_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
51#define CB_BLEND0_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
52#define CB_BLEND0_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
53#define CB_BLEND0_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
54#define CB_BLEND0_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
55#define CB_BLEND0_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
56#define CB_BLEND0_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
57#define CB_BLEND0_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
58#define CB_BLEND0_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
59#define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
60#define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
61#define CB_BLEND0_CONTROL__ENABLE_MASK 0x40000000
62#define CB_BLEND0_CONTROL__ENABLE__SHIFT 0x1e
63#define CB_BLEND0_CONTROL__DISABLE_ROP3_MASK 0x80000000
64#define CB_BLEND0_CONTROL__DISABLE_ROP3__SHIFT 0x1f
65#define CB_BLEND1_CONTROL__COLOR_SRCBLEND_MASK 0x1f
66#define CB_BLEND1_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
67#define CB_BLEND1_CONTROL__COLOR_COMB_FCN_MASK 0xe0
68#define CB_BLEND1_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
69#define CB_BLEND1_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
70#define CB_BLEND1_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
71#define CB_BLEND1_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
72#define CB_BLEND1_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
73#define CB_BLEND1_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
74#define CB_BLEND1_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
75#define CB_BLEND1_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
76#define CB_BLEND1_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
77#define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
78#define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
79#define CB_BLEND1_CONTROL__ENABLE_MASK 0x40000000
80#define CB_BLEND1_CONTROL__ENABLE__SHIFT 0x1e
81#define CB_BLEND1_CONTROL__DISABLE_ROP3_MASK 0x80000000
82#define CB_BLEND1_CONTROL__DISABLE_ROP3__SHIFT 0x1f
83#define CB_BLEND2_CONTROL__COLOR_SRCBLEND_MASK 0x1f
84#define CB_BLEND2_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
85#define CB_BLEND2_CONTROL__COLOR_COMB_FCN_MASK 0xe0
86#define CB_BLEND2_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
87#define CB_BLEND2_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
88#define CB_BLEND2_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
89#define CB_BLEND2_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
90#define CB_BLEND2_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
91#define CB_BLEND2_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
92#define CB_BLEND2_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
93#define CB_BLEND2_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
94#define CB_BLEND2_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
95#define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
96#define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
97#define CB_BLEND2_CONTROL__ENABLE_MASK 0x40000000
98#define CB_BLEND2_CONTROL__ENABLE__SHIFT 0x1e
99#define CB_BLEND2_CONTROL__DISABLE_ROP3_MASK 0x80000000
100#define CB_BLEND2_CONTROL__DISABLE_ROP3__SHIFT 0x1f
101#define CB_BLEND3_CONTROL__COLOR_SRCBLEND_MASK 0x1f
102#define CB_BLEND3_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
103#define CB_BLEND3_CONTROL__COLOR_COMB_FCN_MASK 0xe0
104#define CB_BLEND3_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
105#define CB_BLEND3_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
106#define CB_BLEND3_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
107#define CB_BLEND3_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
108#define CB_BLEND3_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
109#define CB_BLEND3_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
110#define CB_BLEND3_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
111#define CB_BLEND3_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
112#define CB_BLEND3_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
113#define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
114#define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
115#define CB_BLEND3_CONTROL__ENABLE_MASK 0x40000000
116#define CB_BLEND3_CONTROL__ENABLE__SHIFT 0x1e
117#define CB_BLEND3_CONTROL__DISABLE_ROP3_MASK 0x80000000
118#define CB_BLEND3_CONTROL__DISABLE_ROP3__SHIFT 0x1f
119#define CB_BLEND4_CONTROL__COLOR_SRCBLEND_MASK 0x1f
120#define CB_BLEND4_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
121#define CB_BLEND4_CONTROL__COLOR_COMB_FCN_MASK 0xe0
122#define CB_BLEND4_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
123#define CB_BLEND4_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
124#define CB_BLEND4_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
125#define CB_BLEND4_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
126#define CB_BLEND4_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
127#define CB_BLEND4_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
128#define CB_BLEND4_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
129#define CB_BLEND4_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
130#define CB_BLEND4_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
131#define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
132#define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
133#define CB_BLEND4_CONTROL__ENABLE_MASK 0x40000000
134#define CB_BLEND4_CONTROL__ENABLE__SHIFT 0x1e
135#define CB_BLEND4_CONTROL__DISABLE_ROP3_MASK 0x80000000
136#define CB_BLEND4_CONTROL__DISABLE_ROP3__SHIFT 0x1f
137#define CB_BLEND5_CONTROL__COLOR_SRCBLEND_MASK 0x1f
138#define CB_BLEND5_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
139#define CB_BLEND5_CONTROL__COLOR_COMB_FCN_MASK 0xe0
140#define CB_BLEND5_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
141#define CB_BLEND5_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
142#define CB_BLEND5_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
143#define CB_BLEND5_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
144#define CB_BLEND5_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
145#define CB_BLEND5_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
146#define CB_BLEND5_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
147#define CB_BLEND5_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
148#define CB_BLEND5_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
149#define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
150#define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
151#define CB_BLEND5_CONTROL__ENABLE_MASK 0x40000000
152#define CB_BLEND5_CONTROL__ENABLE__SHIFT 0x1e
153#define CB_BLEND5_CONTROL__DISABLE_ROP3_MASK 0x80000000
154#define CB_BLEND5_CONTROL__DISABLE_ROP3__SHIFT 0x1f
155#define CB_BLEND6_CONTROL__COLOR_SRCBLEND_MASK 0x1f
156#define CB_BLEND6_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
157#define CB_BLEND6_CONTROL__COLOR_COMB_FCN_MASK 0xe0
158#define CB_BLEND6_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
159#define CB_BLEND6_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
160#define CB_BLEND6_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
161#define CB_BLEND6_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
162#define CB_BLEND6_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
163#define CB_BLEND6_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
164#define CB_BLEND6_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
165#define CB_BLEND6_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
166#define CB_BLEND6_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
167#define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
168#define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
169#define CB_BLEND6_CONTROL__ENABLE_MASK 0x40000000
170#define CB_BLEND6_CONTROL__ENABLE__SHIFT 0x1e
171#define CB_BLEND6_CONTROL__DISABLE_ROP3_MASK 0x80000000
172#define CB_BLEND6_CONTROL__DISABLE_ROP3__SHIFT 0x1f
173#define CB_BLEND7_CONTROL__COLOR_SRCBLEND_MASK 0x1f
174#define CB_BLEND7_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
175#define CB_BLEND7_CONTROL__COLOR_COMB_FCN_MASK 0xe0
176#define CB_BLEND7_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
177#define CB_BLEND7_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
178#define CB_BLEND7_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
179#define CB_BLEND7_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
180#define CB_BLEND7_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
181#define CB_BLEND7_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
182#define CB_BLEND7_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
183#define CB_BLEND7_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
184#define CB_BLEND7_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
185#define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
186#define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
187#define CB_BLEND7_CONTROL__ENABLE_MASK 0x40000000
188#define CB_BLEND7_CONTROL__ENABLE__SHIFT 0x1e
189#define CB_BLEND7_CONTROL__DISABLE_ROP3_MASK 0x80000000
190#define CB_BLEND7_CONTROL__DISABLE_ROP3__SHIFT 0x1f
191#define CB_COLOR0_BASE__BASE_256B_MASK 0xffffffff
192#define CB_COLOR0_BASE__BASE_256B__SHIFT 0x0
193#define CB_COLOR1_BASE__BASE_256B_MASK 0xffffffff
194#define CB_COLOR1_BASE__BASE_256B__SHIFT 0x0
195#define CB_COLOR2_BASE__BASE_256B_MASK 0xffffffff
196#define CB_COLOR2_BASE__BASE_256B__SHIFT 0x0
197#define CB_COLOR3_BASE__BASE_256B_MASK 0xffffffff
198#define CB_COLOR3_BASE__BASE_256B__SHIFT 0x0
199#define CB_COLOR4_BASE__BASE_256B_MASK 0xffffffff
200#define CB_COLOR4_BASE__BASE_256B__SHIFT 0x0
201#define CB_COLOR5_BASE__BASE_256B_MASK 0xffffffff
202#define CB_COLOR5_BASE__BASE_256B__SHIFT 0x0
203#define CB_COLOR6_BASE__BASE_256B_MASK 0xffffffff
204#define CB_COLOR6_BASE__BASE_256B__SHIFT 0x0
205#define CB_COLOR7_BASE__BASE_256B_MASK 0xffffffff
206#define CB_COLOR7_BASE__BASE_256B__SHIFT 0x0
207#define CB_COLOR0_PITCH__TILE_MAX_MASK 0x7ff
208#define CB_COLOR0_PITCH__TILE_MAX__SHIFT 0x0
209#define CB_COLOR0_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
210#define CB_COLOR0_PITCH__FMASK_TILE_MAX__SHIFT 0x14
211#define CB_COLOR1_PITCH__TILE_MAX_MASK 0x7ff
212#define CB_COLOR1_PITCH__TILE_MAX__SHIFT 0x0
213#define CB_COLOR1_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
214#define CB_COLOR1_PITCH__FMASK_TILE_MAX__SHIFT 0x14
215#define CB_COLOR2_PITCH__TILE_MAX_MASK 0x7ff
216#define CB_COLOR2_PITCH__TILE_MAX__SHIFT 0x0
217#define CB_COLOR2_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
218#define CB_COLOR2_PITCH__FMASK_TILE_MAX__SHIFT 0x14
219#define CB_COLOR3_PITCH__TILE_MAX_MASK 0x7ff
220#define CB_COLOR3_PITCH__TILE_MAX__SHIFT 0x0
221#define CB_COLOR3_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
222#define CB_COLOR3_PITCH__FMASK_TILE_MAX__SHIFT 0x14
223#define CB_COLOR4_PITCH__TILE_MAX_MASK 0x7ff
224#define CB_COLOR4_PITCH__TILE_MAX__SHIFT 0x0
225#define CB_COLOR4_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
226#define CB_COLOR4_PITCH__FMASK_TILE_MAX__SHIFT 0x14
227#define CB_COLOR5_PITCH__TILE_MAX_MASK 0x7ff
228#define CB_COLOR5_PITCH__TILE_MAX__SHIFT 0x0
229#define CB_COLOR5_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
230#define CB_COLOR5_PITCH__FMASK_TILE_MAX__SHIFT 0x14
231#define CB_COLOR6_PITCH__TILE_MAX_MASK 0x7ff
232#define CB_COLOR6_PITCH__TILE_MAX__SHIFT 0x0
233#define CB_COLOR6_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
234#define CB_COLOR6_PITCH__FMASK_TILE_MAX__SHIFT 0x14
235#define CB_COLOR7_PITCH__TILE_MAX_MASK 0x7ff
236#define CB_COLOR7_PITCH__TILE_MAX__SHIFT 0x0
237#define CB_COLOR7_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
238#define CB_COLOR7_PITCH__FMASK_TILE_MAX__SHIFT 0x14
239#define CB_COLOR0_SLICE__TILE_MAX_MASK 0x3fffff
240#define CB_COLOR0_SLICE__TILE_MAX__SHIFT 0x0
241#define CB_COLOR1_SLICE__TILE_MAX_MASK 0x3fffff
242#define CB_COLOR1_SLICE__TILE_MAX__SHIFT 0x0
243#define CB_COLOR2_SLICE__TILE_MAX_MASK 0x3fffff
244#define CB_COLOR2_SLICE__TILE_MAX__SHIFT 0x0
245#define CB_COLOR3_SLICE__TILE_MAX_MASK 0x3fffff
246#define CB_COLOR3_SLICE__TILE_MAX__SHIFT 0x0
247#define CB_COLOR4_SLICE__TILE_MAX_MASK 0x3fffff
248#define CB_COLOR4_SLICE__TILE_MAX__SHIFT 0x0
249#define CB_COLOR5_SLICE__TILE_MAX_MASK 0x3fffff
250#define CB_COLOR5_SLICE__TILE_MAX__SHIFT 0x0
251#define CB_COLOR6_SLICE__TILE_MAX_MASK 0x3fffff
252#define CB_COLOR6_SLICE__TILE_MAX__SHIFT 0x0
253#define CB_COLOR7_SLICE__TILE_MAX_MASK 0x3fffff
254#define CB_COLOR7_SLICE__TILE_MAX__SHIFT 0x0
255#define CB_COLOR0_VIEW__SLICE_START_MASK 0x7ff
256#define CB_COLOR0_VIEW__SLICE_START__SHIFT 0x0
257#define CB_COLOR0_VIEW__SLICE_MAX_MASK 0xffe000
258#define CB_COLOR0_VIEW__SLICE_MAX__SHIFT 0xd
259#define CB_COLOR1_VIEW__SLICE_START_MASK 0x7ff
260#define CB_COLOR1_VIEW__SLICE_START__SHIFT 0x0
261#define CB_COLOR1_VIEW__SLICE_MAX_MASK 0xffe000
262#define CB_COLOR1_VIEW__SLICE_MAX__SHIFT 0xd
263#define CB_COLOR2_VIEW__SLICE_START_MASK 0x7ff
264#define CB_COLOR2_VIEW__SLICE_START__SHIFT 0x0
265#define CB_COLOR2_VIEW__SLICE_MAX_MASK 0xffe000
266#define CB_COLOR2_VIEW__SLICE_MAX__SHIFT 0xd
267#define CB_COLOR3_VIEW__SLICE_START_MASK 0x7ff
268#define CB_COLOR3_VIEW__SLICE_START__SHIFT 0x0
269#define CB_COLOR3_VIEW__SLICE_MAX_MASK 0xffe000
270#define CB_COLOR3_VIEW__SLICE_MAX__SHIFT 0xd
271#define CB_COLOR4_VIEW__SLICE_START_MASK 0x7ff
272#define CB_COLOR4_VIEW__SLICE_START__SHIFT 0x0
273#define CB_COLOR4_VIEW__SLICE_MAX_MASK 0xffe000
274#define CB_COLOR4_VIEW__SLICE_MAX__SHIFT 0xd
275#define CB_COLOR5_VIEW__SLICE_START_MASK 0x7ff
276#define CB_COLOR5_VIEW__SLICE_START__SHIFT 0x0
277#define CB_COLOR5_VIEW__SLICE_MAX_MASK 0xffe000
278#define CB_COLOR5_VIEW__SLICE_MAX__SHIFT 0xd
279#define CB_COLOR6_VIEW__SLICE_START_MASK 0x7ff
280#define CB_COLOR6_VIEW__SLICE_START__SHIFT 0x0
281#define CB_COLOR6_VIEW__SLICE_MAX_MASK 0xffe000
282#define CB_COLOR6_VIEW__SLICE_MAX__SHIFT 0xd
283#define CB_COLOR7_VIEW__SLICE_START_MASK 0x7ff
284#define CB_COLOR7_VIEW__SLICE_START__SHIFT 0x0
285#define CB_COLOR7_VIEW__SLICE_MAX_MASK 0xffe000
286#define CB_COLOR7_VIEW__SLICE_MAX__SHIFT 0xd
287#define CB_COLOR0_INFO__ENDIAN_MASK 0x3
288#define CB_COLOR0_INFO__ENDIAN__SHIFT 0x0
289#define CB_COLOR0_INFO__FORMAT_MASK 0x7c
290#define CB_COLOR0_INFO__FORMAT__SHIFT 0x2
291#define CB_COLOR0_INFO__LINEAR_GENERAL_MASK 0x80
292#define CB_COLOR0_INFO__LINEAR_GENERAL__SHIFT 0x7
293#define CB_COLOR0_INFO__NUMBER_TYPE_MASK 0x700
294#define CB_COLOR0_INFO__NUMBER_TYPE__SHIFT 0x8
295#define CB_COLOR0_INFO__COMP_SWAP_MASK 0x1800
296#define CB_COLOR0_INFO__COMP_SWAP__SHIFT 0xb
297#define CB_COLOR0_INFO__FAST_CLEAR_MASK 0x2000
298#define CB_COLOR0_INFO__FAST_CLEAR__SHIFT 0xd
299#define CB_COLOR0_INFO__COMPRESSION_MASK 0x4000
300#define CB_COLOR0_INFO__COMPRESSION__SHIFT 0xe
301#define CB_COLOR0_INFO__BLEND_CLAMP_MASK 0x8000
302#define CB_COLOR0_INFO__BLEND_CLAMP__SHIFT 0xf
303#define CB_COLOR0_INFO__BLEND_BYPASS_MASK 0x10000
304#define CB_COLOR0_INFO__BLEND_BYPASS__SHIFT 0x10
305#define CB_COLOR0_INFO__SIMPLE_FLOAT_MASK 0x20000
306#define CB_COLOR0_INFO__SIMPLE_FLOAT__SHIFT 0x11
307#define CB_COLOR0_INFO__ROUND_MODE_MASK 0x40000
308#define CB_COLOR0_INFO__ROUND_MODE__SHIFT 0x12
309#define CB_COLOR0_INFO__CMASK_IS_LINEAR_MASK 0x80000
310#define CB_COLOR0_INFO__CMASK_IS_LINEAR__SHIFT 0x13
311#define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
312#define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
313#define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
314#define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
315#define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
316#define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
317#define CB_COLOR0_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000
318#define CB_COLOR0_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
319#define CB_COLOR0_INFO__DCC_ENABLE_MASK 0x10000000
320#define CB_COLOR0_INFO__DCC_ENABLE__SHIFT 0x1c
321#define CB_COLOR0_INFO__CMASK_ADDR_TYPE_MASK 0x60000000
322#define CB_COLOR0_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
323#define CB_COLOR1_INFO__ENDIAN_MASK 0x3
324#define CB_COLOR1_INFO__ENDIAN__SHIFT 0x0
325#define CB_COLOR1_INFO__FORMAT_MASK 0x7c
326#define CB_COLOR1_INFO__FORMAT__SHIFT 0x2
327#define CB_COLOR1_INFO__LINEAR_GENERAL_MASK 0x80
328#define CB_COLOR1_INFO__LINEAR_GENERAL__SHIFT 0x7
329#define CB_COLOR1_INFO__NUMBER_TYPE_MASK 0x700
330#define CB_COLOR1_INFO__NUMBER_TYPE__SHIFT 0x8
331#define CB_COLOR1_INFO__COMP_SWAP_MASK 0x1800
332#define CB_COLOR1_INFO__COMP_SWAP__SHIFT 0xb
333#define CB_COLOR1_INFO__FAST_CLEAR_MASK 0x2000
334#define CB_COLOR1_INFO__FAST_CLEAR__SHIFT 0xd
335#define CB_COLOR1_INFO__COMPRESSION_MASK 0x4000
336#define CB_COLOR1_INFO__COMPRESSION__SHIFT 0xe
337#define CB_COLOR1_INFO__BLEND_CLAMP_MASK 0x8000
338#define CB_COLOR1_INFO__BLEND_CLAMP__SHIFT 0xf
339#define CB_COLOR1_INFO__BLEND_BYPASS_MASK 0x10000
340#define CB_COLOR1_INFO__BLEND_BYPASS__SHIFT 0x10
341#define CB_COLOR1_INFO__SIMPLE_FLOAT_MASK 0x20000
342#define CB_COLOR1_INFO__SIMPLE_FLOAT__SHIFT 0x11
343#define CB_COLOR1_INFO__ROUND_MODE_MASK 0x40000
344#define CB_COLOR1_INFO__ROUND_MODE__SHIFT 0x12
345#define CB_COLOR1_INFO__CMASK_IS_LINEAR_MASK 0x80000
346#define CB_COLOR1_INFO__CMASK_IS_LINEAR__SHIFT 0x13
347#define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
348#define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
349#define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
350#define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
351#define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
352#define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
353#define CB_COLOR1_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000
354#define CB_COLOR1_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
355#define CB_COLOR1_INFO__DCC_ENABLE_MASK 0x10000000
356#define CB_COLOR1_INFO__DCC_ENABLE__SHIFT 0x1c
357#define CB_COLOR1_INFO__CMASK_ADDR_TYPE_MASK 0x60000000
358#define CB_COLOR1_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
359#define CB_COLOR2_INFO__ENDIAN_MASK 0x3
360#define CB_COLOR2_INFO__ENDIAN__SHIFT 0x0
361#define CB_COLOR2_INFO__FORMAT_MASK 0x7c
362#define CB_COLOR2_INFO__FORMAT__SHIFT 0x2
363#define CB_COLOR2_INFO__LINEAR_GENERAL_MASK 0x80
364#define CB_COLOR2_INFO__LINEAR_GENERAL__SHIFT 0x7
365#define CB_COLOR2_INFO__NUMBER_TYPE_MASK 0x700
366#define CB_COLOR2_INFO__NUMBER_TYPE__SHIFT 0x8
367#define CB_COLOR2_INFO__COMP_SWAP_MASK 0x1800
368#define CB_COLOR2_INFO__COMP_SWAP__SHIFT 0xb
369#define CB_COLOR2_INFO__FAST_CLEAR_MASK 0x2000
370#define CB_COLOR2_INFO__FAST_CLEAR__SHIFT 0xd
371#define CB_COLOR2_INFO__COMPRESSION_MASK 0x4000
372#define CB_COLOR2_INFO__COMPRESSION__SHIFT 0xe
373#define CB_COLOR2_INFO__BLEND_CLAMP_MASK 0x8000
374#define CB_COLOR2_INFO__BLEND_CLAMP__SHIFT 0xf
375#define CB_COLOR2_INFO__BLEND_BYPASS_MASK 0x10000
376#define CB_COLOR2_INFO__BLEND_BYPASS__SHIFT 0x10
377#define CB_COLOR2_INFO__SIMPLE_FLOAT_MASK 0x20000
378#define CB_COLOR2_INFO__SIMPLE_FLOAT__SHIFT 0x11
379#define CB_COLOR2_INFO__ROUND_MODE_MASK 0x40000
380#define CB_COLOR2_INFO__ROUND_MODE__SHIFT 0x12
381#define CB_COLOR2_INFO__CMASK_IS_LINEAR_MASK 0x80000
382#define CB_COLOR2_INFO__CMASK_IS_LINEAR__SHIFT 0x13
383#define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
384#define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
385#define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
386#define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
387#define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
388#define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
389#define CB_COLOR2_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000
390#define CB_COLOR2_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
391#define CB_COLOR2_INFO__DCC_ENABLE_MASK 0x10000000
392#define CB_COLOR2_INFO__DCC_ENABLE__SHIFT 0x1c
393#define CB_COLOR2_INFO__CMASK_ADDR_TYPE_MASK 0x60000000
394#define CB_COLOR2_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
395#define CB_COLOR3_INFO__ENDIAN_MASK 0x3
396#define CB_COLOR3_INFO__ENDIAN__SHIFT 0x0
397#define CB_COLOR3_INFO__FORMAT_MASK 0x7c
398#define CB_COLOR3_INFO__FORMAT__SHIFT 0x2
399#define CB_COLOR3_INFO__LINEAR_GENERAL_MASK 0x80
400#define CB_COLOR3_INFO__LINEAR_GENERAL__SHIFT 0x7
401#define CB_COLOR3_INFO__NUMBER_TYPE_MASK 0x700
402#define CB_COLOR3_INFO__NUMBER_TYPE__SHIFT 0x8
403#define CB_COLOR3_INFO__COMP_SWAP_MASK 0x1800
404#define CB_COLOR3_INFO__COMP_SWAP__SHIFT 0xb
405#define CB_COLOR3_INFO__FAST_CLEAR_MASK 0x2000
406#define CB_COLOR3_INFO__FAST_CLEAR__SHIFT 0xd
407#define CB_COLOR3_INFO__COMPRESSION_MASK 0x4000
408#define CB_COLOR3_INFO__COMPRESSION__SHIFT 0xe
409#define CB_COLOR3_INFO__BLEND_CLAMP_MASK 0x8000
410#define CB_COLOR3_INFO__BLEND_CLAMP__SHIFT 0xf
411#define CB_COLOR3_INFO__BLEND_BYPASS_MASK 0x10000
412#define CB_COLOR3_INFO__BLEND_BYPASS__SHIFT 0x10
413#define CB_COLOR3_INFO__SIMPLE_FLOAT_MASK 0x20000
414#define CB_COLOR3_INFO__SIMPLE_FLOAT__SHIFT 0x11
415#define CB_COLOR3_INFO__ROUND_MODE_MASK 0x40000
416#define CB_COLOR3_INFO__ROUND_MODE__SHIFT 0x12
417#define CB_COLOR3_INFO__CMASK_IS_LINEAR_MASK 0x80000
418#define CB_COLOR3_INFO__CMASK_IS_LINEAR__SHIFT 0x13
419#define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
420#define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
421#define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
422#define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
423#define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
424#define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
425#define CB_COLOR3_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000
426#define CB_COLOR3_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
427#define CB_COLOR3_INFO__DCC_ENABLE_MASK 0x10000000
428#define CB_COLOR3_INFO__DCC_ENABLE__SHIFT 0x1c
429#define CB_COLOR3_INFO__CMASK_ADDR_TYPE_MASK 0x60000000
430#define CB_COLOR3_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
431#define CB_COLOR4_INFO__ENDIAN_MASK 0x3
432#define CB_COLOR4_INFO__ENDIAN__SHIFT 0x0
433#define CB_COLOR4_INFO__FORMAT_MASK 0x7c
434#define CB_COLOR4_INFO__FORMAT__SHIFT 0x2
435#define CB_COLOR4_INFO__LINEAR_GENERAL_MASK 0x80
436#define CB_COLOR4_INFO__LINEAR_GENERAL__SHIFT 0x7
437#define CB_COLOR4_INFO__NUMBER_TYPE_MASK 0x700
438#define CB_COLOR4_INFO__NUMBER_TYPE__SHIFT 0x8
439#define CB_COLOR4_INFO__COMP_SWAP_MASK 0x1800
440#define CB_COLOR4_INFO__COMP_SWAP__SHIFT 0xb
441#define CB_COLOR4_INFO__FAST_CLEAR_MASK 0x2000
442#define CB_COLOR4_INFO__FAST_CLEAR__SHIFT 0xd
443#define CB_COLOR4_INFO__COMPRESSION_MASK 0x4000
444#define CB_COLOR4_INFO__COMPRESSION__SHIFT 0xe
445#define CB_COLOR4_INFO__BLEND_CLAMP_MASK 0x8000
446#define CB_COLOR4_INFO__BLEND_CLAMP__SHIFT 0xf
447#define CB_COLOR4_INFO__BLEND_BYPASS_MASK 0x10000
448#define CB_COLOR4_INFO__BLEND_BYPASS__SHIFT 0x10
449#define CB_COLOR4_INFO__SIMPLE_FLOAT_MASK 0x20000
450#define CB_COLOR4_INFO__SIMPLE_FLOAT__SHIFT 0x11
451#define CB_COLOR4_INFO__ROUND_MODE_MASK 0x40000
452#define CB_COLOR4_INFO__ROUND_MODE__SHIFT 0x12
453#define CB_COLOR4_INFO__CMASK_IS_LINEAR_MASK 0x80000
454#define CB_COLOR4_INFO__CMASK_IS_LINEAR__SHIFT 0x13
455#define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
456#define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
457#define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
458#define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
459#define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
460#define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
461#define CB_COLOR4_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000
462#define CB_COLOR4_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
463#define CB_COLOR4_INFO__DCC_ENABLE_MASK 0x10000000
464#define CB_COLOR4_INFO__DCC_ENABLE__SHIFT 0x1c
465#define CB_COLOR4_INFO__CMASK_ADDR_TYPE_MASK 0x60000000
466#define CB_COLOR4_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
467#define CB_COLOR5_INFO__ENDIAN_MASK 0x3
468#define CB_COLOR5_INFO__ENDIAN__SHIFT 0x0
469#define CB_COLOR5_INFO__FORMAT_MASK 0x7c
470#define CB_COLOR5_INFO__FORMAT__SHIFT 0x2
471#define CB_COLOR5_INFO__LINEAR_GENERAL_MASK 0x80
472#define CB_COLOR5_INFO__LINEAR_GENERAL__SHIFT 0x7
473#define CB_COLOR5_INFO__NUMBER_TYPE_MASK 0x700
474#define CB_COLOR5_INFO__NUMBER_TYPE__SHIFT 0x8
475#define CB_COLOR5_INFO__COMP_SWAP_MASK 0x1800
476#define CB_COLOR5_INFO__COMP_SWAP__SHIFT 0xb
477#define CB_COLOR5_INFO__FAST_CLEAR_MASK 0x2000
478#define CB_COLOR5_INFO__FAST_CLEAR__SHIFT 0xd
479#define CB_COLOR5_INFO__COMPRESSION_MASK 0x4000
480#define CB_COLOR5_INFO__COMPRESSION__SHIFT 0xe
481#define CB_COLOR5_INFO__BLEND_CLAMP_MASK 0x8000
482#define CB_COLOR5_INFO__BLEND_CLAMP__SHIFT 0xf
483#define CB_COLOR5_INFO__BLEND_BYPASS_MASK 0x10000
484#define CB_COLOR5_INFO__BLEND_BYPASS__SHIFT 0x10
485#define CB_COLOR5_INFO__SIMPLE_FLOAT_MASK 0x20000
486#define CB_COLOR5_INFO__SIMPLE_FLOAT__SHIFT 0x11
487#define CB_COLOR5_INFO__ROUND_MODE_MASK 0x40000
488#define CB_COLOR5_INFO__ROUND_MODE__SHIFT 0x12
489#define CB_COLOR5_INFO__CMASK_IS_LINEAR_MASK 0x80000
490#define CB_COLOR5_INFO__CMASK_IS_LINEAR__SHIFT 0x13
491#define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
492#define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
493#define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
494#define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
495#define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
496#define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
497#define CB_COLOR5_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000
498#define CB_COLOR5_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
499#define CB_COLOR5_INFO__DCC_ENABLE_MASK 0x10000000
500#define CB_COLOR5_INFO__DCC_ENABLE__SHIFT 0x1c
501#define CB_COLOR5_INFO__CMASK_ADDR_TYPE_MASK 0x60000000
502#define CB_COLOR5_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
503#define CB_COLOR6_INFO__ENDIAN_MASK 0x3
504#define CB_COLOR6_INFO__ENDIAN__SHIFT 0x0
505#define CB_COLOR6_INFO__FORMAT_MASK 0x7c
506#define CB_COLOR6_INFO__FORMAT__SHIFT 0x2
507#define CB_COLOR6_INFO__LINEAR_GENERAL_MASK 0x80
508#define CB_COLOR6_INFO__LINEAR_GENERAL__SHIFT 0x7
509#define CB_COLOR6_INFO__NUMBER_TYPE_MASK 0x700
510#define CB_COLOR6_INFO__NUMBER_TYPE__SHIFT 0x8
511#define CB_COLOR6_INFO__COMP_SWAP_MASK 0x1800
512#define CB_COLOR6_INFO__COMP_SWAP__SHIFT 0xb
513#define CB_COLOR6_INFO__FAST_CLEAR_MASK 0x2000
514#define CB_COLOR6_INFO__FAST_CLEAR__SHIFT 0xd
515#define CB_COLOR6_INFO__COMPRESSION_MASK 0x4000
516#define CB_COLOR6_INFO__COMPRESSION__SHIFT 0xe
517#define CB_COLOR6_INFO__BLEND_CLAMP_MASK 0x8000
518#define CB_COLOR6_INFO__BLEND_CLAMP__SHIFT 0xf
519#define CB_COLOR6_INFO__BLEND_BYPASS_MASK 0x10000
520#define CB_COLOR6_INFO__BLEND_BYPASS__SHIFT 0x10
521#define CB_COLOR6_INFO__SIMPLE_FLOAT_MASK 0x20000
522#define CB_COLOR6_INFO__SIMPLE_FLOAT__SHIFT 0x11
523#define CB_COLOR6_INFO__ROUND_MODE_MASK 0x40000
524#define CB_COLOR6_INFO__ROUND_MODE__SHIFT 0x12
525#define CB_COLOR6_INFO__CMASK_IS_LINEAR_MASK 0x80000
526#define CB_COLOR6_INFO__CMASK_IS_LINEAR__SHIFT 0x13
527#define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
528#define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
529#define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
530#define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
531#define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
532#define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
533#define CB_COLOR6_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000
534#define CB_COLOR6_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
535#define CB_COLOR6_INFO__DCC_ENABLE_MASK 0x10000000
536#define CB_COLOR6_INFO__DCC_ENABLE__SHIFT 0x1c
537#define CB_COLOR6_INFO__CMASK_ADDR_TYPE_MASK 0x60000000
538#define CB_COLOR6_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
539#define CB_COLOR7_INFO__ENDIAN_MASK 0x3
540#define CB_COLOR7_INFO__ENDIAN__SHIFT 0x0
541#define CB_COLOR7_INFO__FORMAT_MASK 0x7c
542#define CB_COLOR7_INFO__FORMAT__SHIFT 0x2
543#define CB_COLOR7_INFO__LINEAR_GENERAL_MASK 0x80
544#define CB_COLOR7_INFO__LINEAR_GENERAL__SHIFT 0x7
545#define CB_COLOR7_INFO__NUMBER_TYPE_MASK 0x700
546#define CB_COLOR7_INFO__NUMBER_TYPE__SHIFT 0x8
547#define CB_COLOR7_INFO__COMP_SWAP_MASK 0x1800
548#define CB_COLOR7_INFO__COMP_SWAP__SHIFT 0xb
549#define CB_COLOR7_INFO__FAST_CLEAR_MASK 0x2000
550#define CB_COLOR7_INFO__FAST_CLEAR__SHIFT 0xd
551#define CB_COLOR7_INFO__COMPRESSION_MASK 0x4000
552#define CB_COLOR7_INFO__COMPRESSION__SHIFT 0xe
553#define CB_COLOR7_INFO__BLEND_CLAMP_MASK 0x8000
554#define CB_COLOR7_INFO__BLEND_CLAMP__SHIFT 0xf
555#define CB_COLOR7_INFO__BLEND_BYPASS_MASK 0x10000
556#define CB_COLOR7_INFO__BLEND_BYPASS__SHIFT 0x10
557#define CB_COLOR7_INFO__SIMPLE_FLOAT_MASK 0x20000
558#define CB_COLOR7_INFO__SIMPLE_FLOAT__SHIFT 0x11
559#define CB_COLOR7_INFO__ROUND_MODE_MASK 0x40000
560#define CB_COLOR7_INFO__ROUND_MODE__SHIFT 0x12
561#define CB_COLOR7_INFO__CMASK_IS_LINEAR_MASK 0x80000
562#define CB_COLOR7_INFO__CMASK_IS_LINEAR__SHIFT 0x13
563#define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
564#define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
565#define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
566#define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
567#define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
568#define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
569#define CB_COLOR7_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000
570#define CB_COLOR7_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
571#define CB_COLOR7_INFO__DCC_ENABLE_MASK 0x10000000
572#define CB_COLOR7_INFO__DCC_ENABLE__SHIFT 0x1c
573#define CB_COLOR7_INFO__CMASK_ADDR_TYPE_MASK 0x60000000
574#define CB_COLOR7_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
575#define CB_COLOR0_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
576#define CB_COLOR0_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
577#define CB_COLOR0_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
578#define CB_COLOR0_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
579#define CB_COLOR0_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
580#define CB_COLOR0_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
581#define CB_COLOR0_ATTRIB__NUM_SAMPLES_MASK 0x7000
582#define CB_COLOR0_ATTRIB__NUM_SAMPLES__SHIFT 0xc
583#define CB_COLOR0_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
584#define CB_COLOR0_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
585#define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
586#define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
587#define CB_COLOR1_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
588#define CB_COLOR1_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
589#define CB_COLOR1_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
590#define CB_COLOR1_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
591#define CB_COLOR1_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
592#define CB_COLOR1_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
593#define CB_COLOR1_ATTRIB__NUM_SAMPLES_MASK 0x7000
594#define CB_COLOR1_ATTRIB__NUM_SAMPLES__SHIFT 0xc
595#define CB_COLOR1_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
596#define CB_COLOR1_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
597#define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
598#define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
599#define CB_COLOR2_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
600#define CB_COLOR2_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
601#define CB_COLOR2_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
602#define CB_COLOR2_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
603#define CB_COLOR2_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
604#define CB_COLOR2_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
605#define CB_COLOR2_ATTRIB__NUM_SAMPLES_MASK 0x7000
606#define CB_COLOR2_ATTRIB__NUM_SAMPLES__SHIFT 0xc
607#define CB_COLOR2_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
608#define CB_COLOR2_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
609#define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
610#define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
611#define CB_COLOR3_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
612#define CB_COLOR3_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
613#define CB_COLOR3_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
614#define CB_COLOR3_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
615#define CB_COLOR3_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
616#define CB_COLOR3_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
617#define CB_COLOR3_ATTRIB__NUM_SAMPLES_MASK 0x7000
618#define CB_COLOR3_ATTRIB__NUM_SAMPLES__SHIFT 0xc
619#define CB_COLOR3_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
620#define CB_COLOR3_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
621#define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
622#define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
623#define CB_COLOR4_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
624#define CB_COLOR4_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
625#define CB_COLOR4_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
626#define CB_COLOR4_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
627#define CB_COLOR4_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
628#define CB_COLOR4_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
629#define CB_COLOR4_ATTRIB__NUM_SAMPLES_MASK 0x7000
630#define CB_COLOR4_ATTRIB__NUM_SAMPLES__SHIFT 0xc
631#define CB_COLOR4_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
632#define CB_COLOR4_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
633#define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
634#define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
635#define CB_COLOR5_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
636#define CB_COLOR5_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
637#define CB_COLOR5_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
638#define CB_COLOR5_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
639#define CB_COLOR5_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
640#define CB_COLOR5_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
641#define CB_COLOR5_ATTRIB__NUM_SAMPLES_MASK 0x7000
642#define CB_COLOR5_ATTRIB__NUM_SAMPLES__SHIFT 0xc
643#define CB_COLOR5_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
644#define CB_COLOR5_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
645#define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
646#define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
647#define CB_COLOR6_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
648#define CB_COLOR6_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
649#define CB_COLOR6_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
650#define CB_COLOR6_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
651#define CB_COLOR6_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
652#define CB_COLOR6_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
653#define CB_COLOR6_ATTRIB__NUM_SAMPLES_MASK 0x7000
654#define CB_COLOR6_ATTRIB__NUM_SAMPLES__SHIFT 0xc
655#define CB_COLOR6_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
656#define CB_COLOR6_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
657#define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
658#define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
659#define CB_COLOR7_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
660#define CB_COLOR7_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
661#define CB_COLOR7_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
662#define CB_COLOR7_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
663#define CB_COLOR7_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
664#define CB_COLOR7_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
665#define CB_COLOR7_ATTRIB__NUM_SAMPLES_MASK 0x7000
666#define CB_COLOR7_ATTRIB__NUM_SAMPLES__SHIFT 0xc
667#define CB_COLOR7_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
668#define CB_COLOR7_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
669#define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
670#define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
671#define CB_COLOR0_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
672#define CB_COLOR0_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
673#define CB_COLOR0_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2
674#define CB_COLOR0_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
675#define CB_COLOR0_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc
676#define CB_COLOR0_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
677#define CB_COLOR0_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10
678#define CB_COLOR0_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
679#define CB_COLOR0_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60
680#define CB_COLOR0_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
681#define CB_COLOR0_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180
682#define CB_COLOR0_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
683#define CB_COLOR0_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200
684#define CB_COLOR0_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
685#define CB_COLOR0_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00
686#define CB_COLOR0_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
687#define CB_COLOR0_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000
688#define CB_COLOR0_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
689#define CB_COLOR1_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
690#define CB_COLOR1_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
691#define CB_COLOR1_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2
692#define CB_COLOR1_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
693#define CB_COLOR1_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc
694#define CB_COLOR1_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
695#define CB_COLOR1_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10
696#define CB_COLOR1_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
697#define CB_COLOR1_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60
698#define CB_COLOR1_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
699#define CB_COLOR1_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180
700#define CB_COLOR1_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
701#define CB_COLOR1_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200
702#define CB_COLOR1_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
703#define CB_COLOR1_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00
704#define CB_COLOR1_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
705#define CB_COLOR1_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000
706#define CB_COLOR1_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
707#define CB_COLOR2_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
708#define CB_COLOR2_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
709#define CB_COLOR2_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2
710#define CB_COLOR2_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
711#define CB_COLOR2_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc
712#define CB_COLOR2_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
713#define CB_COLOR2_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10
714#define CB_COLOR2_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
715#define CB_COLOR2_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60
716#define CB_COLOR2_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
717#define CB_COLOR2_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180
718#define CB_COLOR2_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
719#define CB_COLOR2_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200
720#define CB_COLOR2_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
721#define CB_COLOR2_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00
722#define CB_COLOR2_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
723#define CB_COLOR2_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000
724#define CB_COLOR2_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
725#define CB_COLOR3_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
726#define CB_COLOR3_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
727#define CB_COLOR3_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2
728#define CB_COLOR3_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
729#define CB_COLOR3_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc
730#define CB_COLOR3_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
731#define CB_COLOR3_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10
732#define CB_COLOR3_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
733#define CB_COLOR3_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60
734#define CB_COLOR3_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
735#define CB_COLOR3_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180
736#define CB_COLOR3_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
737#define CB_COLOR3_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200
738#define CB_COLOR3_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
739#define CB_COLOR3_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00
740#define CB_COLOR3_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
741#define CB_COLOR3_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000
742#define CB_COLOR3_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
743#define CB_COLOR4_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
744#define CB_COLOR4_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
745#define CB_COLOR4_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2
746#define CB_COLOR4_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
747#define CB_COLOR4_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc
748#define CB_COLOR4_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
749#define CB_COLOR4_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10
750#define CB_COLOR4_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
751#define CB_COLOR4_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60
752#define CB_COLOR4_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
753#define CB_COLOR4_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180
754#define CB_COLOR4_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
755#define CB_COLOR4_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200
756#define CB_COLOR4_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
757#define CB_COLOR4_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00
758#define CB_COLOR4_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
759#define CB_COLOR4_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000
760#define CB_COLOR4_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
761#define CB_COLOR5_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
762#define CB_COLOR5_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
763#define CB_COLOR5_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2
764#define CB_COLOR5_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
765#define CB_COLOR5_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc
766#define CB_COLOR5_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
767#define CB_COLOR5_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10
768#define CB_COLOR5_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
769#define CB_COLOR5_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60
770#define CB_COLOR5_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
771#define CB_COLOR5_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180
772#define CB_COLOR5_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
773#define CB_COLOR5_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200
774#define CB_COLOR5_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
775#define CB_COLOR5_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00
776#define CB_COLOR5_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
777#define CB_COLOR5_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000
778#define CB_COLOR5_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
779#define CB_COLOR6_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
780#define CB_COLOR6_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
781#define CB_COLOR6_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2
782#define CB_COLOR6_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
783#define CB_COLOR6_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc
784#define CB_COLOR6_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
785#define CB_COLOR6_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10
786#define CB_COLOR6_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
787#define CB_COLOR6_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60
788#define CB_COLOR6_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
789#define CB_COLOR6_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180
790#define CB_COLOR6_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
791#define CB_COLOR6_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200
792#define CB_COLOR6_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
793#define CB_COLOR6_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00
794#define CB_COLOR6_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
795#define CB_COLOR6_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000
796#define CB_COLOR6_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
797#define CB_COLOR7_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
798#define CB_COLOR7_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
799#define CB_COLOR7_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2
800#define CB_COLOR7_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
801#define CB_COLOR7_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc
802#define CB_COLOR7_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
803#define CB_COLOR7_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10
804#define CB_COLOR7_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
805#define CB_COLOR7_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60
806#define CB_COLOR7_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
807#define CB_COLOR7_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180
808#define CB_COLOR7_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
809#define CB_COLOR7_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200
810#define CB_COLOR7_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
811#define CB_COLOR7_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00
812#define CB_COLOR7_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
813#define CB_COLOR7_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000
814#define CB_COLOR7_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
815#define CB_COLOR0_CMASK__BASE_256B_MASK 0xffffffff
816#define CB_COLOR0_CMASK__BASE_256B__SHIFT 0x0
817#define CB_COLOR1_CMASK__BASE_256B_MASK 0xffffffff
818#define CB_COLOR1_CMASK__BASE_256B__SHIFT 0x0
819#define CB_COLOR2_CMASK__BASE_256B_MASK 0xffffffff
820#define CB_COLOR2_CMASK__BASE_256B__SHIFT 0x0
821#define CB_COLOR3_CMASK__BASE_256B_MASK 0xffffffff
822#define CB_COLOR3_CMASK__BASE_256B__SHIFT 0x0
823#define CB_COLOR4_CMASK__BASE_256B_MASK 0xffffffff
824#define CB_COLOR4_CMASK__BASE_256B__SHIFT 0x0
825#define CB_COLOR5_CMASK__BASE_256B_MASK 0xffffffff
826#define CB_COLOR5_CMASK__BASE_256B__SHIFT 0x0
827#define CB_COLOR6_CMASK__BASE_256B_MASK 0xffffffff
828#define CB_COLOR6_CMASK__BASE_256B__SHIFT 0x0
829#define CB_COLOR7_CMASK__BASE_256B_MASK 0xffffffff
830#define CB_COLOR7_CMASK__BASE_256B__SHIFT 0x0
831#define CB_COLOR0_CMASK_SLICE__TILE_MAX_MASK 0x3fff
832#define CB_COLOR0_CMASK_SLICE__TILE_MAX__SHIFT 0x0
833#define CB_COLOR1_CMASK_SLICE__TILE_MAX_MASK 0x3fff
834#define CB_COLOR1_CMASK_SLICE__TILE_MAX__SHIFT 0x0
835#define CB_COLOR2_CMASK_SLICE__TILE_MAX_MASK 0x3fff
836#define CB_COLOR2_CMASK_SLICE__TILE_MAX__SHIFT 0x0
837#define CB_COLOR3_CMASK_SLICE__TILE_MAX_MASK 0x3fff
838#define CB_COLOR3_CMASK_SLICE__TILE_MAX__SHIFT 0x0
839#define CB_COLOR4_CMASK_SLICE__TILE_MAX_MASK 0x3fff
840#define CB_COLOR4_CMASK_SLICE__TILE_MAX__SHIFT 0x0
841#define CB_COLOR5_CMASK_SLICE__TILE_MAX_MASK 0x3fff
842#define CB_COLOR5_CMASK_SLICE__TILE_MAX__SHIFT 0x0
843#define CB_COLOR6_CMASK_SLICE__TILE_MAX_MASK 0x3fff
844#define CB_COLOR6_CMASK_SLICE__TILE_MAX__SHIFT 0x0
845#define CB_COLOR7_CMASK_SLICE__TILE_MAX_MASK 0x3fff
846#define CB_COLOR7_CMASK_SLICE__TILE_MAX__SHIFT 0x0
847#define CB_COLOR0_FMASK__BASE_256B_MASK 0xffffffff
848#define CB_COLOR0_FMASK__BASE_256B__SHIFT 0x0
849#define CB_COLOR1_FMASK__BASE_256B_MASK 0xffffffff
850#define CB_COLOR1_FMASK__BASE_256B__SHIFT 0x0
851#define CB_COLOR2_FMASK__BASE_256B_MASK 0xffffffff
852#define CB_COLOR2_FMASK__BASE_256B__SHIFT 0x0
853#define CB_COLOR3_FMASK__BASE_256B_MASK 0xffffffff
854#define CB_COLOR3_FMASK__BASE_256B__SHIFT 0x0
855#define CB_COLOR4_FMASK__BASE_256B_MASK 0xffffffff
856#define CB_COLOR4_FMASK__BASE_256B__SHIFT 0x0
857#define CB_COLOR5_FMASK__BASE_256B_MASK 0xffffffff
858#define CB_COLOR5_FMASK__BASE_256B__SHIFT 0x0
859#define CB_COLOR6_FMASK__BASE_256B_MASK 0xffffffff
860#define CB_COLOR6_FMASK__BASE_256B__SHIFT 0x0
861#define CB_COLOR7_FMASK__BASE_256B_MASK 0xffffffff
862#define CB_COLOR7_FMASK__BASE_256B__SHIFT 0x0
863#define CB_COLOR0_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
864#define CB_COLOR0_FMASK_SLICE__TILE_MAX__SHIFT 0x0
865#define CB_COLOR1_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
866#define CB_COLOR1_FMASK_SLICE__TILE_MAX__SHIFT 0x0
867#define CB_COLOR2_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
868#define CB_COLOR2_FMASK_SLICE__TILE_MAX__SHIFT 0x0
869#define CB_COLOR3_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
870#define CB_COLOR3_FMASK_SLICE__TILE_MAX__SHIFT 0x0
871#define CB_COLOR4_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
872#define CB_COLOR4_FMASK_SLICE__TILE_MAX__SHIFT 0x0
873#define CB_COLOR5_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
874#define CB_COLOR5_FMASK_SLICE__TILE_MAX__SHIFT 0x0
875#define CB_COLOR6_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
876#define CB_COLOR6_FMASK_SLICE__TILE_MAX__SHIFT 0x0
877#define CB_COLOR7_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
878#define CB_COLOR7_FMASK_SLICE__TILE_MAX__SHIFT 0x0
879#define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
880#define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
881#define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
882#define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
883#define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
884#define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
885#define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
886#define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
887#define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
888#define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
889#define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
890#define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
891#define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
892#define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
893#define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
894#define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
895#define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
896#define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
897#define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
898#define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
899#define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
900#define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
901#define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
902#define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
903#define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
904#define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
905#define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
906#define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
907#define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
908#define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
909#define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
910#define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
911#define CB_COLOR0_DCC_BASE__BASE_256B_MASK 0xffffffff
912#define CB_COLOR0_DCC_BASE__BASE_256B__SHIFT 0x0
913#define CB_COLOR1_DCC_BASE__BASE_256B_MASK 0xffffffff
914#define CB_COLOR1_DCC_BASE__BASE_256B__SHIFT 0x0
915#define CB_COLOR2_DCC_BASE__BASE_256B_MASK 0xffffffff
916#define CB_COLOR2_DCC_BASE__BASE_256B__SHIFT 0x0
917#define CB_COLOR3_DCC_BASE__BASE_256B_MASK 0xffffffff
918#define CB_COLOR3_DCC_BASE__BASE_256B__SHIFT 0x0
919#define CB_COLOR4_DCC_BASE__BASE_256B_MASK 0xffffffff
920#define CB_COLOR4_DCC_BASE__BASE_256B__SHIFT 0x0
921#define CB_COLOR5_DCC_BASE__BASE_256B_MASK 0xffffffff
922#define CB_COLOR5_DCC_BASE__BASE_256B__SHIFT 0x0
923#define CB_COLOR6_DCC_BASE__BASE_256B_MASK 0xffffffff
924#define CB_COLOR6_DCC_BASE__BASE_256B__SHIFT 0x0
925#define CB_COLOR7_DCC_BASE__BASE_256B_MASK 0xffffffff
926#define CB_COLOR7_DCC_BASE__BASE_256B__SHIFT 0x0
927#define CB_TARGET_MASK__TARGET0_ENABLE_MASK 0xf
928#define CB_TARGET_MASK__TARGET0_ENABLE__SHIFT 0x0
929#define CB_TARGET_MASK__TARGET1_ENABLE_MASK 0xf0
930#define CB_TARGET_MASK__TARGET1_ENABLE__SHIFT 0x4
931#define CB_TARGET_MASK__TARGET2_ENABLE_MASK 0xf00
932#define CB_TARGET_MASK__TARGET2_ENABLE__SHIFT 0x8
933#define CB_TARGET_MASK__TARGET3_ENABLE_MASK 0xf000
934#define CB_TARGET_MASK__TARGET3_ENABLE__SHIFT 0xc
935#define CB_TARGET_MASK__TARGET4_ENABLE_MASK 0xf0000
936#define CB_TARGET_MASK__TARGET4_ENABLE__SHIFT 0x10
937#define CB_TARGET_MASK__TARGET5_ENABLE_MASK 0xf00000
938#define CB_TARGET_MASK__TARGET5_ENABLE__SHIFT 0x14
939#define CB_TARGET_MASK__TARGET6_ENABLE_MASK 0xf000000
940#define CB_TARGET_MASK__TARGET6_ENABLE__SHIFT 0x18
941#define CB_TARGET_MASK__TARGET7_ENABLE_MASK 0xf0000000
942#define CB_TARGET_MASK__TARGET7_ENABLE__SHIFT 0x1c
943#define CB_SHADER_MASK__OUTPUT0_ENABLE_MASK 0xf
944#define CB_SHADER_MASK__OUTPUT0_ENABLE__SHIFT 0x0
945#define CB_SHADER_MASK__OUTPUT1_ENABLE_MASK 0xf0
946#define CB_SHADER_MASK__OUTPUT1_ENABLE__SHIFT 0x4
947#define CB_SHADER_MASK__OUTPUT2_ENABLE_MASK 0xf00
948#define CB_SHADER_MASK__OUTPUT2_ENABLE__SHIFT 0x8
949#define CB_SHADER_MASK__OUTPUT3_ENABLE_MASK 0xf000
950#define CB_SHADER_MASK__OUTPUT3_ENABLE__SHIFT 0xc
951#define CB_SHADER_MASK__OUTPUT4_ENABLE_MASK 0xf0000
952#define CB_SHADER_MASK__OUTPUT4_ENABLE__SHIFT 0x10
953#define CB_SHADER_MASK__OUTPUT5_ENABLE_MASK 0xf00000
954#define CB_SHADER_MASK__OUTPUT5_ENABLE__SHIFT 0x14
955#define CB_SHADER_MASK__OUTPUT6_ENABLE_MASK 0xf000000
956#define CB_SHADER_MASK__OUTPUT6_ENABLE__SHIFT 0x18
957#define CB_SHADER_MASK__OUTPUT7_ENABLE_MASK 0xf0000000
958#define CB_SHADER_MASK__OUTPUT7_ENABLE__SHIFT 0x1c
959#define CB_HW_CONTROL__CM_CACHE_EVICT_POINT_MASK 0xf
960#define CB_HW_CONTROL__CM_CACHE_EVICT_POINT__SHIFT 0x0
961#define CB_HW_CONTROL__FC_CACHE_EVICT_POINT_MASK 0x3c0
962#define CB_HW_CONTROL__FC_CACHE_EVICT_POINT__SHIFT 0x6
963#define CB_HW_CONTROL__CC_CACHE_EVICT_POINT_MASK 0xf000
964#define CB_HW_CONTROL__CC_CACHE_EVICT_POINT__SHIFT 0xc
965#define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE_MASK 0x10000
966#define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE__SHIFT 0x10
967#define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING_MASK 0x40000
968#define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING__SHIFT 0x12
969#define CB_HW_CONTROL__FORCE_NEEDS_DST_MASK 0x80000
970#define CB_HW_CONTROL__FORCE_NEEDS_DST__SHIFT 0x13
971#define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE_MASK 0x100000
972#define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE__SHIFT 0x14
973#define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST_MASK 0x200000
974#define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST__SHIFT 0x15
975#define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK_MASK 0x400000
976#define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK__SHIFT 0x16
977#define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG_MASK 0x800000
978#define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG__SHIFT 0x17
979#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST_MASK 0x1000000
980#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT 0x18
981#define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS_MASK 0x2000000
982#define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS__SHIFT 0x19
983#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK 0x4000000
984#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT 0x1a
985#define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED_MASK 0x8000000
986#define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED__SHIFT 0x1b
987#define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT_MASK 0x10000000
988#define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT__SHIFT 0x1c
989#define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT_MASK 0x20000000
990#define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT__SHIFT 0x1d
991#define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT_MASK 0x40000000
992#define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT__SHIFT 0x1e
993#define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE_MASK 0x80000000
994#define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE__SHIFT 0x1f
995#define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS_MASK 0x1f
996#define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS__SHIFT 0x0
997#define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS_MASK 0x7e0
998#define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS__SHIFT 0x5
999#define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS_MASK 0x1f800
1000#define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS__SHIFT 0xb
1001#define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH_MASK 0x3fe0000
1002#define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH__SHIFT 0x11
1003#define CB_HW_CONTROL_1__CHICKEN_BITS_MASK 0xfc000000
1004#define CB_HW_CONTROL_1__CHICKEN_BITS__SHIFT 0x1a
1005#define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH_MASK 0xff
1006#define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH__SHIFT 0x0
1007#define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH_MASK 0x7f00
1008#define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH__SHIFT 0x8
1009#define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH_MASK 0x7f8000
1010#define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH__SHIFT 0xf
1011#define CB_HW_CONTROL_2__DRR_ASSUMED_FIFO_DEPTH_DIV8_MASK 0xf000000
1012#define CB_HW_CONTROL_2__DRR_ASSUMED_FIFO_DEPTH_DIV8__SHIFT 0x18
1013#define CB_HW_CONTROL_2__CHICKEN_BITS_MASK 0xf0000000
1014#define CB_HW_CONTROL_2__CHICKEN_BITS__SHIFT 0x1c
1015#define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL_MASK 0x1
1016#define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL__SHIFT 0x0
1017#define CB_HW_CONTROL_3__RAM_ADDRESS_CONFLICTS_DISALLOWED_MASK 0x2
1018#define CB_HW_CONTROL_3__RAM_ADDRESS_CONFLICTS_DISALLOWED__SHIFT 0x1
1019#define CB_HW_CONTROL_3__DISABLE_FAST_CLEAR_FETCH_OPT_MASK 0x4
1020#define CB_HW_CONTROL_3__DISABLE_FAST_CLEAR_FETCH_OPT__SHIFT 0x2
1021#define CB_HW_CONTROL_3__DISABLE_QUAD_MARKER_DROP_STOP_MASK 0x8
1022#define CB_HW_CONTROL_3__DISABLE_QUAD_MARKER_DROP_STOP__SHIFT 0x3
1023#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_CAM_CLR_MASK 0x10
1024#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_CAM_CLR__SHIFT 0x4
1025#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_STATUS_ACCUM_MASK 0x20
1026#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_STATUS_ACCUM__SHIFT 0x5
1027#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_KEY_MOD_MASK 0x40
1028#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_KEY_MOD__SHIFT 0x6
1029#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_PANIC_GATING_MASK 0x80
1030#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_PANIC_GATING__SHIFT 0x7
1031#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_TARGET_MASK_VALIDATION_MASK 0x100
1032#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_TARGET_MASK_VALIDATION__SHIFT 0x8
1033#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DEPTH_MASK 0x1f
1034#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DEPTH__SHIFT 0x0
1035#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DISABLE_MASK 0x20
1036#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DISABLE__SHIFT 0x5
1037#define CB_DCC_CONFIG__OVERWRITE_COMBINER_CC_POP_DISABLE_MASK 0x40
1038#define CB_DCC_CONFIG__OVERWRITE_COMBINER_CC_POP_DISABLE__SHIFT 0x6
1039#define CB_DCC_CONFIG__FC_RDLAT_KEYID_FIFO_DEPTH_MASK 0xff00
1040#define CB_DCC_CONFIG__FC_RDLAT_KEYID_FIFO_DEPTH__SHIFT 0x8
1041#define CB_DCC_CONFIG__READ_RETURN_SKID_FIFO_DEPTH_MASK 0x7f0000
1042#define CB_DCC_CONFIG__READ_RETURN_SKID_FIFO_DEPTH__SHIFT 0x10
1043#define CB_DCC_CONFIG__DCC_CACHE_EVICT_POINT_MASK 0xf000000
1044#define CB_DCC_CONFIG__DCC_CACHE_EVICT_POINT__SHIFT 0x18
1045#define CB_DCC_CONFIG__DCC_CACHE_NUM_TAGS_MASK 0xf0000000
1046#define CB_DCC_CONFIG__DCC_CACHE_NUM_TAGS__SHIFT 0x1c
1047#define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE_MASK 0x1
1048#define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE__SHIFT 0x0
1049#define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL_MASK 0xe
1050#define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL__SHIFT 0x1
1051#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE_MASK 0x10
1052#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE__SHIFT 0x4
1053#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL_MASK 0x3e0
1054#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL__SHIFT 0x5
1055#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE_MASK 0x400
1056#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE__SHIFT 0xa
1057#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL_MASK 0x800
1058#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL__SHIFT 0xb
1059#define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE_MASK 0x1000
1060#define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE__SHIFT 0xc
1061#define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL_MASK 0xe000
1062#define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL__SHIFT 0xd
1063#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE_MASK 0x20000
1064#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE__SHIFT 0x11
1065#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL_MASK 0x1c0000
1066#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL__SHIFT 0x12
1067#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE_MASK 0x200000
1068#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE__SHIFT 0x15
1069#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL_MASK 0xc00000
1070#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL__SHIFT 0x16
1071#define CB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x1ff
1072#define CB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
1073#define CB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x7fc00
1074#define CB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
1075#define CB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
1076#define CB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
1077#define CB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000
1078#define CB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
1079#define CB_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
1080#define CB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
1081#define CB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x1ff
1082#define CB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
1083#define CB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x7fc00
1084#define CB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
1085#define CB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000
1086#define CB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
1087#define CB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000
1088#define CB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
1089#define CB_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x1ff
1090#define CB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
1091#define CB_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
1092#define CB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
1093#define CB_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x1ff
1094#define CB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
1095#define CB_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000
1096#define CB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
1097#define CB_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x1ff
1098#define CB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
1099#define CB_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000
1100#define CB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
1101#define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
1102#define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
1103#define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
1104#define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
1105#define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
1106#define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
1107#define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
1108#define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
1109#define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
1110#define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
1111#define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
1112#define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
1113#define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
1114#define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
1115#define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
1116#define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
1117#define CB_CGTT_SCLK_CTRL__ON_DELAY_MASK 0xf
1118#define CB_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0
1119#define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
1120#define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
1121#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
1122#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
1123#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
1124#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
1125#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
1126#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
1127#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
1128#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
1129#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
1130#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
1131#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
1132#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
1133#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
1134#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
1135#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
1136#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
1137#define CB_DEBUG_BUS_17__TILE_INTFC_BUSY_MASK 0x1
1138#define CB_DEBUG_BUS_17__TILE_INTFC_BUSY__SHIFT 0x0
1139#define CB_DEBUG_BUS_17__MU_BUSY_MASK 0x2
1140#define CB_DEBUG_BUS_17__MU_BUSY__SHIFT 0x1
1141#define CB_DEBUG_BUS_17__TQ_BUSY_MASK 0x4
1142#define CB_DEBUG_BUS_17__TQ_BUSY__SHIFT 0x2
1143#define CB_DEBUG_BUS_17__AC_BUSY_MASK 0x8
1144#define CB_DEBUG_BUS_17__AC_BUSY__SHIFT 0x3
1145#define CB_DEBUG_BUS_17__CRW_BUSY_MASK 0x10
1146#define CB_DEBUG_BUS_17__CRW_BUSY__SHIFT 0x4
1147#define CB_DEBUG_BUS_17__CACHE_CTRL_BUSY_MASK 0x20
1148#define CB_DEBUG_BUS_17__CACHE_CTRL_BUSY__SHIFT 0x5
1149#define CB_DEBUG_BUS_17__MC_WR_PENDING_MASK 0x40
1150#define CB_DEBUG_BUS_17__MC_WR_PENDING__SHIFT 0x6
1151#define CB_DEBUG_BUS_17__FC_WR_PENDING_MASK 0x80
1152#define CB_DEBUG_BUS_17__FC_WR_PENDING__SHIFT 0x7
1153#define CB_DEBUG_BUS_17__FC_RD_PENDING_MASK 0x100
1154#define CB_DEBUG_BUS_17__FC_RD_PENDING__SHIFT 0x8
1155#define CB_DEBUG_BUS_17__EVICT_PENDING_MASK 0x200
1156#define CB_DEBUG_BUS_17__EVICT_PENDING__SHIFT 0x9
1157#define CB_DEBUG_BUS_17__LAST_RD_ARB_WINNER_MASK 0x400
1158#define CB_DEBUG_BUS_17__LAST_RD_ARB_WINNER__SHIFT 0xa
1159#define CB_DEBUG_BUS_17__MU_STATE_MASK 0x7f800
1160#define CB_DEBUG_BUS_17__MU_STATE__SHIFT 0xb
1161#define CB_DEBUG_BUS_18__TILE_RETIREMENT_BUSY_MASK 0x1
1162#define CB_DEBUG_BUS_18__TILE_RETIREMENT_BUSY__SHIFT 0x0
1163#define CB_DEBUG_BUS_18__FOP_BUSY_MASK 0x2
1164#define CB_DEBUG_BUS_18__FOP_BUSY__SHIFT 0x1
1165#define CB_DEBUG_BUS_18__CLEAR_BUSY_MASK 0x4
1166#define CB_DEBUG_BUS_18__CLEAR_BUSY__SHIFT 0x2
1167#define CB_DEBUG_BUS_18__LAT_BUSY_MASK 0x8
1168#define CB_DEBUG_BUS_18__LAT_BUSY__SHIFT 0x3
1169#define CB_DEBUG_BUS_18__CACHE_CTL_BUSY_MASK 0x10
1170#define CB_DEBUG_BUS_18__CACHE_CTL_BUSY__SHIFT 0x4
1171#define CB_DEBUG_BUS_18__ADDR_BUSY_MASK 0x20
1172#define CB_DEBUG_BUS_18__ADDR_BUSY__SHIFT 0x5
1173#define CB_DEBUG_BUS_18__MERGE_BUSY_MASK 0x40
1174#define CB_DEBUG_BUS_18__MERGE_BUSY__SHIFT 0x6
1175#define CB_DEBUG_BUS_18__QUAD_BUSY_MASK 0x80
1176#define CB_DEBUG_BUS_18__QUAD_BUSY__SHIFT 0x7
1177#define CB_DEBUG_BUS_18__TILE_BUSY_MASK 0x100
1178#define CB_DEBUG_BUS_18__TILE_BUSY__SHIFT 0x8
1179#define CB_DEBUG_BUS_18__DCC_BUSY_MASK 0x200
1180#define CB_DEBUG_BUS_18__DCC_BUSY__SHIFT 0x9
1181#define CB_DEBUG_BUS_18__DOC_BUSY_MASK 0x400
1182#define CB_DEBUG_BUS_18__DOC_BUSY__SHIFT 0xa
1183#define CB_DEBUG_BUS_18__DAG_BUSY_MASK 0x800
1184#define CB_DEBUG_BUS_18__DAG_BUSY__SHIFT 0xb
1185#define CB_DEBUG_BUS_18__DOC_STALL_MASK 0x1000
1186#define CB_DEBUG_BUS_18__DOC_STALL__SHIFT 0xc
1187#define CB_DEBUG_BUS_18__DOC_QT_CAM_FULL_MASK 0x2000
1188#define CB_DEBUG_BUS_18__DOC_QT_CAM_FULL__SHIFT 0xd
1189#define CB_DEBUG_BUS_18__DOC_CL_CAM_FULL_MASK 0x4000
1190#define CB_DEBUG_BUS_18__DOC_CL_CAM_FULL__SHIFT 0xe
1191#define CB_DEBUG_BUS_18__DOC_QUAD_PTR_FIFO_FULL_MASK 0x8000
1192#define CB_DEBUG_BUS_18__DOC_QUAD_PTR_FIFO_FULL__SHIFT 0xf
1193#define CB_DEBUG_BUS_18__DOC_SECTOR_MASK_FIFO_FULL_MASK 0x10000
1194#define CB_DEBUG_BUS_18__DOC_SECTOR_MASK_FIFO_FULL__SHIFT 0x10
1195#define CB_DEBUG_BUS_18__DCS_READ_WINNER_LAST_MASK 0x20000
1196#define CB_DEBUG_BUS_18__DCS_READ_WINNER_LAST__SHIFT 0x11
1197#define CB_DEBUG_BUS_18__DCS_READ_EV_PENDING_MASK 0x40000
1198#define CB_DEBUG_BUS_18__DCS_READ_EV_PENDING__SHIFT 0x12
1199#define CB_DEBUG_BUS_18__DCS_WRITE_CC_PENDING_MASK 0x80000
1200#define CB_DEBUG_BUS_18__DCS_WRITE_CC_PENDING__SHIFT 0x13
1201#define CB_DEBUG_BUS_18__DCS_READ_CC_PENDING_MASK 0x100000
1202#define CB_DEBUG_BUS_18__DCS_READ_CC_PENDING__SHIFT 0x14
1203#define CB_DEBUG_BUS_18__DCS_WRITE_MC_PENDING_MASK 0x200000
1204#define CB_DEBUG_BUS_18__DCS_WRITE_MC_PENDING__SHIFT 0x15
1205#define CB_DEBUG_BUS_19__SURF_SYNC_STATE_MASK 0x3
1206#define CB_DEBUG_BUS_19__SURF_SYNC_STATE__SHIFT 0x0
1207#define CB_DEBUG_BUS_19__SURF_SYNC_START_MASK 0x4
1208#define CB_DEBUG_BUS_19__SURF_SYNC_START__SHIFT 0x2
1209#define CB_DEBUG_BUS_19__SF_BUSY_MASK 0x8
1210#define CB_DEBUG_BUS_19__SF_BUSY__SHIFT 0x3
1211#define CB_DEBUG_BUS_19__CS_BUSY_MASK 0x10
1212#define CB_DEBUG_BUS_19__CS_BUSY__SHIFT 0x4
1213#define CB_DEBUG_BUS_19__RB_BUSY_MASK 0x20
1214#define CB_DEBUG_BUS_19__RB_BUSY__SHIFT 0x5
1215#define CB_DEBUG_BUS_19__DS_BUSY_MASK 0x40
1216#define CB_DEBUG_BUS_19__DS_BUSY__SHIFT 0x6
1217#define CB_DEBUG_BUS_19__TB_BUSY_MASK 0x80
1218#define CB_DEBUG_BUS_19__TB_BUSY__SHIFT 0x7
1219#define CB_DEBUG_BUS_19__IB_BUSY_MASK 0x100
1220#define CB_DEBUG_BUS_19__IB_BUSY__SHIFT 0x8
1221#define CB_DEBUG_BUS_19__DRR_BUSY_MASK 0x200
1222#define CB_DEBUG_BUS_19__DRR_BUSY__SHIFT 0x9
1223#define CB_DEBUG_BUS_19__DF_BUSY_MASK 0x400
1224#define CB_DEBUG_BUS_19__DF_BUSY__SHIFT 0xa
1225#define CB_DEBUG_BUS_19__DD_BUSY_MASK 0x800
1226#define CB_DEBUG_BUS_19__DD_BUSY__SHIFT 0xb
1227#define CB_DEBUG_BUS_19__DC_BUSY_MASK 0x1000
1228#define CB_DEBUG_BUS_19__DC_BUSY__SHIFT 0xc
1229#define CB_DEBUG_BUS_19__DK_BUSY_MASK 0x2000
1230#define CB_DEBUG_BUS_19__DK_BUSY__SHIFT 0xd
1231#define CB_DEBUG_BUS_19__DF_SKID_FIFO_EMPTY_MASK 0x4000
1232#define CB_DEBUG_BUS_19__DF_SKID_FIFO_EMPTY__SHIFT 0xe
1233#define CB_DEBUG_BUS_19__DF_CLEAR_FIFO_EMPTY_MASK 0x8000
1234#define CB_DEBUG_BUS_19__DF_CLEAR_FIFO_EMPTY__SHIFT 0xf
1235#define CB_DEBUG_BUS_19__DD_READY_MASK 0x10000
1236#define CB_DEBUG_BUS_19__DD_READY__SHIFT 0x10
1237#define CB_DEBUG_BUS_19__DC_FIFO_FULL_MASK 0x20000
1238#define CB_DEBUG_BUS_19__DC_FIFO_FULL__SHIFT 0x11
1239#define CB_DEBUG_BUS_19__DC_READY_MASK 0x40000
1240#define CB_DEBUG_BUS_19__DC_READY__SHIFT 0x12
1241#define CB_DEBUG_BUS_20__MC_RDREQ_CREDITS_MASK 0x3f
1242#define CB_DEBUG_BUS_20__MC_RDREQ_CREDITS__SHIFT 0x0
1243#define CB_DEBUG_BUS_20__MC_WRREQ_CREDITS_MASK 0xfc0
1244#define CB_DEBUG_BUS_20__MC_WRREQ_CREDITS__SHIFT 0x6
1245#define CB_DEBUG_BUS_20__CC_RDREQ_HAD_ITS_TURN_MASK 0x1000
1246#define CB_DEBUG_BUS_20__CC_RDREQ_HAD_ITS_TURN__SHIFT 0xc
1247#define CB_DEBUG_BUS_20__FC_RDREQ_HAD_ITS_TURN_MASK 0x2000
1248#define CB_DEBUG_BUS_20__FC_RDREQ_HAD_ITS_TURN__SHIFT 0xd
1249#define CB_DEBUG_BUS_20__CM_RDREQ_HAD_ITS_TURN_MASK 0x4000
1250#define CB_DEBUG_BUS_20__CM_RDREQ_HAD_ITS_TURN__SHIFT 0xe
1251#define CB_DEBUG_BUS_20__CC_WRREQ_HAD_ITS_TURN_MASK 0x10000
1252#define CB_DEBUG_BUS_20__CC_WRREQ_HAD_ITS_TURN__SHIFT 0x10
1253#define CB_DEBUG_BUS_20__FC_WRREQ_HAD_ITS_TURN_MASK 0x20000
1254#define CB_DEBUG_BUS_20__FC_WRREQ_HAD_ITS_TURN__SHIFT 0x11
1255#define CB_DEBUG_BUS_20__CM_WRREQ_HAD_ITS_TURN_MASK 0x40000
1256#define CB_DEBUG_BUS_20__CM_WRREQ_HAD_ITS_TURN__SHIFT 0x12
1257#define CB_DEBUG_BUS_20__CC_WRREQ_FIFO_EMPTY_MASK 0x100000
1258#define CB_DEBUG_BUS_20__CC_WRREQ_FIFO_EMPTY__SHIFT 0x14
1259#define CB_DEBUG_BUS_20__FC_WRREQ_FIFO_EMPTY_MASK 0x200000
1260#define CB_DEBUG_BUS_20__FC_WRREQ_FIFO_EMPTY__SHIFT 0x15
1261#define CB_DEBUG_BUS_20__CM_WRREQ_FIFO_EMPTY_MASK 0x400000
1262#define CB_DEBUG_BUS_20__CM_WRREQ_FIFO_EMPTY__SHIFT 0x16
1263#define CB_DEBUG_BUS_20__DCC_WRREQ_FIFO_EMPTY_MASK 0x800000
1264#define CB_DEBUG_BUS_20__DCC_WRREQ_FIFO_EMPTY__SHIFT 0x17
1265#define CB_DEBUG_BUS_21__CM_BUSY_MASK 0x1
1266#define CB_DEBUG_BUS_21__CM_BUSY__SHIFT 0x0
1267#define CB_DEBUG_BUS_21__FC_BUSY_MASK 0x2
1268#define CB_DEBUG_BUS_21__FC_BUSY__SHIFT 0x1
1269#define CB_DEBUG_BUS_21__CC_BUSY_MASK 0x4
1270#define CB_DEBUG_BUS_21__CC_BUSY__SHIFT 0x2
1271#define CB_DEBUG_BUS_21__BB_BUSY_MASK 0x8
1272#define CB_DEBUG_BUS_21__BB_BUSY__SHIFT 0x3
1273#define CB_DEBUG_BUS_21__MA_BUSY_MASK 0x10
1274#define CB_DEBUG_BUS_21__MA_BUSY__SHIFT 0x4
1275#define CB_DEBUG_BUS_21__CORE_SCLK_VLD_MASK 0x20
1276#define CB_DEBUG_BUS_21__CORE_SCLK_VLD__SHIFT 0x5
1277#define CB_DEBUG_BUS_21__REG_SCLK1_VLD_MASK 0x40
1278#define CB_DEBUG_BUS_21__REG_SCLK1_VLD__SHIFT 0x6
1279#define CB_DEBUG_BUS_21__REG_SCLK0_VLD_MASK 0x80
1280#define CB_DEBUG_BUS_21__REG_SCLK0_VLD__SHIFT 0x7
1281#define CB_DEBUG_BUS_22__OUTSTANDING_MC_READS_MASK 0xfff
1282#define CB_DEBUG_BUS_22__OUTSTANDING_MC_READS__SHIFT 0x0
1283#define CB_DEBUG_BUS_22__OUTSTANDING_MC_WRITES_MASK 0xfff000
1284#define CB_DEBUG_BUS_22__OUTSTANDING_MC_WRITES__SHIFT 0xc
1285#define CP_DFY_CNTL__POLICY_MASK 0x1
1286#define CP_DFY_CNTL__POLICY__SHIFT 0x0
1287#define CP_DFY_CNTL__MTYPE_MASK 0xc
1288#define CP_DFY_CNTL__MTYPE__SHIFT 0x2
1289#define CP_DFY_CNTL__LFSR_RESET_MASK 0x10000000
1290#define CP_DFY_CNTL__LFSR_RESET__SHIFT 0x1c
1291#define CP_DFY_CNTL__MODE_MASK 0x60000000
1292#define CP_DFY_CNTL__MODE__SHIFT 0x1d
1293#define CP_DFY_CNTL__ENABLE_MASK 0x80000000
1294#define CP_DFY_CNTL__ENABLE__SHIFT 0x1f
1295#define CP_DFY_STAT__BURST_COUNT_MASK 0xffff
1296#define CP_DFY_STAT__BURST_COUNT__SHIFT 0x0
1297#define CP_DFY_STAT__TAGS_PENDING_MASK 0x1ff0000
1298#define CP_DFY_STAT__TAGS_PENDING__SHIFT 0x10
1299#define CP_DFY_STAT__BUSY_MASK 0x80000000
1300#define CP_DFY_STAT__BUSY__SHIFT 0x1f
1301#define CP_DFY_ADDR_HI__ADDR_HI_MASK 0xffffffff
1302#define CP_DFY_ADDR_HI__ADDR_HI__SHIFT 0x0
1303#define CP_DFY_ADDR_LO__ADDR_LO_MASK 0xffffffe0
1304#define CP_DFY_ADDR_LO__ADDR_LO__SHIFT 0x5
1305#define CP_DFY_DATA_0__DATA_MASK 0xffffffff
1306#define CP_DFY_DATA_0__DATA__SHIFT 0x0
1307#define CP_DFY_DATA_1__DATA_MASK 0xffffffff
1308#define CP_DFY_DATA_1__DATA__SHIFT 0x0
1309#define CP_DFY_DATA_2__DATA_MASK 0xffffffff
1310#define CP_DFY_DATA_2__DATA__SHIFT 0x0
1311#define CP_DFY_DATA_3__DATA_MASK 0xffffffff
1312#define CP_DFY_DATA_3__DATA__SHIFT 0x0
1313#define CP_DFY_DATA_4__DATA_MASK 0xffffffff
1314#define CP_DFY_DATA_4__DATA__SHIFT 0x0
1315#define CP_DFY_DATA_5__DATA_MASK 0xffffffff
1316#define CP_DFY_DATA_5__DATA__SHIFT 0x0
1317#define CP_DFY_DATA_6__DATA_MASK 0xffffffff
1318#define CP_DFY_DATA_6__DATA__SHIFT 0x0
1319#define CP_DFY_DATA_7__DATA_MASK 0xffffffff
1320#define CP_DFY_DATA_7__DATA__SHIFT 0x0
1321#define CP_DFY_DATA_8__DATA_MASK 0xffffffff
1322#define CP_DFY_DATA_8__DATA__SHIFT 0x0
1323#define CP_DFY_DATA_9__DATA_MASK 0xffffffff
1324#define CP_DFY_DATA_9__DATA__SHIFT 0x0
1325#define CP_DFY_DATA_10__DATA_MASK 0xffffffff
1326#define CP_DFY_DATA_10__DATA__SHIFT 0x0
1327#define CP_DFY_DATA_11__DATA_MASK 0xffffffff
1328#define CP_DFY_DATA_11__DATA__SHIFT 0x0
1329#define CP_DFY_DATA_12__DATA_MASK 0xffffffff
1330#define CP_DFY_DATA_12__DATA__SHIFT 0x0
1331#define CP_DFY_DATA_13__DATA_MASK 0xffffffff
1332#define CP_DFY_DATA_13__DATA__SHIFT 0x0
1333#define CP_DFY_DATA_14__DATA_MASK 0xffffffff
1334#define CP_DFY_DATA_14__DATA__SHIFT 0x0
1335#define CP_DFY_DATA_15__DATA_MASK 0xffffffff
1336#define CP_DFY_DATA_15__DATA__SHIFT 0x0
1337#define CP_DFY_CMD__OFFSET_MASK 0x1ff
1338#define CP_DFY_CMD__OFFSET__SHIFT 0x0
1339#define CP_DFY_CMD__SIZE_MASK 0xffff0000
1340#define CP_DFY_CMD__SIZE__SHIFT 0x10
1341#define CP_CPC_MGCG_SYNC_CNTL__COOLDOWN_PERIOD_MASK 0xff
1342#define CP_CPC_MGCG_SYNC_CNTL__COOLDOWN_PERIOD__SHIFT 0x0
1343#define CP_CPC_MGCG_SYNC_CNTL__WARMUP_PERIOD_MASK 0xff00
1344#define CP_CPC_MGCG_SYNC_CNTL__WARMUP_PERIOD__SHIFT 0x8
1345#define CP_RB0_BASE__RB_BASE_MASK 0xffffffff
1346#define CP_RB0_BASE__RB_BASE__SHIFT 0x0
1347#define CP_RB0_BASE_HI__RB_BASE_HI_MASK 0xff
1348#define CP_RB0_BASE_HI__RB_BASE_HI__SHIFT 0x0
1349#define CP_RB_BASE__RB_BASE_MASK 0xffffffff
1350#define CP_RB_BASE__RB_BASE__SHIFT 0x0
1351#define CP_RB1_BASE__RB_BASE_MASK 0xffffffff
1352#define CP_RB1_BASE__RB_BASE__SHIFT 0x0
1353#define CP_RB1_BASE_HI__RB_BASE_HI_MASK 0xff
1354#define CP_RB1_BASE_HI__RB_BASE_HI__SHIFT 0x0
1355#define CP_RB2_BASE__RB_BASE_MASK 0xffffffff
1356#define CP_RB2_BASE__RB_BASE__SHIFT 0x0
1357#define CP_RB0_CNTL__RB_BUFSZ_MASK 0x3f
1358#define CP_RB0_CNTL__RB_BUFSZ__SHIFT 0x0
1359#define CP_RB0_CNTL__RB_BLKSZ_MASK 0x3f00
1360#define CP_RB0_CNTL__RB_BLKSZ__SHIFT 0x8
1361#define CP_RB0_CNTL__MTYPE_MASK 0x18000
1362#define CP_RB0_CNTL__MTYPE__SHIFT 0xf
1363#define CP_RB0_CNTL__BUF_SWAP_MASK 0x60000
1364#define CP_RB0_CNTL__BUF_SWAP__SHIFT 0x11
1365#define CP_RB0_CNTL__MIN_AVAILSZ_MASK 0x300000
1366#define CP_RB0_CNTL__MIN_AVAILSZ__SHIFT 0x14
1367#define CP_RB0_CNTL__MIN_IB_AVAILSZ_MASK 0xc00000
1368#define CP_RB0_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16
1369#define CP_RB0_CNTL__CACHE_POLICY_MASK 0x1000000
1370#define CP_RB0_CNTL__CACHE_POLICY__SHIFT 0x18
1371#define CP_RB0_CNTL__RB_NO_UPDATE_MASK 0x8000000
1372#define CP_RB0_CNTL__RB_NO_UPDATE__SHIFT 0x1b
1373#define CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000
1374#define CP_RB0_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f
1375#define CP_RB_CNTL__RB_BUFSZ_MASK 0x3f
1376#define CP_RB_CNTL__RB_BUFSZ__SHIFT 0x0
1377#define CP_RB_CNTL__RB_BLKSZ_MASK 0x3f00
1378#define CP_RB_CNTL__RB_BLKSZ__SHIFT 0x8
1379#define CP_RB_CNTL__MTYPE_MASK 0x18000
1380#define CP_RB_CNTL__MTYPE__SHIFT 0xf
1381#define CP_RB_CNTL__BUF_SWAP_MASK 0x60000
1382#define CP_RB_CNTL__BUF_SWAP__SHIFT 0x11
1383#define CP_RB_CNTL__MIN_AVAILSZ_MASK 0x300000
1384#define CP_RB_CNTL__MIN_AVAILSZ__SHIFT 0x14
1385#define CP_RB_CNTL__MIN_IB_AVAILSZ_MASK 0xc00000
1386#define CP_RB_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16
1387#define CP_RB_CNTL__CACHE_POLICY_MASK 0x1000000
1388#define CP_RB_CNTL__CACHE_POLICY__SHIFT 0x18
1389#define CP_RB_CNTL__RB_NO_UPDATE_MASK 0x8000000
1390#define CP_RB_CNTL__RB_NO_UPDATE__SHIFT 0x1b
1391#define CP_RB_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000
1392#define CP_RB_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f
1393#define CP_RB1_CNTL__RB_BUFSZ_MASK 0x3f
1394#define CP_RB1_CNTL__RB_BUFSZ__SHIFT 0x0
1395#define CP_RB1_CNTL__RB_BLKSZ_MASK 0x3f00
1396#define CP_RB1_CNTL__RB_BLKSZ__SHIFT 0x8
1397#define CP_RB1_CNTL__MTYPE_MASK 0x18000
1398#define CP_RB1_CNTL__MTYPE__SHIFT 0xf
1399#define CP_RB1_CNTL__MIN_AVAILSZ_MASK 0x300000
1400#define CP_RB1_CNTL__MIN_AVAILSZ__SHIFT 0x14
1401#define CP_RB1_CNTL__MIN_IB_AVAILSZ_MASK 0xc00000
1402#define CP_RB1_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16
1403#define CP_RB1_CNTL__CACHE_POLICY_MASK 0x1000000
1404#define CP_RB1_CNTL__CACHE_POLICY__SHIFT 0x18
1405#define CP_RB1_CNTL__RB_NO_UPDATE_MASK 0x8000000
1406#define CP_RB1_CNTL__RB_NO_UPDATE__SHIFT 0x1b
1407#define CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000
1408#define CP_RB1_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f
1409#define CP_RB2_CNTL__RB_BUFSZ_MASK 0x3f
1410#define CP_RB2_CNTL__RB_BUFSZ__SHIFT 0x0
1411#define CP_RB2_CNTL__RB_BLKSZ_MASK 0x3f00
1412#define CP_RB2_CNTL__RB_BLKSZ__SHIFT 0x8
1413#define CP_RB2_CNTL__MTYPE_MASK 0x18000
1414#define CP_RB2_CNTL__MTYPE__SHIFT 0xf
1415#define CP_RB2_CNTL__MIN_AVAILSZ_MASK 0x300000
1416#define CP_RB2_CNTL__MIN_AVAILSZ__SHIFT 0x14
1417#define CP_RB2_CNTL__MIN_IB_AVAILSZ_MASK 0xc00000
1418#define CP_RB2_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16
1419#define CP_RB2_CNTL__CACHE_POLICY_MASK 0x1000000
1420#define CP_RB2_CNTL__CACHE_POLICY__SHIFT 0x18
1421#define CP_RB2_CNTL__RB_NO_UPDATE_MASK 0x8000000
1422#define CP_RB2_CNTL__RB_NO_UPDATE__SHIFT 0x1b
1423#define CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000
1424#define CP_RB2_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f
1425#define CP_RB_RPTR_WR__RB_RPTR_WR_MASK 0xfffff
1426#define CP_RB_RPTR_WR__RB_RPTR_WR__SHIFT 0x0
1427#define CP_RB0_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x3
1428#define CP_RB0_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x0
1429#define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffc
1430#define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2
1431#define CP_RB_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x3
1432#define CP_RB_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x0
1433#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffc
1434#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2
1435#define CP_RB1_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x3
1436#define CP_RB1_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x0
1437#define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffc
1438#define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2
1439#define CP_RB2_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x3
1440#define CP_RB2_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x0
1441#define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffc
1442#define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2
1443#define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0xffff
1444#define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0
1445#define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0xffff
1446#define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0
1447#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0xffff
1448#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0
1449#define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0xffff
1450#define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0
1451#define CP_RB0_WPTR__RB_WPTR_MASK 0xfffff
1452#define CP_RB0_WPTR__RB_WPTR__SHIFT 0x0
1453#define CP_RB_WPTR__RB_WPTR_MASK 0xfffff
1454#define CP_RB_WPTR__RB_WPTR__SHIFT 0x0
1455#define CP_RB1_WPTR__RB_WPTR_MASK 0xfffff
1456#define CP_RB1_WPTR__RB_WPTR__SHIFT 0x0
1457#define CP_RB2_WPTR__RB_WPTR_MASK 0xfffff
1458#define CP_RB2_WPTR__RB_WPTR__SHIFT 0x0
1459#define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO_MASK 0xfffffffc
1460#define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO__SHIFT 0x2
1461#define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI_MASK 0xff
1462#define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI__SHIFT 0x0
1463#define CP_INT_CNTL__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x800
1464#define CP_INT_CNTL__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb
1465#define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
1466#define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
1467#define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
1468#define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
1469#define CP_INT_CNTL__CMP_BUSY_INT_ENABLE_MASK 0x40000
1470#define CP_INT_CNTL__CMP_BUSY_INT_ENABLE__SHIFT 0x12
1471#define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK 0x80000
1472#define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE__SHIFT 0x13
1473#define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK 0x100000
1474#define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14
1475#define CP_INT_CNTL__GFX_IDLE_INT_ENABLE_MASK 0x200000
1476#define CP_INT_CNTL__GFX_IDLE_INT_ENABLE__SHIFT 0x15
1477#define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE_MASK 0x400000
1478#define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE__SHIFT 0x16
1479#define CP_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
1480#define CP_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
1481#define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
1482#define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
1483#define CP_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
1484#define CP_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
1485#define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
1486#define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
1487#define CP_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
1488#define CP_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
1489#define CP_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
1490#define CP_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
1491#define CP_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
1492#define CP_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
1493#define CP_INT_CNTL_RING0__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x800
1494#define CP_INT_CNTL_RING0__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb
1495#define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
1496#define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
1497#define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
1498#define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
1499#define CP_INT_CNTL_RING0__CMP_BUSY_INT_ENABLE_MASK 0x40000
1500#define CP_INT_CNTL_RING0__CMP_BUSY_INT_ENABLE__SHIFT 0x12
1501#define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK 0x80000
1502#define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE__SHIFT 0x13
1503#define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK 0x100000
1504#define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14
1505#define CP_INT_CNTL_RING0__GFX_IDLE_INT_ENABLE_MASK 0x200000
1506#define CP_INT_CNTL_RING0__GFX_IDLE_INT_ENABLE__SHIFT 0x15
1507#define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK 0x400000
1508#define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE__SHIFT 0x16
1509#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK 0x800000
1510#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE__SHIFT 0x17
1511#define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
1512#define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
1513#define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK 0x4000000
1514#define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
1515#define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
1516#define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
1517#define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE_MASK 0x20000000
1518#define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE__SHIFT 0x1d
1519#define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE_MASK 0x40000000
1520#define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE__SHIFT 0x1e
1521#define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE_MASK 0x80000000
1522#define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE__SHIFT 0x1f
1523#define CP_INT_CNTL_RING1__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x800
1524#define CP_INT_CNTL_RING1__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb
1525#define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
1526#define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
1527#define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
1528#define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
1529#define CP_INT_CNTL_RING1__CMP_BUSY_INT_ENABLE_MASK 0x40000
1530#define CP_INT_CNTL_RING1__CMP_BUSY_INT_ENABLE__SHIFT 0x12
1531#define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE_MASK 0x80000
1532#define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE__SHIFT 0x13
1533#define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE_MASK 0x100000
1534#define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14
1535#define CP_INT_CNTL_RING1__GFX_IDLE_INT_ENABLE_MASK 0x200000
1536#define CP_INT_CNTL_RING1__GFX_IDLE_INT_ENABLE__SHIFT 0x15
1537#define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE_MASK 0x400000
1538#define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE__SHIFT 0x16
1539#define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE_MASK 0x800000
1540#define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE__SHIFT 0x17
1541#define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
1542#define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
1543#define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK 0x4000000
1544#define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
1545#define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
1546#define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
1547#define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE_MASK 0x20000000
1548#define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE__SHIFT 0x1d
1549#define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE_MASK 0x40000000
1550#define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE__SHIFT 0x1e
1551#define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE_MASK 0x80000000
1552#define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE__SHIFT 0x1f
1553#define CP_INT_CNTL_RING2__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x800
1554#define CP_INT_CNTL_RING2__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb
1555#define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
1556#define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
1557#define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
1558#define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
1559#define CP_INT_CNTL_RING2__CMP_BUSY_INT_ENABLE_MASK 0x40000
1560#define CP_INT_CNTL_RING2__CMP_BUSY_INT_ENABLE__SHIFT 0x12
1561#define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE_MASK 0x80000
1562#define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE__SHIFT 0x13
1563#define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE_MASK 0x100000
1564#define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14
1565#define CP_INT_CNTL_RING2__GFX_IDLE_INT_ENABLE_MASK 0x200000
1566#define CP_INT_CNTL_RING2__GFX_IDLE_INT_ENABLE__SHIFT 0x15
1567#define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE_MASK 0x400000
1568#define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE__SHIFT 0x16
1569#define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE_MASK 0x800000
1570#define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE__SHIFT 0x17
1571#define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
1572#define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
1573#define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK 0x4000000
1574#define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
1575#define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
1576#define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
1577#define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE_MASK 0x20000000
1578#define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE__SHIFT 0x1d
1579#define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE_MASK 0x40000000
1580#define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE__SHIFT 0x1e
1581#define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE_MASK 0x80000000
1582#define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE__SHIFT 0x1f
1583#define CP_INT_STATUS__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x800
1584#define CP_INT_STATUS__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb
1585#define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT_MASK 0x4000
1586#define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT__SHIFT 0xe
1587#define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x20000
1588#define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11
1589#define CP_INT_STATUS__CMP_BUSY_INT_STAT_MASK 0x40000
1590#define CP_INT_STATUS__CMP_BUSY_INT_STAT__SHIFT 0x12
1591#define CP_INT_STATUS__CNTX_BUSY_INT_STAT_MASK 0x80000
1592#define CP_INT_STATUS__CNTX_BUSY_INT_STAT__SHIFT 0x13
1593#define CP_INT_STATUS__CNTX_EMPTY_INT_STAT_MASK 0x100000
1594#define CP_INT_STATUS__CNTX_EMPTY_INT_STAT__SHIFT 0x14
1595#define CP_INT_STATUS__GFX_IDLE_INT_STAT_MASK 0x200000
1596#define CP_INT_STATUS__GFX_IDLE_INT_STAT__SHIFT 0x15
1597#define CP_INT_STATUS__PRIV_INSTR_INT_STAT_MASK 0x400000
1598#define CP_INT_STATUS__PRIV_INSTR_INT_STAT__SHIFT 0x16
1599#define CP_INT_STATUS__PRIV_REG_INT_STAT_MASK 0x800000
1600#define CP_INT_STATUS__PRIV_REG_INT_STAT__SHIFT 0x17
1601#define CP_INT_STATUS__OPCODE_ERROR_INT_STAT_MASK 0x1000000
1602#define CP_INT_STATUS__OPCODE_ERROR_INT_STAT__SHIFT 0x18
1603#define CP_INT_STATUS__TIME_STAMP_INT_STAT_MASK 0x4000000
1604#define CP_INT_STATUS__TIME_STAMP_INT_STAT__SHIFT 0x1a
1605#define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT_MASK 0x8000000
1606#define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b
1607#define CP_INT_STATUS__GENERIC2_INT_STAT_MASK 0x20000000
1608#define CP_INT_STATUS__GENERIC2_INT_STAT__SHIFT 0x1d
1609#define CP_INT_STATUS__GENERIC1_INT_STAT_MASK 0x40000000
1610#define CP_INT_STATUS__GENERIC1_INT_STAT__SHIFT 0x1e
1611#define CP_INT_STATUS__GENERIC0_INT_STAT_MASK 0x80000000
1612#define CP_INT_STATUS__GENERIC0_INT_STAT__SHIFT 0x1f
1613#define CP_INT_STATUS_RING0__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x800
1614#define CP_INT_STATUS_RING0__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb
1615#define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT_MASK 0x4000
1616#define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT__SHIFT 0xe
1617#define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x20000
1618#define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11
1619#define CP_INT_STATUS_RING0__CMP_BUSY_INT_STAT_MASK 0x40000
1620#define CP_INT_STATUS_RING0__CMP_BUSY_INT_STAT__SHIFT 0x12
1621#define CP_INT_STATUS_RING0__GCNTX_BUSY_INT_STAT_MASK 0x80000
1622#define CP_INT_STATUS_RING0__GCNTX_BUSY_INT_STAT__SHIFT 0x13
1623#define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT_MASK 0x100000
1624#define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT__SHIFT 0x14
1625#define CP_INT_STATUS_RING0__GFX_IDLE_INT_STAT_MASK 0x200000
1626#define CP_INT_STATUS_RING0__GFX_IDLE_INT_STAT__SHIFT 0x15
1627#define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT_MASK 0x400000
1628#define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT__SHIFT 0x16
1629#define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT_MASK 0x800000
1630#define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT__SHIFT 0x17
1631#define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT_MASK 0x1000000
1632#define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT__SHIFT 0x18
1633#define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT_MASK 0x4000000
1634#define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT__SHIFT 0x1a
1635#define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT_MASK 0x8000000
1636#define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b
1637#define CP_INT_STATUS_RING0__GENERIC2_INT_STAT_MASK 0x20000000
1638#define CP_INT_STATUS_RING0__GENERIC2_INT_STAT__SHIFT 0x1d
1639#define CP_INT_STATUS_RING0__GENERIC1_INT_STAT_MASK 0x40000000
1640#define CP_INT_STATUS_RING0__GENERIC1_INT_STAT__SHIFT 0x1e
1641#define CP_INT_STATUS_RING0__GENERIC0_INT_STAT_MASK 0x80000000
1642#define CP_INT_STATUS_RING0__GENERIC0_INT_STAT__SHIFT 0x1f
1643#define CP_INT_STATUS_RING1__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x800
1644#define CP_INT_STATUS_RING1__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb
1645#define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT_MASK 0x4000
1646#define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT__SHIFT 0xe
1647#define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x20000
1648#define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11
1649#define CP_INT_STATUS_RING1__CMP_BUSY_INT_STAT_MASK 0x40000
1650#define CP_INT_STATUS_RING1__CMP_BUSY_INT_STAT__SHIFT 0x12
1651#define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT_MASK 0x80000
1652#define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT__SHIFT 0x13
1653#define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT_MASK 0x100000
1654#define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT__SHIFT 0x14
1655#define CP_INT_STATUS_RING1__GFX_IDLE_INT_STAT_MASK 0x200000
1656#define CP_INT_STATUS_RING1__GFX_IDLE_INT_STAT__SHIFT 0x15
1657#define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT_MASK 0x400000
1658#define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT__SHIFT 0x16
1659#define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT_MASK 0x800000
1660#define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT__SHIFT 0x17
1661#define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT_MASK 0x1000000
1662#define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT__SHIFT 0x18
1663#define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT_MASK 0x4000000
1664#define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT__SHIFT 0x1a
1665#define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT_MASK 0x8000000
1666#define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b
1667#define CP_INT_STATUS_RING1__GENERIC2_INT_STAT_MASK 0x20000000
1668#define CP_INT_STATUS_RING1__GENERIC2_INT_STAT__SHIFT 0x1d
1669#define CP_INT_STATUS_RING1__GENERIC1_INT_STAT_MASK 0x40000000
1670#define CP_INT_STATUS_RING1__GENERIC1_INT_STAT__SHIFT 0x1e
1671#define CP_INT_STATUS_RING1__GENERIC0_INT_STAT_MASK 0x80000000
1672#define CP_INT_STATUS_RING1__GENERIC0_INT_STAT__SHIFT 0x1f
1673#define CP_INT_STATUS_RING2__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x800
1674#define CP_INT_STATUS_RING2__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb
1675#define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT_MASK 0x4000
1676#define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT__SHIFT 0xe
1677#define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x20000
1678#define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11
1679#define CP_INT_STATUS_RING2__CMP_BUSY_INT_STAT_MASK 0x40000
1680#define CP_INT_STATUS_RING2__CMP_BUSY_INT_STAT__SHIFT 0x12
1681#define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT_MASK 0x80000
1682#define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT__SHIFT 0x13
1683#define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT_MASK 0x100000
1684#define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT__SHIFT 0x14
1685#define CP_INT_STATUS_RING2__GFX_IDLE_INT_STAT_MASK 0x200000
1686#define CP_INT_STATUS_RING2__GFX_IDLE_INT_STAT__SHIFT 0x15
1687#define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT_MASK 0x400000
1688#define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT__SHIFT 0x16
1689#define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT_MASK 0x800000
1690#define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT__SHIFT 0x17
1691#define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT_MASK 0x1000000
1692#define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT__SHIFT 0x18
1693#define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT_MASK 0x4000000
1694#define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT__SHIFT 0x1a
1695#define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT_MASK 0x8000000
1696#define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b
1697#define CP_INT_STATUS_RING2__GENERIC2_INT_STAT_MASK 0x20000000
1698#define CP_INT_STATUS_RING2__GENERIC2_INT_STAT__SHIFT 0x1d
1699#define CP_INT_STATUS_RING2__GENERIC1_INT_STAT_MASK 0x40000000
1700#define CP_INT_STATUS_RING2__GENERIC1_INT_STAT__SHIFT 0x1e
1701#define CP_INT_STATUS_RING2__GENERIC0_INT_STAT_MASK 0x80000000
1702#define CP_INT_STATUS_RING2__GENERIC0_INT_STAT__SHIFT 0x1f
1703#define CP_DEVICE_ID__DEVICE_ID_MASK 0xff
1704#define CP_DEVICE_ID__DEVICE_ID__SHIFT 0x0
1705#define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0xff
1706#define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0
1707#define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0xff00
1708#define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8
1709#define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0xff0000
1710#define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10
1711#define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000
1712#define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18
1713#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0xff
1714#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0
1715#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0xff00
1716#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8
1717#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0xff0000
1718#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10
1719#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000
1720#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18
1721#define CP_RING0_PRIORITY__PRIORITY_MASK 0x3
1722#define CP_RING0_PRIORITY__PRIORITY__SHIFT 0x0
1723#define CP_ME0_PIPE0_PRIORITY__PRIORITY_MASK 0x3
1724#define CP_ME0_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0
1725#define CP_RING1_PRIORITY__PRIORITY_MASK 0x3
1726#define CP_RING1_PRIORITY__PRIORITY__SHIFT 0x0
1727#define CP_ME0_PIPE1_PRIORITY__PRIORITY_MASK 0x3
1728#define CP_ME0_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0
1729#define CP_RING2_PRIORITY__PRIORITY_MASK 0x3
1730#define CP_RING2_PRIORITY__PRIORITY__SHIFT 0x0
1731#define CP_ME0_PIPE2_PRIORITY__PRIORITY_MASK 0x3
1732#define CP_ME0_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0
1733#define CP_ENDIAN_SWAP__ENDIAN_SWAP_MASK 0x3
1734#define CP_ENDIAN_SWAP__ENDIAN_SWAP__SHIFT 0x0
1735#define CP_RB_VMID__RB0_VMID_MASK 0xf
1736#define CP_RB_VMID__RB0_VMID__SHIFT 0x0
1737#define CP_RB_VMID__RB1_VMID_MASK 0xf00
1738#define CP_RB_VMID__RB1_VMID__SHIFT 0x8
1739#define CP_RB_VMID__RB2_VMID_MASK 0xf0000
1740#define CP_RB_VMID__RB2_VMID__SHIFT 0x10
1741#define CP_ME0_PIPE0_VMID__VMID_MASK 0xf
1742#define CP_ME0_PIPE0_VMID__VMID__SHIFT 0x0
1743#define CP_ME0_PIPE1_VMID__VMID_MASK 0xf
1744#define CP_ME0_PIPE1_VMID__VMID__SHIFT 0x0
1745#define CP_RB_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x7ffffc
1746#define CP_RB_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x2
1747#define CP_RB_DOORBELL_CONTROL__DOORBELL_EN_MASK 0x40000000
1748#define CP_RB_DOORBELL_CONTROL__DOORBELL_EN__SHIFT 0x1e
1749#define CP_RB_DOORBELL_CONTROL__DOORBELL_HIT_MASK 0x80000000
1750#define CP_RB_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT 0x1f
1751#define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_MASK 0x7ffffc
1752#define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER__SHIFT 0x2
1753#define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK 0x7ffffc
1754#define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER__SHIFT 0x2
1755#define CP_MEC_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_MASK 0x7ffffc
1756#define CP_MEC_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER__SHIFT 0x2
1757#define CP_MEC_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK 0x7ffffc
1758#define CP_MEC_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER__SHIFT 0x2
1759#define CP_PFP_UCODE_ADDR__UCODE_ADDR_MASK 0x1fff
1760#define CP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
1761#define CP_PFP_UCODE_DATA__UCODE_DATA_MASK 0xffffffff
1762#define CP_PFP_UCODE_DATA__UCODE_DATA__SHIFT 0x0
1763#define CP_ME_RAM_RADDR__ME_RAM_RADDR_MASK 0x1fff
1764#define CP_ME_RAM_RADDR__ME_RAM_RADDR__SHIFT 0x0
1765#define CP_ME_RAM_WADDR__ME_RAM_WADDR_MASK 0x1fff
1766#define CP_ME_RAM_WADDR__ME_RAM_WADDR__SHIFT 0x0
1767#define CP_ME_RAM_DATA__ME_RAM_DATA_MASK 0xffffffff
1768#define CP_ME_RAM_DATA__ME_RAM_DATA__SHIFT 0x0
1769#define CGTT_CPC_CLK_CTRL__ON_DELAY_MASK 0xf
1770#define CGTT_CPC_CLK_CTRL__ON_DELAY__SHIFT 0x0
1771#define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
1772#define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
1773#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000
1774#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d
1775#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000
1776#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
1777#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000
1778#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
1779#define CGTT_CPF_CLK_CTRL__ON_DELAY_MASK 0xf
1780#define CGTT_CPF_CLK_CTRL__ON_DELAY__SHIFT 0x0
1781#define CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
1782#define CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
1783#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000
1784#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d
1785#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000
1786#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
1787#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000
1788#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
1789#define CGTT_CP_CLK_CTRL__ON_DELAY_MASK 0xf
1790#define CGTT_CP_CLK_CTRL__ON_DELAY__SHIFT 0x0
1791#define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
1792#define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
1793#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000
1794#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d
1795#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000
1796#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
1797#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000
1798#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
1799#define CP_CE_UCODE_ADDR__UCODE_ADDR_MASK 0xfff
1800#define CP_CE_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
1801#define CP_CE_UCODE_DATA__UCODE_DATA_MASK 0xffffffff
1802#define CP_CE_UCODE_DATA__UCODE_DATA__SHIFT 0x0
1803#define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR_MASK 0x1ffff
1804#define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
1805#define CP_MEC_ME1_UCODE_DATA__UCODE_DATA_MASK 0xffffffff
1806#define CP_MEC_ME1_UCODE_DATA__UCODE_DATA__SHIFT 0x0
1807#define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR_MASK 0x1ffff
1808#define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
1809#define CP_MEC_ME2_UCODE_DATA__UCODE_DATA_MASK 0xffffffff
1810#define CP_MEC_ME2_UCODE_DATA__UCODE_DATA__SHIFT 0x0
1811#define CP_PFP_F32_INTERRUPT__PRIV_REG_INT_MASK 0x2
1812#define CP_PFP_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1
1813#define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT_MASK 0x2
1814#define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1
1815#define CP_MEC2_F32_INTERRUPT__PRIV_REG_INT_MASK 0x2
1816#define CP_MEC2_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1
1817#define CP_MEC1_F32_INT_DIS__EDC_ROQ_FED_INT_MASK 0x1
1818#define CP_MEC1_F32_INT_DIS__EDC_ROQ_FED_INT__SHIFT 0x0
1819#define CP_MEC1_F32_INT_DIS__PRIV_REG_INT_MASK 0x2
1820#define CP_MEC1_F32_INT_DIS__PRIV_REG_INT__SHIFT 0x1
1821#define CP_MEC1_F32_INT_DIS__RESERVED_BIT_ERR_INT_MASK 0x4
1822#define CP_MEC1_F32_INT_DIS__RESERVED_BIT_ERR_INT__SHIFT 0x2
1823#define CP_MEC1_F32_INT_DIS__EDC_TC_FED_INT_MASK 0x8
1824#define CP_MEC1_F32_INT_DIS__EDC_TC_FED_INT__SHIFT 0x3
1825#define CP_MEC1_F32_INT_DIS__EDC_GDS_FED_INT_MASK 0x10
1826#define CP_MEC1_F32_INT_DIS__EDC_GDS_FED_INT__SHIFT 0x4
1827#define CP_MEC1_F32_INT_DIS__EDC_SCRATCH_FED_INT_MASK 0x20
1828#define CP_MEC1_F32_INT_DIS__EDC_SCRATCH_FED_INT__SHIFT 0x5
1829#define CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT_MASK 0x40
1830#define CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT 0x6
1831#define CP_MEC1_F32_INT_DIS__SUA_VIOLATION_INT_MASK 0x80
1832#define CP_MEC1_F32_INT_DIS__SUA_VIOLATION_INT__SHIFT 0x7
1833#define CP_MEC1_F32_INT_DIS__EDC_DMA_FED_INT_MASK 0x100
1834#define CP_MEC1_F32_INT_DIS__EDC_DMA_FED_INT__SHIFT 0x8
1835#define CP_MEC1_F32_INT_DIS__IQ_TIMER_INT_MASK 0x200
1836#define CP_MEC1_F32_INT_DIS__IQ_TIMER_INT__SHIFT 0x9
1837#define CP_MEC2_F32_INT_DIS__EDC_ROQ_FED_INT_MASK 0x1
1838#define CP_MEC2_F32_INT_DIS__EDC_ROQ_FED_INT__SHIFT 0x0
1839#define CP_MEC2_F32_INT_DIS__PRIV_REG_INT_MASK 0x2
1840#define CP_MEC2_F32_INT_DIS__PRIV_REG_INT__SHIFT 0x1
1841#define CP_MEC2_F32_INT_DIS__RESERVED_BIT_ERR_INT_MASK 0x4
1842#define CP_MEC2_F32_INT_DIS__RESERVED_BIT_ERR_INT__SHIFT 0x2
1843#define CP_MEC2_F32_INT_DIS__EDC_TC_FED_INT_MASK 0x8
1844#define CP_MEC2_F32_INT_DIS__EDC_TC_FED_INT__SHIFT 0x3
1845#define CP_MEC2_F32_INT_DIS__EDC_GDS_FED_INT_MASK 0x10
1846#define CP_MEC2_F32_INT_DIS__EDC_GDS_FED_INT__SHIFT 0x4
1847#define CP_MEC2_F32_INT_DIS__EDC_SCRATCH_FED_INT_MASK 0x20
1848#define CP_MEC2_F32_INT_DIS__EDC_SCRATCH_FED_INT__SHIFT 0x5
1849#define CP_MEC2_F32_INT_DIS__WAVE_RESTORE_INT_MASK 0x40
1850#define CP_MEC2_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT 0x6
1851#define CP_MEC2_F32_INT_DIS__SUA_VIOLATION_INT_MASK 0x80
1852#define CP_MEC2_F32_INT_DIS__SUA_VIOLATION_INT__SHIFT 0x7
1853#define CP_MEC2_F32_INT_DIS__EDC_DMA_FED_INT_MASK 0x100
1854#define CP_MEC2_F32_INT_DIS__EDC_DMA_FED_INT__SHIFT 0x8
1855#define CP_MEC2_F32_INT_DIS__IQ_TIMER_INT_MASK 0x200
1856#define CP_MEC2_F32_INT_DIS__IQ_TIMER_INT__SHIFT 0x9
1857#define CP_VIRT_STATUS__VIRT_STATUS_MASK 0xffffffff
1858#define CP_VIRT_STATUS__VIRT_STATUS__SHIFT 0x0
1859#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0_MASK 0x1
1860#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0__SHIFT 0x0
1861#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1_MASK 0x2
1862#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1__SHIFT 0x1
1863#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0_MASK 0x100
1864#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0__SHIFT 0x8
1865#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1_MASK 0x200
1866#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1__SHIFT 0x9
1867#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2_MASK 0x400
1868#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2__SHIFT 0xa
1869#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE3_MASK 0x800
1870#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE3__SHIFT 0xb
1871#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0_MASK 0x10000
1872#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0__SHIFT 0x10
1873#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE1_MASK 0x20000
1874#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE1__SHIFT 0x11
1875#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2_MASK 0x40000
1876#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2__SHIFT 0x12
1877#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3_MASK 0x80000
1878#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3__SHIFT 0x13
1879#define CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK 0x1
1880#define CP_MEM_SLP_CNTL__CP_MEM_LS_EN__SHIFT 0x0
1881#define CP_MEM_SLP_CNTL__CP_MEM_DS_EN_MASK 0x2
1882#define CP_MEM_SLP_CNTL__CP_MEM_DS_EN__SHIFT 0x1
1883#define CP_MEM_SLP_CNTL__RESERVED_MASK 0x7c
1884#define CP_MEM_SLP_CNTL__RESERVED__SHIFT 0x2
1885#define CP_MEM_SLP_CNTL__CP_LS_DS_BUSY_OVERRIDE_MASK 0x80
1886#define CP_MEM_SLP_CNTL__CP_LS_DS_BUSY_OVERRIDE__SHIFT 0x7
1887#define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY_MASK 0xff00
1888#define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY__SHIFT 0x8
1889#define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY_MASK 0xff0000
1890#define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY__SHIFT 0x10
1891#define CP_MEM_SLP_CNTL__RESERVED1_MASK 0xff000000
1892#define CP_MEM_SLP_CNTL__RESERVED1__SHIFT 0x18
1893#define CP_ECC_FIRSTOCCURRENCE__INTERFACE_MASK 0x3
1894#define CP_ECC_FIRSTOCCURRENCE__INTERFACE__SHIFT 0x0
1895#define CP_ECC_FIRSTOCCURRENCE__CLIENT_MASK 0xf0
1896#define CP_ECC_FIRSTOCCURRENCE__CLIENT__SHIFT 0x4
1897#define CP_ECC_FIRSTOCCURRENCE__ME_MASK 0x300
1898#define CP_ECC_FIRSTOCCURRENCE__ME__SHIFT 0x8
1899#define CP_ECC_FIRSTOCCURRENCE__PIPE_MASK 0xc00
1900#define CP_ECC_FIRSTOCCURRENCE__PIPE__SHIFT 0xa
1901#define CP_ECC_FIRSTOCCURRENCE__QUEUE_MASK 0x7000
1902#define CP_ECC_FIRSTOCCURRENCE__QUEUE__SHIFT 0xc
1903#define CP_ECC_FIRSTOCCURRENCE__VMID_MASK 0xf0000
1904#define CP_ECC_FIRSTOCCURRENCE__VMID__SHIFT 0x10
1905#define CP_ECC_FIRSTOCCURRENCE_RING0__OBSOLETE_MASK 0xffffffff
1906#define CP_ECC_FIRSTOCCURRENCE_RING0__OBSOLETE__SHIFT 0x0
1907#define CP_ECC_FIRSTOCCURRENCE_RING1__OBSOLETE_MASK 0xffffffff
1908#define CP_ECC_FIRSTOCCURRENCE_RING1__OBSOLETE__SHIFT 0x0
1909#define CP_ECC_FIRSTOCCURRENCE_RING2__OBSOLETE_MASK 0xffffffff
1910#define CP_ECC_FIRSTOCCURRENCE_RING2__OBSOLETE__SHIFT 0x0
1911#define CP_PQ_WPTR_POLL_CNTL__PERIOD_MASK 0xff
1912#define CP_PQ_WPTR_POLL_CNTL__PERIOD__SHIFT 0x0
1913#define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE_MASK 0x40000000
1914#define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE__SHIFT 0x1e
1915#define CP_PQ_WPTR_POLL_CNTL__EN_MASK 0x80000000
1916#define CP_PQ_WPTR_POLL_CNTL__EN__SHIFT 0x1f
1917#define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK_MASK 0xffffffff
1918#define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK__SHIFT 0x0
1919#define CPC_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000
1920#define CPC_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
1921#define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
1922#define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
1923#define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
1924#define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
1925#define CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000
1926#define CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
1927#define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
1928#define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
1929#define CPC_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
1930#define CPC_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
1931#define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
1932#define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
1933#define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
1934#define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
1935#define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
1936#define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
1937#define CPC_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
1938#define CPC_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
1939#define CPC_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
1940#define CPC_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
1941#define CPC_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
1942#define CPC_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
1943#define CP_ME1_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000
1944#define CP_ME1_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
1945#define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
1946#define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
1947#define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
1948#define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
1949#define CP_ME1_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000
1950#define CP_ME1_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
1951#define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
1952#define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
1953#define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
1954#define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
1955#define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
1956#define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
1957#define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
1958#define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
1959#define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
1960#define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
1961#define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
1962#define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
1963#define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
1964#define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
1965#define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
1966#define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
1967#define CP_ME1_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000
1968#define CP_ME1_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
1969#define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
1970#define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
1971#define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
1972#define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
1973#define CP_ME1_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000
1974#define CP_ME1_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
1975#define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
1976#define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
1977#define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
1978#define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
1979#define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
1980#define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
1981#define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
1982#define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
1983#define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
1984#define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
1985#define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
1986#define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
1987#define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
1988#define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
1989#define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
1990#define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
1991#define CP_ME1_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000
1992#define CP_ME1_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
1993#define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
1994#define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
1995#define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
1996#define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
1997#define CP_ME1_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000
1998#define CP_ME1_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
1999#define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
2000#define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
2001#define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
2002#define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
2003#define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
2004#define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
2005#define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
2006#define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
2007#define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
2008#define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
2009#define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
2010#define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
2011#define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
2012#define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
2013#define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
2014#define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
2015#define CP_ME1_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000
2016#define CP_ME1_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
2017#define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
2018#define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
2019#define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
2020#define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
2021#define CP_ME1_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000
2022#define CP_ME1_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
2023#define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
2024#define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
2025#define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
2026#define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
2027#define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
2028#define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
2029#define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
2030#define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
2031#define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
2032#define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
2033#define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
2034#define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
2035#define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
2036#define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
2037#define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
2038#define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
2039#define CP_ME2_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000
2040#define CP_ME2_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
2041#define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
2042#define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
2043#define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
2044#define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
2045#define CP_ME2_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000
2046#define CP_ME2_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
2047#define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
2048#define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
2049#define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
2050#define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
2051#define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
2052#define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
2053#define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
2054#define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
2055#define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
2056#define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
2057#define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
2058#define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
2059#define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
2060#define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
2061#define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
2062#define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
2063#define CP_ME2_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000
2064#define CP_ME2_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
2065#define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
2066#define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
2067#define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
2068#define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
2069#define CP_ME2_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000
2070#define CP_ME2_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
2071#define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
2072#define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
2073#define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
2074#define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
2075#define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
2076#define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
2077#define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
2078#define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
2079#define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
2080#define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
2081#define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
2082#define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
2083#define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
2084#define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
2085#define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
2086#define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
2087#define CP_ME2_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000
2088#define CP_ME2_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
2089#define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
2090#define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
2091#define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
2092#define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
2093#define CP_ME2_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000
2094#define CP_ME2_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
2095#define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
2096#define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
2097#define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
2098#define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
2099#define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
2100#define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
2101#define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
2102#define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
2103#define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
2104#define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
2105#define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
2106#define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
2107#define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
2108#define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
2109#define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
2110#define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
2111#define CP_ME2_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000
2112#define CP_ME2_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
2113#define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
2114#define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
2115#define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
2116#define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
2117#define CP_ME2_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000
2118#define CP_ME2_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
2119#define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
2120#define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
2121#define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
2122#define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
2123#define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
2124#define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
2125#define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
2126#define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
2127#define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
2128#define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
2129#define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
2130#define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
2131#define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
2132#define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
2133#define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
2134#define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
2135#define CPC_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000
2136#define CPC_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
2137#define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
2138#define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
2139#define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
2140#define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
2141#define CPC_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000
2142#define CPC_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
2143#define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
2144#define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
2145#define CPC_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
2146#define CPC_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
2147#define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
2148#define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
2149#define CPC_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
2150#define CPC_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
2151#define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
2152#define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
2153#define CPC_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
2154#define CPC_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
2155#define CPC_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
2156#define CPC_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
2157#define CPC_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
2158#define CPC_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
2159#define CP_ME1_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000
2160#define CP_ME1_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
2161#define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
2162#define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
2163#define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
2164#define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
2165#define CP_ME1_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000
2166#define CP_ME1_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
2167#define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
2168#define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
2169#define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
2170#define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
2171#define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
2172#define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
2173#define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
2174#define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
2175#define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
2176#define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
2177#define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
2178#define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
2179#define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
2180#define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
2181#define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
2182#define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
2183#define CP_ME1_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000
2184#define CP_ME1_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
2185#define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
2186#define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
2187#define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
2188#define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
2189#define CP_ME1_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000
2190#define CP_ME1_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
2191#define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
2192#define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
2193#define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
2194#define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
2195#define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
2196#define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
2197#define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
2198#define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
2199#define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
2200#define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
2201#define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
2202#define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
2203#define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
2204#define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
2205#define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
2206#define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
2207#define CP_ME1_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000
2208#define CP_ME1_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
2209#define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
2210#define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
2211#define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
2212#define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
2213#define CP_ME1_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000
2214#define CP_ME1_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
2215#define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
2216#define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
2217#define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
2218#define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
2219#define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
2220#define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
2221#define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
2222#define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
2223#define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
2224#define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
2225#define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
2226#define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
2227#define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
2228#define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
2229#define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
2230#define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
2231#define CP_ME1_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000
2232#define CP_ME1_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
2233#define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
2234#define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
2235#define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
2236#define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
2237#define CP_ME1_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000
2238#define CP_ME1_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
2239#define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
2240#define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
2241#define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
2242#define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
2243#define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
2244#define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
2245#define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
2246#define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
2247#define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
2248#define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
2249#define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
2250#define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
2251#define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
2252#define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
2253#define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
2254#define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
2255#define CP_ME2_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000
2256#define CP_ME2_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
2257#define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
2258#define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
2259#define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
2260#define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
2261#define CP_ME2_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000
2262#define CP_ME2_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
2263#define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
2264#define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
2265#define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
2266#define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
2267#define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
2268#define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
2269#define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
2270#define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
2271#define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
2272#define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
2273#define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
2274#define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
2275#define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
2276#define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
2277#define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
2278#define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
2279#define CP_ME2_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000
2280#define CP_ME2_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
2281#define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
2282#define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
2283#define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
2284#define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
2285#define CP_ME2_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000
2286#define CP_ME2_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
2287#define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
2288#define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
2289#define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
2290#define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
2291#define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
2292#define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
2293#define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
2294#define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
2295#define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
2296#define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
2297#define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
2298#define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
2299#define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
2300#define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
2301#define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
2302#define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
2303#define CP_ME2_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000
2304#define CP_ME2_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
2305#define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
2306#define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
2307#define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
2308#define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
2309#define CP_ME2_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000
2310#define CP_ME2_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
2311#define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
2312#define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
2313#define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
2314#define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
2315#define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
2316#define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
2317#define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
2318#define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
2319#define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
2320#define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
2321#define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
2322#define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
2323#define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
2324#define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
2325#define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
2326#define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
2327#define CP_ME2_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000
2328#define CP_ME2_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
2329#define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
2330#define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
2331#define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
2332#define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
2333#define CP_ME2_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000
2334#define CP_ME2_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
2335#define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
2336#define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
2337#define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
2338#define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
2339#define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
2340#define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
2341#define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
2342#define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
2343#define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
2344#define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
2345#define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
2346#define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
2347#define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
2348#define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
2349#define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
2350#define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
2351#define CP_ME1_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED_MASK 0x1000
2352#define CP_ME1_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED__SHIFT 0xc
2353#define CP_ME1_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED_MASK 0x2000
2354#define CP_ME1_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED__SHIFT 0xd
2355#define CP_ME1_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x4000
2356#define CP_ME1_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0xe
2357#define CP_ME1_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS_MASK 0x8000
2358#define CP_ME1_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
2359#define CP_ME1_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x20000
2360#define CP_ME1_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x11
2361#define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x800000
2362#define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17
2363#define CP_ME1_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x1000000
2364#define CP_ME1_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x18
2365#define CP_ME1_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x4000000
2366#define CP_ME1_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x1a
2367#define CP_ME1_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x8000000
2368#define CP_ME1_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x1b
2369#define CP_ME1_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000
2370#define CP_ME1_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d
2371#define CP_ME1_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000
2372#define CP_ME1_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x1e
2373#define CP_ME1_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000
2374#define CP_ME1_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x1f
2375#define CP_ME2_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED_MASK 0x1000
2376#define CP_ME2_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED__SHIFT 0xc
2377#define CP_ME2_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED_MASK 0x2000
2378#define CP_ME2_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED__SHIFT 0xd
2379#define CP_ME2_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x4000
2380#define CP_ME2_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0xe
2381#define CP_ME2_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS_MASK 0x8000
2382#define CP_ME2_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
2383#define CP_ME2_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x20000
2384#define CP_ME2_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x11
2385#define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x800000
2386#define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17
2387#define CP_ME2_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x1000000
2388#define CP_ME2_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x18
2389#define CP_ME2_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x4000000
2390#define CP_ME2_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x1a
2391#define CP_ME2_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x8000000
2392#define CP_ME2_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x1b
2393#define CP_ME2_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000
2394#define CP_ME2_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d
2395#define CP_ME2_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000
2396#define CP_ME2_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x1e
2397#define CP_ME2_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000
2398#define CP_ME2_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x1f
2399#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0xff
2400#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0
2401#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0xff00
2402#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8
2403#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0xff0000
2404#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10
2405#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000
2406#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18
2407#define CP_ME1_PIPE0_PRIORITY__PRIORITY_MASK 0x3
2408#define CP_ME1_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0
2409#define CP_ME1_PIPE1_PRIORITY__PRIORITY_MASK 0x3
2410#define CP_ME1_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0
2411#define CP_ME1_PIPE2_PRIORITY__PRIORITY_MASK 0x3
2412#define CP_ME1_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0
2413#define CP_ME1_PIPE3_PRIORITY__PRIORITY_MASK 0x3
2414#define CP_ME1_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0
2415#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0xff
2416#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0
2417#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0xff00
2418#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8
2419#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0xff0000
2420#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10
2421#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000
2422#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18
2423#define CP_ME2_PIPE0_PRIORITY__PRIORITY_MASK 0x3
2424#define CP_ME2_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0
2425#define CP_ME2_PIPE1_PRIORITY__PRIORITY_MASK 0x3
2426#define CP_ME2_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0
2427#define CP_ME2_PIPE2_PRIORITY__PRIORITY_MASK 0x3
2428#define CP_ME2_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0
2429#define CP_ME2_PIPE3_PRIORITY__PRIORITY_MASK 0x3
2430#define CP_ME2_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0
2431#define CP_CE_PRGRM_CNTR_START__IP_START_MASK 0x7ff
2432#define CP_CE_PRGRM_CNTR_START__IP_START__SHIFT 0x0
2433#define CP_PFP_PRGRM_CNTR_START__IP_START_MASK 0xfff
2434#define CP_PFP_PRGRM_CNTR_START__IP_START__SHIFT 0x0
2435#define CP_ME_PRGRM_CNTR_START__IP_START_MASK 0xfff
2436#define CP_ME_PRGRM_CNTR_START__IP_START__SHIFT 0x0
2437#define CP_MEC1_PRGRM_CNTR_START__IP_START_MASK 0xffff
2438#define CP_MEC1_PRGRM_CNTR_START__IP_START__SHIFT 0x0
2439#define CP_MEC2_PRGRM_CNTR_START__IP_START_MASK 0xffff
2440#define CP_MEC2_PRGRM_CNTR_START__IP_START__SHIFT 0x0
2441#define CP_CE_INTR_ROUTINE_START__IR_START_MASK 0x7ff
2442#define CP_CE_INTR_ROUTINE_START__IR_START__SHIFT 0x0
2443#define CP_PFP_INTR_ROUTINE_START__IR_START_MASK 0xfff
2444#define CP_PFP_INTR_ROUTINE_START__IR_START__SHIFT 0x0
2445#define CP_ME_INTR_ROUTINE_START__IR_START_MASK 0xfff
2446#define CP_ME_INTR_ROUTINE_START__IR_START__SHIFT 0x0
2447#define CP_MEC1_INTR_ROUTINE_START__IR_START_MASK 0xffff
2448#define CP_MEC1_INTR_ROUTINE_START__IR_START__SHIFT 0x0
2449#define CP_MEC2_INTR_ROUTINE_START__IR_START_MASK 0xffff
2450#define CP_MEC2_INTR_ROUTINE_START__IR_START__SHIFT 0x0
2451#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_WD_CNTX_MASK 0x7
2452#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_WD_CNTX__SHIFT 0x0
2453#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX_MASK 0x70
2454#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX__SHIFT 0x4
2455#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_WD_CNTX_MASK 0x70000
2456#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_WD_CNTX__SHIFT 0x10
2457#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX_MASK 0x700000
2458#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX__SHIFT 0x14
2459#define CP_MAX_CONTEXT__MAX_CONTEXT_MASK 0x7
2460#define CP_MAX_CONTEXT__MAX_CONTEXT__SHIFT 0x0
2461#define CP_IQ_WAIT_TIME1__IB_OFFLOAD_MASK 0xff
2462#define CP_IQ_WAIT_TIME1__IB_OFFLOAD__SHIFT 0x0
2463#define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD_MASK 0xff00
2464#define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD__SHIFT 0x8
2465#define CP_IQ_WAIT_TIME1__WRM_OFFLOAD_MASK 0xff0000
2466#define CP_IQ_WAIT_TIME1__WRM_OFFLOAD__SHIFT 0x10
2467#define CP_IQ_WAIT_TIME1__GWS_MASK 0xff000000
2468#define CP_IQ_WAIT_TIME1__GWS__SHIFT 0x18
2469#define CP_IQ_WAIT_TIME2__QUE_SLEEP_MASK 0xff
2470#define CP_IQ_WAIT_TIME2__QUE_SLEEP__SHIFT 0x0
2471#define CP_IQ_WAIT_TIME2__SCH_WAVE_MASK 0xff00
2472#define CP_IQ_WAIT_TIME2__SCH_WAVE__SHIFT 0x8
2473#define CP_IQ_WAIT_TIME2__SEM_REARM_MASK 0xff0000
2474#define CP_IQ_WAIT_TIME2__SEM_REARM__SHIFT 0x10
2475#define CP_IQ_WAIT_TIME2__DEQ_RETRY_MASK 0xff000000
2476#define CP_IQ_WAIT_TIME2__DEQ_RETRY__SHIFT 0x18
2477#define CP_VMID_RESET__RESET_REQUEST_MASK 0xffff
2478#define CP_VMID_RESET__RESET_REQUEST__SHIFT 0x0
2479#define CP_VMID_RESET__RESET_STATUS_MASK 0xffff0000
2480#define CP_VMID_RESET__RESET_STATUS__SHIFT 0x10
2481#define CP_VMID_PREEMPT__PREEMPT_REQUEST_MASK 0xffff
2482#define CP_VMID_PREEMPT__PREEMPT_REQUEST__SHIFT 0x0
2483#define CP_VMID_PREEMPT__VIRT_COMMAND_MASK 0xf0000
2484#define CP_VMID_PREEMPT__VIRT_COMMAND__SHIFT 0x10
2485#define CP_VMID_STATUS__PREEMPT_DE_STATUS_MASK 0xffff
2486#define CP_VMID_STATUS__PREEMPT_DE_STATUS__SHIFT 0x0
2487#define CP_VMID_STATUS__PREEMPT_CE_STATUS_MASK 0xffff0000
2488#define CP_VMID_STATUS__PREEMPT_CE_STATUS__SHIFT 0x10
2489#define CPC_INT_CNTX_ID__CNTX_ID_MASK 0xfffffff
2490#define CPC_INT_CNTX_ID__CNTX_ID__SHIFT 0x0
2491#define CPC_INT_CNTX_ID__QUEUE_ID_MASK 0x70000000
2492#define CPC_INT_CNTX_ID__QUEUE_ID__SHIFT 0x1c
2493#define CP_PQ_STATUS__DOORBELL_UPDATED_MASK 0x1
2494#define CP_PQ_STATUS__DOORBELL_UPDATED__SHIFT 0x0
2495#define CP_PQ_STATUS__DOORBELL_ENABLE_MASK 0x2
2496#define CP_PQ_STATUS__DOORBELL_ENABLE__SHIFT 0x1
2497#define CP_CPC_IC_BASE_LO__IC_BASE_LO_MASK 0xfffff000
2498#define CP_CPC_IC_BASE_LO__IC_BASE_LO__SHIFT 0xc
2499#define CP_CPC_IC_BASE_HI__IC_BASE_HI_MASK 0xffff
2500#define CP_CPC_IC_BASE_HI__IC_BASE_HI__SHIFT 0x0
2501#define CP_CPC_IC_BASE_CNTL__VMID_MASK 0xf
2502#define CP_CPC_IC_BASE_CNTL__VMID__SHIFT 0x0
2503#define CP_CPC_IC_BASE_CNTL__ATC_MASK 0x800000
2504#define CP_CPC_IC_BASE_CNTL__ATC__SHIFT 0x17
2505#define CP_CPC_IC_BASE_CNTL__CACHE_POLICY_MASK 0x1000000
2506#define CP_CPC_IC_BASE_CNTL__CACHE_POLICY__SHIFT 0x18
2507#define CP_CPC_IC_BASE_CNTL__MTYPE_MASK 0x18000000
2508#define CP_CPC_IC_BASE_CNTL__MTYPE__SHIFT 0x1b
2509#define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE_MASK 0x1
2510#define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT 0x0
2511#define CP_CPC_IC_OP_CNTL__PRIME_ICACHE_MASK 0x10
2512#define CP_CPC_IC_OP_CNTL__PRIME_ICACHE__SHIFT 0x4
2513#define CP_CPC_IC_OP_CNTL__ICACHE_PRIMED_MASK 0x20
2514#define CP_CPC_IC_OP_CNTL__ICACHE_PRIMED__SHIFT 0x5
2515#define CP_CPC_STATUS__MEC1_BUSY_MASK 0x1
2516#define CP_CPC_STATUS__MEC1_BUSY__SHIFT 0x0
2517#define CP_CPC_STATUS__MEC2_BUSY_MASK 0x2
2518#define CP_CPC_STATUS__MEC2_BUSY__SHIFT 0x1
2519#define CP_CPC_STATUS__DC0_BUSY_MASK 0x4
2520#define CP_CPC_STATUS__DC0_BUSY__SHIFT 0x2
2521#define CP_CPC_STATUS__DC1_BUSY_MASK 0x8
2522#define CP_CPC_STATUS__DC1_BUSY__SHIFT 0x3
2523#define CP_CPC_STATUS__RCIU1_BUSY_MASK 0x10
2524#define CP_CPC_STATUS__RCIU1_BUSY__SHIFT 0x4
2525#define CP_CPC_STATUS__RCIU2_BUSY_MASK 0x20
2526#define CP_CPC_STATUS__RCIU2_BUSY__SHIFT 0x5
2527#define CP_CPC_STATUS__ROQ1_BUSY_MASK 0x40
2528#define CP_CPC_STATUS__ROQ1_BUSY__SHIFT 0x6
2529#define CP_CPC_STATUS__ROQ2_BUSY_MASK 0x80
2530#define CP_CPC_STATUS__ROQ2_BUSY__SHIFT 0x7
2531#define CP_CPC_STATUS__TCIU_BUSY_MASK 0x400
2532#define CP_CPC_STATUS__TCIU_BUSY__SHIFT 0xa
2533#define CP_CPC_STATUS__SCRATCH_RAM_BUSY_MASK 0x800
2534#define CP_CPC_STATUS__SCRATCH_RAM_BUSY__SHIFT 0xb
2535#define CP_CPC_STATUS__QU_BUSY_MASK 0x1000
2536#define CP_CPC_STATUS__QU_BUSY__SHIFT 0xc
2537#define CP_CPC_STATUS__ATCL2IU_BUSY_MASK 0x2000
2538#define CP_CPC_STATUS__ATCL2IU_BUSY__SHIFT 0xd
2539#define CP_CPC_STATUS__CPG_CPC_BUSY_MASK 0x20000000
2540#define CP_CPC_STATUS__CPG_CPC_BUSY__SHIFT 0x1d
2541#define CP_CPC_STATUS__CPF_CPC_BUSY_MASK 0x40000000
2542#define CP_CPC_STATUS__CPF_CPC_BUSY__SHIFT 0x1e
2543#define CP_CPC_STATUS__CPC_BUSY_MASK 0x80000000
2544#define CP_CPC_STATUS__CPC_BUSY__SHIFT 0x1f
2545#define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY_MASK 0x1
2546#define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY__SHIFT 0x0
2547#define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY_MASK 0x2
2548#define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY__SHIFT 0x1
2549#define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY_MASK 0x4
2550#define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY__SHIFT 0x2
2551#define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY_MASK 0x8
2552#define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY__SHIFT 0x3
2553#define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY_MASK 0x10
2554#define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY__SHIFT 0x4
2555#define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY_MASK 0x20
2556#define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY__SHIFT 0x5
2557#define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY_MASK 0x40
2558#define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY__SHIFT 0x6
2559#define CP_CPC_BUSY_STAT__MEC1_TC_BUSY_MASK 0x80
2560#define CP_CPC_BUSY_STAT__MEC1_TC_BUSY__SHIFT 0x7
2561#define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY_MASK 0x100
2562#define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY__SHIFT 0x8
2563#define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY_MASK 0x200
2564#define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY__SHIFT 0x9
2565#define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY_MASK 0x400
2566#define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY__SHIFT 0xa
2567#define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY_MASK 0x800
2568#define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY__SHIFT 0xb
2569#define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY_MASK 0x1000
2570#define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY__SHIFT 0xc
2571#define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY_MASK 0x2000
2572#define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY__SHIFT 0xd
2573#define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY_MASK 0x10000
2574#define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY__SHIFT 0x10
2575#define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY_MASK 0x20000
2576#define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY__SHIFT 0x11
2577#define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY_MASK 0x40000
2578#define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY__SHIFT 0x12
2579#define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY_MASK 0x80000
2580#define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY__SHIFT 0x13
2581#define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY_MASK 0x100000
2582#define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY__SHIFT 0x14
2583#define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY_MASK 0x200000
2584#define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY__SHIFT 0x15
2585#define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY_MASK 0x400000
2586#define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY__SHIFT 0x16
2587#define CP_CPC_BUSY_STAT__MEC2_TC_BUSY_MASK 0x800000
2588#define CP_CPC_BUSY_STAT__MEC2_TC_BUSY__SHIFT 0x17
2589#define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY_MASK 0x1000000
2590#define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY__SHIFT 0x18
2591#define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY_MASK 0x2000000
2592#define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY__SHIFT 0x19
2593#define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY_MASK 0x4000000
2594#define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY__SHIFT 0x1a
2595#define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY_MASK 0x8000000
2596#define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY__SHIFT 0x1b
2597#define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY_MASK 0x10000000
2598#define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY__SHIFT 0x1c
2599#define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY_MASK 0x20000000
2600#define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY__SHIFT 0x1d
2601#define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL_MASK 0x8
2602#define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL__SHIFT 0x3
2603#define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION_MASK 0x10
2604#define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION__SHIFT 0x4
2605#define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL_MASK 0x40
2606#define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL__SHIFT 0x6
2607#define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET_MASK 0x100
2608#define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET__SHIFT 0x8
2609#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_MASK 0x200
2610#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU__SHIFT 0x9
2611#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ_MASK 0x400
2612#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ__SHIFT 0xa
2613#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA_MASK 0x2000
2614#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA__SHIFT 0xd
2615#define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET_MASK 0x10000
2616#define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET__SHIFT 0x10
2617#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_MASK 0x20000
2618#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU__SHIFT 0x11
2619#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ_MASK 0x40000
2620#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ__SHIFT 0x12
2621#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA_MASK 0x200000
2622#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA__SHIFT 0x15
2623#define CP_CPC_STALLED_STAT1__ATCL2IU_WAITING_ON_FREE_MASK 0x400000
2624#define CP_CPC_STALLED_STAT1__ATCL2IU_WAITING_ON_FREE__SHIFT 0x16
2625#define CP_CPC_STALLED_STAT1__ATCL2IU_WAITING_ON_TAGS_MASK 0x800000
2626#define CP_CPC_STALLED_STAT1__ATCL2IU_WAITING_ON_TAGS__SHIFT 0x17
2627#define CP_CPC_STALLED_STAT1__ATCL1_WAITING_ON_TRANS_MASK 0x1000000
2628#define CP_CPC_STALLED_STAT1__ATCL1_WAITING_ON_TRANS__SHIFT 0x18
2629#define CP_CPF_STATUS__POST_WPTR_GFX_BUSY_MASK 0x1
2630#define CP_CPF_STATUS__POST_WPTR_GFX_BUSY__SHIFT 0x0
2631#define CP_CPF_STATUS__CSF_BUSY_MASK 0x2
2632#define CP_CPF_STATUS__CSF_BUSY__SHIFT 0x1
2633#define CP_CPF_STATUS__ROQ_ALIGN_BUSY_MASK 0x10
2634#define CP_CPF_STATUS__ROQ_ALIGN_BUSY__SHIFT 0x4
2635#define CP_CPF_STATUS__ROQ_RING_BUSY_MASK 0x20
2636#define CP_CPF_STATUS__ROQ_RING_BUSY__SHIFT 0x5
2637#define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY_MASK 0x40
2638#define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY__SHIFT 0x6
2639#define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY_MASK 0x80
2640#define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY__SHIFT 0x7
2641#define CP_CPF_STATUS__ROQ_STATE_BUSY_MASK 0x100
2642#define CP_CPF_STATUS__ROQ_STATE_BUSY__SHIFT 0x8
2643#define CP_CPF_STATUS__ROQ_CE_RING_BUSY_MASK 0x200
2644#define CP_CPF_STATUS__ROQ_CE_RING_BUSY__SHIFT 0x9
2645#define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY_MASK 0x400
2646#define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY__SHIFT 0xa
2647#define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY_MASK 0x800
2648#define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY__SHIFT 0xb
2649#define CP_CPF_STATUS__SEMAPHORE_BUSY_MASK 0x1000
2650#define CP_CPF_STATUS__SEMAPHORE_BUSY__SHIFT 0xc
2651#define CP_CPF_STATUS__INTERRUPT_BUSY_MASK 0x2000
2652#define CP_CPF_STATUS__INTERRUPT_BUSY__SHIFT 0xd
2653#define CP_CPF_STATUS__TCIU_BUSY_MASK 0x4000
2654#define CP_CPF_STATUS__TCIU_BUSY__SHIFT 0xe
2655#define CP_CPF_STATUS__HQD_BUSY_MASK 0x8000
2656#define CP_CPF_STATUS__HQD_BUSY__SHIFT 0xf
2657#define CP_CPF_STATUS__PRT_BUSY_MASK 0x10000
2658#define CP_CPF_STATUS__PRT_BUSY__SHIFT 0x10
2659#define CP_CPF_STATUS__ATCL2IU_BUSY_MASK 0x20000
2660#define CP_CPF_STATUS__ATCL2IU_BUSY__SHIFT 0x11
2661#define CP_CPF_STATUS__CPF_GFX_BUSY_MASK 0x4000000
2662#define CP_CPF_STATUS__CPF_GFX_BUSY__SHIFT 0x1a
2663#define CP_CPF_STATUS__CPF_CMP_BUSY_MASK 0x8000000
2664#define CP_CPF_STATUS__CPF_CMP_BUSY__SHIFT 0x1b
2665#define CP_CPF_STATUS__GRBM_CPF_STAT_BUSY_MASK 0x30000000
2666#define CP_CPF_STATUS__GRBM_CPF_STAT_BUSY__SHIFT 0x1c
2667#define CP_CPF_STATUS__CPC_CPF_BUSY_MASK 0x40000000
2668#define CP_CPF_STATUS__CPC_CPF_BUSY__SHIFT 0x1e
2669#define CP_CPF_STATUS__CPF_BUSY_MASK 0x80000000
2670#define CP_CPF_STATUS__CPF_BUSY__SHIFT 0x1f
2671#define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x1
2672#define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x0
2673#define CP_CPF_BUSY_STAT__CSF_RING_BUSY_MASK 0x2
2674#define CP_CPF_BUSY_STAT__CSF_RING_BUSY__SHIFT 0x1
2675#define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY_MASK 0x4
2676#define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY__SHIFT 0x2
2677#define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY_MASK 0x8
2678#define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY__SHIFT 0x3
2679#define CP_CPF_BUSY_STAT__CSF_STATE_BUSY_MASK 0x10
2680#define CP_CPF_BUSY_STAT__CSF_STATE_BUSY__SHIFT 0x4
2681#define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY_MASK 0x20
2682#define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY__SHIFT 0x5
2683#define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY_MASK 0x40
2684#define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY__SHIFT 0x6
2685#define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY_MASK 0x80
2686#define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY__SHIFT 0x7
2687#define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY_MASK 0x100
2688#define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY__SHIFT 0x8
2689#define CP_CPF_BUSY_STAT__OUTSTANDING_READ_TAGS_MASK 0x200
2690#define CP_CPF_BUSY_STAT__OUTSTANDING_READ_TAGS__SHIFT 0x9
2691#define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY_MASK 0x800
2692#define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY__SHIFT 0xb
2693#define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY_MASK 0x1000
2694#define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY__SHIFT 0xc
2695#define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY_MASK 0x2000
2696#define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY__SHIFT 0xd
2697#define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY_MASK 0x4000
2698#define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY__SHIFT 0xe
2699#define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY_MASK 0x8000
2700#define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY__SHIFT 0xf
2701#define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY_MASK 0x10000
2702#define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY__SHIFT 0x10
2703#define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY_MASK 0x20000
2704#define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY__SHIFT 0x11
2705#define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY_MASK 0x40000
2706#define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY__SHIFT 0x12
2707#define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY_MASK 0x80000
2708#define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY__SHIFT 0x13
2709#define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY_MASK 0x100000
2710#define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY__SHIFT 0x14
2711#define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY_MASK 0x200000
2712#define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY__SHIFT 0x15
2713#define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY_MASK 0x400000
2714#define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY__SHIFT 0x16
2715#define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY_MASK 0x800000
2716#define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY__SHIFT 0x17
2717#define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY_MASK 0x1000000
2718#define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY__SHIFT 0x18
2719#define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY_MASK 0x2000000
2720#define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY__SHIFT 0x19
2721#define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY_MASK 0x4000000
2722#define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY__SHIFT 0x1a
2723#define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY_MASK 0x8000000
2724#define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY__SHIFT 0x1b
2725#define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY_MASK 0x10000000
2726#define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY__SHIFT 0x1c
2727#define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY_MASK 0x20000000
2728#define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY__SHIFT 0x1d
2729#define CP_CPF_BUSY_STAT__HQD_PQ_BUSY_MASK 0x40000000
2730#define CP_CPF_BUSY_STAT__HQD_PQ_BUSY__SHIFT 0x1e
2731#define CP_CPF_BUSY_STAT__HQD_IB_BUSY_MASK 0x80000000
2732#define CP_CPF_BUSY_STAT__HQD_IB_BUSY__SHIFT 0x1f
2733#define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA_MASK 0x1
2734#define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA__SHIFT 0x0
2735#define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA_MASK 0x2
2736#define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA__SHIFT 0x1
2737#define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA_MASK 0x4
2738#define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA__SHIFT 0x2
2739#define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA_MASK 0x8
2740#define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA__SHIFT 0x3
2741#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE_MASK 0x20
2742#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE__SHIFT 0x5
2743#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS_MASK 0x40
2744#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS__SHIFT 0x6
2745#define CP_CPF_STALLED_STAT1__ATCL2IU_WAITING_ON_FREE_MASK 0x80
2746#define CP_CPF_STALLED_STAT1__ATCL2IU_WAITING_ON_FREE__SHIFT 0x7
2747#define CP_CPF_STALLED_STAT1__ATCL2IU_WAITING_ON_TAGS_MASK 0x100
2748#define CP_CPF_STALLED_STAT1__ATCL2IU_WAITING_ON_TAGS__SHIFT 0x8
2749#define CP_CPF_STALLED_STAT1__ATCL1_WAITING_ON_TRANS_MASK 0x200
2750#define CP_CPF_STALLED_STAT1__ATCL1_WAITING_ON_TRANS__SHIFT 0x9
2751#define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x3f
2752#define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0
2753#define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE_MASK 0x10
2754#define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE__SHIFT 0x4
2755#define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET_MASK 0x10000
2756#define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET__SHIFT 0x10
2757#define CP_MEC_CNTL__MEC_ME1_PIPE1_RESET_MASK 0x20000
2758#define CP_MEC_CNTL__MEC_ME1_PIPE1_RESET__SHIFT 0x11
2759#define CP_MEC_CNTL__MEC_ME1_PIPE2_RESET_MASK 0x40000
2760#define CP_MEC_CNTL__MEC_ME1_PIPE2_RESET__SHIFT 0x12
2761#define CP_MEC_CNTL__MEC_ME1_PIPE3_RESET_MASK 0x80000
2762#define CP_MEC_CNTL__MEC_ME1_PIPE3_RESET__SHIFT 0x13
2763#define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET_MASK 0x100000
2764#define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET__SHIFT 0x14
2765#define CP_MEC_CNTL__MEC_ME2_PIPE1_RESET_MASK 0x200000
2766#define CP_MEC_CNTL__MEC_ME2_PIPE1_RESET__SHIFT 0x15
2767#define CP_MEC_CNTL__MEC_ME2_HALT_MASK 0x10000000
2768#define CP_MEC_CNTL__MEC_ME2_HALT__SHIFT 0x1c
2769#define CP_MEC_CNTL__MEC_ME2_STEP_MASK 0x20000000
2770#define CP_MEC_CNTL__MEC_ME2_STEP__SHIFT 0x1d
2771#define CP_MEC_CNTL__MEC_ME1_HALT_MASK 0x40000000
2772#define CP_MEC_CNTL__MEC_ME1_HALT__SHIFT 0x1e
2773#define CP_MEC_CNTL__MEC_ME1_STEP_MASK 0x80000000
2774#define CP_MEC_CNTL__MEC_ME1_STEP__SHIFT 0x1f
2775#define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP_MASK 0xffffffff
2776#define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP__SHIFT 0x0
2777#define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP_MASK 0xffffffff
2778#define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP__SHIFT 0x0
2779#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0x1ff
2780#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0
2781#define CP_CPC_SCRATCH_DATA__SCRATCH_DATA_MASK 0xffffffff
2782#define CP_CPC_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0
2783#define CPG_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f
2784#define CPG_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
2785#define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
2786#define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
2787#define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
2788#define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
2789#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3f
2790#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
2791#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xfc00
2792#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
2793#define CPG_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f
2794#define CPG_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
2795#define CPG_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xfc00
2796#define CPG_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
2797#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
2798#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
2799#define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
2800#define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
2801#define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
2802#define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
2803#define CPC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f
2804#define CPC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
2805#define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
2806#define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
2807#define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
2808#define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
2809#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3f
2810#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
2811#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xfc00
2812#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
2813#define CPC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f
2814#define CPC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
2815#define CPC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xfc00
2816#define CPC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
2817#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
2818#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
2819#define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
2820#define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
2821#define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
2822#define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
2823#define CPF_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f
2824#define CPF_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
2825#define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
2826#define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
2827#define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
2828#define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
2829#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3f
2830#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
2831#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xfc00
2832#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
2833#define CPF_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f
2834#define CPF_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
2835#define CPF_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xfc00
2836#define CPF_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
2837#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
2838#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
2839#define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
2840#define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
2841#define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
2842#define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
2843#define CP_CPC_HALT_HYST_COUNT__COUNT_MASK 0xf
2844#define CP_CPC_HALT_HYST_COUNT__COUNT__SHIFT 0x0
2845#define CP_DRAW_OBJECT__OBJECT_MASK 0xffffffff
2846#define CP_DRAW_OBJECT__OBJECT__SHIFT 0x0
2847#define CP_DRAW_OBJECT_COUNTER__COUNT_MASK 0xffff
2848#define CP_DRAW_OBJECT_COUNTER__COUNT__SHIFT 0x0
2849#define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI_MASK 0xffffffff
2850#define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI__SHIFT 0x0
2851#define CP_DRAW_WINDOW_HI__WINDOW_HI_MASK 0xffffffff
2852#define CP_DRAW_WINDOW_HI__WINDOW_HI__SHIFT 0x0
2853#define CP_DRAW_WINDOW_LO__MIN_MASK 0xffff
2854#define CP_DRAW_WINDOW_LO__MIN__SHIFT 0x0
2855#define CP_DRAW_WINDOW_LO__MAX_MASK 0xffff0000
2856#define CP_DRAW_WINDOW_LO__MAX__SHIFT 0x10
2857#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX_MASK 0x1
2858#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX__SHIFT 0x0
2859#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN_MASK 0x2
2860#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN__SHIFT 0x1
2861#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI_MASK 0x4
2862#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI__SHIFT 0x2
2863#define CP_DRAW_WINDOW_CNTL__MODE_MASK 0x100
2864#define CP_DRAW_WINDOW_CNTL__MODE__SHIFT 0x8
2865#define CP_PRT_LOD_STATS_CNTL0__BU_SIZE_MASK 0xffffffff
2866#define CP_PRT_LOD_STATS_CNTL0__BU_SIZE__SHIFT 0x0
2867#define CP_PRT_LOD_STATS_CNTL1__BASE_LO_MASK 0xffffffff
2868#define CP_PRT_LOD_STATS_CNTL1__BASE_LO__SHIFT 0x0
2869#define CP_PRT_LOD_STATS_CNTL2__BASE_HI_MASK 0x3
2870#define CP_PRT_LOD_STATS_CNTL2__BASE_HI__SHIFT 0x0
2871#define CP_PRT_LOD_STATS_CNTL2__INTERVAL_MASK 0x3fc
2872#define CP_PRT_LOD_STATS_CNTL2__INTERVAL__SHIFT 0x2
2873#define CP_PRT_LOD_STATS_CNTL2__RESET_CNT_MASK 0x3fc00
2874#define CP_PRT_LOD_STATS_CNTL2__RESET_CNT__SHIFT 0xa
2875#define CP_PRT_LOD_STATS_CNTL2__RESET_FORCE_MASK 0x40000
2876#define CP_PRT_LOD_STATS_CNTL2__RESET_FORCE__SHIFT 0x12
2877#define CP_PRT_LOD_STATS_CNTL2__REPORT_AND_RESET_MASK 0x80000
2878#define CP_PRT_LOD_STATS_CNTL2__REPORT_AND_RESET__SHIFT 0x13
2879#define CP_PRT_LOD_STATS_CNTL2__MC_VMID_MASK 0x7800000
2880#define CP_PRT_LOD_STATS_CNTL2__MC_VMID__SHIFT 0x17
2881#define CP_PRT_LOD_STATS_CNTL2__CACHE_POLICY_MASK 0x10000000
2882#define CP_PRT_LOD_STATS_CNTL2__CACHE_POLICY__SHIFT 0x1c
2883#define CP_PRT_LOD_STATS_CNTL2__MTYPE_MASK 0xc0000000
2884#define CP_PRT_LOD_STATS_CNTL2__MTYPE__SHIFT 0x1e
2885#define CP_CE_COMPARE_COUNT__COMPARE_COUNT_MASK 0xffffffff
2886#define CP_CE_COMPARE_COUNT__COMPARE_COUNT__SHIFT 0x0
2887#define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT_MASK 0xffffffff
2888#define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT 0x0
2889#define CP_DE_CE_COUNT__CONST_ENGINE_COUNT_MASK 0xffffffff
2890#define CP_DE_CE_COUNT__CONST_ENGINE_COUNT__SHIFT 0x0
2891#define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT_MASK 0xffffffff
2892#define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT__SHIFT 0x0
2893#define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT_MASK 0xffffffff
2894#define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT 0x0
2895#define CP_EOP_DONE_EVENT_CNTL__WBINV_TC_OP_MASK 0x7f
2896#define CP_EOP_DONE_EVENT_CNTL__WBINV_TC_OP__SHIFT 0x0
2897#define CP_EOP_DONE_EVENT_CNTL__WBINV_ACTION_ENA_MASK 0x3f000
2898#define CP_EOP_DONE_EVENT_CNTL__WBINV_ACTION_ENA__SHIFT 0xc
2899#define CP_EOP_DONE_EVENT_CNTL__CACHE_CONTROL_MASK 0x2000000
2900#define CP_EOP_DONE_EVENT_CNTL__CACHE_CONTROL__SHIFT 0x19
2901#define CP_EOP_DONE_EVENT_CNTL__MTYPE_MASK 0x18000000
2902#define CP_EOP_DONE_EVENT_CNTL__MTYPE__SHIFT 0x1b
2903#define CP_EOP_DONE_DATA_CNTL__CNTX_ID_MASK 0xffff
2904#define CP_EOP_DONE_DATA_CNTL__CNTX_ID__SHIFT 0x0
2905#define CP_EOP_DONE_DATA_CNTL__DST_SEL_MASK 0x30000
2906#define CP_EOP_DONE_DATA_CNTL__DST_SEL__SHIFT 0x10
2907#define CP_EOP_DONE_DATA_CNTL__INT_SEL_MASK 0x7000000
2908#define CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT 0x18
2909#define CP_EOP_DONE_DATA_CNTL__DATA_SEL_MASK 0xe0000000
2910#define CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT 0x1d
2911#define CP_EOP_DONE_CNTX_ID__CNTX_ID_MASK 0xfffffff
2912#define CP_EOP_DONE_CNTX_ID__CNTX_ID__SHIFT 0x0
2913#define CP_EOP_DONE_ADDR_LO__ADDR_LO_MASK 0xfffffffc
2914#define CP_EOP_DONE_ADDR_LO__ADDR_LO__SHIFT 0x2
2915#define CP_EOP_DONE_ADDR_HI__ADDR_HI_MASK 0xffff
2916#define CP_EOP_DONE_ADDR_HI__ADDR_HI__SHIFT 0x0
2917#define CP_EOP_DONE_DATA_LO__DATA_LO_MASK 0xffffffff
2918#define CP_EOP_DONE_DATA_LO__DATA_LO__SHIFT 0x0
2919#define CP_EOP_DONE_DATA_HI__DATA_HI_MASK 0xffffffff
2920#define CP_EOP_DONE_DATA_HI__DATA_HI__SHIFT 0x0
2921#define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO_MASK 0xffffffff
2922#define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO__SHIFT 0x0
2923#define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI_MASK 0xffffffff
2924#define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI__SHIFT 0x0
2925#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO_MASK 0xfffffffc
2926#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO__SHIFT 0x2
2927#define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI_MASK 0xffff
2928#define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI__SHIFT 0x0
2929#define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO_MASK 0xffffffff
2930#define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO__SHIFT 0x0
2931#define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI_MASK 0xffffffff
2932#define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI__SHIFT 0x0
2933#define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO_MASK 0xffffffff
2934#define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO__SHIFT 0x0
2935#define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI_MASK 0xffffffff
2936#define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI__SHIFT 0x0
2937#define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO_MASK 0xffffffff
2938#define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO__SHIFT 0x0
2939#define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI_MASK 0xffffffff
2940#define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI__SHIFT 0x0
2941#define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO_MASK 0xffffffff
2942#define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO__SHIFT 0x0
2943#define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI_MASK 0xffffffff
2944#define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI__SHIFT 0x0
2945#define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO_MASK 0xffffffff
2946#define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO__SHIFT 0x0
2947#define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI_MASK 0xffffffff
2948#define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI__SHIFT 0x0
2949#define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO_MASK 0xffffffff
2950#define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO__SHIFT 0x0
2951#define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI_MASK 0xffffffff
2952#define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI__SHIFT 0x0
2953#define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO_MASK 0xffffffff
2954#define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO__SHIFT 0x0
2955#define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI_MASK 0xffffffff
2956#define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI__SHIFT 0x0
2957#define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO_MASK 0xffffffff
2958#define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO__SHIFT 0x0
2959#define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI_MASK 0xffffffff
2960#define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI__SHIFT 0x0
2961#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO_MASK 0xfffffffc
2962#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO__SHIFT 0x2
2963#define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI_MASK 0xffff
2964#define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI__SHIFT 0x0
2965#define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO_MASK 0xffffffff
2966#define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO__SHIFT 0x0
2967#define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI_MASK 0xffffffff
2968#define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI__SHIFT 0x0
2969#define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO_MASK 0xffffffff
2970#define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO__SHIFT 0x0
2971#define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI_MASK 0xffffffff
2972#define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI__SHIFT 0x0
2973#define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO_MASK 0xffffffff
2974#define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO__SHIFT 0x0
2975#define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI_MASK 0xffffffff
2976#define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI__SHIFT 0x0
2977#define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO_MASK 0xffffffff
2978#define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO__SHIFT 0x0
2979#define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI_MASK 0xffffffff
2980#define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI__SHIFT 0x0
2981#define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO_MASK 0xffffffff
2982#define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO__SHIFT 0x0
2983#define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI_MASK 0xffffffff
2984#define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI__SHIFT 0x0
2985#define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO_MASK 0xffffffff
2986#define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO__SHIFT 0x0
2987#define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI_MASK 0xffffffff
2988#define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI__SHIFT 0x0
2989#define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO_MASK 0xffffffff
2990#define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO__SHIFT 0x0
2991#define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI_MASK 0xffffffff
2992#define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI__SHIFT 0x0
2993#define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO_MASK 0xffffffff
2994#define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO__SHIFT 0x0
2995#define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI_MASK 0xffffffff
2996#define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI__SHIFT 0x0
2997#define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO_MASK 0xffffffff
2998#define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO__SHIFT 0x0
2999#define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI_MASK 0xffffffff
3000#define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI__SHIFT 0x0
3001#define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO_MASK 0xffffffff
3002#define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO__SHIFT 0x0
3003#define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI_MASK 0xffffffff
3004#define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI__SHIFT 0x0
3005#define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE_MASK 0xffffffff
3006#define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE__SHIFT 0x0
3007#define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE_MASK 0xffffffff
3008#define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE__SHIFT 0x0
3009#define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO_MASK 0xffffffff
3010#define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO__SHIFT 0x0
3011#define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI_MASK 0xffffffff
3012#define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI__SHIFT 0x0
3013#define CP_PIPE_STATS_CONTROL__CACHE_CONTROL_MASK 0x2000000
3014#define CP_PIPE_STATS_CONTROL__CACHE_CONTROL__SHIFT 0x19
3015#define CP_PIPE_STATS_CONTROL__MTYPE_MASK 0x18000000
3016#define CP_PIPE_STATS_CONTROL__MTYPE__SHIFT 0x1b
3017#define CP_STREAM_OUT_CONTROL__CACHE_CONTROL_MASK 0x2000000
3018#define CP_STREAM_OUT_CONTROL__CACHE_CONTROL__SHIFT 0x19
3019#define CP_STREAM_OUT_CONTROL__MTYPE_MASK 0x18000000
3020#define CP_STREAM_OUT_CONTROL__MTYPE__SHIFT 0x1b
3021#define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE_MASK 0x1
3022#define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE__SHIFT 0x0
3023#define SCRATCH_REG0__SCRATCH_REG0_MASK 0xffffffff
3024#define SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x0
3025#define SCRATCH_REG1__SCRATCH_REG1_MASK 0xffffffff
3026#define SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x0
3027#define SCRATCH_REG2__SCRATCH_REG2_MASK 0xffffffff
3028#define SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x0
3029#define SCRATCH_REG3__SCRATCH_REG3_MASK 0xffffffff
3030#define SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x0
3031#define SCRATCH_REG4__SCRATCH_REG4_MASK 0xffffffff
3032#define SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x0
3033#define SCRATCH_REG5__SCRATCH_REG5_MASK 0xffffffff
3034#define SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x0
3035#define SCRATCH_REG6__SCRATCH_REG6_MASK 0xffffffff
3036#define SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x0
3037#define SCRATCH_REG7__SCRATCH_REG7_MASK 0xffffffff
3038#define SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x0
3039#define SCRATCH_UMSK__OBSOLETE_UMSK_MASK 0xff
3040#define SCRATCH_UMSK__OBSOLETE_UMSK__SHIFT 0x0
3041#define SCRATCH_UMSK__OBSOLETE_SWAP_MASK 0x30000
3042#define SCRATCH_UMSK__OBSOLETE_SWAP__SHIFT 0x10
3043#define SCRATCH_ADDR__OBSOLETE_ADDR_MASK 0xffffffff
3044#define SCRATCH_ADDR__OBSOLETE_ADDR__SHIFT 0x0
3045#define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xffffffff
3046#define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0
3047#define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xffffffff
3048#define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0
3049#define CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xffffffff
3050#define CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0
3051#define CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xffffffff
3052#define CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0
3053#define CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xffffffff
3054#define CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0
3055#define CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xffffffff
3056#define CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0
3057#define CP_APPEND_ADDR_LO__MEM_ADDR_LO_MASK 0xfffffffc
3058#define CP_APPEND_ADDR_LO__MEM_ADDR_LO__SHIFT 0x2
3059#define CP_APPEND_ADDR_HI__MEM_ADDR_HI_MASK 0xffff
3060#define CP_APPEND_ADDR_HI__MEM_ADDR_HI__SHIFT 0x0
3061#define CP_APPEND_ADDR_HI__CS_PS_SEL_MASK 0x10000
3062#define CP_APPEND_ADDR_HI__CS_PS_SEL__SHIFT 0x10
3063#define CP_APPEND_ADDR_HI__CACHE_POLICY_MASK 0x2000000
3064#define CP_APPEND_ADDR_HI__CACHE_POLICY__SHIFT 0x19
3065#define CP_APPEND_ADDR_HI__MTYPE_MASK 0x18000000
3066#define CP_APPEND_ADDR_HI__MTYPE__SHIFT 0x1b
3067#define CP_APPEND_ADDR_HI__COMMAND_MASK 0xe0000000
3068#define CP_APPEND_ADDR_HI__COMMAND__SHIFT 0x1d
3069#define CP_APPEND_DATA__DATA_MASK 0xffffffff
3070#define CP_APPEND_DATA__DATA__SHIFT 0x0
3071#define CP_APPEND_LAST_CS_FENCE__LAST_FENCE_MASK 0xffffffff
3072#define CP_APPEND_LAST_CS_FENCE__LAST_FENCE__SHIFT 0x0
3073#define CP_APPEND_LAST_PS_FENCE__LAST_FENCE_MASK 0xffffffff
3074#define CP_APPEND_LAST_PS_FENCE__LAST_FENCE__SHIFT 0x0
3075#define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xffffffff
3076#define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0
3077#define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xffffffff
3078#define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0
3079#define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xffffffff
3080#define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0
3081#define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xffffffff
3082#define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0
3083#define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xffffffff
3084#define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0
3085#define CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xffffffff
3086#define CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0
3087#define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xffffffff
3088#define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0
3089#define CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xffffffff
3090#define CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0
3091#define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xffffffff
3092#define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0
3093#define CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xffffffff
3094#define CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0
3095#define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xffffffff
3096#define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0
3097#define CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xffffffff
3098#define CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0
3099#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_SWAP_MASK 0x3
3100#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_SWAP__SHIFT 0x0
3101#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO_MASK 0xfffffffc
3102#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO__SHIFT 0x2
3103#define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI_MASK 0xffff
3104#define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI__SHIFT 0x0
3105#define CP_ME_MC_WADDR_HI__MTYPE_MASK 0x300000
3106#define CP_ME_MC_WADDR_HI__MTYPE__SHIFT 0x14
3107#define CP_ME_MC_WADDR_HI__CACHE_POLICY_MASK 0x400000
3108#define CP_ME_MC_WADDR_HI__CACHE_POLICY__SHIFT 0x16
3109#define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO_MASK 0xffffffff
3110#define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO__SHIFT 0x0
3111#define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI_MASK 0xffffffff
3112#define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI__SHIFT 0x0
3113#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_SWAP_MASK 0x3
3114#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_SWAP__SHIFT 0x0
3115#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO_MASK 0xfffffffc
3116#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO__SHIFT 0x2
3117#define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI_MASK 0xffff
3118#define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI__SHIFT 0x0
3119#define CP_ME_MC_RADDR_HI__MTYPE_MASK 0x300000
3120#define CP_ME_MC_RADDR_HI__MTYPE__SHIFT 0x14
3121#define CP_ME_MC_RADDR_HI__CACHE_POLICY_MASK 0x400000
3122#define CP_ME_MC_RADDR_HI__CACHE_POLICY__SHIFT 0x16
3123#define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER_MASK 0xffffffff
3124#define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER__SHIFT 0x0
3125#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK 0x3
3126#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT 0x0
3127#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO_MASK 0xfffffff8
3128#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT 0x3
3129#define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI_MASK 0xffff
3130#define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT 0x0
3131#define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK 0x10000
3132#define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x10
3133#define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK 0x100000
3134#define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x14
3135#define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x3000000
3136#define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x18
3137#define CP_SIG_SEM_ADDR_HI__SEM_SELECT_MASK 0xe0000000
3138#define CP_SIG_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x1d
3139#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK 0x3
3140#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT 0x0
3141#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO_MASK 0xfffffff8
3142#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT 0x3
3143#define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI_MASK 0xffff
3144#define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT 0x0
3145#define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK 0x10000
3146#define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x10
3147#define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK 0x100000
3148#define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x14
3149#define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x3000000
3150#define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x18
3151#define CP_WAIT_SEM_ADDR_HI__SEM_SELECT_MASK 0xe0000000
3152#define CP_WAIT_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x1d
3153#define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT_MASK 0xffffffff
3154#define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT__SHIFT 0x0
3155#define CP_COHER_START_DELAY__START_DELAY_COUNT_MASK 0x3f
3156#define CP_COHER_START_DELAY__START_DELAY_COUNT__SHIFT 0x0
3157#define CP_COHER_CNTL__DEST_BASE_0_ENA_MASK 0x1
3158#define CP_COHER_CNTL__DEST_BASE_0_ENA__SHIFT 0x0
3159#define CP_COHER_CNTL__DEST_BASE_1_ENA_MASK 0x2
3160#define CP_COHER_CNTL__DEST_BASE_1_ENA__SHIFT 0x1
3161#define CP_COHER_CNTL__TC_SD_ACTION_ENA_MASK 0x4
3162#define CP_COHER_CNTL__TC_SD_ACTION_ENA__SHIFT 0x2
3163#define CP_COHER_CNTL__TC_NC_ACTION_ENA_MASK 0x8
3164#define CP_COHER_CNTL__TC_NC_ACTION_ENA__SHIFT 0x3
3165#define CP_COHER_CNTL__CB0_DEST_BASE_ENA_MASK 0x40
3166#define CP_COHER_CNTL__CB0_DEST_BASE_ENA__SHIFT 0x6
3167#define CP_COHER_CNTL__CB1_DEST_BASE_ENA_MASK 0x80
3168#define CP_COHER_CNTL__CB1_DEST_BASE_ENA__SHIFT 0x7
3169#define CP_COHER_CNTL__CB2_DEST_BASE_ENA_MASK 0x100
3170#define CP_COHER_CNTL__CB2_DEST_BASE_ENA__SHIFT 0x8
3171#define CP_COHER_CNTL__CB3_DEST_BASE_ENA_MASK 0x200
3172#define CP_COHER_CNTL__CB3_DEST_BASE_ENA__SHIFT 0x9
3173#define CP_COHER_CNTL__CB4_DEST_BASE_ENA_MASK 0x400
3174#define CP_COHER_CNTL__CB4_DEST_BASE_ENA__SHIFT 0xa
3175#define CP_COHER_CNTL__CB5_DEST_BASE_ENA_MASK 0x800
3176#define CP_COHER_CNTL__CB5_DEST_BASE_ENA__SHIFT 0xb
3177#define CP_COHER_CNTL__CB6_DEST_BASE_ENA_MASK 0x1000
3178#define CP_COHER_CNTL__CB6_DEST_BASE_ENA__SHIFT 0xc
3179#define CP_COHER_CNTL__CB7_DEST_BASE_ENA_MASK 0x2000
3180#define CP_COHER_CNTL__CB7_DEST_BASE_ENA__SHIFT 0xd
3181#define CP_COHER_CNTL__DB_DEST_BASE_ENA_MASK 0x4000
3182#define CP_COHER_CNTL__DB_DEST_BASE_ENA__SHIFT 0xe
3183#define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA_MASK 0x8000
3184#define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA__SHIFT 0xf
3185#define CP_COHER_CNTL__TC_WB_ACTION_ENA_MASK 0x40000
3186#define CP_COHER_CNTL__TC_WB_ACTION_ENA__SHIFT 0x12
3187#define CP_COHER_CNTL__DEST_BASE_2_ENA_MASK 0x80000
3188#define CP_COHER_CNTL__DEST_BASE_2_ENA__SHIFT 0x13
3189#define CP_COHER_CNTL__DEST_BASE_3_ENA_MASK 0x200000
3190#define CP_COHER_CNTL__DEST_BASE_3_ENA__SHIFT 0x15
3191#define CP_COHER_CNTL__TCL1_ACTION_ENA_MASK 0x400000
3192#define CP_COHER_CNTL__TCL1_ACTION_ENA__SHIFT 0x16
3193#define CP_COHER_CNTL__TC_ACTION_ENA_MASK 0x800000
3194#define CP_COHER_CNTL__TC_ACTION_ENA__SHIFT 0x17
3195#define CP_COHER_CNTL__CB_ACTION_ENA_MASK 0x2000000
3196#define CP_COHER_CNTL__CB_ACTION_ENA__SHIFT 0x19
3197#define CP_COHER_CNTL__DB_ACTION_ENA_MASK 0x4000000
3198#define CP_COHER_CNTL__DB_ACTION_ENA__SHIFT 0x1a
3199#define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA_MASK 0x8000000
3200#define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA__SHIFT 0x1b
3201#define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA_MASK 0x10000000
3202#define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA__SHIFT 0x1c
3203#define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA_MASK 0x20000000
3204#define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA__SHIFT 0x1d
3205#define CP_COHER_CNTL__SH_KCACHE_WB_ACTION_ENA_MASK 0x40000000
3206#define CP_COHER_CNTL__SH_KCACHE_WB_ACTION_ENA__SHIFT 0x1e
3207#define CP_COHER_CNTL__SH_SD_ACTION_ENA_MASK 0x80000000
3208#define CP_COHER_CNTL__SH_SD_ACTION_ENA__SHIFT 0x1f
3209#define CP_COHER_SIZE__COHER_SIZE_256B_MASK 0xffffffff
3210#define CP_COHER_SIZE__COHER_SIZE_256B__SHIFT 0x0
3211#define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B_MASK 0xff
3212#define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B__SHIFT 0x0
3213#define CP_COHER_BASE__COHER_BASE_256B_MASK 0xffffffff
3214#define CP_COHER_BASE__COHER_BASE_256B__SHIFT 0x0
3215#define CP_COHER_BASE_HI__COHER_BASE_HI_256B_MASK 0xff
3216#define CP_COHER_BASE_HI__COHER_BASE_HI_256B__SHIFT 0x0
3217#define CP_COHER_STATUS__MATCHING_GFX_CNTX_MASK 0xff
3218#define CP_COHER_STATUS__MATCHING_GFX_CNTX__SHIFT 0x0
3219#define CP_COHER_STATUS__MEID_MASK 0x3000000
3220#define CP_COHER_STATUS__MEID__SHIFT 0x18
3221#define CP_COHER_STATUS__PHASE1_STATUS_MASK 0x40000000
3222#define CP_COHER_STATUS__PHASE1_STATUS__SHIFT 0x1e
3223#define CP_COHER_STATUS__STATUS_MASK 0x80000000
3224#define CP_COHER_STATUS__STATUS__SHIFT 0x1f
3225#define COHER_DEST_BASE_0__DEST_BASE_256B_MASK 0xffffffff
3226#define COHER_DEST_BASE_0__DEST_BASE_256B__SHIFT 0x0
3227#define COHER_DEST_BASE_1__DEST_BASE_256B_MASK 0xffffffff
3228#define COHER_DEST_BASE_1__DEST_BASE_256B__SHIFT 0x0
3229#define COHER_DEST_BASE_2__DEST_BASE_256B_MASK 0xffffffff
3230#define COHER_DEST_BASE_2__DEST_BASE_256B__SHIFT 0x0
3231#define COHER_DEST_BASE_3__DEST_BASE_256B_MASK 0xffffffff
3232#define COHER_DEST_BASE_3__DEST_BASE_256B__SHIFT 0x0
3233#define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B_MASK 0xffffffff
3234#define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B__SHIFT 0x0
3235#define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B_MASK 0xffffffff
3236#define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B__SHIFT 0x0
3237#define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B_MASK 0xffffffff
3238#define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B__SHIFT 0x0
3239#define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B_MASK 0xffffffff
3240#define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B__SHIFT 0x0
3241#define CP_DMA_ME_SRC_ADDR__SRC_ADDR_MASK 0xffffffff
3242#define CP_DMA_ME_SRC_ADDR__SRC_ADDR__SHIFT 0x0
3243#define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0xffff
3244#define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x0
3245#define CP_DMA_ME_DST_ADDR__DST_ADDR_MASK 0xffffffff
3246#define CP_DMA_ME_DST_ADDR__DST_ADDR__SHIFT 0x0
3247#define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI_MASK 0xffff
3248#define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x0
3249#define CP_DMA_ME_CONTROL__SRC_MTYPE_MASK 0xc00
3250#define CP_DMA_ME_CONTROL__SRC_MTYPE__SHIFT 0xa
3251#define CP_DMA_ME_CONTROL__SRC_ATC_MASK 0x1000
3252#define CP_DMA_ME_CONTROL__SRC_ATC__SHIFT 0xc
3253#define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY_MASK 0x2000
3254#define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY__SHIFT 0xd
3255#define CP_DMA_ME_CONTROL__DST_SELECT_MASK 0x300000
3256#define CP_DMA_ME_CONTROL__DST_SELECT__SHIFT 0x14
3257#define CP_DMA_ME_CONTROL__DST_MTYPE_MASK 0xc00000
3258#define CP_DMA_ME_CONTROL__DST_MTYPE__SHIFT 0x16
3259#define CP_DMA_ME_CONTROL__DST_ATC_MASK 0x1000000
3260#define CP_DMA_ME_CONTROL__DST_ATC__SHIFT 0x18
3261#define CP_DMA_ME_CONTROL__DST_CACHE_POLICY_MASK 0x2000000
3262#define CP_DMA_ME_CONTROL__DST_CACHE_POLICY__SHIFT 0x19
3263#define CP_DMA_ME_CONTROL__SRC_SELECT_MASK 0x60000000
3264#define CP_DMA_ME_CONTROL__SRC_SELECT__SHIFT 0x1d
3265#define CP_DMA_ME_COMMAND__BYTE_COUNT_MASK 0x1fffff
3266#define CP_DMA_ME_COMMAND__BYTE_COUNT__SHIFT 0x0
3267#define CP_DMA_ME_COMMAND__DIS_WC_MASK 0x200000
3268#define CP_DMA_ME_COMMAND__DIS_WC__SHIFT 0x15
3269#define CP_DMA_ME_COMMAND__SRC_SWAP_MASK 0xc00000
3270#define CP_DMA_ME_COMMAND__SRC_SWAP__SHIFT 0x16
3271#define CP_DMA_ME_COMMAND__DST_SWAP_MASK 0x3000000
3272#define CP_DMA_ME_COMMAND__DST_SWAP__SHIFT 0x18
3273#define CP_DMA_ME_COMMAND__SAS_MASK 0x4000000
3274#define CP_DMA_ME_COMMAND__SAS__SHIFT 0x1a
3275#define CP_DMA_ME_COMMAND__DAS_MASK 0x8000000
3276#define CP_DMA_ME_COMMAND__DAS__SHIFT 0x1b
3277#define CP_DMA_ME_COMMAND__SAIC_MASK 0x10000000
3278#define CP_DMA_ME_COMMAND__SAIC__SHIFT 0x1c
3279#define CP_DMA_ME_COMMAND__DAIC_MASK 0x20000000
3280#define CP_DMA_ME_COMMAND__DAIC__SHIFT 0x1d
3281#define CP_DMA_ME_COMMAND__RAW_WAIT_MASK 0x40000000
3282#define CP_DMA_ME_COMMAND__RAW_WAIT__SHIFT 0x1e
3283#define CP_DMA_PFP_SRC_ADDR__SRC_ADDR_MASK 0xffffffff
3284#define CP_DMA_PFP_SRC_ADDR__SRC_ADDR__SHIFT 0x0
3285#define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0xffff
3286#define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x0
3287#define CP_DMA_PFP_DST_ADDR__DST_ADDR_MASK 0xffffffff
3288#define CP_DMA_PFP_DST_ADDR__DST_ADDR__SHIFT 0x0
3289#define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI_MASK 0xffff
3290#define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x0
3291#define CP_DMA_PFP_CONTROL__SRC_MTYPE_MASK 0xc00
3292#define CP_DMA_PFP_CONTROL__SRC_MTYPE__SHIFT 0xa
3293#define CP_DMA_PFP_CONTROL__SRC_ATC_MASK 0x1000
3294#define CP_DMA_PFP_CONTROL__SRC_ATC__SHIFT 0xc
3295#define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY_MASK 0x2000
3296#define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY__SHIFT 0xd
3297#define CP_DMA_PFP_CONTROL__DST_SELECT_MASK 0x300000
3298#define CP_DMA_PFP_CONTROL__DST_SELECT__SHIFT 0x14
3299#define CP_DMA_PFP_CONTROL__DST_MTYPE_MASK 0xc00000
3300#define CP_DMA_PFP_CONTROL__DST_MTYPE__SHIFT 0x16
3301#define CP_DMA_PFP_CONTROL__DST_ATC_MASK 0x1000000
3302#define CP_DMA_PFP_CONTROL__DST_ATC__SHIFT 0x18
3303#define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY_MASK 0x2000000
3304#define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY__SHIFT 0x19
3305#define CP_DMA_PFP_CONTROL__SRC_SELECT_MASK 0x60000000
3306#define CP_DMA_PFP_CONTROL__SRC_SELECT__SHIFT 0x1d
3307#define CP_DMA_PFP_COMMAND__BYTE_COUNT_MASK 0x1fffff
3308#define CP_DMA_PFP_COMMAND__BYTE_COUNT__SHIFT 0x0
3309#define CP_DMA_PFP_COMMAND__DIS_WC_MASK 0x200000
3310#define CP_DMA_PFP_COMMAND__DIS_WC__SHIFT 0x15
3311#define CP_DMA_PFP_COMMAND__SRC_SWAP_MASK 0xc00000
3312#define CP_DMA_PFP_COMMAND__SRC_SWAP__SHIFT 0x16
3313#define CP_DMA_PFP_COMMAND__DST_SWAP_MASK 0x3000000
3314#define CP_DMA_PFP_COMMAND__DST_SWAP__SHIFT 0x18
3315#define CP_DMA_PFP_COMMAND__SAS_MASK 0x4000000
3316#define CP_DMA_PFP_COMMAND__SAS__SHIFT 0x1a
3317#define CP_DMA_PFP_COMMAND__DAS_MASK 0x8000000
3318#define CP_DMA_PFP_COMMAND__DAS__SHIFT 0x1b
3319#define CP_DMA_PFP_COMMAND__SAIC_MASK 0x10000000
3320#define CP_DMA_PFP_COMMAND__SAIC__SHIFT 0x1c
3321#define CP_DMA_PFP_COMMAND__DAIC_MASK 0x20000000
3322#define CP_DMA_PFP_COMMAND__DAIC__SHIFT 0x1d
3323#define CP_DMA_PFP_COMMAND__RAW_WAIT_MASK 0x40000000
3324#define CP_DMA_PFP_COMMAND__RAW_WAIT__SHIFT 0x1e
3325#define CP_DMA_CNTL__MIN_AVAILSZ_MASK 0x30
3326#define CP_DMA_CNTL__MIN_AVAILSZ__SHIFT 0x4
3327#define CP_DMA_CNTL__BUFFER_DEPTH_MASK 0xf0000
3328#define CP_DMA_CNTL__BUFFER_DEPTH__SHIFT 0x10
3329#define CP_DMA_CNTL__PIO_FIFO_EMPTY_MASK 0x10000000
3330#define CP_DMA_CNTL__PIO_FIFO_EMPTY__SHIFT 0x1c
3331#define CP_DMA_CNTL__PIO_FIFO_FULL_MASK 0x20000000
3332#define CP_DMA_CNTL__PIO_FIFO_FULL__SHIFT 0x1d
3333#define CP_DMA_CNTL__PIO_COUNT_MASK 0xc0000000
3334#define CP_DMA_CNTL__PIO_COUNT__SHIFT 0x1e
3335#define CP_DMA_READ_TAGS__DMA_READ_TAG_MASK 0x3ffffff
3336#define CP_DMA_READ_TAGS__DMA_READ_TAG__SHIFT 0x0
3337#define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID_MASK 0x10000000
3338#define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID__SHIFT 0x1c
3339#define CP_PFP_IB_CONTROL__IB_EN_MASK 0xff
3340#define CP_PFP_IB_CONTROL__IB_EN__SHIFT 0x0
3341#define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN_MASK 0x1
3342#define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN__SHIFT 0x0
3343#define CP_PFP_LOAD_CONTROL__CNTX_REG_EN_MASK 0x2
3344#define CP_PFP_LOAD_CONTROL__CNTX_REG_EN__SHIFT 0x1
3345#define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN_MASK 0x10000
3346#define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN__SHIFT 0x10
3347#define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN_MASK 0x1000000
3348#define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN__SHIFT 0x18
3349#define CP_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0xff
3350#define CP_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0
3351#define CP_SCRATCH_DATA__SCRATCH_DATA_MASK 0xffffffff
3352#define CP_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0
3353#define CP_RB_OFFSET__RB_OFFSET_MASK 0xfffff
3354#define CP_RB_OFFSET__RB_OFFSET__SHIFT 0x0
3355#define CP_IB1_OFFSET__IB1_OFFSET_MASK 0xfffff
3356#define CP_IB1_OFFSET__IB1_OFFSET__SHIFT 0x0
3357#define CP_IB2_OFFSET__IB2_OFFSET_MASK 0xfffff
3358#define CP_IB2_OFFSET__IB2_OFFSET__SHIFT 0x0
3359#define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN_MASK 0xfffff
3360#define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN__SHIFT 0x0
3361#define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END_MASK 0xfffff
3362#define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END__SHIFT 0x0
3363#define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN_MASK 0xfffff
3364#define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN__SHIFT 0x0
3365#define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END_MASK 0xfffff
3366#define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END__SHIFT 0x0
3367#define CP_CE_IB1_OFFSET__IB1_OFFSET_MASK 0xfffff
3368#define CP_CE_IB1_OFFSET__IB1_OFFSET__SHIFT 0x0
3369#define CP_CE_IB2_OFFSET__IB2_OFFSET_MASK 0xfffff
3370#define CP_CE_IB2_OFFSET__IB2_OFFSET__SHIFT 0x0
3371#define CP_CE_COUNTER__CONST_ENGINE_COUNT_MASK 0xffffffff
3372#define CP_CE_COUNTER__CONST_ENGINE_COUNT__SHIFT 0x0
3373#define CP_CE_RB_OFFSET__RB_OFFSET_MASK 0xfffff
3374#define CP_CE_RB_OFFSET__RB_OFFSET__SHIFT 0x0
3375#define CP_PFP_COMPLETION_STATUS__STATUS_MASK 0x3
3376#define CP_PFP_COMPLETION_STATUS__STATUS__SHIFT 0x0
3377#define CP_CE_COMPLETION_STATUS__STATUS_MASK 0x3
3378#define CP_CE_COMPLETION_STATUS__STATUS__SHIFT 0x0
3379#define CP_PRED_NOT_VISIBLE__NOT_VISIBLE_MASK 0x1
3380#define CP_PRED_NOT_VISIBLE__NOT_VISIBLE__SHIFT 0x0
3381#define CP_PFP_METADATA_BASE_ADDR__ADDR_LO_MASK 0xffffffff
3382#define CP_PFP_METADATA_BASE_ADDR__ADDR_LO__SHIFT 0x0
3383#define CP_PFP_METADATA_BASE_ADDR_HI__ADDR_HI_MASK 0xffff
3384#define CP_PFP_METADATA_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0
3385#define CP_CE_METADATA_BASE_ADDR__ADDR_LO_MASK 0xffffffff
3386#define CP_CE_METADATA_BASE_ADDR__ADDR_LO__SHIFT 0x0
3387#define CP_CE_METADATA_BASE_ADDR_HI__ADDR_HI_MASK 0xffff
3388#define CP_CE_METADATA_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0
3389#define CP_DRAW_INDX_INDR_ADDR__ADDR_LO_MASK 0xffffffff
3390#define CP_DRAW_INDX_INDR_ADDR__ADDR_LO__SHIFT 0x0
3391#define CP_DRAW_INDX_INDR_ADDR_HI__ADDR_HI_MASK 0xffff
3392#define CP_DRAW_INDX_INDR_ADDR_HI__ADDR_HI__SHIFT 0x0
3393#define CP_DISPATCH_INDR_ADDR__ADDR_LO_MASK 0xffffffff
3394#define CP_DISPATCH_INDR_ADDR__ADDR_LO__SHIFT 0x0
3395#define CP_DISPATCH_INDR_ADDR_HI__ADDR_HI_MASK 0xffff
3396#define CP_DISPATCH_INDR_ADDR_HI__ADDR_HI__SHIFT 0x0
3397#define CP_INDEX_BASE_ADDR__ADDR_LO_MASK 0xffffffff
3398#define CP_INDEX_BASE_ADDR__ADDR_LO__SHIFT 0x0
3399#define CP_INDEX_BASE_ADDR_HI__ADDR_HI_MASK 0xffff
3400#define CP_INDEX_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0
3401#define CP_INDEX_TYPE__INDEX_TYPE_MASK 0x3
3402#define CP_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0
3403#define CP_GDS_BKUP_ADDR__ADDR_LO_MASK 0xffffffff
3404#define CP_GDS_BKUP_ADDR__ADDR_LO__SHIFT 0x0
3405#define CP_GDS_BKUP_ADDR_HI__ADDR_HI_MASK 0xffff
3406#define CP_GDS_BKUP_ADDR_HI__ADDR_HI__SHIFT 0x0
3407#define CP_SAMPLE_STATUS__Z_PASS_ACITVE_MASK 0x1
3408#define CP_SAMPLE_STATUS__Z_PASS_ACITVE__SHIFT 0x0
3409#define CP_SAMPLE_STATUS__STREAMOUT_ACTIVE_MASK 0x2
3410#define CP_SAMPLE_STATUS__STREAMOUT_ACTIVE__SHIFT 0x1
3411#define CP_SAMPLE_STATUS__PIPELINE_ACTIVE_MASK 0x4
3412#define CP_SAMPLE_STATUS__PIPELINE_ACTIVE__SHIFT 0x2
3413#define CP_SAMPLE_STATUS__STIPPLE_ACTIVE_MASK 0x8
3414#define CP_SAMPLE_STATUS__STIPPLE_ACTIVE__SHIFT 0x3
3415#define CP_SAMPLE_STATUS__VGT_BUFFERS_ACTIVE_MASK 0x10
3416#define CP_SAMPLE_STATUS__VGT_BUFFERS_ACTIVE__SHIFT 0x4
3417#define CP_SAMPLE_STATUS__SCREEN_EXT_ACTIVE_MASK 0x20
3418#define CP_SAMPLE_STATUS__SCREEN_EXT_ACTIVE__SHIFT 0x5
3419#define CP_SAMPLE_STATUS__DRAW_INDIRECT_ACTIVE_MASK 0x40
3420#define CP_SAMPLE_STATUS__DRAW_INDIRECT_ACTIVE__SHIFT 0x6
3421#define CP_SAMPLE_STATUS__DISP_INDIRECT_ACTIVE_MASK 0x80
3422#define CP_SAMPLE_STATUS__DISP_INDIRECT_ACTIVE__SHIFT 0x7
3423#define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV_MASK 0x1
3424#define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV__SHIFT 0x0
3425#define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV_MASK 0x4
3426#define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV__SHIFT 0x2
3427#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV_MASK 0x10
3428#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV__SHIFT 0x4
3429#define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG_MASK 0x400
3430#define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG__SHIFT 0xa
3431#define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG_MASK 0x800
3432#define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG__SHIFT 0xb
3433#define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM_MASK 0x1000
3434#define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM__SHIFT 0xc
3435#define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x2000
3436#define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0xd
3437#define CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA_MASK 0x4000
3438#define CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA__SHIFT 0xe
3439#define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA_MASK 0x8000
3440#define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA__SHIFT 0xf
3441#define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE_MASK 0x800000
3442#define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE__SHIFT 0x17
3443#define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE_MASK 0x1000000
3444#define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE__SHIFT 0x18
3445#define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE_MASK 0x2000000
3446#define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE__SHIFT 0x19
3447#define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ_MASK 0x4000000
3448#define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ__SHIFT 0x1a
3449#define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ_MASK 0x8000000
3450#define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ__SHIFT 0x1b
3451#define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ_MASK 0x10000000
3452#define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ__SHIFT 0x1c
3453#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION_MASK 0x20000000
3454#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION__SHIFT 0x1d
3455#define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV_MASK 0x1
3456#define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0
3457#define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV_MASK 0x2
3458#define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV__SHIFT 0x1
3459#define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV_MASK 0x4
3460#define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV__SHIFT 0x2
3461#define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING_MASK 0x10
3462#define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING__SHIFT 0x4
3463#define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING_MASK 0x20
3464#define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING__SHIFT 0x5
3465#define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA_MASK 0x100
3466#define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA__SHIFT 0x8
3467#define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER_MASK 0x200
3468#define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER__SHIFT 0x9
3469#define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER_MASK 0x400
3470#define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER__SHIFT 0xa
3471#define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME_MASK 0x800
3472#define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME__SHIFT 0xb
3473#define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV_MASK 0x1000
3474#define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV__SHIFT 0xc
3475#define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV_MASK 0x2000
3476#define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV__SHIFT 0xd
3477#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP_MASK 0x4000
3478#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP__SHIFT 0xe
3479#define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH_MASK 0x8000
3480#define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH__SHIFT 0xf
3481#define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x10000
3482#define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x10
3483#define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x20000
3484#define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x11
3485#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ_MASK 0x40000
3486#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ__SHIFT 0x12
3487#define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM_MASK 0x80000
3488#define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x13
3489#define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x100000
3490#define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x14
3491#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE_MASK 0x200000
3492#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE__SHIFT 0x15
3493#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM_MASK 0x400000
3494#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM__SHIFT 0x16
3495#define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING_MASK 0x800000
3496#define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING__SHIFT 0x17
3497#define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING_MASK 0x1000000
3498#define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING__SHIFT 0x18
3499#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE_MASK 0x2000000
3500#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE__SHIFT 0x19
3501#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE_MASK 0x4000000
3502#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE__SHIFT 0x1a
3503#define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM_MASK 0x8000000
3504#define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM__SHIFT 0x1b
3505#define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION_MASK 0x10000000
3506#define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION__SHIFT 0x1c
3507#define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE_MASK 0x20000000
3508#define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE__SHIFT 0x1d
3509#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS_MASK 0x40000000
3510#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS__SHIFT 0x1e
3511#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN_MASK 0x80000000
3512#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN__SHIFT 0x1f
3513#define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV_MASK 0x1
3514#define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0
3515#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV_MASK 0x2
3516#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV__SHIFT 0x1
3517#define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER_MASK 0x4
3518#define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER__SHIFT 0x2
3519#define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY_MASK 0x8
3520#define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY__SHIFT 0x3
3521#define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY_MASK 0x10
3522#define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY__SHIFT 0x4
3523#define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY_MASK 0x20
3524#define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY__SHIFT 0x5
3525#define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV_MASK 0x40
3526#define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV__SHIFT 0x6
3527#define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV_MASK 0x80
3528#define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV__SHIFT 0x7
3529#define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA_MASK 0x400
3530#define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA__SHIFT 0xa
3531#define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG_MASK 0x800
3532#define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG__SHIFT 0xb
3533#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_MASK 0x1000
3534#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER__SHIFT 0xc
3535#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW_MASK 0x2000
3536#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW__SHIFT 0xd
3537#define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE_MASK 0x4000
3538#define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE__SHIFT 0xe
3539#define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS_MASK 0x8000
3540#define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS__SHIFT 0xf
3541#define CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM_MASK 0x10000
3542#define CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x10
3543#define CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x20000
3544#define CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x11
3545#define CP_STALLED_STAT3__ATCL2IU_WAITING_ON_FREE_MASK 0x40000
3546#define CP_STALLED_STAT3__ATCL2IU_WAITING_ON_FREE__SHIFT 0x12
3547#define CP_STALLED_STAT3__ATCL2IU_WAITING_ON_TAGS_MASK 0x80000
3548#define CP_STALLED_STAT3__ATCL2IU_WAITING_ON_TAGS__SHIFT 0x13
3549#define CP_STALLED_STAT3__ATCL1_WAITING_ON_TRANS_MASK 0x100000
3550#define CP_STALLED_STAT3__ATCL1_WAITING_ON_TRANS__SHIFT 0x14
3551#define CP_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x1
3552#define CP_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x0
3553#define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO_MASK 0x40
3554#define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO__SHIFT 0x6
3555#define CP_BUSY_STAT__PFP_PARSING_PACKETS_MASK 0x80
3556#define CP_BUSY_STAT__PFP_PARSING_PACKETS__SHIFT 0x7
3557#define CP_BUSY_STAT__ME_PARSING_PACKETS_MASK 0x100
3558#define CP_BUSY_STAT__ME_PARSING_PACKETS__SHIFT 0x8
3559#define CP_BUSY_STAT__RCIU_PFP_BUSY_MASK 0x200
3560#define CP_BUSY_STAT__RCIU_PFP_BUSY__SHIFT 0x9
3561#define CP_BUSY_STAT__RCIU_ME_BUSY_MASK 0x400
3562#define CP_BUSY_STAT__RCIU_ME_BUSY__SHIFT 0xa
3563#define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY_MASK 0x1000
3564#define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY__SHIFT 0xc
3565#define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING_MASK 0x2000
3566#define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING__SHIFT 0xd
3567#define CP_BUSY_STAT__SEM_POLLING_FOR_PASS_MASK 0x4000
3568#define CP_BUSY_STAT__SEM_POLLING_FOR_PASS__SHIFT 0xe
3569#define CP_BUSY_STAT__GFX_CONTEXT_BUSY_MASK 0x8000
3570#define CP_BUSY_STAT__GFX_CONTEXT_BUSY__SHIFT 0xf
3571#define CP_BUSY_STAT__ME_PARSER_BUSY_MASK 0x20000
3572#define CP_BUSY_STAT__ME_PARSER_BUSY__SHIFT 0x11
3573#define CP_BUSY_STAT__EOP_DONE_BUSY_MASK 0x40000
3574#define CP_BUSY_STAT__EOP_DONE_BUSY__SHIFT 0x12
3575#define CP_BUSY_STAT__STRM_OUT_BUSY_MASK 0x80000
3576#define CP_BUSY_STAT__STRM_OUT_BUSY__SHIFT 0x13
3577#define CP_BUSY_STAT__PIPE_STATS_BUSY_MASK 0x100000
3578#define CP_BUSY_STAT__PIPE_STATS_BUSY__SHIFT 0x14
3579#define CP_BUSY_STAT__RCIU_CE_BUSY_MASK 0x200000
3580#define CP_BUSY_STAT__RCIU_CE_BUSY__SHIFT 0x15
3581#define CP_BUSY_STAT__CE_PARSING_PACKETS_MASK 0x400000
3582#define CP_BUSY_STAT__CE_PARSING_PACKETS__SHIFT 0x16
3583#define CP_STAT__ROQ_RING_BUSY_MASK 0x200
3584#define CP_STAT__ROQ_RING_BUSY__SHIFT 0x9
3585#define CP_STAT__ROQ_INDIRECT1_BUSY_MASK 0x400
3586#define CP_STAT__ROQ_INDIRECT1_BUSY__SHIFT 0xa
3587#define CP_STAT__ROQ_INDIRECT2_BUSY_MASK 0x800
3588#define CP_STAT__ROQ_INDIRECT2_BUSY__SHIFT 0xb
3589#define CP_STAT__ROQ_STATE_BUSY_MASK 0x1000
3590#define CP_STAT__ROQ_STATE_BUSY__SHIFT 0xc
3591#define CP_STAT__DC_BUSY_MASK 0x2000
3592#define CP_STAT__DC_BUSY__SHIFT 0xd
3593#define CP_STAT__ATCL2IU_BUSY_MASK 0x4000
3594#define CP_STAT__ATCL2IU_BUSY__SHIFT 0xe
3595#define CP_STAT__PFP_BUSY_MASK 0x8000
3596#define CP_STAT__PFP_BUSY__SHIFT 0xf
3597#define CP_STAT__MEQ_BUSY_MASK 0x10000
3598#define CP_STAT__MEQ_BUSY__SHIFT 0x10
3599#define CP_STAT__ME_BUSY_MASK 0x20000
3600#define CP_STAT__ME_BUSY__SHIFT 0x11
3601#define CP_STAT__QUERY_BUSY_MASK 0x40000
3602#define CP_STAT__QUERY_BUSY__SHIFT 0x12
3603#define CP_STAT__SEMAPHORE_BUSY_MASK 0x80000
3604#define CP_STAT__SEMAPHORE_BUSY__SHIFT 0x13
3605#define CP_STAT__INTERRUPT_BUSY_MASK 0x100000
3606#define CP_STAT__INTERRUPT_BUSY__SHIFT 0x14
3607#define CP_STAT__SURFACE_SYNC_BUSY_MASK 0x200000
3608#define CP_STAT__SURFACE_SYNC_BUSY__SHIFT 0x15
3609#define CP_STAT__DMA_BUSY_MASK 0x400000
3610#define CP_STAT__DMA_BUSY__SHIFT 0x16
3611#define CP_STAT__RCIU_BUSY_MASK 0x800000
3612#define CP_STAT__RCIU_BUSY__SHIFT 0x17
3613#define CP_STAT__SCRATCH_RAM_BUSY_MASK 0x1000000
3614#define CP_STAT__SCRATCH_RAM_BUSY__SHIFT 0x18
3615#define CP_STAT__CPC_CPG_BUSY_MASK 0x2000000
3616#define CP_STAT__CPC_CPG_BUSY__SHIFT 0x19
3617#define CP_STAT__CE_BUSY_MASK 0x4000000
3618#define CP_STAT__CE_BUSY__SHIFT 0x1a
3619#define CP_STAT__TCIU_BUSY_MASK 0x8000000
3620#define CP_STAT__TCIU_BUSY__SHIFT 0x1b
3621#define CP_STAT__ROQ_CE_RING_BUSY_MASK 0x10000000
3622#define CP_STAT__ROQ_CE_RING_BUSY__SHIFT 0x1c
3623#define CP_STAT__ROQ_CE_INDIRECT1_BUSY_MASK 0x20000000
3624#define CP_STAT__ROQ_CE_INDIRECT1_BUSY__SHIFT 0x1d
3625#define CP_STAT__ROQ_CE_INDIRECT2_BUSY_MASK 0x40000000
3626#define CP_STAT__ROQ_CE_INDIRECT2_BUSY__SHIFT 0x1e
3627#define CP_STAT__CP_BUSY_MASK 0x80000000
3628#define CP_STAT__CP_BUSY__SHIFT 0x1f
3629#define CP_ME_HEADER_DUMP__ME_HEADER_DUMP_MASK 0xffffffff
3630#define CP_ME_HEADER_DUMP__ME_HEADER_DUMP__SHIFT 0x0
3631#define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP_MASK 0xffffffff
3632#define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP__SHIFT 0x0
3633#define CP_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x3f
3634#define CP_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0
3635#define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS_MASK 0x3f00
3636#define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS__SHIFT 0x8
3637#define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP_MASK 0x3f0000
3638#define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP__SHIFT 0x10
3639#define CP_CE_HEADER_DUMP__CE_HEADER_DUMP_MASK 0xffffffff
3640#define CP_CE_HEADER_DUMP__CE_HEADER_DUMP__SHIFT 0x0
3641#define CP_CSF_STAT__BUFFER_SLOTS_ALLOCATED_MASK 0xf
3642#define CP_CSF_STAT__BUFFER_SLOTS_ALLOCATED__SHIFT 0x0
3643#define CP_CSF_STAT__BUFFER_REQUEST_COUNT_MASK 0x1ff00
3644#define CP_CSF_STAT__BUFFER_REQUEST_COUNT__SHIFT 0x8
3645#define CP_CSF_CNTL__FETCH_BUFFER_DEPTH_MASK 0xf
3646#define CP_CSF_CNTL__FETCH_BUFFER_DEPTH__SHIFT 0x0
3647#define CP_ME_CNTL__CE_INVALIDATE_ICACHE_MASK 0x10
3648#define CP_ME_CNTL__CE_INVALIDATE_ICACHE__SHIFT 0x4
3649#define CP_ME_CNTL__PFP_INVALIDATE_ICACHE_MASK 0x40
3650#define CP_ME_CNTL__PFP_INVALIDATE_ICACHE__SHIFT 0x6
3651#define CP_ME_CNTL__ME_INVALIDATE_ICACHE_MASK 0x100
3652#define CP_ME_CNTL__ME_INVALIDATE_ICACHE__SHIFT 0x8
3653#define CP_ME_CNTL__CE_PIPE0_RESET_MASK 0x10000
3654#define CP_ME_CNTL__CE_PIPE0_RESET__SHIFT 0x10
3655#define CP_ME_CNTL__PFP_PIPE0_RESET_MASK 0x40000
3656#define CP_ME_CNTL__PFP_PIPE0_RESET__SHIFT 0x12
3657#define CP_ME_CNTL__ME_PIPE0_RESET_MASK 0x100000
3658#define CP_ME_CNTL__ME_PIPE0_RESET__SHIFT 0x14
3659#define CP_ME_CNTL__CE_HALT_MASK 0x1000000
3660#define CP_ME_CNTL__CE_HALT__SHIFT 0x18
3661#define CP_ME_CNTL__CE_STEP_MASK 0x2000000
3662#define CP_ME_CNTL__CE_STEP__SHIFT 0x19
3663#define CP_ME_CNTL__PFP_HALT_MASK 0x4000000
3664#define CP_ME_CNTL__PFP_HALT__SHIFT 0x1a
3665#define CP_ME_CNTL__PFP_STEP_MASK 0x8000000
3666#define CP_ME_CNTL__PFP_STEP__SHIFT 0x1b
3667#define CP_ME_CNTL__ME_HALT_MASK 0x10000000
3668#define CP_ME_CNTL__ME_HALT__SHIFT 0x1c
3669#define CP_ME_CNTL__ME_STEP_MASK 0x20000000
3670#define CP_ME_CNTL__ME_STEP__SHIFT 0x1d
3671#define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS_MASK 0xff
3672#define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS__SHIFT 0x0
3673#define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT_MASK 0x700
3674#define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT__SHIFT 0x8
3675#define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS_MASK 0xff00000
3676#define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS__SHIFT 0x14
3677#define CP_CNTX_STAT__CURRENT_GFX_CONTEXT_MASK 0x70000000
3678#define CP_CNTX_STAT__CURRENT_GFX_CONTEXT__SHIFT 0x1c
3679#define CP_ME_PREEMPTION__OBSOLETE_MASK 0x1
3680#define CP_ME_PREEMPTION__OBSOLETE__SHIFT 0x0
3681#define CP_RB0_RPTR__RB_RPTR_MASK 0xfffff
3682#define CP_RB0_RPTR__RB_RPTR__SHIFT 0x0
3683#define CP_RB_RPTR__RB_RPTR_MASK 0xfffff
3684#define CP_RB_RPTR__RB_RPTR__SHIFT 0x0
3685#define CP_RB1_RPTR__RB_RPTR_MASK 0xfffff
3686#define CP_RB1_RPTR__RB_RPTR__SHIFT 0x0
3687#define CP_RB2_RPTR__RB_RPTR_MASK 0xfffff
3688#define CP_RB2_RPTR__RB_RPTR__SHIFT 0x0
3689#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER_MASK 0xfffffff
3690#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER__SHIFT 0x0
3691#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT_MASK 0xf0000000
3692#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT__SHIFT 0x1c
3693#define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK 0xffff
3694#define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT 0x0
3695#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000
3696#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
3697#define CP_CE_INIT_BASE_LO__INIT_BASE_LO_MASK 0xffffffe0
3698#define CP_CE_INIT_BASE_LO__INIT_BASE_LO__SHIFT 0x5
3699#define CP_CE_INIT_BASE_HI__INIT_BASE_HI_MASK 0xffff
3700#define CP_CE_INIT_BASE_HI__INIT_BASE_HI__SHIFT 0x0
3701#define CP_CE_INIT_BUFSZ__INIT_BUFSZ_MASK 0xfff
3702#define CP_CE_INIT_BUFSZ__INIT_BUFSZ__SHIFT 0x0
3703#define CP_CE_IB1_BASE_LO__IB1_BASE_LO_MASK 0xfffffffc
3704#define CP_CE_IB1_BASE_LO__IB1_BASE_LO__SHIFT 0x2
3705#define CP_CE_IB1_BASE_HI__IB1_BASE_HI_MASK 0xffff
3706#define CP_CE_IB1_BASE_HI__IB1_BASE_HI__SHIFT 0x0
3707#define CP_CE_IB1_BUFSZ__IB1_BUFSZ_MASK 0xfffff
3708#define CP_CE_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x0
3709#define CP_CE_IB2_BASE_LO__IB2_BASE_LO_MASK 0xfffffffc
3710#define CP_CE_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x2
3711#define CP_CE_IB2_BASE_HI__IB2_BASE_HI_MASK 0xffff
3712#define CP_CE_IB2_BASE_HI__IB2_BASE_HI__SHIFT 0x0
3713#define CP_CE_IB2_BUFSZ__IB2_BUFSZ_MASK 0xfffff
3714#define CP_CE_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x0
3715#define CP_IB1_BASE_LO__IB1_BASE_LO_MASK 0xfffffffc
3716#define CP_IB1_BASE_LO__IB1_BASE_LO__SHIFT 0x2
3717#define CP_IB1_BASE_HI__IB1_BASE_HI_MASK 0xffff
3718#define CP_IB1_BASE_HI__IB1_BASE_HI__SHIFT 0x0
3719#define CP_IB1_BUFSZ__IB1_BUFSZ_MASK 0xfffff
3720#define CP_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x0
3721#define CP_IB2_BASE_LO__IB2_BASE_LO_MASK 0xfffffffc
3722#define CP_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x2
3723#define CP_IB2_BASE_HI__IB2_BASE_HI_MASK 0xffff
3724#define CP_IB2_BASE_HI__IB2_BASE_HI__SHIFT 0x0
3725#define CP_IB2_BUFSZ__IB2_BUFSZ_MASK 0xfffff
3726#define CP_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x0
3727#define CP_ST_BASE_LO__ST_BASE_LO_MASK 0xfffffffc
3728#define CP_ST_BASE_LO__ST_BASE_LO__SHIFT 0x2
3729#define CP_ST_BASE_HI__ST_BASE_HI_MASK 0xffff
3730#define CP_ST_BASE_HI__ST_BASE_HI__SHIFT 0x0
3731#define CP_ST_BUFSZ__ST_BUFSZ_MASK 0xfffff
3732#define CP_ST_BUFSZ__ST_BUFSZ__SHIFT 0x0
3733#define CP_ROQ_THRESHOLDS__IB1_START_MASK 0xff
3734#define CP_ROQ_THRESHOLDS__IB1_START__SHIFT 0x0
3735#define CP_ROQ_THRESHOLDS__IB2_START_MASK 0xff00
3736#define CP_ROQ_THRESHOLDS__IB2_START__SHIFT 0x8
3737#define CP_MEQ_STQ_THRESHOLD__STQ_START_MASK 0xff
3738#define CP_MEQ_STQ_THRESHOLD__STQ_START__SHIFT 0x0
3739#define CP_ROQ1_THRESHOLDS__RB1_START_MASK 0xff
3740#define CP_ROQ1_THRESHOLDS__RB1_START__SHIFT 0x0
3741#define CP_ROQ1_THRESHOLDS__RB2_START_MASK 0xff00
3742#define CP_ROQ1_THRESHOLDS__RB2_START__SHIFT 0x8
3743#define CP_ROQ1_THRESHOLDS__R0_IB1_START_MASK 0xff0000
3744#define CP_ROQ1_THRESHOLDS__R0_IB1_START__SHIFT 0x10
3745#define CP_ROQ1_THRESHOLDS__R1_IB1_START_MASK 0xff000000
3746#define CP_ROQ1_THRESHOLDS__R1_IB1_START__SHIFT 0x18
3747#define CP_ROQ2_THRESHOLDS__R2_IB1_START_MASK 0xff
3748#define CP_ROQ2_THRESHOLDS__R2_IB1_START__SHIFT 0x0
3749#define CP_ROQ2_THRESHOLDS__R0_IB2_START_MASK 0xff00
3750#define CP_ROQ2_THRESHOLDS__R0_IB2_START__SHIFT 0x8
3751#define CP_ROQ2_THRESHOLDS__R1_IB2_START_MASK 0xff0000
3752#define CP_ROQ2_THRESHOLDS__R1_IB2_START__SHIFT 0x10
3753#define CP_ROQ2_THRESHOLDS__R2_IB2_START_MASK 0xff000000
3754#define CP_ROQ2_THRESHOLDS__R2_IB2_START__SHIFT 0x18
3755#define CP_STQ_THRESHOLDS__STQ0_START_MASK 0xff
3756#define CP_STQ_THRESHOLDS__STQ0_START__SHIFT 0x0
3757#define CP_STQ_THRESHOLDS__STQ1_START_MASK 0xff00
3758#define CP_STQ_THRESHOLDS__STQ1_START__SHIFT 0x8
3759#define CP_STQ_THRESHOLDS__STQ2_START_MASK 0xff0000
3760#define CP_STQ_THRESHOLDS__STQ2_START__SHIFT 0x10
3761#define CP_QUEUE_THRESHOLDS__ROQ_IB1_START_MASK 0x3f
3762#define CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT 0x0
3763#define CP_QUEUE_THRESHOLDS__ROQ_IB2_START_MASK 0x3f00
3764#define CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT 0x8
3765#define CP_MEQ_THRESHOLDS__MEQ1_START_MASK 0xff
3766#define CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT 0x0
3767#define CP_MEQ_THRESHOLDS__MEQ2_START_MASK 0xff00
3768#define CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT 0x8
3769#define CP_ROQ_AVAIL__ROQ_CNT_RING_MASK 0x7ff
3770#define CP_ROQ_AVAIL__ROQ_CNT_RING__SHIFT 0x0
3771#define CP_ROQ_AVAIL__ROQ_CNT_IB1_MASK 0x7ff0000
3772#define CP_ROQ_AVAIL__ROQ_CNT_IB1__SHIFT 0x10
3773#define CP_STQ_AVAIL__STQ_CNT_MASK 0x1ff
3774#define CP_STQ_AVAIL__STQ_CNT__SHIFT 0x0
3775#define CP_ROQ2_AVAIL__ROQ_CNT_IB2_MASK 0x7ff
3776#define CP_ROQ2_AVAIL__ROQ_CNT_IB2__SHIFT 0x0
3777#define CP_MEQ_AVAIL__MEQ_CNT_MASK 0x3ff
3778#define CP_MEQ_AVAIL__MEQ_CNT__SHIFT 0x0
3779#define CP_CMD_INDEX__CMD_INDEX_MASK 0x7ff
3780#define CP_CMD_INDEX__CMD_INDEX__SHIFT 0x0
3781#define CP_CMD_INDEX__CMD_ME_SEL_MASK 0x3000
3782#define CP_CMD_INDEX__CMD_ME_SEL__SHIFT 0xc
3783#define CP_CMD_INDEX__CMD_QUEUE_SEL_MASK 0x70000
3784#define CP_CMD_INDEX__CMD_QUEUE_SEL__SHIFT 0x10
3785#define CP_CMD_DATA__CMD_DATA_MASK 0xffffffff
3786#define CP_CMD_DATA__CMD_DATA__SHIFT 0x0
3787#define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY_MASK 0x3ff
3788#define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY__SHIFT 0x0
3789#define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY_MASK 0x3ff0000
3790#define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY__SHIFT 0x10
3791#define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1_MASK 0x3ff
3792#define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1__SHIFT 0x0
3793#define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1_MASK 0x3ff0000
3794#define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1__SHIFT 0x10
3795#define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2_MASK 0x3ff
3796#define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2__SHIFT 0x0
3797#define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2_MASK 0x3ff0000
3798#define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2__SHIFT 0x10
3799#define CP_STQ_STAT__STQ_RPTR_MASK 0x3ff
3800#define CP_STQ_STAT__STQ_RPTR__SHIFT 0x0
3801#define CP_STQ_WR_STAT__STQ_WPTR_MASK 0x3ff
3802#define CP_STQ_WR_STAT__STQ_WPTR__SHIFT 0x0
3803#define CP_MEQ_STAT__MEQ_RPTR_MASK 0x3ff
3804#define CP_MEQ_STAT__MEQ_RPTR__SHIFT 0x0
3805#define CP_MEQ_STAT__MEQ_WPTR_MASK 0x3ff0000
3806#define CP_MEQ_STAT__MEQ_WPTR__SHIFT 0x10
3807#define CP_CEQ1_AVAIL__CEQ_CNT_RING_MASK 0x7ff
3808#define CP_CEQ1_AVAIL__CEQ_CNT_RING__SHIFT 0x0
3809#define CP_CEQ1_AVAIL__CEQ_CNT_IB1_MASK 0x7ff0000
3810#define CP_CEQ1_AVAIL__CEQ_CNT_IB1__SHIFT 0x10
3811#define CP_CEQ2_AVAIL__CEQ_CNT_IB2_MASK 0x7ff
3812#define CP_CEQ2_AVAIL__CEQ_CNT_IB2__SHIFT 0x0
3813#define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY_MASK 0x3ff
3814#define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY__SHIFT 0x0
3815#define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY_MASK 0x3ff0000
3816#define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY__SHIFT 0x10
3817#define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1_MASK 0x3ff
3818#define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1__SHIFT 0x0
3819#define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1_MASK 0x3ff0000
3820#define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1__SHIFT 0x10
3821#define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2_MASK 0x3ff
3822#define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2__SHIFT 0x0
3823#define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2_MASK 0x3ff0000
3824#define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2__SHIFT 0x10
3825#define CP_INT_STAT_DEBUG__CP_VM_DOORBELL_WR_INT_ASSERTED_MASK 0x800
3826#define CP_INT_STAT_DEBUG__CP_VM_DOORBELL_WR_INT_ASSERTED__SHIFT 0xb
3827#define CP_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x4000
3828#define CP_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0xe
3829#define CP_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x20000
3830#define CP_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x11
3831#define CP_INT_STAT_DEBUG__CMP_BUSY_INT_ASSERTED_MASK 0x40000
3832#define CP_INT_STAT_DEBUG__CMP_BUSY_INT_ASSERTED__SHIFT 0x12
3833#define CP_INT_STAT_DEBUG__CNTX_BUSY_INT_ASSERTED_MASK 0x80000
3834#define CP_INT_STAT_DEBUG__CNTX_BUSY_INT_ASSERTED__SHIFT 0x13
3835#define CP_INT_STAT_DEBUG__CNTX_EMPTY_INT_ASSERTED_MASK 0x100000
3836#define CP_INT_STAT_DEBUG__CNTX_EMPTY_INT_ASSERTED__SHIFT 0x14
3837#define CP_INT_STAT_DEBUG__GFX_IDLE_INT_ASSERTED_MASK 0x200000
3838#define CP_INT_STAT_DEBUG__GFX_IDLE_INT_ASSERTED__SHIFT 0x15
3839#define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED_MASK 0x400000
3840#define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED__SHIFT 0x16
3841#define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x800000
3842#define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17
3843#define CP_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x1000000
3844#define CP_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x18
3845#define CP_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x4000000
3846#define CP_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x1a
3847#define CP_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x8000000
3848#define CP_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x1b
3849#define CP_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000
3850#define CP_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d
3851#define CP_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000
3852#define CP_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x1e
3853#define CP_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000
3854#define CP_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x1f
3855#define CP_PERFMON_CNTL__PERFMON_STATE_MASK 0xf
3856#define CP_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
3857#define CP_PERFMON_CNTL__SPM_PERFMON_STATE_MASK 0xf0
3858#define CP_PERFMON_CNTL__SPM_PERFMON_STATE__SHIFT 0x4
3859#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK 0x300
3860#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT 0x8
3861#define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x400
3862#define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa
3863#define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE_MASK 0x80000000
3864#define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE__SHIFT 0x1f
3865#define CP_RINGID__RINGID_MASK 0x3
3866#define CP_RINGID__RINGID__SHIFT 0x0
3867#define CP_PIPEID__PIPE_ID_MASK 0x3
3868#define CP_PIPEID__PIPE_ID__SHIFT 0x0
3869#define CP_VMID__VMID_MASK 0xf
3870#define CP_VMID__VMID__SHIFT 0x0
3871#define CP_HPD_ROQ_OFFSETS__IQ_OFFSET_MASK 0x7
3872#define CP_HPD_ROQ_OFFSETS__IQ_OFFSET__SHIFT 0x0
3873#define CP_HPD_ROQ_OFFSETS__PQ_OFFSET_MASK 0x3f00
3874#define CP_HPD_ROQ_OFFSETS__PQ_OFFSET__SHIFT 0x8
3875#define CP_HPD_ROQ_OFFSETS__IB_OFFSET_MASK 0x3f0000
3876#define CP_HPD_ROQ_OFFSETS__IB_OFFSET__SHIFT 0x10
3877#define CP_HPD_STATUS0__QUEUE_STATE_MASK 0x1f
3878#define CP_HPD_STATUS0__QUEUE_STATE__SHIFT 0x0
3879#define CP_HPD_STATUS0__MAPPED_QUEUE_MASK 0xe0
3880#define CP_HPD_STATUS0__MAPPED_QUEUE__SHIFT 0x5
3881#define CP_HPD_STATUS0__QUEUE_AVAILABLE_MASK 0xff00
3882#define CP_HPD_STATUS0__QUEUE_AVAILABLE__SHIFT 0x8
3883#define CP_MQD_BASE_ADDR__BASE_ADDR_MASK 0xfffffffc
3884#define CP_MQD_BASE_ADDR__BASE_ADDR__SHIFT 0x2
3885#define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0xffff
3886#define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0
3887#define CP_HQD_ACTIVE__ACTIVE_MASK 0x1
3888#define CP_HQD_ACTIVE__ACTIVE__SHIFT 0x0
3889#define CP_HQD_ACTIVE__BUSY_GATE_MASK 0x2
3890#define CP_HQD_ACTIVE__BUSY_GATE__SHIFT 0x1
3891#define CP_HQD_VMID__VMID_MASK 0xf
3892#define CP_HQD_VMID__VMID__SHIFT 0x0
3893#define CP_HQD_VMID__IB_VMID_MASK 0xf00
3894#define CP_HQD_VMID__IB_VMID__SHIFT 0x8
3895#define CP_HQD_VMID__VQID_MASK 0x3ff0000
3896#define CP_HQD_VMID__VQID__SHIFT 0x10
3897#define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK 0x1
3898#define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ__SHIFT 0x0
3899#define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE_MASK 0x3ff00
3900#define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT 0x8
3901#define CP_HQD_PERSISTENT_STATE__RESTORE_ACTIVE_MASK 0x10000000
3902#define CP_HQD_PERSISTENT_STATE__RESTORE_ACTIVE__SHIFT 0x1c
3903#define CP_HQD_PERSISTENT_STATE__RELAUNCH_WAVES_MASK 0x20000000
3904#define CP_HQD_PERSISTENT_STATE__RELAUNCH_WAVES__SHIFT 0x1d
3905#define CP_HQD_PERSISTENT_STATE__QSWITCH_MODE_MASK 0x40000000
3906#define CP_HQD_PERSISTENT_STATE__QSWITCH_MODE__SHIFT 0x1e
3907#define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE_MASK 0x80000000
3908#define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE__SHIFT 0x1f
3909#define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY_MASK 0x3
3910#define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY__SHIFT 0x0
3911#define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL_MASK 0xf
3912#define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL__SHIFT 0x0
3913#define CP_HQD_QUANTUM__QUANTUM_EN_MASK 0x1
3914#define CP_HQD_QUANTUM__QUANTUM_EN__SHIFT 0x0
3915#define CP_HQD_QUANTUM__QUANTUM_SCALE_MASK 0x10
3916#define CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT 0x4
3917#define CP_HQD_QUANTUM__QUANTUM_DURATION_MASK 0x3f00
3918#define CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT 0x8
3919#define CP_HQD_QUANTUM__QUANTUM_ACTIVE_MASK 0x80000000
3920#define CP_HQD_QUANTUM__QUANTUM_ACTIVE__SHIFT 0x1f
3921#define CP_HQD_PQ_BASE__ADDR_MASK 0xffffffff
3922#define CP_HQD_PQ_BASE__ADDR__SHIFT 0x0
3923#define CP_HQD_PQ_BASE_HI__ADDR_HI_MASK 0xff
3924#define CP_HQD_PQ_BASE_HI__ADDR_HI__SHIFT 0x0
3925#define CP_HQD_PQ_RPTR__CONSUMED_OFFSET_MASK 0xffffffff
3926#define CP_HQD_PQ_RPTR__CONSUMED_OFFSET__SHIFT 0x0
3927#define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR_MASK 0xfffffffc
3928#define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR__SHIFT 0x2
3929#define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI_MASK 0xffff
3930#define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI__SHIFT 0x0
3931#define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR_MASK 0xfffffffc
3932#define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR__SHIFT 0x2
3933#define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI_MASK 0xffff
3934#define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI__SHIFT 0x0
3935#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE_MASK 0x1
3936#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE__SHIFT 0x0
3937#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP_MASK 0x2
3938#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT 0x1
3939#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x7ffffc
3940#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x2
3941#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_CARRY_BITS_MASK 0x3800000
3942#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_CARRY_BITS__SHIFT 0x17
3943#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE_MASK 0x10000000
3944#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE__SHIFT 0x1c
3945#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT_MASK 0x20000000
3946#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT__SHIFT 0x1d
3947#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK 0x40000000
3948#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN__SHIFT 0x1e
3949#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT_MASK 0x80000000
3950#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT 0x1f
3951#define CP_HQD_PQ_WPTR__OFFSET_MASK 0xffffffff
3952#define CP_HQD_PQ_WPTR__OFFSET__SHIFT 0x0
3953#define CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK 0x3f
3954#define CP_HQD_PQ_CONTROL__QUEUE_SIZE__SHIFT 0x0
3955#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK 0x3f00
3956#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT 0x8
3957#define CP_HQD_PQ_CONTROL__MTYPE_MASK 0x18000
3958#define CP_HQD_PQ_CONTROL__MTYPE__SHIFT 0xf
3959#define CP_HQD_PQ_CONTROL__ENDIAN_SWAP_MASK 0x60000
3960#define CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT 0x11
3961#define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE_MASK 0x300000
3962#define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE__SHIFT 0x14
3963#define CP_HQD_PQ_CONTROL__PQ_ATC_MASK 0x800000
3964#define CP_HQD_PQ_CONTROL__PQ_ATC__SHIFT 0x17
3965#define CP_HQD_PQ_CONTROL__CACHE_POLICY_MASK 0x1000000
3966#define CP_HQD_PQ_CONTROL__CACHE_POLICY__SHIFT 0x18
3967#define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR_MASK 0x6000000
3968#define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT 0x19
3969#define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK 0x8000000
3970#define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR__SHIFT 0x1b
3971#define CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK 0x10000000
3972#define CP_HQD_PQ_CONTROL__UNORD_DISPATCH__SHIFT 0x1c
3973#define CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP_MASK 0x20000000
3974#define CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP__SHIFT 0x1d
3975#define CP_HQD_PQ_CONTROL__PRIV_STATE_MASK 0x40000000
3976#define CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT 0x1e
3977#define CP_HQD_PQ_CONTROL__KMD_QUEUE_MASK 0x80000000
3978#define CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT 0x1f
3979#define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR_MASK 0xfffffffc
3980#define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR__SHIFT 0x2
3981#define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI_MASK 0xffff
3982#define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI__SHIFT 0x0
3983#define CP_HQD_IB_RPTR__CONSUMED_OFFSET_MASK 0xfffff
3984#define CP_HQD_IB_RPTR__CONSUMED_OFFSET__SHIFT 0x0
3985#define CP_HQD_IB_CONTROL__IB_SIZE_MASK 0xfffff
3986#define CP_HQD_IB_CONTROL__IB_SIZE__SHIFT 0x0
3987#define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE_MASK 0x300000
3988#define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT 0x14
3989#define CP_HQD_IB_CONTROL__IB_ATC_MASK 0x800000
3990#define CP_HQD_IB_CONTROL__IB_ATC__SHIFT 0x17
3991#define CP_HQD_IB_CONTROL__IB_CACHE_POLICY_MASK 0x1000000
3992#define CP_HQD_IB_CONTROL__IB_CACHE_POLICY__SHIFT 0x18
3993#define CP_HQD_IB_CONTROL__MTYPE_MASK 0x18000000
3994#define CP_HQD_IB_CONTROL__MTYPE__SHIFT 0x1b
3995#define CP_HQD_IB_CONTROL__PROCESSING_IB_MASK 0x80000000
3996#define CP_HQD_IB_CONTROL__PROCESSING_IB__SHIFT 0x1f
3997#define CP_HQD_IQ_TIMER__WAIT_TIME_MASK 0xff
3998#define CP_HQD_IQ_TIMER__WAIT_TIME__SHIFT 0x0
3999#define CP_HQD_IQ_TIMER__RETRY_TYPE_MASK 0x700
4000#define CP_HQD_IQ_TIMER__RETRY_TYPE__SHIFT 0x8
4001#define CP_HQD_IQ_TIMER__IMMEDIATE_EXPIRE_MASK 0x800
4002#define CP_HQD_IQ_TIMER__IMMEDIATE_EXPIRE__SHIFT 0xb
4003#define CP_HQD_IQ_TIMER__INTERRUPT_TYPE_MASK 0x3000
4004#define CP_HQD_IQ_TIMER__INTERRUPT_TYPE__SHIFT 0xc
4005#define CP_HQD_IQ_TIMER__CLOCK_COUNT_MASK 0xc000
4006#define CP_HQD_IQ_TIMER__CLOCK_COUNT__SHIFT 0xe
4007#define CP_HQD_IQ_TIMER__INTERRUPT_SIZE_MASK 0x3f0000
4008#define CP_HQD_IQ_TIMER__INTERRUPT_SIZE__SHIFT 0x10
4009#define CP_HQD_IQ_TIMER__QUANTUM_TIMER_MASK 0x400000
4010#define CP_HQD_IQ_TIMER__QUANTUM_TIMER__SHIFT 0x16
4011#define CP_HQD_IQ_TIMER__IQ_ATC_MASK 0x800000
4012#define CP_HQD_IQ_TIMER__IQ_ATC__SHIFT 0x17
4013#define CP_HQD_IQ_TIMER__CACHE_POLICY_MASK 0x1000000
4014#define CP_HQD_IQ_TIMER__CACHE_POLICY__SHIFT 0x18
4015#define CP_HQD_IQ_TIMER__MTYPE_MASK 0x18000000
4016#define CP_HQD_IQ_TIMER__MTYPE__SHIFT 0x1b
4017#define CP_HQD_IQ_TIMER__PROCESS_IQ_EN_MASK 0x20000000
4018#define CP_HQD_IQ_TIMER__PROCESS_IQ_EN__SHIFT 0x1d
4019#define CP_HQD_IQ_TIMER__PROCESSING_IQ_MASK 0x40000000
4020#define CP_HQD_IQ_TIMER__PROCESSING_IQ__SHIFT 0x1e
4021#define CP_HQD_IQ_TIMER__ACTIVE_MASK 0x80000000
4022#define CP_HQD_IQ_TIMER__ACTIVE__SHIFT 0x1f
4023#define CP_HQD_IQ_RPTR__OFFSET_MASK 0x3f
4024#define CP_HQD_IQ_RPTR__OFFSET__SHIFT 0x0
4025#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_MASK 0x7
4026#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ__SHIFT 0x0
4027#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK 0x10
4028#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND__SHIFT 0x4
4029#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT_MASK 0x100
4030#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT__SHIFT 0x8
4031#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN_MASK 0x200
4032#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN__SHIFT 0x9
4033#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN_MASK 0x400
4034#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN__SHIFT 0xa
4035#define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD_MASK 0x1
4036#define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD__SHIFT 0x0
4037#define CP_HQD_OFFLOAD__DMA_OFFLOAD_MASK 0x1
4038#define CP_HQD_OFFLOAD__DMA_OFFLOAD__SHIFT 0x0
4039#define CP_HQD_OFFLOAD__DMA_OFFLOAD_EN_MASK 0x2
4040#define CP_HQD_OFFLOAD__DMA_OFFLOAD_EN__SHIFT 0x1
4041#define CP_HQD_OFFLOAD__EOP_OFFLOAD_MASK 0x10
4042#define CP_HQD_OFFLOAD__EOP_OFFLOAD__SHIFT 0x4
4043#define CP_HQD_OFFLOAD__EOP_OFFLOAD_EN_MASK 0x20
4044#define CP_HQD_OFFLOAD__EOP_OFFLOAD_EN__SHIFT 0x5
4045#define CP_HQD_SEMA_CMD__RETRY_MASK 0x1
4046#define CP_HQD_SEMA_CMD__RETRY__SHIFT 0x0
4047#define CP_HQD_SEMA_CMD__RESULT_MASK 0x6
4048#define CP_HQD_SEMA_CMD__RESULT__SHIFT 0x1
4049#define CP_HQD_MSG_TYPE__ACTION_MASK 0x7
4050#define CP_HQD_MSG_TYPE__ACTION__SHIFT 0x0
4051#define CP_HQD_MSG_TYPE__SAVE_STATE_MASK 0x70
4052#define CP_HQD_MSG_TYPE__SAVE_STATE__SHIFT 0x4
4053#define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO_MASK 0xffffffff
4054#define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO__SHIFT 0x0
4055#define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI_MASK 0xffffffff
4056#define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI__SHIFT 0x0
4057#define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO_MASK 0xffffffff
4058#define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO__SHIFT 0x0
4059#define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI_MASK 0xffffffff
4060#define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI__SHIFT 0x0
4061#define CP_HQD_HQ_SCHEDULER0__SCHEDULER_MASK 0xffffffff
4062#define CP_HQD_HQ_SCHEDULER0__SCHEDULER__SHIFT 0x0
4063#define CP_HQD_HQ_STATUS0__DEQUEUE_STATUS_MASK 0x3
4064#define CP_HQD_HQ_STATUS0__DEQUEUE_STATUS__SHIFT 0x0
4065#define CP_HQD_HQ_STATUS0__DEQUEUE_RETRY_CNT_MASK 0xc
4066#define CP_HQD_HQ_STATUS0__DEQUEUE_RETRY_CNT__SHIFT 0x2
4067#define CP_HQD_HQ_STATUS0__RSV_6_4_MASK 0x70
4068#define CP_HQD_HQ_STATUS0__RSV_6_4__SHIFT 0x4
4069#define CP_HQD_HQ_STATUS0__SCRATCH_RAM_INIT_MASK 0x80
4070#define CP_HQD_HQ_STATUS0__SCRATCH_RAM_INIT__SHIFT 0x7
4071#define CP_HQD_HQ_STATUS0__TCL2_DIRTY_MASK 0x100
4072#define CP_HQD_HQ_STATUS0__TCL2_DIRTY__SHIFT 0x8
4073#define CP_HQD_HQ_STATUS0__PG_ACTIVATED_MASK 0x200
4074#define CP_HQD_HQ_STATUS0__PG_ACTIVATED__SHIFT 0x9
4075#define CP_HQD_HQ_STATUS0__RSVR_31_10_MASK 0xfffffc00
4076#define CP_HQD_HQ_STATUS0__RSVR_31_10__SHIFT 0xa
4077#define CP_HQD_HQ_SCHEDULER1__SCHEDULER_MASK 0xffffffff
4078#define CP_HQD_HQ_SCHEDULER1__SCHEDULER__SHIFT 0x0
4079#define CP_HQD_HQ_CONTROL0__CONTROL_MASK 0xffffffff
4080#define CP_HQD_HQ_CONTROL0__CONTROL__SHIFT 0x0
4081#define CP_MQD_CONTROL__VMID_MASK 0xf
4082#define CP_MQD_CONTROL__VMID__SHIFT 0x0
4083#define CP_MQD_CONTROL__PROCESSING_MQD_MASK 0x1000
4084#define CP_MQD_CONTROL__PROCESSING_MQD__SHIFT 0xc
4085#define CP_MQD_CONTROL__PROCESSING_MQD_EN_MASK 0x2000
4086#define CP_MQD_CONTROL__PROCESSING_MQD_EN__SHIFT 0xd
4087#define CP_MQD_CONTROL__MQD_ATC_MASK 0x800000
4088#define CP_MQD_CONTROL__MQD_ATC__SHIFT 0x17
4089#define CP_MQD_CONTROL__CACHE_POLICY_MASK 0x1000000
4090#define CP_MQD_CONTROL__CACHE_POLICY__SHIFT 0x18
4091#define CP_MQD_CONTROL__MTYPE_MASK 0x18000000
4092#define CP_MQD_CONTROL__MTYPE__SHIFT 0x1b
4093#define CP_HQD_HQ_STATUS1__STATUS_MASK 0xffffffff
4094#define CP_HQD_HQ_STATUS1__STATUS__SHIFT 0x0
4095#define CP_HQD_HQ_CONTROL1__CONTROL_MASK 0xffffffff
4096#define CP_HQD_HQ_CONTROL1__CONTROL__SHIFT 0x0
4097#define CP_HQD_EOP_BASE_ADDR__BASE_ADDR_MASK 0xffffffff
4098#define CP_HQD_EOP_BASE_ADDR__BASE_ADDR__SHIFT 0x0
4099#define CP_HQD_EOP_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0xff
4100#define CP_HQD_EOP_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0
4101#define CP_HQD_EOP_CONTROL__EOP_SIZE_MASK 0x3f
4102#define CP_HQD_EOP_CONTROL__EOP_SIZE__SHIFT 0x0
4103#define CP_HQD_EOP_CONTROL__PROCESSING_EOP_MASK 0x100
4104#define CP_HQD_EOP_CONTROL__PROCESSING_EOP__SHIFT 0x8
4105#define CP_HQD_EOP_CONTROL__PROCESS_EOP_EN_MASK 0x1000
4106#define CP_HQD_EOP_CONTROL__PROCESS_EOP_EN__SHIFT 0xc
4107#define CP_HQD_EOP_CONTROL__PROCESSING_EOPIB_MASK 0x2000
4108#define CP_HQD_EOP_CONTROL__PROCESSING_EOPIB__SHIFT 0xd
4109#define CP_HQD_EOP_CONTROL__PROCESS_EOPIB_EN_MASK 0x4000
4110#define CP_HQD_EOP_CONTROL__PROCESS_EOPIB_EN__SHIFT 0xe
4111#define CP_HQD_EOP_CONTROL__MTYPE_MASK 0x18000
4112#define CP_HQD_EOP_CONTROL__MTYPE__SHIFT 0xf
4113#define CP_HQD_EOP_CONTROL__EOP_ATC_MASK 0x800000
4114#define CP_HQD_EOP_CONTROL__EOP_ATC__SHIFT 0x17
4115#define CP_HQD_EOP_CONTROL__CACHE_POLICY_MASK 0x1000000
4116#define CP_HQD_EOP_CONTROL__CACHE_POLICY__SHIFT 0x18
4117#define CP_HQD_EOP_CONTROL__SIG_SEM_RESULT_MASK 0x60000000
4118#define CP_HQD_EOP_CONTROL__SIG_SEM_RESULT__SHIFT 0x1d
4119#define CP_HQD_EOP_CONTROL__PEND_SIG_SEM_MASK 0x80000000
4120#define CP_HQD_EOP_CONTROL__PEND_SIG_SEM__SHIFT 0x1f
4121#define CP_HQD_EOP_RPTR__RPTR_MASK 0x1fff
4122#define CP_HQD_EOP_RPTR__RPTR__SHIFT 0x0
4123#define CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR_MASK 0x40000000
4124#define CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR__SHIFT 0x1e
4125#define CP_HQD_EOP_RPTR__INIT_FETCHER_MASK 0x80000000
4126#define CP_HQD_EOP_RPTR__INIT_FETCHER__SHIFT 0x1f
4127#define CP_HQD_EOP_WPTR__WPTR_MASK 0x1fff
4128#define CP_HQD_EOP_WPTR__WPTR__SHIFT 0x0
4129#define CP_HQD_EOP_WPTR__EOP_AVAIL_MASK 0x1fff0000
4130#define CP_HQD_EOP_WPTR__EOP_AVAIL__SHIFT 0x10
4131#define CP_HQD_EOP_EVENTS__EVENT_COUNT_MASK 0xfff
4132#define CP_HQD_EOP_EVENTS__EVENT_COUNT__SHIFT 0x0
4133#define CP_HQD_EOP_EVENTS__CS_PARTIAL_FLUSH_PEND_MASK 0x10000
4134#define CP_HQD_EOP_EVENTS__CS_PARTIAL_FLUSH_PEND__SHIFT 0x10
4135#define CP_HQD_CTX_SAVE_BASE_ADDR_LO__ADDR_MASK 0xfffff000
4136#define CP_HQD_CTX_SAVE_BASE_ADDR_LO__ADDR__SHIFT 0xc
4137#define CP_HQD_CTX_SAVE_BASE_ADDR_HI__ADDR_HI_MASK 0xffff
4138#define CP_HQD_CTX_SAVE_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0
4139#define CP_HQD_CTX_SAVE_CONTROL__ATC_MASK 0x1
4140#define CP_HQD_CTX_SAVE_CONTROL__ATC__SHIFT 0x0
4141#define CP_HQD_CTX_SAVE_CONTROL__MTYPE_MASK 0x6
4142#define CP_HQD_CTX_SAVE_CONTROL__MTYPE__SHIFT 0x1
4143#define CP_HQD_CTX_SAVE_CONTROL__POLICY_MASK 0x8
4144#define CP_HQD_CTX_SAVE_CONTROL__POLICY__SHIFT 0x3
4145#define CP_HQD_CNTL_STACK_OFFSET__OFFSET_MASK 0x7ffc
4146#define CP_HQD_CNTL_STACK_OFFSET__OFFSET__SHIFT 0x2
4147#define CP_HQD_CNTL_STACK_SIZE__SIZE_MASK 0x7000
4148#define CP_HQD_CNTL_STACK_SIZE__SIZE__SHIFT 0xc
4149#define CP_HQD_WG_STATE_OFFSET__OFFSET_MASK 0x1fffffc
4150#define CP_HQD_WG_STATE_OFFSET__OFFSET__SHIFT 0x2
4151#define CP_HQD_CTX_SAVE_SIZE__SIZE_MASK 0x1fff000
4152#define CP_HQD_CTX_SAVE_SIZE__SIZE__SHIFT 0xc
4153#define CP_HQD_GDS_RESOURCE_STATE__OA_REQUIRED_MASK 0x1
4154#define CP_HQD_GDS_RESOURCE_STATE__OA_REQUIRED__SHIFT 0x0
4155#define CP_HQD_GDS_RESOURCE_STATE__OA_ACQUIRED_MASK 0x2
4156#define CP_HQD_GDS_RESOURCE_STATE__OA_ACQUIRED__SHIFT 0x1
4157#define CP_HQD_GDS_RESOURCE_STATE__GWS_SIZE_MASK 0x3f0
4158#define CP_HQD_GDS_RESOURCE_STATE__GWS_SIZE__SHIFT 0x4
4159#define CP_HQD_GDS_RESOURCE_STATE__GWS_PNTR_MASK 0x3f000
4160#define CP_HQD_GDS_RESOURCE_STATE__GWS_PNTR__SHIFT 0xc
4161#define CP_HQD_ERROR__EDC_ERROR_ID_MASK 0xf
4162#define CP_HQD_ERROR__EDC_ERROR_ID__SHIFT 0x0
4163#define CP_HQD_ERROR__SUA_ERROR_MASK 0x10
4164#define CP_HQD_ERROR__SUA_ERROR__SHIFT 0x4
4165#define CP_HQD_EOP_WPTR_MEM__WPTR_MASK 0x1fff
4166#define CP_HQD_EOP_WPTR_MEM__WPTR__SHIFT 0x0
4167#define CP_HQD_EOP_DONES__DONE_COUNT_MASK 0xffffffff
4168#define CP_HQD_EOP_DONES__DONE_COUNT__SHIFT 0x0
4169#define DB_Z_READ_BASE__BASE_256B_MASK 0xffffffff
4170#define DB_Z_READ_BASE__BASE_256B__SHIFT 0x0
4171#define DB_STENCIL_READ_BASE__BASE_256B_MASK 0xffffffff
4172#define DB_STENCIL_READ_BASE__BASE_256B__SHIFT 0x0
4173#define DB_Z_WRITE_BASE__BASE_256B_MASK 0xffffffff
4174#define DB_Z_WRITE_BASE__BASE_256B__SHIFT 0x0
4175#define DB_STENCIL_WRITE_BASE__BASE_256B_MASK 0xffffffff
4176#define DB_STENCIL_WRITE_BASE__BASE_256B__SHIFT 0x0
4177#define DB_DEPTH_INFO__ADDR5_SWIZZLE_MASK_MASK 0xf
4178#define DB_DEPTH_INFO__ADDR5_SWIZZLE_MASK__SHIFT 0x0
4179#define DB_DEPTH_INFO__ARRAY_MODE_MASK 0xf0
4180#define DB_DEPTH_INFO__ARRAY_MODE__SHIFT 0x4
4181#define DB_DEPTH_INFO__PIPE_CONFIG_MASK 0x1f00
4182#define DB_DEPTH_INFO__PIPE_CONFIG__SHIFT 0x8
4183#define DB_DEPTH_INFO__BANK_WIDTH_MASK 0x6000
4184#define DB_DEPTH_INFO__BANK_WIDTH__SHIFT 0xd
4185#define DB_DEPTH_INFO__BANK_HEIGHT_MASK 0x18000
4186#define DB_DEPTH_INFO__BANK_HEIGHT__SHIFT 0xf
4187#define DB_DEPTH_INFO__MACRO_TILE_ASPECT_MASK 0x60000
4188#define DB_DEPTH_INFO__MACRO_TILE_ASPECT__SHIFT 0x11
4189#define DB_DEPTH_INFO__NUM_BANKS_MASK 0x180000
4190#define DB_DEPTH_INFO__NUM_BANKS__SHIFT 0x13
4191#define DB_Z_INFO__FORMAT_MASK 0x3
4192#define DB_Z_INFO__FORMAT__SHIFT 0x0
4193#define DB_Z_INFO__NUM_SAMPLES_MASK 0xc
4194#define DB_Z_INFO__NUM_SAMPLES__SHIFT 0x2
4195#define DB_Z_INFO__TILE_SPLIT_MASK 0xe000
4196#define DB_Z_INFO__TILE_SPLIT__SHIFT 0xd
4197#define DB_Z_INFO__TILE_MODE_INDEX_MASK 0x700000
4198#define DB_Z_INFO__TILE_MODE_INDEX__SHIFT 0x14
4199#define DB_Z_INFO__DECOMPRESS_ON_N_ZPLANES_MASK 0x7800000
4200#define DB_Z_INFO__DECOMPRESS_ON_N_ZPLANES__SHIFT 0x17
4201#define DB_Z_INFO__ALLOW_EXPCLEAR_MASK 0x8000000
4202#define DB_Z_INFO__ALLOW_EXPCLEAR__SHIFT 0x1b
4203#define DB_Z_INFO__READ_SIZE_MASK 0x10000000
4204#define DB_Z_INFO__READ_SIZE__SHIFT 0x1c
4205#define DB_Z_INFO__TILE_SURFACE_ENABLE_MASK 0x20000000
4206#define DB_Z_INFO__TILE_SURFACE_ENABLE__SHIFT 0x1d
4207#define DB_Z_INFO__CLEAR_DISALLOWED_MASK 0x40000000
4208#define DB_Z_INFO__CLEAR_DISALLOWED__SHIFT 0x1e
4209#define DB_Z_INFO__ZRANGE_PRECISION_MASK 0x80000000
4210#define DB_Z_INFO__ZRANGE_PRECISION__SHIFT 0x1f
4211#define DB_STENCIL_INFO__FORMAT_MASK 0x1
4212#define DB_STENCIL_INFO__FORMAT__SHIFT 0x0
4213#define DB_STENCIL_INFO__TILE_SPLIT_MASK 0xe000
4214#define DB_STENCIL_INFO__TILE_SPLIT__SHIFT 0xd
4215#define DB_STENCIL_INFO__TILE_MODE_INDEX_MASK 0x700000
4216#define DB_STENCIL_INFO__TILE_MODE_INDEX__SHIFT 0x14
4217#define DB_STENCIL_INFO__ALLOW_EXPCLEAR_MASK 0x8000000
4218#define DB_STENCIL_INFO__ALLOW_EXPCLEAR__SHIFT 0x1b
4219#define DB_STENCIL_INFO__TILE_STENCIL_DISABLE_MASK 0x20000000
4220#define DB_STENCIL_INFO__TILE_STENCIL_DISABLE__SHIFT 0x1d
4221#define DB_STENCIL_INFO__CLEAR_DISALLOWED_MASK 0x40000000
4222#define DB_STENCIL_INFO__CLEAR_DISALLOWED__SHIFT 0x1e
4223#define DB_DEPTH_SIZE__PITCH_TILE_MAX_MASK 0x7ff
4224#define DB_DEPTH_SIZE__PITCH_TILE_MAX__SHIFT 0x0
4225#define DB_DEPTH_SIZE__HEIGHT_TILE_MAX_MASK 0x3ff800
4226#define DB_DEPTH_SIZE__HEIGHT_TILE_MAX__SHIFT 0xb
4227#define DB_DEPTH_SLICE__SLICE_TILE_MAX_MASK 0x3fffff
4228#define DB_DEPTH_SLICE__SLICE_TILE_MAX__SHIFT 0x0
4229#define DB_DEPTH_VIEW__SLICE_START_MASK 0x7ff
4230#define DB_DEPTH_VIEW__SLICE_START__SHIFT 0x0
4231#define DB_DEPTH_VIEW__SLICE_MAX_MASK 0xffe000
4232#define DB_DEPTH_VIEW__SLICE_MAX__SHIFT 0xd
4233#define DB_DEPTH_VIEW__Z_READ_ONLY_MASK 0x1000000
4234#define DB_DEPTH_VIEW__Z_READ_ONLY__SHIFT 0x18
4235#define DB_DEPTH_VIEW__STENCIL_READ_ONLY_MASK 0x2000000
4236#define DB_DEPTH_VIEW__STENCIL_READ_ONLY__SHIFT 0x19
4237#define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE_MASK 0x1
4238#define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE__SHIFT 0x0
4239#define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE_MASK 0x2
4240#define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE__SHIFT 0x1
4241#define DB_RENDER_CONTROL__DEPTH_COPY_MASK 0x4
4242#define DB_RENDER_CONTROL__DEPTH_COPY__SHIFT 0x2
4243#define DB_RENDER_CONTROL__STENCIL_COPY_MASK 0x8
4244#define DB_RENDER_CONTROL__STENCIL_COPY__SHIFT 0x3
4245#define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE_MASK 0x10
4246#define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE__SHIFT 0x4
4247#define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE_MASK 0x20
4248#define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE__SHIFT 0x5
4249#define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE_MASK 0x40
4250#define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE__SHIFT 0x6
4251#define DB_RENDER_CONTROL__COPY_CENTROID_MASK 0x80
4252#define DB_RENDER_CONTROL__COPY_CENTROID__SHIFT 0x7
4253#define DB_RENDER_CONTROL__COPY_SAMPLE_MASK 0xf00
4254#define DB_RENDER_CONTROL__COPY_SAMPLE__SHIFT 0x8
4255#define DB_RENDER_CONTROL__DECOMPRESS_ENABLE_MASK 0x1000
4256#define DB_RENDER_CONTROL__DECOMPRESS_ENABLE__SHIFT 0xc
4257#define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE_MASK 0x1
4258#define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE__SHIFT 0x0
4259#define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS_MASK 0x2
4260#define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS__SHIFT 0x1
4261#define DB_COUNT_CONTROL__SAMPLE_RATE_MASK 0x70
4262#define DB_COUNT_CONTROL__SAMPLE_RATE__SHIFT 0x4
4263#define DB_COUNT_CONTROL__ZPASS_ENABLE_MASK 0xf00
4264#define DB_COUNT_CONTROL__ZPASS_ENABLE__SHIFT 0x8
4265#define DB_COUNT_CONTROL__ZFAIL_ENABLE_MASK 0xf000
4266#define DB_COUNT_CONTROL__ZFAIL_ENABLE__SHIFT 0xc
4267#define DB_COUNT_CONTROL__SFAIL_ENABLE_MASK 0xf0000
4268#define DB_COUNT_CONTROL__SFAIL_ENABLE__SHIFT 0x10
4269#define DB_COUNT_CONTROL__DBFAIL_ENABLE_MASK 0xf00000
4270#define DB_COUNT_CONTROL__DBFAIL_ENABLE__SHIFT 0x14
4271#define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE_MASK 0xf000000
4272#define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE__SHIFT 0x18
4273#define DB_COUNT_CONTROL__SLICE_ODD_ENABLE_MASK 0xf0000000
4274#define DB_COUNT_CONTROL__SLICE_ODD_ENABLE__SHIFT 0x1c
4275#define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE_MASK 0x3
4276#define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE__SHIFT 0x0
4277#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0_MASK 0xc
4278#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0__SHIFT 0x2
4279#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1_MASK 0x30
4280#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1__SHIFT 0x4
4281#define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER_MASK 0x40
4282#define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER__SHIFT 0x6
4283#define DB_RENDER_OVERRIDE__FAST_Z_DISABLE_MASK 0x80
4284#define DB_RENDER_OVERRIDE__FAST_Z_DISABLE__SHIFT 0x7
4285#define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE_MASK 0x100
4286#define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE__SHIFT 0x8
4287#define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE_MASK 0x200
4288#define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE__SHIFT 0x9
4289#define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL_MASK 0x400
4290#define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL__SHIFT 0xa
4291#define DB_RENDER_OVERRIDE__FORCE_Z_READ_MASK 0x800
4292#define DB_RENDER_OVERRIDE__FORCE_Z_READ__SHIFT 0xb
4293#define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ_MASK 0x1000
4294#define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ__SHIFT 0xc
4295#define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE_MASK 0x6000
4296#define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE__SHIFT 0xd
4297#define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT_MASK 0x8000
4298#define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT__SHIFT 0xf
4299#define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP_MASK 0x10000
4300#define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP__SHIFT 0x10
4301#define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE_MASK 0x20000
4302#define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE__SHIFT 0x11
4303#define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED_MASK 0x40000
4304#define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED__SHIFT 0x12
4305#define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM_MASK 0x180000
4306#define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM__SHIFT 0x13
4307#define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT_MASK 0x3e00000
4308#define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT__SHIFT 0x15
4309#define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES_MASK 0x4000000
4310#define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES__SHIFT 0x1a
4311#define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY_MASK 0x8000000
4312#define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY__SHIFT 0x1b
4313#define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY_MASK 0x10000000
4314#define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY__SHIFT 0x1c
4315#define DB_RENDER_OVERRIDE__FORCE_Z_VALID_MASK 0x20000000
4316#define DB_RENDER_OVERRIDE__FORCE_Z_VALID__SHIFT 0x1d
4317#define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID_MASK 0x40000000
4318#define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID__SHIFT 0x1e
4319#define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION_MASK 0x80000000
4320#define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION__SHIFT 0x1f
4321#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL_MASK 0x3
4322#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL__SHIFT 0x0
4323#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN_MASK 0x1c
4324#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN__SHIFT 0x2
4325#define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION_MASK 0x20
4326#define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION__SHIFT 0x5
4327#define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION_MASK 0x40
4328#define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION__SHIFT 0x6
4329#define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION_MASK 0x80
4330#define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION__SHIFT 0x7
4331#define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH_MASK 0x100
4332#define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH__SHIFT 0x8
4333#define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP_MASK 0x200
4334#define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP__SHIFT 0x9
4335#define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE_MASK 0x400
4336#define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE__SHIFT 0xa
4337#define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE_MASK 0x800
4338#define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE__SHIFT 0xb
4339#define DB_RENDER_OVERRIDE2__HIZ_ZFUNC_MASK 0x7000
4340#define DB_RENDER_OVERRIDE2__HIZ_ZFUNC__SHIFT 0xc
4341#define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF_MASK 0x38000
4342#define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF__SHIFT 0xf
4343#define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF_MASK 0x1c0000
4344#define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF__SHIFT 0x12
4345#define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE_MASK 0x200000
4346#define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE__SHIFT 0x15
4347#define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS_MASK 0x400000
4348#define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS__SHIFT 0x16
4349#define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS_MASK 0x800000
4350#define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS__SHIFT 0x17
4351#define DB_EQAA__MAX_ANCHOR_SAMPLES_MASK 0x7
4352#define DB_EQAA__MAX_ANCHOR_SAMPLES__SHIFT 0x0
4353#define DB_EQAA__PS_ITER_SAMPLES_MASK 0x70
4354#define DB_EQAA__PS_ITER_SAMPLES__SHIFT 0x4
4355#define DB_EQAA__MASK_EXPORT_NUM_SAMPLES_MASK 0x700
4356#define DB_EQAA__MASK_EXPORT_NUM_SAMPLES__SHIFT 0x8
4357#define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES_MASK 0x7000
4358#define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES__SHIFT 0xc
4359#define DB_EQAA__HIGH_QUALITY_INTERSECTIONS_MASK 0x10000
4360#define DB_EQAA__HIGH_QUALITY_INTERSECTIONS__SHIFT 0x10
4361#define DB_EQAA__INCOHERENT_EQAA_READS_MASK 0x20000
4362#define DB_EQAA__INCOHERENT_EQAA_READS__SHIFT 0x11
4363#define DB_EQAA__INTERPOLATE_COMP_Z_MASK 0x40000
4364#define DB_EQAA__INTERPOLATE_COMP_Z__SHIFT 0x12
4365#define DB_EQAA__INTERPOLATE_SRC_Z_MASK 0x80000
4366#define DB_EQAA__INTERPOLATE_SRC_Z__SHIFT 0x13
4367#define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS_MASK 0x100000
4368#define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS__SHIFT 0x14
4369#define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE_MASK 0x200000
4370#define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE__SHIFT 0x15
4371#define DB_EQAA__OVERRASTERIZATION_AMOUNT_MASK 0x7000000
4372#define DB_EQAA__OVERRASTERIZATION_AMOUNT__SHIFT 0x18
4373#define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION_MASK 0x8000000
4374#define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION__SHIFT 0x1b
4375#define DB_SHADER_CONTROL__Z_EXPORT_ENABLE_MASK 0x1
4376#define DB_SHADER_CONTROL__Z_EXPORT_ENABLE__SHIFT 0x0
4377#define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE_MASK 0x2
4378#define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE__SHIFT 0x1
4379#define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE_MASK 0x4
4380#define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE__SHIFT 0x2
4381#define DB_SHADER_CONTROL__Z_ORDER_MASK 0x30
4382#define DB_SHADER_CONTROL__Z_ORDER__SHIFT 0x4
4383#define DB_SHADER_CONTROL__KILL_ENABLE_MASK 0x40
4384#define DB_SHADER_CONTROL__KILL_ENABLE__SHIFT 0x6
4385#define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE_MASK 0x80
4386#define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE__SHIFT 0x7
4387#define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE_MASK 0x100
4388#define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE__SHIFT 0x8
4389#define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL_MASK 0x200
4390#define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL__SHIFT 0x9
4391#define DB_SHADER_CONTROL__EXEC_ON_NOOP_MASK 0x400
4392#define DB_SHADER_CONTROL__EXEC_ON_NOOP__SHIFT 0xa
4393#define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE_MASK 0x800
4394#define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE__SHIFT 0xb
4395#define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER_MASK 0x1000
4396#define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER__SHIFT 0xc
4397#define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT_MASK 0x6000
4398#define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT__SHIFT 0xd
4399#define DB_DEPTH_BOUNDS_MIN__MIN_MASK 0xffffffff
4400#define DB_DEPTH_BOUNDS_MIN__MIN__SHIFT 0x0
4401#define DB_DEPTH_BOUNDS_MAX__MAX_MASK 0xffffffff
4402#define DB_DEPTH_BOUNDS_MAX__MAX__SHIFT 0x0
4403#define DB_STENCIL_CLEAR__CLEAR_MASK 0xff
4404#define DB_STENCIL_CLEAR__CLEAR__SHIFT 0x0
4405#define DB_DEPTH_CLEAR__DEPTH_CLEAR_MASK 0xffffffff
4406#define DB_DEPTH_CLEAR__DEPTH_CLEAR__SHIFT 0x0
4407#define DB_HTILE_DATA_BASE__BASE_256B_MASK 0xffffffff
4408#define DB_HTILE_DATA_BASE__BASE_256B__SHIFT 0x0
4409#define DB_HTILE_SURFACE__LINEAR_MASK 0x1
4410#define DB_HTILE_SURFACE__LINEAR__SHIFT 0x0
4411#define DB_HTILE_SURFACE__FULL_CACHE_MASK 0x2
4412#define DB_HTILE_SURFACE__FULL_CACHE__SHIFT 0x1
4413#define DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN_MASK 0x4
4414#define DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN__SHIFT 0x2
4415#define DB_HTILE_SURFACE__PRELOAD_MASK 0x8
4416#define DB_HTILE_SURFACE__PRELOAD__SHIFT 0x3
4417#define DB_HTILE_SURFACE__PREFETCH_WIDTH_MASK 0x3f0
4418#define DB_HTILE_SURFACE__PREFETCH_WIDTH__SHIFT 0x4
4419#define DB_HTILE_SURFACE__PREFETCH_HEIGHT_MASK 0xfc00
4420#define DB_HTILE_SURFACE__PREFETCH_HEIGHT__SHIFT 0xa
4421#define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE_MASK 0x10000
4422#define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE__SHIFT 0x10
4423#define DB_HTILE_SURFACE__TC_COMPATIBLE_MASK 0x20000
4424#define DB_HTILE_SURFACE__TC_COMPATIBLE__SHIFT 0x11
4425#define DB_PRELOAD_CONTROL__START_X_MASK 0xff
4426#define DB_PRELOAD_CONTROL__START_X__SHIFT 0x0
4427#define DB_PRELOAD_CONTROL__START_Y_MASK 0xff00
4428#define DB_PRELOAD_CONTROL__START_Y__SHIFT 0x8
4429#define DB_PRELOAD_CONTROL__MAX_X_MASK 0xff0000
4430#define DB_PRELOAD_CONTROL__MAX_X__SHIFT 0x10
4431#define DB_PRELOAD_CONTROL__MAX_Y_MASK 0xff000000
4432#define DB_PRELOAD_CONTROL__MAX_Y__SHIFT 0x18
4433#define DB_STENCILREFMASK__STENCILTESTVAL_MASK 0xff
4434#define DB_STENCILREFMASK__STENCILTESTVAL__SHIFT 0x0
4435#define DB_STENCILREFMASK__STENCILMASK_MASK 0xff00
4436#define DB_STENCILREFMASK__STENCILMASK__SHIFT 0x8
4437#define DB_STENCILREFMASK__STENCILWRITEMASK_MASK 0xff0000
4438#define DB_STENCILREFMASK__STENCILWRITEMASK__SHIFT 0x10
4439#define DB_STENCILREFMASK__STENCILOPVAL_MASK 0xff000000
4440#define DB_STENCILREFMASK__STENCILOPVAL__SHIFT 0x18
4441#define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF_MASK 0xff
4442#define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF__SHIFT 0x0
4443#define DB_STENCILREFMASK_BF__STENCILMASK_BF_MASK 0xff00
4444#define DB_STENCILREFMASK_BF__STENCILMASK_BF__SHIFT 0x8
4445#define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF_MASK 0xff0000
4446#define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF__SHIFT 0x10
4447#define DB_STENCILREFMASK_BF__STENCILOPVAL_BF_MASK 0xff000000
4448#define DB_STENCILREFMASK_BF__STENCILOPVAL_BF__SHIFT 0x18
4449#define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0_MASK 0x7
4450#define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0__SHIFT 0x0
4451#define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0_MASK 0xff0
4452#define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0__SHIFT 0x4
4453#define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0_MASK 0xff000
4454#define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0__SHIFT 0xc
4455#define DB_SRESULTS_COMPARE_STATE0__ENABLE0_MASK 0x1000000
4456#define DB_SRESULTS_COMPARE_STATE0__ENABLE0__SHIFT 0x18
4457#define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1_MASK 0x7
4458#define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1__SHIFT 0x0
4459#define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1_MASK 0xff0
4460#define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1__SHIFT 0x4
4461#define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1_MASK 0xff000
4462#define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1__SHIFT 0xc
4463#define DB_SRESULTS_COMPARE_STATE1__ENABLE1_MASK 0x1000000
4464#define DB_SRESULTS_COMPARE_STATE1__ENABLE1__SHIFT 0x18
4465#define DB_DEPTH_CONTROL__STENCIL_ENABLE_MASK 0x1
4466#define DB_DEPTH_CONTROL__STENCIL_ENABLE__SHIFT 0x0
4467#define DB_DEPTH_CONTROL__Z_ENABLE_MASK 0x2
4468#define DB_DEPTH_CONTROL__Z_ENABLE__SHIFT 0x1
4469#define DB_DEPTH_CONTROL__Z_WRITE_ENABLE_MASK 0x4
4470#define DB_DEPTH_CONTROL__Z_WRITE_ENABLE__SHIFT 0x2
4471#define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE_MASK 0x8
4472#define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE__SHIFT 0x3
4473#define DB_DEPTH_CONTROL__ZFUNC_MASK 0x70
4474#define DB_DEPTH_CONTROL__ZFUNC__SHIFT 0x4
4475#define DB_DEPTH_CONTROL__BACKFACE_ENABLE_MASK 0x80
4476#define DB_DEPTH_CONTROL__BACKFACE_ENABLE__SHIFT 0x7
4477#define DB_DEPTH_CONTROL__STENCILFUNC_MASK 0x700
4478#define DB_DEPTH_CONTROL__STENCILFUNC__SHIFT 0x8
4479#define DB_DEPTH_CONTROL__STENCILFUNC_BF_MASK 0x700000
4480#define DB_DEPTH_CONTROL__STENCILFUNC_BF__SHIFT 0x14
4481#define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL_MASK 0x40000000
4482#define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL__SHIFT 0x1e
4483#define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS_MASK 0x80000000
4484#define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS__SHIFT 0x1f
4485#define DB_STENCIL_CONTROL__STENCILFAIL_MASK 0xf
4486#define DB_STENCIL_CONTROL__STENCILFAIL__SHIFT 0x0
4487#define DB_STENCIL_CONTROL__STENCILZPASS_MASK 0xf0
4488#define DB_STENCIL_CONTROL__STENCILZPASS__SHIFT 0x4
4489#define DB_STENCIL_CONTROL__STENCILZFAIL_MASK 0xf00
4490#define DB_STENCIL_CONTROL__STENCILZFAIL__SHIFT 0x8
4491#define DB_STENCIL_CONTROL__STENCILFAIL_BF_MASK 0xf000
4492#define DB_STENCIL_CONTROL__STENCILFAIL_BF__SHIFT 0xc
4493#define DB_STENCIL_CONTROL__STENCILZPASS_BF_MASK 0xf0000
4494#define DB_STENCIL_CONTROL__STENCILZPASS_BF__SHIFT 0x10
4495#define DB_STENCIL_CONTROL__STENCILZFAIL_BF_MASK 0xf00000
4496#define DB_STENCIL_CONTROL__STENCILZFAIL_BF__SHIFT 0x14
4497#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE_MASK 0x1
4498#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE__SHIFT 0x0
4499#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0_MASK 0x300
4500#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0__SHIFT 0x8
4501#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1_MASK 0xc00
4502#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1__SHIFT 0xa
4503#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2_MASK 0x3000
4504#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2__SHIFT 0xc
4505#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3_MASK 0xc000
4506#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3__SHIFT 0xe
4507#define DB_ALPHA_TO_MASK__OFFSET_ROUND_MASK 0x10000
4508#define DB_ALPHA_TO_MASK__OFFSET_ROUND__SHIFT 0x10
4509#define DB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff
4510#define DB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
4511#define DB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00
4512#define DB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
4513#define DB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
4514#define DB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
4515#define DB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000
4516#define DB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
4517#define DB_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
4518#define DB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
4519#define DB_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff
4520#define DB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
4521#define DB_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00
4522#define DB_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
4523#define DB_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
4524#define DB_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
4525#define DB_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000
4526#define DB_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
4527#define DB_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
4528#define DB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
4529#define DB_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff
4530#define DB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
4531#define DB_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0xffc00
4532#define DB_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa
4533#define DB_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000
4534#define DB_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
4535#define DB_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0xf000000
4536#define DB_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18
4537#define DB_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000
4538#define DB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
4539#define DB_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff
4540#define DB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
4541#define DB_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0xffc00
4542#define DB_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa
4543#define DB_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000
4544#define DB_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
4545#define DB_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0xf000000
4546#define DB_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18
4547#define DB_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000
4548#define DB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
4549#define DB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff
4550#define DB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
4551#define DB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00
4552#define DB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
4553#define DB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000
4554#define DB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
4555#define DB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000
4556#define DB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
4557#define DB_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff
4558#define DB_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
4559#define DB_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00
4560#define DB_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
4561#define DB_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xf000000
4562#define DB_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18
4563#define DB_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf0000000
4564#define DB_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c
4565#define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
4566#define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
4567#define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
4568#define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
4569#define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
4570#define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
4571#define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
4572#define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
4573#define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
4574#define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
4575#define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
4576#define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
4577#define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
4578#define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
4579#define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
4580#define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
4581#define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE_MASK 0x1
4582#define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE__SHIFT 0x0
4583#define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE_MASK 0x2
4584#define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE__SHIFT 0x1
4585#define DB_DEBUG__FETCH_FULL_Z_TILE_MASK 0x4
4586#define DB_DEBUG__FETCH_FULL_Z_TILE__SHIFT 0x2
4587#define DB_DEBUG__FETCH_FULL_STENCIL_TILE_MASK 0x8
4588#define DB_DEBUG__FETCH_FULL_STENCIL_TILE__SHIFT 0x3
4589#define DB_DEBUG__FORCE_Z_MODE_MASK 0x30
4590#define DB_DEBUG__FORCE_Z_MODE__SHIFT 0x4
4591#define DB_DEBUG__DEBUG_FORCE_DEPTH_READ_MASK 0x40
4592#define DB_DEBUG__DEBUG_FORCE_DEPTH_READ__SHIFT 0x6
4593#define DB_DEBUG__DEBUG_FORCE_STENCIL_READ_MASK 0x80
4594#define DB_DEBUG__DEBUG_FORCE_STENCIL_READ__SHIFT 0x7
4595#define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE_MASK 0x300
4596#define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE__SHIFT 0x8
4597#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0_MASK 0xc00
4598#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0__SHIFT 0xa
4599#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1_MASK 0x3000
4600#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1__SHIFT 0xc
4601#define DB_DEBUG__DEBUG_FAST_Z_DISABLE_MASK 0x4000
4602#define DB_DEBUG__DEBUG_FAST_Z_DISABLE__SHIFT 0xe
4603#define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE_MASK 0x8000
4604#define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE__SHIFT 0xf
4605#define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE_MASK 0x10000
4606#define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE__SHIFT 0x10
4607#define DB_DEBUG__DISABLE_SUMM_SQUADS_MASK 0x20000
4608#define DB_DEBUG__DISABLE_SUMM_SQUADS__SHIFT 0x11
4609#define DB_DEBUG__DEPTH_CACHE_FORCE_MISS_MASK 0x40000
4610#define DB_DEBUG__DEPTH_CACHE_FORCE_MISS__SHIFT 0x12
4611#define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE_MASK 0x180000
4612#define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE__SHIFT 0x13
4613#define DB_DEBUG__NEVER_FREE_Z_ONLY_MASK 0x200000
4614#define DB_DEBUG__NEVER_FREE_Z_ONLY__SHIFT 0x15
4615#define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS_MASK 0x400000
4616#define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS__SHIFT 0x16
4617#define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION_MASK 0x800000
4618#define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION__SHIFT 0x17
4619#define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES_MASK 0xf000000
4620#define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES__SHIFT 0x18
4621#define DB_DEBUG__ONE_FREE_IN_FLIGHT_MASK 0x10000000
4622#define DB_DEBUG__ONE_FREE_IN_FLIGHT__SHIFT 0x1c
4623#define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT_MASK 0x20000000
4624#define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT__SHIFT 0x1d
4625#define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC_MASK 0x40000000
4626#define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC__SHIFT 0x1e
4627#define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC_MASK 0x80000000
4628#define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC__SHIFT 0x1f
4629#define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING_MASK 0x1
4630#define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING__SHIFT 0x0
4631#define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE_MASK 0x2
4632#define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE__SHIFT 0x1
4633#define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE_MASK 0x4
4634#define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE__SHIFT 0x2
4635#define DB_DEBUG2__DTR_ROUND_ROBIN_ARB_MASK 0x8
4636#define DB_DEBUG2__DTR_ROUND_ROBIN_ARB__SHIFT 0x3
4637#define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM_MASK 0x10
4638#define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM__SHIFT 0x4
4639#define DB_DEBUG2__DISABLE_PREZL_LPF_STALL_MASK 0x20
4640#define DB_DEBUG2__DISABLE_PREZL_LPF_STALL__SHIFT 0x5
4641#define DB_DEBUG2__ENABLE_PREZL_CB_STALL_MASK 0x40
4642#define DB_DEBUG2__ENABLE_PREZL_CB_STALL__SHIFT 0x6
4643#define DB_DEBUG2__DISABLE_PREZL_LPF_STALL_REZ_MASK 0x80
4644#define DB_DEBUG2__DISABLE_PREZL_LPF_STALL_REZ__SHIFT 0x7
4645#define DB_DEBUG2__DISABLE_PREZL_CB_STALL_REZ_MASK 0x100
4646#define DB_DEBUG2__DISABLE_PREZL_CB_STALL_REZ__SHIFT 0x8
4647#define DB_DEBUG2__CLK_OFF_DELAY_MASK 0x3e00
4648#define DB_DEBUG2__CLK_OFF_DELAY__SHIFT 0x9
4649#define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER_MASK 0x4000
4650#define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER__SHIFT 0xe
4651#define DB_DEBUG2__ENABLE_SUBTILE_GROUPING_MASK 0x8000
4652#define DB_DEBUG2__ENABLE_SUBTILE_GROUPING__SHIFT 0xf
4653#define DB_DEBUG2__DISABLE_HTILE_PAIRED_PIPES_MASK 0x10000
4654#define DB_DEBUG2__DISABLE_HTILE_PAIRED_PIPES__SHIFT 0x10
4655#define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING_MASK 0x20000
4656#define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING__SHIFT 0x11
4657#define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING_MASK 0x40000
4658#define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING__SHIFT 0x12
4659#define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL_MASK 0x80000
4660#define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL__SHIFT 0x13
4661#define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM_MASK 0x10000000
4662#define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM__SHIFT 0x1c
4663#define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL_MASK 0x20000000
4664#define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL__SHIFT 0x1d
4665#define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM_MASK 0x40000000
4666#define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM__SHIFT 0x1e
4667#define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT_MASK 0x80000000
4668#define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT__SHIFT 0x1f
4669#define DB_DEBUG3__FORCE_DB_IS_GOOD_MASK 0x4
4670#define DB_DEBUG3__FORCE_DB_IS_GOOD__SHIFT 0x2
4671#define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION_MASK 0x8
4672#define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION__SHIFT 0x3
4673#define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP_MASK 0x10
4674#define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP__SHIFT 0x4
4675#define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z_MASK 0x20
4676#define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z__SHIFT 0x5
4677#define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z_MASK 0x40
4678#define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z__SHIFT 0x6
4679#define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS_MASK 0x80
4680#define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS__SHIFT 0x7
4681#define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION_MASK 0x100
4682#define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION__SHIFT 0x8
4683#define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT_MASK 0x200
4684#define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT__SHIFT 0x9
4685#define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP_MASK 0x400
4686#define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP__SHIFT 0xa
4687#define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS_MASK 0x800
4688#define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS__SHIFT 0xb
4689#define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING_MASK 0x1000
4690#define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING__SHIFT 0xc
4691#define DB_DEBUG3__DISABLE_OP_DF_BYPASS_MASK 0x2000
4692#define DB_DEBUG3__DISABLE_OP_DF_BYPASS__SHIFT 0xd
4693#define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE_MASK 0x4000
4694#define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE__SHIFT 0xe
4695#define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK_MASK 0x8000
4696#define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK__SHIFT 0xf
4697#define DB_DEBUG3__ALLOW_RF2P_RW_COLLISION_MASK 0x10000
4698#define DB_DEBUG3__ALLOW_RF2P_RW_COLLISION__SHIFT 0x10
4699#define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE_MASK 0x20000
4700#define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE__SHIFT 0x11
4701#define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING_MASK 0x40000
4702#define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING__SHIFT 0x12
4703#define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE_MASK 0x80000
4704#define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE__SHIFT 0x13
4705#define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE_MASK 0x100000
4706#define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE__SHIFT 0x14
4707#define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT_MASK 0x200000
4708#define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT__SHIFT 0x15
4709#define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB_MASK 0x400000
4710#define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB__SHIFT 0x16
4711#define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD_MASK 0x800000
4712#define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD__SHIFT 0x17
4713#define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT_MASK 0x1000000
4714#define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT__SHIFT 0x18
4715#define DB_DEBUG3__DISABLE_DI_DT_STALL_MASK 0x2000000
4716#define DB_DEBUG3__DISABLE_DI_DT_STALL__SHIFT 0x19
4717#define DB_DEBUG3__ENABLE_DB_PROCESS_RESET_MASK 0x4000000
4718#define DB_DEBUG3__ENABLE_DB_PROCESS_RESET__SHIFT 0x1a
4719#define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX_MASK 0x8000000
4720#define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX__SHIFT 0x1b
4721#define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND_MASK 0x10000000
4722#define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND__SHIFT 0x1c
4723#define DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND_MASK 0x20000000
4724#define DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND__SHIFT 0x1d
4725#define DB_DEBUG3__DISABLE_4XAA_2P_DELAYED_WRITE_MASK 0x40000000
4726#define DB_DEBUG3__DISABLE_4XAA_2P_DELAYED_WRITE__SHIFT 0x1e
4727#define DB_DEBUG3__DISABLE_4XAA_2P_INTERLEAVED_PMASK_MASK 0x80000000
4728#define DB_DEBUG3__DISABLE_4XAA_2P_INTERLEAVED_PMASK__SHIFT 0x1f
4729#define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION_MASK 0x1
4730#define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION__SHIFT 0x0
4731#define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION_MASK 0x2
4732#define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION__SHIFT 0x1
4733#define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL_MASK 0x4
4734#define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL__SHIFT 0x2
4735#define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL_MASK 0x8
4736#define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL__SHIFT 0x3
4737#define DB_DEBUG4__DB_EXTRA_DEBUG4_MASK 0xfffffff0
4738#define DB_DEBUG4__DB_EXTRA_DEBUG4__SHIFT 0x4
4739#define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS_MASK 0x1f
4740#define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS__SHIFT 0x0
4741#define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS_MASK 0x3e0
4742#define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS__SHIFT 0x5
4743#define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS_MASK 0x1c00
4744#define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS__SHIFT 0xa
4745#define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS_MASK 0x7f000000
4746#define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS__SHIFT 0x18
4747#define DB_WATERMARKS__DEPTH_FREE_MASK 0x1f
4748#define DB_WATERMARKS__DEPTH_FREE__SHIFT 0x0
4749#define DB_WATERMARKS__DEPTH_FLUSH_MASK 0x7e0
4750#define DB_WATERMARKS__DEPTH_FLUSH__SHIFT 0x5
4751#define DB_WATERMARKS__FORCE_SUMMARIZE_MASK 0x7800
4752#define DB_WATERMARKS__FORCE_SUMMARIZE__SHIFT 0xb
4753#define DB_WATERMARKS__DEPTH_PENDING_FREE_MASK 0xf8000
4754#define DB_WATERMARKS__DEPTH_PENDING_FREE__SHIFT 0xf
4755#define DB_WATERMARKS__DEPTH_CACHELINE_FREE_MASK 0x7f00000
4756#define DB_WATERMARKS__DEPTH_CACHELINE_FREE__SHIFT 0x14
4757#define DB_WATERMARKS__EARLY_Z_PANIC_DISABLE_MASK 0x8000000
4758#define DB_WATERMARKS__EARLY_Z_PANIC_DISABLE__SHIFT 0x1b
4759#define DB_WATERMARKS__LATE_Z_PANIC_DISABLE_MASK 0x10000000
4760#define DB_WATERMARKS__LATE_Z_PANIC_DISABLE__SHIFT 0x1c
4761#define DB_WATERMARKS__RE_Z_PANIC_DISABLE_MASK 0x20000000
4762#define DB_WATERMARKS__RE_Z_PANIC_DISABLE__SHIFT 0x1d
4763#define DB_WATERMARKS__AUTO_FLUSH_HTILE_MASK 0x40000000
4764#define DB_WATERMARKS__AUTO_FLUSH_HTILE__SHIFT 0x1e
4765#define DB_WATERMARKS__AUTO_FLUSH_QUAD_MASK 0x80000000
4766#define DB_WATERMARKS__AUTO_FLUSH_QUAD__SHIFT 0x1f
4767#define DB_SUBTILE_CONTROL__MSAA1_X_MASK 0x3
4768#define DB_SUBTILE_CONTROL__MSAA1_X__SHIFT 0x0
4769#define DB_SUBTILE_CONTROL__MSAA1_Y_MASK 0xc
4770#define DB_SUBTILE_CONTROL__MSAA1_Y__SHIFT 0x2
4771#define DB_SUBTILE_CONTROL__MSAA2_X_MASK 0x30
4772#define DB_SUBTILE_CONTROL__MSAA2_X__SHIFT 0x4
4773#define DB_SUBTILE_CONTROL__MSAA2_Y_MASK 0xc0
4774#define DB_SUBTILE_CONTROL__MSAA2_Y__SHIFT 0x6
4775#define DB_SUBTILE_CONTROL__MSAA4_X_MASK 0x300
4776#define DB_SUBTILE_CONTROL__MSAA4_X__SHIFT 0x8
4777#define DB_SUBTILE_CONTROL__MSAA4_Y_MASK 0xc00
4778#define DB_SUBTILE_CONTROL__MSAA4_Y__SHIFT 0xa
4779#define DB_SUBTILE_CONTROL__MSAA8_X_MASK 0x3000
4780#define DB_SUBTILE_CONTROL__MSAA8_X__SHIFT 0xc
4781#define DB_SUBTILE_CONTROL__MSAA8_Y_MASK 0xc000
4782#define DB_SUBTILE_CONTROL__MSAA8_Y__SHIFT 0xe
4783#define DB_SUBTILE_CONTROL__MSAA16_X_MASK 0x30000
4784#define DB_SUBTILE_CONTROL__MSAA16_X__SHIFT 0x10
4785#define DB_SUBTILE_CONTROL__MSAA16_Y_MASK 0xc0000
4786#define DB_SUBTILE_CONTROL__MSAA16_Y__SHIFT 0x12
4787#define DB_FREE_CACHELINES__FREE_DTILE_DEPTH_MASK 0x7f
4788#define DB_FREE_CACHELINES__FREE_DTILE_DEPTH__SHIFT 0x0
4789#define DB_FREE_CACHELINES__FREE_PLANE_DEPTH_MASK 0x3f80
4790#define DB_FREE_CACHELINES__FREE_PLANE_DEPTH__SHIFT 0x7
4791#define DB_FREE_CACHELINES__FREE_Z_DEPTH_MASK 0x1fc000
4792#define DB_FREE_CACHELINES__FREE_Z_DEPTH__SHIFT 0xe
4793#define DB_FREE_CACHELINES__FREE_HTILE_DEPTH_MASK 0x1e00000
4794#define DB_FREE_CACHELINES__FREE_HTILE_DEPTH__SHIFT 0x15
4795#define DB_FREE_CACHELINES__QUAD_READ_REQS_MASK 0xfe000000
4796#define DB_FREE_CACHELINES__QUAD_READ_REQS__SHIFT 0x19
4797#define DB_FIFO_DEPTH1__MI_RDREQ_FIFO_DEPTH_MASK 0x1f
4798#define DB_FIFO_DEPTH1__MI_RDREQ_FIFO_DEPTH__SHIFT 0x0
4799#define DB_FIFO_DEPTH1__MI_WRREQ_FIFO_DEPTH_MASK 0x3e0
4800#define DB_FIFO_DEPTH1__MI_WRREQ_FIFO_DEPTH__SHIFT 0x5
4801#define DB_FIFO_DEPTH1__MCC_DEPTH_MASK 0xfc00
4802#define DB_FIFO_DEPTH1__MCC_DEPTH__SHIFT 0xa
4803#define DB_FIFO_DEPTH1__QC_DEPTH_MASK 0x1f0000
4804#define DB_FIFO_DEPTH1__QC_DEPTH__SHIFT 0x10
4805#define DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH_MASK 0x1fe00000
4806#define DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH__SHIFT 0x15
4807#define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH_MASK 0xff
4808#define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH__SHIFT 0x0
4809#define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH_MASK 0x7f00
4810#define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH__SHIFT 0x8
4811#define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH_MASK 0x1ff8000
4812#define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH__SHIFT 0xf
4813#define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH_MASK 0xfe000000
4814#define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH__SHIFT 0x19
4815#define DB_CGTT_CLK_CTRL_0__ON_DELAY_MASK 0xf
4816#define DB_CGTT_CLK_CTRL_0__ON_DELAY__SHIFT 0x0
4817#define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS_MASK 0xff0
4818#define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS__SHIFT 0x4
4819#define DB_CGTT_CLK_CTRL_0__RESERVED_MASK 0xfff000
4820#define DB_CGTT_CLK_CTRL_0__RESERVED__SHIFT 0xc
4821#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7_MASK 0x1000000
4822#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7__SHIFT 0x18
4823#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6_MASK 0x2000000
4824#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6__SHIFT 0x19
4825#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5_MASK 0x4000000
4826#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5__SHIFT 0x1a
4827#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4_MASK 0x8000000
4828#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4__SHIFT 0x1b
4829#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3_MASK 0x10000000
4830#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3__SHIFT 0x1c
4831#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2_MASK 0x20000000
4832#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2__SHIFT 0x1d
4833#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1_MASK 0x40000000
4834#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1__SHIFT 0x1e
4835#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0_MASK 0x80000000
4836#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0__SHIFT 0x1f
4837#define DB_ZPASS_COUNT_LOW__COUNT_LOW_MASK 0xffffffff
4838#define DB_ZPASS_COUNT_LOW__COUNT_LOW__SHIFT 0x0
4839#define DB_ZPASS_COUNT_HI__COUNT_HI_MASK 0x7fffffff
4840#define DB_ZPASS_COUNT_HI__COUNT_HI__SHIFT 0x0
4841#define DB_RING_CONTROL__COUNTER_CONTROL_MASK 0x3
4842#define DB_RING_CONTROL__COUNTER_CONTROL__SHIFT 0x0
4843#define DB_READ_DEBUG_0__BUSY_DATA0_MASK 0xffffffff
4844#define DB_READ_DEBUG_0__BUSY_DATA0__SHIFT 0x0
4845#define DB_READ_DEBUG_1__BUSY_DATA1_MASK 0xffffffff
4846#define DB_READ_DEBUG_1__BUSY_DATA1__SHIFT 0x0
4847#define DB_READ_DEBUG_2__BUSY_DATA2_MASK 0xffffffff
4848#define DB_READ_DEBUG_2__BUSY_DATA2__SHIFT 0x0
4849#define DB_READ_DEBUG_3__DEBUG_DATA_MASK 0xffffffff
4850#define DB_READ_DEBUG_3__DEBUG_DATA__SHIFT 0x0
4851#define DB_READ_DEBUG_4__DEBUG_DATA_MASK 0xffffffff
4852#define DB_READ_DEBUG_4__DEBUG_DATA__SHIFT 0x0
4853#define DB_READ_DEBUG_5__DEBUG_DATA_MASK 0xffffffff
4854#define DB_READ_DEBUG_5__DEBUG_DATA__SHIFT 0x0
4855#define DB_READ_DEBUG_6__DEBUG_DATA_MASK 0xffffffff
4856#define DB_READ_DEBUG_6__DEBUG_DATA__SHIFT 0x0
4857#define DB_READ_DEBUG_7__DEBUG_DATA_MASK 0xffffffff
4858#define DB_READ_DEBUG_7__DEBUG_DATA__SHIFT 0x0
4859#define DB_READ_DEBUG_8__DEBUG_DATA_MASK 0xffffffff
4860#define DB_READ_DEBUG_8__DEBUG_DATA__SHIFT 0x0
4861#define DB_READ_DEBUG_9__DEBUG_DATA_MASK 0xffffffff
4862#define DB_READ_DEBUG_9__DEBUG_DATA__SHIFT 0x0
4863#define DB_READ_DEBUG_A__DEBUG_DATA_MASK 0xffffffff
4864#define DB_READ_DEBUG_A__DEBUG_DATA__SHIFT 0x0
4865#define DB_READ_DEBUG_B__DEBUG_DATA_MASK 0xffffffff
4866#define DB_READ_DEBUG_B__DEBUG_DATA__SHIFT 0x0
4867#define DB_READ_DEBUG_C__DEBUG_DATA_MASK 0xffffffff
4868#define DB_READ_DEBUG_C__DEBUG_DATA__SHIFT 0x0
4869#define DB_READ_DEBUG_D__DEBUG_DATA_MASK 0xffffffff
4870#define DB_READ_DEBUG_D__DEBUG_DATA__SHIFT 0x0
4871#define DB_READ_DEBUG_E__DEBUG_DATA_MASK 0xffffffff
4872#define DB_READ_DEBUG_E__DEBUG_DATA__SHIFT 0x0
4873#define DB_READ_DEBUG_F__DEBUG_DATA_MASK 0xffffffff
4874#define DB_READ_DEBUG_F__DEBUG_DATA__SHIFT 0x0
4875#define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW_MASK 0xffffffff
4876#define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW__SHIFT 0x0
4877#define DB_OCCLUSION_COUNT0_HI__COUNT_HI_MASK 0x7fffffff
4878#define DB_OCCLUSION_COUNT0_HI__COUNT_HI__SHIFT 0x0
4879#define DB_OCCLUSION_COUNT1_LOW__COUNT_LOW_MASK 0xffffffff
4880#define DB_OCCLUSION_COUNT1_LOW__COUNT_LOW__SHIFT 0x0
4881#define DB_OCCLUSION_COUNT1_HI__COUNT_HI_MASK 0x7fffffff
4882#define DB_OCCLUSION_COUNT1_HI__COUNT_HI__SHIFT 0x0
4883#define DB_OCCLUSION_COUNT2_LOW__COUNT_LOW_MASK 0xffffffff
4884#define DB_OCCLUSION_COUNT2_LOW__COUNT_LOW__SHIFT 0x0
4885#define DB_OCCLUSION_COUNT2_HI__COUNT_HI_MASK 0x7fffffff
4886#define DB_OCCLUSION_COUNT2_HI__COUNT_HI__SHIFT 0x0
4887#define DB_OCCLUSION_COUNT3_LOW__COUNT_LOW_MASK 0xffffffff
4888#define DB_OCCLUSION_COUNT3_LOW__COUNT_LOW__SHIFT 0x0
4889#define DB_OCCLUSION_COUNT3_HI__COUNT_HI_MASK 0x7fffffff
4890#define DB_OCCLUSION_COUNT3_HI__COUNT_HI__SHIFT 0x0
4891#define CC_RB_REDUNDANCY__FAILED_RB0_MASK 0xf00
4892#define CC_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8
4893#define CC_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x1000
4894#define CC_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc
4895#define CC_RB_REDUNDANCY__FAILED_RB1_MASK 0xf0000
4896#define CC_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10
4897#define CC_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x100000
4898#define CC_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14
4899#define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0xff0000
4900#define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10
4901#define GC_USER_RB_REDUNDANCY__FAILED_RB0_MASK 0xf00
4902#define GC_USER_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8
4903#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x1000
4904#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc
4905#define GC_USER_RB_REDUNDANCY__FAILED_RB1_MASK 0xf0000
4906#define GC_USER_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10
4907#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x100000
4908#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14
4909#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0xff0000
4910#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10
4911#define GB_ADDR_CONFIG__NUM_PIPES_MASK 0x7
4912#define GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
4913#define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
4914#define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
4915#define GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700
4916#define GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
4917#define GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000
4918#define GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc
4919#define GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000
4920#define GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
4921#define GB_ADDR_CONFIG__NUM_GPUS_MASK 0x700000
4922#define GB_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
4923#define GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000
4924#define GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
4925#define GB_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000
4926#define GB_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
4927#define GB_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000
4928#define GB_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
4929#define GB_BACKEND_MAP__BACKEND_MAP_MASK 0xffffffff
4930#define GB_BACKEND_MAP__BACKEND_MAP__SHIFT 0x0
4931#define GB_GPU_ID__GPU_ID_MASK 0xf
4932#define GB_GPU_ID__GPU_ID__SHIFT 0x0
4933#define CC_RB_DAISY_CHAIN__RB_0_MASK 0xf
4934#define CC_RB_DAISY_CHAIN__RB_0__SHIFT 0x0
4935#define CC_RB_DAISY_CHAIN__RB_1_MASK 0xf0
4936#define CC_RB_DAISY_CHAIN__RB_1__SHIFT 0x4
4937#define CC_RB_DAISY_CHAIN__RB_2_MASK 0xf00
4938#define CC_RB_DAISY_CHAIN__RB_2__SHIFT 0x8
4939#define CC_RB_DAISY_CHAIN__RB_3_MASK 0xf000
4940#define CC_RB_DAISY_CHAIN__RB_3__SHIFT 0xc
4941#define CC_RB_DAISY_CHAIN__RB_4_MASK 0xf0000
4942#define CC_RB_DAISY_CHAIN__RB_4__SHIFT 0x10
4943#define CC_RB_DAISY_CHAIN__RB_5_MASK 0xf00000
4944#define CC_RB_DAISY_CHAIN__RB_5__SHIFT 0x14
4945#define CC_RB_DAISY_CHAIN__RB_6_MASK 0xf000000
4946#define CC_RB_DAISY_CHAIN__RB_6__SHIFT 0x18
4947#define CC_RB_DAISY_CHAIN__RB_7_MASK 0xf0000000
4948#define CC_RB_DAISY_CHAIN__RB_7__SHIFT 0x1c
4949#define GB_TILE_MODE0__ARRAY_MODE_MASK 0x3c
4950#define GB_TILE_MODE0__ARRAY_MODE__SHIFT 0x2
4951#define GB_TILE_MODE0__PIPE_CONFIG_MASK 0x7c0
4952#define GB_TILE_MODE0__PIPE_CONFIG__SHIFT 0x6
4953#define GB_TILE_MODE0__TILE_SPLIT_MASK 0x3800
4954#define GB_TILE_MODE0__TILE_SPLIT__SHIFT 0xb
4955#define GB_TILE_MODE0__MICRO_TILE_MODE_NEW_MASK 0x1c00000
4956#define GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT 0x16
4957#define GB_TILE_MODE0__SAMPLE_SPLIT_MASK 0x6000000
4958#define GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT 0x19
4959#define GB_TILE_MODE1__ARRAY_MODE_MASK 0x3c
4960#define GB_TILE_MODE1__ARRAY_MODE__SHIFT 0x2
4961#define GB_TILE_MODE1__PIPE_CONFIG_MASK 0x7c0
4962#define GB_TILE_MODE1__PIPE_CONFIG__SHIFT 0x6
4963#define GB_TILE_MODE1__TILE_SPLIT_MASK 0x3800
4964#define GB_TILE_MODE1__TILE_SPLIT__SHIFT 0xb
4965#define GB_TILE_MODE1__MICRO_TILE_MODE_NEW_MASK 0x1c00000
4966#define GB_TILE_MODE1__MICRO_TILE_MODE_NEW__SHIFT 0x16
4967#define GB_TILE_MODE1__SAMPLE_SPLIT_MASK 0x6000000
4968#define GB_TILE_MODE1__SAMPLE_SPLIT__SHIFT 0x19
4969#define GB_TILE_MODE2__ARRAY_MODE_MASK 0x3c
4970#define GB_TILE_MODE2__ARRAY_MODE__SHIFT 0x2
4971#define GB_TILE_MODE2__PIPE_CONFIG_MASK 0x7c0
4972#define GB_TILE_MODE2__PIPE_CONFIG__SHIFT 0x6
4973#define GB_TILE_MODE2__TILE_SPLIT_MASK 0x3800
4974#define GB_TILE_MODE2__TILE_SPLIT__SHIFT 0xb
4975#define GB_TILE_MODE2__MICRO_TILE_MODE_NEW_MASK 0x1c00000
4976#define GB_TILE_MODE2__MICRO_TILE_MODE_NEW__SHIFT 0x16
4977#define GB_TILE_MODE2__SAMPLE_SPLIT_MASK 0x6000000
4978#define GB_TILE_MODE2__SAMPLE_SPLIT__SHIFT 0x19
4979#define GB_TILE_MODE3__ARRAY_MODE_MASK 0x3c
4980#define GB_TILE_MODE3__ARRAY_MODE__SHIFT 0x2
4981#define GB_TILE_MODE3__PIPE_CONFIG_MASK 0x7c0
4982#define GB_TILE_MODE3__PIPE_CONFIG__SHIFT 0x6
4983#define GB_TILE_MODE3__TILE_SPLIT_MASK 0x3800
4984#define GB_TILE_MODE3__TILE_SPLIT__SHIFT 0xb
4985#define GB_TILE_MODE3__MICRO_TILE_MODE_NEW_MASK 0x1c00000
4986#define GB_TILE_MODE3__MICRO_TILE_MODE_NEW__SHIFT 0x16
4987#define GB_TILE_MODE3__SAMPLE_SPLIT_MASK 0x6000000
4988#define GB_TILE_MODE3__SAMPLE_SPLIT__SHIFT 0x19
4989#define GB_TILE_MODE4__ARRAY_MODE_MASK 0x3c
4990#define GB_TILE_MODE4__ARRAY_MODE__SHIFT 0x2
4991#define GB_TILE_MODE4__PIPE_CONFIG_MASK 0x7c0
4992#define GB_TILE_MODE4__PIPE_CONFIG__SHIFT 0x6
4993#define GB_TILE_MODE4__TILE_SPLIT_MASK 0x3800
4994#define GB_TILE_MODE4__TILE_SPLIT__SHIFT 0xb
4995#define GB_TILE_MODE4__MICRO_TILE_MODE_NEW_MASK 0x1c00000
4996#define GB_TILE_MODE4__MICRO_TILE_MODE_NEW__SHIFT 0x16
4997#define GB_TILE_MODE4__SAMPLE_SPLIT_MASK 0x6000000
4998#define GB_TILE_MODE4__SAMPLE_SPLIT__SHIFT 0x19
4999#define GB_TILE_MODE5__ARRAY_MODE_MASK 0x3c
5000#define GB_TILE_MODE5__ARRAY_MODE__SHIFT 0x2
5001#define GB_TILE_MODE5__PIPE_CONFIG_MASK 0x7c0
5002#define GB_TILE_MODE5__PIPE_CONFIG__SHIFT 0x6
5003#define GB_TILE_MODE5__TILE_SPLIT_MASK 0x3800
5004#define GB_TILE_MODE5__TILE_SPLIT__SHIFT 0xb
5005#define GB_TILE_MODE5__MICRO_TILE_MODE_NEW_MASK 0x1c00000
5006#define GB_TILE_MODE5__MICRO_TILE_MODE_NEW__SHIFT 0x16
5007#define GB_TILE_MODE5__SAMPLE_SPLIT_MASK 0x6000000
5008#define GB_TILE_MODE5__SAMPLE_SPLIT__SHIFT 0x19
5009#define GB_TILE_MODE6__ARRAY_MODE_MASK 0x3c
5010#define GB_TILE_MODE6__ARRAY_MODE__SHIFT 0x2
5011#define GB_TILE_MODE6__PIPE_CONFIG_MASK 0x7c0
5012#define GB_TILE_MODE6__PIPE_CONFIG__SHIFT 0x6
5013#define GB_TILE_MODE6__TILE_SPLIT_MASK 0x3800
5014#define GB_TILE_MODE6__TILE_SPLIT__SHIFT 0xb
5015#define GB_TILE_MODE6__MICRO_TILE_MODE_NEW_MASK 0x1c00000
5016#define GB_TILE_MODE6__MICRO_TILE_MODE_NEW__SHIFT 0x16
5017#define GB_TILE_MODE6__SAMPLE_SPLIT_MASK 0x6000000
5018#define GB_TILE_MODE6__SAMPLE_SPLIT__SHIFT 0x19
5019#define GB_TILE_MODE7__ARRAY_MODE_MASK 0x3c
5020#define GB_TILE_MODE7__ARRAY_MODE__SHIFT 0x2
5021#define GB_TILE_MODE7__PIPE_CONFIG_MASK 0x7c0
5022#define GB_TILE_MODE7__PIPE_CONFIG__SHIFT 0x6
5023#define GB_TILE_MODE7__TILE_SPLIT_MASK 0x3800
5024#define GB_TILE_MODE7__TILE_SPLIT__SHIFT 0xb
5025#define GB_TILE_MODE7__MICRO_TILE_MODE_NEW_MASK 0x1c00000
5026#define GB_TILE_MODE7__MICRO_TILE_MODE_NEW__SHIFT 0x16
5027#define GB_TILE_MODE7__SAMPLE_SPLIT_MASK 0x6000000
5028#define GB_TILE_MODE7__SAMPLE_SPLIT__SHIFT 0x19
5029#define GB_TILE_MODE8__ARRAY_MODE_MASK 0x3c
5030#define GB_TILE_MODE8__ARRAY_MODE__SHIFT 0x2
5031#define GB_TILE_MODE8__PIPE_CONFIG_MASK 0x7c0
5032#define GB_TILE_MODE8__PIPE_CONFIG__SHIFT 0x6
5033#define GB_TILE_MODE8__TILE_SPLIT_MASK 0x3800
5034#define GB_TILE_MODE8__TILE_SPLIT__SHIFT 0xb
5035#define GB_TILE_MODE8__MICRO_TILE_MODE_NEW_MASK 0x1c00000
5036#define GB_TILE_MODE8__MICRO_TILE_MODE_NEW__SHIFT 0x16
5037#define GB_TILE_MODE8__SAMPLE_SPLIT_MASK 0x6000000
5038#define GB_TILE_MODE8__SAMPLE_SPLIT__SHIFT 0x19
5039#define GB_TILE_MODE9__ARRAY_MODE_MASK 0x3c
5040#define GB_TILE_MODE9__ARRAY_MODE__SHIFT 0x2
5041#define GB_TILE_MODE9__PIPE_CONFIG_MASK 0x7c0
5042#define GB_TILE_MODE9__PIPE_CONFIG__SHIFT 0x6
5043#define GB_TILE_MODE9__TILE_SPLIT_MASK 0x3800
5044#define GB_TILE_MODE9__TILE_SPLIT__SHIFT 0xb
5045#define GB_TILE_MODE9__MICRO_TILE_MODE_NEW_MASK 0x1c00000
5046#define GB_TILE_MODE9__MICRO_TILE_MODE_NEW__SHIFT 0x16
5047#define GB_TILE_MODE9__SAMPLE_SPLIT_MASK 0x6000000
5048#define GB_TILE_MODE9__SAMPLE_SPLIT__SHIFT 0x19
5049#define GB_TILE_MODE10__ARRAY_MODE_MASK 0x3c
5050#define GB_TILE_MODE10__ARRAY_MODE__SHIFT 0x2
5051#define GB_TILE_MODE10__PIPE_CONFIG_MASK 0x7c0
5052#define GB_TILE_MODE10__PIPE_CONFIG__SHIFT 0x6
5053#define GB_TILE_MODE10__TILE_SPLIT_MASK 0x3800
5054#define GB_TILE_MODE10__TILE_SPLIT__SHIFT 0xb
5055#define GB_TILE_MODE10__MICRO_TILE_MODE_NEW_MASK 0x1c00000
5056#define GB_TILE_MODE10__MICRO_TILE_MODE_NEW__SHIFT 0x16
5057#define GB_TILE_MODE10__SAMPLE_SPLIT_MASK 0x6000000
5058#define GB_TILE_MODE10__SAMPLE_SPLIT__SHIFT 0x19
5059#define GB_TILE_MODE11__ARRAY_MODE_MASK 0x3c
5060#define GB_TILE_MODE11__ARRAY_MODE__SHIFT 0x2
5061#define GB_TILE_MODE11__PIPE_CONFIG_MASK 0x7c0
5062#define GB_TILE_MODE11__PIPE_CONFIG__SHIFT 0x6
5063#define GB_TILE_MODE11__TILE_SPLIT_MASK 0x3800
5064#define GB_TILE_MODE11__TILE_SPLIT__SHIFT 0xb
5065#define GB_TILE_MODE11__MICRO_TILE_MODE_NEW_MASK 0x1c00000
5066#define GB_TILE_MODE11__MICRO_TILE_MODE_NEW__SHIFT 0x16
5067#define GB_TILE_MODE11__SAMPLE_SPLIT_MASK 0x6000000
5068#define GB_TILE_MODE11__SAMPLE_SPLIT__SHIFT 0x19
5069#define GB_TILE_MODE12__ARRAY_MODE_MASK 0x3c
5070#define GB_TILE_MODE12__ARRAY_MODE__SHIFT 0x2
5071#define GB_TILE_MODE12__PIPE_CONFIG_MASK 0x7c0
5072#define GB_TILE_MODE12__PIPE_CONFIG__SHIFT 0x6
5073#define GB_TILE_MODE12__TILE_SPLIT_MASK 0x3800
5074#define GB_TILE_MODE12__TILE_SPLIT__SHIFT 0xb
5075#define GB_TILE_MODE12__MICRO_TILE_MODE_NEW_MASK 0x1c00000
5076#define GB_TILE_MODE12__MICRO_TILE_MODE_NEW__SHIFT 0x16
5077#define GB_TILE_MODE12__SAMPLE_SPLIT_MASK 0x6000000
5078#define GB_TILE_MODE12__SAMPLE_SPLIT__SHIFT 0x19
5079#define GB_TILE_MODE13__ARRAY_MODE_MASK 0x3c
5080#define GB_TILE_MODE13__ARRAY_MODE__SHIFT 0x2
5081#define GB_TILE_MODE13__PIPE_CONFIG_MASK 0x7c0
5082#define GB_TILE_MODE13__PIPE_CONFIG__SHIFT 0x6
5083#define GB_TILE_MODE13__TILE_SPLIT_MASK 0x3800
5084#define GB_TILE_MODE13__TILE_SPLIT__SHIFT 0xb
5085#define GB_TILE_MODE13__MICRO_TILE_MODE_NEW_MASK 0x1c00000
5086#define GB_TILE_MODE13__MICRO_TILE_MODE_NEW__SHIFT 0x16
5087#define GB_TILE_MODE13__SAMPLE_SPLIT_MASK 0x6000000
5088#define GB_TILE_MODE13__SAMPLE_SPLIT__SHIFT 0x19
5089#define GB_TILE_MODE14__ARRAY_MODE_MASK 0x3c
5090#define GB_TILE_MODE14__ARRAY_MODE__SHIFT 0x2
5091#define GB_TILE_MODE14__PIPE_CONFIG_MASK 0x7c0
5092#define GB_TILE_MODE14__PIPE_CONFIG__SHIFT 0x6
5093#define GB_TILE_MODE14__TILE_SPLIT_MASK 0x3800
5094#define GB_TILE_MODE14__TILE_SPLIT__SHIFT 0xb
5095#define GB_TILE_MODE14__MICRO_TILE_MODE_NEW_MASK 0x1c00000
5096#define GB_TILE_MODE14__MICRO_TILE_MODE_NEW__SHIFT 0x16
5097#define GB_TILE_MODE14__SAMPLE_SPLIT_MASK 0x6000000
5098#define GB_TILE_MODE14__SAMPLE_SPLIT__SHIFT 0x19
5099#define GB_TILE_MODE15__ARRAY_MODE_MASK 0x3c
5100#define GB_TILE_MODE15__ARRAY_MODE__SHIFT 0x2
5101#define GB_TILE_MODE15__PIPE_CONFIG_MASK 0x7c0
5102#define GB_TILE_MODE15__PIPE_CONFIG__SHIFT 0x6
5103#define GB_TILE_MODE15__TILE_SPLIT_MASK 0x3800
5104#define GB_TILE_MODE15__TILE_SPLIT__SHIFT 0xb
5105#define GB_TILE_MODE15__MICRO_TILE_MODE_NEW_MASK 0x1c00000
5106#define GB_TILE_MODE15__MICRO_TILE_MODE_NEW__SHIFT 0x16
5107#define GB_TILE_MODE15__SAMPLE_SPLIT_MASK 0x6000000
5108#define GB_TILE_MODE15__SAMPLE_SPLIT__SHIFT 0x19
5109#define GB_TILE_MODE16__ARRAY_MODE_MASK 0x3c
5110#define GB_TILE_MODE16__ARRAY_MODE__SHIFT 0x2
5111#define GB_TILE_MODE16__PIPE_CONFIG_MASK 0x7c0
5112#define GB_TILE_MODE16__PIPE_CONFIG__SHIFT 0x6
5113#define GB_TILE_MODE16__TILE_SPLIT_MASK 0x3800
5114#define GB_TILE_MODE16__TILE_SPLIT__SHIFT 0xb
5115#define GB_TILE_MODE16__MICRO_TILE_MODE_NEW_MASK 0x1c00000
5116#define GB_TILE_MODE16__MICRO_TILE_MODE_NEW__SHIFT 0x16
5117#define GB_TILE_MODE16__SAMPLE_SPLIT_MASK 0x6000000
5118#define GB_TILE_MODE16__SAMPLE_SPLIT__SHIFT 0x19
5119#define GB_TILE_MODE17__ARRAY_MODE_MASK 0x3c
5120#define GB_TILE_MODE17__ARRAY_MODE__SHIFT 0x2
5121#define GB_TILE_MODE17__PIPE_CONFIG_MASK 0x7c0
5122#define GB_TILE_MODE17__PIPE_CONFIG__SHIFT 0x6
5123#define GB_TILE_MODE17__TILE_SPLIT_MASK 0x3800
5124#define GB_TILE_MODE17__TILE_SPLIT__SHIFT 0xb
5125#define GB_TILE_MODE17__MICRO_TILE_MODE_NEW_MASK 0x1c00000
5126#define GB_TILE_MODE17__MICRO_TILE_MODE_NEW__SHIFT 0x16
5127#define GB_TILE_MODE17__SAMPLE_SPLIT_MASK 0x6000000
5128#define GB_TILE_MODE17__SAMPLE_SPLIT__SHIFT 0x19
5129#define GB_TILE_MODE18__ARRAY_MODE_MASK 0x3c
5130#define GB_TILE_MODE18__ARRAY_MODE__SHIFT 0x2
5131#define GB_TILE_MODE18__PIPE_CONFIG_MASK 0x7c0
5132#define GB_TILE_MODE18__PIPE_CONFIG__SHIFT 0x6
5133#define GB_TILE_MODE18__TILE_SPLIT_MASK 0x3800
5134#define GB_TILE_MODE18__TILE_SPLIT__SHIFT 0xb
5135#define GB_TILE_MODE18__MICRO_TILE_MODE_NEW_MASK 0x1c00000
5136#define GB_TILE_MODE18__MICRO_TILE_MODE_NEW__SHIFT 0x16
5137#define GB_TILE_MODE18__SAMPLE_SPLIT_MASK 0x6000000
5138#define GB_TILE_MODE18__SAMPLE_SPLIT__SHIFT 0x19
5139#define GB_TILE_MODE19__ARRAY_MODE_MASK 0x3c
5140#define GB_TILE_MODE19__ARRAY_MODE__SHIFT 0x2
5141#define GB_TILE_MODE19__PIPE_CONFIG_MASK 0x7c0
5142#define GB_TILE_MODE19__PIPE_CONFIG__SHIFT 0x6
5143#define GB_TILE_MODE19__TILE_SPLIT_MASK 0x3800
5144#define GB_TILE_MODE19__TILE_SPLIT__SHIFT 0xb
5145#define GB_TILE_MODE19__MICRO_TILE_MODE_NEW_MASK 0x1c00000
5146#define GB_TILE_MODE19__MICRO_TILE_MODE_NEW__SHIFT 0x16
5147#define GB_TILE_MODE19__SAMPLE_SPLIT_MASK 0x6000000
5148#define GB_TILE_MODE19__SAMPLE_SPLIT__SHIFT 0x19
5149#define GB_TILE_MODE20__ARRAY_MODE_MASK 0x3c
5150#define GB_TILE_MODE20__ARRAY_MODE__SHIFT 0x2
5151#define GB_TILE_MODE20__PIPE_CONFIG_MASK 0x7c0
5152#define GB_TILE_MODE20__PIPE_CONFIG__SHIFT 0x6
5153#define GB_TILE_MODE20__TILE_SPLIT_MASK 0x3800
5154#define GB_TILE_MODE20__TILE_SPLIT__SHIFT 0xb
5155#define GB_TILE_MODE20__MICRO_TILE_MODE_NEW_MASK 0x1c00000
5156#define GB_TILE_MODE20__MICRO_TILE_MODE_NEW__SHIFT 0x16
5157#define GB_TILE_MODE20__SAMPLE_SPLIT_MASK 0x6000000
5158#define GB_TILE_MODE20__SAMPLE_SPLIT__SHIFT 0x19
5159#define GB_TILE_MODE21__ARRAY_MODE_MASK 0x3c
5160#define GB_TILE_MODE21__ARRAY_MODE__SHIFT 0x2
5161#define GB_TILE_MODE21__PIPE_CONFIG_MASK 0x7c0
5162#define GB_TILE_MODE21__PIPE_CONFIG__SHIFT 0x6
5163#define GB_TILE_MODE21__TILE_SPLIT_MASK 0x3800
5164#define GB_TILE_MODE21__TILE_SPLIT__SHIFT 0xb
5165#define GB_TILE_MODE21__MICRO_TILE_MODE_NEW_MASK 0x1c00000
5166#define GB_TILE_MODE21__MICRO_TILE_MODE_NEW__SHIFT 0x16
5167#define GB_TILE_MODE21__SAMPLE_SPLIT_MASK 0x6000000
5168#define GB_TILE_MODE21__SAMPLE_SPLIT__SHIFT 0x19
5169#define GB_TILE_MODE22__ARRAY_MODE_MASK 0x3c
5170#define GB_TILE_MODE22__ARRAY_MODE__SHIFT 0x2
5171#define GB_TILE_MODE22__PIPE_CONFIG_MASK 0x7c0
5172#define GB_TILE_MODE22__PIPE_CONFIG__SHIFT 0x6
5173#define GB_TILE_MODE22__TILE_SPLIT_MASK 0x3800
5174#define GB_TILE_MODE22__TILE_SPLIT__SHIFT 0xb
5175#define GB_TILE_MODE22__MICRO_TILE_MODE_NEW_MASK 0x1c00000
5176#define GB_TILE_MODE22__MICRO_TILE_MODE_NEW__SHIFT 0x16
5177#define GB_TILE_MODE22__SAMPLE_SPLIT_MASK 0x6000000
5178#define GB_TILE_MODE22__SAMPLE_SPLIT__SHIFT 0x19
5179#define GB_TILE_MODE23__ARRAY_MODE_MASK 0x3c
5180#define GB_TILE_MODE23__ARRAY_MODE__SHIFT 0x2
5181#define GB_TILE_MODE23__PIPE_CONFIG_MASK 0x7c0
5182#define GB_TILE_MODE23__PIPE_CONFIG__SHIFT 0x6
5183#define GB_TILE_MODE23__TILE_SPLIT_MASK 0x3800
5184#define GB_TILE_MODE23__TILE_SPLIT__SHIFT 0xb
5185#define GB_TILE_MODE23__MICRO_TILE_MODE_NEW_MASK 0x1c00000
5186#define GB_TILE_MODE23__MICRO_TILE_MODE_NEW__SHIFT 0x16
5187#define GB_TILE_MODE23__SAMPLE_SPLIT_MASK 0x6000000
5188#define GB_TILE_MODE23__SAMPLE_SPLIT__SHIFT 0x19
5189#define GB_TILE_MODE24__ARRAY_MODE_MASK 0x3c
5190#define GB_TILE_MODE24__ARRAY_MODE__SHIFT 0x2
5191#define GB_TILE_MODE24__PIPE_CONFIG_MASK 0x7c0
5192#define GB_TILE_MODE24__PIPE_CONFIG__SHIFT 0x6
5193#define GB_TILE_MODE24__TILE_SPLIT_MASK 0x3800
5194#define GB_TILE_MODE24__TILE_SPLIT__SHIFT 0xb
5195#define GB_TILE_MODE24__MICRO_TILE_MODE_NEW_MASK 0x1c00000
5196#define GB_TILE_MODE24__MICRO_TILE_MODE_NEW__SHIFT 0x16
5197#define GB_TILE_MODE24__SAMPLE_SPLIT_MASK 0x6000000
5198#define GB_TILE_MODE24__SAMPLE_SPLIT__SHIFT 0x19
5199#define GB_TILE_MODE25__ARRAY_MODE_MASK 0x3c
5200#define GB_TILE_MODE25__ARRAY_MODE__SHIFT 0x2
5201#define GB_TILE_MODE25__PIPE_CONFIG_MASK 0x7c0
5202#define GB_TILE_MODE25__PIPE_CONFIG__SHIFT 0x6
5203#define GB_TILE_MODE25__TILE_SPLIT_MASK 0x3800
5204#define GB_TILE_MODE25__TILE_SPLIT__SHIFT 0xb
5205#define GB_TILE_MODE25__MICRO_TILE_MODE_NEW_MASK 0x1c00000
5206#define GB_TILE_MODE25__MICRO_TILE_MODE_NEW__SHIFT 0x16
5207#define GB_TILE_MODE25__SAMPLE_SPLIT_MASK 0x6000000
5208#define GB_TILE_MODE25__SAMPLE_SPLIT__SHIFT 0x19
5209#define GB_TILE_MODE26__ARRAY_MODE_MASK 0x3c
5210#define GB_TILE_MODE26__ARRAY_MODE__SHIFT 0x2
5211#define GB_TILE_MODE26__PIPE_CONFIG_MASK 0x7c0
5212#define GB_TILE_MODE26__PIPE_CONFIG__SHIFT 0x6
5213#define GB_TILE_MODE26__TILE_SPLIT_MASK 0x3800
5214#define GB_TILE_MODE26__TILE_SPLIT__SHIFT 0xb
5215#define GB_TILE_MODE26__MICRO_TILE_MODE_NEW_MASK 0x1c00000
5216#define GB_TILE_MODE26__MICRO_TILE_MODE_NEW__SHIFT 0x16
5217#define GB_TILE_MODE26__SAMPLE_SPLIT_MASK 0x6000000
5218#define GB_TILE_MODE26__SAMPLE_SPLIT__SHIFT 0x19
5219#define GB_TILE_MODE27__ARRAY_MODE_MASK 0x3c
5220#define GB_TILE_MODE27__ARRAY_MODE__SHIFT 0x2
5221#define GB_TILE_MODE27__PIPE_CONFIG_MASK 0x7c0
5222#define GB_TILE_MODE27__PIPE_CONFIG__SHIFT 0x6
5223#define GB_TILE_MODE27__TILE_SPLIT_MASK 0x3800
5224#define GB_TILE_MODE27__TILE_SPLIT__SHIFT 0xb
5225#define GB_TILE_MODE27__MICRO_TILE_MODE_NEW_MASK 0x1c00000
5226#define GB_TILE_MODE27__MICRO_TILE_MODE_NEW__SHIFT 0x16
5227#define GB_TILE_MODE27__SAMPLE_SPLIT_MASK 0x6000000
5228#define GB_TILE_MODE27__SAMPLE_SPLIT__SHIFT 0x19
5229#define GB_TILE_MODE28__ARRAY_MODE_MASK 0x3c
5230#define GB_TILE_MODE28__ARRAY_MODE__SHIFT 0x2
5231#define GB_TILE_MODE28__PIPE_CONFIG_MASK 0x7c0
5232#define GB_TILE_MODE28__PIPE_CONFIG__SHIFT 0x6
5233#define GB_TILE_MODE28__TILE_SPLIT_MASK 0x3800
5234#define GB_TILE_MODE28__TILE_SPLIT__SHIFT 0xb
5235#define GB_TILE_MODE28__MICRO_TILE_MODE_NEW_MASK 0x1c00000
5236#define GB_TILE_MODE28__MICRO_TILE_MODE_NEW__SHIFT 0x16
5237#define GB_TILE_MODE28__SAMPLE_SPLIT_MASK 0x6000000
5238#define GB_TILE_MODE28__SAMPLE_SPLIT__SHIFT 0x19
5239#define GB_TILE_MODE29__ARRAY_MODE_MASK 0x3c
5240#define GB_TILE_MODE29__ARRAY_MODE__SHIFT 0x2
5241#define GB_TILE_MODE29__PIPE_CONFIG_MASK 0x7c0
5242#define GB_TILE_MODE29__PIPE_CONFIG__SHIFT 0x6
5243#define GB_TILE_MODE29__TILE_SPLIT_MASK 0x3800
5244#define GB_TILE_MODE29__TILE_SPLIT__SHIFT 0xb
5245#define GB_TILE_MODE29__MICRO_TILE_MODE_NEW_MASK 0x1c00000
5246#define GB_TILE_MODE29__MICRO_TILE_MODE_NEW__SHIFT 0x16
5247#define GB_TILE_MODE29__SAMPLE_SPLIT_MASK 0x6000000
5248#define GB_TILE_MODE29__SAMPLE_SPLIT__SHIFT 0x19
5249#define GB_TILE_MODE30__ARRAY_MODE_MASK 0x3c
5250#define GB_TILE_MODE30__ARRAY_MODE__SHIFT 0x2
5251#define GB_TILE_MODE30__PIPE_CONFIG_MASK 0x7c0
5252#define GB_TILE_MODE30__PIPE_CONFIG__SHIFT 0x6
5253#define GB_TILE_MODE30__TILE_SPLIT_MASK 0x3800
5254#define GB_TILE_MODE30__TILE_SPLIT__SHIFT 0xb
5255#define GB_TILE_MODE30__MICRO_TILE_MODE_NEW_MASK 0x1c00000
5256#define GB_TILE_MODE30__MICRO_TILE_MODE_NEW__SHIFT 0x16
5257#define GB_TILE_MODE30__SAMPLE_SPLIT_MASK 0x6000000
5258#define GB_TILE_MODE30__SAMPLE_SPLIT__SHIFT 0x19
5259#define GB_TILE_MODE31__ARRAY_MODE_MASK 0x3c
5260#define GB_TILE_MODE31__ARRAY_MODE__SHIFT 0x2
5261#define GB_TILE_MODE31__PIPE_CONFIG_MASK 0x7c0
5262#define GB_TILE_MODE31__PIPE_CONFIG__SHIFT 0x6
5263#define GB_TILE_MODE31__TILE_SPLIT_MASK 0x3800
5264#define GB_TILE_MODE31__TILE_SPLIT__SHIFT 0xb
5265#define GB_TILE_MODE31__MICRO_TILE_MODE_NEW_MASK 0x1c00000
5266#define GB_TILE_MODE31__MICRO_TILE_MODE_NEW__SHIFT 0x16
5267#define GB_TILE_MODE31__SAMPLE_SPLIT_MASK 0x6000000
5268#define GB_TILE_MODE31__SAMPLE_SPLIT__SHIFT 0x19
5269#define GB_MACROTILE_MODE0__BANK_WIDTH_MASK 0x3
5270#define GB_MACROTILE_MODE0__BANK_WIDTH__SHIFT 0x0
5271#define GB_MACROTILE_MODE0__BANK_HEIGHT_MASK 0xc
5272#define GB_MACROTILE_MODE0__BANK_HEIGHT__SHIFT 0x2
5273#define GB_MACROTILE_MODE0__MACRO_TILE_ASPECT_MASK 0x30
5274#define GB_MACROTILE_MODE0__MACRO_TILE_ASPECT__SHIFT 0x4
5275#define GB_MACROTILE_MODE0__NUM_BANKS_MASK 0xc0
5276#define GB_MACROTILE_MODE0__NUM_BANKS__SHIFT 0x6
5277#define GB_MACROTILE_MODE1__BANK_WIDTH_MASK 0x3
5278#define GB_MACROTILE_MODE1__BANK_WIDTH__SHIFT 0x0
5279#define GB_MACROTILE_MODE1__BANK_HEIGHT_MASK 0xc
5280#define GB_MACROTILE_MODE1__BANK_HEIGHT__SHIFT 0x2
5281#define GB_MACROTILE_MODE1__MACRO_TILE_ASPECT_MASK 0x30
5282#define GB_MACROTILE_MODE1__MACRO_TILE_ASPECT__SHIFT 0x4
5283#define GB_MACROTILE_MODE1__NUM_BANKS_MASK 0xc0
5284#define GB_MACROTILE_MODE1__NUM_BANKS__SHIFT 0x6
5285#define GB_MACROTILE_MODE2__BANK_WIDTH_MASK 0x3
5286#define GB_MACROTILE_MODE2__BANK_WIDTH__SHIFT 0x0
5287#define GB_MACROTILE_MODE2__BANK_HEIGHT_MASK 0xc
5288#define GB_MACROTILE_MODE2__BANK_HEIGHT__SHIFT 0x2
5289#define GB_MACROTILE_MODE2__MACRO_TILE_ASPECT_MASK 0x30
5290#define GB_MACROTILE_MODE2__MACRO_TILE_ASPECT__SHIFT 0x4
5291#define GB_MACROTILE_MODE2__NUM_BANKS_MASK 0xc0
5292#define GB_MACROTILE_MODE2__NUM_BANKS__SHIFT 0x6
5293#define GB_MACROTILE_MODE3__BANK_WIDTH_MASK 0x3
5294#define GB_MACROTILE_MODE3__BANK_WIDTH__SHIFT 0x0
5295#define GB_MACROTILE_MODE3__BANK_HEIGHT_MASK 0xc
5296#define GB_MACROTILE_MODE3__BANK_HEIGHT__SHIFT 0x2
5297#define GB_MACROTILE_MODE3__MACRO_TILE_ASPECT_MASK 0x30
5298#define GB_MACROTILE_MODE3__MACRO_TILE_ASPECT__SHIFT 0x4
5299#define GB_MACROTILE_MODE3__NUM_BANKS_MASK 0xc0
5300#define GB_MACROTILE_MODE3__NUM_BANKS__SHIFT 0x6
5301#define GB_MACROTILE_MODE4__BANK_WIDTH_MASK 0x3
5302#define GB_MACROTILE_MODE4__BANK_WIDTH__SHIFT 0x0
5303#define GB_MACROTILE_MODE4__BANK_HEIGHT_MASK 0xc
5304#define GB_MACROTILE_MODE4__BANK_HEIGHT__SHIFT 0x2
5305#define GB_MACROTILE_MODE4__MACRO_TILE_ASPECT_MASK 0x30
5306#define GB_MACROTILE_MODE4__MACRO_TILE_ASPECT__SHIFT 0x4
5307#define GB_MACROTILE_MODE4__NUM_BANKS_MASK 0xc0
5308#define GB_MACROTILE_MODE4__NUM_BANKS__SHIFT 0x6
5309#define GB_MACROTILE_MODE5__BANK_WIDTH_MASK 0x3
5310#define GB_MACROTILE_MODE5__BANK_WIDTH__SHIFT 0x0
5311#define GB_MACROTILE_MODE5__BANK_HEIGHT_MASK 0xc
5312#define GB_MACROTILE_MODE5__BANK_HEIGHT__SHIFT 0x2
5313#define GB_MACROTILE_MODE5__MACRO_TILE_ASPECT_MASK 0x30
5314#define GB_MACROTILE_MODE5__MACRO_TILE_ASPECT__SHIFT 0x4
5315#define GB_MACROTILE_MODE5__NUM_BANKS_MASK 0xc0
5316#define GB_MACROTILE_MODE5__NUM_BANKS__SHIFT 0x6
5317#define GB_MACROTILE_MODE6__BANK_WIDTH_MASK 0x3
5318#define GB_MACROTILE_MODE6__BANK_WIDTH__SHIFT 0x0
5319#define GB_MACROTILE_MODE6__BANK_HEIGHT_MASK 0xc
5320#define GB_MACROTILE_MODE6__BANK_HEIGHT__SHIFT 0x2
5321#define GB_MACROTILE_MODE6__MACRO_TILE_ASPECT_MASK 0x30
5322#define GB_MACROTILE_MODE6__MACRO_TILE_ASPECT__SHIFT 0x4
5323#define GB_MACROTILE_MODE6__NUM_BANKS_MASK 0xc0
5324#define GB_MACROTILE_MODE6__NUM_BANKS__SHIFT 0x6
5325#define GB_MACROTILE_MODE7__BANK_WIDTH_MASK 0x3
5326#define GB_MACROTILE_MODE7__BANK_WIDTH__SHIFT 0x0
5327#define GB_MACROTILE_MODE7__BANK_HEIGHT_MASK 0xc
5328#define GB_MACROTILE_MODE7__BANK_HEIGHT__SHIFT 0x2
5329#define GB_MACROTILE_MODE7__MACRO_TILE_ASPECT_MASK 0x30
5330#define GB_MACROTILE_MODE7__MACRO_TILE_ASPECT__SHIFT 0x4
5331#define GB_MACROTILE_MODE7__NUM_BANKS_MASK 0xc0
5332#define GB_MACROTILE_MODE7__NUM_BANKS__SHIFT 0x6
5333#define GB_MACROTILE_MODE8__BANK_WIDTH_MASK 0x3
5334#define GB_MACROTILE_MODE8__BANK_WIDTH__SHIFT 0x0
5335#define GB_MACROTILE_MODE8__BANK_HEIGHT_MASK 0xc
5336#define GB_MACROTILE_MODE8__BANK_HEIGHT__SHIFT 0x2
5337#define GB_MACROTILE_MODE8__MACRO_TILE_ASPECT_MASK 0x30
5338#define GB_MACROTILE_MODE8__MACRO_TILE_ASPECT__SHIFT 0x4
5339#define GB_MACROTILE_MODE8__NUM_BANKS_MASK 0xc0
5340#define GB_MACROTILE_MODE8__NUM_BANKS__SHIFT 0x6
5341#define GB_MACROTILE_MODE9__BANK_WIDTH_MASK 0x3
5342#define GB_MACROTILE_MODE9__BANK_WIDTH__SHIFT 0x0
5343#define GB_MACROTILE_MODE9__BANK_HEIGHT_MASK 0xc
5344#define GB_MACROTILE_MODE9__BANK_HEIGHT__SHIFT 0x2
5345#define GB_MACROTILE_MODE9__MACRO_TILE_ASPECT_MASK 0x30
5346#define GB_MACROTILE_MODE9__MACRO_TILE_ASPECT__SHIFT 0x4
5347#define GB_MACROTILE_MODE9__NUM_BANKS_MASK 0xc0
5348#define GB_MACROTILE_MODE9__NUM_BANKS__SHIFT 0x6
5349#define GB_MACROTILE_MODE10__BANK_WIDTH_MASK 0x3
5350#define GB_MACROTILE_MODE10__BANK_WIDTH__SHIFT 0x0
5351#define GB_MACROTILE_MODE10__BANK_HEIGHT_MASK 0xc
5352#define GB_MACROTILE_MODE10__BANK_HEIGHT__SHIFT 0x2
5353#define GB_MACROTILE_MODE10__MACRO_TILE_ASPECT_MASK 0x30
5354#define GB_MACROTILE_MODE10__MACRO_TILE_ASPECT__SHIFT 0x4
5355#define GB_MACROTILE_MODE10__NUM_BANKS_MASK 0xc0
5356#define GB_MACROTILE_MODE10__NUM_BANKS__SHIFT 0x6
5357#define GB_MACROTILE_MODE11__BANK_WIDTH_MASK 0x3
5358#define GB_MACROTILE_MODE11__BANK_WIDTH__SHIFT 0x0
5359#define GB_MACROTILE_MODE11__BANK_HEIGHT_MASK 0xc
5360#define GB_MACROTILE_MODE11__BANK_HEIGHT__SHIFT 0x2
5361#define GB_MACROTILE_MODE11__MACRO_TILE_ASPECT_MASK 0x30
5362#define GB_MACROTILE_MODE11__MACRO_TILE_ASPECT__SHIFT 0x4
5363#define GB_MACROTILE_MODE11__NUM_BANKS_MASK 0xc0
5364#define GB_MACROTILE_MODE11__NUM_BANKS__SHIFT 0x6
5365#define GB_MACROTILE_MODE12__BANK_WIDTH_MASK 0x3
5366#define GB_MACROTILE_MODE12__BANK_WIDTH__SHIFT 0x0
5367#define GB_MACROTILE_MODE12__BANK_HEIGHT_MASK 0xc
5368#define GB_MACROTILE_MODE12__BANK_HEIGHT__SHIFT 0x2
5369#define GB_MACROTILE_MODE12__MACRO_TILE_ASPECT_MASK 0x30
5370#define GB_MACROTILE_MODE12__MACRO_TILE_ASPECT__SHIFT 0x4
5371#define GB_MACROTILE_MODE12__NUM_BANKS_MASK 0xc0
5372#define GB_MACROTILE_MODE12__NUM_BANKS__SHIFT 0x6
5373#define GB_MACROTILE_MODE13__BANK_WIDTH_MASK 0x3
5374#define GB_MACROTILE_MODE13__BANK_WIDTH__SHIFT 0x0
5375#define GB_MACROTILE_MODE13__BANK_HEIGHT_MASK 0xc
5376#define GB_MACROTILE_MODE13__BANK_HEIGHT__SHIFT 0x2
5377#define GB_MACROTILE_MODE13__MACRO_TILE_ASPECT_MASK 0x30
5378#define GB_MACROTILE_MODE13__MACRO_TILE_ASPECT__SHIFT 0x4
5379#define GB_MACROTILE_MODE13__NUM_BANKS_MASK 0xc0
5380#define GB_MACROTILE_MODE13__NUM_BANKS__SHIFT 0x6
5381#define GB_MACROTILE_MODE14__BANK_WIDTH_MASK 0x3
5382#define GB_MACROTILE_MODE14__BANK_WIDTH__SHIFT 0x0
5383#define GB_MACROTILE_MODE14__BANK_HEIGHT_MASK 0xc
5384#define GB_MACROTILE_MODE14__BANK_HEIGHT__SHIFT 0x2
5385#define GB_MACROTILE_MODE14__MACRO_TILE_ASPECT_MASK 0x30
5386#define GB_MACROTILE_MODE14__MACRO_TILE_ASPECT__SHIFT 0x4
5387#define GB_MACROTILE_MODE14__NUM_BANKS_MASK 0xc0
5388#define GB_MACROTILE_MODE14__NUM_BANKS__SHIFT 0x6
5389#define GB_MACROTILE_MODE15__BANK_WIDTH_MASK 0x3
5390#define GB_MACROTILE_MODE15__BANK_WIDTH__SHIFT 0x0
5391#define GB_MACROTILE_MODE15__BANK_HEIGHT_MASK 0xc
5392#define GB_MACROTILE_MODE15__BANK_HEIGHT__SHIFT 0x2
5393#define GB_MACROTILE_MODE15__MACRO_TILE_ASPECT_MASK 0x30
5394#define GB_MACROTILE_MODE15__MACRO_TILE_ASPECT__SHIFT 0x4
5395#define GB_MACROTILE_MODE15__NUM_BANKS_MASK 0xc0
5396#define GB_MACROTILE_MODE15__NUM_BANKS__SHIFT 0x6
5397#define GB_EDC_MODE__FORCE_SEC_ON_DED_MASK 0x10000
5398#define GB_EDC_MODE__FORCE_SEC_ON_DED__SHIFT 0x10
5399#define GB_EDC_MODE__DED_MODE_MASK 0x300000
5400#define GB_EDC_MODE__DED_MODE__SHIFT 0x14
5401#define GB_EDC_MODE__PROP_FED_MASK 0x20000000
5402#define GB_EDC_MODE__PROP_FED__SHIFT 0x1d
5403#define GB_EDC_MODE__BYPASS_MASK 0x80000000
5404#define GB_EDC_MODE__BYPASS__SHIFT 0x1f
5405#define CC_GC_EDC_CONFIG__DIS_EDC_MASK 0x2
5406#define CC_GC_EDC_CONFIG__DIS_EDC__SHIFT 0x1
5407#define RAS_SIGNATURE_CONTROL__ENABLE_MASK 0x1
5408#define RAS_SIGNATURE_CONTROL__ENABLE__SHIFT 0x0
5409#define RAS_SIGNATURE_MASK__INPUT_BUS_MASK_MASK 0xffffffff
5410#define RAS_SIGNATURE_MASK__INPUT_BUS_MASK__SHIFT 0x0
5411#define RAS_SX_SIGNATURE0__SIGNATURE_MASK 0xffffffff
5412#define RAS_SX_SIGNATURE0__SIGNATURE__SHIFT 0x0
5413#define RAS_SX_SIGNATURE1__SIGNATURE_MASK 0xffffffff
5414#define RAS_SX_SIGNATURE1__SIGNATURE__SHIFT 0x0
5415#define RAS_SX_SIGNATURE2__SIGNATURE_MASK 0xffffffff
5416#define RAS_SX_SIGNATURE2__SIGNATURE__SHIFT 0x0
5417#define RAS_SX_SIGNATURE3__SIGNATURE_MASK 0xffffffff
5418#define RAS_SX_SIGNATURE3__SIGNATURE__SHIFT 0x0
5419#define RAS_DB_SIGNATURE0__SIGNATURE_MASK 0xffffffff
5420#define RAS_DB_SIGNATURE0__SIGNATURE__SHIFT 0x0
5421#define RAS_PA_SIGNATURE0__SIGNATURE_MASK 0xffffffff
5422#define RAS_PA_SIGNATURE0__SIGNATURE__SHIFT 0x0
5423#define RAS_VGT_SIGNATURE0__SIGNATURE_MASK 0xffffffff
5424#define RAS_VGT_SIGNATURE0__SIGNATURE__SHIFT 0x0
5425#define RAS_SQ_SIGNATURE0__SIGNATURE_MASK 0xffffffff
5426#define RAS_SQ_SIGNATURE0__SIGNATURE__SHIFT 0x0
5427#define RAS_SC_SIGNATURE0__SIGNATURE_MASK 0xffffffff
5428#define RAS_SC_SIGNATURE0__SIGNATURE__SHIFT 0x0
5429#define RAS_SC_SIGNATURE1__SIGNATURE_MASK 0xffffffff
5430#define RAS_SC_SIGNATURE1__SIGNATURE__SHIFT 0x0
5431#define RAS_SC_SIGNATURE2__SIGNATURE_MASK 0xffffffff
5432#define RAS_SC_SIGNATURE2__SIGNATURE__SHIFT 0x0
5433#define RAS_SC_SIGNATURE3__SIGNATURE_MASK 0xffffffff
5434#define RAS_SC_SIGNATURE3__SIGNATURE__SHIFT 0x0
5435#define RAS_SC_SIGNATURE4__SIGNATURE_MASK 0xffffffff
5436#define RAS_SC_SIGNATURE4__SIGNATURE__SHIFT 0x0
5437#define RAS_SC_SIGNATURE5__SIGNATURE_MASK 0xffffffff
5438#define RAS_SC_SIGNATURE5__SIGNATURE__SHIFT 0x0
5439#define RAS_SC_SIGNATURE6__SIGNATURE_MASK 0xffffffff
5440#define RAS_SC_SIGNATURE6__SIGNATURE__SHIFT 0x0
5441#define RAS_SC_SIGNATURE7__SIGNATURE_MASK 0xffffffff
5442#define RAS_SC_SIGNATURE7__SIGNATURE__SHIFT 0x0
5443#define RAS_IA_SIGNATURE0__SIGNATURE_MASK 0xffffffff
5444#define RAS_IA_SIGNATURE0__SIGNATURE__SHIFT 0x0
5445#define RAS_IA_SIGNATURE1__SIGNATURE_MASK 0xffffffff
5446#define RAS_IA_SIGNATURE1__SIGNATURE__SHIFT 0x0
5447#define RAS_SPI_SIGNATURE0__SIGNATURE_MASK 0xffffffff
5448#define RAS_SPI_SIGNATURE0__SIGNATURE__SHIFT 0x0
5449#define RAS_SPI_SIGNATURE1__SIGNATURE_MASK 0xffffffff
5450#define RAS_SPI_SIGNATURE1__SIGNATURE__SHIFT 0x0
5451#define RAS_TA_SIGNATURE0__SIGNATURE_MASK 0xffffffff
5452#define RAS_TA_SIGNATURE0__SIGNATURE__SHIFT 0x0
5453#define RAS_TD_SIGNATURE0__SIGNATURE_MASK 0xffffffff
5454#define RAS_TD_SIGNATURE0__SIGNATURE__SHIFT 0x0
5455#define RAS_CB_SIGNATURE0__SIGNATURE_MASK 0xffffffff
5456#define RAS_CB_SIGNATURE0__SIGNATURE__SHIFT 0x0
5457#define RAS_BCI_SIGNATURE0__SIGNATURE_MASK 0xffffffff
5458#define RAS_BCI_SIGNATURE0__SIGNATURE__SHIFT 0x0
5459#define RAS_BCI_SIGNATURE1__SIGNATURE_MASK 0xffffffff
5460#define RAS_BCI_SIGNATURE1__SIGNATURE__SHIFT 0x0
5461#define RAS_TA_SIGNATURE1__SIGNATURE_MASK 0xffffffff
5462#define RAS_TA_SIGNATURE1__SIGNATURE__SHIFT 0x0
5463#define GRBM_HYP_CAM_INDEX__CAM_INDEX_MASK 0x7
5464#define GRBM_HYP_CAM_INDEX__CAM_INDEX__SHIFT 0x0
5465#define GRBM_CAM_INDEX__CAM_INDEX_MASK 0x7
5466#define GRBM_CAM_INDEX__CAM_INDEX__SHIFT 0x0
5467#define GRBM_HYP_CAM_DATA__CAM_ADDR_MASK 0xffff
5468#define GRBM_HYP_CAM_DATA__CAM_ADDR__SHIFT 0x0
5469#define GRBM_HYP_CAM_DATA__CAM_REMAPADDR_MASK 0xffff0000
5470#define GRBM_HYP_CAM_DATA__CAM_REMAPADDR__SHIFT 0x10
5471#define GRBM_CAM_DATA__CAM_ADDR_MASK 0xffff
5472#define GRBM_CAM_DATA__CAM_ADDR__SHIFT 0x0
5473#define GRBM_CAM_DATA__CAM_REMAPADDR_MASK 0xffff0000
5474#define GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT 0x10
5475#define GRBM_CNTL__READ_TIMEOUT_MASK 0xff
5476#define GRBM_CNTL__READ_TIMEOUT__SHIFT 0x0
5477#define GRBM_CNTL__REPORT_LAST_RDERR_MASK 0x80000000
5478#define GRBM_CNTL__REPORT_LAST_RDERR__SHIFT 0x1f
5479#define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD_MASK 0x3f
5480#define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD__SHIFT 0x0
5481#define GRBM_SKEW_CNTL__SKEW_COUNT_MASK 0xfc0
5482#define GRBM_SKEW_CNTL__SKEW_COUNT__SHIFT 0x6
5483#define GRBM_PWR_CNTL__ALL_REQ_TYPE_MASK 0x3
5484#define GRBM_PWR_CNTL__ALL_REQ_TYPE__SHIFT 0x0
5485#define GRBM_PWR_CNTL__GFX_REQ_TYPE_MASK 0xc
5486#define GRBM_PWR_CNTL__GFX_REQ_TYPE__SHIFT 0x2
5487#define GRBM_PWR_CNTL__ALL_RSP_TYPE_MASK 0x30
5488#define GRBM_PWR_CNTL__ALL_RSP_TYPE__SHIFT 0x4
5489#define GRBM_PWR_CNTL__GFX_RSP_TYPE_MASK 0xc0
5490#define GRBM_PWR_CNTL__GFX_RSP_TYPE__SHIFT 0x6
5491#define GRBM_PWR_CNTL__GFX_REQ_EN_MASK 0x4000
5492#define GRBM_PWR_CNTL__GFX_REQ_EN__SHIFT 0xe
5493#define GRBM_PWR_CNTL__ALL_REQ_EN_MASK 0x8000
5494#define GRBM_PWR_CNTL__ALL_REQ_EN__SHIFT 0xf
5495#define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL_MASK 0xf
5496#define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL__SHIFT 0x0
5497#define GRBM_STATUS__SRBM_RQ_PENDING_MASK 0x20
5498#define GRBM_STATUS__SRBM_RQ_PENDING__SHIFT 0x5
5499#define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING_MASK 0x80
5500#define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING__SHIFT 0x7
5501#define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING_MASK 0x100
5502#define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING__SHIFT 0x8
5503#define GRBM_STATUS__GDS_DMA_RQ_PENDING_MASK 0x200
5504#define GRBM_STATUS__GDS_DMA_RQ_PENDING__SHIFT 0x9
5505#define GRBM_STATUS__DB_CLEAN_MASK 0x1000
5506#define GRBM_STATUS__DB_CLEAN__SHIFT 0xc
5507#define GRBM_STATUS__CB_CLEAN_MASK 0x2000
5508#define GRBM_STATUS__CB_CLEAN__SHIFT 0xd
5509#define GRBM_STATUS__TA_BUSY_MASK 0x4000
5510#define GRBM_STATUS__TA_BUSY__SHIFT 0xe
5511#define GRBM_STATUS__GDS_BUSY_MASK 0x8000
5512#define GRBM_STATUS__GDS_BUSY__SHIFT 0xf
5513#define GRBM_STATUS__WD_BUSY_NO_DMA_MASK 0x10000
5514#define GRBM_STATUS__WD_BUSY_NO_DMA__SHIFT 0x10
5515#define GRBM_STATUS__VGT_BUSY_MASK 0x20000
5516#define GRBM_STATUS__VGT_BUSY__SHIFT 0x11
5517#define GRBM_STATUS__IA_BUSY_NO_DMA_MASK 0x40000
5518#define GRBM_STATUS__IA_BUSY_NO_DMA__SHIFT 0x12
5519#define GRBM_STATUS__IA_BUSY_MASK 0x80000
5520#define GRBM_STATUS__IA_BUSY__SHIFT 0x13
5521#define GRBM_STATUS__SX_BUSY_MASK 0x100000
5522#define GRBM_STATUS__SX_BUSY__SHIFT 0x14
5523#define GRBM_STATUS__WD_BUSY_MASK 0x200000
5524#define GRBM_STATUS__WD_BUSY__SHIFT 0x15
5525#define GRBM_STATUS__SPI_BUSY_MASK 0x400000
5526#define GRBM_STATUS__SPI_BUSY__SHIFT 0x16
5527#define GRBM_STATUS__BCI_BUSY_MASK 0x800000
5528#define GRBM_STATUS__BCI_BUSY__SHIFT 0x17
5529#define GRBM_STATUS__SC_BUSY_MASK 0x1000000
5530#define GRBM_STATUS__SC_BUSY__SHIFT 0x18
5531#define GRBM_STATUS__PA_BUSY_MASK 0x2000000
5532#define GRBM_STATUS__PA_BUSY__SHIFT 0x19
5533#define GRBM_STATUS__DB_BUSY_MASK 0x4000000
5534#define GRBM_STATUS__DB_BUSY__SHIFT 0x1a
5535#define GRBM_STATUS__CP_COHERENCY_BUSY_MASK 0x10000000
5536#define GRBM_STATUS__CP_COHERENCY_BUSY__SHIFT 0x1c
5537#define GRBM_STATUS__CP_BUSY_MASK 0x20000000
5538#define GRBM_STATUS__CP_BUSY__SHIFT 0x1d
5539#define GRBM_STATUS__CB_BUSY_MASK 0x40000000
5540#define GRBM_STATUS__CB_BUSY__SHIFT 0x1e
5541#define GRBM_STATUS__GUI_ACTIVE_MASK 0x80000000
5542#define GRBM_STATUS__GUI_ACTIVE__SHIFT 0x1f
5543#define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL_MASK 0xf
5544#define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL__SHIFT 0x0
5545#define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING_MASK 0x10
5546#define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING__SHIFT 0x4
5547#define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING_MASK 0x20
5548#define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING__SHIFT 0x5
5549#define GRBM_STATUS2__ME1PIPE0_RQ_PENDING_MASK 0x40
5550#define GRBM_STATUS2__ME1PIPE0_RQ_PENDING__SHIFT 0x6
5551#define GRBM_STATUS2__ME1PIPE1_RQ_PENDING_MASK 0x80
5552#define GRBM_STATUS2__ME1PIPE1_RQ_PENDING__SHIFT 0x7
5553#define GRBM_STATUS2__ME1PIPE2_RQ_PENDING_MASK 0x100
5554#define GRBM_STATUS2__ME1PIPE2_RQ_PENDING__SHIFT 0x8
5555#define GRBM_STATUS2__ME1PIPE3_RQ_PENDING_MASK 0x200
5556#define GRBM_STATUS2__ME1PIPE3_RQ_PENDING__SHIFT 0x9
5557#define GRBM_STATUS2__ME2PIPE0_RQ_PENDING_MASK 0x400
5558#define GRBM_STATUS2__ME2PIPE0_RQ_PENDING__SHIFT 0xa
5559#define GRBM_STATUS2__ME2PIPE1_RQ_PENDING_MASK 0x800
5560#define GRBM_STATUS2__ME2PIPE1_RQ_PENDING__SHIFT 0xb
5561#define GRBM_STATUS2__ME2PIPE2_RQ_PENDING_MASK 0x1000
5562#define GRBM_STATUS2__ME2PIPE2_RQ_PENDING__SHIFT 0xc
5563#define GRBM_STATUS2__ME2PIPE3_RQ_PENDING_MASK 0x2000
5564#define GRBM_STATUS2__ME2PIPE3_RQ_PENDING__SHIFT 0xd
5565#define GRBM_STATUS2__RLC_RQ_PENDING_MASK 0x4000
5566#define GRBM_STATUS2__RLC_RQ_PENDING__SHIFT 0xe
5567#define GRBM_STATUS2__RLC_BUSY_MASK 0x1000000
5568#define GRBM_STATUS2__RLC_BUSY__SHIFT 0x18
5569#define GRBM_STATUS2__TC_BUSY_MASK 0x2000000
5570#define GRBM_STATUS2__TC_BUSY__SHIFT 0x19
5571#define GRBM_STATUS2__TCC_CC_RESIDENT_MASK 0x4000000
5572#define GRBM_STATUS2__TCC_CC_RESIDENT__SHIFT 0x1a
5573#define GRBM_STATUS2__CPF_BUSY_MASK 0x10000000
5574#define GRBM_STATUS2__CPF_BUSY__SHIFT 0x1c
5575#define GRBM_STATUS2__CPC_BUSY_MASK 0x20000000
5576#define GRBM_STATUS2__CPC_BUSY__SHIFT 0x1d
5577#define GRBM_STATUS2__CPG_BUSY_MASK 0x40000000
5578#define GRBM_STATUS2__CPG_BUSY__SHIFT 0x1e
5579#define GRBM_STATUS_SE0__DB_CLEAN_MASK 0x2
5580#define GRBM_STATUS_SE0__DB_CLEAN__SHIFT 0x1
5581#define GRBM_STATUS_SE0__CB_CLEAN_MASK 0x4
5582#define GRBM_STATUS_SE0__CB_CLEAN__SHIFT 0x2
5583#define GRBM_STATUS_SE0__BCI_BUSY_MASK 0x400000
5584#define GRBM_STATUS_SE0__BCI_BUSY__SHIFT 0x16
5585#define GRBM_STATUS_SE0__VGT_BUSY_MASK 0x800000
5586#define GRBM_STATUS_SE0__VGT_BUSY__SHIFT 0x17
5587#define GRBM_STATUS_SE0__PA_BUSY_MASK 0x1000000
5588#define GRBM_STATUS_SE0__PA_BUSY__SHIFT 0x18
5589#define GRBM_STATUS_SE0__TA_BUSY_MASK 0x2000000
5590#define GRBM_STATUS_SE0__TA_BUSY__SHIFT 0x19
5591#define GRBM_STATUS_SE0__SX_BUSY_MASK 0x4000000
5592#define GRBM_STATUS_SE0__SX_BUSY__SHIFT 0x1a
5593#define GRBM_STATUS_SE0__SPI_BUSY_MASK 0x8000000
5594#define GRBM_STATUS_SE0__SPI_BUSY__SHIFT 0x1b
5595#define GRBM_STATUS_SE0__SC_BUSY_MASK 0x20000000
5596#define GRBM_STATUS_SE0__SC_BUSY__SHIFT 0x1d
5597#define GRBM_STATUS_SE0__DB_BUSY_MASK 0x40000000
5598#define GRBM_STATUS_SE0__DB_BUSY__SHIFT 0x1e
5599#define GRBM_STATUS_SE0__CB_BUSY_MASK 0x80000000
5600#define GRBM_STATUS_SE0__CB_BUSY__SHIFT 0x1f
5601#define GRBM_STATUS_SE1__DB_CLEAN_MASK 0x2
5602#define GRBM_STATUS_SE1__DB_CLEAN__SHIFT 0x1
5603#define GRBM_STATUS_SE1__CB_CLEAN_MASK 0x4
5604#define GRBM_STATUS_SE1__CB_CLEAN__SHIFT 0x2
5605#define GRBM_STATUS_SE1__BCI_BUSY_MASK 0x400000
5606#define GRBM_STATUS_SE1__BCI_BUSY__SHIFT 0x16
5607#define GRBM_STATUS_SE1__VGT_BUSY_MASK 0x800000
5608#define GRBM_STATUS_SE1__VGT_BUSY__SHIFT 0x17
5609#define GRBM_STATUS_SE1__PA_BUSY_MASK 0x1000000
5610#define GRBM_STATUS_SE1__PA_BUSY__SHIFT 0x18
5611#define GRBM_STATUS_SE1__TA_BUSY_MASK 0x2000000
5612#define GRBM_STATUS_SE1__TA_BUSY__SHIFT 0x19
5613#define GRBM_STATUS_SE1__SX_BUSY_MASK 0x4000000
5614#define GRBM_STATUS_SE1__SX_BUSY__SHIFT 0x1a
5615#define GRBM_STATUS_SE1__SPI_BUSY_MASK 0x8000000
5616#define GRBM_STATUS_SE1__SPI_BUSY__SHIFT 0x1b
5617#define GRBM_STATUS_SE1__SC_BUSY_MASK 0x20000000
5618#define GRBM_STATUS_SE1__SC_BUSY__SHIFT 0x1d
5619#define GRBM_STATUS_SE1__DB_BUSY_MASK 0x40000000
5620#define GRBM_STATUS_SE1__DB_BUSY__SHIFT 0x1e
5621#define GRBM_STATUS_SE1__CB_BUSY_MASK 0x80000000
5622#define GRBM_STATUS_SE1__CB_BUSY__SHIFT 0x1f
5623#define GRBM_STATUS_SE2__DB_CLEAN_MASK 0x2
5624#define GRBM_STATUS_SE2__DB_CLEAN__SHIFT 0x1
5625#define GRBM_STATUS_SE2__CB_CLEAN_MASK 0x4
5626#define GRBM_STATUS_SE2__CB_CLEAN__SHIFT 0x2
5627#define GRBM_STATUS_SE2__BCI_BUSY_MASK 0x400000
5628#define GRBM_STATUS_SE2__BCI_BUSY__SHIFT 0x16
5629#define GRBM_STATUS_SE2__VGT_BUSY_MASK 0x800000
5630#define GRBM_STATUS_SE2__VGT_BUSY__SHIFT 0x17
5631#define GRBM_STATUS_SE2__PA_BUSY_MASK 0x1000000
5632#define GRBM_STATUS_SE2__PA_BUSY__SHIFT 0x18
5633#define GRBM_STATUS_SE2__TA_BUSY_MASK 0x2000000
5634#define GRBM_STATUS_SE2__TA_BUSY__SHIFT 0x19
5635#define GRBM_STATUS_SE2__SX_BUSY_MASK 0x4000000
5636#define GRBM_STATUS_SE2__SX_BUSY__SHIFT 0x1a
5637#define GRBM_STATUS_SE2__SPI_BUSY_MASK 0x8000000
5638#define GRBM_STATUS_SE2__SPI_BUSY__SHIFT 0x1b
5639#define GRBM_STATUS_SE2__SC_BUSY_MASK 0x20000000
5640#define GRBM_STATUS_SE2__SC_BUSY__SHIFT 0x1d
5641#define GRBM_STATUS_SE2__DB_BUSY_MASK 0x40000000
5642#define GRBM_STATUS_SE2__DB_BUSY__SHIFT 0x1e
5643#define GRBM_STATUS_SE2__CB_BUSY_MASK 0x80000000
5644#define GRBM_STATUS_SE2__CB_BUSY__SHIFT 0x1f
5645#define GRBM_STATUS_SE3__DB_CLEAN_MASK 0x2
5646#define GRBM_STATUS_SE3__DB_CLEAN__SHIFT 0x1
5647#define GRBM_STATUS_SE3__CB_CLEAN_MASK 0x4
5648#define GRBM_STATUS_SE3__CB_CLEAN__SHIFT 0x2
5649#define GRBM_STATUS_SE3__BCI_BUSY_MASK 0x400000
5650#define GRBM_STATUS_SE3__BCI_BUSY__SHIFT 0x16
5651#define GRBM_STATUS_SE3__VGT_BUSY_MASK 0x800000
5652#define GRBM_STATUS_SE3__VGT_BUSY__SHIFT 0x17
5653#define GRBM_STATUS_SE3__PA_BUSY_MASK 0x1000000
5654#define GRBM_STATUS_SE3__PA_BUSY__SHIFT 0x18
5655#define GRBM_STATUS_SE3__TA_BUSY_MASK 0x2000000
5656#define GRBM_STATUS_SE3__TA_BUSY__SHIFT 0x19
5657#define GRBM_STATUS_SE3__SX_BUSY_MASK 0x4000000
5658#define GRBM_STATUS_SE3__SX_BUSY__SHIFT 0x1a
5659#define GRBM_STATUS_SE3__SPI_BUSY_MASK 0x8000000
5660#define GRBM_STATUS_SE3__SPI_BUSY__SHIFT 0x1b
5661#define GRBM_STATUS_SE3__SC_BUSY_MASK 0x20000000
5662#define GRBM_STATUS_SE3__SC_BUSY__SHIFT 0x1d
5663#define GRBM_STATUS_SE3__DB_BUSY_MASK 0x40000000
5664#define GRBM_STATUS_SE3__DB_BUSY__SHIFT 0x1e
5665#define GRBM_STATUS_SE3__CB_BUSY_MASK 0x80000000
5666#define GRBM_STATUS_SE3__CB_BUSY__SHIFT 0x1f
5667#define GRBM_SOFT_RESET__SOFT_RESET_CP_MASK 0x1
5668#define GRBM_SOFT_RESET__SOFT_RESET_CP__SHIFT 0x0
5669#define GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK 0x4
5670#define GRBM_SOFT_RESET__SOFT_RESET_RLC__SHIFT 0x2
5671#define GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK 0x10000
5672#define GRBM_SOFT_RESET__SOFT_RESET_GFX__SHIFT 0x10
5673#define GRBM_SOFT_RESET__SOFT_RESET_CPF_MASK 0x20000
5674#define GRBM_SOFT_RESET__SOFT_RESET_CPF__SHIFT 0x11
5675#define GRBM_SOFT_RESET__SOFT_RESET_CPC_MASK 0x40000
5676#define GRBM_SOFT_RESET__SOFT_RESET_CPC__SHIFT 0x12
5677#define GRBM_SOFT_RESET__SOFT_RESET_CPG_MASK 0x80000
5678#define GRBM_SOFT_RESET__SOFT_RESET_CPG__SHIFT 0x13
5679#define GRBM_SOFT_RESET__SOFT_RESET_CAC_MASK 0x100000
5680#define GRBM_SOFT_RESET__SOFT_RESET_CAC__SHIFT 0x14
5681#define GRBM_DEBUG_CNTL__GRBM_DEBUG_INDEX_MASK 0x3f
5682#define GRBM_DEBUG_CNTL__GRBM_DEBUG_INDEX__SHIFT 0x0
5683#define GRBM_DEBUG_DATA__DATA_MASK 0xffffffff
5684#define GRBM_DEBUG_DATA__DATA__SHIFT 0x0
5685#define GRBM_GFX_INDEX__INSTANCE_INDEX_MASK 0xff
5686#define GRBM_GFX_INDEX__INSTANCE_INDEX__SHIFT 0x0
5687#define GRBM_GFX_INDEX__SH_INDEX_MASK 0xff00
5688#define GRBM_GFX_INDEX__SH_INDEX__SHIFT 0x8
5689#define GRBM_GFX_INDEX__SE_INDEX_MASK 0xff0000
5690#define GRBM_GFX_INDEX__SE_INDEX__SHIFT 0x10
5691#define GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK 0x20000000
5692#define GRBM_GFX_INDEX__SH_BROADCAST_WRITES__SHIFT 0x1d
5693#define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK 0x40000000
5694#define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT 0x1e
5695#define GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK 0x80000000
5696#define GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT 0x1f
5697#define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf
5698#define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0
5699#define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00
5700#define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8
5701#define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_MASK 0xff
5702#define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS__SHIFT 0x0
5703#define GRBM_DEBUG__IGNORE_RDY_MASK 0x2
5704#define GRBM_DEBUG__IGNORE_RDY__SHIFT 0x1
5705#define GRBM_DEBUG__IGNORE_FAO_MASK 0x20
5706#define GRBM_DEBUG__IGNORE_FAO__SHIFT 0x5
5707#define GRBM_DEBUG__DISABLE_READ_TIMEOUT_MASK 0x40
5708#define GRBM_DEBUG__DISABLE_READ_TIMEOUT__SHIFT 0x6
5709#define GRBM_DEBUG__SNAPSHOT_FREE_CNTRS_MASK 0x80
5710#define GRBM_DEBUG__SNAPSHOT_FREE_CNTRS__SHIFT 0x7
5711#define GRBM_DEBUG__HYSTERESIS_GUI_ACTIVE_MASK 0xf00
5712#define GRBM_DEBUG__HYSTERESIS_GUI_ACTIVE__SHIFT 0x8
5713#define GRBM_DEBUG__GFX_CLOCK_DOMAIN_OVERRIDE_MASK 0x1000
5714#define GRBM_DEBUG__GFX_CLOCK_DOMAIN_OVERRIDE__SHIFT 0xc
5715#define GRBM_DEBUG__GRBM_TRAP_ENABLE_MASK 0x2000
5716#define GRBM_DEBUG__GRBM_TRAP_ENABLE__SHIFT 0xd
5717#define GRBM_DEBUG__DEBUG_BUS_FGCG_EN_MASK 0x80000000
5718#define GRBM_DEBUG__DEBUG_BUS_FGCG_EN__SHIFT 0x1f
5719#define GRBM_DEBUG_SNAPSHOT__CPF_RDY_MASK 0x1
5720#define GRBM_DEBUG_SNAPSHOT__CPF_RDY__SHIFT 0x0
5721#define GRBM_DEBUG_SNAPSHOT__CPG_RDY_MASK 0x2
5722#define GRBM_DEBUG_SNAPSHOT__CPG_RDY__SHIFT 0x1
5723#define GRBM_DEBUG_SNAPSHOT__SRBM_RDY_MASK 0x4
5724#define GRBM_DEBUG_SNAPSHOT__SRBM_RDY__SHIFT 0x2
5725#define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE0_RDY_MASK 0x8
5726#define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE0_RDY__SHIFT 0x3
5727#define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE1_RDY_MASK 0x10
5728#define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE1_RDY__SHIFT 0x4
5729#define GRBM_DEBUG_SNAPSHOT__GDS_RDY_MASK 0x20
5730#define GRBM_DEBUG_SNAPSHOT__GDS_RDY__SHIFT 0x5
5731#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY0_MASK 0x40
5732#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY0__SHIFT 0x6
5733#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY0_MASK 0x80
5734#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY0__SHIFT 0x7
5735#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY0_MASK 0x100
5736#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY0__SHIFT 0x8
5737#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY0_MASK 0x200
5738#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY0__SHIFT 0x9
5739#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY0_MASK 0x400
5740#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY0__SHIFT 0xa
5741#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY0_MASK 0x800
5742#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY0__SHIFT 0xb
5743#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY0_MASK 0x1000
5744#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY0__SHIFT 0xc
5745#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY0_MASK 0x2000
5746#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY0__SHIFT 0xd
5747#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY1_MASK 0x4000
5748#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY1__SHIFT 0xe
5749#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY1_MASK 0x8000
5750#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY1__SHIFT 0xf
5751#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY1_MASK 0x10000
5752#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY1__SHIFT 0x10
5753#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY1_MASK 0x20000
5754#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY1__SHIFT 0x11
5755#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY1_MASK 0x40000
5756#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY1__SHIFT 0x12
5757#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY1_MASK 0x80000
5758#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY1__SHIFT 0x13
5759#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY1_MASK 0x100000
5760#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY1__SHIFT 0x14
5761#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY1_MASK 0x200000
5762#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY1__SHIFT 0x15
5763#define GRBM_READ_ERROR__READ_ADDRESS_MASK 0x3fffc
5764#define GRBM_READ_ERROR__READ_ADDRESS__SHIFT 0x2
5765#define GRBM_READ_ERROR__READ_PIPEID_MASK 0x300000
5766#define GRBM_READ_ERROR__READ_PIPEID__SHIFT 0x14
5767#define GRBM_READ_ERROR__READ_MEID_MASK 0xc00000
5768#define GRBM_READ_ERROR__READ_MEID__SHIFT 0x16
5769#define GRBM_READ_ERROR__READ_ERROR_MASK 0x80000000
5770#define GRBM_READ_ERROR__READ_ERROR__SHIFT 0x1f
5771#define GRBM_READ_ERROR2__READ_REQUESTER_SRBM_MASK 0x20000
5772#define GRBM_READ_ERROR2__READ_REQUESTER_SRBM__SHIFT 0x11
5773#define GRBM_READ_ERROR2__READ_REQUESTER_RLC_MASK 0x40000
5774#define GRBM_READ_ERROR2__READ_REQUESTER_RLC__SHIFT 0x12
5775#define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA_MASK 0x80000
5776#define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA__SHIFT 0x13
5777#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF_MASK 0x100000
5778#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF__SHIFT 0x14
5779#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF_MASK 0x200000
5780#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF__SHIFT 0x15
5781#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF_MASK 0x400000
5782#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF__SHIFT 0x16
5783#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF_MASK 0x800000
5784#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF__SHIFT 0x17
5785#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0_MASK 0x1000000
5786#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0__SHIFT 0x18
5787#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1_MASK 0x2000000
5788#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1__SHIFT 0x19
5789#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2_MASK 0x4000000
5790#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2__SHIFT 0x1a
5791#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3_MASK 0x8000000
5792#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3__SHIFT 0x1b
5793#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0_MASK 0x10000000
5794#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0__SHIFT 0x1c
5795#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1_MASK 0x20000000
5796#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1__SHIFT 0x1d
5797#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2_MASK 0x40000000
5798#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2__SHIFT 0x1e
5799#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3_MASK 0x80000000
5800#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3__SHIFT 0x1f
5801#define GRBM_INT_CNTL__RDERR_INT_ENABLE_MASK 0x1
5802#define GRBM_INT_CNTL__RDERR_INT_ENABLE__SHIFT 0x0
5803#define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE_MASK 0x80000
5804#define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE__SHIFT 0x13
5805#define GRBM_TRAP_OP__RW_MASK 0x1
5806#define GRBM_TRAP_OP__RW__SHIFT 0x0
5807#define GRBM_TRAP_ADDR__DATA_MASK 0xffff
5808#define GRBM_TRAP_ADDR__DATA__SHIFT 0x0
5809#define GRBM_TRAP_ADDR_MSK__DATA_MASK 0xffff
5810#define GRBM_TRAP_ADDR_MSK__DATA__SHIFT 0x0
5811#define GRBM_TRAP_WD__DATA_MASK 0xffffffff
5812#define GRBM_TRAP_WD__DATA__SHIFT 0x0
5813#define GRBM_TRAP_WD_MSK__DATA_MASK 0xffffffff
5814#define GRBM_TRAP_WD_MSK__DATA__SHIFT 0x0
5815#define GRBM_DSM_BYPASS__BYPASS_BITS_MASK 0x3
5816#define GRBM_DSM_BYPASS__BYPASS_BITS__SHIFT 0x0
5817#define GRBM_DSM_BYPASS__BYPASS_EN_MASK 0x4
5818#define GRBM_DSM_BYPASS__BYPASS_EN__SHIFT 0x2
5819#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC_MASK 0x1
5820#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC__SHIFT 0x0
5821#define GRBM_WRITE_ERROR__WRITE_REQUESTER_SRBM_MASK 0x2
5822#define GRBM_WRITE_ERROR__WRITE_REQUESTER_SRBM__SHIFT 0x1
5823#define GRBM_WRITE_ERROR__WRITE_SSRCID_MASK 0x1c
5824#define GRBM_WRITE_ERROR__WRITE_SSRCID__SHIFT 0x2
5825#define GRBM_WRITE_ERROR__WRITE_VFID_MASK 0x1e0
5826#define GRBM_WRITE_ERROR__WRITE_VFID__SHIFT 0x5
5827#define GRBM_WRITE_ERROR__WRITE_VF_MASK 0x1000
5828#define GRBM_WRITE_ERROR__WRITE_VF__SHIFT 0xc
5829#define GRBM_WRITE_ERROR__WRITE_VMID_MASK 0x1e000
5830#define GRBM_WRITE_ERROR__WRITE_VMID__SHIFT 0xd
5831#define GRBM_WRITE_ERROR__WRITE_PIPEID_MASK 0x300000
5832#define GRBM_WRITE_ERROR__WRITE_PIPEID__SHIFT 0x14
5833#define GRBM_WRITE_ERROR__WRITE_MEID_MASK 0xc00000
5834#define GRBM_WRITE_ERROR__WRITE_MEID__SHIFT 0x16
5835#define GRBM_WRITE_ERROR__WRITE_ERROR_MASK 0x80000000
5836#define GRBM_WRITE_ERROR__WRITE_ERROR__SHIFT 0x1f
5837#define GRBM_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f
5838#define GRBM_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
5839#define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400
5840#define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
5841#define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800
5842#define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
5843#define GRBM_PERFCOUNTER0_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x1000
5844#define GRBM_PERFCOUNTER0_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0xc
5845#define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x2000
5846#define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xd
5847#define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x4000
5848#define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xe
5849#define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x10000
5850#define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x10
5851#define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x20000
5852#define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x11
5853#define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x40000
5854#define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x12
5855#define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK 0x80000
5856#define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT 0x13
5857#define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x100000
5858#define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x14
5859#define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x200000
5860#define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x15
5861#define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK 0x400000
5862#define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT 0x16
5863#define GRBM_PERFCOUNTER0_SELECT__IA_BUSY_USER_DEFINED_MASK_MASK 0x800000
5864#define GRBM_PERFCOUNTER0_SELECT__IA_BUSY_USER_DEFINED_MASK__SHIFT 0x17
5865#define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK 0x1000000
5866#define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT 0x18
5867#define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x2000000
5868#define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x19
5869#define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x4000000
5870#define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x1a
5871#define GRBM_PERFCOUNTER0_SELECT__TC_BUSY_USER_DEFINED_MASK_MASK 0x8000000
5872#define GRBM_PERFCOUNTER0_SELECT__TC_BUSY_USER_DEFINED_MASK__SHIFT 0x1b
5873#define GRBM_PERFCOUNTER0_SELECT__WD_BUSY_USER_DEFINED_MASK_MASK 0x10000000
5874#define GRBM_PERFCOUNTER0_SELECT__WD_BUSY_USER_DEFINED_MASK__SHIFT 0x1c
5875#define GRBM_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f
5876#define GRBM_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
5877#define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400
5878#define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
5879#define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800
5880#define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
5881#define GRBM_PERFCOUNTER1_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x1000
5882#define GRBM_PERFCOUNTER1_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0xc
5883#define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x2000
5884#define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xd
5885#define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x4000
5886#define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xe
5887#define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x10000
5888#define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x10
5889#define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x20000
5890#define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x11
5891#define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x40000
5892#define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x12
5893#define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK 0x80000
5894#define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT 0x13
5895#define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x100000
5896#define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x14
5897#define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x200000
5898#define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x15
5899#define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK 0x400000
5900#define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT 0x16
5901#define GRBM_PERFCOUNTER1_SELECT__IA_BUSY_USER_DEFINED_MASK_MASK 0x800000
5902#define GRBM_PERFCOUNTER1_SELECT__IA_BUSY_USER_DEFINED_MASK__SHIFT 0x17
5903#define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK 0x1000000
5904#define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT 0x18
5905#define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x2000000
5906#define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x19
5907#define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x4000000
5908#define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x1a
5909#define GRBM_PERFCOUNTER1_SELECT__TC_BUSY_USER_DEFINED_MASK_MASK 0x8000000
5910#define GRBM_PERFCOUNTER1_SELECT__TC_BUSY_USER_DEFINED_MASK__SHIFT 0x1b
5911#define GRBM_PERFCOUNTER1_SELECT__WD_BUSY_USER_DEFINED_MASK_MASK 0x10000000
5912#define GRBM_PERFCOUNTER1_SELECT__WD_BUSY_USER_DEFINED_MASK__SHIFT 0x1c
5913#define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x3f
5914#define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0
5915#define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400
5916#define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
5917#define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800
5918#define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
5919#define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x1000
5920#define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc
5921#define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x2000
5922#define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd
5923#define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x8000
5924#define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf
5925#define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x10000
5926#define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10
5927#define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x20000
5928#define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11
5929#define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x40000
5930#define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12
5931#define GRBM_SE0_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x80000
5932#define GRBM_SE0_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13
5933#define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x100000
5934#define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14
5935#define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x200000
5936#define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15
5937#define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x3f
5938#define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0
5939#define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400
5940#define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
5941#define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800
5942#define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
5943#define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x1000
5944#define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc
5945#define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x2000
5946#define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd
5947#define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x8000
5948#define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf
5949#define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x10000
5950#define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10
5951#define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x20000
5952#define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11
5953#define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x40000
5954#define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12
5955#define GRBM_SE1_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x80000
5956#define GRBM_SE1_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13
5957#define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x100000
5958#define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14
5959#define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x200000
5960#define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15
5961#define GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x3f
5962#define GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0
5963#define GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400
5964#define GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
5965#define GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800
5966#define GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
5967#define GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x1000
5968#define GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc
5969#define GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x2000
5970#define GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd
5971#define GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x8000
5972#define GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf
5973#define GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x10000
5974#define GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10
5975#define GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x20000
5976#define GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11
5977#define GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x40000
5978#define GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12
5979#define GRBM_SE2_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x80000
5980#define GRBM_SE2_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13
5981#define GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x100000
5982#define GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14
5983#define GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x200000
5984#define GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15
5985#define GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x3f
5986#define GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0
5987#define GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400
5988#define GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
5989#define GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800
5990#define GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
5991#define GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x1000
5992#define GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc
5993#define GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x2000
5994#define GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd
5995#define GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x8000
5996#define GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf
5997#define GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x10000
5998#define GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10
5999#define GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x20000
6000#define GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11
6001#define GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x40000
6002#define GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12
6003#define GRBM_SE3_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x80000
6004#define GRBM_SE3_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13
6005#define GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x100000
6006#define GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14
6007#define GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x200000
6008#define GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15
6009#define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
6010#define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
6011#define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
6012#define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
6013#define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
6014#define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
6015#define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
6016#define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
6017#define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xffffffff
6018#define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0
6019#define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xffffffff
6020#define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0
6021#define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xffffffff
6022#define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0
6023#define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xffffffff
6024#define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0
6025#define GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xffffffff
6026#define GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0
6027#define GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xffffffff
6028#define GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0
6029#define GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xffffffff
6030#define GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0
6031#define GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xffffffff
6032#define GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0
6033#define GRBM_SCRATCH_REG0__SCRATCH_REG0_MASK 0xffffffff
6034#define GRBM_SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x0
6035#define GRBM_SCRATCH_REG1__SCRATCH_REG1_MASK 0xffffffff
6036#define GRBM_SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x0
6037#define GRBM_SCRATCH_REG2__SCRATCH_REG2_MASK 0xffffffff
6038#define GRBM_SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x0
6039#define GRBM_SCRATCH_REG3__SCRATCH_REG3_MASK 0xffffffff
6040#define GRBM_SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x0
6041#define GRBM_SCRATCH_REG4__SCRATCH_REG4_MASK 0xffffffff
6042#define GRBM_SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x0
6043#define GRBM_SCRATCH_REG5__SCRATCH_REG5_MASK 0xffffffff
6044#define GRBM_SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x0
6045#define GRBM_SCRATCH_REG6__SCRATCH_REG6_MASK 0xffffffff
6046#define GRBM_SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x0
6047#define GRBM_SCRATCH_REG7__SCRATCH_REG7_MASK 0xffffffff
6048#define GRBM_SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x0
6049#define DEBUG_INDEX__DEBUG_INDEX_MASK 0x3ffff
6050#define DEBUG_INDEX__DEBUG_INDEX__SHIFT 0x0
6051#define DEBUG_DATA__DEBUG_DATA_MASK 0xffffffff
6052#define DEBUG_DATA__DEBUG_DATA__SHIFT 0x0
6053#define GRBM_NOWHERE__DATA_MASK 0xffffffff
6054#define GRBM_NOWHERE__DATA__SHIFT 0x0
6055#define PA_CL_VPORT_XSCALE__VPORT_XSCALE_MASK 0xffffffff
6056#define PA_CL_VPORT_XSCALE__VPORT_XSCALE__SHIFT 0x0
6057#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET_MASK 0xffffffff
6058#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET__SHIFT 0x0
6059#define PA_CL_VPORT_YSCALE__VPORT_YSCALE_MASK 0xffffffff
6060#define PA_CL_VPORT_YSCALE__VPORT_YSCALE__SHIFT 0x0
6061#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET_MASK 0xffffffff
6062#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET__SHIFT 0x0
6063#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE_MASK 0xffffffff
6064#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE__SHIFT 0x0
6065#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET_MASK 0xffffffff
6066#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET__SHIFT 0x0
6067#define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE_MASK 0xffffffff
6068#define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE__SHIFT 0x0
6069#define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE_MASK 0xffffffff
6070#define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE__SHIFT 0x0
6071#define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE_MASK 0xffffffff
6072#define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE__SHIFT 0x0
6073#define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE_MASK 0xffffffff
6074#define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE__SHIFT 0x0
6075#define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE_MASK 0xffffffff
6076#define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE__SHIFT 0x0
6077#define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE_MASK 0xffffffff
6078#define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE__SHIFT 0x0
6079#define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE_MASK 0xffffffff
6080#define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE__SHIFT 0x0
6081#define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE_MASK 0xffffffff
6082#define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE__SHIFT 0x0
6083#define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE_MASK 0xffffffff
6084#define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE__SHIFT 0x0
6085#define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE_MASK 0xffffffff
6086#define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE__SHIFT 0x0
6087#define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE_MASK 0xffffffff
6088#define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE__SHIFT 0x0
6089#define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE_MASK 0xffffffff
6090#define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE__SHIFT 0x0
6091#define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE_MASK 0xffffffff
6092#define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE__SHIFT 0x0
6093#define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE_MASK 0xffffffff
6094#define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE__SHIFT 0x0
6095#define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE_MASK 0xffffffff
6096#define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE__SHIFT 0x0
6097#define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET_MASK 0xffffffff
6098#define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET__SHIFT 0x0
6099#define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET_MASK 0xffffffff
6100#define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET__SHIFT 0x0
6101#define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET_MASK 0xffffffff
6102#define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET__SHIFT 0x0
6103#define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET_MASK 0xffffffff
6104#define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET__SHIFT 0x0
6105#define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET_MASK 0xffffffff
6106#define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET__SHIFT 0x0
6107#define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET_MASK 0xffffffff
6108#define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET__SHIFT 0x0
6109#define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET_MASK 0xffffffff
6110#define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET__SHIFT 0x0
6111#define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET_MASK 0xffffffff
6112#define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET__SHIFT 0x0
6113#define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET_MASK 0xffffffff
6114#define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET__SHIFT 0x0
6115#define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET_MASK 0xffffffff
6116#define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET__SHIFT 0x0
6117#define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET_MASK 0xffffffff
6118#define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET__SHIFT 0x0
6119#define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET_MASK 0xffffffff
6120#define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET__SHIFT 0x0
6121#define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET_MASK 0xffffffff
6122#define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET__SHIFT 0x0
6123#define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET_MASK 0xffffffff
6124#define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET__SHIFT 0x0
6125#define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET_MASK 0xffffffff
6126#define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET__SHIFT 0x0
6127#define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE_MASK 0xffffffff
6128#define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE__SHIFT 0x0
6129#define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE_MASK 0xffffffff
6130#define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE__SHIFT 0x0
6131#define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE_MASK 0xffffffff
6132#define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE__SHIFT 0x0
6133#define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE_MASK 0xffffffff
6134#define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE__SHIFT 0x0
6135#define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE_MASK 0xffffffff
6136#define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE__SHIFT 0x0
6137#define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE_MASK 0xffffffff
6138#define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE__SHIFT 0x0
6139#define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE_MASK 0xffffffff
6140#define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE__SHIFT 0x0
6141#define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE_MASK 0xffffffff
6142#define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE__SHIFT 0x0
6143#define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE_MASK 0xffffffff
6144#define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE__SHIFT 0x0
6145#define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE_MASK 0xffffffff
6146#define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE__SHIFT 0x0
6147#define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE_MASK 0xffffffff
6148#define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE__SHIFT 0x0
6149#define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE_MASK 0xffffffff
6150#define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE__SHIFT 0x0
6151#define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE_MASK 0xffffffff
6152#define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE__SHIFT 0x0
6153#define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE_MASK 0xffffffff
6154#define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE__SHIFT 0x0
6155#define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE_MASK 0xffffffff
6156#define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE__SHIFT 0x0
6157#define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET_MASK 0xffffffff
6158#define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET__SHIFT 0x0
6159#define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET_MASK 0xffffffff
6160#define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET__SHIFT 0x0
6161#define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET_MASK 0xffffffff
6162#define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET__SHIFT 0x0
6163#define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET_MASK 0xffffffff
6164#define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET__SHIFT 0x0
6165#define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET_MASK 0xffffffff
6166#define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET__SHIFT 0x0
6167#define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET_MASK 0xffffffff
6168#define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET__SHIFT 0x0
6169#define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET_MASK 0xffffffff
6170#define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET__SHIFT 0x0
6171#define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET_MASK 0xffffffff
6172#define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET__SHIFT 0x0
6173#define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET_MASK 0xffffffff
6174#define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET__SHIFT 0x0
6175#define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET_MASK 0xffffffff
6176#define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET__SHIFT 0x0
6177#define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET_MASK 0xffffffff
6178#define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET__SHIFT 0x0
6179#define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET_MASK 0xffffffff
6180#define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET__SHIFT 0x0
6181#define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET_MASK 0xffffffff
6182#define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET__SHIFT 0x0
6183#define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET_MASK 0xffffffff
6184#define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET__SHIFT 0x0
6185#define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET_MASK 0xffffffff
6186#define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET__SHIFT 0x0
6187#define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE_MASK 0xffffffff
6188#define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE__SHIFT 0x0
6189#define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE_MASK 0xffffffff
6190#define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE__SHIFT 0x0
6191#define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE_MASK 0xffffffff
6192#define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE__SHIFT 0x0
6193#define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE_MASK 0xffffffff
6194#define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE__SHIFT 0x0
6195#define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE_MASK 0xffffffff
6196#define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE__SHIFT 0x0
6197#define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE_MASK 0xffffffff
6198#define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE__SHIFT 0x0
6199#define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE_MASK 0xffffffff
6200#define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE__SHIFT 0x0
6201#define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE_MASK 0xffffffff
6202#define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE__SHIFT 0x0
6203#define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE_MASK 0xffffffff
6204#define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE__SHIFT 0x0
6205#define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE_MASK 0xffffffff
6206#define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE__SHIFT 0x0
6207#define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE_MASK 0xffffffff
6208#define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE__SHIFT 0x0
6209#define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE_MASK 0xffffffff
6210#define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE__SHIFT 0x0
6211#define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE_MASK 0xffffffff
6212#define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE__SHIFT 0x0
6213#define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE_MASK 0xffffffff
6214#define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE__SHIFT 0x0
6215#define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE_MASK 0xffffffff
6216#define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE__SHIFT 0x0
6217#define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET_MASK 0xffffffff
6218#define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET__SHIFT 0x0
6219#define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET_MASK 0xffffffff
6220#define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET__SHIFT 0x0
6221#define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET_MASK 0xffffffff
6222#define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET__SHIFT 0x0
6223#define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET_MASK 0xffffffff
6224#define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET__SHIFT 0x0
6225#define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET_MASK 0xffffffff
6226#define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET__SHIFT 0x0
6227#define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET_MASK 0xffffffff
6228#define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET__SHIFT 0x0
6229#define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET_MASK 0xffffffff
6230#define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET__SHIFT 0x0
6231#define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET_MASK 0xffffffff
6232#define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET__SHIFT 0x0
6233#define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET_MASK 0xffffffff
6234#define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET__SHIFT 0x0
6235#define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET_MASK 0xffffffff
6236#define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET__SHIFT 0x0
6237#define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET_MASK 0xffffffff
6238#define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET__SHIFT 0x0
6239#define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET_MASK 0xffffffff
6240#define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET__SHIFT 0x0
6241#define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET_MASK 0xffffffff
6242#define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET__SHIFT 0x0
6243#define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET_MASK 0xffffffff
6244#define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET__SHIFT 0x0
6245#define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET_MASK 0xffffffff
6246#define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET__SHIFT 0x0
6247#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA_MASK 0x1
6248#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA__SHIFT 0x0
6249#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA_MASK 0x2
6250#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA__SHIFT 0x1
6251#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA_MASK 0x4
6252#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA__SHIFT 0x2
6253#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA_MASK 0x8
6254#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA__SHIFT 0x3
6255#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA_MASK 0x10
6256#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA__SHIFT 0x4
6257#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA_MASK 0x20
6258#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA__SHIFT 0x5
6259#define PA_CL_VTE_CNTL__VTX_XY_FMT_MASK 0x100
6260#define PA_CL_VTE_CNTL__VTX_XY_FMT__SHIFT 0x8
6261#define PA_CL_VTE_CNTL__VTX_Z_FMT_MASK 0x200
6262#define PA_CL_VTE_CNTL__VTX_Z_FMT__SHIFT 0x9
6263#define PA_CL_VTE_CNTL__VTX_W0_FMT_MASK 0x400
6264#define PA_CL_VTE_CNTL__VTX_W0_FMT__SHIFT 0xa
6265#define PA_CL_VTE_CNTL__PERFCOUNTER_REF_MASK 0x800
6266#define PA_CL_VTE_CNTL__PERFCOUNTER_REF__SHIFT 0xb
6267#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0_MASK 0x1
6268#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0__SHIFT 0x0
6269#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1_MASK 0x2
6270#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1__SHIFT 0x1
6271#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2_MASK 0x4
6272#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2__SHIFT 0x2
6273#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3_MASK 0x8
6274#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3__SHIFT 0x3
6275#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4_MASK 0x10
6276#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4__SHIFT 0x4
6277#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5_MASK 0x20
6278#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5__SHIFT 0x5
6279#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6_MASK 0x40
6280#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6__SHIFT 0x6
6281#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7_MASK 0x80
6282#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7__SHIFT 0x7
6283#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0_MASK 0x100
6284#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0__SHIFT 0x8
6285#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1_MASK 0x200
6286#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1__SHIFT 0x9
6287#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2_MASK 0x400
6288#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2__SHIFT 0xa
6289#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3_MASK 0x800
6290#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3__SHIFT 0xb
6291#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4_MASK 0x1000
6292#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4__SHIFT 0xc
6293#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5_MASK 0x2000
6294#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5__SHIFT 0xd
6295#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6_MASK 0x4000
6296#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6__SHIFT 0xe
6297#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7_MASK 0x8000
6298#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7__SHIFT 0xf
6299#define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE_MASK 0x10000
6300#define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE__SHIFT 0x10
6301#define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG_MASK 0x20000
6302#define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG__SHIFT 0x11
6303#define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX_MASK 0x40000
6304#define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX__SHIFT 0x12
6305#define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX_MASK 0x80000
6306#define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX__SHIFT 0x13
6307#define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG_MASK 0x100000
6308#define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG__SHIFT 0x14
6309#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA_MASK 0x200000
6310#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA__SHIFT 0x15
6311#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA_MASK 0x400000
6312#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA__SHIFT 0x16
6313#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA_MASK 0x800000
6314#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA__SHIFT 0x17
6315#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA_MASK 0x1000000
6316#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA__SHIFT 0x18
6317#define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG_MASK 0x2000000
6318#define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG__SHIFT 0x19
6319#define PA_CL_VS_OUT_CNTL__USE_VTX_LINE_WIDTH_MASK 0x4000000
6320#define PA_CL_VS_OUT_CNTL__USE_VTX_LINE_WIDTH__SHIFT 0x1a
6321#define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD_MASK 0x1
6322#define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD__SHIFT 0x0
6323#define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD_MASK 0x2
6324#define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD__SHIFT 0x1
6325#define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD_MASK 0x4
6326#define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD__SHIFT 0x2
6327#define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0_MASK 0x8
6328#define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0__SHIFT 0x3
6329#define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN_MASK 0x10
6330#define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN__SHIFT 0x4
6331#define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN_MASK 0x20
6332#define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN__SHIFT 0x5
6333#define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN_MASK 0x40
6334#define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN__SHIFT 0x6
6335#define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0_MASK 0x80
6336#define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0__SHIFT 0x7
6337#define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF_MASK 0x100
6338#define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF__SHIFT 0x8
6339#define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN_MASK 0x200
6340#define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN__SHIFT 0x9
6341#define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF_MASK 0x400
6342#define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF__SHIFT 0xa
6343#define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN_MASK 0x800
6344#define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN__SHIFT 0xb
6345#define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF_MASK 0x1000
6346#define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF__SHIFT 0xc
6347#define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN_MASK 0x2000
6348#define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN__SHIFT 0xd
6349#define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD_MASK 0x4000
6350#define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD__SHIFT 0xe
6351#define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0_MASK 0x100000
6352#define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0__SHIFT 0x14
6353#define PA_CL_CLIP_CNTL__UCP_ENA_0_MASK 0x1
6354#define PA_CL_CLIP_CNTL__UCP_ENA_0__SHIFT 0x0
6355#define PA_CL_CLIP_CNTL__UCP_ENA_1_MASK 0x2
6356#define PA_CL_CLIP_CNTL__UCP_ENA_1__SHIFT 0x1
6357#define PA_CL_CLIP_CNTL__UCP_ENA_2_MASK 0x4
6358#define PA_CL_CLIP_CNTL__UCP_ENA_2__SHIFT 0x2
6359#define PA_CL_CLIP_CNTL__UCP_ENA_3_MASK 0x8
6360#define PA_CL_CLIP_CNTL__UCP_ENA_3__SHIFT 0x3
6361#define PA_CL_CLIP_CNTL__UCP_ENA_4_MASK 0x10
6362#define PA_CL_CLIP_CNTL__UCP_ENA_4__SHIFT 0x4
6363#define PA_CL_CLIP_CNTL__UCP_ENA_5_MASK 0x20
6364#define PA_CL_CLIP_CNTL__UCP_ENA_5__SHIFT 0x5
6365#define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG_MASK 0x2000
6366#define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG__SHIFT 0xd
6367#define PA_CL_CLIP_CNTL__PS_UCP_MODE_MASK 0xc000
6368#define PA_CL_CLIP_CNTL__PS_UCP_MODE__SHIFT 0xe
6369#define PA_CL_CLIP_CNTL__CLIP_DISABLE_MASK 0x10000
6370#define PA_CL_CLIP_CNTL__CLIP_DISABLE__SHIFT 0x10
6371#define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA_MASK 0x20000
6372#define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA__SHIFT 0x11
6373#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA_MASK 0x40000
6374#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA__SHIFT 0x12
6375#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF_MASK 0x80000
6376#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF__SHIFT 0x13
6377#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT_MASK 0x100000
6378#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT__SHIFT 0x14
6379#define PA_CL_CLIP_CNTL__VTX_KILL_OR_MASK 0x200000
6380#define PA_CL_CLIP_CNTL__VTX_KILL_OR__SHIFT 0x15
6381#define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL_MASK 0x400000
6382#define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL__SHIFT 0x16
6383#define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA_MASK 0x1000000
6384#define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA__SHIFT 0x18
6385#define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE_MASK 0x2000000
6386#define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE__SHIFT 0x19
6387#define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE_MASK 0x4000000
6388#define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE__SHIFT 0x1a
6389#define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE_MASK 0x8000000
6390#define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE__SHIFT 0x1b
6391#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER_MASK 0xffffffff
6392#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER__SHIFT 0x0
6393#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER_MASK 0xffffffff
6394#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER__SHIFT 0x0
6395#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER_MASK 0xffffffff
6396#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER__SHIFT 0x0
6397#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER_MASK 0xffffffff
6398#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER__SHIFT 0x0
6399#define PA_CL_UCP_0_X__DATA_REGISTER_MASK 0xffffffff
6400#define PA_CL_UCP_0_X__DATA_REGISTER__SHIFT 0x0
6401#define PA_CL_UCP_0_Y__DATA_REGISTER_MASK 0xffffffff
6402#define PA_CL_UCP_0_Y__DATA_REGISTER__SHIFT 0x0
6403#define PA_CL_UCP_0_Z__DATA_REGISTER_MASK 0xffffffff
6404#define PA_CL_UCP_0_Z__DATA_REGISTER__SHIFT 0x0
6405#define PA_CL_UCP_0_W__DATA_REGISTER_MASK 0xffffffff
6406#define PA_CL_UCP_0_W__DATA_REGISTER__SHIFT 0x0
6407#define PA_CL_UCP_1_X__DATA_REGISTER_MASK 0xffffffff
6408#define PA_CL_UCP_1_X__DATA_REGISTER__SHIFT 0x0
6409#define PA_CL_UCP_1_Y__DATA_REGISTER_MASK 0xffffffff
6410#define PA_CL_UCP_1_Y__DATA_REGISTER__SHIFT 0x0
6411#define PA_CL_UCP_1_Z__DATA_REGISTER_MASK 0xffffffff
6412#define PA_CL_UCP_1_Z__DATA_REGISTER__SHIFT 0x0
6413#define PA_CL_UCP_1_W__DATA_REGISTER_MASK 0xffffffff
6414#define PA_CL_UCP_1_W__DATA_REGISTER__SHIFT 0x0
6415#define PA_CL_UCP_2_X__DATA_REGISTER_MASK 0xffffffff
6416#define PA_CL_UCP_2_X__DATA_REGISTER__SHIFT 0x0
6417#define PA_CL_UCP_2_Y__DATA_REGISTER_MASK 0xffffffff
6418#define PA_CL_UCP_2_Y__DATA_REGISTER__SHIFT 0x0
6419#define PA_CL_UCP_2_Z__DATA_REGISTER_MASK 0xffffffff
6420#define PA_CL_UCP_2_Z__DATA_REGISTER__SHIFT 0x0
6421#define PA_CL_UCP_2_W__DATA_REGISTER_MASK 0xffffffff
6422#define PA_CL_UCP_2_W__DATA_REGISTER__SHIFT 0x0
6423#define PA_CL_UCP_3_X__DATA_REGISTER_MASK 0xffffffff
6424#define PA_CL_UCP_3_X__DATA_REGISTER__SHIFT 0x0
6425#define PA_CL_UCP_3_Y__DATA_REGISTER_MASK 0xffffffff
6426#define PA_CL_UCP_3_Y__DATA_REGISTER__SHIFT 0x0
6427#define PA_CL_UCP_3_Z__DATA_REGISTER_MASK 0xffffffff
6428#define PA_CL_UCP_3_Z__DATA_REGISTER__SHIFT 0x0
6429#define PA_CL_UCP_3_W__DATA_REGISTER_MASK 0xffffffff
6430#define PA_CL_UCP_3_W__DATA_REGISTER__SHIFT 0x0
6431#define PA_CL_UCP_4_X__DATA_REGISTER_MASK 0xffffffff
6432#define PA_CL_UCP_4_X__DATA_REGISTER__SHIFT 0x0
6433#define PA_CL_UCP_4_Y__DATA_REGISTER_MASK 0xffffffff
6434#define PA_CL_UCP_4_Y__DATA_REGISTER__SHIFT 0x0
6435#define PA_CL_UCP_4_Z__DATA_REGISTER_MASK 0xffffffff
6436#define PA_CL_UCP_4_Z__DATA_REGISTER__SHIFT 0x0
6437#define PA_CL_UCP_4_W__DATA_REGISTER_MASK 0xffffffff
6438#define PA_CL_UCP_4_W__DATA_REGISTER__SHIFT 0x0
6439#define PA_CL_UCP_5_X__DATA_REGISTER_MASK 0xffffffff
6440#define PA_CL_UCP_5_X__DATA_REGISTER__SHIFT 0x0
6441#define PA_CL_UCP_5_Y__DATA_REGISTER_MASK 0xffffffff
6442#define PA_CL_UCP_5_Y__DATA_REGISTER__SHIFT 0x0
6443#define PA_CL_UCP_5_Z__DATA_REGISTER_MASK 0xffffffff
6444#define PA_CL_UCP_5_Z__DATA_REGISTER__SHIFT 0x0
6445#define PA_CL_UCP_5_W__DATA_REGISTER_MASK 0xffffffff
6446#define PA_CL_UCP_5_W__DATA_REGISTER__SHIFT 0x0
6447#define PA_CL_POINT_X_RAD__DATA_REGISTER_MASK 0xffffffff
6448#define PA_CL_POINT_X_RAD__DATA_REGISTER__SHIFT 0x0
6449#define PA_CL_POINT_Y_RAD__DATA_REGISTER_MASK 0xffffffff
6450#define PA_CL_POINT_Y_RAD__DATA_REGISTER__SHIFT 0x0
6451#define PA_CL_POINT_SIZE__DATA_REGISTER_MASK 0xffffffff
6452#define PA_CL_POINT_SIZE__DATA_REGISTER__SHIFT 0x0
6453#define PA_CL_POINT_CULL_RAD__DATA_REGISTER_MASK 0xffffffff
6454#define PA_CL_POINT_CULL_RAD__DATA_REGISTER__SHIFT 0x0
6455#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK 0x1
6456#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA__SHIFT 0x0
6457#define PA_CL_ENHANCE__NUM_CLIP_SEQ_MASK 0x6
6458#define PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT 0x1
6459#define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL_MASK 0x8
6460#define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL__SHIFT 0x3
6461#define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE_MASK 0x10
6462#define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE__SHIFT 0x4
6463#define PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL_MASK 0x20
6464#define PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL__SHIFT 0x5
6465#define PA_CL_ENHANCE__ECO_SPARE3_MASK 0x10000000
6466#define PA_CL_ENHANCE__ECO_SPARE3__SHIFT 0x1c
6467#define PA_CL_ENHANCE__ECO_SPARE2_MASK 0x20000000
6468#define PA_CL_ENHANCE__ECO_SPARE2__SHIFT 0x1d
6469#define PA_CL_ENHANCE__ECO_SPARE1_MASK 0x40000000
6470#define PA_CL_ENHANCE__ECO_SPARE1__SHIFT 0x1e
6471#define PA_CL_ENHANCE__ECO_SPARE0_MASK 0x80000000
6472#define PA_CL_ENHANCE__ECO_SPARE0__SHIFT 0x1f
6473#define PA_CL_RESET_DEBUG__CL_TRIV_DISC_DISABLE_MASK 0x1
6474#define PA_CL_RESET_DEBUG__CL_TRIV_DISC_DISABLE__SHIFT 0x0
6475#define PA_SU_VTX_CNTL__PIX_CENTER_MASK 0x1
6476#define PA_SU_VTX_CNTL__PIX_CENTER__SHIFT 0x0
6477#define PA_SU_VTX_CNTL__ROUND_MODE_MASK 0x6
6478#define PA_SU_VTX_CNTL__ROUND_MODE__SHIFT 0x1
6479#define PA_SU_VTX_CNTL__QUANT_MODE_MASK 0x38
6480#define PA_SU_VTX_CNTL__QUANT_MODE__SHIFT 0x3
6481#define PA_SU_POINT_SIZE__HEIGHT_MASK 0xffff
6482#define PA_SU_POINT_SIZE__HEIGHT__SHIFT 0x0
6483#define PA_SU_POINT_SIZE__WIDTH_MASK 0xffff0000
6484#define PA_SU_POINT_SIZE__WIDTH__SHIFT 0x10
6485#define PA_SU_POINT_MINMAX__MIN_SIZE_MASK 0xffff
6486#define PA_SU_POINT_MINMAX__MIN_SIZE__SHIFT 0x0
6487#define PA_SU_POINT_MINMAX__MAX_SIZE_MASK 0xffff0000
6488#define PA_SU_POINT_MINMAX__MAX_SIZE__SHIFT 0x10
6489#define PA_SU_LINE_CNTL__WIDTH_MASK 0xffff
6490#define PA_SU_LINE_CNTL__WIDTH__SHIFT 0x0
6491#define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET_MASK 0x3
6492#define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET__SHIFT 0x0
6493#define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH_MASK 0x4
6494#define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH__SHIFT 0x2
6495#define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM_MASK 0x8
6496#define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM__SHIFT 0x3
6497#define PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST_MASK 0x10
6498#define PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST__SHIFT 0x4
6499#define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE_MASK 0xffffffff
6500#define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE__SHIFT 0x0
6501#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE_MASK 0x1
6502#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE__SHIFT 0x0
6503#define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE_MASK 0x2
6504#define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE__SHIFT 0x1
6505#define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE_MASK 0x4
6506#define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE__SHIFT 0x2
6507#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE_MASK 0x8
6508#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE__SHIFT 0x3
6509#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA_MASK 0x10
6510#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA__SHIFT 0x4
6511#define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA_MASK 0x20
6512#define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA__SHIFT 0x5
6513#define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA_MASK 0x40
6514#define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA__SHIFT 0x6
6515#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA_MASK 0x80
6516#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA__SHIFT 0x7
6517#define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT_MASK 0xff00
6518#define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT__SHIFT 0x8
6519#define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION_MASK 0x40000000
6520#define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION__SHIFT 0x1e
6521#define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION_MASK 0x80000000
6522#define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION__SHIFT 0x1f
6523#define PA_SU_SC_MODE_CNTL__CULL_FRONT_MASK 0x1
6524#define PA_SU_SC_MODE_CNTL__CULL_FRONT__SHIFT 0x0
6525#define PA_SU_SC_MODE_CNTL__CULL_BACK_MASK 0x2
6526#define PA_SU_SC_MODE_CNTL__CULL_BACK__SHIFT 0x1
6527#define PA_SU_SC_MODE_CNTL__FACE_MASK 0x4
6528#define PA_SU_SC_MODE_CNTL__FACE__SHIFT 0x2
6529#define PA_SU_SC_MODE_CNTL__POLY_MODE_MASK 0x18
6530#define PA_SU_SC_MODE_CNTL__POLY_MODE__SHIFT 0x3
6531#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE_MASK 0xe0
6532#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE__SHIFT 0x5
6533#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE_MASK 0x700
6534#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE__SHIFT 0x8
6535#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE_MASK 0x800
6536#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE__SHIFT 0xb
6537#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE_MASK 0x1000
6538#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE__SHIFT 0xc
6539#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE_MASK 0x2000
6540#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE__SHIFT 0xd
6541#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE_MASK 0x10000
6542#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE__SHIFT 0x10
6543#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST_MASK 0x80000
6544#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST__SHIFT 0x13
6545#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS_MASK 0x100000
6546#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS__SHIFT 0x14
6547#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA_MASK 0x200000
6548#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT 0x15
6549#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS_MASK 0xff
6550#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS__SHIFT 0x0
6551#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT_MASK 0x100
6552#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT__SHIFT 0x8
6553#define PA_SU_POLY_OFFSET_CLAMP__CLAMP_MASK 0xffffffff
6554#define PA_SU_POLY_OFFSET_CLAMP__CLAMP__SHIFT 0x0
6555#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE_MASK 0xffffffff
6556#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE__SHIFT 0x0
6557#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET_MASK 0xffffffff
6558#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET__SHIFT 0x0
6559#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE_MASK 0xffffffff
6560#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE__SHIFT 0x0
6561#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET_MASK 0xffffffff
6562#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET__SHIFT 0x0
6563#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X_MASK 0x1ff
6564#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X__SHIFT 0x0
6565#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y_MASK 0x1ff0000
6566#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y__SHIFT 0x10
6567#define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE_MASK 0xffffff
6568#define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE__SHIFT 0x0
6569#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff
6570#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
6571#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00
6572#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
6573#define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
6574#define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
6575#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff
6576#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
6577#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00
6578#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
6579#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff
6580#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
6581#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00
6582#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
6583#define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
6584#define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
6585#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff
6586#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
6587#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00
6588#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
6589#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff
6590#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
6591#define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000
6592#define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
6593#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff
6594#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
6595#define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000
6596#define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
6597#define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
6598#define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
6599#define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffff
6600#define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
6601#define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
6602#define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
6603#define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffff
6604#define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
6605#define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
6606#define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
6607#define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffff
6608#define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
6609#define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
6610#define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
6611#define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffff
6612#define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
6613#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES_MASK 0x7
6614#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES__SHIFT 0x0
6615#define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN_MASK 0x10
6616#define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN__SHIFT 0x4
6617#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST_MASK 0x1e000
6618#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST__SHIFT 0xd
6619#define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES_MASK 0x700000
6620#define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES__SHIFT 0x14
6621#define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE_MASK 0x3000000
6622#define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE__SHIFT 0x18
6623#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0_MASK 0xffff
6624#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0__SHIFT 0x0
6625#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0_MASK 0xffff0000
6626#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0__SHIFT 0x10
6627#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1_MASK 0xffff
6628#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1__SHIFT 0x0
6629#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1_MASK 0xffff0000
6630#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1__SHIFT 0x10
6631#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X_MASK 0xf
6632#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X__SHIFT 0x0
6633#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y_MASK 0xf0
6634#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y__SHIFT 0x4
6635#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X_MASK 0xf00
6636#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X__SHIFT 0x8
6637#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y_MASK 0xf000
6638#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y__SHIFT 0xc
6639#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X_MASK 0xf0000
6640#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X__SHIFT 0x10
6641#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y_MASK 0xf00000
6642#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y__SHIFT 0x14
6643#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X_MASK 0xf000000
6644#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X__SHIFT 0x18
6645#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y_MASK 0xf0000000
6646#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y__SHIFT 0x1c
6647#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X_MASK 0xf
6648#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X__SHIFT 0x0
6649#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y_MASK 0xf0
6650#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y__SHIFT 0x4
6651#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X_MASK 0xf00
6652#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X__SHIFT 0x8
6653#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y_MASK 0xf000
6654#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y__SHIFT 0xc
6655#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X_MASK 0xf0000
6656#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X__SHIFT 0x10
6657#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y_MASK 0xf00000
6658#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y__SHIFT 0x14
6659#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X_MASK 0xf000000
6660#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X__SHIFT 0x18
6661#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y_MASK 0xf0000000
6662#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y__SHIFT 0x1c
6663#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X_MASK 0xf
6664#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X__SHIFT 0x0
6665#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y_MASK 0xf0
6666#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y__SHIFT 0x4
6667#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X_MASK 0xf00
6668#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X__SHIFT 0x8
6669#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y_MASK 0xf000
6670#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y__SHIFT 0xc
6671#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X_MASK 0xf0000
6672#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X__SHIFT 0x10
6673#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y_MASK 0xf00000
6674#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y__SHIFT 0x14
6675#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X_MASK 0xf000000
6676#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X__SHIFT 0x18
6677#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y_MASK 0xf0000000
6678#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y__SHIFT 0x1c
6679#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X_MASK 0xf
6680#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X__SHIFT 0x0
6681#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y_MASK 0xf0
6682#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y__SHIFT 0x4
6683#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X_MASK 0xf00
6684#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X__SHIFT 0x8
6685#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y_MASK 0xf000
6686#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y__SHIFT 0xc
6687#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X_MASK 0xf0000
6688#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X__SHIFT 0x10
6689#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y_MASK 0xf00000
6690#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y__SHIFT 0x14
6691#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X_MASK 0xf000000
6692#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X__SHIFT 0x18
6693#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y_MASK 0xf0000000
6694#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y__SHIFT 0x1c
6695#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X_MASK 0xf
6696#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X__SHIFT 0x0
6697#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y_MASK 0xf0
6698#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y__SHIFT 0x4
6699#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X_MASK 0xf00
6700#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X__SHIFT 0x8
6701#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y_MASK 0xf000
6702#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y__SHIFT 0xc
6703#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X_MASK 0xf0000
6704#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X__SHIFT 0x10
6705#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y_MASK 0xf00000
6706#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y__SHIFT 0x14
6707#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X_MASK 0xf000000
6708#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X__SHIFT 0x18
6709#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y_MASK 0xf0000000
6710#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y__SHIFT 0x1c
6711#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X_MASK 0xf
6712#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X__SHIFT 0x0
6713#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y_MASK 0xf0
6714#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y__SHIFT 0x4
6715#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X_MASK 0xf00
6716#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X__SHIFT 0x8
6717#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y_MASK 0xf000
6718#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y__SHIFT 0xc
6719#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X_MASK 0xf0000
6720#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X__SHIFT 0x10
6721#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y_MASK 0xf00000
6722#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y__SHIFT 0x14
6723#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X_MASK 0xf000000
6724#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X__SHIFT 0x18
6725#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y_MASK 0xf0000000
6726#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y__SHIFT 0x1c
6727#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X_MASK 0xf
6728#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X__SHIFT 0x0
6729#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y_MASK 0xf0
6730#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y__SHIFT 0x4
6731#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X_MASK 0xf00
6732#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X__SHIFT 0x8
6733#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y_MASK 0xf000
6734#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y__SHIFT 0xc
6735#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X_MASK 0xf0000
6736#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X__SHIFT 0x10
6737#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y_MASK 0xf00000
6738#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y__SHIFT 0x14
6739#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X_MASK 0xf000000
6740#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X__SHIFT 0x18
6741#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y_MASK 0xf0000000
6742#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y__SHIFT 0x1c
6743#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X_MASK 0xf
6744#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X__SHIFT 0x0
6745#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y_MASK 0xf0
6746#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y__SHIFT 0x4
6747#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X_MASK 0xf00
6748#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X__SHIFT 0x8
6749#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y_MASK 0xf000
6750#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y__SHIFT 0xc
6751#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X_MASK 0xf0000
6752#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X__SHIFT 0x10
6753#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y_MASK 0xf00000
6754#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y__SHIFT 0x14
6755#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X_MASK 0xf000000
6756#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X__SHIFT 0x18
6757#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y_MASK 0xf0000000
6758#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y__SHIFT 0x1c
6759#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X_MASK 0xf
6760#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X__SHIFT 0x0
6761#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y_MASK 0xf0
6762#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y__SHIFT 0x4
6763#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X_MASK 0xf00
6764#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X__SHIFT 0x8
6765#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y_MASK 0xf000
6766#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y__SHIFT 0xc
6767#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X_MASK 0xf0000
6768#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X__SHIFT 0x10
6769#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y_MASK 0xf00000
6770#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y__SHIFT 0x14
6771#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X_MASK 0xf000000
6772#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X__SHIFT 0x18
6773#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y_MASK 0xf0000000
6774#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y__SHIFT 0x1c
6775#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X_MASK 0xf
6776#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X__SHIFT 0x0
6777#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y_MASK 0xf0
6778#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y__SHIFT 0x4
6779#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X_MASK 0xf00
6780#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X__SHIFT 0x8
6781#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y_MASK 0xf000
6782#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y__SHIFT 0xc
6783#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X_MASK 0xf0000
6784#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X__SHIFT 0x10
6785#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y_MASK 0xf00000
6786#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y__SHIFT 0x14
6787#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X_MASK 0xf000000
6788#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X__SHIFT 0x18
6789#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y_MASK 0xf0000000
6790#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y__SHIFT 0x1c
6791#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X_MASK 0xf
6792#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X__SHIFT 0x0
6793#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y_MASK 0xf0
6794#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y__SHIFT 0x4
6795#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X_MASK 0xf00
6796#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X__SHIFT 0x8
6797#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y_MASK 0xf000
6798#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y__SHIFT 0xc
6799#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X_MASK 0xf0000
6800#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X__SHIFT 0x10
6801#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y_MASK 0xf00000
6802#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y__SHIFT 0x14
6803#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X_MASK 0xf000000
6804#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X__SHIFT 0x18
6805#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y_MASK 0xf0000000
6806#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y__SHIFT 0x1c
6807#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X_MASK 0xf
6808#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X__SHIFT 0x0
6809#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y_MASK 0xf0
6810#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y__SHIFT 0x4
6811#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X_MASK 0xf00
6812#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X__SHIFT 0x8
6813#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y_MASK 0xf000
6814#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y__SHIFT 0xc
6815#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X_MASK 0xf0000
6816#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X__SHIFT 0x10
6817#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y_MASK 0xf00000
6818#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y__SHIFT 0x14
6819#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X_MASK 0xf000000
6820#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X__SHIFT 0x18
6821#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y_MASK 0xf0000000
6822#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y__SHIFT 0x1c
6823#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X_MASK 0xf
6824#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X__SHIFT 0x0
6825#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y_MASK 0xf0
6826#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y__SHIFT 0x4
6827#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X_MASK 0xf00
6828#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X__SHIFT 0x8
6829#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y_MASK 0xf000
6830#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y__SHIFT 0xc
6831#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X_MASK 0xf0000
6832#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X__SHIFT 0x10
6833#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y_MASK 0xf00000
6834#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y__SHIFT 0x14
6835#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X_MASK 0xf000000
6836#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X__SHIFT 0x18
6837#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y_MASK 0xf0000000
6838#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y__SHIFT 0x1c
6839#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X_MASK 0xf
6840#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X__SHIFT 0x0
6841#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y_MASK 0xf0
6842#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y__SHIFT 0x4
6843#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X_MASK 0xf00
6844#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X__SHIFT 0x8
6845#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y_MASK 0xf000
6846#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y__SHIFT 0xc
6847#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X_MASK 0xf0000
6848#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X__SHIFT 0x10
6849#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y_MASK 0xf00000
6850#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y__SHIFT 0x14
6851#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X_MASK 0xf000000
6852#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X__SHIFT 0x18
6853#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y_MASK 0xf0000000
6854#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y__SHIFT 0x1c
6855#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X_MASK 0xf
6856#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X__SHIFT 0x0
6857#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y_MASK 0xf0
6858#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y__SHIFT 0x4
6859#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X_MASK 0xf00
6860#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X__SHIFT 0x8
6861#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y_MASK 0xf000
6862#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y__SHIFT 0xc
6863#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X_MASK 0xf0000
6864#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X__SHIFT 0x10
6865#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y_MASK 0xf00000
6866#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y__SHIFT 0x14
6867#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X_MASK 0xf000000
6868#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X__SHIFT 0x18
6869#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y_MASK 0xf0000000
6870#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y__SHIFT 0x1c
6871#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X_MASK 0xf
6872#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X__SHIFT 0x0
6873#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y_MASK 0xf0
6874#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y__SHIFT 0x4
6875#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X_MASK 0xf00
6876#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X__SHIFT 0x8
6877#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y_MASK 0xf000
6878#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y__SHIFT 0xc
6879#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X_MASK 0xf0000
6880#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X__SHIFT 0x10
6881#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y_MASK 0xf00000
6882#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y__SHIFT 0x14
6883#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X_MASK 0xf000000
6884#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X__SHIFT 0x18
6885#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y_MASK 0xf0000000
6886#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y__SHIFT 0x1c
6887#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0_MASK 0xf
6888#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0__SHIFT 0x0
6889#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1_MASK 0xf0
6890#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1__SHIFT 0x4
6891#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2_MASK 0xf00
6892#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2__SHIFT 0x8
6893#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3_MASK 0xf000
6894#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3__SHIFT 0xc
6895#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4_MASK 0xf0000
6896#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4__SHIFT 0x10
6897#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5_MASK 0xf00000
6898#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5__SHIFT 0x14
6899#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6_MASK 0xf000000
6900#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6__SHIFT 0x18
6901#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7_MASK 0xf0000000
6902#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7__SHIFT 0x1c
6903#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8_MASK 0xf
6904#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8__SHIFT 0x0
6905#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9_MASK 0xf0
6906#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9__SHIFT 0x4
6907#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10_MASK 0xf00
6908#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10__SHIFT 0x8
6909#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11_MASK 0xf000
6910#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11__SHIFT 0xc
6911#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12_MASK 0xf0000
6912#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12__SHIFT 0x10
6913#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13_MASK 0xf00000
6914#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13__SHIFT 0x14
6915#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14_MASK 0xf000000
6916#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14__SHIFT 0x18
6917#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15_MASK 0xf0000000
6918#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15__SHIFT 0x1c
6919#define PA_SC_CLIPRECT_0_TL__TL_X_MASK 0x7fff
6920#define PA_SC_CLIPRECT_0_TL__TL_X__SHIFT 0x0
6921#define PA_SC_CLIPRECT_0_TL__TL_Y_MASK 0x7fff0000
6922#define PA_SC_CLIPRECT_0_TL__TL_Y__SHIFT 0x10
6923#define PA_SC_CLIPRECT_0_BR__BR_X_MASK 0x7fff
6924#define PA_SC_CLIPRECT_0_BR__BR_X__SHIFT 0x0
6925#define PA_SC_CLIPRECT_0_BR__BR_Y_MASK 0x7fff0000
6926#define PA_SC_CLIPRECT_0_BR__BR_Y__SHIFT 0x10
6927#define PA_SC_CLIPRECT_1_TL__TL_X_MASK 0x7fff
6928#define PA_SC_CLIPRECT_1_TL__TL_X__SHIFT 0x0
6929#define PA_SC_CLIPRECT_1_TL__TL_Y_MASK 0x7fff0000
6930#define PA_SC_CLIPRECT_1_TL__TL_Y__SHIFT 0x10
6931#define PA_SC_CLIPRECT_1_BR__BR_X_MASK 0x7fff
6932#define PA_SC_CLIPRECT_1_BR__BR_X__SHIFT 0x0
6933#define PA_SC_CLIPRECT_1_BR__BR_Y_MASK 0x7fff0000
6934#define PA_SC_CLIPRECT_1_BR__BR_Y__SHIFT 0x10
6935#define PA_SC_CLIPRECT_2_TL__TL_X_MASK 0x7fff
6936#define PA_SC_CLIPRECT_2_TL__TL_X__SHIFT 0x0
6937#define PA_SC_CLIPRECT_2_TL__TL_Y_MASK 0x7fff0000
6938#define PA_SC_CLIPRECT_2_TL__TL_Y__SHIFT 0x10
6939#define PA_SC_CLIPRECT_2_BR__BR_X_MASK 0x7fff
6940#define PA_SC_CLIPRECT_2_BR__BR_X__SHIFT 0x0
6941#define PA_SC_CLIPRECT_2_BR__BR_Y_MASK 0x7fff0000
6942#define PA_SC_CLIPRECT_2_BR__BR_Y__SHIFT 0x10
6943#define PA_SC_CLIPRECT_3_TL__TL_X_MASK 0x7fff
6944#define PA_SC_CLIPRECT_3_TL__TL_X__SHIFT 0x0
6945#define PA_SC_CLIPRECT_3_TL__TL_Y_MASK 0x7fff0000
6946#define PA_SC_CLIPRECT_3_TL__TL_Y__SHIFT 0x10
6947#define PA_SC_CLIPRECT_3_BR__BR_X_MASK 0x7fff
6948#define PA_SC_CLIPRECT_3_BR__BR_X__SHIFT 0x0
6949#define PA_SC_CLIPRECT_3_BR__BR_Y_MASK 0x7fff0000
6950#define PA_SC_CLIPRECT_3_BR__BR_Y__SHIFT 0x10
6951#define PA_SC_CLIPRECT_RULE__CLIP_RULE_MASK 0xffff
6952#define PA_SC_CLIPRECT_RULE__CLIP_RULE__SHIFT 0x0
6953#define PA_SC_EDGERULE__ER_TRI_MASK 0xf
6954#define PA_SC_EDGERULE__ER_TRI__SHIFT 0x0
6955#define PA_SC_EDGERULE__ER_POINT_MASK 0xf0
6956#define PA_SC_EDGERULE__ER_POINT__SHIFT 0x4
6957#define PA_SC_EDGERULE__ER_RECT_MASK 0xf00
6958#define PA_SC_EDGERULE__ER_RECT__SHIFT 0x8
6959#define PA_SC_EDGERULE__ER_LINE_LR_MASK 0x3f000
6960#define PA_SC_EDGERULE__ER_LINE_LR__SHIFT 0xc
6961#define PA_SC_EDGERULE__ER_LINE_RL_MASK 0xfc0000
6962#define PA_SC_EDGERULE__ER_LINE_RL__SHIFT 0x12
6963#define PA_SC_EDGERULE__ER_LINE_TB_MASK 0xf000000
6964#define PA_SC_EDGERULE__ER_LINE_TB__SHIFT 0x18
6965#define PA_SC_EDGERULE__ER_LINE_BT_MASK 0xf0000000
6966#define PA_SC_EDGERULE__ER_LINE_BT__SHIFT 0x1c
6967#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH_MASK 0x200
6968#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH__SHIFT 0x9
6969#define PA_SC_LINE_CNTL__LAST_PIXEL_MASK 0x400
6970#define PA_SC_LINE_CNTL__LAST_PIXEL__SHIFT 0xa
6971#define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA_MASK 0x800
6972#define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA__SHIFT 0xb
6973#define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA_MASK 0x1000
6974#define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA__SHIFT 0xc
6975#define PA_SC_LINE_STIPPLE__LINE_PATTERN_MASK 0xffff
6976#define PA_SC_LINE_STIPPLE__LINE_PATTERN__SHIFT 0x0
6977#define PA_SC_LINE_STIPPLE__REPEAT_COUNT_MASK 0xff0000
6978#define PA_SC_LINE_STIPPLE__REPEAT_COUNT__SHIFT 0x10
6979#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER_MASK 0x10000000
6980#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER__SHIFT 0x1c
6981#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL_MASK 0x60000000
6982#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL__SHIFT 0x1d
6983#define PA_SC_MODE_CNTL_0__MSAA_ENABLE_MASK 0x1
6984#define PA_SC_MODE_CNTL_0__MSAA_ENABLE__SHIFT 0x0
6985#define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE_MASK 0x2
6986#define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE__SHIFT 0x1
6987#define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE_MASK 0x4
6988#define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE__SHIFT 0x2
6989#define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR_MASK 0x8
6990#define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR__SHIFT 0x3
6991#define PA_SC_MODE_CNTL_1__WALK_SIZE_MASK 0x1
6992#define PA_SC_MODE_CNTL_1__WALK_SIZE__SHIFT 0x0
6993#define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT_MASK 0x2
6994#define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT__SHIFT 0x1
6995#define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST_MASK 0x4
6996#define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST__SHIFT 0x2
6997#define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE_MASK 0x8
6998#define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE__SHIFT 0x3
6999#define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE_MASK 0x70
7000#define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE__SHIFT 0x4
7001#define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE_MASK 0x80
7002#define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE__SHIFT 0x7
7003#define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE_MASK 0x100
7004#define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE__SHIFT 0x8
7005#define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE_MASK 0x200
7006#define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE__SHIFT 0x9
7007#define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR_MASK 0x400
7008#define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR__SHIFT 0xa
7009#define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT_MASK 0x800
7010#define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT__SHIFT 0xb
7011#define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET_MASK 0x1000
7012#define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET__SHIFT 0xc
7013#define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT_MASK 0x2000
7014#define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT__SHIFT 0xd
7015#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z_MASK 0x4000
7016#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z__SHIFT 0xe
7017#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK_MASK 0x8000
7018#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK__SHIFT 0xf
7019#define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE_MASK 0x10000
7020#define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE__SHIFT 0x10
7021#define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE_MASK 0x20000
7022#define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE__SHIFT 0x11
7023#define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE_MASK 0x40000
7024#define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE__SHIFT 0x12
7025#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE_MASK 0x80000
7026#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE__SHIFT 0x13
7027#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_MASK 0xf00000
7028#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE__SHIFT 0x14
7029#define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE_MASK 0x1000000
7030#define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE__SHIFT 0x18
7031#define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE_MASK 0x2000000
7032#define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE__SHIFT 0x19
7033#define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE_MASK 0x4000000
7034#define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE__SHIFT 0x1a
7035#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE_MASK 0x8000000
7036#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE__SHIFT 0x1b
7037#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK_MASK 0x70000000
7038#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK__SHIFT 0x1c
7039#define PA_SC_RASTER_CONFIG__RB_MAP_PKR0_MASK 0x3
7040#define PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT 0x0
7041#define PA_SC_RASTER_CONFIG__RB_MAP_PKR1_MASK 0xc
7042#define PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT 0x2
7043#define PA_SC_RASTER_CONFIG__RB_XSEL2_MASK 0x30
7044#define PA_SC_RASTER_CONFIG__RB_XSEL2__SHIFT 0x4
7045#define PA_SC_RASTER_CONFIG__RB_XSEL_MASK 0x40
7046#define PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT 0x6
7047#define PA_SC_RASTER_CONFIG__RB_YSEL_MASK 0x80
7048#define PA_SC_RASTER_CONFIG__RB_YSEL__SHIFT 0x7
7049#define PA_SC_RASTER_CONFIG__PKR_MAP_MASK 0x300
7050#define PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT 0x8
7051#define PA_SC_RASTER_CONFIG__PKR_XSEL_MASK 0xc00
7052#define PA_SC_RASTER_CONFIG__PKR_XSEL__SHIFT 0xa
7053#define PA_SC_RASTER_CONFIG__PKR_YSEL_MASK 0x3000
7054#define PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT 0xc
7055#define PA_SC_RASTER_CONFIG__PKR_XSEL2_MASK 0xc000
7056#define PA_SC_RASTER_CONFIG__PKR_XSEL2__SHIFT 0xe
7057#define PA_SC_RASTER_CONFIG__SC_MAP_MASK 0x30000
7058#define PA_SC_RASTER_CONFIG__SC_MAP__SHIFT 0x10
7059#define PA_SC_RASTER_CONFIG__SC_XSEL_MASK 0xc0000
7060#define PA_SC_RASTER_CONFIG__SC_XSEL__SHIFT 0x12
7061#define PA_SC_RASTER_CONFIG__SC_YSEL_MASK 0x300000
7062#define PA_SC_RASTER_CONFIG__SC_YSEL__SHIFT 0x14
7063#define PA_SC_RASTER_CONFIG__SE_MAP_MASK 0x3000000
7064#define PA_SC_RASTER_CONFIG__SE_MAP__SHIFT 0x18
7065#define PA_SC_RASTER_CONFIG__SE_XSEL_MASK 0xc000000
7066#define PA_SC_RASTER_CONFIG__SE_XSEL__SHIFT 0x1a
7067#define PA_SC_RASTER_CONFIG__SE_YSEL_MASK 0x30000000
7068#define PA_SC_RASTER_CONFIG__SE_YSEL__SHIFT 0x1c
7069#define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP_MASK 0x3
7070#define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP__SHIFT 0x0
7071#define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL_MASK 0xc
7072#define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL__SHIFT 0x2
7073#define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL_MASK 0x30
7074#define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL__SHIFT 0x4
7075#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE_MASK 0x3
7076#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE__SHIFT 0x0
7077#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE_MASK 0xc
7078#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE__SHIFT 0x2
7079#define PA_SC_GENERIC_SCISSOR_TL__TL_X_MASK 0x7fff
7080#define PA_SC_GENERIC_SCISSOR_TL__TL_X__SHIFT 0x0
7081#define PA_SC_GENERIC_SCISSOR_TL__TL_Y_MASK 0x7fff0000
7082#define PA_SC_GENERIC_SCISSOR_TL__TL_Y__SHIFT 0x10
7083#define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
7084#define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
7085#define PA_SC_GENERIC_SCISSOR_BR__BR_X_MASK 0x7fff
7086#define PA_SC_GENERIC_SCISSOR_BR__BR_X__SHIFT 0x0
7087#define PA_SC_GENERIC_SCISSOR_BR__BR_Y_MASK 0x7fff0000
7088#define PA_SC_GENERIC_SCISSOR_BR__BR_Y__SHIFT 0x10
7089#define PA_SC_SCREEN_SCISSOR_TL__TL_X_MASK 0xffff
7090#define PA_SC_SCREEN_SCISSOR_TL__TL_X__SHIFT 0x0
7091#define PA_SC_SCREEN_SCISSOR_TL__TL_Y_MASK 0xffff0000
7092#define PA_SC_SCREEN_SCISSOR_TL__TL_Y__SHIFT 0x10
7093#define PA_SC_SCREEN_SCISSOR_BR__BR_X_MASK 0xffff
7094#define PA_SC_SCREEN_SCISSOR_BR__BR_X__SHIFT 0x0
7095#define PA_SC_SCREEN_SCISSOR_BR__BR_Y_MASK 0xffff0000
7096#define PA_SC_SCREEN_SCISSOR_BR__BR_Y__SHIFT 0x10
7097#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET_MASK 0xffff
7098#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET__SHIFT 0x0
7099#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET_MASK 0xffff0000
7100#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET__SHIFT 0x10
7101#define PA_SC_WINDOW_SCISSOR_TL__TL_X_MASK 0x7fff
7102#define PA_SC_WINDOW_SCISSOR_TL__TL_X__SHIFT 0x0
7103#define PA_SC_WINDOW_SCISSOR_TL__TL_Y_MASK 0x7fff0000
7104#define PA_SC_WINDOW_SCISSOR_TL__TL_Y__SHIFT 0x10
7105#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
7106#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
7107#define PA_SC_WINDOW_SCISSOR_BR__BR_X_MASK 0x7fff
7108#define PA_SC_WINDOW_SCISSOR_BR__BR_X__SHIFT 0x0
7109#define PA_SC_WINDOW_SCISSOR_BR__BR_Y_MASK 0x7fff0000
7110#define PA_SC_WINDOW_SCISSOR_BR__BR_Y__SHIFT 0x10
7111#define PA_SC_VPORT_SCISSOR_0_TL__TL_X_MASK 0x7fff
7112#define PA_SC_VPORT_SCISSOR_0_TL__TL_X__SHIFT 0x0
7113#define PA_SC_VPORT_SCISSOR_0_TL__TL_Y_MASK 0x7fff0000
7114#define PA_SC_VPORT_SCISSOR_0_TL__TL_Y__SHIFT 0x10
7115#define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
7116#define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
7117#define PA_SC_VPORT_SCISSOR_1_TL__TL_X_MASK 0x7fff
7118#define PA_SC_VPORT_SCISSOR_1_TL__TL_X__SHIFT 0x0
7119#define PA_SC_VPORT_SCISSOR_1_TL__TL_Y_MASK 0x7fff0000
7120#define PA_SC_VPORT_SCISSOR_1_TL__TL_Y__SHIFT 0x10
7121#define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
7122#define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
7123#define PA_SC_VPORT_SCISSOR_2_TL__TL_X_MASK 0x7fff
7124#define PA_SC_VPORT_SCISSOR_2_TL__TL_X__SHIFT 0x0
7125#define PA_SC_VPORT_SCISSOR_2_TL__TL_Y_MASK 0x7fff0000
7126#define PA_SC_VPORT_SCISSOR_2_TL__TL_Y__SHIFT 0x10
7127#define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
7128#define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
7129#define PA_SC_VPORT_SCISSOR_3_TL__TL_X_MASK 0x7fff
7130#define PA_SC_VPORT_SCISSOR_3_TL__TL_X__SHIFT 0x0
7131#define PA_SC_VPORT_SCISSOR_3_TL__TL_Y_MASK 0x7fff0000
7132#define PA_SC_VPORT_SCISSOR_3_TL__TL_Y__SHIFT 0x10
7133#define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
7134#define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
7135#define PA_SC_VPORT_SCISSOR_4_TL__TL_X_MASK 0x7fff
7136#define PA_SC_VPORT_SCISSOR_4_TL__TL_X__SHIFT 0x0
7137#define PA_SC_VPORT_SCISSOR_4_TL__TL_Y_MASK 0x7fff0000
7138#define PA_SC_VPORT_SCISSOR_4_TL__TL_Y__SHIFT 0x10
7139#define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
7140#define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
7141#define PA_SC_VPORT_SCISSOR_5_TL__TL_X_MASK 0x7fff
7142#define PA_SC_VPORT_SCISSOR_5_TL__TL_X__SHIFT 0x0
7143#define PA_SC_VPORT_SCISSOR_5_TL__TL_Y_MASK 0x7fff0000
7144#define PA_SC_VPORT_SCISSOR_5_TL__TL_Y__SHIFT 0x10
7145#define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
7146#define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
7147#define PA_SC_VPORT_SCISSOR_6_TL__TL_X_MASK 0x7fff
7148#define PA_SC_VPORT_SCISSOR_6_TL__TL_X__SHIFT 0x0
7149#define PA_SC_VPORT_SCISSOR_6_TL__TL_Y_MASK 0x7fff0000
7150#define PA_SC_VPORT_SCISSOR_6_TL__TL_Y__SHIFT 0x10
7151#define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
7152#define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
7153#define PA_SC_VPORT_SCISSOR_7_TL__TL_X_MASK 0x7fff
7154#define PA_SC_VPORT_SCISSOR_7_TL__TL_X__SHIFT 0x0
7155#define PA_SC_VPORT_SCISSOR_7_TL__TL_Y_MASK 0x7fff0000
7156#define PA_SC_VPORT_SCISSOR_7_TL__TL_Y__SHIFT 0x10
7157#define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
7158#define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
7159#define PA_SC_VPORT_SCISSOR_8_TL__TL_X_MASK 0x7fff
7160#define PA_SC_VPORT_SCISSOR_8_TL__TL_X__SHIFT 0x0
7161#define PA_SC_VPORT_SCISSOR_8_TL__TL_Y_MASK 0x7fff0000
7162#define PA_SC_VPORT_SCISSOR_8_TL__TL_Y__SHIFT 0x10
7163#define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
7164#define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
7165#define PA_SC_VPORT_SCISSOR_9_TL__TL_X_MASK 0x7fff
7166#define PA_SC_VPORT_SCISSOR_9_TL__TL_X__SHIFT 0x0
7167#define PA_SC_VPORT_SCISSOR_9_TL__TL_Y_MASK 0x7fff0000
7168#define PA_SC_VPORT_SCISSOR_9_TL__TL_Y__SHIFT 0x10
7169#define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
7170#define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
7171#define PA_SC_VPORT_SCISSOR_10_TL__TL_X_MASK 0x7fff
7172#define PA_SC_VPORT_SCISSOR_10_TL__TL_X__SHIFT 0x0
7173#define PA_SC_VPORT_SCISSOR_10_TL__TL_Y_MASK 0x7fff0000
7174#define PA_SC_VPORT_SCISSOR_10_TL__TL_Y__SHIFT 0x10
7175#define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
7176#define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
7177#define PA_SC_VPORT_SCISSOR_11_TL__TL_X_MASK 0x7fff
7178#define PA_SC_VPORT_SCISSOR_11_TL__TL_X__SHIFT 0x0
7179#define PA_SC_VPORT_SCISSOR_11_TL__TL_Y_MASK 0x7fff0000
7180#define PA_SC_VPORT_SCISSOR_11_TL__TL_Y__SHIFT 0x10
7181#define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
7182#define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
7183#define PA_SC_VPORT_SCISSOR_12_TL__TL_X_MASK 0x7fff
7184#define PA_SC_VPORT_SCISSOR_12_TL__TL_X__SHIFT 0x0
7185#define PA_SC_VPORT_SCISSOR_12_TL__TL_Y_MASK 0x7fff0000
7186#define PA_SC_VPORT_SCISSOR_12_TL__TL_Y__SHIFT 0x10
7187#define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
7188#define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
7189#define PA_SC_VPORT_SCISSOR_13_TL__TL_X_MASK 0x7fff
7190#define PA_SC_VPORT_SCISSOR_13_TL__TL_X__SHIFT 0x0
7191#define PA_SC_VPORT_SCISSOR_13_TL__TL_Y_MASK 0x7fff0000
7192#define PA_SC_VPORT_SCISSOR_13_TL__TL_Y__SHIFT 0x10
7193#define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
7194#define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
7195#define PA_SC_VPORT_SCISSOR_14_TL__TL_X_MASK 0x7fff
7196#define PA_SC_VPORT_SCISSOR_14_TL__TL_X__SHIFT 0x0
7197#define PA_SC_VPORT_SCISSOR_14_TL__TL_Y_MASK 0x7fff0000
7198#define PA_SC_VPORT_SCISSOR_14_TL__TL_Y__SHIFT 0x10
7199#define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
7200#define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
7201#define PA_SC_VPORT_SCISSOR_15_TL__TL_X_MASK 0x7fff
7202#define PA_SC_VPORT_SCISSOR_15_TL__TL_X__SHIFT 0x0
7203#define PA_SC_VPORT_SCISSOR_15_TL__TL_Y_MASK 0x7fff0000
7204#define PA_SC_VPORT_SCISSOR_15_TL__TL_Y__SHIFT 0x10
7205#define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
7206#define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
7207#define PA_SC_VPORT_SCISSOR_0_BR__BR_X_MASK 0x7fff
7208#define PA_SC_VPORT_SCISSOR_0_BR__BR_X__SHIFT 0x0
7209#define PA_SC_VPORT_SCISSOR_0_BR__BR_Y_MASK 0x7fff0000
7210#define PA_SC_VPORT_SCISSOR_0_BR__BR_Y__SHIFT 0x10
7211#define PA_SC_VPORT_SCISSOR_1_BR__BR_X_MASK 0x7fff
7212#define PA_SC_VPORT_SCISSOR_1_BR__BR_X__SHIFT 0x0
7213#define PA_SC_VPORT_SCISSOR_1_BR__BR_Y_MASK 0x7fff0000
7214#define PA_SC_VPORT_SCISSOR_1_BR__BR_Y__SHIFT 0x10
7215#define PA_SC_VPORT_SCISSOR_2_BR__BR_X_MASK 0x7fff
7216#define PA_SC_VPORT_SCISSOR_2_BR__BR_X__SHIFT 0x0
7217#define PA_SC_VPORT_SCISSOR_2_BR__BR_Y_MASK 0x7fff0000
7218#define PA_SC_VPORT_SCISSOR_2_BR__BR_Y__SHIFT 0x10
7219#define PA_SC_VPORT_SCISSOR_3_BR__BR_X_MASK 0x7fff
7220#define PA_SC_VPORT_SCISSOR_3_BR__BR_X__SHIFT 0x0
7221#define PA_SC_VPORT_SCISSOR_3_BR__BR_Y_MASK 0x7fff0000
7222#define PA_SC_VPORT_SCISSOR_3_BR__BR_Y__SHIFT 0x10
7223#define PA_SC_VPORT_SCISSOR_4_BR__BR_X_MASK 0x7fff
7224#define PA_SC_VPORT_SCISSOR_4_BR__BR_X__SHIFT 0x0
7225#define PA_SC_VPORT_SCISSOR_4_BR__BR_Y_MASK 0x7fff0000
7226#define PA_SC_VPORT_SCISSOR_4_BR__BR_Y__SHIFT 0x10
7227#define PA_SC_VPORT_SCISSOR_5_BR__BR_X_MASK 0x7fff
7228#define PA_SC_VPORT_SCISSOR_5_BR__BR_X__SHIFT 0x0
7229#define PA_SC_VPORT_SCISSOR_5_BR__BR_Y_MASK 0x7fff0000
7230#define PA_SC_VPORT_SCISSOR_5_BR__BR_Y__SHIFT 0x10
7231#define PA_SC_VPORT_SCISSOR_6_BR__BR_X_MASK 0x7fff
7232#define PA_SC_VPORT_SCISSOR_6_BR__BR_X__SHIFT 0x0
7233#define PA_SC_VPORT_SCISSOR_6_BR__BR_Y_MASK 0x7fff0000
7234#define PA_SC_VPORT_SCISSOR_6_BR__BR_Y__SHIFT 0x10
7235#define PA_SC_VPORT_SCISSOR_7_BR__BR_X_MASK 0x7fff
7236#define PA_SC_VPORT_SCISSOR_7_BR__BR_X__SHIFT 0x0
7237#define PA_SC_VPORT_SCISSOR_7_BR__BR_Y_MASK 0x7fff0000
7238#define PA_SC_VPORT_SCISSOR_7_BR__BR_Y__SHIFT 0x10
7239#define PA_SC_VPORT_SCISSOR_8_BR__BR_X_MASK 0x7fff
7240#define PA_SC_VPORT_SCISSOR_8_BR__BR_X__SHIFT 0x0
7241#define PA_SC_VPORT_SCISSOR_8_BR__BR_Y_MASK 0x7fff0000
7242#define PA_SC_VPORT_SCISSOR_8_BR__BR_Y__SHIFT 0x10
7243#define PA_SC_VPORT_SCISSOR_9_BR__BR_X_MASK 0x7fff
7244#define PA_SC_VPORT_SCISSOR_9_BR__BR_X__SHIFT 0x0
7245#define PA_SC_VPORT_SCISSOR_9_BR__BR_Y_MASK 0x7fff0000
7246#define PA_SC_VPORT_SCISSOR_9_BR__BR_Y__SHIFT 0x10
7247#define PA_SC_VPORT_SCISSOR_10_BR__BR_X_MASK 0x7fff
7248#define PA_SC_VPORT_SCISSOR_10_BR__BR_X__SHIFT 0x0
7249#define PA_SC_VPORT_SCISSOR_10_BR__BR_Y_MASK 0x7fff0000
7250#define PA_SC_VPORT_SCISSOR_10_BR__BR_Y__SHIFT 0x10
7251#define PA_SC_VPORT_SCISSOR_11_BR__BR_X_MASK 0x7fff
7252#define PA_SC_VPORT_SCISSOR_11_BR__BR_X__SHIFT 0x0
7253#define PA_SC_VPORT_SCISSOR_11_BR__BR_Y_MASK 0x7fff0000
7254#define PA_SC_VPORT_SCISSOR_11_BR__BR_Y__SHIFT 0x10
7255#define PA_SC_VPORT_SCISSOR_12_BR__BR_X_MASK 0x7fff
7256#define PA_SC_VPORT_SCISSOR_12_BR__BR_X__SHIFT 0x0
7257#define PA_SC_VPORT_SCISSOR_12_BR__BR_Y_MASK 0x7fff0000
7258#define PA_SC_VPORT_SCISSOR_12_BR__BR_Y__SHIFT 0x10
7259#define PA_SC_VPORT_SCISSOR_13_BR__BR_X_MASK 0x7fff
7260#define PA_SC_VPORT_SCISSOR_13_BR__BR_X__SHIFT 0x0
7261#define PA_SC_VPORT_SCISSOR_13_BR__BR_Y_MASK 0x7fff0000
7262#define PA_SC_VPORT_SCISSOR_13_BR__BR_Y__SHIFT 0x10
7263#define PA_SC_VPORT_SCISSOR_14_BR__BR_X_MASK 0x7fff
7264#define PA_SC_VPORT_SCISSOR_14_BR__BR_X__SHIFT 0x0
7265#define PA_SC_VPORT_SCISSOR_14_BR__BR_Y_MASK 0x7fff0000
7266#define PA_SC_VPORT_SCISSOR_14_BR__BR_Y__SHIFT 0x10
7267#define PA_SC_VPORT_SCISSOR_15_BR__BR_X_MASK 0x7fff
7268#define PA_SC_VPORT_SCISSOR_15_BR__BR_X__SHIFT 0x0
7269#define PA_SC_VPORT_SCISSOR_15_BR__BR_Y_MASK 0x7fff0000
7270#define PA_SC_VPORT_SCISSOR_15_BR__BR_Y__SHIFT 0x10
7271#define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN_MASK 0xffffffff
7272#define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN__SHIFT 0x0
7273#define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN_MASK 0xffffffff
7274#define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN__SHIFT 0x0
7275#define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN_MASK 0xffffffff
7276#define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN__SHIFT 0x0
7277#define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN_MASK 0xffffffff
7278#define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN__SHIFT 0x0
7279#define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN_MASK 0xffffffff
7280#define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN__SHIFT 0x0
7281#define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN_MASK 0xffffffff
7282#define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN__SHIFT 0x0
7283#define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN_MASK 0xffffffff
7284#define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN__SHIFT 0x0
7285#define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN_MASK 0xffffffff
7286#define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN__SHIFT 0x0
7287#define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN_MASK 0xffffffff
7288#define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN__SHIFT 0x0
7289#define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN_MASK 0xffffffff
7290#define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN__SHIFT 0x0
7291#define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN_MASK 0xffffffff
7292#define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN__SHIFT 0x0
7293#define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN_MASK 0xffffffff
7294#define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN__SHIFT 0x0
7295#define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN_MASK 0xffffffff
7296#define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN__SHIFT 0x0
7297#define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN_MASK 0xffffffff
7298#define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN__SHIFT 0x0
7299#define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN_MASK 0xffffffff
7300#define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN__SHIFT 0x0
7301#define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN_MASK 0xffffffff
7302#define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN__SHIFT 0x0
7303#define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX_MASK 0xffffffff
7304#define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX__SHIFT 0x0
7305#define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX_MASK 0xffffffff
7306#define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX__SHIFT 0x0
7307#define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX_MASK 0xffffffff
7308#define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX__SHIFT 0x0
7309#define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX_MASK 0xffffffff
7310#define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX__SHIFT 0x0
7311#define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX_MASK 0xffffffff
7312#define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX__SHIFT 0x0
7313#define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX_MASK 0xffffffff
7314#define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX__SHIFT 0x0
7315#define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX_MASK 0xffffffff
7316#define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX__SHIFT 0x0
7317#define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX_MASK 0xffffffff
7318#define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX__SHIFT 0x0
7319#define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX_MASK 0xffffffff
7320#define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX__SHIFT 0x0
7321#define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX_MASK 0xffffffff
7322#define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX__SHIFT 0x0
7323#define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX_MASK 0xffffffff
7324#define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX__SHIFT 0x0
7325#define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX_MASK 0xffffffff
7326#define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX__SHIFT 0x0
7327#define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX_MASK 0xffffffff
7328#define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX__SHIFT 0x0
7329#define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX_MASK 0xffffffff
7330#define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX__SHIFT 0x0
7331#define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX_MASK 0xffffffff
7332#define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX__SHIFT 0x0
7333#define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX_MASK 0xffffffff
7334#define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX__SHIFT 0x0
7335#define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK 0x1
7336#define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER__SHIFT 0x0
7337#define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX_MASK 0x2
7338#define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX__SHIFT 0x1
7339#define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX_MASK 0x4
7340#define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX__SHIFT 0x2
7341#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS_MASK 0x8
7342#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS__SHIFT 0x3
7343#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID_MASK 0x10
7344#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID__SHIFT 0x4
7345#define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX_MASK 0x20
7346#define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX__SHIFT 0x5
7347#define PA_SC_ENHANCE__DISABLE_PW_BUBBLE_COLLAPSE_MASK 0xc0
7348#define PA_SC_ENHANCE__DISABLE_PW_BUBBLE_COLLAPSE__SHIFT 0x6
7349#define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER_MASK 0x100
7350#define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER__SHIFT 0x8
7351#define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION_MASK 0x200
7352#define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION__SHIFT 0x9
7353#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM_MASK 0x400
7354#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM__SHIFT 0xa
7355#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE_MASK 0x800
7356#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE__SHIFT 0xb
7357#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE_MASK 0x1000
7358#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE__SHIFT 0xc
7359#define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE_MASK 0x2000
7360#define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE__SHIFT 0xd
7361#define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS_MASK 0x4000
7362#define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS__SHIFT 0xe
7363#define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE_MASK 0x8000
7364#define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE__SHIFT 0xf
7365#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE_MASK 0x10000
7366#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE__SHIFT 0x10
7367#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE_MASK 0x20000
7368#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE__SHIFT 0x11
7369#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST_MASK 0x40000
7370#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST__SHIFT 0x12
7371#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING_MASK 0x80000
7372#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING__SHIFT 0x13
7373#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY_MASK 0x100000
7374#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY__SHIFT 0x14
7375#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING_MASK 0x200000
7376#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING__SHIFT 0x15
7377#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING_MASK 0x400000
7378#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING__SHIFT 0x16
7379#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS_MASK 0x800000
7380#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS__SHIFT 0x17
7381#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID_MASK 0x1000000
7382#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID__SHIFT 0x18
7383#define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO_MASK 0x2000000
7384#define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO__SHIFT 0x19
7385#define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT_MASK 0x4000000
7386#define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT__SHIFT 0x1a
7387#define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING_MASK 0x8000000
7388#define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING__SHIFT 0x1b
7389#define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET_MASK 0x10000000
7390#define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET__SHIFT 0x1c
7391#define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET_MASK 0x20000000
7392#define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET__SHIFT 0x1d
7393#define PA_SC_ENHANCE__ECO_SPARE1_MASK 0x40000000
7394#define PA_SC_ENHANCE__ECO_SPARE1__SHIFT 0x1e
7395#define PA_SC_ENHANCE__ECO_SPARE0_MASK 0x80000000
7396#define PA_SC_ENHANCE__ECO_SPARE0__SHIFT 0x1f
7397#define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE_MASK 0x3f
7398#define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT 0x0
7399#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE_MASK 0x7fc0
7400#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT 0x6
7401#define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE_MASK 0x1f8000
7402#define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT 0xf
7403#define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE_MASK 0xff800000
7404#define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT 0x17
7405#define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE_MASK 0x3f
7406#define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE__SHIFT 0x0
7407#define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE_MASK 0xfc0
7408#define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE__SHIFT 0x6
7409#define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE_MASK 0x3f000
7410#define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE__SHIFT 0xc
7411#define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE_MASK 0xfc0000
7412#define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE__SHIFT 0x12
7413#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT_MASK 0xffff
7414#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT 0x0
7415#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT_MASK 0xffff0000
7416#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT 0x10
7417#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR_MASK 0xf
7418#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR__SHIFT 0x0
7419#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT_MASK 0xff00
7420#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT__SHIFT 0x8
7421#define PA_SC_SCREEN_EXTENT_MIN_0__X_MASK 0xffff
7422#define PA_SC_SCREEN_EXTENT_MIN_0__X__SHIFT 0x0
7423#define PA_SC_SCREEN_EXTENT_MIN_0__Y_MASK 0xffff0000
7424#define PA_SC_SCREEN_EXTENT_MIN_0__Y__SHIFT 0x10
7425#define PA_SC_SCREEN_EXTENT_MAX_0__X_MASK 0xffff
7426#define PA_SC_SCREEN_EXTENT_MAX_0__X__SHIFT 0x0
7427#define PA_SC_SCREEN_EXTENT_MAX_0__Y_MASK 0xffff0000
7428#define PA_SC_SCREEN_EXTENT_MAX_0__Y__SHIFT 0x10
7429#define PA_SC_SCREEN_EXTENT_MIN_1__X_MASK 0xffff
7430#define PA_SC_SCREEN_EXTENT_MIN_1__X__SHIFT 0x0
7431#define PA_SC_SCREEN_EXTENT_MIN_1__Y_MASK 0xffff0000
7432#define PA_SC_SCREEN_EXTENT_MIN_1__Y__SHIFT 0x10
7433#define PA_SC_SCREEN_EXTENT_MAX_1__X_MASK 0xffff
7434#define PA_SC_SCREEN_EXTENT_MAX_1__X__SHIFT 0x0
7435#define PA_SC_SCREEN_EXTENT_MAX_1__Y_MASK 0xffff0000
7436#define PA_SC_SCREEN_EXTENT_MAX_1__Y__SHIFT 0x10
7437#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff
7438#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
7439#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00
7440#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
7441#define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
7442#define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
7443#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff
7444#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
7445#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00
7446#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
7447#define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff
7448#define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
7449#define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff
7450#define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
7451#define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff
7452#define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
7453#define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x3ff
7454#define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0
7455#define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x3ff
7456#define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0
7457#define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0x3ff
7458#define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x0
7459#define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0x3ff
7460#define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x0
7461#define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
7462#define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
7463#define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
7464#define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
7465#define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
7466#define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
7467#define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
7468#define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
7469#define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
7470#define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
7471#define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
7472#define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
7473#define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
7474#define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
7475#define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
7476#define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
7477#define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xffffffff
7478#define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0
7479#define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xffffffff
7480#define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0
7481#define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xffffffff
7482#define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0
7483#define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xffffffff
7484#define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0
7485#define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xffffffff
7486#define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x0
7487#define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xffffffff
7488#define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x0
7489#define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xffffffff
7490#define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x0
7491#define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xffffffff
7492#define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x0
7493#define PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x1
7494#define PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0
7495#define PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x2
7496#define PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1
7497#define PA_SC_P3D_TRAP_SCREEN_H__X_COORD_MASK 0x3fff
7498#define PA_SC_P3D_TRAP_SCREEN_H__X_COORD__SHIFT 0x0
7499#define PA_SC_P3D_TRAP_SCREEN_V__Y_COORD_MASK 0x3fff
7500#define PA_SC_P3D_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0
7501#define PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0xffff
7502#define PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0
7503#define PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT_MASK 0xffff
7504#define PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0
7505#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x1
7506#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0
7507#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x2
7508#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1
7509#define PA_SC_HP3D_TRAP_SCREEN_H__X_COORD_MASK 0x3fff
7510#define PA_SC_HP3D_TRAP_SCREEN_H__X_COORD__SHIFT 0x0
7511#define PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD_MASK 0x3fff
7512#define PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0
7513#define PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0xffff
7514#define PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0
7515#define PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT_MASK 0xffff
7516#define PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0
7517#define PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x1
7518#define PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0
7519#define PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x2
7520#define PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1
7521#define PA_SC_TRAP_SCREEN_H__X_COORD_MASK 0x3fff
7522#define PA_SC_TRAP_SCREEN_H__X_COORD__SHIFT 0x0
7523#define PA_SC_TRAP_SCREEN_V__Y_COORD_MASK 0x3fff
7524#define PA_SC_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0
7525#define PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0xffff
7526#define PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0
7527#define PA_SC_TRAP_SCREEN_COUNT__COUNT_MASK 0xffff
7528#define PA_SC_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0
7529#define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x1
7530#define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0
7531#define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x1
7532#define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0
7533#define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x1
7534#define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0
7535#define PA_CL_CNTL_STATUS__CL_BUSY_MASK 0x80000000
7536#define PA_CL_CNTL_STATUS__CL_BUSY__SHIFT 0x1f
7537#define PA_SU_CNTL_STATUS__SU_BUSY_MASK 0x80000000
7538#define PA_SU_CNTL_STATUS__SU_BUSY__SHIFT 0x1f
7539#define PA_SC_FIFO_DEPTH_CNTL__DEPTH_MASK 0x3ff
7540#define PA_SC_FIFO_DEPTH_CNTL__DEPTH__SHIFT 0x0
7541#define CGTT_PA_CLK_CTRL__ON_DELAY_MASK 0xf
7542#define CGTT_PA_CLK_CTRL__ON_DELAY__SHIFT 0x0
7543#define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
7544#define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
7545#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
7546#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
7547#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
7548#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
7549#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
7550#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
7551#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
7552#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
7553#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
7554#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
7555#define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE_MASK 0x20000000
7556#define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE__SHIFT 0x1d
7557#define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE_MASK 0x40000000
7558#define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE__SHIFT 0x1e
7559#define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE_MASK 0x80000000
7560#define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE__SHIFT 0x1f
7561#define CGTT_SC_CLK_CTRL__ON_DELAY_MASK 0xf
7562#define CGTT_SC_CLK_CTRL__ON_DELAY__SHIFT 0x0
7563#define CGTT_SC_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
7564#define CGTT_SC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
7565#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
7566#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
7567#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
7568#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
7569#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
7570#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
7571#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
7572#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
7573#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
7574#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
7575#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
7576#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
7577#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
7578#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
7579#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
7580#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
7581#define PA_SU_DEBUG_CNTL__SU_DEBUG_INDX_MASK 0x1f
7582#define PA_SU_DEBUG_CNTL__SU_DEBUG_INDX__SHIFT 0x0
7583#define PA_SU_DEBUG_DATA__DATA_MASK 0xffffffff
7584#define PA_SU_DEBUG_DATA__DATA__SHIFT 0x0
7585#define PA_SC_DEBUG_CNTL__SC_DEBUG_INDX_MASK 0x3f
7586#define PA_SC_DEBUG_CNTL__SC_DEBUG_INDX__SHIFT 0x0
7587#define PA_SC_DEBUG_DATA__DATA_MASK 0xffffffff
7588#define PA_SC_DEBUG_DATA__DATA__SHIFT 0x0
7589#define CLIPPER_DEBUG_REG00__ALWAYS_ZERO_MASK 0xff
7590#define CLIPPER_DEBUG_REG00__ALWAYS_ZERO__SHIFT 0x0
7591#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write_MASK 0x100
7592#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write__SHIFT 0x8
7593#define CLIPPER_DEBUG_REG00__su_clip_baryc_free_MASK 0x600
7594#define CLIPPER_DEBUG_REG00__su_clip_baryc_free__SHIFT 0x9
7595#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write_MASK 0x800
7596#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write__SHIFT 0xb
7597#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full_MASK 0x1000
7598#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full__SHIFT 0xc
7599#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty_MASK 0x2000
7600#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty__SHIFT 0xd
7601#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full_MASK 0x4000
7602#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full__SHIFT 0xe
7603#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty_MASK 0x8000
7604#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty__SHIFT 0xf
7605#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full_MASK 0x10000
7606#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full__SHIFT 0x10
7607#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty_MASK 0x20000
7608#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty__SHIFT 0x11
7609#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full_MASK 0x40000
7610#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full__SHIFT 0x12
7611#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty_MASK 0x80000
7612#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty__SHIFT 0x13
7613#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full_MASK 0x100000
7614#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full__SHIFT 0x14
7615#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty_MASK 0x200000
7616#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty__SHIFT 0x15
7617#define CLIPPER_DEBUG_REG00__clipcode_fifo_full_MASK 0x400000
7618#define CLIPPER_DEBUG_REG00__clipcode_fifo_full__SHIFT 0x16
7619#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty_MASK 0x800000
7620#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty__SHIFT 0x17
7621#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full_MASK 0x1000000
7622#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full__SHIFT 0x18
7623#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty_MASK 0x2000000
7624#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty__SHIFT 0x19
7625#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full_MASK 0x4000000
7626#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full__SHIFT 0x1a
7627#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty_MASK 0x8000000
7628#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty__SHIFT 0x1b
7629#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full_MASK 0x10000000
7630#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full__SHIFT 0x1c
7631#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_write_MASK 0x20000000
7632#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_write__SHIFT 0x1d
7633#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_write_MASK 0x40000000
7634#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_write__SHIFT 0x1e
7635#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_write_MASK 0x80000000
7636#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_write__SHIFT 0x1f
7637#define CLIPPER_DEBUG_REG01__ALWAYS_ZERO_MASK 0xff
7638#define CLIPPER_DEBUG_REG01__ALWAYS_ZERO__SHIFT 0x0
7639#define CLIPPER_DEBUG_REG01__clip_extra_bc_valid_MASK 0x700
7640#define CLIPPER_DEBUG_REG01__clip_extra_bc_valid__SHIFT 0x8
7641#define CLIPPER_DEBUG_REG01__clip_vert_vte_valid_MASK 0x3800
7642#define CLIPPER_DEBUG_REG01__clip_vert_vte_valid__SHIFT 0xb
7643#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_deallocate_MASK 0x1c000
7644#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_deallocate__SHIFT 0xe
7645#define CLIPPER_DEBUG_REG01__clip_to_outsm_deallocate_slot_MASK 0xe0000
7646#define CLIPPER_DEBUG_REG01__clip_to_outsm_deallocate_slot__SHIFT 0x11
7647#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive_MASK 0x100000
7648#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive__SHIFT 0x14
7649#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_2_MASK 0x200000
7650#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_2__SHIFT 0x15
7651#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_1_MASK 0x400000
7652#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_1__SHIFT 0x16
7653#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_0_MASK 0x800000
7654#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_0__SHIFT 0x17
7655#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_extra_bc_valid_MASK 0x1000000
7656#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_extra_bc_valid__SHIFT 0x18
7657#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vte_naninf_kill_MASK 0x2000000
7658#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vte_naninf_kill__SHIFT 0x19
7659#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vertex_store_indx_MASK 0xc000000
7660#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vertex_store_indx__SHIFT 0x1a
7661#define CLIPPER_DEBUG_REG01__clip_ga_bc_fifo_write_MASK 0x10000000
7662#define CLIPPER_DEBUG_REG01__clip_ga_bc_fifo_write__SHIFT 0x1c
7663#define CLIPPER_DEBUG_REG01__clip_to_ga_fifo_write_MASK 0x20000000
7664#define CLIPPER_DEBUG_REG01__clip_to_ga_fifo_write__SHIFT 0x1d
7665#define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_advanceread_MASK 0x40000000
7666#define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_advanceread__SHIFT 0x1e
7667#define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_empty_MASK 0x80000000
7668#define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_empty__SHIFT 0x1f
7669#define CLIPPER_DEBUG_REG02__clip_extra_bc_valid_MASK 0x7
7670#define CLIPPER_DEBUG_REG02__clip_extra_bc_valid__SHIFT 0x0
7671#define CLIPPER_DEBUG_REG02__clip_vert_vte_valid_MASK 0x38
7672#define CLIPPER_DEBUG_REG02__clip_vert_vte_valid__SHIFT 0x3
7673#define CLIPPER_DEBUG_REG02__clip_to_outsm_clip_seq_indx_MASK 0xc0
7674#define CLIPPER_DEBUG_REG02__clip_to_outsm_clip_seq_indx__SHIFT 0x6
7675#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_2_MASK 0xf00
7676#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_2__SHIFT 0x8
7677#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_1_MASK 0xf000
7678#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_1__SHIFT 0xc
7679#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_0_MASK 0xf0000
7680#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_0__SHIFT 0x10
7681#define CLIPPER_DEBUG_REG02__clip_to_clipga_extra_bc_coords_MASK 0x100000
7682#define CLIPPER_DEBUG_REG02__clip_to_clipga_extra_bc_coords__SHIFT 0x14
7683#define CLIPPER_DEBUG_REG02__clip_to_clipga_vte_naninf_kill_MASK 0x200000
7684#define CLIPPER_DEBUG_REG02__clip_to_clipga_vte_naninf_kill__SHIFT 0x15
7685#define CLIPPER_DEBUG_REG02__clip_to_outsm_end_of_packet_MASK 0x400000
7686#define CLIPPER_DEBUG_REG02__clip_to_outsm_end_of_packet__SHIFT 0x16
7687#define CLIPPER_DEBUG_REG02__clip_to_outsm_first_prim_of_slot_MASK 0x800000
7688#define CLIPPER_DEBUG_REG02__clip_to_outsm_first_prim_of_slot__SHIFT 0x17
7689#define CLIPPER_DEBUG_REG02__clip_to_outsm_clipped_prim_MASK 0x1000000
7690#define CLIPPER_DEBUG_REG02__clip_to_outsm_clipped_prim__SHIFT 0x18
7691#define CLIPPER_DEBUG_REG02__clip_to_outsm_null_primitive_MASK 0x2000000
7692#define CLIPPER_DEBUG_REG02__clip_to_outsm_null_primitive__SHIFT 0x19
7693#define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_full_MASK 0x4000000
7694#define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_full__SHIFT 0x1a
7695#define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_full_MASK 0x8000000
7696#define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_full__SHIFT 0x1b
7697#define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_write_MASK 0x10000000
7698#define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_write__SHIFT 0x1c
7699#define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_write_MASK 0x20000000
7700#define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_write__SHIFT 0x1d
7701#define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_advanceread_MASK 0x40000000
7702#define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_advanceread__SHIFT 0x1e
7703#define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_empty_MASK 0x80000000
7704#define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_empty__SHIFT 0x1f
7705#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_code_or_MASK 0x3fff
7706#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_code_or__SHIFT 0x0
7707#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event_id_MASK 0xfc000
7708#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event_id__SHIFT 0xe
7709#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_state_var_indx_MASK 0x700000
7710#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_state_var_indx__SHIFT 0x14
7711#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive_MASK 0x800000
7712#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive__SHIFT 0x17
7713#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_deallocate_slot_MASK 0x7000000
7714#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_deallocate_slot__SHIFT 0x18
7715#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_first_prim_of_slot_MASK 0x8000000
7716#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_first_prim_of_slot__SHIFT 0x1b
7717#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_end_of_packet_MASK 0x10000000
7718#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_end_of_packet__SHIFT 0x1c
7719#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event_MASK 0x20000000
7720#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event__SHIFT 0x1d
7721#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive_MASK 0x40000000
7722#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive__SHIFT 0x1e
7723#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000
7724#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x1f
7725#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_param_cache_indx_0_MASK 0x7fe
7726#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_param_cache_indx_0__SHIFT 0x1
7727#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_2_MASK 0x1f800
7728#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_2__SHIFT 0xb
7729#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_1_MASK 0x7e0000
7730#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_1__SHIFT 0x11
7731#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000
7732#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_0__SHIFT 0x17
7733#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event_MASK 0x20000000
7734#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event__SHIFT 0x1d
7735#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_null_primitive_MASK 0x40000000
7736#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_null_primitive__SHIFT 0x1e
7737#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000
7738#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x1f
7739#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_code_or_MASK 0x3fff
7740#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_code_or__SHIFT 0x0
7741#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event_id_MASK 0xfc000
7742#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event_id__SHIFT 0xe
7743#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_state_var_indx_MASK 0x700000
7744#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_state_var_indx__SHIFT 0x14
7745#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_primitive_MASK 0x800000
7746#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_primitive__SHIFT 0x17
7747#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_deallocate_slot_MASK 0x7000000
7748#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_deallocate_slot__SHIFT 0x18
7749#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_first_prim_of_slot_MASK 0x8000000
7750#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_first_prim_of_slot__SHIFT 0x1b
7751#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_end_of_packet_MASK 0x10000000
7752#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_end_of_packet__SHIFT 0x1c
7753#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event_MASK 0x20000000
7754#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event__SHIFT 0x1d
7755#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_null_primitive_MASK 0x40000000
7756#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_null_primitive__SHIFT 0x1e
7757#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_prim_valid_MASK 0x80000000
7758#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_prim_valid__SHIFT 0x1f
7759#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_param_cache_indx_0_MASK 0x7fe
7760#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_param_cache_indx_0__SHIFT 0x1
7761#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_2_MASK 0x1f800
7762#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_2__SHIFT 0xb
7763#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_1_MASK 0x7e0000
7764#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_1__SHIFT 0x11
7765#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000
7766#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_0__SHIFT 0x17
7767#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_event_MASK 0x20000000
7768#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_event__SHIFT 0x1d
7769#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_null_primitive_MASK 0x40000000
7770#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_null_primitive__SHIFT 0x1e
7771#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_prim_valid_MASK 0x80000000
7772#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_prim_valid__SHIFT 0x1f
7773#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_code_or_MASK 0x3fff
7774#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_code_or__SHIFT 0x0
7775#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event_id_MASK 0xfc000
7776#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event_id__SHIFT 0xe
7777#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_state_var_indx_MASK 0x700000
7778#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_state_var_indx__SHIFT 0x14
7779#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_primitive_MASK 0x800000
7780#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_primitive__SHIFT 0x17
7781#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_deallocate_slot_MASK 0x7000000
7782#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_deallocate_slot__SHIFT 0x18
7783#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_first_prim_of_slot_MASK 0x8000000
7784#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_first_prim_of_slot__SHIFT 0x1b
7785#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_end_of_packet_MASK 0x10000000
7786#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_end_of_packet__SHIFT 0x1c
7787#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event_MASK 0x20000000
7788#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event__SHIFT 0x1d
7789#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_null_primitive_MASK 0x40000000
7790#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_null_primitive__SHIFT 0x1e
7791#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_prim_valid_MASK 0x80000000
7792#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_prim_valid__SHIFT 0x1f
7793#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_param_cache_indx_0_MASK 0x7fe
7794#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_param_cache_indx_0__SHIFT 0x1
7795#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_2_MASK 0x1f800
7796#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_2__SHIFT 0xb
7797#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_1_MASK 0x7e0000
7798#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_1__SHIFT 0x11
7799#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000
7800#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_0__SHIFT 0x17
7801#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_event_MASK 0x20000000
7802#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_event__SHIFT 0x1d
7803#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_null_primitive_MASK 0x40000000
7804#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_null_primitive__SHIFT 0x1e
7805#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_prim_valid_MASK 0x80000000
7806#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_prim_valid__SHIFT 0x1f
7807#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_code_or_MASK 0x3fff
7808#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_code_or__SHIFT 0x0
7809#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event_id_MASK 0xfc000
7810#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event_id__SHIFT 0xe
7811#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_state_var_indx_MASK 0x700000
7812#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_state_var_indx__SHIFT 0x14
7813#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_primitive_MASK 0x800000
7814#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_primitive__SHIFT 0x17
7815#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_deallocate_slot_MASK 0x7000000
7816#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_deallocate_slot__SHIFT 0x18
7817#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_first_prim_of_slot_MASK 0x8000000
7818#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_first_prim_of_slot__SHIFT 0x1b
7819#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_end_of_packet_MASK 0x10000000
7820#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_end_of_packet__SHIFT 0x1c
7821#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event_MASK 0x20000000
7822#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event__SHIFT 0x1d
7823#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_null_primitive_MASK 0x40000000
7824#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_null_primitive__SHIFT 0x1e
7825#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_prim_valid_MASK 0x80000000
7826#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_prim_valid__SHIFT 0x1f
7827#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_param_cache_indx_0_MASK 0x7fe
7828#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_param_cache_indx_0__SHIFT 0x1
7829#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_2_MASK 0x1f800
7830#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_2__SHIFT 0xb
7831#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_1_MASK 0x7e0000
7832#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_1__SHIFT 0x11
7833#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000
7834#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_0__SHIFT 0x17
7835#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_event_MASK 0x20000000
7836#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_event__SHIFT 0x1d
7837#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_null_primitive_MASK 0x40000000
7838#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_null_primitive__SHIFT 0x1e
7839#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_prim_valid_MASK 0x80000000
7840#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_prim_valid__SHIFT 0x1f
7841#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_event_MASK 0x1
7842#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_event__SHIFT 0x0
7843#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_event_MASK 0x2
7844#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_event__SHIFT 0x1
7845#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_event_MASK 0x4
7846#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_event__SHIFT 0x2
7847#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_event_MASK 0x8
7848#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_event__SHIFT 0x3
7849#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_primitive_MASK 0x10
7850#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_primitive__SHIFT 0x4
7851#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_primitive_MASK 0x20
7852#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_primitive__SHIFT 0x5
7853#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_primitive_MASK 0x40
7854#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_primitive__SHIFT 0x6
7855#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_primitive_MASK 0x80
7856#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_primitive__SHIFT 0x7
7857#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_to_outsm_cnt_MASK 0xf00
7858#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x8
7859#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_to_outsm_cnt_MASK 0xf000
7860#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0xc
7861#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_to_outsm_cnt_MASK 0xf0000
7862#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x10
7863#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK 0xf00000
7864#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x14
7865#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_prim_valid_MASK 0x1000000
7866#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_prim_valid__SHIFT 0x18
7867#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_prim_valid_MASK 0x2000000
7868#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_prim_valid__SHIFT 0x19
7869#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_prim_valid_MASK 0x4000000
7870#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_prim_valid__SHIFT 0x1a
7871#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_prim_valid_MASK 0x8000000
7872#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_prim_valid__SHIFT 0x1b
7873#define CLIPPER_DEBUG_REG11__clipsm3_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x10000000
7874#define CLIPPER_DEBUG_REG11__clipsm3_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x1c
7875#define CLIPPER_DEBUG_REG11__clipsm2_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x20000000
7876#define CLIPPER_DEBUG_REG11__clipsm2_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x1d
7877#define CLIPPER_DEBUG_REG11__clipsm1_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x40000000
7878#define CLIPPER_DEBUG_REG11__clipsm1_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x1e
7879#define CLIPPER_DEBUG_REG11__clipsm0_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x80000000
7880#define CLIPPER_DEBUG_REG11__clipsm0_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x1f
7881#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO_MASK 0xff
7882#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO__SHIFT 0x0
7883#define CLIPPER_DEBUG_REG12__clip_priority_available_vte_out_clip_MASK 0x1f00
7884#define CLIPPER_DEBUG_REG12__clip_priority_available_vte_out_clip__SHIFT 0x8
7885#define CLIPPER_DEBUG_REG12__clip_priority_available_clip_verts_MASK 0x3e000
7886#define CLIPPER_DEBUG_REG12__clip_priority_available_clip_verts__SHIFT 0xd
7887#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_out_MASK 0xc0000
7888#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_out__SHIFT 0x12
7889#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_vert_MASK 0x300000
7890#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_vert__SHIFT 0x14
7891#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_load_MASK 0xc00000
7892#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_load__SHIFT 0x16
7893#define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_clip_primitive_MASK 0x1000000
7894#define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_clip_primitive__SHIFT 0x18
7895#define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_prim_valid_MASK 0x2000000
7896#define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_prim_valid__SHIFT 0x19
7897#define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_clip_primitive_MASK 0x4000000
7898#define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_clip_primitive__SHIFT 0x1a
7899#define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_prim_valid_MASK 0x8000000
7900#define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_prim_valid__SHIFT 0x1b
7901#define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_clip_primitive_MASK 0x10000000
7902#define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_clip_primitive__SHIFT 0x1c
7903#define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_prim_valid_MASK 0x20000000
7904#define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_prim_valid__SHIFT 0x1d
7905#define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_clip_primitive_MASK 0x40000000
7906#define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_clip_primitive__SHIFT 0x1e
7907#define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000
7908#define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x1f
7909#define CLIPPER_DEBUG_REG13__clprim_in_back_state_var_indx_MASK 0x7
7910#define CLIPPER_DEBUG_REG13__clprim_in_back_state_var_indx__SHIFT 0x0
7911#define CLIPPER_DEBUG_REG13__point_clip_candidate_MASK 0x8
7912#define CLIPPER_DEBUG_REG13__point_clip_candidate__SHIFT 0x3
7913#define CLIPPER_DEBUG_REG13__prim_nan_kill_MASK 0x10
7914#define CLIPPER_DEBUG_REG13__prim_nan_kill__SHIFT 0x4
7915#define CLIPPER_DEBUG_REG13__clprim_clip_primitive_MASK 0x20
7916#define CLIPPER_DEBUG_REG13__clprim_clip_primitive__SHIFT 0x5
7917#define CLIPPER_DEBUG_REG13__clprim_cull_primitive_MASK 0x40
7918#define CLIPPER_DEBUG_REG13__clprim_cull_primitive__SHIFT 0x6
7919#define CLIPPER_DEBUG_REG13__prim_back_valid_MASK 0x80
7920#define CLIPPER_DEBUG_REG13__prim_back_valid__SHIFT 0x7
7921#define CLIPPER_DEBUG_REG13__vertval_bits_vertex_cc_next_valid_MASK 0xf00
7922#define CLIPPER_DEBUG_REG13__vertval_bits_vertex_cc_next_valid__SHIFT 0x8
7923#define CLIPPER_DEBUG_REG13__clipcc_vertex_store_indx_MASK 0x3000
7924#define CLIPPER_DEBUG_REG13__clipcc_vertex_store_indx__SHIFT 0xc
7925#define CLIPPER_DEBUG_REG13__vte_out_orig_fifo_fifo_empty_MASK 0x4000
7926#define CLIPPER_DEBUG_REG13__vte_out_orig_fifo_fifo_empty__SHIFT 0xe
7927#define CLIPPER_DEBUG_REG13__clipcode_fifo_fifo_empty_MASK 0x8000
7928#define CLIPPER_DEBUG_REG13__clipcode_fifo_fifo_empty__SHIFT 0xf
7929#define CLIPPER_DEBUG_REG13__ccgen_to_clipcc_fifo_empty_MASK 0x10000
7930#define CLIPPER_DEBUG_REG13__ccgen_to_clipcc_fifo_empty__SHIFT 0x10
7931#define CLIPPER_DEBUG_REG13__clip_priority_seq_indx_out_cnt_MASK 0x1e0000
7932#define CLIPPER_DEBUG_REG13__clip_priority_seq_indx_out_cnt__SHIFT 0x11
7933#define CLIPPER_DEBUG_REG13__outsm_clr_rd_orig_vertices_MASK 0x600000
7934#define CLIPPER_DEBUG_REG13__outsm_clr_rd_orig_vertices__SHIFT 0x15
7935#define CLIPPER_DEBUG_REG13__outsm_clr_rd_clipsm_wait_MASK 0x800000
7936#define CLIPPER_DEBUG_REG13__outsm_clr_rd_clipsm_wait__SHIFT 0x17
7937#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_contents_MASK 0x1f000000
7938#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_contents__SHIFT 0x18
7939#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_full_MASK 0x20000000
7940#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_full__SHIFT 0x1d
7941#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_advanceread_MASK 0x40000000
7942#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_advanceread__SHIFT 0x1e
7943#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_write_MASK 0x80000000
7944#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_write__SHIFT 0x1f
7945#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_2_MASK 0x3f
7946#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_2__SHIFT 0x0
7947#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_1_MASK 0xfc0
7948#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_1__SHIFT 0x6
7949#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_0_MASK 0x3f000
7950#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_0__SHIFT 0xc
7951#define CLIPPER_DEBUG_REG14__outputclprimtoclip_null_primitive_MASK 0x40000
7952#define CLIPPER_DEBUG_REG14__outputclprimtoclip_null_primitive__SHIFT 0x12
7953#define CLIPPER_DEBUG_REG14__clprim_in_back_end_of_packet_MASK 0x80000
7954#define CLIPPER_DEBUG_REG14__clprim_in_back_end_of_packet__SHIFT 0x13
7955#define CLIPPER_DEBUG_REG14__clprim_in_back_first_prim_of_slot_MASK 0x100000
7956#define CLIPPER_DEBUG_REG14__clprim_in_back_first_prim_of_slot__SHIFT 0x14
7957#define CLIPPER_DEBUG_REG14__clprim_in_back_deallocate_slot_MASK 0xe00000
7958#define CLIPPER_DEBUG_REG14__clprim_in_back_deallocate_slot__SHIFT 0x15
7959#define CLIPPER_DEBUG_REG14__clprim_in_back_event_id_MASK 0x3f000000
7960#define CLIPPER_DEBUG_REG14__clprim_in_back_event_id__SHIFT 0x18
7961#define CLIPPER_DEBUG_REG14__clprim_in_back_event_MASK 0x40000000
7962#define CLIPPER_DEBUG_REG14__clprim_in_back_event__SHIFT 0x1e
7963#define CLIPPER_DEBUG_REG14__prim_back_valid_MASK 0x80000000
7964#define CLIPPER_DEBUG_REG14__prim_back_valid__SHIFT 0x1f
7965#define CLIPPER_DEBUG_REG15__vertval_bits_vertex_vertex_store_msb_MASK 0xffff
7966#define CLIPPER_DEBUG_REG15__vertval_bits_vertex_vertex_store_msb__SHIFT 0x0
7967#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_2_MASK 0x1f0000
7968#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_2__SHIFT 0x10
7969#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_1_MASK 0x3e00000
7970#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_1__SHIFT 0x15
7971#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_0_MASK 0x7c000000
7972#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_0__SHIFT 0x1a
7973#define CLIPPER_DEBUG_REG15__primic_to_clprim_valid_MASK 0x80000000
7974#define CLIPPER_DEBUG_REG15__primic_to_clprim_valid__SHIFT 0x1f
7975#define CLIPPER_DEBUG_REG16__sm0_prim_end_state_MASK 0x7f
7976#define CLIPPER_DEBUG_REG16__sm0_prim_end_state__SHIFT 0x0
7977#define CLIPPER_DEBUG_REG16__sm0_ps_expand_MASK 0x80
7978#define CLIPPER_DEBUG_REG16__sm0_ps_expand__SHIFT 0x7
7979#define CLIPPER_DEBUG_REG16__sm0_clip_vert_cnt_MASK 0x1f00
7980#define CLIPPER_DEBUG_REG16__sm0_clip_vert_cnt__SHIFT 0x8
7981#define CLIPPER_DEBUG_REG16__sm0_vertex_clip_cnt_MASK 0x3e000
7982#define CLIPPER_DEBUG_REG16__sm0_vertex_clip_cnt__SHIFT 0xd
7983#define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_1_MASK 0x40000
7984#define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_1__SHIFT 0x12
7985#define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_0_MASK 0x80000
7986#define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_0__SHIFT 0x13
7987#define CLIPPER_DEBUG_REG16__sm0_current_state_MASK 0x7f00000
7988#define CLIPPER_DEBUG_REG16__sm0_current_state__SHIFT 0x14
7989#define CLIPPER_DEBUG_REG16__sm0_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x8000000
7990#define CLIPPER_DEBUG_REG16__sm0_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x1b
7991#define CLIPPER_DEBUG_REG16__sm0_clip_to_outsm_fifo_full_MASK 0x10000000
7992#define CLIPPER_DEBUG_REG16__sm0_clip_to_outsm_fifo_full__SHIFT 0x1c
7993#define CLIPPER_DEBUG_REG16__sm0_highest_priority_seq_MASK 0x20000000
7994#define CLIPPER_DEBUG_REG16__sm0_highest_priority_seq__SHIFT 0x1d
7995#define CLIPPER_DEBUG_REG16__sm0_outputcliptoclipga_0_MASK 0x40000000
7996#define CLIPPER_DEBUG_REG16__sm0_outputcliptoclipga_0__SHIFT 0x1e
7997#define CLIPPER_DEBUG_REG16__sm0_clprim_to_clip_prim_valid_MASK 0x80000000
7998#define CLIPPER_DEBUG_REG16__sm0_clprim_to_clip_prim_valid__SHIFT 0x1f
7999#define CLIPPER_DEBUG_REG17__sm1_prim_end_state_MASK 0x7f
8000#define CLIPPER_DEBUG_REG17__sm1_prim_end_state__SHIFT 0x0
8001#define CLIPPER_DEBUG_REG17__sm1_ps_expand_MASK 0x80
8002#define CLIPPER_DEBUG_REG17__sm1_ps_expand__SHIFT 0x7
8003#define CLIPPER_DEBUG_REG17__sm1_clip_vert_cnt_MASK 0x1f00
8004#define CLIPPER_DEBUG_REG17__sm1_clip_vert_cnt__SHIFT 0x8
8005#define CLIPPER_DEBUG_REG17__sm1_vertex_clip_cnt_MASK 0x3e000
8006#define CLIPPER_DEBUG_REG17__sm1_vertex_clip_cnt__SHIFT 0xd
8007#define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_1_MASK 0x40000
8008#define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_1__SHIFT 0x12
8009#define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_0_MASK 0x80000
8010#define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_0__SHIFT 0x13
8011#define CLIPPER_DEBUG_REG17__sm1_current_state_MASK 0x7f00000
8012#define CLIPPER_DEBUG_REG17__sm1_current_state__SHIFT 0x14
8013#define CLIPPER_DEBUG_REG17__sm1_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x8000000
8014#define CLIPPER_DEBUG_REG17__sm1_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x1b
8015#define CLIPPER_DEBUG_REG17__sm1_clip_to_outsm_fifo_full_MASK 0x10000000
8016#define CLIPPER_DEBUG_REG17__sm1_clip_to_outsm_fifo_full__SHIFT 0x1c
8017#define CLIPPER_DEBUG_REG17__sm1_highest_priority_seq_MASK 0x20000000
8018#define CLIPPER_DEBUG_REG17__sm1_highest_priority_seq__SHIFT 0x1d
8019#define CLIPPER_DEBUG_REG17__sm1_outputcliptoclipga_0_MASK 0x40000000
8020#define CLIPPER_DEBUG_REG17__sm1_outputcliptoclipga_0__SHIFT 0x1e
8021#define CLIPPER_DEBUG_REG17__sm1_clprim_to_clip_prim_valid_MASK 0x80000000
8022#define CLIPPER_DEBUG_REG17__sm1_clprim_to_clip_prim_valid__SHIFT 0x1f
8023#define CLIPPER_DEBUG_REG18__sm2_prim_end_state_MASK 0x7f
8024#define CLIPPER_DEBUG_REG18__sm2_prim_end_state__SHIFT 0x0
8025#define CLIPPER_DEBUG_REG18__sm2_ps_expand_MASK 0x80
8026#define CLIPPER_DEBUG_REG18__sm2_ps_expand__SHIFT 0x7
8027#define CLIPPER_DEBUG_REG18__sm2_clip_vert_cnt_MASK 0x1f00
8028#define CLIPPER_DEBUG_REG18__sm2_clip_vert_cnt__SHIFT 0x8
8029#define CLIPPER_DEBUG_REG18__sm2_vertex_clip_cnt_MASK 0x3e000
8030#define CLIPPER_DEBUG_REG18__sm2_vertex_clip_cnt__SHIFT 0xd
8031#define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_1_MASK 0x40000
8032#define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_1__SHIFT 0x12
8033#define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_0_MASK 0x80000
8034#define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_0__SHIFT 0x13
8035#define CLIPPER_DEBUG_REG18__sm2_current_state_MASK 0x7f00000
8036#define CLIPPER_DEBUG_REG18__sm2_current_state__SHIFT 0x14
8037#define CLIPPER_DEBUG_REG18__sm2_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x8000000
8038#define CLIPPER_DEBUG_REG18__sm2_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x1b
8039#define CLIPPER_DEBUG_REG18__sm2_clip_to_outsm_fifo_full_MASK 0x10000000
8040#define CLIPPER_DEBUG_REG18__sm2_clip_to_outsm_fifo_full__SHIFT 0x1c
8041#define CLIPPER_DEBUG_REG18__sm2_highest_priority_seq_MASK 0x20000000
8042#define CLIPPER_DEBUG_REG18__sm2_highest_priority_seq__SHIFT 0x1d
8043#define CLIPPER_DEBUG_REG18__sm2_outputcliptoclipga_0_MASK 0x40000000
8044#define CLIPPER_DEBUG_REG18__sm2_outputcliptoclipga_0__SHIFT 0x1e
8045#define CLIPPER_DEBUG_REG18__sm2_clprim_to_clip_prim_valid_MASK 0x80000000
8046#define CLIPPER_DEBUG_REG18__sm2_clprim_to_clip_prim_valid__SHIFT 0x1f
8047#define CLIPPER_DEBUG_REG19__sm3_prim_end_state_MASK 0x7f
8048#define CLIPPER_DEBUG_REG19__sm3_prim_end_state__SHIFT 0x0
8049#define CLIPPER_DEBUG_REG19__sm3_ps_expand_MASK 0x80
8050#define CLIPPER_DEBUG_REG19__sm3_ps_expand__SHIFT 0x7
8051#define CLIPPER_DEBUG_REG19__sm3_clip_vert_cnt_MASK 0x1f00
8052#define CLIPPER_DEBUG_REG19__sm3_clip_vert_cnt__SHIFT 0x8
8053#define CLIPPER_DEBUG_REG19__sm3_vertex_clip_cnt_MASK 0x3e000
8054#define CLIPPER_DEBUG_REG19__sm3_vertex_clip_cnt__SHIFT 0xd
8055#define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_1_MASK 0x40000
8056#define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_1__SHIFT 0x12
8057#define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_0_MASK 0x80000
8058#define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_0__SHIFT 0x13
8059#define CLIPPER_DEBUG_REG19__sm3_current_state_MASK 0x7f00000
8060#define CLIPPER_DEBUG_REG19__sm3_current_state__SHIFT 0x14
8061#define CLIPPER_DEBUG_REG19__sm3_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x8000000
8062#define CLIPPER_DEBUG_REG19__sm3_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x1b
8063#define CLIPPER_DEBUG_REG19__sm3_clip_to_outsm_fifo_full_MASK 0x10000000
8064#define CLIPPER_DEBUG_REG19__sm3_clip_to_outsm_fifo_full__SHIFT 0x1c
8065#define CLIPPER_DEBUG_REG19__sm3_highest_priority_seq_MASK 0x20000000
8066#define CLIPPER_DEBUG_REG19__sm3_highest_priority_seq__SHIFT 0x1d
8067#define CLIPPER_DEBUG_REG19__sm3_outputcliptoclipga_0_MASK 0x40000000
8068#define CLIPPER_DEBUG_REG19__sm3_outputcliptoclipga_0__SHIFT 0x1e
8069#define CLIPPER_DEBUG_REG19__sm3_clprim_to_clip_prim_valid_MASK 0x80000000
8070#define CLIPPER_DEBUG_REG19__sm3_clprim_to_clip_prim_valid__SHIFT 0x1f
8071#define SXIFCCG_DEBUG_REG0__position_address_MASK 0x3f
8072#define SXIFCCG_DEBUG_REG0__position_address__SHIFT 0x0
8073#define SXIFCCG_DEBUG_REG0__point_address_MASK 0x1c0
8074#define SXIFCCG_DEBUG_REG0__point_address__SHIFT 0x6
8075#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx_MASK 0xe00
8076#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx__SHIFT 0x9
8077#define SXIFCCG_DEBUG_REG0__sx_pending_rd_req_mask_MASK 0xf000
8078#define SXIFCCG_DEBUG_REG0__sx_pending_rd_req_mask__SHIFT 0xc
8079#define SXIFCCG_DEBUG_REG0__sx_pending_rd_pci_MASK 0x3ff0000
8080#define SXIFCCG_DEBUG_REG0__sx_pending_rd_pci__SHIFT 0x10
8081#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel_MASK 0xc000000
8082#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel__SHIFT 0x1a
8083#define SXIFCCG_DEBUG_REG0__sx_pending_rd_sp_id_MASK 0x30000000
8084#define SXIFCCG_DEBUG_REG0__sx_pending_rd_sp_id__SHIFT 0x1c
8085#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc_MASK 0x40000000
8086#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc__SHIFT 0x1e
8087#define SXIFCCG_DEBUG_REG0__sx_pending_rd_advance_MASK 0x80000000
8088#define SXIFCCG_DEBUG_REG0__sx_pending_rd_advance__SHIFT 0x1f
8089#define SXIFCCG_DEBUG_REG1__available_positions_MASK 0x7f
8090#define SXIFCCG_DEBUG_REG1__available_positions__SHIFT 0x0
8091#define SXIFCCG_DEBUG_REG1__sx_receive_indx_MASK 0x380
8092#define SXIFCCG_DEBUG_REG1__sx_receive_indx__SHIFT 0x7
8093#define SXIFCCG_DEBUG_REG1__sx_pending_fifo_contents_MASK 0x7c00
8094#define SXIFCCG_DEBUG_REG1__sx_pending_fifo_contents__SHIFT 0xa
8095#define SXIFCCG_DEBUG_REG1__statevar_bits_vs_out_misc_vec_ena_MASK 0x8000
8096#define SXIFCCG_DEBUG_REG1__statevar_bits_vs_out_misc_vec_ena__SHIFT 0xf
8097#define SXIFCCG_DEBUG_REG1__statevar_bits_disable_sp_MASK 0xf0000
8098#define SXIFCCG_DEBUG_REG1__statevar_bits_disable_sp__SHIFT 0x10
8099#define SXIFCCG_DEBUG_REG1__aux_sel_MASK 0x300000
8100#define SXIFCCG_DEBUG_REG1__aux_sel__SHIFT 0x14
8101#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_1_MASK 0x400000
8102#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_1__SHIFT 0x16
8103#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_0_MASK 0x800000
8104#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_0__SHIFT 0x17
8105#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_1_MASK 0xf000000
8106#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_1__SHIFT 0x18
8107#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_0_MASK 0xf0000000
8108#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_0__SHIFT 0x1c
8109#define SXIFCCG_DEBUG_REG2__param_cache_base_MASK 0x7f
8110#define SXIFCCG_DEBUG_REG2__param_cache_base__SHIFT 0x0
8111#define SXIFCCG_DEBUG_REG2__sx_aux_MASK 0x180
8112#define SXIFCCG_DEBUG_REG2__sx_aux__SHIFT 0x7
8113#define SXIFCCG_DEBUG_REG2__sx_request_indx_MASK 0x7e00
8114#define SXIFCCG_DEBUG_REG2__sx_request_indx__SHIFT 0x9
8115#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded_MASK 0x8000
8116#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded__SHIFT 0xf
8117#define SXIFCCG_DEBUG_REG2__req_active_verts_MASK 0x7f0000
8118#define SXIFCCG_DEBUG_REG2__req_active_verts__SHIFT 0x10
8119#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx_MASK 0x3800000
8120#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx__SHIFT 0x17
8121#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_active_verts_MASK 0xfc000000
8122#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_active_verts__SHIFT 0x1a
8123#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO_MASK 0xff
8124#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO__SHIFT 0x0
8125#define SXIFCCG_DEBUG_REG3__vertex_fifo_entriesavailable_MASK 0xf00
8126#define SXIFCCG_DEBUG_REG3__vertex_fifo_entriesavailable__SHIFT 0x8
8127#define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist1_vec_ena_MASK 0x1000
8128#define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist1_vec_ena__SHIFT 0xc
8129#define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist0_vec_ena_MASK 0x2000
8130#define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist0_vec_ena__SHIFT 0xd
8131#define SXIFCCG_DEBUG_REG3__available_positions_MASK 0x1fc000
8132#define SXIFCCG_DEBUG_REG3__available_positions__SHIFT 0xe
8133#define SXIFCCG_DEBUG_REG3__current_state_MASK 0x600000
8134#define SXIFCCG_DEBUG_REG3__current_state__SHIFT 0x15
8135#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty_MASK 0x800000
8136#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty__SHIFT 0x17
8137#define SXIFCCG_DEBUG_REG3__vertex_fifo_full_MASK 0x1000000
8138#define SXIFCCG_DEBUG_REG3__vertex_fifo_full__SHIFT 0x18
8139#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty_MASK 0x2000000
8140#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty__SHIFT 0x19
8141#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full_MASK 0x4000000
8142#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full__SHIFT 0x1a
8143#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty_MASK 0x8000000
8144#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty__SHIFT 0x1b
8145#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full_MASK 0x10000000
8146#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full__SHIFT 0x1c
8147#define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_fifo_full_MASK 0x20000000
8148#define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_fifo_full__SHIFT 0x1d
8149#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_write_MASK 0x40000000
8150#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_write__SHIFT 0x1e
8151#define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_write_MASK 0x80000000
8152#define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_write__SHIFT 0x1f
8153#define SETUP_DEBUG_REG0__su_baryc_cntl_state_MASK 0x3
8154#define SETUP_DEBUG_REG0__su_baryc_cntl_state__SHIFT 0x0
8155#define SETUP_DEBUG_REG0__su_cntl_state_MASK 0x3c
8156#define SETUP_DEBUG_REG0__su_cntl_state__SHIFT 0x2
8157#define SETUP_DEBUG_REG0__pmode_state_MASK 0x3f00
8158#define SETUP_DEBUG_REG0__pmode_state__SHIFT 0x8
8159#define SETUP_DEBUG_REG0__ge_stallb_MASK 0x4000
8160#define SETUP_DEBUG_REG0__ge_stallb__SHIFT 0xe
8161#define SETUP_DEBUG_REG0__geom_enable_MASK 0x8000
8162#define SETUP_DEBUG_REG0__geom_enable__SHIFT 0xf
8163#define SETUP_DEBUG_REG0__su_clip_baryc_free_MASK 0x30000
8164#define SETUP_DEBUG_REG0__su_clip_baryc_free__SHIFT 0x10
8165#define SETUP_DEBUG_REG0__su_clip_rtr_MASK 0x40000
8166#define SETUP_DEBUG_REG0__su_clip_rtr__SHIFT 0x12
8167#define SETUP_DEBUG_REG0__pfifo_busy_MASK 0x80000
8168#define SETUP_DEBUG_REG0__pfifo_busy__SHIFT 0x13
8169#define SETUP_DEBUG_REG0__su_cntl_busy_MASK 0x100000
8170#define SETUP_DEBUG_REG0__su_cntl_busy__SHIFT 0x14
8171#define SETUP_DEBUG_REG0__geom_busy_MASK 0x200000
8172#define SETUP_DEBUG_REG0__geom_busy__SHIFT 0x15
8173#define SETUP_DEBUG_REG0__event_id_gated_MASK 0xfc00000
8174#define SETUP_DEBUG_REG0__event_id_gated__SHIFT 0x16
8175#define SETUP_DEBUG_REG0__event_gated_MASK 0x10000000
8176#define SETUP_DEBUG_REG0__event_gated__SHIFT 0x1c
8177#define SETUP_DEBUG_REG0__pmode_prim_gated_MASK 0x20000000
8178#define SETUP_DEBUG_REG0__pmode_prim_gated__SHIFT 0x1d
8179#define SETUP_DEBUG_REG0__su_dyn_sclk_vld_MASK 0x40000000
8180#define SETUP_DEBUG_REG0__su_dyn_sclk_vld__SHIFT 0x1e
8181#define SETUP_DEBUG_REG0__cl_dyn_sclk_vld_MASK 0x80000000
8182#define SETUP_DEBUG_REG0__cl_dyn_sclk_vld__SHIFT 0x1f
8183#define SETUP_DEBUG_REG1__y_sort0_gated_23_8_MASK 0xffff
8184#define SETUP_DEBUG_REG1__y_sort0_gated_23_8__SHIFT 0x0
8185#define SETUP_DEBUG_REG1__x_sort0_gated_23_8_MASK 0xffff0000
8186#define SETUP_DEBUG_REG1__x_sort0_gated_23_8__SHIFT 0x10
8187#define SETUP_DEBUG_REG2__y_sort1_gated_23_8_MASK 0xffff
8188#define SETUP_DEBUG_REG2__y_sort1_gated_23_8__SHIFT 0x0
8189#define SETUP_DEBUG_REG2__x_sort1_gated_23_8_MASK 0xffff0000
8190#define SETUP_DEBUG_REG2__x_sort1_gated_23_8__SHIFT 0x10
8191#define SETUP_DEBUG_REG3__y_sort2_gated_23_8_MASK 0xffff
8192#define SETUP_DEBUG_REG3__y_sort2_gated_23_8__SHIFT 0x0
8193#define SETUP_DEBUG_REG3__x_sort2_gated_23_8_MASK 0xffff0000
8194#define SETUP_DEBUG_REG3__x_sort2_gated_23_8__SHIFT 0x10
8195#define SETUP_DEBUG_REG4__attr_indx_sort0_gated_MASK 0x3fff
8196#define SETUP_DEBUG_REG4__attr_indx_sort0_gated__SHIFT 0x0
8197#define SETUP_DEBUG_REG4__null_prim_gated_MASK 0x4000
8198#define SETUP_DEBUG_REG4__null_prim_gated__SHIFT 0xe
8199#define SETUP_DEBUG_REG4__backfacing_gated_MASK 0x8000
8200#define SETUP_DEBUG_REG4__backfacing_gated__SHIFT 0xf
8201#define SETUP_DEBUG_REG4__st_indx_gated_MASK 0x70000
8202#define SETUP_DEBUG_REG4__st_indx_gated__SHIFT 0x10
8203#define SETUP_DEBUG_REG4__clipped_gated_MASK 0x80000
8204#define SETUP_DEBUG_REG4__clipped_gated__SHIFT 0x13
8205#define SETUP_DEBUG_REG4__dealloc_slot_gated_MASK 0x700000
8206#define SETUP_DEBUG_REG4__dealloc_slot_gated__SHIFT 0x14
8207#define SETUP_DEBUG_REG4__xmajor_gated_MASK 0x800000
8208#define SETUP_DEBUG_REG4__xmajor_gated__SHIFT 0x17
8209#define SETUP_DEBUG_REG4__diamond_rule_gated_MASK 0x3000000
8210#define SETUP_DEBUG_REG4__diamond_rule_gated__SHIFT 0x18
8211#define SETUP_DEBUG_REG4__type_gated_MASK 0x1c000000
8212#define SETUP_DEBUG_REG4__type_gated__SHIFT 0x1a
8213#define SETUP_DEBUG_REG4__fpov_gated_MASK 0x60000000
8214#define SETUP_DEBUG_REG4__fpov_gated__SHIFT 0x1d
8215#define SETUP_DEBUG_REG4__eop_gated_MASK 0x80000000
8216#define SETUP_DEBUG_REG4__eop_gated__SHIFT 0x1f
8217#define SETUP_DEBUG_REG5__attr_indx_sort2_gated_MASK 0x3fff
8218#define SETUP_DEBUG_REG5__attr_indx_sort2_gated__SHIFT 0x0
8219#define SETUP_DEBUG_REG5__attr_indx_sort1_gated_MASK 0xfffc000
8220#define SETUP_DEBUG_REG5__attr_indx_sort1_gated__SHIFT 0xe
8221#define SETUP_DEBUG_REG5__provoking_vtx_gated_MASK 0x30000000
8222#define SETUP_DEBUG_REG5__provoking_vtx_gated__SHIFT 0x1c
8223#define SETUP_DEBUG_REG5__valid_prim_gated_MASK 0x40000000
8224#define SETUP_DEBUG_REG5__valid_prim_gated__SHIFT 0x1e
8225#define SETUP_DEBUG_REG5__pa_reg_sclk_vld_MASK 0x80000000
8226#define SETUP_DEBUG_REG5__pa_reg_sclk_vld__SHIFT 0x1f
8227#define PA_SC_DEBUG_REG0__REG0_FIELD0_MASK 0x3
8228#define PA_SC_DEBUG_REG0__REG0_FIELD0__SHIFT 0x0
8229#define PA_SC_DEBUG_REG0__REG0_FIELD1_MASK 0xc
8230#define PA_SC_DEBUG_REG0__REG0_FIELD1__SHIFT 0x2
8231#define PA_SC_DEBUG_REG1__REG1_FIELD0_MASK 0x3
8232#define PA_SC_DEBUG_REG1__REG1_FIELD0__SHIFT 0x0
8233#define PA_SC_DEBUG_REG1__REG1_FIELD1_MASK 0xc
8234#define PA_SC_DEBUG_REG1__REG1_FIELD1__SHIFT 0x2
8235#define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN_MASK 0x1
8236#define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN__SHIFT 0x0
8237#define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN_MASK 0x2
8238#define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN__SHIFT 0x1
8239#define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000_MASK 0x4
8240#define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000__SHIFT 0x2
8241#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL_MASK 0x8
8242#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL__SHIFT 0x3
8243#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE_MASK 0x10
8244#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE__SHIFT 0x4
8245#define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS_MASK 0x20
8246#define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS__SHIFT 0x5
8247#define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE_MASK 0x40
8248#define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE__SHIFT 0x6
8249#define COMPUTE_DISPATCH_INITIATOR__DISPATCH_CACHE_CNTL_MASK 0x380
8250#define COMPUTE_DISPATCH_INITIATOR__DISPATCH_CACHE_CNTL__SHIFT 0x7
8251#define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL_MASK 0x400
8252#define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL__SHIFT 0xa
8253#define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL_MASK 0x800
8254#define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL__SHIFT 0xb
8255#define COMPUTE_DISPATCH_INITIATOR__DATA_ATC_MASK 0x1000
8256#define COMPUTE_DISPATCH_INITIATOR__DATA_ATC__SHIFT 0xc
8257#define COMPUTE_DISPATCH_INITIATOR__RESTORE_MASK 0x4000
8258#define COMPUTE_DISPATCH_INITIATOR__RESTORE__SHIFT 0xe
8259#define COMPUTE_DIM_X__SIZE_MASK 0xffffffff
8260#define COMPUTE_DIM_X__SIZE__SHIFT 0x0
8261#define COMPUTE_DIM_Y__SIZE_MASK 0xffffffff
8262#define COMPUTE_DIM_Y__SIZE__SHIFT 0x0
8263#define COMPUTE_DIM_Z__SIZE_MASK 0xffffffff
8264#define COMPUTE_DIM_Z__SIZE__SHIFT 0x0
8265#define COMPUTE_START_X__START_MASK 0xffffffff
8266#define COMPUTE_START_X__START__SHIFT 0x0
8267#define COMPUTE_START_Y__START_MASK 0xffffffff
8268#define COMPUTE_START_Y__START__SHIFT 0x0
8269#define COMPUTE_START_Z__START_MASK 0xffffffff
8270#define COMPUTE_START_Z__START__SHIFT 0x0
8271#define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL_MASK 0xffff
8272#define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL__SHIFT 0x0
8273#define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL_MASK 0xffff0000
8274#define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL__SHIFT 0x10
8275#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL_MASK 0xffff
8276#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL__SHIFT 0x0
8277#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL_MASK 0xffff0000
8278#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL__SHIFT 0x10
8279#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL_MASK 0xffff
8280#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL__SHIFT 0x0
8281#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL_MASK 0xffff0000
8282#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL__SHIFT 0x10
8283#define COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE_MASK 0x1
8284#define COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE__SHIFT 0x0
8285#define COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE_MASK 0x1
8286#define COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE__SHIFT 0x0
8287#define COMPUTE_PGM_LO__DATA_MASK 0xffffffff
8288#define COMPUTE_PGM_LO__DATA__SHIFT 0x0
8289#define COMPUTE_PGM_HI__DATA_MASK 0xff
8290#define COMPUTE_PGM_HI__DATA__SHIFT 0x0
8291#define COMPUTE_PGM_HI__INST_ATC_MASK 0x100
8292#define COMPUTE_PGM_HI__INST_ATC__SHIFT 0x8
8293#define COMPUTE_TBA_LO__DATA_MASK 0xffffffff
8294#define COMPUTE_TBA_LO__DATA__SHIFT 0x0
8295#define COMPUTE_TBA_HI__DATA_MASK 0xff
8296#define COMPUTE_TBA_HI__DATA__SHIFT 0x0
8297#define COMPUTE_TMA_LO__DATA_MASK 0xffffffff
8298#define COMPUTE_TMA_LO__DATA__SHIFT 0x0
8299#define COMPUTE_TMA_HI__DATA_MASK 0xff
8300#define COMPUTE_TMA_HI__DATA__SHIFT 0x0
8301#define COMPUTE_PGM_RSRC1__VGPRS_MASK 0x3f
8302#define COMPUTE_PGM_RSRC1__VGPRS__SHIFT 0x0
8303#define COMPUTE_PGM_RSRC1__SGPRS_MASK 0x3c0
8304#define COMPUTE_PGM_RSRC1__SGPRS__SHIFT 0x6
8305#define COMPUTE_PGM_RSRC1__PRIORITY_MASK 0xc00
8306#define COMPUTE_PGM_RSRC1__PRIORITY__SHIFT 0xa
8307#define COMPUTE_PGM_RSRC1__FLOAT_MODE_MASK 0xff000
8308#define COMPUTE_PGM_RSRC1__FLOAT_MODE__SHIFT 0xc
8309#define COMPUTE_PGM_RSRC1__PRIV_MASK 0x100000
8310#define COMPUTE_PGM_RSRC1__PRIV__SHIFT 0x14
8311#define COMPUTE_PGM_RSRC1__DX10_CLAMP_MASK 0x200000
8312#define COMPUTE_PGM_RSRC1__DX10_CLAMP__SHIFT 0x15
8313#define COMPUTE_PGM_RSRC1__DEBUG_MODE_MASK 0x400000
8314#define COMPUTE_PGM_RSRC1__DEBUG_MODE__SHIFT 0x16
8315#define COMPUTE_PGM_RSRC1__IEEE_MODE_MASK 0x800000
8316#define COMPUTE_PGM_RSRC1__IEEE_MODE__SHIFT 0x17
8317#define COMPUTE_PGM_RSRC1__BULKY_MASK 0x1000000
8318#define COMPUTE_PGM_RSRC1__BULKY__SHIFT 0x18
8319#define COMPUTE_PGM_RSRC1__CDBG_USER_MASK 0x2000000
8320#define COMPUTE_PGM_RSRC1__CDBG_USER__SHIFT 0x19
8321#define COMPUTE_PGM_RSRC2__SCRATCH_EN_MASK 0x1
8322#define COMPUTE_PGM_RSRC2__SCRATCH_EN__SHIFT 0x0
8323#define COMPUTE_PGM_RSRC2__USER_SGPR_MASK 0x3e
8324#define COMPUTE_PGM_RSRC2__USER_SGPR__SHIFT 0x1
8325#define COMPUTE_PGM_RSRC2__TRAP_PRESENT_MASK 0x40
8326#define COMPUTE_PGM_RSRC2__TRAP_PRESENT__SHIFT 0x6
8327#define COMPUTE_PGM_RSRC2__TGID_X_EN_MASK 0x80
8328#define COMPUTE_PGM_RSRC2__TGID_X_EN__SHIFT 0x7
8329#define COMPUTE_PGM_RSRC2__TGID_Y_EN_MASK 0x100
8330#define COMPUTE_PGM_RSRC2__TGID_Y_EN__SHIFT 0x8
8331#define COMPUTE_PGM_RSRC2__TGID_Z_EN_MASK 0x200
8332#define COMPUTE_PGM_RSRC2__TGID_Z_EN__SHIFT 0x9
8333#define COMPUTE_PGM_RSRC2__TG_SIZE_EN_MASK 0x400
8334#define COMPUTE_PGM_RSRC2__TG_SIZE_EN__SHIFT 0xa
8335#define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT_MASK 0x1800
8336#define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT__SHIFT 0xb
8337#define COMPUTE_PGM_RSRC2__EXCP_EN_MSB_MASK 0x6000
8338#define COMPUTE_PGM_RSRC2__EXCP_EN_MSB__SHIFT 0xd
8339#define COMPUTE_PGM_RSRC2__LDS_SIZE_MASK 0xff8000
8340#define COMPUTE_PGM_RSRC2__LDS_SIZE__SHIFT 0xf
8341#define COMPUTE_PGM_RSRC2__EXCP_EN_MASK 0x7f000000
8342#define COMPUTE_PGM_RSRC2__EXCP_EN__SHIFT 0x18
8343#define COMPUTE_VMID__DATA_MASK 0xf
8344#define COMPUTE_VMID__DATA__SHIFT 0x0
8345#define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH_MASK 0x3ff
8346#define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH__SHIFT 0x0
8347#define COMPUTE_RESOURCE_LIMITS__TG_PER_CU_MASK 0xf000
8348#define COMPUTE_RESOURCE_LIMITS__TG_PER_CU__SHIFT 0xc
8349#define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD_MASK 0x3f0000
8350#define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD__SHIFT 0x10
8351#define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL_MASK 0x400000
8352#define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL__SHIFT 0x16
8353#define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST_MASK 0x800000
8354#define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST__SHIFT 0x17
8355#define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT_MASK 0x7000000
8356#define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT__SHIFT 0x18
8357#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH0_CU_EN_MASK 0xffff
8358#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH0_CU_EN__SHIFT 0x0
8359#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH1_CU_EN_MASK 0xffff0000
8360#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH1_CU_EN__SHIFT 0x10
8361#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH0_CU_EN_MASK 0xffff
8362#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH0_CU_EN__SHIFT 0x0
8363#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH1_CU_EN_MASK 0xffff0000
8364#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH1_CU_EN__SHIFT 0x10
8365#define COMPUTE_TMPRING_SIZE__WAVES_MASK 0xfff
8366#define COMPUTE_TMPRING_SIZE__WAVES__SHIFT 0x0
8367#define COMPUTE_TMPRING_SIZE__WAVESIZE_MASK 0x1fff000
8368#define COMPUTE_TMPRING_SIZE__WAVESIZE__SHIFT 0xc
8369#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH0_CU_EN_MASK 0xffff
8370#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH0_CU_EN__SHIFT 0x0
8371#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH1_CU_EN_MASK 0xffff0000
8372#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH1_CU_EN__SHIFT 0x10
8373#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH0_CU_EN_MASK 0xffff
8374#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH0_CU_EN__SHIFT 0x0
8375#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH1_CU_EN_MASK 0xffff0000
8376#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH1_CU_EN__SHIFT 0x10
8377#define COMPUTE_RESTART_X__RESTART_MASK 0xffffffff
8378#define COMPUTE_RESTART_X__RESTART__SHIFT 0x0
8379#define COMPUTE_RESTART_Y__RESTART_MASK 0xffffffff
8380#define COMPUTE_RESTART_Y__RESTART__SHIFT 0x0
8381#define COMPUTE_RESTART_Z__RESTART_MASK 0xffffffff
8382#define COMPUTE_RESTART_Z__RESTART__SHIFT 0x0
8383#define COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE_MASK 0x1
8384#define COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE__SHIFT 0x0
8385#define COMPUTE_MISC_RESERVED__SEND_SEID_MASK 0x3
8386#define COMPUTE_MISC_RESERVED__SEND_SEID__SHIFT 0x0
8387#define COMPUTE_MISC_RESERVED__RESERVED2_MASK 0x4
8388#define COMPUTE_MISC_RESERVED__RESERVED2__SHIFT 0x2
8389#define COMPUTE_MISC_RESERVED__RESERVED3_MASK 0x8
8390#define COMPUTE_MISC_RESERVED__RESERVED3__SHIFT 0x3
8391#define COMPUTE_MISC_RESERVED__RESERVED4_MASK 0x10
8392#define COMPUTE_MISC_RESERVED__RESERVED4__SHIFT 0x4
8393#define COMPUTE_MISC_RESERVED__WAVE_ID_BASE_MASK 0x1ffe0
8394#define COMPUTE_MISC_RESERVED__WAVE_ID_BASE__SHIFT 0x5
8395#define COMPUTE_DISPATCH_ID__DISPATCH_ID_MASK 0xffffffff
8396#define COMPUTE_DISPATCH_ID__DISPATCH_ID__SHIFT 0x0
8397#define COMPUTE_THREADGROUP_ID__THREADGROUP_ID_MASK 0xffffffff
8398#define COMPUTE_THREADGROUP_ID__THREADGROUP_ID__SHIFT 0x0
8399#define COMPUTE_RELAUNCH__PAYLOAD_MASK 0x3fffffff
8400#define COMPUTE_RELAUNCH__PAYLOAD__SHIFT 0x0
8401#define COMPUTE_RELAUNCH__IS_EVENT_MASK 0x40000000
8402#define COMPUTE_RELAUNCH__IS_EVENT__SHIFT 0x1e
8403#define COMPUTE_RELAUNCH__IS_STATE_MASK 0x80000000
8404#define COMPUTE_RELAUNCH__IS_STATE__SHIFT 0x1f
8405#define COMPUTE_WAVE_RESTORE_ADDR_LO__ADDR_MASK 0xffffffff
8406#define COMPUTE_WAVE_RESTORE_ADDR_LO__ADDR__SHIFT 0x0
8407#define COMPUTE_WAVE_RESTORE_ADDR_HI__ADDR_MASK 0xffff
8408#define COMPUTE_WAVE_RESTORE_ADDR_HI__ADDR__SHIFT 0x0
8409#define COMPUTE_WAVE_RESTORE_CONTROL__ATC_MASK 0x1
8410#define COMPUTE_WAVE_RESTORE_CONTROL__ATC__SHIFT 0x0
8411#define COMPUTE_WAVE_RESTORE_CONTROL__MTYPE_MASK 0x6
8412#define COMPUTE_WAVE_RESTORE_CONTROL__MTYPE__SHIFT 0x1
8413#define COMPUTE_USER_DATA_0__DATA_MASK 0xffffffff
8414#define COMPUTE_USER_DATA_0__DATA__SHIFT 0x0
8415#define COMPUTE_USER_DATA_1__DATA_MASK 0xffffffff
8416#define COMPUTE_USER_DATA_1__DATA__SHIFT 0x0
8417#define COMPUTE_USER_DATA_2__DATA_MASK 0xffffffff
8418#define COMPUTE_USER_DATA_2__DATA__SHIFT 0x0
8419#define COMPUTE_USER_DATA_3__DATA_MASK 0xffffffff
8420#define COMPUTE_USER_DATA_3__DATA__SHIFT 0x0
8421#define COMPUTE_USER_DATA_4__DATA_MASK 0xffffffff
8422#define COMPUTE_USER_DATA_4__DATA__SHIFT 0x0
8423#define COMPUTE_USER_DATA_5__DATA_MASK 0xffffffff
8424#define COMPUTE_USER_DATA_5__DATA__SHIFT 0x0
8425#define COMPUTE_USER_DATA_6__DATA_MASK 0xffffffff
8426#define COMPUTE_USER_DATA_6__DATA__SHIFT 0x0
8427#define COMPUTE_USER_DATA_7__DATA_MASK 0xffffffff
8428#define COMPUTE_USER_DATA_7__DATA__SHIFT 0x0
8429#define COMPUTE_USER_DATA_8__DATA_MASK 0xffffffff
8430#define COMPUTE_USER_DATA_8__DATA__SHIFT 0x0
8431#define COMPUTE_USER_DATA_9__DATA_MASK 0xffffffff
8432#define COMPUTE_USER_DATA_9__DATA__SHIFT 0x0
8433#define COMPUTE_USER_DATA_10__DATA_MASK 0xffffffff
8434#define COMPUTE_USER_DATA_10__DATA__SHIFT 0x0
8435#define COMPUTE_USER_DATA_11__DATA_MASK 0xffffffff
8436#define COMPUTE_USER_DATA_11__DATA__SHIFT 0x0
8437#define COMPUTE_USER_DATA_12__DATA_MASK 0xffffffff
8438#define COMPUTE_USER_DATA_12__DATA__SHIFT 0x0
8439#define COMPUTE_USER_DATA_13__DATA_MASK 0xffffffff
8440#define COMPUTE_USER_DATA_13__DATA__SHIFT 0x0
8441#define COMPUTE_USER_DATA_14__DATA_MASK 0xffffffff
8442#define COMPUTE_USER_DATA_14__DATA__SHIFT 0x0
8443#define COMPUTE_USER_DATA_15__DATA_MASK 0xffffffff
8444#define COMPUTE_USER_DATA_15__DATA__SHIFT 0x0
8445#define COMPUTE_NOWHERE__DATA_MASK 0xffffffff
8446#define COMPUTE_NOWHERE__DATA__SHIFT 0x0
8447#define CSPRIV_CONNECT__DOORBELL_OFFSET_MASK 0x1fffff
8448#define CSPRIV_CONNECT__DOORBELL_OFFSET__SHIFT 0x0
8449#define CSPRIV_CONNECT__QUEUE_ID_MASK 0xe00000
8450#define CSPRIV_CONNECT__QUEUE_ID__SHIFT 0x15
8451#define CSPRIV_CONNECT__VMID_MASK 0x3c000000
8452#define CSPRIV_CONNECT__VMID__SHIFT 0x1a
8453#define CSPRIV_CONNECT__UNORD_DISP_MASK 0x80000000
8454#define CSPRIV_CONNECT__UNORD_DISP__SHIFT 0x1f
8455#define CSPRIV_THREAD_TRACE_TG0__TGID_X_MASK 0xffffffff
8456#define CSPRIV_THREAD_TRACE_TG0__TGID_X__SHIFT 0x0
8457#define CSPRIV_THREAD_TRACE_TG1__TGID_Y_MASK 0xffffffff
8458#define CSPRIV_THREAD_TRACE_TG1__TGID_Y__SHIFT 0x0
8459#define CSPRIV_THREAD_TRACE_TG2__TGID_Z_MASK 0xffffffff
8460#define CSPRIV_THREAD_TRACE_TG2__TGID_Z__SHIFT 0x0
8461#define CSPRIV_THREAD_TRACE_TG3__WAVE_ID_BASE_MASK 0xfff
8462#define CSPRIV_THREAD_TRACE_TG3__WAVE_ID_BASE__SHIFT 0x0
8463#define CSPRIV_THREAD_TRACE_TG3__THREADS_IN_GROUP_MASK 0xfff000
8464#define CSPRIV_THREAD_TRACE_TG3__THREADS_IN_GROUP__SHIFT 0xc
8465#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_X_FLAG_MASK 0x1000000
8466#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_X_FLAG__SHIFT 0x18
8467#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_Y_FLAG_MASK 0x2000000
8468#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_Y_FLAG__SHIFT 0x19
8469#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_Z_FLAG_MASK 0x4000000
8470#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_Z_FLAG__SHIFT 0x1a
8471#define CSPRIV_THREAD_TRACE_TG3__LAST_TG_MASK 0x8000000
8472#define CSPRIV_THREAD_TRACE_TG3__LAST_TG__SHIFT 0x1b
8473#define CSPRIV_THREAD_TRACE_TG3__FIRST_TG_MASK 0x10000000
8474#define CSPRIV_THREAD_TRACE_TG3__FIRST_TG__SHIFT 0x1c
8475#define CSPRIV_THREAD_TRACE_EVENT__EVENT_ID_MASK 0x1f
8476#define CSPRIV_THREAD_TRACE_EVENT__EVENT_ID__SHIFT 0x0
8477#define RLC_CNTL__RLC_ENABLE_F32_MASK 0x1
8478#define RLC_CNTL__RLC_ENABLE_F32__SHIFT 0x0
8479#define RLC_CNTL__FORCE_RETRY_MASK 0x2
8480#define RLC_CNTL__FORCE_RETRY__SHIFT 0x1
8481#define RLC_CNTL__READ_CACHE_DISABLE_MASK 0x4
8482#define RLC_CNTL__READ_CACHE_DISABLE__SHIFT 0x2
8483#define RLC_CNTL__RLC_STEP_F32_MASK 0x8
8484#define RLC_CNTL__RLC_STEP_F32__SHIFT 0x3
8485#define RLC_CNTL__SOFT_RESET_DEBUG_MODE_MASK 0x10
8486#define RLC_CNTL__SOFT_RESET_DEBUG_MODE__SHIFT 0x4
8487#define RLC_CNTL__RESERVED_MASK 0xffffff00
8488#define RLC_CNTL__RESERVED__SHIFT 0x8
8489#define RLC_DEBUG_SELECT__SELECT_MASK 0xff
8490#define RLC_DEBUG_SELECT__SELECT__SHIFT 0x0
8491#define RLC_DEBUG_SELECT__RESERVED_MASK 0xffffff00
8492#define RLC_DEBUG_SELECT__RESERVED__SHIFT 0x8
8493#define RLC_DEBUG__DATA_MASK 0xffffffff
8494#define RLC_DEBUG__DATA__SHIFT 0x0
8495#define RLC_MC_CNTL__WRREQ_SWAP_MASK 0x3
8496#define RLC_MC_CNTL__WRREQ_SWAP__SHIFT 0x0
8497#define RLC_MC_CNTL__WRREQ_TRAN_MASK 0x4
8498#define RLC_MC_CNTL__WRREQ_TRAN__SHIFT 0x2
8499#define RLC_MC_CNTL__WRREQ_PRIV_MASK 0x8
8500#define RLC_MC_CNTL__WRREQ_PRIV__SHIFT 0x3
8501#define RLC_MC_CNTL__WRNFO_STALL_MASK 0x10
8502#define RLC_MC_CNTL__WRNFO_STALL__SHIFT 0x4
8503#define RLC_MC_CNTL__WRNFO_URG_MASK 0x1e0
8504#define RLC_MC_CNTL__WRNFO_URG__SHIFT 0x5
8505#define RLC_MC_CNTL__WRREQ_DW_IMASK_MASK 0x1e00
8506#define RLC_MC_CNTL__WRREQ_DW_IMASK__SHIFT 0x9
8507#define RLC_MC_CNTL__RESERVED_B_MASK 0xfe000
8508#define RLC_MC_CNTL__RESERVED_B__SHIFT 0xd
8509#define RLC_MC_CNTL__RDNFO_URG_MASK 0xf00000
8510#define RLC_MC_CNTL__RDNFO_URG__SHIFT 0x14
8511#define RLC_MC_CNTL__RDREQ_SWAP_MASK 0x3000000
8512#define RLC_MC_CNTL__RDREQ_SWAP__SHIFT 0x18
8513#define RLC_MC_CNTL__RDREQ_TRAN_MASK 0x4000000
8514#define RLC_MC_CNTL__RDREQ_TRAN__SHIFT 0x1a
8515#define RLC_MC_CNTL__RDREQ_PRIV_MASK 0x8000000
8516#define RLC_MC_CNTL__RDREQ_PRIV__SHIFT 0x1b
8517#define RLC_MC_CNTL__RDNFO_STALL_MASK 0x10000000
8518#define RLC_MC_CNTL__RDNFO_STALL__SHIFT 0x1c
8519#define RLC_MC_CNTL__RESERVED_MASK 0xe0000000
8520#define RLC_MC_CNTL__RESERVED__SHIFT 0x1d
8521#define RLC_STAT__RLC_BUSY_MASK 0x1
8522#define RLC_STAT__RLC_BUSY__SHIFT 0x0
8523#define RLC_STAT__RLC_GPM_BUSY_MASK 0x2
8524#define RLC_STAT__RLC_GPM_BUSY__SHIFT 0x1
8525#define RLC_STAT__RLC_SPM_BUSY_MASK 0x4
8526#define RLC_STAT__RLC_SPM_BUSY__SHIFT 0x2
8527#define RLC_STAT__RESERVED_MASK 0xfffffff8
8528#define RLC_STAT__RESERVED__SHIFT 0x3
8529#define RLC_SAFE_MODE__CMD_MASK 0x1
8530#define RLC_SAFE_MODE__CMD__SHIFT 0x0
8531#define RLC_SAFE_MODE__MESSAGE_MASK 0x1e
8532#define RLC_SAFE_MODE__MESSAGE__SHIFT 0x1
8533#define RLC_SAFE_MODE__RESERVED1_MASK 0xe0
8534#define RLC_SAFE_MODE__RESERVED1__SHIFT 0x5
8535#define RLC_SAFE_MODE__RESPONSE_MASK 0xf00
8536#define RLC_SAFE_MODE__RESPONSE__SHIFT 0x8
8537#define RLC_SAFE_MODE__RESERVED_MASK 0xfffff000
8538#define RLC_SAFE_MODE__RESERVED__SHIFT 0xc
8539#define RLC_SOFT_RESET_GPU__SOFT_RESET_GPU_MASK 0x1
8540#define RLC_SOFT_RESET_GPU__SOFT_RESET_GPU__SHIFT 0x0
8541#define RLC_SOFT_RESET_GPU__RESERVED_MASK 0xfffffffe
8542#define RLC_SOFT_RESET_GPU__RESERVED__SHIFT 0x1
8543#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK 0x1
8544#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN__SHIFT 0x0
8545#define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN_MASK 0x2
8546#define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN__SHIFT 0x1
8547#define RLC_MEM_SLP_CNTL__RESERVED_MASK 0x7c
8548#define RLC_MEM_SLP_CNTL__RESERVED__SHIFT 0x2
8549#define RLC_MEM_SLP_CNTL__RLC_LS_DS_BUSY_OVERRIDE_MASK 0x80
8550#define RLC_MEM_SLP_CNTL__RLC_LS_DS_BUSY_OVERRIDE__SHIFT 0x7
8551#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY_MASK 0xff00
8552#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY__SHIFT 0x8
8553#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY_MASK 0xff0000
8554#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY__SHIFT 0x10
8555#define RLC_MEM_SLP_CNTL__RESERVED1_MASK 0xff000000
8556#define RLC_MEM_SLP_CNTL__RESERVED1__SHIFT 0x18
8557#define SMU_RLC_RESPONSE__RESP_MASK 0xffffffff
8558#define SMU_RLC_RESPONSE__RESP__SHIFT 0x0
8559#define RLC_RLCV_SAFE_MODE__CMD_MASK 0x1
8560#define RLC_RLCV_SAFE_MODE__CMD__SHIFT 0x0
8561#define RLC_RLCV_SAFE_MODE__MESSAGE_MASK 0x1e
8562#define RLC_RLCV_SAFE_MODE__MESSAGE__SHIFT 0x1
8563#define RLC_RLCV_SAFE_MODE__RESERVED1_MASK 0xe0
8564#define RLC_RLCV_SAFE_MODE__RESERVED1__SHIFT 0x5
8565#define RLC_RLCV_SAFE_MODE__RESPONSE_MASK 0xf00
8566#define RLC_RLCV_SAFE_MODE__RESPONSE__SHIFT 0x8
8567#define RLC_RLCV_SAFE_MODE__RESERVED_MASK 0xfffff000
8568#define RLC_RLCV_SAFE_MODE__RESERVED__SHIFT 0xc
8569#define RLC_SMU_SAFE_MODE__CMD_MASK 0x1
8570#define RLC_SMU_SAFE_MODE__CMD__SHIFT 0x0
8571#define RLC_SMU_SAFE_MODE__MESSAGE_MASK 0x1e
8572#define RLC_SMU_SAFE_MODE__MESSAGE__SHIFT 0x1
8573#define RLC_SMU_SAFE_MODE__RESERVED1_MASK 0xe0
8574#define RLC_SMU_SAFE_MODE__RESERVED1__SHIFT 0x5
8575#define RLC_SMU_SAFE_MODE__RESPONSE_MASK 0xf00
8576#define RLC_SMU_SAFE_MODE__RESPONSE__SHIFT 0x8
8577#define RLC_SMU_SAFE_MODE__RESERVED_MASK 0xfffff000
8578#define RLC_SMU_SAFE_MODE__RESERVED__SHIFT 0xc
8579#define RLC_RLCV_COMMAND__CMD_MASK 0xf
8580#define RLC_RLCV_COMMAND__CMD__SHIFT 0x0
8581#define RLC_RLCV_COMMAND__RESERVED_MASK 0xfffffff0
8582#define RLC_RLCV_COMMAND__RESERVED__SHIFT 0x4
8583#define RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK 0x1
8584#define RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE__SHIFT 0x0
8585#define RLC_PERFMON_CNTL__PERFMON_STATE_MASK 0x7
8586#define RLC_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
8587#define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x400
8588#define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa
8589#define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0xff
8590#define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
8591#define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0xff
8592#define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
8593#define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
8594#define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
8595#define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
8596#define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
8597#define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
8598#define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
8599#define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
8600#define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
8601#define CGTT_RLC_CLK_CTRL__ON_DELAY_MASK 0xf
8602#define CGTT_RLC_CLK_CTRL__ON_DELAY__SHIFT 0x0
8603#define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
8604#define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
8605#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000
8606#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
8607#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000
8608#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
8609#define RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK 0x1
8610#define RLC_LB_CNTL__LOAD_BALANCE_ENABLE__SHIFT 0x0
8611#define RLC_LB_CNTL__LB_CNT_CP_BUSY_MASK 0x2
8612#define RLC_LB_CNTL__LB_CNT_CP_BUSY__SHIFT 0x1
8613#define RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK 0x4
8614#define RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE__SHIFT 0x2
8615#define RLC_LB_CNTL__LB_CNT_REG_INC_MASK 0x8
8616#define RLC_LB_CNTL__LB_CNT_REG_INC__SHIFT 0x3
8617#define RLC_LB_CNTL__CU_MASK_USED_OFF_HYST_MASK 0xff0
8618#define RLC_LB_CNTL__CU_MASK_USED_OFF_HYST__SHIFT 0x4
8619#define RLC_LB_CNTL__RESERVED_MASK 0xfffff000
8620#define RLC_LB_CNTL__RESERVED__SHIFT 0xc
8621#define RLC_LB_CNTR_MAX__LB_CNTR_MAX_MASK 0xffffffff
8622#define RLC_LB_CNTR_MAX__LB_CNTR_MAX__SHIFT 0x0
8623#define RLC_LB_CNTR_INIT__LB_CNTR_INIT_MASK 0xffffffff
8624#define RLC_LB_CNTR_INIT__LB_CNTR_INIT__SHIFT 0x0
8625#define RLC_LOAD_BALANCE_CNTR__RLC_LOAD_BALANCE_CNTR_MASK 0xffffffff
8626#define RLC_LOAD_BALANCE_CNTR__RLC_LOAD_BALANCE_CNTR__SHIFT 0x0
8627#define RLC_SAVE_AND_RESTORE_BASE__BASE_MASK 0xffffffff
8628#define RLC_SAVE_AND_RESTORE_BASE__BASE__SHIFT 0x0
8629#define RLC_JUMP_TABLE_RESTORE__ADDR_MASK 0xffffffff
8630#define RLC_JUMP_TABLE_RESTORE__ADDR__SHIFT 0x0
8631#define RLC_DRIVER_CPDMA_STATUS__DRIVER_REQUEST_MASK 0x1
8632#define RLC_DRIVER_CPDMA_STATUS__DRIVER_REQUEST__SHIFT 0x0
8633#define RLC_DRIVER_CPDMA_STATUS__RESERVED1_MASK 0xe
8634#define RLC_DRIVER_CPDMA_STATUS__RESERVED1__SHIFT 0x1
8635#define RLC_DRIVER_CPDMA_STATUS__DRIVER_ACK_MASK 0x10
8636#define RLC_DRIVER_CPDMA_STATUS__DRIVER_ACK__SHIFT 0x4
8637#define RLC_DRIVER_CPDMA_STATUS__RESERVED_MASK 0xffffffe0
8638#define RLC_DRIVER_CPDMA_STATUS__RESERVED__SHIFT 0x5
8639#define RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE_MASK 0xff
8640#define RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE__SHIFT 0x0
8641#define RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK 0xff00
8642#define RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT 0x8
8643#define RLC_PG_DELAY_2__PERCU_TIMEOUT_VALUE_MASK 0xffff0000
8644#define RLC_PG_DELAY_2__PERCU_TIMEOUT_VALUE__SHIFT 0x10
8645#define RLC_GPM_DEBUG_SELECT__SELECT_MASK 0xff
8646#define RLC_GPM_DEBUG_SELECT__SELECT__SHIFT 0x0
8647#define RLC_GPM_DEBUG_SELECT__F32_DEBUG_SELECT_MASK 0x300
8648#define RLC_GPM_DEBUG_SELECT__F32_DEBUG_SELECT__SHIFT 0x8
8649#define RLC_GPM_DEBUG_SELECT__RESERVED_MASK 0xfffffc00
8650#define RLC_GPM_DEBUG_SELECT__RESERVED__SHIFT 0xa
8651#define RLC_GPM_DEBUG__DATA_MASK 0xffffffff
8652#define RLC_GPM_DEBUG__DATA__SHIFT 0x0
8653#define RLC_HYP_GPM_UCODE_ADDR__UCODE_ADDR_MASK 0xfff
8654#define RLC_HYP_GPM_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
8655#define RLC_HYP_GPM_UCODE_ADDR__RESERVED_MASK 0xfffff000
8656#define RLC_HYP_GPM_UCODE_ADDR__RESERVED__SHIFT 0xc
8657#define RLC_GPM_UCODE_ADDR__UCODE_ADDR_MASK 0xfff
8658#define RLC_GPM_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
8659#define RLC_GPM_UCODE_ADDR__RESERVED_MASK 0xfffff000
8660#define RLC_GPM_UCODE_ADDR__RESERVED__SHIFT 0xc
8661#define RLC_HYP_GPM_UCODE_DATA__UCODE_DATA_MASK 0xffffffff
8662#define RLC_HYP_GPM_UCODE_DATA__UCODE_DATA__SHIFT 0x0
8663#define RLC_GPM_UCODE_DATA__UCODE_DATA_MASK 0xffffffff
8664#define RLC_GPM_UCODE_DATA__UCODE_DATA__SHIFT 0x0
8665#define GPU_BIST_CONTROL__STOP_ON_FAIL_HW_MASK 0x1
8666#define GPU_BIST_CONTROL__STOP_ON_FAIL_HW__SHIFT 0x0
8667#define GPU_BIST_CONTROL__STOP_ON_FAIL_CU_HARV_MASK 0x2
8668#define GPU_BIST_CONTROL__STOP_ON_FAIL_CU_HARV__SHIFT 0x1
8669#define GPU_BIST_CONTROL__CU_HARV_LOOP_COUNT_MASK 0x3c
8670#define GPU_BIST_CONTROL__CU_HARV_LOOP_COUNT__SHIFT 0x2
8671#define GPU_BIST_CONTROL__RESERVED_MASK 0xffff80
8672#define GPU_BIST_CONTROL__RESERVED__SHIFT 0x7
8673#define GPU_BIST_CONTROL__GLOBAL_LOOP_COUNT_MASK 0xff000000
8674#define GPU_BIST_CONTROL__GLOBAL_LOOP_COUNT__SHIFT 0x18
8675#define RLC_ROM_CNTL__USE_ROM_MASK 0x1
8676#define RLC_ROM_CNTL__USE_ROM__SHIFT 0x0
8677#define RLC_ROM_CNTL__SLP_MODE_EN_MASK 0x2
8678#define RLC_ROM_CNTL__SLP_MODE_EN__SHIFT 0x1
8679#define RLC_ROM_CNTL__EFUSE_DISTRIB_EN_MASK 0x4
8680#define RLC_ROM_CNTL__EFUSE_DISTRIB_EN__SHIFT 0x2
8681#define RLC_ROM_CNTL__HELLOWORLD_EN_MASK 0x8
8682#define RLC_ROM_CNTL__HELLOWORLD_EN__SHIFT 0x3
8683#define RLC_ROM_CNTL__CU_HARVEST_EN_MASK 0x10
8684#define RLC_ROM_CNTL__CU_HARVEST_EN__SHIFT 0x4
8685#define RLC_ROM_CNTL__RESERVED_MASK 0xffffffe0
8686#define RLC_ROM_CNTL__RESERVED__SHIFT 0x5
8687#define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB_MASK 0xffffffff
8688#define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB__SHIFT 0x0
8689#define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB_MASK 0xffffffff
8690#define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB__SHIFT 0x0
8691#define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE_MASK 0x1
8692#define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE__SHIFT 0x0
8693#define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED_MASK 0xfffffffe
8694#define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED__SHIFT 0x1
8695#define RLC_UCODE_CNTL__RLC_UCODE_FLAGS_MASK 0xffffffff
8696#define RLC_UCODE_CNTL__RLC_UCODE_FLAGS__SHIFT 0x0
8697#define RLC_GPM_STAT__RLC_BUSY_MASK 0x1
8698#define RLC_GPM_STAT__RLC_BUSY__SHIFT 0x0
8699#define RLC_GPM_STAT__GFX_POWER_STATUS_MASK 0x2
8700#define RLC_GPM_STAT__GFX_POWER_STATUS__SHIFT 0x1
8701#define RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK 0x4
8702#define RLC_GPM_STAT__GFX_CLOCK_STATUS__SHIFT 0x2
8703#define RLC_GPM_STAT__GFX_LS_STATUS_MASK 0x8
8704#define RLC_GPM_STAT__GFX_LS_STATUS__SHIFT 0x3
8705#define RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS_MASK 0x10
8706#define RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS__SHIFT 0x4
8707#define RLC_GPM_STAT__CNTX_IDLE_BEING_PROCESSED_MASK 0x20
8708#define RLC_GPM_STAT__CNTX_IDLE_BEING_PROCESSED__SHIFT 0x5
8709#define RLC_GPM_STAT__CNTX_BUSY_BEING_PROCESSED_MASK 0x40
8710#define RLC_GPM_STAT__CNTX_BUSY_BEING_PROCESSED__SHIFT 0x6
8711#define RLC_GPM_STAT__GFX_IDLE_BEING_PROCESSED_MASK 0x80
8712#define RLC_GPM_STAT__GFX_IDLE_BEING_PROCESSED__SHIFT 0x7
8713#define RLC_GPM_STAT__CMP_BUSY_BEING_PROCESSED_MASK 0x100
8714#define RLC_GPM_STAT__CMP_BUSY_BEING_PROCESSED__SHIFT 0x8
8715#define RLC_GPM_STAT__SAVING_REGISTERS_MASK 0x200
8716#define RLC_GPM_STAT__SAVING_REGISTERS__SHIFT 0x9
8717#define RLC_GPM_STAT__RESTORING_REGISTERS_MASK 0x400
8718#define RLC_GPM_STAT__RESTORING_REGISTERS__SHIFT 0xa
8719#define RLC_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE_MASK 0x800
8720#define RLC_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE__SHIFT 0xb
8721#define RLC_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE_MASK 0x1000
8722#define RLC_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE__SHIFT 0xc
8723#define RLC_GPM_STAT__STATIC_CU_POWERING_UP_MASK 0x2000
8724#define RLC_GPM_STAT__STATIC_CU_POWERING_UP__SHIFT 0xd
8725#define RLC_GPM_STAT__STATIC_CU_POWERING_DOWN_MASK 0x4000
8726#define RLC_GPM_STAT__STATIC_CU_POWERING_DOWN__SHIFT 0xe
8727#define RLC_GPM_STAT__DYN_CU_POWERING_UP_MASK 0x8000
8728#define RLC_GPM_STAT__DYN_CU_POWERING_UP__SHIFT 0xf
8729#define RLC_GPM_STAT__DYN_CU_POWERING_DOWN_MASK 0x10000
8730#define RLC_GPM_STAT__DYN_CU_POWERING_DOWN__SHIFT 0x10
8731#define RLC_GPM_STAT__ABORTED_PD_SEQUENCE_MASK 0x20000
8732#define RLC_GPM_STAT__ABORTED_PD_SEQUENCE__SHIFT 0x11
8733#define RLC_GPM_STAT__PG_ERROR_STATUS_MASK 0xff000000
8734#define RLC_GPM_STAT__PG_ERROR_STATUS__SHIFT 0x18
8735#define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL_MASK 0x3f
8736#define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL__SHIFT 0x0
8737#define RLC_GPU_CLOCK_32_RES_SEL__RESERVED_MASK 0xffffffc0
8738#define RLC_GPU_CLOCK_32_RES_SEL__RESERVED__SHIFT 0x6
8739#define RLC_GPU_CLOCK_32__GPU_CLOCK_32_MASK 0xffffffff
8740#define RLC_GPU_CLOCK_32__GPU_CLOCK_32__SHIFT 0x0
8741#define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK 0x1
8742#define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE__SHIFT 0x0
8743#define RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK 0x2
8744#define RLC_PG_CNTL__GFX_POWER_GATING_SRC__SHIFT 0x1
8745#define RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK 0x4
8746#define RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE__SHIFT 0x2
8747#define RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK 0x8
8748#define RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE__SHIFT 0x3
8749#define RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE_MASK 0x10
8750#define RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE__SHIFT 0x4
8751#define RLC_PG_CNTL__RESERVED_MASK 0x3fe0
8752#define RLC_PG_CNTL__RESERVED__SHIFT 0x5
8753#define RLC_PG_CNTL__PG_OVERRIDE_MASK 0x4000
8754#define RLC_PG_CNTL__PG_OVERRIDE__SHIFT 0xe
8755#define RLC_PG_CNTL__CP_PG_DISABLE_MASK 0x8000
8756#define RLC_PG_CNTL__CP_PG_DISABLE__SHIFT 0xf
8757#define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE_MASK 0x10000
8758#define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE__SHIFT 0x10
8759#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK 0x20000
8760#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE__SHIFT 0x11
8761#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK 0x40000
8762#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE__SHIFT 0x12
8763#define RLC_PG_CNTL__SMU_HANDSHAKE_ENABLE_MASK 0x80000
8764#define RLC_PG_CNTL__SMU_HANDSHAKE_ENABLE__SHIFT 0x13
8765#define RLC_PG_CNTL__QUICK_PG_ENABLE_MASK 0x100000
8766#define RLC_PG_CNTL__QUICK_PG_ENABLE__SHIFT 0x14
8767#define RLC_PG_CNTL__RESERVED1_MASK 0xe00000
8768#define RLC_PG_CNTL__RESERVED1__SHIFT 0x15
8769#define RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY_MASK 0xff
8770#define RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY__SHIFT 0x0
8771#define RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY_MASK 0xff00
8772#define RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY__SHIFT 0x8
8773#define RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY_MASK 0xff0000
8774#define RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY__SHIFT 0x10
8775#define RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY_MASK 0xff000000
8776#define RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY__SHIFT 0x18
8777#define RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE_MASK 0x1
8778#define RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE__SHIFT 0x0
8779#define RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE_MASK 0x2
8780#define RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE__SHIFT 0x1
8781#define RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE_MASK 0x4
8782#define RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE__SHIFT 0x2
8783#define RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE_MASK 0x8
8784#define RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE__SHIFT 0x3
8785#define RLC_GPM_THREAD_ENABLE__RESERVED_MASK 0xfffffff0
8786#define RLC_GPM_THREAD_ENABLE__RESERVED__SHIFT 0x4
8787#define RLC_GPM_VMID_THREAD0__RLC_VMID_MASK 0xf
8788#define RLC_GPM_VMID_THREAD0__RLC_VMID__SHIFT 0x0
8789#define RLC_GPM_VMID_THREAD0__RESERVED0_MASK 0xf0
8790#define RLC_GPM_VMID_THREAD0__RESERVED0__SHIFT 0x4
8791#define RLC_GPM_VMID_THREAD0__RLC_QUEUEID_MASK 0x700
8792#define RLC_GPM_VMID_THREAD0__RLC_QUEUEID__SHIFT 0x8
8793#define RLC_GPM_VMID_THREAD0__RESERVED1_MASK 0xfffff800
8794#define RLC_GPM_VMID_THREAD0__RESERVED1__SHIFT 0xb
8795#define RLC_GPM_VMID_THREAD1__RLC_VMID_MASK 0xf
8796#define RLC_GPM_VMID_THREAD1__RLC_VMID__SHIFT 0x0
8797#define RLC_GPM_VMID_THREAD1__RESERVED0_MASK 0xf0
8798#define RLC_GPM_VMID_THREAD1__RESERVED0__SHIFT 0x4
8799#define RLC_GPM_VMID_THREAD1__RLC_QUEUEID_MASK 0x700
8800#define RLC_GPM_VMID_THREAD1__RLC_QUEUEID__SHIFT 0x8
8801#define RLC_GPM_VMID_THREAD1__RESERVED1_MASK 0xfffff800
8802#define RLC_GPM_VMID_THREAD1__RESERVED1__SHIFT 0xb
8803#define RLC_CGTT_MGCG_OVERRIDE__OVERRIDE_MASK 0xffffffff
8804#define RLC_CGTT_MGCG_OVERRIDE__OVERRIDE__SHIFT 0x0
8805#define RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK 0x1
8806#define RLC_CGCG_CGLS_CTRL__CGCG_EN__SHIFT 0x0
8807#define RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK 0x2
8808#define RLC_CGCG_CGLS_CTRL__CGLS_EN__SHIFT 0x1
8809#define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK 0xfc
8810#define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT 0x2
8811#define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK 0x7ffff00
8812#define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT 0x8
8813#define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER_MASK 0x8000000
8814#define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER__SHIFT 0x1b
8815#define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL_MASK 0x10000000
8816#define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL__SHIFT 0x1c
8817#define RLC_CGCG_CGLS_CTRL__SLEEP_MODE_MASK 0x60000000
8818#define RLC_CGCG_CGLS_CTRL__SLEEP_MODE__SHIFT 0x1d
8819#define RLC_CGCG_CGLS_CTRL__SIM_SILICON_EN_MASK 0x80000000
8820#define RLC_CGCG_CGLS_CTRL__SIM_SILICON_EN__SHIFT 0x1f
8821#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT_MASK 0xf
8822#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT__SHIFT 0x0
8823#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT_MASK 0xf0
8824#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT__SHIFT 0x4
8825#define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT_MASK 0xf00
8826#define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT__SHIFT 0x8
8827#define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT_MASK 0xf000
8828#define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT__SHIFT 0xc
8829#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT_MASK 0xfff0000
8830#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT__SHIFT 0x10
8831#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT_MASK 0xf0000000
8832#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT__SHIFT 0x1c
8833#define RLC_DYN_PG_STATUS__PG_STATUS_CU_MASK_MASK 0xffffffff
8834#define RLC_DYN_PG_STATUS__PG_STATUS_CU_MASK__SHIFT 0x0
8835#define RLC_DYN_PG_REQUEST__PG_REQUEST_CU_MASK_MASK 0xffffffff
8836#define RLC_DYN_PG_REQUEST__PG_REQUEST_CU_MASK__SHIFT 0x0
8837#define RLC_PG_DELAY__POWER_UP_DELAY_MASK 0xff
8838#define RLC_PG_DELAY__POWER_UP_DELAY__SHIFT 0x0
8839#define RLC_PG_DELAY__POWER_DOWN_DELAY_MASK 0xff00
8840#define RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT 0x8
8841#define RLC_PG_DELAY__CMD_PROPAGATE_DELAY_MASK 0xff0000
8842#define RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT 0x10
8843#define RLC_PG_DELAY__MEM_SLEEP_DELAY_MASK 0xff000000
8844#define RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT 0x18
8845#define RLC_CU_STATUS__WORK_PENDING_MASK 0xffffffff
8846#define RLC_CU_STATUS__WORK_PENDING__SHIFT 0x0
8847#define RLC_LB_INIT_CU_MASK__INIT_CU_MASK_MASK 0xffffffff
8848#define RLC_LB_INIT_CU_MASK__INIT_CU_MASK__SHIFT 0x0
8849#define RLC_LB_ALWAYS_ACTIVE_CU_MASK__ALWAYS_ACTIVE_CU_MASK_MASK 0xffffffff
8850#define RLC_LB_ALWAYS_ACTIVE_CU_MASK__ALWAYS_ACTIVE_CU_MASK__SHIFT 0x0
8851#define RLC_LB_PARAMS__SKIP_L2_CHECK_MASK 0x1
8852#define RLC_LB_PARAMS__SKIP_L2_CHECK__SHIFT 0x0
8853#define RLC_LB_PARAMS__FIFO_SAMPLES_MASK 0xfe
8854#define RLC_LB_PARAMS__FIFO_SAMPLES__SHIFT 0x1
8855#define RLC_LB_PARAMS__PG_IDLE_SAMPLES_MASK 0xff00
8856#define RLC_LB_PARAMS__PG_IDLE_SAMPLES__SHIFT 0x8
8857#define RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL_MASK 0xffff0000
8858#define RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL__SHIFT 0x10
8859#define RLC_THREAD1_DELAY__CU_IDEL_DELAY_MASK 0xff
8860#define RLC_THREAD1_DELAY__CU_IDEL_DELAY__SHIFT 0x0
8861#define RLC_THREAD1_DELAY__LBPW_INNER_LOOP_DELAY_MASK 0xff00
8862#define RLC_THREAD1_DELAY__LBPW_INNER_LOOP_DELAY__SHIFT 0x8
8863#define RLC_THREAD1_DELAY__LBPW_OUTER_LOOP_DELAY_MASK 0xff0000
8864#define RLC_THREAD1_DELAY__LBPW_OUTER_LOOP_DELAY__SHIFT 0x10
8865#define RLC_THREAD1_DELAY__SPARE_MASK 0xff000000
8866#define RLC_THREAD1_DELAY__SPARE__SHIFT 0x18
8867#define RLC_PG_ALWAYS_ON_CU_MASK__AON_CU_MASK_MASK 0xffffffff
8868#define RLC_PG_ALWAYS_ON_CU_MASK__AON_CU_MASK__SHIFT 0x0
8869#define RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK 0xff
8870#define RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT 0x0
8871#define RLC_MAX_PG_CU__SPARE_MASK 0xffffff00
8872#define RLC_MAX_PG_CU__SPARE__SHIFT 0x8
8873#define RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK 0x1
8874#define RLC_AUTO_PG_CTRL__AUTO_PG_EN__SHIFT 0x0
8875#define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN_MASK 0x2
8876#define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN__SHIFT 0x1
8877#define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN_MASK 0x4
8878#define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN__SHIFT 0x2
8879#define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK 0x7fff8
8880#define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT 0x3
8881#define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK 0xfff80000
8882#define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD__SHIFT 0x13
8883#define RLC_SMU_GRBM_REG_SAVE_CTRL__START_GRBM_REG_SAVE_MASK 0x1
8884#define RLC_SMU_GRBM_REG_SAVE_CTRL__START_GRBM_REG_SAVE__SHIFT 0x0
8885#define RLC_SMU_GRBM_REG_SAVE_CTRL__SPARE_MASK 0xfffffffe
8886#define RLC_SMU_GRBM_REG_SAVE_CTRL__SPARE__SHIFT 0x1
8887#define RLC_SMU_PG_CTRL__START_PG_MASK 0x1
8888#define RLC_SMU_PG_CTRL__START_PG__SHIFT 0x0
8889#define RLC_SMU_PG_CTRL__SPARE_MASK 0xfffffffe
8890#define RLC_SMU_PG_CTRL__SPARE__SHIFT 0x1
8891#define RLC_SMU_PG_WAKE_UP_CTRL__START_PG_WAKE_UP_MASK 0x1
8892#define RLC_SMU_PG_WAKE_UP_CTRL__START_PG_WAKE_UP__SHIFT 0x0
8893#define RLC_SMU_PG_WAKE_UP_CTRL__SPARE_MASK 0xfffffffe
8894#define RLC_SMU_PG_WAKE_UP_CTRL__SPARE__SHIFT 0x1
8895#define RLC_SERDES_RD_MASTER_INDEX__CU_ID_MASK 0xf
8896#define RLC_SERDES_RD_MASTER_INDEX__CU_ID__SHIFT 0x0
8897#define RLC_SERDES_RD_MASTER_INDEX__SH_ID_MASK 0x30
8898#define RLC_SERDES_RD_MASTER_INDEX__SH_ID__SHIFT 0x4
8899#define RLC_SERDES_RD_MASTER_INDEX__SE_ID_MASK 0x1c0
8900#define RLC_SERDES_RD_MASTER_INDEX__SE_ID__SHIFT 0x6
8901#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_ID_MASK 0x200
8902#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_ID__SHIFT 0x9
8903#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_MASK 0x400
8904#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU__SHIFT 0xa
8905#define RLC_SERDES_RD_MASTER_INDEX__NON_SE_MASK 0x7800
8906#define RLC_SERDES_RD_MASTER_INDEX__NON_SE__SHIFT 0xb
8907#define RLC_SERDES_RD_MASTER_INDEX__DATA_REG_ID_MASK 0x18000
8908#define RLC_SERDES_RD_MASTER_INDEX__DATA_REG_ID__SHIFT 0xf
8909#define RLC_SERDES_RD_MASTER_INDEX__SPARE_MASK 0xfffe0000
8910#define RLC_SERDES_RD_MASTER_INDEX__SPARE__SHIFT 0x11
8911#define RLC_SERDES_RD_DATA_0__DATA_MASK 0xffffffff
8912#define RLC_SERDES_RD_DATA_0__DATA__SHIFT 0x0
8913#define RLC_SERDES_RD_DATA_1__DATA_MASK 0xffffffff
8914#define RLC_SERDES_RD_DATA_1__DATA__SHIFT 0x0
8915#define RLC_SERDES_RD_DATA_2__DATA_MASK 0xffffffff
8916#define RLC_SERDES_RD_DATA_2__DATA__SHIFT 0x0
8917#define RLC_SERDES_WR_CU_MASTER_MASK__MASTER_MASK_MASK 0xffffffff
8918#define RLC_SERDES_WR_CU_MASTER_MASK__MASTER_MASK__SHIFT 0x0
8919#define RLC_SERDES_WR_NONCU_MASTER_MASK__SE_MASTER_MASK_MASK 0xffff
8920#define RLC_SERDES_WR_NONCU_MASTER_MASK__SE_MASTER_MASK__SHIFT 0x0
8921#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_MASTER_MASK_MASK 0x10000
8922#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_MASTER_MASK__SHIFT 0x10
8923#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_GFX_MASTER_MASK_MASK 0x20000
8924#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_GFX_MASTER_MASK__SHIFT 0x11
8925#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC0_MASTER_MASK_MASK 0x40000
8926#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC0_MASTER_MASK__SHIFT 0x12
8927#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC1_MASTER_MASK_MASK 0x80000
8928#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC1_MASTER_MASK__SHIFT 0x13
8929#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE0_MASTER_MASK_MASK 0x100000
8930#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE0_MASTER_MASK__SHIFT 0x14
8931#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE1_MASTER_MASK_MASK 0x200000
8932#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE1_MASTER_MASK__SHIFT 0x15
8933#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE2_MASTER_MASK_MASK 0x400000
8934#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE2_MASTER_MASK__SHIFT 0x16
8935#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE3_MASTER_MASK_MASK 0x800000
8936#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE3_MASTER_MASK__SHIFT 0x17
8937#define RLC_SERDES_WR_NONCU_MASTER_MASK__RESERVED_MASK 0xff000000
8938#define RLC_SERDES_WR_NONCU_MASTER_MASK__RESERVED__SHIFT 0x18
8939#define RLC_SERDES_WR_CTRL__BPM_ADDR_MASK 0xff
8940#define RLC_SERDES_WR_CTRL__BPM_ADDR__SHIFT 0x0
8941#define RLC_SERDES_WR_CTRL__POWER_DOWN_MASK 0x100
8942#define RLC_SERDES_WR_CTRL__POWER_DOWN__SHIFT 0x8
8943#define RLC_SERDES_WR_CTRL__POWER_UP_MASK 0x200
8944#define RLC_SERDES_WR_CTRL__POWER_UP__SHIFT 0x9
8945#define RLC_SERDES_WR_CTRL__P1_SELECT_MASK 0x400
8946#define RLC_SERDES_WR_CTRL__P1_SELECT__SHIFT 0xa
8947#define RLC_SERDES_WR_CTRL__P2_SELECT_MASK 0x800
8948#define RLC_SERDES_WR_CTRL__P2_SELECT__SHIFT 0xb
8949#define RLC_SERDES_WR_CTRL__WRITE_COMMAND_MASK 0x1000
8950#define RLC_SERDES_WR_CTRL__WRITE_COMMAND__SHIFT 0xc
8951#define RLC_SERDES_WR_CTRL__READ_COMMAND_MASK 0x2000
8952#define RLC_SERDES_WR_CTRL__READ_COMMAND__SHIFT 0xd
8953#define RLC_SERDES_WR_CTRL__RDDATA_RESET_MASK 0x4000
8954#define RLC_SERDES_WR_CTRL__RDDATA_RESET__SHIFT 0xe
8955#define RLC_SERDES_WR_CTRL__SHORT_FORMAT_MASK 0x8000
8956#define RLC_SERDES_WR_CTRL__SHORT_FORMAT__SHIFT 0xf
8957#define RLC_SERDES_WR_CTRL__BPM_DATA_MASK 0x3ff0000
8958#define RLC_SERDES_WR_CTRL__BPM_DATA__SHIFT 0x10
8959#define RLC_SERDES_WR_CTRL__SRBM_OVERRIDE_MASK 0x4000000
8960#define RLC_SERDES_WR_CTRL__SRBM_OVERRIDE__SHIFT 0x1a
8961#define RLC_SERDES_WR_CTRL__RSVD_BPM_ADDR_MASK 0x8000000
8962#define RLC_SERDES_WR_CTRL__RSVD_BPM_ADDR__SHIFT 0x1b
8963#define RLC_SERDES_WR_CTRL__REG_ADDR_MASK 0xf0000000
8964#define RLC_SERDES_WR_CTRL__REG_ADDR__SHIFT 0x1c
8965#define RLC_SERDES_WR_DATA__DATA_MASK 0xffffffff
8966#define RLC_SERDES_WR_DATA__DATA__SHIFT 0x0
8967#define RLC_SERDES_CU_MASTER_BUSY__BUSY_BUSY_MASK 0xffffffff
8968#define RLC_SERDES_CU_MASTER_BUSY__BUSY_BUSY__SHIFT 0x0
8969#define RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK 0xffff
8970#define RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY__SHIFT 0x0
8971#define RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK 0x10000
8972#define RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY__SHIFT 0x10
8973#define RLC_SERDES_NONCU_MASTER_BUSY__GC_GFX_MASTER_BUSY_MASK 0x20000
8974#define RLC_SERDES_NONCU_MASTER_BUSY__GC_GFX_MASTER_BUSY__SHIFT 0x11
8975#define RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK 0x40000
8976#define RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY__SHIFT 0x12
8977#define RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK 0x80000
8978#define RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY__SHIFT 0x13
8979#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE0_MASTER_BUSY_MASK 0x100000
8980#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE0_MASTER_BUSY__SHIFT 0x14
8981#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE1_MASTER_BUSY_MASK 0x200000
8982#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE1_MASTER_BUSY__SHIFT 0x15
8983#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE2_MASTER_BUSY_MASK 0x400000
8984#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE2_MASTER_BUSY__SHIFT 0x16
8985#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE3_MASTER_BUSY_MASK 0x800000
8986#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE3_MASTER_BUSY__SHIFT 0x17
8987#define RLC_SERDES_NONCU_MASTER_BUSY__RESERVED_MASK 0xff000000
8988#define RLC_SERDES_NONCU_MASTER_BUSY__RESERVED__SHIFT 0x18
8989#define RLC_GPM_GENERAL_0__DATA_MASK 0xffffffff
8990#define RLC_GPM_GENERAL_0__DATA__SHIFT 0x0
8991#define RLC_GPM_GENERAL_1__DATA_MASK 0xffffffff
8992#define RLC_GPM_GENERAL_1__DATA__SHIFT 0x0
8993#define RLC_GPM_GENERAL_2__DATA_MASK 0xffffffff
8994#define RLC_GPM_GENERAL_2__DATA__SHIFT 0x0
8995#define RLC_GPM_GENERAL_3__DATA_MASK 0xffffffff
8996#define RLC_GPM_GENERAL_3__DATA__SHIFT 0x0
8997#define RLC_GPM_GENERAL_4__DATA_MASK 0xffffffff
8998#define RLC_GPM_GENERAL_4__DATA__SHIFT 0x0
8999#define RLC_GPM_GENERAL_5__DATA_MASK 0xffffffff
9000#define RLC_GPM_GENERAL_5__DATA__SHIFT 0x0
9001#define RLC_GPM_GENERAL_6__DATA_MASK 0xffffffff
9002#define RLC_GPM_GENERAL_6__DATA__SHIFT 0x0
9003#define RLC_GPM_GENERAL_7__DATA_MASK 0xffffffff
9004#define RLC_GPM_GENERAL_7__DATA__SHIFT 0x0
9005#define RLC_GPM_CU_PD_TIMEOUT__TIMEOUT_MASK 0xffffffff
9006#define RLC_GPM_CU_PD_TIMEOUT__TIMEOUT__SHIFT 0x0
9007#define RLC_GPM_SCRATCH_ADDR__ADDR_MASK 0x1ff
9008#define RLC_GPM_SCRATCH_ADDR__ADDR__SHIFT 0x0
9009#define RLC_GPM_SCRATCH_ADDR__RESERVED_MASK 0xfffffe00
9010#define RLC_GPM_SCRATCH_ADDR__RESERVED__SHIFT 0x9
9011#define RLC_GPM_SCRATCH_DATA__DATA_MASK 0xffffffff
9012#define RLC_GPM_SCRATCH_DATA__DATA__SHIFT 0x0
9013#define RLC_STATIC_PG_STATUS__PG_STATUS_CU_MASK_MASK 0xffffffff
9014#define RLC_STATIC_PG_STATUS__PG_STATUS_CU_MASK__SHIFT 0x0
9015#define RLC_GPM_PERF_COUNT_0__FEATURE_SEL_MASK 0xf
9016#define RLC_GPM_PERF_COUNT_0__FEATURE_SEL__SHIFT 0x0
9017#define RLC_GPM_PERF_COUNT_0__SE_INDEX_MASK 0xf0
9018#define RLC_GPM_PERF_COUNT_0__SE_INDEX__SHIFT 0x4
9019#define RLC_GPM_PERF_COUNT_0__SH_INDEX_MASK 0xf00
9020#define RLC_GPM_PERF_COUNT_0__SH_INDEX__SHIFT 0x8
9021#define RLC_GPM_PERF_COUNT_0__CU_INDEX_MASK 0xf000
9022#define RLC_GPM_PERF_COUNT_0__CU_INDEX__SHIFT 0xc
9023#define RLC_GPM_PERF_COUNT_0__EVENT_SEL_MASK 0x30000
9024#define RLC_GPM_PERF_COUNT_0__EVENT_SEL__SHIFT 0x10
9025#define RLC_GPM_PERF_COUNT_0__UNUSED_MASK 0xc0000
9026#define RLC_GPM_PERF_COUNT_0__UNUSED__SHIFT 0x12
9027#define RLC_GPM_PERF_COUNT_0__ENABLE_MASK 0x100000
9028#define RLC_GPM_PERF_COUNT_0__ENABLE__SHIFT 0x14
9029#define RLC_GPM_PERF_COUNT_0__RESERVED_MASK 0xffe00000
9030#define RLC_GPM_PERF_COUNT_0__RESERVED__SHIFT 0x15
9031#define RLC_GPM_PERF_COUNT_1__FEATURE_SEL_MASK 0xf
9032#define RLC_GPM_PERF_COUNT_1__FEATURE_SEL__SHIFT 0x0
9033#define RLC_GPM_PERF_COUNT_1__SE_INDEX_MASK 0xf0
9034#define RLC_GPM_PERF_COUNT_1__SE_INDEX__SHIFT 0x4
9035#define RLC_GPM_PERF_COUNT_1__SH_INDEX_MASK 0xf00
9036#define RLC_GPM_PERF_COUNT_1__SH_INDEX__SHIFT 0x8
9037#define RLC_GPM_PERF_COUNT_1__CU_INDEX_MASK 0xf000
9038#define RLC_GPM_PERF_COUNT_1__CU_INDEX__SHIFT 0xc
9039#define RLC_GPM_PERF_COUNT_1__EVENT_SEL_MASK 0x30000
9040#define RLC_GPM_PERF_COUNT_1__EVENT_SEL__SHIFT 0x10
9041#define RLC_GPM_PERF_COUNT_1__UNUSED_MASK 0xc0000
9042#define RLC_GPM_PERF_COUNT_1__UNUSED__SHIFT 0x12
9043#define RLC_GPM_PERF_COUNT_1__ENABLE_MASK 0x100000
9044#define RLC_GPM_PERF_COUNT_1__ENABLE__SHIFT 0x14
9045#define RLC_GPM_PERF_COUNT_1__RESERVED_MASK 0xffe00000
9046#define RLC_GPM_PERF_COUNT_1__RESERVED__SHIFT 0x15
9047#define RLC_GPR_REG1__DATA_MASK 0xffffffff
9048#define RLC_GPR_REG1__DATA__SHIFT 0x0
9049#define RLC_GPR_REG2__DATA_MASK 0xffffffff
9050#define RLC_GPR_REG2__DATA__SHIFT 0x0
9051#define RLC_MGCG_CTRL__MGCG_EN_MASK 0x1
9052#define RLC_MGCG_CTRL__MGCG_EN__SHIFT 0x0
9053#define RLC_MGCG_CTRL__SILICON_EN_MASK 0x2
9054#define RLC_MGCG_CTRL__SILICON_EN__SHIFT 0x1
9055#define RLC_MGCG_CTRL__SIMULATION_EN_MASK 0x4
9056#define RLC_MGCG_CTRL__SIMULATION_EN__SHIFT 0x2
9057#define RLC_MGCG_CTRL__ON_DELAY_MASK 0x78
9058#define RLC_MGCG_CTRL__ON_DELAY__SHIFT 0x3
9059#define RLC_MGCG_CTRL__OFF_HYSTERESIS_MASK 0x7f80
9060#define RLC_MGCG_CTRL__OFF_HYSTERESIS__SHIFT 0x7
9061#define RLC_MGCG_CTRL__SPARE_MASK 0xffff8000
9062#define RLC_MGCG_CTRL__SPARE__SHIFT 0xf
9063#define RLC_GPM_THREAD_RESET__THREAD0_RESET_MASK 0x1
9064#define RLC_GPM_THREAD_RESET__THREAD0_RESET__SHIFT 0x0
9065#define RLC_GPM_THREAD_RESET__THREAD1_RESET_MASK 0x2
9066#define RLC_GPM_THREAD_RESET__THREAD1_RESET__SHIFT 0x1
9067#define RLC_GPM_THREAD_RESET__THREAD2_RESET_MASK 0x4
9068#define RLC_GPM_THREAD_RESET__THREAD2_RESET__SHIFT 0x2
9069#define RLC_GPM_THREAD_RESET__THREAD3_RESET_MASK 0x8
9070#define RLC_GPM_THREAD_RESET__THREAD3_RESET__SHIFT 0x3
9071#define RLC_GPM_THREAD_RESET__RESERVED_MASK 0xfffffff0
9072#define RLC_GPM_THREAD_RESET__RESERVED__SHIFT 0x4
9073#define RLC_SPM_VMID__RLC_SPM_VMID_MASK 0xf
9074#define RLC_SPM_VMID__RLC_SPM_VMID__SHIFT 0x0
9075#define RLC_SPM_VMID__RESERVED_MASK 0xfffffff0
9076#define RLC_SPM_VMID__RESERVED__SHIFT 0x4
9077#define RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL_MASK 0x1
9078#define RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL__SHIFT 0x0
9079#define RLC_SPM_INT_CNTL__RESERVED_MASK 0xfffffffe
9080#define RLC_SPM_INT_CNTL__RESERVED__SHIFT 0x1
9081#define RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS_MASK 0x1
9082#define RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS__SHIFT 0x0
9083#define RLC_SPM_INT_STATUS__RESERVED_MASK 0xfffffffe
9084#define RLC_SPM_INT_STATUS__RESERVED__SHIFT 0x1
9085#define RLC_SPM_DEBUG_SELECT__SELECT_MASK 0xff
9086#define RLC_SPM_DEBUG_SELECT__SELECT__SHIFT 0x0
9087#define RLC_SPM_DEBUG_SELECT__RESERVED_MASK 0x7f00
9088#define RLC_SPM_DEBUG_SELECT__RESERVED__SHIFT 0x8
9089#define RLC_SPM_DEBUG_SELECT__RLC_SPM_DEBUG_MODE_MASK 0x8000
9090#define RLC_SPM_DEBUG_SELECT__RLC_SPM_DEBUG_MODE__SHIFT 0xf
9091#define RLC_SPM_DEBUG_SELECT__RLC_SPM_NUM_SAMPLE_MASK 0xffff0000
9092#define RLC_SPM_DEBUG_SELECT__RLC_SPM_NUM_SAMPLE__SHIFT 0x10
9093#define RLC_SPM_DEBUG__DATA_MASK 0xffffffff
9094#define RLC_SPM_DEBUG__DATA__SHIFT 0x0
9095#define RLC_GPM_LOG_ADDR__ADDR_MASK 0xffffffff
9096#define RLC_GPM_LOG_ADDR__ADDR__SHIFT 0x0
9097#define RLC_SMU_MESSAGE__CMD_MASK 0xffffffff
9098#define RLC_SMU_MESSAGE__CMD__SHIFT 0x0
9099#define RLC_GPM_LOG_SIZE__SIZE_MASK 0xffffffff
9100#define RLC_GPM_LOG_SIZE__SIZE__SHIFT 0x0
9101#define RLC_GPM_LOG_CONT__CONT_MASK 0xffffffff
9102#define RLC_GPM_LOG_CONT__CONT__SHIFT 0x0
9103#define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK 0xff
9104#define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT 0x0
9105#define RLC_GPM_INT_DISABLE_TH0__DISABLE_MASK 0xffffffff
9106#define RLC_GPM_INT_DISABLE_TH0__DISABLE__SHIFT 0x0
9107#define RLC_GPM_INT_DISABLE_TH1__DISABLE_MASK 0xffffffff
9108#define RLC_GPM_INT_DISABLE_TH1__DISABLE__SHIFT 0x0
9109#define RLC_GPM_INT_FORCE_TH0__FORCE_MASK 0xffffffff
9110#define RLC_GPM_INT_FORCE_TH0__FORCE__SHIFT 0x0
9111#define RLC_GPM_INT_FORCE_TH1__FORCE_MASK 0xffffffff
9112#define RLC_GPM_INT_FORCE_TH1__FORCE__SHIFT 0x0
9113#define RLC_SRM_CNTL__SRM_ENABLE_MASK 0x1
9114#define RLC_SRM_CNTL__SRM_ENABLE__SHIFT 0x0
9115#define RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK 0x2
9116#define RLC_SRM_CNTL__AUTO_INCR_ADDR__SHIFT 0x1
9117#define RLC_SRM_CNTL__RESERVED_MASK 0xfffffffc
9118#define RLC_SRM_CNTL__RESERVED__SHIFT 0x2
9119#define RLC_SRM_DEBUG_SELECT__SELECT_MASK 0xff
9120#define RLC_SRM_DEBUG_SELECT__SELECT__SHIFT 0x0
9121#define RLC_SRM_DEBUG_SELECT__RESERVED_MASK 0xffffff00
9122#define RLC_SRM_DEBUG_SELECT__RESERVED__SHIFT 0x8
9123#define RLC_SRM_DEBUG__DATA_MASK 0xffffffff
9124#define RLC_SRM_DEBUG__DATA__SHIFT 0x0
9125#define RLC_SRM_ARAM_DATA__DATA_MASK 0xffffffff
9126#define RLC_SRM_ARAM_DATA__DATA__SHIFT 0x0
9127#define RLC_SRM_DRAM_ADDR__RESERVED_MASK 0xfffffc00
9128#define RLC_SRM_DRAM_ADDR__RESERVED__SHIFT 0xa
9129#define RLC_SRM_DRAM_DATA__DATA_MASK 0xffffffff
9130#define RLC_SRM_DRAM_DATA__DATA__SHIFT 0x0
9131#define RLC_SRM_GPM_COMMAND__OP_MASK 0x1
9132#define RLC_SRM_GPM_COMMAND__OP__SHIFT 0x0
9133#define RLC_SRM_GPM_COMMAND__INDEX_CNTL_MASK 0x2
9134#define RLC_SRM_GPM_COMMAND__INDEX_CNTL__SHIFT 0x1
9135#define RLC_SRM_GPM_COMMAND__INDEX_CNTL_NUM_MASK 0x1c
9136#define RLC_SRM_GPM_COMMAND__INDEX_CNTL_NUM__SHIFT 0x2
9137#define RLC_SRM_GPM_COMMAND__SIZE_MASK 0x1ffe0
9138#define RLC_SRM_GPM_COMMAND__SIZE__SHIFT 0x5
9139#define RLC_SRM_GPM_COMMAND__START_OFFSET_MASK 0x1ffe0000
9140#define RLC_SRM_GPM_COMMAND__START_OFFSET__SHIFT 0x11
9141#define RLC_SRM_GPM_COMMAND__RESERVED1_MASK 0x60000000
9142#define RLC_SRM_GPM_COMMAND__RESERVED1__SHIFT 0x1d
9143#define RLC_SRM_GPM_COMMAND__DEST_MEMORY_MASK 0x80000000
9144#define RLC_SRM_GPM_COMMAND__DEST_MEMORY__SHIFT 0x1f
9145#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_EMPTY_MASK 0x1
9146#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_EMPTY__SHIFT 0x0
9147#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_FULL_MASK 0x2
9148#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_FULL__SHIFT 0x1
9149#define RLC_SRM_GPM_COMMAND_STATUS__RESERVED_MASK 0xfffffffc
9150#define RLC_SRM_GPM_COMMAND_STATUS__RESERVED__SHIFT 0x2
9151#define RLC_SRM_RLCV_COMMAND__OP_MASK 0x1
9152#define RLC_SRM_RLCV_COMMAND__OP__SHIFT 0x0
9153#define RLC_SRM_RLCV_COMMAND__RESERVED_MASK 0xe
9154#define RLC_SRM_RLCV_COMMAND__RESERVED__SHIFT 0x1
9155#define RLC_SRM_RLCV_COMMAND__SIZE_MASK 0xfff0
9156#define RLC_SRM_RLCV_COMMAND__SIZE__SHIFT 0x4
9157#define RLC_SRM_RLCV_COMMAND__START_OFFSET_MASK 0xfff0000
9158#define RLC_SRM_RLCV_COMMAND__START_OFFSET__SHIFT 0x10
9159#define RLC_SRM_RLCV_COMMAND__RESERVED1_MASK 0x70000000
9160#define RLC_SRM_RLCV_COMMAND__RESERVED1__SHIFT 0x1c
9161#define RLC_SRM_RLCV_COMMAND__DEST_MEMORY_MASK 0x80000000
9162#define RLC_SRM_RLCV_COMMAND__DEST_MEMORY__SHIFT 0x1f
9163#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_EMPTY_MASK 0x1
9164#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_EMPTY__SHIFT 0x0
9165#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_FULL_MASK 0x2
9166#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_FULL__SHIFT 0x1
9167#define RLC_SRM_RLCV_COMMAND_STATUS__RESERVED_MASK 0xfffffffc
9168#define RLC_SRM_RLCV_COMMAND_STATUS__RESERVED__SHIFT 0x2
9169#define RLC_SRM_INDEX_CNTL_ADDR_0__ADDRESS_MASK 0xffff
9170#define RLC_SRM_INDEX_CNTL_ADDR_0__ADDRESS__SHIFT 0x0
9171#define RLC_SRM_INDEX_CNTL_ADDR_0__RESERVED_MASK 0xffff0000
9172#define RLC_SRM_INDEX_CNTL_ADDR_0__RESERVED__SHIFT 0x10
9173#define RLC_SRM_INDEX_CNTL_ADDR_1__ADDRESS_MASK 0xffff
9174#define RLC_SRM_INDEX_CNTL_ADDR_1__ADDRESS__SHIFT 0x0
9175#define RLC_SRM_INDEX_CNTL_ADDR_1__RESERVED_MASK 0xffff0000
9176#define RLC_SRM_INDEX_CNTL_ADDR_1__RESERVED__SHIFT 0x10
9177#define RLC_SRM_INDEX_CNTL_ADDR_2__ADDRESS_MASK 0xffff
9178#define RLC_SRM_INDEX_CNTL_ADDR_2__ADDRESS__SHIFT 0x0
9179#define RLC_SRM_INDEX_CNTL_ADDR_2__RESERVED_MASK 0xffff0000
9180#define RLC_SRM_INDEX_CNTL_ADDR_2__RESERVED__SHIFT 0x10
9181#define RLC_SRM_INDEX_CNTL_ADDR_3__ADDRESS_MASK 0xffff
9182#define RLC_SRM_INDEX_CNTL_ADDR_3__ADDRESS__SHIFT 0x0
9183#define RLC_SRM_INDEX_CNTL_ADDR_3__RESERVED_MASK 0xffff0000
9184#define RLC_SRM_INDEX_CNTL_ADDR_3__RESERVED__SHIFT 0x10
9185#define RLC_SRM_INDEX_CNTL_ADDR_4__ADDRESS_MASK 0xffff
9186#define RLC_SRM_INDEX_CNTL_ADDR_4__ADDRESS__SHIFT 0x0
9187#define RLC_SRM_INDEX_CNTL_ADDR_4__RESERVED_MASK 0xffff0000
9188#define RLC_SRM_INDEX_CNTL_ADDR_4__RESERVED__SHIFT 0x10
9189#define RLC_SRM_INDEX_CNTL_ADDR_5__ADDRESS_MASK 0xffff
9190#define RLC_SRM_INDEX_CNTL_ADDR_5__ADDRESS__SHIFT 0x0
9191#define RLC_SRM_INDEX_CNTL_ADDR_5__RESERVED_MASK 0xffff0000
9192#define RLC_SRM_INDEX_CNTL_ADDR_5__RESERVED__SHIFT 0x10
9193#define RLC_SRM_INDEX_CNTL_ADDR_6__ADDRESS_MASK 0xffff
9194#define RLC_SRM_INDEX_CNTL_ADDR_6__ADDRESS__SHIFT 0x0
9195#define RLC_SRM_INDEX_CNTL_ADDR_6__RESERVED_MASK 0xffff0000
9196#define RLC_SRM_INDEX_CNTL_ADDR_6__RESERVED__SHIFT 0x10
9197#define RLC_SRM_INDEX_CNTL_ADDR_7__ADDRESS_MASK 0xffff
9198#define RLC_SRM_INDEX_CNTL_ADDR_7__ADDRESS__SHIFT 0x0
9199#define RLC_SRM_INDEX_CNTL_ADDR_7__RESERVED_MASK 0xffff0000
9200#define RLC_SRM_INDEX_CNTL_ADDR_7__RESERVED__SHIFT 0x10
9201#define RLC_SRM_INDEX_CNTL_DATA_0__DATA_MASK 0xffffffff
9202#define RLC_SRM_INDEX_CNTL_DATA_0__DATA__SHIFT 0x0
9203#define RLC_SRM_INDEX_CNTL_DATA_1__DATA_MASK 0xffffffff
9204#define RLC_SRM_INDEX_CNTL_DATA_1__DATA__SHIFT 0x0
9205#define RLC_SRM_INDEX_CNTL_DATA_2__DATA_MASK 0xffffffff
9206#define RLC_SRM_INDEX_CNTL_DATA_2__DATA__SHIFT 0x0
9207#define RLC_SRM_INDEX_CNTL_DATA_3__DATA_MASK 0xffffffff
9208#define RLC_SRM_INDEX_CNTL_DATA_3__DATA__SHIFT 0x0
9209#define RLC_SRM_INDEX_CNTL_DATA_4__DATA_MASK 0xffffffff
9210#define RLC_SRM_INDEX_CNTL_DATA_4__DATA__SHIFT 0x0
9211#define RLC_SRM_INDEX_CNTL_DATA_5__DATA_MASK 0xffffffff
9212#define RLC_SRM_INDEX_CNTL_DATA_5__DATA__SHIFT 0x0
9213#define RLC_SRM_INDEX_CNTL_DATA_6__DATA_MASK 0xffffffff
9214#define RLC_SRM_INDEX_CNTL_DATA_6__DATA__SHIFT 0x0
9215#define RLC_SRM_INDEX_CNTL_DATA_7__DATA_MASK 0xffffffff
9216#define RLC_SRM_INDEX_CNTL_DATA_7__DATA__SHIFT 0x0
9217#define RLC_SRM_STAT__SRM_STATUS_MASK 0x1
9218#define RLC_SRM_STAT__SRM_STATUS__SHIFT 0x0
9219#define RLC_SRM_STAT__RESERVED_MASK 0xfffffffe
9220#define RLC_SRM_STAT__RESERVED__SHIFT 0x1
9221#define RLC_SRM_GPM_ABORT__ABORT_MASK 0x1
9222#define RLC_SRM_GPM_ABORT__ABORT__SHIFT 0x0
9223#define RLC_SRM_GPM_ABORT__RESERVED_MASK 0xfffffffe
9224#define RLC_SRM_GPM_ABORT__RESERVED__SHIFT 0x1
9225#define RLC_CSIB_ADDR_LO__ADDRESS_MASK 0xffffffff
9226#define RLC_CSIB_ADDR_LO__ADDRESS__SHIFT 0x0
9227#define RLC_CSIB_ADDR_HI__ADDRESS_MASK 0xffff
9228#define RLC_CSIB_ADDR_HI__ADDRESS__SHIFT 0x0
9229#define RLC_CSIB_LENGTH__LENGTH_MASK 0xffffffff
9230#define RLC_CSIB_LENGTH__LENGTH__SHIFT 0x0
9231#define RLC_CP_RESPONSE0__RESPONSE_MASK 0xffffffff
9232#define RLC_CP_RESPONSE0__RESPONSE__SHIFT 0x0
9233#define RLC_CP_RESPONSE1__RESPONSE_MASK 0xffffffff
9234#define RLC_CP_RESPONSE1__RESPONSE__SHIFT 0x0
9235#define RLC_CP_RESPONSE2__RESPONSE_MASK 0xffffffff
9236#define RLC_CP_RESPONSE2__RESPONSE__SHIFT 0x0
9237#define RLC_CP_RESPONSE3__RESPONSE_MASK 0xffffffff
9238#define RLC_CP_RESPONSE3__RESPONSE__SHIFT 0x0
9239#define RLC_SMU_COMMAND__CMD_MASK 0xffffffff
9240#define RLC_SMU_COMMAND__CMD__SHIFT 0x0
9241#define RLC_CP_SCHEDULERS__scheduler0_MASK 0xff
9242#define RLC_CP_SCHEDULERS__scheduler0__SHIFT 0x0
9243#define RLC_CP_SCHEDULERS__scheduler1_MASK 0xff00
9244#define RLC_CP_SCHEDULERS__scheduler1__SHIFT 0x8
9245#define RLC_CP_SCHEDULERS__scheduler2_MASK 0xff0000
9246#define RLC_CP_SCHEDULERS__scheduler2__SHIFT 0x10
9247#define RLC_CP_SCHEDULERS__scheduler3_MASK 0xff000000
9248#define RLC_CP_SCHEDULERS__scheduler3__SHIFT 0x18
9249#define RLC_SPM_PERFMON_CNTL__RESERVED1_MASK 0xfff
9250#define RLC_SPM_PERFMON_CNTL__RESERVED1__SHIFT 0x0
9251#define RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE_MASK 0x3000
9252#define RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE__SHIFT 0xc
9253#define RLC_SPM_PERFMON_CNTL__RESERVED_MASK 0xc000
9254#define RLC_SPM_PERFMON_CNTL__RESERVED__SHIFT 0xe
9255#define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL_MASK 0xffff0000
9256#define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL__SHIFT 0x10
9257#define RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO_MASK 0xffffffff
9258#define RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO__SHIFT 0x0
9259#define RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI_MASK 0xffff
9260#define RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI__SHIFT 0x0
9261#define RLC_SPM_PERFMON_RING_BASE_HI__RESERVED_MASK 0xffff0000
9262#define RLC_SPM_PERFMON_RING_BASE_HI__RESERVED__SHIFT 0x10
9263#define RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE_MASK 0xffffffff
9264#define RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE__SHIFT 0x0
9265#define RLC_SPM_PERFMON_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE_MASK 0xff
9266#define RLC_SPM_PERFMON_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE__SHIFT 0x0
9267#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED1_MASK 0x700
9268#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED1__SHIFT 0x8
9269#define RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_LINE_MASK 0xf800
9270#define RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_LINE__SHIFT 0xb
9271#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE0_NUM_LINE_MASK 0x1f0000
9272#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE0_NUM_LINE__SHIFT 0x10
9273#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE1_NUM_LINE_MASK 0x3e00000
9274#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE1_NUM_LINE__SHIFT 0x15
9275#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE2_NUM_LINE_MASK 0x7c000000
9276#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE2_NUM_LINE__SHIFT 0x1a
9277#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED_MASK 0x80000000
9278#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED__SHIFT 0x1f
9279#define RLC_SPM_SE_MUXSEL_ADDR__PERFMON_SEL_ADDR_MASK 0xffffffff
9280#define RLC_SPM_SE_MUXSEL_ADDR__PERFMON_SEL_ADDR__SHIFT 0x0
9281#define RLC_SPM_SE_MUXSEL_DATA__PERFMON_SEL_DATA_MASK 0xffffffff
9282#define RLC_SPM_SE_MUXSEL_DATA__PERFMON_SEL_DATA__SHIFT 0x0
9283#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
9284#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
9285#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
9286#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
9287#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
9288#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
9289#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
9290#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
9291#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
9292#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
9293#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
9294#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
9295#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
9296#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
9297#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
9298#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
9299#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
9300#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
9301#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
9302#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
9303#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
9304#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
9305#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
9306#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
9307#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
9308#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
9309#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
9310#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
9311#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
9312#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
9313#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
9314#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
9315#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
9316#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
9317#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
9318#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
9319#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
9320#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
9321#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
9322#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
9323#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
9324#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
9325#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
9326#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
9327#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
9328#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
9329#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
9330#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
9331#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
9332#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
9333#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
9334#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
9335#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
9336#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
9337#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
9338#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
9339#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
9340#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
9341#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
9342#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
9343#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
9344#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
9345#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
9346#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
9347#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
9348#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
9349#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
9350#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
9351#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
9352#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
9353#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
9354#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
9355#define RLC_SPM_GLOBAL_MUXSEL_ADDR__PERFMON_SEL_ADDR_MASK 0xffffffff
9356#define RLC_SPM_GLOBAL_MUXSEL_ADDR__PERFMON_SEL_ADDR__SHIFT 0x0
9357#define RLC_SPM_GLOBAL_MUXSEL_DATA__PERFMON_SEL_DATA_MASK 0xffffffff
9358#define RLC_SPM_GLOBAL_MUXSEL_DATA__PERFMON_SEL_DATA__SHIFT 0x0
9359#define RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR_MASK 0xffffffff
9360#define RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR__SHIFT 0x0
9361#define RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD_MASK 0xffffffff
9362#define RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD__SHIFT 0x0
9363#define RLC_SPM_DBR0_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
9364#define RLC_SPM_DBR0_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
9365#define RLC_SPM_DBR0_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
9366#define RLC_SPM_DBR0_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
9367#define RLC_SPM_DBR1_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
9368#define RLC_SPM_DBR1_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
9369#define RLC_SPM_DBR1_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
9370#define RLC_SPM_DBR1_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
9371#define RLC_SPM_CBR0_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
9372#define RLC_SPM_CBR0_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
9373#define RLC_SPM_CBR0_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
9374#define RLC_SPM_CBR0_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
9375#define RLC_SPM_CBR1_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
9376#define RLC_SPM_CBR1_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
9377#define RLC_SPM_CBR1_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
9378#define RLC_SPM_CBR1_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
9379#define RLC_GPU_IOV_VF_ENABLE__VF_ENABLE_MASK 0x1
9380#define RLC_GPU_IOV_VF_ENABLE__VF_ENABLE__SHIFT 0x0
9381#define RLC_GPU_IOV_VF_ENABLE__RESERVED_MASK 0xfffe
9382#define RLC_GPU_IOV_VF_ENABLE__RESERVED__SHIFT 0x1
9383#define RLC_GPU_IOV_VF_ENABLE__VF_NUM_MASK 0xffff0000
9384#define RLC_GPU_IOV_VF_ENABLE__VF_NUM__SHIFT 0x10
9385#define RLC_GPU_IOV_CFG_REG1__CMD_TYPE_MASK 0xf
9386#define RLC_GPU_IOV_CFG_REG1__CMD_TYPE__SHIFT 0x0
9387#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_MASK 0x10
9388#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE__SHIFT 0x4
9389#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_INTR_EN_MASK 0x20
9390#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_INTR_EN__SHIFT 0x5
9391#define RLC_GPU_IOV_CFG_REG1__RESERVED_MASK 0xc0
9392#define RLC_GPU_IOV_CFG_REG1__RESERVED__SHIFT 0x6
9393#define RLC_GPU_IOV_CFG_REG1__FCN_ID_MASK 0xff00
9394#define RLC_GPU_IOV_CFG_REG1__FCN_ID__SHIFT 0x8
9395#define RLC_GPU_IOV_CFG_REG1__NEXT_FCN_ID_MASK 0xff0000
9396#define RLC_GPU_IOV_CFG_REG1__NEXT_FCN_ID__SHIFT 0x10
9397#define RLC_GPU_IOV_CFG_REG1__RESERVED1_MASK 0xff000000
9398#define RLC_GPU_IOV_CFG_REG1__RESERVED1__SHIFT 0x18
9399#define RLC_GPU_IOV_CFG_REG2__CMD_STATUS_MASK 0xf
9400#define RLC_GPU_IOV_CFG_REG2__CMD_STATUS__SHIFT 0x0
9401#define RLC_GPU_IOV_CFG_REG2__RESERVED_MASK 0xfffffff0
9402#define RLC_GPU_IOV_CFG_REG2__RESERVED__SHIFT 0x4
9403#define RLC_GPU_IOV_CFG_REG6__CNTXT_SIZE_MASK 0x7f
9404#define RLC_GPU_IOV_CFG_REG6__CNTXT_SIZE__SHIFT 0x0
9405#define RLC_GPU_IOV_CFG_REG6__CNTXT_LOCATION_MASK 0x80
9406#define RLC_GPU_IOV_CFG_REG6__CNTXT_LOCATION__SHIFT 0x7
9407#define RLC_GPU_IOV_CFG_REG6__RESERVED_MASK 0x300
9408#define RLC_GPU_IOV_CFG_REG6__RESERVED__SHIFT 0x8
9409#define RLC_GPU_IOV_CFG_REG6__CNTXT_OFFSET_MASK 0xfffffc00
9410#define RLC_GPU_IOV_CFG_REG6__CNTXT_OFFSET__SHIFT 0xa
9411#define RLC_GPU_IOV_CFG_REG8__VM_BUSY_STATUS_MASK 0xffffffff
9412#define RLC_GPU_IOV_CFG_REG8__VM_BUSY_STATUS__SHIFT 0x0
9413#define RLC_GPU_IOV_CFG_REG9__ACTIVE_FCN_ID_MASK 0xff
9414#define RLC_GPU_IOV_CFG_REG9__ACTIVE_FCN_ID__SHIFT 0x0
9415#define RLC_GPU_IOV_CFG_REG9__ACTIVE_FCN_ID_STATUS_MASK 0xf00
9416#define RLC_GPU_IOV_CFG_REG9__ACTIVE_FCN_ID_STATUS__SHIFT 0x8
9417#define RLC_GPU_IOV_CFG_REG9__RESERVED_MASK 0xfffff000
9418#define RLC_GPU_IOV_CFG_REG9__RESERVED__SHIFT 0xc
9419#define RLC_GPU_IOV_CFG_REG10__TIME_QUANTA_PF_MASK 0xffff
9420#define RLC_GPU_IOV_CFG_REG10__TIME_QUANTA_PF__SHIFT 0x0
9421#define RLC_GPU_IOV_CFG_REG10__RESERVED_MASK 0xffff0000
9422#define RLC_GPU_IOV_CFG_REG10__RESERVED__SHIFT 0x10
9423#define RLC_GPU_IOV_CFG_REG11__YIELD_MASK 0xffffffff
9424#define RLC_GPU_IOV_CFG_REG11__YIELD__SHIFT 0x0
9425#define RLC_GPU_IOV_CFG_REG12__TIME_QUANTA_VF0_MASK 0xff
9426#define RLC_GPU_IOV_CFG_REG12__TIME_QUANTA_VF0__SHIFT 0x0
9427#define RLC_GPU_IOV_CFG_REG12__TIME_QUANTA_VF1_MASK 0xff00
9428#define RLC_GPU_IOV_CFG_REG12__TIME_QUANTA_VF1__SHIFT 0x8
9429#define RLC_GPU_IOV_CFG_REG12__TIME_QUANTA_VF2_MASK 0xff0000
9430#define RLC_GPU_IOV_CFG_REG12__TIME_QUANTA_VF2__SHIFT 0x10
9431#define RLC_GPU_IOV_CFG_REG12__TIME_QUANTA_VF3_MASK 0xff000000
9432#define RLC_GPU_IOV_CFG_REG12__TIME_QUANTA_VF3__SHIFT 0x18
9433#define RLC_GPU_IOV_CFG_REG13__TIME_QUANTA_VF4_MASK 0xff
9434#define RLC_GPU_IOV_CFG_REG13__TIME_QUANTA_VF4__SHIFT 0x0
9435#define RLC_GPU_IOV_CFG_REG13__TIME_QUANTA_VF5_MASK 0xff00
9436#define RLC_GPU_IOV_CFG_REG13__TIME_QUANTA_VF5__SHIFT 0x8
9437#define RLC_GPU_IOV_CFG_REG13__TIME_QUANTA_VF6_MASK 0xff0000
9438#define RLC_GPU_IOV_CFG_REG13__TIME_QUANTA_VF6__SHIFT 0x10
9439#define RLC_GPU_IOV_CFG_REG13__TIME_QUANTA_VF7_MASK 0xff000000
9440#define RLC_GPU_IOV_CFG_REG13__TIME_QUANTA_VF7__SHIFT 0x18
9441#define RLC_GPU_IOV_CFG_REG14__TIME_QUANTA_VF8_MASK 0xff
9442#define RLC_GPU_IOV_CFG_REG14__TIME_QUANTA_VF8__SHIFT 0x0
9443#define RLC_GPU_IOV_CFG_REG14__TIME_QUANTA_VF9_MASK 0xff00
9444#define RLC_GPU_IOV_CFG_REG14__TIME_QUANTA_VF9__SHIFT 0x8
9445#define RLC_GPU_IOV_CFG_REG14__TIME_QUANTA_VF10_MASK 0xff0000
9446#define RLC_GPU_IOV_CFG_REG14__TIME_QUANTA_VF10__SHIFT 0x10
9447#define RLC_GPU_IOV_CFG_REG14__TIME_QUANTA_VF11_MASK 0xff000000
9448#define RLC_GPU_IOV_CFG_REG14__TIME_QUANTA_VF11__SHIFT 0x18
9449#define RLC_GPU_IOV_CFG_REG15__TIME_QUANTA_VF12_MASK 0xff
9450#define RLC_GPU_IOV_CFG_REG15__TIME_QUANTA_VF12__SHIFT 0x0
9451#define RLC_GPU_IOV_CFG_REG15__TIME_QUANTA_VF13_MASK 0xff00
9452#define RLC_GPU_IOV_CFG_REG15__TIME_QUANTA_VF13__SHIFT 0x8
9453#define RLC_GPU_IOV_CFG_REG15__TIME_QUANTA_VF14_MASK 0xff0000
9454#define RLC_GPU_IOV_CFG_REG15__TIME_QUANTA_VF14__SHIFT 0x10
9455#define RLC_GPU_IOV_CFG_REG15__TIME_QUANTA_VF15_MASK 0xff000000
9456#define RLC_GPU_IOV_CFG_REG15__TIME_QUANTA_VF15__SHIFT 0x18
9457#define RLC_GPU_IOV_ACTIVE_FCN_ID__VF_ID_MASK 0xf
9458#define RLC_GPU_IOV_ACTIVE_FCN_ID__VF_ID__SHIFT 0x0
9459#define RLC_GPU_IOV_ACTIVE_FCN_ID__RESERVED_MASK 0x7ffffff0
9460#define RLC_GPU_IOV_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4
9461#define RLC_GPU_IOV_ACTIVE_FCN_ID__PF_VF_MASK 0x80000000
9462#define RLC_GPU_IOV_ACTIVE_FCN_ID__PF_VF__SHIFT 0x1f
9463#define RLC_GPM_VMID_THREAD2__RLC_VMID_MASK 0xf
9464#define RLC_GPM_VMID_THREAD2__RLC_VMID__SHIFT 0x0
9465#define RLC_GPM_VMID_THREAD2__RESERVED0_MASK 0xf0
9466#define RLC_GPM_VMID_THREAD2__RESERVED0__SHIFT 0x4
9467#define RLC_GPM_VMID_THREAD2__RLC_QUEUEID_MASK 0x700
9468#define RLC_GPM_VMID_THREAD2__RLC_QUEUEID__SHIFT 0x8
9469#define RLC_GPM_VMID_THREAD2__RESERVED1_MASK 0xfffff800
9470#define RLC_GPM_VMID_THREAD2__RESERVED1__SHIFT 0xb
9471#define RLC_GPU_IOV_UCODE_ADDR__UCODE_ADDR_MASK 0xfff
9472#define RLC_GPU_IOV_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
9473#define RLC_GPU_IOV_UCODE_ADDR__RESERVED_MASK 0xfffff000
9474#define RLC_GPU_IOV_UCODE_ADDR__RESERVED__SHIFT 0xc
9475#define RLC_GPU_IOV_UCODE_DATA__UCODE_DATA_MASK 0xffffffff
9476#define RLC_GPU_IOV_UCODE_DATA__UCODE_DATA__SHIFT 0x0
9477#define RLC_GPU_IOV_SCRATCH_ADDR__ADDR_MASK 0x1ff
9478#define RLC_GPU_IOV_SCRATCH_ADDR__ADDR__SHIFT 0x0
9479#define RLC_GPU_IOV_SCRATCH_ADDR__RESERVED_MASK 0xfffffe00
9480#define RLC_GPU_IOV_SCRATCH_ADDR__RESERVED__SHIFT 0x9
9481#define RLC_GPU_IOV_SCRATCH_DATA__DATA_MASK 0xffffffff
9482#define RLC_GPU_IOV_SCRATCH_DATA__DATA__SHIFT 0x0
9483#define RLC_GPU_IOV_F32_CNTL__ENABLE_MASK 0x1
9484#define RLC_GPU_IOV_F32_CNTL__ENABLE__SHIFT 0x0
9485#define RLC_GPU_IOV_F32_CNTL__RESERVED_MASK 0xfffffffe
9486#define RLC_GPU_IOV_F32_CNTL__RESERVED__SHIFT 0x1
9487#define RLC_GPU_IOV_F32_RESET__RESET_MASK 0x1
9488#define RLC_GPU_IOV_F32_RESET__RESET__SHIFT 0x0
9489#define RLC_GPU_IOV_F32_RESET__RESERVED_MASK 0xfffffffe
9490#define RLC_GPU_IOV_F32_RESET__RESERVED__SHIFT 0x1
9491#define RLC_GPU_IOV_SDMA0_STATUS__PREEMPTED_MASK 0x1
9492#define RLC_GPU_IOV_SDMA0_STATUS__PREEMPTED__SHIFT 0x0
9493#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED_MASK 0xfe
9494#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED__SHIFT 0x1
9495#define RLC_GPU_IOV_SDMA0_STATUS__SAVED_MASK 0x100
9496#define RLC_GPU_IOV_SDMA0_STATUS__SAVED__SHIFT 0x8
9497#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED1_MASK 0xe00
9498#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED1__SHIFT 0x9
9499#define RLC_GPU_IOV_SDMA0_STATUS__RESTORED_MASK 0x1000
9500#define RLC_GPU_IOV_SDMA0_STATUS__RESTORED__SHIFT 0xc
9501#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED2_MASK 0xffffe000
9502#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED2__SHIFT 0xd
9503#define RLC_GPU_IOV_SDMA1_STATUS__PREEMPTED_MASK 0x1
9504#define RLC_GPU_IOV_SDMA1_STATUS__PREEMPTED__SHIFT 0x0
9505#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED_MASK 0xfe
9506#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED__SHIFT 0x1
9507#define RLC_GPU_IOV_SDMA1_STATUS__SAVED_MASK 0x100
9508#define RLC_GPU_IOV_SDMA1_STATUS__SAVED__SHIFT 0x8
9509#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED1_MASK 0xe00
9510#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED1__SHIFT 0x9
9511#define RLC_GPU_IOV_SDMA1_STATUS__RESTORED_MASK 0x1000
9512#define RLC_GPU_IOV_SDMA1_STATUS__RESTORED__SHIFT 0xc
9513#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED2_MASK 0xffffe000
9514#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED2__SHIFT 0xd
9515#define RLC_GPU_IOV_SMU_RESPONSE__RESP_MASK 0xffffffff
9516#define RLC_GPU_IOV_SMU_RESPONSE__RESP__SHIFT 0x0
9517#define RLC_GPU_IOV_VIRT_RESET_REQ__VF_FLR_MASK 0xffff
9518#define RLC_GPU_IOV_VIRT_RESET_REQ__VF_FLR__SHIFT 0x0
9519#define RLC_GPU_IOV_VIRT_RESET_REQ__RESERVED_MASK 0x7fff0000
9520#define RLC_GPU_IOV_VIRT_RESET_REQ__RESERVED__SHIFT 0x10
9521#define RLC_GPU_IOV_VIRT_RESET_REQ__SOFT_PF_FLR_MASK 0x80000000
9522#define RLC_GPU_IOV_VIRT_RESET_REQ__SOFT_PF_FLR__SHIFT 0x1f
9523#define RLC_GPU_IOV_RLC_RESPONSE__RESP_MASK 0xffffffff
9524#define RLC_GPU_IOV_RLC_RESPONSE__RESP__SHIFT 0x0
9525#define RLC_GPU_IOV_INT_DISABLE__DISABLE_MASK 0xffffffff
9526#define RLC_GPU_IOV_INT_DISABLE__DISABLE__SHIFT 0x0
9527#define RLC_GPU_IOV_INT_FORCE__FORCE_MASK 0xffffffff
9528#define RLC_GPU_IOV_INT_FORCE__FORCE__SHIFT 0x0
9529#define RLC_GPU_IOV_SDMA0_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xffffffff
9530#define RLC_GPU_IOV_SDMA0_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0
9531#define RLC_GPU_IOV_SDMA1_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xffffffff
9532#define RLC_GPU_IOV_SDMA1_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0
9533#define RLC_GPU_IOV_SCH_0__DATA_MASK 0xffffffff
9534#define RLC_GPU_IOV_SCH_0__DATA__SHIFT 0x0
9535#define RLC_GPU_IOV_SCH_1__DATA_MASK 0xffffffff
9536#define RLC_GPU_IOV_SCH_1__DATA__SHIFT 0x0
9537#define RLC_GPU_IOV_SCH_2__DATA_MASK 0xffffffff
9538#define RLC_GPU_IOV_SCH_2__DATA__SHIFT 0x0
9539#define RLC_GPU_IOV_SCH_3__DATA_MASK 0xffffffff
9540#define RLC_GPU_IOV_SCH_3__DATA__SHIFT 0x0
9541#define RLC_GPU_IOV_SCH_INT__interrupt_MASK 0xffffffff
9542#define RLC_GPU_IOV_SCH_INT__interrupt__SHIFT 0x0
9543#define SPI_PS_INPUT_CNTL_0__OFFSET_MASK 0x3f
9544#define SPI_PS_INPUT_CNTL_0__OFFSET__SHIFT 0x0
9545#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_MASK 0x300
9546#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL__SHIFT 0x8
9547#define SPI_PS_INPUT_CNTL_0__FLAT_SHADE_MASK 0x400
9548#define SPI_PS_INPUT_CNTL_0__FLAT_SHADE__SHIFT 0xa
9549#define SPI_PS_INPUT_CNTL_0__CYL_WRAP_MASK 0x1e000
9550#define SPI_PS_INPUT_CNTL_0__CYL_WRAP__SHIFT 0xd
9551#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_MASK 0x20000
9552#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX__SHIFT 0x11
9553#define SPI_PS_INPUT_CNTL_0__DUP_MASK 0x40000
9554#define SPI_PS_INPUT_CNTL_0__DUP__SHIFT 0x12
9555#define SPI_PS_INPUT_CNTL_0__FP16_INTERP_MODE_MASK 0x80000
9556#define SPI_PS_INPUT_CNTL_0__FP16_INTERP_MODE__SHIFT 0x13
9557#define SPI_PS_INPUT_CNTL_0__USE_DEFAULT_ATTR1_MASK 0x100000
9558#define SPI_PS_INPUT_CNTL_0__USE_DEFAULT_ATTR1__SHIFT 0x14
9559#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_ATTR1_MASK 0x600000
9560#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_ATTR1__SHIFT 0x15
9561#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_ATTR1_MASK 0x800000
9562#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
9563#define SPI_PS_INPUT_CNTL_0__ATTR0_VALID_MASK 0x1000000
9564#define SPI_PS_INPUT_CNTL_0__ATTR0_VALID__SHIFT 0x18
9565#define SPI_PS_INPUT_CNTL_0__ATTR1_VALID_MASK 0x2000000
9566#define SPI_PS_INPUT_CNTL_0__ATTR1_VALID__SHIFT 0x19
9567#define SPI_PS_INPUT_CNTL_1__OFFSET_MASK 0x3f
9568#define SPI_PS_INPUT_CNTL_1__OFFSET__SHIFT 0x0
9569#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_MASK 0x300
9570#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL__SHIFT 0x8
9571#define SPI_PS_INPUT_CNTL_1__FLAT_SHADE_MASK 0x400
9572#define SPI_PS_INPUT_CNTL_1__FLAT_SHADE__SHIFT 0xa
9573#define SPI_PS_INPUT_CNTL_1__CYL_WRAP_MASK 0x1e000
9574#define SPI_PS_INPUT_CNTL_1__CYL_WRAP__SHIFT 0xd
9575#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_MASK 0x20000
9576#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX__SHIFT 0x11
9577#define SPI_PS_INPUT_CNTL_1__DUP_MASK 0x40000
9578#define SPI_PS_INPUT_CNTL_1__DUP__SHIFT 0x12
9579#define SPI_PS_INPUT_CNTL_1__FP16_INTERP_MODE_MASK 0x80000
9580#define SPI_PS_INPUT_CNTL_1__FP16_INTERP_MODE__SHIFT 0x13
9581#define SPI_PS_INPUT_CNTL_1__USE_DEFAULT_ATTR1_MASK 0x100000
9582#define SPI_PS_INPUT_CNTL_1__USE_DEFAULT_ATTR1__SHIFT 0x14
9583#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_ATTR1_MASK 0x600000
9584#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_ATTR1__SHIFT 0x15
9585#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_ATTR1_MASK 0x800000
9586#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
9587#define SPI_PS_INPUT_CNTL_1__ATTR0_VALID_MASK 0x1000000
9588#define SPI_PS_INPUT_CNTL_1__ATTR0_VALID__SHIFT 0x18
9589#define SPI_PS_INPUT_CNTL_1__ATTR1_VALID_MASK 0x2000000
9590#define SPI_PS_INPUT_CNTL_1__ATTR1_VALID__SHIFT 0x19
9591#define SPI_PS_INPUT_CNTL_2__OFFSET_MASK 0x3f
9592#define SPI_PS_INPUT_CNTL_2__OFFSET__SHIFT 0x0
9593#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_MASK 0x300
9594#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL__SHIFT 0x8
9595#define SPI_PS_INPUT_CNTL_2__FLAT_SHADE_MASK 0x400
9596#define SPI_PS_INPUT_CNTL_2__FLAT_SHADE__SHIFT 0xa
9597#define SPI_PS_INPUT_CNTL_2__CYL_WRAP_MASK 0x1e000
9598#define SPI_PS_INPUT_CNTL_2__CYL_WRAP__SHIFT 0xd
9599#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_MASK 0x20000
9600#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX__SHIFT 0x11
9601#define SPI_PS_INPUT_CNTL_2__DUP_MASK 0x40000
9602#define SPI_PS_INPUT_CNTL_2__DUP__SHIFT 0x12
9603#define SPI_PS_INPUT_CNTL_2__FP16_INTERP_MODE_MASK 0x80000
9604#define SPI_PS_INPUT_CNTL_2__FP16_INTERP_MODE__SHIFT 0x13
9605#define SPI_PS_INPUT_CNTL_2__USE_DEFAULT_ATTR1_MASK 0x100000
9606#define SPI_PS_INPUT_CNTL_2__USE_DEFAULT_ATTR1__SHIFT 0x14
9607#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_ATTR1_MASK 0x600000
9608#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_ATTR1__SHIFT 0x15
9609#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_ATTR1_MASK 0x800000
9610#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
9611#define SPI_PS_INPUT_CNTL_2__ATTR0_VALID_MASK 0x1000000
9612#define SPI_PS_INPUT_CNTL_2__ATTR0_VALID__SHIFT 0x18
9613#define SPI_PS_INPUT_CNTL_2__ATTR1_VALID_MASK 0x2000000
9614#define SPI_PS_INPUT_CNTL_2__ATTR1_VALID__SHIFT 0x19
9615#define SPI_PS_INPUT_CNTL_3__OFFSET_MASK 0x3f
9616#define SPI_PS_INPUT_CNTL_3__OFFSET__SHIFT 0x0
9617#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_MASK 0x300
9618#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL__SHIFT 0x8
9619#define SPI_PS_INPUT_CNTL_3__FLAT_SHADE_MASK 0x400
9620#define SPI_PS_INPUT_CNTL_3__FLAT_SHADE__SHIFT 0xa
9621#define SPI_PS_INPUT_CNTL_3__CYL_WRAP_MASK 0x1e000
9622#define SPI_PS_INPUT_CNTL_3__CYL_WRAP__SHIFT 0xd
9623#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_MASK 0x20000
9624#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX__SHIFT 0x11
9625#define SPI_PS_INPUT_CNTL_3__DUP_MASK 0x40000
9626#define SPI_PS_INPUT_CNTL_3__DUP__SHIFT 0x12
9627#define SPI_PS_INPUT_CNTL_3__FP16_INTERP_MODE_MASK 0x80000
9628#define SPI_PS_INPUT_CNTL_3__FP16_INTERP_MODE__SHIFT 0x13
9629#define SPI_PS_INPUT_CNTL_3__USE_DEFAULT_ATTR1_MASK 0x100000
9630#define SPI_PS_INPUT_CNTL_3__USE_DEFAULT_ATTR1__SHIFT 0x14
9631#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_ATTR1_MASK 0x600000
9632#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_ATTR1__SHIFT 0x15
9633#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_ATTR1_MASK 0x800000
9634#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
9635#define SPI_PS_INPUT_CNTL_3__ATTR0_VALID_MASK 0x1000000
9636#define SPI_PS_INPUT_CNTL_3__ATTR0_VALID__SHIFT 0x18
9637#define SPI_PS_INPUT_CNTL_3__ATTR1_VALID_MASK 0x2000000
9638#define SPI_PS_INPUT_CNTL_3__ATTR1_VALID__SHIFT 0x19
9639#define SPI_PS_INPUT_CNTL_4__OFFSET_MASK 0x3f
9640#define SPI_PS_INPUT_CNTL_4__OFFSET__SHIFT 0x0
9641#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_MASK 0x300
9642#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL__SHIFT 0x8
9643#define SPI_PS_INPUT_CNTL_4__FLAT_SHADE_MASK 0x400
9644#define SPI_PS_INPUT_CNTL_4__FLAT_SHADE__SHIFT 0xa
9645#define SPI_PS_INPUT_CNTL_4__CYL_WRAP_MASK 0x1e000
9646#define SPI_PS_INPUT_CNTL_4__CYL_WRAP__SHIFT 0xd
9647#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_MASK 0x20000
9648#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX__SHIFT 0x11
9649#define SPI_PS_INPUT_CNTL_4__DUP_MASK 0x40000
9650#define SPI_PS_INPUT_CNTL_4__DUP__SHIFT 0x12
9651#define SPI_PS_INPUT_CNTL_4__FP16_INTERP_MODE_MASK 0x80000
9652#define SPI_PS_INPUT_CNTL_4__FP16_INTERP_MODE__SHIFT 0x13
9653#define SPI_PS_INPUT_CNTL_4__USE_DEFAULT_ATTR1_MASK 0x100000
9654#define SPI_PS_INPUT_CNTL_4__USE_DEFAULT_ATTR1__SHIFT 0x14
9655#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_ATTR1_MASK 0x600000
9656#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_ATTR1__SHIFT 0x15
9657#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_ATTR1_MASK 0x800000
9658#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
9659#define SPI_PS_INPUT_CNTL_4__ATTR0_VALID_MASK 0x1000000
9660#define SPI_PS_INPUT_CNTL_4__ATTR0_VALID__SHIFT 0x18
9661#define SPI_PS_INPUT_CNTL_4__ATTR1_VALID_MASK 0x2000000
9662#define SPI_PS_INPUT_CNTL_4__ATTR1_VALID__SHIFT 0x19
9663#define SPI_PS_INPUT_CNTL_5__OFFSET_MASK 0x3f
9664#define SPI_PS_INPUT_CNTL_5__OFFSET__SHIFT 0x0
9665#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_MASK 0x300
9666#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL__SHIFT 0x8
9667#define SPI_PS_INPUT_CNTL_5__FLAT_SHADE_MASK 0x400
9668#define SPI_PS_INPUT_CNTL_5__FLAT_SHADE__SHIFT 0xa
9669#define SPI_PS_INPUT_CNTL_5__CYL_WRAP_MASK 0x1e000
9670#define SPI_PS_INPUT_CNTL_5__CYL_WRAP__SHIFT 0xd
9671#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_MASK 0x20000
9672#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX__SHIFT 0x11
9673#define SPI_PS_INPUT_CNTL_5__DUP_MASK 0x40000
9674#define SPI_PS_INPUT_CNTL_5__DUP__SHIFT 0x12
9675#define SPI_PS_INPUT_CNTL_5__FP16_INTERP_MODE_MASK 0x80000
9676#define SPI_PS_INPUT_CNTL_5__FP16_INTERP_MODE__SHIFT 0x13
9677#define SPI_PS_INPUT_CNTL_5__USE_DEFAULT_ATTR1_MASK 0x100000
9678#define SPI_PS_INPUT_CNTL_5__USE_DEFAULT_ATTR1__SHIFT 0x14
9679#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_ATTR1_MASK 0x600000
9680#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_ATTR1__SHIFT 0x15
9681#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_ATTR1_MASK 0x800000
9682#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
9683#define SPI_PS_INPUT_CNTL_5__ATTR0_VALID_MASK 0x1000000
9684#define SPI_PS_INPUT_CNTL_5__ATTR0_VALID__SHIFT 0x18
9685#define SPI_PS_INPUT_CNTL_5__ATTR1_VALID_MASK 0x2000000
9686#define SPI_PS_INPUT_CNTL_5__ATTR1_VALID__SHIFT 0x19
9687#define SPI_PS_INPUT_CNTL_6__OFFSET_MASK 0x3f
9688#define SPI_PS_INPUT_CNTL_6__OFFSET__SHIFT 0x0
9689#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_MASK 0x300
9690#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL__SHIFT 0x8
9691#define SPI_PS_INPUT_CNTL_6__FLAT_SHADE_MASK 0x400
9692#define SPI_PS_INPUT_CNTL_6__FLAT_SHADE__SHIFT 0xa
9693#define SPI_PS_INPUT_CNTL_6__CYL_WRAP_MASK 0x1e000
9694#define SPI_PS_INPUT_CNTL_6__CYL_WRAP__SHIFT 0xd
9695#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_MASK 0x20000
9696#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX__SHIFT 0x11
9697#define SPI_PS_INPUT_CNTL_6__DUP_MASK 0x40000
9698#define SPI_PS_INPUT_CNTL_6__DUP__SHIFT 0x12
9699#define SPI_PS_INPUT_CNTL_6__FP16_INTERP_MODE_MASK 0x80000
9700#define SPI_PS_INPUT_CNTL_6__FP16_INTERP_MODE__SHIFT 0x13
9701#define SPI_PS_INPUT_CNTL_6__USE_DEFAULT_ATTR1_MASK 0x100000
9702#define SPI_PS_INPUT_CNTL_6__USE_DEFAULT_ATTR1__SHIFT 0x14
9703#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_ATTR1_MASK 0x600000
9704#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_ATTR1__SHIFT 0x15
9705#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_ATTR1_MASK 0x800000
9706#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
9707#define SPI_PS_INPUT_CNTL_6__ATTR0_VALID_MASK 0x1000000
9708#define SPI_PS_INPUT_CNTL_6__ATTR0_VALID__SHIFT 0x18
9709#define SPI_PS_INPUT_CNTL_6__ATTR1_VALID_MASK 0x2000000
9710#define SPI_PS_INPUT_CNTL_6__ATTR1_VALID__SHIFT 0x19
9711#define SPI_PS_INPUT_CNTL_7__OFFSET_MASK 0x3f
9712#define SPI_PS_INPUT_CNTL_7__OFFSET__SHIFT 0x0
9713#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_MASK 0x300
9714#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL__SHIFT 0x8
9715#define SPI_PS_INPUT_CNTL_7__FLAT_SHADE_MASK 0x400
9716#define SPI_PS_INPUT_CNTL_7__FLAT_SHADE__SHIFT 0xa
9717#define SPI_PS_INPUT_CNTL_7__CYL_WRAP_MASK 0x1e000
9718#define SPI_PS_INPUT_CNTL_7__CYL_WRAP__SHIFT 0xd
9719#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_MASK 0x20000
9720#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX__SHIFT 0x11
9721#define SPI_PS_INPUT_CNTL_7__DUP_MASK 0x40000
9722#define SPI_PS_INPUT_CNTL_7__DUP__SHIFT 0x12
9723#define SPI_PS_INPUT_CNTL_7__FP16_INTERP_MODE_MASK 0x80000
9724#define SPI_PS_INPUT_CNTL_7__FP16_INTERP_MODE__SHIFT 0x13
9725#define SPI_PS_INPUT_CNTL_7__USE_DEFAULT_ATTR1_MASK 0x100000
9726#define SPI_PS_INPUT_CNTL_7__USE_DEFAULT_ATTR1__SHIFT 0x14
9727#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_ATTR1_MASK 0x600000
9728#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_ATTR1__SHIFT 0x15
9729#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_ATTR1_MASK 0x800000
9730#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
9731#define SPI_PS_INPUT_CNTL_7__ATTR0_VALID_MASK 0x1000000
9732#define SPI_PS_INPUT_CNTL_7__ATTR0_VALID__SHIFT 0x18
9733#define SPI_PS_INPUT_CNTL_7__ATTR1_VALID_MASK 0x2000000
9734#define SPI_PS_INPUT_CNTL_7__ATTR1_VALID__SHIFT 0x19
9735#define SPI_PS_INPUT_CNTL_8__OFFSET_MASK 0x3f
9736#define SPI_PS_INPUT_CNTL_8__OFFSET__SHIFT 0x0
9737#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_MASK 0x300
9738#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL__SHIFT 0x8
9739#define SPI_PS_INPUT_CNTL_8__FLAT_SHADE_MASK 0x400
9740#define SPI_PS_INPUT_CNTL_8__FLAT_SHADE__SHIFT 0xa
9741#define SPI_PS_INPUT_CNTL_8__CYL_WRAP_MASK 0x1e000
9742#define SPI_PS_INPUT_CNTL_8__CYL_WRAP__SHIFT 0xd
9743#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_MASK 0x20000
9744#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX__SHIFT 0x11
9745#define SPI_PS_INPUT_CNTL_8__DUP_MASK 0x40000
9746#define SPI_PS_INPUT_CNTL_8__DUP__SHIFT 0x12
9747#define SPI_PS_INPUT_CNTL_8__FP16_INTERP_MODE_MASK 0x80000
9748#define SPI_PS_INPUT_CNTL_8__FP16_INTERP_MODE__SHIFT 0x13
9749#define SPI_PS_INPUT_CNTL_8__USE_DEFAULT_ATTR1_MASK 0x100000
9750#define SPI_PS_INPUT_CNTL_8__USE_DEFAULT_ATTR1__SHIFT 0x14
9751#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_ATTR1_MASK 0x600000
9752#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_ATTR1__SHIFT 0x15
9753#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_ATTR1_MASK 0x800000
9754#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
9755#define SPI_PS_INPUT_CNTL_8__ATTR0_VALID_MASK 0x1000000
9756#define SPI_PS_INPUT_CNTL_8__ATTR0_VALID__SHIFT 0x18
9757#define SPI_PS_INPUT_CNTL_8__ATTR1_VALID_MASK 0x2000000
9758#define SPI_PS_INPUT_CNTL_8__ATTR1_VALID__SHIFT 0x19
9759#define SPI_PS_INPUT_CNTL_9__OFFSET_MASK 0x3f
9760#define SPI_PS_INPUT_CNTL_9__OFFSET__SHIFT 0x0
9761#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_MASK 0x300
9762#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL__SHIFT 0x8
9763#define SPI_PS_INPUT_CNTL_9__FLAT_SHADE_MASK 0x400
9764#define SPI_PS_INPUT_CNTL_9__FLAT_SHADE__SHIFT 0xa
9765#define SPI_PS_INPUT_CNTL_9__CYL_WRAP_MASK 0x1e000
9766#define SPI_PS_INPUT_CNTL_9__CYL_WRAP__SHIFT 0xd
9767#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_MASK 0x20000
9768#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX__SHIFT 0x11
9769#define SPI_PS_INPUT_CNTL_9__DUP_MASK 0x40000
9770#define SPI_PS_INPUT_CNTL_9__DUP__SHIFT 0x12
9771#define SPI_PS_INPUT_CNTL_9__FP16_INTERP_MODE_MASK 0x80000
9772#define SPI_PS_INPUT_CNTL_9__FP16_INTERP_MODE__SHIFT 0x13
9773#define SPI_PS_INPUT_CNTL_9__USE_DEFAULT_ATTR1_MASK 0x100000
9774#define SPI_PS_INPUT_CNTL_9__USE_DEFAULT_ATTR1__SHIFT 0x14
9775#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_ATTR1_MASK 0x600000
9776#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_ATTR1__SHIFT 0x15
9777#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_ATTR1_MASK 0x800000
9778#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
9779#define SPI_PS_INPUT_CNTL_9__ATTR0_VALID_MASK 0x1000000
9780#define SPI_PS_INPUT_CNTL_9__ATTR0_VALID__SHIFT 0x18
9781#define SPI_PS_INPUT_CNTL_9__ATTR1_VALID_MASK 0x2000000
9782#define SPI_PS_INPUT_CNTL_9__ATTR1_VALID__SHIFT 0x19
9783#define SPI_PS_INPUT_CNTL_10__OFFSET_MASK 0x3f
9784#define SPI_PS_INPUT_CNTL_10__OFFSET__SHIFT 0x0
9785#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_MASK 0x300
9786#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL__SHIFT 0x8
9787#define SPI_PS_INPUT_CNTL_10__FLAT_SHADE_MASK 0x400
9788#define SPI_PS_INPUT_CNTL_10__FLAT_SHADE__SHIFT 0xa
9789#define SPI_PS_INPUT_CNTL_10__CYL_WRAP_MASK 0x1e000
9790#define SPI_PS_INPUT_CNTL_10__CYL_WRAP__SHIFT 0xd
9791#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_MASK 0x20000
9792#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX__SHIFT 0x11
9793#define SPI_PS_INPUT_CNTL_10__DUP_MASK 0x40000
9794#define SPI_PS_INPUT_CNTL_10__DUP__SHIFT 0x12
9795#define SPI_PS_INPUT_CNTL_10__FP16_INTERP_MODE_MASK 0x80000
9796#define SPI_PS_INPUT_CNTL_10__FP16_INTERP_MODE__SHIFT 0x13
9797#define SPI_PS_INPUT_CNTL_10__USE_DEFAULT_ATTR1_MASK 0x100000
9798#define SPI_PS_INPUT_CNTL_10__USE_DEFAULT_ATTR1__SHIFT 0x14
9799#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_ATTR1_MASK 0x600000
9800#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_ATTR1__SHIFT 0x15
9801#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_ATTR1_MASK 0x800000
9802#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
9803#define SPI_PS_INPUT_CNTL_10__ATTR0_VALID_MASK 0x1000000
9804#define SPI_PS_INPUT_CNTL_10__ATTR0_VALID__SHIFT 0x18
9805#define SPI_PS_INPUT_CNTL_10__ATTR1_VALID_MASK 0x2000000
9806#define SPI_PS_INPUT_CNTL_10__ATTR1_VALID__SHIFT 0x19
9807#define SPI_PS_INPUT_CNTL_11__OFFSET_MASK 0x3f
9808#define SPI_PS_INPUT_CNTL_11__OFFSET__SHIFT 0x0
9809#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_MASK 0x300
9810#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL__SHIFT 0x8
9811#define SPI_PS_INPUT_CNTL_11__FLAT_SHADE_MASK 0x400
9812#define SPI_PS_INPUT_CNTL_11__FLAT_SHADE__SHIFT 0xa
9813#define SPI_PS_INPUT_CNTL_11__CYL_WRAP_MASK 0x1e000
9814#define SPI_PS_INPUT_CNTL_11__CYL_WRAP__SHIFT 0xd
9815#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_MASK 0x20000
9816#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX__SHIFT 0x11
9817#define SPI_PS_INPUT_CNTL_11__DUP_MASK 0x40000
9818#define SPI_PS_INPUT_CNTL_11__DUP__SHIFT 0x12
9819#define SPI_PS_INPUT_CNTL_11__FP16_INTERP_MODE_MASK 0x80000
9820#define SPI_PS_INPUT_CNTL_11__FP16_INTERP_MODE__SHIFT 0x13
9821#define SPI_PS_INPUT_CNTL_11__USE_DEFAULT_ATTR1_MASK 0x100000
9822#define SPI_PS_INPUT_CNTL_11__USE_DEFAULT_ATTR1__SHIFT 0x14
9823#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_ATTR1_MASK 0x600000
9824#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_ATTR1__SHIFT 0x15
9825#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_ATTR1_MASK 0x800000
9826#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
9827#define SPI_PS_INPUT_CNTL_11__ATTR0_VALID_MASK 0x1000000
9828#define SPI_PS_INPUT_CNTL_11__ATTR0_VALID__SHIFT 0x18
9829#define SPI_PS_INPUT_CNTL_11__ATTR1_VALID_MASK 0x2000000
9830#define SPI_PS_INPUT_CNTL_11__ATTR1_VALID__SHIFT 0x19
9831#define SPI_PS_INPUT_CNTL_12__OFFSET_MASK 0x3f
9832#define SPI_PS_INPUT_CNTL_12__OFFSET__SHIFT 0x0
9833#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_MASK 0x300
9834#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL__SHIFT 0x8
9835#define SPI_PS_INPUT_CNTL_12__FLAT_SHADE_MASK 0x400
9836#define SPI_PS_INPUT_CNTL_12__FLAT_SHADE__SHIFT 0xa
9837#define SPI_PS_INPUT_CNTL_12__CYL_WRAP_MASK 0x1e000
9838#define SPI_PS_INPUT_CNTL_12__CYL_WRAP__SHIFT 0xd
9839#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_MASK 0x20000
9840#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX__SHIFT 0x11
9841#define SPI_PS_INPUT_CNTL_12__DUP_MASK 0x40000
9842#define SPI_PS_INPUT_CNTL_12__DUP__SHIFT 0x12
9843#define SPI_PS_INPUT_CNTL_12__FP16_INTERP_MODE_MASK 0x80000
9844#define SPI_PS_INPUT_CNTL_12__FP16_INTERP_MODE__SHIFT 0x13
9845#define SPI_PS_INPUT_CNTL_12__USE_DEFAULT_ATTR1_MASK 0x100000
9846#define SPI_PS_INPUT_CNTL_12__USE_DEFAULT_ATTR1__SHIFT 0x14
9847#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_ATTR1_MASK 0x600000
9848#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_ATTR1__SHIFT 0x15
9849#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_ATTR1_MASK 0x800000
9850#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
9851#define SPI_PS_INPUT_CNTL_12__ATTR0_VALID_MASK 0x1000000
9852#define SPI_PS_INPUT_CNTL_12__ATTR0_VALID__SHIFT 0x18
9853#define SPI_PS_INPUT_CNTL_12__ATTR1_VALID_MASK 0x2000000
9854#define SPI_PS_INPUT_CNTL_12__ATTR1_VALID__SHIFT 0x19
9855#define SPI_PS_INPUT_CNTL_13__OFFSET_MASK 0x3f
9856#define SPI_PS_INPUT_CNTL_13__OFFSET__SHIFT 0x0
9857#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_MASK 0x300
9858#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL__SHIFT 0x8
9859#define SPI_PS_INPUT_CNTL_13__FLAT_SHADE_MASK 0x400
9860#define SPI_PS_INPUT_CNTL_13__FLAT_SHADE__SHIFT 0xa
9861#define SPI_PS_INPUT_CNTL_13__CYL_WRAP_MASK 0x1e000
9862#define SPI_PS_INPUT_CNTL_13__CYL_WRAP__SHIFT 0xd
9863#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_MASK 0x20000
9864#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX__SHIFT 0x11
9865#define SPI_PS_INPUT_CNTL_13__DUP_MASK 0x40000
9866#define SPI_PS_INPUT_CNTL_13__DUP__SHIFT 0x12
9867#define SPI_PS_INPUT_CNTL_13__FP16_INTERP_MODE_MASK 0x80000
9868#define SPI_PS_INPUT_CNTL_13__FP16_INTERP_MODE__SHIFT 0x13
9869#define SPI_PS_INPUT_CNTL_13__USE_DEFAULT_ATTR1_MASK 0x100000
9870#define SPI_PS_INPUT_CNTL_13__USE_DEFAULT_ATTR1__SHIFT 0x14
9871#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_ATTR1_MASK 0x600000
9872#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_ATTR1__SHIFT 0x15
9873#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_ATTR1_MASK 0x800000
9874#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
9875#define SPI_PS_INPUT_CNTL_13__ATTR0_VALID_MASK 0x1000000
9876#define SPI_PS_INPUT_CNTL_13__ATTR0_VALID__SHIFT 0x18
9877#define SPI_PS_INPUT_CNTL_13__ATTR1_VALID_MASK 0x2000000
9878#define SPI_PS_INPUT_CNTL_13__ATTR1_VALID__SHIFT 0x19
9879#define SPI_PS_INPUT_CNTL_14__OFFSET_MASK 0x3f
9880#define SPI_PS_INPUT_CNTL_14__OFFSET__SHIFT 0x0
9881#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_MASK 0x300
9882#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL__SHIFT 0x8
9883#define SPI_PS_INPUT_CNTL_14__FLAT_SHADE_MASK 0x400
9884#define SPI_PS_INPUT_CNTL_14__FLAT_SHADE__SHIFT 0xa
9885#define SPI_PS_INPUT_CNTL_14__CYL_WRAP_MASK 0x1e000
9886#define SPI_PS_INPUT_CNTL_14__CYL_WRAP__SHIFT 0xd
9887#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_MASK 0x20000
9888#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX__SHIFT 0x11
9889#define SPI_PS_INPUT_CNTL_14__DUP_MASK 0x40000
9890#define SPI_PS_INPUT_CNTL_14__DUP__SHIFT 0x12
9891#define SPI_PS_INPUT_CNTL_14__FP16_INTERP_MODE_MASK 0x80000
9892#define SPI_PS_INPUT_CNTL_14__FP16_INTERP_MODE__SHIFT 0x13
9893#define SPI_PS_INPUT_CNTL_14__USE_DEFAULT_ATTR1_MASK 0x100000
9894#define SPI_PS_INPUT_CNTL_14__USE_DEFAULT_ATTR1__SHIFT 0x14
9895#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_ATTR1_MASK 0x600000
9896#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_ATTR1__SHIFT 0x15
9897#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_ATTR1_MASK 0x800000
9898#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
9899#define SPI_PS_INPUT_CNTL_14__ATTR0_VALID_MASK 0x1000000
9900#define SPI_PS_INPUT_CNTL_14__ATTR0_VALID__SHIFT 0x18
9901#define SPI_PS_INPUT_CNTL_14__ATTR1_VALID_MASK 0x2000000
9902#define SPI_PS_INPUT_CNTL_14__ATTR1_VALID__SHIFT 0x19
9903#define SPI_PS_INPUT_CNTL_15__OFFSET_MASK 0x3f
9904#define SPI_PS_INPUT_CNTL_15__OFFSET__SHIFT 0x0
9905#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_MASK 0x300
9906#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL__SHIFT 0x8
9907#define SPI_PS_INPUT_CNTL_15__FLAT_SHADE_MASK 0x400
9908#define SPI_PS_INPUT_CNTL_15__FLAT_SHADE__SHIFT 0xa
9909#define SPI_PS_INPUT_CNTL_15__CYL_WRAP_MASK 0x1e000
9910#define SPI_PS_INPUT_CNTL_15__CYL_WRAP__SHIFT 0xd
9911#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_MASK 0x20000
9912#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX__SHIFT 0x11
9913#define SPI_PS_INPUT_CNTL_15__DUP_MASK 0x40000
9914#define SPI_PS_INPUT_CNTL_15__DUP__SHIFT 0x12
9915#define SPI_PS_INPUT_CNTL_15__FP16_INTERP_MODE_MASK 0x80000
9916#define SPI_PS_INPUT_CNTL_15__FP16_INTERP_MODE__SHIFT 0x13
9917#define SPI_PS_INPUT_CNTL_15__USE_DEFAULT_ATTR1_MASK 0x100000
9918#define SPI_PS_INPUT_CNTL_15__USE_DEFAULT_ATTR1__SHIFT 0x14
9919#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_ATTR1_MASK 0x600000
9920#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_ATTR1__SHIFT 0x15
9921#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_ATTR1_MASK 0x800000
9922#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
9923#define SPI_PS_INPUT_CNTL_15__ATTR0_VALID_MASK 0x1000000
9924#define SPI_PS_INPUT_CNTL_15__ATTR0_VALID__SHIFT 0x18
9925#define SPI_PS_INPUT_CNTL_15__ATTR1_VALID_MASK 0x2000000
9926#define SPI_PS_INPUT_CNTL_15__ATTR1_VALID__SHIFT 0x19
9927#define SPI_PS_INPUT_CNTL_16__OFFSET_MASK 0x3f
9928#define SPI_PS_INPUT_CNTL_16__OFFSET__SHIFT 0x0
9929#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_MASK 0x300
9930#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL__SHIFT 0x8
9931#define SPI_PS_INPUT_CNTL_16__FLAT_SHADE_MASK 0x400
9932#define SPI_PS_INPUT_CNTL_16__FLAT_SHADE__SHIFT 0xa
9933#define SPI_PS_INPUT_CNTL_16__CYL_WRAP_MASK 0x1e000
9934#define SPI_PS_INPUT_CNTL_16__CYL_WRAP__SHIFT 0xd
9935#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_MASK 0x20000
9936#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX__SHIFT 0x11
9937#define SPI_PS_INPUT_CNTL_16__DUP_MASK 0x40000
9938#define SPI_PS_INPUT_CNTL_16__DUP__SHIFT 0x12
9939#define SPI_PS_INPUT_CNTL_16__FP16_INTERP_MODE_MASK 0x80000
9940#define SPI_PS_INPUT_CNTL_16__FP16_INTERP_MODE__SHIFT 0x13
9941#define SPI_PS_INPUT_CNTL_16__USE_DEFAULT_ATTR1_MASK 0x100000
9942#define SPI_PS_INPUT_CNTL_16__USE_DEFAULT_ATTR1__SHIFT 0x14
9943#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_ATTR1_MASK 0x600000
9944#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_ATTR1__SHIFT 0x15
9945#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_ATTR1_MASK 0x800000
9946#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
9947#define SPI_PS_INPUT_CNTL_16__ATTR0_VALID_MASK 0x1000000
9948#define SPI_PS_INPUT_CNTL_16__ATTR0_VALID__SHIFT 0x18
9949#define SPI_PS_INPUT_CNTL_16__ATTR1_VALID_MASK 0x2000000
9950#define SPI_PS_INPUT_CNTL_16__ATTR1_VALID__SHIFT 0x19
9951#define SPI_PS_INPUT_CNTL_17__OFFSET_MASK 0x3f
9952#define SPI_PS_INPUT_CNTL_17__OFFSET__SHIFT 0x0
9953#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_MASK 0x300
9954#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL__SHIFT 0x8
9955#define SPI_PS_INPUT_CNTL_17__FLAT_SHADE_MASK 0x400
9956#define SPI_PS_INPUT_CNTL_17__FLAT_SHADE__SHIFT 0xa
9957#define SPI_PS_INPUT_CNTL_17__CYL_WRAP_MASK 0x1e000
9958#define SPI_PS_INPUT_CNTL_17__CYL_WRAP__SHIFT 0xd
9959#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_MASK 0x20000
9960#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX__SHIFT 0x11
9961#define SPI_PS_INPUT_CNTL_17__DUP_MASK 0x40000
9962#define SPI_PS_INPUT_CNTL_17__DUP__SHIFT 0x12
9963#define SPI_PS_INPUT_CNTL_17__FP16_INTERP_MODE_MASK 0x80000
9964#define SPI_PS_INPUT_CNTL_17__FP16_INTERP_MODE__SHIFT 0x13
9965#define SPI_PS_INPUT_CNTL_17__USE_DEFAULT_ATTR1_MASK 0x100000
9966#define SPI_PS_INPUT_CNTL_17__USE_DEFAULT_ATTR1__SHIFT 0x14
9967#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_ATTR1_MASK 0x600000
9968#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_ATTR1__SHIFT 0x15
9969#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_ATTR1_MASK 0x800000
9970#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
9971#define SPI_PS_INPUT_CNTL_17__ATTR0_VALID_MASK 0x1000000
9972#define SPI_PS_INPUT_CNTL_17__ATTR0_VALID__SHIFT 0x18
9973#define SPI_PS_INPUT_CNTL_17__ATTR1_VALID_MASK 0x2000000
9974#define SPI_PS_INPUT_CNTL_17__ATTR1_VALID__SHIFT 0x19
9975#define SPI_PS_INPUT_CNTL_18__OFFSET_MASK 0x3f
9976#define SPI_PS_INPUT_CNTL_18__OFFSET__SHIFT 0x0
9977#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_MASK 0x300
9978#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL__SHIFT 0x8
9979#define SPI_PS_INPUT_CNTL_18__FLAT_SHADE_MASK 0x400
9980#define SPI_PS_INPUT_CNTL_18__FLAT_SHADE__SHIFT 0xa
9981#define SPI_PS_INPUT_CNTL_18__CYL_WRAP_MASK 0x1e000
9982#define SPI_PS_INPUT_CNTL_18__CYL_WRAP__SHIFT 0xd
9983#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_MASK 0x20000
9984#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX__SHIFT 0x11
9985#define SPI_PS_INPUT_CNTL_18__DUP_MASK 0x40000
9986#define SPI_PS_INPUT_CNTL_18__DUP__SHIFT 0x12
9987#define SPI_PS_INPUT_CNTL_18__FP16_INTERP_MODE_MASK 0x80000
9988#define SPI_PS_INPUT_CNTL_18__FP16_INTERP_MODE__SHIFT 0x13
9989#define SPI_PS_INPUT_CNTL_18__USE_DEFAULT_ATTR1_MASK 0x100000
9990#define SPI_PS_INPUT_CNTL_18__USE_DEFAULT_ATTR1__SHIFT 0x14
9991#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_ATTR1_MASK 0x600000
9992#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_ATTR1__SHIFT 0x15
9993#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_ATTR1_MASK 0x800000
9994#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
9995#define SPI_PS_INPUT_CNTL_18__ATTR0_VALID_MASK 0x1000000
9996#define SPI_PS_INPUT_CNTL_18__ATTR0_VALID__SHIFT 0x18
9997#define SPI_PS_INPUT_CNTL_18__ATTR1_VALID_MASK 0x2000000
9998#define SPI_PS_INPUT_CNTL_18__ATTR1_VALID__SHIFT 0x19
9999#define SPI_PS_INPUT_CNTL_19__OFFSET_MASK 0x3f
10000#define SPI_PS_INPUT_CNTL_19__OFFSET__SHIFT 0x0
10001#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_MASK 0x300
10002#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL__SHIFT 0x8
10003#define SPI_PS_INPUT_CNTL_19__FLAT_SHADE_MASK 0x400
10004#define SPI_PS_INPUT_CNTL_19__FLAT_SHADE__SHIFT 0xa
10005#define SPI_PS_INPUT_CNTL_19__CYL_WRAP_MASK 0x1e000
10006#define SPI_PS_INPUT_CNTL_19__CYL_WRAP__SHIFT 0xd
10007#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_MASK 0x20000
10008#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX__SHIFT 0x11
10009#define SPI_PS_INPUT_CNTL_19__DUP_MASK 0x40000
10010#define SPI_PS_INPUT_CNTL_19__DUP__SHIFT 0x12
10011#define SPI_PS_INPUT_CNTL_19__FP16_INTERP_MODE_MASK 0x80000
10012#define SPI_PS_INPUT_CNTL_19__FP16_INTERP_MODE__SHIFT 0x13
10013#define SPI_PS_INPUT_CNTL_19__USE_DEFAULT_ATTR1_MASK 0x100000
10014#define SPI_PS_INPUT_CNTL_19__USE_DEFAULT_ATTR1__SHIFT 0x14
10015#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_ATTR1_MASK 0x600000
10016#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_ATTR1__SHIFT 0x15
10017#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_ATTR1_MASK 0x800000
10018#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
10019#define SPI_PS_INPUT_CNTL_19__ATTR0_VALID_MASK 0x1000000
10020#define SPI_PS_INPUT_CNTL_19__ATTR0_VALID__SHIFT 0x18
10021#define SPI_PS_INPUT_CNTL_19__ATTR1_VALID_MASK 0x2000000
10022#define SPI_PS_INPUT_CNTL_19__ATTR1_VALID__SHIFT 0x19
10023#define SPI_PS_INPUT_CNTL_20__OFFSET_MASK 0x3f
10024#define SPI_PS_INPUT_CNTL_20__OFFSET__SHIFT 0x0
10025#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_MASK 0x300
10026#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL__SHIFT 0x8
10027#define SPI_PS_INPUT_CNTL_20__FLAT_SHADE_MASK 0x400
10028#define SPI_PS_INPUT_CNTL_20__FLAT_SHADE__SHIFT 0xa
10029#define SPI_PS_INPUT_CNTL_20__DUP_MASK 0x40000
10030#define SPI_PS_INPUT_CNTL_20__DUP__SHIFT 0x12
10031#define SPI_PS_INPUT_CNTL_20__FP16_INTERP_MODE_MASK 0x80000
10032#define SPI_PS_INPUT_CNTL_20__FP16_INTERP_MODE__SHIFT 0x13
10033#define SPI_PS_INPUT_CNTL_20__USE_DEFAULT_ATTR1_MASK 0x100000
10034#define SPI_PS_INPUT_CNTL_20__USE_DEFAULT_ATTR1__SHIFT 0x14
10035#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_ATTR1_MASK 0x600000
10036#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_ATTR1__SHIFT 0x15
10037#define SPI_PS_INPUT_CNTL_20__ATTR0_VALID_MASK 0x1000000
10038#define SPI_PS_INPUT_CNTL_20__ATTR0_VALID__SHIFT 0x18
10039#define SPI_PS_INPUT_CNTL_20__ATTR1_VALID_MASK 0x2000000
10040#define SPI_PS_INPUT_CNTL_20__ATTR1_VALID__SHIFT 0x19
10041#define SPI_PS_INPUT_CNTL_21__OFFSET_MASK 0x3f
10042#define SPI_PS_INPUT_CNTL_21__OFFSET__SHIFT 0x0
10043#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_MASK 0x300
10044#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL__SHIFT 0x8
10045#define SPI_PS_INPUT_CNTL_21__FLAT_SHADE_MASK 0x400
10046#define SPI_PS_INPUT_CNTL_21__FLAT_SHADE__SHIFT 0xa
10047#define SPI_PS_INPUT_CNTL_21__DUP_MASK 0x40000
10048#define SPI_PS_INPUT_CNTL_21__DUP__SHIFT 0x12
10049#define SPI_PS_INPUT_CNTL_21__FP16_INTERP_MODE_MASK 0x80000
10050#define SPI_PS_INPUT_CNTL_21__FP16_INTERP_MODE__SHIFT 0x13
10051#define SPI_PS_INPUT_CNTL_21__USE_DEFAULT_ATTR1_MASK 0x100000
10052#define SPI_PS_INPUT_CNTL_21__USE_DEFAULT_ATTR1__SHIFT 0x14
10053#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_ATTR1_MASK 0x600000
10054#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_ATTR1__SHIFT 0x15
10055#define SPI_PS_INPUT_CNTL_21__ATTR0_VALID_MASK 0x1000000
10056#define SPI_PS_INPUT_CNTL_21__ATTR0_VALID__SHIFT 0x18
10057#define SPI_PS_INPUT_CNTL_21__ATTR1_VALID_MASK 0x2000000
10058#define SPI_PS_INPUT_CNTL_21__ATTR1_VALID__SHIFT 0x19
10059#define SPI_PS_INPUT_CNTL_22__OFFSET_MASK 0x3f
10060#define SPI_PS_INPUT_CNTL_22__OFFSET__SHIFT 0x0
10061#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_MASK 0x300
10062#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL__SHIFT 0x8
10063#define SPI_PS_INPUT_CNTL_22__FLAT_SHADE_MASK 0x400
10064#define SPI_PS_INPUT_CNTL_22__FLAT_SHADE__SHIFT 0xa
10065#define SPI_PS_INPUT_CNTL_22__DUP_MASK 0x40000
10066#define SPI_PS_INPUT_CNTL_22__DUP__SHIFT 0x12
10067#define SPI_PS_INPUT_CNTL_22__FP16_INTERP_MODE_MASK 0x80000
10068#define SPI_PS_INPUT_CNTL_22__FP16_INTERP_MODE__SHIFT 0x13
10069#define SPI_PS_INPUT_CNTL_22__USE_DEFAULT_ATTR1_MASK 0x100000
10070#define SPI_PS_INPUT_CNTL_22__USE_DEFAULT_ATTR1__SHIFT 0x14
10071#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_ATTR1_MASK 0x600000
10072#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_ATTR1__SHIFT 0x15
10073#define SPI_PS_INPUT_CNTL_22__ATTR0_VALID_MASK 0x1000000
10074#define SPI_PS_INPUT_CNTL_22__ATTR0_VALID__SHIFT 0x18
10075#define SPI_PS_INPUT_CNTL_22__ATTR1_VALID_MASK 0x2000000
10076#define SPI_PS_INPUT_CNTL_22__ATTR1_VALID__SHIFT 0x19
10077#define SPI_PS_INPUT_CNTL_23__OFFSET_MASK 0x3f
10078#define SPI_PS_INPUT_CNTL_23__OFFSET__SHIFT 0x0
10079#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_MASK 0x300
10080#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL__SHIFT 0x8
10081#define SPI_PS_INPUT_CNTL_23__FLAT_SHADE_MASK 0x400
10082#define SPI_PS_INPUT_CNTL_23__FLAT_SHADE__SHIFT 0xa
10083#define SPI_PS_INPUT_CNTL_23__DUP_MASK 0x40000
10084#define SPI_PS_INPUT_CNTL_23__DUP__SHIFT 0x12
10085#define SPI_PS_INPUT_CNTL_23__FP16_INTERP_MODE_MASK 0x80000
10086#define SPI_PS_INPUT_CNTL_23__FP16_INTERP_MODE__SHIFT 0x13
10087#define SPI_PS_INPUT_CNTL_23__USE_DEFAULT_ATTR1_MASK 0x100000
10088#define SPI_PS_INPUT_CNTL_23__USE_DEFAULT_ATTR1__SHIFT 0x14
10089#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_ATTR1_MASK 0x600000
10090#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_ATTR1__SHIFT 0x15
10091#define SPI_PS_INPUT_CNTL_23__ATTR0_VALID_MASK 0x1000000
10092#define SPI_PS_INPUT_CNTL_23__ATTR0_VALID__SHIFT 0x18
10093#define SPI_PS_INPUT_CNTL_23__ATTR1_VALID_MASK 0x2000000
10094#define SPI_PS_INPUT_CNTL_23__ATTR1_VALID__SHIFT 0x19
10095#define SPI_PS_INPUT_CNTL_24__OFFSET_MASK 0x3f
10096#define SPI_PS_INPUT_CNTL_24__OFFSET__SHIFT 0x0
10097#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_MASK 0x300
10098#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL__SHIFT 0x8
10099#define SPI_PS_INPUT_CNTL_24__FLAT_SHADE_MASK 0x400
10100#define SPI_PS_INPUT_CNTL_24__FLAT_SHADE__SHIFT 0xa
10101#define SPI_PS_INPUT_CNTL_24__DUP_MASK 0x40000
10102#define SPI_PS_INPUT_CNTL_24__DUP__SHIFT 0x12
10103#define SPI_PS_INPUT_CNTL_24__FP16_INTERP_MODE_MASK 0x80000
10104#define SPI_PS_INPUT_CNTL_24__FP16_INTERP_MODE__SHIFT 0x13
10105#define SPI_PS_INPUT_CNTL_24__USE_DEFAULT_ATTR1_MASK 0x100000
10106#define SPI_PS_INPUT_CNTL_24__USE_DEFAULT_ATTR1__SHIFT 0x14
10107#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_ATTR1_MASK 0x600000
10108#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_ATTR1__SHIFT 0x15
10109#define SPI_PS_INPUT_CNTL_24__ATTR0_VALID_MASK 0x1000000
10110#define SPI_PS_INPUT_CNTL_24__ATTR0_VALID__SHIFT 0x18
10111#define SPI_PS_INPUT_CNTL_24__ATTR1_VALID_MASK 0x2000000
10112#define SPI_PS_INPUT_CNTL_24__ATTR1_VALID__SHIFT 0x19
10113#define SPI_PS_INPUT_CNTL_25__OFFSET_MASK 0x3f
10114#define SPI_PS_INPUT_CNTL_25__OFFSET__SHIFT 0x0
10115#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_MASK 0x300
10116#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL__SHIFT 0x8
10117#define SPI_PS_INPUT_CNTL_25__FLAT_SHADE_MASK 0x400
10118#define SPI_PS_INPUT_CNTL_25__FLAT_SHADE__SHIFT 0xa
10119#define SPI_PS_INPUT_CNTL_25__DUP_MASK 0x40000
10120#define SPI_PS_INPUT_CNTL_25__DUP__SHIFT 0x12
10121#define SPI_PS_INPUT_CNTL_25__FP16_INTERP_MODE_MASK 0x80000
10122#define SPI_PS_INPUT_CNTL_25__FP16_INTERP_MODE__SHIFT 0x13
10123#define SPI_PS_INPUT_CNTL_25__USE_DEFAULT_ATTR1_MASK 0x100000
10124#define SPI_PS_INPUT_CNTL_25__USE_DEFAULT_ATTR1__SHIFT 0x14
10125#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_ATTR1_MASK 0x600000
10126#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_ATTR1__SHIFT 0x15
10127#define SPI_PS_INPUT_CNTL_25__ATTR0_VALID_MASK 0x1000000
10128#define SPI_PS_INPUT_CNTL_25__ATTR0_VALID__SHIFT 0x18
10129#define SPI_PS_INPUT_CNTL_25__ATTR1_VALID_MASK 0x2000000
10130#define SPI_PS_INPUT_CNTL_25__ATTR1_VALID__SHIFT 0x19
10131#define SPI_PS_INPUT_CNTL_26__OFFSET_MASK 0x3f
10132#define SPI_PS_INPUT_CNTL_26__OFFSET__SHIFT 0x0
10133#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_MASK 0x300
10134#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL__SHIFT 0x8
10135#define SPI_PS_INPUT_CNTL_26__FLAT_SHADE_MASK 0x400
10136#define SPI_PS_INPUT_CNTL_26__FLAT_SHADE__SHIFT 0xa
10137#define SPI_PS_INPUT_CNTL_26__DUP_MASK 0x40000
10138#define SPI_PS_INPUT_CNTL_26__DUP__SHIFT 0x12
10139#define SPI_PS_INPUT_CNTL_26__FP16_INTERP_MODE_MASK 0x80000
10140#define SPI_PS_INPUT_CNTL_26__FP16_INTERP_MODE__SHIFT 0x13
10141#define SPI_PS_INPUT_CNTL_26__USE_DEFAULT_ATTR1_MASK 0x100000
10142#define SPI_PS_INPUT_CNTL_26__USE_DEFAULT_ATTR1__SHIFT 0x14
10143#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_ATTR1_MASK 0x600000
10144#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_ATTR1__SHIFT 0x15
10145#define SPI_PS_INPUT_CNTL_26__ATTR0_VALID_MASK 0x1000000
10146#define SPI_PS_INPUT_CNTL_26__ATTR0_VALID__SHIFT 0x18
10147#define SPI_PS_INPUT_CNTL_26__ATTR1_VALID_MASK 0x2000000
10148#define SPI_PS_INPUT_CNTL_26__ATTR1_VALID__SHIFT 0x19
10149#define SPI_PS_INPUT_CNTL_27__OFFSET_MASK 0x3f
10150#define SPI_PS_INPUT_CNTL_27__OFFSET__SHIFT 0x0
10151#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_MASK 0x300
10152#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL__SHIFT 0x8
10153#define SPI_PS_INPUT_CNTL_27__FLAT_SHADE_MASK 0x400
10154#define SPI_PS_INPUT_CNTL_27__FLAT_SHADE__SHIFT 0xa
10155#define SPI_PS_INPUT_CNTL_27__DUP_MASK 0x40000
10156#define SPI_PS_INPUT_CNTL_27__DUP__SHIFT 0x12
10157#define SPI_PS_INPUT_CNTL_27__FP16_INTERP_MODE_MASK 0x80000
10158#define SPI_PS_INPUT_CNTL_27__FP16_INTERP_MODE__SHIFT 0x13
10159#define SPI_PS_INPUT_CNTL_27__USE_DEFAULT_ATTR1_MASK 0x100000
10160#define SPI_PS_INPUT_CNTL_27__USE_DEFAULT_ATTR1__SHIFT 0x14
10161#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_ATTR1_MASK 0x600000
10162#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_ATTR1__SHIFT 0x15
10163#define SPI_PS_INPUT_CNTL_27__ATTR0_VALID_MASK 0x1000000
10164#define SPI_PS_INPUT_CNTL_27__ATTR0_VALID__SHIFT 0x18
10165#define SPI_PS_INPUT_CNTL_27__ATTR1_VALID_MASK 0x2000000
10166#define SPI_PS_INPUT_CNTL_27__ATTR1_VALID__SHIFT 0x19
10167#define SPI_PS_INPUT_CNTL_28__OFFSET_MASK 0x3f
10168#define SPI_PS_INPUT_CNTL_28__OFFSET__SHIFT 0x0
10169#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_MASK 0x300
10170#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL__SHIFT 0x8
10171#define SPI_PS_INPUT_CNTL_28__FLAT_SHADE_MASK 0x400
10172#define SPI_PS_INPUT_CNTL_28__FLAT_SHADE__SHIFT 0xa
10173#define SPI_PS_INPUT_CNTL_28__DUP_MASK 0x40000
10174#define SPI_PS_INPUT_CNTL_28__DUP__SHIFT 0x12
10175#define SPI_PS_INPUT_CNTL_28__FP16_INTERP_MODE_MASK 0x80000
10176#define SPI_PS_INPUT_CNTL_28__FP16_INTERP_MODE__SHIFT 0x13
10177#define SPI_PS_INPUT_CNTL_28__USE_DEFAULT_ATTR1_MASK 0x100000
10178#define SPI_PS_INPUT_CNTL_28__USE_DEFAULT_ATTR1__SHIFT 0x14
10179#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_ATTR1_MASK 0x600000
10180#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_ATTR1__SHIFT 0x15
10181#define SPI_PS_INPUT_CNTL_28__ATTR0_VALID_MASK 0x1000000
10182#define SPI_PS_INPUT_CNTL_28__ATTR0_VALID__SHIFT 0x18
10183#define SPI_PS_INPUT_CNTL_28__ATTR1_VALID_MASK 0x2000000
10184#define SPI_PS_INPUT_CNTL_28__ATTR1_VALID__SHIFT 0x19
10185#define SPI_PS_INPUT_CNTL_29__OFFSET_MASK 0x3f
10186#define SPI_PS_INPUT_CNTL_29__OFFSET__SHIFT 0x0
10187#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_MASK 0x300
10188#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL__SHIFT 0x8
10189#define SPI_PS_INPUT_CNTL_29__FLAT_SHADE_MASK 0x400
10190#define SPI_PS_INPUT_CNTL_29__FLAT_SHADE__SHIFT 0xa
10191#define SPI_PS_INPUT_CNTL_29__DUP_MASK 0x40000
10192#define SPI_PS_INPUT_CNTL_29__DUP__SHIFT 0x12
10193#define SPI_PS_INPUT_CNTL_29__FP16_INTERP_MODE_MASK 0x80000
10194#define SPI_PS_INPUT_CNTL_29__FP16_INTERP_MODE__SHIFT 0x13
10195#define SPI_PS_INPUT_CNTL_29__USE_DEFAULT_ATTR1_MASK 0x100000
10196#define SPI_PS_INPUT_CNTL_29__USE_DEFAULT_ATTR1__SHIFT 0x14
10197#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_ATTR1_MASK 0x600000
10198#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_ATTR1__SHIFT 0x15
10199#define SPI_PS_INPUT_CNTL_29__ATTR0_VALID_MASK 0x1000000
10200#define SPI_PS_INPUT_CNTL_29__ATTR0_VALID__SHIFT 0x18
10201#define SPI_PS_INPUT_CNTL_29__ATTR1_VALID_MASK 0x2000000
10202#define SPI_PS_INPUT_CNTL_29__ATTR1_VALID__SHIFT 0x19
10203#define SPI_PS_INPUT_CNTL_30__OFFSET_MASK 0x3f
10204#define SPI_PS_INPUT_CNTL_30__OFFSET__SHIFT 0x0
10205#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_MASK 0x300
10206#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL__SHIFT 0x8
10207#define SPI_PS_INPUT_CNTL_30__FLAT_SHADE_MASK 0x400
10208#define SPI_PS_INPUT_CNTL_30__FLAT_SHADE__SHIFT 0xa
10209#define SPI_PS_INPUT_CNTL_30__DUP_MASK 0x40000
10210#define SPI_PS_INPUT_CNTL_30__DUP__SHIFT 0x12
10211#define SPI_PS_INPUT_CNTL_30__FP16_INTERP_MODE_MASK 0x80000
10212#define SPI_PS_INPUT_CNTL_30__FP16_INTERP_MODE__SHIFT 0x13
10213#define SPI_PS_INPUT_CNTL_30__USE_DEFAULT_ATTR1_MASK 0x100000
10214#define SPI_PS_INPUT_CNTL_30__USE_DEFAULT_ATTR1__SHIFT 0x14
10215#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_ATTR1_MASK 0x600000
10216#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_ATTR1__SHIFT 0x15
10217#define SPI_PS_INPUT_CNTL_30__ATTR0_VALID_MASK 0x1000000
10218#define SPI_PS_INPUT_CNTL_30__ATTR0_VALID__SHIFT 0x18
10219#define SPI_PS_INPUT_CNTL_30__ATTR1_VALID_MASK 0x2000000
10220#define SPI_PS_INPUT_CNTL_30__ATTR1_VALID__SHIFT 0x19
10221#define SPI_PS_INPUT_CNTL_31__OFFSET_MASK 0x3f
10222#define SPI_PS_INPUT_CNTL_31__OFFSET__SHIFT 0x0
10223#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_MASK 0x300
10224#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL__SHIFT 0x8
10225#define SPI_PS_INPUT_CNTL_31__FLAT_SHADE_MASK 0x400
10226#define SPI_PS_INPUT_CNTL_31__FLAT_SHADE__SHIFT 0xa
10227#define SPI_PS_INPUT_CNTL_31__DUP_MASK 0x40000
10228#define SPI_PS_INPUT_CNTL_31__DUP__SHIFT 0x12
10229#define SPI_PS_INPUT_CNTL_31__FP16_INTERP_MODE_MASK 0x80000
10230#define SPI_PS_INPUT_CNTL_31__FP16_INTERP_MODE__SHIFT 0x13
10231#define SPI_PS_INPUT_CNTL_31__USE_DEFAULT_ATTR1_MASK 0x100000
10232#define SPI_PS_INPUT_CNTL_31__USE_DEFAULT_ATTR1__SHIFT 0x14
10233#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_ATTR1_MASK 0x600000
10234#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_ATTR1__SHIFT 0x15
10235#define SPI_PS_INPUT_CNTL_31__ATTR0_VALID_MASK 0x1000000
10236#define SPI_PS_INPUT_CNTL_31__ATTR0_VALID__SHIFT 0x18
10237#define SPI_PS_INPUT_CNTL_31__ATTR1_VALID_MASK 0x2000000
10238#define SPI_PS_INPUT_CNTL_31__ATTR1_VALID__SHIFT 0x19
10239#define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT_MASK 0x3e
10240#define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT__SHIFT 0x1
10241#define SPI_VS_OUT_CONFIG__VS_HALF_PACK_MASK 0x40
10242#define SPI_VS_OUT_CONFIG__VS_HALF_PACK__SHIFT 0x6
10243#define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA_MASK 0x1
10244#define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA__SHIFT 0x0
10245#define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA_MASK 0x2
10246#define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA__SHIFT 0x1
10247#define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA_MASK 0x4
10248#define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA__SHIFT 0x2
10249#define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA_MASK 0x8
10250#define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA__SHIFT 0x3
10251#define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA_MASK 0x10
10252#define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA__SHIFT 0x4
10253#define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA_MASK 0x20
10254#define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA__SHIFT 0x5
10255#define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA_MASK 0x40
10256#define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA__SHIFT 0x6
10257#define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA_MASK 0x80
10258#define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA__SHIFT 0x7
10259#define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA_MASK 0x100
10260#define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA__SHIFT 0x8
10261#define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA_MASK 0x200
10262#define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA__SHIFT 0x9
10263#define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA_MASK 0x400
10264#define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA__SHIFT 0xa
10265#define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA_MASK 0x800
10266#define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA__SHIFT 0xb
10267#define SPI_PS_INPUT_ENA__FRONT_FACE_ENA_MASK 0x1000
10268#define SPI_PS_INPUT_ENA__FRONT_FACE_ENA__SHIFT 0xc
10269#define SPI_PS_INPUT_ENA__ANCILLARY_ENA_MASK 0x2000
10270#define SPI_PS_INPUT_ENA__ANCILLARY_ENA__SHIFT 0xd
10271#define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA_MASK 0x4000
10272#define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA__SHIFT 0xe
10273#define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA_MASK 0x8000
10274#define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA__SHIFT 0xf
10275#define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA_MASK 0x1
10276#define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA__SHIFT 0x0
10277#define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA_MASK 0x2
10278#define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA__SHIFT 0x1
10279#define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA_MASK 0x4
10280#define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA__SHIFT 0x2
10281#define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA_MASK 0x8
10282#define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA__SHIFT 0x3
10283#define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA_MASK 0x10
10284#define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA__SHIFT 0x4
10285#define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA_MASK 0x20
10286#define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA__SHIFT 0x5
10287#define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA_MASK 0x40
10288#define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA__SHIFT 0x6
10289#define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA_MASK 0x80
10290#define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA__SHIFT 0x7
10291#define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA_MASK 0x100
10292#define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA__SHIFT 0x8
10293#define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA_MASK 0x200
10294#define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA__SHIFT 0x9
10295#define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA_MASK 0x400
10296#define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA__SHIFT 0xa
10297#define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA_MASK 0x800
10298#define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA__SHIFT 0xb
10299#define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA_MASK 0x1000
10300#define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA__SHIFT 0xc
10301#define SPI_PS_INPUT_ADDR__ANCILLARY_ENA_MASK 0x2000
10302#define SPI_PS_INPUT_ADDR__ANCILLARY_ENA__SHIFT 0xd
10303#define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA_MASK 0x4000
10304#define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA__SHIFT 0xe
10305#define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA_MASK 0x8000
10306#define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA__SHIFT 0xf
10307#define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA_MASK 0x1
10308#define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA__SHIFT 0x0
10309#define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA_MASK 0x2
10310#define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA__SHIFT 0x1
10311#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X_MASK 0x1c
10312#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X__SHIFT 0x2
10313#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y_MASK 0xe0
10314#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y__SHIFT 0x5
10315#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z_MASK 0x700
10316#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z__SHIFT 0x8
10317#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W_MASK 0x3800
10318#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W__SHIFT 0xb
10319#define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1_MASK 0x4000
10320#define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1__SHIFT 0xe
10321#define SPI_PS_IN_CONTROL__NUM_INTERP_MASK 0x3f
10322#define SPI_PS_IN_CONTROL__NUM_INTERP__SHIFT 0x0
10323#define SPI_PS_IN_CONTROL__PARAM_GEN_MASK 0x40
10324#define SPI_PS_IN_CONTROL__PARAM_GEN__SHIFT 0x6
10325#define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE_MASK 0x4000
10326#define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE__SHIFT 0xe
10327#define SPI_BARYC_CNTL__PERSP_CENTER_CNTL_MASK 0x1
10328#define SPI_BARYC_CNTL__PERSP_CENTER_CNTL__SHIFT 0x0
10329#define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL_MASK 0x10
10330#define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL__SHIFT 0x4
10331#define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL_MASK 0x100
10332#define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL__SHIFT 0x8
10333#define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL_MASK 0x1000
10334#define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL__SHIFT 0xc
10335#define SPI_BARYC_CNTL__POS_FLOAT_LOCATION_MASK 0x30000
10336#define SPI_BARYC_CNTL__POS_FLOAT_LOCATION__SHIFT 0x10
10337#define SPI_BARYC_CNTL__POS_FLOAT_ULC_MASK 0x100000
10338#define SPI_BARYC_CNTL__POS_FLOAT_ULC__SHIFT 0x14
10339#define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS_MASK 0x1000000
10340#define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS__SHIFT 0x18
10341#define SPI_TMPRING_SIZE__WAVES_MASK 0xfff
10342#define SPI_TMPRING_SIZE__WAVES__SHIFT 0x0
10343#define SPI_TMPRING_SIZE__WAVESIZE_MASK 0x1fff000
10344#define SPI_TMPRING_SIZE__WAVESIZE__SHIFT 0xc
10345#define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT_MASK 0xf
10346#define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT__SHIFT 0x0
10347#define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT_MASK 0xf0
10348#define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT__SHIFT 0x4
10349#define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT_MASK 0xf00
10350#define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT__SHIFT 0x8
10351#define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT_MASK 0xf000
10352#define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT__SHIFT 0xc
10353#define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT_MASK 0xf
10354#define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT__SHIFT 0x0
10355#define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT_MASK 0xf
10356#define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT__SHIFT 0x0
10357#define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT_MASK 0xf0
10358#define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT__SHIFT 0x4
10359#define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT_MASK 0xf00
10360#define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT__SHIFT 0x8
10361#define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT_MASK 0xf000
10362#define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT__SHIFT 0xc
10363#define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT_MASK 0xf0000
10364#define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT__SHIFT 0x10
10365#define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT_MASK 0xf00000
10366#define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT__SHIFT 0x14
10367#define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT_MASK 0xf000000
10368#define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT__SHIFT 0x18
10369#define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT_MASK 0xf0000000
10370#define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT__SHIFT 0x1c
10371#define SPI_ARB_PRIORITY__PIPE_ORDER_TS0_MASK 0x7
10372#define SPI_ARB_PRIORITY__PIPE_ORDER_TS0__SHIFT 0x0
10373#define SPI_ARB_PRIORITY__PIPE_ORDER_TS1_MASK 0x38
10374#define SPI_ARB_PRIORITY__PIPE_ORDER_TS1__SHIFT 0x3
10375#define SPI_ARB_PRIORITY__PIPE_ORDER_TS2_MASK 0x1c0
10376#define SPI_ARB_PRIORITY__PIPE_ORDER_TS2__SHIFT 0x6
10377#define SPI_ARB_PRIORITY__PIPE_ORDER_TS3_MASK 0xe00
10378#define SPI_ARB_PRIORITY__PIPE_ORDER_TS3__SHIFT 0x9
10379#define SPI_ARB_PRIORITY__TS0_DUR_MULT_MASK 0x3000
10380#define SPI_ARB_PRIORITY__TS0_DUR_MULT__SHIFT 0xc
10381#define SPI_ARB_PRIORITY__TS1_DUR_MULT_MASK 0xc000
10382#define SPI_ARB_PRIORITY__TS1_DUR_MULT__SHIFT 0xe
10383#define SPI_ARB_PRIORITY__TS2_DUR_MULT_MASK 0x30000
10384#define SPI_ARB_PRIORITY__TS2_DUR_MULT__SHIFT 0x10
10385#define SPI_ARB_PRIORITY__TS3_DUR_MULT_MASK 0xc0000
10386#define SPI_ARB_PRIORITY__TS3_DUR_MULT__SHIFT 0x12
10387#define SPI_ARB_CYCLES_0__TS0_DURATION_MASK 0xffff
10388#define SPI_ARB_CYCLES_0__TS0_DURATION__SHIFT 0x0
10389#define SPI_ARB_CYCLES_0__TS1_DURATION_MASK 0xffff0000
10390#define SPI_ARB_CYCLES_0__TS1_DURATION__SHIFT 0x10
10391#define SPI_ARB_CYCLES_1__TS2_DURATION_MASK 0xffff
10392#define SPI_ARB_CYCLES_1__TS2_DURATION__SHIFT 0x0
10393#define SPI_ARB_CYCLES_1__TS3_DURATION_MASK 0xffff0000
10394#define SPI_ARB_CYCLES_1__TS3_DURATION__SHIFT 0x10
10395#define SPI_CDBG_SYS_GFX__PS_EN_MASK 0x1
10396#define SPI_CDBG_SYS_GFX__PS_EN__SHIFT 0x0
10397#define SPI_CDBG_SYS_GFX__VS_EN_MASK 0x2
10398#define SPI_CDBG_SYS_GFX__VS_EN__SHIFT 0x1
10399#define SPI_CDBG_SYS_GFX__GS_EN_MASK 0x4
10400#define SPI_CDBG_SYS_GFX__GS_EN__SHIFT 0x2
10401#define SPI_CDBG_SYS_GFX__ES_EN_MASK 0x8
10402#define SPI_CDBG_SYS_GFX__ES_EN__SHIFT 0x3
10403#define SPI_CDBG_SYS_GFX__HS_EN_MASK 0x10
10404#define SPI_CDBG_SYS_GFX__HS_EN__SHIFT 0x4
10405#define SPI_CDBG_SYS_GFX__LS_EN_MASK 0x20
10406#define SPI_CDBG_SYS_GFX__LS_EN__SHIFT 0x5
10407#define SPI_CDBG_SYS_GFX__CS_EN_MASK 0x40
10408#define SPI_CDBG_SYS_GFX__CS_EN__SHIFT 0x6
10409#define SPI_CDBG_SYS_HP3D__PS_EN_MASK 0x1
10410#define SPI_CDBG_SYS_HP3D__PS_EN__SHIFT 0x0
10411#define SPI_CDBG_SYS_HP3D__VS_EN_MASK 0x2
10412#define SPI_CDBG_SYS_HP3D__VS_EN__SHIFT 0x1
10413#define SPI_CDBG_SYS_HP3D__GS_EN_MASK 0x4
10414#define SPI_CDBG_SYS_HP3D__GS_EN__SHIFT 0x2
10415#define SPI_CDBG_SYS_HP3D__ES_EN_MASK 0x8
10416#define SPI_CDBG_SYS_HP3D__ES_EN__SHIFT 0x3
10417#define SPI_CDBG_SYS_HP3D__HS_EN_MASK 0x10
10418#define SPI_CDBG_SYS_HP3D__HS_EN__SHIFT 0x4
10419#define SPI_CDBG_SYS_HP3D__LS_EN_MASK 0x20
10420#define SPI_CDBG_SYS_HP3D__LS_EN__SHIFT 0x5
10421#define SPI_CDBG_SYS_CS0__PIPE0_MASK 0xff
10422#define SPI_CDBG_SYS_CS0__PIPE0__SHIFT 0x0
10423#define SPI_CDBG_SYS_CS0__PIPE1_MASK 0xff00
10424#define SPI_CDBG_SYS_CS0__PIPE1__SHIFT 0x8
10425#define SPI_CDBG_SYS_CS0__PIPE2_MASK 0xff0000
10426#define SPI_CDBG_SYS_CS0__PIPE2__SHIFT 0x10
10427#define SPI_CDBG_SYS_CS0__PIPE3_MASK 0xff000000
10428#define SPI_CDBG_SYS_CS0__PIPE3__SHIFT 0x18
10429#define SPI_CDBG_SYS_CS1__PIPE0_MASK 0xff
10430#define SPI_CDBG_SYS_CS1__PIPE0__SHIFT 0x0
10431#define SPI_CDBG_SYS_CS1__PIPE1_MASK 0xff00
10432#define SPI_CDBG_SYS_CS1__PIPE1__SHIFT 0x8
10433#define SPI_CDBG_SYS_CS1__PIPE2_MASK 0xff0000
10434#define SPI_CDBG_SYS_CS1__PIPE2__SHIFT 0x10
10435#define SPI_CDBG_SYS_CS1__PIPE3_MASK 0xff000000
10436#define SPI_CDBG_SYS_CS1__PIPE3__SHIFT 0x18
10437#define SPI_WCL_PIPE_PERCENT_GFX__VALUE_MASK 0x7f
10438#define SPI_WCL_PIPE_PERCENT_GFX__VALUE__SHIFT 0x0
10439#define SPI_WCL_PIPE_PERCENT_GFX__LS_GRP_VALUE_MASK 0xf80
10440#define SPI_WCL_PIPE_PERCENT_GFX__LS_GRP_VALUE__SHIFT 0x7
10441#define SPI_WCL_PIPE_PERCENT_GFX__HS_GRP_VALUE_MASK 0x1f000
10442#define SPI_WCL_PIPE_PERCENT_GFX__HS_GRP_VALUE__SHIFT 0xc
10443#define SPI_WCL_PIPE_PERCENT_GFX__ES_GRP_VALUE_MASK 0x3e0000
10444#define SPI_WCL_PIPE_PERCENT_GFX__ES_GRP_VALUE__SHIFT 0x11
10445#define SPI_WCL_PIPE_PERCENT_GFX__GS_GRP_VALUE_MASK 0x7c00000
10446#define SPI_WCL_PIPE_PERCENT_GFX__GS_GRP_VALUE__SHIFT 0x16
10447#define SPI_WCL_PIPE_PERCENT_HP3D__VALUE_MASK 0x7f
10448#define SPI_WCL_PIPE_PERCENT_HP3D__VALUE__SHIFT 0x0
10449#define SPI_WCL_PIPE_PERCENT_HP3D__LS_GRP_VALUE_MASK 0xf80
10450#define SPI_WCL_PIPE_PERCENT_HP3D__LS_GRP_VALUE__SHIFT 0x7
10451#define SPI_WCL_PIPE_PERCENT_HP3D__HS_GRP_VALUE_MASK 0x1f000
10452#define SPI_WCL_PIPE_PERCENT_HP3D__HS_GRP_VALUE__SHIFT 0xc
10453#define SPI_WCL_PIPE_PERCENT_HP3D__ES_GRP_VALUE_MASK 0x3e0000
10454#define SPI_WCL_PIPE_PERCENT_HP3D__ES_GRP_VALUE__SHIFT 0x11
10455#define SPI_WCL_PIPE_PERCENT_HP3D__GS_GRP_VALUE_MASK 0x7c00000
10456#define SPI_WCL_PIPE_PERCENT_HP3D__GS_GRP_VALUE__SHIFT 0x16
10457#define SPI_WCL_PIPE_PERCENT_CS0__VALUE_MASK 0x7f
10458#define SPI_WCL_PIPE_PERCENT_CS0__VALUE__SHIFT 0x0
10459#define SPI_WCL_PIPE_PERCENT_CS1__VALUE_MASK 0x7f
10460#define SPI_WCL_PIPE_PERCENT_CS1__VALUE__SHIFT 0x0
10461#define SPI_WCL_PIPE_PERCENT_CS2__VALUE_MASK 0x7f
10462#define SPI_WCL_PIPE_PERCENT_CS2__VALUE__SHIFT 0x0
10463#define SPI_WCL_PIPE_PERCENT_CS3__VALUE_MASK 0x7f
10464#define SPI_WCL_PIPE_PERCENT_CS3__VALUE__SHIFT 0x0
10465#define SPI_WCL_PIPE_PERCENT_CS4__VALUE_MASK 0x7f
10466#define SPI_WCL_PIPE_PERCENT_CS4__VALUE__SHIFT 0x0
10467#define SPI_WCL_PIPE_PERCENT_CS5__VALUE_MASK 0x7f
10468#define SPI_WCL_PIPE_PERCENT_CS5__VALUE__SHIFT 0x0
10469#define SPI_WCL_PIPE_PERCENT_CS6__VALUE_MASK 0x7f
10470#define SPI_WCL_PIPE_PERCENT_CS6__VALUE__SHIFT 0x0
10471#define SPI_WCL_PIPE_PERCENT_CS7__VALUE_MASK 0x7f
10472#define SPI_WCL_PIPE_PERCENT_CS7__VALUE__SHIFT 0x0
10473#define SPI_GDBG_WAVE_CNTL__STALL_RA_MASK 0x1
10474#define SPI_GDBG_WAVE_CNTL__STALL_RA__SHIFT 0x0
10475#define SPI_GDBG_WAVE_CNTL__STALL_VMID_MASK 0x1fffe
10476#define SPI_GDBG_WAVE_CNTL__STALL_VMID__SHIFT 0x1
10477#define SPI_GDBG_TRAP_CONFIG__ME_SEL_MASK 0x3
10478#define SPI_GDBG_TRAP_CONFIG__ME_SEL__SHIFT 0x0
10479#define SPI_GDBG_TRAP_CONFIG__PIPE_SEL_MASK 0xc
10480#define SPI_GDBG_TRAP_CONFIG__PIPE_SEL__SHIFT 0x2
10481#define SPI_GDBG_TRAP_CONFIG__QUEUE_SEL_MASK 0x70
10482#define SPI_GDBG_TRAP_CONFIG__QUEUE_SEL__SHIFT 0x4
10483#define SPI_GDBG_TRAP_CONFIG__ME_MATCH_MASK 0x80
10484#define SPI_GDBG_TRAP_CONFIG__ME_MATCH__SHIFT 0x7
10485#define SPI_GDBG_TRAP_CONFIG__PIPE_MATCH_MASK 0x100
10486#define SPI_GDBG_TRAP_CONFIG__PIPE_MATCH__SHIFT 0x8
10487#define SPI_GDBG_TRAP_CONFIG__QUEUE_MATCH_MASK 0x200
10488#define SPI_GDBG_TRAP_CONFIG__QUEUE_MATCH__SHIFT 0x9
10489#define SPI_GDBG_TRAP_CONFIG__TRAP_EN_MASK 0x8000
10490#define SPI_GDBG_TRAP_CONFIG__TRAP_EN__SHIFT 0xf
10491#define SPI_GDBG_TRAP_CONFIG__VMID_SEL_MASK 0xffff0000
10492#define SPI_GDBG_TRAP_CONFIG__VMID_SEL__SHIFT 0x10
10493#define SPI_GDBG_TRAP_MASK__EXCP_EN_MASK 0x1ff
10494#define SPI_GDBG_TRAP_MASK__EXCP_EN__SHIFT 0x0
10495#define SPI_GDBG_TRAP_MASK__REPLACE_MASK 0x200
10496#define SPI_GDBG_TRAP_MASK__REPLACE__SHIFT 0x9
10497#define SPI_GDBG_TBA_LO__MEM_BASE_MASK 0xffffffff
10498#define SPI_GDBG_TBA_LO__MEM_BASE__SHIFT 0x0
10499#define SPI_GDBG_TBA_HI__MEM_BASE_MASK 0xff
10500#define SPI_GDBG_TBA_HI__MEM_BASE__SHIFT 0x0
10501#define SPI_GDBG_TMA_LO__MEM_BASE_MASK 0xffffffff
10502#define SPI_GDBG_TMA_LO__MEM_BASE__SHIFT 0x0
10503#define SPI_GDBG_TMA_HI__MEM_BASE_MASK 0xff
10504#define SPI_GDBG_TMA_HI__MEM_BASE__SHIFT 0x0
10505#define SPI_GDBG_TRAP_DATA0__DATA_MASK 0xffffffff
10506#define SPI_GDBG_TRAP_DATA0__DATA__SHIFT 0x0
10507#define SPI_GDBG_TRAP_DATA1__DATA_MASK 0xffffffff
10508#define SPI_GDBG_TRAP_DATA1__DATA__SHIFT 0x0
10509#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_MASK 0x1
10510#define SPI_RESET_DEBUG__DISABLE_GFX_RESET__SHIFT 0x0
10511#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PER_VMID_MASK 0x2
10512#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PER_VMID__SHIFT 0x1
10513#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_ALL_VMID_MASK 0x4
10514#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_ALL_VMID__SHIFT 0x2
10515#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_RESOURCE_MASK 0x8
10516#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_RESOURCE__SHIFT 0x3
10517#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PRIORITY_MASK 0x10
10518#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PRIORITY__SHIFT 0x4
10519#define SPI_COMPUTE_QUEUE_RESET__RESET_MASK 0x1
10520#define SPI_COMPUTE_QUEUE_RESET__RESET__SHIFT 0x0
10521#define SPI_RESOURCE_RESERVE_CU_0__VGPR_MASK 0xf
10522#define SPI_RESOURCE_RESERVE_CU_0__VGPR__SHIFT 0x0
10523#define SPI_RESOURCE_RESERVE_CU_0__SGPR_MASK 0xf0
10524#define SPI_RESOURCE_RESERVE_CU_0__SGPR__SHIFT 0x4
10525#define SPI_RESOURCE_RESERVE_CU_0__LDS_MASK 0xf00
10526#define SPI_RESOURCE_RESERVE_CU_0__LDS__SHIFT 0x8
10527#define SPI_RESOURCE_RESERVE_CU_0__WAVES_MASK 0x7000
10528#define SPI_RESOURCE_RESERVE_CU_0__WAVES__SHIFT 0xc
10529#define SPI_RESOURCE_RESERVE_CU_0__BARRIERS_MASK 0x78000
10530#define SPI_RESOURCE_RESERVE_CU_0__BARRIERS__SHIFT 0xf
10531#define SPI_RESOURCE_RESERVE_CU_1__VGPR_MASK 0xf
10532#define SPI_RESOURCE_RESERVE_CU_1__VGPR__SHIFT 0x0
10533#define SPI_RESOURCE_RESERVE_CU_1__SGPR_MASK 0xf0
10534#define SPI_RESOURCE_RESERVE_CU_1__SGPR__SHIFT 0x4
10535#define SPI_RESOURCE_RESERVE_CU_1__LDS_MASK 0xf00
10536#define SPI_RESOURCE_RESERVE_CU_1__LDS__SHIFT 0x8
10537#define SPI_RESOURCE_RESERVE_CU_1__WAVES_MASK 0x7000
10538#define SPI_RESOURCE_RESERVE_CU_1__WAVES__SHIFT 0xc
10539#define SPI_RESOURCE_RESERVE_CU_1__BARRIERS_MASK 0x78000
10540#define SPI_RESOURCE_RESERVE_CU_1__BARRIERS__SHIFT 0xf
10541#define SPI_RESOURCE_RESERVE_CU_2__VGPR_MASK 0xf
10542#define SPI_RESOURCE_RESERVE_CU_2__VGPR__SHIFT 0x0
10543#define SPI_RESOURCE_RESERVE_CU_2__SGPR_MASK 0xf0
10544#define SPI_RESOURCE_RESERVE_CU_2__SGPR__SHIFT 0x4
10545#define SPI_RESOURCE_RESERVE_CU_2__LDS_MASK 0xf00
10546#define SPI_RESOURCE_RESERVE_CU_2__LDS__SHIFT 0x8
10547#define SPI_RESOURCE_RESERVE_CU_2__WAVES_MASK 0x7000
10548#define SPI_RESOURCE_RESERVE_CU_2__WAVES__SHIFT 0xc
10549#define SPI_RESOURCE_RESERVE_CU_2__BARRIERS_MASK 0x78000
10550#define SPI_RESOURCE_RESERVE_CU_2__BARRIERS__SHIFT 0xf
10551#define SPI_RESOURCE_RESERVE_CU_3__VGPR_MASK 0xf
10552#define SPI_RESOURCE_RESERVE_CU_3__VGPR__SHIFT 0x0
10553#define SPI_RESOURCE_RESERVE_CU_3__SGPR_MASK 0xf0
10554#define SPI_RESOURCE_RESERVE_CU_3__SGPR__SHIFT 0x4
10555#define SPI_RESOURCE_RESERVE_CU_3__LDS_MASK 0xf00
10556#define SPI_RESOURCE_RESERVE_CU_3__LDS__SHIFT 0x8
10557#define SPI_RESOURCE_RESERVE_CU_3__WAVES_MASK 0x7000
10558#define SPI_RESOURCE_RESERVE_CU_3__WAVES__SHIFT 0xc
10559#define SPI_RESOURCE_RESERVE_CU_3__BARRIERS_MASK 0x78000
10560#define SPI_RESOURCE_RESERVE_CU_3__BARRIERS__SHIFT 0xf
10561#define SPI_RESOURCE_RESERVE_CU_4__VGPR_MASK 0xf
10562#define SPI_RESOURCE_RESERVE_CU_4__VGPR__SHIFT 0x0
10563#define SPI_RESOURCE_RESERVE_CU_4__SGPR_MASK 0xf0
10564#define SPI_RESOURCE_RESERVE_CU_4__SGPR__SHIFT 0x4
10565#define SPI_RESOURCE_RESERVE_CU_4__LDS_MASK 0xf00
10566#define SPI_RESOURCE_RESERVE_CU_4__LDS__SHIFT 0x8
10567#define SPI_RESOURCE_RESERVE_CU_4__WAVES_MASK 0x7000
10568#define SPI_RESOURCE_RESERVE_CU_4__WAVES__SHIFT 0xc
10569#define SPI_RESOURCE_RESERVE_CU_4__BARRIERS_MASK 0x78000
10570#define SPI_RESOURCE_RESERVE_CU_4__BARRIERS__SHIFT 0xf
10571#define SPI_RESOURCE_RESERVE_CU_5__VGPR_MASK 0xf
10572#define SPI_RESOURCE_RESERVE_CU_5__VGPR__SHIFT 0x0
10573#define SPI_RESOURCE_RESERVE_CU_5__SGPR_MASK 0xf0
10574#define SPI_RESOURCE_RESERVE_CU_5__SGPR__SHIFT 0x4
10575#define SPI_RESOURCE_RESERVE_CU_5__LDS_MASK 0xf00
10576#define SPI_RESOURCE_RESERVE_CU_5__LDS__SHIFT 0x8
10577#define SPI_RESOURCE_RESERVE_CU_5__WAVES_MASK 0x7000
10578#define SPI_RESOURCE_RESERVE_CU_5__WAVES__SHIFT 0xc
10579#define SPI_RESOURCE_RESERVE_CU_5__BARRIERS_MASK 0x78000
10580#define SPI_RESOURCE_RESERVE_CU_5__BARRIERS__SHIFT 0xf
10581#define SPI_RESOURCE_RESERVE_CU_6__VGPR_MASK 0xf
10582#define SPI_RESOURCE_RESERVE_CU_6__VGPR__SHIFT 0x0
10583#define SPI_RESOURCE_RESERVE_CU_6__SGPR_MASK 0xf0
10584#define SPI_RESOURCE_RESERVE_CU_6__SGPR__SHIFT 0x4
10585#define SPI_RESOURCE_RESERVE_CU_6__LDS_MASK 0xf00
10586#define SPI_RESOURCE_RESERVE_CU_6__LDS__SHIFT 0x8
10587#define SPI_RESOURCE_RESERVE_CU_6__WAVES_MASK 0x7000
10588#define SPI_RESOURCE_RESERVE_CU_6__WAVES__SHIFT 0xc
10589#define SPI_RESOURCE_RESERVE_CU_6__BARRIERS_MASK 0x78000
10590#define SPI_RESOURCE_RESERVE_CU_6__BARRIERS__SHIFT 0xf
10591#define SPI_RESOURCE_RESERVE_CU_7__VGPR_MASK 0xf
10592#define SPI_RESOURCE_RESERVE_CU_7__VGPR__SHIFT 0x0
10593#define SPI_RESOURCE_RESERVE_CU_7__SGPR_MASK 0xf0
10594#define SPI_RESOURCE_RESERVE_CU_7__SGPR__SHIFT 0x4
10595#define SPI_RESOURCE_RESERVE_CU_7__LDS_MASK 0xf00
10596#define SPI_RESOURCE_RESERVE_CU_7__LDS__SHIFT 0x8
10597#define SPI_RESOURCE_RESERVE_CU_7__WAVES_MASK 0x7000
10598#define SPI_RESOURCE_RESERVE_CU_7__WAVES__SHIFT 0xc
10599#define SPI_RESOURCE_RESERVE_CU_7__BARRIERS_MASK 0x78000
10600#define SPI_RESOURCE_RESERVE_CU_7__BARRIERS__SHIFT 0xf
10601#define SPI_RESOURCE_RESERVE_CU_8__VGPR_MASK 0xf
10602#define SPI_RESOURCE_RESERVE_CU_8__VGPR__SHIFT 0x0
10603#define SPI_RESOURCE_RESERVE_CU_8__SGPR_MASK 0xf0
10604#define SPI_RESOURCE_RESERVE_CU_8__SGPR__SHIFT 0x4
10605#define SPI_RESOURCE_RESERVE_CU_8__LDS_MASK 0xf00
10606#define SPI_RESOURCE_RESERVE_CU_8__LDS__SHIFT 0x8
10607#define SPI_RESOURCE_RESERVE_CU_8__WAVES_MASK 0x7000
10608#define SPI_RESOURCE_RESERVE_CU_8__WAVES__SHIFT 0xc
10609#define SPI_RESOURCE_RESERVE_CU_8__BARRIERS_MASK 0x78000
10610#define SPI_RESOURCE_RESERVE_CU_8__BARRIERS__SHIFT 0xf
10611#define SPI_RESOURCE_RESERVE_CU_9__VGPR_MASK 0xf
10612#define SPI_RESOURCE_RESERVE_CU_9__VGPR__SHIFT 0x0
10613#define SPI_RESOURCE_RESERVE_CU_9__SGPR_MASK 0xf0
10614#define SPI_RESOURCE_RESERVE_CU_9__SGPR__SHIFT 0x4
10615#define SPI_RESOURCE_RESERVE_CU_9__LDS_MASK 0xf00
10616#define SPI_RESOURCE_RESERVE_CU_9__LDS__SHIFT 0x8
10617#define SPI_RESOURCE_RESERVE_CU_9__WAVES_MASK 0x7000
10618#define SPI_RESOURCE_RESERVE_CU_9__WAVES__SHIFT 0xc
10619#define SPI_RESOURCE_RESERVE_CU_9__BARRIERS_MASK 0x78000
10620#define SPI_RESOURCE_RESERVE_CU_9__BARRIERS__SHIFT 0xf
10621#define SPI_RESOURCE_RESERVE_CU_10__VGPR_MASK 0xf
10622#define SPI_RESOURCE_RESERVE_CU_10__VGPR__SHIFT 0x0
10623#define SPI_RESOURCE_RESERVE_CU_10__SGPR_MASK 0xf0
10624#define SPI_RESOURCE_RESERVE_CU_10__SGPR__SHIFT 0x4
10625#define SPI_RESOURCE_RESERVE_CU_10__LDS_MASK 0xf00
10626#define SPI_RESOURCE_RESERVE_CU_10__LDS__SHIFT 0x8
10627#define SPI_RESOURCE_RESERVE_CU_10__WAVES_MASK 0x7000
10628#define SPI_RESOURCE_RESERVE_CU_10__WAVES__SHIFT 0xc
10629#define SPI_RESOURCE_RESERVE_CU_10__BARRIERS_MASK 0x78000
10630#define SPI_RESOURCE_RESERVE_CU_10__BARRIERS__SHIFT 0xf
10631#define SPI_RESOURCE_RESERVE_CU_11__VGPR_MASK 0xf
10632#define SPI_RESOURCE_RESERVE_CU_11__VGPR__SHIFT 0x0
10633#define SPI_RESOURCE_RESERVE_CU_11__SGPR_MASK 0xf0
10634#define SPI_RESOURCE_RESERVE_CU_11__SGPR__SHIFT 0x4
10635#define SPI_RESOURCE_RESERVE_CU_11__LDS_MASK 0xf00
10636#define SPI_RESOURCE_RESERVE_CU_11__LDS__SHIFT 0x8
10637#define SPI_RESOURCE_RESERVE_CU_11__WAVES_MASK 0x7000
10638#define SPI_RESOURCE_RESERVE_CU_11__WAVES__SHIFT 0xc
10639#define SPI_RESOURCE_RESERVE_CU_11__BARRIERS_MASK 0x78000
10640#define SPI_RESOURCE_RESERVE_CU_11__BARRIERS__SHIFT 0xf
10641#define SPI_RESOURCE_RESERVE_CU_12__VGPR_MASK 0xf
10642#define SPI_RESOURCE_RESERVE_CU_12__VGPR__SHIFT 0x0
10643#define SPI_RESOURCE_RESERVE_CU_12__SGPR_MASK 0xf0
10644#define SPI_RESOURCE_RESERVE_CU_12__SGPR__SHIFT 0x4
10645#define SPI_RESOURCE_RESERVE_CU_12__LDS_MASK 0xf00
10646#define SPI_RESOURCE_RESERVE_CU_12__LDS__SHIFT 0x8
10647#define SPI_RESOURCE_RESERVE_CU_12__WAVES_MASK 0x7000
10648#define SPI_RESOURCE_RESERVE_CU_12__WAVES__SHIFT 0xc
10649#define SPI_RESOURCE_RESERVE_CU_12__BARRIERS_MASK 0x78000
10650#define SPI_RESOURCE_RESERVE_CU_12__BARRIERS__SHIFT 0xf
10651#define SPI_RESOURCE_RESERVE_CU_13__VGPR_MASK 0xf
10652#define SPI_RESOURCE_RESERVE_CU_13__VGPR__SHIFT 0x0
10653#define SPI_RESOURCE_RESERVE_CU_13__SGPR_MASK 0xf0
10654#define SPI_RESOURCE_RESERVE_CU_13__SGPR__SHIFT 0x4
10655#define SPI_RESOURCE_RESERVE_CU_13__LDS_MASK 0xf00
10656#define SPI_RESOURCE_RESERVE_CU_13__LDS__SHIFT 0x8
10657#define SPI_RESOURCE_RESERVE_CU_13__WAVES_MASK 0x7000
10658#define SPI_RESOURCE_RESERVE_CU_13__WAVES__SHIFT 0xc
10659#define SPI_RESOURCE_RESERVE_CU_13__BARRIERS_MASK 0x78000
10660#define SPI_RESOURCE_RESERVE_CU_13__BARRIERS__SHIFT 0xf
10661#define SPI_RESOURCE_RESERVE_CU_14__VGPR_MASK 0xf
10662#define SPI_RESOURCE_RESERVE_CU_14__VGPR__SHIFT 0x0
10663#define SPI_RESOURCE_RESERVE_CU_14__SGPR_MASK 0xf0
10664#define SPI_RESOURCE_RESERVE_CU_14__SGPR__SHIFT 0x4
10665#define SPI_RESOURCE_RESERVE_CU_14__LDS_MASK 0xf00
10666#define SPI_RESOURCE_RESERVE_CU_14__LDS__SHIFT 0x8
10667#define SPI_RESOURCE_RESERVE_CU_14__WAVES_MASK 0x7000
10668#define SPI_RESOURCE_RESERVE_CU_14__WAVES__SHIFT 0xc
10669#define SPI_RESOURCE_RESERVE_CU_14__BARRIERS_MASK 0x78000
10670#define SPI_RESOURCE_RESERVE_CU_14__BARRIERS__SHIFT 0xf
10671#define SPI_RESOURCE_RESERVE_CU_15__VGPR_MASK 0xf
10672#define SPI_RESOURCE_RESERVE_CU_15__VGPR__SHIFT 0x0
10673#define SPI_RESOURCE_RESERVE_CU_15__SGPR_MASK 0xf0
10674#define SPI_RESOURCE_RESERVE_CU_15__SGPR__SHIFT 0x4
10675#define SPI_RESOURCE_RESERVE_CU_15__LDS_MASK 0xf00
10676#define SPI_RESOURCE_RESERVE_CU_15__LDS__SHIFT 0x8
10677#define SPI_RESOURCE_RESERVE_CU_15__WAVES_MASK 0x7000
10678#define SPI_RESOURCE_RESERVE_CU_15__WAVES__SHIFT 0xc
10679#define SPI_RESOURCE_RESERVE_CU_15__BARRIERS_MASK 0x78000
10680#define SPI_RESOURCE_RESERVE_CU_15__BARRIERS__SHIFT 0xf
10681#define SPI_RESOURCE_RESERVE_EN_CU_0__EN_MASK 0x1
10682#define SPI_RESOURCE_RESERVE_EN_CU_0__EN__SHIFT 0x0
10683#define SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK_MASK 0xfffe
10684#define SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK__SHIFT 0x1
10685#define SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK_MASK 0xff0000
10686#define SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK__SHIFT 0x10
10687#define SPI_RESOURCE_RESERVE_EN_CU_0__RESERVE_SPACE_ONLY_MASK 0x1000000
10688#define SPI_RESOURCE_RESERVE_EN_CU_0__RESERVE_SPACE_ONLY__SHIFT 0x18
10689#define SPI_RESOURCE_RESERVE_EN_CU_1__EN_MASK 0x1
10690#define SPI_RESOURCE_RESERVE_EN_CU_1__EN__SHIFT 0x0
10691#define SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK_MASK 0xfffe
10692#define SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK__SHIFT 0x1
10693#define SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK_MASK 0xff0000
10694#define SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK__SHIFT 0x10
10695#define SPI_RESOURCE_RESERVE_EN_CU_1__RESERVE_SPACE_ONLY_MASK 0x1000000
10696#define SPI_RESOURCE_RESERVE_EN_CU_1__RESERVE_SPACE_ONLY__SHIFT 0x18
10697#define SPI_RESOURCE_RESERVE_EN_CU_2__EN_MASK 0x1
10698#define SPI_RESOURCE_RESERVE_EN_CU_2__EN__SHIFT 0x0
10699#define SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK_MASK 0xfffe
10700#define SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK__SHIFT 0x1
10701#define SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK_MASK 0xff0000
10702#define SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK__SHIFT 0x10
10703#define SPI_RESOURCE_RESERVE_EN_CU_2__RESERVE_SPACE_ONLY_MASK 0x1000000
10704#define SPI_RESOURCE_RESERVE_EN_CU_2__RESERVE_SPACE_ONLY__SHIFT 0x18
10705#define SPI_RESOURCE_RESERVE_EN_CU_3__EN_MASK 0x1
10706#define SPI_RESOURCE_RESERVE_EN_CU_3__EN__SHIFT 0x0
10707#define SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK_MASK 0xfffe
10708#define SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK__SHIFT 0x1
10709#define SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK_MASK 0xff0000
10710#define SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK__SHIFT 0x10
10711#define SPI_RESOURCE_RESERVE_EN_CU_3__RESERVE_SPACE_ONLY_MASK 0x1000000
10712#define SPI_RESOURCE_RESERVE_EN_CU_3__RESERVE_SPACE_ONLY__SHIFT 0x18
10713#define SPI_RESOURCE_RESERVE_EN_CU_4__EN_MASK 0x1
10714#define SPI_RESOURCE_RESERVE_EN_CU_4__EN__SHIFT 0x0
10715#define SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK_MASK 0xfffe
10716#define SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK__SHIFT 0x1
10717#define SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK_MASK 0xff0000
10718#define SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK__SHIFT 0x10
10719#define SPI_RESOURCE_RESERVE_EN_CU_4__RESERVE_SPACE_ONLY_MASK 0x1000000
10720#define SPI_RESOURCE_RESERVE_EN_CU_4__RESERVE_SPACE_ONLY__SHIFT 0x18
10721#define SPI_RESOURCE_RESERVE_EN_CU_5__EN_MASK 0x1
10722#define SPI_RESOURCE_RESERVE_EN_CU_5__EN__SHIFT 0x0
10723#define SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK_MASK 0xfffe
10724#define SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK__SHIFT 0x1
10725#define SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK_MASK 0xff0000
10726#define SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK__SHIFT 0x10
10727#define SPI_RESOURCE_RESERVE_EN_CU_5__RESERVE_SPACE_ONLY_MASK 0x1000000
10728#define SPI_RESOURCE_RESERVE_EN_CU_5__RESERVE_SPACE_ONLY__SHIFT 0x18
10729#define SPI_RESOURCE_RESERVE_EN_CU_6__EN_MASK 0x1
10730#define SPI_RESOURCE_RESERVE_EN_CU_6__EN__SHIFT 0x0
10731#define SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK_MASK 0xfffe
10732#define SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK__SHIFT 0x1
10733#define SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK_MASK 0xff0000
10734#define SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK__SHIFT 0x10
10735#define SPI_RESOURCE_RESERVE_EN_CU_6__RESERVE_SPACE_ONLY_MASK 0x1000000
10736#define SPI_RESOURCE_RESERVE_EN_CU_6__RESERVE_SPACE_ONLY__SHIFT 0x18
10737#define SPI_RESOURCE_RESERVE_EN_CU_7__EN_MASK 0x1
10738#define SPI_RESOURCE_RESERVE_EN_CU_7__EN__SHIFT 0x0
10739#define SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK_MASK 0xfffe
10740#define SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK__SHIFT 0x1
10741#define SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK_MASK 0xff0000
10742#define SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK__SHIFT 0x10
10743#define SPI_RESOURCE_RESERVE_EN_CU_7__RESERVE_SPACE_ONLY_MASK 0x1000000
10744#define SPI_RESOURCE_RESERVE_EN_CU_7__RESERVE_SPACE_ONLY__SHIFT 0x18
10745#define SPI_RESOURCE_RESERVE_EN_CU_8__EN_MASK 0x1
10746#define SPI_RESOURCE_RESERVE_EN_CU_8__EN__SHIFT 0x0
10747#define SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK_MASK 0xfffe
10748#define SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK__SHIFT 0x1
10749#define SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK_MASK 0xff0000
10750#define SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK__SHIFT 0x10
10751#define SPI_RESOURCE_RESERVE_EN_CU_8__RESERVE_SPACE_ONLY_MASK 0x1000000
10752#define SPI_RESOURCE_RESERVE_EN_CU_8__RESERVE_SPACE_ONLY__SHIFT 0x18
10753#define SPI_RESOURCE_RESERVE_EN_CU_9__EN_MASK 0x1
10754#define SPI_RESOURCE_RESERVE_EN_CU_9__EN__SHIFT 0x0
10755#define SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK_MASK 0xfffe
10756#define SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK__SHIFT 0x1
10757#define SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK_MASK 0xff0000
10758#define SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK__SHIFT 0x10
10759#define SPI_RESOURCE_RESERVE_EN_CU_9__RESERVE_SPACE_ONLY_MASK 0x1000000
10760#define SPI_RESOURCE_RESERVE_EN_CU_9__RESERVE_SPACE_ONLY__SHIFT 0x18
10761#define SPI_RESOURCE_RESERVE_EN_CU_10__EN_MASK 0x1
10762#define SPI_RESOURCE_RESERVE_EN_CU_10__EN__SHIFT 0x0
10763#define SPI_RESOURCE_RESERVE_EN_CU_10__TYPE_MASK_MASK 0xfffe
10764#define SPI_RESOURCE_RESERVE_EN_CU_10__TYPE_MASK__SHIFT 0x1
10765#define SPI_RESOURCE_RESERVE_EN_CU_10__QUEUE_MASK_MASK 0xff0000
10766#define SPI_RESOURCE_RESERVE_EN_CU_10__QUEUE_MASK__SHIFT 0x10
10767#define SPI_RESOURCE_RESERVE_EN_CU_10__RESERVE_SPACE_ONLY_MASK 0x1000000
10768#define SPI_RESOURCE_RESERVE_EN_CU_10__RESERVE_SPACE_ONLY__SHIFT 0x18
10769#define SPI_RESOURCE_RESERVE_EN_CU_11__EN_MASK 0x1
10770#define SPI_RESOURCE_RESERVE_EN_CU_11__EN__SHIFT 0x0
10771#define SPI_RESOURCE_RESERVE_EN_CU_11__TYPE_MASK_MASK 0xfffe
10772#define SPI_RESOURCE_RESERVE_EN_CU_11__TYPE_MASK__SHIFT 0x1
10773#define SPI_RESOURCE_RESERVE_EN_CU_11__QUEUE_MASK_MASK 0xff0000
10774#define SPI_RESOURCE_RESERVE_EN_CU_11__QUEUE_MASK__SHIFT 0x10
10775#define SPI_RESOURCE_RESERVE_EN_CU_11__RESERVE_SPACE_ONLY