1 | /* |
2 | * Copyright 2020 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included in |
12 | * all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * |
22 | * |
23 | */ |
24 | #ifndef _mp_13_0_4_SH_MASK_HEADER |
25 | #define |
26 | |
27 | |
28 | // addressBlock: mp_SmuMp0_SmnDec |
29 | //MP0_SMN_C2PMSG_32 |
30 | #define MP0_SMN_C2PMSG_32__CONTENT__SHIFT 0x0 |
31 | #define MP0_SMN_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL |
32 | //MP0_SMN_C2PMSG_33 |
33 | #define MP0_SMN_C2PMSG_33__CONTENT__SHIFT 0x0 |
34 | #define MP0_SMN_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL |
35 | //MP0_SMN_C2PMSG_34 |
36 | #define MP0_SMN_C2PMSG_34__CONTENT__SHIFT 0x0 |
37 | #define MP0_SMN_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL |
38 | //MP0_SMN_C2PMSG_35 |
39 | #define MP0_SMN_C2PMSG_35__CONTENT__SHIFT 0x0 |
40 | #define MP0_SMN_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL |
41 | //MP0_SMN_C2PMSG_36 |
42 | #define MP0_SMN_C2PMSG_36__CONTENT__SHIFT 0x0 |
43 | #define MP0_SMN_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL |
44 | //MP0_SMN_C2PMSG_37 |
45 | #define MP0_SMN_C2PMSG_37__CONTENT__SHIFT 0x0 |
46 | #define MP0_SMN_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL |
47 | //MP0_SMN_C2PMSG_38 |
48 | #define MP0_SMN_C2PMSG_38__CONTENT__SHIFT 0x0 |
49 | #define MP0_SMN_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL |
50 | //MP0_SMN_C2PMSG_39 |
51 | #define MP0_SMN_C2PMSG_39__CONTENT__SHIFT 0x0 |
52 | #define MP0_SMN_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL |
53 | //MP0_SMN_C2PMSG_40 |
54 | #define MP0_SMN_C2PMSG_40__CONTENT__SHIFT 0x0 |
55 | #define MP0_SMN_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL |
56 | //MP0_SMN_C2PMSG_41 |
57 | #define MP0_SMN_C2PMSG_41__CONTENT__SHIFT 0x0 |
58 | #define MP0_SMN_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL |
59 | //MP0_SMN_C2PMSG_42 |
60 | #define MP0_SMN_C2PMSG_42__CONTENT__SHIFT 0x0 |
61 | #define MP0_SMN_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL |
62 | //MP0_SMN_C2PMSG_43 |
63 | #define MP0_SMN_C2PMSG_43__CONTENT__SHIFT 0x0 |
64 | #define MP0_SMN_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL |
65 | //MP0_SMN_C2PMSG_44 |
66 | #define MP0_SMN_C2PMSG_44__CONTENT__SHIFT 0x0 |
67 | #define MP0_SMN_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL |
68 | //MP0_SMN_C2PMSG_45 |
69 | #define MP0_SMN_C2PMSG_45__CONTENT__SHIFT 0x0 |
70 | #define MP0_SMN_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL |
71 | //MP0_SMN_C2PMSG_46 |
72 | #define MP0_SMN_C2PMSG_46__CONTENT__SHIFT 0x0 |
73 | #define MP0_SMN_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL |
74 | //MP0_SMN_C2PMSG_47 |
75 | #define MP0_SMN_C2PMSG_47__CONTENT__SHIFT 0x0 |
76 | #define MP0_SMN_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL |
77 | //MP0_SMN_C2PMSG_48 |
78 | #define MP0_SMN_C2PMSG_48__CONTENT__SHIFT 0x0 |
79 | #define MP0_SMN_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL |
80 | //MP0_SMN_C2PMSG_49 |
81 | #define MP0_SMN_C2PMSG_49__CONTENT__SHIFT 0x0 |
82 | #define MP0_SMN_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL |
83 | //MP0_SMN_C2PMSG_50 |
84 | #define MP0_SMN_C2PMSG_50__CONTENT__SHIFT 0x0 |
85 | #define MP0_SMN_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL |
86 | //MP0_SMN_C2PMSG_51 |
87 | #define MP0_SMN_C2PMSG_51__CONTENT__SHIFT 0x0 |
88 | #define MP0_SMN_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL |
89 | //MP0_SMN_C2PMSG_52 |
90 | #define MP0_SMN_C2PMSG_52__CONTENT__SHIFT 0x0 |
91 | #define MP0_SMN_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL |
92 | //MP0_SMN_C2PMSG_53 |
93 | #define MP0_SMN_C2PMSG_53__CONTENT__SHIFT 0x0 |
94 | #define MP0_SMN_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL |
95 | //MP0_SMN_C2PMSG_54 |
96 | #define MP0_SMN_C2PMSG_54__CONTENT__SHIFT 0x0 |
97 | #define MP0_SMN_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL |
98 | //MP0_SMN_C2PMSG_55 |
99 | #define MP0_SMN_C2PMSG_55__CONTENT__SHIFT 0x0 |
100 | #define MP0_SMN_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL |
101 | //MP0_SMN_C2PMSG_56 |
102 | #define MP0_SMN_C2PMSG_56__CONTENT__SHIFT 0x0 |
103 | #define MP0_SMN_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL |
104 | //MP0_SMN_C2PMSG_57 |
105 | #define MP0_SMN_C2PMSG_57__CONTENT__SHIFT 0x0 |
106 | #define MP0_SMN_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL |
107 | //MP0_SMN_C2PMSG_58 |
108 | #define MP0_SMN_C2PMSG_58__CONTENT__SHIFT 0x0 |
109 | #define MP0_SMN_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL |
110 | //MP0_SMN_C2PMSG_59 |
111 | #define MP0_SMN_C2PMSG_59__CONTENT__SHIFT 0x0 |
112 | #define MP0_SMN_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL |
113 | //MP0_SMN_C2PMSG_60 |
114 | #define MP0_SMN_C2PMSG_60__CONTENT__SHIFT 0x0 |
115 | #define MP0_SMN_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL |
116 | //MP0_SMN_C2PMSG_61 |
117 | #define MP0_SMN_C2PMSG_61__CONTENT__SHIFT 0x0 |
118 | #define MP0_SMN_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL |
119 | //MP0_SMN_C2PMSG_62 |
120 | #define MP0_SMN_C2PMSG_62__CONTENT__SHIFT 0x0 |
121 | #define MP0_SMN_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL |
122 | //MP0_SMN_C2PMSG_63 |
123 | #define MP0_SMN_C2PMSG_63__CONTENT__SHIFT 0x0 |
124 | #define MP0_SMN_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL |
125 | //MP0_SMN_C2PMSG_64 |
126 | #define MP0_SMN_C2PMSG_64__CONTENT__SHIFT 0x0 |
127 | #define MP0_SMN_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL |
128 | //MP0_SMN_C2PMSG_65 |
129 | #define MP0_SMN_C2PMSG_65__CONTENT__SHIFT 0x0 |
130 | #define MP0_SMN_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL |
131 | //MP0_SMN_C2PMSG_66 |
132 | #define MP0_SMN_C2PMSG_66__CONTENT__SHIFT 0x0 |
133 | #define MP0_SMN_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL |
134 | //MP0_SMN_C2PMSG_67 |
135 | #define MP0_SMN_C2PMSG_67__CONTENT__SHIFT 0x0 |
136 | #define MP0_SMN_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL |
137 | //MP0_SMN_C2PMSG_68 |
138 | #define MP0_SMN_C2PMSG_68__CONTENT__SHIFT 0x0 |
139 | #define MP0_SMN_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL |
140 | //MP0_SMN_C2PMSG_69 |
141 | #define MP0_SMN_C2PMSG_69__CONTENT__SHIFT 0x0 |
142 | #define MP0_SMN_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL |
143 | //MP0_SMN_C2PMSG_70 |
144 | #define MP0_SMN_C2PMSG_70__CONTENT__SHIFT 0x0 |
145 | #define MP0_SMN_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL |
146 | //MP0_SMN_C2PMSG_71 |
147 | #define MP0_SMN_C2PMSG_71__CONTENT__SHIFT 0x0 |
148 | #define MP0_SMN_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL |
149 | //MP0_SMN_C2PMSG_72 |
150 | #define MP0_SMN_C2PMSG_72__CONTENT__SHIFT 0x0 |
151 | #define MP0_SMN_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL |
152 | //MP0_SMN_C2PMSG_73 |
153 | #define MP0_SMN_C2PMSG_73__CONTENT__SHIFT 0x0 |
154 | #define MP0_SMN_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL |
155 | //MP0_SMN_C2PMSG_74 |
156 | #define MP0_SMN_C2PMSG_74__CONTENT__SHIFT 0x0 |
157 | #define MP0_SMN_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL |
158 | //MP0_SMN_C2PMSG_75 |
159 | #define MP0_SMN_C2PMSG_75__CONTENT__SHIFT 0x0 |
160 | #define MP0_SMN_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL |
161 | //MP0_SMN_C2PMSG_76 |
162 | #define MP0_SMN_C2PMSG_76__CONTENT__SHIFT 0x0 |
163 | #define MP0_SMN_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL |
164 | //MP0_SMN_C2PMSG_77 |
165 | #define MP0_SMN_C2PMSG_77__CONTENT__SHIFT 0x0 |
166 | #define MP0_SMN_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL |
167 | //MP0_SMN_C2PMSG_78 |
168 | #define MP0_SMN_C2PMSG_78__CONTENT__SHIFT 0x0 |
169 | #define MP0_SMN_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL |
170 | //MP0_SMN_C2PMSG_79 |
171 | #define MP0_SMN_C2PMSG_79__CONTENT__SHIFT 0x0 |
172 | #define MP0_SMN_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL |
173 | //MP0_SMN_C2PMSG_80 |
174 | #define MP0_SMN_C2PMSG_80__CONTENT__SHIFT 0x0 |
175 | #define MP0_SMN_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL |
176 | //MP0_SMN_C2PMSG_81 |
177 | #define MP0_SMN_C2PMSG_81__CONTENT__SHIFT 0x0 |
178 | #define MP0_SMN_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL |
179 | //MP0_SMN_C2PMSG_82 |
180 | #define MP0_SMN_C2PMSG_82__CONTENT__SHIFT 0x0 |
181 | #define MP0_SMN_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL |
182 | //MP0_SMN_C2PMSG_83 |
183 | #define MP0_SMN_C2PMSG_83__CONTENT__SHIFT 0x0 |
184 | #define MP0_SMN_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL |
185 | //MP0_SMN_C2PMSG_84 |
186 | #define MP0_SMN_C2PMSG_84__CONTENT__SHIFT 0x0 |
187 | #define MP0_SMN_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL |
188 | //MP0_SMN_C2PMSG_85 |
189 | #define MP0_SMN_C2PMSG_85__CONTENT__SHIFT 0x0 |
190 | #define MP0_SMN_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL |
191 | //MP0_SMN_C2PMSG_86 |
192 | #define MP0_SMN_C2PMSG_86__CONTENT__SHIFT 0x0 |
193 | #define MP0_SMN_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL |
194 | //MP0_SMN_C2PMSG_87 |
195 | #define MP0_SMN_C2PMSG_87__CONTENT__SHIFT 0x0 |
196 | #define MP0_SMN_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL |
197 | //MP0_SMN_C2PMSG_88 |
198 | #define MP0_SMN_C2PMSG_88__CONTENT__SHIFT 0x0 |
199 | #define MP0_SMN_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL |
200 | //MP0_SMN_C2PMSG_89 |
201 | #define MP0_SMN_C2PMSG_89__CONTENT__SHIFT 0x0 |
202 | #define MP0_SMN_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL |
203 | //MP0_SMN_C2PMSG_90 |
204 | #define MP0_SMN_C2PMSG_90__CONTENT__SHIFT 0x0 |
205 | #define MP0_SMN_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL |
206 | //MP0_SMN_C2PMSG_91 |
207 | #define MP0_SMN_C2PMSG_91__CONTENT__SHIFT 0x0 |
208 | #define MP0_SMN_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL |
209 | //MP0_SMN_C2PMSG_92 |
210 | #define MP0_SMN_C2PMSG_92__CONTENT__SHIFT 0x0 |
211 | #define MP0_SMN_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL |
212 | //MP0_SMN_C2PMSG_93 |
213 | #define MP0_SMN_C2PMSG_93__CONTENT__SHIFT 0x0 |
214 | #define MP0_SMN_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL |
215 | //MP0_SMN_C2PMSG_94 |
216 | #define MP0_SMN_C2PMSG_94__CONTENT__SHIFT 0x0 |
217 | #define MP0_SMN_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL |
218 | //MP0_SMN_C2PMSG_95 |
219 | #define MP0_SMN_C2PMSG_95__CONTENT__SHIFT 0x0 |
220 | #define MP0_SMN_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL |
221 | //MP0_SMN_C2PMSG_96 |
222 | #define MP0_SMN_C2PMSG_96__CONTENT__SHIFT 0x0 |
223 | #define MP0_SMN_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL |
224 | //MP0_SMN_C2PMSG_97 |
225 | #define MP0_SMN_C2PMSG_97__CONTENT__SHIFT 0x0 |
226 | #define MP0_SMN_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL |
227 | //MP0_SMN_C2PMSG_98 |
228 | #define MP0_SMN_C2PMSG_98__CONTENT__SHIFT 0x0 |
229 | #define MP0_SMN_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL |
230 | //MP0_SMN_C2PMSG_99 |
231 | #define MP0_SMN_C2PMSG_99__CONTENT__SHIFT 0x0 |
232 | #define MP0_SMN_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL |
233 | //MP0_SMN_C2PMSG_100 |
234 | #define MP0_SMN_C2PMSG_100__CONTENT__SHIFT 0x0 |
235 | #define MP0_SMN_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL |
236 | //MP0_SMN_C2PMSG_101 |
237 | #define MP0_SMN_C2PMSG_101__CONTENT__SHIFT 0x0 |
238 | #define MP0_SMN_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL |
239 | //MP0_SMN_C2PMSG_102 |
240 | #define MP0_SMN_C2PMSG_102__CONTENT__SHIFT 0x0 |
241 | #define MP0_SMN_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL |
242 | //MP0_SMN_C2PMSG_103 |
243 | #define MP0_SMN_C2PMSG_103__CONTENT__SHIFT 0x0 |
244 | #define MP0_SMN_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL |
245 | //MP0_SMN_IH_CREDIT |
246 | #define MP0_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 |
247 | #define MP0_SMN_IH_CREDIT__CLIENT_ID__SHIFT 0x10 |
248 | #define MP0_SMN_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L |
249 | #define MP0_SMN_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L |
250 | //MP0_SMN_IH_SW_INT |
251 | #define MP0_SMN_IH_SW_INT__ID__SHIFT 0x0 |
252 | #define MP0_SMN_IH_SW_INT__VALID__SHIFT 0x8 |
253 | #define MP0_SMN_IH_SW_INT__ID_MASK 0x000000FFL |
254 | #define MP0_SMN_IH_SW_INT__VALID_MASK 0x00000100L |
255 | //MP0_SMN_IH_SW_INT_CTRL |
256 | #define MP0_SMN_IH_SW_INT_CTRL__INT_MASK__SHIFT 0x0 |
257 | #define MP0_SMN_IH_SW_INT_CTRL__INT_ACK__SHIFT 0x8 |
258 | #define MP0_SMN_IH_SW_INT_CTRL__INT_MASK_MASK 0x00000001L |
259 | #define MP0_SMN_IH_SW_INT_CTRL__INT_ACK_MASK 0x00000100L |
260 | |
261 | |
262 | // addressBlock: mp_SmuMp1_SmnDec |
263 | //MP1_SMN_C2PMSG_32 |
264 | #define MP1_SMN_C2PMSG_32__CONTENT__SHIFT 0x0 |
265 | #define MP1_SMN_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL |
266 | //MP1_SMN_C2PMSG_33 |
267 | #define MP1_SMN_C2PMSG_33__CONTENT__SHIFT 0x0 |
268 | #define MP1_SMN_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL |
269 | //MP1_SMN_C2PMSG_34 |
270 | #define MP1_SMN_C2PMSG_34__CONTENT__SHIFT 0x0 |
271 | #define MP1_SMN_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL |
272 | //MP1_SMN_C2PMSG_35 |
273 | #define MP1_SMN_C2PMSG_35__CONTENT__SHIFT 0x0 |
274 | #define MP1_SMN_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL |
275 | //MP1_SMN_C2PMSG_36 |
276 | #define MP1_SMN_C2PMSG_36__CONTENT__SHIFT 0x0 |
277 | #define MP1_SMN_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL |
278 | //MP1_SMN_C2PMSG_37 |
279 | #define MP1_SMN_C2PMSG_37__CONTENT__SHIFT 0x0 |
280 | #define MP1_SMN_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL |
281 | //MP1_SMN_C2PMSG_38 |
282 | #define MP1_SMN_C2PMSG_38__CONTENT__SHIFT 0x0 |
283 | #define MP1_SMN_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL |
284 | //MP1_SMN_C2PMSG_39 |
285 | #define MP1_SMN_C2PMSG_39__CONTENT__SHIFT 0x0 |
286 | #define MP1_SMN_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL |
287 | //MP1_SMN_C2PMSG_40 |
288 | #define MP1_SMN_C2PMSG_40__CONTENT__SHIFT 0x0 |
289 | #define MP1_SMN_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL |
290 | //MP1_SMN_C2PMSG_41 |
291 | #define MP1_SMN_C2PMSG_41__CONTENT__SHIFT 0x0 |
292 | #define MP1_SMN_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL |
293 | //MP1_SMN_C2PMSG_42 |
294 | #define MP1_SMN_C2PMSG_42__CONTENT__SHIFT 0x0 |
295 | #define MP1_SMN_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL |
296 | //MP1_SMN_C2PMSG_43 |
297 | #define MP1_SMN_C2PMSG_43__CONTENT__SHIFT 0x0 |
298 | #define MP1_SMN_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL |
299 | //MP1_SMN_C2PMSG_44 |
300 | #define MP1_SMN_C2PMSG_44__CONTENT__SHIFT 0x0 |
301 | #define MP1_SMN_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL |
302 | //MP1_SMN_C2PMSG_45 |
303 | #define MP1_SMN_C2PMSG_45__CONTENT__SHIFT 0x0 |
304 | #define MP1_SMN_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL |
305 | //MP1_SMN_C2PMSG_46 |
306 | #define MP1_SMN_C2PMSG_46__CONTENT__SHIFT 0x0 |
307 | #define MP1_SMN_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL |
308 | //MP1_SMN_C2PMSG_47 |
309 | #define MP1_SMN_C2PMSG_47__CONTENT__SHIFT 0x0 |
310 | #define MP1_SMN_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL |
311 | //MP1_SMN_C2PMSG_48 |
312 | #define MP1_SMN_C2PMSG_48__CONTENT__SHIFT 0x0 |
313 | #define MP1_SMN_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL |
314 | //MP1_SMN_C2PMSG_49 |
315 | #define MP1_SMN_C2PMSG_49__CONTENT__SHIFT 0x0 |
316 | #define MP1_SMN_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL |
317 | //MP1_SMN_C2PMSG_50 |
318 | #define MP1_SMN_C2PMSG_50__CONTENT__SHIFT 0x0 |
319 | #define MP1_SMN_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL |
320 | //MP1_SMN_C2PMSG_51 |
321 | #define MP1_SMN_C2PMSG_51__CONTENT__SHIFT 0x0 |
322 | #define MP1_SMN_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL |
323 | //MP1_SMN_C2PMSG_52 |
324 | #define MP1_SMN_C2PMSG_52__CONTENT__SHIFT 0x0 |
325 | #define MP1_SMN_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL |
326 | //MP1_SMN_C2PMSG_53 |
327 | #define MP1_SMN_C2PMSG_53__CONTENT__SHIFT 0x0 |
328 | #define MP1_SMN_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL |
329 | //MP1_SMN_C2PMSG_54 |
330 | #define MP1_SMN_C2PMSG_54__CONTENT__SHIFT 0x0 |
331 | #define MP1_SMN_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL |
332 | //MP1_SMN_C2PMSG_55 |
333 | #define MP1_SMN_C2PMSG_55__CONTENT__SHIFT 0x0 |
334 | #define MP1_SMN_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL |
335 | //MP1_SMN_C2PMSG_56 |
336 | #define MP1_SMN_C2PMSG_56__CONTENT__SHIFT 0x0 |
337 | #define MP1_SMN_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL |
338 | //MP1_SMN_C2PMSG_57 |
339 | #define MP1_SMN_C2PMSG_57__CONTENT__SHIFT 0x0 |
340 | #define MP1_SMN_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL |
341 | //MP1_SMN_C2PMSG_58 |
342 | #define MP1_SMN_C2PMSG_58__CONTENT__SHIFT 0x0 |
343 | #define MP1_SMN_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL |
344 | //MP1_SMN_C2PMSG_59 |
345 | #define MP1_SMN_C2PMSG_59__CONTENT__SHIFT 0x0 |
346 | #define MP1_SMN_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL |
347 | //MP1_SMN_C2PMSG_60 |
348 | #define MP1_SMN_C2PMSG_60__CONTENT__SHIFT 0x0 |
349 | #define MP1_SMN_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL |
350 | //MP1_SMN_C2PMSG_61 |
351 | #define MP1_SMN_C2PMSG_61__CONTENT__SHIFT 0x0 |
352 | #define MP1_SMN_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL |
353 | //MP1_SMN_C2PMSG_62 |
354 | #define MP1_SMN_C2PMSG_62__CONTENT__SHIFT 0x0 |
355 | #define MP1_SMN_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL |
356 | //MP1_SMN_C2PMSG_63 |
357 | #define MP1_SMN_C2PMSG_63__CONTENT__SHIFT 0x0 |
358 | #define MP1_SMN_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL |
359 | //MP1_SMN_C2PMSG_64 |
360 | #define MP1_SMN_C2PMSG_64__CONTENT__SHIFT 0x0 |
361 | #define MP1_SMN_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL |
362 | //MP1_SMN_C2PMSG_65 |
363 | #define MP1_SMN_C2PMSG_65__CONTENT__SHIFT 0x0 |
364 | #define MP1_SMN_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL |
365 | //MP1_SMN_C2PMSG_66 |
366 | #define MP1_SMN_C2PMSG_66__CONTENT__SHIFT 0x0 |
367 | #define MP1_SMN_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL |
368 | //MP1_SMN_C2PMSG_67 |
369 | #define MP1_SMN_C2PMSG_67__CONTENT__SHIFT 0x0 |
370 | #define MP1_SMN_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL |
371 | //MP1_SMN_C2PMSG_68 |
372 | #define MP1_SMN_C2PMSG_68__CONTENT__SHIFT 0x0 |
373 | #define MP1_SMN_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL |
374 | //MP1_SMN_C2PMSG_69 |
375 | #define MP1_SMN_C2PMSG_69__CONTENT__SHIFT 0x0 |
376 | #define MP1_SMN_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL |
377 | //MP1_SMN_C2PMSG_70 |
378 | #define MP1_SMN_C2PMSG_70__CONTENT__SHIFT 0x0 |
379 | #define MP1_SMN_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL |
380 | //MP1_SMN_C2PMSG_71 |
381 | #define MP1_SMN_C2PMSG_71__CONTENT__SHIFT 0x0 |
382 | #define MP1_SMN_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL |
383 | //MP1_SMN_C2PMSG_72 |
384 | #define MP1_SMN_C2PMSG_72__CONTENT__SHIFT 0x0 |
385 | #define MP1_SMN_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL |
386 | //MP1_SMN_C2PMSG_73 |
387 | #define MP1_SMN_C2PMSG_73__CONTENT__SHIFT 0x0 |
388 | #define MP1_SMN_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL |
389 | //MP1_SMN_C2PMSG_74 |
390 | #define MP1_SMN_C2PMSG_74__CONTENT__SHIFT 0x0 |
391 | #define MP1_SMN_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL |
392 | //MP1_SMN_C2PMSG_75 |
393 | #define MP1_SMN_C2PMSG_75__CONTENT__SHIFT 0x0 |
394 | #define MP1_SMN_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL |
395 | //MP1_SMN_C2PMSG_76 |
396 | #define MP1_SMN_C2PMSG_76__CONTENT__SHIFT 0x0 |
397 | #define MP1_SMN_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL |
398 | //MP1_SMN_C2PMSG_77 |
399 | #define MP1_SMN_C2PMSG_77__CONTENT__SHIFT 0x0 |
400 | #define MP1_SMN_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL |
401 | //MP1_SMN_C2PMSG_78 |
402 | #define MP1_SMN_C2PMSG_78__CONTENT__SHIFT 0x0 |
403 | #define MP1_SMN_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL |
404 | //MP1_SMN_C2PMSG_79 |
405 | #define MP1_SMN_C2PMSG_79__CONTENT__SHIFT 0x0 |
406 | #define MP1_SMN_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL |
407 | //MP1_SMN_C2PMSG_80 |
408 | #define MP1_SMN_C2PMSG_80__CONTENT__SHIFT 0x0 |
409 | #define MP1_SMN_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL |
410 | //MP1_SMN_C2PMSG_81 |
411 | #define MP1_SMN_C2PMSG_81__CONTENT__SHIFT 0x0 |
412 | #define MP1_SMN_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL |
413 | //MP1_SMN_C2PMSG_82 |
414 | #define MP1_SMN_C2PMSG_82__CONTENT__SHIFT 0x0 |
415 | #define MP1_SMN_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL |
416 | //MP1_SMN_C2PMSG_83 |
417 | #define MP1_SMN_C2PMSG_83__CONTENT__SHIFT 0x0 |
418 | #define MP1_SMN_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL |
419 | //MP1_SMN_C2PMSG_84 |
420 | #define MP1_SMN_C2PMSG_84__CONTENT__SHIFT 0x0 |
421 | #define MP1_SMN_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL |
422 | //MP1_SMN_C2PMSG_85 |
423 | #define MP1_SMN_C2PMSG_85__CONTENT__SHIFT 0x0 |
424 | #define MP1_SMN_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL |
425 | //MP1_SMN_C2PMSG_86 |
426 | #define MP1_SMN_C2PMSG_86__CONTENT__SHIFT 0x0 |
427 | #define MP1_SMN_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL |
428 | //MP1_SMN_C2PMSG_87 |
429 | #define MP1_SMN_C2PMSG_87__CONTENT__SHIFT 0x0 |
430 | #define MP1_SMN_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL |
431 | //MP1_SMN_C2PMSG_88 |
432 | #define MP1_SMN_C2PMSG_88__CONTENT__SHIFT 0x0 |
433 | #define MP1_SMN_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL |
434 | //MP1_SMN_C2PMSG_89 |
435 | #define MP1_SMN_C2PMSG_89__CONTENT__SHIFT 0x0 |
436 | #define MP1_SMN_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL |
437 | //MP1_SMN_C2PMSG_90 |
438 | #define MP1_SMN_C2PMSG_90__CONTENT__SHIFT 0x0 |
439 | #define MP1_SMN_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL |
440 | //MP1_SMN_C2PMSG_91 |
441 | #define MP1_SMN_C2PMSG_91__CONTENT__SHIFT 0x0 |
442 | #define MP1_SMN_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL |
443 | //MP1_SMN_C2PMSG_92 |
444 | #define MP1_SMN_C2PMSG_92__CONTENT__SHIFT 0x0 |
445 | #define MP1_SMN_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL |
446 | //MP1_SMN_C2PMSG_93 |
447 | #define MP1_SMN_C2PMSG_93__CONTENT__SHIFT 0x0 |
448 | #define MP1_SMN_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL |
449 | //MP1_SMN_C2PMSG_94 |
450 | #define MP1_SMN_C2PMSG_94__CONTENT__SHIFT 0x0 |
451 | #define MP1_SMN_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL |
452 | //MP1_SMN_C2PMSG_95 |
453 | #define MP1_SMN_C2PMSG_95__CONTENT__SHIFT 0x0 |
454 | #define MP1_SMN_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL |
455 | //MP1_SMN_C2PMSG_96 |
456 | #define MP1_SMN_C2PMSG_96__CONTENT__SHIFT 0x0 |
457 | #define MP1_SMN_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL |
458 | //MP1_SMN_C2PMSG_97 |
459 | #define MP1_SMN_C2PMSG_97__CONTENT__SHIFT 0x0 |
460 | #define MP1_SMN_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL |
461 | //MP1_SMN_C2PMSG_98 |
462 | #define MP1_SMN_C2PMSG_98__CONTENT__SHIFT 0x0 |
463 | #define MP1_SMN_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL |
464 | //MP1_SMN_C2PMSG_99 |
465 | #define MP1_SMN_C2PMSG_99__CONTENT__SHIFT 0x0 |
466 | #define MP1_SMN_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL |
467 | //MP1_SMN_C2PMSG_100 |
468 | #define MP1_SMN_C2PMSG_100__CONTENT__SHIFT 0x0 |
469 | #define MP1_SMN_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL |
470 | //MP1_SMN_C2PMSG_101 |
471 | #define MP1_SMN_C2PMSG_101__CONTENT__SHIFT 0x0 |
472 | #define MP1_SMN_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL |
473 | //MP1_SMN_C2PMSG_102 |
474 | #define MP1_SMN_C2PMSG_102__CONTENT__SHIFT 0x0 |
475 | #define MP1_SMN_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL |
476 | //MP1_SMN_C2PMSG_103 |
477 | #define MP1_SMN_C2PMSG_103__CONTENT__SHIFT 0x0 |
478 | #define MP1_SMN_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL |
479 | //MP1_SMN_C2PMSG_104 |
480 | #define MP1_SMN_C2PMSG_104__CONTENT__SHIFT 0x0 |
481 | #define MP1_SMN_C2PMSG_104__CONTENT_MASK 0xFFFFFFFFL |
482 | //MP1_SMN_C2PMSG_105 |
483 | #define MP1_SMN_C2PMSG_105__CONTENT__SHIFT 0x0 |
484 | #define MP1_SMN_C2PMSG_105__CONTENT_MASK 0xFFFFFFFFL |
485 | //MP1_SMN_C2PMSG_106 |
486 | #define MP1_SMN_C2PMSG_106__CONTENT__SHIFT 0x0 |
487 | #define MP1_SMN_C2PMSG_106__CONTENT_MASK 0xFFFFFFFFL |
488 | //MP1_SMN_C2PMSG_107 |
489 | #define MP1_SMN_C2PMSG_107__CONTENT__SHIFT 0x0 |
490 | #define MP1_SMN_C2PMSG_107__CONTENT_MASK 0xFFFFFFFFL |
491 | //MP1_SMN_C2PMSG_108 |
492 | #define MP1_SMN_C2PMSG_108__CONTENT__SHIFT 0x0 |
493 | #define MP1_SMN_C2PMSG_108__CONTENT_MASK 0xFFFFFFFFL |
494 | //MP1_SMN_C2PMSG_109 |
495 | #define MP1_SMN_C2PMSG_109__CONTENT__SHIFT 0x0 |
496 | #define MP1_SMN_C2PMSG_109__CONTENT_MASK 0xFFFFFFFFL |
497 | //MP1_SMN_C2PMSG_110 |
498 | #define MP1_SMN_C2PMSG_110__CONTENT__SHIFT 0x0 |
499 | #define MP1_SMN_C2PMSG_110__CONTENT_MASK 0xFFFFFFFFL |
500 | //MP1_SMN_C2PMSG_111 |
501 | #define MP1_SMN_C2PMSG_111__CONTENT__SHIFT 0x0 |
502 | #define MP1_SMN_C2PMSG_111__CONTENT_MASK 0xFFFFFFFFL |
503 | //MP1_SMN_C2PMSG_112 |
504 | #define MP1_SMN_C2PMSG_112__CONTENT__SHIFT 0x0 |
505 | #define MP1_SMN_C2PMSG_112__CONTENT_MASK 0xFFFFFFFFL |
506 | //MP1_SMN_C2PMSG_113 |
507 | #define MP1_SMN_C2PMSG_113__CONTENT__SHIFT 0x0 |
508 | #define MP1_SMN_C2PMSG_113__CONTENT_MASK 0xFFFFFFFFL |
509 | //MP1_SMN_C2PMSG_114 |
510 | #define MP1_SMN_C2PMSG_114__CONTENT__SHIFT 0x0 |
511 | #define MP1_SMN_C2PMSG_114__CONTENT_MASK 0xFFFFFFFFL |
512 | //MP1_SMN_C2PMSG_115 |
513 | #define MP1_SMN_C2PMSG_115__CONTENT__SHIFT 0x0 |
514 | #define MP1_SMN_C2PMSG_115__CONTENT_MASK 0xFFFFFFFFL |
515 | //MP1_SMN_C2PMSG_116 |
516 | #define MP1_SMN_C2PMSG_116__CONTENT__SHIFT 0x0 |
517 | #define MP1_SMN_C2PMSG_116__CONTENT_MASK 0xFFFFFFFFL |
518 | //MP1_SMN_C2PMSG_117 |
519 | #define MP1_SMN_C2PMSG_117__CONTENT__SHIFT 0x0 |
520 | #define MP1_SMN_C2PMSG_117__CONTENT_MASK 0xFFFFFFFFL |
521 | //MP1_SMN_C2PMSG_118 |
522 | #define MP1_SMN_C2PMSG_118__CONTENT__SHIFT 0x0 |
523 | #define MP1_SMN_C2PMSG_118__CONTENT_MASK 0xFFFFFFFFL |
524 | //MP1_SMN_C2PMSG_119 |
525 | #define MP1_SMN_C2PMSG_119__CONTENT__SHIFT 0x0 |
526 | #define MP1_SMN_C2PMSG_119__CONTENT_MASK 0xFFFFFFFFL |
527 | //MP1_SMN_C2PMSG_120 |
528 | #define MP1_SMN_C2PMSG_120__CONTENT__SHIFT 0x0 |
529 | #define MP1_SMN_C2PMSG_120__CONTENT_MASK 0xFFFFFFFFL |
530 | //MP1_SMN_C2PMSG_121 |
531 | #define MP1_SMN_C2PMSG_121__CONTENT__SHIFT 0x0 |
532 | #define MP1_SMN_C2PMSG_121__CONTENT_MASK 0xFFFFFFFFL |
533 | //MP1_SMN_C2PMSG_122 |
534 | #define MP1_SMN_C2PMSG_122__CONTENT__SHIFT 0x0 |
535 | #define MP1_SMN_C2PMSG_122__CONTENT_MASK 0xFFFFFFFFL |
536 | //MP1_SMN_C2PMSG_123 |
537 | #define MP1_SMN_C2PMSG_123__CONTENT__SHIFT 0x0 |
538 | #define MP1_SMN_C2PMSG_123__CONTENT_MASK 0xFFFFFFFFL |
539 | //MP1_SMN_C2PMSG_124 |
540 | #define MP1_SMN_C2PMSG_124__CONTENT__SHIFT 0x0 |
541 | #define MP1_SMN_C2PMSG_124__CONTENT_MASK 0xFFFFFFFFL |
542 | //MP1_SMN_C2PMSG_125 |
543 | #define MP1_SMN_C2PMSG_125__CONTENT__SHIFT 0x0 |
544 | #define MP1_SMN_C2PMSG_125__CONTENT_MASK 0xFFFFFFFFL |
545 | //MP1_SMN_C2PMSG_126 |
546 | #define MP1_SMN_C2PMSG_126__CONTENT__SHIFT 0x0 |
547 | #define MP1_SMN_C2PMSG_126__CONTENT_MASK 0xFFFFFFFFL |
548 | //MP1_SMN_C2PMSG_127 |
549 | #define MP1_SMN_C2PMSG_127__CONTENT__SHIFT 0x0 |
550 | #define MP1_SMN_C2PMSG_127__CONTENT_MASK 0xFFFFFFFFL |
551 | //MP1_SMN_IH_CREDIT |
552 | #define MP1_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 |
553 | #define MP1_SMN_IH_CREDIT__CLIENT_ID__SHIFT 0x10 |
554 | #define MP1_SMN_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L |
555 | #define MP1_SMN_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L |
556 | //MP1_SMN_IH_SW_INT |
557 | #define MP1_SMN_IH_SW_INT__ID__SHIFT 0x0 |
558 | #define MP1_SMN_IH_SW_INT__VALID__SHIFT 0x8 |
559 | #define MP1_SMN_IH_SW_INT__ID_MASK 0x000000FFL |
560 | #define MP1_SMN_IH_SW_INT__VALID_MASK 0x00000100L |
561 | //MP1_SMN_IH_SW_INT_CTRL |
562 | #define MP1_SMN_IH_SW_INT_CTRL__INT_MASK__SHIFT 0x0 |
563 | #define MP1_SMN_IH_SW_INT_CTRL__INT_ACK__SHIFT 0x8 |
564 | #define MP1_SMN_IH_SW_INT_CTRL__INT_MASK_MASK 0x00000001L |
565 | #define MP1_SMN_IH_SW_INT_CTRL__INT_ACK_MASK 0x00000100L |
566 | //MP1_SMN_FPS_CNT |
567 | #define MP1_SMN_FPS_CNT__COUNT__SHIFT 0x0 |
568 | #define MP1_SMN_FPS_CNT__COUNT_MASK 0xFFFFFFFFL |
569 | //MP1_SMN_EXT_SCRATCH0 |
570 | #define MP1_SMN_EXT_SCRATCH0__DATA__SHIFT 0x0 |
571 | #define MP1_SMN_EXT_SCRATCH0__DATA_MASK 0xFFFFFFFFL |
572 | //MP1_SMN_EXT_SCRATCH1 |
573 | #define MP1_SMN_EXT_SCRATCH1__DATA__SHIFT 0x0 |
574 | #define MP1_SMN_EXT_SCRATCH1__DATA_MASK 0xFFFFFFFFL |
575 | //MP1_SMN_EXT_SCRATCH2 |
576 | #define MP1_SMN_EXT_SCRATCH2__DATA__SHIFT 0x0 |
577 | #define MP1_SMN_EXT_SCRATCH2__DATA_MASK 0xFFFFFFFFL |
578 | //MP1_SMN_EXT_SCRATCH3 |
579 | #define MP1_SMN_EXT_SCRATCH3__DATA__SHIFT 0x0 |
580 | #define MP1_SMN_EXT_SCRATCH3__DATA_MASK 0xFFFFFFFFL |
581 | //MP1_SMN_EXT_SCRATCH4 |
582 | #define MP1_SMN_EXT_SCRATCH4__DATA__SHIFT 0x0 |
583 | #define MP1_SMN_EXT_SCRATCH4__DATA_MASK 0xFFFFFFFFL |
584 | //MP1_SMN_EXT_SCRATCH5 |
585 | #define MP1_SMN_EXT_SCRATCH5__DATA__SHIFT 0x0 |
586 | #define MP1_SMN_EXT_SCRATCH5__DATA_MASK 0xFFFFFFFFL |
587 | //MP1_SMN_EXT_SCRATCH6 |
588 | #define MP1_SMN_EXT_SCRATCH6__DATA__SHIFT 0x0 |
589 | #define MP1_SMN_EXT_SCRATCH6__DATA_MASK 0xFFFFFFFFL |
590 | //MP1_SMN_EXT_SCRATCH7 |
591 | #define MP1_SMN_EXT_SCRATCH7__DATA__SHIFT 0x0 |
592 | #define MP1_SMN_EXT_SCRATCH7__DATA_MASK 0xFFFFFFFFL |
593 | |
594 | |
595 | #endif |
596 | |