| 1 | /* |
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| 2 | * Copyright 2022 Advanced Micro Devices, Inc. |
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| 3 | * |
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| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 5 | * copy of this software and associated documentation files (the "Software"), |
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| 6 | * to deal in the Software without restriction, including without limitation |
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| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 9 | * Software is furnished to do so, subject to the following conditions: |
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| 10 | * |
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| 11 | * The above copyright notice and this permission notice shall be included in |
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| 12 | * all copies or substantial portions of the Software. |
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| 13 | * |
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| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
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| 21 | * |
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| 22 | */ |
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| 23 | |
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| 24 | |
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| 25 | #ifndef _mp_13_0_8_OFFSET_HEADER |
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| 26 | #define |
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| 27 | |
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| 28 | |
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| 29 | |
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| 30 | // addressBlock: mp_SmuMp0_SmnDec |
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| 31 | // base address: 0x0 |
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| 32 | #define regMP0_SMN_C2PMSG_32 0x0060 |
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| 33 | #define regMP0_SMN_C2PMSG_32_BASE_IDX 0 |
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| 34 | #define regMP0_SMN_C2PMSG_33 0x0061 |
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| 35 | #define regMP0_SMN_C2PMSG_33_BASE_IDX 0 |
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| 36 | #define regMP0_SMN_C2PMSG_34 0x0062 |
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| 37 | #define regMP0_SMN_C2PMSG_34_BASE_IDX 0 |
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| 38 | #define regMP0_SMN_C2PMSG_35 0x0063 |
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| 39 | #define regMP0_SMN_C2PMSG_35_BASE_IDX 0 |
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| 40 | #define regMP0_SMN_C2PMSG_36 0x0064 |
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| 41 | #define regMP0_SMN_C2PMSG_36_BASE_IDX 0 |
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| 42 | #define regMP0_SMN_C2PMSG_37 0x0065 |
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| 43 | #define regMP0_SMN_C2PMSG_37_BASE_IDX 0 |
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| 44 | #define regMP0_SMN_C2PMSG_38 0x0066 |
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| 45 | #define regMP0_SMN_C2PMSG_38_BASE_IDX 0 |
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| 46 | #define regMP0_SMN_C2PMSG_39 0x0067 |
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| 47 | #define regMP0_SMN_C2PMSG_39_BASE_IDX 0 |
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| 48 | #define regMP0_SMN_C2PMSG_40 0x0068 |
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| 49 | #define regMP0_SMN_C2PMSG_40_BASE_IDX 0 |
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| 50 | #define regMP0_SMN_C2PMSG_41 0x0069 |
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| 51 | #define regMP0_SMN_C2PMSG_41_BASE_IDX 0 |
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| 52 | #define regMP0_SMN_C2PMSG_42 0x006a |
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| 53 | #define regMP0_SMN_C2PMSG_42_BASE_IDX 0 |
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| 54 | #define regMP0_SMN_C2PMSG_43 0x006b |
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| 55 | #define regMP0_SMN_C2PMSG_43_BASE_IDX 0 |
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| 56 | #define regMP0_SMN_C2PMSG_44 0x006c |
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| 57 | #define regMP0_SMN_C2PMSG_44_BASE_IDX 0 |
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| 58 | #define regMP0_SMN_C2PMSG_45 0x006d |
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| 59 | #define regMP0_SMN_C2PMSG_45_BASE_IDX 0 |
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| 60 | #define regMP0_SMN_C2PMSG_46 0x006e |
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| 61 | #define regMP0_SMN_C2PMSG_46_BASE_IDX 0 |
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| 62 | #define regMP0_SMN_C2PMSG_47 0x006f |
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| 63 | #define regMP0_SMN_C2PMSG_47_BASE_IDX 0 |
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| 64 | #define regMP0_SMN_C2PMSG_48 0x0070 |
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| 65 | #define regMP0_SMN_C2PMSG_48_BASE_IDX 0 |
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| 66 | #define regMP0_SMN_C2PMSG_49 0x0071 |
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| 67 | #define regMP0_SMN_C2PMSG_49_BASE_IDX 0 |
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| 68 | #define regMP0_SMN_C2PMSG_50 0x0072 |
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| 69 | #define regMP0_SMN_C2PMSG_50_BASE_IDX 0 |
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| 70 | #define regMP0_SMN_C2PMSG_51 0x0073 |
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| 71 | #define regMP0_SMN_C2PMSG_51_BASE_IDX 0 |
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| 72 | #define regMP0_SMN_C2PMSG_52 0x0074 |
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| 73 | #define regMP0_SMN_C2PMSG_52_BASE_IDX 0 |
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| 74 | #define regMP0_SMN_C2PMSG_53 0x0075 |
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| 75 | #define regMP0_SMN_C2PMSG_53_BASE_IDX 0 |
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| 76 | #define regMP0_SMN_C2PMSG_54 0x0076 |
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| 77 | #define regMP0_SMN_C2PMSG_54_BASE_IDX 0 |
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| 78 | #define regMP0_SMN_C2PMSG_55 0x0077 |
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| 79 | #define regMP0_SMN_C2PMSG_55_BASE_IDX 0 |
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| 80 | #define regMP0_SMN_C2PMSG_56 0x0078 |
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| 81 | #define regMP0_SMN_C2PMSG_56_BASE_IDX 0 |
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| 82 | #define regMP0_SMN_C2PMSG_57 0x0079 |
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| 83 | #define regMP0_SMN_C2PMSG_57_BASE_IDX 0 |
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| 84 | #define regMP0_SMN_C2PMSG_58 0x007a |
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| 85 | #define regMP0_SMN_C2PMSG_58_BASE_IDX 0 |
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| 86 | #define regMP0_SMN_C2PMSG_59 0x007b |
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| 87 | #define regMP0_SMN_C2PMSG_59_BASE_IDX 0 |
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| 88 | #define regMP0_SMN_C2PMSG_60 0x007c |
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| 89 | #define regMP0_SMN_C2PMSG_60_BASE_IDX 0 |
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| 90 | #define regMP0_SMN_C2PMSG_61 0x007d |
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| 91 | #define regMP0_SMN_C2PMSG_61_BASE_IDX 0 |
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| 92 | #define regMP0_SMN_C2PMSG_62 0x007e |
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| 93 | #define regMP0_SMN_C2PMSG_62_BASE_IDX 0 |
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| 94 | #define regMP0_SMN_C2PMSG_63 0x007f |
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| 95 | #define regMP0_SMN_C2PMSG_63_BASE_IDX 0 |
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| 96 | #define regMP0_SMN_C2PMSG_64 0x0080 |
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| 97 | #define regMP0_SMN_C2PMSG_64_BASE_IDX 0 |
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| 98 | #define regMP0_SMN_C2PMSG_65 0x0081 |
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| 99 | #define regMP0_SMN_C2PMSG_65_BASE_IDX 0 |
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| 100 | #define regMP0_SMN_C2PMSG_66 0x0082 |
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| 101 | #define regMP0_SMN_C2PMSG_66_BASE_IDX 0 |
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| 102 | #define regMP0_SMN_C2PMSG_67 0x0083 |
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| 103 | #define regMP0_SMN_C2PMSG_67_BASE_IDX 0 |
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| 104 | #define regMP0_SMN_C2PMSG_68 0x0084 |
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| 105 | #define regMP0_SMN_C2PMSG_68_BASE_IDX 0 |
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| 106 | #define regMP0_SMN_C2PMSG_69 0x0085 |
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| 107 | #define regMP0_SMN_C2PMSG_69_BASE_IDX 0 |
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| 108 | #define regMP0_SMN_C2PMSG_70 0x0086 |
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| 109 | #define regMP0_SMN_C2PMSG_70_BASE_IDX 0 |
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| 110 | #define regMP0_SMN_C2PMSG_71 0x0087 |
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| 111 | #define regMP0_SMN_C2PMSG_71_BASE_IDX 0 |
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| 112 | #define regMP0_SMN_C2PMSG_72 0x0088 |
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| 113 | #define regMP0_SMN_C2PMSG_72_BASE_IDX 0 |
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| 114 | #define regMP0_SMN_C2PMSG_73 0x0089 |
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| 115 | #define regMP0_SMN_C2PMSG_73_BASE_IDX 0 |
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| 116 | #define regMP0_SMN_C2PMSG_74 0x008a |
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| 117 | #define regMP0_SMN_C2PMSG_74_BASE_IDX 0 |
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| 118 | #define regMP0_SMN_C2PMSG_75 0x008b |
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| 119 | #define regMP0_SMN_C2PMSG_75_BASE_IDX 0 |
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| 120 | #define regMP0_SMN_C2PMSG_76 0x008c |
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| 121 | #define regMP0_SMN_C2PMSG_76_BASE_IDX 0 |
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| 122 | #define regMP0_SMN_C2PMSG_77 0x008d |
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| 123 | #define regMP0_SMN_C2PMSG_77_BASE_IDX 0 |
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| 124 | #define regMP0_SMN_C2PMSG_78 0x008e |
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| 125 | #define regMP0_SMN_C2PMSG_78_BASE_IDX 0 |
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| 126 | #define regMP0_SMN_C2PMSG_79 0x008f |
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| 127 | #define regMP0_SMN_C2PMSG_79_BASE_IDX 0 |
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| 128 | #define regMP0_SMN_C2PMSG_80 0x0090 |
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| 129 | #define regMP0_SMN_C2PMSG_80_BASE_IDX 0 |
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| 130 | #define regMP0_SMN_C2PMSG_81 0x0091 |
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| 131 | #define regMP0_SMN_C2PMSG_81_BASE_IDX 0 |
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| 132 | #define regMP0_SMN_C2PMSG_82 0x0092 |
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| 133 | #define regMP0_SMN_C2PMSG_82_BASE_IDX 0 |
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| 134 | #define regMP0_SMN_C2PMSG_83 0x0093 |
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| 135 | #define regMP0_SMN_C2PMSG_83_BASE_IDX 0 |
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| 136 | #define regMP0_SMN_C2PMSG_84 0x0094 |
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| 137 | #define regMP0_SMN_C2PMSG_84_BASE_IDX 0 |
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| 138 | #define regMP0_SMN_C2PMSG_85 0x0095 |
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| 139 | #define regMP0_SMN_C2PMSG_85_BASE_IDX 0 |
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| 140 | #define regMP0_SMN_C2PMSG_86 0x0096 |
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| 141 | #define regMP0_SMN_C2PMSG_86_BASE_IDX 0 |
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| 142 | #define regMP0_SMN_C2PMSG_87 0x0097 |
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| 143 | #define regMP0_SMN_C2PMSG_87_BASE_IDX 0 |
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| 144 | #define regMP0_SMN_C2PMSG_88 0x0098 |
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| 145 | #define regMP0_SMN_C2PMSG_88_BASE_IDX 0 |
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| 146 | #define regMP0_SMN_C2PMSG_89 0x0099 |
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| 147 | #define regMP0_SMN_C2PMSG_89_BASE_IDX 0 |
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| 148 | #define regMP0_SMN_C2PMSG_90 0x009a |
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| 149 | #define regMP0_SMN_C2PMSG_90_BASE_IDX 0 |
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| 150 | #define regMP0_SMN_C2PMSG_91 0x009b |
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| 151 | #define regMP0_SMN_C2PMSG_91_BASE_IDX 0 |
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| 152 | #define regMP0_SMN_C2PMSG_92 0x009c |
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| 153 | #define regMP0_SMN_C2PMSG_92_BASE_IDX 0 |
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| 154 | #define regMP0_SMN_C2PMSG_93 0x009d |
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| 155 | #define regMP0_SMN_C2PMSG_93_BASE_IDX 0 |
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| 156 | #define regMP0_SMN_C2PMSG_94 0x009e |
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| 157 | #define regMP0_SMN_C2PMSG_94_BASE_IDX 0 |
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| 158 | #define regMP0_SMN_C2PMSG_95 0x009f |
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| 159 | #define regMP0_SMN_C2PMSG_95_BASE_IDX 0 |
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| 160 | #define regMP0_SMN_C2PMSG_96 0x00a0 |
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| 161 | #define regMP0_SMN_C2PMSG_96_BASE_IDX 0 |
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| 162 | #define regMP0_SMN_C2PMSG_97 0x00a1 |
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| 163 | #define regMP0_SMN_C2PMSG_97_BASE_IDX 0 |
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| 164 | #define regMP0_SMN_C2PMSG_98 0x00a2 |
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| 165 | #define regMP0_SMN_C2PMSG_98_BASE_IDX 0 |
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| 166 | #define regMP0_SMN_C2PMSG_99 0x00a3 |
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| 167 | #define regMP0_SMN_C2PMSG_99_BASE_IDX 0 |
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| 168 | #define regMP0_SMN_C2PMSG_100 0x00a4 |
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| 169 | #define regMP0_SMN_C2PMSG_100_BASE_IDX 0 |
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| 170 | #define regMP0_SMN_C2PMSG_101 0x00a5 |
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| 171 | #define regMP0_SMN_C2PMSG_101_BASE_IDX 0 |
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| 172 | #define regMP0_SMN_C2PMSG_102 0x00a6 |
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| 173 | #define regMP0_SMN_C2PMSG_102_BASE_IDX 0 |
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| 174 | #define regMP0_SMN_C2PMSG_103 0x00a7 |
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| 175 | #define regMP0_SMN_C2PMSG_103_BASE_IDX 0 |
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| 176 | #define regMP0_SMN_IH_CREDIT 0x00c1 |
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| 177 | #define regMP0_SMN_IH_CREDIT_BASE_IDX 0 |
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| 178 | #define regMP0_SMN_IH_SW_INT 0x00c2 |
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| 179 | #define regMP0_SMN_IH_SW_INT_BASE_IDX 0 |
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| 180 | #define regMP0_SMN_IH_SW_INT_CTRL 0x00c3 |
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| 181 | #define regMP0_SMN_IH_SW_INT_CTRL_BASE_IDX 0 |
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| 182 | |
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| 183 | |
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| 184 | // addressBlock: mp_SmuMp1_SmnDec |
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| 185 | // base address: 0x0 |
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| 186 | #define regMP1_SMN_C2PMSG_32 0x0260 |
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| 187 | #define regMP1_SMN_C2PMSG_32_BASE_IDX 0 |
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| 188 | #define regMP1_SMN_C2PMSG_33 0x0261 |
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| 189 | #define regMP1_SMN_C2PMSG_33_BASE_IDX 0 |
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| 190 | #define regMP1_SMN_C2PMSG_34 0x0262 |
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| 191 | #define regMP1_SMN_C2PMSG_34_BASE_IDX 0 |
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| 192 | #define regMP1_SMN_C2PMSG_35 0x0263 |
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| 193 | #define regMP1_SMN_C2PMSG_35_BASE_IDX 0 |
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| 194 | #define regMP1_SMN_C2PMSG_36 0x0264 |
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| 195 | #define regMP1_SMN_C2PMSG_36_BASE_IDX 0 |
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| 196 | #define regMP1_SMN_C2PMSG_37 0x0265 |
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| 197 | #define regMP1_SMN_C2PMSG_37_BASE_IDX 0 |
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| 198 | #define regMP1_SMN_C2PMSG_38 0x0266 |
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| 199 | #define regMP1_SMN_C2PMSG_38_BASE_IDX 0 |
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| 200 | #define regMP1_SMN_C2PMSG_39 0x0267 |
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| 201 | #define regMP1_SMN_C2PMSG_39_BASE_IDX 0 |
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| 202 | #define regMP1_SMN_C2PMSG_40 0x0268 |
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| 203 | #define regMP1_SMN_C2PMSG_40_BASE_IDX 0 |
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| 204 | #define regMP1_SMN_C2PMSG_41 0x0269 |
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| 205 | #define regMP1_SMN_C2PMSG_41_BASE_IDX 0 |
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| 206 | #define regMP1_SMN_C2PMSG_42 0x026a |
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| 207 | #define regMP1_SMN_C2PMSG_42_BASE_IDX 0 |
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| 208 | #define regMP1_SMN_C2PMSG_43 0x026b |
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| 209 | #define regMP1_SMN_C2PMSG_43_BASE_IDX 0 |
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| 210 | #define regMP1_SMN_C2PMSG_44 0x026c |
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| 211 | #define regMP1_SMN_C2PMSG_44_BASE_IDX 0 |
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| 212 | #define regMP1_SMN_C2PMSG_45 0x026d |
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| 213 | #define regMP1_SMN_C2PMSG_45_BASE_IDX 0 |
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| 214 | #define regMP1_SMN_C2PMSG_46 0x026e |
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| 215 | #define regMP1_SMN_C2PMSG_46_BASE_IDX 0 |
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| 216 | #define regMP1_SMN_C2PMSG_47 0x026f |
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| 217 | #define regMP1_SMN_C2PMSG_47_BASE_IDX 0 |
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| 218 | #define regMP1_SMN_C2PMSG_48 0x0270 |
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| 219 | #define regMP1_SMN_C2PMSG_48_BASE_IDX 0 |
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| 220 | #define regMP1_SMN_C2PMSG_49 0x0271 |
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| 221 | #define regMP1_SMN_C2PMSG_49_BASE_IDX 0 |
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| 222 | #define regMP1_SMN_C2PMSG_50 0x0272 |
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| 223 | #define regMP1_SMN_C2PMSG_50_BASE_IDX 0 |
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| 224 | #define regMP1_SMN_C2PMSG_51 0x0273 |
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| 225 | #define regMP1_SMN_C2PMSG_51_BASE_IDX 0 |
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| 226 | #define regMP1_SMN_C2PMSG_52 0x0274 |
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| 227 | #define regMP1_SMN_C2PMSG_52_BASE_IDX 0 |
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| 228 | #define regMP1_SMN_C2PMSG_53 0x0275 |
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| 229 | #define regMP1_SMN_C2PMSG_53_BASE_IDX 0 |
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| 230 | #define regMP1_SMN_C2PMSG_54 0x0276 |
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| 231 | #define regMP1_SMN_C2PMSG_54_BASE_IDX 0 |
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| 232 | #define regMP1_SMN_C2PMSG_55 0x0277 |
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| 233 | #define regMP1_SMN_C2PMSG_55_BASE_IDX 0 |
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| 234 | #define regMP1_SMN_C2PMSG_56 0x0278 |
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| 235 | #define regMP1_SMN_C2PMSG_56_BASE_IDX 0 |
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| 236 | #define regMP1_SMN_C2PMSG_57 0x0279 |
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| 237 | #define regMP1_SMN_C2PMSG_57_BASE_IDX 0 |
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| 238 | #define regMP1_SMN_C2PMSG_58 0x027a |
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| 239 | #define regMP1_SMN_C2PMSG_58_BASE_IDX 0 |
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| 240 | #define regMP1_SMN_C2PMSG_59 0x027b |
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| 241 | #define regMP1_SMN_C2PMSG_59_BASE_IDX 0 |
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| 242 | #define regMP1_SMN_C2PMSG_60 0x027c |
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| 243 | #define regMP1_SMN_C2PMSG_60_BASE_IDX 0 |
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| 244 | #define regMP1_SMN_C2PMSG_61 0x027d |
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| 245 | #define regMP1_SMN_C2PMSG_61_BASE_IDX 0 |
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| 246 | #define regMP1_SMN_C2PMSG_62 0x027e |
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| 247 | #define regMP1_SMN_C2PMSG_62_BASE_IDX 0 |
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| 248 | #define regMP1_SMN_C2PMSG_63 0x027f |
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| 249 | #define regMP1_SMN_C2PMSG_63_BASE_IDX 0 |
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| 250 | #define regMP1_SMN_C2PMSG_64 0x0280 |
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| 251 | #define regMP1_SMN_C2PMSG_64_BASE_IDX 0 |
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| 252 | #define regMP1_SMN_C2PMSG_65 0x0281 |
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| 253 | #define regMP1_SMN_C2PMSG_65_BASE_IDX 0 |
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| 254 | #define regMP1_SMN_C2PMSG_66 0x0282 |
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| 255 | #define regMP1_SMN_C2PMSG_66_BASE_IDX 0 |
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| 256 | #define regMP1_SMN_C2PMSG_67 0x0283 |
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| 257 | #define regMP1_SMN_C2PMSG_67_BASE_IDX 0 |
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| 258 | #define regMP1_SMN_C2PMSG_68 0x0284 |
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| 259 | #define regMP1_SMN_C2PMSG_68_BASE_IDX 0 |
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| 260 | #define regMP1_SMN_C2PMSG_69 0x0285 |
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| 261 | #define regMP1_SMN_C2PMSG_69_BASE_IDX 0 |
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| 262 | #define regMP1_SMN_C2PMSG_70 0x0286 |
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| 263 | #define regMP1_SMN_C2PMSG_70_BASE_IDX 0 |
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| 264 | #define regMP1_SMN_C2PMSG_71 0x0287 |
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| 265 | #define regMP1_SMN_C2PMSG_71_BASE_IDX 0 |
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| 266 | #define regMP1_SMN_C2PMSG_72 0x0288 |
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| 267 | #define regMP1_SMN_C2PMSG_72_BASE_IDX 0 |
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| 268 | #define regMP1_SMN_C2PMSG_73 0x0289 |
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| 269 | #define regMP1_SMN_C2PMSG_73_BASE_IDX 0 |
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| 270 | #define regMP1_SMN_C2PMSG_74 0x028a |
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| 271 | #define regMP1_SMN_C2PMSG_74_BASE_IDX 0 |
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| 272 | #define regMP1_SMN_C2PMSG_75 0x028b |
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| 273 | #define regMP1_SMN_C2PMSG_75_BASE_IDX 0 |
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| 274 | #define regMP1_SMN_C2PMSG_76 0x028c |
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| 275 | #define regMP1_SMN_C2PMSG_76_BASE_IDX 0 |
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| 276 | #define regMP1_SMN_C2PMSG_77 0x028d |
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| 277 | #define regMP1_SMN_C2PMSG_77_BASE_IDX 0 |
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| 278 | #define regMP1_SMN_C2PMSG_78 0x028e |
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| 279 | #define regMP1_SMN_C2PMSG_78_BASE_IDX 0 |
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| 280 | #define regMP1_SMN_C2PMSG_79 0x028f |
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| 281 | #define regMP1_SMN_C2PMSG_79_BASE_IDX 0 |
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| 282 | #define regMP1_SMN_C2PMSG_80 0x0290 |
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| 283 | #define regMP1_SMN_C2PMSG_80_BASE_IDX 0 |
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| 284 | #define regMP1_SMN_C2PMSG_81 0x0291 |
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| 285 | #define regMP1_SMN_C2PMSG_81_BASE_IDX 0 |
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| 286 | #define regMP1_SMN_C2PMSG_82 0x0292 |
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| 287 | #define regMP1_SMN_C2PMSG_82_BASE_IDX 0 |
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| 288 | #define regMP1_SMN_C2PMSG_83 0x0293 |
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| 289 | #define regMP1_SMN_C2PMSG_83_BASE_IDX 0 |
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| 290 | #define regMP1_SMN_C2PMSG_84 0x0294 |
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| 291 | #define regMP1_SMN_C2PMSG_84_BASE_IDX 0 |
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| 292 | #define regMP1_SMN_C2PMSG_85 0x0295 |
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| 293 | #define regMP1_SMN_C2PMSG_85_BASE_IDX 0 |
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| 294 | #define regMP1_SMN_C2PMSG_86 0x0296 |
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| 295 | #define regMP1_SMN_C2PMSG_86_BASE_IDX 0 |
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| 296 | #define regMP1_SMN_C2PMSG_87 0x0297 |
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| 297 | #define regMP1_SMN_C2PMSG_87_BASE_IDX 0 |
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| 298 | #define regMP1_SMN_C2PMSG_88 0x0298 |
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| 299 | #define regMP1_SMN_C2PMSG_88_BASE_IDX 0 |
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| 300 | #define regMP1_SMN_C2PMSG_89 0x0299 |
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| 301 | #define regMP1_SMN_C2PMSG_89_BASE_IDX 0 |
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| 302 | #define regMP1_SMN_C2PMSG_90 0x029a |
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| 303 | #define regMP1_SMN_C2PMSG_90_BASE_IDX 0 |
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| 304 | #define regMP1_SMN_C2PMSG_91 0x029b |
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| 305 | #define regMP1_SMN_C2PMSG_91_BASE_IDX 0 |
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| 306 | #define regMP1_SMN_C2PMSG_92 0x029c |
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| 307 | #define regMP1_SMN_C2PMSG_92_BASE_IDX 0 |
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| 308 | #define regMP1_SMN_C2PMSG_93 0x029d |
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| 309 | #define regMP1_SMN_C2PMSG_93_BASE_IDX 0 |
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| 310 | #define regMP1_SMN_C2PMSG_94 0x029e |
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| 311 | #define regMP1_SMN_C2PMSG_94_BASE_IDX 0 |
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| 312 | #define regMP1_SMN_C2PMSG_95 0x029f |
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| 313 | #define regMP1_SMN_C2PMSG_95_BASE_IDX 0 |
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| 314 | #define regMP1_SMN_C2PMSG_96 0x02a0 |
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| 315 | #define regMP1_SMN_C2PMSG_96_BASE_IDX 0 |
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| 316 | #define regMP1_SMN_C2PMSG_97 0x02a1 |
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| 317 | #define regMP1_SMN_C2PMSG_97_BASE_IDX 0 |
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| 318 | #define regMP1_SMN_C2PMSG_98 0x02a2 |
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| 319 | #define regMP1_SMN_C2PMSG_98_BASE_IDX 0 |
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| 320 | #define regMP1_SMN_C2PMSG_99 0x02a3 |
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| 321 | #define regMP1_SMN_C2PMSG_99_BASE_IDX 0 |
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| 322 | #define regMP1_SMN_C2PMSG_100 0x02a4 |
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| 323 | #define regMP1_SMN_C2PMSG_100_BASE_IDX 0 |
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| 324 | #define regMP1_SMN_C2PMSG_101 0x02a5 |
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| 325 | #define regMP1_SMN_C2PMSG_101_BASE_IDX 0 |
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| 326 | #define regMP1_SMN_C2PMSG_102 0x02a6 |
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| 327 | #define regMP1_SMN_C2PMSG_102_BASE_IDX 0 |
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| 328 | #define regMP1_SMN_C2PMSG_103 0x02a7 |
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| 329 | #define regMP1_SMN_C2PMSG_103_BASE_IDX 0 |
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| 330 | #define regMP1_SMN_C2PMSG_104 0x02a8 |
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| 331 | #define regMP1_SMN_C2PMSG_104_BASE_IDX 0 |
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| 332 | #define regMP1_SMN_C2PMSG_105 0x02a9 |
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| 333 | #define regMP1_SMN_C2PMSG_105_BASE_IDX 0 |
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| 334 | #define regMP1_SMN_C2PMSG_106 0x02aa |
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| 335 | #define regMP1_SMN_C2PMSG_106_BASE_IDX 0 |
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| 336 | #define regMP1_SMN_C2PMSG_107 0x02ab |
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| 337 | #define regMP1_SMN_C2PMSG_107_BASE_IDX 0 |
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| 338 | #define regMP1_SMN_C2PMSG_108 0x02ac |
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| 339 | #define regMP1_SMN_C2PMSG_108_BASE_IDX 0 |
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| 340 | #define regMP1_SMN_C2PMSG_109 0x02ad |
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| 341 | #define regMP1_SMN_C2PMSG_109_BASE_IDX 0 |
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| 342 | #define regMP1_SMN_C2PMSG_110 0x02ae |
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| 343 | #define regMP1_SMN_C2PMSG_110_BASE_IDX 0 |
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| 344 | #define regMP1_SMN_C2PMSG_111 0x02af |
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| 345 | #define regMP1_SMN_C2PMSG_111_BASE_IDX 0 |
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| 346 | #define regMP1_SMN_C2PMSG_112 0x02b0 |
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| 347 | #define regMP1_SMN_C2PMSG_112_BASE_IDX 0 |
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| 348 | #define regMP1_SMN_C2PMSG_113 0x02b1 |
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| 349 | #define regMP1_SMN_C2PMSG_113_BASE_IDX 0 |
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| 350 | #define regMP1_SMN_C2PMSG_114 0x02b2 |
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| 351 | #define regMP1_SMN_C2PMSG_114_BASE_IDX 0 |
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| 352 | #define regMP1_SMN_C2PMSG_115 0x02b3 |
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| 353 | #define regMP1_SMN_C2PMSG_115_BASE_IDX 0 |
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| 354 | #define regMP1_SMN_C2PMSG_116 0x02b4 |
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| 355 | #define regMP1_SMN_C2PMSG_116_BASE_IDX 0 |
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| 356 | #define regMP1_SMN_C2PMSG_117 0x02b5 |
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| 357 | #define regMP1_SMN_C2PMSG_117_BASE_IDX 0 |
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| 358 | #define regMP1_SMN_C2PMSG_118 0x02b6 |
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| 359 | #define regMP1_SMN_C2PMSG_118_BASE_IDX 0 |
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| 360 | #define regMP1_SMN_C2PMSG_119 0x02b7 |
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| 361 | #define regMP1_SMN_C2PMSG_119_BASE_IDX 0 |
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| 362 | #define regMP1_SMN_C2PMSG_120 0x02b8 |
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| 363 | #define regMP1_SMN_C2PMSG_120_BASE_IDX 0 |
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| 364 | #define regMP1_SMN_C2PMSG_121 0x02b9 |
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| 365 | #define regMP1_SMN_C2PMSG_121_BASE_IDX 0 |
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| 366 | #define regMP1_SMN_C2PMSG_122 0x02ba |
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| 367 | #define regMP1_SMN_C2PMSG_122_BASE_IDX 0 |
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| 368 | #define regMP1_SMN_C2PMSG_123 0x02bb |
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| 369 | #define regMP1_SMN_C2PMSG_123_BASE_IDX 0 |
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| 370 | #define regMP1_SMN_C2PMSG_124 0x02bc |
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| 371 | #define regMP1_SMN_C2PMSG_124_BASE_IDX 0 |
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| 372 | #define regMP1_SMN_C2PMSG_125 0x02bd |
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| 373 | #define regMP1_SMN_C2PMSG_125_BASE_IDX 0 |
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| 374 | #define regMP1_SMN_C2PMSG_126 0x02be |
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| 375 | #define regMP1_SMN_C2PMSG_126_BASE_IDX 0 |
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| 376 | #define regMP1_SMN_C2PMSG_127 0x02bf |
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| 377 | #define regMP1_SMN_C2PMSG_127_BASE_IDX 0 |
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| 378 | #define regMP1_SMN_IH_CREDIT 0x02c1 |
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| 379 | #define regMP1_SMN_IH_CREDIT_BASE_IDX 0 |
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| 380 | #define regMP1_SMN_IH_SW_INT 0x02c2 |
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| 381 | #define regMP1_SMN_IH_SW_INT_BASE_IDX 0 |
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| 382 | #define regMP1_SMN_IH_SW_INT_CTRL 0x02c3 |
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| 383 | #define regMP1_SMN_IH_SW_INT_CTRL_BASE_IDX 0 |
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| 384 | #define regMP1_SMN_FPS_CNT 0x02c4 |
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| 385 | #define regMP1_SMN_FPS_CNT_BASE_IDX 0 |
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| 386 | #define regMP1_SMN_EXT_SCRATCH0 0x0340 |
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| 387 | #define regMP1_SMN_EXT_SCRATCH0_BASE_IDX 0 |
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| 388 | #define regMP1_SMN_EXT_SCRATCH1 0x0341 |
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| 389 | #define regMP1_SMN_EXT_SCRATCH1_BASE_IDX 0 |
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| 390 | #define regMP1_SMN_EXT_SCRATCH2 0x0342 |
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| 391 | #define regMP1_SMN_EXT_SCRATCH2_BASE_IDX 0 |
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| 392 | #define regMP1_SMN_EXT_SCRATCH3 0x0343 |
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| 393 | #define regMP1_SMN_EXT_SCRATCH3_BASE_IDX 0 |
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| 394 | #define regMP1_SMN_EXT_SCRATCH4 0x0344 |
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| 395 | #define regMP1_SMN_EXT_SCRATCH4_BASE_IDX 0 |
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| 396 | #define regMP1_SMN_EXT_SCRATCH5 0x0345 |
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| 397 | #define regMP1_SMN_EXT_SCRATCH5_BASE_IDX 0 |
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| 398 | #define regMP1_SMN_EXT_SCRATCH6 0x0346 |
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| 399 | #define regMP1_SMN_EXT_SCRATCH6_BASE_IDX 0 |
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| 400 | #define regMP1_SMN_EXT_SCRATCH7 0x0347 |
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| 401 | #define regMP1_SMN_EXT_SCRATCH7_BASE_IDX 0 |
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| 402 | |
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| 403 | |
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| 404 | // addressBlock: mp_SmuMp1Pub_CruDec |
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| 405 | // base address: 0x0 |
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| 406 | #define regMP1_FIRMWARE_FLAGS 0xbee009 |
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| 407 | #define regMP1_FIRMWARE_FLAGS_BASE_IDX 0 |
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| 408 | |
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| 409 | |
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| 410 | #endif |
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| 411 | |
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