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1/*
2 * Copyright (C) 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20 */
21#ifndef _nbio_6_1_DEFAULT_HEADER
22#define _nbio_6_1_DEFAULT_HEADER
23
24
25// addressBlock: nbio_pcie_pswuscfg0_cfgdecp
26#define cfgPSWUSCFG0_VENDOR_ID_DEFAULT 0x00000000
27#define cfgPSWUSCFG0_DEVICE_ID_DEFAULT 0x00000000
28#define cfgPSWUSCFG0_COMMAND_DEFAULT 0x00000000
29#define cfgPSWUSCFG0_STATUS_DEFAULT 0x00000000
30#define cfgPSWUSCFG0_REVISION_ID_DEFAULT 0x00000000
31#define cfgPSWUSCFG0_PROG_INTERFACE_DEFAULT 0x00000000
32#define cfgPSWUSCFG0_SUB_CLASS_DEFAULT 0x00000000
33#define cfgPSWUSCFG0_BASE_CLASS_DEFAULT 0x00000000
34#define cfgPSWUSCFG0_CACHE_LINE_DEFAULT 0x00000000
35#define cfgPSWUSCFG0_LATENCY_DEFAULT 0x00000000
36#define cfgPSWUSCFG0_HEADER_DEFAULT 0x00000000
37#define cfgPSWUSCFG0_BIST_DEFAULT 0x00000000
38#define cfgPSWUSCFG0_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000
39#define cfgPSWUSCFG0_IO_BASE_LIMIT_DEFAULT 0x00000000
40#define cfgPSWUSCFG0_SECONDARY_STATUS_DEFAULT 0x00000000
41#define cfgPSWUSCFG0_MEM_BASE_LIMIT_DEFAULT 0x00000000
42#define cfgPSWUSCFG0_PREF_BASE_LIMIT_DEFAULT 0x00000000
43#define cfgPSWUSCFG0_PREF_BASE_UPPER_DEFAULT 0x00000000
44#define cfgPSWUSCFG0_PREF_LIMIT_UPPER_DEFAULT 0x00000000
45#define cfgPSWUSCFG0_IO_BASE_LIMIT_HI_DEFAULT 0x00000000
46#define cfgPSWUSCFG0_CAP_PTR_DEFAULT 0x00000000
47#define cfgPSWUSCFG0_INTERRUPT_LINE_DEFAULT 0x000000ff
48#define cfgPSWUSCFG0_INTERRUPT_PIN_DEFAULT 0x00000000
49#define cfgPSWUSCFG0_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000
50#define cfgEXT_BRIDGE_CNTL_DEFAULT 0x00000000
51#define cfgPSWUSCFG0_VENDOR_CAP_LIST_DEFAULT 0x00000000
52#define cfgPSWUSCFG0_ADAPTER_ID_W_DEFAULT 0x00000000
53#define cfgPSWUSCFG0_PMI_CAP_LIST_DEFAULT 0x00000000
54#define cfgPSWUSCFG0_PMI_CAP_DEFAULT 0x00000000
55#define cfgPSWUSCFG0_PMI_STATUS_CNTL_DEFAULT 0x00000000
56#define cfgPSWUSCFG0_PCIE_CAP_LIST_DEFAULT 0x0000a000
57#define cfgPSWUSCFG0_PCIE_CAP_DEFAULT 0x00000002
58#define cfgPSWUSCFG0_DEVICE_CAP_DEFAULT 0x00000000
59#define cfgPSWUSCFG0_DEVICE_CNTL_DEFAULT 0x00002810
60#define cfgPSWUSCFG0_DEVICE_STATUS_DEFAULT 0x00000000
61#define cfgPSWUSCFG0_LINK_CAP_DEFAULT 0x00011c03
62#define cfgPSWUSCFG0_LINK_CNTL_DEFAULT 0x00000000
63#define cfgPSWUSCFG0_LINK_STATUS_DEFAULT 0x00000001
64#define cfgPSWUSCFG0_DEVICE_CAP2_DEFAULT 0x00000000
65#define cfgPSWUSCFG0_DEVICE_CNTL2_DEFAULT 0x00000000
66#define cfgPSWUSCFG0_DEVICE_STATUS2_DEFAULT 0x00000000
67#define cfgPSWUSCFG0_LINK_CAP2_DEFAULT 0x0000000e
68#define cfgPSWUSCFG0_LINK_CNTL2_DEFAULT 0x00000003
69#define cfgPSWUSCFG0_LINK_STATUS2_DEFAULT 0x00000000
70#define cfgPSWUSCFG0_MSI_CAP_LIST_DEFAULT 0x0000c000
71#define cfgPSWUSCFG0_MSI_MSG_CNTL_DEFAULT 0x00000000
72#define cfgPSWUSCFG0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
73#define cfgPSWUSCFG0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
74#define cfgPSWUSCFG0_MSI_MSG_DATA_DEFAULT 0x00000000
75#define cfgPSWUSCFG0_MSI_MSG_DATA_64_DEFAULT 0x00000000
76#define cfgPSWUSCFG0_SSID_CAP_LIST_DEFAULT 0x0000c800
77#define cfgPSWUSCFG0_SSID_CAP_DEFAULT 0x00000000
78#define cfgMSI_MAP_CAP_LIST_DEFAULT 0x00000000
79#define cfgMSI_MAP_CAP_DEFAULT 0x00000000
80#define cfgMSI_MAP_ADDR_LO_DEFAULT 0x00000000
81#define cfgMSI_MAP_ADDR_HI_DEFAULT 0x00000000
82#define cfgPSWUSCFG0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
83#define cfgPSWUSCFG0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
84#define cfgPSWUSCFG0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
85#define cfgPSWUSCFG0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
86#define cfgPSWUSCFG0_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000
87#define cfgPSWUSCFG0_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000
88#define cfgPSWUSCFG0_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000
89#define cfgPSWUSCFG0_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000
90#define cfgPSWUSCFG0_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000
91#define cfgPSWUSCFG0_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000
92#define cfgPSWUSCFG0_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe
93#define cfgPSWUSCFG0_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000002
94#define cfgPSWUSCFG0_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000
95#define cfgPSWUSCFG0_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000
96#define cfgPSWUSCFG0_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000002
97#define cfgPSWUSCFG0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000
98#define cfgPSWUSCFG0_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000
99#define cfgPSWUSCFG0_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000
100#define cfgPSWUSCFG0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x27020000
101#define cfgPSWUSCFG0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
102#define cfgPSWUSCFG0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00400000
103#define cfgPSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
104#define cfgPSWUSCFG0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
105#define cfgPSWUSCFG0_PCIE_CORR_ERR_MASK_DEFAULT 0x00006000
106#define cfgPSWUSCFG0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
107#define cfgPSWUSCFG0_PCIE_HDR_LOG0_DEFAULT 0x00000000
108#define cfgPSWUSCFG0_PCIE_HDR_LOG1_DEFAULT 0x00000000
109#define cfgPSWUSCFG0_PCIE_HDR_LOG2_DEFAULT 0x00000000
110#define cfgPSWUSCFG0_PCIE_HDR_LOG3_DEFAULT 0x00000000
111#define cfgPSWUSCFG0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
112#define cfgPSWUSCFG0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
113#define cfgPSWUSCFG0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
114#define cfgPSWUSCFG0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
115#define cfgPSWUSCFG0_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a000000
116#define cfgPSWUSCFG0_PCIE_LINK_CNTL3_DEFAULT 0x00000000
117#define cfgPSWUSCFG0_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000
118#define cfgPSWUSCFG0_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
119#define cfgPSWUSCFG0_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
120#define cfgPSWUSCFG0_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
121#define cfgPSWUSCFG0_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
122#define cfgPSWUSCFG0_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
123#define cfgPSWUSCFG0_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
124#define cfgPSWUSCFG0_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
125#define cfgPSWUSCFG0_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
126#define cfgPSWUSCFG0_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
127#define cfgPSWUSCFG0_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
128#define cfgPSWUSCFG0_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
129#define cfgPSWUSCFG0_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
130#define cfgPSWUSCFG0_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
131#define cfgPSWUSCFG0_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
132#define cfgPSWUSCFG0_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
133#define cfgPSWUSCFG0_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f7f
134#define cfgPSWUSCFG0_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2f000000
135#define cfgPSWUSCFG0_PCIE_ACS_CAP_DEFAULT 0x00000000
136#define cfgPSWUSCFG0_PCIE_ACS_CNTL_DEFAULT 0x00000000
137#define cfgPSWUSCFG0_PCIE_MC_ENH_CAP_LIST_DEFAULT 0x32000000
138#define cfgPSWUSCFG0_PCIE_MC_CAP_DEFAULT 0x00000000
139#define cfgPSWUSCFG0_PCIE_MC_CNTL_DEFAULT 0x00000000
140#define cfgPSWUSCFG0_PCIE_MC_ADDR0_DEFAULT 0x00000000
141#define cfgPSWUSCFG0_PCIE_MC_ADDR1_DEFAULT 0x00000000
142#define cfgPSWUSCFG0_PCIE_MC_RCV0_DEFAULT 0x00000000
143#define cfgPSWUSCFG0_PCIE_MC_RCV1_DEFAULT 0x00000000
144#define cfgPSWUSCFG0_PCIE_MC_BLOCK_ALL0_DEFAULT 0x00000000
145#define cfgPSWUSCFG0_PCIE_MC_BLOCK_ALL1_DEFAULT 0x00000000
146#define cfgPSWUSCFG0_PCIE_MC_BLOCK_UNTRANSLATED_0_DEFAULT 0x00000000
147#define cfgPSWUSCFG0_PCIE_MC_BLOCK_UNTRANSLATED_1_DEFAULT 0x00000000
148#define cfgPCIE_MC_OVERLAY_BAR0_DEFAULT 0x00000000
149#define cfgPCIE_MC_OVERLAY_BAR1_DEFAULT 0x00000000
150#define cfgPSWUSCFG0_PCIE_LTR_ENH_CAP_LIST_DEFAULT 0x32800000
151#define cfgPSWUSCFG0_PCIE_LTR_CAP_DEFAULT 0x00000000
152#define cfgPSWUSCFG0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x38000000
153#define cfgPSWUSCFG0_PCIE_ARI_CAP_DEFAULT 0x00000000
154#define cfgPSWUSCFG0_PCIE_ARI_CNTL_DEFAULT 0x00000000
155#define cfgPCIE_L1_PM_SUB_CAP_LIST_DEFAULT 0x00000000
156#define cfgPCIE_L1_PM_SUB_CAP_DEFAULT 0x00000000
157#define cfgPCIE_L1_PM_SUB_CNTL_DEFAULT 0x00000000
158#define cfgPCIE_L1_PM_SUB_CNTL2_DEFAULT 0x00000028
159#define cfgPCIE_ESM_CAP_LIST_DEFAULT 0x00000000
160#define cfgPCIE_ESM_HEADER_1_DEFAULT 0x00000000
161#define cfgPCIE_ESM_HEADER_2_DEFAULT 0x00000000
162#define cfgPCIE_ESM_STATUS_DEFAULT 0x00000000
163#define cfgPCIE_ESM_CTRL_DEFAULT 0x00000000
164#define cfgPCIE_ESM_CAP_1_DEFAULT 0x00000000
165#define cfgPCIE_ESM_CAP_2_DEFAULT 0x00000000
166#define cfgPCIE_ESM_CAP_3_DEFAULT 0x00000000
167#define cfgPCIE_ESM_CAP_4_DEFAULT 0x00000000
168#define cfgPCIE_ESM_CAP_5_DEFAULT 0x00000000
169#define cfgPCIE_ESM_CAP_6_DEFAULT 0x00000000
170#define cfgPCIE_ESM_CAP_7_DEFAULT 0x00000000
171
172
173// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_bifcfgdecp
174#define cfgBIF_CFG_DEV0_EPF0_0_VENDOR_ID_DEFAULT 0x00000000
175#define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_ID_DEFAULT 0x00000000
176#define cfgBIF_CFG_DEV0_EPF0_0_COMMAND_DEFAULT 0x00000000
177#define cfgBIF_CFG_DEV0_EPF0_0_STATUS_DEFAULT 0x00000000
178#define cfgBIF_CFG_DEV0_EPF0_0_REVISION_ID_DEFAULT 0x00000000
179#define cfgBIF_CFG_DEV0_EPF0_0_PROG_INTERFACE_DEFAULT 0x00000000
180#define cfgBIF_CFG_DEV0_EPF0_0_SUB_CLASS_DEFAULT 0x00000000
181#define cfgBIF_CFG_DEV0_EPF0_0_BASE_CLASS_DEFAULT 0x00000000
182#define cfgBIF_CFG_DEV0_EPF0_0_CACHE_LINE_DEFAULT 0x00000000
183#define cfgBIF_CFG_DEV0_EPF0_0_LATENCY_DEFAULT 0x00000000
184#define cfgBIF_CFG_DEV0_EPF0_0_HEADER_DEFAULT 0x00000000
185#define cfgBIF_CFG_DEV0_EPF0_0_BIST_DEFAULT 0x00000000
186#define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_1_DEFAULT 0x00000000
187#define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_2_DEFAULT 0x00000000
188#define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_3_DEFAULT 0x00000000
189#define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_4_DEFAULT 0x00000000
190#define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_5_DEFAULT 0x00000000
191#define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_6_DEFAULT 0x00000000
192#define cfgBIF_CFG_DEV0_EPF0_0_ADAPTER_ID_DEFAULT 0x00000000
193#define cfgBIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR_DEFAULT 0x00000000
194#define cfgBIF_CFG_DEV0_EPF0_0_CAP_PTR_DEFAULT 0x00000000
195#define cfgBIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE_DEFAULT 0x000000ff
196#define cfgBIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN_DEFAULT 0x00000000
197#define cfgBIF_CFG_DEV0_EPF0_0_MIN_GRANT_DEFAULT 0x00000000
198#define cfgBIF_CFG_DEV0_EPF0_0_MAX_LATENCY_DEFAULT 0x00000000
199#define cfgBIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST_DEFAULT 0x00000000
200#define cfgBIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W_DEFAULT 0x00000000
201#define cfgBIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST_DEFAULT 0x00000000
202#define cfgBIF_CFG_DEV0_EPF0_0_PMI_CAP_DEFAULT 0x00000000
203#define cfgBIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL_DEFAULT 0x00000000
204#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST_DEFAULT 0x0000a000
205#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_CAP_DEFAULT 0x00000002
206#define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_CAP_DEFAULT 0x10000000
207#define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL_DEFAULT 0x00002810
208#define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS_DEFAULT 0x00000000
209#define cfgBIF_CFG_DEV0_EPF0_0_LINK_CAP_DEFAULT 0x00011c03
210#define cfgBIF_CFG_DEV0_EPF0_0_LINK_CNTL_DEFAULT 0x00000000
211#define cfgBIF_CFG_DEV0_EPF0_0_LINK_STATUS_DEFAULT 0x00000001
212#define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_CAP2_DEFAULT 0x00000000
213#define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2_DEFAULT 0x00000000
214#define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2_DEFAULT 0x00000000
215#define cfgBIF_CFG_DEV0_EPF0_0_LINK_CAP2_DEFAULT 0x0000000e
216#define cfgBIF_CFG_DEV0_EPF0_0_LINK_CNTL2_DEFAULT 0x00000003
217#define cfgBIF_CFG_DEV0_EPF0_0_LINK_STATUS2_DEFAULT 0x00000000
218#define cfgBIF_CFG_DEV0_EPF0_0_SLOT_CAP2_DEFAULT 0x00000000
219#define cfgBIF_CFG_DEV0_EPF0_0_SLOT_CNTL2_DEFAULT 0x00000000
220#define cfgBIF_CFG_DEV0_EPF0_0_SLOT_STATUS2_DEFAULT 0x00000000
221#define cfgBIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST_DEFAULT 0x0000c000
222#define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL_DEFAULT 0x00000080
223#define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
224#define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
225#define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_DEFAULT 0x00000000
226#define cfgBIF_CFG_DEV0_EPF0_0_MSI_MASK_DEFAULT 0x00000000
227#define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64_DEFAULT 0x00000000
228#define cfgBIF_CFG_DEV0_EPF0_0_MSI_MASK_64_DEFAULT 0x00000000
229#define cfgBIF_CFG_DEV0_EPF0_0_MSI_PENDING_DEFAULT 0x00000000
230#define cfgBIF_CFG_DEV0_EPF0_0_MSI_PENDING_64_DEFAULT 0x00000000
231#define cfgBIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST_DEFAULT 0x00000000
232#define cfgBIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL_DEFAULT 0x00000000
233#define cfgBIF_CFG_DEV0_EPF0_0_MSIX_TABLE_DEFAULT 0x00000000
234#define cfgBIF_CFG_DEV0_EPF0_0_MSIX_PBA_DEFAULT 0x00000000
235#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
236#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
237#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
238#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
239#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000
240#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000
241#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000
242#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000
243#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000
244#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000
245#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe
246#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000000
247#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000
248#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000
249#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000000
250#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000
251#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000
252#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000
253#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
254#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
255#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
256#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
257#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
258#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000
259#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
260#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0_DEFAULT 0x00000000
261#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1_DEFAULT 0x00000000
262#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2_DEFAULT 0x00000000
263#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3_DEFAULT 0x00000000
264#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
265#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
266#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
267#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
268#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000
269#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP_DEFAULT 0x00000000
270#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL_DEFAULT 0x00000020
271#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP_DEFAULT 0x00000000
272#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL_DEFAULT 0x00000000
273#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP_DEFAULT 0x00000000
274#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL_DEFAULT 0x00000000
275#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP_DEFAULT 0x00000000
276#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL_DEFAULT 0x00000000
277#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP_DEFAULT 0x00000000
278#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL_DEFAULT 0x00000000
279#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP_DEFAULT 0x00000000
280#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL_DEFAULT 0x00000000
281#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000
282#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000
283#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000
284#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000
285#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000
286#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP_DEFAULT 0x00000000
287#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000
288#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS_DEFAULT 0x00000100
289#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL_DEFAULT 0x00000000
290#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000
291#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000
292#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000
293#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000
294#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000
295#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000
296#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000
297#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000
298#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a010019
299#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3_DEFAULT 0x00000000
300#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000
301#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f00
302#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f00
303#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f00
304#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f00
305#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f00
306#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f00
307#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f00
308#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f00
309#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f00
310#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f00
311#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f00
312#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f00
313#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f00
314#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f00
315#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f00
316#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f00
317#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000
318#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP_DEFAULT 0x00000000
319#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL_DEFAULT 0x00000000
320#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
321#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP_DEFAULT 0x00000000
322#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL_DEFAULT 0x00000000
323#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST_DEFAULT 0x2d000000
324#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL_DEFAULT 0x00000000
325#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS_DEFAULT 0x00000000
326#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY_DEFAULT 0x00000000
327#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC_DEFAULT 0x00000000
328#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST_DEFAULT 0x2e000000
329#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP_DEFAULT 0x00000000
330#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL_DEFAULT 0x00000000
331#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST_DEFAULT 0x2f000000
332#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP_DEFAULT 0x00000000
333#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CNTL_DEFAULT 0x00000000
334#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST_DEFAULT 0x32000000
335#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP_DEFAULT 0x00000000
336#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL_DEFAULT 0x00000000
337#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0_DEFAULT 0x00000000
338#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR1_DEFAULT 0x00000000
339#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV0_DEFAULT 0x00000000
340#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV1_DEFAULT 0x00000000
341#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL0_DEFAULT 0x00000000
342#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL1_DEFAULT 0x00000000
343#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_0_DEFAULT 0x00000000
344#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_1_DEFAULT 0x00000000
345#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST_DEFAULT 0x32800000
346#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP_DEFAULT 0x00000000
347#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000
348#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP_DEFAULT 0x00000000
349#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL_DEFAULT 0x00000000
350#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST_DEFAULT 0x00000000
351#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP_DEFAULT 0x00000000
352#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL_DEFAULT 0x00000000
353#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS_DEFAULT 0x00000000
354#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS_DEFAULT 0x00000000
355#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS_DEFAULT 0x00000000
356#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS_DEFAULT 0x00000000
357#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK_DEFAULT 0x00000000
358#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET_DEFAULT 0x00000000
359#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE_DEFAULT 0x00000000
360#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID_DEFAULT 0x00000000
361#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE_DEFAULT 0x00000000
362#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE_DEFAULT 0x00000001
363#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0_DEFAULT 0x00000000
364#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1_DEFAULT 0x00000000
365#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2_DEFAULT 0x00000000
366#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3_DEFAULT 0x00000000
367#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4_DEFAULT 0x00000000
368#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5_DEFAULT 0x00000000
369#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_DEFAULT 0x00000000
370#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_DEFAULT 0x00000000
371#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_DEFAULT 0x00000000
372#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW_DEFAULT 0x00000000
373#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_DEFAULT 0x00000000
374#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_DEFAULT 0x00000000
375#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_DEFAULT 0x00000000
376#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0_DEFAULT 0x00000000
377#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_DEFAULT 0x00000000
378#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2_DEFAULT 0x00000000
379#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT_DEFAULT 0x00000000
380#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB_DEFAULT 0x00000000
381#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS_DEFAULT 0x00000000
382#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB_DEFAULT 0x00000000
383#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB_DEFAULT 0x00000000
384#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB_DEFAULT 0x00000000
385#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB_DEFAULT 0x00000000
386#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB_DEFAULT 0x00000000
387#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB_DEFAULT 0x00000000
388#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB_DEFAULT 0x00000000
389#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB_DEFAULT 0x00000000
390#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB_DEFAULT 0x00000000
391#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB_DEFAULT 0x00000000
392#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB_DEFAULT 0x00000000
393#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB_DEFAULT 0x00000000
394#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB_DEFAULT 0x00000000
395#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB_DEFAULT 0x00000000
396#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB_DEFAULT 0x00000000
397#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB_DEFAULT 0x00000000
398#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0_DEFAULT 0x00000000
399#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1_DEFAULT 0x00000000
400#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2_DEFAULT 0x00000000
401#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3_DEFAULT 0x00000000
402#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4_DEFAULT 0x00000000
403#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5_DEFAULT 0x00000000
404#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6_DEFAULT 0x00000000
405#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7_DEFAULT 0x00000000
406#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8_DEFAULT 0x00000000
407#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0_DEFAULT 0x00000000
408#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1_DEFAULT 0x00000000
409#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2_DEFAULT 0x00000000
410#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3_DEFAULT 0x00000000
411#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4_DEFAULT 0x00000000
412#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5_DEFAULT 0x00000000
413#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6_DEFAULT 0x00000000
414#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7_DEFAULT 0x00000000
415#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8_DEFAULT 0x00000000
416#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0_DEFAULT 0x00000000
417#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1_DEFAULT 0x00000000
418#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2_DEFAULT 0x00000000
419#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3_DEFAULT 0x00000000
420#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4_DEFAULT 0x00000000
421#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5_DEFAULT 0x00000000
422#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6_DEFAULT 0x00000000
423#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7_DEFAULT 0x00000000
424#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8_DEFAULT 0x00000000
425
426
427// addressBlock: nbio_nbif_bif_cfg_dev0_epf1_bifcfgdecp
428#define cfgBIF_CFG_DEV0_EPF1_0_VENDOR_ID_DEFAULT 0x00000000
429#define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_ID_DEFAULT 0x00000000
430#define cfgBIF_CFG_DEV0_EPF1_0_COMMAND_DEFAULT 0x00000000
431#define cfgBIF_CFG_DEV0_EPF1_0_STATUS_DEFAULT 0x00000000
432#define cfgBIF_CFG_DEV0_EPF1_0_REVISION_ID_DEFAULT 0x00000000
433#define cfgBIF_CFG_DEV0_EPF1_0_PROG_INTERFACE_DEFAULT 0x00000000
434#define cfgBIF_CFG_DEV0_EPF1_0_SUB_CLASS_DEFAULT 0x00000000
435#define cfgBIF_CFG_DEV0_EPF1_0_BASE_CLASS_DEFAULT 0x00000000
436#define cfgBIF_CFG_DEV0_EPF1_0_CACHE_LINE_DEFAULT 0x00000000
437#define cfgBIF_CFG_DEV0_EPF1_0_LATENCY_DEFAULT 0x00000000
438#define cfgBIF_CFG_DEV0_EPF1_0_HEADER_DEFAULT 0x00000000
439#define cfgBIF_CFG_DEV0_EPF1_0_BIST_DEFAULT 0x00000000
440#define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_1_DEFAULT 0x00000000
441#define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_2_DEFAULT 0x00000000
442#define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_3_DEFAULT 0x00000000
443#define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_4_DEFAULT 0x00000000
444#define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_5_DEFAULT 0x00000000
445#define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_6_DEFAULT 0x00000000
446#define cfgBIF_CFG_DEV0_EPF1_0_ADAPTER_ID_DEFAULT 0x00000000
447#define cfgBIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR_DEFAULT 0x00000000
448#define cfgBIF_CFG_DEV0_EPF1_0_CAP_PTR_DEFAULT 0x00000000
449#define cfgBIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE_DEFAULT 0x000000ff
450#define cfgBIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN_DEFAULT 0x00000000
451#define cfgBIF_CFG_DEV0_EPF1_0_MIN_GRANT_DEFAULT 0x00000000
452#define cfgBIF_CFG_DEV0_EPF1_0_MAX_LATENCY_DEFAULT 0x00000000
453#define cfgBIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST_DEFAULT 0x00000000
454#define cfgBIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W_DEFAULT 0x00000000
455#define cfgBIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST_DEFAULT 0x00000000
456#define cfgBIF_CFG_DEV0_EPF1_0_PMI_CAP_DEFAULT 0x00000000
457#define cfgBIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL_DEFAULT 0x00000000
458#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST_DEFAULT 0x0000a000
459#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CAP_DEFAULT 0x00000002
460#define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CAP_DEFAULT 0x10000000
461#define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CNTL_DEFAULT 0x00002810
462#define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_STATUS_DEFAULT 0x00000000
463#define cfgBIF_CFG_DEV0_EPF1_0_LINK_CAP_DEFAULT 0x00011c03
464#define cfgBIF_CFG_DEV0_EPF1_0_LINK_CNTL_DEFAULT 0x00000000
465#define cfgBIF_CFG_DEV0_EPF1_0_LINK_STATUS_DEFAULT 0x00000001
466#define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CAP2_DEFAULT 0x00000000
467#define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2_DEFAULT 0x00000000
468#define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2_DEFAULT 0x00000000
469#define cfgBIF_CFG_DEV0_EPF1_0_LINK_CAP2_DEFAULT 0x0000000e
470#define cfgBIF_CFG_DEV0_EPF1_0_LINK_CNTL2_DEFAULT 0x00000003
471#define cfgBIF_CFG_DEV0_EPF1_0_LINK_STATUS2_DEFAULT 0x00000000
472#define cfgBIF_CFG_DEV0_EPF1_0_SLOT_CAP2_DEFAULT 0x00000000
473#define cfgBIF_CFG_DEV0_EPF1_0_SLOT_CNTL2_DEFAULT 0x00000000
474#define cfgBIF_CFG_DEV0_EPF1_0_SLOT_STATUS2_DEFAULT 0x00000000
475#define cfgBIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST_DEFAULT 0x0000c000
476#define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL_DEFAULT 0x00000080
477#define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
478#define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
479#define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_DEFAULT 0x00000000
480#define cfgBIF_CFG_DEV0_EPF1_0_MSI_MASK_DEFAULT 0x00000000
481#define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64_DEFAULT 0x00000000
482#define cfgBIF_CFG_DEV0_EPF1_0_MSI_MASK_64_DEFAULT 0x00000000
483#define cfgBIF_CFG_DEV0_EPF1_0_MSI_PENDING_DEFAULT 0x00000000
484#define cfgBIF_CFG_DEV0_EPF1_0_MSI_PENDING_64_DEFAULT 0x00000000
485#define cfgBIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST_DEFAULT 0x00000000
486#define cfgBIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL_DEFAULT 0x00000000
487#define cfgBIF_CFG_DEV0_EPF1_0_MSIX_TABLE_DEFAULT 0x00000000
488#define cfgBIF_CFG_DEV0_EPF1_0_MSIX_PBA_DEFAULT 0x00000000
489#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
490#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
491#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
492#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
493#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000
494#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000
495#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000
496#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000
497#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000
498#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000
499#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe
500#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000000
501#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000
502#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000
503#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000000
504#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000
505#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000
506#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000
507#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
508#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
509#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
510#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
511#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
512#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000
513#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
514#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0_DEFAULT 0x00000000
515#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1_DEFAULT 0x00000000
516#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2_DEFAULT 0x00000000
517#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3_DEFAULT 0x00000000
518#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
519#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
520#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
521#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
522#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000
523#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP_DEFAULT 0x00000000
524#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL_DEFAULT 0x00000020
525#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP_DEFAULT 0x00000000
526#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL_DEFAULT 0x00000000
527#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP_DEFAULT 0x00000000
528#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL_DEFAULT 0x00000000
529#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP_DEFAULT 0x00000000
530#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL_DEFAULT 0x00000000
531#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP_DEFAULT 0x00000000
532#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL_DEFAULT 0x00000000
533#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP_DEFAULT 0x00000000
534#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL_DEFAULT 0x00000000
535#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000
536#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000
537#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000
538#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000
539#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000
540#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP_DEFAULT 0x00000000
541#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000
542#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS_DEFAULT 0x00000100
543#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL_DEFAULT 0x00000000
544#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000
545#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000
546#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000
547#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000
548#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000
549#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000
550#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000
551#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000
552#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a010019
553#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3_DEFAULT 0x00000000
554#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000
555#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f00
556#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f00
557#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f00
558#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f00
559#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f00
560#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f00
561#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f00
562#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f00
563#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f00
564#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f00
565#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f00
566#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f00
567#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f00
568#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f00
569#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f00
570#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f00
571#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000
572#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP_DEFAULT 0x00000000
573#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL_DEFAULT 0x00000000
574#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
575#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP_DEFAULT 0x00000000
576#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ATS_CNTL_DEFAULT 0x00000000
577#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST_DEFAULT 0x2d000000
578#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_CNTL_DEFAULT 0x00000000
579#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS_DEFAULT 0x00000000
580#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY_DEFAULT 0x00000000
581#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC_DEFAULT 0x00000000
582#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST_DEFAULT 0x2e000000
583#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP_DEFAULT 0x00000000
584#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL_DEFAULT 0x00000000
585#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST_DEFAULT 0x2f000000
586#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP_DEFAULT 0x00000000
587#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CNTL_DEFAULT 0x00000000
588#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST_DEFAULT 0x32000000
589#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP_DEFAULT 0x00000000
590#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL_DEFAULT 0x00000000
591#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0_DEFAULT 0x00000000
592#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR1_DEFAULT 0x00000000
593#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV0_DEFAULT 0x00000000
594#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV1_DEFAULT 0x00000000
595#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL0_DEFAULT 0x00000000
596#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL1_DEFAULT 0x00000000
597#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_0_DEFAULT 0x00000000
598#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_1_DEFAULT 0x00000000
599#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST_DEFAULT 0x32800000
600#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP_DEFAULT 0x00000000
601#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000
602#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP_DEFAULT 0x00000000
603#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL_DEFAULT 0x00000000
604#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST_DEFAULT 0x00000000
605#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP_DEFAULT 0x00000000
606#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL_DEFAULT 0x00000000
607#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_STATUS_DEFAULT 0x00000000
608#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_INITIAL_VFS_DEFAULT 0x00000000
609#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_TOTAL_VFS_DEFAULT 0x00000000
610#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_NUM_VFS_DEFAULT 0x00000000
611#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FUNC_DEP_LINK_DEFAULT 0x00000000
612#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FIRST_VF_OFFSET_DEFAULT 0x00000000
613#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_STRIDE_DEFAULT 0x00000000
614#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_DEVICE_ID_DEFAULT 0x00000000
615#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE_DEFAULT 0x00000000
616#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE_DEFAULT 0x00000001
617#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_0_DEFAULT 0x00000000
618#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_1_DEFAULT 0x00000000
619#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_2_DEFAULT 0x00000000
620#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_3_DEFAULT 0x00000000
621#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_4_DEFAULT 0x00000000
622#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_5_DEFAULT 0x00000000
623#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_DEFAULT 0x00000000
624#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_DEFAULT 0x00000000
625#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_DEFAULT 0x00000000
626#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW_DEFAULT 0x00000000
627#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_DEFAULT 0x00000000
628#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_DEFAULT 0x00000000
629#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_DEFAULT 0x00000000
630#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0_DEFAULT 0x00000000
631#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_DEFAULT 0x00000000
632#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2_DEFAULT 0x00000000
633#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT_DEFAULT 0x00000000
634#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB_DEFAULT 0x00000000
635#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS_DEFAULT 0x00000000
636#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB_DEFAULT 0x00000000
637#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB_DEFAULT 0x00000000
638#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB_DEFAULT 0x00000000
639#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB_DEFAULT 0x00000000
640#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB_DEFAULT 0x00000000
641#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB_DEFAULT 0x00000000
642#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB_DEFAULT 0x00000000
643#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB_DEFAULT 0x00000000
644#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB_DEFAULT 0x00000000
645#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB_DEFAULT 0x00000000
646#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB_DEFAULT 0x00000000
647#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB_DEFAULT 0x00000000
648#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB_DEFAULT 0x00000000
649#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB_DEFAULT 0x00000000
650#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB_DEFAULT 0x00000000
651#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB_DEFAULT 0x00000000
652#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0_DEFAULT 0x00000000
653#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1_DEFAULT 0x00000000
654#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2_DEFAULT 0x00000000
655#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3_DEFAULT 0x00000000
656#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4_DEFAULT 0x00000000
657#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5_DEFAULT 0x00000000
658#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6_DEFAULT 0x00000000
659#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7_DEFAULT 0x00000000
660#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8_DEFAULT 0x00000000
661#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0_DEFAULT 0x00000000
662#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1_DEFAULT 0x00000000
663#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2_DEFAULT 0x00000000
664#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3_DEFAULT 0x00000000
665#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4_DEFAULT 0x00000000
666#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5_DEFAULT 0x00000000
667#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6_DEFAULT 0x00000000
668#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7_DEFAULT 0x00000000
669#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8_DEFAULT 0x00000000
670#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0_DEFAULT 0x00000000
671#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1_DEFAULT 0x00000000
672#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2_DEFAULT 0x00000000
673#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3_DEFAULT 0x00000000
674#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4_DEFAULT 0x00000000
675#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5_DEFAULT 0x00000000
676#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6_DEFAULT 0x00000000
677#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7_DEFAULT 0x00000000
678#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8_DEFAULT 0x00000000
679
680
681// addressBlock: nbio_nbif_bif_cfg_dev0_swds_bifcfgdecp
682#define cfgBIF_CFG_DEV0_SWDS0_VENDOR_ID_DEFAULT 0x00000000
683#define cfgBIF_CFG_DEV0_SWDS0_DEVICE_ID_DEFAULT 0x00000000
684#define cfgBIF_CFG_DEV0_SWDS0_COMMAND_DEFAULT 0x00000000
685#define cfgBIF_CFG_DEV0_SWDS0_STATUS_DEFAULT 0x00000000
686#define cfgBIF_CFG_DEV0_SWDS0_REVISION_ID_DEFAULT 0x00000000
687#define cfgBIF_CFG_DEV0_SWDS0_PROG_INTERFACE_DEFAULT 0x00000000
688#define cfgBIF_CFG_DEV0_SWDS0_SUB_CLASS_DEFAULT 0x00000000
689#define cfgBIF_CFG_DEV0_SWDS0_BASE_CLASS_DEFAULT 0x00000000
690#define cfgBIF_CFG_DEV0_SWDS0_CACHE_LINE_DEFAULT 0x00000000
691#define cfgBIF_CFG_DEV0_SWDS0_LATENCY_DEFAULT 0x00000000
692#define cfgBIF_CFG_DEV0_SWDS0_HEADER_DEFAULT 0x00000000
693#define cfgBIF_CFG_DEV0_SWDS0_BIST_DEFAULT 0x00000000
694#define cfgBIF_CFG_DEV0_SWDS0_BASE_ADDR_1_DEFAULT 0x00000000
695#define cfgBIF_CFG_DEV0_SWDS0_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000
696#define cfgBIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT_DEFAULT 0x00000000
697#define cfgBIF_CFG_DEV0_SWDS0_SECONDARY_STATUS_DEFAULT 0x00000000
698#define cfgBIF_CFG_DEV0_SWDS0_MEM_BASE_LIMIT_DEFAULT 0x00000000
699#define cfgBIF_CFG_DEV0_SWDS0_PREF_BASE_LIMIT_DEFAULT 0x00000000
700#define cfgBIF_CFG_DEV0_SWDS0_PREF_BASE_UPPER_DEFAULT 0x00000000
701#define cfgBIF_CFG_DEV0_SWDS0_PREF_LIMIT_UPPER_DEFAULT 0x00000000
702#define cfgBIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT_HI_DEFAULT 0x00000000
703#define cfgBIF_CFG_DEV0_SWDS0_CAP_PTR_DEFAULT 0x00000000
704#define cfgBIF_CFG_DEV0_SWDS0_INTERRUPT_LINE_DEFAULT 0x000000ff
705#define cfgBIF_CFG_DEV0_SWDS0_INTERRUPT_PIN_DEFAULT 0x00000001
706#define cfgBIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000
707#define cfgBIF_CFG_DEV0_SWDS0_PMI_CAP_LIST_DEFAULT 0x00000000
708#define cfgBIF_CFG_DEV0_SWDS0_PMI_CAP_DEFAULT 0x00000000
709#define cfgBIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL_DEFAULT 0x00000000
710#define cfgBIF_CFG_DEV0_SWDS0_PCIE_CAP_LIST_DEFAULT 0x0000a000
711#define cfgBIF_CFG_DEV0_SWDS0_PCIE_CAP_DEFAULT 0x00000062
712#define cfgBIF_CFG_DEV0_SWDS0_DEVICE_CAP_DEFAULT 0x00000000
713#define cfgBIF_CFG_DEV0_SWDS0_DEVICE_CNTL_DEFAULT 0x00002810
714#define cfgBIF_CFG_DEV0_SWDS0_DEVICE_STATUS_DEFAULT 0x00000000
715#define cfgBIF_CFG_DEV0_SWDS0_LINK_CAP_DEFAULT 0x00011c03
716#define cfgBIF_CFG_DEV0_SWDS0_LINK_CNTL_DEFAULT 0x00000000
717#define cfgBIF_CFG_DEV0_SWDS0_LINK_STATUS_DEFAULT 0x00002001
718#define cfgBIF_CFG_DEV0_SWDS0_SLOT_CAP_DEFAULT 0x00000000
719#define cfgBIF_CFG_DEV0_SWDS0_SLOT_CNTL_DEFAULT 0x00000000
720#define cfgBIF_CFG_DEV0_SWDS0_SLOT_STATUS_DEFAULT 0x00000000
721#define cfgBIF_CFG_DEV0_SWDS0_DEVICE_CAP2_DEFAULT 0x00000000
722#define cfgBIF_CFG_DEV0_SWDS0_DEVICE_CNTL2_DEFAULT 0x00000000
723#define cfgBIF_CFG_DEV0_SWDS0_DEVICE_STATUS2_DEFAULT 0x00000000
724#define cfgBIF_CFG_DEV0_SWDS0_LINK_CAP2_DEFAULT 0x0000000e
725#define cfgBIF_CFG_DEV0_SWDS0_LINK_CNTL2_DEFAULT 0x00000003
726#define cfgBIF_CFG_DEV0_SWDS0_LINK_STATUS2_DEFAULT 0x00000000
727#define cfgBIF_CFG_DEV0_SWDS0_SLOT_CAP2_DEFAULT 0x00000000
728#define cfgBIF_CFG_DEV0_SWDS0_SLOT_CNTL2_DEFAULT 0x00000000
729#define cfgBIF_CFG_DEV0_SWDS0_SLOT_STATUS2_DEFAULT 0x00000000
730#define cfgBIF_CFG_DEV0_SWDS0_MSI_CAP_LIST_DEFAULT 0x0000c000
731#define cfgBIF_CFG_DEV0_SWDS0_MSI_MSG_CNTL_DEFAULT 0x00000080
732#define cfgBIF_CFG_DEV0_SWDS0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
733#define cfgBIF_CFG_DEV0_SWDS0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
734#define cfgBIF_CFG_DEV0_SWDS0_MSI_MSG_DATA_DEFAULT 0x00000000
735#define cfgBIF_CFG_DEV0_SWDS0_MSI_MSG_DATA_64_DEFAULT 0x00000000
736#define cfgBIF_CFG_DEV0_SWDS0_SSID_CAP_LIST_DEFAULT 0x00000000
737#define cfgBIF_CFG_DEV0_SWDS0_SSID_CAP_DEFAULT 0x00000000
738#define cfgBIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
739#define cfgBIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
740#define cfgBIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
741#define cfgBIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
742#define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000
743#define cfgBIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000
744#define cfgBIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000
745#define cfgBIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000
746#define cfgBIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000
747#define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000
748#define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe
749#define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000000
750#define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000
751#define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000
752#define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000000
753#define cfgBIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000
754#define cfgBIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000
755#define cfgBIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000
756#define cfgBIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
757#define cfgBIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
758#define cfgBIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
759#define cfgBIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
760#define cfgBIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
761#define cfgBIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000
762#define cfgBIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
763#define cfgBIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG0_DEFAULT 0x00000000
764#define cfgBIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG1_DEFAULT 0x00000000
765#define cfgBIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG2_DEFAULT 0x00000000
766#define cfgBIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG3_DEFAULT 0x00000000
767#define cfgBIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
768#define cfgBIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
769#define cfgBIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
770#define cfgBIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
771#define cfgBIF_CFG_DEV0_SWDS0_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a000000
772#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LINK_CNTL3_DEFAULT 0x00000000
773#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000
774#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f0f
775#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f0f
776#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f0f
777#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f0f
778#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f0f
779#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f0f
780#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f0f
781#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f0f
782#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f0f
783#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f0f
784#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f0f
785#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f0f
786#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f0f
787#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f0f
788#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f0f
789#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f0f
790#define cfgBIF_CFG_DEV0_SWDS0_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2f000000
791#define cfgBIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP_DEFAULT 0x00000000
792#define cfgBIF_CFG_DEV0_SWDS0_PCIE_ACS_CNTL_DEFAULT 0x00000000
793
794
795// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf0_bifcfgdecp
796#define cfgBIF_CFG_DEV0_EPF0_VF0_0_VENDOR_ID_DEFAULT 0x00000000
797#define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_ID_DEFAULT 0x00000000
798#define cfgBIF_CFG_DEV0_EPF0_VF0_0_COMMAND_DEFAULT 0x00000000
799#define cfgBIF_CFG_DEV0_EPF0_VF0_0_STATUS_DEFAULT 0x00000000
800#define cfgBIF_CFG_DEV0_EPF0_VF0_0_REVISION_ID_DEFAULT 0x00000000
801#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PROG_INTERFACE_DEFAULT 0x00000000
802#define cfgBIF_CFG_DEV0_EPF0_VF0_0_SUB_CLASS_DEFAULT 0x00000000
803#define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_CLASS_DEFAULT 0x00000000
804#define cfgBIF_CFG_DEV0_EPF0_VF0_0_CACHE_LINE_DEFAULT 0x00000000
805#define cfgBIF_CFG_DEV0_EPF0_VF0_0_LATENCY_DEFAULT 0x00000000
806#define cfgBIF_CFG_DEV0_EPF0_VF0_0_HEADER_DEFAULT 0x00000000
807#define cfgBIF_CFG_DEV0_EPF0_VF0_0_BIST_DEFAULT 0x00000000
808#define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_1_DEFAULT 0x00000000
809#define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_2_DEFAULT 0x00000000
810#define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_3_DEFAULT 0x00000000
811#define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_4_DEFAULT 0x00000000
812#define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_5_DEFAULT 0x00000000
813#define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_6_DEFAULT 0x00000000
814#define cfgBIF_CFG_DEV0_EPF0_VF0_0_ADAPTER_ID_DEFAULT 0x00000000
815#define cfgBIF_CFG_DEV0_EPF0_VF0_0_ROM_BASE_ADDR_DEFAULT 0x00000000
816#define cfgBIF_CFG_DEV0_EPF0_VF0_0_CAP_PTR_DEFAULT 0x00000000
817#define cfgBIF_CFG_DEV0_EPF0_VF0_0_INTERRUPT_LINE_DEFAULT 0x000000ff
818#define cfgBIF_CFG_DEV0_EPF0_VF0_0_INTERRUPT_PIN_DEFAULT 0x00000000
819#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP_LIST_DEFAULT 0x0000a000
820#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP_DEFAULT 0x00000002
821#define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP_DEFAULT 0x10000000
822#define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL_DEFAULT 0x00002810
823#define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS_DEFAULT 0x00000000
824#define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP_DEFAULT 0x00011c03
825#define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL_DEFAULT 0x00000000
826#define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS_DEFAULT 0x00000001
827#define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2_DEFAULT 0x00000000
828#define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2_DEFAULT 0x00000000
829#define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS2_DEFAULT 0x00000000
830#define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2_DEFAULT 0x0000000e
831#define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2_DEFAULT 0x00000003
832#define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2_DEFAULT 0x00000000
833#define cfgBIF_CFG_DEV0_EPF0_VF0_0_SLOT_CAP2_DEFAULT 0x00000000
834#define cfgBIF_CFG_DEV0_EPF0_VF0_0_SLOT_CNTL2_DEFAULT 0x00000000
835#define cfgBIF_CFG_DEV0_EPF0_VF0_0_SLOT_STATUS2_DEFAULT 0x00000000
836#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_CAP_LIST_DEFAULT 0x0000c000
837#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL_DEFAULT 0x00000080
838#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
839#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
840#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_DATA_DEFAULT 0x00000000
841#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MASK_DEFAULT 0x00000000
842#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_DATA_64_DEFAULT 0x00000000
843#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MASK_64_DEFAULT 0x00000000
844#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_PENDING_DEFAULT 0x00000000
845#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_PENDING_64_DEFAULT 0x00000000
846#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSIX_CAP_LIST_DEFAULT 0x00000000
847#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSIX_MSG_CNTL_DEFAULT 0x00000000
848#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSIX_TABLE_DEFAULT 0x00000000
849#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSIX_PBA_DEFAULT 0x00000000
850#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
851#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
852#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
853#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
854#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
855#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
856#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
857#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
858#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
859#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000
860#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
861#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG0_DEFAULT 0x00000000
862#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG1_DEFAULT 0x00000000
863#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG2_DEFAULT 0x00000000
864#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG3_DEFAULT 0x00000000
865#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
866#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
867#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
868#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
869#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
870#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_CAP_DEFAULT 0x00000000
871#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_CNTL_DEFAULT 0x00000000
872#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000
873#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CAP_DEFAULT 0x00000000
874#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CNTL_DEFAULT 0x00000000
875
876
877// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf1_bifcfgdecp
878#define cfgBIF_CFG_DEV0_EPF0_VF1_0_VENDOR_ID_DEFAULT 0x00000000
879#define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_ID_DEFAULT 0x00000000
880#define cfgBIF_CFG_DEV0_EPF0_VF1_0_COMMAND_DEFAULT 0x00000000
881#define cfgBIF_CFG_DEV0_EPF0_VF1_0_STATUS_DEFAULT 0x00000000
882#define cfgBIF_CFG_DEV0_EPF0_VF1_0_REVISION_ID_DEFAULT 0x00000000
883#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PROG_INTERFACE_DEFAULT 0x00000000
884#define cfgBIF_CFG_DEV0_EPF0_VF1_0_SUB_CLASS_DEFAULT 0x00000000
885#define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_CLASS_DEFAULT 0x00000000
886#define cfgBIF_CFG_DEV0_EPF0_VF1_0_CACHE_LINE_DEFAULT 0x00000000
887#define cfgBIF_CFG_DEV0_EPF0_VF1_0_LATENCY_DEFAULT 0x00000000
888#define cfgBIF_CFG_DEV0_EPF0_VF1_0_HEADER_DEFAULT 0x00000000
889#define cfgBIF_CFG_DEV0_EPF0_VF1_0_BIST_DEFAULT 0x00000000
890#define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_1_DEFAULT 0x00000000
891#define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_2_DEFAULT 0x00000000
892#define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_3_DEFAULT 0x00000000
893#define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_4_DEFAULT 0x00000000
894#define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_5_DEFAULT 0x00000000
895#define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_6_DEFAULT 0x00000000
896#define cfgBIF_CFG_DEV0_EPF0_VF1_0_ADAPTER_ID_DEFAULT 0x00000000
897#define cfgBIF_CFG_DEV0_EPF0_VF1_0_ROM_BASE_ADDR_DEFAULT 0x00000000
898#define cfgBIF_CFG_DEV0_EPF0_VF1_0_CAP_PTR_DEFAULT 0x00000000
899#define cfgBIF_CFG_DEV0_EPF0_VF1_0_INTERRUPT_LINE_DEFAULT 0x000000ff
900#define cfgBIF_CFG_DEV0_EPF0_VF1_0_INTERRUPT_PIN_DEFAULT 0x00000000
901#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP_LIST_DEFAULT 0x0000a000
902#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP_DEFAULT 0x00000002
903#define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP_DEFAULT 0x10000000
904#define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL_DEFAULT 0x00002810
905#define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS_DEFAULT 0x00000000
906#define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP_DEFAULT 0x00011c03
907#define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL_DEFAULT 0x00000000
908#define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS_DEFAULT 0x00000001
909#define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2_DEFAULT 0x00000000
910#define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2_DEFAULT 0x00000000
911#define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS2_DEFAULT 0x00000000
912#define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2_DEFAULT 0x0000000e
913#define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2_DEFAULT 0x00000003
914#define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2_DEFAULT 0x00000000
915#define cfgBIF_CFG_DEV0_EPF0_VF1_0_SLOT_CAP2_DEFAULT 0x00000000
916#define cfgBIF_CFG_DEV0_EPF0_VF1_0_SLOT_CNTL2_DEFAULT 0x00000000
917#define cfgBIF_CFG_DEV0_EPF0_VF1_0_SLOT_STATUS2_DEFAULT 0x00000000
918#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_CAP_LIST_DEFAULT 0x0000c000
919#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL_DEFAULT 0x00000080
920#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
921#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
922#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_DATA_DEFAULT 0x00000000
923#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MASK_DEFAULT 0x00000000
924#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_DATA_64_DEFAULT 0x00000000
925#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MASK_64_DEFAULT 0x00000000
926#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_PENDING_DEFAULT 0x00000000
927#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_PENDING_64_DEFAULT 0x00000000
928#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSIX_CAP_LIST_DEFAULT 0x00000000
929#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSIX_MSG_CNTL_DEFAULT 0x00000000
930#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSIX_TABLE_DEFAULT 0x00000000
931#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSIX_PBA_DEFAULT 0x00000000
932#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
933#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
934#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
935#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
936#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
937#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
938#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
939#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
940#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
941#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000
942#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
943#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG0_DEFAULT 0x00000000
944#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG1_DEFAULT 0x00000000
945#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG2_DEFAULT 0x00000000
946#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG3_DEFAULT 0x00000000
947#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
948#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
949#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
950#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
951#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
952#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_CAP_DEFAULT 0x00000000
953#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_CNTL_DEFAULT 0x00000000
954#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000
955#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CAP_DEFAULT 0x00000000
956#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CNTL_DEFAULT 0x00000000
957
958
959// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf2_bifcfgdecp
960#define cfgBIF_CFG_DEV0_EPF0_VF2_0_VENDOR_ID_DEFAULT 0x00000000
961#define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_ID_DEFAULT 0x00000000
962#define cfgBIF_CFG_DEV0_EPF0_VF2_0_COMMAND_DEFAULT 0x00000000
963#define cfgBIF_CFG_DEV0_EPF0_VF2_0_STATUS_DEFAULT 0x00000000
964#define cfgBIF_CFG_DEV0_EPF0_VF2_0_REVISION_ID_DEFAULT 0x00000000
965#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PROG_INTERFACE_DEFAULT 0x00000000
966#define cfgBIF_CFG_DEV0_EPF0_VF2_0_SUB_CLASS_DEFAULT 0x00000000
967#define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_CLASS_DEFAULT 0x00000000
968#define cfgBIF_CFG_DEV0_EPF0_VF2_0_CACHE_LINE_DEFAULT 0x00000000
969#define cfgBIF_CFG_DEV0_EPF0_VF2_0_LATENCY_DEFAULT 0x00000000
970#define cfgBIF_CFG_DEV0_EPF0_VF2_0_HEADER_DEFAULT 0x00000000
971#define cfgBIF_CFG_DEV0_EPF0_VF2_0_BIST_DEFAULT 0x00000000
972#define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_1_DEFAULT 0x00000000
973#define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_2_DEFAULT 0x00000000
974#define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_3_DEFAULT 0x00000000
975#define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_4_DEFAULT 0x00000000
976#define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_5_DEFAULT 0x00000000
977#define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_6_DEFAULT 0x00000000
978#define cfgBIF_CFG_DEV0_EPF0_VF2_0_ADAPTER_ID_DEFAULT 0x00000000
979#define cfgBIF_CFG_DEV0_EPF0_VF2_0_ROM_BASE_ADDR_DEFAULT 0x00000000
980#define cfgBIF_CFG_DEV0_EPF0_VF2_0_CAP_PTR_DEFAULT 0x00000000
981#define cfgBIF_CFG_DEV0_EPF0_VF2_0_INTERRUPT_LINE_DEFAULT 0x000000ff
982#define cfgBIF_CFG_DEV0_EPF0_VF2_0_INTERRUPT_PIN_DEFAULT 0x00000000
983#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP_LIST_DEFAULT 0x0000a000
984#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP_DEFAULT 0x00000002
985#define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP_DEFAULT 0x10000000
986#define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL_DEFAULT 0x00002810
987#define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS_DEFAULT 0x00000000
988#define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP_DEFAULT 0x00011c03
989#define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL_DEFAULT 0x00000000
990#define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS_DEFAULT 0x00000001
991#define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2_DEFAULT 0x00000000
992#define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2_DEFAULT 0x00000000
993#define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS2_DEFAULT 0x00000000
994#define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2_DEFAULT 0x0000000e
995#define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2_DEFAULT 0x00000003
996#define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2_DEFAULT 0x00000000
997#define cfgBIF_CFG_DEV0_EPF0_VF2_0_SLOT_CAP2_DEFAULT 0x00000000
998#define cfgBIF_CFG_DEV0_EPF0_VF2_0_SLOT_CNTL2_DEFAULT 0x00000000
999#define cfgBIF_CFG_DEV0_EPF0_VF2_0_SLOT_STATUS2_DEFAULT 0x00000000
1000#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_CAP_LIST_DEFAULT 0x0000c000
1001#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL_DEFAULT 0x00000080
1002#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
1003#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
1004#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_DATA_DEFAULT 0x00000000
1005#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MASK_DEFAULT 0x00000000
1006#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_DATA_64_DEFAULT 0x00000000
1007#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MASK_64_DEFAULT 0x00000000
1008#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_PENDING_DEFAULT 0x00000000
1009#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_PENDING_64_DEFAULT 0x00000000
1010#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSIX_CAP_LIST_DEFAULT 0x00000000
1011#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSIX_MSG_CNTL_DEFAULT 0x00000000
1012#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSIX_TABLE_DEFAULT 0x00000000
1013#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSIX_PBA_DEFAULT 0x00000000
1014#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
1015#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
1016#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
1017#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
1018#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
1019#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
1020#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
1021#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
1022#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
1023#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000
1024#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
1025#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG0_DEFAULT 0x00000000
1026#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG1_DEFAULT 0x00000000
1027#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG2_DEFAULT 0x00000000
1028#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG3_DEFAULT 0x00000000
1029#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
1030#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
1031#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
1032#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
1033#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
1034#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_CAP_DEFAULT 0x00000000
1035#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_CNTL_DEFAULT 0x00000000
1036#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000
1037#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CAP_DEFAULT 0x00000000
1038#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CNTL_DEFAULT 0x00000000
1039
1040
1041// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf3_bifcfgdecp
1042#define cfgBIF_CFG_DEV0_EPF0_VF3_0_VENDOR_ID_DEFAULT 0x00000000
1043#define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_ID_DEFAULT 0x00000000
1044#define cfgBIF_CFG_DEV0_EPF0_VF3_0_COMMAND_DEFAULT 0x00000000
1045#define cfgBIF_CFG_DEV0_EPF0_VF3_0_STATUS_DEFAULT 0x00000000
1046#define cfgBIF_CFG_DEV0_EPF0_VF3_0_REVISION_ID_DEFAULT 0x00000000
1047#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PROG_INTERFACE_DEFAULT 0x00000000
1048#define cfgBIF_CFG_DEV0_EPF0_VF3_0_SUB_CLASS_DEFAULT 0x00000000
1049#define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_CLASS_DEFAULT 0x00000000
1050#define cfgBIF_CFG_DEV0_EPF0_VF3_0_CACHE_LINE_DEFAULT 0x00000000
1051#define cfgBIF_CFG_DEV0_EPF0_VF3_0_LATENCY_DEFAULT 0x00000000
1052#define cfgBIF_CFG_DEV0_EPF0_VF3_0_HEADER_DEFAULT 0x00000000
1053#define cfgBIF_CFG_DEV0_EPF0_VF3_0_BIST_DEFAULT 0x00000000
1054#define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_1_DEFAULT 0x00000000
1055#define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_2_DEFAULT 0x00000000
1056#define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_3_DEFAULT 0x00000000
1057#define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_4_DEFAULT 0x00000000
1058#define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_5_DEFAULT 0x00000000
1059#define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_6_DEFAULT 0x00000000
1060#define cfgBIF_CFG_DEV0_EPF0_VF3_0_ADAPTER_ID_DEFAULT 0x00000000
1061#define cfgBIF_CFG_DEV0_EPF0_VF3_0_ROM_BASE_ADDR_DEFAULT 0x00000000
1062#define cfgBIF_CFG_DEV0_EPF0_VF3_0_CAP_PTR_DEFAULT 0x00000000
1063#define cfgBIF_CFG_DEV0_EPF0_VF3_0_INTERRUPT_LINE_DEFAULT 0x000000ff
1064#define cfgBIF_CFG_DEV0_EPF0_VF3_0_INTERRUPT_PIN_DEFAULT 0x00000000
1065#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP_LIST_DEFAULT 0x0000a000
1066#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP_DEFAULT 0x00000002
1067#define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP_DEFAULT 0x10000000
1068#define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL_DEFAULT 0x00002810
1069#define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS_DEFAULT 0x00000000
1070#define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP_DEFAULT 0x00011c03
1071#define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL_DEFAULT 0x00000000
1072#define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS_DEFAULT 0x00000001
1073#define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2_DEFAULT 0x00000000
1074#define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2_DEFAULT 0x00000000
1075#define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS2_DEFAULT 0x00000000
1076#define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2_DEFAULT 0x0000000e
1077#define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2_DEFAULT 0x00000003
1078#define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2_DEFAULT 0x00000000
1079#define cfgBIF_CFG_DEV0_EPF0_VF3_0_SLOT_CAP2_DEFAULT 0x00000000
1080#define cfgBIF_CFG_DEV0_EPF0_VF3_0_SLOT_CNTL2_DEFAULT 0x00000000
1081#define cfgBIF_CFG_DEV0_EPF0_VF3_0_SLOT_STATUS2_DEFAULT 0x00000000
1082#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_CAP_LIST_DEFAULT 0x0000c000
1083#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL_DEFAULT 0x00000080
1084#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
1085#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
1086#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_DATA_DEFAULT 0x00000000
1087#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MASK_DEFAULT 0x00000000
1088#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_DATA_64_DEFAULT 0x00000000
1089#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MASK_64_DEFAULT 0x00000000
1090#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_PENDING_DEFAULT 0x00000000
1091#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_PENDING_64_DEFAULT 0x00000000
1092#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSIX_CAP_LIST_DEFAULT 0x00000000
1093#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSIX_MSG_CNTL_DEFAULT 0x00000000
1094#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSIX_TABLE_DEFAULT 0x00000000
1095#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSIX_PBA_DEFAULT 0x00000000
1096#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
1097#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
1098#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
1099#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
1100#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
1101#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
1102#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
1103#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
1104#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
1105#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000
1106#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
1107#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG0_DEFAULT 0x00000000
1108#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG1_DEFAULT 0x00000000
1109#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG2_DEFAULT 0x00000000
1110#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG3_DEFAULT 0x00000000
1111#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
1112#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
1113#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
1114#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
1115#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
1116#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_CAP_DEFAULT 0x00000000
1117#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_CNTL_DEFAULT 0x00000000
1118#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000
1119#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CAP_DEFAULT 0x00000000
1120#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CNTL_DEFAULT 0x00000000
1121
1122
1123// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf4_bifcfgdecp
1124#define cfgBIF_CFG_DEV0_EPF0_VF4_0_VENDOR_ID_DEFAULT 0x00000000
1125#define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_ID_DEFAULT 0x00000000
1126#define cfgBIF_CFG_DEV0_EPF0_VF4_0_COMMAND_DEFAULT 0x00000000
1127#define cfgBIF_CFG_DEV0_EPF0_VF4_0_STATUS_DEFAULT 0x00000000
1128#define cfgBIF_CFG_DEV0_EPF0_VF4_0_REVISION_ID_DEFAULT 0x00000000
1129#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PROG_INTERFACE_DEFAULT 0x00000000
1130#define cfgBIF_CFG_DEV0_EPF0_VF4_0_SUB_CLASS_DEFAULT 0x00000000
1131#define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_CLASS_DEFAULT 0x00000000
1132#define cfgBIF_CFG_DEV0_EPF0_VF4_0_CACHE_LINE_DEFAULT 0x00000000
1133#define cfgBIF_CFG_DEV0_EPF0_VF4_0_LATENCY_DEFAULT 0x00000000
1134#define cfgBIF_CFG_DEV0_EPF0_VF4_0_HEADER_DEFAULT 0x00000000
1135#define cfgBIF_CFG_DEV0_EPF0_VF4_0_BIST_DEFAULT 0x00000000
1136#define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_1_DEFAULT 0x00000000
1137#define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_2_DEFAULT 0x00000000
1138#define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_3_DEFAULT 0x00000000
1139#define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_4_DEFAULT 0x00000000
1140#define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_5_DEFAULT 0x00000000
1141#define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_6_DEFAULT 0x00000000
1142#define cfgBIF_CFG_DEV0_EPF0_VF4_0_ADAPTER_ID_DEFAULT 0x00000000
1143#define cfgBIF_CFG_DEV0_EPF0_VF4_0_ROM_BASE_ADDR_DEFAULT 0x00000000
1144#define cfgBIF_CFG_DEV0_EPF0_VF4_0_CAP_PTR_DEFAULT 0x00000000
1145#define cfgBIF_CFG_DEV0_EPF0_VF4_0_INTERRUPT_LINE_DEFAULT 0x000000ff
1146#define cfgBIF_CFG_DEV0_EPF0_VF4_0_INTERRUPT_PIN_DEFAULT 0x00000000
1147#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP_LIST_DEFAULT 0x0000a000
1148#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP_DEFAULT 0x00000002
1149#define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP_DEFAULT 0x10000000
1150#define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL_DEFAULT 0x00002810
1151#define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS_DEFAULT 0x00000000
1152#define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP_DEFAULT 0x00011c03
1153#define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL_DEFAULT 0x00000000
1154#define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS_DEFAULT 0x00000001
1155#define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2_DEFAULT 0x00000000
1156#define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2_DEFAULT 0x00000000
1157#define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS2_DEFAULT 0x00000000
1158#define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2_DEFAULT 0x0000000e
1159#define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2_DEFAULT 0x00000003
1160#define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2_DEFAULT 0x00000000
1161#define cfgBIF_CFG_DEV0_EPF0_VF4_0_SLOT_CAP2_DEFAULT 0x00000000
1162#define cfgBIF_CFG_DEV0_EPF0_VF4_0_SLOT_CNTL2_DEFAULT 0x00000000
1163#define cfgBIF_CFG_DEV0_EPF0_VF4_0_SLOT_STATUS2_DEFAULT 0x00000000
1164#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_CAP_LIST_DEFAULT 0x0000c000
1165#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL_DEFAULT 0x00000080
1166#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
1167#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
1168#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_DATA_DEFAULT 0x00000000
1169#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MASK_DEFAULT 0x00000000
1170#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_DATA_64_DEFAULT 0x00000000
1171#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MASK_64_DEFAULT 0x00000000
1172#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_PENDING_DEFAULT 0x00000000
1173#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_PENDING_64_DEFAULT 0x00000000
1174#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSIX_CAP_LIST_DEFAULT 0x00000000
1175#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSIX_MSG_CNTL_DEFAULT 0x00000000
1176#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSIX_TABLE_DEFAULT 0x00000000
1177#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSIX_PBA_DEFAULT 0x00000000
1178#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
1179#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
1180#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
1181#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
1182#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
1183#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
1184#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
1185#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
1186#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
1187#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000
1188#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
1189#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG0_DEFAULT 0x00000000
1190#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG1_DEFAULT 0x00000000
1191#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG2_DEFAULT 0x00000000
1192#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG3_DEFAULT 0x00000000
1193#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
1194#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
1195#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
1196#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
1197#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
1198#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_CAP_DEFAULT 0x00000000
1199#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_CNTL_DEFAULT 0x00000000
1200#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000
1201#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CAP_DEFAULT 0x00000000
1202#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CNTL_DEFAULT 0x00000000
1203
1204
1205// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf5_bifcfgdecp
1206#define cfgBIF_CFG_DEV0_EPF0_VF5_0_VENDOR_ID_DEFAULT 0x00000000
1207#define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_ID_DEFAULT 0x00000000
1208#define cfgBIF_CFG_DEV0_EPF0_VF5_0_COMMAND_DEFAULT 0x00000000
1209#define cfgBIF_CFG_DEV0_EPF0_VF5_0_STATUS_DEFAULT 0x00000000
1210#define cfgBIF_CFG_DEV0_EPF0_VF5_0_REVISION_ID_DEFAULT 0x00000000
1211#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PROG_INTERFACE_DEFAULT 0x00000000
1212#define cfgBIF_CFG_DEV0_EPF0_VF5_0_SUB_CLASS_DEFAULT 0x00000000
1213#define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_CLASS_DEFAULT 0x00000000
1214#define cfgBIF_CFG_DEV0_EPF0_VF5_0_CACHE_LINE_DEFAULT 0x00000000
1215#define cfgBIF_CFG_DEV0_EPF0_VF5_0_LATENCY_DEFAULT 0x00000000
1216#define cfgBIF_CFG_DEV0_EPF0_VF5_0_HEADER_DEFAULT 0x00000000
1217#define cfgBIF_CFG_DEV0_EPF0_VF5_0_BIST_DEFAULT 0x00000000
1218#define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_1_DEFAULT 0x00000000
1219#define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_2_DEFAULT 0x00000000
1220#define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_3_DEFAULT 0x00000000
1221#define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_4_DEFAULT 0x00000000
1222#define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_5_DEFAULT 0x00000000
1223#define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_6_DEFAULT 0x00000000
1224#define cfgBIF_CFG_DEV0_EPF0_VF5_0_ADAPTER_ID_DEFAULT 0x00000000
1225#define cfgBIF_CFG_DEV0_EPF0_VF5_0_ROM_BASE_ADDR_DEFAULT 0x00000000
1226#define cfgBIF_CFG_DEV0_EPF0_VF5_0_CAP_PTR_DEFAULT 0x00000000
1227#define cfgBIF_CFG_DEV0_EPF0_VF5_0_INTERRUPT_LINE_DEFAULT 0x000000ff
1228#define cfgBIF_CFG_DEV0_EPF0_VF5_0_INTERRUPT_PIN_DEFAULT 0x00000000
1229#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP_LIST_DEFAULT 0x0000a000
1230#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP_DEFAULT 0x00000002
1231#define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP_DEFAULT 0x10000000
1232#define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL_DEFAULT 0x00002810
1233#define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS_DEFAULT 0x00000000
1234#define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP_DEFAULT 0x00011c03
1235#define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL_DEFAULT 0x00000000
1236#define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS_DEFAULT 0x00000001
1237#define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2_DEFAULT 0x00000000
1238#define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2_DEFAULT 0x00000000
1239#define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS2_DEFAULT 0x00000000
1240#define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2_DEFAULT 0x0000000e
1241#define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2_DEFAULT 0x00000003
1242#define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2_DEFAULT 0x00000000
1243#define cfgBIF_CFG_DEV0_EPF0_VF5_0_SLOT_CAP2_DEFAULT 0x00000000
1244#define cfgBIF_CFG_DEV0_EPF0_VF5_0_SLOT_CNTL2_DEFAULT 0x00000000
1245#define cfgBIF_CFG_DEV0_EPF0_VF5_0_SLOT_STATUS2_DEFAULT 0x00000000
1246#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_CAP_LIST_DEFAULT 0x0000c000
1247#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL_DEFAULT 0x00000080
1248#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
1249#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
1250#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_DATA_DEFAULT 0x00000000
1251#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MASK_DEFAULT 0x00000000
1252#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_DATA_64_DEFAULT 0x00000000
1253#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MASK_64_DEFAULT 0x00000000
1254#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_PENDING_DEFAULT 0x00000000
1255#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_PENDING_64_DEFAULT 0x00000000
1256#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSIX_CAP_LIST_DEFAULT 0x00000000
1257#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSIX_MSG_CNTL_DEFAULT 0x00000000
1258#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSIX_TABLE_DEFAULT 0x00000000
1259#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSIX_PBA_DEFAULT 0x00000000
1260#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
1261#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
1262#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
1263#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
1264#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
1265#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
1266#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
1267#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
1268#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
1269#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000
1270#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
1271#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG0_DEFAULT 0x00000000
1272#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG1_DEFAULT 0x00000000
1273#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG2_DEFAULT 0x00000000
1274#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG3_DEFAULT 0x00000000
1275#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
1276#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
1277#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
1278#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
1279#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
1280#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_CAP_DEFAULT 0x00000000
1281#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_CNTL_DEFAULT 0x00000000
1282#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000
1283#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CAP_DEFAULT 0x00000000
1284#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CNTL_DEFAULT 0x00000000
1285
1286
1287// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf6_bifcfgdecp
1288#define cfgBIF_CFG_DEV0_EPF0_VF6_0_VENDOR_ID_DEFAULT 0x00000000
1289#define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_ID_DEFAULT 0x00000000
1290#define cfgBIF_CFG_DEV0_EPF0_VF6_0_COMMAND_DEFAULT 0x00000000
1291#define cfgBIF_CFG_DEV0_EPF0_VF6_0_STATUS_DEFAULT 0x00000000
1292#define cfgBIF_CFG_DEV0_EPF0_VF6_0_REVISION_ID_DEFAULT 0x00000000
1293#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PROG_INTERFACE_DEFAULT 0x00000000
1294#define cfgBIF_CFG_DEV0_EPF0_VF6_0_SUB_CLASS_DEFAULT 0x00000000
1295#define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_CLASS_DEFAULT 0x00000000
1296#define cfgBIF_CFG_DEV0_EPF0_VF6_0_CACHE_LINE_DEFAULT 0x00000000
1297#define cfgBIF_CFG_DEV0_EPF0_VF6_0_LATENCY_DEFAULT 0x00000000
1298#define cfgBIF_CFG_DEV0_EPF0_VF6_0_HEADER_DEFAULT 0x00000000
1299#define cfgBIF_CFG_DEV0_EPF0_VF6_0_BIST_DEFAULT 0x00000000
1300#define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_1_DEFAULT 0x00000000
1301#define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_2_DEFAULT 0x00000000
1302#define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_3_DEFAULT 0x00000000
1303#define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_4_DEFAULT 0x00000000
1304#define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_5_DEFAULT 0x00000000
1305#define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_6_DEFAULT 0x00000000
1306#define cfgBIF_CFG_DEV0_EPF0_VF6_0_ADAPTER_ID_DEFAULT 0x00000000
1307#define cfgBIF_CFG_DEV0_EPF0_VF6_0_ROM_BASE_ADDR_DEFAULT 0x00000000
1308#define cfgBIF_CFG_DEV0_EPF0_VF6_0_CAP_PTR_DEFAULT 0x00000000
1309#define cfgBIF_CFG_DEV0_EPF0_VF6_0_INTERRUPT_LINE_DEFAULT 0x000000ff
1310#define cfgBIF_CFG_DEV0_EPF0_VF6_0_INTERRUPT_PIN_DEFAULT 0x00000000
1311#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP_LIST_DEFAULT 0x0000a000
1312#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP_DEFAULT 0x00000002
1313#define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP_DEFAULT 0x10000000
1314#define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL_DEFAULT 0x00002810
1315#define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS_DEFAULT 0x00000000
1316#define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP_DEFAULT 0x00011c03
1317#define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL_DEFAULT 0x00000000
1318#define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS_DEFAULT 0x00000001
1319#define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2_DEFAULT 0x00000000
1320#define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2_DEFAULT 0x00000000
1321#define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS2_DEFAULT 0x00000000
1322#define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2_DEFAULT 0x0000000e
1323#define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2_DEFAULT 0x00000003
1324#define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2_DEFAULT 0x00000000
1325#define cfgBIF_CFG_DEV0_EPF0_VF6_0_SLOT_CAP2_DEFAULT 0x00000000
1326#define cfgBIF_CFG_DEV0_EPF0_VF6_0_SLOT_CNTL2_DEFAULT 0x00000000
1327#define cfgBIF_CFG_DEV0_EPF0_VF6_0_SLOT_STATUS2_DEFAULT 0x00000000
1328#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_CAP_LIST_DEFAULT 0x0000c000
1329#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL_DEFAULT 0x00000080
1330#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
1331#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
1332#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_DATA_DEFAULT 0x00000000
1333#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MASK_DEFAULT 0x00000000
1334#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_DATA_64_DEFAULT 0x00000000
1335#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MASK_64_DEFAULT 0x00000000
1336#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_PENDING_DEFAULT 0x00000000
1337#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_PENDING_64_DEFAULT 0x00000000
1338#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSIX_CAP_LIST_DEFAULT 0x00000000
1339#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSIX_MSG_CNTL_DEFAULT 0x00000000
1340#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSIX_TABLE_DEFAULT 0x00000000
1341#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSIX_PBA_DEFAULT 0x00000000
1342#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
1343#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
1344#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
1345#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
1346#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
1347#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
1348#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
1349#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
1350#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
1351#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000
1352#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
1353#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG0_DEFAULT 0x00000000
1354#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG1_DEFAULT 0x00000000
1355#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG2_DEFAULT 0x00000000
1356#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG3_DEFAULT 0x00000000
1357#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
1358#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
1359#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
1360#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
1361#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
1362#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_CAP_DEFAULT 0x00000000
1363#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_CNTL_DEFAULT 0x00000000
1364#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000
1365#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CAP_DEFAULT 0x00000000
1366#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CNTL_DEFAULT 0x00000000
1367
1368
1369// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf7_bifcfgdecp
1370#define cfgBIF_CFG_DEV0_EPF0_VF7_0_VENDOR_ID_DEFAULT 0x00000000
1371#define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_ID_DEFAULT 0x00000000
1372#define cfgBIF_CFG_DEV0_EPF0_VF7_0_COMMAND_DEFAULT 0x00000000
1373#define cfgBIF_CFG_DEV0_EPF0_VF7_0_STATUS_DEFAULT 0x00000000
1374#define cfgBIF_CFG_DEV0_EPF0_VF7_0_REVISION_ID_DEFAULT 0x00000000
1375#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PROG_INTERFACE_DEFAULT 0x00000000
1376#define cfgBIF_CFG_DEV0_EPF0_VF7_0_SUB_CLASS_DEFAULT 0x00000000
1377#define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_CLASS_DEFAULT 0x00000000
1378#define cfgBIF_CFG_DEV0_EPF0_VF7_0_CACHE_LINE_DEFAULT 0x00000000
1379#define cfgBIF_CFG_DEV0_EPF0_VF7_0_LATENCY_DEFAULT 0x00000000
1380#define cfgBIF_CFG_DEV0_EPF0_VF7_0_HEADER_DEFAULT 0x00000000
1381#define cfgBIF_CFG_DEV0_EPF0_VF7_0_BIST_DEFAULT 0x00000000
1382#define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_1_DEFAULT 0x00000000
1383#define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_2_DEFAULT 0x00000000
1384#define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_3_DEFAULT 0x00000000
1385#define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_4_DEFAULT 0x00000000
1386#define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_5_DEFAULT 0x00000000
1387#define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_6_DEFAULT 0x00000000
1388#define cfgBIF_CFG_DEV0_EPF0_VF7_0_ADAPTER_ID_DEFAULT 0x00000000
1389#define cfgBIF_CFG_DEV0_EPF0_VF7_0_ROM_BASE_ADDR_DEFAULT 0x00000000
1390#define cfgBIF_CFG_DEV0_EPF0_VF7_0_CAP_PTR_DEFAULT 0x00000000
1391#define cfgBIF_CFG_DEV0_EPF0_VF7_0_INTERRUPT_LINE_DEFAULT 0x000000ff
1392#define cfgBIF_CFG_DEV0_EPF0_VF7_0_INTERRUPT_PIN_DEFAULT 0x00000000
1393#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP_LIST_DEFAULT 0x0000a000
1394#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP_DEFAULT 0x00000002
1395#define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP_DEFAULT 0x10000000
1396#define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL_DEFAULT 0x00002810
1397#define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS_DEFAULT 0x00000000
1398#define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP_DEFAULT 0x00011c03
1399#define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL_DEFAULT 0x00000000
1400#define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS_DEFAULT 0x00000001
1401#define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2_DEFAULT 0x00000000
1402#define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2_DEFAULT 0x00000000
1403#define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS2_DEFAULT 0x00000000
1404#define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2_DEFAULT 0x0000000e
1405#define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2_DEFAULT 0x00000003
1406#define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2_DEFAULT 0x00000000
1407#define cfgBIF_CFG_DEV0_EPF0_VF7_0_SLOT_CAP2_DEFAULT 0x00000000
1408#define cfgBIF_CFG_DEV0_EPF0_VF7_0_SLOT_CNTL2_DEFAULT 0x00000000
1409#define cfgBIF_CFG_DEV0_EPF0_VF7_0_SLOT_STATUS2_DEFAULT 0x00000000
1410#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_CAP_LIST_DEFAULT 0x0000c000
1411#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL_DEFAULT 0x00000080
1412#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
1413#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
1414#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_DATA_DEFAULT 0x00000000
1415#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MASK_DEFAULT 0x00000000
1416#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_DATA_64_DEFAULT 0x00000000
1417#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MASK_64_DEFAULT 0x00000000
1418#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_PENDING_DEFAULT 0x00000000
1419#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_PENDING_64_DEFAULT 0x00000000
1420#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSIX_CAP_LIST_DEFAULT 0x00000000
1421#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSIX_MSG_CNTL_DEFAULT 0x00000000
1422#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSIX_TABLE_DEFAULT 0x00000000
1423#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSIX_PBA_DEFAULT 0x00000000
1424#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
1425#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
1426#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
1427#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
1428#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
1429#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
1430#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
1431#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
1432#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
1433#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000
1434#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
1435#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG0_DEFAULT 0x00000000
1436#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG1_DEFAULT 0x00000000
1437#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG2_DEFAULT 0x00000000
1438#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG3_DEFAULT 0x00000000
1439#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
1440#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
1441#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
1442#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
1443#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
1444#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_CAP_DEFAULT 0x00000000
1445#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_CNTL_DEFAULT 0x00000000
1446#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000
1447#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CAP_DEFAULT 0x00000000
1448#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CNTL_DEFAULT 0x00000000
1449
1450
1451// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf8_bifcfgdecp
1452#define cfgBIF_CFG_DEV0_EPF0_VF8_0_VENDOR_ID_DEFAULT 0x00000000
1453#define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_ID_DEFAULT 0x00000000
1454#define cfgBIF_CFG_DEV0_EPF0_VF8_0_COMMAND_DEFAULT 0x00000000
1455#define cfgBIF_CFG_DEV0_EPF0_VF8_0_STATUS_DEFAULT 0x00000000
1456#define cfgBIF_CFG_DEV0_EPF0_VF8_0_REVISION_ID_DEFAULT 0x00000000
1457#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PROG_INTERFACE_DEFAULT 0x00000000
1458#define cfgBIF_CFG_DEV0_EPF0_VF8_0_SUB_CLASS_DEFAULT 0x00000000
1459#define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_CLASS_DEFAULT 0x00000000
1460#define cfgBIF_CFG_DEV0_EPF0_VF8_0_CACHE_LINE_DEFAULT 0x00000000
1461#define cfgBIF_CFG_DEV0_EPF0_VF8_0_LATENCY_DEFAULT 0x00000000
1462#define cfgBIF_CFG_DEV0_EPF0_VF8_0_HEADER_DEFAULT 0x00000000
1463#define cfgBIF_CFG_DEV0_EPF0_VF8_0_BIST_DEFAULT 0x00000000
1464#define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_1_DEFAULT 0x00000000
1465#define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_2_DEFAULT 0x00000000
1466#define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_3_DEFAULT 0x00000000
1467#define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_4_DEFAULT 0x00000000
1468#define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_5_DEFAULT 0x00000000
1469#define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_6_DEFAULT 0x00000000
1470#define cfgBIF_CFG_DEV0_EPF0_VF8_0_ADAPTER_ID_DEFAULT 0x00000000
1471#define cfgBIF_CFG_DEV0_EPF0_VF8_0_ROM_BASE_ADDR_DEFAULT 0x00000000
1472#define cfgBIF_CFG_DEV0_EPF0_VF8_0_CAP_PTR_DEFAULT 0x00000000
1473#define cfgBIF_CFG_DEV0_EPF0_VF8_0_INTERRUPT_LINE_DEFAULT 0x000000ff
1474#define cfgBIF_CFG_DEV0_EPF0_VF8_0_INTERRUPT_PIN_DEFAULT 0x00000000
1475#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP_LIST_DEFAULT 0x0000a000
1476#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP_DEFAULT 0x00000002
1477#define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP_DEFAULT 0x10000000
1478#define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL_DEFAULT 0x00002810
1479#define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS_DEFAULT 0x00000000
1480#define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP_DEFAULT 0x00011c03
1481#define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL_DEFAULT 0x00000000
1482#define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS_DEFAULT 0x00000001
1483#define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2_DEFAULT 0x00000000
1484#define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2_DEFAULT 0x00000000
1485#define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS2_DEFAULT 0x00000000
1486#define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2_DEFAULT 0x0000000e
1487#define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2_DEFAULT 0x00000003
1488#define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2_DEFAULT 0x00000000
1489#define cfgBIF_CFG_DEV0_EPF0_VF8_0_SLOT_CAP2_DEFAULT 0x00000000
1490#define cfgBIF_CFG_DEV0_EPF0_VF8_0_SLOT_CNTL2_DEFAULT 0x00000000
1491#define cfgBIF_CFG_DEV0_EPF0_VF8_0_SLOT_STATUS2_DEFAULT 0x00000000
1492#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_CAP_LIST_DEFAULT 0x0000c000
1493#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL_DEFAULT 0x00000080
1494#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
1495#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
1496#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_DATA_DEFAULT 0x00000000
1497#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MASK_DEFAULT 0x00000000
1498#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_DATA_64_DEFAULT 0x00000000
1499#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MASK_64_DEFAULT 0x00000000
1500#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_PENDING_DEFAULT 0x00000000
1501#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_PENDING_64_DEFAULT 0x00000000
1502#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSIX_CAP_LIST_DEFAULT 0x00000000
1503#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSIX_MSG_CNTL_DEFAULT 0x00000000
1504#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSIX_TABLE_DEFAULT 0x00000000
1505#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSIX_PBA_DEFAULT 0x00000000
1506#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
1507#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
1508#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
1509#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
1510#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
1511#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
1512#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
1513#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
1514#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
1515#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000
1516#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
1517#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG0_DEFAULT 0x00000000
1518#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG1_DEFAULT 0x00000000
1519#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG2_DEFAULT 0x00000000
1520#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG3_DEFAULT 0x00000000
1521#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
1522#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
1523#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
1524#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
1525#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
1526#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_CAP_DEFAULT 0x00000000
1527#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_CNTL_DEFAULT 0x00000000
1528#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000
1529#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CAP_DEFAULT 0x00000000
1530#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CNTL_DEFAULT 0x00000000
1531
1532
1533// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf9_bifcfgdecp
1534#define cfgBIF_CFG_DEV0_EPF0_VF9_0_VENDOR_ID_DEFAULT 0x00000000
1535#define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_ID_DEFAULT 0x00000000
1536#define cfgBIF_CFG_DEV0_EPF0_VF9_0_COMMAND_DEFAULT 0x00000000
1537#define cfgBIF_CFG_DEV0_EPF0_VF9_0_STATUS_DEFAULT 0x00000000
1538#define cfgBIF_CFG_DEV0_EPF0_VF9_0_REVISION_ID_DEFAULT 0x00000000
1539#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PROG_INTERFACE_DEFAULT 0x00000000
1540#define cfgBIF_CFG_DEV0_EPF0_VF9_0_SUB_CLASS_DEFAULT 0x00000000
1541#define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_CLASS_DEFAULT 0x00000000
1542#define cfgBIF_CFG_DEV0_EPF0_VF9_0_CACHE_LINE_DEFAULT 0x00000000
1543#define cfgBIF_CFG_DEV0_EPF0_VF9_0_LATENCY_DEFAULT 0x00000000
1544#define cfgBIF_CFG_DEV0_EPF0_VF9_0_HEADER_DEFAULT 0x00000000
1545#define cfgBIF_CFG_DEV0_EPF0_VF9_0_BIST_DEFAULT 0x00000000
1546#define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_1_DEFAULT 0x00000000
1547#define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_2_DEFAULT 0x00000000
1548#define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_3_DEFAULT 0x00000000
1549#define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_4_DEFAULT 0x00000000
1550#define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_5_DEFAULT 0x00000000
1551#define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_6_DEFAULT 0x00000000
1552#define cfgBIF_CFG_DEV0_EPF0_VF9_0_ADAPTER_ID_DEFAULT 0x00000000
1553#define cfgBIF_CFG_DEV0_EPF0_VF9_0_ROM_BASE_ADDR_DEFAULT 0x00000000
1554#define cfgBIF_CFG_DEV0_EPF0_VF9_0_CAP_PTR_DEFAULT 0x00000000
1555#define cfgBIF_CFG_DEV0_EPF0_VF9_0_INTERRUPT_LINE_DEFAULT 0x000000ff
1556#define cfgBIF_CFG_DEV0_EPF0_VF9_0_INTERRUPT_PIN_DEFAULT 0x00000000
1557#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP_LIST_DEFAULT 0x0000a000
1558#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP_DEFAULT 0x00000002
1559#define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP_DEFAULT 0x10000000
1560#define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL_DEFAULT 0x00002810
1561#define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS_DEFAULT 0x00000000
1562#define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP_DEFAULT 0x00011c03
1563#define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL_DEFAULT 0x00000000
1564#define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS_DEFAULT 0x00000001
1565#define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2_DEFAULT 0x00000000
1566#define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2_DEFAULT 0x00000000
1567#define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS2_DEFAULT 0x00000000
1568#define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2_DEFAULT 0x0000000e
1569#define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2_DEFAULT 0x00000003
1570#define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2_DEFAULT 0x00000000
1571#define cfgBIF_CFG_DEV0_EPF0_VF9_0_SLOT_CAP2_DEFAULT 0x00000000
1572#define cfgBIF_CFG_DEV0_EPF0_VF9_0_SLOT_CNTL2_DEFAULT 0x00000000
1573#define cfgBIF_CFG_DEV0_EPF0_VF9_0_SLOT_STATUS2_DEFAULT 0x00000000
1574#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_CAP_LIST_DEFAULT 0x0000c000
1575#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL_DEFAULT 0x00000080
1576#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
1577#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
1578#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_DATA_DEFAULT 0x00000000
1579#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MASK_DEFAULT 0x00000000
1580#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_DATA_64_DEFAULT 0x00000000
1581#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MASK_64_DEFAULT 0x00000000
1582#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_PENDING_DEFAULT 0x00000000
1583#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_PENDING_64_DEFAULT 0x00000000
1584#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSIX_CAP_LIST_DEFAULT 0x00000000
1585#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSIX_MSG_CNTL_DEFAULT 0x00000000
1586#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSIX_TABLE_DEFAULT 0x00000000
1587#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSIX_PBA_DEFAULT 0x00000000
1588#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
1589#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
1590#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
1591#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
1592#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
1593#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
1594#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
1595#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
1596#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
1597#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000
1598#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
1599#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG0_DEFAULT 0x00000000
1600#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG1_DEFAULT 0x00000000
1601#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG2_DEFAULT 0x00000000
1602#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG3_DEFAULT 0x00000000
1603#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
1604#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
1605#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
1606#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
1607#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
1608#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_CAP_DEFAULT 0x00000000
1609#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_CNTL_DEFAULT 0x00000000
1610#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000
1611#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CAP_DEFAULT 0x00000000
1612#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CNTL_DEFAULT 0x00000000
1613
1614
1615// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf10_bifcfgdecp
1616#define cfgBIF_CFG_DEV0_EPF0_VF10_0_VENDOR_ID_DEFAULT 0x00000000
1617#define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_ID_DEFAULT 0x00000000
1618#define cfgBIF_CFG_DEV0_EPF0_VF10_0_COMMAND_DEFAULT 0x00000000
1619#define cfgBIF_CFG_DEV0_EPF0_VF10_0_STATUS_DEFAULT 0x00000000
1620#define cfgBIF_CFG_DEV0_EPF0_VF10_0_REVISION_ID_DEFAULT 0x00000000
1621#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PROG_INTERFACE_DEFAULT 0x00000000
1622#define cfgBIF_CFG_DEV0_EPF0_VF10_0_SUB_CLASS_DEFAULT 0x00000000
1623#define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_CLASS_DEFAULT 0x00000000
1624#define cfgBIF_CFG_DEV0_EPF0_VF10_0_CACHE_LINE_DEFAULT 0x00000000
1625#define cfgBIF_CFG_DEV0_EPF0_VF10_0_LATENCY_DEFAULT 0x00000000
1626#define cfgBIF_CFG_DEV0_EPF0_VF10_0_HEADER_DEFAULT 0x00000000
1627#define cfgBIF_CFG_DEV0_EPF0_VF10_0_BIST_DEFAULT 0x00000000
1628#define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_1_DEFAULT 0x00000000
1629#define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_2_DEFAULT 0x00000000
1630#define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_3_DEFAULT 0x00000000
1631#define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_4_DEFAULT 0x00000000
1632#define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_5_DEFAULT 0x00000000
1633#define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_6_DEFAULT 0x00000000
1634#define cfgBIF_CFG_DEV0_EPF0_VF10_0_ADAPTER_ID_DEFAULT 0x00000000
1635#define cfgBIF_CFG_DEV0_EPF0_VF10_0_ROM_BASE_ADDR_DEFAULT 0x00000000
1636#define cfgBIF_CFG_DEV0_EPF0_VF10_0_CAP_PTR_DEFAULT 0x00000000
1637#define cfgBIF_CFG_DEV0_EPF0_VF10_0_INTERRUPT_LINE_DEFAULT 0x000000ff
1638#define cfgBIF_CFG_DEV0_EPF0_VF10_0_INTERRUPT_PIN_DEFAULT 0x00000000
1639#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP_LIST_DEFAULT 0x0000a000
1640#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP_DEFAULT 0x00000002
1641#define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP_DEFAULT 0x10000000
1642#define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL_DEFAULT 0x00002810
1643#define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS_DEFAULT 0x00000000
1644#define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP_DEFAULT 0x00011c03
1645#define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL_DEFAULT 0x00000000
1646#define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS_DEFAULT 0x00000001
1647#define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2_DEFAULT 0x00000000
1648#define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2_DEFAULT 0x00000000
1649#define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS2_DEFAULT 0x00000000
1650#define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2_DEFAULT 0x0000000e
1651#define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2_DEFAULT 0x00000003
1652#define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2_DEFAULT 0x00000000
1653#define cfgBIF_CFG_DEV0_EPF0_VF10_0_SLOT_CAP2_DEFAULT 0x00000000
1654#define cfgBIF_CFG_DEV0_EPF0_VF10_0_SLOT_CNTL2_DEFAULT 0x00000000
1655#define cfgBIF_CFG_DEV0_EPF0_VF10_0_SLOT_STATUS2_DEFAULT 0x00000000
1656#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_CAP_LIST_DEFAULT 0x0000c000
1657#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL_DEFAULT 0x00000080
1658#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
1659#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
1660#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_DATA_DEFAULT 0x00000000
1661#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MASK_DEFAULT 0x00000000
1662#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_DATA_64_DEFAULT 0x00000000
1663#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MASK_64_DEFAULT 0x00000000
1664#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_PENDING_DEFAULT 0x00000000
1665#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_PENDING_64_DEFAULT 0x00000000
1666#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSIX_CAP_LIST_DEFAULT 0x00000000
1667#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSIX_MSG_CNTL_DEFAULT 0x00000000
1668#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSIX_TABLE_DEFAULT 0x00000000
1669#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSIX_PBA_DEFAULT 0x00000000
1670#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
1671#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
1672#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
1673#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
1674#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
1675#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
1676#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
1677#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
1678#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
1679#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000
1680#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
1681#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG0_DEFAULT 0x00000000
1682#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG1_DEFAULT 0x00000000
1683#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG2_DEFAULT 0x00000000
1684#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG3_DEFAULT 0x00000000
1685#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
1686#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
1687#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
1688#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
1689#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
1690#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_CAP_DEFAULT 0x00000000
1691#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_CNTL_DEFAULT 0x00000000
1692#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000
1693#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CAP_DEFAULT 0x00000000
1694#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CNTL_DEFAULT 0x00000000
1695
1696
1697// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf11_bifcfgdecp
1698#define cfgBIF_CFG_DEV0_EPF0_VF11_0_VENDOR_ID_DEFAULT 0x00000000
1699#define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_ID_DEFAULT 0x00000000
1700#define cfgBIF_CFG_DEV0_EPF0_VF11_0_COMMAND_DEFAULT 0x00000000
1701#define cfgBIF_CFG_DEV0_EPF0_VF11_0_STATUS_DEFAULT 0x00000000
1702#define cfgBIF_CFG_DEV0_EPF0_VF11_0_REVISION_ID_DEFAULT 0x00000000
1703#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PROG_INTERFACE_DEFAULT 0x00000000
1704#define cfgBIF_CFG_DEV0_EPF0_VF11_0_SUB_CLASS_DEFAULT 0x00000000
1705#define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_CLASS_DEFAULT 0x00000000
1706#define cfgBIF_CFG_DEV0_EPF0_VF11_0_CACHE_LINE_DEFAULT 0x00000000
1707#define cfgBIF_CFG_DEV0_EPF0_VF11_0_LATENCY_DEFAULT 0x00000000
1708#define cfgBIF_CFG_DEV0_EPF0_VF11_0_HEADER_DEFAULT 0x00000000
1709#define cfgBIF_CFG_DEV0_EPF0_VF11_0_BIST_DEFAULT 0x00000000
1710#define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_1_DEFAULT 0x00000000
1711#define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_2_DEFAULT 0x00000000
1712#define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_3_DEFAULT 0x00000000
1713#define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_4_DEFAULT 0x00000000
1714#define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_5_DEFAULT 0x00000000
1715#define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_6_DEFAULT 0x00000000
1716#define cfgBIF_CFG_DEV0_EPF0_VF11_0_ADAPTER_ID_DEFAULT 0x00000000
1717#define cfgBIF_CFG_DEV0_EPF0_VF11_0_ROM_BASE_ADDR_DEFAULT 0x00000000
1718#define cfgBIF_CFG_DEV0_EPF0_VF11_0_CAP_PTR_DEFAULT 0x00000000
1719#define cfgBIF_CFG_DEV0_EPF0_VF11_0_INTERRUPT_LINE_DEFAULT 0x000000ff
1720#define cfgBIF_CFG_DEV0_EPF0_VF11_0_INTERRUPT_PIN_DEFAULT 0x00000000
1721#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP_LIST_DEFAULT 0x0000a000
1722#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP_DEFAULT 0x00000002
1723#define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP_DEFAULT 0x10000000
1724#define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL_DEFAULT 0x00002810
1725#define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS_DEFAULT 0x00000000
1726#define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP_DEFAULT 0x00011c03
1727#define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL_DEFAULT 0x00000000
1728#define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS_DEFAULT 0x00000001
1729#define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2_DEFAULT 0x00000000
1730#define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2_DEFAULT 0x00000000
1731#define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS2_DEFAULT 0x00000000
1732#define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2_DEFAULT 0x0000000e
1733#define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2_DEFAULT 0x00000003
1734#define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2_DEFAULT 0x00000000
1735#define cfgBIF_CFG_DEV0_EPF0_VF11_0_SLOT_CAP2_DEFAULT 0x00000000
1736#define cfgBIF_CFG_DEV0_EPF0_VF11_0_SLOT_CNTL2_DEFAULT 0x00000000
1737#define cfgBIF_CFG_DEV0_EPF0_VF11_0_SLOT_STATUS2_DEFAULT 0x00000000
1738#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_CAP_LIST_DEFAULT 0x0000c000
1739#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL_DEFAULT 0x00000080
1740#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
1741#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
1742#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_DATA_DEFAULT 0x00000000
1743#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MASK_DEFAULT 0x00000000
1744#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_DATA_64_DEFAULT 0x00000000
1745#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MASK_64_DEFAULT 0x00000000
1746#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_PENDING_DEFAULT 0x00000000
1747#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_PENDING_64_DEFAULT 0x00000000
1748#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSIX_CAP_LIST_DEFAULT 0x00000000
1749#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSIX_MSG_CNTL_DEFAULT 0x00000000
1750#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSIX_TABLE_DEFAULT 0x00000000
1751#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSIX_PBA_DEFAULT 0x00000000
1752#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
1753#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
1754#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
1755#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
1756#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
1757#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
1758#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
1759#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
1760#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
1761#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000
1762#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
1763#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG0_DEFAULT 0x00000000
1764#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG1_DEFAULT 0x00000000
1765#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG2_DEFAULT 0x00000000
1766#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG3_DEFAULT 0x00000000
1767#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
1768#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
1769#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
1770#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
1771#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
1772#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_CAP_DEFAULT 0x00000000
1773#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_CNTL_DEFAULT 0x00000000
1774#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000
1775#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CAP_DEFAULT 0x00000000
1776#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CNTL_DEFAULT 0x00000000
1777
1778
1779// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf12_bifcfgdecp
1780#define cfgBIF_CFG_DEV0_EPF0_VF12_0_VENDOR_ID_DEFAULT 0x00000000
1781#define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_ID_DEFAULT 0x00000000
1782#define cfgBIF_CFG_DEV0_EPF0_VF12_0_COMMAND_DEFAULT 0x00000000
1783#define cfgBIF_CFG_DEV0_EPF0_VF12_0_STATUS_DEFAULT 0x00000000
1784#define cfgBIF_CFG_DEV0_EPF0_VF12_0_REVISION_ID_DEFAULT 0x00000000
1785#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PROG_INTERFACE_DEFAULT 0x00000000
1786#define cfgBIF_CFG_DEV0_EPF0_VF12_0_SUB_CLASS_DEFAULT 0x00000000
1787#define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_CLASS_DEFAULT 0x00000000
1788#define cfgBIF_CFG_DEV0_EPF0_VF12_0_CACHE_LINE_DEFAULT 0x00000000
1789#define cfgBIF_CFG_DEV0_EPF0_VF12_0_LATENCY_DEFAULT 0x00000000
1790#define cfgBIF_CFG_DEV0_EPF0_VF12_0_HEADER_DEFAULT 0x00000000
1791#define cfgBIF_CFG_DEV0_EPF0_VF12_0_BIST_DEFAULT 0x00000000
1792#define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_1_DEFAULT 0x00000000
1793#define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_2_DEFAULT 0x00000000
1794#define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_3_DEFAULT 0x00000000
1795#define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_4_DEFAULT 0x00000000
1796#define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_5_DEFAULT 0x00000000
1797#define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_6_DEFAULT 0x00000000
1798#define cfgBIF_CFG_DEV0_EPF0_VF12_0_ADAPTER_ID_DEFAULT 0x00000000
1799#define cfgBIF_CFG_DEV0_EPF0_VF12_0_ROM_BASE_ADDR_DEFAULT 0x00000000
1800#define cfgBIF_CFG_DEV0_EPF0_VF12_0_CAP_PTR_DEFAULT 0x00000000
1801#define cfgBIF_CFG_DEV0_EPF0_VF12_0_INTERRUPT_LINE_DEFAULT 0x000000ff
1802#define cfgBIF_CFG_DEV0_EPF0_VF12_0_INTERRUPT_PIN_DEFAULT 0x00000000
1803#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP_LIST_DEFAULT 0x0000a000
1804#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP_DEFAULT 0x00000002
1805#define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP_DEFAULT 0x10000000
1806#define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL_DEFAULT 0x00002810
1807#define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS_DEFAULT 0x00000000
1808#define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP_DEFAULT 0x00011c03
1809#define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL_DEFAULT 0x00000000
1810#define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS_DEFAULT 0x00000001
1811#define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2_DEFAULT 0x00000000
1812#define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2_DEFAULT 0x00000000
1813#define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS2_DEFAULT 0x00000000
1814#define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2_DEFAULT 0x0000000e
1815#define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2_DEFAULT 0x00000003
1816#define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2_DEFAULT 0x00000000
1817#define cfgBIF_CFG_DEV0_EPF0_VF12_0_SLOT_CAP2_DEFAULT 0x00000000
1818#define cfgBIF_CFG_DEV0_EPF0_VF12_0_SLOT_CNTL2_DEFAULT 0x00000000
1819#define cfgBIF_CFG_DEV0_EPF0_VF12_0_SLOT_STATUS2_DEFAULT 0x00000000
1820#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_CAP_LIST_DEFAULT 0x0000c000
1821#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL_DEFAULT 0x00000080
1822#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
1823#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
1824#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_DATA_DEFAULT 0x00000000
1825#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MASK_DEFAULT 0x00000000
1826#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_DATA_64_DEFAULT 0x00000000
1827#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MASK_64_DEFAULT 0x00000000
1828#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_PENDING_DEFAULT 0x00000000
1829#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_PENDING_64_DEFAULT 0x00000000
1830#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSIX_CAP_LIST_DEFAULT 0x00000000
1831#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSIX_MSG_CNTL_DEFAULT 0x00000000
1832#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSIX_TABLE_DEFAULT 0x00000000
1833#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSIX_PBA_DEFAULT 0x00000000
1834#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
1835#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
1836#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
1837#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
1838#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
1839#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
1840#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
1841#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
1842#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
1843#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000
1844#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
1845#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG0_DEFAULT 0x00000000
1846#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG1_DEFAULT 0x00000000
1847#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG2_DEFAULT 0x00000000
1848#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG3_DEFAULT 0x00000000
1849#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
1850#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
1851#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
1852#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
1853#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
1854#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_CAP_DEFAULT 0x00000000
1855#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_CNTL_DEFAULT 0x00000000
1856#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000
1857#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CAP_DEFAULT 0x00000000
1858#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CNTL_DEFAULT 0x00000000
1859
1860
1861// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf13_bifcfgdecp
1862#define cfgBIF_CFG_DEV0_EPF0_VF13_0_VENDOR_ID_DEFAULT 0x00000000
1863#define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_ID_DEFAULT 0x00000000
1864#define cfgBIF_CFG_DEV0_EPF0_VF13_0_COMMAND_DEFAULT 0x00000000
1865#define cfgBIF_CFG_DEV0_EPF0_VF13_0_STATUS_DEFAULT 0x00000000
1866#define cfgBIF_CFG_DEV0_EPF0_VF13_0_REVISION_ID_DEFAULT 0x00000000
1867#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PROG_INTERFACE_DEFAULT 0x00000000
1868#define cfgBIF_CFG_DEV0_EPF0_VF13_0_SUB_CLASS_DEFAULT 0x00000000
1869#define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_CLASS_DEFAULT 0x00000000
1870#define cfgBIF_CFG_DEV0_EPF0_VF13_0_CACHE_LINE_DEFAULT 0x00000000
1871#define cfgBIF_CFG_DEV0_EPF0_VF13_0_LATENCY_DEFAULT 0x00000000
1872#define cfgBIF_CFG_DEV0_EPF0_VF13_0_HEADER_DEFAULT 0x00000000
1873#define cfgBIF_CFG_DEV0_EPF0_VF13_0_BIST_DEFAULT 0x00000000
1874#define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_1_DEFAULT 0x00000000
1875#define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_2_DEFAULT 0x00000000
1876#define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_3_DEFAULT 0x00000000
1877#define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_4_DEFAULT 0x00000000
1878#define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_5_DEFAULT 0x00000000
1879#define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_6_DEFAULT 0x00000000
1880#define cfgBIF_CFG_DEV0_EPF0_VF13_0_ADAPTER_ID_DEFAULT 0x00000000
1881#define cfgBIF_CFG_DEV0_EPF0_VF13_0_ROM_BASE_ADDR_DEFAULT 0x00000000
1882#define cfgBIF_CFG_DEV0_EPF0_VF13_0_CAP_PTR_DEFAULT 0x00000000
1883#define cfgBIF_CFG_DEV0_EPF0_VF13_0_INTERRUPT_LINE_DEFAULT 0x000000ff
1884#define cfgBIF_CFG_DEV0_EPF0_VF13_0_INTERRUPT_PIN_DEFAULT 0x00000000
1885#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP_LIST_DEFAULT 0x0000a000
1886#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP_DEFAULT 0x00000002
1887#define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP_DEFAULT 0x10000000
1888#define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL_DEFAULT 0x00002810
1889#define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS_DEFAULT 0x00000000
1890#define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP_DEFAULT 0x00011c03
1891#define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL_DEFAULT 0x00000000
1892#define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS_DEFAULT 0x00000001
1893#define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2_DEFAULT 0x00000000
1894#define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2_DEFAULT 0x00000000
1895#define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS2_DEFAULT 0x00000000
1896#define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2_DEFAULT 0x0000000e
1897#define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2_DEFAULT 0x00000003
1898#define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2_DEFAULT 0x00000000
1899#define cfgBIF_CFG_DEV0_EPF0_VF13_0_SLOT_CAP2_DEFAULT 0x00000000
1900#define cfgBIF_CFG_DEV0_EPF0_VF13_0_SLOT_CNTL2_DEFAULT 0x00000000
1901#define cfgBIF_CFG_DEV0_EPF0_VF13_0_SLOT_STATUS2_DEFAULT 0x00000000
1902#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_CAP_LIST_DEFAULT 0x0000c000
1903#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL_DEFAULT 0x00000080
1904#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
1905#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
1906#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_DATA_DEFAULT 0x00000000
1907#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MASK_DEFAULT 0x00000000
1908#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_DATA_64_DEFAULT 0x00000000
1909#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MASK_64_DEFAULT 0x00000000
1910#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_PENDING_DEFAULT 0x00000000
1911#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_PENDING_64_DEFAULT 0x00000000
1912#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSIX_CAP_LIST_DEFAULT 0x00000000
1913#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSIX_MSG_CNTL_DEFAULT 0x00000000
1914#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSIX_TABLE_DEFAULT 0x00000000
1915#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSIX_PBA_DEFAULT 0x00000000
1916#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
1917#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
1918#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
1919#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
1920#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
1921#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
1922#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
1923#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
1924#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
1925#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000
1926#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
1927#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG0_DEFAULT 0x00000000
1928#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG1_DEFAULT 0x00000000
1929#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG2_DEFAULT 0x00000000
1930#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG3_DEFAULT 0x00000000
1931#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
1932#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
1933#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
1934#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
1935#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
1936#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_CAP_DEFAULT 0x00000000
1937#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_CNTL_DEFAULT 0x00000000
1938#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000
1939#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CAP_DEFAULT 0x00000000
1940#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CNTL_DEFAULT 0x00000000
1941
1942
1943// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf14_bifcfgdecp
1944#define cfgBIF_CFG_DEV0_EPF0_VF14_0_VENDOR_ID_DEFAULT 0x00000000
1945#define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_ID_DEFAULT 0x00000000
1946#define cfgBIF_CFG_DEV0_EPF0_VF14_0_COMMAND_DEFAULT 0x00000000
1947#define cfgBIF_CFG_DEV0_EPF0_VF14_0_STATUS_DEFAULT 0x00000000
1948#define cfgBIF_CFG_DEV0_EPF0_VF14_0_REVISION_ID_DEFAULT 0x00000000
1949#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PROG_INTERFACE_DEFAULT 0x00000000
1950#define cfgBIF_CFG_DEV0_EPF0_VF14_0_SUB_CLASS_DEFAULT 0x00000000
1951#define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_CLASS_DEFAULT 0x00000000
1952#define cfgBIF_CFG_DEV0_EPF0_VF14_0_CACHE_LINE_DEFAULT 0x00000000
1953#define cfgBIF_CFG_DEV0_EPF0_VF14_0_LATENCY_DEFAULT 0x00000000
1954#define cfgBIF_CFG_DEV0_EPF0_VF14_0_HEADER_DEFAULT 0x00000000
1955#define cfgBIF_CFG_DEV0_EPF0_VF14_0_BIST_DEFAULT 0x00000000
1956#define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_1_DEFAULT 0x00000000
1957#define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_2_DEFAULT 0x00000000
1958#define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_3_DEFAULT 0x00000000
1959#define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_4_DEFAULT 0x00000000
1960#define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_5_DEFAULT 0x00000000
1961#define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_6_DEFAULT 0x00000000
1962#define cfgBIF_CFG_DEV0_EPF0_VF14_0_ADAPTER_ID_DEFAULT 0x00000000
1963#define cfgBIF_CFG_DEV0_EPF0_VF14_0_ROM_BASE_ADDR_DEFAULT 0x00000000
1964#define cfgBIF_CFG_DEV0_EPF0_VF14_0_CAP_PTR_DEFAULT 0x00000000
1965#define cfgBIF_CFG_DEV0_EPF0_VF14_0_INTERRUPT_LINE_DEFAULT 0x000000ff
1966#define cfgBIF_CFG_DEV0_EPF0_VF14_0_INTERRUPT_PIN_DEFAULT 0x00000000
1967#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP_LIST_DEFAULT 0x0000a000
1968#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP_DEFAULT 0x00000002
1969#define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP_DEFAULT 0x10000000
1970#define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL_DEFAULT 0x00002810
1971#define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS_DEFAULT 0x00000000
1972#define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP_DEFAULT 0x00011c03
1973#define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL_DEFAULT 0x00000000
1974#define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS_DEFAULT 0x00000001
1975#define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2_DEFAULT 0x00000000
1976#define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2_DEFAULT 0x00000000
1977#define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS2_DEFAULT 0x00000000
1978#define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2_DEFAULT 0x0000000e
1979#define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2_DEFAULT 0x00000003
1980#define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2_DEFAULT 0x00000000
1981#define cfgBIF_CFG_DEV0_EPF0_VF14_0_SLOT_CAP2_DEFAULT 0x00000000
1982#define cfgBIF_CFG_DEV0_EPF0_VF14_0_SLOT_CNTL2_DEFAULT 0x00000000
1983#define cfgBIF_CFG_DEV0_EPF0_VF14_0_SLOT_STATUS2_DEFAULT 0x00000000
1984#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_CAP_LIST_DEFAULT 0x0000c000
1985#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL_DEFAULT 0x00000080
1986#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
1987#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
1988#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_DATA_DEFAULT 0x00000000
1989#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MASK_DEFAULT 0x00000000
1990#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_DATA_64_DEFAULT 0x00000000
1991#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MASK_64_DEFAULT 0x00000000
1992#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_PENDING_DEFAULT 0x00000000
1993#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_PENDING_64_DEFAULT 0x00000000
1994#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSIX_CAP_LIST_DEFAULT 0x00000000
1995#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSIX_MSG_CNTL_DEFAULT 0x00000000
1996#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSIX_TABLE_DEFAULT 0x00000000
1997#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSIX_PBA_DEFAULT 0x00000000
1998#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
1999#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
2000#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
2001#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
2002#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
2003#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
2004#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
2005#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
2006#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
2007#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000
2008#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
2009#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG0_DEFAULT 0x00000000
2010#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG1_DEFAULT 0x00000000
2011#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG2_DEFAULT 0x00000000
2012#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG3_DEFAULT 0x00000000
2013#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
2014#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
2015#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
2016#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
2017#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
2018#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_CAP_DEFAULT 0x00000000
2019#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_CNTL_DEFAULT 0x00000000
2020#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000
2021#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CAP_DEFAULT 0x00000000
2022#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CNTL_DEFAULT 0x00000000
2023
2024
2025// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf15_bifcfgdecp
2026#define cfgBIF_CFG_DEV0_EPF0_VF15_0_VENDOR_ID_DEFAULT 0x00000000
2027#define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_ID_DEFAULT 0x00000000
2028#define cfgBIF_CFG_DEV0_EPF0_VF15_0_COMMAND_DEFAULT 0x00000000
2029#define cfgBIF_CFG_DEV0_EPF0_VF15_0_STATUS_DEFAULT 0x00000000
2030#define cfgBIF_CFG_DEV0_EPF0_VF15_0_REVISION_ID_DEFAULT 0x00000000
2031#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PROG_INTERFACE_DEFAULT 0x00000000
2032#define cfgBIF_CFG_DEV0_EPF0_VF15_0_SUB_CLASS_DEFAULT 0x00000000
2033#define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_CLASS_DEFAULT 0x00000000
2034#define cfgBIF_CFG_DEV0_EPF0_VF15_0_CACHE_LINE_DEFAULT 0x00000000
2035#define cfgBIF_CFG_DEV0_EPF0_VF15_0_LATENCY_DEFAULT 0x00000000
2036#define cfgBIF_CFG_DEV0_EPF0_VF15_0_HEADER_DEFAULT 0x00000000
2037#define cfgBIF_CFG_DEV0_EPF0_VF15_0_BIST_DEFAULT 0x00000000
2038#define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_1_DEFAULT 0x00000000
2039#define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_2_DEFAULT 0x00000000
2040#define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_3_DEFAULT 0x00000000
2041#define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_4_DEFAULT 0x00000000
2042#define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_5_DEFAULT 0x00000000
2043#define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_6_DEFAULT 0x00000000
2044#define cfgBIF_CFG_DEV0_EPF0_VF15_0_ADAPTER_ID_DEFAULT 0x00000000
2045#define cfgBIF_CFG_DEV0_EPF0_VF15_0_ROM_BASE_ADDR_DEFAULT 0x00000000
2046#define cfgBIF_CFG_DEV0_EPF0_VF15_0_CAP_PTR_DEFAULT 0x00000000
2047#define cfgBIF_CFG_DEV0_EPF0_VF15_0_INTERRUPT_LINE_DEFAULT 0x000000ff
2048#define cfgBIF_CFG_DEV0_EPF0_VF15_0_INTERRUPT_PIN_DEFAULT 0x00000000
2049#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP_LIST_DEFAULT 0x0000a000
2050#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP_DEFAULT 0x00000002
2051#define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP_DEFAULT 0x10000000
2052#define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL_DEFAULT 0x00002810
2053#define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS_DEFAULT 0x00000000
2054#define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP_DEFAULT 0x00011c03
2055#define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL_DEFAULT 0x00000000
2056#define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS_DEFAULT 0x00000001
2057#define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2_DEFAULT 0x00000000
2058#define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2_DEFAULT 0x00000000
2059#define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS2_DEFAULT 0x00000000
2060#define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2_DEFAULT 0x0000000e
2061#define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2_DEFAULT 0x00000003
2062#define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2_DEFAULT 0x00000000
2063#define cfgBIF_CFG_DEV0_EPF0_VF15_0_SLOT_CAP2_DEFAULT 0x00000000
2064#define cfgBIF_CFG_DEV0_EPF0_VF15_0_SLOT_CNTL2_DEFAULT 0x00000000
2065#define cfgBIF_CFG_DEV0_EPF0_VF15_0_SLOT_STATUS2_DEFAULT 0x00000000
2066#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_CAP_LIST_DEFAULT 0x0000c000
2067#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL_DEFAULT 0x00000080
2068#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
2069#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
2070#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_DATA_DEFAULT 0x00000000
2071#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MASK_DEFAULT 0x00000000
2072#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_DATA_64_DEFAULT 0x00000000
2073#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MASK_64_DEFAULT 0x00000000
2074#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_PENDING_DEFAULT 0x00000000
2075#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_PENDING_64_DEFAULT 0x00000000
2076#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSIX_CAP_LIST_DEFAULT 0x00000000
2077#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSIX_MSG_CNTL_DEFAULT 0x00000000
2078#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSIX_TABLE_DEFAULT 0x00000000
2079#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSIX_PBA_DEFAULT 0x00000000
2080#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
2081#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
2082#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
2083#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
2084#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
2085#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
2086#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
2087#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
2088#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
2089#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000
2090#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
2091#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG0_DEFAULT 0x00000000
2092#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG1_DEFAULT 0x00000000
2093#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG2_DEFAULT 0x00000000
2094#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG3_DEFAULT 0x00000000
2095#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
2096#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
2097#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
2098#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
2099#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
2100#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_CAP_DEFAULT 0x00000000
2101#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_CNTL_DEFAULT 0x00000000
2102#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000
2103#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CAP_DEFAULT 0x00000000
2104#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CNTL_DEFAULT 0x00000000
2105
2106
2107// addressBlock: nbio_nbif_bif_bx_pf_SYSPFVFDEC[0..767]
2108#define mmMM_INDEX_DEFAULT 0x00000000
2109#define mmMM_DATA_DEFAULT 0x00000000
2110#define mmMM_INDEX_HI_DEFAULT 0x00000000
2111
2112
2113// addressBlock: nbio_nbif_bif_bx_pf_SYSDEC[0..767]
2114#define mmSYSHUB_INDEX_OVLP_DEFAULT 0x00000000
2115#define mmSYSHUB_DATA_OVLP_DEFAULT 0x00000000
2116#define mmPCIE_INDEX_DEFAULT 0x00000000
2117#define mmPCIE_DATA_DEFAULT 0x00000000
2118#define mmPCIE_INDEX2_DEFAULT 0x00000000
2119#define mmPCIE_DATA2_DEFAULT 0x00000000
2120#define mmSBIOS_SCRATCH_0_DEFAULT 0x00000000
2121#define mmSBIOS_SCRATCH_1_DEFAULT 0x00000000
2122#define mmSBIOS_SCRATCH_2_DEFAULT 0x00000000
2123#define mmSBIOS_SCRATCH_3_DEFAULT 0x00000000
2124#define mmBIOS_SCRATCH_0_DEFAULT 0x00000000
2125#define mmBIOS_SCRATCH_1_DEFAULT 0x00000000
2126#define mmBIOS_SCRATCH_2_DEFAULT 0x00000000
2127#define mmBIOS_SCRATCH_3_DEFAULT 0x00000000
2128#define mmBIOS_SCRATCH_4_DEFAULT 0x00000000
2129#define mmBIOS_SCRATCH_5_DEFAULT 0x00000000
2130#define mmBIOS_SCRATCH_6_DEFAULT 0x00000000
2131#define mmBIOS_SCRATCH_7_DEFAULT 0x00000000
2132#define mmBIOS_SCRATCH_8_DEFAULT 0x00000000
2133#define mmBIOS_SCRATCH_9_DEFAULT 0x00000000
2134#define mmBIOS_SCRATCH_10_DEFAULT 0x00000000
2135#define mmBIOS_SCRATCH_11_DEFAULT 0x00000000
2136#define mmBIOS_SCRATCH_12_DEFAULT 0x00000000
2137#define mmBIOS_SCRATCH_13_DEFAULT 0x00000000
2138#define mmBIOS_SCRATCH_14_DEFAULT 0x00000000
2139#define mmBIOS_SCRATCH_15_DEFAULT 0x00000000
2140#define mmBIF_RLC_INTR_CNTL_DEFAULT 0x00000000
2141#define mmBIF_VCE_INTR_CNTL_DEFAULT 0x00000000
2142#define mmBIF_UVD_INTR_CNTL_DEFAULT 0x00000000
2143#define mmGFX_MMIOREG_CAM_ADDR0_DEFAULT 0x00000000
2144#define mmGFX_MMIOREG_CAM_REMAP_ADDR0_DEFAULT 0x00000000
2145#define mmGFX_MMIOREG_CAM_ADDR1_DEFAULT 0x00000000
2146#define mmGFX_MMIOREG_CAM_REMAP_ADDR1_DEFAULT 0x00000000
2147#define mmGFX_MMIOREG_CAM_ADDR2_DEFAULT 0x00000000
2148#define mmGFX_MMIOREG_CAM_REMAP_ADDR2_DEFAULT 0x00000000
2149#define mmGFX_MMIOREG_CAM_ADDR3_DEFAULT 0x00000000
2150#define mmGFX_MMIOREG_CAM_REMAP_ADDR3_DEFAULT 0x00000000
2151#define mmGFX_MMIOREG_CAM_ADDR4_DEFAULT 0x00000000
2152#define mmGFX_MMIOREG_CAM_REMAP_ADDR4_DEFAULT 0x00000000
2153#define mmGFX_MMIOREG_CAM_ADDR5_DEFAULT 0x00000000
2154#define mmGFX_MMIOREG_CAM_REMAP_ADDR5_DEFAULT 0x00000000
2155#define mmGFX_MMIOREG_CAM_ADDR6_DEFAULT 0x00000000
2156#define mmGFX_MMIOREG_CAM_REMAP_ADDR6_DEFAULT 0x00000000
2157#define mmGFX_MMIOREG_CAM_ADDR7_DEFAULT 0x00000000
2158#define mmGFX_MMIOREG_CAM_REMAP_ADDR7_DEFAULT 0x00000000
2159#define mmGFX_MMIOREG_CAM_CNTL_DEFAULT 0x00000000
2160#define mmGFX_MMIOREG_CAM_ZERO_CPL_DEFAULT 0x00000000
2161#define mmGFX_MMIOREG_CAM_ONE_CPL_DEFAULT 0x00000000
2162#define mmGFX_MMIOREG_CAM_PROGRAMMABLE_CPL_DEFAULT 0x00000000
2163
2164
2165// addressBlock: nbio_nbif_syshub_mmreg_ind_syshubdec[32..39]
2166#define mmSYSHUB_INDEX_DEFAULT 0x00000000
2167#define mmSYSHUB_DATA_DEFAULT 0x00000000
2168
2169
2170// addressBlock: nbio_nbif_rcc_strap_BIFDEC1[13440..14975]
2171#define mmRCC_DEV0_EPF0_STRAP0_DEFAULT 0x30000000
2172
2173
2174// addressBlock: nbio_nbif_rcc_ep_dev0_BIFDEC1[13440..14975]
2175#define mmEP_PCIE_SCRATCH_DEFAULT 0x00000000
2176#define mmEP_PCIE_CNTL_DEFAULT 0x00000100
2177#define mmEP_PCIE_INT_CNTL_DEFAULT 0x00000000
2178#define mmEP_PCIE_INT_STATUS_DEFAULT 0x00000000
2179#define mmEP_PCIE_RX_CNTL2_DEFAULT 0x00000000
2180#define mmEP_PCIE_BUS_CNTL_DEFAULT 0x00000080
2181#define mmEP_PCIE_CFG_CNTL_DEFAULT 0x00000000
2182#define mmEP_PCIE_TX_LTR_CNTL_DEFAULT 0x00007468
2183#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x000000fa
2184#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x000000c8
2185#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000096
2186#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000064
2187#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x0000004b
2188#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000032
2189#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000019
2190#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x0000000a
2191#define mmEP_PCIE_F0_DPA_CAP_DEFAULT 0x190a1000
2192#define mmEP_PCIE_F0_DPA_LATENCY_INDICATOR_DEFAULT 0x000000f0
2193#define mmEP_PCIE_F0_DPA_CNTL_DEFAULT 0x00000100
2194#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x000000fa
2195#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x000000c8
2196#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000096
2197#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000064
2198#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x0000004b
2199#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000032
2200#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000019
2201#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x0000000a
2202#define mmEP_PCIE_PME_CONTROL_DEFAULT 0x00000000
2203#define mmEP_PCIEP_RESERVED_DEFAULT 0x00000000
2204#define mmEP_PCIE_TX_CNTL_DEFAULT 0x00000000
2205#define mmEP_PCIE_TX_REQUESTER_ID_DEFAULT 0x00000000
2206#define mmEP_PCIE_ERR_CNTL_DEFAULT 0x00000500
2207#define mmEP_PCIE_RX_CNTL_DEFAULT 0x01000000
2208#define mmEP_PCIE_LC_SPEED_CNTL_DEFAULT 0x00000000
2209
2210
2211// addressBlock: nbio_nbif_rcc_dwn_dev0_BIFDEC1[13440..14975]
2212#define mmDN_PCIE_RESERVED_DEFAULT 0x00000000
2213#define mmDN_PCIE_SCRATCH_DEFAULT 0x00000000
2214#define mmDN_PCIE_CNTL_DEFAULT 0x00000000
2215#define mmDN_PCIE_CONFIG_CNTL_DEFAULT 0x00000000
2216#define mmDN_PCIE_RX_CNTL2_DEFAULT 0x00000000
2217#define mmDN_PCIE_BUS_CNTL_DEFAULT 0x00000080
2218#define mmDN_PCIE_CFG_CNTL_DEFAULT 0x00000000
2219
2220
2221// addressBlock: nbio_nbif_rcc_dwnp_dev0_BIFDEC1[13440..14975]
2222#define mmPCIE_ERR_CNTL_DEFAULT 0x00000500
2223#define mmPCIE_RX_CNTL_DEFAULT 0x00000000
2224#define mmPCIE_LC_SPEED_CNTL_DEFAULT 0x00000000
2225#define mmPCIE_LC_CNTL2_DEFAULT 0x00000000
2226#define mmPCIEP_STRAP_MISC_DEFAULT 0x00000000
2227#define mmLTR_MSG_INFO_FROM_EP_DEFAULT 0x00000000
2228
2229
2230// addressBlock: nbio_nbif_rcc_pf_0_BIFPFVFDEC1[13440..14975]
2231#define mmRCC_PF_0_0_RCC_ERR_LOG_DEFAULT 0x00000000
2232#define mmRCC_PF_0_0_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000
2233#define mmRCC_PF_0_0_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000
2234#define mmRCC_PF_0_0_RCC_CONFIG_RESERVED_DEFAULT 0x00000000
2235#define mmRCC_PF_0_0_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000
2236
2237
2238// addressBlock: nbio_nbif_rcc_pf_0_BIFDEC1[13440..14975]
2239#define mmRCC_ERR_INT_CNTL_DEFAULT 0x00000000
2240#define mmRCC_BACO_CNTL_MISC_DEFAULT 0x00000000
2241#define mmRCC_RESET_EN_DEFAULT 0x00008000
2242#define mmRCC_VDM_SUPPORT_DEFAULT 0x00000000
2243#define mmRCC_PEER_REG_RANGE0_DEFAULT 0xffff0000
2244#define mmRCC_PEER_REG_RANGE1_DEFAULT 0xffff0000
2245#define mmRCC_BUS_CNTL_DEFAULT 0x00000000
2246#define mmRCC_CONFIG_CNTL_DEFAULT 0x00000000
2247#define mmRCC_CONFIG_F0_BASE_DEFAULT 0x00000000
2248#define mmRCC_CONFIG_APER_SIZE_DEFAULT 0x00000000
2249#define mmRCC_CONFIG_REG_APER_SIZE_DEFAULT 0x00000000
2250#define mmRCC_XDMA_LO_DEFAULT 0x00000000
2251#define mmRCC_XDMA_HI_DEFAULT 0x00000000
2252#define mmRCC_FEATURES_CONTROL_MISC_DEFAULT 0x00000000
2253#define mmRCC_BUSNUM_CNTL1_DEFAULT 0x00000000
2254#define mmRCC_BUSNUM_LIST0_DEFAULT 0x00000000
2255#define mmRCC_BUSNUM_LIST1_DEFAULT 0x00000000
2256#define mmRCC_BUSNUM_CNTL2_DEFAULT 0x00000000
2257#define mmRCC_CAPTURE_HOST_BUSNUM_DEFAULT 0x00000000
2258#define mmRCC_HOST_BUSNUM_DEFAULT 0x00000000
2259#define mmRCC_PEER0_FB_OFFSET_HI_DEFAULT 0x00000000
2260#define mmRCC_PEER0_FB_OFFSET_LO_DEFAULT 0x00000000
2261#define mmRCC_PEER1_FB_OFFSET_HI_DEFAULT 0x00000000
2262#define mmRCC_PEER1_FB_OFFSET_LO_DEFAULT 0x00000000
2263#define mmRCC_PEER2_FB_OFFSET_HI_DEFAULT 0x00000000
2264#define mmRCC_PEER2_FB_OFFSET_LO_DEFAULT 0x00000000
2265#define mmRCC_PEER3_FB_OFFSET_HI_DEFAULT 0x00000000
2266#define mmRCC_PEER3_FB_OFFSET_LO_DEFAULT 0x00000000
2267#define mmRCC_CMN_LINK_CNTL_DEFAULT 0x00400000
2268#define mmRCC_EP_REQUESTERID_RESTORE_DEFAULT 0x00000000
2269#define mmRCC_LTR_LSWITCH_CNTL_DEFAULT 0x00000000
2270#define mmRCC_MH_ARB_CNTL_DEFAULT 0x00000000
2271
2272
2273// addressBlock: nbio_nbif_bif_bx_pf_BIFDEC1[13440..14975]
2274#define mmBIF_MM_INDACCESS_CNTL_DEFAULT 0x00000000
2275#define mmBUS_CNTL_DEFAULT 0x00000000
2276#define mmBIF_SCRATCH0_DEFAULT 0x00000000
2277#define mmBIF_SCRATCH1_DEFAULT 0x00000000
2278#define mmBX_RESET_EN_DEFAULT 0x00010003
2279#define mmMM_CFGREGS_CNTL_DEFAULT 0x00000000
2280#define mmBX_RESET_CNTL_DEFAULT 0x00000000
2281#define mmINTERRUPT_CNTL_DEFAULT 0x00000000
2282#define mmINTERRUPT_CNTL2_DEFAULT 0x00000000
2283#define mmCLKREQB_PAD_CNTL_DEFAULT 0x000008e0
2284#define mmBIF_FEATURES_CONTROL_MISC_DEFAULT 0x00000000
2285#define mmBIF_DOORBELL_CNTL_DEFAULT 0x00000000
2286#define mmBIF_DOORBELL_INT_CNTL_DEFAULT 0x00000000
2287#define mmBIF_FB_EN_DEFAULT 0x00000000
2288#define mmBIF_BUSY_DELAY_CNTR_DEFAULT 0x0000003f
2289#define mmBIF_MST_TRANS_PENDING_VF_DEFAULT 0x00000000
2290#define mmBIF_SLV_TRANS_PENDING_VF_DEFAULT 0x00000000
2291#define mmBACO_CNTL_DEFAULT 0x00000000
2292#define mmBIF_BACO_EXIT_TIME0_DEFAULT 0x00000100
2293#define mmBIF_BACO_EXIT_TIMER1_DEFAULT 0x00000200
2294#define mmBIF_BACO_EXIT_TIMER2_DEFAULT 0x00000300
2295#define mmBIF_BACO_EXIT_TIMER3_DEFAULT 0x00000500
2296#define mmBIF_BACO_EXIT_TIMER4_DEFAULT 0x00000400
2297#define mmMEM_TYPE_CNTL_DEFAULT 0x00000000
2298#define mmSMU_BIF_VDDGFX_PWR_STATUS_DEFAULT 0x00000000
2299#define mmBIF_VDDGFX_GFX0_LOWER_DEFAULT 0xc0008000
2300#define mmBIF_VDDGFX_GFX0_UPPER_DEFAULT 0x0000cffc
2301#define mmBIF_VDDGFX_GFX1_LOWER_DEFAULT 0xc0028000
2302#define mmBIF_VDDGFX_GFX1_UPPER_DEFAULT 0x00031ffc
2303#define mmBIF_VDDGFX_GFX2_LOWER_DEFAULT 0xc0034000
2304#define mmBIF_VDDGFX_GFX2_UPPER_DEFAULT 0x00037ffc
2305#define mmBIF_VDDGFX_GFX3_LOWER_DEFAULT 0xc003c000
2306#define mmBIF_VDDGFX_GFX3_UPPER_DEFAULT 0x0003e1fc
2307#define mmBIF_VDDGFX_GFX4_LOWER_DEFAULT 0xc003ec00
2308#define mmBIF_VDDGFX_GFX4_UPPER_DEFAULT 0x0003f1fc
2309#define mmBIF_VDDGFX_GFX5_LOWER_DEFAULT 0xc003fc00
2310#define mmBIF_VDDGFX_GFX5_UPPER_DEFAULT 0x0003fffc
2311#define mmBIF_VDDGFX_RSV1_LOWER_DEFAULT 0x00000000
2312#define mmBIF_VDDGFX_RSV1_UPPER_DEFAULT 0x00000000
2313#define mmBIF_VDDGFX_RSV2_LOWER_DEFAULT 0x00000000
2314#define mmBIF_VDDGFX_RSV2_UPPER_DEFAULT 0x00000000
2315#define mmBIF_VDDGFX_RSV3_LOWER_DEFAULT 0x00000000
2316#define mmBIF_VDDGFX_RSV3_UPPER_DEFAULT 0x00000000
2317#define mmBIF_VDDGFX_RSV4_LOWER_DEFAULT 0x00000000
2318#define mmBIF_VDDGFX_RSV4_UPPER_DEFAULT 0x00000000
2319#define mmBIF_VDDGFX_FB_CMP_DEFAULT 0x00000000
2320#define mmBIF_DOORBELL_GBLAPER1_LOWER_DEFAULT 0x80000780
2321#define mmBIF_DOORBELL_GBLAPER1_UPPER_DEFAULT 0x000007fc
2322#define mmBIF_DOORBELL_GBLAPER2_LOWER_DEFAULT 0x80000800
2323#define mmBIF_DOORBELL_GBLAPER2_UPPER_DEFAULT 0x0000087c
2324#define mmREMAP_HDP_MEM_FLUSH_CNTL_DEFAULT 0x0000385c
2325#define mmREMAP_HDP_REG_FLUSH_CNTL_DEFAULT 0x00003858
2326#define mmBIF_RB_CNTL_DEFAULT 0x00000000
2327#define mmBIF_RB_BASE_DEFAULT 0x00000000
2328#define mmBIF_RB_RPTR_DEFAULT 0x00000000
2329#define mmBIF_RB_WPTR_DEFAULT 0x00000000
2330#define mmBIF_RB_WPTR_ADDR_HI_DEFAULT 0x00000000
2331#define mmBIF_RB_WPTR_ADDR_LO_DEFAULT 0x00000000
2332#define mmMAILBOX_INDEX_DEFAULT 0x00000000
2333#define mmBIF_UVD_GPUIOV_CFG_SIZE_DEFAULT 0x00000008
2334#define mmBIF_VCE_GPUIOV_CFG_SIZE_DEFAULT 0x00000008
2335#define mmBIF_GFX_SDMA_GPUIOV_CFG_SIZE_DEFAULT 0x00000008
2336#define mmBIF_PERSTB_PAD_CNTL_DEFAULT 0x000000c0
2337#define mmBIF_PX_EN_PAD_CNTL_DEFAULT 0x00000031
2338#define mmBIF_REFPADKIN_PAD_CNTL_DEFAULT 0x00000007
2339#define mmBIF_CLKREQB_PAD_CNTL_DEFAULT 0x00600100
2340
2341
2342// addressBlock: nbio_nbif_bif_bx_pf_BIFPFVFDEC1
2343#define mmBIF_BX_PF0_BIF_BME_STATUS_DEFAULT 0x00000000
2344#define mmBIF_BX_PF0_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000
2345#define mmBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000
2346#define mmBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000
2347#define mmBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100
2348#define mmBIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
2349#define mmBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
2350#define mmBIF_BX_PF0_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000
2351#define mmBIF_BX_PF0_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000
2352#define mmBIF_BX_PF0_BIF_TRANS_PENDING_DEFAULT 0x00000000
2353#define mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000
2354#define mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000
2355#define mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000
2356#define mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000
2357#define mmBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000
2358#define mmBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000
2359#define mmBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000
2360#define mmBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000
2361#define mmBIF_BX_PF0_MAILBOX_CONTROL_DEFAULT 0x00000000
2362#define mmBIF_BX_PF0_MAILBOX_INT_CNTL_DEFAULT 0x00000000
2363#define mmBIF_BX_PF0_BIF_VMHV_MAILBOX_DEFAULT 0x00000000
2364
2365
2366// addressBlock: nbio_nbif_gdc_GDCDEC[14976..15487]
2367#define mmNGDC_SDP_PORT_CTRL_DEFAULT 0x0000000f
2368#define mmSHUB_REGS_IF_CTL_DEFAULT 0x00000000
2369#define mmNGDC_RESERVED_0_DEFAULT 0x00000000
2370#define mmNGDC_RESERVED_1_DEFAULT 0x00000000
2371#define mmNGDC_SDP_PORT_CTRL_SOCCLK_DEFAULT 0x0000000f
2372#define mmBIF_SDMA0_DOORBELL_RANGE_DEFAULT 0x00000000
2373#define mmBIF_SDMA1_DOORBELL_RANGE_DEFAULT 0x00000000
2374#define mmBIF_IH_DOORBELL_RANGE_DEFAULT 0x00000000
2375#define mmBIF_MMSCH0_DOORBELL_RANGE_DEFAULT 0x00000000
2376#define mmBIF_DOORBELL_FENCE_CNTL_DEFAULT 0x00000000
2377#define mmS2A_MISC_CNTL_DEFAULT 0x00000000
2378
2379
2380// addressBlock: nbio_nbif_rcc_pf_0_BIFDEC2
2381#define mmRCC_PF_0_GFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000
2382#define mmRCC_PF_0_GFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000
2383#define mmRCC_PF_0_GFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000
2384#define mmRCC_PF_0_GFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001
2385#define mmRCC_PF_0_GFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000
2386#define mmRCC_PF_0_GFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000
2387#define mmRCC_PF_0_GFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000
2388#define mmRCC_PF_0_GFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001
2389#define mmRCC_PF_0_GFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000
2390#define mmRCC_PF_0_GFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000
2391#define mmRCC_PF_0_GFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000
2392#define mmRCC_PF_0_GFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001
2393#define mmRCC_PF_0_GFXMSIX_PBA_DEFAULT 0x00000000
2394
2395
2396// addressBlock: nbio_nbif_gdc_GDCDEC
2397#define smnGDC1_NGDC_SDP_PORT_CTRL_DEFAULT 0x0000000f
2398#define smnGDC1_SHUB_REGS_IF_CTL_DEFAULT 0x00000000
2399#define smnGDC1_NGDC_RESERVED_0_DEFAULT 0x00000000
2400#define smnGDC1_NGDC_RESERVED_1_DEFAULT 0x00000000
2401#define smnGDC1_NGDC_SDP_PORT_CTRL_SOCCLK_DEFAULT 0x0000000f
2402#define smnGDC1_BIF_SDMA0_DOORBELL_RANGE_DEFAULT 0x00000000
2403#define smnGDC1_BIF_SDMA1_DOORBELL_RANGE_DEFAULT 0x00000000
2404#define smnGDC1_BIF_IH_DOORBELL_RANGE_DEFAULT 0x00000000
2405#define smnGDC1_BIF_MMSCH0_DOORBELL_RANGE_DEFAULT 0x00000000
2406#define smnGDC1_BIF_DOORBELL_FENCE_CNTL_DEFAULT 0x00000000
2407#define smnGDC1_S2A_MISC_CNTL_DEFAULT 0x00000000
2408
2409
2410// addressBlock: nbio_nbif_syshub_mmreg_direct_syshubdirect
2411#define smnSYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK_DEFAULT 0x00000000
2412#define smnSYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL2_SOCCLK_DEFAULT 0x00000100
2413#define smnSYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK_DEFAULT 0x00000000
2414#define smnSYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK_DEFAULT 0x00000000
2415#define smnSYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_SYSHUB_QOS_CNTL_DEFAULT 0x0000001e
2416#define smnSYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_SYSHUB_QOS_CNTL_DEFAULT 0x0000001e
2417#define smnSYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL0_CNTL_DEFAULT 0x20200000
2418#define smnSYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL1_CNTL_DEFAULT 0x20200000
2419#define smnSYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL2_CNTL_DEFAULT 0x20200000
2420#define smnSYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL3_CNTL_DEFAULT 0x20200000
2421#define smnSYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL4_CNTL_DEFAULT 0x20200000
2422#define smnSYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL5_CNTL_DEFAULT 0x20200000
2423#define smnSYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_CL0_CNTL_DEFAULT 0x20200000
2424#define smnSYSHUB_MMREG_DIRECT_DMA_CLK0_SW2_CL0_CNTL_DEFAULT 0x20200000
2425#define smnSYSHUB_MMREG_DIRECT_HST_CLK0_SW0_CL0_CNTL_DEFAULT 0x00000000
2426#define smnSYSHUB_MMREG_DIRECT_HST_CLK0_SW0_CL1_CNTL_DEFAULT 0x00000000
2427#define smnSYSHUB_MMREG_DIRECT_HST_CLK0_SW0_CL2_CNTL_DEFAULT 0x00000000
2428#define smnSYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL0_CNTL_DEFAULT 0x00000000
2429#define smnSYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL1_CNTL_DEFAULT 0x00000000
2430#define smnSYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL2_CNTL_DEFAULT 0x00000000
2431#define smnSYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL3_CNTL_DEFAULT 0x00000000
2432#define smnSYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL4_CNTL_DEFAULT 0x00000000
2433#define smnSYSHUB_MMREG_DIRECT_SYSHUB_CG_CNTL_DEFAULT 0x00082000
2434#define smnSYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE_DEFAULT 0x00000000
2435#define smnSYSHUB_MMREG_DIRECT_SYSHUB_HP_TIMER_DEFAULT 0x00000100
2436#define smnSYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK_DEFAULT 0x00000080
2437#define smnSYSHUB_MMREG_DIRECT_SYSHUB_SCRATCH_DEFAULT 0x00000040
2438#define smnSYSHUB_MMREG_DIRECT_SYSHUB_CL_MASK_DEFAULT 0x00000000
2439#define smnSYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK_DEFAULT 0x00000000
2440#define smnSYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL2_SHUBCLK_DEFAULT 0x00000100
2441#define smnSYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK_DEFAULT 0x00000000
2442#define smnSYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK_DEFAULT 0x00000000
2443#define smnSYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_SYSHUB_QOS_CNTL_DEFAULT 0x0000001e
2444#define smnSYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_SYSHUB_QOS_CNTL_DEFAULT 0x0000001e
2445#define smnSYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL0_CNTL_DEFAULT 0x20200000
2446#define smnSYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL1_CNTL_DEFAULT 0x20200000
2447#define smnSYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL2_CNTL_DEFAULT 0x20200000
2448#define smnSYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL3_CNTL_DEFAULT 0x20200000
2449#define smnSYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL4_CNTL_DEFAULT 0x20200000
2450#define smnSYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL0_CNTL_DEFAULT 0x20200000
2451#define smnSYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL1_CNTL_DEFAULT 0x20200000
2452#define smnSYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL2_CNTL_DEFAULT 0x20200000
2453#define smnSYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL3_CNTL_DEFAULT 0x20200000
2454#define smnSYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL4_CNTL_DEFAULT 0x20200000
2455#define smnSYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK_DEFAULT 0x00000080
2456#define smnSYSHUB_MMREG_DIRECT_NIC400_0_ASIB_0_FN_MOD_DEFAULT 0x00000000
2457#define smnSYSHUB_MMREG_DIRECT_NIC400_0_AMIB_0_FN_MOD_BM_ISS_DEFAULT 0x00000000
2458#define smnSYSHUB_MMREG_DIRECT_NIC400_0_AMIB_1_FN_MOD_BM_ISS_DEFAULT 0x00000000
2459#define smnSYSHUB_MMREG_DIRECT_NIC400_0_AMIB_2_FN_MOD_BM_ISS_DEFAULT 0x00000000
2460#define smnSYSHUB_MMREG_DIRECT_NIC400_1_ASIB_0_FN_MOD_DEFAULT 0x00000000
2461#define smnSYSHUB_MMREG_DIRECT_NIC400_1_AMIB_0_FN_MOD_DEFAULT 0x00000000
2462#define smnSYSHUB_MMREG_DIRECT_NIC400_1_AMIB_1_FN_MOD_DEFAULT 0x00000000
2463#define smnSYSHUB_MMREG_DIRECT_NIC400_1_AMIB_2_FN_MOD_DEFAULT 0x00000000
2464#define smnSYSHUB_MMREG_DIRECT_NIC400_1_AMIB_3_FN_MOD_DEFAULT 0x00000000
2465#define smnSYSHUB_MMREG_DIRECT_NIC400_1_AMIB_4_FN_MOD_DEFAULT 0x00000000
2466#define smnSYSHUB_MMREG_DIRECT_NIC400_2_ASIB_0_FN_MOD_DEFAULT 0x00000000
2467#define smnSYSHUB_MMREG_DIRECT_NIC400_2_ASIB_1_FN_MOD_DEFAULT 0x00000000
2468#define smnSYSHUB_MMREG_DIRECT_NIC400_2_ASIB_2_FN_MOD_DEFAULT 0x00000000
2469#define smnSYSHUB_MMREG_DIRECT_NIC400_2_AMIB_0_FN_MOD_BM_ISS_DEFAULT 0x00000000
2470
2471
2472// addressBlock: nbio_nbif_nbif_sion_SIONDEC
2473#define smnSION_CL0_RdRsp_BurstTarget_REG0_DEFAULT 0x00000000
2474#define smnSION_CL0_RdRsp_BurstTarget_REG1_DEFAULT 0x00000000
2475#define smnSION_CL0_RdRsp_TimeSlot_REG0_DEFAULT 0x00000000
2476#define smnSION_CL0_RdRsp_TimeSlot_REG1_DEFAULT 0x00000000
2477#define smnSION_CL0_WrRsp_BurstTarget_REG0_DEFAULT 0x00000000
2478#define smnSION_CL0_WrRsp_BurstTarget_REG1_DEFAULT 0x00000000
2479#define smnSION_CL0_WrRsp_TimeSlot_REG0_DEFAULT 0x00000000
2480#define smnSION_CL0_WrRsp_TimeSlot_REG1_DEFAULT 0x00000000
2481#define smnSION_CL0_Req_BurstTarget_REG0_DEFAULT 0x00000000
2482#define smnSION_CL0_Req_BurstTarget_REG1_DEFAULT 0x00000000
2483#define smnSION_CL0_Req_TimeSlot_REG0_DEFAULT 0x00000000
2484#define smnSION_CL0_Req_TimeSlot_REG1_DEFAULT 0x00000000
2485#define smnSION_CL0_ReqPoolCredit_Alloc_REG0_DEFAULT 0x00000000
2486#define smnSION_CL0_ReqPoolCredit_Alloc_REG1_DEFAULT 0x00000000
2487#define smnSION_CL0_DataPoolCredit_Alloc_REG0_DEFAULT 0x00000000
2488#define smnSION_CL0_DataPoolCredit_Alloc_REG1_DEFAULT 0x00000000
2489#define smnSION_CL0_RdRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000
2490#define smnSION_CL0_RdRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000
2491#define smnSION_CL0_WrRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000
2492#define smnSION_CL0_WrRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000
2493#define smnSION_CL1_RdRsp_BurstTarget_REG0_DEFAULT 0x00000000
2494#define smnSION_CL1_RdRsp_BurstTarget_REG1_DEFAULT 0x00000000
2495#define smnSION_CL1_RdRsp_TimeSlot_REG0_DEFAULT 0x00000000
2496#define smnSION_CL1_RdRsp_TimeSlot_REG1_DEFAULT 0x00000000
2497#define smnSION_CL1_WrRsp_BurstTarget_REG0_DEFAULT 0x00000000
2498#define smnSION_CL1_WrRsp_BurstTarget_REG1_DEFAULT 0x00000000
2499#define smnSION_CL1_WrRsp_TimeSlot_REG0_DEFAULT 0x00000000
2500#define smnSION_CL1_WrRsp_TimeSlot_REG1_DEFAULT 0x00000000
2501#define smnSION_CL1_Req_BurstTarget_REG0_DEFAULT 0x00000000
2502#define smnSION_CL1_Req_BurstTarget_REG1_DEFAULT 0x00000000
2503#define smnSION_CL1_Req_TimeSlot_REG0_DEFAULT 0x00000000
2504#define smnSION_CL1_Req_TimeSlot_REG1_DEFAULT 0x00000000
2505#define smnSION_CL1_ReqPoolCredit_Alloc_REG0_DEFAULT 0x00000000
2506#define smnSION_CL1_ReqPoolCredit_Alloc_REG1_DEFAULT 0x00000000
2507#define smnSION_CL1_DataPoolCredit_Alloc_REG0_DEFAULT 0x00000000
2508#define smnSION_CL1_DataPoolCredit_Alloc_REG1_DEFAULT 0x00000000
2509#define smnSION_CL1_RdRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000
2510#define smnSION_CL1_RdRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000
2511#define smnSION_CL1_WrRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000
2512#define smnSION_CL1_WrRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000
2513#define smnSION_CL2_RdRsp_BurstTarget_REG0_DEFAULT 0x00000000
2514#define smnSION_CL2_RdRsp_BurstTarget_REG1_DEFAULT 0x00000000
2515#define smnSION_CL2_RdRsp_TimeSlot_REG0_DEFAULT 0x00000000
2516#define smnSION_CL2_RdRsp_TimeSlot_REG1_DEFAULT 0x00000000
2517#define smnSION_CL2_WrRsp_BurstTarget_REG0_DEFAULT 0x00000000
2518#define smnSION_CL2_WrRsp_BurstTarget_REG1_DEFAULT 0x00000000
2519#define smnSION_CL2_WrRsp_TimeSlot_REG0_DEFAULT 0x00000000
2520#define smnSION_CL2_WrRsp_TimeSlot_REG1_DEFAULT 0x00000000
2521#define smnSION_CL2_Req_BurstTarget_REG0_DEFAULT 0x00000000
2522#define smnSION_CL2_Req_BurstTarget_REG1_DEFAULT 0x00000000
2523#define smnSION_CL2_Req_TimeSlot_REG0_DEFAULT 0x00000000
2524#define smnSION_CL2_Req_TimeSlot_REG1_DEFAULT 0x00000000
2525#define smnSION_CL2_ReqPoolCredit_Alloc_REG0_DEFAULT 0x00000000
2526#define smnSION_CL2_ReqPoolCredit_Alloc_REG1_DEFAULT 0x00000000
2527#define smnSION_CL2_DataPoolCredit_Alloc_REG0_DEFAULT 0x00000000
2528#define smnSION_CL2_DataPoolCredit_Alloc_REG1_DEFAULT 0x00000000
2529#define smnSION_CL2_RdRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000
2530#define smnSION_CL2_RdRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000
2531#define smnSION_CL2_WrRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000
2532#define smnSION_CL2_WrRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000
2533#define smnSION_CL3_RdRsp_BurstTarget_REG0_DEFAULT 0x00000000
2534#define smnSION_CL3_RdRsp_BurstTarget_REG1_DEFAULT 0x00000000
2535#define smnSION_CL3_RdRsp_TimeSlot_REG0_DEFAULT 0x00000000
2536#define smnSION_CL3_RdRsp_TimeSlot_REG1_DEFAULT 0x00000000
2537#define smnSION_CL3_WrRsp_BurstTarget_REG0_DEFAULT 0x00000000
2538#define smnSION_CL3_WrRsp_BurstTarget_REG1_DEFAULT 0x00000000
2539#define smnSION_CL3_WrRsp_TimeSlot_REG0_DEFAULT 0x00000000
2540#define smnSION_CL3_WrRsp_TimeSlot_REG1_DEFAULT 0x00000000
2541#define smnSION_CL3_Req_BurstTarget_REG0_DEFAULT 0x00000000
2542#define smnSION_CL3_Req_BurstTarget_REG1_DEFAULT 0x00000000
2543#define smnSION_CL3_Req_TimeSlot_REG0_DEFAULT 0x00000000
2544#define smnSION_CL3_Req_TimeSlot_REG1_DEFAULT 0x00000000
2545#define smnSION_CL3_ReqPoolCredit_Alloc_REG0_DEFAULT 0x00000000
2546#define smnSION_CL3_ReqPoolCredit_Alloc_REG1_DEFAULT 0x00000000
2547#define smnSION_CL3_DataPoolCredit_Alloc_REG0_DEFAULT 0x00000000
2548#define smnSION_CL3_DataPoolCredit_Alloc_REG1_DEFAULT 0x00000000
2549#define smnSION_CL3_RdRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000
2550#define smnSION_CL3_RdRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000
2551#define smnSION_CL3_WrRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000
2552#define smnSION_CL3_WrRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000
2553#define smnSION_CL4_RdRsp_BurstTarget_REG0_DEFAULT 0x00000000
2554#define smnSION_CL4_RdRsp_BurstTarget_REG1_DEFAULT 0x00000000
2555#define smnSION_CL4_RdRsp_TimeSlot_REG0_DEFAULT 0x00000000
2556#define smnSION_CL4_RdRsp_TimeSlot_REG1_DEFAULT 0x00000000
2557#define smnSION_CL4_WrRsp_BurstTarget_REG0_DEFAULT 0x00000000
2558#define smnSION_CL4_WrRsp_BurstTarget_REG1_DEFAULT 0x00000000
2559#define smnSION_CL4_WrRsp_TimeSlot_REG0_DEFAULT 0x00000000
2560#define smnSION_CL4_WrRsp_TimeSlot_REG1_DEFAULT 0x00000000
2561#define smnSION_CL4_Req_BurstTarget_REG0_DEFAULT 0x00000000
2562#define smnSION_CL4_Req_BurstTarget_REG1_DEFAULT 0x00000000
2563#define smnSION_CL4_Req_TimeSlot_REG0_DEFAULT 0x00000000
2564#define smnSION_CL4_Req_TimeSlot_REG1_DEFAULT 0x00000000
2565#define smnSION_CL4_ReqPoolCredit_Alloc_REG0_DEFAULT 0x00000000
2566#define smnSION_CL4_ReqPoolCredit_Alloc_REG1_DEFAULT 0x00000000
2567#define smnSION_CL4_DataPoolCredit_Alloc_REG0_DEFAULT 0x00000000
2568#define smnSION_CL4_DataPoolCredit_Alloc_REG1_DEFAULT 0x00000000
2569#define smnSION_CL4_RdRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000
2570#define smnSION_CL4_RdRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000
2571#define smnSION_CL4_WrRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000
2572#define smnSION_CL4_WrRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000
2573#define smnSION_CL5_RdRsp_BurstTarget_REG0_DEFAULT 0x00000000
2574#define smnSION_CL5_RdRsp_BurstTarget_REG1_DEFAULT 0x00000000
2575#define smnSION_CL5_RdRsp_TimeSlot_REG0_DEFAULT 0x00000000
2576#define smnSION_CL5_RdRsp_TimeSlot_REG1_DEFAULT 0x00000000
2577#define smnSION_CL5_WrRsp_BurstTarget_REG0_DEFAULT 0x00000000
2578#define smnSION_CL5_WrRsp_BurstTarget_REG1_DEFAULT 0x00000000
2579#define smnSION_CL5_WrRsp_TimeSlot_REG0_DEFAULT 0x00000000
2580#define smnSION_CL5_WrRsp_TimeSlot_REG1_DEFAULT 0x00000000
2581#define smnSION_CL5_Req_BurstTarget_REG0_DEFAULT 0x00000000
2582#define smnSION_CL5_Req_BurstTarget_REG1_DEFAULT 0x00000000
2583#define smnSION_CL5_Req_TimeSlot_REG0_DEFAULT 0x00000000
2584#define smnSION_CL5_Req_TimeSlot_REG1_DEFAULT 0x00000000
2585#define smnSION_CL5_ReqPoolCredit_Alloc_REG0_DEFAULT 0x00000000
2586#define smnSION_CL5_ReqPoolCredit_Alloc_REG1_DEFAULT 0x00000000
2587#define smnSION_CL5_DataPoolCredit_Alloc_REG0_DEFAULT 0x00000000
2588#define smnSION_CL5_DataPoolCredit_Alloc_REG1_DEFAULT 0x00000000
2589#define smnSION_CL5_RdRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000
2590#define smnSION_CL5_RdRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000
2591#define smnSION_CL5_WrRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000
2592#define smnSION_CL5_WrRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000
2593#define smnSION_CNTL_REG0_DEFAULT 0x00000000
2594#define smnSION_CNTL_REG1_DEFAULT 0x00000000
2595
2596
2597// addressBlock: nbio_nbif_gdc_rst_GDCRST_DEC
2598#define smnSHUB_PF_FLR_RST_DEFAULT 0x00000000
2599#define smnSHUB_GFX_DRV_VPU_RST_DEFAULT 0x00000000
2600#define smnSHUB_LINK_RESET_DEFAULT 0x00000000
2601#define smnSHUB_PF0_VF_FLR_RST_DEFAULT 0x00000000
2602#define smnSHUB_HARD_RST_CTRL_DEFAULT 0x0000001b
2603#define smnSHUB_SOFT_RST_CTRL_DEFAULT 0x00000009
2604#define smnSHUB_SDP_PORT_RST_DEFAULT 0x00000000
2605#define smnSHUB_RST_MISC_TRL_DEFAULT 0x00100001
2606
2607
2608// addressBlock: nbio_nbif_gdc_ras_gdc_ras_regblk
2609#define smnGDC_RAS_LEAF0_CTRL_DEFAULT 0x00000000
2610#define smnGDC_RAS_LEAF1_CTRL_DEFAULT 0x00000000
2611#define smnGDC_RAS_LEAF2_CTRL_DEFAULT 0x00000000
2612#define smnGDC_RAS_LEAF3_CTRL_DEFAULT 0x00000000
2613#define smnGDC_RAS_LEAF4_CTRL_DEFAULT 0x00000000
2614#define smnGDC_RAS_LEAF5_CTRL_DEFAULT 0x00000000
2615
2616
2617// addressBlock: nbio_nbif_bif_cfg_dev0_swds_bifcfgdecp
2618#define smnBIF_CFG_DEV0_SWDS1_VENDOR_ID_DEFAULT 0x00000000
2619#define smnBIF_CFG_DEV0_SWDS1_DEVICE_ID_DEFAULT 0x00000000
2620#define smnBIF_CFG_DEV0_SWDS1_COMMAND_DEFAULT 0x00000000
2621#define smnBIF_CFG_DEV0_SWDS1_STATUS_DEFAULT 0x00000000
2622#define smnBIF_CFG_DEV0_SWDS1_REVISION_ID_DEFAULT 0x00000000
2623#define smnBIF_CFG_DEV0_SWDS1_PROG_INTERFACE_DEFAULT 0x00000000
2624#define smnBIF_CFG_DEV0_SWDS1_SUB_CLASS_DEFAULT 0x00000000
2625#define smnBIF_CFG_DEV0_SWDS1_BASE_CLASS_DEFAULT 0x00000000
2626#define smnBIF_CFG_DEV0_SWDS1_CACHE_LINE_DEFAULT 0x00000000
2627#define smnBIF_CFG_DEV0_SWDS1_LATENCY_DEFAULT 0x00000000
2628#define smnBIF_CFG_DEV0_SWDS1_HEADER_DEFAULT 0x00000000
2629#define smnBIF_CFG_DEV0_SWDS1_BIST_DEFAULT 0x00000000
2630#define smnBIF_CFG_DEV0_SWDS1_BASE_ADDR_1_DEFAULT 0x00000000
2631#define smnBIF_CFG_DEV0_SWDS1_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000
2632#define smnBIF_CFG_DEV0_SWDS1_IO_BASE_LIMIT_DEFAULT 0x00000000
2633#define smnBIF_CFG_DEV0_SWDS1_SECONDARY_STATUS_DEFAULT 0x00000000
2634#define smnBIF_CFG_DEV0_SWDS1_MEM_BASE_LIMIT_DEFAULT 0x00000000
2635#define smnBIF_CFG_DEV0_SWDS1_PREF_BASE_LIMIT_DEFAULT 0x00000000
2636#define smnBIF_CFG_DEV0_SWDS1_PREF_BASE_UPPER_DEFAULT 0x00000000
2637#define smnBIF_CFG_DEV0_SWDS1_PREF_LIMIT_UPPER_DEFAULT 0x00000000
2638#define smnBIF_CFG_DEV0_SWDS1_IO_BASE_LIMIT_HI_DEFAULT 0x00000000
2639#define smnBIF_CFG_DEV0_SWDS1_CAP_PTR_DEFAULT 0x00000000
2640#define smnBIF_CFG_DEV0_SWDS1_INTERRUPT_LINE_DEFAULT 0x000000ff
2641#define smnBIF_CFG_DEV0_SWDS1_INTERRUPT_PIN_DEFAULT 0x00000001
2642#define smnBIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000
2643#define smnBIF_CFG_DEV0_SWDS1_PMI_CAP_LIST_DEFAULT 0x00000000
2644#define smnBIF_CFG_DEV0_SWDS1_PMI_CAP_DEFAULT 0x00000000
2645#define smnBIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL_DEFAULT 0x00000000
2646#define smnBIF_CFG_DEV0_SWDS1_PCIE_CAP_LIST_DEFAULT 0x0000a000
2647#define smnBIF_CFG_DEV0_SWDS1_PCIE_CAP_DEFAULT 0x00000062
2648#define smnBIF_CFG_DEV0_SWDS1_DEVICE_CAP_DEFAULT 0x00000000
2649#define smnBIF_CFG_DEV0_SWDS1_DEVICE_CNTL_DEFAULT 0x00002810
2650#define smnBIF_CFG_DEV0_SWDS1_DEVICE_STATUS_DEFAULT 0x00000000
2651#define smnBIF_CFG_DEV0_SWDS1_LINK_CAP_DEFAULT 0x00011c03
2652#define smnBIF_CFG_DEV0_SWDS1_LINK_CNTL_DEFAULT 0x00000000
2653#define smnBIF_CFG_DEV0_SWDS1_LINK_STATUS_DEFAULT 0x00002001
2654#define smnBIF_CFG_DEV0_SWDS1_SLOT_CAP_DEFAULT 0x00000000
2655#define smnBIF_CFG_DEV0_SWDS1_SLOT_CNTL_DEFAULT 0x00000000
2656#define smnBIF_CFG_DEV0_SWDS1_SLOT_STATUS_DEFAULT 0x00000000
2657#define smnBIF_CFG_DEV0_SWDS1_DEVICE_CAP2_DEFAULT 0x00000000
2658#define smnBIF_CFG_DEV0_SWDS1_DEVICE_CNTL2_DEFAULT 0x00000000
2659#define smnBIF_CFG_DEV0_SWDS1_DEVICE_STATUS2_DEFAULT 0x00000000
2660#define smnBIF_CFG_DEV0_SWDS1_LINK_CAP2_DEFAULT 0x0000000e
2661#define smnBIF_CFG_DEV0_SWDS1_LINK_CNTL2_DEFAULT 0x00000003
2662#define smnBIF_CFG_DEV0_SWDS1_LINK_STATUS2_DEFAULT 0x00000000
2663#define smnBIF_CFG_DEV0_SWDS1_SLOT_CAP2_DEFAULT 0x00000000
2664#define smnBIF_CFG_DEV0_SWDS1_SLOT_CNTL2_DEFAULT 0x00000000
2665#define smnBIF_CFG_DEV0_SWDS1_SLOT_STATUS2_DEFAULT 0x00000000
2666#define smnBIF_CFG_DEV0_SWDS1_MSI_CAP_LIST_DEFAULT 0x0000c000
2667#define smnBIF_CFG_DEV0_SWDS1_MSI_MSG_CNTL_DEFAULT 0x00000080
2668#define smnBIF_CFG_DEV0_SWDS1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
2669#define smnBIF_CFG_DEV0_SWDS1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
2670#define smnBIF_CFG_DEV0_SWDS1_MSI_MSG_DATA_DEFAULT 0x00000000
2671#define smnBIF_CFG_DEV0_SWDS1_MSI_MSG_DATA_64_DEFAULT 0x00000000
2672#define smnBIF_CFG_DEV0_SWDS1_SSID_CAP_LIST_DEFAULT 0x00000000
2673#define smnBIF_CFG_DEV0_SWDS1_SSID_CAP_DEFAULT 0x00000000
2674#define smnBIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
2675#define smnBIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
2676#define smnBIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
2677#define smnBIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
2678#define smnBIF_CFG_DEV0_SWDS1_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000
2679#define smnBIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000
2680#define smnBIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000
2681#define smnBIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000
2682#define smnBIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000
2683#define smnBIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000
2684#define smnBIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe
2685#define smnBIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000000
2686#define smnBIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000
2687#define smnBIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000
2688#define smnBIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000000
2689#define smnBIF_CFG_DEV0_SWDS1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000
2690#define smnBIF_CFG_DEV0_SWDS1_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000
2691#define smnBIF_CFG_DEV0_SWDS1_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000
2692#define smnBIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
2693#define smnBIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
2694#define smnBIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
2695#define smnBIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
2696#define smnBIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
2697#define smnBIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000
2698#define smnBIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
2699#define smnBIF_CFG_DEV0_SWDS1_PCIE_HDR_LOG0_DEFAULT 0x00000000
2700#define smnBIF_CFG_DEV0_SWDS1_PCIE_HDR_LOG1_DEFAULT 0x00000000
2701#define smnBIF_CFG_DEV0_SWDS1_PCIE_HDR_LOG2_DEFAULT 0x00000000
2702#define smnBIF_CFG_DEV0_SWDS1_PCIE_HDR_LOG3_DEFAULT 0x00000000
2703#define smnBIF_CFG_DEV0_SWDS1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
2704#define smnBIF_CFG_DEV0_SWDS1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
2705#define smnBIF_CFG_DEV0_SWDS1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
2706#define smnBIF_CFG_DEV0_SWDS1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
2707#define smnBIF_CFG_DEV0_SWDS1_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a000000
2708#define smnBIF_CFG_DEV0_SWDS1_PCIE_LINK_CNTL3_DEFAULT 0x00000000
2709#define smnBIF_CFG_DEV0_SWDS1_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000
2710#define smnBIF_CFG_DEV0_SWDS1_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f0f
2711#define smnBIF_CFG_DEV0_SWDS1_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f0f
2712#define smnBIF_CFG_DEV0_SWDS1_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f0f
2713#define smnBIF_CFG_DEV0_SWDS1_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f0f
2714#define smnBIF_CFG_DEV0_SWDS1_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f0f
2715#define smnBIF_CFG_DEV0_SWDS1_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f0f
2716#define smnBIF_CFG_DEV0_SWDS1_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f0f
2717#define smnBIF_CFG_DEV0_SWDS1_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f0f
2718#define smnBIF_CFG_DEV0_SWDS1_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f0f
2719#define smnBIF_CFG_DEV0_SWDS1_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f0f
2720#define smnBIF_CFG_DEV0_SWDS1_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f0f
2721#define smnBIF_CFG_DEV0_SWDS1_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f0f
2722#define smnBIF_CFG_DEV0_SWDS1_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f0f
2723#define smnBIF_CFG_DEV0_SWDS1_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f0f
2724#define smnBIF_CFG_DEV0_SWDS1_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f0f
2725#define smnBIF_CFG_DEV0_SWDS1_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f0f
2726#define smnBIF_CFG_DEV0_SWDS1_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2f000000
2727#define smnBIF_CFG_DEV0_SWDS1_PCIE_ACS_CAP_DEFAULT 0x00000000
2728#define smnBIF_CFG_DEV0_SWDS1_PCIE_ACS_CNTL_DEFAULT 0x00000000
2729
2730
2731// addressBlock: nbio_nbif_bif_bx_pf_SYSPFVFDEC
2732#define smnBIF_BX_PF3_MM_INDEX_DEFAULT 0x00000000
2733#define smnBIF_BX_PF3_MM_DATA_DEFAULT 0x00000000
2734#define smnBIF_BX_PF3_MM_INDEX_HI_DEFAULT 0x00000000
2735
2736
2737// addressBlock: nbio_nbif_bif_bx_pf_SYSDEC
2738#define smnBIF_BX_PF1_SYSHUB_INDEX_OVLP_DEFAULT 0x00000000
2739#define smnBIF_BX_PF1_SYSHUB_DATA_OVLP_DEFAULT 0x00000000
2740#define smnBIF_BX_PF1_PCIE_INDEX_DEFAULT 0x00000000
2741#define smnBIF_BX_PF1_PCIE_DATA_DEFAULT 0x00000000
2742#define smnBIF_BX_PF1_PCIE_INDEX2_DEFAULT 0x00000000
2743#define smnBIF_BX_PF1_PCIE_DATA2_DEFAULT 0x00000000
2744#define smnBIF_BX_PF1_SBIOS_SCRATCH_0_DEFAULT 0x00000000
2745#define smnBIF_BX_PF1_SBIOS_SCRATCH_1_DEFAULT 0x00000000
2746#define smnBIF_BX_PF1_SBIOS_SCRATCH_2_DEFAULT 0x00000000
2747#define smnBIF_BX_PF1_SBIOS_SCRATCH_3_DEFAULT 0x00000000
2748#define smnBIF_BX_PF1_BIOS_SCRATCH_0_DEFAULT 0x00000000
2749#define smnBIF_BX_PF1_BIOS_SCRATCH_1_DEFAULT 0x00000000
2750#define smnBIF_BX_PF1_BIOS_SCRATCH_2_DEFAULT 0x00000000
2751#define smnBIF_BX_PF1_BIOS_SCRATCH_3_DEFAULT 0x00000000
2752#define smnBIF_BX_PF1_BIOS_SCRATCH_4_DEFAULT 0x00000000
2753#define smnBIF_BX_PF1_BIOS_SCRATCH_5_DEFAULT 0x00000000
2754#define smnBIF_BX_PF1_BIOS_SCRATCH_6_DEFAULT 0x00000000
2755#define smnBIF_BX_PF1_BIOS_SCRATCH_7_DEFAULT 0x00000000
2756#define smnBIF_BX_PF1_BIOS_SCRATCH_8_DEFAULT 0x00000000
2757#define smnBIF_BX_PF1_BIOS_SCRATCH_9_DEFAULT 0x00000000
2758#define smnBIF_BX_PF1_BIOS_SCRATCH_10_DEFAULT 0x00000000
2759#define smnBIF_BX_PF1_BIOS_SCRATCH_11_DEFAULT 0x00000000
2760#define smnBIF_BX_PF1_BIOS_SCRATCH_12_DEFAULT 0x00000000
2761#define smnBIF_BX_PF1_BIOS_SCRATCH_13_DEFAULT 0x00000000
2762#define smnBIF_BX_PF1_BIOS_SCRATCH_14_DEFAULT 0x00000000
2763#define smnBIF_BX_PF1_BIOS_SCRATCH_15_DEFAULT 0x00000000
2764#define smnBIF_BX_PF1_BIF_RLC_INTR_CNTL_DEFAULT 0x00000000
2765#define smnBIF_BX_PF1_BIF_VCE_INTR_CNTL_DEFAULT 0x00000000
2766#define smnBIF_BX_PF1_BIF_UVD_INTR_CNTL_DEFAULT 0x00000000
2767#define smnBIF_BX_PF1_GFX_MMIOREG_CAM_ADDR0_DEFAULT 0x00000000
2768#define smnBIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR0_DEFAULT 0x00000000
2769#define smnBIF_BX_PF1_GFX_MMIOREG_CAM_ADDR1_DEFAULT 0x00000000
2770#define smnBIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR1_DEFAULT 0x00000000
2771#define smnBIF_BX_PF1_GFX_MMIOREG_CAM_ADDR2_DEFAULT 0x00000000
2772#define smnBIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR2_DEFAULT 0x00000000
2773#define smnBIF_BX_PF1_GFX_MMIOREG_CAM_ADDR3_DEFAULT 0x00000000
2774#define smnBIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR3_DEFAULT 0x00000000
2775#define smnBIF_BX_PF1_GFX_MMIOREG_CAM_ADDR4_DEFAULT 0x00000000
2776#define smnBIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR4_DEFAULT 0x00000000
2777#define smnBIF_BX_PF1_GFX_MMIOREG_CAM_ADDR5_DEFAULT 0x00000000
2778#define smnBIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR5_DEFAULT 0x00000000
2779#define smnBIF_BX_PF1_GFX_MMIOREG_CAM_ADDR6_DEFAULT 0x00000000
2780#define smnBIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR6_DEFAULT 0x00000000
2781#define smnBIF_BX_PF1_GFX_MMIOREG_CAM_ADDR7_DEFAULT 0x00000000
2782#define smnBIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR7_DEFAULT 0x00000000
2783#define smnBIF_BX_PF1_GFX_MMIOREG_CAM_CNTL_DEFAULT 0x00000000
2784#define smnBIF_BX_PF1_GFX_MMIOREG_CAM_ZERO_CPL_DEFAULT 0x00000000
2785#define smnBIF_BX_PF1_GFX_MMIOREG_CAM_ONE_CPL_DEFAULT 0x00000000
2786#define smnBIF_BX_PF1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL_DEFAULT 0x00000000
2787
2788
2789// addressBlock: nbio_nbif_rcc_strap_BIFDEC1
2790#define smnRCC_STRAP1_RCC_DEV0_EPF0_STRAP0_DEFAULT 0x30000000
2791
2792
2793// addressBlock: nbio_nbif_rcc_pf_0_BIFPFVFDEC1
2794#define smnRCC_PF_0_1_RCC_ERR_LOG_DEFAULT 0x00000000
2795#define smnRCC_PF_0_1_RCC_DOORBELL_APER_EN_DEFAULT 0x00000000
2796#define smnRCC_PF_0_1_RCC_CONFIG_MEMSIZE_DEFAULT 0x00000000
2797#define smnRCC_PF_0_1_RCC_CONFIG_RESERVED_DEFAULT 0x00000000
2798#define smnRCC_PF_0_1_RCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000
2799
2800
2801// addressBlock: nbio_nbif_bif_bx_pf_BIFDEC1
2802#define smnBIF_BX_PF1_BIF_MM_INDACCESS_CNTL_DEFAULT 0x00000000
2803#define smnBIF_BX_PF1_BUS_CNTL_DEFAULT 0x00000000
2804#define smnBIF_BX_PF1_BIF_SCRATCH0_DEFAULT 0x00000000
2805#define smnBIF_BX_PF1_BIF_SCRATCH1_DEFAULT 0x00000000
2806#define smnBIF_BX_PF1_BX_RESET_EN_DEFAULT 0x00010003
2807#define smnBIF_BX_PF1_MM_CFGREGS_CNTL_DEFAULT 0x00000000
2808#define smnBIF_BX_PF1_BX_RESET_CNTL_DEFAULT 0x00000000
2809#define smnBIF_BX_PF1_INTERRUPT_CNTL_DEFAULT 0x00000000
2810#define smnBIF_BX_PF1_INTERRUPT_CNTL2_DEFAULT 0x00000000
2811#define smnBIF_BX_PF1_CLKREQB_PAD_CNTL_DEFAULT 0x000008e0
2812#define smnBIF_BX_PF1_BIF_FEATURES_CONTROL_MISC_DEFAULT 0x00000000
2813#define smnBIF_BX_PF1_BIF_DOORBELL_CNTL_DEFAULT 0x00000000
2814#define smnBIF_BX_PF1_BIF_DOORBELL_INT_CNTL_DEFAULT 0x00000000
2815#define smnBIF_BX_PF1_BIF_FB_EN_DEFAULT 0x00000000
2816#define smnBIF_BX_PF1_BIF_BUSY_DELAY_CNTR_DEFAULT 0x0000003f
2817#define smnBIF_BX_PF1_BIF_MST_TRANS_PENDING_VF_DEFAULT 0x00000000
2818#define smnBIF_BX_PF1_BIF_SLV_TRANS_PENDING_VF_DEFAULT 0x00000000
2819#define smnBIF_BX_PF1_BACO_CNTL_DEFAULT 0x00000000
2820#define smnBIF_BX_PF1_BIF_BACO_EXIT_TIME0_DEFAULT 0x00000100
2821#define smnBIF_BX_PF1_BIF_BACO_EXIT_TIMER1_DEFAULT 0x00000200
2822#define smnBIF_BX_PF1_BIF_BACO_EXIT_TIMER2_DEFAULT 0x00000300
2823#define smnBIF_BX_PF1_BIF_BACO_EXIT_TIMER3_DEFAULT 0x00000500
2824#define smnBIF_BX_PF1_BIF_BACO_EXIT_TIMER4_DEFAULT 0x00000400
2825#define smnBIF_BX_PF1_MEM_TYPE_CNTL_DEFAULT 0x00000000
2826#define smnBIF_BX_PF1_SMU_BIF_VDDGFX_PWR_STATUS_DEFAULT 0x00000000
2827#define smnBIF_BX_PF1_BIF_VDDGFX_GFX0_LOWER_DEFAULT 0xc0008000
2828#define smnBIF_BX_PF1_BIF_VDDGFX_GFX0_UPPER_DEFAULT 0x0000cffc
2829#define smnBIF_BX_PF1_BIF_VDDGFX_GFX1_LOWER_DEFAULT 0xc0028000
2830#define smnBIF_BX_PF1_BIF_VDDGFX_GFX1_UPPER_DEFAULT 0x00031ffc
2831#define smnBIF_BX_PF1_BIF_VDDGFX_GFX2_LOWER_DEFAULT 0xc0034000
2832#define smnBIF_BX_PF1_BIF_VDDGFX_GFX2_UPPER_DEFAULT 0x00037ffc
2833#define smnBIF_BX_PF1_BIF_VDDGFX_GFX3_LOWER_DEFAULT 0xc003c000
2834#define smnBIF_BX_PF1_BIF_VDDGFX_GFX3_UPPER_DEFAULT 0x0003e1fc
2835#define smnBIF_BX_PF1_BIF_VDDGFX_GFX4_LOWER_DEFAULT 0xc003ec00
2836#define smnBIF_BX_PF1_BIF_VDDGFX_GFX4_UPPER_DEFAULT 0x0003f1fc
2837#define smnBIF_BX_PF1_BIF_VDDGFX_GFX5_LOWER_DEFAULT 0xc003fc00
2838#define smnBIF_BX_PF1_BIF_VDDGFX_GFX5_UPPER_DEFAULT 0x0003fffc
2839#define smnBIF_BX_PF1_BIF_VDDGFX_RSV1_LOWER_DEFAULT 0x00000000
2840#define smnBIF_BX_PF1_BIF_VDDGFX_RSV1_UPPER_DEFAULT 0x00000000
2841#define smnBIF_BX_PF1_BIF_VDDGFX_RSV2_LOWER_DEFAULT 0x00000000
2842#define smnBIF_BX_PF1_BIF_VDDGFX_RSV2_UPPER_DEFAULT 0x00000000
2843#define smnBIF_BX_PF1_BIF_VDDGFX_RSV3_LOWER_DEFAULT 0x00000000
2844#define smnBIF_BX_PF1_BIF_VDDGFX_RSV3_UPPER_DEFAULT 0x00000000
2845#define smnBIF_BX_PF1_BIF_VDDGFX_RSV4_LOWER_DEFAULT 0x00000000
2846#define smnBIF_BX_PF1_BIF_VDDGFX_RSV4_UPPER_DEFAULT 0x00000000
2847#define smnBIF_BX_PF1_BIF_VDDGFX_FB_CMP_DEFAULT 0x00000000
2848#define smnBIF_BX_PF1_BIF_DOORBELL_GBLAPER1_LOWER_DEFAULT 0x80000780
2849#define smnBIF_BX_PF1_BIF_DOORBELL_GBLAPER1_UPPER_DEFAULT 0x000007fc
2850#define smnBIF_BX_PF1_BIF_DOORBELL_GBLAPER2_LOWER_DEFAULT 0x80000800
2851#define smnBIF_BX_PF1_BIF_DOORBELL_GBLAPER2_UPPER_DEFAULT 0x0000087c
2852#define smnBIF_BX_PF1_REMAP_HDP_MEM_FLUSH_CNTL_DEFAULT 0x0000385c
2853#define smnBIF_BX_PF1_REMAP_HDP_REG_FLUSH_CNTL_DEFAULT 0x00003858
2854#define smnBIF_BX_PF1_BIF_RB_CNTL_DEFAULT 0x00000000
2855#define smnBIF_BX_PF1_BIF_RB_BASE_DEFAULT 0x00000000
2856#define smnBIF_BX_PF1_BIF_RB_RPTR_DEFAULT 0x00000000
2857#define smnBIF_BX_PF1_BIF_RB_WPTR_DEFAULT 0x00000000
2858#define smnBIF_BX_PF1_BIF_RB_WPTR_ADDR_HI_DEFAULT 0x00000000
2859#define smnBIF_BX_PF1_BIF_RB_WPTR_ADDR_LO_DEFAULT 0x00000000
2860#define smnBIF_BX_PF1_MAILBOX_INDEX_DEFAULT 0x00000000
2861#define smnBIF_BX_PF1_BIF_UVD_GPUIOV_CFG_SIZE_DEFAULT 0x00000008
2862#define smnBIF_BX_PF1_BIF_VCE_GPUIOV_CFG_SIZE_DEFAULT 0x00000008
2863#define smnBIF_BX_PF1_BIF_GFX_SDMA_GPUIOV_CFG_SIZE_DEFAULT 0x00000008
2864#define smnBIF_BX_PF1_BIF_PERSTB_PAD_CNTL_DEFAULT 0x000000c0
2865#define smnBIF_BX_PF1_BIF_PX_EN_PAD_CNTL_DEFAULT 0x00000031
2866#define smnBIF_BX_PF1_BIF_REFPADKIN_PAD_CNTL_DEFAULT 0x00000007
2867#define smnBIF_BX_PF1_BIF_CLKREQB_PAD_CNTL_DEFAULT 0x00600100
2868
2869
2870// addressBlock: nbio_nbif_bif_bx_pf_BIFPFVFDEC1
2871#define smnBIF_BX_PF1_BIF_BME_STATUS_DEFAULT 0x00000000
2872#define smnBIF_BX_PF1_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000
2873#define smnBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000
2874#define smnBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000
2875#define smnBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100
2876#define smnBIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
2877#define smnBIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000
2878#define smnBIF_BX_PF1_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000
2879#define smnBIF_BX_PF1_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000
2880#define smnBIF_BX_PF1_BIF_TRANS_PENDING_DEFAULT 0x00000000
2881#define smnBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000
2882#define smnBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000
2883#define smnBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000
2884#define smnBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000
2885#define smnBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000
2886#define smnBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000
2887#define smnBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000
2888#define smnBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000
2889#define smnBIF_BX_PF1_MAILBOX_CONTROL_DEFAULT 0x00000000
2890#define smnBIF_BX_PF1_MAILBOX_INT_CNTL_DEFAULT 0x00000000
2891#define smnBIF_BX_PF1_BIF_VMHV_MAILBOX_DEFAULT 0x00000000
2892
2893
2894// addressBlock: nbio_nbif_rcc_shadow_reg_shadowdec
2895#define smnSHADOW_COMMAND_DEFAULT 0x00000000
2896#define smnSHADOW_BASE_ADDR_1_DEFAULT 0x00000000
2897#define smnSHADOW_BASE_ADDR_2_DEFAULT 0x00000000
2898#define smnSHADOW_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000
2899#define smnSHADOW_IO_BASE_LIMIT_DEFAULT 0x00000000
2900#define smnSHADOW_MEM_BASE_LIMIT_DEFAULT 0x00000000
2901#define smnSHADOW_PREF_BASE_LIMIT_DEFAULT 0x00000000
2902#define smnSHADOW_PREF_BASE_UPPER_DEFAULT 0x00000000
2903#define smnSHADOW_PREF_LIMIT_UPPER_DEFAULT 0x00000000
2904#define smnSHADOW_IO_BASE_LIMIT_HI_DEFAULT 0x00000000
2905#define smnSHADOW_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000
2906#define smnSUC_INDEX_DEFAULT 0x00000000
2907#define smnSUC_DATA_DEFAULT 0x00000000
2908
2909
2910// addressBlock: nbio_nbif_rcc_ep_dev0_RCCPORTDEC
2911#define smnRCC_EP_DEV0_1_EP_PCIE_SCRATCH_DEFAULT 0x00000000
2912#define smnRCC_EP_DEV0_1_EP_PCIE_CNTL_DEFAULT 0x00000100
2913#define smnRCC_EP_DEV0_1_EP_PCIE_INT_CNTL_DEFAULT 0x00000000
2914#define smnRCC_EP_DEV0_1_EP_PCIE_INT_STATUS_DEFAULT 0x00000000
2915#define smnRCC_EP_DEV0_1_EP_PCIE_RX_CNTL2_DEFAULT 0x00000000
2916#define smnRCC_EP_DEV0_1_EP_PCIE_BUS_CNTL_DEFAULT 0x00000080
2917#define smnRCC_EP_DEV0_1_EP_PCIE_CFG_CNTL_DEFAULT 0x00000000
2918#define smnRCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL_DEFAULT 0x00007468
2919#define smnRCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP_DEFAULT 0x190a1000
2920#define smnRCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR_DEFAULT 0x000000f0
2921#define smnRCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL_DEFAULT 0x00000100
2922#define smnRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x000000fa
2923#define smnRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x000000c8
2924#define smnRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000096
2925#define smnRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000064
2926#define smnRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x0000004b
2927#define smnRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000032
2928#define smnRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000019
2929#define smnRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x0000000a
2930#define smnRCC_EP_DEV0_1_EP_PCIE_PME_CONTROL_DEFAULT 0x00000000
2931#define smnRCC_EP_DEV0_1_EP_PCIEP_RESERVED_DEFAULT 0x00000000
2932#define smnRCC_EP_DEV0_1_EP_PCIE_TX_CNTL_DEFAULT 0x00000000
2933#define smnRCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID_DEFAULT 0x00000000
2934#define smnRCC_EP_DEV0_1_EP_PCIE_ERR_CNTL_DEFAULT 0x00000500
2935#define smnRCC_EP_DEV0_1_EP_PCIE_RX_CNTL_DEFAULT 0x01000000
2936#define smnRCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL_DEFAULT 0x00000000
2937
2938
2939// addressBlock: nbio_nbif_rcc_dwn_dev0_RCCPORTDEC
2940#define smnRCC_DWN_DEV0_1_DN_PCIE_RESERVED_DEFAULT 0x00000000
2941#define smnRCC_DWN_DEV0_1_DN_PCIE_SCRATCH_DEFAULT 0x00000000
2942#define smnRCC_DWN_DEV0_1_DN_PCIE_CNTL_DEFAULT 0x00000000
2943#define smnRCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL_DEFAULT 0x00000000
2944#define smnRCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2_DEFAULT 0x00000000
2945#define smnRCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL_DEFAULT 0x00000080
2946#define smnRCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL_DEFAULT 0x00000000
2947
2948
2949// addressBlock: nbio_nbif_rcc_dwnp_dev0_RCCPORTDEC
2950#define smnRCC_DWNP_DEV0_1_PCIE_ERR_CNTL_DEFAULT 0x00000500
2951#define smnRCC_DWNP_DEV0_1_PCIE_RX_CNTL_DEFAULT 0x00000000
2952#define smnRCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL_DEFAULT 0x00000000
2953#define smnRCC_DWNP_DEV0_1_PCIE_LC_CNTL2_DEFAULT 0x00000000
2954#define smnRCC_DWNP_DEV0_1_PCIEP_STRAP_MISC_DEFAULT 0x00000000
2955#define smnRCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP_DEFAULT 0x00000000
2956
2957
2958// addressBlock: nbio_nbif_rcc_strap_rcc_strap_internal
2959#define smnRCC_STRAP2_RCC_DEV0_EPF0_STRAP0_DEFAULT 0x30000000
2960
2961
2962// addressBlock: nbio_nbif_bif_bx_pf_SUMDEC
2963#define smnSUM_INDEX_DEFAULT 0x00000000
2964#define smnSUM_DATA_DEFAULT 0x00000000
2965
2966
2967// addressBlock: nbio_nbif_bif_misc_bif_misc_regblk
2968#define smnMISC_SCRATCH_DEFAULT 0x00000000
2969#define smnINTR_LINE_POLARITY_DEFAULT 0x00000000
2970#define smnINTR_LINE_ENABLE_DEFAULT 0x00000000
2971#define smnOUTSTANDING_VC_ALLOC_DEFAULT 0x6f06c0cf
2972#define smnBIFC_MISC_CTRL0_DEFAULT 0x08000004
2973#define smnBIFC_MISC_CTRL1_DEFAULT 0x10108c04
2974#define smnBIFC_BME_ERR_LOG_DEFAULT 0x00000000
2975#define smnBIFC_RCCBIH_BME_ERR_LOG_DEFAULT 0x00000000
2976#define smnBIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1_DEFAULT 0x00000000
2977#define smnBIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3_DEFAULT 0x00000000
2978#define smnBIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5_DEFAULT 0x00000000
2979#define smnBIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7_DEFAULT 0x00000000
2980#define smnNBIF_VWIRE_CTRL_DEFAULT 0x00000000
2981#define smnNBIF_SMN_VWR_VCHG_DIS_CTRL_DEFAULT 0x00000000
2982#define smnNBIF_SMN_VWR_VCHG_RST_CTRL0_DEFAULT 0x00000000
2983#define smnNBIF_SMN_VWR_VCHG_TRIG_DEFAULT 0x00000000
2984#define smnNBIF_SMN_VWR_WTRIG_CNTL_DEFAULT 0x00000000
2985#define smnNBIF_SMN_VWR_VCHG_DIS_CTRL_1_DEFAULT 0x00000000
2986#define smnNBIF_MGCG_CTRL_LCLK_DEFAULT 0x00000080
2987#define smnNBIF_DS_CTRL_LCLK_DEFAULT 0x01000000
2988#define smnSMN_MST_CNTL0_DEFAULT 0x00000001
2989#define smnSMN_MST_EP_CNTL1_DEFAULT 0x00000000
2990#define smnSMN_MST_EP_CNTL2_DEFAULT 0x00000000
2991#define smnNBIF_SDP_VWR_VCHG_DIS_CTRL_DEFAULT 0x00000000
2992#define smnNBIF_SDP_VWR_VCHG_RST_CTRL0_DEFAULT 0x00000000
2993#define smnNBIF_SDP_VWR_VCHG_RST_CTRL1_DEFAULT 0x00000000
2994#define smnNBIF_SDP_VWR_VCHG_TRIG_DEFAULT 0x00000000
2995#define smnBME_DUMMY_CNTL_0_DEFAULT 0x0000aaaa
2996#define smnBIFC_THT_CNTL_DEFAULT 0x00000222
2997#define smnBIFC_HSTARB_CNTL_DEFAULT 0x00000000
2998#define smnBIFC_GSI_CNTL_DEFAULT 0x000017c0
2999#define smnBIFC_PCIEFUNC_CNTL_DEFAULT 0x00000000
3000#define smnBIFC_SDP_CNTL_0_DEFAULT 0x3f3f3f3f
3001#define smnBIFC_SDP_CNTL_1_DEFAULT 0x00000000
3002#define smnBIFC_PERF_CNTL_0_DEFAULT 0x00000000
3003#define smnBIFC_PERF_CNTL_1_DEFAULT 0x00000000
3004#define smnBIFC_PERF_CNT_MMIO_RD_DEFAULT 0x00000000
3005#define smnBIFC_PERF_CNT_MMIO_WR_DEFAULT 0x00000000
3006#define smnBIFC_PERF_CNT_DMA_RD_DEFAULT 0x00000000
3007#define smnBIFC_PERF_CNT_DMA_WR_DEFAULT 0x00000000
3008#define smnNBIF_REGIF_ERRSET_CTRL_DEFAULT 0x00000000
3009#define smnSMN_MST_EP_CNTL3_DEFAULT 0x00000000
3010#define smnSMN_MST_EP_CNTL4_DEFAULT 0x00000000
3011#define smnSMN_MST_CNTL1_DEFAULT 0x00000000
3012#define smnSMN_MST_EP_CNTL5_DEFAULT 0x00000000
3013#define smnBIF_SELFRING_BUFFER_VID_DEFAULT 0x0000605f
3014#define smnBIF_SELFRING_VECTOR_CNTL_DEFAULT 0x00000000
3015#define smnBIF_GMI_WRR_WEIGHT_DEFAULT 0x00040404
3016
3017
3018// addressBlock: nbio_nbif_rcc_pfc_amdgfx_RCCPFCDEC
3019#define smnRCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL_DEFAULT 0x00000000
3020#define smnRCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE_DEFAULT 0x00000000
3021#define smnRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0_DEFAULT 0x00000000
3022#define smnRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_1_DEFAULT 0x00000000
3023#define smnRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_2_DEFAULT 0x00000000
3024#define smnRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_3_DEFAULT 0x00000000
3025#define smnRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_4_DEFAULT 0x00000000
3026#define smnRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_5_DEFAULT 0x00000000
3027#define smnRCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL_DEFAULT 0x00000000
3028
3029
3030// addressBlock: nbio_nbif_rcc_pfc_amdgfxaz_RCCPFCDEC
3031#define smnRCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL_DEFAULT 0x00000000
3032#define smnRCC_PFC_AMDGFXAZ_RCC_PFC_PME_RESTORE_DEFAULT 0x00000000
3033#define smnRCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0_DEFAULT 0x00000000
3034#define smnRCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_1_DEFAULT 0x00000000
3035#define smnRCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_2_DEFAULT 0x00000000
3036#define smnRCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_3_DEFAULT 0x00000000
3037#define smnRCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_4_DEFAULT 0x00000000
3038#define smnRCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_5_DEFAULT 0x00000000
3039#define smnRCC_PFC_AMDGFXAZ_RCC_PFC_AUXPWR_CNTL_DEFAULT 0x00000000
3040
3041
3042// addressBlock: nbio_nbif_bif_rst_bif_rst_regblk
3043#define smnHARD_RST_CTRL_DEFAULT 0xb0000055
3044#define smnRSMU_SOFT_RST_CTRL_DEFAULT 0x90000000
3045#define smnSELF_SOFT_RST_DEFAULT 0x00000000
3046#define smnBIF_GFX_DRV_VPU_RST_DEFAULT 0x00000000
3047#define smnBIF_RST_MISC_CTRL_DEFAULT 0x000e0648
3048#define smnBIF_RST_MISC_CTRL2_DEFAULT 0x00000000
3049#define smnBIF_RST_MISC_CTRL3_DEFAULT 0x00104900
3050#define smnBIF_RST_GFXVF_FLR_IDLE_DEFAULT 0x00000000
3051#define smnDEV0_PF0_FLR_RST_CTRL_DEFAULT 0x8206a0a9
3052#define smnDEV0_PF1_FLR_RST_CTRL_DEFAULT 0x02060009
3053#define smnDEV0_PF2_FLR_RST_CTRL_DEFAULT 0x02060009
3054#define smnDEV0_PF3_FLR_RST_CTRL_DEFAULT 0x02060009
3055#define smnDEV0_PF4_FLR_RST_CTRL_DEFAULT 0x02060009
3056#define smnDEV0_PF5_FLR_RST_CTRL_DEFAULT 0x02060009
3057#define smnDEV0_PF6_FLR_RST_CTRL_DEFAULT 0x02060009
3058#define smnDEV0_PF7_FLR_RST_CTRL_DEFAULT 0x02060009
3059#define smnBIF_INST_RESET_INTR_STS_DEFAULT 0x00000000
3060#define smnBIF_PF_FLR_INTR_STS_DEFAULT 0x00000000
3061#define smnBIF_D3HOTD0_INTR_STS_DEFAULT 0x00000000
3062#define smnBIF_POWER_INTR_STS_DEFAULT 0x00000000
3063#define smnBIF_PF_DSTATE_INTR_STS_DEFAULT 0x00000000
3064#define smnBIF_PF0_VF_FLR_INTR_STS_DEFAULT 0x00000000
3065#define smnBIF_INST_RESET_INTR_MASK_DEFAULT 0x00000000
3066#define smnBIF_PF_FLR_INTR_MASK_DEFAULT 0x00000000
3067#define smnBIF_D3HOTD0_INTR_MASK_DEFAULT 0x000000ff
3068#define smnBIF_POWER_INTR_MASK_DEFAULT 0x00000000
3069#define smnBIF_PF_DSTATE_INTR_MASK_DEFAULT 0x00000000
3070#define smnBIF_PF0_VF_FLR_INTR_MASK_DEFAULT 0x00000000
3071#define smnBIF_PF_FLR_RST_DEFAULT 0x00000000
3072#define smnBIF_PF0_VF_FLR_RST_DEFAULT 0x00000000
3073#define smnBIF_DEV0_PF0_DSTATE_VALUE_DEFAULT 0x00000000
3074#define smnBIF_DEV0_PF1_DSTATE_VALUE_DEFAULT 0x00000000
3075#define smnBIF_DEV0_PF2_DSTATE_VALUE_DEFAULT 0x00000000
3076#define smnBIF_DEV0_PF3_DSTATE_VALUE_DEFAULT 0x00000000
3077#define smnBIF_DEV0_PF4_DSTATE_VALUE_DEFAULT 0x00000000
3078#define smnBIF_DEV0_PF5_DSTATE_VALUE_DEFAULT 0x00000000
3079#define smnBIF_DEV0_PF6_DSTATE_VALUE_DEFAULT 0x00000000
3080#define smnBIF_DEV0_PF7_DSTATE_VALUE_DEFAULT 0x00000000
3081#define smnDEV0_PF0_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b
3082#define smnDEV0_PF1_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b
3083#define smnDEV0_PF2_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b
3084#define smnDEV0_PF3_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b
3085#define smnDEV0_PF4_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b
3086#define smnDEV0_PF5_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b
3087#define smnDEV0_PF6_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b
3088#define smnDEV0_PF7_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b
3089#define smnBIF_PORT0_DSTATE_VALUE_DEFAULT 0x00000000
3090
3091
3092// addressBlock: nbio_nbif_bif_ras_bif_ras_regblk
3093#define smnBIF_RAS_LEAF0_CTRL_DEFAULT 0x00000000
3094#define smnBIF_RAS_LEAF1_CTRL_DEFAULT 0x00000000
3095#define smnBIF_RAS_LEAF2_CTRL_DEFAULT 0x00000000
3096#define smnBIF_RAS_MISC_CTRL_DEFAULT 0x00000000
3097#define smnBIF_IOHUB_RAS_IH_CNTL_DEFAULT 0x00000000
3098#define smnBIF_RAS_VWR_FROM_IOHUB_DEFAULT 0x00000000
3099
3100
3101// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_bifcfgdecp
3102#define smnBIF_CFG_DEV0_EPF0_1_VENDOR_ID_DEFAULT 0x00000000
3103#define smnBIF_CFG_DEV0_EPF0_1_DEVICE_ID_DEFAULT 0x00000000
3104#define smnBIF_CFG_DEV0_EPF0_1_COMMAND_DEFAULT 0x00000000
3105#define smnBIF_CFG_DEV0_EPF0_1_STATUS_DEFAULT 0x00000000
3106#define smnBIF_CFG_DEV0_EPF0_1_REVISION_ID_DEFAULT 0x00000000
3107#define smnBIF_CFG_DEV0_EPF0_1_PROG_INTERFACE_DEFAULT 0x00000000
3108#define smnBIF_CFG_DEV0_EPF0_1_SUB_CLASS_DEFAULT 0x00000000
3109#define smnBIF_CFG_DEV0_EPF0_1_BASE_CLASS_DEFAULT 0x00000000
3110#define smnBIF_CFG_DEV0_EPF0_1_CACHE_LINE_DEFAULT 0x00000000
3111#define smnBIF_CFG_DEV0_EPF0_1_LATENCY_DEFAULT 0x00000000
3112#define smnBIF_CFG_DEV0_EPF0_1_HEADER_DEFAULT 0x00000000
3113#define smnBIF_CFG_DEV0_EPF0_1_BIST_DEFAULT 0x00000000
3114#define smnBIF_CFG_DEV0_EPF0_1_BASE_ADDR_1_DEFAULT 0x00000000
3115#define smnBIF_CFG_DEV0_EPF0_1_BASE_ADDR_2_DEFAULT 0x00000000
3116#define smnBIF_CFG_DEV0_EPF0_1_BASE_ADDR_3_DEFAULT 0x00000000
3117#define smnBIF_CFG_DEV0_EPF0_1_BASE_ADDR_4_DEFAULT 0x00000000
3118#define smnBIF_CFG_DEV0_EPF0_1_BASE_ADDR_5_DEFAULT 0x00000000
3119#define smnBIF_CFG_DEV0_EPF0_1_BASE_ADDR_6_DEFAULT 0x00000000
3120#define smnBIF_CFG_DEV0_EPF0_1_ADAPTER_ID_DEFAULT 0x00000000
3121#define smnBIF_CFG_DEV0_EPF0_1_ROM_BASE_ADDR_DEFAULT 0x00000000
3122#define smnBIF_CFG_DEV0_EPF0_1_CAP_PTR_DEFAULT 0x00000000
3123#define smnBIF_CFG_DEV0_EPF0_1_INTERRUPT_LINE_DEFAULT 0x000000ff
3124#define smnBIF_CFG_DEV0_EPF0_1_INTERRUPT_PIN_DEFAULT 0x00000000
3125#define smnBIF_CFG_DEV0_EPF0_1_MIN_GRANT_DEFAULT 0x00000000
3126#define smnBIF_CFG_DEV0_EPF0_1_MAX_LATENCY_DEFAULT 0x00000000
3127#define smnBIF_CFG_DEV0_EPF0_1_VENDOR_CAP_LIST_DEFAULT 0x00000000
3128#define smnBIF_CFG_DEV0_EPF0_1_ADAPTER_ID_W_DEFAULT 0x00000000
3129#define smnBIF_CFG_DEV0_EPF0_1_PMI_CAP_LIST_DEFAULT 0x00000000
3130#define smnBIF_CFG_DEV0_EPF0_1_PMI_CAP_DEFAULT 0x00000000
3131#define smnBIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL_DEFAULT 0x00000000
3132#define smnBIF_CFG_DEV0_EPF0_1_PCIE_CAP_LIST_DEFAULT 0x0000a000
3133#define smnBIF_CFG_DEV0_EPF0_1_PCIE_CAP_DEFAULT 0x00000002
3134#define smnBIF_CFG_DEV0_EPF0_1_DEVICE_CAP_DEFAULT 0x10000000
3135#define smnBIF_CFG_DEV0_EPF0_1_DEVICE_CNTL_DEFAULT 0x00002810
3136#define smnBIF_CFG_DEV0_EPF0_1_DEVICE_STATUS_DEFAULT 0x00000000
3137#define smnBIF_CFG_DEV0_EPF0_1_LINK_CAP_DEFAULT 0x00011c03
3138#define smnBIF_CFG_DEV0_EPF0_1_LINK_CNTL_DEFAULT 0x00000000
3139#define smnBIF_CFG_DEV0_EPF0_1_LINK_STATUS_DEFAULT 0x00000001
3140#define smnBIF_CFG_DEV0_EPF0_1_DEVICE_CAP2_DEFAULT 0x00000000
3141#define smnBIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2_DEFAULT 0x00000000
3142#define smnBIF_CFG_DEV0_EPF0_1_DEVICE_STATUS2_DEFAULT 0x00000000
3143#define smnBIF_CFG_DEV0_EPF0_1_LINK_CAP2_DEFAULT 0x0000000e
3144#define smnBIF_CFG_DEV0_EPF0_1_LINK_CNTL2_DEFAULT 0x00000003
3145#define smnBIF_CFG_DEV0_EPF0_1_LINK_STATUS2_DEFAULT 0x00000000
3146#define smnBIF_CFG_DEV0_EPF0_1_SLOT_CAP2_DEFAULT 0x00000000
3147#define smnBIF_CFG_DEV0_EPF0_1_SLOT_CNTL2_DEFAULT 0x00000000
3148#define smnBIF_CFG_DEV0_EPF0_1_SLOT_STATUS2_DEFAULT 0x00000000
3149#define smnBIF_CFG_DEV0_EPF0_1_MSI_CAP_LIST_DEFAULT 0x0000c000
3150#define smnBIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL_DEFAULT 0x00000080
3151#define smnBIF_CFG_DEV0_EPF0_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
3152#define smnBIF_CFG_DEV0_EPF0_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
3153#define smnBIF_CFG_DEV0_EPF0_1_MSI_MSG_DATA_DEFAULT 0x00000000
3154#define smnBIF_CFG_DEV0_EPF0_1_MSI_MASK_DEFAULT 0x00000000
3155#define smnBIF_CFG_DEV0_EPF0_1_MSI_MSG_DATA_64_DEFAULT 0x00000000
3156#define smnBIF_CFG_DEV0_EPF0_1_MSI_MASK_64_DEFAULT 0x00000000
3157#define smnBIF_CFG_DEV0_EPF0_1_MSI_PENDING_DEFAULT 0x00000000
3158#define smnBIF_CFG_DEV0_EPF0_1_MSI_PENDING_64_DEFAULT 0x00000000
3159#define smnBIF_CFG_DEV0_EPF0_1_MSIX_CAP_LIST_DEFAULT 0x00000000
3160#define smnBIF_CFG_DEV0_EPF0_1_MSIX_MSG_CNTL_DEFAULT 0x00000000
3161#define smnBIF_CFG_DEV0_EPF0_1_MSIX_TABLE_DEFAULT 0x00000000
3162#define smnBIF_CFG_DEV0_EPF0_1_MSIX_PBA_DEFAULT 0x00000000
3163#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
3164#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
3165#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
3166#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
3167#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000
3168#define smnBIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000
3169#define smnBIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000
3170#define smnBIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000
3171#define smnBIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000
3172#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000
3173#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe
3174#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000000
3175#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000
3176#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000
3177#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000000
3178#define smnBIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000
3179#define smnBIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000
3180#define smnBIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000
3181#define smnBIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
3182#define smnBIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
3183#define smnBIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
3184#define smnBIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
3185#define smnBIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
3186#define smnBIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000
3187#define smnBIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
3188#define smnBIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG0_DEFAULT 0x00000000
3189#define smnBIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG1_DEFAULT 0x00000000
3190#define smnBIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG2_DEFAULT 0x00000000
3191#define smnBIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG3_DEFAULT 0x00000000
3192#define smnBIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
3193#define smnBIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
3194#define smnBIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
3195#define smnBIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
3196#define smnBIF_CFG_DEV0_EPF0_1_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000
3197#define smnBIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CAP_DEFAULT 0x00000000
3198#define smnBIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL_DEFAULT 0x00000020
3199#define smnBIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CAP_DEFAULT 0x00000000
3200#define smnBIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL_DEFAULT 0x00000000
3201#define smnBIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CAP_DEFAULT 0x00000000
3202#define smnBIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL_DEFAULT 0x00000000
3203#define smnBIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CAP_DEFAULT 0x00000000
3204#define smnBIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL_DEFAULT 0x00000000
3205#define smnBIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CAP_DEFAULT 0x00000000
3206#define smnBIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL_DEFAULT 0x00000000
3207#define smnBIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CAP_DEFAULT 0x00000000
3208#define smnBIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL_DEFAULT 0x00000000
3209#define smnBIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000
3210#define smnBIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000
3211#define smnBIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000
3212#define smnBIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000
3213#define smnBIF_CFG_DEV0_EPF0_1_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000
3214#define smnBIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP_DEFAULT 0x00000000
3215#define smnBIF_CFG_DEV0_EPF0_1_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000
3216#define smnBIF_CFG_DEV0_EPF0_1_PCIE_DPA_STATUS_DEFAULT 0x00000100
3217#define smnBIF_CFG_DEV0_EPF0_1_PCIE_DPA_CNTL_DEFAULT 0x00000000
3218#define smnBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000
3219#define smnBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000
3220#define smnBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000
3221#define smnBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000
3222#define smnBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000
3223#define smnBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000
3224#define smnBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000
3225#define smnBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000
3226#define smnBIF_CFG_DEV0_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a010019
3227#define smnBIF_CFG_DEV0_EPF0_1_PCIE_LINK_CNTL3_DEFAULT 0x00000000
3228#define smnBIF_CFG_DEV0_EPF0_1_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000
3229#define smnBIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f00
3230#define smnBIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f00
3231#define smnBIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f00
3232#define smnBIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f00
3233#define smnBIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f00
3234#define smnBIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f00
3235#define smnBIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f00
3236#define smnBIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f00
3237#define smnBIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f00
3238#define smnBIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f00
3239#define smnBIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f00
3240#define smnBIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f00
3241#define smnBIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f00
3242#define smnBIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f00
3243#define smnBIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f00
3244#define smnBIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f00
3245#define smnBIF_CFG_DEV0_EPF0_1_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000
3246#define smnBIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP_DEFAULT 0x00000000
3247#define smnBIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL_DEFAULT 0x00000000
3248#define smnBIF_CFG_DEV0_EPF0_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
3249#define smnBIF_CFG_DEV0_EPF0_1_PCIE_ATS_CAP_DEFAULT 0x00000000
3250#define smnBIF_CFG_DEV0_EPF0_1_PCIE_ATS_CNTL_DEFAULT 0x00000000
3251#define smnBIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_ENH_CAP_LIST_DEFAULT 0x2d000000
3252#define smnBIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_CNTL_DEFAULT 0x00000000
3253#define smnBIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_STATUS_DEFAULT 0x00000000
3254#define smnBIF_CFG_DEV0_EPF0_1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY_DEFAULT 0x00000000
3255#define smnBIF_CFG_DEV0_EPF0_1_PCIE_OUTSTAND_PAGE_REQ_ALLOC_DEFAULT 0x00000000
3256#define smnBIF_CFG_DEV0_EPF0_1_PCIE_PASID_ENH_CAP_LIST_DEFAULT 0x2e000000
3257#define smnBIF_CFG_DEV0_EPF0_1_PCIE_PASID_CAP_DEFAULT 0x00000000
3258#define smnBIF_CFG_DEV0_EPF0_1_PCIE_PASID_CNTL_DEFAULT 0x00000000
3259#define smnBIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_ENH_CAP_LIST_DEFAULT 0x2f000000
3260#define smnBIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP_DEFAULT 0x00000000
3261#define smnBIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CNTL_DEFAULT 0x00000000
3262#define smnBIF_CFG_DEV0_EPF0_1_PCIE_MC_ENH_CAP_LIST_DEFAULT 0x32000000
3263#define smnBIF_CFG_DEV0_EPF0_1_PCIE_MC_CAP_DEFAULT 0x00000000
3264#define smnBIF_CFG_DEV0_EPF0_1_PCIE_MC_CNTL_DEFAULT 0x00000000
3265#define smnBIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR0_DEFAULT 0x00000000
3266#define smnBIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR1_DEFAULT 0x00000000
3267#define smnBIF_CFG_DEV0_EPF0_1_PCIE_MC_RCV0_DEFAULT 0x00000000
3268#define smnBIF_CFG_DEV0_EPF0_1_PCIE_MC_RCV1_DEFAULT 0x00000000
3269#define smnBIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_ALL0_DEFAULT 0x00000000
3270#define smnBIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_ALL1_DEFAULT 0x00000000
3271#define smnBIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_UNTRANSLATED_0_DEFAULT 0x00000000
3272#define smnBIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_UNTRANSLATED_1_DEFAULT 0x00000000
3273#define smnBIF_CFG_DEV0_EPF0_1_PCIE_LTR_ENH_CAP_LIST_DEFAULT 0x32800000
3274#define smnBIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP_DEFAULT 0x00000000
3275#define smnBIF_CFG_DEV0_EPF0_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000
3276#define smnBIF_CFG_DEV0_EPF0_1_PCIE_ARI_CAP_DEFAULT 0x00000000
3277#define smnBIF_CFG_DEV0_EPF0_1_PCIE_ARI_CNTL_DEFAULT 0x00000000
3278#define smnBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_ENH_CAP_LIST_DEFAULT 0x00000000
3279#define smnBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP_DEFAULT 0x00000000
3280#define smnBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL_DEFAULT 0x00000000
3281#define smnBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_STATUS_DEFAULT 0x00000000
3282#define smnBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_INITIAL_VFS_DEFAULT 0x00000000
3283#define smnBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_TOTAL_VFS_DEFAULT 0x00000000
3284#define smnBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_NUM_VFS_DEFAULT 0x00000000
3285#define smnBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_FUNC_DEP_LINK_DEFAULT 0x00000000
3286#define smnBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_FIRST_VF_OFFSET_DEFAULT 0x00000000
3287#define smnBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_STRIDE_DEFAULT 0x00000000
3288#define smnBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_DEVICE_ID_DEFAULT 0x00000000
3289#define smnBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE_DEFAULT 0x00000000
3290#define smnBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE_DEFAULT 0x00000001
3291#define smnBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_0_DEFAULT 0x00000000
3292#define smnBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_1_DEFAULT 0x00000000
3293#define smnBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_2_DEFAULT 0x00000000
3294#define smnBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_3_DEFAULT 0x00000000
3295#define smnBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_4_DEFAULT 0x00000000
3296#define smnBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_5_DEFAULT 0x00000000
3297#define smnBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_DEFAULT 0x00000000
3298#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_DEFAULT 0x00000000
3299#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_DEFAULT 0x00000000
3300#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW_DEFAULT 0x00000000
3301#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_DEFAULT 0x00000000
3302#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_DEFAULT 0x00000000
3303#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_DEFAULT 0x00000000
3304#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0_DEFAULT 0x00000000
3305#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_DEFAULT 0x00000000
3306#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2_DEFAULT 0x00000000
3307#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT_DEFAULT 0x00000000
3308#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB_DEFAULT 0x00000000
3309#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS_DEFAULT 0x00000000
3310#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB_DEFAULT 0x00000000
3311#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB_DEFAULT 0x00000000
3312#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB_DEFAULT 0x00000000
3313#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB_DEFAULT 0x00000000
3314#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB_DEFAULT 0x00000000
3315#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB_DEFAULT 0x00000000
3316#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB_DEFAULT 0x00000000
3317#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB_DEFAULT 0x00000000
3318#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB_DEFAULT 0x00000000
3319#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB_DEFAULT 0x00000000
3320#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB_DEFAULT 0x00000000
3321#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB_DEFAULT 0x00000000
3322#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB_DEFAULT 0x00000000
3323#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB_DEFAULT 0x00000000
3324#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB_DEFAULT 0x00000000
3325#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB_DEFAULT 0x00000000
3326#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0_DEFAULT 0x00000000
3327#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1_DEFAULT 0x00000000
3328#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2_DEFAULT 0x00000000
3329#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3_DEFAULT 0x00000000
3330#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4_DEFAULT 0x00000000
3331#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5_DEFAULT 0x00000000
3332#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6_DEFAULT 0x00000000
3333#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7_DEFAULT 0x00000000
3334#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8_DEFAULT 0x00000000
3335#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0_DEFAULT 0x00000000
3336#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1_DEFAULT 0x00000000
3337#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2_DEFAULT 0x00000000
3338#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3_DEFAULT 0x00000000
3339#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4_DEFAULT 0x00000000
3340#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5_DEFAULT 0x00000000
3341#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6_DEFAULT 0x00000000
3342#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7_DEFAULT 0x00000000
3343#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8_DEFAULT 0x00000000
3344#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0_DEFAULT 0x00000000
3345#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1_DEFAULT 0x00000000
3346#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2_DEFAULT 0x00000000
3347#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3_DEFAULT 0x00000000
3348#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4_DEFAULT 0x00000000
3349#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5_DEFAULT 0x00000000
3350#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6_DEFAULT 0x00000000
3351#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7_DEFAULT 0x00000000
3352#define smnBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8_DEFAULT 0x00000000
3353
3354
3355// addressBlock: nbio_nbif_bif_cfg_dev0_epf1_bifcfgdecp
3356#define smnBIF_CFG_DEV0_EPF1_1_VENDOR_ID_DEFAULT 0x00000000
3357#define smnBIF_CFG_DEV0_EPF1_1_DEVICE_ID_DEFAULT 0x00000000
3358#define smnBIF_CFG_DEV0_EPF1_1_COMMAND_DEFAULT 0x00000000
3359#define smnBIF_CFG_DEV0_EPF1_1_STATUS_DEFAULT 0x00000000
3360#define smnBIF_CFG_DEV0_EPF1_1_REVISION_ID_DEFAULT 0x00000000
3361#define smnBIF_CFG_DEV0_EPF1_1_PROG_INTERFACE_DEFAULT 0x00000000
3362#define smnBIF_CFG_DEV0_EPF1_1_SUB_CLASS_DEFAULT 0x00000000
3363#define smnBIF_CFG_DEV0_EPF1_1_BASE_CLASS_DEFAULT 0x00000000
3364#define smnBIF_CFG_DEV0_EPF1_1_CACHE_LINE_DEFAULT 0x00000000
3365#define smnBIF_CFG_DEV0_EPF1_1_LATENCY_DEFAULT 0x00000000
3366#define smnBIF_CFG_DEV0_EPF1_1_HEADER_DEFAULT 0x00000000
3367#define smnBIF_CFG_DEV0_EPF1_1_BIST_DEFAULT 0x00000000
3368#define smnBIF_CFG_DEV0_EPF1_1_BASE_ADDR_1_DEFAULT 0x00000000
3369#define smnBIF_CFG_DEV0_EPF1_1_BASE_ADDR_2_DEFAULT 0x00000000
3370#define smnBIF_CFG_DEV0_EPF1_1_BASE_ADDR_3_DEFAULT 0x00000000
3371#define smnBIF_CFG_DEV0_EPF1_1_BASE_ADDR_4_DEFAULT 0x00000000
3372#define smnBIF_CFG_DEV0_EPF1_1_BASE_ADDR_5_DEFAULT 0x00000000
3373#define smnBIF_CFG_DEV0_EPF1_1_BASE_ADDR_6_DEFAULT 0x00000000
3374#define smnBIF_CFG_DEV0_EPF1_1_ADAPTER_ID_DEFAULT 0x00000000
3375#define smnBIF_CFG_DEV0_EPF1_1_ROM_BASE_ADDR_DEFAULT 0x00000000
3376#define smnBIF_CFG_DEV0_EPF1_1_CAP_PTR_DEFAULT 0x00000000
3377#define smnBIF_CFG_DEV0_EPF1_1_INTERRUPT_LINE_DEFAULT 0x000000ff
3378#define smnBIF_CFG_DEV0_EPF1_1_INTERRUPT_PIN_DEFAULT 0x00000000
3379#define smnBIF_CFG_DEV0_EPF1_1_MIN_GRANT_DEFAULT 0x00000000
3380#define smnBIF_CFG_DEV0_EPF1_1_MAX_LATENCY_DEFAULT 0x00000000
3381#define smnBIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST_DEFAULT 0x00000000
3382#define smnBIF_CFG_DEV0_EPF1_1_ADAPTER_ID_W_DEFAULT 0x00000000
3383#define smnBIF_CFG_DEV0_EPF1_1_PMI_CAP_LIST_DEFAULT 0x00000000
3384#define smnBIF_CFG_DEV0_EPF1_1_PMI_CAP_DEFAULT 0x00000000
3385#define smnBIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL_DEFAULT 0x00000000
3386#define smnBIF_CFG_DEV0_EPF1_1_PCIE_CAP_LIST_DEFAULT 0x0000a000
3387#define smnBIF_CFG_DEV0_EPF1_1_PCIE_CAP_DEFAULT 0x00000002
3388#define smnBIF_CFG_DEV0_EPF1_1_DEVICE_CAP_DEFAULT 0x10000000
3389#define smnBIF_CFG_DEV0_EPF1_1_DEVICE_CNTL_DEFAULT 0x00002810
3390#define smnBIF_CFG_DEV0_EPF1_1_DEVICE_STATUS_DEFAULT 0x00000000
3391#define smnBIF_CFG_DEV0_EPF1_1_LINK_CAP_DEFAULT 0x00011c03
3392#define smnBIF_CFG_DEV0_EPF1_1_LINK_CNTL_DEFAULT 0x00000000
3393#define smnBIF_CFG_DEV0_EPF1_1_LINK_STATUS_DEFAULT 0x00000001
3394#define smnBIF_CFG_DEV0_EPF1_1_DEVICE_CAP2_DEFAULT 0x00000000
3395#define smnBIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2_DEFAULT 0x00000000
3396#define smnBIF_CFG_DEV0_EPF1_1_DEVICE_STATUS2_DEFAULT 0x00000000
3397#define smnBIF_CFG_DEV0_EPF1_1_LINK_CAP2_DEFAULT 0x0000000e
3398#define smnBIF_CFG_DEV0_EPF1_1_LINK_CNTL2_DEFAULT 0x00000003
3399#define smnBIF_CFG_DEV0_EPF1_1_LINK_STATUS2_DEFAULT 0x00000000
3400#define smnBIF_CFG_DEV0_EPF1_1_SLOT_CAP2_DEFAULT 0x00000000
3401#define smnBIF_CFG_DEV0_EPF1_1_SLOT_CNTL2_DEFAULT 0x00000000
3402#define smnBIF_CFG_DEV0_EPF1_1_SLOT_STATUS2_DEFAULT 0x00000000
3403#define smnBIF_CFG_DEV0_EPF1_1_MSI_CAP_LIST_DEFAULT 0x0000c000
3404#define smnBIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL_DEFAULT 0x00000080
3405#define smnBIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
3406#define smnBIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
3407#define smnBIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA_DEFAULT 0x00000000
3408#define smnBIF_CFG_DEV0_EPF1_1_MSI_MASK_DEFAULT 0x00000000
3409#define smnBIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA_64_DEFAULT 0x00000000
3410#define smnBIF_CFG_DEV0_EPF1_1_MSI_MASK_64_DEFAULT 0x00000000
3411#define smnBIF_CFG_DEV0_EPF1_1_MSI_PENDING_DEFAULT 0x00000000
3412#define smnBIF_CFG_DEV0_EPF1_1_MSI_PENDING_64_DEFAULT 0x00000000
3413#define smnBIF_CFG_DEV0_EPF1_1_MSIX_CAP_LIST_DEFAULT 0x00000000
3414#define smnBIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL_DEFAULT 0x00000000
3415#define smnBIF_CFG_DEV0_EPF1_1_MSIX_TABLE_DEFAULT 0x00000000
3416#define smnBIF_CFG_DEV0_EPF1_1_MSIX_PBA_DEFAULT 0x00000000
3417#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
3418#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
3419#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
3420#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
3421#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000
3422#define smnBIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000
3423#define smnBIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000
3424#define smnBIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000
3425#define smnBIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000
3426#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000
3427#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe
3428#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000000
3429#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000
3430#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000
3431#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000000
3432#define smnBIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000
3433#define smnBIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000
3434#define smnBIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000
3435#define smnBIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
3436#define smnBIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
3437#define smnBIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
3438#define smnBIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
3439#define smnBIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
3440#define smnBIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000
3441#define smnBIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
3442#define smnBIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG0_DEFAULT 0x00000000
3443#define smnBIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG1_DEFAULT 0x00000000
3444#define smnBIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG2_DEFAULT 0x00000000
3445#define smnBIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG3_DEFAULT 0x00000000
3446#define smnBIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
3447#define smnBIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
3448#define smnBIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
3449#define smnBIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
3450#define smnBIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000
3451#define smnBIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CAP_DEFAULT 0x00000000
3452#define smnBIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL_DEFAULT 0x00000020
3453#define smnBIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CAP_DEFAULT 0x00000000
3454#define smnBIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL_DEFAULT 0x00000000
3455#define smnBIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CAP_DEFAULT 0x00000000
3456#define smnBIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL_DEFAULT 0x00000000
3457#define smnBIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CAP_DEFAULT 0x00000000
3458#define smnBIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL_DEFAULT 0x00000000
3459#define smnBIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CAP_DEFAULT 0x00000000
3460#define smnBIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL_DEFAULT 0x00000000
3461#define smnBIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CAP_DEFAULT 0x00000000
3462#define smnBIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL_DEFAULT 0x00000000
3463#define smnBIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000
3464#define smnBIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000
3465#define smnBIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000
3466#define smnBIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000
3467#define smnBIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000
3468#define smnBIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP_DEFAULT 0x00000000
3469#define smnBIF_CFG_DEV0_EPF1_1_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000
3470#define smnBIF_CFG_DEV0_EPF1_1_PCIE_DPA_STATUS_DEFAULT 0x00000100
3471#define smnBIF_CFG_DEV0_EPF1_1_PCIE_DPA_CNTL_DEFAULT 0x00000000
3472#define smnBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000
3473#define smnBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000
3474#define smnBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000
3475#define smnBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000
3476#define smnBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000
3477#define smnBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000
3478#define smnBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000
3479#define smnBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000
3480#define smnBIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a010019
3481#define smnBIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3_DEFAULT 0x00000000
3482#define smnBIF_CFG_DEV0_EPF1_1_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000
3483#define smnBIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f00
3484#define smnBIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f00
3485#define smnBIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f00
3486#define smnBIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f00
3487#define smnBIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f00
3488#define smnBIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f00
3489#define smnBIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f00
3490#define smnBIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f00
3491#define smnBIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f00
3492#define smnBIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f00
3493#define smnBIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f00
3494#define smnBIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f00
3495#define smnBIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f00
3496#define smnBIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f00
3497#define smnBIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f00
3498#define smnBIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f00
3499#define smnBIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000
3500#define smnBIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP_DEFAULT 0x00000000
3501#define smnBIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL_DEFAULT 0x00000000
3502#define smnBIF_CFG_DEV0_EPF1_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
3503#define smnBIF_CFG_DEV0_EPF1_1_PCIE_ATS_CAP_DEFAULT 0x00000000
3504#define smnBIF_CFG_DEV0_EPF1_1_PCIE_ATS_CNTL_DEFAULT 0x00000000
3505#define smnBIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_ENH_CAP_LIST_DEFAULT 0x2d000000
3506#define smnBIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_CNTL_DEFAULT 0x00000000
3507#define smnBIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS_DEFAULT 0x00000000
3508#define smnBIF_CFG_DEV0_EPF1_1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY_DEFAULT 0x00000000
3509#define smnBIF_CFG_DEV0_EPF1_1_PCIE_OUTSTAND_PAGE_REQ_ALLOC_DEFAULT 0x00000000
3510#define smnBIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST_DEFAULT 0x2e000000
3511#define smnBIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP_DEFAULT 0x00000000
3512#define smnBIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL_DEFAULT 0x00000000
3513#define smnBIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST_DEFAULT 0x2f000000
3514#define smnBIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP_DEFAULT 0x00000000
3515#define smnBIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CNTL_DEFAULT 0x00000000
3516#define smnBIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST_DEFAULT 0x32000000
3517#define smnBIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP_DEFAULT 0x00000000
3518#define smnBIF_CFG_DEV0_EPF1_1_PCIE_MC_CNTL_DEFAULT 0x00000000
3519#define smnBIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR0_DEFAULT 0x00000000
3520#define smnBIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR1_DEFAULT 0x00000000
3521#define smnBIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV0_DEFAULT 0x00000000
3522#define smnBIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV1_DEFAULT 0x00000000
3523#define smnBIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL0_DEFAULT 0x00000000
3524#define smnBIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL1_DEFAULT 0x00000000
3525#define smnBIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_0_DEFAULT 0x00000000
3526#define smnBIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_1_DEFAULT 0x00000000
3527#define smnBIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST_DEFAULT 0x32800000
3528#define smnBIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP_DEFAULT 0x00000000
3529#define smnBIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000
3530#define smnBIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP_DEFAULT 0x00000000
3531#define smnBIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL_DEFAULT 0x00000000
3532#define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST_DEFAULT 0x00000000
3533#define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP_DEFAULT 0x00000000
3534#define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL_DEFAULT 0x00000000
3535#define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_STATUS_DEFAULT 0x00000000
3536#define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_INITIAL_VFS_DEFAULT 0x00000000
3537#define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_TOTAL_VFS_DEFAULT 0x00000000
3538#define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_NUM_VFS_DEFAULT 0x00000000
3539#define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FUNC_DEP_LINK_DEFAULT 0x00000000
3540#define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FIRST_VF_OFFSET_DEFAULT 0x00000000
3541#define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_STRIDE_DEFAULT 0x00000000
3542#define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_DEVICE_ID_DEFAULT 0x00000000
3543#define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE_DEFAULT 0x00000000
3544#define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE_DEFAULT 0x00000001
3545#define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_0_DEFAULT 0x00000000
3546#define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_1_DEFAULT 0x00000000
3547#define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_2_DEFAULT 0x00000000
3548#define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_3_DEFAULT 0x00000000
3549#define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_4_DEFAULT 0x00000000
3550#define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_5_DEFAULT 0x00000000
3551#define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_DEFAULT 0x00000000
3552#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_DEFAULT 0x00000000
3553#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_DEFAULT 0x00000000
3554#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW_DEFAULT 0x00000000
3555#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_DEFAULT 0x00000000
3556#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_DEFAULT 0x00000000
3557#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_DEFAULT 0x00000000
3558#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0_DEFAULT 0x00000000
3559#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_DEFAULT 0x00000000
3560#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2_DEFAULT 0x00000000
3561#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT_DEFAULT 0x00000000
3562#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB_DEFAULT 0x00000000
3563#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS_DEFAULT 0x00000000
3564#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB_DEFAULT 0x00000000
3565#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB_DEFAULT 0x00000000
3566#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB_DEFAULT 0x00000000
3567#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB_DEFAULT 0x00000000
3568#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB_DEFAULT 0x00000000
3569#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB_DEFAULT 0x00000000
3570#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB_DEFAULT 0x00000000
3571#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB_DEFAULT 0x00000000
3572#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB_DEFAULT 0x00000000
3573#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB_DEFAULT 0x00000000
3574#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB_DEFAULT 0x00000000
3575#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB_DEFAULT 0x00000000
3576#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB_DEFAULT 0x00000000
3577#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB_DEFAULT 0x00000000
3578#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB_DEFAULT 0x00000000
3579#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB_DEFAULT 0x00000000
3580#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0_DEFAULT 0x00000000
3581#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1_DEFAULT 0x00000000
3582#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2_DEFAULT 0x00000000
3583#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3_DEFAULT 0x00000000
3584#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4_DEFAULT 0x00000000
3585#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5_DEFAULT 0x00000000
3586#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6_DEFAULT 0x00000000
3587#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7_DEFAULT 0x00000000
3588#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8_DEFAULT 0x00000000
3589#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0_DEFAULT 0x00000000
3590#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1_DEFAULT 0x00000000
3591#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2_DEFAULT 0x00000000
3592#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3_DEFAULT 0x00000000
3593#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4_DEFAULT 0x00000000
3594#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5_DEFAULT 0x00000000
3595#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6_DEFAULT 0x00000000
3596#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7_DEFAULT 0x00000000
3597#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8_DEFAULT 0x00000000
3598#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0_DEFAULT 0x00000000
3599#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1_DEFAULT 0x00000000
3600#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2_DEFAULT 0x00000000
3601#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3_DEFAULT 0x00000000
3602#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4_DEFAULT 0x00000000
3603#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5_DEFAULT 0x00000000
3604#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6_DEFAULT 0x00000000
3605#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7_DEFAULT 0x00000000
3606#define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8_DEFAULT 0x00000000
3607
3608
3609// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf0_bifcfgdecp
3610#define smnBIF_CFG_DEV0_EPF0_VF0_1_VENDOR_ID_DEFAULT 0x00000000
3611#define smnBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_ID_DEFAULT 0x00000000
3612#define smnBIF_CFG_DEV0_EPF0_VF0_1_COMMAND_DEFAULT 0x00000000
3613#define smnBIF_CFG_DEV0_EPF0_VF0_1_STATUS_DEFAULT 0x00000000
3614#define smnBIF_CFG_DEV0_EPF0_VF0_1_REVISION_ID_DEFAULT 0x00000000
3615#define smnBIF_CFG_DEV0_EPF0_VF0_1_PROG_INTERFACE_DEFAULT 0x00000000
3616#define smnBIF_CFG_DEV0_EPF0_VF0_1_SUB_CLASS_DEFAULT 0x00000000
3617#define smnBIF_CFG_DEV0_EPF0_VF0_1_BASE_CLASS_DEFAULT 0x00000000
3618#define smnBIF_CFG_DEV0_EPF0_VF0_1_CACHE_LINE_DEFAULT 0x00000000
3619#define smnBIF_CFG_DEV0_EPF0_VF0_1_LATENCY_DEFAULT 0x00000000
3620#define smnBIF_CFG_DEV0_EPF0_VF0_1_HEADER_DEFAULT 0x00000000
3621#define smnBIF_CFG_DEV0_EPF0_VF0_1_BIST_DEFAULT 0x00000000
3622#define smnBIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_1_DEFAULT 0x00000000
3623#define smnBIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_2_DEFAULT 0x00000000
3624#define smnBIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_3_DEFAULT 0x00000000
3625#define smnBIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_4_DEFAULT 0x00000000
3626#define smnBIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_5_DEFAULT 0x00000000
3627#define smnBIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_6_DEFAULT 0x00000000
3628#define smnBIF_CFG_DEV0_EPF0_VF0_1_ADAPTER_ID_DEFAULT 0x00000000
3629#define smnBIF_CFG_DEV0_EPF0_VF0_1_ROM_BASE_ADDR_DEFAULT 0x00000000
3630#define smnBIF_CFG_DEV0_EPF0_VF0_1_CAP_PTR_DEFAULT 0x00000000
3631#define smnBIF_CFG_DEV0_EPF0_VF0_1_INTERRUPT_LINE_DEFAULT 0x000000ff
3632#define smnBIF_CFG_DEV0_EPF0_VF0_1_INTERRUPT_PIN_DEFAULT 0x00000000
3633#define smnBIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP_LIST_DEFAULT 0x0000a000
3634#define smnBIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP_DEFAULT 0x00000002
3635#define smnBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP_DEFAULT 0x10000000
3636#define smnBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL_DEFAULT 0x00002810
3637#define smnBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS_DEFAULT 0x00000000
3638#define smnBIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP_DEFAULT 0x00011c03
3639#define smnBIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL_DEFAULT 0x00000000
3640#define smnBIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS_DEFAULT 0x00000001
3641#define smnBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2_DEFAULT 0x00000000
3642#define smnBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2_DEFAULT 0x00000000
3643#define smnBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS2_DEFAULT 0x00000000
3644#define smnBIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2_DEFAULT 0x0000000e
3645#define smnBIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2_DEFAULT 0x00000003
3646#define smnBIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2_DEFAULT 0x00000000
3647#define smnBIF_CFG_DEV0_EPF0_VF0_1_SLOT_CAP2_DEFAULT 0x00000000
3648#define smnBIF_CFG_DEV0_EPF0_VF0_1_SLOT_CNTL2_DEFAULT 0x00000000
3649#define smnBIF_CFG_DEV0_EPF0_VF0_1_SLOT_STATUS2_DEFAULT 0x00000000
3650#define smnBIF_CFG_DEV0_EPF0_VF0_1_MSI_CAP_LIST_DEFAULT 0x0000c000
3651#define smnBIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL_DEFAULT 0x00000080
3652#define smnBIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
3653#define smnBIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
3654#define smnBIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_DATA_DEFAULT 0x00000000
3655#define smnBIF_CFG_DEV0_EPF0_VF0_1_MSI_MASK_DEFAULT 0x00000000
3656#define smnBIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_DATA_64_DEFAULT 0x00000000
3657#define smnBIF_CFG_DEV0_EPF0_VF0_1_MSI_MASK_64_DEFAULT 0x00000000
3658#define smnBIF_CFG_DEV0_EPF0_VF0_1_MSI_PENDING_DEFAULT 0x00000000
3659#define smnBIF_CFG_DEV0_EPF0_VF0_1_MSI_PENDING_64_DEFAULT 0x00000000
3660#define smnBIF_CFG_DEV0_EPF0_VF0_1_MSIX_CAP_LIST_DEFAULT 0x00000000
3661#define smnBIF_CFG_DEV0_EPF0_VF0_1_MSIX_MSG_CNTL_DEFAULT 0x00000000
3662#define smnBIF_CFG_DEV0_EPF0_VF0_1_MSIX_TABLE_DEFAULT 0x00000000
3663#define smnBIF_CFG_DEV0_EPF0_VF0_1_MSIX_PBA_DEFAULT 0x00000000
3664#define smnBIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
3665#define smnBIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
3666#define smnBIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
3667#define smnBIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
3668#define smnBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
3669#define smnBIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
3670#define smnBIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
3671#define smnBIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
3672#define smnBIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
3673#define smnBIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000
3674#define smnBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
3675#define smnBIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG0_DEFAULT 0x00000000
3676#define smnBIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG1_DEFAULT 0x00000000
3677#define smnBIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG2_DEFAULT 0x00000000
3678#define smnBIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG3_DEFAULT 0x00000000
3679#define smnBIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
3680#define smnBIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
3681#define smnBIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
3682#define smnBIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
3683#define smnBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
3684#define smnBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_CAP_DEFAULT 0x00000000
3685#define smnBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_CNTL_DEFAULT 0x00000000
3686#define smnBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000
3687#define smnBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CAP_DEFAULT 0x00000000
3688#define smnBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CNTL_DEFAULT 0x00000000
3689
3690
3691// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf1_bifcfgdecp
3692#define smnBIF_CFG_DEV0_EPF0_VF1_1_VENDOR_ID_DEFAULT 0x00000000
3693#define smnBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_ID_DEFAULT 0x00000000
3694#define smnBIF_CFG_DEV0_EPF0_VF1_1_COMMAND_DEFAULT 0x00000000
3695#define smnBIF_CFG_DEV0_EPF0_VF1_1_STATUS_DEFAULT 0x00000000
3696#define smnBIF_CFG_DEV0_EPF0_VF1_1_REVISION_ID_DEFAULT 0x00000000
3697#define smnBIF_CFG_DEV0_EPF0_VF1_1_PROG_INTERFACE_DEFAULT 0x00000000
3698#define smnBIF_CFG_DEV0_EPF0_VF1_1_SUB_CLASS_DEFAULT 0x00000000
3699#define smnBIF_CFG_DEV0_EPF0_VF1_1_BASE_CLASS_DEFAULT 0x00000000
3700#define smnBIF_CFG_DEV0_EPF0_VF1_1_CACHE_LINE_DEFAULT 0x00000000
3701#define smnBIF_CFG_DEV0_EPF0_VF1_1_LATENCY_DEFAULT 0x00000000
3702#define smnBIF_CFG_DEV0_EPF0_VF1_1_HEADER_DEFAULT 0x00000000
3703#define smnBIF_CFG_DEV0_EPF0_VF1_1_BIST_DEFAULT 0x00000000
3704#define smnBIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_1_DEFAULT 0x00000000
3705#define smnBIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_2_DEFAULT 0x00000000
3706#define smnBIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_3_DEFAULT 0x00000000
3707#define smnBIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_4_DEFAULT 0x00000000
3708#define smnBIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_5_DEFAULT 0x00000000
3709#define smnBIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_6_DEFAULT 0x00000000
3710#define smnBIF_CFG_DEV0_EPF0_VF1_1_ADAPTER_ID_DEFAULT 0x00000000
3711#define smnBIF_CFG_DEV0_EPF0_VF1_1_ROM_BASE_ADDR_DEFAULT 0x00000000
3712#define smnBIF_CFG_DEV0_EPF0_VF1_1_CAP_PTR_DEFAULT 0x00000000
3713#define smnBIF_CFG_DEV0_EPF0_VF1_1_INTERRUPT_LINE_DEFAULT 0x000000ff
3714#define smnBIF_CFG_DEV0_EPF0_VF1_1_INTERRUPT_PIN_DEFAULT 0x00000000
3715#define smnBIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP_LIST_DEFAULT 0x0000a000
3716#define smnBIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP_DEFAULT 0x00000002
3717#define smnBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP_DEFAULT 0x10000000
3718#define smnBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL_DEFAULT 0x00002810
3719#define smnBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS_DEFAULT 0x00000000
3720#define smnBIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP_DEFAULT 0x00011c03
3721#define smnBIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL_DEFAULT 0x00000000
3722#define smnBIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS_DEFAULT 0x00000001
3723#define smnBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2_DEFAULT 0x00000000
3724#define smnBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2_DEFAULT 0x00000000
3725#define smnBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS2_DEFAULT 0x00000000
3726#define smnBIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2_DEFAULT 0x0000000e
3727#define smnBIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2_DEFAULT 0x00000003
3728#define smnBIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2_DEFAULT 0x00000000
3729#define smnBIF_CFG_DEV0_EPF0_VF1_1_SLOT_CAP2_DEFAULT 0x00000000
3730#define smnBIF_CFG_DEV0_EPF0_VF1_1_SLOT_CNTL2_DEFAULT 0x00000000
3731#define smnBIF_CFG_DEV0_EPF0_VF1_1_SLOT_STATUS2_DEFAULT 0x00000000
3732#define smnBIF_CFG_DEV0_EPF0_VF1_1_MSI_CAP_LIST_DEFAULT 0x0000c000
3733#define smnBIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL_DEFAULT 0x00000080
3734#define smnBIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
3735#define smnBIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
3736#define smnBIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_DATA_DEFAULT 0x00000000
3737#define smnBIF_CFG_DEV0_EPF0_VF1_1_MSI_MASK_DEFAULT 0x00000000
3738#define smnBIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_DATA_64_DEFAULT 0x00000000
3739#define smnBIF_CFG_DEV0_EPF0_VF1_1_MSI_MASK_64_DEFAULT 0x00000000
3740#define smnBIF_CFG_DEV0_EPF0_VF1_1_MSI_PENDING_DEFAULT 0x00000000
3741#define smnBIF_CFG_DEV0_EPF0_VF1_1_MSI_PENDING_64_DEFAULT 0x00000000
3742#define smnBIF_CFG_DEV0_EPF0_VF1_1_MSIX_CAP_LIST_DEFAULT 0x00000000
3743#define smnBIF_CFG_DEV0_EPF0_VF1_1_MSIX_MSG_CNTL_DEFAULT 0x00000000
3744#define smnBIF_CFG_DEV0_EPF0_VF1_1_MSIX_TABLE_DEFAULT 0x00000000
3745#define smnBIF_CFG_DEV0_EPF0_VF1_1_MSIX_PBA_DEFAULT 0x00000000
3746#define smnBIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
3747#define smnBIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
3748#define smnBIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
3749#define smnBIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
3750#define smnBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
3751#define smnBIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
3752#define smnBIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
3753#define smnBIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
3754#define smnBIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
3755#define smnBIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000
3756#define smnBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
3757#define smnBIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG0_DEFAULT 0x00000000
3758#define smnBIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG1_DEFAULT 0x00000000
3759#define smnBIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG2_DEFAULT 0x00000000
3760#define smnBIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG3_DEFAULT 0x00000000
3761#define smnBIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
3762#define smnBIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
3763#define smnBIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
3764#define smnBIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
3765#define smnBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
3766#define smnBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_CAP_DEFAULT 0x00000000
3767#define smnBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_CNTL_DEFAULT 0x00000000
3768#define smnBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000
3769#define smnBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CAP_DEFAULT 0x00000000
3770#define smnBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CNTL_DEFAULT 0x00000000
3771
3772
3773// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf2_bifcfgdecp
3774#define smnBIF_CFG_DEV0_EPF0_VF2_1_VENDOR_ID_DEFAULT 0x00000000
3775#define smnBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_ID_DEFAULT 0x00000000
3776#define smnBIF_CFG_DEV0_EPF0_VF2_1_COMMAND_DEFAULT 0x00000000
3777#define smnBIF_CFG_DEV0_EPF0_VF2_1_STATUS_DEFAULT 0x00000000
3778#define smnBIF_CFG_DEV0_EPF0_VF2_1_REVISION_ID_DEFAULT 0x00000000
3779#define smnBIF_CFG_DEV0_EPF0_VF2_1_PROG_INTERFACE_DEFAULT 0x00000000
3780#define smnBIF_CFG_DEV0_EPF0_VF2_1_SUB_CLASS_DEFAULT 0x00000000
3781#define smnBIF_CFG_DEV0_EPF0_VF2_1_BASE_CLASS_DEFAULT 0x00000000
3782#define smnBIF_CFG_DEV0_EPF0_VF2_1_CACHE_LINE_DEFAULT 0x00000000
3783#define smnBIF_CFG_DEV0_EPF0_VF2_1_LATENCY_DEFAULT 0x00000000
3784#define smnBIF_CFG_DEV0_EPF0_VF2_1_HEADER_DEFAULT 0x00000000
3785#define smnBIF_CFG_DEV0_EPF0_VF2_1_BIST_DEFAULT 0x00000000
3786#define smnBIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_1_DEFAULT 0x00000000
3787#define smnBIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_2_DEFAULT 0x00000000
3788#define smnBIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_3_DEFAULT 0x00000000
3789#define smnBIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_4_DEFAULT 0x00000000
3790#define smnBIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_5_DEFAULT 0x00000000
3791#define smnBIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_6_DEFAULT 0x00000000
3792#define smnBIF_CFG_DEV0_EPF0_VF2_1_ADAPTER_ID_DEFAULT 0x00000000
3793#define smnBIF_CFG_DEV0_EPF0_VF2_1_ROM_BASE_ADDR_DEFAULT 0x00000000
3794#define smnBIF_CFG_DEV0_EPF0_VF2_1_CAP_PTR_DEFAULT 0x00000000
3795#define smnBIF_CFG_DEV0_EPF0_VF2_1_INTERRUPT_LINE_DEFAULT 0x000000ff
3796#define smnBIF_CFG_DEV0_EPF0_VF2_1_INTERRUPT_PIN_DEFAULT 0x00000000
3797#define smnBIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP_LIST_DEFAULT 0x0000a000
3798#define smnBIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP_DEFAULT 0x00000002
3799#define smnBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP_DEFAULT 0x10000000
3800#define smnBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL_DEFAULT 0x00002810
3801#define smnBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS_DEFAULT 0x00000000
3802#define smnBIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP_DEFAULT 0x00011c03
3803#define smnBIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL_DEFAULT 0x00000000
3804#define smnBIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS_DEFAULT 0x00000001
3805#define smnBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2_DEFAULT 0x00000000
3806#define smnBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2_DEFAULT 0x00000000
3807#define smnBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS2_DEFAULT 0x00000000
3808#define smnBIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2_DEFAULT 0x0000000e
3809#define smnBIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2_DEFAULT 0x00000003
3810#define smnBIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2_DEFAULT 0x00000000
3811#define smnBIF_CFG_DEV0_EPF0_VF2_1_SLOT_CAP2_DEFAULT 0x00000000
3812#define smnBIF_CFG_DEV0_EPF0_VF2_1_SLOT_CNTL2_DEFAULT 0x00000000
3813#define smnBIF_CFG_DEV0_EPF0_VF2_1_SLOT_STATUS2_DEFAULT 0x00000000
3814#define smnBIF_CFG_DEV0_EPF0_VF2_1_MSI_CAP_LIST_DEFAULT 0x0000c000
3815#define smnBIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL_DEFAULT 0x00000080
3816#define smnBIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
3817#define smnBIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
3818#define smnBIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_DATA_DEFAULT 0x00000000
3819#define smnBIF_CFG_DEV0_EPF0_VF2_1_MSI_MASK_DEFAULT 0x00000000
3820#define smnBIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_DATA_64_DEFAULT 0x00000000
3821#define smnBIF_CFG_DEV0_EPF0_VF2_1_MSI_MASK_64_DEFAULT 0x00000000
3822#define smnBIF_CFG_DEV0_EPF0_VF2_1_MSI_PENDING_DEFAULT 0x00000000
3823#define smnBIF_CFG_DEV0_EPF0_VF2_1_MSI_PENDING_64_DEFAULT 0x00000000
3824#define smnBIF_CFG_DEV0_EPF0_VF2_1_MSIX_CAP_LIST_DEFAULT 0x00000000
3825#define smnBIF_CFG_DEV0_EPF0_VF2_1_MSIX_MSG_CNTL_DEFAULT 0x00000000
3826#define smnBIF_CFG_DEV0_EPF0_VF2_1_MSIX_TABLE_DEFAULT 0x00000000
3827#define smnBIF_CFG_DEV0_EPF0_VF2_1_MSIX_PBA_DEFAULT 0x00000000
3828#define smnBIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
3829#define smnBIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
3830#define smnBIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
3831#define smnBIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
3832#define smnBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
3833#define smnBIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
3834#define smnBIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
3835#define smnBIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
3836#define smnBIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
3837#define smnBIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000
3838#define smnBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
3839#define smnBIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG0_DEFAULT 0x00000000
3840#define smnBIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG1_DEFAULT 0x00000000
3841#define smnBIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG2_DEFAULT 0x00000000
3842#define smnBIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG3_DEFAULT 0x00000000
3843#define smnBIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
3844#define smnBIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
3845#define smnBIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
3846#define smnBIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
3847#define smnBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
3848#define smnBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_CAP_DEFAULT 0x00000000
3849#define smnBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_CNTL_DEFAULT 0x00000000
3850#define smnBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000
3851#define smnBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CAP_DEFAULT 0x00000000
3852#define smnBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CNTL_DEFAULT 0x00000000
3853
3854
3855// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf3_bifcfgdecp
3856#define smnBIF_CFG_DEV0_EPF0_VF3_1_VENDOR_ID_DEFAULT 0x00000000
3857#define smnBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_ID_DEFAULT 0x00000000
3858#define smnBIF_CFG_DEV0_EPF0_VF3_1_COMMAND_DEFAULT 0x00000000
3859#define smnBIF_CFG_DEV0_EPF0_VF3_1_STATUS_DEFAULT 0x00000000
3860#define smnBIF_CFG_DEV0_EPF0_VF3_1_REVISION_ID_DEFAULT 0x00000000
3861#define smnBIF_CFG_DEV0_EPF0_VF3_1_PROG_INTERFACE_DEFAULT 0x00000000
3862#define smnBIF_CFG_DEV0_EPF0_VF3_1_SUB_CLASS_DEFAULT 0x00000000
3863#define smnBIF_CFG_DEV0_EPF0_VF3_1_BASE_CLASS_DEFAULT 0x00000000
3864#define smnBIF_CFG_DEV0_EPF0_VF3_1_CACHE_LINE_DEFAULT 0x00000000
3865#define smnBIF_CFG_DEV0_EPF0_VF3_1_LATENCY_DEFAULT 0x00000000
3866#define smnBIF_CFG_DEV0_EPF0_VF3_1_HEADER_DEFAULT 0x00000000
3867#define smnBIF_CFG_DEV0_EPF0_VF3_1_BIST_DEFAULT 0x00000000
3868#define smnBIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_1_DEFAULT 0x00000000
3869#define smnBIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_2_DEFAULT 0x00000000
3870#define smnBIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_3_DEFAULT 0x00000000
3871#define smnBIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_4_DEFAULT 0x00000000
3872#define smnBIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_5_DEFAULT 0x00000000
3873#define smnBIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_6_DEFAULT 0x00000000
3874#define smnBIF_CFG_DEV0_EPF0_VF3_1_ADAPTER_ID_DEFAULT 0x00000000
3875#define smnBIF_CFG_DEV0_EPF0_VF3_1_ROM_BASE_ADDR_DEFAULT 0x00000000
3876#define smnBIF_CFG_DEV0_EPF0_VF3_1_CAP_PTR_DEFAULT 0x00000000
3877#define smnBIF_CFG_DEV0_EPF0_VF3_1_INTERRUPT_LINE_DEFAULT 0x000000ff
3878#define smnBIF_CFG_DEV0_EPF0_VF3_1_INTERRUPT_PIN_DEFAULT 0x00000000
3879#define smnBIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP_LIST_DEFAULT 0x0000a000
3880#define smnBIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP_DEFAULT 0x00000002
3881#define smnBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP_DEFAULT 0x10000000
3882#define smnBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL_DEFAULT 0x00002810
3883#define smnBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS_DEFAULT 0x00000000
3884#define smnBIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP_DEFAULT 0x00011c03
3885#define smnBIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL_DEFAULT 0x00000000
3886#define smnBIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS_DEFAULT 0x00000001
3887#define smnBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2_DEFAULT 0x00000000
3888#define smnBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2_DEFAULT 0x00000000
3889#define smnBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS2_DEFAULT 0x00000000
3890#define smnBIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2_DEFAULT 0x0000000e
3891#define smnBIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2_DEFAULT 0x00000003
3892#define smnBIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2_DEFAULT 0x00000000
3893#define smnBIF_CFG_DEV0_EPF0_VF3_1_SLOT_CAP2_DEFAULT 0x00000000
3894#define smnBIF_CFG_DEV0_EPF0_VF3_1_SLOT_CNTL2_DEFAULT 0x00000000
3895#define smnBIF_CFG_DEV0_EPF0_VF3_1_SLOT_STATUS2_DEFAULT 0x00000000
3896#define smnBIF_CFG_DEV0_EPF0_VF3_1_MSI_CAP_LIST_DEFAULT 0x0000c000
3897#define smnBIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL_DEFAULT 0x00000080
3898#define smnBIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
3899#define smnBIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
3900#define smnBIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_DATA_DEFAULT 0x00000000
3901#define smnBIF_CFG_DEV0_EPF0_VF3_1_MSI_MASK_DEFAULT 0x00000000
3902#define smnBIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_DATA_64_DEFAULT 0x00000000
3903#define smnBIF_CFG_DEV0_EPF0_VF3_1_MSI_MASK_64_DEFAULT 0x00000000
3904#define smnBIF_CFG_DEV0_EPF0_VF3_1_MSI_PENDING_DEFAULT 0x00000000
3905#define smnBIF_CFG_DEV0_EPF0_VF3_1_MSI_PENDING_64_DEFAULT 0x00000000
3906#define smnBIF_CFG_DEV0_EPF0_VF3_1_MSIX_CAP_LIST_DEFAULT 0x00000000
3907#define smnBIF_CFG_DEV0_EPF0_VF3_1_MSIX_MSG_CNTL_DEFAULT 0x00000000
3908#define smnBIF_CFG_DEV0_EPF0_VF3_1_MSIX_TABLE_DEFAULT 0x00000000
3909#define smnBIF_CFG_DEV0_EPF0_VF3_1_MSIX_PBA_DEFAULT 0x00000000
3910#define smnBIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
3911#define smnBIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
3912#define smnBIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
3913#define smnBIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
3914#define smnBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
3915#define smnBIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
3916#define smnBIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
3917#define smnBIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
3918#define smnBIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
3919#define smnBIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000
3920#define smnBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
3921#define smnBIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG0_DEFAULT 0x00000000
3922#define smnBIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG1_DEFAULT 0x00000000
3923#define smnBIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG2_DEFAULT 0x00000000
3924#define smnBIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG3_DEFAULT 0x00000000
3925#define smnBIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
3926#define smnBIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
3927#define smnBIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
3928#define smnBIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
3929#define smnBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
3930#define smnBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_CAP_DEFAULT 0x00000000
3931#define smnBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_CNTL_DEFAULT 0x00000000
3932#define smnBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000
3933#define smnBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CAP_DEFAULT 0x00000000
3934#define smnBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CNTL_DEFAULT 0x00000000
3935
3936
3937// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf4_bifcfgdecp
3938#define smnBIF_CFG_DEV0_EPF0_VF4_1_VENDOR_ID_DEFAULT 0x00000000
3939#define smnBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_ID_DEFAULT 0x00000000
3940#define smnBIF_CFG_DEV0_EPF0_VF4_1_COMMAND_DEFAULT 0x00000000
3941#define smnBIF_CFG_DEV0_EPF0_VF4_1_STATUS_DEFAULT 0x00000000
3942#define smnBIF_CFG_DEV0_EPF0_VF4_1_REVISION_ID_DEFAULT 0x00000000
3943#define smnBIF_CFG_DEV0_EPF0_VF4_1_PROG_INTERFACE_DEFAULT 0x00000000
3944#define smnBIF_CFG_DEV0_EPF0_VF4_1_SUB_CLASS_DEFAULT 0x00000000
3945#define smnBIF_CFG_DEV0_EPF0_VF4_1_BASE_CLASS_DEFAULT 0x00000000
3946#define smnBIF_CFG_DEV0_EPF0_VF4_1_CACHE_LINE_DEFAULT 0x00000000
3947#define smnBIF_CFG_DEV0_EPF0_VF4_1_LATENCY_DEFAULT 0x00000000
3948#define smnBIF_CFG_DEV0_EPF0_VF4_1_HEADER_DEFAULT 0x00000000
3949#define smnBIF_CFG_DEV0_EPF0_VF4_1_BIST_DEFAULT 0x00000000
3950#define smnBIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_1_DEFAULT 0x00000000
3951#define smnBIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_2_DEFAULT 0x00000000
3952#define smnBIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_3_DEFAULT 0x00000000
3953#define smnBIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_4_DEFAULT 0x00000000
3954#define smnBIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_5_DEFAULT 0x00000000
3955#define smnBIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_6_DEFAULT 0x00000000
3956#define smnBIF_CFG_DEV0_EPF0_VF4_1_ADAPTER_ID_DEFAULT 0x00000000
3957#define smnBIF_CFG_DEV0_EPF0_VF4_1_ROM_BASE_ADDR_DEFAULT 0x00000000
3958#define smnBIF_CFG_DEV0_EPF0_VF4_1_CAP_PTR_DEFAULT 0x00000000
3959#define smnBIF_CFG_DEV0_EPF0_VF4_1_INTERRUPT_LINE_DEFAULT 0x000000ff
3960#define smnBIF_CFG_DEV0_EPF0_VF4_1_INTERRUPT_PIN_DEFAULT 0x00000000
3961#define smnBIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP_LIST_DEFAULT 0x0000a000
3962#define smnBIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP_DEFAULT 0x00000002
3963#define smnBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP_DEFAULT 0x10000000
3964#define smnBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL_DEFAULT 0x00002810
3965#define smnBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS_DEFAULT 0x00000000
3966#define smnBIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP_DEFAULT 0x00011c03
3967#define smnBIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL_DEFAULT 0x00000000
3968#define smnBIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS_DEFAULT 0x00000001
3969#define smnBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2_DEFAULT 0x00000000
3970#define smnBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2_DEFAULT 0x00000000
3971#define smnBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS2_DEFAULT 0x00000000
3972#define smnBIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2_DEFAULT 0x0000000e
3973#define smnBIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2_DEFAULT 0x00000003
3974#define smnBIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2_DEFAULT 0x00000000
3975#define smnBIF_CFG_DEV0_EPF0_VF4_1_SLOT_CAP2_DEFAULT 0x00000000
3976#define smnBIF_CFG_DEV0_EPF0_VF4_1_SLOT_CNTL2_DEFAULT 0x00000000
3977#define smnBIF_CFG_DEV0_EPF0_VF4_1_SLOT_STATUS2_DEFAULT 0x00000000
3978#define smnBIF_CFG_DEV0_EPF0_VF4_1_MSI_CAP_LIST_DEFAULT 0x0000c000
3979#define smnBIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL_DEFAULT 0x00000080
3980#define smnBIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
3981#define smnBIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
3982#define smnBIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_DATA_DEFAULT 0x00000000
3983#define smnBIF_CFG_DEV0_EPF0_VF4_1_MSI_MASK_DEFAULT 0x00000000
3984#define smnBIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_DATA_64_DEFAULT 0x00000000
3985#define smnBIF_CFG_DEV0_EPF0_VF4_1_MSI_MASK_64_DEFAULT 0x00000000
3986#define smnBIF_CFG_DEV0_EPF0_VF4_1_MSI_PENDING_DEFAULT 0x00000000
3987#define smnBIF_CFG_DEV0_EPF0_VF4_1_MSI_PENDING_64_DEFAULT 0x00000000
3988#define smnBIF_CFG_DEV0_EPF0_VF4_1_MSIX_CAP_LIST_DEFAULT 0x00000000
3989#define smnBIF_CFG_DEV0_EPF0_VF4_1_MSIX_MSG_CNTL_DEFAULT 0x00000000
3990#define smnBIF_CFG_DEV0_EPF0_VF4_1_MSIX_TABLE_DEFAULT 0x00000000
3991#define smnBIF_CFG_DEV0_EPF0_VF4_1_MSIX_PBA_DEFAULT 0x00000000
3992#define smnBIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
3993#define smnBIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
3994#define smnBIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
3995#define smnBIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
3996#define smnBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
3997#define smnBIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
3998#define smnBIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
3999#define smnBIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
4000#define smnBIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
4001#define smnBIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000
4002#define smnBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
4003#define smnBIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG0_DEFAULT 0x00000000
4004#define smnBIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG1_DEFAULT 0x00000000
4005#define smnBIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG2_DEFAULT 0x00000000
4006#define smnBIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG3_DEFAULT 0x00000000
4007#define smnBIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
4008#define smnBIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
4009#define smnBIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
4010#define smnBIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
4011#define smnBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
4012#define smnBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_CAP_DEFAULT 0x00000000
4013#define smnBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_CNTL_DEFAULT 0x00000000
4014#define smnBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000
4015#define smnBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CAP_DEFAULT 0x00000000
4016#define smnBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CNTL_DEFAULT 0x00000000
4017
4018
4019// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf5_bifcfgdecp
4020#define smnBIF_CFG_DEV0_EPF0_VF5_1_VENDOR_ID_DEFAULT 0x00000000
4021#define smnBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_ID_DEFAULT 0x00000000
4022#define smnBIF_CFG_DEV0_EPF0_VF5_1_COMMAND_DEFAULT 0x00000000
4023#define smnBIF_CFG_DEV0_EPF0_VF5_1_STATUS_DEFAULT 0x00000000
4024#define smnBIF_CFG_DEV0_EPF0_VF5_1_REVISION_ID_DEFAULT 0x00000000
4025#define smnBIF_CFG_DEV0_EPF0_VF5_1_PROG_INTERFACE_DEFAULT 0x00000000
4026#define smnBIF_CFG_DEV0_EPF0_VF5_1_SUB_CLASS_DEFAULT 0x00000000
4027#define smnBIF_CFG_DEV0_EPF0_VF5_1_BASE_CLASS_DEFAULT 0x00000000
4028#define smnBIF_CFG_DEV0_EPF0_VF5_1_CACHE_LINE_DEFAULT 0x00000000
4029#define smnBIF_CFG_DEV0_EPF0_VF5_1_LATENCY_DEFAULT 0x00000000
4030#define smnBIF_CFG_DEV0_EPF0_VF5_1_HEADER_DEFAULT 0x00000000
4031#define smnBIF_CFG_DEV0_EPF0_VF5_1_BIST_DEFAULT 0x00000000
4032#define smnBIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_1_DEFAULT 0x00000000
4033#define smnBIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_2_DEFAULT 0x00000000
4034#define smnBIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_3_DEFAULT 0x00000000
4035#define smnBIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_4_DEFAULT 0x00000000
4036#define smnBIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_5_DEFAULT 0x00000000
4037#define smnBIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_6_DEFAULT 0x00000000
4038#define smnBIF_CFG_DEV0_EPF0_VF5_1_ADAPTER_ID_DEFAULT 0x00000000
4039#define smnBIF_CFG_DEV0_EPF0_VF5_1_ROM_BASE_ADDR_DEFAULT 0x00000000
4040#define smnBIF_CFG_DEV0_EPF0_VF5_1_CAP_PTR_DEFAULT 0x00000000
4041#define smnBIF_CFG_DEV0_EPF0_VF5_1_INTERRUPT_LINE_DEFAULT 0x000000ff
4042#define smnBIF_CFG_DEV0_EPF0_VF5_1_INTERRUPT_PIN_DEFAULT 0x00000000
4043#define smnBIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP_LIST_DEFAULT 0x0000a000
4044#define smnBIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP_DEFAULT 0x00000002
4045#define smnBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP_DEFAULT 0x10000000
4046#define smnBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL_DEFAULT 0x00002810
4047#define smnBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS_DEFAULT 0x00000000
4048#define smnBIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP_DEFAULT 0x00011c03
4049#define smnBIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL_DEFAULT 0x00000000
4050#define smnBIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS_DEFAULT 0x00000001
4051#define smnBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2_DEFAULT 0x00000000
4052#define smnBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2_DEFAULT 0x00000000
4053#define smnBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS2_DEFAULT 0x00000000
4054#define smnBIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2_DEFAULT 0x0000000e
4055#define smnBIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2_DEFAULT 0x00000003
4056#define smnBIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2_DEFAULT 0x00000000
4057#define smnBIF_CFG_DEV0_EPF0_VF5_1_SLOT_CAP2_DEFAULT 0x00000000
4058#define smnBIF_CFG_DEV0_EPF0_VF5_1_SLOT_CNTL2_DEFAULT 0x00000000
4059#define smnBIF_CFG_DEV0_EPF0_VF5_1_SLOT_STATUS2_DEFAULT 0x00000000
4060#define smnBIF_CFG_DEV0_EPF0_VF5_1_MSI_CAP_LIST_DEFAULT 0x0000c000
4061#define smnBIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL_DEFAULT 0x00000080
4062#define smnBIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
4063#define smnBIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
4064#define smnBIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_DATA_DEFAULT 0x00000000
4065#define smnBIF_CFG_DEV0_EPF0_VF5_1_MSI_MASK_DEFAULT 0x00000000
4066#define smnBIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_DATA_64_DEFAULT 0x00000000
4067#define smnBIF_CFG_DEV0_EPF0_VF5_1_MSI_MASK_64_DEFAULT 0x00000000
4068#define smnBIF_CFG_DEV0_EPF0_VF5_1_MSI_PENDING_DEFAULT 0x00000000
4069#define smnBIF_CFG_DEV0_EPF0_VF5_1_MSI_PENDING_64_DEFAULT 0x00000000
4070#define smnBIF_CFG_DEV0_EPF0_VF5_1_MSIX_CAP_LIST_DEFAULT 0x00000000
4071#define smnBIF_CFG_DEV0_EPF0_VF5_1_MSIX_MSG_CNTL_DEFAULT 0x00000000
4072#define smnBIF_CFG_DEV0_EPF0_VF5_1_MSIX_TABLE_DEFAULT 0x00000000
4073#define smnBIF_CFG_DEV0_EPF0_VF5_1_MSIX_PBA_DEFAULT 0x00000000
4074#define smnBIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
4075#define smnBIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
4076#define smnBIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
4077#define smnBIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
4078#define smnBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
4079#define smnBIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
4080#define smnBIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
4081#define smnBIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
4082#define smnBIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
4083#define smnBIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000
4084#define smnBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
4085#define smnBIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG0_DEFAULT 0x00000000
4086#define smnBIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG1_DEFAULT 0x00000000
4087#define smnBIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG2_DEFAULT 0x00000000
4088#define smnBIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG3_DEFAULT 0x00000000
4089#define smnBIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
4090#define smnBIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
4091#define smnBIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
4092#define smnBIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
4093#define smnBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
4094#define smnBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_CAP_DEFAULT 0x00000000
4095#define smnBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_CNTL_DEFAULT 0x00000000
4096#define smnBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000
4097#define smnBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CAP_DEFAULT 0x00000000
4098#define smnBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CNTL_DEFAULT 0x00000000
4099
4100
4101// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf6_bifcfgdecp
4102#define smnBIF_CFG_DEV0_EPF0_VF6_1_VENDOR_ID_DEFAULT 0x00000000
4103#define smnBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_ID_DEFAULT 0x00000000
4104#define smnBIF_CFG_DEV0_EPF0_VF6_1_COMMAND_DEFAULT 0x00000000
4105#define smnBIF_CFG_DEV0_EPF0_VF6_1_STATUS_DEFAULT 0x00000000
4106#define smnBIF_CFG_DEV0_EPF0_VF6_1_REVISION_ID_DEFAULT 0x00000000
4107#define smnBIF_CFG_DEV0_EPF0_VF6_1_PROG_INTERFACE_DEFAULT 0x00000000
4108#define smnBIF_CFG_DEV0_EPF0_VF6_1_SUB_CLASS_DEFAULT 0x00000000
4109#define smnBIF_CFG_DEV0_EPF0_VF6_1_BASE_CLASS_DEFAULT 0x00000000
4110#define smnBIF_CFG_DEV0_EPF0_VF6_1_CACHE_LINE_DEFAULT 0x00000000
4111#define smnBIF_CFG_DEV0_EPF0_VF6_1_LATENCY_DEFAULT 0x00000000
4112#define smnBIF_CFG_DEV0_EPF0_VF6_1_HEADER_DEFAULT 0x00000000
4113#define smnBIF_CFG_DEV0_EPF0_VF6_1_BIST_DEFAULT 0x00000000
4114#define smnBIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_1_DEFAULT 0x00000000
4115#define smnBIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_2_DEFAULT 0x00000000
4116#define smnBIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_3_DEFAULT 0x00000000
4117#define smnBIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_4_DEFAULT 0x00000000
4118#define smnBIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_5_DEFAULT 0x00000000
4119#define smnBIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_6_DEFAULT 0x00000000
4120#define smnBIF_CFG_DEV0_EPF0_VF6_1_ADAPTER_ID_DEFAULT 0x00000000
4121#define smnBIF_CFG_DEV0_EPF0_VF6_1_ROM_BASE_ADDR_DEFAULT 0x00000000
4122#define smnBIF_CFG_DEV0_EPF0_VF6_1_CAP_PTR_DEFAULT 0x00000000
4123#define smnBIF_CFG_DEV0_EPF0_VF6_1_INTERRUPT_LINE_DEFAULT 0x000000ff
4124#define smnBIF_CFG_DEV0_EPF0_VF6_1_INTERRUPT_PIN_DEFAULT 0x00000000
4125#define smnBIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP_LIST_DEFAULT 0x0000a000
4126#define smnBIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP_DEFAULT 0x00000002
4127#define smnBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP_DEFAULT 0x10000000
4128#define smnBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL_DEFAULT 0x00002810
4129#define smnBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS_DEFAULT 0x00000000
4130#define smnBIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP_DEFAULT 0x00011c03
4131#define smnBIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL_DEFAULT 0x00000000
4132#define smnBIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS_DEFAULT 0x00000001
4133#define smnBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2_DEFAULT 0x00000000
4134#define smnBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2_DEFAULT 0x00000000
4135#define smnBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS2_DEFAULT 0x00000000
4136#define smnBIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2_DEFAULT 0x0000000e
4137#define smnBIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2_DEFAULT 0x00000003
4138#define smnBIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2_DEFAULT 0x00000000
4139#define smnBIF_CFG_DEV0_EPF0_VF6_1_SLOT_CAP2_DEFAULT 0x00000000
4140#define smnBIF_CFG_DEV0_EPF0_VF6_1_SLOT_CNTL2_DEFAULT 0x00000000
4141#define smnBIF_CFG_DEV0_EPF0_VF6_1_SLOT_STATUS2_DEFAULT 0x00000000
4142#define smnBIF_CFG_DEV0_EPF0_VF6_1_MSI_CAP_LIST_DEFAULT 0x0000c000
4143#define smnBIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL_DEFAULT 0x00000080
4144#define smnBIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
4145#define smnBIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
4146#define smnBIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_DATA_DEFAULT 0x00000000
4147#define smnBIF_CFG_DEV0_EPF0_VF6_1_MSI_MASK_DEFAULT 0x00000000
4148#define smnBIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_DATA_64_DEFAULT 0x00000000
4149#define smnBIF_CFG_DEV0_EPF0_VF6_1_MSI_MASK_64_DEFAULT 0x00000000
4150#define smnBIF_CFG_DEV0_EPF0_VF6_1_MSI_PENDING_DEFAULT 0x00000000
4151#define smnBIF_CFG_DEV0_EPF0_VF6_1_MSI_PENDING_64_DEFAULT 0x00000000
4152#define smnBIF_CFG_DEV0_EPF0_VF6_1_MSIX_CAP_LIST_DEFAULT 0x00000000
4153#define smnBIF_CFG_DEV0_EPF0_VF6_1_MSIX_MSG_CNTL_DEFAULT 0x00000000
4154#define smnBIF_CFG_DEV0_EPF0_VF6_1_MSIX_TABLE_DEFAULT 0x00000000
4155#define smnBIF_CFG_DEV0_EPF0_VF6_1_MSIX_PBA_DEFAULT 0x00000000
4156#define smnBIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
4157#define smnBIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
4158#define smnBIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
4159#define smnBIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
4160#define smnBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
4161#define smnBIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
4162#define smnBIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
4163#define smnBIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
4164#define smnBIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
4165#define smnBIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000
4166#define smnBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
4167#define smnBIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG0_DEFAULT 0x00000000
4168#define smnBIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG1_DEFAULT 0x00000000
4169#define smnBIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG2_DEFAULT 0x00000000
4170#define smnBIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG3_DEFAULT 0x00000000
4171#define smnBIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
4172#define smnBIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
4173#define smnBIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
4174#define smnBIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
4175#define smnBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
4176#define smnBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_CAP_DEFAULT 0x00000000
4177#define smnBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_CNTL_DEFAULT 0x00000000
4178#define smnBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000
4179#define smnBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CAP_DEFAULT 0x00000000
4180#define smnBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CNTL_DEFAULT 0x00000000
4181
4182
4183// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf7_bifcfgdecp
4184#define smnBIF_CFG_DEV0_EPF0_VF7_1_VENDOR_ID_DEFAULT 0x00000000
4185#define smnBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_ID_DEFAULT 0x00000000
4186#define smnBIF_CFG_DEV0_EPF0_VF7_1_COMMAND_DEFAULT 0x00000000
4187#define smnBIF_CFG_DEV0_EPF0_VF7_1_STATUS_DEFAULT 0x00000000
4188#define smnBIF_CFG_DEV0_EPF0_VF7_1_REVISION_ID_DEFAULT 0x00000000
4189#define smnBIF_CFG_DEV0_EPF0_VF7_1_PROG_INTERFACE_DEFAULT 0x00000000
4190#define smnBIF_CFG_DEV0_EPF0_VF7_1_SUB_CLASS_DEFAULT 0x00000000
4191#define smnBIF_CFG_DEV0_EPF0_VF7_1_BASE_CLASS_DEFAULT 0x00000000
4192#define smnBIF_CFG_DEV0_EPF0_VF7_1_CACHE_LINE_DEFAULT 0x00000000
4193#define smnBIF_CFG_DEV0_EPF0_VF7_1_LATENCY_DEFAULT 0x00000000
4194#define smnBIF_CFG_DEV0_EPF0_VF7_1_HEADER_DEFAULT 0x00000000
4195#define smnBIF_CFG_DEV0_EPF0_VF7_1_BIST_DEFAULT 0x00000000
4196#define smnBIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_1_DEFAULT 0x00000000
4197#define smnBIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_2_DEFAULT 0x00000000
4198#define smnBIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_3_DEFAULT 0x00000000
4199#define smnBIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_4_DEFAULT 0x00000000
4200#define smnBIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_5_DEFAULT 0x00000000
4201#define smnBIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_6_DEFAULT 0x00000000
4202#define smnBIF_CFG_DEV0_EPF0_VF7_1_ADAPTER_ID_DEFAULT 0x00000000
4203#define smnBIF_CFG_DEV0_EPF0_VF7_1_ROM_BASE_ADDR_DEFAULT 0x00000000
4204#define smnBIF_CFG_DEV0_EPF0_VF7_1_CAP_PTR_DEFAULT 0x00000000
4205#define smnBIF_CFG_DEV0_EPF0_VF7_1_INTERRUPT_LINE_DEFAULT 0x000000ff
4206#define smnBIF_CFG_DEV0_EPF0_VF7_1_INTERRUPT_PIN_DEFAULT 0x00000000
4207#define smnBIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP_LIST_DEFAULT 0x0000a000
4208#define smnBIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP_DEFAULT 0x00000002
4209#define smnBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP_DEFAULT 0x10000000
4210#define smnBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL_DEFAULT 0x00002810
4211#define smnBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS_DEFAULT 0x00000000
4212#define smnBIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP_DEFAULT 0x00011c03
4213#define smnBIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL_DEFAULT 0x00000000
4214#define smnBIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS_DEFAULT 0x00000001
4215#define smnBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2_DEFAULT 0x00000000
4216#define smnBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2_DEFAULT 0x00000000
4217#define smnBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS2_DEFAULT 0x00000000
4218#define smnBIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2_DEFAULT 0x0000000e
4219#define smnBIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2_DEFAULT 0x00000003
4220#define smnBIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2_DEFAULT 0x00000000
4221#define smnBIF_CFG_DEV0_EPF0_VF7_1_SLOT_CAP2_DEFAULT 0x00000000
4222#define smnBIF_CFG_DEV0_EPF0_VF7_1_SLOT_CNTL2_DEFAULT 0x00000000
4223#define smnBIF_CFG_DEV0_EPF0_VF7_1_SLOT_STATUS2_DEFAULT 0x00000000
4224#define smnBIF_CFG_DEV0_EPF0_VF7_1_MSI_CAP_LIST_DEFAULT 0x0000c000
4225#define smnBIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL_DEFAULT 0x00000080
4226#define smnBIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
4227#define smnBIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
4228#define smnBIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_DATA_DEFAULT 0x00000000
4229#define smnBIF_CFG_DEV0_EPF0_VF7_1_MSI_MASK_DEFAULT 0x00000000
4230#define smnBIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_DATA_64_DEFAULT 0x00000000
4231#define smnBIF_CFG_DEV0_EPF0_VF7_1_MSI_MASK_64_DEFAULT 0x00000000
4232#define smnBIF_CFG_DEV0_EPF0_VF7_1_MSI_PENDING_DEFAULT 0x00000000
4233#define smnBIF_CFG_DEV0_EPF0_VF7_1_MSI_PENDING_64_DEFAULT 0x00000000
4234#define smnBIF_CFG_DEV0_EPF0_VF7_1_MSIX_CAP_LIST_DEFAULT 0x00000000
4235#define smnBIF_CFG_DEV0_EPF0_VF7_1_MSIX_MSG_CNTL_DEFAULT 0x00000000
4236#define smnBIF_CFG_DEV0_EPF0_VF7_1_MSIX_TABLE_DEFAULT 0x00000000
4237#define smnBIF_CFG_DEV0_EPF0_VF7_1_MSIX_PBA_DEFAULT 0x00000000
4238#define smnBIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
4239#define smnBIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
4240#define smnBIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
4241#define smnBIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
4242#define smnBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
4243#define smnBIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
4244#define smnBIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
4245#define smnBIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
4246#define smnBIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
4247#define smnBIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000
4248#define smnBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
4249#define smnBIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG0_DEFAULT 0x00000000
4250#define smnBIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG1_DEFAULT 0x00000000
4251#define smnBIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG2_DEFAULT 0x00000000
4252#define smnBIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG3_DEFAULT 0x00000000
4253#define smnBIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
4254#define smnBIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
4255#define smnBIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
4256#define smnBIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
4257#define smnBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
4258#define smnBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_CAP_DEFAULT 0x00000000
4259#define smnBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_CNTL_DEFAULT 0x00000000
4260#define smnBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000
4261#define smnBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CAP_DEFAULT 0x00000000
4262#define smnBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CNTL_DEFAULT 0x00000000
4263
4264
4265// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf8_bifcfgdecp
4266#define smnBIF_CFG_DEV0_EPF0_VF8_1_VENDOR_ID_DEFAULT 0x00000000
4267#define smnBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_ID_DEFAULT 0x00000000
4268#define smnBIF_CFG_DEV0_EPF0_VF8_1_COMMAND_DEFAULT 0x00000000
4269#define smnBIF_CFG_DEV0_EPF0_VF8_1_STATUS_DEFAULT 0x00000000
4270#define smnBIF_CFG_DEV0_EPF0_VF8_1_REVISION_ID_DEFAULT 0x00000000
4271#define smnBIF_CFG_DEV0_EPF0_VF8_1_PROG_INTERFACE_DEFAULT 0x00000000
4272#define smnBIF_CFG_DEV0_EPF0_VF8_1_SUB_CLASS_DEFAULT 0x00000000
4273#define smnBIF_CFG_DEV0_EPF0_VF8_1_BASE_CLASS_DEFAULT 0x00000000
4274#define smnBIF_CFG_DEV0_EPF0_VF8_1_CACHE_LINE_DEFAULT 0x00000000
4275#define smnBIF_CFG_DEV0_EPF0_VF8_1_LATENCY_DEFAULT 0x00000000
4276#define smnBIF_CFG_DEV0_EPF0_VF8_1_HEADER_DEFAULT 0x00000000
4277#define smnBIF_CFG_DEV0_EPF0_VF8_1_BIST_DEFAULT 0x00000000
4278#define smnBIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_1_DEFAULT 0x00000000
4279#define smnBIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_2_DEFAULT 0x00000000
4280#define smnBIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_3_DEFAULT 0x00000000
4281#define smnBIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_4_DEFAULT 0x00000000
4282#define smnBIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_5_DEFAULT 0x00000000
4283#define smnBIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_6_DEFAULT 0x00000000
4284#define smnBIF_CFG_DEV0_EPF0_VF8_1_ADAPTER_ID_DEFAULT 0x00000000
4285#define smnBIF_CFG_DEV0_EPF0_VF8_1_ROM_BASE_ADDR_DEFAULT 0x00000000
4286#define smnBIF_CFG_DEV0_EPF0_VF8_1_CAP_PTR_DEFAULT 0x00000000
4287#define smnBIF_CFG_DEV0_EPF0_VF8_1_INTERRUPT_LINE_DEFAULT 0x000000ff
4288#define smnBIF_CFG_DEV0_EPF0_VF8_1_INTERRUPT_PIN_DEFAULT 0x00000000
4289#define smnBIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP_LIST_DEFAULT 0x0000a000
4290#define smnBIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP_DEFAULT 0x00000002
4291#define smnBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP_DEFAULT 0x10000000
4292#define smnBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL_DEFAULT 0x00002810
4293#define smnBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS_DEFAULT 0x00000000
4294#define smnBIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP_DEFAULT 0x00011c03
4295#define smnBIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL_DEFAULT 0x00000000
4296#define smnBIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS_DEFAULT 0x00000001
4297#define smnBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2_DEFAULT 0x00000000
4298#define smnBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2_DEFAULT 0x00000000
4299#define smnBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS2_DEFAULT 0x00000000
4300#define smnBIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2_DEFAULT 0x0000000e
4301#define smnBIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2_DEFAULT 0x00000003
4302#define smnBIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2_DEFAULT 0x00000000
4303#define smnBIF_CFG_DEV0_EPF0_VF8_1_SLOT_CAP2_DEFAULT 0x00000000
4304#define smnBIF_CFG_DEV0_EPF0_VF8_1_SLOT_CNTL2_DEFAULT 0x00000000
4305#define smnBIF_CFG_DEV0_EPF0_VF8_1_SLOT_STATUS2_DEFAULT 0x00000000
4306#define smnBIF_CFG_DEV0_EPF0_VF8_1_MSI_CAP_LIST_DEFAULT 0x0000c000
4307#define smnBIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL_DEFAULT 0x00000080
4308#define smnBIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
4309#define smnBIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
4310#define smnBIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_DATA_DEFAULT 0x00000000
4311#define smnBIF_CFG_DEV0_EPF0_VF8_1_MSI_MASK_DEFAULT 0x00000000
4312#define smnBIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_DATA_64_DEFAULT 0x00000000
4313#define smnBIF_CFG_DEV0_EPF0_VF8_1_MSI_MASK_64_DEFAULT 0x00000000
4314#define smnBIF_CFG_DEV0_EPF0_VF8_1_MSI_PENDING_DEFAULT 0x00000000
4315#define smnBIF_CFG_DEV0_EPF0_VF8_1_MSI_PENDING_64_DEFAULT 0x00000000
4316#define smnBIF_CFG_DEV0_EPF0_VF8_1_MSIX_CAP_LIST_DEFAULT 0x00000000
4317#define smnBIF_CFG_DEV0_EPF0_VF8_1_MSIX_MSG_CNTL_DEFAULT 0x00000000
4318#define smnBIF_CFG_DEV0_EPF0_VF8_1_MSIX_TABLE_DEFAULT 0x00000000
4319#define smnBIF_CFG_DEV0_EPF0_VF8_1_MSIX_PBA_DEFAULT 0x00000000
4320#define smnBIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
4321#define smnBIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
4322#define smnBIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
4323#define smnBIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
4324#define smnBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
4325#define smnBIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
4326#define smnBIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
4327#define smnBIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
4328#define smnBIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
4329#define smnBIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000
4330#define smnBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
4331#define smnBIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG0_DEFAULT 0x00000000
4332#define smnBIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG1_DEFAULT 0x00000000
4333#define smnBIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG2_DEFAULT 0x00000000
4334#define smnBIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG3_DEFAULT 0x00000000
4335#define smnBIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
4336#define smnBIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
4337#define smnBIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
4338#define smnBIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
4339#define smnBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
4340#define smnBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_CAP_DEFAULT 0x00000000
4341#define smnBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_CNTL_DEFAULT 0x00000000
4342#define smnBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000
4343#define smnBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CAP_DEFAULT 0x00000000
4344#define smnBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CNTL_DEFAULT 0x00000000
4345
4346
4347// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf9_bifcfgdecp
4348#define smnBIF_CFG_DEV0_EPF0_VF9_1_VENDOR_ID_DEFAULT 0x00000000
4349#define smnBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_ID_DEFAULT 0x00000000
4350#define smnBIF_CFG_DEV0_EPF0_VF9_1_COMMAND_DEFAULT 0x00000000
4351#define smnBIF_CFG_DEV0_EPF0_VF9_1_STATUS_DEFAULT 0x00000000
4352#define smnBIF_CFG_DEV0_EPF0_VF9_1_REVISION_ID_DEFAULT 0x00000000
4353#define smnBIF_CFG_DEV0_EPF0_VF9_1_PROG_INTERFACE_DEFAULT 0x00000000
4354#define smnBIF_CFG_DEV0_EPF0_VF9_1_SUB_CLASS_DEFAULT 0x00000000
4355#define smnBIF_CFG_DEV0_EPF0_VF9_1_BASE_CLASS_DEFAULT 0x00000000
4356#define smnBIF_CFG_DEV0_EPF0_VF9_1_CACHE_LINE_DEFAULT 0x00000000
4357#define smnBIF_CFG_DEV0_EPF0_VF9_1_LATENCY_DEFAULT 0x00000000
4358#define smnBIF_CFG_DEV0_EPF0_VF9_1_HEADER_DEFAULT 0x00000000
4359#define smnBIF_CFG_DEV0_EPF0_VF9_1_BIST_DEFAULT 0x00000000
4360#define smnBIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_1_DEFAULT 0x00000000
4361#define smnBIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_2_DEFAULT 0x00000000
4362#define smnBIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_3_DEFAULT 0x00000000
4363#define smnBIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_4_DEFAULT 0x00000000
4364#define smnBIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_5_DEFAULT 0x00000000
4365#define smnBIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_6_DEFAULT 0x00000000
4366#define smnBIF_CFG_DEV0_EPF0_VF9_1_ADAPTER_ID_DEFAULT 0x00000000
4367#define smnBIF_CFG_DEV0_EPF0_VF9_1_ROM_BASE_ADDR_DEFAULT 0x00000000
4368#define smnBIF_CFG_DEV0_EPF0_VF9_1_CAP_PTR_DEFAULT 0x00000000
4369#define smnBIF_CFG_DEV0_EPF0_VF9_1_INTERRUPT_LINE_DEFAULT 0x000000ff
4370#define smnBIF_CFG_DEV0_EPF0_VF9_1_INTERRUPT_PIN_DEFAULT 0x00000000
4371#define smnBIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP_LIST_DEFAULT 0x0000a000
4372#define smnBIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP_DEFAULT 0x00000002
4373#define smnBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP_DEFAULT 0x10000000
4374#define smnBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL_DEFAULT 0x00002810
4375#define smnBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS_DEFAULT 0x00000000
4376#define smnBIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP_DEFAULT 0x00011c03
4377#define smnBIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL_DEFAULT 0x00000000
4378#define smnBIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS_DEFAULT 0x00000001
4379#define smnBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2_DEFAULT 0x00000000
4380#define smnBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2_DEFAULT 0x00000000
4381#define smnBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS2_DEFAULT 0x00000000
4382#define smnBIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2_DEFAULT 0x0000000e
4383#define smnBIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2_DEFAULT 0x00000003
4384#define smnBIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2_DEFAULT 0x00000000
4385#define smnBIF_CFG_DEV0_EPF0_VF9_1_SLOT_CAP2_DEFAULT 0x00000000
4386#define smnBIF_CFG_DEV0_EPF0_VF9_1_SLOT_CNTL2_DEFAULT 0x00000000
4387#define smnBIF_CFG_DEV0_EPF0_VF9_1_SLOT_STATUS2_DEFAULT 0x00000000
4388#define smnBIF_CFG_DEV0_EPF0_VF9_1_MSI_CAP_LIST_DEFAULT 0x0000c000
4389#define smnBIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL_DEFAULT 0x00000080
4390#define smnBIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
4391#define smnBIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
4392#define smnBIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_DATA_DEFAULT 0x00000000
4393#define smnBIF_CFG_DEV0_EPF0_VF9_1_MSI_MASK_DEFAULT 0x00000000
4394#define smnBIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_DATA_64_DEFAULT 0x00000000
4395#define smnBIF_CFG_DEV0_EPF0_VF9_1_MSI_MASK_64_DEFAULT 0x00000000
4396#define smnBIF_CFG_DEV0_EPF0_VF9_1_MSI_PENDING_DEFAULT 0x00000000
4397#define smnBIF_CFG_DEV0_EPF0_VF9_1_MSI_PENDING_64_DEFAULT 0x00000000
4398#define smnBIF_CFG_DEV0_EPF0_VF9_1_MSIX_CAP_LIST_DEFAULT 0x00000000
4399#define smnBIF_CFG_DEV0_EPF0_VF9_1_MSIX_MSG_CNTL_DEFAULT 0x00000000
4400#define smnBIF_CFG_DEV0_EPF0_VF9_1_MSIX_TABLE_DEFAULT 0x00000000
4401#define smnBIF_CFG_DEV0_EPF0_VF9_1_MSIX_PBA_DEFAULT 0x00000000
4402#define smnBIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
4403#define smnBIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
4404#define smnBIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
4405#define smnBIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
4406#define smnBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
4407#define smnBIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
4408#define smnBIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
4409#define smnBIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
4410#define smnBIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
4411#define smnBIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000
4412#define smnBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
4413#define smnBIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG0_DEFAULT 0x00000000
4414#define smnBIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG1_DEFAULT 0x00000000
4415#define smnBIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG2_DEFAULT 0x00000000
4416#define smnBIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG3_DEFAULT 0x00000000
4417#define smnBIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
4418#define smnBIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
4419#define smnBIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
4420#define smnBIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
4421#define smnBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
4422#define smnBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_CAP_DEFAULT 0x00000000
4423#define smnBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_CNTL_DEFAULT 0x00000000
4424#define smnBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000
4425#define smnBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CAP_DEFAULT 0x00000000
4426#define smnBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CNTL_DEFAULT 0x00000000
4427
4428
4429// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf10_bifcfgdecp
4430#define smnBIF_CFG_DEV0_EPF0_VF10_1_VENDOR_ID_DEFAULT 0x00000000
4431#define smnBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_ID_DEFAULT 0x00000000
4432#define smnBIF_CFG_DEV0_EPF0_VF10_1_COMMAND_DEFAULT 0x00000000
4433#define smnBIF_CFG_DEV0_EPF0_VF10_1_STATUS_DEFAULT 0x00000000
4434#define smnBIF_CFG_DEV0_EPF0_VF10_1_REVISION_ID_DEFAULT 0x00000000
4435#define smnBIF_CFG_DEV0_EPF0_VF10_1_PROG_INTERFACE_DEFAULT 0x00000000
4436#define smnBIF_CFG_DEV0_EPF0_VF10_1_SUB_CLASS_DEFAULT 0x00000000
4437#define smnBIF_CFG_DEV0_EPF0_VF10_1_BASE_CLASS_DEFAULT 0x00000000
4438#define smnBIF_CFG_DEV0_EPF0_VF10_1_CACHE_LINE_DEFAULT 0x00000000
4439#define smnBIF_CFG_DEV0_EPF0_VF10_1_LATENCY_DEFAULT 0x00000000
4440#define smnBIF_CFG_DEV0_EPF0_VF10_1_HEADER_DEFAULT 0x00000000
4441#define smnBIF_CFG_DEV0_EPF0_VF10_1_BIST_DEFAULT 0x00000000
4442#define smnBIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_1_DEFAULT 0x00000000
4443#define smnBIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_2_DEFAULT 0x00000000
4444#define smnBIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_3_DEFAULT 0x00000000
4445#define smnBIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_4_DEFAULT 0x00000000
4446#define smnBIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_5_DEFAULT 0x00000000
4447#define smnBIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_6_DEFAULT 0x00000000
4448#define smnBIF_CFG_DEV0_EPF0_VF10_1_ADAPTER_ID_DEFAULT 0x00000000
4449#define smnBIF_CFG_DEV0_EPF0_VF10_1_ROM_BASE_ADDR_DEFAULT 0x00000000
4450#define smnBIF_CFG_DEV0_EPF0_VF10_1_CAP_PTR_DEFAULT 0x00000000
4451#define smnBIF_CFG_DEV0_EPF0_VF10_1_INTERRUPT_LINE_DEFAULT 0x000000ff
4452#define smnBIF_CFG_DEV0_EPF0_VF10_1_INTERRUPT_PIN_DEFAULT 0x00000000
4453#define smnBIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP_LIST_DEFAULT 0x0000a000
4454#define smnBIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP_DEFAULT 0x00000002
4455#define smnBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP_DEFAULT 0x10000000
4456#define smnBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL_DEFAULT 0x00002810
4457#define smnBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS_DEFAULT 0x00000000
4458#define smnBIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP_DEFAULT 0x00011c03
4459#define smnBIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL_DEFAULT 0x00000000
4460#define smnBIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS_DEFAULT 0x00000001
4461#define smnBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2_DEFAULT 0x00000000
4462#define smnBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2_DEFAULT 0x00000000
4463#define smnBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS2_DEFAULT 0x00000000
4464#define smnBIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2_DEFAULT 0x0000000e
4465#define smnBIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2_DEFAULT 0x00000003
4466#define smnBIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2_DEFAULT 0x00000000
4467#define smnBIF_CFG_DEV0_EPF0_VF10_1_SLOT_CAP2_DEFAULT 0x00000000
4468#define smnBIF_CFG_DEV0_EPF0_VF10_1_SLOT_CNTL2_DEFAULT 0x00000000
4469#define smnBIF_CFG_DEV0_EPF0_VF10_1_SLOT_STATUS2_DEFAULT 0x00000000
4470#define smnBIF_CFG_DEV0_EPF0_VF10_1_MSI_CAP_LIST_DEFAULT 0x0000c000
4471#define smnBIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL_DEFAULT 0x00000080
4472#define smnBIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
4473#define smnBIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
4474#define smnBIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_DATA_DEFAULT 0x00000000
4475#define smnBIF_CFG_DEV0_EPF0_VF10_1_MSI_MASK_DEFAULT 0x00000000
4476#define smnBIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_DATA_64_DEFAULT 0x00000000
4477#define smnBIF_CFG_DEV0_EPF0_VF10_1_MSI_MASK_64_DEFAULT 0x00000000
4478#define smnBIF_CFG_DEV0_EPF0_VF10_1_MSI_PENDING_DEFAULT 0x00000000
4479#define smnBIF_CFG_DEV0_EPF0_VF10_1_MSI_PENDING_64_DEFAULT 0x00000000
4480#define smnBIF_CFG_DEV0_EPF0_VF10_1_MSIX_CAP_LIST_DEFAULT 0x00000000
4481#define smnBIF_CFG_DEV0_EPF0_VF10_1_MSIX_MSG_CNTL_DEFAULT 0x00000000
4482#define smnBIF_CFG_DEV0_EPF0_VF10_1_MSIX_TABLE_DEFAULT 0x00000000
4483#define smnBIF_CFG_DEV0_EPF0_VF10_1_MSIX_PBA_DEFAULT 0x00000000
4484#define smnBIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
4485#define smnBIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
4486#define smnBIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
4487#define smnBIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
4488#define smnBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
4489#define smnBIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
4490#define smnBIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
4491#define smnBIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
4492#define smnBIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
4493#define smnBIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000
4494#define smnBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
4495#define smnBIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG0_DEFAULT 0x00000000
4496#define smnBIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG1_DEFAULT 0x00000000
4497#define smnBIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG2_DEFAULT 0x00000000
4498#define smnBIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG3_DEFAULT 0x00000000
4499#define smnBIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
4500#define smnBIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
4501#define smnBIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
4502#define smnBIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
4503#define smnBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
4504#define smnBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_CAP_DEFAULT 0x00000000
4505#define smnBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_CNTL_DEFAULT 0x00000000
4506#define smnBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000
4507#define smnBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CAP_DEFAULT 0x00000000
4508#define smnBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CNTL_DEFAULT 0x00000000
4509
4510
4511// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf11_bifcfgdecp
4512#define smnBIF_CFG_DEV0_EPF0_VF11_1_VENDOR_ID_DEFAULT 0x00000000
4513#define smnBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_ID_DEFAULT 0x00000000
4514#define smnBIF_CFG_DEV0_EPF0_VF11_1_COMMAND_DEFAULT 0x00000000
4515#define smnBIF_CFG_DEV0_EPF0_VF11_1_STATUS_DEFAULT 0x00000000
4516#define smnBIF_CFG_DEV0_EPF0_VF11_1_REVISION_ID_DEFAULT 0x00000000
4517#define smnBIF_CFG_DEV0_EPF0_VF11_1_PROG_INTERFACE_DEFAULT 0x00000000
4518#define smnBIF_CFG_DEV0_EPF0_VF11_1_SUB_CLASS_DEFAULT 0x00000000
4519#define smnBIF_CFG_DEV0_EPF0_VF11_1_BASE_CLASS_DEFAULT 0x00000000
4520#define smnBIF_CFG_DEV0_EPF0_VF11_1_CACHE_LINE_DEFAULT 0x00000000
4521#define smnBIF_CFG_DEV0_EPF0_VF11_1_LATENCY_DEFAULT 0x00000000
4522#define smnBIF_CFG_DEV0_EPF0_VF11_1_HEADER_DEFAULT 0x00000000
4523#define smnBIF_CFG_DEV0_EPF0_VF11_1_BIST_DEFAULT 0x00000000
4524#define smnBIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_1_DEFAULT 0x00000000
4525#define smnBIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_2_DEFAULT 0x00000000
4526#define smnBIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_3_DEFAULT 0x00000000
4527#define smnBIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_4_DEFAULT 0x00000000
4528#define smnBIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_5_DEFAULT 0x00000000
4529#define smnBIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_6_DEFAULT 0x00000000
4530#define smnBIF_CFG_DEV0_EPF0_VF11_1_ADAPTER_ID_DEFAULT 0x00000000
4531#define smnBIF_CFG_DEV0_EPF0_VF11_1_ROM_BASE_ADDR_DEFAULT 0x00000000
4532#define smnBIF_CFG_DEV0_EPF0_VF11_1_CAP_PTR_DEFAULT 0x00000000
4533#define smnBIF_CFG_DEV0_EPF0_VF11_1_INTERRUPT_LINE_DEFAULT 0x000000ff
4534#define smnBIF_CFG_DEV0_EPF0_VF11_1_INTERRUPT_PIN_DEFAULT 0x00000000
4535#define smnBIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP_LIST_DEFAULT 0x0000a000
4536#define smnBIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP_DEFAULT 0x00000002
4537#define smnBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP_DEFAULT 0x10000000
4538#define smnBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL_DEFAULT 0x00002810
4539#define smnBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS_DEFAULT 0x00000000
4540#define smnBIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP_DEFAULT 0x00011c03
4541#define smnBIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL_DEFAULT 0x00000000
4542#define smnBIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS_DEFAULT 0x00000001
4543#define smnBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2_DEFAULT 0x00000000
4544#define smnBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2_DEFAULT 0x00000000
4545#define smnBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS2_DEFAULT 0x00000000
4546#define smnBIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2_DEFAULT 0x0000000e
4547#define smnBIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2_DEFAULT 0x00000003
4548#define smnBIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2_DEFAULT 0x00000000
4549#define smnBIF_CFG_DEV0_EPF0_VF11_1_SLOT_CAP2_DEFAULT 0x00000000
4550#define smnBIF_CFG_DEV0_EPF0_VF11_1_SLOT_CNTL2_DEFAULT 0x00000000
4551#define smnBIF_CFG_DEV0_EPF0_VF11_1_SLOT_STATUS2_DEFAULT 0x00000000
4552#define smnBIF_CFG_DEV0_EPF0_VF11_1_MSI_CAP_LIST_DEFAULT 0x0000c000
4553#define smnBIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL_DEFAULT 0x00000080
4554#define smnBIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
4555#define smnBIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
4556#define smnBIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_DATA_DEFAULT 0x00000000
4557#define smnBIF_CFG_DEV0_EPF0_VF11_1_MSI_MASK_DEFAULT 0x00000000
4558#define smnBIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_DATA_64_DEFAULT 0x00000000
4559#define smnBIF_CFG_DEV0_EPF0_VF11_1_MSI_MASK_64_DEFAULT 0x00000000
4560#define smnBIF_CFG_DEV0_EPF0_VF11_1_MSI_PENDING_DEFAULT 0x00000000
4561#define smnBIF_CFG_DEV0_EPF0_VF11_1_MSI_PENDING_64_DEFAULT 0x00000000
4562#define smnBIF_CFG_DEV0_EPF0_VF11_1_MSIX_CAP_LIST_DEFAULT 0x00000000
4563#define smnBIF_CFG_DEV0_EPF0_VF11_1_MSIX_MSG_CNTL_DEFAULT 0x00000000
4564#define smnBIF_CFG_DEV0_EPF0_VF11_1_MSIX_TABLE_DEFAULT 0x00000000
4565#define smnBIF_CFG_DEV0_EPF0_VF11_1_MSIX_PBA_DEFAULT 0x00000000
4566#define smnBIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
4567#define smnBIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
4568#define smnBIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
4569#define smnBIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
4570#define smnBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
4571#define smnBIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
4572#define smnBIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
4573#define smnBIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
4574#define smnBIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
4575#define smnBIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000
4576#define smnBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
4577#define smnBIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG0_DEFAULT 0x00000000
4578#define smnBIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG1_DEFAULT 0x00000000
4579#define smnBIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG2_DEFAULT 0x00000000
4580#define smnBIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG3_DEFAULT 0x00000000
4581#define smnBIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
4582#define smnBIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
4583#define smnBIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
4584#define smnBIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
4585#define smnBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
4586#define smnBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_CAP_DEFAULT 0x00000000
4587#define smnBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_CNTL_DEFAULT 0x00000000
4588#define smnBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000
4589#define smnBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CAP_DEFAULT 0x00000000
4590#define smnBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CNTL_DEFAULT 0x00000000
4591
4592
4593// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf12_bifcfgdecp
4594#define smnBIF_CFG_DEV0_EPF0_VF12_1_VENDOR_ID_DEFAULT 0x00000000
4595#define smnBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_ID_DEFAULT 0x00000000
4596#define smnBIF_CFG_DEV0_EPF0_VF12_1_COMMAND_DEFAULT 0x00000000
4597#define smnBIF_CFG_DEV0_EPF0_VF12_1_STATUS_DEFAULT 0x00000000
4598#define smnBIF_CFG_DEV0_EPF0_VF12_1_REVISION_ID_DEFAULT 0x00000000
4599#define smnBIF_CFG_DEV0_EPF0_VF12_1_PROG_INTERFACE_DEFAULT 0x00000000
4600#define smnBIF_CFG_DEV0_EPF0_VF12_1_SUB_CLASS_DEFAULT 0x00000000
4601#define smnBIF_CFG_DEV0_EPF0_VF12_1_BASE_CLASS_DEFAULT 0x00000000
4602#define smnBIF_CFG_DEV0_EPF0_VF12_1_CACHE_LINE_DEFAULT 0x00000000
4603#define smnBIF_CFG_DEV0_EPF0_VF12_1_LATENCY_DEFAULT 0x00000000
4604#define smnBIF_CFG_DEV0_EPF0_VF12_1_HEADER_DEFAULT 0x00000000
4605#define smnBIF_CFG_DEV0_EPF0_VF12_1_BIST_DEFAULT 0x00000000
4606#define smnBIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_1_DEFAULT 0x00000000
4607#define smnBIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_2_DEFAULT 0x00000000
4608#define smnBIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_3_DEFAULT 0x00000000
4609#define smnBIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_4_DEFAULT 0x00000000
4610#define smnBIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_5_DEFAULT 0x00000000
4611#define smnBIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_6_DEFAULT 0x00000000
4612#define smnBIF_CFG_DEV0_EPF0_VF12_1_ADAPTER_ID_DEFAULT 0x00000000
4613#define smnBIF_CFG_DEV0_EPF0_VF12_1_ROM_BASE_ADDR_DEFAULT 0x00000000
4614#define smnBIF_CFG_DEV0_EPF0_VF12_1_CAP_PTR_DEFAULT 0x00000000
4615#define smnBIF_CFG_DEV0_EPF0_VF12_1_INTERRUPT_LINE_DEFAULT 0x000000ff
4616#define smnBIF_CFG_DEV0_EPF0_VF12_1_INTERRUPT_PIN_DEFAULT 0x00000000
4617#define smnBIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP_LIST_DEFAULT 0x0000a000
4618#define smnBIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP_DEFAULT 0x00000002
4619#define smnBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP_DEFAULT 0x10000000
4620#define smnBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL_DEFAULT 0x00002810
4621#define smnBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS_DEFAULT 0x00000000
4622#define smnBIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP_DEFAULT 0x00011c03
4623#define smnBIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL_DEFAULT 0x00000000
4624#define smnBIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS_DEFAULT 0x00000001
4625#define smnBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2_DEFAULT 0x00000000
4626#define smnBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2_DEFAULT 0x00000000
4627#define smnBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS2_DEFAULT 0x00000000
4628#define smnBIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2_DEFAULT 0x0000000e
4629#define smnBIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2_DEFAULT 0x00000003
4630#define smnBIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2_DEFAULT 0x00000000
4631#define smnBIF_CFG_DEV0_EPF0_VF12_1_SLOT_CAP2_DEFAULT 0x00000000
4632#define smnBIF_CFG_DEV0_EPF0_VF12_1_SLOT_CNTL2_DEFAULT 0x00000000
4633#define smnBIF_CFG_DEV0_EPF0_VF12_1_SLOT_STATUS2_DEFAULT 0x00000000
4634#define smnBIF_CFG_DEV0_EPF0_VF12_1_MSI_CAP_LIST_DEFAULT 0x0000c000
4635#define smnBIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL_DEFAULT 0x00000080
4636#define smnBIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
4637#define smnBIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
4638#define smnBIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_DATA_DEFAULT 0x00000000
4639#define smnBIF_CFG_DEV0_EPF0_VF12_1_MSI_MASK_DEFAULT 0x00000000
4640#define smnBIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_DATA_64_DEFAULT 0x00000000
4641#define smnBIF_CFG_DEV0_EPF0_VF12_1_MSI_MASK_64_DEFAULT 0x00000000
4642#define smnBIF_CFG_DEV0_EPF0_VF12_1_MSI_PENDING_DEFAULT 0x00000000
4643#define smnBIF_CFG_DEV0_EPF0_VF12_1_MSI_PENDING_64_DEFAULT 0x00000000
4644#define smnBIF_CFG_DEV0_EPF0_VF12_1_MSIX_CAP_LIST_DEFAULT 0x00000000
4645#define smnBIF_CFG_DEV0_EPF0_VF12_1_MSIX_MSG_CNTL_DEFAULT 0x00000000
4646#define smnBIF_CFG_DEV0_EPF0_VF12_1_MSIX_TABLE_DEFAULT 0x00000000
4647#define smnBIF_CFG_DEV0_EPF0_VF12_1_MSIX_PBA_DEFAULT 0x00000000
4648#define smnBIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
4649#define smnBIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
4650#define smnBIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
4651#define smnBIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
4652#define smnBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
4653#define smnBIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
4654#define smnBIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
4655#define smnBIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
4656#define smnBIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
4657#define smnBIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000
4658#define smnBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
4659#define smnBIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG0_DEFAULT 0x00000000
4660#define smnBIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG1_DEFAULT 0x00000000
4661#define smnBIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG2_DEFAULT 0x00000000
4662#define smnBIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG3_DEFAULT 0x00000000
4663#define smnBIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
4664#define smnBIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
4665#define smnBIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
4666#define smnBIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
4667#define smnBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
4668#define smnBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_CAP_DEFAULT 0x00000000
4669#define smnBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_CNTL_DEFAULT 0x00000000
4670#define smnBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000
4671#define smnBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CAP_DEFAULT 0x00000000
4672#define smnBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CNTL_DEFAULT 0x00000000
4673
4674
4675// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf13_bifcfgdecp
4676#define smnBIF_CFG_DEV0_EPF0_VF13_1_VENDOR_ID_DEFAULT 0x00000000
4677#define smnBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_ID_DEFAULT 0x00000000
4678#define smnBIF_CFG_DEV0_EPF0_VF13_1_COMMAND_DEFAULT 0x00000000
4679#define smnBIF_CFG_DEV0_EPF0_VF13_1_STATUS_DEFAULT 0x00000000
4680#define smnBIF_CFG_DEV0_EPF0_VF13_1_REVISION_ID_DEFAULT 0x00000000
4681#define smnBIF_CFG_DEV0_EPF0_VF13_1_PROG_INTERFACE_DEFAULT 0x00000000
4682#define smnBIF_CFG_DEV0_EPF0_VF13_1_SUB_CLASS_DEFAULT 0x00000000
4683#define smnBIF_CFG_DEV0_EPF0_VF13_1_BASE_CLASS_DEFAULT 0x00000000
4684#define smnBIF_CFG_DEV0_EPF0_VF13_1_CACHE_LINE_DEFAULT 0x00000000
4685#define smnBIF_CFG_DEV0_EPF0_VF13_1_LATENCY_DEFAULT 0x00000000
4686#define smnBIF_CFG_DEV0_EPF0_VF13_1_HEADER_DEFAULT 0x00000000
4687#define smnBIF_CFG_DEV0_EPF0_VF13_1_BIST_DEFAULT 0x00000000
4688#define smnBIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_1_DEFAULT 0x00000000
4689#define smnBIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_2_DEFAULT 0x00000000
4690#define smnBIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_3_DEFAULT 0x00000000
4691#define smnBIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_4_DEFAULT 0x00000000
4692#define smnBIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_5_DEFAULT 0x00000000
4693#define smnBIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_6_DEFAULT 0x00000000
4694#define smnBIF_CFG_DEV0_EPF0_VF13_1_ADAPTER_ID_DEFAULT 0x00000000
4695#define smnBIF_CFG_DEV0_EPF0_VF13_1_ROM_BASE_ADDR_DEFAULT 0x00000000
4696#define smnBIF_CFG_DEV0_EPF0_VF13_1_CAP_PTR_DEFAULT 0x00000000
4697#define smnBIF_CFG_DEV0_EPF0_VF13_1_INTERRUPT_LINE_DEFAULT 0x000000ff
4698#define smnBIF_CFG_DEV0_EPF0_VF13_1_INTERRUPT_PIN_DEFAULT 0x00000000
4699#define smnBIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP_LIST_DEFAULT 0x0000a000
4700#define smnBIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP_DEFAULT 0x00000002
4701#define smnBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP_DEFAULT 0x10000000
4702#define smnBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL_DEFAULT 0x00002810
4703#define smnBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS_DEFAULT 0x00000000
4704#define smnBIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP_DEFAULT 0x00011c03
4705#define smnBIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL_DEFAULT 0x00000000
4706#define smnBIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS_DEFAULT 0x00000001
4707#define smnBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2_DEFAULT 0x00000000
4708#define smnBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2_DEFAULT 0x00000000
4709#define smnBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS2_DEFAULT 0x00000000
4710#define smnBIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2_DEFAULT 0x0000000e
4711#define smnBIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2_DEFAULT 0x00000003
4712#define smnBIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2_DEFAULT 0x00000000
4713#define smnBIF_CFG_DEV0_EPF0_VF13_1_SLOT_CAP2_DEFAULT 0x00000000
4714#define smnBIF_CFG_DEV0_EPF0_VF13_1_SLOT_CNTL2_DEFAULT 0x00000000
4715#define smnBIF_CFG_DEV0_EPF0_VF13_1_SLOT_STATUS2_DEFAULT 0x00000000
4716#define smnBIF_CFG_DEV0_EPF0_VF13_1_MSI_CAP_LIST_DEFAULT 0x0000c000
4717#define smnBIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL_DEFAULT 0x00000080
4718#define smnBIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
4719#define smnBIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
4720#define smnBIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_DATA_DEFAULT 0x00000000
4721#define smnBIF_CFG_DEV0_EPF0_VF13_1_MSI_MASK_DEFAULT 0x00000000
4722#define smnBIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_DATA_64_DEFAULT 0x00000000
4723#define smnBIF_CFG_DEV0_EPF0_VF13_1_MSI_MASK_64_DEFAULT 0x00000000
4724#define smnBIF_CFG_DEV0_EPF0_VF13_1_MSI_PENDING_DEFAULT 0x00000000
4725#define smnBIF_CFG_DEV0_EPF0_VF13_1_MSI_PENDING_64_DEFAULT 0x00000000
4726#define smnBIF_CFG_DEV0_EPF0_VF13_1_MSIX_CAP_LIST_DEFAULT 0x00000000
4727#define smnBIF_CFG_DEV0_EPF0_VF13_1_MSIX_MSG_CNTL_DEFAULT 0x00000000
4728#define smnBIF_CFG_DEV0_EPF0_VF13_1_MSIX_TABLE_DEFAULT 0x00000000
4729#define smnBIF_CFG_DEV0_EPF0_VF13_1_MSIX_PBA_DEFAULT 0x00000000
4730#define smnBIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
4731#define smnBIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
4732#define smnBIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
4733#define smnBIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
4734#define smnBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
4735#define smnBIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
4736#define smnBIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
4737#define smnBIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
4738#define smnBIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
4739#define smnBIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000
4740#define smnBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
4741#define smnBIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG0_DEFAULT 0x00000000
4742#define smnBIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG1_DEFAULT 0x00000000
4743#define smnBIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG2_DEFAULT 0x00000000
4744#define smnBIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG3_DEFAULT 0x00000000
4745#define smnBIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
4746#define smnBIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
4747#define smnBIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
4748#define smnBIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
4749#define smnBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
4750#define smnBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_CAP_DEFAULT 0x00000000
4751#define smnBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_CNTL_DEFAULT 0x00000000
4752#define smnBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000
4753#define smnBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CAP_DEFAULT 0x00000000
4754#define smnBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CNTL_DEFAULT 0x00000000
4755
4756
4757// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf14_bifcfgdecp
4758#define smnBIF_CFG_DEV0_EPF0_VF14_1_VENDOR_ID_DEFAULT 0x00000000
4759#define smnBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_ID_DEFAULT 0x00000000
4760#define smnBIF_CFG_DEV0_EPF0_VF14_1_COMMAND_DEFAULT 0x00000000
4761#define smnBIF_CFG_DEV0_EPF0_VF14_1_STATUS_DEFAULT 0x00000000
4762#define smnBIF_CFG_DEV0_EPF0_VF14_1_REVISION_ID_DEFAULT 0x00000000
4763#define smnBIF_CFG_DEV0_EPF0_VF14_1_PROG_INTERFACE_DEFAULT 0x00000000
4764#define smnBIF_CFG_DEV0_EPF0_VF14_1_SUB_CLASS_DEFAULT 0x00000000
4765#define smnBIF_CFG_DEV0_EPF0_VF14_1_BASE_CLASS_DEFAULT 0x00000000
4766#define smnBIF_CFG_DEV0_EPF0_VF14_1_CACHE_LINE_DEFAULT 0x00000000
4767#define smnBIF_CFG_DEV0_EPF0_VF14_1_LATENCY_DEFAULT 0x00000000
4768#define smnBIF_CFG_DEV0_EPF0_VF14_1_HEADER_DEFAULT 0x00000000
4769#define smnBIF_CFG_DEV0_EPF0_VF14_1_BIST_DEFAULT 0x00000000
4770#define smnBIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_1_DEFAULT 0x00000000
4771#define smnBIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_2_DEFAULT 0x00000000
4772#define smnBIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_3_DEFAULT 0x00000000
4773#define smnBIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_4_DEFAULT 0x00000000
4774#define smnBIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_5_DEFAULT 0x00000000
4775#define smnBIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_6_DEFAULT 0x00000000
4776#define smnBIF_CFG_DEV0_EPF0_VF14_1_ADAPTER_ID_DEFAULT 0x00000000
4777#define smnBIF_CFG_DEV0_EPF0_VF14_1_ROM_BASE_ADDR_DEFAULT 0x00000000
4778#define smnBIF_CFG_DEV0_EPF0_VF14_1_CAP_PTR_DEFAULT 0x00000000
4779#define smnBIF_CFG_DEV0_EPF0_VF14_1_INTERRUPT_LINE_DEFAULT 0x000000ff
4780#define smnBIF_CFG_DEV0_EPF0_VF14_1_INTERRUPT_PIN_DEFAULT 0x00000000
4781#define smnBIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP_LIST_DEFAULT 0x0000a000
4782#define smnBIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP_DEFAULT 0x00000002
4783#define smnBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP_DEFAULT 0x10000000
4784#define smnBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL_DEFAULT 0x00002810
4785#define smnBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS_DEFAULT 0x00000000
4786#define smnBIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP_DEFAULT 0x00011c03
4787#define smnBIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL_DEFAULT 0x00000000
4788#define smnBIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS_DEFAULT 0x00000001
4789#define smnBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2_DEFAULT 0x00000000
4790#define smnBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2_DEFAULT 0x00000000
4791#define smnBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS2_DEFAULT 0x00000000
4792#define smnBIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2_DEFAULT 0x0000000e
4793#define smnBIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2_DEFAULT 0x00000003
4794#define smnBIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2_DEFAULT 0x00000000
4795#define smnBIF_CFG_DEV0_EPF0_VF14_1_SLOT_CAP2_DEFAULT 0x00000000
4796#define smnBIF_CFG_DEV0_EPF0_VF14_1_SLOT_CNTL2_DEFAULT 0x00000000
4797#define smnBIF_CFG_DEV0_EPF0_VF14_1_SLOT_STATUS2_DEFAULT 0x00000000
4798#define smnBIF_CFG_DEV0_EPF0_VF14_1_MSI_CAP_LIST_DEFAULT 0x0000c000
4799#define smnBIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL_DEFAULT 0x00000080
4800#define smnBIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
4801#define smnBIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
4802#define smnBIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_DATA_DEFAULT 0x00000000
4803#define smnBIF_CFG_DEV0_EPF0_VF14_1_MSI_MASK_DEFAULT 0x00000000
4804#define smnBIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_DATA_64_DEFAULT 0x00000000
4805#define smnBIF_CFG_DEV0_EPF0_VF14_1_MSI_MASK_64_DEFAULT 0x00000000
4806#define smnBIF_CFG_DEV0_EPF0_VF14_1_MSI_PENDING_DEFAULT 0x00000000
4807#define smnBIF_CFG_DEV0_EPF0_VF14_1_MSI_PENDING_64_DEFAULT 0x00000000
4808#define smnBIF_CFG_DEV0_EPF0_VF14_1_MSIX_CAP_LIST_DEFAULT 0x00000000
4809#define smnBIF_CFG_DEV0_EPF0_VF14_1_MSIX_MSG_CNTL_DEFAULT 0x00000000
4810#define smnBIF_CFG_DEV0_EPF0_VF14_1_MSIX_TABLE_DEFAULT 0x00000000
4811#define smnBIF_CFG_DEV0_EPF0_VF14_1_MSIX_PBA_DEFAULT 0x00000000
4812#define smnBIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
4813#define smnBIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
4814#define smnBIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
4815#define smnBIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
4816#define smnBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
4817#define smnBIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
4818#define smnBIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
4819#define smnBIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
4820#define smnBIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
4821#define smnBIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000
4822#define smnBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
4823#define smnBIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG0_DEFAULT 0x00000000
4824#define smnBIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG1_DEFAULT 0x00000000
4825#define smnBIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG2_DEFAULT 0x00000000
4826#define smnBIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG3_DEFAULT 0x00000000
4827#define smnBIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
4828#define smnBIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
4829#define smnBIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
4830#define smnBIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
4831#define smnBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
4832#define smnBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_CAP_DEFAULT 0x00000000
4833#define smnBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_CNTL_DEFAULT 0x00000000
4834#define smnBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000
4835#define smnBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CAP_DEFAULT 0x00000000
4836#define smnBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CNTL_DEFAULT 0x00000000
4837
4838
4839// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf15_bifcfgdecp
4840#define smnBIF_CFG_DEV0_EPF0_VF15_1_VENDOR_ID_DEFAULT 0x00000000
4841#define smnBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_ID_DEFAULT 0x00000000
4842#define smnBIF_CFG_DEV0_EPF0_VF15_1_COMMAND_DEFAULT 0x00000000
4843#define smnBIF_CFG_DEV0_EPF0_VF15_1_STATUS_DEFAULT 0x00000000
4844#define smnBIF_CFG_DEV0_EPF0_VF15_1_REVISION_ID_DEFAULT 0x00000000
4845#define smnBIF_CFG_DEV0_EPF0_VF15_1_PROG_INTERFACE_DEFAULT 0x00000000
4846#define smnBIF_CFG_DEV0_EPF0_VF15_1_SUB_CLASS_DEFAULT 0x00000000
4847#define smnBIF_CFG_DEV0_EPF0_VF15_1_BASE_CLASS_DEFAULT 0x00000000
4848#define smnBIF_CFG_DEV0_EPF0_VF15_1_CACHE_LINE_DEFAULT 0x00000000
4849#define smnBIF_CFG_DEV0_EPF0_VF15_1_LATENCY_DEFAULT 0x00000000
4850#define smnBIF_CFG_DEV0_EPF0_VF15_1_HEADER_DEFAULT 0x00000000
4851#define smnBIF_CFG_DEV0_EPF0_VF15_1_BIST_DEFAULT 0x00000000
4852#define smnBIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_1_DEFAULT 0x00000000
4853#define smnBIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_2_DEFAULT 0x00000000
4854#define smnBIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_3_DEFAULT 0x00000000
4855#define smnBIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_4_DEFAULT 0x00000000
4856#define smnBIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_5_DEFAULT 0x00000000
4857#define smnBIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_6_DEFAULT 0x00000000
4858#define smnBIF_CFG_DEV0_EPF0_VF15_1_ADAPTER_ID_DEFAULT 0x00000000
4859#define smnBIF_CFG_DEV0_EPF0_VF15_1_ROM_BASE_ADDR_DEFAULT 0x00000000
4860#define smnBIF_CFG_DEV0_EPF0_VF15_1_CAP_PTR_DEFAULT 0x00000000
4861#define smnBIF_CFG_DEV0_EPF0_VF15_1_INTERRUPT_LINE_DEFAULT 0x000000ff
4862#define smnBIF_CFG_DEV0_EPF0_VF15_1_INTERRUPT_PIN_DEFAULT 0x00000000
4863#define smnBIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP_LIST_DEFAULT 0x0000a000
4864#define smnBIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP_DEFAULT 0x00000002
4865#define smnBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP_DEFAULT 0x10000000
4866#define smnBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL_DEFAULT 0x00002810
4867#define smnBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS_DEFAULT 0x00000000
4868#define smnBIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP_DEFAULT 0x00011c03
4869#define smnBIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL_DEFAULT 0x00000000
4870#define smnBIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS_DEFAULT 0x00000001
4871#define smnBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2_DEFAULT 0x00000000
4872#define smnBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2_DEFAULT 0x00000000
4873#define smnBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS2_DEFAULT 0x00000000
4874#define smnBIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2_DEFAULT 0x0000000e
4875#define smnBIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2_DEFAULT 0x00000003
4876#define smnBIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2_DEFAULT 0x00000000
4877#define smnBIF_CFG_DEV0_EPF0_VF15_1_SLOT_CAP2_DEFAULT 0x00000000
4878#define smnBIF_CFG_DEV0_EPF0_VF15_1_SLOT_CNTL2_DEFAULT 0x00000000
4879#define smnBIF_CFG_DEV0_EPF0_VF15_1_SLOT_STATUS2_DEFAULT 0x00000000
4880#define smnBIF_CFG_DEV0_EPF0_VF15_1_MSI_CAP_LIST_DEFAULT 0x0000c000
4881#define smnBIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL_DEFAULT 0x00000080
4882#define smnBIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000
4883#define smnBIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000
4884#define smnBIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_DATA_DEFAULT 0x00000000
4885#define smnBIF_CFG_DEV0_EPF0_VF15_1_MSI_MASK_DEFAULT 0x00000000
4886#define smnBIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_DATA_64_DEFAULT 0x00000000
4887#define smnBIF_CFG_DEV0_EPF0_VF15_1_MSI_MASK_64_DEFAULT 0x00000000
4888#define smnBIF_CFG_DEV0_EPF0_VF15_1_MSI_PENDING_DEFAULT 0x00000000
4889#define smnBIF_CFG_DEV0_EPF0_VF15_1_MSI_PENDING_64_DEFAULT 0x00000000
4890#define smnBIF_CFG_DEV0_EPF0_VF15_1_MSIX_CAP_LIST_DEFAULT 0x00000000
4891#define smnBIF_CFG_DEV0_EPF0_VF15_1_MSIX_MSG_CNTL_DEFAULT 0x00000000
4892#define smnBIF_CFG_DEV0_EPF0_VF15_1_MSIX_TABLE_DEFAULT 0x00000000
4893#define smnBIF_CFG_DEV0_EPF0_VF15_1_MSIX_PBA_DEFAULT 0x00000000
4894#define smnBIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000
4895#define smnBIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000
4896#define smnBIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000
4897#define smnBIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000
4898#define smnBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000
4899#define smnBIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000
4900#define smnBIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000
4901#define smnBIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010
4902#define smnBIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000
4903#define smnBIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000
4904#define smnBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000
4905#define smnBIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG0_DEFAULT 0x00000000
4906#define smnBIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG1_DEFAULT 0x00000000
4907#define smnBIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG2_DEFAULT 0x00000000
4908#define smnBIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG3_DEFAULT 0x00000000
4909#define smnBIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000
4910#define smnBIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000
4911#define smnBIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000
4912#define smnBIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000
4913#define smnBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000
4914#define smnBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_CAP_DEFAULT 0x00000000
4915#define smnBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_CNTL_DEFAULT 0x00000000
4916#define smnBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000
4917#define smnBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CAP_DEFAULT 0x00000000
4918#define smnBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CNTL_DEFAULT 0x00000000
4919
4920
4921// addressBlock: nbio_nbif_pciemsix_amdgfx_MSIXTDEC
4922#define smnPCIEMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000
4923#define smnPCIEMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000
4924#define smnPCIEMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000
4925#define smnPCIEMSIX_VECT0_CONTROL_DEFAULT 0x00000000
4926#define smnPCIEMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000
4927#define smnPCIEMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000
4928#define smnPCIEMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000
4929#define smnPCIEMSIX_VECT1_CONTROL_DEFAULT 0x00000000
4930#define smnPCIEMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000
4931#define smnPCIEMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000
4932#define smnPCIEMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000
4933#define smnPCIEMSIX_VECT2_CONTROL_DEFAULT 0x00000000
4934#define smnPCIEMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000
4935#define smnPCIEMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000
4936#define smnPCIEMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000
4937#define smnPCIEMSIX_VECT3_CONTROL_DEFAULT 0x00000000
4938#define smnPCIEMSIX_VECT4_ADDR_LO_DEFAULT 0x00000000
4939#define smnPCIEMSIX_VECT4_ADDR_HI_DEFAULT 0x00000000
4940#define smnPCIEMSIX_VECT4_MSG_DATA_DEFAULT 0x00000000
4941#define smnPCIEMSIX_VECT4_CONTROL_DEFAULT 0x00000000
4942#define smnPCIEMSIX_VECT5_ADDR_LO_DEFAULT 0x00000000
4943#define smnPCIEMSIX_VECT5_ADDR_HI_DEFAULT 0x00000000
4944#define smnPCIEMSIX_VECT5_MSG_DATA_DEFAULT 0x00000000
4945#define smnPCIEMSIX_VECT5_CONTROL_DEFAULT 0x00000000
4946#define smnPCIEMSIX_VECT6_ADDR_LO_DEFAULT 0x00000000
4947#define smnPCIEMSIX_VECT6_ADDR_HI_DEFAULT 0x00000000
4948#define smnPCIEMSIX_VECT6_MSG_DATA_DEFAULT 0x00000000
4949#define smnPCIEMSIX_VECT6_CONTROL_DEFAULT 0x00000000
4950#define smnPCIEMSIX_VECT7_ADDR_LO_DEFAULT 0x00000000
4951#define smnPCIEMSIX_VECT7_ADDR_HI_DEFAULT 0x00000000
4952#define smnPCIEMSIX_VECT7_MSG_DATA_DEFAULT 0x00000000
4953#define smnPCIEMSIX_VECT7_CONTROL_DEFAULT 0x00000000
4954#define smnPCIEMSIX_VECT8_ADDR_LO_DEFAULT 0x00000000
4955#define smnPCIEMSIX_VECT8_ADDR_HI_DEFAULT 0x00000000
4956#define smnPCIEMSIX_VECT8_MSG_DATA_DEFAULT 0x00000000
4957#define smnPCIEMSIX_VECT8_CONTROL_DEFAULT 0x00000000
4958#define smnPCIEMSIX_VECT9_ADDR_LO_DEFAULT 0x00000000
4959#define smnPCIEMSIX_VECT9_ADDR_HI_DEFAULT 0x00000000
4960#define smnPCIEMSIX_VECT9_MSG_DATA_DEFAULT 0x00000000
4961#define smnPCIEMSIX_VECT9_CONTROL_DEFAULT 0x00000000
4962#define smnPCIEMSIX_VECT10_ADDR_LO_DEFAULT 0x00000000
4963#define smnPCIEMSIX_VECT10_ADDR_HI_DEFAULT 0x00000000
4964#define smnPCIEMSIX_VECT10_MSG_DATA_DEFAULT 0x00000000
4965#define smnPCIEMSIX_VECT10_CONTROL_DEFAULT 0x00000000
4966#define smnPCIEMSIX_VECT11_ADDR_LO_DEFAULT 0x00000000
4967#define smnPCIEMSIX_VECT11_ADDR_HI_DEFAULT 0x00000000
4968#define smnPCIEMSIX_VECT11_MSG_DATA_DEFAULT 0x00000000
4969#define smnPCIEMSIX_VECT11_CONTROL_DEFAULT 0x00000000
4970#define smnPCIEMSIX_VECT12_ADDR_LO_DEFAULT 0x00000000
4971#define smnPCIEMSIX_VECT12_ADDR_HI_DEFAULT 0x00000000
4972#define smnPCIEMSIX_VECT12_MSG_DATA_DEFAULT 0x00000000
4973#define smnPCIEMSIX_VECT12_CONTROL_DEFAULT 0x00000000
4974#define smnPCIEMSIX_VECT13_ADDR_LO_DEFAULT 0x00000000
4975#define smnPCIEMSIX_VECT13_ADDR_HI_DEFAULT 0x00000000
4976#define smnPCIEMSIX_VECT13_MSG_DATA_DEFAULT 0x00000000
4977#define smnPCIEMSIX_VECT13_CONTROL_DEFAULT 0x00000000
4978#define smnPCIEMSIX_VECT14_ADDR_LO_DEFAULT 0x00000000
4979#define smnPCIEMSIX_VECT14_ADDR_HI_DEFAULT 0x00000000
4980#define smnPCIEMSIX_VECT14_MSG_DATA_DEFAULT 0x00000000
4981#define smnPCIEMSIX_VECT14_CONTROL_DEFAULT 0x00000000
4982#define smnPCIEMSIX_VECT15_ADDR_LO_DEFAULT 0x00000000
4983#define smnPCIEMSIX_VECT15_ADDR_HI_DEFAULT 0x00000000
4984#define smnPCIEMSIX_VECT15_MSG_DATA_DEFAULT 0x00000000
4985#define smnPCIEMSIX_VECT15_CONTROL_DEFAULT 0x00000000
4986#define smnPCIEMSIX_VECT16_ADDR_LO_DEFAULT 0x00000000
4987#define smnPCIEMSIX_VECT16_ADDR_HI_DEFAULT 0x00000000
4988#define smnPCIEMSIX_VECT16_MSG_DATA_DEFAULT 0x00000000
4989#define smnPCIEMSIX_VECT16_CONTROL_DEFAULT 0x00000000
4990#define smnPCIEMSIX_VECT17_ADDR_LO_DEFAULT 0x00000000
4991#define smnPCIEMSIX_VECT17_ADDR_HI_DEFAULT 0x00000000
4992#define smnPCIEMSIX_VECT17_MSG_DATA_DEFAULT 0x00000000
4993#define smnPCIEMSIX_VECT17_CONTROL_DEFAULT 0x00000000
4994#define smnPCIEMSIX_VECT18_ADDR_LO_DEFAULT 0x00000000
4995#define smnPCIEMSIX_VECT18_ADDR_HI_DEFAULT 0x00000000
4996#define smnPCIEMSIX_VECT18_MSG_DATA_DEFAULT 0x00000000
4997#define smnPCIEMSIX_VECT18_CONTROL_DEFAULT 0x00000000
4998#define smnPCIEMSIX_VECT19_ADDR_LO_DEFAULT 0x00000000
4999#define smnPCIEMSIX_VECT19_ADDR_HI_DEFAULT 0x00000000
5000#define smnPCIEMSIX_VECT19_MSG_DATA_DEFAULT 0x00000000
5001#define smnPCIEMSIX_VECT19_CONTROL_DEFAULT 0x00000000
5002#define smnPCIEMSIX_VECT20_ADDR_LO_DEFAULT 0x00000000
5003#define smnPCIEMSIX_VECT20_ADDR_HI_DEFAULT 0x00000000
5004#define smnPCIEMSIX_VECT20_MSG_DATA_DEFAULT 0x00000000
5005#define smnPCIEMSIX_VECT20_CONTROL_DEFAULT 0x00000000
5006#define smnPCIEMSIX_VECT21_ADDR_LO_DEFAULT 0x00000000
5007#define smnPCIEMSIX_VECT21_ADDR_HI_DEFAULT 0x00000000
5008#define smnPCIEMSIX_VECT21_MSG_DATA_DEFAULT 0x00000000
5009#define smnPCIEMSIX_VECT21_CONTROL_DEFAULT 0x00000000
5010#define smnPCIEMSIX_VECT22_ADDR_LO_DEFAULT 0x00000000
5011#define smnPCIEMSIX_VECT22_ADDR_HI_DEFAULT 0x00000000
5012#define smnPCIEMSIX_VECT22_MSG_DATA_DEFAULT 0x00000000
5013#define smnPCIEMSIX_VECT22_CONTROL_DEFAULT 0x00000000
5014#define smnPCIEMSIX_VECT23_ADDR_LO_DEFAULT 0x00000000
5015#define smnPCIEMSIX_VECT23_ADDR_HI_DEFAULT 0x00000000
5016#define smnPCIEMSIX_VECT23_MSG_DATA_DEFAULT 0x00000000
5017#define smnPCIEMSIX_VECT23_CONTROL_DEFAULT 0x00000000
5018#define smnPCIEMSIX_VECT24_ADDR_LO_DEFAULT 0x00000000
5019#define smnPCIEMSIX_VECT24_ADDR_HI_DEFAULT 0x00000000
5020#define smnPCIEMSIX_VECT24_MSG_DATA_DEFAULT 0x00000000
5021#define smnPCIEMSIX_VECT24_CONTROL_DEFAULT 0x00000000
5022#define smnPCIEMSIX_VECT25_ADDR_LO_DEFAULT 0x00000000
5023#define smnPCIEMSIX_VECT25_ADDR_HI_DEFAULT 0x00000000
5024#define smnPCIEMSIX_VECT25_MSG_DATA_DEFAULT 0x00000000
5025#define smnPCIEMSIX_VECT25_CONTROL_DEFAULT 0x00000000
5026#define smnPCIEMSIX_VECT26_ADDR_LO_DEFAULT 0x00000000
5027#define smnPCIEMSIX_VECT26_ADDR_HI_DEFAULT 0x00000000
5028#define smnPCIEMSIX_VECT26_MSG_DATA_DEFAULT 0x00000000
5029#define smnPCIEMSIX_VECT26_CONTROL_DEFAULT 0x00000000
5030#define smnPCIEMSIX_VECT27_ADDR_LO_DEFAULT 0x00000000
5031#define smnPCIEMSIX_VECT27_ADDR_HI_DEFAULT 0x00000000
5032#define smnPCIEMSIX_VECT27_MSG_DATA_DEFAULT 0x00000000
5033#define smnPCIEMSIX_VECT27_CONTROL_DEFAULT 0x00000000
5034#define smnPCIEMSIX_VECT28_ADDR_LO_DEFAULT 0x00000000
5035#define smnPCIEMSIX_VECT28_ADDR_HI_DEFAULT 0x00000000
5036#define smnPCIEMSIX_VECT28_MSG_DATA_DEFAULT 0x00000000
5037#define smnPCIEMSIX_VECT28_CONTROL_DEFAULT 0x00000000
5038#define smnPCIEMSIX_VECT29_ADDR_LO_DEFAULT 0x00000000
5039#define smnPCIEMSIX_VECT29_ADDR_HI_DEFAULT 0x00000000
5040#define smnPCIEMSIX_VECT29_MSG_DATA_DEFAULT 0x00000000
5041#define smnPCIEMSIX_VECT29_CONTROL_DEFAULT 0x00000000
5042#define smnPCIEMSIX_VECT30_ADDR_LO_DEFAULT 0x00000000
5043#define smnPCIEMSIX_VECT30_ADDR_HI_DEFAULT 0x00000000
5044#define smnPCIEMSIX_VECT30_MSG_DATA_DEFAULT 0x00000000
5045#define smnPCIEMSIX_VECT30_CONTROL_DEFAULT 0x00000000
5046#define smnPCIEMSIX_VECT31_ADDR_LO_DEFAULT 0x00000000
5047#define smnPCIEMSIX_VECT31_ADDR_HI_DEFAULT 0x00000000
5048#define smnPCIEMSIX_VECT31_MSG_DATA_DEFAULT 0x00000000
5049#define smnPCIEMSIX_VECT31_CONTROL_DEFAULT 0x00000000
5050
5051
5052// addressBlock: nbio_nbif_pciemsix_amdgfx_MSIXPDEC
5053#define smnPCIEMSIX_PBA_DEFAULT 0x00000000
5054
5055
5056// addressBlock: nbio_pcie_pswusp0_pciedir_p
5057#define smnPCIEP_RESERVED_DEFAULT 0x00000000
5058#define smnPCIEP_SCRATCH_DEFAULT 0x00000000
5059#define smnPCIEP_PORT_CNTL_DEFAULT 0x00010009
5060#define smnPCIE_TX_CNTL_DEFAULT 0x00508000
5061#define smnPCIE_TX_REQUESTER_ID_DEFAULT 0x00000000
5062#define smnPCIE_TX_VENDOR_SPECIFIC_DEFAULT 0x00000000
5063#define smnPCIE_TX_REQUEST_NUM_CNTL_DEFAULT 0x02000000
5064#define smnPCIE_TX_SEQ_DEFAULT 0x00000000
5065#define smnPCIE_TX_REPLAY_DEFAULT 0x00900003
5066#define smnPCIE_TX_ACK_LATENCY_LIMIT_DEFAULT 0x00000000
5067#define smnPCIE_TX_CREDITS_ADVT_P_DEFAULT 0x00000000
5068#define smnPCIE_TX_CREDITS_ADVT_NP_DEFAULT 0x00000000
5069#define smnPCIE_TX_CREDITS_ADVT_CPL_DEFAULT 0x00000000
5070#define smnPCIE_TX_CREDITS_INIT_P_DEFAULT 0x00000000
5071#define smnPCIE_TX_CREDITS_INIT_NP_DEFAULT 0x00000000
5072#define smnPCIE_TX_CREDITS_INIT_CPL_DEFAULT 0x00000000
5073#define smnPCIE_TX_CREDITS_STATUS_DEFAULT 0x00000000
5074#define smnPCIE_TX_CREDITS_FCU_THRESHOLD_DEFAULT 0x03330333
5075#define smnPCIE_P_PORT_LANE_STATUS_DEFAULT 0x00000000
5076#define smnPCIE_FC_P_DEFAULT 0x00000208
5077#define smnPCIE_FC_NP_DEFAULT 0x00000202
5078#define smnPCIE_FC_CPL_DEFAULT 0x00000000
5079#define smnPSWUSP0_PCIE_ERR_CNTL_DEFAULT 0x00000500
5080#define smnPSWUSP0_PCIE_RX_CNTL_DEFAULT 0x01084000
5081#define smnPCIE_RX_EXPECTED_SEQNUM_DEFAULT 0x00000000
5082#define smnPCIE_RX_VENDOR_SPECIFIC_DEFAULT 0x00000000
5083#define smnPCIE_RX_CNTL3_DEFAULT 0x00000000
5084#define smnPCIE_RX_CREDITS_ALLOCATED_P_DEFAULT 0x00000000
5085#define smnPCIE_RX_CREDITS_ALLOCATED_NP_DEFAULT 0x00000000
5086#define smnPCIE_RX_CREDITS_ALLOCATED_CPL_DEFAULT 0x00000000
5087#define smnPCIEP_ERROR_INJECT_PHYSICAL_DEFAULT 0x00000000
5088#define smnPCIEP_ERROR_INJECT_TRANSACTION_DEFAULT 0x00000000
5089#define smnPCIEP_SRIOV_PRIV_CTRL_DEFAULT 0x00000000
5090#define smnPCIEP_NAK_COUNTER_DEFAULT 0x00000000
5091#define smnPCIE_LC_CNTL_DEFAULT 0x40010050
5092#define smnPCIE_LC_TRAINING_CNTL_DEFAULT 0x94009880
5093#define smnPCIE_LC_LINK_WIDTH_CNTL_DEFAULT 0xda800006
5094#define smnPCIE_LC_N_FTS_CNTL_DEFAULT 0x00ff820c
5095#define smnPSWUSP0_PCIE_LC_SPEED_CNTL_DEFAULT 0x04400100
5096#define smnPCIE_LC_STATE0_DEFAULT 0x00000000
5097#define smnPCIE_LC_STATE1_DEFAULT 0x00000000
5098#define smnPCIE_LC_STATE2_DEFAULT 0x00000000
5099#define smnPCIE_LC_STATE3_DEFAULT 0x00000000
5100#define smnPCIE_LC_STATE4_DEFAULT 0x00000000
5101#define smnPCIE_LC_STATE5_DEFAULT 0x00000000
5102#define smnPCIE_LINK_MANAGEMENT_CNTL2_DEFAULT 0x00000000
5103#define smnPSWUSP0_PCIE_LC_CNTL2_DEFAULT 0x96180280
5104#define smnPCIE_LC_BW_CHANGE_CNTL_DEFAULT 0x00000000
5105#define smnPCIE_LC_CDR_CNTL_DEFAULT 0x01018060
5106#define smnPCIE_LC_LANE_CNTL_DEFAULT 0x00000000
5107#define smnPCIE_LC_CNTL3_DEFAULT 0x2850a020
5108#define smnPCIE_LC_CNTL4_DEFAULT 0x0340048c
5109#define smnPCIE_LC_CNTL5_DEFAULT 0x40410b2c
5110#define smnPCIE_LC_FORCE_COEFF_DEFAULT 0x00080000
5111#define smnPCIE_LC_BEST_EQ_SETTINGS_DEFAULT 0x00000000
5112#define smnPCIE_LC_FORCE_EQ_REQ_COEFF_DEFAULT 0x00000000
5113#define smnPCIE_LC_CNTL6_DEFAULT 0x8a000010
5114#define smnPCIE_LC_CNTL7_DEFAULT 0x8000020e
5115#define smnPCIE_LINK_MANAGEMENT_STATUS_DEFAULT 0x00000000
5116#define smnPCIE_LINK_MANAGEMENT_MASK_DEFAULT 0x00003fff
5117#define smnPCIE_LINK_MANAGEMENT_CNTL_DEFAULT 0x00000000
5118#define smnPCIEP_STRAP_LC_DEFAULT 0x00000000
5119#define smnPSWUSP0_PCIEP_STRAP_MISC_DEFAULT 0x00000000
5120#define smnPCIE_LC_L1_PM_SUBSTATE_DEFAULT 0x00540000
5121#define smnPCIE_LC_L1_PM_SUBSTATE2_DEFAULT 0x00000000
5122#define smnPCIE_LC_PORT_ORDER_DEFAULT 0x00000000
5123#define smnPCIEP_BCH_ECC_CNTL_DEFAULT 0x00000100
5124
5125
5126// addressBlock: nbio_pcie_pciedir
5127#define smnPCIE_RESERVED_DEFAULT 0x00000000
5128#define smnPCIE_SCRATCH_DEFAULT 0x00000000
5129#define smnPCIE_RX_NUM_NAK_DEFAULT 0x00000000
5130#define smnPCIE_RX_NUM_NAK_GENERATED_DEFAULT 0x00000000
5131#define smnPCIE_CNTL_DEFAULT 0x80e31000
5132#define smnPCIE_CONFIG_CNTL_DEFAULT 0x0800010f
5133#define smnPCIE_TX_TRACKING_ADDR_LO_DEFAULT 0x00000000
5134#define smnPCIE_TX_TRACKING_ADDR_HI_DEFAULT 0x00000000
5135#define smnPCIE_TX_TRACKING_CTRL_STATUS_DEFAULT 0x00000000
5136#define smnPCIE_BW_BY_UNITID_DEFAULT 0x00000000
5137#define smnPCIE_CNTL2_DEFAULT 0x0e000109
5138#define smnPCIE_RX_CNTL2_DEFAULT 0x00000000
5139#define smnPCIE_TX_F0_ATTR_CNTL_DEFAULT 0x00000000
5140#define smnPCIE_TX_SWUS_ATTR_CNTL_DEFAULT 0x00000000
5141#define smnPCIE_CI_CNTL_DEFAULT 0x00000010
5142#define smnPCIE_BUS_CNTL_DEFAULT 0x00000000
5143#define smnPCIE_LC_STATE6_DEFAULT 0x00000000
5144#define smnPCIE_LC_STATE7_DEFAULT 0x00000000
5145#define smnPCIE_LC_STATE8_DEFAULT 0x00000000
5146#define smnPCIE_LC_STATE9_DEFAULT 0x00000000
5147#define smnPCIE_LC_STATE10_DEFAULT 0x00000000
5148#define smnPCIE_LC_STATE11_DEFAULT 0x00000000
5149#define smnPCIE_LC_STATUS1_DEFAULT 0x00000000
5150#define smnPCIE_LC_STATUS2_DEFAULT 0x00000000
5151#define smnPCIE_WPR_CNTL_DEFAULT 0x00000005
5152#define smnPCIE_RX_LAST_TLP0_DEFAULT 0x00000000
5153#define smnPCIE_RX_LAST_TLP1_DEFAULT 0x00000000
5154#define smnPCIE_RX_LAST_TLP2_DEFAULT 0x00000000
5155#define smnPCIE_RX_LAST_TLP3_DEFAULT 0x00000000
5156#define smnPCIE_TX_LAST_TLP0_DEFAULT 0x00000000
5157#define smnPCIE_TX_LAST_TLP1_DEFAULT 0x00000000
5158#define smnPCIE_TX_LAST_TLP2_DEFAULT 0x00000000
5159#define smnPCIE_TX_LAST_TLP3_DEFAULT 0x00000000
5160#define smnPCIE_I2C_REG_ADDR_EXPAND_DEFAULT 0x00000000
5161#define smnPCIE_I2C_REG_DATA_DEFAULT 0x00000000
5162#define smnPCIE_CFG_CNTL_DEFAULT 0x00000000
5163#define smnPCIE_LC_PM_CNTL_DEFAULT 0x76543210
5164#define smnPCIE_LC_PORT_ORDER_CNTL_DEFAULT 0x00000000
5165#define smnPCIE_P_CNTL_DEFAULT 0x00010000
5166#define smnPCIE_P_BUF_STATUS_DEFAULT 0x00000000
5167#define smnPCIE_P_DECODER_STATUS_DEFAULT 0x00000000
5168#define smnPCIE_P_MISC_STATUS_DEFAULT 0x00000000
5169#define smnPCIE_P_RCV_L0S_FTS_DET_DEFAULT 0x000000ff
5170#define smnPCIE_RX_AD_DEFAULT 0x00000002
5171#define smnPCIE_SDP_CTRL_DEFAULT 0x00000002
5172#define smnPCIE_SDP_SWUS_SLV_ATTR_CTRL_DEFAULT 0x00000000
5173#define smnPCIE_PERF_COUNT_CNTL_DEFAULT 0x00000000
5174#define smnPCIE_PERF_CNTL_TXCLK_DEFAULT 0x00000000
5175#define smnPCIE_PERF_COUNT0_TXCLK_DEFAULT 0x00000000
5176#define smnPCIE_PERF_COUNT1_TXCLK_DEFAULT 0x00000000
5177#define smnPCIE_PERF_CNTL_MST_R_CLK_DEFAULT 0x00000000
5178#define smnPCIE_PERF_COUNT0_MST_R_CLK_DEFAULT 0x00000000
5179#define smnPCIE_PERF_COUNT1_MST_R_CLK_DEFAULT 0x00000000
5180#define smnPCIE_PERF_CNTL_MST_C_CLK_DEFAULT 0x00000000
5181#define smnPCIE_PERF_COUNT0_MST_C_CLK_DEFAULT 0x00000000
5182#define smnPCIE_PERF_COUNT1_MST_C_CLK_DEFAULT 0x00000000
5183#define smnPCIE_PERF_CNTL_SLV_R_CLK_DEFAULT 0x00000000
5184#define smnPCIE_PERF_COUNT0_SLV_R_CLK_DEFAULT 0x00000000
5185#define smnPCIE_PERF_COUNT1_SLV_R_CLK_DEFAULT 0x00000000
5186#define smnPCIE_PERF_CNTL_SLV_S_C_CLK_DEFAULT 0x00000000
5187#define smnPCIE_PERF_COUNT0_SLV_S_C_CLK_DEFAULT 0x00000000
5188#define smnPCIE_PERF_COUNT1_SLV_S_C_CLK_DEFAULT 0x00000000
5189#define smnPCIE_PERF_CNTL_SLV_NS_C_CLK_DEFAULT 0x00000000
5190#define smnPCIE_PERF_COUNT0_SLV_NS_C_CLK_DEFAULT 0x00000000
5191#define smnPCIE_PERF_COUNT1_SLV_NS_C_CLK_DEFAULT 0x00000000
5192#define smnPCIE_PERF_CNTL_EVENT0_PORT_SEL_DEFAULT 0x00000000
5193#define smnPCIE_PERF_CNTL_EVENT1_PORT_SEL_DEFAULT 0x00000000
5194#define smnPCIE_PERF_CNTL_TXCLK2_DEFAULT 0x00000000
5195#define smnPCIE_PERF_COUNT0_TXCLK2_DEFAULT 0x00000000
5196#define smnPCIE_PERF_COUNT1_TXCLK2_DEFAULT 0x00000000
5197#define smnPCIE_PRBS_CLR_DEFAULT 0x00000000
5198#define smnPCIE_PRBS_STATUS1_DEFAULT 0x00000000
5199#define smnPCIE_PRBS_STATUS2_DEFAULT 0x00000000
5200#define smnPCIE_PRBS_FREERUN_DEFAULT 0x00000000
5201#define smnPCIE_PRBS_MISC_DEFAULT 0x00000000
5202#define smnPCIE_PRBS_USER_PATTERN_DEFAULT 0x00000000
5203#define smnPCIE_PRBS_LO_BITCNT_DEFAULT 0x00000000
5204#define smnPCIE_PRBS_HI_BITCNT_DEFAULT 0x00000000
5205#define smnPCIE_PRBS_ERRCNT_0_DEFAULT 0x00000000
5206#define smnPCIE_PRBS_ERRCNT_1_DEFAULT 0x00000000
5207#define smnPCIE_PRBS_ERRCNT_2_DEFAULT 0x00000000
5208#define smnPCIE_PRBS_ERRCNT_3_DEFAULT 0x00000000
5209#define smnPCIE_PRBS_ERRCNT_4_DEFAULT 0x00000000
5210#define smnPCIE_PRBS_ERRCNT_5_DEFAULT 0x00000000
5211#define smnPCIE_PRBS_ERRCNT_6_DEFAULT 0x00000000
5212#define smnPCIE_PRBS_ERRCNT_7_DEFAULT 0x00000000
5213#define smnPCIE_PRBS_ERRCNT_8_DEFAULT 0x00000000
5214#define smnPCIE_PRBS_ERRCNT_9_DEFAULT 0x00000000
5215#define smnPCIE_PRBS_ERRCNT_10_DEFAULT 0x00000000
5216#define smnPCIE_PRBS_ERRCNT_11_DEFAULT 0x00000000
5217#define smnPCIE_PRBS_ERRCNT_12_DEFAULT 0x00000000
5218#define smnPCIE_PRBS_ERRCNT_13_DEFAULT 0x00000000
5219#define smnPCIE_PRBS_ERRCNT_14_DEFAULT 0x00000000
5220#define smnPCIE_PRBS_ERRCNT_15_DEFAULT 0x00000000
5221#define smnSWRST_COMMAND_STATUS_DEFAULT 0x00000000
5222#define smnSWRST_GENERAL_CONTROL_DEFAULT 0x02001002
5223#define smnSWRST_COMMAND_0_DEFAULT 0x00000000
5224#define smnSWRST_COMMAND_1_DEFAULT 0x04000000
5225#define smnSWRST_CONTROL_0_DEFAULT 0x5600ff00
5226#define smnSWRST_CONTROL_1_DEFAULT 0xc220ffff
5227#define smnSWRST_CONTROL_2_DEFAULT 0x00000000
5228#define smnSWRST_CONTROL_3_DEFAULT 0x00000000
5229#define smnSWRST_CONTROL_4_DEFAULT 0x5c00ff01
5230#define smnSWRST_CONTROL_5_DEFAULT 0xfe20ffff
5231#define smnSWRST_CONTROL_6_DEFAULT 0x000007ff
5232#define smnSWRST_EP_COMMAND_0_DEFAULT 0x00000000
5233#define smnSWRST_EP_CONTROL_0_DEFAULT 0x00000500
5234#define smnCPM_CONTROL_DEFAULT 0x00803e00
5235#define smnSMN_APERTURE_ID_A_DEFAULT 0x00000000
5236#define smnSMN_APERTURE_ID_B_DEFAULT 0x00000000
5237#define smnRSMU_MASTER_CONTROL_DEFAULT 0x00000000
5238#define smnRSMU_SLAVE_CONTROL_DEFAULT 0x00000001
5239#define smnRSMU_POWER_GATING_CONTROL_DEFAULT 0x00000800
5240#define smnRSMU_BIOS_TIMER_CMD_DEFAULT 0x00000000
5241#define smnRSMU_BIOS_TIMER_CNTL_DEFAULT 0x00000064
5242#define smnLNCNT_CONTROL_DEFAULT 0x00000000
5243#define smnCFG_LNC_WINDOW_REGISTER_DEFAULT 0x00000000
5244#define smnLNCNT_QUAN_THRD_DEFAULT 0x00000000
5245#define smnLNCNT_WEIGHT_DEFAULT 0x00000000
5246#define smnLNC_TOTAL_WACC_REGISTER_DEFAULT 0x00000000
5247#define smnLNC_BW_WACC_REGISTER_DEFAULT 0x00000000
5248#define smnLNC_CMN_WACC_REGISTER_DEFAULT 0x00000000
5249#define smnSMU_INT_PIN_SHARING_PORT_INDICATOR_DEFAULT 0x00000000
5250#define smnSMU_PCIE_FENCED1_REG_DEFAULT 0x00000000
5251#define smnSMU_PCIE_FENCED2_REG_DEFAULT 0x00000000
5252
5253
5254// addressBlock: nbio_pipe_pcs_dwc_e12mp_phy_x4_ns0_dwc_e12mp_phy_x4_ns_UP16_dwc_e12mp_phy_x4_ns_UP16_mem_map
5255#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_IDCODE_LO_DEFAULT 0x000074cd
5256#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_IDCODE_HI_DEFAULT 0x00000733
5257#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_REFCLK_OVRD_IN_DEFAULT 0x00000070
5258#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_B_DIV_CLK_OVRD_IN_DEFAULT 0x00000000
5259#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_0_DEFAULT 0x00000328
5260#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_1_DEFAULT 0x00000000
5261#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_OVRD_IN_2_DEFAULT 0x00000043
5262#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_OVRD_IN_0_DEFAULT 0x00000194
5263#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_OVRD_IN_1_DEFAULT 0x0000a000
5264#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_OVRD_IN_2_DEFAULT 0x00000043
5265#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_SUP_OVRD_IN_DEFAULT 0x00000008
5266#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_SUP_OVRD_OUT_DEFAULT 0x00000004
5267#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_LVL_OVRD_IN_DEFAULT 0x000001d0
5268#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_ASIC_IN_0_DEFAULT 0x00000000
5269#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_ASIC_IN_1_DEFAULT 0x00000000
5270#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_ASIC_IN_2_DEFAULT 0x00000000
5271#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_ASIC_IN_0_DEFAULT 0x00000000
5272#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_ASIC_IN_1_DEFAULT 0x00000000
5273#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_ASIC_IN_2_DEFAULT 0x00000000
5274#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_B_DIV_CLK_ASIC_IN_DEFAULT 0x00000000
5275#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ASIC_IN_DEFAULT 0x00000000
5276#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_LVL_ASIC_IN_DEFAULT 0x00000000
5277#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLA_OVRD_OUT_DEFAULT 0x00000002
5278#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_MPLLB_OVRD_OUT_DEFAULT 0x00000002
5279#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_RTUNE_OVRD_OUT_DEFAULT 0x00000000
5280#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_RX_TERM_OVRD_OUT_DEFAULT 0x00000000
5281#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_ANA_STAT_DEFAULT 0x00000000
5282#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_DEFAULT 0x00000018
5283#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD_DEFAULT 0x00000000
5284#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT_DEFAULT 0x00000000
5285#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD_DEFAULT 0x00000d00
5286#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD_DEFAULT 0x00005200
5287#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD_DEFAULT 0x0000894a
5288#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_DEFAULT 0x00000066
5289#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL_DEFAULT 0x00000000
5290#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE_DEFAULT 0x00000000
5291#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_SSC_SS_PHASE_DEFAULT 0x00004000
5292#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_SSC_SS_FREQ_0_DEFAULT 0x00000025
5293#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLA_SSC_SS_FREQ_1_DEFAULT 0x00000066
5294#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL_DEFAULT 0x00000018
5295#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD_DEFAULT 0x00000000
5296#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT_DEFAULT 0x00000000
5297#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD_DEFAULT 0x00000d00
5298#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD_DEFAULT 0x00005200
5299#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD_DEFAULT 0x0000894a
5300#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_DEFAULT 0x00000066
5301#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL_DEFAULT 0x00000000
5302#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE_DEFAULT 0x00000000
5303#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_SSC_SS_PHASE_DEFAULT 0x00004000
5304#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_SSC_SS_FREQ_0_DEFAULT 0x00000025
5305#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_MPLLB_SSC_SS_FREQ_1_DEFAULT 0x00000066
5306#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_MISC_DEFAULT 0x00000028
5307#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_OVRD_DEFAULT 0x00000000
5308#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB1_DEFAULT 0x00000000
5309#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB2_DEFAULT 0x00000000
5310#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLA_ATB3_DEFAULT 0x00000000
5311#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_MISC_DEFAULT 0x00000028
5312#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_OVRD_DEFAULT 0x00000000
5313#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB1_DEFAULT 0x00000000
5314#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB2_DEFAULT 0x00000000
5315#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_MPLLB_ATB3_DEFAULT 0x00000000
5316#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_RTUNE_CTRL_DEFAULT 0x00000000
5317#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_SWITCH_PWR_MEAS_DEFAULT 0x00000000
5318#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_SWITCH_MISC_MEAS_DEFAULT 0x00000012
5319#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_ANA_BG_DEFAULT 0x0000000e
5320#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_CONFIG_DEFAULT 0x00000000
5321#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_STAT_DEFAULT 0x00000000
5322#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_RX_SET_VAL_DEFAULT 0x00000000
5323#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_TXDN_SET_VAL_DEFAULT 0x00000000
5324#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_TXUP_SET_VAL_DEFAULT 0x00000000
5325#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_RX_STAT_DEFAULT 0x00000000
5326#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_TXDN_STAT_DEFAULT 0x00000000
5327#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUP_DIG_RTUNE_TXUP_STAT_DEFAULT 0x00000000
5328#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_LANE_OVRD_IN_DEFAULT 0x00000000
5329#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_0_DEFAULT 0x00000000
5330#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_1_DEFAULT 0x00005078
5331#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_IN_2_DEFAULT 0x00000000
5332#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_OVRD_OUT_DEFAULT 0x00000000
5333#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_0_DEFAULT 0x00000000
5334#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_1_DEFAULT 0x00000014
5335#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_2_DEFAULT 0x000003e8
5336#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_IN_3_DEFAULT 0x00000000
5337#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0_DEFAULT 0x000037f8
5338#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1_DEFAULT 0x00000400
5339#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_OUT_0_DEFAULT 0x00000000
5340#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_LANE_ASIC_IN_DEFAULT 0x00000000
5341#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_0_DEFAULT 0x00000000
5342#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_1_DEFAULT 0x00000000
5343#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_IN_2_DEFAULT 0x00000000
5344#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_TX_ASIC_OUT_DEFAULT 0x00000000
5345#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_0_DEFAULT 0x00000000
5346#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_IN_1_DEFAULT 0x00000000
5347#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0_DEFAULT 0x00000000
5348#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1_DEFAULT 0x00000000
5349#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0_DEFAULT 0x00000000
5350#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1_DEFAULT 0x00000000
5351#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_ASIC_OUT_0_DEFAULT 0x00000000
5352#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_2_DEFAULT 0x00002040
5353#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ASIC_RX_OVRD_EQ_IN_3_DEFAULT 0x00002040
5354#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0_DEFAULT 0x000000e7
5355#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S_DEFAULT 0x00000046
5356#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P1_DEFAULT 0x00000112
5357#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2_DEFAULT 0x00000110
5358#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0_DEFAULT 0x00001a0c
5359#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1_DEFAULT 0x0000e6cc
5360#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2_DEFAULT 0x00000d5d
5361#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3_DEFAULT 0x00002907
5362#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_TX_LBERT_CTL_DEFAULT 0x00000000
5363#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0_DEFAULT 0x00000cff
5364#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S_DEFAULT 0x00000407
5365#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P1_DEFAULT 0x00000301
5366#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PSTATE_P2_DEFAULT 0x00000301
5367#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0_DEFAULT 0x00000307
5368#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1_DEFAULT 0x00001434
5369#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2_DEFAULT 0x00000006
5370#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_PWRCTL_RX_PWRUP_CTL_0_DEFAULT 0x00000000
5371#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0_DEFAULT 0x00000002
5372#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1_DEFAULT 0x00000100
5373#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2_DEFAULT 0x00002600
5374#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0_DEFAULT 0x00003521
5375#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1_DEFAULT 0x00000002
5376#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0_DEFAULT 0x00000000
5377#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1_DEFAULT 0x00000000
5378#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2_DEFAULT 0x00000000
5379#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_RX_ALIGN_XAUI_COMM_MASK_DEFAULT 0x000003ff
5380#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_LBERT_CTL_DEFAULT 0x00000000
5381#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_LBERT_ERR_DEFAULT 0x00000000
5382#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_0_DEFAULT 0x0000000f
5383#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_1_DEFAULT 0x00004c39
5384#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_2_DEFAULT 0x00004abb
5385#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_3_DEFAULT 0x000000d6
5386#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_CDR_CTL_4_DEFAULT 0x00002cdb
5387#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_CDR_STAT_DEFAULT 0x00000000
5388#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_DPLL_FREQ_DEFAULT 0x00002000
5389#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_DPLL_FREQ_BOUND_0_DEFAULT 0x000004c8
5390#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_DPLL_FREQ_BOUND_1_DEFAULT 0x0000019c
5391#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0_DEFAULT 0x00000c10
5392#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1_DEFAULT 0x00000009
5393#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2_DEFAULT 0x000000c2
5394#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3_DEFAULT 0x00000000
5395#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_4_DEFAULT 0x00000000
5396#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_5_DEFAULT 0x00000000
5397#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6_DEFAULT 0x0000792b
5398#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7_DEFAULT 0x00004342
5399#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8_DEFAULT 0x00004925
5400#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9_DEFAULT 0x00000000
5401#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG_DEFAULT 0x0000001f
5402#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ATT_STATUS_DEFAULT 0x00000000
5403#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_VGA_STATUS_DEFAULT 0x00000000
5404#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_CTLE_STATUS_DEFAULT 0x00000000
5405#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS_DEFAULT 0x00000000
5406#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS_DEFAULT 0x00000000
5407#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS_DEFAULT 0x00000000
5408#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS_DEFAULT 0x00000000
5409#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS_DEFAULT 0x00000000
5410#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST_DEFAULT 0x00000080
5411#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST_DEFAULT 0x00000080
5412#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST_DEFAULT 0x00000080
5413#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST_DEFAULT 0x00000080
5414#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN_DEFAULT 0x00000007
5415#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD_DEFAULT 0x00000007
5416#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST_DEFAULT 0x00000080
5417#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST_DEFAULT 0x00000080
5418#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL_DEFAULT 0x00000000
5419#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST_DEFAULT 0x00000080
5420#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST_DEFAULT 0x00000080
5421#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_LD_VAL_1_DEFAULT 0x00000040
5422#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_DATA_MSK_DEFAULT 0x0000ffff
5423#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL0_DEFAULT 0x00003c06
5424#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL1_DEFAULT 0x00000800
5425#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL0_DEFAULT 0x00004000
5426#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL1_DEFAULT 0x00000008
5427#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_SMPL_CNT1_DEFAULT 0x00000000
5428#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_0_DEFAULT 0x00000000
5429#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_1_DEFAULT 0x00000000
5430#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_2_DEFAULT 0x00000000
5431#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_3_DEFAULT 0x00000000
5432#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_4_DEFAULT 0x00000000
5433#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_5_DEFAULT 0x00000000
5434#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CNT_6_DEFAULT 0x00000000
5435#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL_DEFAULT 0x00000019
5436#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL2_DEFAULT 0x00000000
5437#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL3_DEFAULT 0x00000000
5438#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL4_DEFAULT 0x00000000
5439#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_MATCH_CTL5_DEFAULT 0x00000000
5440#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_STAT_STAT_CTL2_DEFAULT 0x00000000
5441#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_OVRD_OUT_DEFAULT 0x00000000
5442#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT_DEFAULT 0x00000000
5443#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT_DEFAULT 0x00000000
5444#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0_DEFAULT 0x00000000
5445#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1_DEFAULT 0x00000000
5446#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2_DEFAULT 0x00000000
5447#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3_DEFAULT 0x00000000
5448#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_TX_EQ_OVRD_OUT_4_DEFAULT 0x00000000
5449#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CTL_OVRD_OUT_DEFAULT 0x00000000
5450#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_PWR_OVRD_OUT_DEFAULT 0x00000000
5451#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0_DEFAULT 0x00000000
5452#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_VCO_OVRD_OUT_1_DEFAULT 0x00000002
5453#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_CAL_DEFAULT 0x00000000
5454#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_DAC_CTRL_DEFAULT 0x00000080
5455#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_DAC_CTRL_OVRD_DEFAULT 0x00000000
5456#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_DAC_CTRL_SEL_DEFAULT 0x00000000
5457#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_AFE_ATT_VGA_DEFAULT 0x00000000
5458#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_AFE_CTLE_DEFAULT 0x00000000
5459#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_SCOPE_DEFAULT 0x00000000
5460#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_SLICER_CTRL_DEFAULT 0x00000077
5461#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST_DEFAULT 0x00000007
5462#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_IQ_SENSE_EN_DEFAULT 0x00000000
5463#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN_DEFAULT 0x00000000
5464#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE_DEFAULT 0x00000000
5465#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK_DEFAULT 0x00000000
5466#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_STATUS_0_DEFAULT 0x00000000
5467#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_ANA_STATUS_1_DEFAULT 0x00000000
5468#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_MEAS_DEFAULT 0x00000000
5469#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_PWR_OVRD_DEFAULT 0x00000000
5470#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ALT_BUS_DEFAULT 0x00000000
5471#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB1_DEFAULT 0x00000000
5472#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_ATB2_DEFAULT 0x00000000
5473#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_VBOOST_DEFAULT 0x00000000
5474#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_TERM_CODE_DN_DEFAULT 0x00000000
5475#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_TERM_CODE_UP_DEFAULT 0x000000fe
5476#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_IBOOST_CODE_DEFAULT 0x00000000
5477#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_OVRD_CLK_DEFAULT 0x00000000
5478#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_TX_MISC_DEFAULT 0x00000000
5479#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_IQSKEW_DEFAULT 0x00000000
5480#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_DCC_OVRD_DEFAULT 0x00000000
5481#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL1_DEFAULT 0x00000000
5482#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_REGREF_DEFAULT 0x00000000
5483#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CDR_AFE_DEFAULT 0x000000f0
5484#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_PWR_CTRL2_DEFAULT 0x00000000
5485#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_MISC_OVRD_DEFAULT 0x00000000
5486#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CAL_MUXA_DEFAULT 0x00000000
5487#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_MEAS1_DEFAULT 0x00000000
5488#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_MEAS2_DEFAULT 0x00000000
5489#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_CAL_MUXB_DEFAULT 0x00000000
5490#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_TERM_DEFAULT 0x00000000
5491#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_SLC_CTRL_DEFAULT 0x00000000
5492#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE0_ANA_RX_ATB_VREG_DEFAULT 0x00000000
5493#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_LANE_OVRD_IN_DEFAULT 0x00000000
5494#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_0_DEFAULT 0x00000000
5495#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_1_DEFAULT 0x00005078
5496#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_IN_2_DEFAULT 0x00000000
5497#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_OVRD_OUT_DEFAULT 0x00000000
5498#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_0_DEFAULT 0x00000000
5499#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_1_DEFAULT 0x00000014
5500#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_2_DEFAULT 0x000003e8
5501#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_IN_3_DEFAULT 0x00000000
5502#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0_DEFAULT 0x000037f8
5503#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1_DEFAULT 0x00000400
5504#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_OUT_0_DEFAULT 0x00000000
5505#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_LANE_ASIC_IN_DEFAULT 0x00000000
5506#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_0_DEFAULT 0x00000000
5507#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_1_DEFAULT 0x00000000
5508#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_IN_2_DEFAULT 0x00000000
5509#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_TX_ASIC_OUT_DEFAULT 0x00000000
5510#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_0_DEFAULT 0x00000000
5511#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_IN_1_DEFAULT 0x00000000
5512#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0_DEFAULT 0x00000000
5513#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1_DEFAULT 0x00000000
5514#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0_DEFAULT 0x00000000
5515#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1_DEFAULT 0x00000000
5516#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_ASIC_OUT_0_DEFAULT 0x00000000
5517#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_2_DEFAULT 0x00002040
5518#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ASIC_RX_OVRD_EQ_IN_3_DEFAULT 0x00002040
5519#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0_DEFAULT 0x000000e7
5520#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S_DEFAULT 0x00000046
5521#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P1_DEFAULT 0x00000112
5522#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2_DEFAULT 0x00000110
5523#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0_DEFAULT 0x00001a0c
5524#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1_DEFAULT 0x0000e6cc
5525#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2_DEFAULT 0x00000d5d
5526#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3_DEFAULT 0x00002907
5527#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_TX_LBERT_CTL_DEFAULT 0x00000000
5528#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0_DEFAULT 0x00000cff
5529#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S_DEFAULT 0x00000407
5530#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P1_DEFAULT 0x00000301
5531#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PSTATE_P2_DEFAULT 0x00000301
5532#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0_DEFAULT 0x00000307
5533#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1_DEFAULT 0x00001434
5534#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2_DEFAULT 0x00000006
5535#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_PWRCTL_RX_PWRUP_CTL_0_DEFAULT 0x00000000
5536#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0_DEFAULT 0x00000002
5537#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1_DEFAULT 0x00000100
5538#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2_DEFAULT 0x00002600
5539#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0_DEFAULT 0x00003521
5540#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1_DEFAULT 0x00000002
5541#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0_DEFAULT 0x00000000
5542#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1_DEFAULT 0x00000000
5543#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2_DEFAULT 0x00000000
5544#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK_DEFAULT 0x000003ff
5545#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_LBERT_CTL_DEFAULT 0x00000000
5546#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_LBERT_ERR_DEFAULT 0x00000000
5547#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_0_DEFAULT 0x0000000f
5548#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_1_DEFAULT 0x00004c39
5549#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_2_DEFAULT 0x00004abb
5550#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_3_DEFAULT 0x000000d6
5551#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_CDR_CTL_4_DEFAULT 0x00002cdb
5552#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_CDR_STAT_DEFAULT 0x00000000
5553#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_DPLL_FREQ_DEFAULT 0x00002000
5554#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_DPLL_FREQ_BOUND_0_DEFAULT 0x000004c8
5555#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_DPLL_FREQ_BOUND_1_DEFAULT 0x0000019c
5556#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0_DEFAULT 0x00000c10
5557#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1_DEFAULT 0x00000009
5558#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2_DEFAULT 0x000000c2
5559#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3_DEFAULT 0x00000000
5560#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_4_DEFAULT 0x00000000
5561#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_5_DEFAULT 0x00000000
5562#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6_DEFAULT 0x0000792b
5563#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7_DEFAULT 0x00004342
5564#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8_DEFAULT 0x00004925
5565#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9_DEFAULT 0x00000000
5566#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG_DEFAULT 0x0000001f
5567#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ATT_STATUS_DEFAULT 0x00000000
5568#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_VGA_STATUS_DEFAULT 0x00000000
5569#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_CTLE_STATUS_DEFAULT 0x00000000
5570#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS_DEFAULT 0x00000000
5571#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS_DEFAULT 0x00000000
5572#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS_DEFAULT 0x00000000
5573#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS_DEFAULT 0x00000000
5574#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS_DEFAULT 0x00000000
5575#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST_DEFAULT 0x00000080
5576#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST_DEFAULT 0x00000080
5577#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST_DEFAULT 0x00000080
5578#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST_DEFAULT 0x00000080
5579#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN_DEFAULT 0x00000007
5580#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD_DEFAULT 0x00000007
5581#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST_DEFAULT 0x00000080
5582#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST_DEFAULT 0x00000080
5583#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL_DEFAULT 0x00000000
5584#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST_DEFAULT 0x00000080
5585#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST_DEFAULT 0x00000080
5586#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_LD_VAL_1_DEFAULT 0x00000040
5587#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_DATA_MSK_DEFAULT 0x0000ffff
5588#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL0_DEFAULT 0x00003c06
5589#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL1_DEFAULT 0x00000800
5590#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL0_DEFAULT 0x00004000
5591#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL1_DEFAULT 0x00000008
5592#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_SMPL_CNT1_DEFAULT 0x00000000
5593#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_0_DEFAULT 0x00000000
5594#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_1_DEFAULT 0x00000000
5595#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_2_DEFAULT 0x00000000
5596#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_3_DEFAULT 0x00000000
5597#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_4_DEFAULT 0x00000000
5598#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_5_DEFAULT 0x00000000
5599#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CNT_6_DEFAULT 0x00000000
5600#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL_DEFAULT 0x00000019
5601#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL2_DEFAULT 0x00000000
5602#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL3_DEFAULT 0x00000000
5603#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL4_DEFAULT 0x00000000
5604#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_MATCH_CTL5_DEFAULT 0x00000000
5605#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_STAT_STAT_CTL2_DEFAULT 0x00000000
5606#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_OVRD_OUT_DEFAULT 0x00000000
5607#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT_DEFAULT 0x00000000
5608#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT_DEFAULT 0x00000000
5609#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0_DEFAULT 0x00000000
5610#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1_DEFAULT 0x00000000
5611#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2_DEFAULT 0x00000000
5612#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3_DEFAULT 0x00000000
5613#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_TX_EQ_OVRD_OUT_4_DEFAULT 0x00000000
5614#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CTL_OVRD_OUT_DEFAULT 0x00000000
5615#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_PWR_OVRD_OUT_DEFAULT 0x00000000
5616#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0_DEFAULT 0x00000000
5617#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_VCO_OVRD_OUT_1_DEFAULT 0x00000002
5618#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_CAL_DEFAULT 0x00000000
5619#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_DAC_CTRL_DEFAULT 0x00000080
5620#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_DAC_CTRL_OVRD_DEFAULT 0x00000000
5621#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_DAC_CTRL_SEL_DEFAULT 0x00000000
5622#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_AFE_ATT_VGA_DEFAULT 0x00000000
5623#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_AFE_CTLE_DEFAULT 0x00000000
5624#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_SCOPE_DEFAULT 0x00000000
5625#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_SLICER_CTRL_DEFAULT 0x00000077
5626#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST_DEFAULT 0x00000007
5627#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN_DEFAULT 0x00000000
5628#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN_DEFAULT 0x00000000
5629#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE_DEFAULT 0x00000000
5630#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK_DEFAULT 0x00000000
5631#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_STATUS_0_DEFAULT 0x00000000
5632#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_ANA_STATUS_1_DEFAULT 0x00000000
5633#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_MEAS_DEFAULT 0x00000000
5634#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_PWR_OVRD_DEFAULT 0x00000000
5635#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ALT_BUS_DEFAULT 0x00000000
5636#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB1_DEFAULT 0x00000000
5637#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_ATB2_DEFAULT 0x00000000
5638#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_VBOOST_DEFAULT 0x00000000
5639#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_TERM_CODE_DN_DEFAULT 0x00000000
5640#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_TERM_CODE_UP_DEFAULT 0x000000fe
5641#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_IBOOST_CODE_DEFAULT 0x00000000
5642#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_OVRD_CLK_DEFAULT 0x00000000
5643#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_TX_MISC_DEFAULT 0x00000000
5644#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_IQSKEW_DEFAULT 0x00000000
5645#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_DCC_OVRD_DEFAULT 0x00000000
5646#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL1_DEFAULT 0x00000000
5647#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_REGREF_DEFAULT 0x00000000
5648#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CDR_AFE_DEFAULT 0x000000f0
5649#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_PWR_CTRL2_DEFAULT 0x00000000
5650#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_MISC_OVRD_DEFAULT 0x00000000
5651#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CAL_MUXA_DEFAULT 0x00000000
5652#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_MEAS1_DEFAULT 0x00000000
5653#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_MEAS2_DEFAULT 0x00000000
5654#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_CAL_MUXB_DEFAULT 0x00000000
5655#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_TERM_DEFAULT 0x00000000
5656#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_SLC_CTRL_DEFAULT 0x00000000
5657#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE1_ANA_RX_ATB_VREG_DEFAULT 0x00000000
5658#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_LANE_OVRD_IN_DEFAULT 0x00000000
5659#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_0_DEFAULT 0x00000000
5660#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_1_DEFAULT 0x00005078
5661#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_IN_2_DEFAULT 0x00000000
5662#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_OVRD_OUT_DEFAULT 0x00000000
5663#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_0_DEFAULT 0x00000000
5664#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_1_DEFAULT 0x00000014
5665#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_2_DEFAULT 0x000003e8
5666#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_IN_3_DEFAULT 0x00000000
5667#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_0_DEFAULT 0x000037f8
5668#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_1_DEFAULT 0x00000400
5669#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_OUT_0_DEFAULT 0x00000000
5670#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_LANE_ASIC_IN_DEFAULT 0x00000000
5671#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_0_DEFAULT 0x00000000
5672#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_1_DEFAULT 0x00000000
5673#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_IN_2_DEFAULT 0x00000000
5674#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_TX_ASIC_OUT_DEFAULT 0x00000000
5675#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_0_DEFAULT 0x00000000
5676#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_IN_1_DEFAULT 0x00000000
5677#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_0_DEFAULT 0x00000000
5678#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_EQ_ASIC_IN_1_DEFAULT 0x00000000
5679#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0_DEFAULT 0x00000000
5680#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1_DEFAULT 0x00000000
5681#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_ASIC_OUT_0_DEFAULT 0x00000000
5682#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_2_DEFAULT 0x00002040
5683#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ASIC_RX_OVRD_EQ_IN_3_DEFAULT 0x00002040
5684#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0_DEFAULT 0x000000e7
5685#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P0S_DEFAULT 0x00000046
5686#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P1_DEFAULT 0x00000112
5687#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PSTATE_P2_DEFAULT 0x00000110
5688#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_0_DEFAULT 0x00001a0c
5689#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_1_DEFAULT 0x0000e6cc
5690#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_2_DEFAULT 0x00000d5d
5691#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_PWRCTL_TX_PWRUP_TIME_3_DEFAULT 0x00002907
5692#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_TX_LBERT_CTL_DEFAULT 0x00000000
5693#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0_DEFAULT 0x00000cff
5694#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P0S_DEFAULT 0x00000407
5695#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P1_DEFAULT 0x00000301
5696#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PSTATE_P2_DEFAULT 0x00000301
5697#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_0_DEFAULT 0x00000307
5698#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_1_DEFAULT 0x00001434
5699#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_TIME_2_DEFAULT 0x00000006
5700#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_PWRCTL_RX_PWRUP_CTL_0_DEFAULT 0x00000000
5701#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0_DEFAULT 0x00000002
5702#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1_DEFAULT 0x00000100
5703#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2_DEFAULT 0x00002600
5704#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0_DEFAULT 0x00003521
5705#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1_DEFAULT 0x00000002
5706#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_0_DEFAULT 0x00000000
5707#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_1_DEFAULT 0x00000000
5708#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_STAT_2_DEFAULT 0x00000000
5709#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_RX_ALIGN_XAUI_COMM_MASK_DEFAULT 0x000003ff
5710#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_LBERT_CTL_DEFAULT 0x00000000
5711#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_LBERT_ERR_DEFAULT 0x00000000
5712#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_0_DEFAULT 0x0000000f
5713#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_1_DEFAULT 0x00004c39
5714#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_2_DEFAULT 0x00004abb
5715#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_3_DEFAULT 0x000000d6
5716#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_CDR_CTL_4_DEFAULT 0x00002cdb
5717#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_CDR_STAT_DEFAULT 0x00000000
5718#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_DPLL_FREQ_DEFAULT 0x00002000
5719#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_DPLL_FREQ_BOUND_0_DEFAULT 0x000004c8
5720#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_DPLL_FREQ_BOUND_1_DEFAULT 0x0000019c
5721#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_0_DEFAULT 0x00000c10
5722#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_1_DEFAULT 0x00000009
5723#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_2_DEFAULT 0x000000c2
5724#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_3_DEFAULT 0x00000000
5725#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_4_DEFAULT 0x00000000
5726#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_5_DEFAULT 0x00000000
5727#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_6_DEFAULT 0x0000792b
5728#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_7_DEFAULT 0x00004342
5729#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_8_DEFAULT 0x00004925
5730#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ADPT_CFG_9_DEFAULT 0x00000000
5731#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_RST_ADPT_CFG_DEFAULT 0x0000001f
5732#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ATT_STATUS_DEFAULT 0x00000000
5733#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_VGA_STATUS_DEFAULT 0x00000000
5734#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_CTLE_STATUS_DEFAULT 0x00000000
5735#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP1_STATUS_DEFAULT 0x00000000
5736#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP2_STATUS_DEFAULT 0x00000000
5737#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP3_STATUS_DEFAULT 0x00000000
5738#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP4_STATUS_DEFAULT 0x00000000
5739#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_TAP5_STATUS_DEFAULT 0x00000000
5740#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST_DEFAULT 0x00000080
5741#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST_DEFAULT 0x00000080
5742#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST_DEFAULT 0x00000080
5743#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST_DEFAULT 0x00000080
5744#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN_DEFAULT 0x00000007
5745#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD_DEFAULT 0x00000007
5746#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST_DEFAULT 0x00000080
5747#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST_DEFAULT 0x00000080
5748#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL_DEFAULT 0x00000000
5749#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST_DEFAULT 0x00000080
5750#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST_DEFAULT 0x00000080
5751#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_LD_VAL_1_DEFAULT 0x00000040
5752#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_DATA_MSK_DEFAULT 0x0000ffff
5753#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL0_DEFAULT 0x00003c06
5754#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL1_DEFAULT 0x00000800
5755#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL0_DEFAULT 0x00004000
5756#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL1_DEFAULT 0x00000008
5757#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_SMPL_CNT1_DEFAULT 0x00000000
5758#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_0_DEFAULT 0x00000000
5759#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_1_DEFAULT 0x00000000
5760#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_2_DEFAULT 0x00000000
5761#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_3_DEFAULT 0x00000000
5762#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_4_DEFAULT 0x00000000
5763#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_5_DEFAULT 0x00000000
5764#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CNT_6_DEFAULT 0x00000000
5765#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_CAL_COMP_CLK_CTL_DEFAULT 0x00000019
5766#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL2_DEFAULT 0x00000000
5767#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL3_DEFAULT 0x00000000
5768#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL4_DEFAULT 0x00000000
5769#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_MATCH_CTL5_DEFAULT 0x00000000
5770#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_STAT_STAT_CTL2_DEFAULT 0x00000000
5771#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_OVRD_OUT_DEFAULT 0x00000000
5772#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT_DEFAULT 0x00000000
5773#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT_DEFAULT 0x00000000
5774#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_0_DEFAULT 0x00000000
5775#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_1_DEFAULT 0x00000000
5776#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_2_DEFAULT 0x00000000
5777#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_3_DEFAULT 0x00000000
5778#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_TX_EQ_OVRD_OUT_4_DEFAULT 0x00000000
5779#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CTL_OVRD_OUT_DEFAULT 0x00000000
5780#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_PWR_OVRD_OUT_DEFAULT 0x00000000
5781#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_0_DEFAULT 0x00000000
5782#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_VCO_OVRD_OUT_1_DEFAULT 0x00000002
5783#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_CAL_DEFAULT 0x00000000
5784#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_DAC_CTRL_DEFAULT 0x00000080
5785#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_DAC_CTRL_OVRD_DEFAULT 0x00000000
5786#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_DAC_CTRL_SEL_DEFAULT 0x00000000
5787#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_AFE_ATT_VGA_DEFAULT 0x00000000
5788#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_AFE_CTLE_DEFAULT 0x00000000
5789#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_SCOPE_DEFAULT 0x00000000
5790#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_SLICER_CTRL_DEFAULT 0x00000077
5791#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST_DEFAULT 0x00000007
5792#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_IQ_SENSE_EN_DEFAULT 0x00000000
5793#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN_DEFAULT 0x00000000
5794#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE_DEFAULT 0x00000000
5795#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK_DEFAULT 0x00000000
5796#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_STATUS_0_DEFAULT 0x00000000
5797#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_ANA_STATUS_1_DEFAULT 0x00000000
5798#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_MEAS_DEFAULT 0x00000000
5799#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_PWR_OVRD_DEFAULT 0x00000000
5800#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ALT_BUS_DEFAULT 0x00000000
5801#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB1_DEFAULT 0x00000000
5802#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_ATB2_DEFAULT 0x00000000
5803#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_VBOOST_DEFAULT 0x00000000
5804#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_TERM_CODE_DN_DEFAULT 0x00000000
5805#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_TERM_CODE_UP_DEFAULT 0x000000fe
5806#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_IBOOST_CODE_DEFAULT 0x00000000
5807#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_OVRD_CLK_DEFAULT 0x00000000
5808#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_TX_MISC_DEFAULT 0x00000000
5809#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_IQSKEW_DEFAULT 0x00000000
5810#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_DCC_OVRD_DEFAULT 0x00000000
5811#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL1_DEFAULT 0x00000000
5812#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_REGREF_DEFAULT 0x00000000
5813#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CDR_AFE_DEFAULT 0x000000f0
5814#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_PWR_CTRL2_DEFAULT 0x00000000
5815#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_MISC_OVRD_DEFAULT 0x00000000
5816#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CAL_MUXA_DEFAULT 0x00000000
5817#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_MEAS1_DEFAULT 0x00000000
5818#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_MEAS2_DEFAULT 0x00000000
5819#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_CAL_MUXB_DEFAULT 0x00000000
5820#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_TERM_DEFAULT 0x00000000
5821#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_SLC_CTRL_DEFAULT 0x00000000
5822#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE2_ANA_RX_ATB_VREG_DEFAULT 0x00000000
5823#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_LANE_OVRD_IN_DEFAULT 0x00000000
5824#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_0_DEFAULT 0x00000000
5825#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_1_DEFAULT 0x00005078
5826#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_IN_2_DEFAULT 0x00000000
5827#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_OVRD_OUT_DEFAULT 0x00000000
5828#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_0_DEFAULT 0x00000000
5829#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_1_DEFAULT 0x00000014
5830#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_2_DEFAULT 0x000003e8
5831#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_IN_3_DEFAULT 0x00000000
5832#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_0_DEFAULT 0x000037f8
5833#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_1_DEFAULT 0x00000400
5834#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_OUT_0_DEFAULT 0x00000000
5835#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_LANE_ASIC_IN_DEFAULT 0x00000000
5836#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_0_DEFAULT 0x00000000
5837#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_1_DEFAULT 0x00000000
5838#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_IN_2_DEFAULT 0x00000000
5839#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_TX_ASIC_OUT_DEFAULT 0x00000000
5840#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_0_DEFAULT 0x00000000
5841#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_IN_1_DEFAULT 0x00000000
5842#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_0_DEFAULT 0x00000000
5843#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_EQ_ASIC_IN_1_DEFAULT 0x00000000
5844#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0_DEFAULT 0x00000000
5845#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1_DEFAULT 0x00000000
5846#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_ASIC_OUT_0_DEFAULT 0x00000000
5847#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_2_DEFAULT 0x00002040
5848#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ASIC_RX_OVRD_EQ_IN_3_DEFAULT 0x00002040
5849#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0_DEFAULT 0x000000e7
5850#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P0S_DEFAULT 0x00000046
5851#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P1_DEFAULT 0x00000112
5852#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PSTATE_P2_DEFAULT 0x00000110
5853#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_0_DEFAULT 0x00001a0c
5854#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_1_DEFAULT 0x0000e6cc
5855#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_2_DEFAULT 0x00000d5d
5856#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_PWRCTL_TX_PWRUP_TIME_3_DEFAULT 0x00002907
5857#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_TX_LBERT_CTL_DEFAULT 0x00000000
5858#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0_DEFAULT 0x00000cff
5859#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P0S_DEFAULT 0x00000407
5860#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P1_DEFAULT 0x00000301
5861#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PSTATE_P2_DEFAULT 0x00000301
5862#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_0_DEFAULT 0x00000307
5863#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_1_DEFAULT 0x00001434
5864#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_TIME_2_DEFAULT 0x00000006
5865#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_PWRCTL_RX_PWRUP_CTL_0_DEFAULT 0x00000000
5866#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0_DEFAULT 0x00000002
5867#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1_DEFAULT 0x00000100
5868#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2_DEFAULT 0x00002600
5869#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0_DEFAULT 0x00003521
5870#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1_DEFAULT 0x00000002
5871#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_0_DEFAULT 0x00000000
5872#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_1_DEFAULT 0x00000000
5873#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_STAT_2_DEFAULT 0x00000000
5874#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_RX_ALIGN_XAUI_COMM_MASK_DEFAULT 0x000003ff
5875#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_LBERT_CTL_DEFAULT 0x00000000
5876#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_LBERT_ERR_DEFAULT 0x00000000
5877#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_0_DEFAULT 0x0000000f
5878#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_1_DEFAULT 0x00004c39
5879#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_2_DEFAULT 0x00004abb
5880#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_3_DEFAULT 0x000000d6
5881#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_CDR_CTL_4_DEFAULT 0x00002cdb
5882#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_CDR_STAT_DEFAULT 0x00000000
5883#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_DPLL_FREQ_DEFAULT 0x00002000
5884#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_DPLL_FREQ_BOUND_0_DEFAULT 0x000004c8
5885#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_DPLL_FREQ_BOUND_1_DEFAULT 0x0000019c
5886#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_0_DEFAULT 0x00000c10
5887#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_1_DEFAULT 0x00000009
5888#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_2_DEFAULT 0x000000c2
5889#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_3_DEFAULT 0x00000000
5890#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_4_DEFAULT 0x00000000
5891#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_5_DEFAULT 0x00000000
5892#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_6_DEFAULT 0x0000792b
5893#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_7_DEFAULT 0x00004342
5894#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_8_DEFAULT 0x00004925
5895#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ADPT_CFG_9_DEFAULT 0x00000000
5896#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_RST_ADPT_CFG_DEFAULT 0x0000001f
5897#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ATT_STATUS_DEFAULT 0x00000000
5898#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_VGA_STATUS_DEFAULT 0x00000000
5899#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_CTLE_STATUS_DEFAULT 0x00000000
5900#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP1_STATUS_DEFAULT 0x00000000
5901#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP2_STATUS_DEFAULT 0x00000000
5902#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP3_STATUS_DEFAULT 0x00000000
5903#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP4_STATUS_DEFAULT 0x00000000
5904#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_TAP5_STATUS_DEFAULT 0x00000000
5905#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST_DEFAULT 0x00000080
5906#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST_DEFAULT 0x00000080
5907#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST_DEFAULT 0x00000080
5908#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST_DEFAULT 0x00000080
5909#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN_DEFAULT 0x00000007
5910#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD_DEFAULT 0x00000007
5911#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST_DEFAULT 0x00000080
5912#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST_DEFAULT 0x00000080
5913#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL_DEFAULT 0x00000000
5914#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST_DEFAULT 0x00000080
5915#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST_DEFAULT 0x00000080
5916#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_LD_VAL_1_DEFAULT 0x00000040
5917#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_DATA_MSK_DEFAULT 0x0000ffff
5918#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL0_DEFAULT 0x00003c06
5919#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL1_DEFAULT 0x00000800
5920#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL0_DEFAULT 0x00004000
5921#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL1_DEFAULT 0x00000008
5922#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_SMPL_CNT1_DEFAULT 0x00000000
5923#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_0_DEFAULT 0x00000000
5924#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_1_DEFAULT 0x00000000
5925#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_2_DEFAULT 0x00000000
5926#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_3_DEFAULT 0x00000000
5927#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_4_DEFAULT 0x00000000
5928#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_5_DEFAULT 0x00000000
5929#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CNT_6_DEFAULT 0x00000000
5930#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_CAL_COMP_CLK_CTL_DEFAULT 0x00000019
5931#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL2_DEFAULT 0x00000000
5932#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL3_DEFAULT 0x00000000
5933#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL4_DEFAULT 0x00000000
5934#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_MATCH_CTL5_DEFAULT 0x00000000
5935#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_STAT_STAT_CTL2_DEFAULT 0x00000000
5936#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_OVRD_OUT_DEFAULT 0x00000000
5937#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT_DEFAULT 0x00000000
5938#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT_DEFAULT 0x00000000
5939#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_0_DEFAULT 0x00000000
5940#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_1_DEFAULT 0x00000000
5941#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_2_DEFAULT 0x00000000
5942#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_3_DEFAULT 0x00000000
5943#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_TX_EQ_OVRD_OUT_4_DEFAULT 0x00000000
5944#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CTL_OVRD_OUT_DEFAULT 0x00000000
5945#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_PWR_OVRD_OUT_DEFAULT 0x00000000
5946#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_0_DEFAULT 0x00000000
5947#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_VCO_OVRD_OUT_1_DEFAULT 0x00000002
5948#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_CAL_DEFAULT 0x00000000
5949#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_DAC_CTRL_DEFAULT 0x00000080
5950#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_DAC_CTRL_OVRD_DEFAULT 0x00000000
5951#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_DAC_CTRL_SEL_DEFAULT 0x00000000
5952#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_AFE_ATT_VGA_DEFAULT 0x00000000
5953#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_AFE_CTLE_DEFAULT 0x00000000
5954#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_SCOPE_DEFAULT 0x00000000
5955#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_SLICER_CTRL_DEFAULT 0x00000077
5956#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST_DEFAULT 0x00000007
5957#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_IQ_SENSE_EN_DEFAULT 0x00000000
5958#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN_DEFAULT 0x00000000
5959#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE_DEFAULT 0x00000000
5960#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK_DEFAULT 0x00000000
5961#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_STATUS_0_DEFAULT 0x00000000
5962#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_ANA_STATUS_1_DEFAULT 0x00000000
5963#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_MEAS_DEFAULT 0x00000000
5964#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_PWR_OVRD_DEFAULT 0x00000000
5965#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ALT_BUS_DEFAULT 0x00000000
5966#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB1_DEFAULT 0x00000000
5967#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_ATB2_DEFAULT 0x00000000
5968#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_VBOOST_DEFAULT 0x00000000
5969#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_TERM_CODE_DN_DEFAULT 0x00000000
5970#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_TERM_CODE_UP_DEFAULT 0x000000fe
5971#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_IBOOST_CODE_DEFAULT 0x00000000
5972#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_OVRD_CLK_DEFAULT 0x00000000
5973#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_TX_MISC_DEFAULT 0x00000000
5974#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_IQSKEW_DEFAULT 0x00000000
5975#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_DCC_OVRD_DEFAULT 0x00000000
5976#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL1_DEFAULT 0x00000000
5977#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_REGREF_DEFAULT 0x00000000
5978#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CDR_AFE_DEFAULT 0x000000f0
5979#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_PWR_CTRL2_DEFAULT 0x00000000
5980#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_MISC_OVRD_DEFAULT 0x00000000
5981#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CAL_MUXA_DEFAULT 0x00000000
5982#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_MEAS1_DEFAULT 0x00000000
5983#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_MEAS2_DEFAULT 0x00000000
5984#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_CAL_MUXB_DEFAULT 0x00000000
5985#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_TERM_DEFAULT 0x00000000
5986#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_SLC_CTRL_DEFAULT 0x00000000
5987#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANE3_ANA_RX_ATB_VREG_DEFAULT 0x00000000
5988#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R0_DEFAULT 0x00005306
5989#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R1_DEFAULT 0x00001f4f
5990#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R2_DEFAULT 0x0000297c
5991#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R3_DEFAULT 0x00000181
5992#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R4_DEFAULT 0x00005555
5993#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R5_DEFAULT 0x00000182
5994#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R6_DEFAULT 0x00001400
5995#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R7_DEFAULT 0x00000183
5996#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R8_DEFAULT 0x00000000
5997#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R9_DEFAULT 0x000001af
5998#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R10_DEFAULT 0x00000012
5999#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R11_DEFAULT 0x00000800
6000#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R12_DEFAULT 0x00000750
6001#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R13_DEFAULT 0x00000807
6002#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R14_DEFAULT 0x00000212
6003#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R15_DEFAULT 0x00001f27
6004#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R16_DEFAULT 0x00004214
6005#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R17_DEFAULT 0x00005306
6006#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R18_DEFAULT 0x00001f50
6007#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R19_DEFAULT 0x0000297d
6008#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R20_DEFAULT 0x000001a8
6009#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R21_DEFAULT 0x00000140
6010#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R22_DEFAULT 0x00000181
6011#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R23_DEFAULT 0x0000aaaa
6012#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R24_DEFAULT 0x00000182
6013#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R25_DEFAULT 0x00002800
6014#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R26_DEFAULT 0x00000183
6015#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R27_DEFAULT 0x00000000
6016#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R28_DEFAULT 0x00000184
6017#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R29_DEFAULT 0x00006800
6018#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R30_DEFAULT 0x000001af
6019#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B0_R31_DEFAULT 0x00000014
6020#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R0_DEFAULT 0x00000800
6021#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R1_DEFAULT 0x00000745
6022#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R2_DEFAULT 0x00000807
6023#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R3_DEFAULT 0x00000227
6024#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R4_DEFAULT 0x00001f27
6025#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R5_DEFAULT 0x00004227
6026#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R6_DEFAULT 0x00005306
6027#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R7_DEFAULT 0x00000181
6028#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R8_DEFAULT 0x00005555
6029#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R9_DEFAULT 0x00000182
6030#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R10_DEFAULT 0x00001400
6031#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R11_DEFAULT 0x00000183
6032#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R12_DEFAULT 0x00000000
6033#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R13_DEFAULT 0x000001af
6034#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R14_DEFAULT 0x00000015
6035#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R15_DEFAULT 0x00000800
6036#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R16_DEFAULT 0x00000746
6037#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R17_DEFAULT 0x00000807
6038#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R18_DEFAULT 0x00000236
6039#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R19_DEFAULT 0x00001f27
6040#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R20_DEFAULT 0x00004236
6041#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R21_DEFAULT 0x00005306
6042#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R22_DEFAULT 0x000001b3
6043#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R23_DEFAULT 0x00000177
6044#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R24_DEFAULT 0x000055dc
6045#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R25_DEFAULT 0x00000181
6046#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R26_DEFAULT 0x0000aaaa
6047#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R27_DEFAULT 0x00000182
6048#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R28_DEFAULT 0x00002800
6049#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R29_DEFAULT 0x00000183
6050#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R30_DEFAULT 0x00000000
6051#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B1_R31_DEFAULT 0x00000184
6052#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R0_DEFAULT 0x00007000
6053#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R1_DEFAULT 0x000001af
6054#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R2_DEFAULT 0x00000010
6055#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R3_DEFAULT 0x00000800
6056#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R4_DEFAULT 0x00000173
6057#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R5_DEFAULT 0x00000807
6058#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R6_DEFAULT 0x0000024a
6059#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R7_DEFAULT 0x00001f26
6060#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R8_DEFAULT 0x0000424a
6061#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R9_DEFAULT 0x00005306
6062#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R10_DEFAULT 0x000055fb
6063#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R11_DEFAULT 0x000001af
6064#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R12_DEFAULT 0x00000011
6065#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R13_DEFAULT 0x00000800
6066#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R14_DEFAULT 0x00000174
6067#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R15_DEFAULT 0x00000807
6068#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R16_DEFAULT 0x00000254
6069#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R17_DEFAULT 0x00001f26
6070#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R18_DEFAULT 0x00004254
6071#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R19_DEFAULT 0x00005306
6072#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R20_DEFAULT 0x00005612
6073#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R21_DEFAULT 0x00000184
6074#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R22_DEFAULT 0x00006c00
6075#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R23_DEFAULT 0x000001af
6076#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R24_DEFAULT 0x00000016
6077#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R25_DEFAULT 0x00000800
6078#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R26_DEFAULT 0x00000179
6079#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R27_DEFAULT 0x00000807
6080#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R28_DEFAULT 0x00000260
6081#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R29_DEFAULT 0x00001f26
6082#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R30_DEFAULT 0x00004260
6083#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B2_R31_DEFAULT 0x00005306
6084#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R0_DEFAULT 0x00005625
6085#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R1_DEFAULT 0x00000181
6086#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R2_DEFAULT 0x00005555
6087#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R3_DEFAULT 0x00000182
6088#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R4_DEFAULT 0x00001400
6089#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R5_DEFAULT 0x00000183
6090#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R6_DEFAULT 0x00000000
6091#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R7_DEFAULT 0x00000184
6092#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R8_DEFAULT 0x00007000
6093#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R9_DEFAULT 0x000001af
6094#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R10_DEFAULT 0x00000012
6095#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R11_DEFAULT 0x00000800
6096#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R12_DEFAULT 0x00000175
6097#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R13_DEFAULT 0x00000807
6098#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R14_DEFAULT 0x00000272
6099#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R15_DEFAULT 0x00001f26
6100#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R16_DEFAULT 0x00004272
6101#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R17_DEFAULT 0x00005306
6102#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R18_DEFAULT 0x00005642
6103#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R19_DEFAULT 0x000001af
6104#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R20_DEFAULT 0x00000013
6105#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R21_DEFAULT 0x00000800
6106#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R22_DEFAULT 0x00000176
6107#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R23_DEFAULT 0x00000807
6108#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R24_DEFAULT 0x0000027c
6109#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R25_DEFAULT 0x00001f26
6110#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R26_DEFAULT 0x0000427c
6111#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R27_DEFAULT 0x00005306
6112#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R28_DEFAULT 0x00005659
6113#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R29_DEFAULT 0x00000184
6114#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R30_DEFAULT 0x00006c00
6115#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B3_R31_DEFAULT 0x000001af
6116#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R0_DEFAULT 0x00000018
6117#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R1_DEFAULT 0x00000800
6118#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R2_DEFAULT 0x0000017a
6119#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R3_DEFAULT 0x00000807
6120#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R4_DEFAULT 0x00000288
6121#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R5_DEFAULT 0x00001f26
6122#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R6_DEFAULT 0x00004288
6123#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R7_DEFAULT 0x00005306
6124#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R8_DEFAULT 0x00001973
6125#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R9_DEFAULT 0x000029ad
6126#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R10_DEFAULT 0x000001af
6127#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R11_DEFAULT 0x00000010
6128#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R12_DEFAULT 0x000001b6
6129#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R13_DEFAULT 0x00000001
6130#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R14_DEFAULT 0x00001974
6131#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R15_DEFAULT 0x000029ad
6132#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R16_DEFAULT 0x000001af
6133#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R17_DEFAULT 0x00000011
6134#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R18_DEFAULT 0x000001b6
6135#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R19_DEFAULT 0x00000001
6136#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R20_DEFAULT 0x00001979
6137#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R21_DEFAULT 0x000029ad
6138#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R22_DEFAULT 0x000001af
6139#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R23_DEFAULT 0x00000016
6140#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R24_DEFAULT 0x000001b6
6141#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R25_DEFAULT 0x00000001
6142#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R26_DEFAULT 0x00001975
6143#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R27_DEFAULT 0x000029ad
6144#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R28_DEFAULT 0x000001af
6145#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R29_DEFAULT 0x00000012
6146#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R30_DEFAULT 0x000001b6
6147#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B4_R31_DEFAULT 0x00000001
6148#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R0_DEFAULT 0x00001976
6149#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R1_DEFAULT 0x000029ad
6150#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R2_DEFAULT 0x000001af
6151#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R3_DEFAULT 0x00000013
6152#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R4_DEFAULT 0x000001b6
6153#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R5_DEFAULT 0x00000001
6154#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R6_DEFAULT 0x0000197a
6155#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R7_DEFAULT 0x000029ad
6156#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R8_DEFAULT 0x000001af
6157#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R9_DEFAULT 0x00000018
6158#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R10_DEFAULT 0x000001b6
6159#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R11_DEFAULT 0x00000001
6160#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R12_DEFAULT 0x00001973
6161#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R13_DEFAULT 0x00002f4b
6162#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R14_DEFAULT 0x00001974
6163#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R15_DEFAULT 0x00002f4c
6164#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R16_DEFAULT 0x00001979
6165#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R17_DEFAULT 0x00002f51
6166#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R18_DEFAULT 0x00001975
6167#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R19_DEFAULT 0x00002f4d
6168#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R20_DEFAULT 0x00001976
6169#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R21_DEFAULT 0x00002f4e
6170#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R22_DEFAULT 0x0000197a
6171#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R23_DEFAULT 0x00002f52
6172#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R24_DEFAULT 0x000001a8
6173#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R25_DEFAULT 0x00000100
6174#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R26_DEFAULT 0x00001f4f
6175#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R27_DEFAULT 0x000029ad
6176#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R28_DEFAULT 0x000001af
6177#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R29_DEFAULT 0x00000010
6178#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R30_DEFAULT 0x000001b6
6179#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B5_R31_DEFAULT 0x00000001
6180#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R0_DEFAULT 0x00001f50
6181#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R1_DEFAULT 0x000029ad
6182#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R2_DEFAULT 0x000001af
6183#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R3_DEFAULT 0x00000012
6184#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R4_DEFAULT 0x000001b6
6185#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R5_DEFAULT 0x00000001
6186#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R6_DEFAULT 0x00001f42
6187#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R7_DEFAULT 0x000029ad
6188#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R8_DEFAULT 0x000001af
6189#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R9_DEFAULT 0x00000003
6190#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R10_DEFAULT 0x000001b6
6191#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R11_DEFAULT 0x00000001
6192#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R12_DEFAULT 0x00001f43
6193#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R13_DEFAULT 0x000029ad
6194#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R14_DEFAULT 0x000001af
6195#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R15_DEFAULT 0x00000004
6196#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R16_DEFAULT 0x000001b6
6197#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R17_DEFAULT 0x00000001
6198#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R18_DEFAULT 0x00001f44
6199#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R19_DEFAULT 0x000029ad
6200#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R20_DEFAULT 0x000001af
6201#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R21_DEFAULT 0x00000005
6202#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R22_DEFAULT 0x000001b6
6203#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R23_DEFAULT 0x00000001
6204#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R24_DEFAULT 0x00001f29
6205#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R25_DEFAULT 0x000042f1
6206#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R26_DEFAULT 0x000001ac
6207#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R27_DEFAULT 0x0000a3a0
6208#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R28_DEFAULT 0x00000180
6209#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R29_DEFAULT 0x000003ff
6210#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R30_DEFAULT 0x00000181
6211#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B6_R31_DEFAULT 0x00000001
6212#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R0_DEFAULT 0x00000182
6213#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R1_DEFAULT 0x00000000
6214#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R2_DEFAULT 0x00000183
6215#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R3_DEFAULT 0x00000000
6216#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R4_DEFAULT 0x00000184
6217#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R5_DEFAULT 0x00004000
6218#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R6_DEFAULT 0x000001b5
6219#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R7_DEFAULT 0x00000001
6220#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R8_DEFAULT 0x000001b4
6221#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R9_DEFAULT 0x00000000
6222#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R10_DEFAULT 0x000001b8
6223#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R11_DEFAULT 0x00000001
6224#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R12_DEFAULT 0x00000800
6225#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R13_DEFAULT 0x00000749
6226#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R14_DEFAULT 0x00000807
6227#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R15_DEFAULT 0x000002f5
6228#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R16_DEFAULT 0x00005329
6229#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R17_DEFAULT 0x000001b4
6230#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R18_DEFAULT 0x00000007
6231#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R19_DEFAULT 0x000001b8
6232#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R20_DEFAULT 0x00000001
6233#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R21_DEFAULT 0x000001b5
6234#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R22_DEFAULT 0x00000000
6235#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R23_DEFAULT 0x000019b4
6236#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R24_DEFAULT 0x00002f53
6237#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R25_DEFAULT 0x000001ac
6238#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R26_DEFAULT 0x00000000
6239#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R27_DEFAULT 0x000001b3
6240#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R28_DEFAULT 0x00000077
6241#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R29_DEFAULT 0x00000100
6242#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R30_DEFAULT 0x00000000
6243#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN2_B7_R31_DEFAULT 0x000001a8
6244#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R0_DEFAULT 0x00000000
6245#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R1_DEFAULT 0x000001ae
6246#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R2_DEFAULT 0x00000000
6247#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R3_DEFAULT 0x000001b6
6248#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R4_DEFAULT 0x00000001
6249#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R5_DEFAULT 0x00005806
6250#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R6_DEFAULT 0x00009080
6251#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R7_DEFAULT 0x00000801
6252#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R8_DEFAULT 0x00000000
6253#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R9_DEFAULT 0x00008660
6254#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R10_DEFAULT 0x00004b15
6255#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R11_DEFAULT 0x00008270
6256#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R12_DEFAULT 0x00004b0e
6257#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R13_DEFAULT 0x0000530f
6258#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R14_DEFAULT 0x00005807
6259#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R15_DEFAULT 0x00007e10
6260#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R16_DEFAULT 0x00000805
6261#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R17_DEFAULT 0x00000001
6262#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R18_DEFAULT 0x00004b1c
6263#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R19_DEFAULT 0x000031c0
6264#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R20_DEFAULT 0x00005807
6265#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R21_DEFAULT 0x00007a10
6266#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R22_DEFAULT 0x00000805
6267#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R23_DEFAULT 0x00000000
6268#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R24_DEFAULT 0x000030d2
6269#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R25_DEFAULT 0x0000618d
6270#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R26_DEFAULT 0x00004313
6271#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R27_DEFAULT 0x0000302d
6272#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R28_DEFAULT 0x000029ad
6273#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R29_DEFAULT 0x000001b6
6274#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R30_DEFAULT 0x00000001
6275#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B0_R31_DEFAULT 0x0000301d
6276#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R0_DEFAULT 0x00004325
6277#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R1_DEFAULT 0x00000801
6278#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R2_DEFAULT 0x00000001
6279#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R3_DEFAULT 0x00003054
6280#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R4_DEFAULT 0x00005327
6281#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R5_DEFAULT 0x00007445
6282#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R6_DEFAULT 0x0000430e
6283#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R7_DEFAULT 0x0000900d
6284#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R8_DEFAULT 0x00005309
6285#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R9_DEFAULT 0x00009080
6286#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R10_DEFAULT 0x00008670
6287#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R11_DEFAULT 0x00004b2d
6288#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R12_DEFAULT 0x0000532e
6289#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R13_DEFAULT 0x00005807
6290#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R14_DEFAULT 0x00007a10
6291#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R15_DEFAULT 0x00000801
6292#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R16_DEFAULT 0x0000ffe8
6293#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R17_DEFAULT 0x0000701d
6294#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R18_DEFAULT 0x00004b35
6295#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R19_DEFAULT 0x000031c0
6296#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R20_DEFAULT 0x0000532d
6297#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R21_DEFAULT 0x0000741d
6298#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R22_DEFAULT 0x00000802
6299#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R23_DEFAULT 0x0000074a
6300#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R24_DEFAULT 0x00000803
6301#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R25_DEFAULT 0x000001b4
6302#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R26_DEFAULT 0x00003323
6303#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R27_DEFAULT 0x000001b8
6304#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R28_DEFAULT 0x00000001
6305#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R29_DEFAULT 0x0000900d
6306#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R30_DEFAULT 0x0000532a
6307#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B1_R31_DEFAULT 0x00001f2a
6308#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R0_DEFAULT 0x00004377
6309#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R1_DEFAULT 0x0000075e
6310#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R2_DEFAULT 0x00000000
6311#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R3_DEFAULT 0x0000080e
6312#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R4_DEFAULT 0x000000fe
6313#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R5_DEFAULT 0x00001f09
6314#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R6_DEFAULT 0x0000080e
6315#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R7_DEFAULT 0x0000ffff
6316#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R8_DEFAULT 0x0000080c
6317#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R9_DEFAULT 0x00000080
6318#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R10_DEFAULT 0x000070cd
6319#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R11_DEFAULT 0x0000080f
6320#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R12_DEFAULT 0x000003ff
6321#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R13_DEFAULT 0x00002f05
6322#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R14_DEFAULT 0x000030d0
6323#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R15_DEFAULT 0x0000080f
6324#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R16_DEFAULT 0x0000ffff
6325#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R17_DEFAULT 0x0000070e
6326#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R18_DEFAULT 0x00000000
6327#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R19_DEFAULT 0x0000070e
6328#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R20_DEFAULT 0x00000002
6329#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R21_DEFAULT 0x00000706
6330#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R22_DEFAULT 0x0000000c
6331#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R23_DEFAULT 0x00001f0f
6332#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R24_DEFAULT 0x0000435a
6333#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R25_DEFAULT 0x00005357
6334#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R26_DEFAULT 0x00000706
6335#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R27_DEFAULT 0x00000008
6336#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R28_DEFAULT 0x00001f0f
6337#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R29_DEFAULT 0x0000435c
6338#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R30_DEFAULT 0x0000080e
6339#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B2_R31_DEFAULT 0x00000600
6340#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R0_DEFAULT 0x00001f09
6341#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R1_DEFAULT 0x0000080e
6342#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R2_DEFAULT 0x0000ffff
6343#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R3_DEFAULT 0x0000608d
6344#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R4_DEFAULT 0x0000700d
6345#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R5_DEFAULT 0x0000080f
6346#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R6_DEFAULT 0x000003ff
6347#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R7_DEFAULT 0x00002f05
6348#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R8_DEFAULT 0x0000080f
6349#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R9_DEFAULT 0x0000ffff
6350#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R10_DEFAULT 0x00000706
6351#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R11_DEFAULT 0x0000000c
6352#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R12_DEFAULT 0x00001f0f
6353#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R13_DEFAULT 0x0000436f
6354#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R14_DEFAULT 0x0000536c
6355#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R15_DEFAULT 0x00000706
6356#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R16_DEFAULT 0x00000000
6357#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R17_DEFAULT 0x00001f0f
6358#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R18_DEFAULT 0x00004371
6359#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R19_DEFAULT 0x00000705
6360#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R20_DEFAULT 0x0000000c
6361#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R21_DEFAULT 0x0000070e
6362#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R22_DEFAULT 0x00000000
6363#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R23_DEFAULT 0x0000078d
6364#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R24_DEFAULT 0x00000010
6365#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R25_DEFAULT 0x00000147
6366#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R26_DEFAULT 0x00000001
6367#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R27_DEFAULT 0x000001a8
6368#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R28_DEFAULT 0x00000000
6369#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R29_DEFAULT 0x00001f6b
6370#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R30_DEFAULT 0x00002960
6371#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B3_R31_DEFAULT 0x00000161
6372#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R0_DEFAULT 0x00000200
6373#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R1_DEFAULT 0x00000162
6374#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R2_DEFAULT 0x00000042
6375#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R3_DEFAULT 0x00000163
6376#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R4_DEFAULT 0x0000007e
6377#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R5_DEFAULT 0x00000164
6378#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R6_DEFAULT 0x00000000
6379#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R7_DEFAULT 0x00000165
6380#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R8_DEFAULT 0x00000000
6381#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R9_DEFAULT 0x00000166
6382#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R10_DEFAULT 0x0000792b
6383#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R11_DEFAULT 0x00000167
6384#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R12_DEFAULT 0x00004342
6385#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R13_DEFAULT 0x00000168
6386#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R14_DEFAULT 0x00000000
6387#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R15_DEFAULT 0x00000801
6388#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R16_DEFAULT 0x00003636
6389#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R17_DEFAULT 0x00001752
6390#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R18_DEFAULT 0x0000608c
6391#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R19_DEFAULT 0x0000701c
6392#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R20_DEFAULT 0x000030d2
6393#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R21_DEFAULT 0x00001751
6394#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R22_DEFAULT 0x0000702c
6395#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R23_DEFAULT 0x00002969
6396#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R24_DEFAULT 0x0000016a
6397#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R25_DEFAULT 0x0000001f
6398#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R26_DEFAULT 0x00001f67
6399#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R27_DEFAULT 0x00002980
6400#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R28_DEFAULT 0x00000181
6401#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R29_DEFAULT 0x0000ffff
6402#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R30_DEFAULT 0x00000182
6403#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B4_R31_DEFAULT 0x00003c02
6404#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R0_DEFAULT 0x00000183
6405#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R1_DEFAULT 0x00000800
6406#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R2_DEFAULT 0x00000184
6407#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R3_DEFAULT 0x00007060
6408#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R4_DEFAULT 0x00000185
6409#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R5_DEFAULT 0x0000247e
6410#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R6_DEFAULT 0x00001f2a
6411#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R7_DEFAULT 0x000043a9
6412#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R8_DEFAULT 0x00008c00
6413#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R9_DEFAULT 0x00001f68
6414#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R10_DEFAULT 0x00002980
6415#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R11_DEFAULT 0x00000182
6416#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R12_DEFAULT 0x00003c06
6417#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R13_DEFAULT 0x00001f6c
6418#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R14_DEFAULT 0x00002960
6419#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R15_DEFAULT 0x00000161
6420#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R16_DEFAULT 0x00000209
6421#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R17_DEFAULT 0x00000162
6422#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R18_DEFAULT 0x000000c2
6423#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R19_DEFAULT 0x00000163
6424#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R20_DEFAULT 0x00004fa0
6425#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R21_DEFAULT 0x00000166
6426#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R22_DEFAULT 0x00007828
6427#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R23_DEFAULT 0x00000168
6428#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R24_DEFAULT 0x000036dc
6429#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R25_DEFAULT 0x00001f2b
6430#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R26_DEFAULT 0x000043bc
6431#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R27_DEFAULT 0x00008c00
6432#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R28_DEFAULT 0x00001f69
6433#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R29_DEFAULT 0x00002980
6434#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R30_DEFAULT 0x00001f6d
6435#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B5_R31_DEFAULT 0x00002960
6436#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R0_DEFAULT 0x00000166
6437#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R1_DEFAULT 0x00007818
6438#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R2_DEFAULT 0x00000168
6439#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R3_DEFAULT 0x0000124a
6440#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R4_DEFAULT 0x00001f2b
6441#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R5_DEFAULT 0x000043c7
6442#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R6_DEFAULT 0x00008c00
6443#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R7_DEFAULT 0x00001f6a
6444#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R8_DEFAULT 0x00002980
6445#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R9_DEFAULT 0x00000181
6446#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R10_DEFAULT 0x0000aaaa
6447#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R11_DEFAULT 0x00000182
6448#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R12_DEFAULT 0x00002806
6449#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R13_DEFAULT 0x00001f6e
6450#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R14_DEFAULT 0x00002960
6451#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R15_DEFAULT 0x00000162
6452#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R16_DEFAULT 0x000000c6
6453#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R17_DEFAULT 0x00000163
6454#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R18_DEFAULT 0x00001000
6455#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R19_DEFAULT 0x00000165
6456#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R20_DEFAULT 0x00003000
6457#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R21_DEFAULT 0x00000166
6458#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R22_DEFAULT 0x00007800
6459#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R23_DEFAULT 0x00000169
6460#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R24_DEFAULT 0x0000b6b6
6461#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R25_DEFAULT 0x00008e00
6462#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R26_DEFAULT 0x0000197b
6463#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R27_DEFAULT 0x0000618d
6464#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R28_DEFAULT 0x000030d0
6465#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R29_DEFAULT 0x00001f6a
6466#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R30_DEFAULT 0x00002980
6467#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B6_R31_DEFAULT 0x00001f6e
6468#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R0_DEFAULT 0x00002960
6469#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R1_DEFAULT 0x00000162
6470#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R2_DEFAULT 0x00000084
6471#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R3_DEFAULT 0x00000165
6472#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R4_DEFAULT 0x0000b000
6473#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R5_DEFAULT 0x00000169
6474#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R6_DEFAULT 0x00008080
6475#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R7_DEFAULT 0x00008e00
6476#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R8_DEFAULT 0x0000197b
6477#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R9_DEFAULT 0x0000618d
6478#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R10_DEFAULT 0x000074d0
6479#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R11_DEFAULT 0x00004bef
6480#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R12_DEFAULT 0x00000711
6481#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R13_DEFAULT 0x00000000
6482#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R14_DEFAULT 0x000053f0
6483#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R15_DEFAULT 0x00002f11
6484#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R16_DEFAULT 0x00000180
6485#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R17_DEFAULT 0x000003ff
6486#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R18_DEFAULT 0x00000181
6487#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R19_DEFAULT 0x0000ffff
6488#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R20_DEFAULT 0x00000182
6489#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R21_DEFAULT 0x00003c46
6490#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R22_DEFAULT 0x00000183
6491#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R23_DEFAULT 0x00000000
6492#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R24_DEFAULT 0x00000184
6493#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R25_DEFAULT 0x00007020
6494#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R26_DEFAULT 0x00000185
6495#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R27_DEFAULT 0x0000247e
6496#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R28_DEFAULT 0x0000080e
6497#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R29_DEFAULT 0x00008000
6498#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R30_DEFAULT 0x00001963
6499#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN3_B7_R31_DEFAULT 0x0000080e
6500#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R0_DEFAULT 0x0000ffff
6501#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R1_DEFAULT 0x00004408
6502#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R2_DEFAULT 0x0000080e
6503#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R3_DEFAULT 0x00000fe0
6504#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R4_DEFAULT 0x0000116e
6505#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R5_DEFAULT 0x0000080e
6506#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R6_DEFAULT 0x0000ffff
6507#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R7_DEFAULT 0x0000540d
6508#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R8_DEFAULT 0x0000080e
6509#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R9_DEFAULT 0x00000fc0
6510#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R10_DEFAULT 0x0000116e
6511#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R11_DEFAULT 0x0000080e
6512#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R12_DEFAULT 0x0000ffff
6513#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R13_DEFAULT 0x000030c4
6514#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R14_DEFAULT 0x0000080e
6515#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R15_DEFAULT 0x00001000
6516#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R16_DEFAULT 0x0000116e
6517#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R17_DEFAULT 0x0000080e
6518#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R18_DEFAULT 0x0000ffff
6519#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R19_DEFAULT 0x000030c5
6520#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R20_DEFAULT 0x00000801
6521#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R21_DEFAULT 0x00000036
6522#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R22_DEFAULT 0x00001751
6523#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R23_DEFAULT 0x0000701c
6524#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R24_DEFAULT 0x000030dc
6525#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R25_DEFAULT 0x00000803
6526#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R26_DEFAULT 0x00000001
6527#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R27_DEFAULT 0x00007435
6528#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R28_DEFAULT 0x00004c23
6529#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R29_DEFAULT 0x0000744c
6530#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R30_DEFAULT 0x000030d2
6531#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B0_R31_DEFAULT 0x00004c38
6532#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R0_DEFAULT 0x00000802
6533#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R1_DEFAULT 0x00000000
6534#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R2_DEFAULT 0x00005438
6535#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R3_DEFAULT 0x0000080e
6536#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R4_DEFAULT 0x00008000
6537#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R5_DEFAULT 0x00001963
6538#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R6_DEFAULT 0x0000080e
6539#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R7_DEFAULT 0x0000ffff
6540#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R8_DEFAULT 0x0000442c
6541#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R9_DEFAULT 0x00000803
6542#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R10_DEFAULT 0x00000080
6543#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R11_DEFAULT 0x0000542e
6544#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R12_DEFAULT 0x00000803
6545#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R13_DEFAULT 0x00000040
6546#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R14_DEFAULT 0x0000744c
6547#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R15_DEFAULT 0x0000703d
6548#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R16_DEFAULT 0x000030d2
6549#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R17_DEFAULT 0x00000803
6550#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R18_DEFAULT 0x00000100
6551#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R19_DEFAULT 0x0000743d
6552#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R20_DEFAULT 0x00004c36
6553#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R21_DEFAULT 0x00005438
6554#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R22_DEFAULT 0x00000802
6555#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R23_DEFAULT 0x000000ff
6556#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R24_DEFAULT 0x00006082
6557#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R25_DEFAULT 0x00006182
6558#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R26_DEFAULT 0x0000302d
6559#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R27_DEFAULT 0x000001ae
6560#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R28_DEFAULT 0x00000001
6561#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R29_DEFAULT 0x000029ad
6562#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R30_DEFAULT 0x000001af
6563#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B1_R31_DEFAULT 0x00000016
6564#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R0_DEFAULT 0x000001b6
6565#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R1_DEFAULT 0x00000001
6566#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R2_DEFAULT 0x00001752
6567#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R3_DEFAULT 0x0000701c
6568#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R4_DEFAULT 0x000030dc
6569#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R5_DEFAULT 0x00000803
6570#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R6_DEFAULT 0x00000001
6571#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R7_DEFAULT 0x00007435
6572#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R8_DEFAULT 0x00004c4f
6573#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R9_DEFAULT 0x0000744c
6574#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R10_DEFAULT 0x000030d2
6575#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R11_DEFAULT 0x00004c64
6576#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R12_DEFAULT 0x00000802
6577#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R13_DEFAULT 0x00000000
6578#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R14_DEFAULT 0x00005464
6579#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R15_DEFAULT 0x0000080e
6580#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R16_DEFAULT 0x00008000
6581#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R17_DEFAULT 0x00001963
6582#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R18_DEFAULT 0x0000080e
6583#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R19_DEFAULT 0x0000ffff
6584#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R20_DEFAULT 0x00004458
6585#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R21_DEFAULT 0x00000803
6586#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R22_DEFAULT 0x00000080
6587#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R23_DEFAULT 0x0000545a
6588#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R24_DEFAULT 0x00000803
6589#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R25_DEFAULT 0x00000040
6590#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R26_DEFAULT 0x0000744c
6591#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R27_DEFAULT 0x0000703d
6592#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R28_DEFAULT 0x000030d2
6593#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R29_DEFAULT 0x00000803
6594#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R30_DEFAULT 0x00000100
6595#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B2_R31_DEFAULT 0x0000743d
6596#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R0_DEFAULT 0x00004c62
6597#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R1_DEFAULT 0x00005464
6598#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R2_DEFAULT 0x00000802
6599#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R3_DEFAULT 0x000000ff
6600#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R4_DEFAULT 0x00006082
6601#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R5_DEFAULT 0x00006182
6602#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R6_DEFAULT 0x0000302d
6603#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R7_DEFAULT 0x000029ad
6604#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R8_DEFAULT 0x000001af
6605#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R9_DEFAULT 0x00000018
6606#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R10_DEFAULT 0x000001b6
6607#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R11_DEFAULT 0x00000001
6608#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R12_DEFAULT 0x000001ae
6609#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R13_DEFAULT 0x00000000
6610#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R14_DEFAULT 0x00008647
6611#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R15_DEFAULT 0x0000080e
6612#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R16_DEFAULT 0x00007fff
6613#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R17_DEFAULT 0x00001989
6614#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R18_DEFAULT 0x0000080e
6615#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R19_DEFAULT 0x0000ffff
6616#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R20_DEFAULT 0x0000601d
6617#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R21_DEFAULT 0x000030d3
6618#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R22_DEFAULT 0x0000080e
6619#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R23_DEFAULT 0x00007fff
6620#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R24_DEFAULT 0x00001986
6621#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R25_DEFAULT 0x0000080e
6622#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R26_DEFAULT 0x0000ffff
6623#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R27_DEFAULT 0x000030d2
6624#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R28_DEFAULT 0x000030d4
6625#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R29_DEFAULT 0x0000613d
6626#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R30_DEFAULT 0x000030d1
6627#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B3_R31_DEFAULT 0x00003025
6628#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R0_DEFAULT 0x00006115
6629#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R1_DEFAULT 0x00007052
6630#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R2_DEFAULT 0x000030d2
6631#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R3_DEFAULT 0x00007021
6632#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R4_DEFAULT 0x0000743d
6633#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R5_DEFAULT 0x00004c87
6634#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R6_DEFAULT 0x0000548d
6635#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R7_DEFAULT 0x00007414
6636#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R8_DEFAULT 0x000030d2
6637#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R9_DEFAULT 0x00007052
6638#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R10_DEFAULT 0x000074d3
6639#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R11_DEFAULT 0x00004c93
6640#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R12_DEFAULT 0x00005490
6641#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R13_DEFAULT 0x00000712
6642#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R14_DEFAULT 0x00000001
6643#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R15_DEFAULT 0x00005495
6644#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R16_DEFAULT 0x00000712
6645#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R17_DEFAULT 0x00000002
6646#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R18_DEFAULT 0x00005495
6647#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R19_DEFAULT 0x00000712
6648#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R20_DEFAULT 0x00000000
6649#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R21_DEFAULT 0x00000800
6650#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R22_DEFAULT 0x00000014
6651#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R23_DEFAULT 0x00000801
6652#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R24_DEFAULT 0x00000002
6653#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R25_DEFAULT 0x00000804
6654#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R26_DEFAULT 0x00000014
6655#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R27_DEFAULT 0x00000805
6656#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R28_DEFAULT 0x00000002
6657#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R29_DEFAULT 0x0000080e
6658#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R30_DEFAULT 0x000003e0
6659#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B4_R31_DEFAULT 0x0000116d
6660#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R0_DEFAULT 0x0000080e
6661#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R1_DEFAULT 0x0000ffff
6662#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R2_DEFAULT 0x000030c2
6663#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R3_DEFAULT 0x0000080e
6664#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R4_DEFAULT 0x00000fe0
6665#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R5_DEFAULT 0x0000116e
6666#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R6_DEFAULT 0x0000080e
6667#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R7_DEFAULT 0x0000ffff
6668#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R8_DEFAULT 0x000030c3
6669#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R9_DEFAULT 0x00007420
6670#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R10_DEFAULT 0x00004cac
6671#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R11_DEFAULT 0x000054c4
6672#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R12_DEFAULT 0x0000080e
6673#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R13_DEFAULT 0x00001000
6674#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R14_DEFAULT 0x0000196e
6675#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R15_DEFAULT 0x0000080e
6676#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R16_DEFAULT 0x0000ffff
6677#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R17_DEFAULT 0x000044b5
6678#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R18_DEFAULT 0x00007434
6679#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R19_DEFAULT 0x00004cb5
6680#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R20_DEFAULT 0x000054c4
6681#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R21_DEFAULT 0x00007412
6682#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R22_DEFAULT 0x00004cb8
6683#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R23_DEFAULT 0x000054c1
6684#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R24_DEFAULT 0x0000080e
6685#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R25_DEFAULT 0x00001000
6686#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R26_DEFAULT 0x0000196e
6687#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R27_DEFAULT 0x0000080e
6688#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R28_DEFAULT 0x0000ffff
6689#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R29_DEFAULT 0x000044c1
6690#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R30_DEFAULT 0x000054bf
6691#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B5_R31_DEFAULT 0x00007453
6692#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R0_DEFAULT 0x00004cc7
6693#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R1_DEFAULT 0x00000714
6694#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R2_DEFAULT 0x00000002
6695#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R3_DEFAULT 0x000054c9
6696#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R4_DEFAULT 0x00000714
6697#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R5_DEFAULT 0x00000001
6698#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R6_DEFAULT 0x000054c9
6699#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R7_DEFAULT 0x00000714
6700#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R8_DEFAULT 0x00000000
6701#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R9_DEFAULT 0x0000196b
6702#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R10_DEFAULT 0x00002f5a
6703#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R11_DEFAULT 0x0000196d
6704#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R12_DEFAULT 0x00002f5c
6705#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R13_DEFAULT 0x0000196c
6706#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R14_DEFAULT 0x00002f5b
6707#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R15_DEFAULT 0x0000196e
6708#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R16_DEFAULT 0x00002f5d
6709#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R17_DEFAULT 0x0000196f
6710#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R18_DEFAULT 0x00002f60
6711#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R19_DEFAULT 0x00001970
6712#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R20_DEFAULT 0x00002f61
6713#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R21_DEFAULT 0x00001971
6714#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R22_DEFAULT 0x00002f62
6715#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R23_DEFAULT 0x00001972
6716#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R24_DEFAULT 0x00002f63
6717#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R25_DEFAULT 0x00000147
6718#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R26_DEFAULT 0x00000000
6719#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R27_DEFAULT 0x0000075e
6720#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R28_DEFAULT 0x00000001
6721#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R29_DEFAULT 0x0000078d
6722#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R30_DEFAULT 0x00000000
6723#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B6_R31_DEFAULT 0x00000710
6724#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R0_DEFAULT 0x00000001
6725#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R1_DEFAULT 0x00001f86
6726#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R2_DEFAULT 0x000044e4
6727#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R3_DEFAULT 0x000054e1
6728#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R4_DEFAULT 0x00000710
6729#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R5_DEFAULT 0x00000000
6730#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R6_DEFAULT 0x0000078c
6731#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R7_DEFAULT 0x00000001
6732#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R8_DEFAULT 0x00005806
6733#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R9_DEFAULT 0x0000078d
6734#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R10_DEFAULT 0x00000029
6735#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R11_DEFAULT 0x00001fe3
6736#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R12_DEFAULT 0x000044f0
6737#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R13_DEFAULT 0x00001fe4
6738#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R14_DEFAULT 0x000044f0
6739#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R15_DEFAULT 0x000054fd
6740#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R16_DEFAULT 0x00009fff
6741#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R17_DEFAULT 0x00001fe3
6742#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R18_DEFAULT 0x000044f4
6743#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R19_DEFAULT 0x000054f7
6744#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R20_DEFAULT 0x00000806
6745#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R21_DEFAULT 0x000004f7
6746#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R22_DEFAULT 0x00005500
6747#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R23_DEFAULT 0x00001fe4
6748#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R24_DEFAULT 0x000044fa
6749#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R25_DEFAULT 0x000054fd
6750#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R26_DEFAULT 0x00000806
6751#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R27_DEFAULT 0x000004fd
6752#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R28_DEFAULT 0x00005571
6753#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R29_DEFAULT 0x0000078d
6754#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R30_DEFAULT 0x00000000
6755#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN4_B7_R31_DEFAULT 0x00005027
6756#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R0_DEFAULT 0x00001f59
6757#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R1_DEFAULT 0x00004503
6758#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R2_DEFAULT 0x000054fd
6759#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R3_DEFAULT 0x000001ae
6760#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R4_DEFAULT 0x00000001
6761#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R5_DEFAULT 0x00000180
6762#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R6_DEFAULT 0x00007fff
6763#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R7_DEFAULT 0x00000181
6764#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R8_DEFAULT 0x00000001
6765#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R9_DEFAULT 0x00000182
6766#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R10_DEFAULT 0x00000000
6767#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R11_DEFAULT 0x00000183
6768#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R12_DEFAULT 0x00000000
6769#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R13_DEFAULT 0x00000184
6770#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R14_DEFAULT 0x00004000
6771#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R15_DEFAULT 0x00000185
6772#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R16_DEFAULT 0x0000247e
6773#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R17_DEFAULT 0x000001ac
6774#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R18_DEFAULT 0x0000a080
6775#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R19_DEFAULT 0x000001af
6776#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R20_DEFAULT 0x00000002
6777#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R21_DEFAULT 0x00000800
6778#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R22_DEFAULT 0x00000741
6779#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R23_DEFAULT 0x00000807
6780#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R24_DEFAULT 0x0000051a
6781#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R25_DEFAULT 0x0000553c
6782#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R26_DEFAULT 0x000001ac
6783#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R27_DEFAULT 0x0000a0c0
6784#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R28_DEFAULT 0x000001af
6785#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R29_DEFAULT 0x00000003
6786#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R30_DEFAULT 0x00000800
6787#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B0_R31_DEFAULT 0x00000742
6788#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R0_DEFAULT 0x00000807
6789#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R1_DEFAULT 0x00000523
6790#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R2_DEFAULT 0x0000553c
6791#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R3_DEFAULT 0x000001ac
6792#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R4_DEFAULT 0x0000a200
6793#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R5_DEFAULT 0x000001af
6794#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R6_DEFAULT 0x00000004
6795#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R7_DEFAULT 0x00000800
6796#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R8_DEFAULT 0x00000743
6797#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R9_DEFAULT 0x00000807
6798#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R10_DEFAULT 0x0000052c
6799#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R11_DEFAULT 0x0000553c
6800#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R12_DEFAULT 0x000001ac
6801#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R13_DEFAULT 0x0000a220
6802#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R14_DEFAULT 0x000001af
6803#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R15_DEFAULT 0x00000005
6804#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R16_DEFAULT 0x00000800
6805#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R17_DEFAULT 0x00000744
6806#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R18_DEFAULT 0x00000807
6807#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R19_DEFAULT 0x00000535
6808#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R20_DEFAULT 0x0000553c
6809#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R21_DEFAULT 0x000001ac
6810#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R22_DEFAULT 0x00002000
6811#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R23_DEFAULT 0x000001ae
6812#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R24_DEFAULT 0x00000000
6813#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R25_DEFAULT 0x000001ac
6814#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R26_DEFAULT 0x00000000
6815#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R27_DEFAULT 0x00005806
6816#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R28_DEFAULT 0x0000320d
6817#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R29_DEFAULT 0x000029ad
6818#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R30_DEFAULT 0x000001b6
6819#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B1_R31_DEFAULT 0x00000001
6820#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R0_DEFAULT 0x00009080
6821#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R1_DEFAULT 0x0000866c
6822#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R2_DEFAULT 0x00004d4b
6823#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R3_DEFAULT 0x0000827c
6824#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R4_DEFAULT 0x00004d46
6825#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R5_DEFAULT 0x00005547
6826#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R6_DEFAULT 0x00005807
6827#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R7_DEFAULT 0x00007e10
6828#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R8_DEFAULT 0x00004d50
6829#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R9_DEFAULT 0x000031c0
6830#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R10_DEFAULT 0x00005807
6831#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R11_DEFAULT 0x00007a10
6832#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R12_DEFAULT 0x000030d2
6833#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R13_DEFAULT 0x0000618d
6834#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R14_DEFAULT 0x00004549
6835#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R15_DEFAULT 0x0000302d
6836#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R16_DEFAULT 0x000029ad
6837#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R17_DEFAULT 0x000001b6
6838#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R18_DEFAULT 0x00000001
6839#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R19_DEFAULT 0x0000900d
6840#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R20_DEFAULT 0x00005807
6841#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R21_DEFAULT 0x0000320d
6842#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R22_DEFAULT 0x000029ad
6843#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R23_DEFAULT 0x000001b6
6844#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R24_DEFAULT 0x00000001
6845#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R25_DEFAULT 0x00009080
6846#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R26_DEFAULT 0x000078a5
6847#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R27_DEFAULT 0x0000744d
6848#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R28_DEFAULT 0x00004d5e
6849#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R29_DEFAULT 0x00005567
6850#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R30_DEFAULT 0x000078a4
6851#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B2_R31_DEFAULT 0x0000745d
6852#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R0_DEFAULT 0x00004d62
6853#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R1_DEFAULT 0x00005563
6854#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R2_DEFAULT 0x00005807
6855#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R3_DEFAULT 0x00007e10
6856#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R4_DEFAULT 0x00004d6c
6857#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R5_DEFAULT 0x000031c0
6858#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R6_DEFAULT 0x00005807
6859#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R7_DEFAULT 0x00007a10
6860#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R8_DEFAULT 0x000030d2
6861#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R9_DEFAULT 0x0000618d
6862#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R10_DEFAULT 0x00004565
6863#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R11_DEFAULT 0x0000302d
6864#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R12_DEFAULT 0x000029ad
6865#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R13_DEFAULT 0x000001b6
6866#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R14_DEFAULT 0x00000001
6867#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R15_DEFAULT 0x0000900d
6868#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R16_DEFAULT 0x00005807
6869#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R17_DEFAULT 0x00001f5e
6870#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R18_DEFAULT 0x00004574
6871#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R19_DEFAULT 0x000054fd
6872#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R20_DEFAULT 0x00000801
6873#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R21_DEFAULT 0x00003636
6874#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R22_DEFAULT 0x00001752
6875#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R23_DEFAULT 0x0000608c
6876#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R24_DEFAULT 0x0000701c
6877#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R25_DEFAULT 0x000030d2
6878#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R26_DEFAULT 0x00001751
6879#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R27_DEFAULT 0x0000702c
6880#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R28_DEFAULT 0x00002969
6881#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R29_DEFAULT 0x00000180
6882#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R30_DEFAULT 0x00007d00
6883#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B3_R31_DEFAULT 0x00000181
6884#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R0_DEFAULT 0x0000ffff
6885#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R1_DEFAULT 0x00000182
6886#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R2_DEFAULT 0x00003c06
6887#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R3_DEFAULT 0x00000183
6888#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R4_DEFAULT 0x00000800
6889#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R5_DEFAULT 0x00000184
6890#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R6_DEFAULT 0x00003060
6891#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R7_DEFAULT 0x00000185
6892#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R8_DEFAULT 0x0000647e
6893#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R9_DEFAULT 0x00000160
6894#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R10_DEFAULT 0x00000004
6895#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R11_DEFAULT 0x00000161
6896#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R12_DEFAULT 0x00000209
6897#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R13_DEFAULT 0x00000162
6898#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R14_DEFAULT 0x000000c2
6899#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R15_DEFAULT 0x00000163
6900#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R16_DEFAULT 0x00000f20
6901#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R17_DEFAULT 0x00000164
6902#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R18_DEFAULT 0x000090a0
6903#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R19_DEFAULT 0x00000165
6904#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R20_DEFAULT 0x00000999
6905#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R21_DEFAULT 0x00000166
6906#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R22_DEFAULT 0x00007800
6907#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R23_DEFAULT 0x00000167
6908#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R24_DEFAULT 0x00004342
6909#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R25_DEFAULT 0x00000168
6910#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R26_DEFAULT 0x00000000
6911#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R27_DEFAULT 0x0000016a
6912#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R28_DEFAULT 0x0000001f
6913#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R29_DEFAULT 0x00008c00
6914#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R30_DEFAULT 0x00000180
6915#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B4_R31_DEFAULT 0x00007d00
6916#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R0_DEFAULT 0x00000181
6917#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R1_DEFAULT 0x0000aaaa
6918#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R2_DEFAULT 0x00000182
6919#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R3_DEFAULT 0x00002806
6920#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R4_DEFAULT 0x00000183
6921#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R5_DEFAULT 0x00000800
6922#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R6_DEFAULT 0x00000184
6923#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R7_DEFAULT 0x00003060
6924#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R8_DEFAULT 0x00000185
6925#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R9_DEFAULT 0x0000647e
6926#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R10_DEFAULT 0x00000160
6927#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R11_DEFAULT 0x00003fff
6928#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R12_DEFAULT 0x00000161
6929#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R13_DEFAULT 0x00000209
6930#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R14_DEFAULT 0x00000162
6931#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R15_DEFAULT 0x000000c6
6932#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R16_DEFAULT 0x00000163
6933#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R17_DEFAULT 0x00001000
6934#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R18_DEFAULT 0x00000164
6935#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R19_DEFAULT 0x00000000
6936#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R20_DEFAULT 0x00000165
6937#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R21_DEFAULT 0x00003000
6938#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R22_DEFAULT 0x00000166
6939#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R23_DEFAULT 0x00007800
6940#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R24_DEFAULT 0x00000167
6941#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R25_DEFAULT 0x00004342
6942#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R26_DEFAULT 0x00000168
6943#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R27_DEFAULT 0x00000000
6944#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R28_DEFAULT 0x00000169
6945#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R29_DEFAULT 0x0000b6b6
6946#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R30_DEFAULT 0x0000016a
6947#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B5_R31_DEFAULT 0x0000001f
6948#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R0_DEFAULT 0x00008e00
6949#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R1_DEFAULT 0x0000197b
6950#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R2_DEFAULT 0x0000618d
6951#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R3_DEFAULT 0x000030d0
6952#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R4_DEFAULT 0x00000180
6953#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R5_DEFAULT 0x00007d00
6954#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R6_DEFAULT 0x00000160
6955#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R7_DEFAULT 0x00003fff
6956#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R8_DEFAULT 0x00000162
6957#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R9_DEFAULT 0x00000084
6958#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R10_DEFAULT 0x00000165
6959#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R11_DEFAULT 0x0000b000
6960#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R12_DEFAULT 0x00000169
6961#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R13_DEFAULT 0x00008080
6962#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R14_DEFAULT 0x00008e00
6963#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R15_DEFAULT 0x0000197b
6964#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R16_DEFAULT 0x0000618d
6965#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R17_DEFAULT 0x000030d1
6966#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R18_DEFAULT 0x00007410
6967#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R19_DEFAULT 0x00004dd7
6968#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R20_DEFAULT 0x00000711
6969#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R21_DEFAULT 0x00000000
6970#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R22_DEFAULT 0x000055d8
6971#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R23_DEFAULT 0x00002f11
6972#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R24_DEFAULT 0x00007010
6973#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R25_DEFAULT 0x0000611d
6974#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R26_DEFAULT 0x000030d2
6975#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R27_DEFAULT 0x00005806
6976#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R28_DEFAULT 0x000001af
6977#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R29_DEFAULT 0x00000010
6978#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R30_DEFAULT 0x000001ad
6979#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B6_R31_DEFAULT 0x00000080
6980#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R0_DEFAULT 0x000001b6
6981#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R1_DEFAULT 0x00000001
6982#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R2_DEFAULT 0x000001af
6983#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R3_DEFAULT 0x00000011
6984#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R4_DEFAULT 0x000001ad
6985#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R5_DEFAULT 0x00000000
6986#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R6_DEFAULT 0x000001b6
6987#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R7_DEFAULT 0x00000001
6988#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R8_DEFAULT 0x000001af
6989#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R9_DEFAULT 0x00000012
6990#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R10_DEFAULT 0x000001b6
6991#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R11_DEFAULT 0x00000001
6992#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R12_DEFAULT 0x000001af
6993#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R13_DEFAULT 0x00000013
6994#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R14_DEFAULT 0x000001b6
6995#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R15_DEFAULT 0x00000001
6996#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R16_DEFAULT 0x000001af
6997#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R17_DEFAULT 0x00000016
6998#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R18_DEFAULT 0x000001ad
6999#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R19_DEFAULT 0x000000ff
7000#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R20_DEFAULT 0x000001b6
7001#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R21_DEFAULT 0x00000001
7002#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R22_DEFAULT 0x000001af
7003#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R23_DEFAULT 0x00000018
7004#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R24_DEFAULT 0x000001b6
7005#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R25_DEFAULT 0x00000001
7006#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R26_DEFAULT 0x00005239
7007#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R27_DEFAULT 0x000001af
7008#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R28_DEFAULT 0x00000010
7009#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R29_DEFAULT 0x000001ad
7010#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R30_DEFAULT 0x00000000
7011#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN5_B7_R31_DEFAULT 0x000001b6
7012#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R0_DEFAULT 0x00000001
7013#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R1_DEFAULT 0x000001af
7014#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R2_DEFAULT 0x00000011
7015#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R3_DEFAULT 0x000001ad
7016#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R4_DEFAULT 0x00000080
7017#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R5_DEFAULT 0x000001b6
7018#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R6_DEFAULT 0x00000001
7019#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R7_DEFAULT 0x000001af
7020#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R8_DEFAULT 0x00000012
7021#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R9_DEFAULT 0x000001ad
7022#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R10_DEFAULT 0x000000ff
7023#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R11_DEFAULT 0x000001b6
7024#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R12_DEFAULT 0x00000001
7025#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R13_DEFAULT 0x000001af
7026#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R14_DEFAULT 0x00000013
7027#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R15_DEFAULT 0x000001b6
7028#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R16_DEFAULT 0x00000001
7029#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R17_DEFAULT 0x0000524b
7030#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R18_DEFAULT 0x000001af
7031#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R19_DEFAULT 0x00000011
7032#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R20_DEFAULT 0x000001ad
7033#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R21_DEFAULT 0x000000ff
7034#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R22_DEFAULT 0x000001b6
7035#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R23_DEFAULT 0x00000001
7036#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R24_DEFAULT 0x000001af
7037#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R25_DEFAULT 0x00000012
7038#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R26_DEFAULT 0x000001ad
7039#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R27_DEFAULT 0x00000000
7040#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R28_DEFAULT 0x000001b6
7041#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R29_DEFAULT 0x00000001
7042#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R30_DEFAULT 0x000001af
7043#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B0_R31_DEFAULT 0x00000016
7044#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R0_DEFAULT 0x000001ad
7045#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R1_DEFAULT 0x00000080
7046#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R2_DEFAULT 0x000001b6
7047#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R3_DEFAULT 0x00000001
7048#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R4_DEFAULT 0x00005255
7049#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R5_DEFAULT 0x000001af
7050#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R6_DEFAULT 0x00000010
7051#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R7_DEFAULT 0x000001ad
7052#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R8_DEFAULT 0x00000000
7053#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R9_DEFAULT 0x000001b6
7054#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R10_DEFAULT 0x00000001
7055#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R11_DEFAULT 0x000001af
7056#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R12_DEFAULT 0x00000011
7057#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R13_DEFAULT 0x000001b6
7058#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R14_DEFAULT 0x00000001
7059#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R15_DEFAULT 0x000001af
7060#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R16_DEFAULT 0x00000012
7061#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R17_DEFAULT 0x000001ad
7062#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R18_DEFAULT 0x00000080
7063#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R19_DEFAULT 0x000001b6
7064#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R20_DEFAULT 0x00000001
7065#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R21_DEFAULT 0x000001af
7066#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R22_DEFAULT 0x00000013
7067#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R23_DEFAULT 0x000001ad
7068#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R24_DEFAULT 0x00000000
7069#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R25_DEFAULT 0x000001b6
7070#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R26_DEFAULT 0x00000001
7071#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R27_DEFAULT 0x000001af
7072#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R28_DEFAULT 0x00000016
7073#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R29_DEFAULT 0x000001ad
7074#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R30_DEFAULT 0x000000ff
7075#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B1_R31_DEFAULT 0x000001b6
7076#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R0_DEFAULT 0x00000001
7077#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R1_DEFAULT 0x00005261
7078#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R2_DEFAULT 0x000001af
7079#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R3_DEFAULT 0x00000010
7080#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R4_DEFAULT 0x000001ad
7081#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R5_DEFAULT 0x000000ff
7082#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R6_DEFAULT 0x000001b6
7083#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R7_DEFAULT 0x00000001
7084#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R8_DEFAULT 0x000001af
7085#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R9_DEFAULT 0x00000011
7086#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R10_DEFAULT 0x000001b6
7087#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R11_DEFAULT 0x00000001
7088#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R12_DEFAULT 0x000001af
7089#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R13_DEFAULT 0x00000012
7090#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R14_DEFAULT 0x000001ad
7091#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R15_DEFAULT 0x00000000
7092#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R16_DEFAULT 0x000001b6
7093#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R17_DEFAULT 0x00000001
7094#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R18_DEFAULT 0x000001af
7095#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R19_DEFAULT 0x00000013
7096#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R20_DEFAULT 0x000001ad
7097#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R21_DEFAULT 0x00000080
7098#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R22_DEFAULT 0x000001b6
7099#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R23_DEFAULT 0x00000001
7100#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R24_DEFAULT 0x00005273
7101#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R25_DEFAULT 0x000001af
7102#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R26_DEFAULT 0x00000010
7103#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R27_DEFAULT 0x000001ad
7104#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R28_DEFAULT 0x00000000
7105#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R29_DEFAULT 0x000001b6
7106#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R30_DEFAULT 0x00000001
7107#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B2_R31_DEFAULT 0x000001af
7108#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R0_DEFAULT 0x00000012
7109#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R1_DEFAULT 0x000001ad
7110#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R2_DEFAULT 0x00000000
7111#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R3_DEFAULT 0x000001b6
7112#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R4_DEFAULT 0x00000001
7113#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R5_DEFAULT 0x000001af
7114#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R6_DEFAULT 0x00000013
7115#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R7_DEFAULT 0x000001ad
7116#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R8_DEFAULT 0x000000ff
7117#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R9_DEFAULT 0x000001b6
7118#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R10_DEFAULT 0x00000001
7119#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R11_DEFAULT 0x000001af
7120#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R12_DEFAULT 0x00000018
7121#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R13_DEFAULT 0x000001ad
7122#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R14_DEFAULT 0x00000080
7123#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R15_DEFAULT 0x000001b6
7124#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R16_DEFAULT 0x00000001
7125#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R17_DEFAULT 0x0000527d
7126#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R18_DEFAULT 0x00000000
7127#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R19_DEFAULT 0x00000000
7128#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R20_DEFAULT 0x00000000
7129#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R21_DEFAULT 0x00000000
7130#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R22_DEFAULT 0x00000000
7131#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R23_DEFAULT 0x00000000
7132#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R24_DEFAULT 0x00000000
7133#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R25_DEFAULT 0x00000000
7134#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R26_DEFAULT 0x00000000
7135#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R27_DEFAULT 0x00000000
7136#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R28_DEFAULT 0x00000000
7137#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R29_DEFAULT 0x00000000
7138#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R30_DEFAULT 0x00000000
7139#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B3_R31_DEFAULT 0x00000000
7140#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R0_DEFAULT 0x00000000
7141#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R1_DEFAULT 0x00000000
7142#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R2_DEFAULT 0x00000000
7143#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R3_DEFAULT 0x00000000
7144#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R4_DEFAULT 0x00000000
7145#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R5_DEFAULT 0x00000000
7146#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R6_DEFAULT 0x00000000
7147#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R7_DEFAULT 0x00000000
7148#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R8_DEFAULT 0x00000000
7149#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R9_DEFAULT 0x00000000
7150#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R10_DEFAULT 0x00000000
7151#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R11_DEFAULT 0x00000000
7152#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R12_DEFAULT 0x00000000
7153#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R13_DEFAULT 0x00000000
7154#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R14_DEFAULT 0x00000000
7155#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R15_DEFAULT 0x00000000
7156#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R16_DEFAULT 0x00000000
7157#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R17_DEFAULT 0x00000000
7158#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R18_DEFAULT 0x00000000
7159#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R19_DEFAULT 0x00000000
7160#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R20_DEFAULT 0x00000000
7161#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R21_DEFAULT 0x00000000
7162#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R22_DEFAULT 0x00000000
7163#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R23_DEFAULT 0x00000000
7164#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R24_DEFAULT 0x00000000
7165#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R25_DEFAULT 0x00000000
7166#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R26_DEFAULT 0x00000000
7167#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R27_DEFAULT 0x00000000
7168#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R28_DEFAULT 0x00000000
7169#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R29_DEFAULT 0x00000000
7170#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R30_DEFAULT 0x00000000
7171#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B4_R31_DEFAULT 0x00000000
7172#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R0_DEFAULT 0x00000000
7173#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R1_DEFAULT 0x00000000
7174#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R2_DEFAULT 0x00000000
7175#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R3_DEFAULT 0x00000000
7176#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R4_DEFAULT 0x00000000
7177#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R5_DEFAULT 0x00000000
7178#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R6_DEFAULT 0x00000000
7179#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R7_DEFAULT 0x00000000
7180#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R8_DEFAULT 0x00000000
7181#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R9_DEFAULT 0x00000000
7182#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R10_DEFAULT 0x00000000
7183#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R11_DEFAULT 0x00000000
7184#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R12_DEFAULT 0x00000000
7185#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R13_DEFAULT 0x00000000
7186#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R14_DEFAULT 0x00000000
7187#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R15_DEFAULT 0x00000000
7188#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R16_DEFAULT 0x00000000
7189#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R17_DEFAULT 0x00000000
7190#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R18_DEFAULT 0x00000000
7191#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R19_DEFAULT 0x00000000
7192#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R20_DEFAULT 0x00000000
7193#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R21_DEFAULT 0x00000000
7194#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R22_DEFAULT 0x00000000
7195#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R23_DEFAULT 0x00000000
7196#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R24_DEFAULT 0x00000000
7197#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R25_DEFAULT 0x00000000
7198#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R26_DEFAULT 0x00000000
7199#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R27_DEFAULT 0x00000000
7200#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R28_DEFAULT 0x00000000
7201#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R29_DEFAULT 0x00000000
7202#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R30_DEFAULT 0x00000000
7203#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B5_R31_DEFAULT 0x00000000
7204#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R0_DEFAULT 0x00000000
7205#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R1_DEFAULT 0x00000000
7206#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R2_DEFAULT 0x00000000
7207#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R3_DEFAULT 0x00000000
7208#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R4_DEFAULT 0x00000000
7209#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R5_DEFAULT 0x00000000
7210#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R6_DEFAULT 0x00000000
7211#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R7_DEFAULT 0x00000000
7212#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R8_DEFAULT 0x00000000
7213#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R9_DEFAULT 0x00000000
7214#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R10_DEFAULT 0x00000000
7215#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R11_DEFAULT 0x00000000
7216#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R12_DEFAULT 0x00000000
7217#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R13_DEFAULT 0x00000000
7218#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R14_DEFAULT 0x00000000
7219#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R15_DEFAULT 0x00000000
7220#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R16_DEFAULT 0x00000000
7221#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R17_DEFAULT 0x00000000
7222#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R18_DEFAULT 0x00000000
7223#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R19_DEFAULT 0x00000000
7224#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R20_DEFAULT 0x00000000
7225#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R21_DEFAULT 0x00000000
7226#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R22_DEFAULT 0x00000000
7227#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R23_DEFAULT 0x00000000
7228#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R24_DEFAULT 0x00000000
7229#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R25_DEFAULT 0x00000000
7230#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R26_DEFAULT 0x00000000
7231#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R27_DEFAULT 0x00000000
7232#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R28_DEFAULT 0x00000000
7233#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R29_DEFAULT 0x00000000
7234#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R30_DEFAULT 0x00000000
7235#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MEM_CMN6_B6_R31_DEFAULT 0x00000000
7236#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_CMN_CTL_DEFAULT 0x00000000
7237#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLA_BW_OVRD_IN_DEFAULT 0x00000043
7238#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_DEFAULT 0x00005000
7239#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLA_SSC_EN_OVRD_IN_DEFAULT 0x00000000
7240#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLB_BW_OVRD_IN_DEFAULT 0x00000043
7241#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_DEFAULT 0x00005000
7242#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWCMN_DIG_MPLLB_SSC_EN_OVRD_IN_DEFAULT 0x00000000
7243#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_DEFAULT 0x0000005b
7244#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1_DEFAULT 0x00000f07
7245#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_PCS_IN_DEFAULT 0x00000000
7246#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT_DEFAULT 0x00000005
7247#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_TX_PCS_OUT_DEFAULT 0x00000000
7248#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_DEFAULT 0x0000008c
7249#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1_DEFAULT 0x00000007
7250#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2_DEFAULT 0x00000000
7251#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3_DEFAULT 0x00008000
7252#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_DEFAULT 0x00000000
7253#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1_DEFAULT 0x00000000
7254#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2_DEFAULT 0x00000000
7255#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3_DEFAULT 0x00000000
7256#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4_DEFAULT 0x00000000
7257#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_DEFAULT 0x00000003
7258#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_PCS_OUT_DEFAULT 0x00000000
7259#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK_DEFAULT 0x00000000
7260#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM_DEFAULT 0x00000000
7261#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR_DEFAULT 0x00000000
7262#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR_DEFAULT 0x00000000
7263#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR_DEFAULT 0x00000000
7264#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PCS_XF_LANE_NUMBER_DEFAULT 0x00000000
7265#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FSM_OVRD_CTL_DEFAULT 0x00000000
7266#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_MEM_ADDR_MON_DEFAULT 0x00000000
7267#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_STATUS_MON_DEFAULT 0x00000000
7268#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL_DEFAULT 0x00000000
7269#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_ADAPT_DEFAULT 0x00000000
7270#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL_DEFAULT 0x00000000
7271#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL_DEFAULT 0x00000000
7272#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_BYPASS_CAL_DEFAULT 0x00000000
7273#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL_DEFAULT 0x00000000
7274#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL_DEFAULT 0x00000000
7275#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT_DEFAULT 0x00000000
7276#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT_DEFAULT 0x00000000
7277#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_SUP_DEFAULT 0x00000000
7278#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE_DEFAULT 0x00000000
7279#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_TX_RXDET_DEFAULT 0x00000000
7280#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_PWRUP_DEFAULT 0x00000000
7281#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT_DEFAULT 0x00000000
7282#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL_DEFAULT 0x00000000
7283#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_FSM_CMNCAL_STATUS_DEFAULT 0x00000000
7284#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_AFE_ATT_IDAC_OFST_DEFAULT 0x00000080
7285#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_AFE_CTLE_IDAC_OFST_DEFAULT 0x00000080
7286#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_AFE_VGA1_IDAC_OFST_DEFAULT 0x00000080
7287#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST_DEFAULT 0x00000080
7288#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST_DEFAULT 0x00000080
7289#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST_DEFAULT 0x00000080
7290#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_PHASE_ODD_VDAC_OFST_DEFAULT 0x00000080
7291#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST_DEFAULT 0x00000080
7292#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST_DEFAULT 0x00000080
7293#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_PHSADJ_LIN_DEFAULT 0x00000000
7294#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_PHSADJ_MAP_DEFAULT 0x00000000
7295#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST_DEFAULT 0x00000080
7296#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST_DEFAULT 0x00000080
7297#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST_DEFAULT 0x00000080
7298#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST_DEFAULT 0x00000080
7299#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST_DEFAULT 0x00000080
7300#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST_DEFAULT 0x00000080
7301#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST_DEFAULT 0x00000080
7302#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_DFE_ERROR_ODD_VDAC_OFST_DEFAULT 0x00000080
7303#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_IQ_PHASE_ADJUST_DEFAULT 0x00000007
7304#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_MPLLA_COARSE_TUNE_DEFAULT 0x00000000
7305#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_MPLLB_COARSE_TUNE_DEFAULT 0x00000000
7306#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RTUNE_RX_VAL_DEFAULT 0x00000000
7307#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RTUNE_TXDN_VAL_DEFAULT 0x00000000
7308#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RTUNE_TXUP_VAL_DEFAULT 0x00000000
7309#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_INIT_PWRUP_DONE_DEFAULT 0x00000000
7310#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_ATT_DEFAULT 0x00000000
7311#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_VGA_DEFAULT 0x00000000
7312#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_CTLE_DEFAULT 0x00000000
7313#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP1_DEFAULT 0x00000000
7314#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADAPT_DONE_DEFAULT 0x00000000
7315#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_FAST_FLAGS_DEFAULT 0x00000000
7316#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP2_DEFAULT 0x00000800
7317#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP3_DEFAULT 0x00000800
7318#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP4_DEFAULT 0x00000800
7319#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP5_DEFAULT 0x00000800
7320#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_SLICER_CTRL_EVEN_DEFAULT 0x00000007
7321#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_RX_SLICER_CTRL_ODD_DEFAULT 0x00000007
7322#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_LANE_CMNCAL_STATUS_DEFAULT 0x00000000
7323#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_ADPT_CTL_0_DEFAULT 0x00000000
7324#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_ADPT_CTL_1_DEFAULT 0x00000000
7325#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_ADPT_CTL_2_DEFAULT 0x00000000
7326#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_ADPT_CTL_3_DEFAULT 0x00000000
7327#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_ADPT_CTL_4_DEFAULT 0x00000000
7328#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_ADPT_CTL_5_DEFAULT 0x00000000
7329#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_ADPT_CTL_6_DEFAULT 0x00000000
7330#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_AON_ADPT_CTL_7_DEFAULT 0x00000000
7331#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ_DEFAULT 0x00000001
7332#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_DEFAULT 0x00000000
7333#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_DEFAULT 0x00000000
7334#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_DEFAULT 0x00000000
7335#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_DEFAULT 0x00000000
7336#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_DEFAULT 0x00000000
7337#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_DEFAULT 0x00000000
7338#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR_DEFAULT 0x00000000
7339#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR_DEFAULT 0x00000000
7340#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR_DEFAULT 0x00000000
7341#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR_DEFAULT 0x00000000
7342#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR_DEFAULT 0x00000000
7343#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR_DEFAULT 0x00000000
7344#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_IRQ_CTL_IRQ_MASK_DEFAULT 0x00000000
7345#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN_DEFAULT 0x00000003
7346#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT_DEFAULT 0x00000003
7347#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN_DEFAULT 0x00000000
7348#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_DEFAULT 0x00000000
7349#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT_DEFAULT 0x00000000
7350#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_TX_PMA_IN_DEFAULT 0x00000000
7351#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT_DEFAULT 0x00000000
7352#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_RX_PMA_IN_DEFAULT 0x00000000
7353#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL_DEFAULT 0x00000000
7354#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_TX_CTL_TX_FSM_CTL_DEFAULT 0x000000de
7355#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_TX_CTL_TX_CLK_CTL_DEFAULT 0x00000001
7356#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_RX_CTL_RX_FSM_CTL_DEFAULT 0x00000000
7357#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL_DEFAULT 0x00000107
7358#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL_DEFAULT 0x00007d09
7359#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS_DEFAULT 0x00000000
7360#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS_DEFAULT 0x00000000
7361#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_DEFAULT 0x0000005b
7362#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1_DEFAULT 0x00000f07
7363#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_PCS_IN_DEFAULT 0x00000000
7364#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT_DEFAULT 0x00000005
7365#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_TX_PCS_OUT_DEFAULT 0x00000000
7366#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_DEFAULT 0x0000008c
7367#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1_DEFAULT 0x00000007
7368#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2_DEFAULT 0x00000000
7369#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3_DEFAULT 0x00008000
7370#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_DEFAULT 0x00000000
7371#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1_DEFAULT 0x00000000
7372#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2_DEFAULT 0x00000000
7373#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3_DEFAULT 0x00000000
7374#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4_DEFAULT 0x00000000
7375#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_DEFAULT 0x00000003
7376#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_PCS_OUT_DEFAULT 0x00000000
7377#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK_DEFAULT 0x00000000
7378#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM_DEFAULT 0x00000000
7379#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR_DEFAULT 0x00000000
7380#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR_DEFAULT 0x00000000
7381#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR_DEFAULT 0x00000000
7382#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PCS_XF_LANE_NUMBER_DEFAULT 0x00000000
7383#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FSM_OVRD_CTL_DEFAULT 0x00000000
7384#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_MEM_ADDR_MON_DEFAULT 0x00000000
7385#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_STATUS_MON_DEFAULT 0x00000000
7386#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL_DEFAULT 0x00000000
7387#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_ADAPT_DEFAULT 0x00000000
7388#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL_DEFAULT 0x00000000
7389#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL_DEFAULT 0x00000000
7390#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_BYPASS_CAL_DEFAULT 0x00000000
7391#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL_DEFAULT 0x00000000
7392#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL_DEFAULT 0x00000000
7393#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT_DEFAULT 0x00000000
7394#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT_DEFAULT 0x00000000
7395#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_SUP_DEFAULT 0x00000000
7396#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE_DEFAULT 0x00000000
7397#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_TX_RXDET_DEFAULT 0x00000000
7398#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_PWRUP_DEFAULT 0x00000000
7399#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT_DEFAULT 0x00000000
7400#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL_DEFAULT 0x00000000
7401#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_FSM_CMNCAL_STATUS_DEFAULT 0x00000000
7402#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_AFE_ATT_IDAC_OFST_DEFAULT 0x00000080
7403#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_AFE_CTLE_IDAC_OFST_DEFAULT 0x00000080
7404#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_AFE_VGA1_IDAC_OFST_DEFAULT 0x00000080
7405#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST_DEFAULT 0x00000080
7406#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST_DEFAULT 0x00000080
7407#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST_DEFAULT 0x00000080
7408#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_PHASE_ODD_VDAC_OFST_DEFAULT 0x00000080
7409#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST_DEFAULT 0x00000080
7410#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST_DEFAULT 0x00000080
7411#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_PHSADJ_LIN_DEFAULT 0x00000000
7412#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_PHSADJ_MAP_DEFAULT 0x00000000
7413#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST_DEFAULT 0x00000080
7414#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST_DEFAULT 0x00000080
7415#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST_DEFAULT 0x00000080
7416#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST_DEFAULT 0x00000080
7417#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST_DEFAULT 0x00000080
7418#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST_DEFAULT 0x00000080
7419#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST_DEFAULT 0x00000080
7420#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_DFE_ERROR_ODD_VDAC_OFST_DEFAULT 0x00000080
7421#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_IQ_PHASE_ADJUST_DEFAULT 0x00000007
7422#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_MPLLA_COARSE_TUNE_DEFAULT 0x00000000
7423#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_MPLLB_COARSE_TUNE_DEFAULT 0x00000000
7424#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RTUNE_RX_VAL_DEFAULT 0x00000000
7425#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RTUNE_TXDN_VAL_DEFAULT 0x00000000
7426#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RTUNE_TXUP_VAL_DEFAULT 0x00000000
7427#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_INIT_PWRUP_DONE_DEFAULT 0x00000000
7428#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_ATT_DEFAULT 0x00000000
7429#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_VGA_DEFAULT 0x00000000
7430#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_CTLE_DEFAULT 0x00000000
7431#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP1_DEFAULT 0x00000000
7432#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADAPT_DONE_DEFAULT 0x00000000
7433#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_FAST_FLAGS_DEFAULT 0x00000000
7434#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP2_DEFAULT 0x00000800
7435#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP3_DEFAULT 0x00000800
7436#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP4_DEFAULT 0x00000800
7437#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP5_DEFAULT 0x00000800
7438#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_SLICER_CTRL_EVEN_DEFAULT 0x00000007
7439#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_RX_SLICER_CTRL_ODD_DEFAULT 0x00000007
7440#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_LANE_CMNCAL_STATUS_DEFAULT 0x00000000
7441#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_ADPT_CTL_0_DEFAULT 0x00000000
7442#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_ADPT_CTL_1_DEFAULT 0x00000000
7443#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_ADPT_CTL_2_DEFAULT 0x00000000
7444#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_ADPT_CTL_3_DEFAULT 0x00000000
7445#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_ADPT_CTL_4_DEFAULT 0x00000000
7446#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_ADPT_CTL_5_DEFAULT 0x00000000
7447#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_ADPT_CTL_6_DEFAULT 0x00000000
7448#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_AON_ADPT_CTL_7_DEFAULT 0x00000000
7449#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ_DEFAULT 0x00000001
7450#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_DEFAULT 0x00000000
7451#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_DEFAULT 0x00000000
7452#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_DEFAULT 0x00000000
7453#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_DEFAULT 0x00000000
7454#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_DEFAULT 0x00000000
7455#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_DEFAULT 0x00000000
7456#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR_DEFAULT 0x00000000
7457#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR_DEFAULT 0x00000000
7458#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR_DEFAULT 0x00000000
7459#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR_DEFAULT 0x00000000
7460#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR_DEFAULT 0x00000000
7461#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR_DEFAULT 0x00000000
7462#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_IRQ_CTL_IRQ_MASK_DEFAULT 0x00000000
7463#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN_DEFAULT 0x00000003
7464#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT_DEFAULT 0x00000003
7465#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN_DEFAULT 0x00000000
7466#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_DEFAULT 0x00000000
7467#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT_DEFAULT 0x00000000
7468#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_TX_PMA_IN_DEFAULT 0x00000000
7469#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT_DEFAULT 0x00000000
7470#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_RX_PMA_IN_DEFAULT 0x00000000
7471#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL_DEFAULT 0x00000000
7472#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_TX_CTL_TX_FSM_CTL_DEFAULT 0x000000de
7473#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_TX_CTL_TX_CLK_CTL_DEFAULT 0x00000001
7474#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_RX_CTL_RX_FSM_CTL_DEFAULT 0x00000000
7475#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL_DEFAULT 0x00000107
7476#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL_DEFAULT 0x00007d09
7477#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS_DEFAULT 0x00000000
7478#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS_DEFAULT 0x00000000
7479#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_DEFAULT 0x0000005b
7480#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_IN_1_DEFAULT 0x00000f07
7481#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_PCS_IN_DEFAULT 0x00000000
7482#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_OVRD_OUT_DEFAULT 0x00000005
7483#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_TX_PCS_OUT_DEFAULT 0x00000000
7484#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_DEFAULT 0x0000008c
7485#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_1_DEFAULT 0x00000007
7486#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2_DEFAULT 0x00000000
7487#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3_DEFAULT 0x00008000
7488#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_DEFAULT 0x00000000
7489#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_1_DEFAULT 0x00000000
7490#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_2_DEFAULT 0x00000000
7491#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_3_DEFAULT 0x00000000
7492#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_IN_4_DEFAULT 0x00000000
7493#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_OVRD_OUT_DEFAULT 0x00000003
7494#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_PCS_OUT_DEFAULT 0x00000000
7495#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_ADAPT_ACK_DEFAULT 0x00000000
7496#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_ADAPT_FOM_DEFAULT 0x00000000
7497#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_TXPRE_DIR_DEFAULT 0x00000000
7498#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_TXMAIN_DIR_DEFAULT 0x00000000
7499#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_RX_TXPOST_DIR_DEFAULT 0x00000000
7500#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PCS_XF_LANE_NUMBER_DEFAULT 0x00000000
7501#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FSM_OVRD_CTL_DEFAULT 0x00000000
7502#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_MEM_ADDR_MON_DEFAULT 0x00000000
7503#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_STATUS_MON_DEFAULT 0x00000000
7504#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_STARTUP_CAL_DEFAULT 0x00000000
7505#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_ADAPT_DEFAULT 0x00000000
7506#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_AFE_CAL_DEFAULT 0x00000000
7507#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_DFE_CAL_DEFAULT 0x00000000
7508#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_BYPASS_CAL_DEFAULT 0x00000000
7509#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_REFLVL_CAL_DEFAULT 0x00000000
7510#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_IQ_CAL_DEFAULT 0x00000000
7511#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_AFE_ADAPT_DEFAULT 0x00000000
7512#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_DFE_ADAPT_DEFAULT 0x00000000
7513#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_SUP_DEFAULT 0x00000000
7514#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_TX_CMN_MODE_DEFAULT 0x00000000
7515#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_TX_RXDET_DEFAULT 0x00000000
7516#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_PWRUP_DEFAULT 0x00000000
7517#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_VCO_WAIT_DEFAULT 0x00000000
7518#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_FAST_RX_VCO_CAL_DEFAULT 0x00000000
7519#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_FSM_CMNCAL_STATUS_DEFAULT 0x00000000
7520#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_AFE_ATT_IDAC_OFST_DEFAULT 0x00000080
7521#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_AFE_CTLE_IDAC_OFST_DEFAULT 0x00000080
7522#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_AFE_VGA1_IDAC_OFST_DEFAULT 0x00000080
7523#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST_DEFAULT 0x00000080
7524#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST_DEFAULT 0x00000080
7525#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST_DEFAULT 0x00000080
7526#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_PHASE_ODD_VDAC_OFST_DEFAULT 0x00000080
7527#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST_DEFAULT 0x00000080
7528#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST_DEFAULT 0x00000080
7529#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_PHSADJ_LIN_DEFAULT 0x00000000
7530#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_PHSADJ_MAP_DEFAULT 0x00000000
7531#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST_DEFAULT 0x00000080
7532#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST_DEFAULT 0x00000080
7533#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST_DEFAULT 0x00000080
7534#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST_DEFAULT 0x00000080
7535#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST_DEFAULT 0x00000080
7536#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST_DEFAULT 0x00000080
7537#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST_DEFAULT 0x00000080
7538#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_DFE_ERROR_ODD_VDAC_OFST_DEFAULT 0x00000080
7539#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_IQ_PHASE_ADJUST_DEFAULT 0x00000007
7540#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_MPLLA_COARSE_TUNE_DEFAULT 0x00000000
7541#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_MPLLB_COARSE_TUNE_DEFAULT 0x00000000
7542#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RTUNE_RX_VAL_DEFAULT 0x00000000
7543#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RTUNE_TXDN_VAL_DEFAULT 0x00000000
7544#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RTUNE_TXUP_VAL_DEFAULT 0x00000000
7545#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_INIT_PWRUP_DONE_DEFAULT 0x00000000
7546#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_ATT_DEFAULT 0x00000000
7547#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_VGA_DEFAULT 0x00000000
7548#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_CTLE_DEFAULT 0x00000000
7549#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP1_DEFAULT 0x00000000
7550#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADAPT_DONE_DEFAULT 0x00000000
7551#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_FAST_FLAGS_DEFAULT 0x00000000
7552#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP2_DEFAULT 0x00000800
7553#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP3_DEFAULT 0x00000800
7554#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP4_DEFAULT 0x00000800
7555#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_ADPT_DFE_TAP5_DEFAULT 0x00000800
7556#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_SLICER_CTRL_EVEN_DEFAULT 0x00000007
7557#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_RX_SLICER_CTRL_ODD_DEFAULT 0x00000007
7558#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_LANE_CMNCAL_STATUS_DEFAULT 0x00000000
7559#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_ADPT_CTL_0_DEFAULT 0x00000000
7560#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_ADPT_CTL_1_DEFAULT 0x00000000
7561#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_ADPT_CTL_2_DEFAULT 0x00000000
7562#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_ADPT_CTL_3_DEFAULT 0x00000000
7563#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_ADPT_CTL_4_DEFAULT 0x00000000
7564#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_ADPT_CTL_5_DEFAULT 0x00000000
7565#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_ADPT_CTL_6_DEFAULT 0x00000000
7566#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_AON_ADPT_CTL_7_DEFAULT 0x00000000
7567#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RESET_RTN_REQ_DEFAULT 0x00000001
7568#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_DEFAULT 0x00000000
7569#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_DEFAULT 0x00000000
7570#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_DEFAULT 0x00000000
7571#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_DEFAULT 0x00000000
7572#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_DEFAULT 0x00000000
7573#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_DEFAULT 0x00000000
7574#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_RESET_IRQ_CLR_DEFAULT 0x00000000
7575#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_REQ_IRQ_CLR_DEFAULT 0x00000000
7576#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_RATE_IRQ_CLR_DEFAULT 0x00000000
7577#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR_DEFAULT 0x00000000
7578#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR_DEFAULT 0x00000000
7579#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR_DEFAULT 0x00000000
7580#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_IRQ_CTL_IRQ_MASK_DEFAULT 0x00000000
7581#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_IN_DEFAULT 0x00000003
7582#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_LANE_OVRD_OUT_DEFAULT 0x00000003
7583#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_SUP_OVRD_IN_DEFAULT 0x00000000
7584#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_SUP_PMA_IN_DEFAULT 0x00000000
7585#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_TX_OVRD_OUT_DEFAULT 0x00000000
7586#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_TX_PMA_IN_DEFAULT 0x00000000
7587#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_RX_OVRD_OUT_DEFAULT 0x00000000
7588#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_RX_PMA_IN_DEFAULT 0x00000000
7589#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_PMA_XF_LANE_RTUNE_CTL_DEFAULT 0x00000000
7590#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_TX_CTL_TX_FSM_CTL_DEFAULT 0x000000de
7591#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_TX_CTL_TX_CLK_CTL_DEFAULT 0x00000001
7592#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_RX_CTL_RX_FSM_CTL_DEFAULT 0x00000000
7593#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_RX_CTL_RX_LOS_MASK_CTL_DEFAULT 0x00000107
7594#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL_DEFAULT 0x00007d09
7595#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_RX_CTL_OFFCAN_CONT_STATUS_DEFAULT 0x00000000
7596#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE2_DIG_RX_CTL_ADAPT_CONT_STATUS_DEFAULT 0x00000000
7597#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_DEFAULT 0x0000005b
7598#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_IN_1_DEFAULT 0x00000f07
7599#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_PCS_IN_DEFAULT 0x00000000
7600#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_OVRD_OUT_DEFAULT 0x00000005
7601#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_TX_PCS_OUT_DEFAULT 0x00000000
7602#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_DEFAULT 0x0000008c
7603#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_1_DEFAULT 0x00000007
7604#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2_DEFAULT 0x00000000
7605#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3_DEFAULT 0x00008000
7606#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_DEFAULT 0x00000000
7607#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_1_DEFAULT 0x00000000
7608#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_2_DEFAULT 0x00000000
7609#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_3_DEFAULT 0x00000000
7610#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_IN_4_DEFAULT 0x00000000
7611#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_OVRD_OUT_DEFAULT 0x00000003
7612#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_PCS_OUT_DEFAULT 0x00000000
7613#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_ADAPT_ACK_DEFAULT 0x00000000
7614#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_ADAPT_FOM_DEFAULT 0x00000000
7615#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_TXPRE_DIR_DEFAULT 0x00000000
7616#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_TXMAIN_DIR_DEFAULT 0x00000000
7617#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_RX_TXPOST_DIR_DEFAULT 0x00000000
7618#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PCS_XF_LANE_NUMBER_DEFAULT 0x00000000
7619#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FSM_OVRD_CTL_DEFAULT 0x00000000
7620#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_MEM_ADDR_MON_DEFAULT 0x00000000
7621#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_STATUS_MON_DEFAULT 0x00000000
7622#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_STARTUP_CAL_DEFAULT 0x00000000
7623#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_ADAPT_DEFAULT 0x00000000
7624#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_AFE_CAL_DEFAULT 0x00000000
7625#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_DFE_CAL_DEFAULT 0x00000000
7626#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_BYPASS_CAL_DEFAULT 0x00000000
7627#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_REFLVL_CAL_DEFAULT 0x00000000
7628#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_IQ_CAL_DEFAULT 0x00000000
7629#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_AFE_ADAPT_DEFAULT 0x00000000
7630#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_DFE_ADAPT_DEFAULT 0x00000000
7631#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_SUP_DEFAULT 0x00000000
7632#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_TX_CMN_MODE_DEFAULT 0x00000000
7633#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_TX_RXDET_DEFAULT 0x00000000
7634#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_PWRUP_DEFAULT 0x00000000
7635#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_VCO_WAIT_DEFAULT 0x00000000
7636#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_FAST_RX_VCO_CAL_DEFAULT 0x00000000
7637#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_FSM_CMNCAL_STATUS_DEFAULT 0x00000000
7638#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_AFE_ATT_IDAC_OFST_DEFAULT 0x00000080
7639#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_AFE_CTLE_IDAC_OFST_DEFAULT 0x00000080
7640#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_AFE_VGA1_IDAC_OFST_DEFAULT 0x00000080
7641#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_SUMMER_EVEN_IDAC_OFST_DEFAULT 0x00000080
7642#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_SUMMER_ODD_IDAC_OFST_DEFAULT 0x00000080
7643#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST_DEFAULT 0x00000080
7644#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_PHASE_ODD_VDAC_OFST_DEFAULT 0x00000080
7645#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_PHASE_EVEN_LOW_VDAC_OFST_DEFAULT 0x00000080
7646#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_PHASE_ODD_LOW_VDAC_OFST_DEFAULT 0x00000080
7647#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_PHSADJ_LIN_DEFAULT 0x00000000
7648#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_PHSADJ_MAP_DEFAULT 0x00000000
7649#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST_DEFAULT 0x00000080
7650#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST_DEFAULT 0x00000080
7651#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST_DEFAULT 0x00000080
7652#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST_DEFAULT 0x00000080
7653#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST_DEFAULT 0x00000080
7654#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST_DEFAULT 0x00000080
7655#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST_DEFAULT 0x00000080
7656#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_DFE_ERROR_ODD_VDAC_OFST_DEFAULT 0x00000080
7657#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_IQ_PHASE_ADJUST_DEFAULT 0x00000007
7658#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_MPLLA_COARSE_TUNE_DEFAULT 0x00000000
7659#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_MPLLB_COARSE_TUNE_DEFAULT 0x00000000
7660#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RTUNE_RX_VAL_DEFAULT 0x00000000
7661#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RTUNE_TXDN_VAL_DEFAULT 0x00000000
7662#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RTUNE_TXUP_VAL_DEFAULT 0x00000000
7663#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_INIT_PWRUP_DONE_DEFAULT 0x00000000
7664#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_ATT_DEFAULT 0x00000000
7665#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_VGA_DEFAULT 0x00000000
7666#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_CTLE_DEFAULT 0x00000000
7667#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP1_DEFAULT 0x00000000
7668#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADAPT_DONE_DEFAULT 0x00000000
7669#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_FAST_FLAGS_DEFAULT 0x00000000
7670#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP2_DEFAULT 0x00000800
7671#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP3_DEFAULT 0x00000800
7672#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP4_DEFAULT 0x00000800
7673#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_ADPT_DFE_TAP5_DEFAULT 0x00000800
7674#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_SLICER_CTRL_EVEN_DEFAULT 0x00000007
7675#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_RX_SLICER_CTRL_ODD_DEFAULT 0x00000007
7676#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_LANE_CMNCAL_STATUS_DEFAULT 0x00000000
7677#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_ADPT_CTL_0_DEFAULT 0x00000000
7678#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_ADPT_CTL_1_DEFAULT 0x00000000
7679#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_ADPT_CTL_2_DEFAULT 0x00000000
7680#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_ADPT_CTL_3_DEFAULT 0x00000000
7681#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_ADPT_CTL_4_DEFAULT 0x00000000
7682#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_ADPT_CTL_5_DEFAULT 0x00000000
7683#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_ADPT_CTL_6_DEFAULT 0x00000000
7684#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_AON_ADPT_CTL_7_DEFAULT 0x00000000
7685#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RESET_RTN_REQ_DEFAULT 0x00000001
7686#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_DEFAULT 0x00000000
7687#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_DEFAULT 0x00000000
7688#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_DEFAULT 0x00000000
7689#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_DEFAULT 0x00000000
7690#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_DEFAULT 0x00000000
7691#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_DEFAULT 0x00000000
7692#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_RESET_IRQ_CLR_DEFAULT 0x00000000
7693#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_REQ_IRQ_CLR_DEFAULT 0x00000000
7694#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_RATE_IRQ_CLR_DEFAULT 0x00000000
7695#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR_DEFAULT 0x00000000
7696#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR_DEFAULT 0x00000000
7697#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR_DEFAULT 0x00000000
7698#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_IRQ_CTL_IRQ_MASK_DEFAULT 0x00000000
7699#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_IN_DEFAULT 0x00000003
7700#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_LANE_OVRD_OUT_DEFAULT 0x00000003
7701#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_SUP_OVRD_IN_DEFAULT 0x00000000
7702#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_SUP_PMA_IN_DEFAULT 0x00000000
7703#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_TX_OVRD_OUT_DEFAULT 0x00000000
7704#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_TX_PMA_IN_DEFAULT 0x00000000
7705#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_RX_OVRD_OUT_DEFAULT 0x00000000
7706#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_RX_PMA_IN_DEFAULT 0x00000000
7707#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_PMA_XF_LANE_RTUNE_CTL_DEFAULT 0x00000000
7708#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_TX_CTL_TX_FSM_CTL_DEFAULT 0x000000de
7709#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_TX_CTL_TX_CLK_CTL_DEFAULT 0x00000001
7710#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_RX_CTL_RX_FSM_CTL_DEFAULT 0x00000000
7711#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_RX_CTL_RX_LOS_MASK_CTL_DEFAULT 0x00000107
7712#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL_DEFAULT 0x00007d09
7713#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_RX_CTL_OFFCAN_CONT_STATUS_DEFAULT 0x00000000
7714#define smnDWC_E12MP_PHY_X4_NS_X4_0_RAWLANE3_DIG_RX_CTL_ADAPT_CONT_STATUS_DEFAULT 0x00000000
7715#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_IDCODE_LO_DEFAULT 0x000004cd
7716#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_IDCODE_HI_DEFAULT 0x00003006
7717#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_REFCLK_OVRD_IN_DEFAULT 0x00000070
7718#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_B_DIV_CLK_OVRD_IN_DEFAULT 0x00000000
7719#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_0_DEFAULT 0x00000328
7720#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_1_DEFAULT 0x00000000
7721#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_OVRD_IN_2_DEFAULT 0x00000043
7722#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_OVRD_IN_0_DEFAULT 0x00000194
7723#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_OVRD_IN_1_DEFAULT 0x0000a000
7724#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_OVRD_IN_2_DEFAULT 0x00000043
7725#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_SUP_OVRD_IN_DEFAULT 0x00000008
7726#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_SUP_OVRD_OUT_DEFAULT 0x00000004
7727#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_LVL_OVRD_IN_DEFAULT 0x000001d0
7728#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_ASIC_IN_0_DEFAULT 0x00000000
7729#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_ASIC_IN_1_DEFAULT 0x00000000
7730#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_ASIC_IN_2_DEFAULT 0x00000000
7731#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_ASIC_IN_0_DEFAULT 0x00000000
7732#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_ASIC_IN_1_DEFAULT 0x00000000
7733#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_ASIC_IN_2_DEFAULT 0x00000000
7734#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_B_DIV_CLK_ASIC_IN_DEFAULT 0x00000000
7735#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ASIC_IN_DEFAULT 0x00000000
7736#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_LVL_ASIC_IN_DEFAULT 0x00000000
7737#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLA_OVRD_OUT_DEFAULT 0x00000002
7738#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_MPLLB_OVRD_OUT_DEFAULT 0x00000002
7739#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_RTUNE_OVRD_OUT_DEFAULT 0x00000000
7740#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_RX_TERM_OVRD_OUT_DEFAULT 0x00000000
7741#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_ANA_STAT_DEFAULT 0x00000000
7742#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL_DEFAULT 0x00000018
7743#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD_DEFAULT 0x00000000
7744#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_STAT_DEFAULT 0x00000000
7745#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD_DEFAULT 0x00000d00
7746#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD_DEFAULT 0x00005200
7747#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD_DEFAULT 0x0000894a
7748#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_DEFAULT 0x00000066
7749#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL_DEFAULT 0x00000000
7750#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE_DEFAULT 0x00000000
7751#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_SSC_SS_PHASE_DEFAULT 0x00004000
7752#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_SSC_SS_FREQ_0_DEFAULT 0x00000025
7753#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLA_SSC_SS_FREQ_1_DEFAULT 0x00000066
7754#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL_DEFAULT 0x00000018
7755#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD_DEFAULT 0x00000000
7756#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_STAT_DEFAULT 0x00000000
7757#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD_DEFAULT 0x00000d00
7758#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD_DEFAULT 0x00005200
7759#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD_DEFAULT 0x0000894a
7760#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_TIME_THRESHOLD_DEFAULT 0x00000066
7761#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL_DEFAULT 0x00000000
7762#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE_DEFAULT 0x00000000
7763#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_SSC_SS_PHASE_DEFAULT 0x00004000
7764#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_SSC_SS_FREQ_0_DEFAULT 0x00000025
7765#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_MPLLB_SSC_SS_FREQ_1_DEFAULT 0x00000066
7766#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_MISC_DEFAULT 0x00000028
7767#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_OVRD_DEFAULT 0x00000000
7768#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB1_DEFAULT 0x00000000
7769#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB2_DEFAULT 0x00000000
7770#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLA_ATB3_DEFAULT 0x00000000
7771#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_MISC_DEFAULT 0x00000028
7772#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_OVRD_DEFAULT 0x00000000
7773#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB1_DEFAULT 0x00000000
7774#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB2_DEFAULT 0x00000000
7775#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_MPLLB_ATB3_DEFAULT 0x00000000
7776#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_RTUNE_CTRL_DEFAULT 0x00000000
7777#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_SWITCH_PWR_MEAS_DEFAULT 0x00000000
7778#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_SWITCH_MISC_MEAS_DEFAULT 0x00000012
7779#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_ANA_BG_DEFAULT 0x0000000e
7780#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_CONFIG_DEFAULT 0x00000000
7781#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_STAT_DEFAULT 0x00000000
7782#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_RX_SET_VAL_DEFAULT 0x00000000
7783#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_TXDN_SET_VAL_DEFAULT 0x00000000
7784#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_TXUP_SET_VAL_DEFAULT 0x00000000
7785#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_RX_STAT_DEFAULT 0x00000000
7786#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_TXDN_STAT_DEFAULT 0x00000000
7787#define smnDWC_E12MP_PHY_X4_NS_X4_0_SUPX_DIG_RTUNE_TXUP_STAT_DEFAULT 0x00000000
7788#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_LANE_OVRD_IN_DEFAULT 0x00000000
7789#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_0_DEFAULT 0x00000000
7790#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_1_DEFAULT 0x00005078
7791#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_IN_2_DEFAULT 0x00000000
7792#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_OVRD_OUT_DEFAULT 0x00000000
7793#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_0_DEFAULT 0x00000000
7794#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_1_DEFAULT 0x00000014
7795#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_2_DEFAULT 0x000003e8
7796#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_IN_3_DEFAULT 0x00000000
7797#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_0_DEFAULT 0x000037f8
7798#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_1_DEFAULT 0x00000400
7799#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_OUT_0_DEFAULT 0x00000000
7800#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_LANE_ASIC_IN_DEFAULT 0x00000000
7801#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_0_DEFAULT 0x00000000
7802#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_1_DEFAULT 0x00000000
7803#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_IN_2_DEFAULT 0x00000000
7804#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_TX_ASIC_OUT_DEFAULT 0x00000000
7805#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_0_DEFAULT 0x00000000
7806#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_IN_1_DEFAULT 0x00000000
7807#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_0_DEFAULT 0x00000000
7808#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_EQ_ASIC_IN_1_DEFAULT 0x00000000
7809#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0_DEFAULT 0x00000000
7810#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1_DEFAULT 0x00000000
7811#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_ASIC_OUT_0_DEFAULT 0x00000000
7812#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_2_DEFAULT 0x00002040
7813#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ASIC_RX_OVRD_EQ_IN_3_DEFAULT 0x00002040
7814#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0_DEFAULT 0x000000e7
7815#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P0S_DEFAULT 0x00000046
7816#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P1_DEFAULT 0x00000112
7817#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PSTATE_P2_DEFAULT 0x00000110
7818#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_0_DEFAULT 0x00001a0c
7819#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_1_DEFAULT 0x0000e6cc
7820#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_2_DEFAULT 0x00000d5d
7821#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_PWRCTL_TX_PWRUP_TIME_3_DEFAULT 0x00002907
7822#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_TX_LBERT_CTL_DEFAULT 0x00000000
7823#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0_DEFAULT 0x00000cff
7824#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P0S_DEFAULT 0x00000407
7825#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P1_DEFAULT 0x00000301
7826#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PSTATE_P2_DEFAULT 0x00000301
7827#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_0_DEFAULT 0x00000307
7828#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_1_DEFAULT 0x00001434
7829#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_TIME_2_DEFAULT 0x00000006
7830#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_PWRCTL_RX_PWRUP_CTL_0_DEFAULT 0x00000000
7831#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0_DEFAULT 0x00000002
7832#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1_DEFAULT 0x00000100
7833#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2_DEFAULT 0x00002600
7834#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0_DEFAULT 0x00003521
7835#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1_DEFAULT 0x00000002
7836#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_0_DEFAULT 0x00000000
7837#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_1_DEFAULT 0x00000000
7838#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_STAT_2_DEFAULT 0x00000000
7839#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_RX_ALIGN_XAUI_COMM_MASK_DEFAULT 0x000003ff
7840#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_LBERT_CTL_DEFAULT 0x00000000
7841#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_LBERT_ERR_DEFAULT 0x00000000
7842#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_0_DEFAULT 0x0000000f
7843#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_1_DEFAULT 0x00004c39
7844#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_2_DEFAULT 0x00004abb
7845#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_3_DEFAULT 0x000000d6
7846#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_CDR_CTL_4_DEFAULT 0x00002cdb
7847#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_CDR_STAT_DEFAULT 0x00000000
7848#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_DPLL_FREQ_DEFAULT 0x00002000
7849#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_DPLL_FREQ_BOUND_0_DEFAULT 0x000004c8
7850#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_DPLL_FREQ_BOUND_1_DEFAULT 0x0000019c
7851#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_0_DEFAULT 0x00000c10
7852#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_1_DEFAULT 0x00000009
7853#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_2_DEFAULT 0x000000c2
7854#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_3_DEFAULT 0x00000000
7855#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_4_DEFAULT 0x00000000
7856#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_5_DEFAULT 0x00000000
7857#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_6_DEFAULT 0x0000792b
7858#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_7_DEFAULT 0x00004342
7859#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_8_DEFAULT 0x00004925
7860#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ADPT_CFG_9_DEFAULT 0x00000000
7861#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_RST_ADPT_CFG_DEFAULT 0x0000001f
7862#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ATT_STATUS_DEFAULT 0x00000000
7863#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_VGA_STATUS_DEFAULT 0x00000000
7864#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_CTLE_STATUS_DEFAULT 0x00000000
7865#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP1_STATUS_DEFAULT 0x00000000
7866#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP2_STATUS_DEFAULT 0x00000000
7867#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP3_STATUS_DEFAULT 0x00000000
7868#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP4_STATUS_DEFAULT 0x00000000
7869#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_TAP5_STATUS_DEFAULT 0x00000000
7870#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_HIGH_VDAC_OFST_DEFAULT 0x00000080
7871#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_EVEN_LOW_VDAC_OFST_DEFAULT 0x00000080
7872#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_HIGH_VDAC_OFST_DEFAULT 0x00000080
7873#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_DATA_ODD_LOW_VDAC_OFST_DEFAULT 0x00000080
7874#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN_DEFAULT 0x00000007
7875#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD_DEFAULT 0x00000007
7876#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST_DEFAULT 0x00000080
7877#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST_DEFAULT 0x00000080
7878#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL_DEFAULT 0x00000000
7879#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_EVEN_VDAC_OFST_DEFAULT 0x00000080
7880#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_ADPTCTL_DFE_BYPASS_ODD_VDAC_OFST_DEFAULT 0x00000080
7881#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_LD_VAL_1_DEFAULT 0x00000040
7882#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_DATA_MSK_DEFAULT 0x0000ffff
7883#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL0_DEFAULT 0x00003c06
7884#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL1_DEFAULT 0x00000800
7885#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL0_DEFAULT 0x00004000
7886#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL1_DEFAULT 0x00000008
7887#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_SMPL_CNT1_DEFAULT 0x00000000
7888#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_0_DEFAULT 0x00000000
7889#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_1_DEFAULT 0x00000000
7890#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_2_DEFAULT 0x00000000
7891#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_3_DEFAULT 0x00000000
7892#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_4_DEFAULT 0x00000000
7893#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_5_DEFAULT 0x00000000
7894#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CNT_6_DEFAULT 0x00000000
7895#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_CAL_COMP_CLK_CTL_DEFAULT 0x00000019
7896#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL2_DEFAULT 0x00000000
7897#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL3_DEFAULT 0x00000000
7898#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL4_DEFAULT 0x00000000
7899#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_MATCH_CTL5_DEFAULT 0x00000000
7900#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_STAT_STAT_CTL2_DEFAULT 0x00000000
7901#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_OVRD_OUT_DEFAULT 0x00000000
7902#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_TERM_UP_CODE_OVRD_OUT_DEFAULT 0x00000000
7903#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_TERM_DN_CODE_OVRD_OUT_DEFAULT 0x00000000
7904#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_0_DEFAULT 0x00000000
7905#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_1_DEFAULT 0x00000000
7906#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_2_DEFAULT 0x00000000
7907#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_3_DEFAULT 0x00000000
7908#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_TX_EQ_OVRD_OUT_4_DEFAULT 0x00000000
7909#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CTL_OVRD_OUT_DEFAULT 0x00000000
7910#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_PWR_OVRD_OUT_DEFAULT 0x00000000
7911#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_0_DEFAULT 0x00000000
7912#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_VCO_OVRD_OUT_1_DEFAULT 0x00000002
7913#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_CAL_DEFAULT 0x00000000
7914#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_DAC_CTRL_DEFAULT 0x00000080
7915#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_DAC_CTRL_OVRD_DEFAULT 0x00000000
7916#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_DAC_CTRL_SEL_DEFAULT 0x00000000
7917#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_AFE_ATT_VGA_DEFAULT 0x00000000
7918#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_AFE_CTLE_DEFAULT 0x00000000
7919#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_SCOPE_DEFAULT 0x00000000
7920#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_SLICER_CTRL_DEFAULT 0x00000077
7921#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST_DEFAULT 0x00000007
7922#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_IQ_SENSE_EN_DEFAULT 0x00000000
7923#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN_DEFAULT 0x00000000
7924#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE_DEFAULT 0x00000000
7925#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK_DEFAULT 0x00000000
7926#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_STATUS_0_DEFAULT 0x00000000
7927#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_ANA_STATUS_1_DEFAULT 0x00000000
7928#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_MEAS_DEFAULT 0x00000000
7929#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_PWR_OVRD_DEFAULT 0x00000000
7930#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ALT_BUS_DEFAULT 0x00000000
7931#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB1_DEFAULT 0x00000000
7932#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_ATB2_DEFAULT 0x00000000
7933#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_VBOOST_DEFAULT 0x00000000
7934#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_TERM_CODE_DN_DEFAULT 0x00000000
7935#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_TERM_CODE_UP_DEFAULT 0x000000fe
7936#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_IBOOST_CODE_DEFAULT 0x00000000
7937#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_OVRD_CLK_DEFAULT 0x00000000
7938#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_TX_MISC_DEFAULT 0x00000000
7939#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_IQSKEW_DEFAULT 0x00000000
7940#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_DCC_OVRD_DEFAULT 0x00000000
7941#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL1_DEFAULT 0x00000000
7942#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_REGREF_DEFAULT 0x00000000
7943#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CDR_AFE_DEFAULT 0x000000f0
7944#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_PWR_CTRL2_DEFAULT 0x00000000
7945#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_MISC_OVRD_DEFAULT 0x00000000
7946#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CAL_MUXA_DEFAULT 0x00000000
7947#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_MEAS1_DEFAULT 0x00000000
7948#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_ATB_MEAS2_DEFAULT 0x00000000
7949#define smnDWC_E12MP_PHY_X4_NS_X4_0_LANEX_ANA_RX_CAL_MUXB_DEFAULT 0x00000000
7950#define smnDWC_