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1/*
2 * Copyright (C) 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20 */
21#ifndef _nbio_6_1_OFFSET_HEADER
22#define _nbio_6_1_OFFSET_HEADER
23
24
25
26// addressBlock: nbio_pcie_pswuscfg0_cfgdecp
27// base address: 0x0
28#define cfgPSWUSCFG0_VENDOR_ID 0x0000
29#define cfgPSWUSCFG0_DEVICE_ID 0x0002
30#define cfgPSWUSCFG0_COMMAND 0x0004
31#define cfgPSWUSCFG0_STATUS 0x0006
32#define cfgPSWUSCFG0_REVISION_ID 0x0008
33#define cfgPSWUSCFG0_PROG_INTERFACE 0x0009
34#define cfgPSWUSCFG0_SUB_CLASS 0x000a
35#define cfgPSWUSCFG0_BASE_CLASS 0x000b
36#define cfgPSWUSCFG0_CACHE_LINE 0x000c
37#define cfgPSWUSCFG0_LATENCY 0x000d
38#define cfgPSWUSCFG0_HEADER 0x000e
39#define cfgPSWUSCFG0_BIST 0x000f
40#define cfgPSWUSCFG0_SUB_BUS_NUMBER_LATENCY 0x0018
41#define cfgPSWUSCFG0_IO_BASE_LIMIT 0x001c
42#define cfgPSWUSCFG0_SECONDARY_STATUS 0x001e
43#define cfgPSWUSCFG0_MEM_BASE_LIMIT 0x0020
44#define cfgPSWUSCFG0_PREF_BASE_LIMIT 0x0024
45#define cfgPSWUSCFG0_PREF_BASE_UPPER 0x0028
46#define cfgPSWUSCFG0_PREF_LIMIT_UPPER 0x002c
47#define cfgPSWUSCFG0_IO_BASE_LIMIT_HI 0x0030
48#define cfgPSWUSCFG0_CAP_PTR 0x0034
49#define cfgPSWUSCFG0_INTERRUPT_LINE 0x003c
50#define cfgPSWUSCFG0_INTERRUPT_PIN 0x003d
51#define cfgPSWUSCFG0_IRQ_BRIDGE_CNTL 0x003e
52#define cfgEXT_BRIDGE_CNTL 0x0040
53#define cfgPSWUSCFG0_VENDOR_CAP_LIST 0x0048
54#define cfgPSWUSCFG0_ADAPTER_ID_W 0x004c
55#define cfgPSWUSCFG0_PMI_CAP_LIST 0x0050
56#define cfgPSWUSCFG0_PMI_CAP 0x0052
57#define cfgPSWUSCFG0_PMI_STATUS_CNTL 0x0054
58#define cfgPSWUSCFG0_PCIE_CAP_LIST 0x0058
59#define cfgPSWUSCFG0_PCIE_CAP 0x005a
60#define cfgPSWUSCFG0_DEVICE_CAP 0x005c
61#define cfgPSWUSCFG0_DEVICE_CNTL 0x0060
62#define cfgPSWUSCFG0_DEVICE_STATUS 0x0062
63#define cfgPSWUSCFG0_LINK_CAP 0x0064
64#define cfgPSWUSCFG0_LINK_CNTL 0x0068
65#define cfgPSWUSCFG0_LINK_STATUS 0x006a
66#define cfgPSWUSCFG0_DEVICE_CAP2 0x007c
67#define cfgPSWUSCFG0_DEVICE_CNTL2 0x0080
68#define cfgPSWUSCFG0_DEVICE_STATUS2 0x0082
69#define cfgPSWUSCFG0_LINK_CAP2 0x0084
70#define cfgPSWUSCFG0_LINK_CNTL2 0x0088
71#define cfgPSWUSCFG0_LINK_STATUS2 0x008a
72#define cfgPSWUSCFG0_MSI_CAP_LIST 0x00a0
73#define cfgPSWUSCFG0_MSI_MSG_CNTL 0x00a2
74#define cfgPSWUSCFG0_MSI_MSG_ADDR_LO 0x00a4
75#define cfgPSWUSCFG0_MSI_MSG_ADDR_HI 0x00a8
76#define cfgPSWUSCFG0_MSI_MSG_DATA 0x00a8
77#define cfgPSWUSCFG0_MSI_MSG_DATA_64 0x00ac
78#define cfgPSWUSCFG0_SSID_CAP_LIST 0x00c0
79#define cfgPSWUSCFG0_SSID_CAP 0x00c4
80#define cfgMSI_MAP_CAP_LIST 0x00c8
81#define cfgMSI_MAP_CAP 0x00ca
82#define cfgMSI_MAP_ADDR_LO 0x00cc
83#define cfgMSI_MAP_ADDR_HI 0x00d0
84#define cfgPSWUSCFG0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
85#define cfgPSWUSCFG0_PCIE_VENDOR_SPECIFIC_HDR 0x0104
86#define cfgPSWUSCFG0_PCIE_VENDOR_SPECIFIC1 0x0108
87#define cfgPSWUSCFG0_PCIE_VENDOR_SPECIFIC2 0x010c
88#define cfgPSWUSCFG0_PCIE_VC_ENH_CAP_LIST 0x0110
89#define cfgPSWUSCFG0_PCIE_PORT_VC_CAP_REG1 0x0114
90#define cfgPSWUSCFG0_PCIE_PORT_VC_CAP_REG2 0x0118
91#define cfgPSWUSCFG0_PCIE_PORT_VC_CNTL 0x011c
92#define cfgPSWUSCFG0_PCIE_PORT_VC_STATUS 0x011e
93#define cfgPSWUSCFG0_PCIE_VC0_RESOURCE_CAP 0x0120
94#define cfgPSWUSCFG0_PCIE_VC0_RESOURCE_CNTL 0x0124
95#define cfgPSWUSCFG0_PCIE_VC0_RESOURCE_STATUS 0x012a
96#define cfgPSWUSCFG0_PCIE_VC1_RESOURCE_CAP 0x012c
97#define cfgPSWUSCFG0_PCIE_VC1_RESOURCE_CNTL 0x0130
98#define cfgPSWUSCFG0_PCIE_VC1_RESOURCE_STATUS 0x0136
99#define cfgPSWUSCFG0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140
100#define cfgPSWUSCFG0_PCIE_DEV_SERIAL_NUM_DW1 0x0144
101#define cfgPSWUSCFG0_PCIE_DEV_SERIAL_NUM_DW2 0x0148
102#define cfgPSWUSCFG0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150
103#define cfgPSWUSCFG0_PCIE_UNCORR_ERR_STATUS 0x0154
104#define cfgPSWUSCFG0_PCIE_UNCORR_ERR_MASK 0x0158
105#define cfgPSWUSCFG0_PCIE_UNCORR_ERR_SEVERITY 0x015c
106#define cfgPSWUSCFG0_PCIE_CORR_ERR_STATUS 0x0160
107#define cfgPSWUSCFG0_PCIE_CORR_ERR_MASK 0x0164
108#define cfgPSWUSCFG0_PCIE_ADV_ERR_CAP_CNTL 0x0168
109#define cfgPSWUSCFG0_PCIE_HDR_LOG0 0x016c
110#define cfgPSWUSCFG0_PCIE_HDR_LOG1 0x0170
111#define cfgPSWUSCFG0_PCIE_HDR_LOG2 0x0174
112#define cfgPSWUSCFG0_PCIE_HDR_LOG3 0x0178
113#define cfgPSWUSCFG0_PCIE_TLP_PREFIX_LOG0 0x0188
114#define cfgPSWUSCFG0_PCIE_TLP_PREFIX_LOG1 0x018c
115#define cfgPSWUSCFG0_PCIE_TLP_PREFIX_LOG2 0x0190
116#define cfgPSWUSCFG0_PCIE_TLP_PREFIX_LOG3 0x0194
117#define cfgPSWUSCFG0_PCIE_SECONDARY_ENH_CAP_LIST 0x0270
118#define cfgPSWUSCFG0_PCIE_LINK_CNTL3 0x0274
119#define cfgPSWUSCFG0_PCIE_LANE_ERROR_STATUS 0x0278
120#define cfgPSWUSCFG0_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c
121#define cfgPSWUSCFG0_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e
122#define cfgPSWUSCFG0_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280
123#define cfgPSWUSCFG0_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282
124#define cfgPSWUSCFG0_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284
125#define cfgPSWUSCFG0_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286
126#define cfgPSWUSCFG0_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288
127#define cfgPSWUSCFG0_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a
128#define cfgPSWUSCFG0_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c
129#define cfgPSWUSCFG0_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e
130#define cfgPSWUSCFG0_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290
131#define cfgPSWUSCFG0_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292
132#define cfgPSWUSCFG0_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294
133#define cfgPSWUSCFG0_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296
134#define cfgPSWUSCFG0_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298
135#define cfgPSWUSCFG0_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a
136#define cfgPSWUSCFG0_PCIE_ACS_ENH_CAP_LIST 0x02a0
137#define cfgPSWUSCFG0_PCIE_ACS_CAP 0x02a4
138#define cfgPSWUSCFG0_PCIE_ACS_CNTL 0x02a6
139#define cfgPSWUSCFG0_PCIE_MC_ENH_CAP_LIST 0x02f0
140#define cfgPSWUSCFG0_PCIE_MC_CAP 0x02f4
141#define cfgPSWUSCFG0_PCIE_MC_CNTL 0x02f6
142#define cfgPSWUSCFG0_PCIE_MC_ADDR0 0x02f8
143#define cfgPSWUSCFG0_PCIE_MC_ADDR1 0x02fc
144#define cfgPSWUSCFG0_PCIE_MC_RCV0 0x0300
145#define cfgPSWUSCFG0_PCIE_MC_RCV1 0x0304
146#define cfgPSWUSCFG0_PCIE_MC_BLOCK_ALL0 0x0308
147#define cfgPSWUSCFG0_PCIE_MC_BLOCK_ALL1 0x030c
148#define cfgPSWUSCFG0_PCIE_MC_BLOCK_UNTRANSLATED_0 0x0310
149#define cfgPSWUSCFG0_PCIE_MC_BLOCK_UNTRANSLATED_1 0x0314
150#define cfgPCIE_MC_OVERLAY_BAR0 0x0318
151#define cfgPCIE_MC_OVERLAY_BAR1 0x031c
152#define cfgPSWUSCFG0_PCIE_LTR_ENH_CAP_LIST 0x0320
153#define cfgPSWUSCFG0_PCIE_LTR_CAP 0x0324
154#define cfgPSWUSCFG0_PCIE_ARI_ENH_CAP_LIST 0x0328
155#define cfgPSWUSCFG0_PCIE_ARI_CAP 0x032c
156#define cfgPSWUSCFG0_PCIE_ARI_CNTL 0x032e
157#define cfgPCIE_L1_PM_SUB_CAP_LIST 0x0370
158#define cfgPCIE_L1_PM_SUB_CAP 0x0374
159#define cfgPCIE_L1_PM_SUB_CNTL 0x0378
160#define cfgPCIE_L1_PM_SUB_CNTL2 0x037c
161#define cfgPCIE_ESM_CAP_LIST 0x03c4
162#define cfgPCIE_ESM_HEADER_1 0x03c8
163#define cfgPCIE_ESM_HEADER_2 0x03cc
164#define cfgPCIE_ESM_STATUS 0x03ce
165#define cfgPCIE_ESM_CTRL 0x03d0
166#define cfgPCIE_ESM_CAP_1 0x03d4
167#define cfgPCIE_ESM_CAP_2 0x03d8
168#define cfgPCIE_ESM_CAP_3 0x03dc
169#define cfgPCIE_ESM_CAP_4 0x03e0
170#define cfgPCIE_ESM_CAP_5 0x03e4
171#define cfgPCIE_ESM_CAP_6 0x03e8
172#define cfgPCIE_ESM_CAP_7 0x03ec
173
174
175// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_bifcfgdecp
176// base address: 0x0
177#define cfgBIF_CFG_DEV0_EPF0_0_VENDOR_ID 0x0000
178#define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_ID 0x0002
179#define cfgBIF_CFG_DEV0_EPF0_0_COMMAND 0x0004
180#define cfgBIF_CFG_DEV0_EPF0_0_STATUS 0x0006
181#define cfgBIF_CFG_DEV0_EPF0_0_REVISION_ID 0x0008
182#define cfgBIF_CFG_DEV0_EPF0_0_PROG_INTERFACE 0x0009
183#define cfgBIF_CFG_DEV0_EPF0_0_SUB_CLASS 0x000a
184#define cfgBIF_CFG_DEV0_EPF0_0_BASE_CLASS 0x000b
185#define cfgBIF_CFG_DEV0_EPF0_0_CACHE_LINE 0x000c
186#define cfgBIF_CFG_DEV0_EPF0_0_LATENCY 0x000d
187#define cfgBIF_CFG_DEV0_EPF0_0_HEADER 0x000e
188#define cfgBIF_CFG_DEV0_EPF0_0_BIST 0x000f
189#define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_1 0x0010
190#define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_2 0x0014
191#define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_3 0x0018
192#define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_4 0x001c
193#define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_5 0x0020
194#define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_6 0x0024
195#define cfgBIF_CFG_DEV0_EPF0_0_ADAPTER_ID 0x002c
196#define cfgBIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR 0x0030
197#define cfgBIF_CFG_DEV0_EPF0_0_CAP_PTR 0x0034
198#define cfgBIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE 0x003c
199#define cfgBIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN 0x003d
200#define cfgBIF_CFG_DEV0_EPF0_0_MIN_GRANT 0x003e
201#define cfgBIF_CFG_DEV0_EPF0_0_MAX_LATENCY 0x003f
202#define cfgBIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST 0x0048
203#define cfgBIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W 0x004c
204#define cfgBIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST 0x0050
205#define cfgBIF_CFG_DEV0_EPF0_0_PMI_CAP 0x0052
206#define cfgBIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL 0x0054
207#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST 0x0064
208#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_CAP 0x0066
209#define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_CAP 0x0068
210#define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL 0x006c
211#define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS 0x006e
212#define cfgBIF_CFG_DEV0_EPF0_0_LINK_CAP 0x0070
213#define cfgBIF_CFG_DEV0_EPF0_0_LINK_CNTL 0x0074
214#define cfgBIF_CFG_DEV0_EPF0_0_LINK_STATUS 0x0076
215#define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_CAP2 0x0088
216#define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2 0x008c
217#define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2 0x008e
218#define cfgBIF_CFG_DEV0_EPF0_0_LINK_CAP2 0x0090
219#define cfgBIF_CFG_DEV0_EPF0_0_LINK_CNTL2 0x0094
220#define cfgBIF_CFG_DEV0_EPF0_0_LINK_STATUS2 0x0096
221#define cfgBIF_CFG_DEV0_EPF0_0_SLOT_CAP2 0x0098
222#define cfgBIF_CFG_DEV0_EPF0_0_SLOT_CNTL2 0x009c
223#define cfgBIF_CFG_DEV0_EPF0_0_SLOT_STATUS2 0x009e
224#define cfgBIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST 0x00a0
225#define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL 0x00a2
226#define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO 0x00a4
227#define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI 0x00a8
228#define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA 0x00a8
229#define cfgBIF_CFG_DEV0_EPF0_0_MSI_MASK 0x00ac
230#define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64 0x00ac
231#define cfgBIF_CFG_DEV0_EPF0_0_MSI_MASK_64 0x00b0
232#define cfgBIF_CFG_DEV0_EPF0_0_MSI_PENDING 0x00b0
233#define cfgBIF_CFG_DEV0_EPF0_0_MSI_PENDING_64 0x00b4
234#define cfgBIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST 0x00c0
235#define cfgBIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL 0x00c2
236#define cfgBIF_CFG_DEV0_EPF0_0_MSIX_TABLE 0x00c4
237#define cfgBIF_CFG_DEV0_EPF0_0_MSIX_PBA 0x00c8
238#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
239#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104
240#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1 0x0108
241#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2 0x010c
242#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST 0x0110
243#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1 0x0114
244#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2 0x0118
245#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL 0x011c
246#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS 0x011e
247#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP 0x0120
248#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL 0x0124
249#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS 0x012a
250#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP 0x012c
251#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL 0x0130
252#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS 0x0136
253#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140
254#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1 0x0144
255#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2 0x0148
256#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150
257#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS 0x0154
258#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK 0x0158
259#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY 0x015c
260#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS 0x0160
261#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK 0x0164
262#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL 0x0168
263#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0 0x016c
264#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1 0x0170
265#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2 0x0174
266#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3 0x0178
267#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0 0x0188
268#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1 0x018c
269#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2 0x0190
270#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3 0x0194
271#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST 0x0200
272#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP 0x0204
273#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL 0x0208
274#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP 0x020c
275#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL 0x0210
276#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP 0x0214
277#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL 0x0218
278#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP 0x021c
279#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL 0x0220
280#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP 0x0224
281#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL 0x0228
282#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP 0x022c
283#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL 0x0230
284#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240
285#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT 0x0244
286#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA 0x0248
287#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP 0x024c
288#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST 0x0250
289#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP 0x0254
290#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR 0x0258
291#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS 0x025c
292#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL 0x025e
293#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260
294#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261
295#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262
296#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263
297#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264
298#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265
299#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266
300#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267
301#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST 0x0270
302#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3 0x0274
303#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS 0x0278
304#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c
305#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e
306#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280
307#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282
308#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284
309#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286
310#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288
311#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a
312#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c
313#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e
314#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290
315#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292
316#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294
317#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296
318#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298
319#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a
320#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST 0x02a0
321#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP 0x02a4
322#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL 0x02a6
323#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST 0x02b0
324#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP 0x02b4
325#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL 0x02b6
326#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST 0x02c0
327#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL 0x02c4
328#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS 0x02c6
329#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY 0x02c8
330#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC 0x02cc
331#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST 0x02d0
332#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP 0x02d4
333#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL 0x02d6
334#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST 0x02e0
335#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP 0x02e4
336#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CNTL 0x02e8
337#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST 0x02f0
338#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP 0x02f4
339#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL 0x02f6
340#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0 0x02f8
341#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR1 0x02fc
342#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV0 0x0300
343#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV1 0x0304
344#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL0 0x0308
345#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL1 0x030c
346#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_0 0x0310
347#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_1 0x0314
348#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST 0x0320
349#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP 0x0324
350#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST 0x0328
351#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP 0x032c
352#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL 0x032e
353#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST 0x0330
354#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP 0x0334
355#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL 0x0338
356#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS 0x033a
357#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS 0x033c
358#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS 0x033e
359#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS 0x0340
360#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK 0x0342
361#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET 0x0344
362#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE 0x0346
363#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID 0x034a
364#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE 0x034c
365#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE 0x0350
366#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0 0x0354
367#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1 0x0358
368#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2 0x035c
369#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3 0x0360
370#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4 0x0364
371#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5 0x0368
372#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0x036c
373#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV 0x0400
374#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV 0x0404
375#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW 0x0408
376#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE 0x040c
377#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS 0x0410
378#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL 0x0414
379#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 0x0418
380#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 0x041c
381#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 0x0420
382#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT 0x0424
383#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB 0x0428
384#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS 0x042c
385#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB 0x0430
386#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB 0x0434
387#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB 0x0438
388#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB 0x043c
389#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB 0x0440
390#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB 0x0444
391#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB 0x0448
392#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB 0x044c
393#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB 0x0450
394#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB 0x0454
395#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB 0x0458
396#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB 0x045c
397#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB 0x0460
398#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB 0x0464
399#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB 0x0468
400#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB 0x046c
401#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0 0x0470
402#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1 0x0474
403#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2 0x0478
404#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3 0x047c
405#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4 0x0480
406#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5 0x0484
407#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6 0x0488
408#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7 0x048c
409#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8 0x0490
410#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0 0x04a0
411#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1 0x04a4
412#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2 0x04a8
413#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3 0x04ac
414#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4 0x04b0
415#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5 0x04b4
416#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6 0x04b8
417#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7 0x04bc
418#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8 0x04c0
419#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0 0x04d0
420#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1 0x04d4
421#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2 0x04d8
422#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3 0x04dc
423#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4 0x04e0
424#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5 0x04e4
425#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6 0x04e8
426#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7 0x04ec
427#define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8 0x04f0
428
429
430// addressBlock: nbio_nbif_bif_cfg_dev0_epf1_bifcfgdecp
431// base address: 0x0
432#define cfgBIF_CFG_DEV0_EPF1_0_VENDOR_ID 0x0000
433#define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_ID 0x0002
434#define cfgBIF_CFG_DEV0_EPF1_0_COMMAND 0x0004
435#define cfgBIF_CFG_DEV0_EPF1_0_STATUS 0x0006
436#define cfgBIF_CFG_DEV0_EPF1_0_REVISION_ID 0x0008
437#define cfgBIF_CFG_DEV0_EPF1_0_PROG_INTERFACE 0x0009
438#define cfgBIF_CFG_DEV0_EPF1_0_SUB_CLASS 0x000a
439#define cfgBIF_CFG_DEV0_EPF1_0_BASE_CLASS 0x000b
440#define cfgBIF_CFG_DEV0_EPF1_0_CACHE_LINE 0x000c
441#define cfgBIF_CFG_DEV0_EPF1_0_LATENCY 0x000d
442#define cfgBIF_CFG_DEV0_EPF1_0_HEADER 0x000e
443#define cfgBIF_CFG_DEV0_EPF1_0_BIST 0x000f
444#define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_1 0x0010
445#define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_2 0x0014
446#define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_3 0x0018
447#define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_4 0x001c
448#define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_5 0x0020
449#define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_6 0x0024
450#define cfgBIF_CFG_DEV0_EPF1_0_ADAPTER_ID 0x002c
451#define cfgBIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR 0x0030
452#define cfgBIF_CFG_DEV0_EPF1_0_CAP_PTR 0x0034
453#define cfgBIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE 0x003c
454#define cfgBIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN 0x003d
455#define cfgBIF_CFG_DEV0_EPF1_0_MIN_GRANT 0x003e
456#define cfgBIF_CFG_DEV0_EPF1_0_MAX_LATENCY 0x003f
457#define cfgBIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST 0x0048
458#define cfgBIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W 0x004c
459#define cfgBIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST 0x0050
460#define cfgBIF_CFG_DEV0_EPF1_0_PMI_CAP 0x0052
461#define cfgBIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL 0x0054
462#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST 0x0064
463#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CAP 0x0066
464#define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CAP 0x0068
465#define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CNTL 0x006c
466#define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_STATUS 0x006e
467#define cfgBIF_CFG_DEV0_EPF1_0_LINK_CAP 0x0070
468#define cfgBIF_CFG_DEV0_EPF1_0_LINK_CNTL 0x0074
469#define cfgBIF_CFG_DEV0_EPF1_0_LINK_STATUS 0x0076
470#define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CAP2 0x0088
471#define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2 0x008c
472#define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2 0x008e
473#define cfgBIF_CFG_DEV0_EPF1_0_LINK_CAP2 0x0090
474#define cfgBIF_CFG_DEV0_EPF1_0_LINK_CNTL2 0x0094
475#define cfgBIF_CFG_DEV0_EPF1_0_LINK_STATUS2 0x0096
476#define cfgBIF_CFG_DEV0_EPF1_0_SLOT_CAP2 0x0098
477#define cfgBIF_CFG_DEV0_EPF1_0_SLOT_CNTL2 0x009c
478#define cfgBIF_CFG_DEV0_EPF1_0_SLOT_STATUS2 0x009e
479#define cfgBIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST 0x00a0
480#define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL 0x00a2
481#define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO 0x00a4
482#define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI 0x00a8
483#define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA 0x00a8
484#define cfgBIF_CFG_DEV0_EPF1_0_MSI_MASK 0x00ac
485#define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64 0x00ac
486#define cfgBIF_CFG_DEV0_EPF1_0_MSI_MASK_64 0x00b0
487#define cfgBIF_CFG_DEV0_EPF1_0_MSI_PENDING 0x00b0
488#define cfgBIF_CFG_DEV0_EPF1_0_MSI_PENDING_64 0x00b4
489#define cfgBIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST 0x00c0
490#define cfgBIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL 0x00c2
491#define cfgBIF_CFG_DEV0_EPF1_0_MSIX_TABLE 0x00c4
492#define cfgBIF_CFG_DEV0_EPF1_0_MSIX_PBA 0x00c8
493#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
494#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104
495#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1 0x0108
496#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2 0x010c
497#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC_ENH_CAP_LIST 0x0110
498#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1 0x0114
499#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG2 0x0118
500#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CNTL 0x011c
501#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_STATUS 0x011e
502#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP 0x0120
503#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL 0x0124
504#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_STATUS 0x012a
505#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP 0x012c
506#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL 0x0130
507#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_STATUS 0x0136
508#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140
509#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW1 0x0144
510#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW2 0x0148
511#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150
512#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS 0x0154
513#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK 0x0158
514#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY 0x015c
515#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS 0x0160
516#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK 0x0164
517#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL 0x0168
518#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0 0x016c
519#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1 0x0170
520#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2 0x0174
521#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3 0x0178
522#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0 0x0188
523#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1 0x018c
524#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2 0x0190
525#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3 0x0194
526#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST 0x0200
527#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP 0x0204
528#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL 0x0208
529#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP 0x020c
530#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL 0x0210
531#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP 0x0214
532#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL 0x0218
533#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP 0x021c
534#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL 0x0220
535#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP 0x0224
536#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL 0x0228
537#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP 0x022c
538#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL 0x0230
539#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240
540#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT 0x0244
541#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA 0x0248
542#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP 0x024c
543#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST 0x0250
544#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP 0x0254
545#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR 0x0258
546#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS 0x025c
547#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL 0x025e
548#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260
549#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261
550#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262
551#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263
552#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264
553#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265
554#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266
555#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267
556#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST 0x0270
557#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3 0x0274
558#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_ERROR_STATUS 0x0278
559#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c
560#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e
561#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280
562#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282
563#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284
564#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286
565#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288
566#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a
567#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c
568#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e
569#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290
570#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292
571#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294
572#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296
573#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298
574#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a
575#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST 0x02a0
576#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP 0x02a4
577#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL 0x02a6
578#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST 0x02b0
579#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP 0x02b4
580#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ATS_CNTL 0x02b6
581#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST 0x02c0
582#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_CNTL 0x02c4
583#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS 0x02c6
584#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY 0x02c8
585#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC 0x02cc
586#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST 0x02d0
587#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP 0x02d4
588#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL 0x02d6
589#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST 0x02e0
590#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP 0x02e4
591#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CNTL 0x02e8
592#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST 0x02f0
593#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP 0x02f4
594#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL 0x02f6
595#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0 0x02f8
596#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR1 0x02fc
597#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV0 0x0300
598#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV1 0x0304
599#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL0 0x0308
600#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL1 0x030c
601#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_0 0x0310
602#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_1 0x0314
603#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST 0x0320
604#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP 0x0324
605#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST 0x0328
606#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP 0x032c
607#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL 0x032e
608#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST 0x0330
609#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP 0x0334
610#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL 0x0338
611#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_STATUS 0x033a
612#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_INITIAL_VFS 0x033c
613#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_TOTAL_VFS 0x033e
614#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_NUM_VFS 0x0340
615#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FUNC_DEP_LINK 0x0342
616#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FIRST_VF_OFFSET 0x0344
617#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_STRIDE 0x0346
618#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_DEVICE_ID 0x034a
619#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE 0x034c
620#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE 0x0350
621#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_0 0x0354
622#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_1 0x0358
623#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_2 0x035c
624#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_3 0x0360
625#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_4 0x0364
626#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_5 0x0368
627#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0x036c
628#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV 0x0400
629#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV 0x0404
630#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW 0x0408
631#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE 0x040c
632#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS 0x0410
633#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL 0x0414
634#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 0x0418
635#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 0x041c
636#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 0x0420
637#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT 0x0424
638#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB 0x0428
639#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS 0x042c
640#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB 0x0430
641#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB 0x0434
642#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB 0x0438
643#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB 0x043c
644#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB 0x0440
645#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB 0x0444
646#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB 0x0448
647#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB 0x044c
648#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB 0x0450
649#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB 0x0454
650#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB 0x0458
651#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB 0x045c
652#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB 0x0460
653#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB 0x0464
654#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB 0x0468
655#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB 0x046c
656#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0 0x0470
657#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1 0x0474
658#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2 0x0478
659#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3 0x047c
660#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4 0x0480
661#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5 0x0484
662#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6 0x0488
663#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7 0x048c
664#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8 0x0490
665#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0 0x04a0
666#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1 0x04a4
667#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2 0x04a8
668#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3 0x04ac
669#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4 0x04b0
670#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5 0x04b4
671#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6 0x04b8
672#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7 0x04bc
673#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8 0x04c0
674#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0 0x04d0
675#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1 0x04d4
676#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2 0x04d8
677#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3 0x04dc
678#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4 0x04e0
679#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5 0x04e4
680#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6 0x04e8
681#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7 0x04ec
682#define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8 0x04f0
683
684
685// addressBlock: nbio_nbif_bif_cfg_dev0_swds_bifcfgdecp
686// base address: 0x0
687#define cfgBIF_CFG_DEV0_SWDS0_VENDOR_ID 0x0000
688#define cfgBIF_CFG_DEV0_SWDS0_DEVICE_ID 0x0002
689#define cfgBIF_CFG_DEV0_SWDS0_COMMAND 0x0004
690#define cfgBIF_CFG_DEV0_SWDS0_STATUS 0x0006
691#define cfgBIF_CFG_DEV0_SWDS0_REVISION_ID 0x0008
692#define cfgBIF_CFG_DEV0_SWDS0_PROG_INTERFACE 0x0009
693#define cfgBIF_CFG_DEV0_SWDS0_SUB_CLASS 0x000a
694#define cfgBIF_CFG_DEV0_SWDS0_BASE_CLASS 0x000b
695#define cfgBIF_CFG_DEV0_SWDS0_CACHE_LINE 0x000c
696#define cfgBIF_CFG_DEV0_SWDS0_LATENCY 0x000d
697#define cfgBIF_CFG_DEV0_SWDS0_HEADER 0x000e
698#define cfgBIF_CFG_DEV0_SWDS0_BIST 0x000f
699#define cfgBIF_CFG_DEV0_SWDS0_BASE_ADDR_1 0x0010
700#define cfgBIF_CFG_DEV0_SWDS0_SUB_BUS_NUMBER_LATENCY 0x0018
701#define cfgBIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT 0x001c
702#define cfgBIF_CFG_DEV0_SWDS0_SECONDARY_STATUS 0x001e
703#define cfgBIF_CFG_DEV0_SWDS0_MEM_BASE_LIMIT 0x0020
704#define cfgBIF_CFG_DEV0_SWDS0_PREF_BASE_LIMIT 0x0024
705#define cfgBIF_CFG_DEV0_SWDS0_PREF_BASE_UPPER 0x0028
706#define cfgBIF_CFG_DEV0_SWDS0_PREF_LIMIT_UPPER 0x002c
707#define cfgBIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT_HI 0x0030
708#define cfgBIF_CFG_DEV0_SWDS0_CAP_PTR 0x0034
709#define cfgBIF_CFG_DEV0_SWDS0_INTERRUPT_LINE 0x003c
710#define cfgBIF_CFG_DEV0_SWDS0_INTERRUPT_PIN 0x003d
711#define cfgBIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL 0x003e
712#define cfgBIF_CFG_DEV0_SWDS0_PMI_CAP_LIST 0x0050
713#define cfgBIF_CFG_DEV0_SWDS0_PMI_CAP 0x0052
714#define cfgBIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL 0x0054
715#define cfgBIF_CFG_DEV0_SWDS0_PCIE_CAP_LIST 0x0058
716#define cfgBIF_CFG_DEV0_SWDS0_PCIE_CAP 0x005a
717#define cfgBIF_CFG_DEV0_SWDS0_DEVICE_CAP 0x005c
718#define cfgBIF_CFG_DEV0_SWDS0_DEVICE_CNTL 0x0060
719#define cfgBIF_CFG_DEV0_SWDS0_DEVICE_STATUS 0x0062
720#define cfgBIF_CFG_DEV0_SWDS0_LINK_CAP 0x0064
721#define cfgBIF_CFG_DEV0_SWDS0_LINK_CNTL 0x0068
722#define cfgBIF_CFG_DEV0_SWDS0_LINK_STATUS 0x006a
723#define cfgBIF_CFG_DEV0_SWDS0_SLOT_CAP 0x006c
724#define cfgBIF_CFG_DEV0_SWDS0_SLOT_CNTL 0x0070
725#define cfgBIF_CFG_DEV0_SWDS0_SLOT_STATUS 0x0072
726#define cfgBIF_CFG_DEV0_SWDS0_DEVICE_CAP2 0x007c
727#define cfgBIF_CFG_DEV0_SWDS0_DEVICE_CNTL2 0x0080
728#define cfgBIF_CFG_DEV0_SWDS0_DEVICE_STATUS2 0x0082
729#define cfgBIF_CFG_DEV0_SWDS0_LINK_CAP2 0x0084
730#define cfgBIF_CFG_DEV0_SWDS0_LINK_CNTL2 0x0088
731#define cfgBIF_CFG_DEV0_SWDS0_LINK_STATUS2 0x008a
732#define cfgBIF_CFG_DEV0_SWDS0_SLOT_CAP2 0x008c
733#define cfgBIF_CFG_DEV0_SWDS0_SLOT_CNTL2 0x0090
734#define cfgBIF_CFG_DEV0_SWDS0_SLOT_STATUS2 0x0092
735#define cfgBIF_CFG_DEV0_SWDS0_MSI_CAP_LIST 0x00a0
736#define cfgBIF_CFG_DEV0_SWDS0_MSI_MSG_CNTL 0x00a2
737#define cfgBIF_CFG_DEV0_SWDS0_MSI_MSG_ADDR_LO 0x00a4
738#define cfgBIF_CFG_DEV0_SWDS0_MSI_MSG_ADDR_HI 0x00a8
739#define cfgBIF_CFG_DEV0_SWDS0_MSI_MSG_DATA 0x00a8
740#define cfgBIF_CFG_DEV0_SWDS0_MSI_MSG_DATA_64 0x00ac
741#define cfgBIF_CFG_DEV0_SWDS0_SSID_CAP_LIST 0x00c0
742#define cfgBIF_CFG_DEV0_SWDS0_SSID_CAP 0x00c4
743#define cfgBIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
744#define cfgBIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_HDR 0x0104
745#define cfgBIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC1 0x0108
746#define cfgBIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC2 0x010c
747#define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC_ENH_CAP_LIST 0x0110
748#define cfgBIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG1 0x0114
749#define cfgBIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG2 0x0118
750#define cfgBIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CNTL 0x011c
751#define cfgBIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_STATUS 0x011e
752#define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CAP 0x0120
753#define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CNTL 0x0124
754#define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_STATUS 0x012a
755#define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CAP 0x012c
756#define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CNTL 0x0130
757#define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_STATUS 0x0136
758#define cfgBIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140
759#define cfgBIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_DW1 0x0144
760#define cfgBIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_DW2 0x0148
761#define cfgBIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150
762#define cfgBIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS 0x0154
763#define cfgBIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK 0x0158
764#define cfgBIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY 0x015c
765#define cfgBIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS 0x0160
766#define cfgBIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK 0x0164
767#define cfgBIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL 0x0168
768#define cfgBIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG0 0x016c
769#define cfgBIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG1 0x0170
770#define cfgBIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG2 0x0174
771#define cfgBIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG3 0x0178
772#define cfgBIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG0 0x0188
773#define cfgBIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG1 0x018c
774#define cfgBIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG2 0x0190
775#define cfgBIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG3 0x0194
776#define cfgBIF_CFG_DEV0_SWDS0_PCIE_SECONDARY_ENH_CAP_LIST 0x0270
777#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LINK_CNTL3 0x0274
778#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_ERROR_STATUS 0x0278
779#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c
780#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e
781#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280
782#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282
783#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284
784#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286
785#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288
786#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a
787#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c
788#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e
789#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290
790#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292
791#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294
792#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296
793#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298
794#define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a
795#define cfgBIF_CFG_DEV0_SWDS0_PCIE_ACS_ENH_CAP_LIST 0x02a0
796#define cfgBIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP 0x02a4
797#define cfgBIF_CFG_DEV0_SWDS0_PCIE_ACS_CNTL 0x02a6
798
799
800// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf0_bifcfgdecp
801// base address: 0x0
802#define cfgBIF_CFG_DEV0_EPF0_VF0_0_VENDOR_ID 0x0000
803#define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_ID 0x0002
804#define cfgBIF_CFG_DEV0_EPF0_VF0_0_COMMAND 0x0004
805#define cfgBIF_CFG_DEV0_EPF0_VF0_0_STATUS 0x0006
806#define cfgBIF_CFG_DEV0_EPF0_VF0_0_REVISION_ID 0x0008
807#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PROG_INTERFACE 0x0009
808#define cfgBIF_CFG_DEV0_EPF0_VF0_0_SUB_CLASS 0x000a
809#define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_CLASS 0x000b
810#define cfgBIF_CFG_DEV0_EPF0_VF0_0_CACHE_LINE 0x000c
811#define cfgBIF_CFG_DEV0_EPF0_VF0_0_LATENCY 0x000d
812#define cfgBIF_CFG_DEV0_EPF0_VF0_0_HEADER 0x000e
813#define cfgBIF_CFG_DEV0_EPF0_VF0_0_BIST 0x000f
814#define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_1 0x0010
815#define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_2 0x0014
816#define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_3 0x0018
817#define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_4 0x001c
818#define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_5 0x0020
819#define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_6 0x0024
820#define cfgBIF_CFG_DEV0_EPF0_VF0_0_ADAPTER_ID 0x002c
821#define cfgBIF_CFG_DEV0_EPF0_VF0_0_ROM_BASE_ADDR 0x0030
822#define cfgBIF_CFG_DEV0_EPF0_VF0_0_CAP_PTR 0x0034
823#define cfgBIF_CFG_DEV0_EPF0_VF0_0_INTERRUPT_LINE 0x003c
824#define cfgBIF_CFG_DEV0_EPF0_VF0_0_INTERRUPT_PIN 0x003d
825#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP_LIST 0x0064
826#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP 0x0066
827#define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP 0x0068
828#define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL 0x006c
829#define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS 0x006e
830#define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP 0x0070
831#define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL 0x0074
832#define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS 0x0076
833#define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2 0x0088
834#define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2 0x008c
835#define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS2 0x008e
836#define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2 0x0090
837#define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2 0x0094
838#define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2 0x0096
839#define cfgBIF_CFG_DEV0_EPF0_VF0_0_SLOT_CAP2 0x0098
840#define cfgBIF_CFG_DEV0_EPF0_VF0_0_SLOT_CNTL2 0x009c
841#define cfgBIF_CFG_DEV0_EPF0_VF0_0_SLOT_STATUS2 0x009e
842#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_CAP_LIST 0x00a0
843#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL 0x00a2
844#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_ADDR_LO 0x00a4
845#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_ADDR_HI 0x00a8
846#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_DATA 0x00a8
847#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MASK 0x00ac
848#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_DATA_64 0x00ac
849#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MASK_64 0x00b0
850#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_PENDING 0x00b0
851#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_PENDING_64 0x00b4
852#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSIX_CAP_LIST 0x00c0
853#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSIX_MSG_CNTL 0x00c2
854#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSIX_TABLE 0x00c4
855#define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSIX_PBA 0x00c8
856#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
857#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104
858#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC1 0x0108
859#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC2 0x010c
860#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150
861#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS 0x0154
862#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK 0x0158
863#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY 0x015c
864#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS 0x0160
865#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK 0x0164
866#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL 0x0168
867#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG0 0x016c
868#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG1 0x0170
869#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG2 0x0174
870#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG3 0x0178
871#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG0 0x0188
872#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG1 0x018c
873#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG2 0x0190
874#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG3 0x0194
875#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_ENH_CAP_LIST 0x02b0
876#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_CAP 0x02b4
877#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_CNTL 0x02b6
878#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_ENH_CAP_LIST 0x0328
879#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CAP 0x032c
880#define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CNTL 0x032e
881
882
883// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf1_bifcfgdecp
884// base address: 0x0
885#define cfgBIF_CFG_DEV0_EPF0_VF1_0_VENDOR_ID 0x0000
886#define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_ID 0x0002
887#define cfgBIF_CFG_DEV0_EPF0_VF1_0_COMMAND 0x0004
888#define cfgBIF_CFG_DEV0_EPF0_VF1_0_STATUS 0x0006
889#define cfgBIF_CFG_DEV0_EPF0_VF1_0_REVISION_ID 0x0008
890#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PROG_INTERFACE 0x0009
891#define cfgBIF_CFG_DEV0_EPF0_VF1_0_SUB_CLASS 0x000a
892#define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_CLASS 0x000b
893#define cfgBIF_CFG_DEV0_EPF0_VF1_0_CACHE_LINE 0x000c
894#define cfgBIF_CFG_DEV0_EPF0_VF1_0_LATENCY 0x000d
895#define cfgBIF_CFG_DEV0_EPF0_VF1_0_HEADER 0x000e
896#define cfgBIF_CFG_DEV0_EPF0_VF1_0_BIST 0x000f
897#define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_1 0x0010
898#define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_2 0x0014
899#define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_3 0x0018
900#define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_4 0x001c
901#define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_5 0x0020
902#define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_6 0x0024
903#define cfgBIF_CFG_DEV0_EPF0_VF1_0_ADAPTER_ID 0x002c
904#define cfgBIF_CFG_DEV0_EPF0_VF1_0_ROM_BASE_ADDR 0x0030
905#define cfgBIF_CFG_DEV0_EPF0_VF1_0_CAP_PTR 0x0034
906#define cfgBIF_CFG_DEV0_EPF0_VF1_0_INTERRUPT_LINE 0x003c
907#define cfgBIF_CFG_DEV0_EPF0_VF1_0_INTERRUPT_PIN 0x003d
908#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP_LIST 0x0064
909#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP 0x0066
910#define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP 0x0068
911#define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL 0x006c
912#define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS 0x006e
913#define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP 0x0070
914#define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL 0x0074
915#define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS 0x0076
916#define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2 0x0088
917#define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2 0x008c
918#define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS2 0x008e
919#define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2 0x0090
920#define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2 0x0094
921#define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2 0x0096
922#define cfgBIF_CFG_DEV0_EPF0_VF1_0_SLOT_CAP2 0x0098
923#define cfgBIF_CFG_DEV0_EPF0_VF1_0_SLOT_CNTL2 0x009c
924#define cfgBIF_CFG_DEV0_EPF0_VF1_0_SLOT_STATUS2 0x009e
925#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_CAP_LIST 0x00a0
926#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL 0x00a2
927#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_ADDR_LO 0x00a4
928#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_ADDR_HI 0x00a8
929#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_DATA 0x00a8
930#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MASK 0x00ac
931#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_DATA_64 0x00ac
932#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MASK_64 0x00b0
933#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_PENDING 0x00b0
934#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_PENDING_64 0x00b4
935#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSIX_CAP_LIST 0x00c0
936#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSIX_MSG_CNTL 0x00c2
937#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSIX_TABLE 0x00c4
938#define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSIX_PBA 0x00c8
939#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
940#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104
941#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC1 0x0108
942#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC2 0x010c
943#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150
944#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS 0x0154
945#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK 0x0158
946#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY 0x015c
947#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS 0x0160
948#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK 0x0164
949#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL 0x0168
950#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG0 0x016c
951#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG1 0x0170
952#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG2 0x0174
953#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG3 0x0178
954#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG0 0x0188
955#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG1 0x018c
956#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG2 0x0190
957#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG3 0x0194
958#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_ENH_CAP_LIST 0x02b0
959#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_CAP 0x02b4
960#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_CNTL 0x02b6
961#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_ENH_CAP_LIST 0x0328
962#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CAP 0x032c
963#define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CNTL 0x032e
964
965
966// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf2_bifcfgdecp
967// base address: 0x0
968#define cfgBIF_CFG_DEV0_EPF0_VF2_0_VENDOR_ID 0x0000
969#define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_ID 0x0002
970#define cfgBIF_CFG_DEV0_EPF0_VF2_0_COMMAND 0x0004
971#define cfgBIF_CFG_DEV0_EPF0_VF2_0_STATUS 0x0006
972#define cfgBIF_CFG_DEV0_EPF0_VF2_0_REVISION_ID 0x0008
973#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PROG_INTERFACE 0x0009
974#define cfgBIF_CFG_DEV0_EPF0_VF2_0_SUB_CLASS 0x000a
975#define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_CLASS 0x000b
976#define cfgBIF_CFG_DEV0_EPF0_VF2_0_CACHE_LINE 0x000c
977#define cfgBIF_CFG_DEV0_EPF0_VF2_0_LATENCY 0x000d
978#define cfgBIF_CFG_DEV0_EPF0_VF2_0_HEADER 0x000e
979#define cfgBIF_CFG_DEV0_EPF0_VF2_0_BIST 0x000f
980#define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_1 0x0010
981#define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_2 0x0014
982#define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_3 0x0018
983#define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_4 0x001c
984#define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_5 0x0020
985#define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_6 0x0024
986#define cfgBIF_CFG_DEV0_EPF0_VF2_0_ADAPTER_ID 0x002c
987#define cfgBIF_CFG_DEV0_EPF0_VF2_0_ROM_BASE_ADDR 0x0030
988#define cfgBIF_CFG_DEV0_EPF0_VF2_0_CAP_PTR 0x0034
989#define cfgBIF_CFG_DEV0_EPF0_VF2_0_INTERRUPT_LINE 0x003c
990#define cfgBIF_CFG_DEV0_EPF0_VF2_0_INTERRUPT_PIN 0x003d
991#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP_LIST 0x0064
992#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP 0x0066
993#define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP 0x0068
994#define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL 0x006c
995#define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS 0x006e
996#define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP 0x0070
997#define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL 0x0074
998#define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS 0x0076
999#define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2 0x0088
1000#define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2 0x008c
1001#define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS2 0x008e
1002#define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2 0x0090
1003#define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2 0x0094
1004#define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2 0x0096
1005#define cfgBIF_CFG_DEV0_EPF0_VF2_0_SLOT_CAP2 0x0098
1006#define cfgBIF_CFG_DEV0_EPF0_VF2_0_SLOT_CNTL2 0x009c
1007#define cfgBIF_CFG_DEV0_EPF0_VF2_0_SLOT_STATUS2 0x009e
1008#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_CAP_LIST 0x00a0
1009#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL 0x00a2
1010#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_ADDR_LO 0x00a4
1011#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_ADDR_HI 0x00a8
1012#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_DATA 0x00a8
1013#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MASK 0x00ac
1014#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_DATA_64 0x00ac
1015#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MASK_64 0x00b0
1016#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_PENDING 0x00b0
1017#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_PENDING_64 0x00b4
1018#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSIX_CAP_LIST 0x00c0
1019#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSIX_MSG_CNTL 0x00c2
1020#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSIX_TABLE 0x00c4
1021#define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSIX_PBA 0x00c8
1022#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
1023#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104
1024#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC1 0x0108
1025#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC2 0x010c
1026#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150
1027#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS 0x0154
1028#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK 0x0158
1029#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY 0x015c
1030#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS 0x0160
1031#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK 0x0164
1032#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL 0x0168
1033#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG0 0x016c
1034#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG1 0x0170
1035#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG2 0x0174
1036#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG3 0x0178
1037#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG0 0x0188
1038#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG1 0x018c
1039#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG2 0x0190
1040#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG3 0x0194
1041#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_ENH_CAP_LIST 0x02b0
1042#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_CAP 0x02b4
1043#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_CNTL 0x02b6
1044#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_ENH_CAP_LIST 0x0328
1045#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CAP 0x032c
1046#define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CNTL 0x032e
1047
1048
1049// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf3_bifcfgdecp
1050// base address: 0x0
1051#define cfgBIF_CFG_DEV0_EPF0_VF3_0_VENDOR_ID 0x0000
1052#define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_ID 0x0002
1053#define cfgBIF_CFG_DEV0_EPF0_VF3_0_COMMAND 0x0004
1054#define cfgBIF_CFG_DEV0_EPF0_VF3_0_STATUS 0x0006
1055#define cfgBIF_CFG_DEV0_EPF0_VF3_0_REVISION_ID 0x0008
1056#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PROG_INTERFACE 0x0009
1057#define cfgBIF_CFG_DEV0_EPF0_VF3_0_SUB_CLASS 0x000a
1058#define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_CLASS 0x000b
1059#define cfgBIF_CFG_DEV0_EPF0_VF3_0_CACHE_LINE 0x000c
1060#define cfgBIF_CFG_DEV0_EPF0_VF3_0_LATENCY 0x000d
1061#define cfgBIF_CFG_DEV0_EPF0_VF3_0_HEADER 0x000e
1062#define cfgBIF_CFG_DEV0_EPF0_VF3_0_BIST 0x000f
1063#define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_1 0x0010
1064#define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_2 0x0014
1065#define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_3 0x0018
1066#define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_4 0x001c
1067#define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_5 0x0020
1068#define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_6 0x0024
1069#define cfgBIF_CFG_DEV0_EPF0_VF3_0_ADAPTER_ID 0x002c
1070#define cfgBIF_CFG_DEV0_EPF0_VF3_0_ROM_BASE_ADDR 0x0030
1071#define cfgBIF_CFG_DEV0_EPF0_VF3_0_CAP_PTR 0x0034
1072#define cfgBIF_CFG_DEV0_EPF0_VF3_0_INTERRUPT_LINE 0x003c
1073#define cfgBIF_CFG_DEV0_EPF0_VF3_0_INTERRUPT_PIN 0x003d
1074#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP_LIST 0x0064
1075#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP 0x0066
1076#define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP 0x0068
1077#define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL 0x006c
1078#define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS 0x006e
1079#define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP 0x0070
1080#define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL 0x0074
1081#define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS 0x0076
1082#define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2 0x0088
1083#define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2 0x008c
1084#define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS2 0x008e
1085#define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2 0x0090
1086#define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2 0x0094
1087#define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2 0x0096
1088#define cfgBIF_CFG_DEV0_EPF0_VF3_0_SLOT_CAP2 0x0098
1089#define cfgBIF_CFG_DEV0_EPF0_VF3_0_SLOT_CNTL2 0x009c
1090#define cfgBIF_CFG_DEV0_EPF0_VF3_0_SLOT_STATUS2 0x009e
1091#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_CAP_LIST 0x00a0
1092#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL 0x00a2
1093#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_ADDR_LO 0x00a4
1094#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_ADDR_HI 0x00a8
1095#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_DATA 0x00a8
1096#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MASK 0x00ac
1097#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_DATA_64 0x00ac
1098#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MASK_64 0x00b0
1099#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_PENDING 0x00b0
1100#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_PENDING_64 0x00b4
1101#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSIX_CAP_LIST 0x00c0
1102#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSIX_MSG_CNTL 0x00c2
1103#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSIX_TABLE 0x00c4
1104#define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSIX_PBA 0x00c8
1105#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
1106#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104
1107#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC1 0x0108
1108#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC2 0x010c
1109#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150
1110#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS 0x0154
1111#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK 0x0158
1112#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY 0x015c
1113#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS 0x0160
1114#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK 0x0164
1115#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL 0x0168
1116#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG0 0x016c
1117#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG1 0x0170
1118#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG2 0x0174
1119#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG3 0x0178
1120#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG0 0x0188
1121#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG1 0x018c
1122#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG2 0x0190
1123#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG3 0x0194
1124#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_ENH_CAP_LIST 0x02b0
1125#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_CAP 0x02b4
1126#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_CNTL 0x02b6
1127#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_ENH_CAP_LIST 0x0328
1128#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CAP 0x032c
1129#define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CNTL 0x032e
1130
1131
1132// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf4_bifcfgdecp
1133// base address: 0x0
1134#define cfgBIF_CFG_DEV0_EPF0_VF4_0_VENDOR_ID 0x0000
1135#define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_ID 0x0002
1136#define cfgBIF_CFG_DEV0_EPF0_VF4_0_COMMAND 0x0004
1137#define cfgBIF_CFG_DEV0_EPF0_VF4_0_STATUS 0x0006
1138#define cfgBIF_CFG_DEV0_EPF0_VF4_0_REVISION_ID 0x0008
1139#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PROG_INTERFACE 0x0009
1140#define cfgBIF_CFG_DEV0_EPF0_VF4_0_SUB_CLASS 0x000a
1141#define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_CLASS 0x000b
1142#define cfgBIF_CFG_DEV0_EPF0_VF4_0_CACHE_LINE 0x000c
1143#define cfgBIF_CFG_DEV0_EPF0_VF4_0_LATENCY 0x000d
1144#define cfgBIF_CFG_DEV0_EPF0_VF4_0_HEADER 0x000e
1145#define cfgBIF_CFG_DEV0_EPF0_VF4_0_BIST 0x000f
1146#define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_1 0x0010
1147#define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_2 0x0014
1148#define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_3 0x0018
1149#define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_4 0x001c
1150#define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_5 0x0020
1151#define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_6 0x0024
1152#define cfgBIF_CFG_DEV0_EPF0_VF4_0_ADAPTER_ID 0x002c
1153#define cfgBIF_CFG_DEV0_EPF0_VF4_0_ROM_BASE_ADDR 0x0030
1154#define cfgBIF_CFG_DEV0_EPF0_VF4_0_CAP_PTR 0x0034
1155#define cfgBIF_CFG_DEV0_EPF0_VF4_0_INTERRUPT_LINE 0x003c
1156#define cfgBIF_CFG_DEV0_EPF0_VF4_0_INTERRUPT_PIN 0x003d
1157#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP_LIST 0x0064
1158#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP 0x0066
1159#define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP 0x0068
1160#define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL 0x006c
1161#define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS 0x006e
1162#define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP 0x0070
1163#define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL 0x0074
1164#define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS 0x0076
1165#define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2 0x0088
1166#define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2 0x008c
1167#define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS2 0x008e
1168#define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2 0x0090
1169#define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2 0x0094
1170#define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2 0x0096
1171#define cfgBIF_CFG_DEV0_EPF0_VF4_0_SLOT_CAP2 0x0098
1172#define cfgBIF_CFG_DEV0_EPF0_VF4_0_SLOT_CNTL2 0x009c
1173#define cfgBIF_CFG_DEV0_EPF0_VF4_0_SLOT_STATUS2 0x009e
1174#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_CAP_LIST 0x00a0
1175#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL 0x00a2
1176#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_ADDR_LO 0x00a4
1177#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_ADDR_HI 0x00a8
1178#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_DATA 0x00a8
1179#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MASK 0x00ac
1180#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_DATA_64 0x00ac
1181#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MASK_64 0x00b0
1182#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_PENDING 0x00b0
1183#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_PENDING_64 0x00b4
1184#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSIX_CAP_LIST 0x00c0
1185#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSIX_MSG_CNTL 0x00c2
1186#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSIX_TABLE 0x00c4
1187#define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSIX_PBA 0x00c8
1188#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
1189#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104
1190#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC1 0x0108
1191#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC2 0x010c
1192#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150
1193#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS 0x0154
1194#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK 0x0158
1195#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY 0x015c
1196#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS 0x0160
1197#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK 0x0164
1198#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL 0x0168
1199#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG0 0x016c
1200#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG1 0x0170
1201#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG2 0x0174
1202#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG3 0x0178
1203#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG0 0x0188
1204#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG1 0x018c
1205#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG2 0x0190
1206#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG3 0x0194
1207#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_ENH_CAP_LIST 0x02b0
1208#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_CAP 0x02b4
1209#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_CNTL 0x02b6
1210#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_ENH_CAP_LIST 0x0328
1211#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CAP 0x032c
1212#define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CNTL 0x032e
1213
1214
1215// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf5_bifcfgdecp
1216// base address: 0x0
1217#define cfgBIF_CFG_DEV0_EPF0_VF5_0_VENDOR_ID 0x0000
1218#define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_ID 0x0002
1219#define cfgBIF_CFG_DEV0_EPF0_VF5_0_COMMAND 0x0004
1220#define cfgBIF_CFG_DEV0_EPF0_VF5_0_STATUS 0x0006
1221#define cfgBIF_CFG_DEV0_EPF0_VF5_0_REVISION_ID 0x0008
1222#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PROG_INTERFACE 0x0009
1223#define cfgBIF_CFG_DEV0_EPF0_VF5_0_SUB_CLASS 0x000a
1224#define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_CLASS 0x000b
1225#define cfgBIF_CFG_DEV0_EPF0_VF5_0_CACHE_LINE 0x000c
1226#define cfgBIF_CFG_DEV0_EPF0_VF5_0_LATENCY 0x000d
1227#define cfgBIF_CFG_DEV0_EPF0_VF5_0_HEADER 0x000e
1228#define cfgBIF_CFG_DEV0_EPF0_VF5_0_BIST 0x000f
1229#define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_1 0x0010
1230#define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_2 0x0014
1231#define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_3 0x0018
1232#define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_4 0x001c
1233#define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_5 0x0020
1234#define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_6 0x0024
1235#define cfgBIF_CFG_DEV0_EPF0_VF5_0_ADAPTER_ID 0x002c
1236#define cfgBIF_CFG_DEV0_EPF0_VF5_0_ROM_BASE_ADDR 0x0030
1237#define cfgBIF_CFG_DEV0_EPF0_VF5_0_CAP_PTR 0x0034
1238#define cfgBIF_CFG_DEV0_EPF0_VF5_0_INTERRUPT_LINE 0x003c
1239#define cfgBIF_CFG_DEV0_EPF0_VF5_0_INTERRUPT_PIN 0x003d
1240#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP_LIST 0x0064
1241#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP 0x0066
1242#define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP 0x0068
1243#define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL 0x006c
1244#define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS 0x006e
1245#define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP 0x0070
1246#define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL 0x0074
1247#define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS 0x0076
1248#define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2 0x0088
1249#define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2 0x008c
1250#define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS2 0x008e
1251#define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2 0x0090
1252#define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2 0x0094
1253#define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2 0x0096
1254#define cfgBIF_CFG_DEV0_EPF0_VF5_0_SLOT_CAP2 0x0098
1255#define cfgBIF_CFG_DEV0_EPF0_VF5_0_SLOT_CNTL2 0x009c
1256#define cfgBIF_CFG_DEV0_EPF0_VF5_0_SLOT_STATUS2 0x009e
1257#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_CAP_LIST 0x00a0
1258#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL 0x00a2
1259#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_ADDR_LO 0x00a4
1260#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_ADDR_HI 0x00a8
1261#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_DATA 0x00a8
1262#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MASK 0x00ac
1263#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_DATA_64 0x00ac
1264#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MASK_64 0x00b0
1265#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_PENDING 0x00b0
1266#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_PENDING_64 0x00b4
1267#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSIX_CAP_LIST 0x00c0
1268#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSIX_MSG_CNTL 0x00c2
1269#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSIX_TABLE 0x00c4
1270#define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSIX_PBA 0x00c8
1271#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
1272#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104
1273#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC1 0x0108
1274#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC2 0x010c
1275#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150
1276#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS 0x0154
1277#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK 0x0158
1278#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY 0x015c
1279#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS 0x0160
1280#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK 0x0164
1281#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL 0x0168
1282#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG0 0x016c
1283#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG1 0x0170
1284#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG2 0x0174
1285#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG3 0x0178
1286#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG0 0x0188
1287#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG1 0x018c
1288#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG2 0x0190
1289#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG3 0x0194
1290#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_ENH_CAP_LIST 0x02b0
1291#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_CAP 0x02b4
1292#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_CNTL 0x02b6
1293#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_ENH_CAP_LIST 0x0328
1294#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CAP 0x032c
1295#define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CNTL 0x032e
1296
1297
1298// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf6_bifcfgdecp
1299// base address: 0x0
1300#define cfgBIF_CFG_DEV0_EPF0_VF6_0_VENDOR_ID 0x0000
1301#define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_ID 0x0002
1302#define cfgBIF_CFG_DEV0_EPF0_VF6_0_COMMAND 0x0004
1303#define cfgBIF_CFG_DEV0_EPF0_VF6_0_STATUS 0x0006
1304#define cfgBIF_CFG_DEV0_EPF0_VF6_0_REVISION_ID 0x0008
1305#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PROG_INTERFACE 0x0009
1306#define cfgBIF_CFG_DEV0_EPF0_VF6_0_SUB_CLASS 0x000a
1307#define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_CLASS 0x000b
1308#define cfgBIF_CFG_DEV0_EPF0_VF6_0_CACHE_LINE 0x000c
1309#define cfgBIF_CFG_DEV0_EPF0_VF6_0_LATENCY 0x000d
1310#define cfgBIF_CFG_DEV0_EPF0_VF6_0_HEADER 0x000e
1311#define cfgBIF_CFG_DEV0_EPF0_VF6_0_BIST 0x000f
1312#define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_1 0x0010
1313#define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_2 0x0014
1314#define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_3 0x0018
1315#define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_4 0x001c
1316#define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_5 0x0020
1317#define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_6 0x0024
1318#define cfgBIF_CFG_DEV0_EPF0_VF6_0_ADAPTER_ID 0x002c
1319#define cfgBIF_CFG_DEV0_EPF0_VF6_0_ROM_BASE_ADDR 0x0030
1320#define cfgBIF_CFG_DEV0_EPF0_VF6_0_CAP_PTR 0x0034
1321#define cfgBIF_CFG_DEV0_EPF0_VF6_0_INTERRUPT_LINE 0x003c
1322#define cfgBIF_CFG_DEV0_EPF0_VF6_0_INTERRUPT_PIN 0x003d
1323#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP_LIST 0x0064
1324#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP 0x0066
1325#define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP 0x0068
1326#define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL 0x006c
1327#define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS 0x006e
1328#define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP 0x0070
1329#define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL 0x0074
1330#define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS 0x0076
1331#define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2 0x0088
1332#define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2 0x008c
1333#define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS2 0x008e
1334#define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2 0x0090
1335#define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2 0x0094
1336#define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2 0x0096
1337#define cfgBIF_CFG_DEV0_EPF0_VF6_0_SLOT_CAP2 0x0098
1338#define cfgBIF_CFG_DEV0_EPF0_VF6_0_SLOT_CNTL2 0x009c
1339#define cfgBIF_CFG_DEV0_EPF0_VF6_0_SLOT_STATUS2 0x009e
1340#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_CAP_LIST 0x00a0
1341#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL 0x00a2
1342#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_ADDR_LO 0x00a4
1343#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_ADDR_HI 0x00a8
1344#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_DATA 0x00a8
1345#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MASK 0x00ac
1346#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_DATA_64 0x00ac
1347#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MASK_64 0x00b0
1348#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_PENDING 0x00b0
1349#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_PENDING_64 0x00b4
1350#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSIX_CAP_LIST 0x00c0
1351#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSIX_MSG_CNTL 0x00c2
1352#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSIX_TABLE 0x00c4
1353#define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSIX_PBA 0x00c8
1354#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
1355#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104
1356#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC1 0x0108
1357#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC2 0x010c
1358#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150
1359#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS 0x0154
1360#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK 0x0158
1361#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY 0x015c
1362#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS 0x0160
1363#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK 0x0164
1364#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL 0x0168
1365#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG0 0x016c
1366#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG1 0x0170
1367#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG2 0x0174
1368#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG3 0x0178
1369#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG0 0x0188
1370#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG1 0x018c
1371#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG2 0x0190
1372#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG3 0x0194
1373#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_ENH_CAP_LIST 0x02b0
1374#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_CAP 0x02b4
1375#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_CNTL 0x02b6
1376#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_ENH_CAP_LIST 0x0328
1377#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CAP 0x032c
1378#define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CNTL 0x032e
1379
1380
1381// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf7_bifcfgdecp
1382// base address: 0x0
1383#define cfgBIF_CFG_DEV0_EPF0_VF7_0_VENDOR_ID 0x0000
1384#define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_ID 0x0002
1385#define cfgBIF_CFG_DEV0_EPF0_VF7_0_COMMAND 0x0004
1386#define cfgBIF_CFG_DEV0_EPF0_VF7_0_STATUS 0x0006
1387#define cfgBIF_CFG_DEV0_EPF0_VF7_0_REVISION_ID 0x0008
1388#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PROG_INTERFACE 0x0009
1389#define cfgBIF_CFG_DEV0_EPF0_VF7_0_SUB_CLASS 0x000a
1390#define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_CLASS 0x000b
1391#define cfgBIF_CFG_DEV0_EPF0_VF7_0_CACHE_LINE 0x000c
1392#define cfgBIF_CFG_DEV0_EPF0_VF7_0_LATENCY 0x000d
1393#define cfgBIF_CFG_DEV0_EPF0_VF7_0_HEADER 0x000e
1394#define cfgBIF_CFG_DEV0_EPF0_VF7_0_BIST 0x000f
1395#define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_1 0x0010
1396#define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_2 0x0014
1397#define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_3 0x0018
1398#define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_4 0x001c
1399#define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_5 0x0020
1400#define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_6 0x0024
1401#define cfgBIF_CFG_DEV0_EPF0_VF7_0_ADAPTER_ID 0x002c
1402#define cfgBIF_CFG_DEV0_EPF0_VF7_0_ROM_BASE_ADDR 0x0030
1403#define cfgBIF_CFG_DEV0_EPF0_VF7_0_CAP_PTR 0x0034
1404#define cfgBIF_CFG_DEV0_EPF0_VF7_0_INTERRUPT_LINE 0x003c
1405#define cfgBIF_CFG_DEV0_EPF0_VF7_0_INTERRUPT_PIN 0x003d
1406#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP_LIST 0x0064
1407#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP 0x0066
1408#define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP 0x0068
1409#define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL 0x006c
1410#define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS 0x006e
1411#define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP 0x0070
1412#define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL 0x0074
1413#define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS 0x0076
1414#define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2 0x0088
1415#define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2 0x008c
1416#define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS2 0x008e
1417#define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2 0x0090
1418#define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2 0x0094
1419#define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2 0x0096
1420#define cfgBIF_CFG_DEV0_EPF0_VF7_0_SLOT_CAP2 0x0098
1421#define cfgBIF_CFG_DEV0_EPF0_VF7_0_SLOT_CNTL2 0x009c
1422#define cfgBIF_CFG_DEV0_EPF0_VF7_0_SLOT_STATUS2 0x009e
1423#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_CAP_LIST 0x00a0
1424#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL 0x00a2
1425#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_ADDR_LO 0x00a4
1426#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_ADDR_HI 0x00a8
1427#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_DATA 0x00a8
1428#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MASK 0x00ac
1429#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_DATA_64 0x00ac
1430#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MASK_64 0x00b0
1431#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_PENDING 0x00b0
1432#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_PENDING_64 0x00b4
1433#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSIX_CAP_LIST 0x00c0
1434#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSIX_MSG_CNTL 0x00c2
1435#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSIX_TABLE 0x00c4
1436#define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSIX_PBA 0x00c8
1437#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
1438#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104
1439#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC1 0x0108
1440#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC2 0x010c
1441#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150
1442#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS 0x0154
1443#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK 0x0158
1444#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY 0x015c
1445#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS 0x0160
1446#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK 0x0164
1447#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL 0x0168
1448#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG0 0x016c
1449#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG1 0x0170
1450#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG2 0x0174
1451#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG3 0x0178
1452#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG0 0x0188
1453#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG1 0x018c
1454#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG2 0x0190
1455#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG3 0x0194
1456#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_ENH_CAP_LIST 0x02b0
1457#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_CAP 0x02b4
1458#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_CNTL 0x02b6
1459#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_ENH_CAP_LIST 0x0328
1460#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CAP 0x032c
1461#define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CNTL 0x032e
1462
1463
1464// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf8_bifcfgdecp
1465// base address: 0x0
1466#define cfgBIF_CFG_DEV0_EPF0_VF8_0_VENDOR_ID 0x0000
1467#define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_ID 0x0002
1468#define cfgBIF_CFG_DEV0_EPF0_VF8_0_COMMAND 0x0004
1469#define cfgBIF_CFG_DEV0_EPF0_VF8_0_STATUS 0x0006
1470#define cfgBIF_CFG_DEV0_EPF0_VF8_0_REVISION_ID 0x0008
1471#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PROG_INTERFACE 0x0009
1472#define cfgBIF_CFG_DEV0_EPF0_VF8_0_SUB_CLASS 0x000a
1473#define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_CLASS 0x000b
1474#define cfgBIF_CFG_DEV0_EPF0_VF8_0_CACHE_LINE 0x000c
1475#define cfgBIF_CFG_DEV0_EPF0_VF8_0_LATENCY 0x000d
1476#define cfgBIF_CFG_DEV0_EPF0_VF8_0_HEADER 0x000e
1477#define cfgBIF_CFG_DEV0_EPF0_VF8_0_BIST 0x000f
1478#define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_1 0x0010
1479#define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_2 0x0014
1480#define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_3 0x0018
1481#define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_4 0x001c
1482#define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_5 0x0020
1483#define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_6 0x0024
1484#define cfgBIF_CFG_DEV0_EPF0_VF8_0_ADAPTER_ID 0x002c
1485#define cfgBIF_CFG_DEV0_EPF0_VF8_0_ROM_BASE_ADDR 0x0030
1486#define cfgBIF_CFG_DEV0_EPF0_VF8_0_CAP_PTR 0x0034
1487#define cfgBIF_CFG_DEV0_EPF0_VF8_0_INTERRUPT_LINE 0x003c
1488#define cfgBIF_CFG_DEV0_EPF0_VF8_0_INTERRUPT_PIN 0x003d
1489#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP_LIST 0x0064
1490#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP 0x0066
1491#define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP 0x0068
1492#define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL 0x006c
1493#define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS 0x006e
1494#define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP 0x0070
1495#define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL 0x0074
1496#define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS 0x0076
1497#define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2 0x0088
1498#define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2 0x008c
1499#define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS2 0x008e
1500#define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2 0x0090
1501#define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2 0x0094
1502#define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2 0x0096
1503#define cfgBIF_CFG_DEV0_EPF0_VF8_0_SLOT_CAP2 0x0098
1504#define cfgBIF_CFG_DEV0_EPF0_VF8_0_SLOT_CNTL2 0x009c
1505#define cfgBIF_CFG_DEV0_EPF0_VF8_0_SLOT_STATUS2 0x009e
1506#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_CAP_LIST 0x00a0
1507#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL 0x00a2
1508#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_ADDR_LO 0x00a4
1509#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_ADDR_HI 0x00a8
1510#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_DATA 0x00a8
1511#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MASK 0x00ac
1512#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_DATA_64 0x00ac
1513#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MASK_64 0x00b0
1514#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_PENDING 0x00b0
1515#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_PENDING_64 0x00b4
1516#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSIX_CAP_LIST 0x00c0
1517#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSIX_MSG_CNTL 0x00c2
1518#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSIX_TABLE 0x00c4
1519#define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSIX_PBA 0x00c8
1520#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
1521#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104
1522#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC1 0x0108
1523#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC2 0x010c
1524#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150
1525#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS 0x0154
1526#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK 0x0158
1527#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY 0x015c
1528#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS 0x0160
1529#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK 0x0164
1530#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL 0x0168
1531#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG0 0x016c
1532#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG1 0x0170
1533#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG2 0x0174
1534#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG3 0x0178
1535#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG0 0x0188
1536#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG1 0x018c
1537#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG2 0x0190
1538#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG3 0x0194
1539#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_ENH_CAP_LIST 0x02b0
1540#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_CAP 0x02b4
1541#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_CNTL 0x02b6
1542#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_ENH_CAP_LIST 0x0328
1543#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CAP 0x032c
1544#define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CNTL 0x032e
1545
1546
1547// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf9_bifcfgdecp
1548// base address: 0x0
1549#define cfgBIF_CFG_DEV0_EPF0_VF9_0_VENDOR_ID 0x0000
1550#define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_ID 0x0002
1551#define cfgBIF_CFG_DEV0_EPF0_VF9_0_COMMAND 0x0004
1552#define cfgBIF_CFG_DEV0_EPF0_VF9_0_STATUS 0x0006
1553#define cfgBIF_CFG_DEV0_EPF0_VF9_0_REVISION_ID 0x0008
1554#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PROG_INTERFACE 0x0009
1555#define cfgBIF_CFG_DEV0_EPF0_VF9_0_SUB_CLASS 0x000a
1556#define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_CLASS 0x000b
1557#define cfgBIF_CFG_DEV0_EPF0_VF9_0_CACHE_LINE 0x000c
1558#define cfgBIF_CFG_DEV0_EPF0_VF9_0_LATENCY 0x000d
1559#define cfgBIF_CFG_DEV0_EPF0_VF9_0_HEADER 0x000e
1560#define cfgBIF_CFG_DEV0_EPF0_VF9_0_BIST 0x000f
1561#define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_1 0x0010
1562#define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_2 0x0014
1563#define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_3 0x0018
1564#define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_4 0x001c
1565#define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_5 0x0020
1566#define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_6 0x0024
1567#define cfgBIF_CFG_DEV0_EPF0_VF9_0_ADAPTER_ID 0x002c
1568#define cfgBIF_CFG_DEV0_EPF0_VF9_0_ROM_BASE_ADDR 0x0030
1569#define cfgBIF_CFG_DEV0_EPF0_VF9_0_CAP_PTR 0x0034
1570#define cfgBIF_CFG_DEV0_EPF0_VF9_0_INTERRUPT_LINE 0x003c
1571#define cfgBIF_CFG_DEV0_EPF0_VF9_0_INTERRUPT_PIN 0x003d
1572#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP_LIST 0x0064
1573#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP 0x0066
1574#define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP 0x0068
1575#define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL 0x006c
1576#define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS 0x006e
1577#define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP 0x0070
1578#define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL 0x0074
1579#define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS 0x0076
1580#define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2 0x0088
1581#define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2 0x008c
1582#define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS2 0x008e
1583#define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2 0x0090
1584#define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2 0x0094
1585#define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2 0x0096
1586#define cfgBIF_CFG_DEV0_EPF0_VF9_0_SLOT_CAP2 0x0098
1587#define cfgBIF_CFG_DEV0_EPF0_VF9_0_SLOT_CNTL2 0x009c
1588#define cfgBIF_CFG_DEV0_EPF0_VF9_0_SLOT_STATUS2 0x009e
1589#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_CAP_LIST 0x00a0
1590#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL 0x00a2
1591#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_ADDR_LO 0x00a4
1592#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_ADDR_HI 0x00a8
1593#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_DATA 0x00a8
1594#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MASK 0x00ac
1595#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_DATA_64 0x00ac
1596#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MASK_64 0x00b0
1597#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_PENDING 0x00b0
1598#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_PENDING_64 0x00b4
1599#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSIX_CAP_LIST 0x00c0
1600#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSIX_MSG_CNTL 0x00c2
1601#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSIX_TABLE 0x00c4
1602#define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSIX_PBA 0x00c8
1603#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
1604#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104
1605#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC1 0x0108
1606#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC2 0x010c
1607#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150
1608#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS 0x0154
1609#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK 0x0158
1610#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY 0x015c
1611#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS 0x0160
1612#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK 0x0164
1613#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL 0x0168
1614#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG0 0x016c
1615#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG1 0x0170
1616#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG2 0x0174
1617#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG3 0x0178
1618#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG0 0x0188
1619#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG1 0x018c
1620#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG2 0x0190
1621#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG3 0x0194
1622#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_ENH_CAP_LIST 0x02b0
1623#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_CAP 0x02b4
1624#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_CNTL 0x02b6
1625#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_ENH_CAP_LIST 0x0328
1626#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CAP 0x032c
1627#define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CNTL 0x032e
1628
1629
1630// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf10_bifcfgdecp
1631// base address: 0x0
1632#define cfgBIF_CFG_DEV0_EPF0_VF10_0_VENDOR_ID 0x0000
1633#define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_ID 0x0002
1634#define cfgBIF_CFG_DEV0_EPF0_VF10_0_COMMAND 0x0004
1635#define cfgBIF_CFG_DEV0_EPF0_VF10_0_STATUS 0x0006
1636#define cfgBIF_CFG_DEV0_EPF0_VF10_0_REVISION_ID 0x0008
1637#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PROG_INTERFACE 0x0009
1638#define cfgBIF_CFG_DEV0_EPF0_VF10_0_SUB_CLASS 0x000a
1639#define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_CLASS 0x000b
1640#define cfgBIF_CFG_DEV0_EPF0_VF10_0_CACHE_LINE 0x000c
1641#define cfgBIF_CFG_DEV0_EPF0_VF10_0_LATENCY 0x000d
1642#define cfgBIF_CFG_DEV0_EPF0_VF10_0_HEADER 0x000e
1643#define cfgBIF_CFG_DEV0_EPF0_VF10_0_BIST 0x000f
1644#define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_1 0x0010
1645#define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_2 0x0014
1646#define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_3 0x0018
1647#define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_4 0x001c
1648#define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_5 0x0020
1649#define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_6 0x0024
1650#define cfgBIF_CFG_DEV0_EPF0_VF10_0_ADAPTER_ID 0x002c
1651#define cfgBIF_CFG_DEV0_EPF0_VF10_0_ROM_BASE_ADDR 0x0030
1652#define cfgBIF_CFG_DEV0_EPF0_VF10_0_CAP_PTR 0x0034
1653#define cfgBIF_CFG_DEV0_EPF0_VF10_0_INTERRUPT_LINE 0x003c
1654#define cfgBIF_CFG_DEV0_EPF0_VF10_0_INTERRUPT_PIN 0x003d
1655#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP_LIST 0x0064
1656#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP 0x0066
1657#define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP 0x0068
1658#define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL 0x006c
1659#define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS 0x006e
1660#define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP 0x0070
1661#define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL 0x0074
1662#define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS 0x0076
1663#define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2 0x0088
1664#define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2 0x008c
1665#define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS2 0x008e
1666#define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2 0x0090
1667#define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2 0x0094
1668#define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2 0x0096
1669#define cfgBIF_CFG_DEV0_EPF0_VF10_0_SLOT_CAP2 0x0098
1670#define cfgBIF_CFG_DEV0_EPF0_VF10_0_SLOT_CNTL2 0x009c
1671#define cfgBIF_CFG_DEV0_EPF0_VF10_0_SLOT_STATUS2 0x009e
1672#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_CAP_LIST 0x00a0
1673#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL 0x00a2
1674#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_ADDR_LO 0x00a4
1675#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_ADDR_HI 0x00a8
1676#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_DATA 0x00a8
1677#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MASK 0x00ac
1678#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_DATA_64 0x00ac
1679#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MASK_64 0x00b0
1680#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_PENDING 0x00b0
1681#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_PENDING_64 0x00b4
1682#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSIX_CAP_LIST 0x00c0
1683#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSIX_MSG_CNTL 0x00c2
1684#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSIX_TABLE 0x00c4
1685#define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSIX_PBA 0x00c8
1686#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
1687#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104
1688#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC1 0x0108
1689#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC2 0x010c
1690#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150
1691#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS 0x0154
1692#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK 0x0158
1693#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY 0x015c
1694#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS 0x0160
1695#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK 0x0164
1696#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL 0x0168
1697#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG0 0x016c
1698#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG1 0x0170
1699#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG2 0x0174
1700#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG3 0x0178
1701#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG0 0x0188
1702#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG1 0x018c
1703#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG2 0x0190
1704#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG3 0x0194
1705#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_ENH_CAP_LIST 0x02b0
1706#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_CAP 0x02b4
1707#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_CNTL 0x02b6
1708#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_ENH_CAP_LIST 0x0328
1709#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CAP 0x032c
1710#define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CNTL 0x032e
1711
1712
1713// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf11_bifcfgdecp
1714// base address: 0x0
1715#define cfgBIF_CFG_DEV0_EPF0_VF11_0_VENDOR_ID 0x0000
1716#define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_ID 0x0002
1717#define cfgBIF_CFG_DEV0_EPF0_VF11_0_COMMAND 0x0004
1718#define cfgBIF_CFG_DEV0_EPF0_VF11_0_STATUS 0x0006
1719#define cfgBIF_CFG_DEV0_EPF0_VF11_0_REVISION_ID 0x0008
1720#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PROG_INTERFACE 0x0009
1721#define cfgBIF_CFG_DEV0_EPF0_VF11_0_SUB_CLASS 0x000a
1722#define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_CLASS 0x000b
1723#define cfgBIF_CFG_DEV0_EPF0_VF11_0_CACHE_LINE 0x000c
1724#define cfgBIF_CFG_DEV0_EPF0_VF11_0_LATENCY 0x000d
1725#define cfgBIF_CFG_DEV0_EPF0_VF11_0_HEADER 0x000e
1726#define cfgBIF_CFG_DEV0_EPF0_VF11_0_BIST 0x000f
1727#define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_1 0x0010
1728#define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_2 0x0014
1729#define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_3 0x0018
1730#define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_4 0x001c
1731#define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_5 0x0020
1732#define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_6 0x0024
1733#define cfgBIF_CFG_DEV0_EPF0_VF11_0_ADAPTER_ID 0x002c
1734#define cfgBIF_CFG_DEV0_EPF0_VF11_0_ROM_BASE_ADDR 0x0030
1735#define cfgBIF_CFG_DEV0_EPF0_VF11_0_CAP_PTR 0x0034
1736#define cfgBIF_CFG_DEV0_EPF0_VF11_0_INTERRUPT_LINE 0x003c
1737#define cfgBIF_CFG_DEV0_EPF0_VF11_0_INTERRUPT_PIN 0x003d
1738#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP_LIST 0x0064
1739#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP 0x0066
1740#define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP 0x0068
1741#define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL 0x006c
1742#define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS 0x006e
1743#define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP 0x0070
1744#define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL 0x0074
1745#define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS 0x0076
1746#define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2 0x0088
1747#define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2 0x008c
1748#define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS2 0x008e
1749#define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2 0x0090
1750#define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2 0x0094
1751#define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2 0x0096
1752#define cfgBIF_CFG_DEV0_EPF0_VF11_0_SLOT_CAP2 0x0098
1753#define cfgBIF_CFG_DEV0_EPF0_VF11_0_SLOT_CNTL2 0x009c
1754#define cfgBIF_CFG_DEV0_EPF0_VF11_0_SLOT_STATUS2 0x009e
1755#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_CAP_LIST 0x00a0
1756#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL 0x00a2
1757#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_ADDR_LO 0x00a4
1758#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_ADDR_HI 0x00a8
1759#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_DATA 0x00a8
1760#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MASK 0x00ac
1761#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_DATA_64 0x00ac
1762#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MASK_64 0x00b0
1763#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_PENDING 0x00b0
1764#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_PENDING_64 0x00b4
1765#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSIX_CAP_LIST 0x00c0
1766#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSIX_MSG_CNTL 0x00c2
1767#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSIX_TABLE 0x00c4
1768#define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSIX_PBA 0x00c8
1769#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
1770#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104
1771#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC1 0x0108
1772#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC2 0x010c
1773#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150
1774#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS 0x0154
1775#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK 0x0158
1776#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY 0x015c
1777#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS 0x0160
1778#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK 0x0164
1779#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL 0x0168
1780#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG0 0x016c
1781#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG1 0x0170
1782#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG2 0x0174
1783#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG3 0x0178
1784#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG0 0x0188
1785#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG1 0x018c
1786#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG2 0x0190
1787#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG3 0x0194
1788#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_ENH_CAP_LIST 0x02b0
1789#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_CAP 0x02b4
1790#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_CNTL 0x02b6
1791#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_ENH_CAP_LIST 0x0328
1792#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CAP 0x032c
1793#define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CNTL 0x032e
1794
1795
1796// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf12_bifcfgdecp
1797// base address: 0x0
1798#define cfgBIF_CFG_DEV0_EPF0_VF12_0_VENDOR_ID 0x0000
1799#define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_ID 0x0002
1800#define cfgBIF_CFG_DEV0_EPF0_VF12_0_COMMAND 0x0004
1801#define cfgBIF_CFG_DEV0_EPF0_VF12_0_STATUS 0x0006
1802#define cfgBIF_CFG_DEV0_EPF0_VF12_0_REVISION_ID 0x0008
1803#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PROG_INTERFACE 0x0009
1804#define cfgBIF_CFG_DEV0_EPF0_VF12_0_SUB_CLASS 0x000a
1805#define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_CLASS 0x000b
1806#define cfgBIF_CFG_DEV0_EPF0_VF12_0_CACHE_LINE 0x000c
1807#define cfgBIF_CFG_DEV0_EPF0_VF12_0_LATENCY 0x000d
1808#define cfgBIF_CFG_DEV0_EPF0_VF12_0_HEADER 0x000e
1809#define cfgBIF_CFG_DEV0_EPF0_VF12_0_BIST 0x000f
1810#define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_1 0x0010
1811#define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_2 0x0014
1812#define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_3 0x0018
1813#define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_4 0x001c
1814#define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_5 0x0020
1815#define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_6 0x0024
1816#define cfgBIF_CFG_DEV0_EPF0_VF12_0_ADAPTER_ID 0x002c
1817#define cfgBIF_CFG_DEV0_EPF0_VF12_0_ROM_BASE_ADDR 0x0030
1818#define cfgBIF_CFG_DEV0_EPF0_VF12_0_CAP_PTR 0x0034
1819#define cfgBIF_CFG_DEV0_EPF0_VF12_0_INTERRUPT_LINE 0x003c
1820#define cfgBIF_CFG_DEV0_EPF0_VF12_0_INTERRUPT_PIN 0x003d
1821#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP_LIST 0x0064
1822#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP 0x0066
1823#define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP 0x0068
1824#define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL 0x006c
1825#define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS 0x006e
1826#define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP 0x0070
1827#define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL 0x0074
1828#define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS 0x0076
1829#define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2 0x0088
1830#define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2 0x008c
1831#define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS2 0x008e
1832#define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2 0x0090
1833#define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2 0x0094
1834#define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2 0x0096
1835#define cfgBIF_CFG_DEV0_EPF0_VF12_0_SLOT_CAP2 0x0098
1836#define cfgBIF_CFG_DEV0_EPF0_VF12_0_SLOT_CNTL2 0x009c
1837#define cfgBIF_CFG_DEV0_EPF0_VF12_0_SLOT_STATUS2 0x009e
1838#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_CAP_LIST 0x00a0
1839#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL 0x00a2
1840#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_ADDR_LO 0x00a4
1841#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_ADDR_HI 0x00a8
1842#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_DATA 0x00a8
1843#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MASK 0x00ac
1844#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_DATA_64 0x00ac
1845#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MASK_64 0x00b0
1846#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_PENDING 0x00b0
1847#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_PENDING_64 0x00b4
1848#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSIX_CAP_LIST 0x00c0
1849#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSIX_MSG_CNTL 0x00c2
1850#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSIX_TABLE 0x00c4
1851#define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSIX_PBA 0x00c8
1852#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
1853#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104
1854#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC1 0x0108
1855#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC2 0x010c
1856#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150
1857#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS 0x0154
1858#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK 0x0158
1859#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY 0x015c
1860#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS 0x0160
1861#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK 0x0164
1862#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL 0x0168
1863#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG0 0x016c
1864#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG1 0x0170
1865#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG2 0x0174
1866#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG3 0x0178
1867#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG0 0x0188
1868#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG1 0x018c
1869#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG2 0x0190
1870#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG3 0x0194
1871#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_ENH_CAP_LIST 0x02b0
1872#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_CAP 0x02b4
1873#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_CNTL 0x02b6
1874#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_ENH_CAP_LIST 0x0328
1875#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CAP 0x032c
1876#define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CNTL 0x032e
1877
1878
1879// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf13_bifcfgdecp
1880// base address: 0x0
1881#define cfgBIF_CFG_DEV0_EPF0_VF13_0_VENDOR_ID 0x0000
1882#define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_ID 0x0002
1883#define cfgBIF_CFG_DEV0_EPF0_VF13_0_COMMAND 0x0004
1884#define cfgBIF_CFG_DEV0_EPF0_VF13_0_STATUS 0x0006
1885#define cfgBIF_CFG_DEV0_EPF0_VF13_0_REVISION_ID 0x0008
1886#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PROG_INTERFACE 0x0009
1887#define cfgBIF_CFG_DEV0_EPF0_VF13_0_SUB_CLASS 0x000a
1888#define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_CLASS 0x000b
1889#define cfgBIF_CFG_DEV0_EPF0_VF13_0_CACHE_LINE 0x000c
1890#define cfgBIF_CFG_DEV0_EPF0_VF13_0_LATENCY 0x000d
1891#define cfgBIF_CFG_DEV0_EPF0_VF13_0_HEADER 0x000e
1892#define cfgBIF_CFG_DEV0_EPF0_VF13_0_BIST 0x000f
1893#define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_1 0x0010
1894#define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_2 0x0014
1895#define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_3 0x0018
1896#define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_4 0x001c
1897#define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_5 0x0020
1898#define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_6 0x0024
1899#define cfgBIF_CFG_DEV0_EPF0_VF13_0_ADAPTER_ID 0x002c
1900#define cfgBIF_CFG_DEV0_EPF0_VF13_0_ROM_BASE_ADDR 0x0030
1901#define cfgBIF_CFG_DEV0_EPF0_VF13_0_CAP_PTR 0x0034
1902#define cfgBIF_CFG_DEV0_EPF0_VF13_0_INTERRUPT_LINE 0x003c
1903#define cfgBIF_CFG_DEV0_EPF0_VF13_0_INTERRUPT_PIN 0x003d
1904#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP_LIST 0x0064
1905#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP 0x0066
1906#define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP 0x0068
1907#define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL 0x006c
1908#define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS 0x006e
1909#define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP 0x0070
1910#define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL 0x0074
1911#define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS 0x0076
1912#define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2 0x0088
1913#define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2 0x008c
1914#define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS2 0x008e
1915#define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2 0x0090
1916#define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2 0x0094
1917#define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2 0x0096
1918#define cfgBIF_CFG_DEV0_EPF0_VF13_0_SLOT_CAP2 0x0098
1919#define cfgBIF_CFG_DEV0_EPF0_VF13_0_SLOT_CNTL2 0x009c
1920#define cfgBIF_CFG_DEV0_EPF0_VF13_0_SLOT_STATUS2 0x009e
1921#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_CAP_LIST 0x00a0
1922#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL 0x00a2
1923#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_ADDR_LO 0x00a4
1924#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_ADDR_HI 0x00a8
1925#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_DATA 0x00a8
1926#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MASK 0x00ac
1927#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_DATA_64 0x00ac
1928#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MASK_64 0x00b0
1929#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_PENDING 0x00b0
1930#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_PENDING_64 0x00b4
1931#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSIX_CAP_LIST 0x00c0
1932#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSIX_MSG_CNTL 0x00c2
1933#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSIX_TABLE 0x00c4
1934#define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSIX_PBA 0x00c8
1935#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
1936#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104
1937#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC1 0x0108
1938#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC2 0x010c
1939#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150
1940#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS 0x0154
1941#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK 0x0158
1942#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY 0x015c
1943#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS 0x0160
1944#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK 0x0164
1945#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL 0x0168
1946#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG0 0x016c
1947#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG1 0x0170
1948#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG2 0x0174
1949#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG3 0x0178
1950#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG0 0x0188
1951#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG1 0x018c
1952#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG2 0x0190
1953#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG3 0x0194
1954#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_ENH_CAP_LIST 0x02b0
1955#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_CAP 0x02b4
1956#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_CNTL 0x02b6
1957#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_ENH_CAP_LIST 0x0328
1958#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CAP 0x032c
1959#define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CNTL 0x032e
1960
1961
1962// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf14_bifcfgdecp
1963// base address: 0x0
1964#define cfgBIF_CFG_DEV0_EPF0_VF14_0_VENDOR_ID 0x0000
1965#define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_ID 0x0002
1966#define cfgBIF_CFG_DEV0_EPF0_VF14_0_COMMAND 0x0004
1967#define cfgBIF_CFG_DEV0_EPF0_VF14_0_STATUS 0x0006
1968#define cfgBIF_CFG_DEV0_EPF0_VF14_0_REVISION_ID 0x0008
1969#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PROG_INTERFACE 0x0009
1970#define cfgBIF_CFG_DEV0_EPF0_VF14_0_SUB_CLASS 0x000a
1971#define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_CLASS 0x000b
1972#define cfgBIF_CFG_DEV0_EPF0_VF14_0_CACHE_LINE 0x000c
1973#define cfgBIF_CFG_DEV0_EPF0_VF14_0_LATENCY 0x000d
1974#define cfgBIF_CFG_DEV0_EPF0_VF14_0_HEADER 0x000e
1975#define cfgBIF_CFG_DEV0_EPF0_VF14_0_BIST 0x000f
1976#define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_1 0x0010
1977#define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_2 0x0014
1978#define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_3 0x0018
1979#define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_4 0x001c
1980#define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_5 0x0020
1981#define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_6 0x0024
1982#define cfgBIF_CFG_DEV0_EPF0_VF14_0_ADAPTER_ID 0x002c
1983#define cfgBIF_CFG_DEV0_EPF0_VF14_0_ROM_BASE_ADDR 0x0030
1984#define cfgBIF_CFG_DEV0_EPF0_VF14_0_CAP_PTR 0x0034
1985#define cfgBIF_CFG_DEV0_EPF0_VF14_0_INTERRUPT_LINE 0x003c
1986#define cfgBIF_CFG_DEV0_EPF0_VF14_0_INTERRUPT_PIN 0x003d
1987#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP_LIST 0x0064
1988#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP 0x0066
1989#define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP 0x0068
1990#define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL 0x006c
1991#define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS 0x006e
1992#define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP 0x0070
1993#define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL 0x0074
1994#define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS 0x0076
1995#define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2 0x0088
1996#define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2 0x008c
1997#define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS2 0x008e
1998#define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2 0x0090
1999#define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2 0x0094
2000#define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2 0x0096
2001#define cfgBIF_CFG_DEV0_EPF0_VF14_0_SLOT_CAP2 0x0098
2002#define cfgBIF_CFG_DEV0_EPF0_VF14_0_SLOT_CNTL2 0x009c
2003#define cfgBIF_CFG_DEV0_EPF0_VF14_0_SLOT_STATUS2 0x009e
2004#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_CAP_LIST 0x00a0
2005#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL 0x00a2
2006#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_ADDR_LO 0x00a4
2007#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_ADDR_HI 0x00a8
2008#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_DATA 0x00a8
2009#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MASK 0x00ac
2010#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_DATA_64 0x00ac
2011#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MASK_64 0x00b0
2012#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_PENDING 0x00b0
2013#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_PENDING_64 0x00b4
2014#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSIX_CAP_LIST 0x00c0
2015#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSIX_MSG_CNTL 0x00c2
2016#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSIX_TABLE 0x00c4
2017#define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSIX_PBA 0x00c8
2018#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
2019#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104
2020#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC1 0x0108
2021#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC2 0x010c
2022#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150
2023#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS 0x0154
2024#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK 0x0158
2025#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY 0x015c
2026#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS 0x0160
2027#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK 0x0164
2028#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL 0x0168
2029#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG0 0x016c
2030#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG1 0x0170
2031#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG2 0x0174
2032#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG3 0x0178
2033#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG0 0x0188
2034#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG1 0x018c
2035#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG2 0x0190
2036#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG3 0x0194
2037#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_ENH_CAP_LIST 0x02b0
2038#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_CAP 0x02b4
2039#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_CNTL 0x02b6
2040#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_ENH_CAP_LIST 0x0328
2041#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CAP 0x032c
2042#define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CNTL 0x032e
2043
2044
2045// addressBlock: nbio_nbif_bif_cfg_dev0_epf0_vf15_bifcfgdecp
2046// base address: 0x0
2047#define cfgBIF_CFG_DEV0_EPF0_VF15_0_VENDOR_ID 0x0000
2048#define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_ID 0x0002
2049#define cfgBIF_CFG_DEV0_EPF0_VF15_0_COMMAND 0x0004
2050#define cfgBIF_CFG_DEV0_EPF0_VF15_0_STATUS 0x0006
2051#define cfgBIF_CFG_DEV0_EPF0_VF15_0_REVISION_ID 0x0008
2052#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PROG_INTERFACE 0x0009
2053#define cfgBIF_CFG_DEV0_EPF0_VF15_0_SUB_CLASS 0x000a
2054#define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_CLASS 0x000b
2055#define cfgBIF_CFG_DEV0_EPF0_VF15_0_CACHE_LINE 0x000c
2056#define cfgBIF_CFG_DEV0_EPF0_VF15_0_LATENCY 0x000d
2057#define cfgBIF_CFG_DEV0_EPF0_VF15_0_HEADER 0x000e
2058#define cfgBIF_CFG_DEV0_EPF0_VF15_0_BIST 0x000f
2059#define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_1 0x0010
2060#define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_2 0x0014
2061#define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_3 0x0018
2062#define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_4 0x001c
2063#define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_5 0x0020
2064#define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_6 0x0024
2065#define cfgBIF_CFG_DEV0_EPF0_VF15_0_ADAPTER_ID 0x002c
2066#define cfgBIF_CFG_DEV0_EPF0_VF15_0_ROM_BASE_ADDR 0x0030
2067#define cfgBIF_CFG_DEV0_EPF0_VF15_0_CAP_PTR 0x0034
2068#define cfgBIF_CFG_DEV0_EPF0_VF15_0_INTERRUPT_LINE 0x003c
2069#define cfgBIF_CFG_DEV0_EPF0_VF15_0_INTERRUPT_PIN 0x003d
2070#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP_LIST 0x0064
2071#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP 0x0066
2072#define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP 0x0068
2073#define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL 0x006c
2074#define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS 0x006e
2075#define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP 0x0070
2076#define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL 0x0074
2077#define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS 0x0076
2078#define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2 0x0088
2079#define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2 0x008c
2080#define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS2 0x008e
2081#define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2 0x0090
2082#define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2 0x0094
2083#define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2 0x0096
2084#define cfgBIF_CFG_DEV0_EPF0_VF15_0_SLOT_CAP2 0x0098
2085#define cfgBIF_CFG_DEV0_EPF0_VF15_0_SLOT_CNTL2 0x009c
2086#define cfgBIF_CFG_DEV0_EPF0_VF15_0_SLOT_STATUS2 0x009e
2087#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_CAP_LIST 0x00a0
2088#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL 0x00a2
2089#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_ADDR_LO 0x00a4
2090#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_ADDR_HI 0x00a8
2091#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_DATA 0x00a8
2092#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MASK 0x00ac
2093#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_DATA_64 0x00ac
2094#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MASK_64 0x00b0
2095#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_PENDING 0x00b0
2096#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_PENDING_64 0x00b4
2097#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSIX_CAP_LIST 0x00c0
2098#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSIX_MSG_CNTL 0x00c2
2099#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSIX_TABLE 0x00c4
2100#define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSIX_PBA 0x00c8
2101#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100
2102#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104
2103#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC1 0x0108
2104#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC2 0x010c
2105#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150
2106#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS 0x0154
2107#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK 0x0158
2108#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY 0x015c
2109#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS 0x0160
2110#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK 0x0164
2111#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL 0x0168
2112#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG0 0x016c
2113#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG1 0x0170
2114#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG2 0x0174
2115#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG3 0x0178
2116#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG0 0x0188
2117#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG1 0x018c
2118#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG2 0x0190
2119#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG3 0x0194
2120#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_ENH_CAP_LIST 0x02b0
2121#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_CAP 0x02b4
2122#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_CNTL 0x02b6
2123#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_ENH_CAP_LIST 0x0328
2124#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CAP 0x032c
2125#define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CNTL 0x032e
2126
2127
2128// addressBlock: nbio_nbif_bif_bx_pf_SYSPFVFDEC[0..767]
2129// base address: 0x0
2130#define mmMM_INDEX 0x0000
2131#define mmMM_INDEX_BASE_IDX 0
2132#define mmMM_DATA 0x0001
2133#define mmMM_DATA_BASE_IDX 0
2134#define mmMM_INDEX_HI 0x0006
2135#define mmMM_INDEX_HI_BASE_IDX 0
2136
2137
2138// addressBlock: nbio_nbif_bif_bx_pf_SYSDEC[0..767]
2139// base address: 0x0
2140#define mmSYSHUB_INDEX_OVLP 0x0008
2141#define mmSYSHUB_INDEX_OVLP_BASE_IDX 0
2142#define mmSYSHUB_DATA_OVLP 0x0009
2143#define mmSYSHUB_DATA_OVLP_BASE_IDX 0
2144#define mmPCIE_INDEX 0x000c
2145#define mmPCIE_INDEX_BASE_IDX 0
2146#define mmPCIE_DATA 0x000d
2147#define mmPCIE_DATA_BASE_IDX 0
2148#define mmPCIE_INDEX2 0x000e
2149#define mmPCIE_INDEX2_BASE_IDX 0
2150#define mmPCIE_DATA2 0x000f
2151#define mmPCIE_DATA2_BASE_IDX 0
2152#define mmSBIOS_SCRATCH_0 0x0034
2153#define mmSBIOS_SCRATCH_0_BASE_IDX 1
2154#define mmSBIOS_SCRATCH_1 0x0035
2155#define mmSBIOS_SCRATCH_1_BASE_IDX 1
2156#define mmSBIOS_SCRATCH_2 0x0036
2157#define mmSBIOS_SCRATCH_2_BASE_IDX 1
2158#define mmSBIOS_SCRATCH_3 0x0037
2159#define mmSBIOS_SCRATCH_3_BASE_IDX 1
2160#define mmBIOS_SCRATCH_0 0x0038
2161#define mmBIOS_SCRATCH_0_BASE_IDX 1
2162#define mmBIOS_SCRATCH_1 0x0039
2163#define mmBIOS_SCRATCH_1_BASE_IDX 1
2164#define mmBIOS_SCRATCH_2 0x003a
2165#define mmBIOS_SCRATCH_2_BASE_IDX 1
2166#define mmBIOS_SCRATCH_3 0x003b
2167#define mmBIOS_SCRATCH_3_BASE_IDX 1
2168#define mmBIOS_SCRATCH_4 0x003c
2169#define mmBIOS_SCRATCH_4_BASE_IDX 1
2170#define mmBIOS_SCRATCH_5 0x003d
2171#define mmBIOS_SCRATCH_5_BASE_IDX 1
2172#define mmBIOS_SCRATCH_6 0x003e
2173#define mmBIOS_SCRATCH_6_BASE_IDX 1
2174#define mmBIOS_SCRATCH_7 0x003f
2175#define mmBIOS_SCRATCH_7_BASE_IDX 1
2176#define mmBIOS_SCRATCH_8 0x0040
2177#define mmBIOS_SCRATCH_8_BASE_IDX 1
2178#define mmBIOS_SCRATCH_9 0x0041
2179#define mmBIOS_SCRATCH_9_BASE_IDX 1
2180#define mmBIOS_SCRATCH_10 0x0042
2181#define mmBIOS_SCRATCH_10_BASE_IDX 1
2182#define mmBIOS_SCRATCH_11 0x0043
2183#define mmBIOS_SCRATCH_11_BASE_IDX 1
2184#define mmBIOS_SCRATCH_12 0x0044
2185#define mmBIOS_SCRATCH_12_BASE_IDX 1
2186#define mmBIOS_SCRATCH_13 0x0045
2187#define mmBIOS_SCRATCH_13_BASE_IDX 1
2188#define mmBIOS_SCRATCH_14 0x0046
2189#define mmBIOS_SCRATCH_14_BASE_IDX 1
2190#define mmBIOS_SCRATCH_15 0x0047
2191#define mmBIOS_SCRATCH_15_BASE_IDX 1
2192#define mmBIF_RLC_INTR_CNTL 0x004c
2193#define mmBIF_RLC_INTR_CNTL_BASE_IDX 1
2194#define mmBIF_VCE_INTR_CNTL 0x004d
2195#define mmBIF_VCE_INTR_CNTL_BASE_IDX 1
2196#define mmBIF_UVD_INTR_CNTL 0x004e
2197#define mmBIF_UVD_INTR_CNTL_BASE_IDX 1
2198#define mmGFX_MMIOREG_CAM_ADDR0 0x006c
2199#define mmGFX_MMIOREG_CAM_ADDR0_BASE_IDX 1
2200#define mmGFX_MMIOREG_CAM_REMAP_ADDR0 0x006d
2201#define mmGFX_MMIOREG_CAM_REMAP_ADDR0_BASE_IDX 1
2202#define mmGFX_MMIOREG_CAM_ADDR1 0x006e
2203#define mmGFX_MMIOREG_CAM_ADDR1_BASE_IDX 1
2204#define mmGFX_MMIOREG_CAM_REMAP_ADDR1 0x006f
2205#define mmGFX_MMIOREG_CAM_REMAP_ADDR1_BASE_IDX 1
2206#define mmGFX_MMIOREG_CAM_ADDR2 0x0070
2207#define mmGFX_MMIOREG_CAM_ADDR2_BASE_IDX 1
2208#define mmGFX_MMIOREG_CAM_REMAP_ADDR2 0x0071
2209#define mmGFX_MMIOREG_CAM_REMAP_ADDR2_BASE_IDX 1
2210#define mmGFX_MMIOREG_CAM_ADDR3 0x0072
2211#define mmGFX_MMIOREG_CAM_ADDR3_BASE_IDX 1
2212#define mmGFX_MMIOREG_CAM_REMAP_ADDR3 0x0073
2213#define mmGFX_MMIOREG_CAM_REMAP_ADDR3_BASE_IDX 1
2214#define mmGFX_MMIOREG_CAM_ADDR4 0x0074
2215#define mmGFX_MMIOREG_CAM_ADDR4_BASE_IDX 1
2216#define mmGFX_MMIOREG_CAM_REMAP_ADDR4 0x0075
2217#define mmGFX_MMIOREG_CAM_REMAP_ADDR4_BASE_IDX 1
2218#define mmGFX_MMIOREG_CAM_ADDR5 0x0076
2219#define mmGFX_MMIOREG_CAM_ADDR5_BASE_IDX 1
2220#define mmGFX_MMIOREG_CAM_REMAP_ADDR5 0x0077
2221#define mmGFX_MMIOREG_CAM_REMAP_ADDR5_BASE_IDX 1
2222#define mmGFX_MMIOREG_CAM_ADDR6 0x0078
2223#define mmGFX_MMIOREG_CAM_ADDR6_BASE_IDX 1
2224#define mmGFX_MMIOREG_CAM_REMAP_ADDR6 0x0079
2225#define mmGFX_MMIOREG_CAM_REMAP_ADDR6_BASE_IDX 1
2226#define mmGFX_MMIOREG_CAM_ADDR7 0x007a
2227#define mmGFX_MMIOREG_CAM_ADDR7_BASE_IDX 1
2228#define mmGFX_MMIOREG_CAM_REMAP_ADDR7 0x007b
2229#define mmGFX_MMIOREG_CAM_REMAP_ADDR7_BASE_IDX 1
2230#define mmGFX_MMIOREG_CAM_CNTL 0x007c
2231#define mmGFX_MMIOREG_CAM_CNTL_BASE_IDX 1
2232#define mmGFX_MMIOREG_CAM_ZERO_CPL 0x007d
2233#define mmGFX_MMIOREG_CAM_ZERO_CPL_BASE_IDX 1
2234#define mmGFX_MMIOREG_CAM_ONE_CPL 0x007e
2235#define mmGFX_MMIOREG_CAM_ONE_CPL_BASE_IDX 1
2236#define mmGFX_MMIOREG_CAM_PROGRAMMABLE_CPL 0x007f
2237#define mmGFX_MMIOREG_CAM_PROGRAMMABLE_CPL_BASE_IDX 1
2238
2239
2240// addressBlock: nbio_nbif_syshub_mmreg_ind_syshubdec[32..39]
2241// base address: 0x20
2242#define mmSYSHUB_INDEX 0x0008
2243#define mmSYSHUB_INDEX_BASE_IDX 0
2244#define mmSYSHUB_DATA 0x0009
2245#define mmSYSHUB_DATA_BASE_IDX 0
2246
2247
2248// addressBlock: nbio_nbif_rcc_strap_BIFDEC1[13440..14975]
2249// base address: 0x3480
2250#define mmRCC_BIF_STRAP0 0x0000
2251#define mmRCC_BIF_STRAP0_BASE_IDX 2
2252#define mmRCC_DEV0_EPF0_STRAP0 0x000f
2253#define mmRCC_DEV0_EPF0_STRAP0_BASE_IDX 2
2254
2255
2256// addressBlock: nbio_nbif_rcc_ep_dev0_BIFDEC1[13440..14975]
2257// base address: 0x3480
2258#define mmEP_PCIE_SCRATCH 0x0023
2259#define mmEP_PCIE_SCRATCH_BASE_IDX 2
2260#define mmEP_PCIE_CNTL 0x0025
2261#define mmEP_PCIE_CNTL_BASE_IDX 2
2262#define mmEP_PCIE_INT_CNTL 0x0026
2263#define mmEP_PCIE_INT_CNTL_BASE_IDX 2
2264#define mmEP_PCIE_INT_STATUS 0x0027
2265#define mmEP_PCIE_INT_STATUS_BASE_IDX 2
2266#define mmEP_PCIE_RX_CNTL2 0x0028
2267#define mmEP_PCIE_RX_CNTL2_BASE_IDX 2
2268#define mmEP_PCIE_BUS_CNTL 0x0029
2269#define mmEP_PCIE_BUS_CNTL_BASE_IDX 2
2270#define mmEP_PCIE_CFG_CNTL 0x002a
2271#define mmEP_PCIE_CFG_CNTL_BASE_IDX 2
2272#define mmEP_PCIE_TX_LTR_CNTL 0x002c
2273#define mmEP_PCIE_TX_LTR_CNTL_BASE_IDX 2
2274#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0 0x002d
2275#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 2
2276#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1 0x002d
2277#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 2
2278#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2 0x002d
2279#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 2
2280#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3 0x002d
2281#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 2
2282#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4 0x002e
2283#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 2
2284#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5 0x002e
2285#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 2
2286#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6 0x002e
2287#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 2
2288#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7 0x002e
2289#define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 2
2290#define mmEP_PCIE_F0_DPA_CAP 0x0032
2291#define mmEP_PCIE_F0_DPA_CAP_BASE_IDX 2
2292#define mmEP_PCIE_F0_DPA_LATENCY_INDICATOR 0x0033
2293#define mmEP_PCIE_F0_DPA_LATENCY_INDICATOR_BASE_IDX 2
2294#define mmEP_PCIE_F0_DPA_CNTL 0x0033
2295#define mmEP_PCIE_F0_DPA_CNTL_BASE_IDX 2
2296#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0x0033
2297#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 2
2298#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0x0034
2299#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 2
2300#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0x0034
2301#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 2
2302#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0x0034
2303#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 2
2304#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0x0034
2305#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 2
2306#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0x0035
2307#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 2
2308#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0x0035
2309#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 2
2310#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0x0035
2311#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 2
2312#define mmEP_PCIE_PME_CONTROL 0x0035
2313#define mmEP_PCIE_PME_CONTROL_BASE_IDX 2
2314#define mmEP_PCIEP_RESERVED 0x0036
2315#define mmEP_PCIEP_RESERVED_BASE_IDX 2
2316#define mmEP_PCIE_TX_CNTL 0x0038
2317#define mmEP_PCIE_TX_CNTL_BASE_IDX 2
2318#define mmEP_PCIE_TX_REQUESTER_ID 0x0039
2319#define mmEP_PCIE_TX_REQUESTER_ID_BASE_IDX 2
2320#define mmEP_PCIE_ERR_CNTL 0x003a
2321#define mmEP_PCIE_ERR_CNTL_BASE_IDX 2
2322#define mmEP_PCIE_RX_CNTL 0x003b
2323#define mmEP_PCIE_RX_CNTL_BASE_IDX 2
2324#define mmEP_PCIE_LC_SPEED_CNTL 0x003c
2325#define mmEP_PCIE_LC_SPEED_CNTL_BASE_IDX 2
2326
2327
2328// addressBlock: nbio_nbif_rcc_dwn_dev0_BIFDEC1[13440..14975]
2329// base address: 0x3480
2330#define mmDN_PCIE_RESERVED 0x0040
2331#define mmDN_PCIE_RESERVED_BASE_IDX 2
2332#define mmDN_PCIE_SCRATCH 0x0041
2333#define mmDN_PCIE_SCRATCH_BASE_IDX 2
2334#define mmDN_PCIE_CNTL 0x0043
2335#define mmDN_PCIE_CNTL_BASE_IDX 2
2336#define mmDN_PCIE_CONFIG_CNTL 0x0044
2337#define mmDN_PCIE_CONFIG_CNTL_BASE_IDX 2
2338#define mmDN_PCIE_RX_CNTL2 0x0045
2339#define mmDN_PCIE_RX_CNTL2_BASE_IDX 2
2340#define mmDN_PCIE_BUS_CNTL 0x0046
2341#define mmDN_PCIE_BUS_CNTL_BASE_IDX 2
2342#define mmDN_PCIE_CFG_CNTL 0x0047
2343#define mmDN_PCIE_CFG_CNTL_BASE_IDX 2
2344
2345
2346// addressBlock: nbio_nbif_rcc_dwnp_dev0_BIFDEC1[13440..14975]
2347// base address: 0x3480
2348#define mmPCIE_ERR_CNTL 0x004f
2349#define mmPCIE_ERR_CNTL_BASE_IDX 2
2350#define mmPCIE_RX_CNTL 0x0050
2351#define mmPCIE_RX_CNTL_BASE_IDX 2
2352#define mmPCIE_LC_SPEED_CNTL 0x0051
2353#define mmPCIE_LC_SPEED_CNTL_BASE_IDX 2
2354#define mmPCIE_LC_CNTL2 0x0052
2355#define mmPCIE_LC_CNTL2_BASE_IDX 2
2356#define mmPCIEP_STRAP_MISC 0x0053
2357#define mmPCIEP_STRAP_MISC_BASE_IDX 2
2358#define mmLTR_MSG_INFO_FROM_EP 0x0054
2359#define mmLTR_MSG_INFO_FROM_EP_BASE_IDX 2
2360
2361
2362// addressBlock: nbio_nbif_rcc_pf_0_BIFPFVFDEC1[13440..14975]
2363// base address: 0x3480
2364#define mmRCC_PF_0_0_RCC_ERR_LOG 0x0085
2365#define mmRCC_PF_0_0_RCC_ERR_LOG_BASE_IDX 2
2366#define mmRCC_PF_0_0_RCC_DOORBELL_APER_EN 0x00c0
2367#define mmRCC_PF_0_0_RCC_DOORBELL_APER_EN_BASE_IDX 2
2368#define mmRCC_PF_0_0_RCC_CONFIG_MEMSIZE 0x00c3
2369#define mmRCC_PF_0_0_RCC_CONFIG_MEMSIZE_BASE_IDX 2
2370#define mmRCC_PF_0_0_RCC_CONFIG_RESERVED 0x00c4
2371#define mmRCC_PF_0_0_RCC_CONFIG_RESERVED_BASE_IDX 2
2372#define mmRCC_PF_0_0_RCC_IOV_FUNC_IDENTIFIER 0x00c5
2373#define mmRCC_PF_0_0_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2
2374
2375
2376// addressBlock: nbio_nbif_rcc_pf_0_BIFDEC1[13440..14975]
2377// base address: 0x3480
2378#define mmRCC_ERR_INT_CNTL 0x0086
2379#define mmRCC_ERR_INT_CNTL_BASE_IDX 2
2380#define mmRCC_BACO_CNTL_MISC 0x0087
2381#define mmRCC_BACO_CNTL_MISC_BASE_IDX 2
2382#define mmRCC_RESET_EN 0x0088
2383#define mmRCC_RESET_EN_BASE_IDX 2
2384#define mmRCC_VDM_SUPPORT 0x0089
2385#define mmRCC_VDM_SUPPORT_BASE_IDX 2
2386#define mmRCC_PEER_REG_RANGE0 0x00be
2387#define mmRCC_PEER_REG_RANGE0_BASE_IDX 2
2388#define mmRCC_PEER_REG_RANGE1 0x00bf
2389#define mmRCC_PEER_REG_RANGE1_BASE_IDX 2
2390#define mmRCC_BUS_CNTL 0x00c1
2391#define mmRCC_BUS_CNTL_BASE_IDX 2
2392#define mmRCC_CONFIG_CNTL 0x00c2
2393#define mmRCC_CONFIG_CNTL_BASE_IDX 2
2394#define mmRCC_CONFIG_F0_BASE 0x00c6
2395#define mmRCC_CONFIG_F0_BASE_BASE_IDX 2
2396#define mmRCC_CONFIG_APER_SIZE 0x00c7
2397#define mmRCC_CONFIG_APER_SIZE_BASE_IDX 2
2398#define mmRCC_CONFIG_REG_APER_SIZE 0x00c8
2399#define mmRCC_CONFIG_REG_APER_SIZE_BASE_IDX 2
2400#define mmRCC_XDMA_LO 0x00c9
2401#define mmRCC_XDMA_LO_BASE_IDX 2
2402#define mmRCC_XDMA_HI 0x00ca
2403#define mmRCC_XDMA_HI_BASE_IDX 2
2404#define mmRCC_FEATURES_CONTROL_MISC 0x00cb
2405#define mmRCC_FEATURES_CONTROL_MISC_BASE_IDX 2
2406#define mmRCC_BUSNUM_CNTL1 0x00cc
2407#define mmRCC_BUSNUM_CNTL1_BASE_IDX 2
2408#define mmRCC_BUSNUM_LIST0 0x00cd
2409#define mmRCC_BUSNUM_LIST0_BASE_IDX 2
2410#define mmRCC_BUSNUM_LIST1 0x00ce
2411#define mmRCC_BUSNUM_LIST1_BASE_IDX 2
2412#define mmRCC_BUSNUM_CNTL2 0x00cf
2413#define mmRCC_BUSNUM_CNTL2_BASE_IDX 2
2414#define mmRCC_CAPTURE_HOST_BUSNUM 0x00d0
2415#define mmRCC_CAPTURE_HOST_BUSNUM_BASE_IDX 2
2416#define mmRCC_HOST_BUSNUM 0x00d1
2417#define mmRCC_HOST_BUSNUM_BASE_IDX 2
2418#define mmRCC_PEER0_FB_OFFSET_HI 0x00d2
2419#define mmRCC_PEER0_FB_OFFSET_HI_BASE_IDX 2
2420#define mmRCC_PEER0_FB_OFFSET_LO 0x00d3
2421#define mmRCC_PEER0_FB_OFFSET_LO_BASE_IDX 2
2422#define mmRCC_PEER1_FB_OFFSET_HI 0x00d4
2423#define mmRCC_PEER1_FB_OFFSET_HI_BASE_IDX 2
2424#define mmRCC_PEER1_FB_OFFSET_LO 0x00d5
2425#define mmRCC_PEER1_FB_OFFSET_LO_BASE_IDX 2
2426#define mmRCC_PEER2_FB_OFFSET_HI 0x00d6
2427#define mmRCC_PEER2_FB_OFFSET_HI_BASE_IDX 2
2428#define mmRCC_PEER2_FB_OFFSET_LO 0x00d7
2429#define mmRCC_PEER2_FB_OFFSET_LO_BASE_IDX 2
2430#define mmRCC_PEER3_FB_OFFSET_HI 0x00d8
2431#define mmRCC_PEER3_FB_OFFSET_HI_BASE_IDX 2
2432#define mmRCC_PEER3_FB_OFFSET_LO 0x00d9
2433#define mmRCC_PEER3_FB_OFFSET_LO_BASE_IDX 2
2434#define mmRCC_CMN_LINK_CNTL 0x00de
2435#define mmRCC_CMN_LINK_CNTL_BASE_IDX 2
2436#define mmRCC_EP_REQUESTERID_RESTORE 0x00df
2437#define mmRCC_EP_REQUESTERID_RESTORE_BASE_IDX 2
2438#define mmRCC_LTR_LSWITCH_CNTL 0x00e0
2439#define mmRCC_LTR_LSWITCH_CNTL_BASE_IDX 2
2440#define mmRCC_MH_ARB_CNTL 0x00e1
2441#define mmRCC_MH_ARB_CNTL_BASE_IDX 2
2442
2443
2444// addressBlock: nbio_nbif_bif_bx_pf_BIFDEC1[13440..14975]
2445// base address: 0x3480
2446#define mmBIF_MM_INDACCESS_CNTL 0x00e6
2447#define mmBIF_MM_INDACCESS_CNTL_BASE_IDX 2
2448#define mmBUS_CNTL 0x00e7
2449#define mmBUS_CNTL_BASE_IDX 2
2450#define mmBIF_SCRATCH0 0x00e8
2451#define mmBIF_SCRATCH0_BASE_IDX 2
2452#define mmBIF_SCRATCH1 0x00e9
2453#define mmBIF_SCRATCH1_BASE_IDX 2
2454#define mmBX_RESET_EN 0x00ed
2455#define mmBX_RESET_EN_BASE_IDX 2
2456#define mmMM_CFGREGS_CNTL 0x00ee
2457#define mmMM_CFGREGS_CNTL_BASE_IDX 2
2458#define mmBX_RESET_CNTL 0x00f0
2459#define mmBX_RESET_CNTL_BASE_IDX 2
2460#define mmINTERRUPT_CNTL 0x00f1
2461#define mmINTERRUPT_CNTL_BASE_IDX 2
2462#define mmINTERRUPT_CNTL2 0x00f2
2463#define mmINTERRUPT_CNTL2_BASE_IDX 2
2464#define mmCLKREQB_PAD_CNTL 0x00f8
2465#define mmCLKREQB_PAD_CNTL_BASE_IDX 2
2466#define mmBIF_FEATURES_CONTROL_MISC 0x00fb
2467#define mmBIF_FEATURES_CONTROL_MISC_BASE_IDX 2
2468#define mmBIF_DOORBELL_CNTL 0x00fc
2469#define mmBIF_DOORBELL_CNTL_BASE_IDX 2
2470#define mmBIF_DOORBELL_INT_CNTL 0x00fd
2471#define mmBIF_DOORBELL_INT_CNTL_BASE_IDX 2
2472#define mmBIF_FB_EN 0x00ff
2473#define mmBIF_FB_EN_BASE_IDX 2
2474#define mmBIF_BUSY_DELAY_CNTR 0x0100
2475#define mmBIF_BUSY_DELAY_CNTR_BASE_IDX 2
2476#define mmBIF_MST_TRANS_PENDING_VF 0x0109
2477#define mmBIF_MST_TRANS_PENDING_VF_BASE_IDX 2
2478#define mmBIF_SLV_TRANS_PENDING_VF 0x010a
2479#define mmBIF_SLV_TRANS_PENDING_VF_BASE_IDX 2
2480#define mmBACO_CNTL 0x010b
2481#define mmBACO_CNTL_BASE_IDX 2
2482#define mmBIF_BACO_EXIT_TIME0 0x010c
2483#define mmBIF_BACO_EXIT_TIME0_BASE_IDX 2
2484#define mmBIF_BACO_EXIT_TIMER1 0x010d
2485#define mmBIF_BACO_EXIT_TIMER1_BASE_IDX 2
2486#define mmBIF_BACO_EXIT_TIMER2 0x010e
2487#define mmBIF_BACO_EXIT_TIMER2_BASE_IDX 2
2488#define mmBIF_BACO_EXIT_TIMER3 0x010f
2489#define mmBIF_BACO_EXIT_TIMER3_BASE_IDX 2
2490#define mmBIF_BACO_EXIT_TIMER4 0x0110
2491#define mmBIF_BACO_EXIT_TIMER4_BASE_IDX 2
2492#define mmMEM_TYPE_CNTL 0x0111
2493#define mmMEM_TYPE_CNTL_BASE_IDX 2
2494#define mmSMU_BIF_VDDGFX_PWR_STATUS 0x0113
2495#define mmSMU_BIF_VDDGFX_PWR_STATUS_BASE_IDX 2
2496#define mmBIF_VDDGFX_GFX0_LOWER 0x0114
2497#define mmBIF_VDDGFX_GFX0_LOWER_BASE_IDX 2
2498#define mmBIF_VDDGFX_GFX0_UPPER 0x0115
2499#define mmBIF_VDDGFX_GFX0_UPPER_BASE_IDX 2
2500#define mmBIF_VDDGFX_GFX1_LOWER 0x0116
2501#define mmBIF_VDDGFX_GFX1_LOWER_BASE_IDX 2
2502#define mmBIF_VDDGFX_GFX1_UPPER 0x0117
2503#define mmBIF_VDDGFX_GFX1_UPPER_BASE_IDX 2
2504#define mmBIF_VDDGFX_GFX2_LOWER 0x0118
2505#define mmBIF_VDDGFX_GFX2_LOWER_BASE_IDX 2
2506#define mmBIF_VDDGFX_GFX2_UPPER 0x0119
2507#define mmBIF_VDDGFX_GFX2_UPPER_BASE_IDX 2
2508#define mmBIF_VDDGFX_GFX3_LOWER 0x011a
2509#define mmBIF_VDDGFX_GFX3_LOWER_BASE_IDX 2
2510#define mmBIF_VDDGFX_GFX3_UPPER 0x011b
2511#define mmBIF_VDDGFX_GFX3_UPPER_BASE_IDX 2
2512#define mmBIF_VDDGFX_GFX4_LOWER 0x011c
2513#define mmBIF_VDDGFX_GFX4_LOWER_BASE_IDX 2
2514#define mmBIF_VDDGFX_GFX4_UPPER 0x011d
2515#define mmBIF_VDDGFX_GFX4_UPPER_BASE_IDX 2
2516#define mmBIF_VDDGFX_GFX5_LOWER 0x011e
2517#define mmBIF_VDDGFX_GFX5_LOWER_BASE_IDX 2
2518#define mmBIF_VDDGFX_GFX5_UPPER 0x011f
2519#define mmBIF_VDDGFX_GFX5_UPPER_BASE_IDX 2
2520#define mmBIF_VDDGFX_RSV1_LOWER 0x0120
2521#define mmBIF_VDDGFX_RSV1_LOWER_BASE_IDX 2
2522#define mmBIF_VDDGFX_RSV1_UPPER 0x0121
2523#define mmBIF_VDDGFX_RSV1_UPPER_BASE_IDX 2
2524#define mmBIF_VDDGFX_RSV2_LOWER 0x0122
2525#define mmBIF_VDDGFX_RSV2_LOWER_BASE_IDX 2
2526#define mmBIF_VDDGFX_RSV2_UPPER 0x0123
2527#define mmBIF_VDDGFX_RSV2_UPPER_BASE_IDX 2
2528#define mmBIF_VDDGFX_RSV3_LOWER 0x0124
2529#define mmBIF_VDDGFX_RSV3_LOWER_BASE_IDX 2
2530#define mmBIF_VDDGFX_RSV3_UPPER 0x0125
2531#define mmBIF_VDDGFX_RSV3_UPPER_BASE_IDX 2
2532#define mmBIF_VDDGFX_RSV4_LOWER 0x0126
2533#define mmBIF_VDDGFX_RSV4_LOWER_BASE_IDX 2
2534#define mmBIF_VDDGFX_RSV4_UPPER 0x0127
2535#define mmBIF_VDDGFX_RSV4_UPPER_BASE_IDX 2
2536#define mmBIF_VDDGFX_FB_CMP 0x0128
2537#define mmBIF_VDDGFX_FB_CMP_BASE_IDX 2
2538#define mmBIF_DOORBELL_GBLAPER1_LOWER 0x0129
2539#define mmBIF_DOORBELL_GBLAPER1_LOWER_BASE_IDX 2
2540#define mmBIF_DOORBELL_GBLAPER1_UPPER 0x012a
2541#define mmBIF_DOORBELL_GBLAPER1_UPPER_BASE_IDX 2
2542#define mmBIF_DOORBELL_GBLAPER2_LOWER 0x012b
2543#define mmBIF_DOORBELL_GBLAPER2_LOWER_BASE_IDX 2
2544#define mmBIF_DOORBELL_GBLAPER2_UPPER 0x012c
2545#define mmBIF_DOORBELL_GBLAPER2_UPPER_BASE_IDX 2
2546#define mmREMAP_HDP_MEM_FLUSH_CNTL 0x012d
2547#define mmREMAP_HDP_MEM_FLUSH_CNTL_BASE_IDX 2
2548#define mmREMAP_HDP_REG_FLUSH_CNTL 0x012e
2549#define mmREMAP_HDP_REG_FLUSH_CNTL_BASE_IDX 2
2550#define mmBIF_RB_CNTL 0x012f
2551#define mmBIF_RB_CNTL_BASE_IDX 2
2552#define mmBIF_RB_BASE 0x0130
2553#define mmBIF_RB_BASE_BASE_IDX 2
2554#define mmBIF_RB_RPTR 0x0131
2555#define mmBIF_RB_RPTR_BASE_IDX 2
2556#define mmBIF_RB_WPTR 0x0132
2557#define mmBIF_RB_WPTR_BASE_IDX 2
2558#define mmBIF_RB_WPTR_ADDR_HI 0x0133
2559#define mmBIF_RB_WPTR_ADDR_HI_BASE_IDX 2
2560#define mmBIF_RB_WPTR_ADDR_LO 0x0134
2561#define mmBIF_RB_WPTR_ADDR_LO_BASE_IDX 2
2562#define mmMAILBOX_INDEX 0x0135
2563#define mmMAILBOX_INDEX_BASE_IDX 2
2564#define mmBIF_UVD_GPUIOV_CFG_SIZE 0x0143
2565#define mmBIF_UVD_GPUIOV_CFG_SIZE_BASE_IDX 2
2566#define mmBIF_VCE_GPUIOV_CFG_SIZE 0x0144
2567#define mmBIF_VCE_GPUIOV_CFG_SIZE_BASE_IDX 2
2568#define mmBIF_GFX_SDMA_GPUIOV_CFG_SIZE 0x0145
2569#define mmBIF_GFX_SDMA_GPUIOV_CFG_SIZE_BASE_IDX 2
2570#define mmBIF_PERSTB_PAD_CNTL 0x0148
2571#define mmBIF_PERSTB_PAD_CNTL_BASE_IDX 2
2572#define mmBIF_PX_EN_PAD_CNTL 0x0149
2573#define mmBIF_PX_EN_PAD_CNTL_BASE_IDX 2
2574#define mmBIF_REFPADKIN_PAD_CNTL 0x014a
2575#define mmBIF_REFPADKIN_PAD_CNTL_BASE_IDX 2
2576#define mmBIF_CLKREQB_PAD_CNTL 0x014b
2577#define mmBIF_CLKREQB_PAD_CNTL_BASE_IDX 2
2578
2579
2580// addressBlock: nbio_nbif_bif_bx_pf_BIFPFVFDEC1
2581// base address: 0x0
2582#define mmBIF_BX_PF0_BIF_BME_STATUS 0x00eb
2583#define mmBIF_BX_PF0_BIF_BME_STATUS_BASE_IDX 2
2584#define mmBIF_BX_PF0_BIF_ATOMIC_ERR_LOG 0x00ec
2585#define mmBIF_BX_PF0_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
2586#define mmBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
2587#define mmBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
2588#define mmBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
2589#define mmBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
2590#define mmBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
2591#define mmBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
2592#define mmBIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
2593#define mmBIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
2594#define mmBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
2595#define mmBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
2596#define mmBIF_BX_PF0_GPU_HDP_FLUSH_REQ 0x0106
2597#define mmBIF_BX_PF0_GPU_HDP_FLUSH_REQ_BASE_IDX 2
2598#define mmBIF_BX_PF0_GPU_HDP_FLUSH_DONE 0x0107
2599#define mmBIF_BX_PF0_GPU_HDP_FLUSH_DONE_BASE_IDX 2
2600#define mmBIF_BX_PF0_BIF_TRANS_PENDING 0x0108
2601#define mmBIF_BX_PF0_BIF_TRANS_PENDING_BASE_IDX 2
2602#define mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0 0x0136
2603#define mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
2604#define mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1 0x0137
2605#define mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
2606#define mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2 0x0138
2607#define mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
2608#define mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3 0x0139
2609#define mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
2610#define mmBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW0 0x013a
2611#define mmBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
2612#define mmBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW1 0x013b
2613#define mmBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
2614#define mmBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2 0x013c
2615#define mmBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
2616#define mmBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW3 0x013d
2617#define mmBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
2618#define mmBIF_BX_PF0_MAILBOX_CONTROL 0x013e
2619#define mmBIF_BX_PF0_MAILBOX_CONTROL_BASE_IDX 2
2620#define mmBIF_BX_PF0_MAILBOX_INT_CNTL 0x013f
2621#define mmBIF_BX_PF0_MAILBOX_INT_CNTL_BASE_IDX 2
2622#define mmBIF_BX_PF0_BIF_VMHV_MAILBOX 0x0140
2623#define mmBIF_BX_PF0_BIF_VMHV_MAILBOX_BASE_IDX 2
2624
2625
2626// addressBlock: nbio_nbif_gdc_GDCDEC[14976..15487]
2627// base address: 0x3a80
2628#define mmNGDC_SDP_PORT_CTRL 0x01c2
2629#define mmNGDC_SDP_PORT_CTRL_BASE_IDX 2
2630#define mmSHUB_REGS_IF_CTL 0x01c3
2631#define mmSHUB_REGS_IF_CTL_BASE_IDX 2
2632#define mmNGDC_RESERVED_0 0x01cb
2633#define mmNGDC_RESERVED_0_BASE_IDX 2
2634#define mmNGDC_RESERVED_1 0x01cc
2635#define mmNGDC_RESERVED_1_BASE_IDX 2
2636#define mmNGDC_SDP_PORT_CTRL_SOCCLK 0x01cd
2637#define mmNGDC_SDP_PORT_CTRL_SOCCLK_BASE_IDX 2
2638#define mmBIF_SDMA0_DOORBELL_RANGE 0x01d0
2639#define mmBIF_SDMA0_DOORBELL_RANGE_BASE_IDX 2
2640#define mmBIF_SDMA1_DOORBELL_RANGE 0x01d1
2641#define mmBIF_SDMA1_DOORBELL_RANGE_BASE_IDX 2
2642#define mmBIF_IH_DOORBELL_RANGE 0x01d2
2643#define mmBIF_IH_DOORBELL_RANGE_BASE_IDX 2
2644#define mmBIF_MMSCH0_DOORBELL_RANGE 0x01d3
2645#define mmBIF_MMSCH0_DOORBELL_RANGE_BASE_IDX 2
2646#define mmBIF_DOORBELL_FENCE_CNTL 0x01de
2647#define mmBIF_DOORBELL_FENCE_CNTL_BASE_IDX 2
2648#define mmS2A_MISC_CNTL 0x01df
2649#define mmS2A_MISC_CNTL_BASE_IDX 2
2650
2651
2652// addressBlock: nbio_nbif_rcc_pf_0_BIFDEC2
2653// base address: 0x0
2654#define mmRCC_PF_0_GFXMSIX_VECT0_ADDR_LO 0x0400
2655#define mmRCC_PF_0_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3
2656#define mmRCC_PF_0_GFXMSIX_VECT0_ADDR_HI 0x0401
2657#define mmRCC_PF_0_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3
2658#define mmRCC_PF_0_GFXMSIX_VECT0_MSG_DATA 0x0402
2659#define mmRCC_PF_0_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3
2660#define mmRCC_PF_0_GFXMSIX_VECT0_CONTROL 0x0403
2661#define mmRCC_PF_0_GFXMSIX_VECT0_CONTROL_BASE_IDX 3
2662#define mmRCC_PF_0_GFXMSIX_VECT1_ADDR_LO 0x0404
2663#define mmRCC_PF_0_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3
2664#define mmRCC_PF_0_GFXMSIX_VECT1_ADDR_HI 0x0405
2665#define mmRCC_PF_0_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3
2666#define mmRCC_PF_0_GFXMSIX_VECT1_MSG_DATA 0x0406
2667#define mmRCC_PF_0_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3
2668#define mmRCC_PF_0_GFXMSIX_VECT1_CONTROL 0x0407
2669#define mmRCC_PF_0_GFXMSIX_VECT1_CONTROL_BASE_IDX 3
2670#define mmRCC_PF_0_GFXMSIX_VECT2_ADDR_LO 0x0408
2671#define mmRCC_PF_0_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3
2672#define mmRCC_PF_0_GFXMSIX_VECT2_ADDR_HI 0x0409
2673#define mmRCC_PF_0_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3
2674#define mmRCC_PF_0_GFXMSIX_VECT2_MSG_DATA 0x040a
2675#define mmRCC_PF_0_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3
2676#define mmRCC_PF_0_GFXMSIX_VECT2_CONTROL 0x040b
2677#define mmRCC_PF_0_GFXMSIX_VECT2_CONTROL_BASE_IDX 3
2678#define mmRCC_PF_0_GFXMSIX_PBA 0x0800
2679#define mmRCC_PF_0_GFXMSIX_PBA_BASE_IDX 3
2680
2681
2682// addressBlock: nbio_nbif_bif_bx_pf_SYSPFVFDEC[0..255]
2683// base address: 0x0
2684//#define mmBIF_BX_PF_MM_INDEX 0x0000
2685//#define mmBIF_BX_PF_MM_DATA 0x0001
2686//#define mmBIF_BX_PF_MM_INDEX_HI 0x0006
2687
2688
2689// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf0_SYSPFVFDEC
2690// base address: 0x0
2691#define mmBIF_BX_DEV0_EPF0_VF0_MM_INDEX 0x0000
2692#define mmBIF_BX_DEV0_EPF0_VF0_MM_INDEX_BASE_IDX 0
2693#define mmBIF_BX_DEV0_EPF0_VF0_MM_DATA 0x0001
2694#define mmBIF_BX_DEV0_EPF0_VF0_MM_DATA_BASE_IDX 0
2695#define mmBIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI 0x0006
2696#define mmBIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI_BASE_IDX 0
2697
2698
2699// addressBlock: nbio_nbif_rcc_dev0_epf0_vf0_BIFPFVFDEC1
2700// base address: 0x0
2701
2702
2703// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf0_BIFPFVFDEC1
2704// base address: 0x0
2705#define mmBIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS 0x00eb
2706#define mmBIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS_BASE_IDX 2
2707#define mmBIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG 0x00ec
2708#define mmBIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
2709#define mmBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
2710#define mmBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
2711#define mmBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
2712#define mmBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
2713#define mmBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
2714#define mmBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
2715#define mmBIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
2716#define mmBIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
2717#define mmBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
2718#define mmBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
2719#define mmBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ 0x0106
2720#define mmBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ_BASE_IDX 2
2721#define mmBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE 0x0107
2722#define mmBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE_BASE_IDX 2
2723#define mmBIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING 0x0108
2724#define mmBIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING_BASE_IDX 2
2725#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0 0x0136
2726#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
2727#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1 0x0137
2728#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
2729#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2 0x0138
2730#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
2731#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3 0x0139
2732#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
2733#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0 0x013a
2734#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
2735#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1 0x013b
2736#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
2737#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2 0x013c
2738#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
2739#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3 0x013d
2740#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
2741#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL 0x013e
2742#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL_BASE_IDX 2
2743#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL 0x013f
2744#define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL_BASE_IDX 2
2745#define mmBIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX 0x0140
2746#define mmBIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX_BASE_IDX 2
2747
2748
2749// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf1_SYSPFVFDEC
2750// base address: 0x0
2751#define mmBIF_BX_DEV0_EPF0_VF1_MM_INDEX 0x0000
2752#define mmBIF_BX_DEV0_EPF0_VF1_MM_INDEX_BASE_IDX 0
2753#define mmBIF_BX_DEV0_EPF0_VF1_MM_DATA 0x0001
2754#define mmBIF_BX_DEV0_EPF0_VF1_MM_DATA_BASE_IDX 0
2755#define mmBIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI 0x0006
2756#define mmBIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI_BASE_IDX 0
2757
2758
2759// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf1_BIFPFVFDEC1
2760// base address: 0x0
2761#define mmBIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS 0x00eb
2762#define mmBIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS_BASE_IDX 2
2763#define mmBIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG 0x00ec
2764#define mmBIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
2765#define mmBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
2766#define mmBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
2767#define mmBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
2768#define mmBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
2769#define mmBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
2770#define mmBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
2771#define mmBIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
2772#define mmBIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
2773#define mmBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
2774#define mmBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
2775#define mmBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ 0x0106
2776#define mmBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ_BASE_IDX 2
2777#define mmBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE 0x0107
2778#define mmBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE_BASE_IDX 2
2779#define mmBIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING 0x0108
2780#define mmBIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING_BASE_IDX 2
2781#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0 0x0136
2782#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
2783#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1 0x0137
2784#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
2785#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2 0x0138
2786#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
2787#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3 0x0139
2788#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
2789#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0 0x013a
2790#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
2791#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1 0x013b
2792#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
2793#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2 0x013c
2794#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
2795#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3 0x013d
2796#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
2797#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL 0x013e
2798#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL_BASE_IDX 2
2799#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL 0x013f
2800#define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL_BASE_IDX 2
2801#define mmBIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX 0x0140
2802#define mmBIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX_BASE_IDX 2
2803
2804
2805// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf2_SYSPFVFDEC
2806// base address: 0x0
2807#define mmBIF_BX_DEV0_EPF0_VF2_MM_INDEX 0x0000
2808#define mmBIF_BX_DEV0_EPF0_VF2_MM_INDEX_BASE_IDX 0
2809#define mmBIF_BX_DEV0_EPF0_VF2_MM_DATA 0x0001
2810#define mmBIF_BX_DEV0_EPF0_VF2_MM_DATA_BASE_IDX 0
2811#define mmBIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI 0x0006
2812#define mmBIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI_BASE_IDX 0
2813
2814
2815// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf2_BIFPFVFDEC1
2816// base address: 0x0
2817#define mmBIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS 0x00eb
2818#define mmBIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS_BASE_IDX 2
2819#define mmBIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG 0x00ec
2820#define mmBIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
2821#define mmBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
2822#define mmBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
2823#define mmBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
2824#define mmBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
2825#define mmBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
2826#define mmBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
2827#define mmBIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
2828#define mmBIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
2829#define mmBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
2830#define mmBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
2831#define mmBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ 0x0106
2832#define mmBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ_BASE_IDX 2
2833#define mmBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE 0x0107
2834#define mmBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE_BASE_IDX 2
2835#define mmBIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING 0x0108
2836#define mmBIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING_BASE_IDX 2
2837#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0 0x0136
2838#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
2839#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1 0x0137
2840#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
2841#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2 0x0138
2842#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
2843#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3 0x0139
2844#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
2845#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0 0x013a
2846#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
2847#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1 0x013b
2848#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
2849#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2 0x013c
2850#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
2851#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3 0x013d
2852#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
2853#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL 0x013e
2854#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL_BASE_IDX 2
2855#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL 0x013f
2856#define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL_BASE_IDX 2
2857#define mmBIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX 0x0140
2858#define mmBIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX_BASE_IDX 2
2859
2860
2861// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf3_SYSPFVFDEC
2862// base address: 0x0
2863#define mmBIF_BX_DEV0_EPF0_VF3_MM_INDEX 0x0000
2864#define mmBIF_BX_DEV0_EPF0_VF3_MM_INDEX_BASE_IDX 0
2865#define mmBIF_BX_DEV0_EPF0_VF3_MM_DATA 0x0001
2866#define mmBIF_BX_DEV0_EPF0_VF3_MM_DATA_BASE_IDX 0
2867#define mmBIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI 0x0006
2868#define mmBIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI_BASE_IDX 0
2869
2870
2871// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf3_BIFPFVFDEC1
2872// base address: 0x0
2873#define mmBIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS 0x00eb
2874#define mmBIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS_BASE_IDX 2
2875#define mmBIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG 0x00ec
2876#define mmBIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
2877#define mmBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
2878#define mmBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
2879#define mmBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
2880#define mmBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
2881#define mmBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
2882#define mmBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
2883#define mmBIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
2884#define mmBIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
2885#define mmBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
2886#define mmBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
2887#define mmBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ 0x0106
2888#define mmBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ_BASE_IDX 2
2889#define mmBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE 0x0107
2890#define mmBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE_BASE_IDX 2
2891#define mmBIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING 0x0108
2892#define mmBIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING_BASE_IDX 2
2893#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0 0x0136
2894#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
2895#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1 0x0137
2896#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
2897#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2 0x0138
2898#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
2899#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3 0x0139
2900#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
2901#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0 0x013a
2902#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
2903#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1 0x013b
2904#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
2905#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2 0x013c
2906#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
2907#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3 0x013d
2908#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
2909#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL 0x013e
2910#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL_BASE_IDX 2
2911#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL 0x013f
2912#define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL_BASE_IDX 2
2913#define mmBIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX 0x0140
2914#define mmBIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX_BASE_IDX 2
2915
2916
2917// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf4_SYSPFVFDEC
2918// base address: 0x0
2919#define mmBIF_BX_DEV0_EPF0_VF4_MM_INDEX 0x0000
2920#define mmBIF_BX_DEV0_EPF0_VF4_MM_INDEX_BASE_IDX 0
2921#define mmBIF_BX_DEV0_EPF0_VF4_MM_DATA 0x0001
2922#define mmBIF_BX_DEV0_EPF0_VF4_MM_DATA_BASE_IDX 0
2923#define mmBIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI 0x0006
2924#define mmBIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI_BASE_IDX 0
2925
2926
2927// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf4_BIFPFVFDEC1
2928// base address: 0x0
2929#define mmBIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS 0x00eb
2930#define mmBIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS_BASE_IDX 2
2931#define mmBIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG 0x00ec
2932#define mmBIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
2933#define mmBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
2934#define mmBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
2935#define mmBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
2936#define mmBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
2937#define mmBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
2938#define mmBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
2939#define mmBIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
2940#define mmBIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
2941#define mmBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
2942#define mmBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
2943#define mmBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ 0x0106
2944#define mmBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ_BASE_IDX 2
2945#define mmBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE 0x0107
2946#define mmBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE_BASE_IDX 2
2947#define mmBIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING 0x0108
2948#define mmBIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING_BASE_IDX 2
2949#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0 0x0136
2950#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
2951#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1 0x0137
2952#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
2953#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2 0x0138
2954#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
2955#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3 0x0139
2956#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
2957#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0 0x013a
2958#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
2959#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1 0x013b
2960#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
2961#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2 0x013c
2962#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
2963#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3 0x013d
2964#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
2965#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL 0x013e
2966#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL_BASE_IDX 2
2967#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL 0x013f
2968#define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL_BASE_IDX 2
2969#define mmBIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX 0x0140
2970#define mmBIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX_BASE_IDX 2
2971
2972
2973// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf5_SYSPFVFDEC
2974// base address: 0x0
2975#define mmBIF_BX_DEV0_EPF0_VF5_MM_INDEX 0x0000
2976#define mmBIF_BX_DEV0_EPF0_VF5_MM_INDEX_BASE_IDX 0
2977#define mmBIF_BX_DEV0_EPF0_VF5_MM_DATA 0x0001
2978#define mmBIF_BX_DEV0_EPF0_VF5_MM_DATA_BASE_IDX 0
2979#define mmBIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI 0x0006
2980#define mmBIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI_BASE_IDX 0
2981
2982
2983// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf5_BIFPFVFDEC1
2984// base address: 0x0
2985#define mmBIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS 0x00eb
2986#define mmBIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS_BASE_IDX 2
2987#define mmBIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG 0x00ec
2988#define mmBIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
2989#define mmBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
2990#define mmBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
2991#define mmBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
2992#define mmBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
2993#define mmBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
2994#define mmBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
2995#define mmBIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
2996#define mmBIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
2997#define mmBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
2998#define mmBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
2999#define mmBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ 0x0106
3000#define mmBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ_BASE_IDX 2
3001#define mmBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE 0x0107
3002#define mmBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE_BASE_IDX 2
3003#define mmBIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING 0x0108
3004#define mmBIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING_BASE_IDX 2
3005#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0 0x0136
3006#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
3007#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1 0x0137
3008#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
3009#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2 0x0138
3010#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
3011#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3 0x0139
3012#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
3013#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0 0x013a
3014#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
3015#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1 0x013b
3016#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
3017#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2 0x013c
3018#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
3019#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3 0x013d
3020#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
3021#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL 0x013e
3022#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL_BASE_IDX 2
3023#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL 0x013f
3024#define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL_BASE_IDX 2
3025#define mmBIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX 0x0140
3026#define mmBIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX_BASE_IDX 2
3027
3028
3029// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf6_SYSPFVFDEC
3030// base address: 0x0
3031#define mmBIF_BX_DEV0_EPF0_VF6_MM_INDEX 0x0000
3032#define mmBIF_BX_DEV0_EPF0_VF6_MM_INDEX_BASE_IDX 0
3033#define mmBIF_BX_DEV0_EPF0_VF6_MM_DATA 0x0001
3034#define mmBIF_BX_DEV0_EPF0_VF6_MM_DATA_BASE_IDX 0
3035#define mmBIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI 0x0006
3036#define mmBIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI_BASE_IDX 0
3037
3038
3039// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf6_BIFPFVFDEC1
3040// base address: 0x0
3041#define mmBIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS 0x00eb
3042#define mmBIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS_BASE_IDX 2
3043#define mmBIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG 0x00ec
3044#define mmBIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
3045#define mmBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
3046#define mmBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
3047#define mmBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
3048#define mmBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
3049#define mmBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
3050#define mmBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
3051#define mmBIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
3052#define mmBIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
3053#define mmBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
3054#define mmBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
3055#define mmBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ 0x0106
3056#define mmBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ_BASE_IDX 2
3057#define mmBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE 0x0107
3058#define mmBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE_BASE_IDX 2
3059#define mmBIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING 0x0108
3060#define mmBIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING_BASE_IDX 2
3061#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0 0x0136
3062#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
3063#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1 0x0137
3064#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
3065#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2 0x0138
3066#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
3067#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3 0x0139
3068#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
3069#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0 0x013a
3070#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
3071#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1 0x013b
3072#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
3073#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2 0x013c
3074#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
3075#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3 0x013d
3076#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
3077#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL 0x013e
3078#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL_BASE_IDX 2
3079#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL 0x013f
3080#define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL_BASE_IDX 2
3081#define mmBIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX 0x0140
3082#define mmBIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX_BASE_IDX 2
3083
3084
3085// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf7_SYSPFVFDEC
3086// base address: 0x0
3087#define mmBIF_BX_DEV0_EPF0_VF7_MM_INDEX 0x0000
3088#define mmBIF_BX_DEV0_EPF0_VF7_MM_INDEX_BASE_IDX 0
3089#define mmBIF_BX_DEV0_EPF0_VF7_MM_DATA 0x0001
3090#define mmBIF_BX_DEV0_EPF0_VF7_MM_DATA_BASE_IDX 0
3091#define mmBIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI 0x0006
3092#define mmBIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI_BASE_IDX 0
3093
3094
3095// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf7_BIFPFVFDEC1
3096// base address: 0x0
3097#define mmBIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS 0x00eb
3098#define mmBIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS_BASE_IDX 2
3099#define mmBIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG 0x00ec
3100#define mmBIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
3101#define mmBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
3102#define mmBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
3103#define mmBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
3104#define mmBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
3105#define mmBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
3106#define mmBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
3107#define mmBIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
3108#define mmBIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
3109#define mmBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
3110#define mmBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
3111#define mmBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ 0x0106
3112#define mmBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ_BASE_IDX 2
3113#define mmBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE 0x0107
3114#define mmBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE_BASE_IDX 2
3115#define mmBIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING 0x0108
3116#define mmBIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING_BASE_IDX 2
3117#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0 0x0136
3118#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
3119#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1 0x0137
3120#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
3121#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2 0x0138
3122#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
3123#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3 0x0139
3124#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
3125#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0 0x013a
3126#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
3127#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1 0x013b
3128#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
3129#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2 0x013c
3130#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
3131#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3 0x013d
3132#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
3133#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL 0x013e
3134#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL_BASE_IDX 2
3135#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL 0x013f
3136#define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL_BASE_IDX 2
3137#define mmBIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX 0x0140
3138#define mmBIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX_BASE_IDX 2
3139
3140
3141// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf8_SYSPFVFDEC
3142// base address: 0x0
3143#define mmBIF_BX_DEV0_EPF0_VF8_MM_INDEX 0x0000
3144#define mmBIF_BX_DEV0_EPF0_VF8_MM_INDEX_BASE_IDX 0
3145#define mmBIF_BX_DEV0_EPF0_VF8_MM_DATA 0x0001
3146#define mmBIF_BX_DEV0_EPF0_VF8_MM_DATA_BASE_IDX 0
3147#define mmBIF_BX_DEV0_EPF0_VF8_MM_INDEX_HI 0x0006
3148#define mmBIF_BX_DEV0_EPF0_VF8_MM_INDEX_HI_BASE_IDX 0
3149
3150
3151// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf8_BIFPFVFDEC1
3152// base address: 0x0
3153#define mmBIF_BX_DEV0_EPF0_VF8_BIF_BME_STATUS 0x00eb
3154#define mmBIF_BX_DEV0_EPF0_VF8_BIF_BME_STATUS_BASE_IDX 2
3155#define mmBIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG 0x00ec
3156#define mmBIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
3157#define mmBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
3158#define mmBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
3159#define mmBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
3160#define mmBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
3161#define mmBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
3162#define mmBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
3163#define mmBIF_BX_DEV0_EPF0_VF8_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
3164#define mmBIF_BX_DEV0_EPF0_VF8_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
3165#define mmBIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
3166#define mmBIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
3167#define mmBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ 0x0106
3168#define mmBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ_BASE_IDX 2
3169#define mmBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE 0x0107
3170#define mmBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE_BASE_IDX 2
3171#define mmBIF_BX_DEV0_EPF0_VF8_BIF_TRANS_PENDING 0x0108
3172#define mmBIF_BX_DEV0_EPF0_VF8_BIF_TRANS_PENDING_BASE_IDX 2
3173#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW0 0x0136
3174#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
3175#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW1 0x0137
3176#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
3177#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW2 0x0138
3178#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
3179#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW3 0x0139
3180#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
3181#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW0 0x013a
3182#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
3183#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW1 0x013b
3184#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
3185#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW2 0x013c
3186#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
3187#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW3 0x013d
3188#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
3189#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL 0x013e
3190#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL_BASE_IDX 2
3191#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_INT_CNTL 0x013f
3192#define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_INT_CNTL_BASE_IDX 2
3193#define mmBIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX 0x0140
3194#define mmBIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX_BASE_IDX 2
3195
3196
3197// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf9_SYSPFVFDEC
3198// base address: 0x0
3199#define mmBIF_BX_DEV0_EPF0_VF9_MM_INDEX 0x0000
3200#define mmBIF_BX_DEV0_EPF0_VF9_MM_INDEX_BASE_IDX 0
3201#define mmBIF_BX_DEV0_EPF0_VF9_MM_DATA 0x0001
3202#define mmBIF_BX_DEV0_EPF0_VF9_MM_DATA_BASE_IDX 0
3203#define mmBIF_BX_DEV0_EPF0_VF9_MM_INDEX_HI 0x0006
3204#define mmBIF_BX_DEV0_EPF0_VF9_MM_INDEX_HI_BASE_IDX 0
3205
3206
3207// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf9_BIFPFVFDEC1
3208// base address: 0x0
3209#define mmBIF_BX_DEV0_EPF0_VF9_BIF_BME_STATUS 0x00eb
3210#define mmBIF_BX_DEV0_EPF0_VF9_BIF_BME_STATUS_BASE_IDX 2
3211#define mmBIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG 0x00ec
3212#define mmBIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
3213#define mmBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
3214#define mmBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
3215#define mmBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
3216#define mmBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
3217#define mmBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
3218#define mmBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
3219#define mmBIF_BX_DEV0_EPF0_VF9_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
3220#define mmBIF_BX_DEV0_EPF0_VF9_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
3221#define mmBIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
3222#define mmBIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
3223#define mmBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ 0x0106
3224#define mmBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ_BASE_IDX 2
3225#define mmBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE 0x0107
3226#define mmBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE_BASE_IDX 2
3227#define mmBIF_BX_DEV0_EPF0_VF9_BIF_TRANS_PENDING 0x0108
3228#define mmBIF_BX_DEV0_EPF0_VF9_BIF_TRANS_PENDING_BASE_IDX 2
3229#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW0 0x0136
3230#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
3231#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW1 0x0137
3232#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
3233#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW2 0x0138
3234#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
3235#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW3 0x0139
3236#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
3237#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW0 0x013a
3238#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
3239#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW1 0x013b
3240#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
3241#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW2 0x013c
3242#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
3243#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW3 0x013d
3244#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
3245#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL 0x013e
3246#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL_BASE_IDX 2
3247#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_INT_CNTL 0x013f
3248#define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_INT_CNTL_BASE_IDX 2
3249#define mmBIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX 0x0140
3250#define mmBIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX_BASE_IDX 2
3251
3252
3253// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf10_SYSPFVFDEC
3254// base address: 0x0
3255#define mmBIF_BX_DEV0_EPF0_VF10_MM_INDEX 0x0000
3256#define mmBIF_BX_DEV0_EPF0_VF10_MM_INDEX_BASE_IDX 0
3257#define mmBIF_BX_DEV0_EPF0_VF10_MM_DATA 0x0001
3258#define mmBIF_BX_DEV0_EPF0_VF10_MM_DATA_BASE_IDX 0
3259#define mmBIF_BX_DEV0_EPF0_VF10_MM_INDEX_HI 0x0006
3260#define mmBIF_BX_DEV0_EPF0_VF10_MM_INDEX_HI_BASE_IDX 0
3261
3262
3263// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf10_BIFPFVFDEC1
3264// base address: 0x0
3265#define mmBIF_BX_DEV0_EPF0_VF10_BIF_BME_STATUS 0x00eb
3266#define mmBIF_BX_DEV0_EPF0_VF10_BIF_BME_STATUS_BASE_IDX 2
3267#define mmBIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG 0x00ec
3268#define mmBIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
3269#define mmBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
3270#define mmBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
3271#define mmBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
3272#define mmBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
3273#define mmBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
3274#define mmBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
3275#define mmBIF_BX_DEV0_EPF0_VF10_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
3276#define mmBIF_BX_DEV0_EPF0_VF10_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
3277#define mmBIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
3278#define mmBIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
3279#define mmBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ 0x0106
3280#define mmBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ_BASE_IDX 2
3281#define mmBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE 0x0107
3282#define mmBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE_BASE_IDX 2
3283#define mmBIF_BX_DEV0_EPF0_VF10_BIF_TRANS_PENDING 0x0108
3284#define mmBIF_BX_DEV0_EPF0_VF10_BIF_TRANS_PENDING_BASE_IDX 2
3285#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW0 0x0136
3286#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
3287#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW1 0x0137
3288#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
3289#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW2 0x0138
3290#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
3291#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW3 0x0139
3292#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
3293#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW0 0x013a
3294#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
3295#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW1 0x013b
3296#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
3297#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW2 0x013c
3298#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
3299#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW3 0x013d
3300#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
3301#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL 0x013e
3302#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL_BASE_IDX 2
3303#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_INT_CNTL 0x013f
3304#define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_INT_CNTL_BASE_IDX 2
3305#define mmBIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX 0x0140
3306#define mmBIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX_BASE_IDX 2
3307
3308
3309// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf11_SYSPFVFDEC
3310// base address: 0x0
3311#define mmBIF_BX_DEV0_EPF0_VF11_MM_INDEX 0x0000
3312#define mmBIF_BX_DEV0_EPF0_VF11_MM_INDEX_BASE_IDX 0
3313#define mmBIF_BX_DEV0_EPF0_VF11_MM_DATA 0x0001
3314#define mmBIF_BX_DEV0_EPF0_VF11_MM_DATA_BASE_IDX 0
3315#define mmBIF_BX_DEV0_EPF0_VF11_MM_INDEX_HI 0x0006
3316#define mmBIF_BX_DEV0_EPF0_VF11_MM_INDEX_HI_BASE_IDX 0
3317
3318
3319// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf11_BIFPFVFDEC1
3320// base address: 0x0
3321#define mmBIF_BX_DEV0_EPF0_VF11_BIF_BME_STATUS 0x00eb
3322#define mmBIF_BX_DEV0_EPF0_VF11_BIF_BME_STATUS_BASE_IDX 2
3323#define mmBIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG 0x00ec
3324#define mmBIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
3325#define mmBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
3326#define mmBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
3327#define mmBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
3328#define mmBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
3329#define mmBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
3330#define mmBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
3331#define mmBIF_BX_DEV0_EPF0_VF11_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
3332#define mmBIF_BX_DEV0_EPF0_VF11_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
3333#define mmBIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
3334#define mmBIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
3335#define mmBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ 0x0106
3336#define mmBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ_BASE_IDX 2
3337#define mmBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE 0x0107
3338#define mmBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE_BASE_IDX 2
3339#define mmBIF_BX_DEV0_EPF0_VF11_BIF_TRANS_PENDING 0x0108
3340#define mmBIF_BX_DEV0_EPF0_VF11_BIF_TRANS_PENDING_BASE_IDX 2
3341#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW0 0x0136
3342#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
3343#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW1 0x0137
3344#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
3345#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW2 0x0138
3346#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
3347#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW3 0x0139
3348#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
3349#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW0 0x013a
3350#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
3351#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW1 0x013b
3352#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
3353#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW2 0x013c
3354#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
3355#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW3 0x013d
3356#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
3357#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL 0x013e
3358#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL_BASE_IDX 2
3359#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_INT_CNTL 0x013f
3360#define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_INT_CNTL_BASE_IDX 2
3361#define mmBIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX 0x0140
3362#define mmBIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX_BASE_IDX 2
3363
3364
3365// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf12_SYSPFVFDEC
3366// base address: 0x0
3367#define mmBIF_BX_DEV0_EPF0_VF12_MM_INDEX 0x0000
3368#define mmBIF_BX_DEV0_EPF0_VF12_MM_INDEX_BASE_IDX 0
3369#define mmBIF_BX_DEV0_EPF0_VF12_MM_DATA 0x0001
3370#define mmBIF_BX_DEV0_EPF0_VF12_MM_DATA_BASE_IDX 0
3371#define mmBIF_BX_DEV0_EPF0_VF12_MM_INDEX_HI 0x0006
3372#define mmBIF_BX_DEV0_EPF0_VF12_MM_INDEX_HI_BASE_IDX 0
3373
3374
3375// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf12_BIFPFVFDEC1
3376// base address: 0x0
3377#define mmBIF_BX_DEV0_EPF0_VF12_BIF_BME_STATUS 0x00eb
3378#define mmBIF_BX_DEV0_EPF0_VF12_BIF_BME_STATUS_BASE_IDX 2
3379#define mmBIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG 0x00ec
3380#define mmBIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
3381#define mmBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
3382#define mmBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
3383#define mmBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
3384#define mmBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
3385#define mmBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
3386#define mmBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
3387#define mmBIF_BX_DEV0_EPF0_VF12_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
3388#define mmBIF_BX_DEV0_EPF0_VF12_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
3389#define mmBIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
3390#define mmBIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
3391#define mmBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ 0x0106
3392#define mmBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ_BASE_IDX 2
3393#define mmBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE 0x0107
3394#define mmBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE_BASE_IDX 2
3395#define mmBIF_BX_DEV0_EPF0_VF12_BIF_TRANS_PENDING 0x0108
3396#define mmBIF_BX_DEV0_EPF0_VF12_BIF_TRANS_PENDING_BASE_IDX 2
3397#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW0 0x0136
3398#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
3399#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW1 0x0137
3400#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
3401#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW2 0x0138
3402#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
3403#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW3 0x0139
3404#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
3405#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW0 0x013a
3406#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
3407#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW1 0x013b
3408#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
3409#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW2 0x013c
3410#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
3411#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW3 0x013d
3412#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
3413#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL 0x013e
3414#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL_BASE_IDX 2
3415#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_INT_CNTL 0x013f
3416#define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_INT_CNTL_BASE_IDX 2
3417#define mmBIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX 0x0140
3418#define mmBIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX_BASE_IDX 2
3419
3420
3421// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf13_SYSPFVFDEC
3422// base address: 0x0
3423#define mmBIF_BX_DEV0_EPF0_VF13_MM_INDEX 0x0000
3424#define mmBIF_BX_DEV0_EPF0_VF13_MM_INDEX_BASE_IDX 0
3425#define mmBIF_BX_DEV0_EPF0_VF13_MM_DATA 0x0001
3426#define mmBIF_BX_DEV0_EPF0_VF13_MM_DATA_BASE_IDX 0
3427#define mmBIF_BX_DEV0_EPF0_VF13_MM_INDEX_HI 0x0006
3428#define mmBIF_BX_DEV0_EPF0_VF13_MM_INDEX_HI_BASE_IDX 0
3429
3430
3431// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf13_BIFPFVFDEC1
3432// base address: 0x0
3433#define mmBIF_BX_DEV0_EPF0_VF13_BIF_BME_STATUS 0x00eb
3434#define mmBIF_BX_DEV0_EPF0_VF13_BIF_BME_STATUS_BASE_IDX 2
3435#define mmBIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG 0x00ec
3436#define mmBIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
3437#define mmBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
3438#define mmBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
3439#define mmBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
3440#define mmBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
3441#define mmBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
3442#define mmBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
3443#define mmBIF_BX_DEV0_EPF0_VF13_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
3444#define mmBIF_BX_DEV0_EPF0_VF13_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
3445#define mmBIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
3446#define mmBIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
3447#define mmBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ 0x0106
3448#define mmBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ_BASE_IDX 2
3449#define mmBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE 0x0107
3450#define mmBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE_BASE_IDX 2
3451#define mmBIF_BX_DEV0_EPF0_VF13_BIF_TRANS_PENDING 0x0108
3452#define mmBIF_BX_DEV0_EPF0_VF13_BIF_TRANS_PENDING_BASE_IDX 2
3453#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW0 0x0136
3454#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
3455#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW1 0x0137
3456#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
3457#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW2 0x0138
3458#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
3459#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW3 0x0139
3460#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
3461#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW0 0x013a
3462#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
3463#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW1 0x013b
3464#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
3465#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW2 0x013c
3466#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
3467#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW3 0x013d
3468#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
3469#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL 0x013e
3470#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL_BASE_IDX 2
3471#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_INT_CNTL 0x013f
3472#define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_INT_CNTL_BASE_IDX 2
3473#define mmBIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX 0x0140
3474#define mmBIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX_BASE_IDX 2
3475
3476
3477// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf14_SYSPFVFDEC
3478// base address: 0x0
3479#define mmBIF_BX_DEV0_EPF0_VF14_MM_INDEX 0x0000
3480#define mmBIF_BX_DEV0_EPF0_VF14_MM_INDEX_BASE_IDX 0
3481#define mmBIF_BX_DEV0_EPF0_VF14_MM_DATA 0x0001
3482#define mmBIF_BX_DEV0_EPF0_VF14_MM_DATA_BASE_IDX 0
3483#define mmBIF_BX_DEV0_EPF0_VF14_MM_INDEX_HI 0x0006
3484#define mmBIF_BX_DEV0_EPF0_VF14_MM_INDEX_HI_BASE_IDX 0
3485
3486
3487// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf14_BIFPFVFDEC1
3488// base address: 0x0
3489#define mmBIF_BX_DEV0_EPF0_VF14_BIF_BME_STATUS 0x00eb
3490#define mmBIF_BX_DEV0_EPF0_VF14_BIF_BME_STATUS_BASE_IDX 2
3491#define mmBIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG 0x00ec
3492#define mmBIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
3493#define mmBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
3494#define mmBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
3495#define mmBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
3496#define mmBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
3497#define mmBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
3498#define mmBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
3499#define mmBIF_BX_DEV0_EPF0_VF14_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
3500#define mmBIF_BX_DEV0_EPF0_VF14_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
3501#define mmBIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
3502#define mmBIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
3503#define mmBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ 0x0106
3504#define mmBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ_BASE_IDX 2
3505#define mmBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE 0x0107
3506#define mmBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE_BASE_IDX 2
3507#define mmBIF_BX_DEV0_EPF0_VF14_BIF_TRANS_PENDING 0x0108
3508#define mmBIF_BX_DEV0_EPF0_VF14_BIF_TRANS_PENDING_BASE_IDX 2
3509#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW0 0x0136
3510#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
3511#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW1 0x0137
3512#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
3513#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW2 0x0138
3514#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
3515#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW3 0x0139
3516#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
3517#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW0 0x013a
3518#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
3519#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW1 0x013b
3520#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
3521#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW2 0x013c
3522#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
3523#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW3 0x013d
3524#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
3525#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL 0x013e
3526#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL_BASE_IDX 2
3527#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_INT_CNTL 0x013f
3528#define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_INT_CNTL_BASE_IDX 2
3529#define mmBIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX 0x0140
3530#define mmBIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX_BASE_IDX 2
3531
3532
3533// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf15_SYSPFVFDEC
3534// base address: 0x0
3535#define mmBIF_BX_DEV0_EPF0_VF15_MM_INDEX 0x0000
3536#define mmBIF_BX_DEV0_EPF0_VF15_MM_INDEX_BASE_IDX 0
3537#define mmBIF_BX_DEV0_EPF0_VF15_MM_DATA 0x0001
3538#define mmBIF_BX_DEV0_EPF0_VF15_MM_DATA_BASE_IDX 0
3539#define mmBIF_BX_DEV0_EPF0_VF15_MM_INDEX_HI 0x0006
3540#define mmBIF_BX_DEV0_EPF0_VF15_MM_INDEX_HI_BASE_IDX 0
3541
3542
3543// addressBlock: nbio_nbif_bif_bx_dev0_epf0_vf15_BIFPFVFDEC1
3544// base address: 0x0
3545#define mmBIF_BX_DEV0_EPF0_VF15_BIF_BME_STATUS 0x00eb
3546#define mmBIF_BX_DEV0_EPF0_VF15_BIF_BME_STATUS_BASE_IDX 2
3547#define mmBIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG 0x00ec
3548#define mmBIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG_BASE_IDX 2
3549#define mmBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3
3550#define mmBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2
3551#define mmBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4
3552#define mmBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2
3553#define mmBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5
3554#define mmBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2
3555#define mmBIF_BX_DEV0_EPF0_VF15_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6
3556#define mmBIF_BX_DEV0_EPF0_VF15_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2
3557#define mmBIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7
3558#define mmBIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2
3559#define mmBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ 0x0106
3560#define mmBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ_BASE_IDX 2
3561#define mmBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE 0x0107
3562#define mmBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE_BASE_IDX 2
3563#define mmBIF_BX_DEV0_EPF0_VF15_BIF_TRANS_PENDING 0x0108
3564#define mmBIF_BX_DEV0_EPF0_VF15_BIF_TRANS_PENDING_BASE_IDX 2
3565#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW0 0x0136
3566#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2
3567#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW1 0x0137
3568#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2
3569#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW2 0x0138
3570#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2
3571#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW3 0x0139
3572#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2
3573#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW0 0x013a
3574#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2
3575#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW1 0x013b
3576#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2
3577#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW2 0x013c
3578#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2
3579#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW3 0x013d
3580#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2
3581#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL 0x013e
3582#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL_BASE_IDX 2
3583#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_INT_CNTL 0x013f
3584#define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_INT_CNTL_BASE_IDX 2
3585#define mmBIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX 0x0140
3586#define mmBIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX_BASE_IDX 2
3587
3588
3589// addressBlock: syshub_mmreg_ind_syshubind
3590// base address: 0x0
3591#define ixSYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK 0x10000
3592#define ixSYSHUB_MMREG_IND_SYSHUB_DS_CTRL2_SOCCLK 0x10004
3593#define ixSYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK 0x10008
3594#define ixSYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK 0x1000c
3595#define ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL 0x10010
3596#define ixSYSHUB_MMREG_IND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL 0x10014
3597#define ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL0_CNTL 0x10018
3598#define ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL1_CNTL 0x1001c
3599#define ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL2_CNTL 0x10020
3600#define ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL3_CNTL 0x10024
3601#define ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL4_CNTL 0x10028
3602#define ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL5_CNTL 0x1002c
3603#define ixSYSHUB_MMREG_IND_DMA_CLK0_SW1_CL0_CNTL 0x10030
3604#define ixSYSHUB_MMREG_IND_DMA_CLK0_SW2_CL0_CNTL 0x10034
3605#define ixSYSHUB_MMREG_IND_HST_CLK0_SW0_CL0_CNTL 0x10100
3606#define ixSYSHUB_MMREG_IND_HST_CLK0_SW0_CL1_CNTL 0x10104
3607#define ixSYSHUB_MMREG_IND_HST_CLK0_SW0_CL2_CNTL 0x10108
3608#define ixSYSHUB_MMREG_IND_HST_CLK0_SW1_CL0_CNTL 0x1010c
3609#define ixSYSHUB_MMREG_IND_HST_CLK0_SW1_CL1_CNTL 0x10110
3610#define ixSYSHUB_MMREG_IND_HST_CLK0_SW1_CL2_CNTL 0x10114
3611#define ixSYSHUB_MMREG_IND_HST_CLK0_SW1_CL3_CNTL 0x10118
3612#define ixSYSHUB_MMREG_IND_HST_CLK0_SW1_CL4_CNTL 0x1011c
3613#define ixSYSHUB_MMREG_IND_SYSHUB_CG_CNTL 0x10300
3614#define ixSYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE 0x10308
3615#define ixSYSHUB_MMREG_IND_SYSHUB_HP_TIMER 0x1030c
3616#define ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK 0x10310
3617#define ixSYSHUB_MMREG_IND_SYSHUB_SCRATCH 0x10f00
3618#define ixSYSHUB_MMREG_IND_SYSHUB_CL_MASK 0x10f04
3619#define ixSYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK 0x11000
3620#define ixSYSHUB_MMREG_IND_SYSHUB_DS_CTRL2_SHUBCLK 0x11004
3621#define ixSYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK 0x11008
3622#define ixSYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK 0x1100c
3623#define ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL 0x11010
3624#define ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL 0x11014
3625#define ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_CL0_CNTL 0x11018
3626#define ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_CL1_CNTL 0x1101c
3627#define ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_CL2_CNTL 0x11020
3628#define ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_CL3_CNTL 0x11024
3629#define ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_CL4_CNTL 0x11028
3630#define ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_CL0_CNTL 0x1102c
3631#define ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_CL1_CNTL 0x11030
3632#define ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_CL2_CNTL 0x11034
3633#define ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_CL3_CNTL 0x11038
3634#define ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_CL4_CNTL 0x1103c
3635#define ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK 0x11040
3636#define ixSYSHUB_MMREG_IND_NIC400_0_ASIB_0_FN_MOD 0x20108
3637#define ixSYSHUB_MMREG_IND_NIC400_0_AMIB_0_FN_MOD_BM_ISS 0x30008
3638#define ixSYSHUB_MMREG_IND_NIC400_0_AMIB_1_FN_MOD_BM_ISS 0x31008
3639#define ixSYSHUB_MMREG_IND_NIC400_0_AMIB_2_FN_MOD_BM_ISS 0x32008
3640#define ixSYSHUB_MMREG_IND_NIC400_1_ASIB_0_FN_MOD 0x40108
3641#define ixSYSHUB_MMREG_IND_NIC400_1_AMIB_0_FN_MOD 0x50008
3642#define ixSYSHUB_MMREG_IND_NIC400_1_AMIB_1_FN_MOD 0x51008
3643#define ixSYSHUB_MMREG_IND_NIC400_1_AMIB_2_FN_MOD 0x52008
3644#define ixSYSHUB_MMREG_IND_NIC400_1_AMIB_3_FN_MOD 0x53008
3645#define ixSYSHUB_MMREG_IND_NIC400_1_AMIB_4_FN_MOD 0x54008
3646#define ixSYSHUB_MMREG_IND_NIC400_2_ASIB_0_FN_MOD 0x60108
3647#define ixSYSHUB_MMREG_IND_NIC400_2_ASIB_1_FN_MOD 0x61108
3648#define ixSYSHUB_MMREG_IND_NIC400_2_ASIB_2_FN_MOD 0x62108
3649#define ixSYSHUB_MMREG_IND_NIC400_2_AMIB_0_FN_MOD_BM_ISS 0x70008
3650
3651#endif
3652

Warning: This file is not a C or C++ file. It does not have highlighting.

source code of linux/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_offset.h