1 | /* |
2 | * Copyright (C) 2017 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included |
12 | * in all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
15 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN |
18 | * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
19 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
20 | */ |
21 | #ifndef _nbio_7_0_DEFAULT_HEADER |
22 | #define |
23 | |
24 | |
25 | // addressBlock: nbio_iohub_nb_nbcfg_nb_cfgdec |
26 | #define cfgNB_NBCFG0_NB_VENDOR_ID_DEFAULT 0x00000000 |
27 | #define cfgNB_NBCFG0_NB_DEVICE_ID_DEFAULT 0x00000000 |
28 | #define cfgNB_NBCFG0_NB_COMMAND_DEFAULT 0x00000000 |
29 | #define cfgNB_NBCFG0_NB_STATUS_DEFAULT 0x00000000 |
30 | #define cfgNB_NBCFG0_NB_REVISION_ID_DEFAULT 0x00000000 |
31 | #define cfgNB_NBCFG0_NB_REGPROG_INF_DEFAULT 0x00000000 |
32 | #define cfgNB_NBCFG0_NB_SUB_CLASS_DEFAULT 0x00000000 |
33 | #define cfgNB_NBCFG0_NB_BASE_CODE_DEFAULT 0x00000000 |
34 | #define cfgNB_NBCFG0_NB_CACHE_LINE_DEFAULT 0x00000000 |
35 | #define cfgNB_NBCFG0_NB_LATENCY_DEFAULT 0x00000000 |
36 | #define 0x00000080 |
37 | #define cfgNB_NBCFG0_NB_ADAPTER_ID_DEFAULT 0x15d01022 |
38 | #define cfgNB_NBCFG0_NB_CAPABILITIES_PTR_DEFAULT 0x00000000 |
39 | #define 0x00000080 |
40 | #define cfgNB_NBCFG0_NB_PCI_CTRL_DEFAULT 0x00000000 |
41 | #define cfgNB_NBCFG0_NB_ADAPTER_ID_W_DEFAULT 0x15d01022 |
42 | #define cfgNB_NBCFG0_NB_SMN_INDEX_EXTENSION_0_DEFAULT 0x00000000 |
43 | #define cfgNB_NBCFG0_NB_SMN_INDEX_0_DEFAULT 0x00000000 |
44 | #define cfgNB_NBCFG0_NB_SMN_DATA_0_DEFAULT 0x00000000 |
45 | #define cfgNB_NBCFG0_NBCFG_SCRATCH_0_DEFAULT 0x00000000 |
46 | #define cfgNB_NBCFG0_NBCFG_SCRATCH_1_DEFAULT 0x00000000 |
47 | #define cfgNB_NBCFG0_NBCFG_SCRATCH_2_DEFAULT 0x00000000 |
48 | #define cfgNB_NBCFG0_NBCFG_SCRATCH_3_DEFAULT 0x00000000 |
49 | #define cfgNB_NBCFG0_NBCFG_SCRATCH_4_DEFAULT 0x00000000 |
50 | #define cfgNB_NBCFG0_NB_PCI_ARB_DEFAULT 0x00000108 |
51 | #define cfgNB_NBCFG0_NB_DRAM_SLOT1_BASE_DEFAULT 0x00000000 |
52 | #define cfgNB_NBCFG0_NB_TOP_OF_DRAM_SLOT1_DEFAULT 0x00000000 |
53 | #define cfgNB_NBCFG0_NB_SMN_INDEX_EXTENSION_1_DEFAULT 0x00000000 |
54 | #define cfgNB_NBCFG0_NB_SMN_INDEX_1_DEFAULT 0x00000000 |
55 | #define cfgNB_NBCFG0_NB_SMN_DATA_1_DEFAULT 0x00000000 |
56 | #define cfgNB_NBCFG0_NB_INDEX_DATA_MUTEX0_DEFAULT 0x00000000 |
57 | #define cfgNB_NBCFG0_NB_INDEX_DATA_MUTEX1_DEFAULT 0x00000000 |
58 | #define cfgNB_NBCFG0_NB_SMN_INDEX_EXTENSION_2_DEFAULT 0x00000000 |
59 | #define cfgNB_NBCFG0_NB_SMN_INDEX_2_DEFAULT 0x00000000 |
60 | #define cfgNB_NBCFG0_NB_SMN_DATA_2_DEFAULT 0x00000000 |
61 | #define cfgNB_NBCFG0_NB_SMN_INDEX_EXTENSION_3_DEFAULT 0x00000000 |
62 | #define cfgNB_NBCFG0_NB_SMN_INDEX_3_DEFAULT 0x00000000 |
63 | #define cfgNB_NBCFG0_NB_SMN_DATA_3_DEFAULT 0x00000000 |
64 | #define cfgNB_NBCFG0_NB_SMN_INDEX_EXTENSION_4_DEFAULT 0x00000000 |
65 | #define cfgNB_NBCFG0_NB_SMN_INDEX_4_DEFAULT 0x00000000 |
66 | #define cfgNB_NBCFG0_NB_SMN_DATA_4_DEFAULT 0x00000000 |
67 | #define cfgNB_NBCFG0_NB_SMN_INDEX_EXTENSION_5_DEFAULT 0x00000000 |
68 | #define cfgNB_NBCFG0_NB_SMN_INDEX_5_DEFAULT 0x00000000 |
69 | #define cfgNB_NBCFG0_NB_SMN_DATA_5_DEFAULT 0x00000000 |
70 | #define cfgNB_NBCFG0_NB_PERF_CNT_CTRL_DEFAULT 0x00808000 |
71 | #define cfgNB_NBCFG0_NB_SMN_INDEX_6_DEFAULT 0x00000000 |
72 | #define cfgNB_NBCFG0_NB_SMN_DATA_6_DEFAULT 0x00000000 |
73 | |
74 | |
75 | // addressBlock: nbio_iohub_iommu_l2_iommul2cfg |
76 | #define cfgIOMMU_L2_0_IOMMU_VENDOR_ID_DEFAULT 0x00001022 |
77 | #define cfgIOMMU_L2_0_IOMMU_DEVICE_ID_DEFAULT 0x000015d1 |
78 | #define cfgIOMMU_L2_0_IOMMU_COMMAND_DEFAULT 0x00000000 |
79 | #define cfgIOMMU_L2_0_IOMMU_STATUS_DEFAULT 0x00000000 |
80 | #define cfgIOMMU_L2_0_IOMMU_REVISION_ID_DEFAULT 0x00000000 |
81 | #define cfgIOMMU_L2_0_IOMMU_REGPROG_INF_DEFAULT 0x00000000 |
82 | #define cfgIOMMU_L2_0_IOMMU_SUB_CLASS_DEFAULT 0x00000000 |
83 | #define cfgIOMMU_L2_0_IOMMU_BASE_CODE_DEFAULT 0x00000000 |
84 | #define cfgIOMMU_L2_0_IOMMU_CACHE_LINE_DEFAULT 0x00000000 |
85 | #define cfgIOMMU_L2_0_IOMMU_LATENCY_DEFAULT 0x00000000 |
86 | #define 0x00000000 |
87 | #define cfgIOMMU_L2_0_IOMMU_BIST_DEFAULT 0x00000000 |
88 | #define cfgIOMMU_L2_0_IOMMU_ADAPTER_ID_DEFAULT 0x00000000 |
89 | #define cfgIOMMU_L2_0_IOMMU_CAPABILITIES_PTR_DEFAULT 0x00000000 |
90 | #define cfgIOMMU_L2_0_IOMMU_INTERRUPT_LINE_DEFAULT 0x00000000 |
91 | #define cfgIOMMU_L2_0_IOMMU_INTERRUPT_PIN_DEFAULT 0x00000001 |
92 | #define 0x00000000 |
93 | #define cfgIOMMU_L2_0_IOMMU_CAP_BASE_LO_DEFAULT 0x00000000 |
94 | #define cfgIOMMU_L2_0_IOMMU_CAP_BASE_HI_DEFAULT 0x00000000 |
95 | #define cfgIOMMU_L2_0_IOMMU_CAP_RANGE_DEFAULT 0x00000000 |
96 | #define cfgIOMMU_L2_0_IOMMU_CAP_MISC_DEFAULT 0x00003000 |
97 | #define cfgIOMMU_L2_0_IOMMU_CAP_MISC_1_DEFAULT 0x00000080 |
98 | #define cfgIOMMU_L2_0_IOMMU_MSI_CAP_DEFAULT 0x00000000 |
99 | #define cfgIOMMU_L2_0_IOMMU_MSI_ADDR_LO_DEFAULT 0x00000000 |
100 | #define cfgIOMMU_L2_0_IOMMU_MSI_ADDR_HI_DEFAULT 0x00000000 |
101 | #define cfgIOMMU_L2_0_IOMMU_MSI_DATA_DEFAULT 0x00000000 |
102 | #define cfgIOMMU_L2_0_IOMMU_MSI_MAPPING_CAP_DEFAULT 0x00000000 |
103 | #define cfgIOMMU_L2_0_IOMMU_ADAPTER_ID_W_DEFAULT 0x00000000 |
104 | #define cfgIOMMU_L2_0_IOMMU_CONTROL_W_DEFAULT 0x00002b01 |
105 | #define cfgIOMMU_L2_0_IOMMU_MMIO_CONTROL0_W_DEFAULT 0x62201ada |
106 | #define cfgIOMMU_L2_0_IOMMU_MMIO_CONTROL1_W_DEFAULT 0x0003cfcf |
107 | #define cfgIOMMU_L2_0_IOMMU_RANGE_W_DEFAULT 0x00000000 |
108 | #define cfgIOMMU_L2_0_IOMMU_DSFX_CONTROL_DEFAULT 0x00000000 |
109 | #define cfgIOMMU_L2_0_IOMMU_DSSX_DUMMY_0_DEFAULT 0x00000000 |
110 | #define cfgIOMMU_L2_0_IOMMU_DSCX_DUMMY_0_DEFAULT 0x00000000 |
111 | #define cfgIOMMU_L2_0_L2B_POISON_DVM_CNTRL_DEFAULT 0x00000002 |
112 | #define cfgIOMMU_L2_0_L2_IOHC_DmaReq_Stall_Control_DEFAULT 0x00000000 |
113 | #define cfgIOMMU_L2_0_IOHC_L2_HostRsp_Stall_Control_DEFAULT 0x00000000 |
114 | #define cfgIOMMU_L2_0_SMMU_MMIO_IDR0_W_DEFAULT 0x2d4f7fbf |
115 | #define cfgIOMMU_L2_0_SMMU_MMIO_IDR1_W_DEFAULT 0x0e739c10 |
116 | #define cfgIOMMU_L2_0_SMMU_MMIO_IDR2_W_DEFAULT 0x00000000 |
117 | #define cfgIOMMU_L2_0_SMMU_MMIO_IDR3_W_DEFAULT 0x00000000 |
118 | #define cfgIOMMU_L2_0_SMMU_MMIO_IDR5_W_DEFAULT 0x00000075 |
119 | #define cfgIOMMU_L2_0_SMMU_MMIO_IIDR_W_DEFAULT 0x00000000 |
120 | #define cfgIOMMU_L2_0_SMMU_AIDR_W_DEFAULT 0x00000000 |
121 | |
122 | |
123 | // addressBlock: nbio_nbif0_bif_cfg_dev0_rc_bifcfgdecp |
124 | #define cfgBIF_CFG_DEV0_RC0_VENDOR_ID_DEFAULT 0x00000000 |
125 | #define cfgBIF_CFG_DEV0_RC0_DEVICE_ID_DEFAULT 0x00000000 |
126 | #define cfgBIF_CFG_DEV0_RC0_COMMAND_DEFAULT 0x00000000 |
127 | #define cfgBIF_CFG_DEV0_RC0_STATUS_DEFAULT 0x00000000 |
128 | #define cfgBIF_CFG_DEV0_RC0_REVISION_ID_DEFAULT 0x00000000 |
129 | #define cfgBIF_CFG_DEV0_RC0_PROG_INTERFACE_DEFAULT 0x00000000 |
130 | #define cfgBIF_CFG_DEV0_RC0_SUB_CLASS_DEFAULT 0x00000000 |
131 | #define cfgBIF_CFG_DEV0_RC0_BASE_CLASS_DEFAULT 0x00000000 |
132 | #define cfgBIF_CFG_DEV0_RC0_CACHE_LINE_DEFAULT 0x00000000 |
133 | #define cfgBIF_CFG_DEV0_RC0_LATENCY_DEFAULT 0x00000000 |
134 | #define 0x00000000 |
135 | #define cfgBIF_CFG_DEV0_RC0_BIST_DEFAULT 0x00000000 |
136 | #define cfgBIF_CFG_DEV0_RC0_BASE_ADDR_1_DEFAULT 0x00000000 |
137 | #define cfgBIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 |
138 | #define cfgBIF_CFG_DEV0_RC0_IO_BASE_LIMIT_DEFAULT 0x00000000 |
139 | #define cfgBIF_CFG_DEV0_RC0_SECONDARY_STATUS_DEFAULT 0x00000000 |
140 | #define cfgBIF_CFG_DEV0_RC0_MEM_BASE_LIMIT_DEFAULT 0x00000000 |
141 | #define cfgBIF_CFG_DEV0_RC0_PREF_BASE_LIMIT_DEFAULT 0x00000000 |
142 | #define cfgBIF_CFG_DEV0_RC0_PREF_BASE_UPPER_DEFAULT 0x00000000 |
143 | #define cfgBIF_CFG_DEV0_RC0_PREF_LIMIT_UPPER_DEFAULT 0x00000000 |
144 | #define cfgBIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI_DEFAULT 0x00000000 |
145 | #define cfgBIF_CFG_DEV0_RC0_CAP_PTR_DEFAULT 0x00000000 |
146 | #define cfgBIF_CFG_DEV0_RC0_INTERRUPT_LINE_DEFAULT 0x000000ff |
147 | #define cfgBIF_CFG_DEV0_RC0_INTERRUPT_PIN_DEFAULT 0x00000001 |
148 | #define cfgBIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000 |
149 | #define cfgBIF_CFG_DEV0_RC0_EXT_BRIDGE_CNTL_DEFAULT 0x00000000 |
150 | #define cfgBIF_CFG_DEV0_RC0_PMI_CAP_LIST_DEFAULT 0x00000000 |
151 | #define cfgBIF_CFG_DEV0_RC0_PMI_CAP_DEFAULT 0x00000000 |
152 | #define cfgBIF_CFG_DEV0_RC0_PMI_STATUS_CNTL_DEFAULT 0x00000000 |
153 | #define cfgBIF_CFG_DEV0_RC0_PCIE_CAP_LIST_DEFAULT 0x0000a000 |
154 | #define cfgBIF_CFG_DEV0_RC0_PCIE_CAP_DEFAULT 0x00000042 |
155 | #define cfgBIF_CFG_DEV0_RC0_DEVICE_CAP_DEFAULT 0x00000000 |
156 | #define cfgBIF_CFG_DEV0_RC0_DEVICE_CNTL_DEFAULT 0x00002810 |
157 | #define cfgBIF_CFG_DEV0_RC0_DEVICE_STATUS_DEFAULT 0x00000000 |
158 | #define cfgBIF_CFG_DEV0_RC0_LINK_CAP_DEFAULT 0x00011c03 |
159 | #define cfgBIF_CFG_DEV0_RC0_LINK_CNTL_DEFAULT 0x00000000 |
160 | #define cfgBIF_CFG_DEV0_RC0_LINK_STATUS_DEFAULT 0x00002001 |
161 | #define cfgBIF_CFG_DEV0_RC0_SLOT_CAP_DEFAULT 0x00000000 |
162 | #define cfgBIF_CFG_DEV0_RC0_SLOT_CNTL_DEFAULT 0x00000000 |
163 | #define cfgBIF_CFG_DEV0_RC0_SLOT_STATUS_DEFAULT 0x00000000 |
164 | #define cfgBIF_CFG_DEV0_RC0_ROOT_CNTL_DEFAULT 0x00000000 |
165 | #define cfgBIF_CFG_DEV0_RC0_ROOT_CAP_DEFAULT 0x00000000 |
166 | #define cfgBIF_CFG_DEV0_RC0_ROOT_STATUS_DEFAULT 0x00000000 |
167 | #define cfgBIF_CFG_DEV0_RC0_DEVICE_CAP2_DEFAULT 0x00000000 |
168 | #define cfgBIF_CFG_DEV0_RC0_DEVICE_CNTL2_DEFAULT 0x00000000 |
169 | #define cfgBIF_CFG_DEV0_RC0_DEVICE_STATUS2_DEFAULT 0x00000000 |
170 | #define cfgBIF_CFG_DEV0_RC0_LINK_CAP2_DEFAULT 0x0000000e |
171 | #define cfgBIF_CFG_DEV0_RC0_LINK_CNTL2_DEFAULT 0x00000003 |
172 | #define cfgBIF_CFG_DEV0_RC0_LINK_STATUS2_DEFAULT 0x00000000 |
173 | #define cfgBIF_CFG_DEV0_RC0_SLOT_CAP2_DEFAULT 0x00000000 |
174 | #define cfgBIF_CFG_DEV0_RC0_SLOT_CNTL2_DEFAULT 0x00000000 |
175 | #define cfgBIF_CFG_DEV0_RC0_SLOT_STATUS2_DEFAULT 0x00000000 |
176 | #define cfgBIF_CFG_DEV0_RC0_MSI_CAP_LIST_DEFAULT 0x0000c000 |
177 | #define cfgBIF_CFG_DEV0_RC0_MSI_MSG_CNTL_DEFAULT 0x00000080 |
178 | #define cfgBIF_CFG_DEV0_RC0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 |
179 | #define cfgBIF_CFG_DEV0_RC0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 |
180 | #define cfgBIF_CFG_DEV0_RC0_MSI_MSG_DATA_DEFAULT 0x00000000 |
181 | #define cfgBIF_CFG_DEV0_RC0_MSI_MSG_DATA_64_DEFAULT 0x00000000 |
182 | #define cfgBIF_CFG_DEV0_RC0_SSID_CAP_LIST_DEFAULT 0x00000000 |
183 | #define cfgBIF_CFG_DEV0_RC0_SSID_CAP_DEFAULT 0x00000000 |
184 | #define cfgBIF_CFG_DEV0_RC0_MSI_MAP_CAP_LIST_DEFAULT 0x00000000 |
185 | #define cfgBIF_CFG_DEV0_RC0_MSI_MAP_CAP_DEFAULT 0x00000000 |
186 | #define cfgBIF_CFG_DEV0_RC0_MSI_MAP_ADDR_LO_DEFAULT 0x00000000 |
187 | #define cfgBIF_CFG_DEV0_RC0_MSI_MAP_ADDR_HI_DEFAULT 0x00000000 |
188 | #define cfgBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 |
189 | #define cfgBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 |
190 | #define cfgBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 |
191 | #define cfgBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 |
192 | #define cfgBIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000 |
193 | #define cfgBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000 |
194 | #define cfgBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000 |
195 | #define cfgBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000 |
196 | #define cfgBIF_CFG_DEV0_RC0_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000 |
197 | #define cfgBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000 |
198 | #define cfgBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe |
199 | #define cfgBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000000 |
200 | #define cfgBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000 |
201 | #define cfgBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000 |
202 | #define cfgBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000000 |
203 | #define cfgBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000 |
204 | #define cfgBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000 |
205 | #define cfgBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000 |
206 | #define cfgBIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 |
207 | #define cfgBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 |
208 | #define cfgBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 |
209 | #define cfgBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 |
210 | #define cfgBIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 |
211 | #define cfgBIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000 |
212 | #define cfgBIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 |
213 | #define cfgBIF_CFG_DEV0_RC0_PCIE_HDR_LOG0_DEFAULT 0x00000000 |
214 | #define cfgBIF_CFG_DEV0_RC0_PCIE_HDR_LOG1_DEFAULT 0x00000000 |
215 | #define cfgBIF_CFG_DEV0_RC0_PCIE_HDR_LOG2_DEFAULT 0x00000000 |
216 | #define cfgBIF_CFG_DEV0_RC0_PCIE_HDR_LOG3_DEFAULT 0x00000000 |
217 | #define cfgBIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD_DEFAULT 0x00000000 |
218 | #define cfgBIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS_DEFAULT 0x00000000 |
219 | #define cfgBIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID_DEFAULT 0x00000000 |
220 | #define cfgBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 |
221 | #define cfgBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 |
222 | #define cfgBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 |
223 | #define cfgBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 |
224 | #define cfgBIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a000000 |
225 | #define cfgBIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3_DEFAULT 0x00000000 |
226 | #define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000 |
227 | #define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
228 | #define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
229 | #define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
230 | #define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
231 | #define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
232 | #define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
233 | #define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
234 | #define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
235 | #define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
236 | #define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
237 | #define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
238 | #define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
239 | #define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
240 | #define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
241 | #define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
242 | #define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
243 | #define cfgBIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2f000000 |
244 | #define cfgBIF_CFG_DEV0_RC0_PCIE_ACS_CAP_DEFAULT 0x00000000 |
245 | #define cfgBIF_CFG_DEV0_RC0_PCIE_ACS_CNTL_DEFAULT 0x00000000 |
246 | |
247 | |
248 | // addressBlock: nbio_nbif0_bif_cfg_dev1_rc_bifcfgdecp |
249 | #define cfgBIF_CFG_DEV1_RC0_VENDOR_ID_DEFAULT 0x00000000 |
250 | #define cfgBIF_CFG_DEV1_RC0_DEVICE_ID_DEFAULT 0x00000000 |
251 | #define cfgBIF_CFG_DEV1_RC0_COMMAND_DEFAULT 0x00000000 |
252 | #define cfgBIF_CFG_DEV1_RC0_STATUS_DEFAULT 0x00000000 |
253 | #define cfgBIF_CFG_DEV1_RC0_REVISION_ID_DEFAULT 0x00000000 |
254 | #define cfgBIF_CFG_DEV1_RC0_PROG_INTERFACE_DEFAULT 0x00000000 |
255 | #define cfgBIF_CFG_DEV1_RC0_SUB_CLASS_DEFAULT 0x00000000 |
256 | #define cfgBIF_CFG_DEV1_RC0_BASE_CLASS_DEFAULT 0x00000000 |
257 | #define cfgBIF_CFG_DEV1_RC0_CACHE_LINE_DEFAULT 0x00000000 |
258 | #define cfgBIF_CFG_DEV1_RC0_LATENCY_DEFAULT 0x00000000 |
259 | #define 0x00000000 |
260 | #define cfgBIF_CFG_DEV1_RC0_BIST_DEFAULT 0x00000000 |
261 | #define cfgBIF_CFG_DEV1_RC0_BASE_ADDR_1_DEFAULT 0x00000000 |
262 | #define cfgBIF_CFG_DEV1_RC0_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 |
263 | #define cfgBIF_CFG_DEV1_RC0_IO_BASE_LIMIT_DEFAULT 0x00000000 |
264 | #define cfgBIF_CFG_DEV1_RC0_SECONDARY_STATUS_DEFAULT 0x00000000 |
265 | #define cfgBIF_CFG_DEV1_RC0_MEM_BASE_LIMIT_DEFAULT 0x00000000 |
266 | #define cfgBIF_CFG_DEV1_RC0_PREF_BASE_LIMIT_DEFAULT 0x00000000 |
267 | #define cfgBIF_CFG_DEV1_RC0_PREF_BASE_UPPER_DEFAULT 0x00000000 |
268 | #define cfgBIF_CFG_DEV1_RC0_PREF_LIMIT_UPPER_DEFAULT 0x00000000 |
269 | #define cfgBIF_CFG_DEV1_RC0_IO_BASE_LIMIT_HI_DEFAULT 0x00000000 |
270 | #define cfgBIF_CFG_DEV1_RC0_CAP_PTR_DEFAULT 0x00000000 |
271 | #define cfgBIF_CFG_DEV1_RC0_INTERRUPT_LINE_DEFAULT 0x000000ff |
272 | #define cfgBIF_CFG_DEV1_RC0_INTERRUPT_PIN_DEFAULT 0x00000001 |
273 | #define cfgBIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000 |
274 | #define cfgBIF_CFG_DEV1_RC0_EXT_BRIDGE_CNTL_DEFAULT 0x00000000 |
275 | #define cfgBIF_CFG_DEV1_RC0_PMI_CAP_LIST_DEFAULT 0x00000000 |
276 | #define cfgBIF_CFG_DEV1_RC0_PMI_CAP_DEFAULT 0x00000000 |
277 | #define cfgBIF_CFG_DEV1_RC0_PMI_STATUS_CNTL_DEFAULT 0x00000000 |
278 | #define cfgBIF_CFG_DEV1_RC0_PCIE_CAP_LIST_DEFAULT 0x0000a000 |
279 | #define cfgBIF_CFG_DEV1_RC0_PCIE_CAP_DEFAULT 0x00000042 |
280 | #define cfgBIF_CFG_DEV1_RC0_DEVICE_CAP_DEFAULT 0x00000000 |
281 | #define cfgBIF_CFG_DEV1_RC0_DEVICE_CNTL_DEFAULT 0x00002810 |
282 | #define cfgBIF_CFG_DEV1_RC0_DEVICE_STATUS_DEFAULT 0x00000000 |
283 | #define cfgBIF_CFG_DEV1_RC0_LINK_CAP_DEFAULT 0x00011c03 |
284 | #define cfgBIF_CFG_DEV1_RC0_LINK_CNTL_DEFAULT 0x00000000 |
285 | #define cfgBIF_CFG_DEV1_RC0_LINK_STATUS_DEFAULT 0x00002001 |
286 | #define cfgBIF_CFG_DEV1_RC0_SLOT_CAP_DEFAULT 0x00000000 |
287 | #define cfgBIF_CFG_DEV1_RC0_SLOT_CNTL_DEFAULT 0x00000000 |
288 | #define cfgBIF_CFG_DEV1_RC0_SLOT_STATUS_DEFAULT 0x00000000 |
289 | #define cfgBIF_CFG_DEV1_RC0_ROOT_CNTL_DEFAULT 0x00000000 |
290 | #define cfgBIF_CFG_DEV1_RC0_ROOT_CAP_DEFAULT 0x00000000 |
291 | #define cfgBIF_CFG_DEV1_RC0_ROOT_STATUS_DEFAULT 0x00000000 |
292 | #define cfgBIF_CFG_DEV1_RC0_DEVICE_CAP2_DEFAULT 0x00000000 |
293 | #define cfgBIF_CFG_DEV1_RC0_DEVICE_CNTL2_DEFAULT 0x00000000 |
294 | #define cfgBIF_CFG_DEV1_RC0_DEVICE_STATUS2_DEFAULT 0x00000000 |
295 | #define cfgBIF_CFG_DEV1_RC0_LINK_CAP2_DEFAULT 0x0000000e |
296 | #define cfgBIF_CFG_DEV1_RC0_LINK_CNTL2_DEFAULT 0x00000003 |
297 | #define cfgBIF_CFG_DEV1_RC0_LINK_STATUS2_DEFAULT 0x00000000 |
298 | #define cfgBIF_CFG_DEV1_RC0_SLOT_CAP2_DEFAULT 0x00000000 |
299 | #define cfgBIF_CFG_DEV1_RC0_SLOT_CNTL2_DEFAULT 0x00000000 |
300 | #define cfgBIF_CFG_DEV1_RC0_SLOT_STATUS2_DEFAULT 0x00000000 |
301 | #define cfgBIF_CFG_DEV1_RC0_MSI_CAP_LIST_DEFAULT 0x0000c000 |
302 | #define cfgBIF_CFG_DEV1_RC0_MSI_MSG_CNTL_DEFAULT 0x00000080 |
303 | #define cfgBIF_CFG_DEV1_RC0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 |
304 | #define cfgBIF_CFG_DEV1_RC0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 |
305 | #define cfgBIF_CFG_DEV1_RC0_MSI_MSG_DATA_DEFAULT 0x00000000 |
306 | #define cfgBIF_CFG_DEV1_RC0_MSI_MSG_DATA_64_DEFAULT 0x00000000 |
307 | #define cfgBIF_CFG_DEV1_RC0_SSID_CAP_LIST_DEFAULT 0x00000000 |
308 | #define cfgBIF_CFG_DEV1_RC0_SSID_CAP_DEFAULT 0x00000000 |
309 | #define cfgBIF_CFG_DEV1_RC0_MSI_MAP_CAP_LIST_DEFAULT 0x00000000 |
310 | #define cfgBIF_CFG_DEV1_RC0_MSI_MAP_CAP_DEFAULT 0x00000000 |
311 | #define cfgBIF_CFG_DEV1_RC0_MSI_MAP_ADDR_LO_DEFAULT 0x00000000 |
312 | #define cfgBIF_CFG_DEV1_RC0_MSI_MAP_ADDR_HI_DEFAULT 0x00000000 |
313 | #define cfgBIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 |
314 | #define cfgBIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 |
315 | #define cfgBIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 |
316 | #define cfgBIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 |
317 | #define cfgBIF_CFG_DEV1_RC0_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000 |
318 | #define cfgBIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000 |
319 | #define cfgBIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000 |
320 | #define cfgBIF_CFG_DEV1_RC0_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000 |
321 | #define cfgBIF_CFG_DEV1_RC0_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000 |
322 | #define cfgBIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000 |
323 | #define cfgBIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe |
324 | #define cfgBIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000000 |
325 | #define cfgBIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000 |
326 | #define cfgBIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000 |
327 | #define cfgBIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000000 |
328 | #define cfgBIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000 |
329 | #define cfgBIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000 |
330 | #define cfgBIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000 |
331 | #define cfgBIF_CFG_DEV1_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 |
332 | #define cfgBIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 |
333 | #define cfgBIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 |
334 | #define cfgBIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 |
335 | #define cfgBIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 |
336 | #define cfgBIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000 |
337 | #define cfgBIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 |
338 | #define cfgBIF_CFG_DEV1_RC0_PCIE_HDR_LOG0_DEFAULT 0x00000000 |
339 | #define cfgBIF_CFG_DEV1_RC0_PCIE_HDR_LOG1_DEFAULT 0x00000000 |
340 | #define cfgBIF_CFG_DEV1_RC0_PCIE_HDR_LOG2_DEFAULT 0x00000000 |
341 | #define cfgBIF_CFG_DEV1_RC0_PCIE_HDR_LOG3_DEFAULT 0x00000000 |
342 | #define cfgBIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_CMD_DEFAULT 0x00000000 |
343 | #define cfgBIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS_DEFAULT 0x00000000 |
344 | #define cfgBIF_CFG_DEV1_RC0_PCIE_ERR_SRC_ID_DEFAULT 0x00000000 |
345 | #define cfgBIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 |
346 | #define cfgBIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 |
347 | #define cfgBIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 |
348 | #define cfgBIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 |
349 | #define cfgBIF_CFG_DEV1_RC0_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a000000 |
350 | #define cfgBIF_CFG_DEV1_RC0_PCIE_LINK_CNTL3_DEFAULT 0x00000000 |
351 | #define cfgBIF_CFG_DEV1_RC0_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000 |
352 | #define cfgBIF_CFG_DEV1_RC0_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
353 | #define cfgBIF_CFG_DEV1_RC0_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
354 | #define cfgBIF_CFG_DEV1_RC0_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
355 | #define cfgBIF_CFG_DEV1_RC0_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
356 | #define cfgBIF_CFG_DEV1_RC0_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
357 | #define cfgBIF_CFG_DEV1_RC0_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
358 | #define cfgBIF_CFG_DEV1_RC0_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
359 | #define cfgBIF_CFG_DEV1_RC0_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
360 | #define cfgBIF_CFG_DEV1_RC0_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
361 | #define cfgBIF_CFG_DEV1_RC0_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
362 | #define cfgBIF_CFG_DEV1_RC0_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
363 | #define cfgBIF_CFG_DEV1_RC0_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
364 | #define cfgBIF_CFG_DEV1_RC0_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
365 | #define cfgBIF_CFG_DEV1_RC0_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
366 | #define cfgBIF_CFG_DEV1_RC0_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
367 | #define cfgBIF_CFG_DEV1_RC0_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
368 | #define cfgBIF_CFG_DEV1_RC0_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2f000000 |
369 | #define cfgBIF_CFG_DEV1_RC0_PCIE_ACS_CAP_DEFAULT 0x00000000 |
370 | #define cfgBIF_CFG_DEV1_RC0_PCIE_ACS_CNTL_DEFAULT 0x00000000 |
371 | |
372 | |
373 | // addressBlock: nbio_iohub_nb_pciedummy0_pciedummy_cfgdec |
374 | #define cfgNB_PCIEDUMMY0_0_DEVICE_VENDOR_ID_DEFAULT 0x00000000 |
375 | #define cfgNB_PCIEDUMMY0_0_STATUS_COMMAND_DEFAULT 0x00000000 |
376 | #define cfgNB_PCIEDUMMY0_0_CLASS_CODE_REVID_DEFAULT 0x00000000 |
377 | #define 0x00800000 |
378 | #define 0x00000080 |
379 | |
380 | |
381 | // addressBlock: nbio_iohub_nb_pciedummy1_pciedummy_cfgdec |
382 | #define cfgNB_PCIEDUMMY1_0_DEVICE_VENDOR_ID_DEFAULT 0x00000000 |
383 | #define cfgNB_PCIEDUMMY1_0_STATUS_COMMAND_DEFAULT 0x00000000 |
384 | #define cfgNB_PCIEDUMMY1_0_CLASS_CODE_REVID_DEFAULT 0x00000000 |
385 | #define 0x00800000 |
386 | #define 0x00000080 |
387 | |
388 | |
389 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_bifcfgdecp |
390 | #define cfgVENDOR_ID_DEFAULT 0x00000000 |
391 | #define cfgDEVICE_ID_DEFAULT 0x00000000 |
392 | #define cfgCOMMAND_DEFAULT 0x00000000 |
393 | #define cfgSTATUS_DEFAULT 0x00000000 |
394 | #define cfgREVISION_ID_DEFAULT 0x00000000 |
395 | #define cfgPROG_INTERFACE_DEFAULT 0x00000000 |
396 | #define cfgSUB_CLASS_DEFAULT 0x00000000 |
397 | #define cfgBASE_CLASS_DEFAULT 0x00000000 |
398 | #define cfgCACHE_LINE_DEFAULT 0x00000000 |
399 | #define cfgLATENCY_DEFAULT 0x00000000 |
400 | #define 0x00000000 |
401 | #define cfgBIST_DEFAULT 0x00000000 |
402 | #define cfgBASE_ADDR_1_DEFAULT 0x00000000 |
403 | #define cfgBASE_ADDR_2_DEFAULT 0x00000000 |
404 | #define cfgBASE_ADDR_3_DEFAULT 0x00000000 |
405 | #define cfgBASE_ADDR_4_DEFAULT 0x00000000 |
406 | #define cfgBASE_ADDR_5_DEFAULT 0x00000000 |
407 | #define cfgBASE_ADDR_6_DEFAULT 0x00000000 |
408 | #define cfgADAPTER_ID_DEFAULT 0x00000000 |
409 | #define cfgROM_BASE_ADDR_DEFAULT 0x00000000 |
410 | #define cfgCAP_PTR_DEFAULT 0x00000000 |
411 | #define cfgINTERRUPT_LINE_DEFAULT 0x000000ff |
412 | #define cfgINTERRUPT_PIN_DEFAULT 0x00000000 |
413 | #define cfgMIN_GRANT_DEFAULT 0x00000000 |
414 | #define cfgMAX_LATENCY_DEFAULT 0x00000000 |
415 | #define cfgVENDOR_CAP_LIST_DEFAULT 0x00000000 |
416 | #define cfgADAPTER_ID_W_DEFAULT 0x00000000 |
417 | #define cfgPMI_CAP_LIST_DEFAULT 0x00000000 |
418 | #define cfgPMI_CAP_DEFAULT 0x00000000 |
419 | #define cfgPMI_STATUS_CNTL_DEFAULT 0x00000000 |
420 | #define cfgPCIE_CAP_LIST_DEFAULT 0x0000a000 |
421 | #define cfgPCIE_CAP_DEFAULT 0x00000002 |
422 | #define cfgDEVICE_CAP_DEFAULT 0x10000000 |
423 | #define cfgDEVICE_CNTL_DEFAULT 0x00002810 |
424 | #define cfgDEVICE_STATUS_DEFAULT 0x00000000 |
425 | #define cfgLINK_CAP_DEFAULT 0x00011c03 |
426 | #define cfgLINK_CNTL_DEFAULT 0x00000000 |
427 | #define cfgLINK_STATUS_DEFAULT 0x00000001 |
428 | #define cfgDEVICE_CAP2_DEFAULT 0x00000000 |
429 | #define cfgDEVICE_CNTL2_DEFAULT 0x00000000 |
430 | #define cfgDEVICE_STATUS2_DEFAULT 0x00000000 |
431 | #define cfgLINK_CAP2_DEFAULT 0x0000000e |
432 | #define cfgLINK_CNTL2_DEFAULT 0x00000003 |
433 | #define cfgLINK_STATUS2_DEFAULT 0x00000000 |
434 | #define cfgSLOT_CAP2_DEFAULT 0x00000000 |
435 | #define cfgSLOT_CNTL2_DEFAULT 0x00000000 |
436 | #define cfgSLOT_STATUS2_DEFAULT 0x00000000 |
437 | #define cfgMSI_CAP_LIST_DEFAULT 0x0000c000 |
438 | #define cfgMSI_MSG_CNTL_DEFAULT 0x00000080 |
439 | #define cfgMSI_MSG_ADDR_LO_DEFAULT 0x00000000 |
440 | #define cfgMSI_MSG_ADDR_HI_DEFAULT 0x00000000 |
441 | #define cfgMSI_MSG_DATA_DEFAULT 0x00000000 |
442 | #define cfgMSI_MASK_DEFAULT 0x00000000 |
443 | #define cfgMSI_MSG_DATA_64_DEFAULT 0x00000000 |
444 | #define cfgMSI_MASK_64_DEFAULT 0x00000000 |
445 | #define cfgMSI_PENDING_DEFAULT 0x00000000 |
446 | #define cfgMSI_PENDING_64_DEFAULT 0x00000000 |
447 | #define cfgMSIX_CAP_LIST_DEFAULT 0x00000000 |
448 | #define cfgMSIX_MSG_CNTL_DEFAULT 0x00000000 |
449 | #define cfgMSIX_TABLE_DEFAULT 0x00000000 |
450 | #define cfgMSIX_PBA_DEFAULT 0x00000000 |
451 | #define cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 |
452 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 |
453 | #define cfgPCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 |
454 | #define cfgPCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 |
455 | #define cfgPCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000 |
456 | #define cfgPCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000 |
457 | #define cfgPCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000 |
458 | #define cfgPCIE_PORT_VC_CNTL_DEFAULT 0x00000000 |
459 | #define cfgPCIE_PORT_VC_STATUS_DEFAULT 0x00000000 |
460 | #define cfgPCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000 |
461 | #define cfgPCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe |
462 | #define cfgPCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000000 |
463 | #define cfgPCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000 |
464 | #define cfgPCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000 |
465 | #define cfgPCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000000 |
466 | #define cfgPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000 |
467 | #define cfgPCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000 |
468 | #define cfgPCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000 |
469 | #define cfgPCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 |
470 | #define cfgPCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 |
471 | #define cfgPCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 |
472 | #define cfgPCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 |
473 | #define cfgPCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 |
474 | #define cfgPCIE_CORR_ERR_MASK_DEFAULT 0x00002000 |
475 | #define cfgPCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 |
476 | #define cfgPCIE_HDR_LOG0_DEFAULT 0x00000000 |
477 | #define cfgPCIE_HDR_LOG1_DEFAULT 0x00000000 |
478 | #define cfgPCIE_HDR_LOG2_DEFAULT 0x00000000 |
479 | #define cfgPCIE_HDR_LOG3_DEFAULT 0x00000000 |
480 | #define cfgPCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 |
481 | #define cfgPCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 |
482 | #define cfgPCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 |
483 | #define cfgPCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 |
484 | #define cfgPCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000 |
485 | #define cfgPCIE_BAR1_CAP_DEFAULT 0x00000000 |
486 | #define cfgPCIE_BAR1_CNTL_DEFAULT 0x00000020 |
487 | #define cfgPCIE_BAR2_CAP_DEFAULT 0x00000000 |
488 | #define cfgPCIE_BAR2_CNTL_DEFAULT 0x00000000 |
489 | #define cfgPCIE_BAR3_CAP_DEFAULT 0x00000000 |
490 | #define cfgPCIE_BAR3_CNTL_DEFAULT 0x00000000 |
491 | #define cfgPCIE_BAR4_CAP_DEFAULT 0x00000000 |
492 | #define cfgPCIE_BAR4_CNTL_DEFAULT 0x00000000 |
493 | #define cfgPCIE_BAR5_CAP_DEFAULT 0x00000000 |
494 | #define cfgPCIE_BAR5_CNTL_DEFAULT 0x00000000 |
495 | #define cfgPCIE_BAR6_CAP_DEFAULT 0x00000000 |
496 | #define cfgPCIE_BAR6_CNTL_DEFAULT 0x00000000 |
497 | #define cfgPCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000 |
498 | #define cfgPCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000 |
499 | #define cfgPCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000 |
500 | #define cfgPCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000 |
501 | #define cfgPCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000 |
502 | #define cfgPCIE_DPA_CAP_DEFAULT 0x00000000 |
503 | #define cfgPCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000 |
504 | #define cfgPCIE_DPA_STATUS_DEFAULT 0x00000100 |
505 | #define cfgPCIE_DPA_CNTL_DEFAULT 0x00000000 |
506 | #define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000 |
507 | #define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000 |
508 | #define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000 |
509 | #define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000 |
510 | #define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000 |
511 | #define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000 |
512 | #define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000 |
513 | #define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000 |
514 | #define cfgPCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a010019 |
515 | #define cfgPCIE_LINK_CNTL3_DEFAULT 0x00000000 |
516 | #define cfgPCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000 |
517 | #define cfgPCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
518 | #define cfgPCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
519 | #define cfgPCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
520 | #define cfgPCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
521 | #define cfgPCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
522 | #define cfgPCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
523 | #define cfgPCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
524 | #define cfgPCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
525 | #define cfgPCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
526 | #define cfgPCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
527 | #define cfgPCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
528 | #define cfgPCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
529 | #define cfgPCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
530 | #define cfgPCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
531 | #define cfgPCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
532 | #define cfgPCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
533 | #define cfgPCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000 |
534 | #define cfgPCIE_ACS_CAP_DEFAULT 0x00000000 |
535 | #define cfgPCIE_ACS_CNTL_DEFAULT 0x00000000 |
536 | #define cfgPCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 |
537 | #define cfgPCIE_ATS_CAP_DEFAULT 0x00000000 |
538 | #define cfgPCIE_ATS_CNTL_DEFAULT 0x00000000 |
539 | #define cfgPCIE_PAGE_REQ_ENH_CAP_LIST_DEFAULT 0x2d000000 |
540 | #define cfgPCIE_PAGE_REQ_CNTL_DEFAULT 0x00000000 |
541 | #define cfgPCIE_PAGE_REQ_STATUS_DEFAULT 0x00000000 |
542 | #define cfgPCIE_OUTSTAND_PAGE_REQ_CAPACITY_DEFAULT 0x00000000 |
543 | #define cfgPCIE_OUTSTAND_PAGE_REQ_ALLOC_DEFAULT 0x00000000 |
544 | #define cfgPCIE_PASID_ENH_CAP_LIST_DEFAULT 0x2e000000 |
545 | #define cfgPCIE_PASID_CAP_DEFAULT 0x00000000 |
546 | #define cfgPCIE_PASID_CNTL_DEFAULT 0x00000000 |
547 | #define cfgPCIE_TPH_REQR_ENH_CAP_LIST_DEFAULT 0x2f000000 |
548 | #define cfgPCIE_TPH_REQR_CAP_DEFAULT 0x00000000 |
549 | #define cfgPCIE_TPH_REQR_CNTL_DEFAULT 0x00000000 |
550 | #define cfgPCIE_MC_ENH_CAP_LIST_DEFAULT 0x32000000 |
551 | #define cfgPCIE_MC_CAP_DEFAULT 0x00000000 |
552 | #define cfgPCIE_MC_CNTL_DEFAULT 0x00000000 |
553 | #define cfgPCIE_MC_ADDR0_DEFAULT 0x00000000 |
554 | #define cfgPCIE_MC_ADDR1_DEFAULT 0x00000000 |
555 | #define cfgPCIE_MC_RCV0_DEFAULT 0x00000000 |
556 | #define cfgPCIE_MC_RCV1_DEFAULT 0x00000000 |
557 | #define cfgPCIE_MC_BLOCK_ALL0_DEFAULT 0x00000000 |
558 | #define cfgPCIE_MC_BLOCK_ALL1_DEFAULT 0x00000000 |
559 | #define cfgPCIE_MC_BLOCK_UNTRANSLATED_0_DEFAULT 0x00000000 |
560 | #define cfgPCIE_MC_BLOCK_UNTRANSLATED_1_DEFAULT 0x00000000 |
561 | #define cfgPCIE_LTR_ENH_CAP_LIST_DEFAULT 0x32800000 |
562 | #define cfgPCIE_LTR_CAP_DEFAULT 0x00000000 |
563 | #define cfgPCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000 |
564 | #define cfgPCIE_ARI_CAP_DEFAULT 0x00000000 |
565 | #define cfgPCIE_ARI_CNTL_DEFAULT 0x00000000 |
566 | #define cfgPCIE_SRIOV_ENH_CAP_LIST_DEFAULT 0x00000000 |
567 | #define cfgPCIE_SRIOV_CAP_DEFAULT 0x00000000 |
568 | #define cfgPCIE_SRIOV_CONTROL_DEFAULT 0x00000000 |
569 | #define cfgPCIE_SRIOV_STATUS_DEFAULT 0x00000000 |
570 | #define cfgPCIE_SRIOV_INITIAL_VFS_DEFAULT 0x00000000 |
571 | #define cfgPCIE_SRIOV_TOTAL_VFS_DEFAULT 0x00000000 |
572 | #define cfgPCIE_SRIOV_NUM_VFS_DEFAULT 0x00000000 |
573 | #define cfgPCIE_SRIOV_FUNC_DEP_LINK_DEFAULT 0x00000000 |
574 | #define cfgPCIE_SRIOV_FIRST_VF_OFFSET_DEFAULT 0x00000000 |
575 | #define cfgPCIE_SRIOV_VF_STRIDE_DEFAULT 0x00000000 |
576 | #define cfgPCIE_SRIOV_VF_DEVICE_ID_DEFAULT 0x00000000 |
577 | #define cfgPCIE_SRIOV_SUPPORTED_PAGE_SIZE_DEFAULT 0x00000000 |
578 | #define cfgPCIE_SRIOV_SYSTEM_PAGE_SIZE_DEFAULT 0x00000001 |
579 | #define cfgPCIE_SRIOV_VF_BASE_ADDR_0_DEFAULT 0x00000000 |
580 | #define cfgPCIE_SRIOV_VF_BASE_ADDR_1_DEFAULT 0x00000000 |
581 | #define cfgPCIE_SRIOV_VF_BASE_ADDR_2_DEFAULT 0x00000000 |
582 | #define cfgPCIE_SRIOV_VF_BASE_ADDR_3_DEFAULT 0x00000000 |
583 | #define cfgPCIE_SRIOV_VF_BASE_ADDR_4_DEFAULT 0x00000000 |
584 | #define cfgPCIE_SRIOV_VF_BASE_ADDR_5_DEFAULT 0x00000000 |
585 | #define cfgPCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_DEFAULT 0x00000000 |
586 | #define cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_DEFAULT 0x00000000 |
587 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_DEFAULT 0x00000000 |
588 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW_DEFAULT 0x00000000 |
589 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_DEFAULT 0x00000000 |
590 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_DEFAULT 0x00000000 |
591 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_DEFAULT 0x00000000 |
592 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0_DEFAULT 0x00000000 |
593 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_DEFAULT 0x00000000 |
594 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2_DEFAULT 0x00000000 |
595 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT_DEFAULT 0x00000000 |
596 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB_DEFAULT 0x00000000 |
597 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS_DEFAULT 0x00000000 |
598 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB_DEFAULT 0x00000000 |
599 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB_DEFAULT 0x00000000 |
600 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB_DEFAULT 0x00000000 |
601 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB_DEFAULT 0x00000000 |
602 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB_DEFAULT 0x00000000 |
603 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB_DEFAULT 0x00000000 |
604 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB_DEFAULT 0x00000000 |
605 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB_DEFAULT 0x00000000 |
606 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB_DEFAULT 0x00000000 |
607 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB_DEFAULT 0x00000000 |
608 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB_DEFAULT 0x00000000 |
609 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB_DEFAULT 0x00000000 |
610 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB_DEFAULT 0x00000000 |
611 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB_DEFAULT 0x00000000 |
612 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB_DEFAULT 0x00000000 |
613 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB_DEFAULT 0x00000000 |
614 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0_DEFAULT 0x00000000 |
615 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1_DEFAULT 0x00000000 |
616 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2_DEFAULT 0x00000000 |
617 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3_DEFAULT 0x00000000 |
618 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4_DEFAULT 0x00000000 |
619 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5_DEFAULT 0x00000000 |
620 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6_DEFAULT 0x00000000 |
621 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7_DEFAULT 0x00000000 |
622 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8_DEFAULT 0x00000000 |
623 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0_DEFAULT 0x00000000 |
624 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1_DEFAULT 0x00000000 |
625 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2_DEFAULT 0x00000000 |
626 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3_DEFAULT 0x00000000 |
627 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4_DEFAULT 0x00000000 |
628 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5_DEFAULT 0x00000000 |
629 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6_DEFAULT 0x00000000 |
630 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7_DEFAULT 0x00000000 |
631 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8_DEFAULT 0x00000000 |
632 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0_DEFAULT 0x00000000 |
633 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1_DEFAULT 0x00000000 |
634 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2_DEFAULT 0x00000000 |
635 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3_DEFAULT 0x00000000 |
636 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4_DEFAULT 0x00000000 |
637 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5_DEFAULT 0x00000000 |
638 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6_DEFAULT 0x00000000 |
639 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7_DEFAULT 0x00000000 |
640 | #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8_DEFAULT 0x00000000 |
641 | |
642 | |
643 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf1_bifcfgdecp |
644 | #define cfgBIF_CFG_DEV0_EPF1_0_VENDOR_ID_DEFAULT 0x00000000 |
645 | #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_ID_DEFAULT 0x00000000 |
646 | #define cfgBIF_CFG_DEV0_EPF1_0_COMMAND_DEFAULT 0x00000000 |
647 | #define cfgBIF_CFG_DEV0_EPF1_0_STATUS_DEFAULT 0x00000000 |
648 | #define cfgBIF_CFG_DEV0_EPF1_0_REVISION_ID_DEFAULT 0x00000000 |
649 | #define cfgBIF_CFG_DEV0_EPF1_0_PROG_INTERFACE_DEFAULT 0x00000000 |
650 | #define cfgBIF_CFG_DEV0_EPF1_0_SUB_CLASS_DEFAULT 0x00000000 |
651 | #define cfgBIF_CFG_DEV0_EPF1_0_BASE_CLASS_DEFAULT 0x00000000 |
652 | #define cfgBIF_CFG_DEV0_EPF1_0_CACHE_LINE_DEFAULT 0x00000000 |
653 | #define cfgBIF_CFG_DEV0_EPF1_0_LATENCY_DEFAULT 0x00000000 |
654 | #define 0x00000000 |
655 | #define cfgBIF_CFG_DEV0_EPF1_0_BIST_DEFAULT 0x00000000 |
656 | #define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_1_DEFAULT 0x00000000 |
657 | #define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_2_DEFAULT 0x00000000 |
658 | #define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_3_DEFAULT 0x00000000 |
659 | #define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_4_DEFAULT 0x00000000 |
660 | #define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_5_DEFAULT 0x00000000 |
661 | #define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_6_DEFAULT 0x00000000 |
662 | #define cfgBIF_CFG_DEV0_EPF1_0_ADAPTER_ID_DEFAULT 0x00000000 |
663 | #define cfgBIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR_DEFAULT 0x00000000 |
664 | #define cfgBIF_CFG_DEV0_EPF1_0_CAP_PTR_DEFAULT 0x00000000 |
665 | #define cfgBIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE_DEFAULT 0x000000ff |
666 | #define cfgBIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN_DEFAULT 0x00000000 |
667 | #define cfgBIF_CFG_DEV0_EPF1_0_MIN_GRANT_DEFAULT 0x00000000 |
668 | #define cfgBIF_CFG_DEV0_EPF1_0_MAX_LATENCY_DEFAULT 0x00000000 |
669 | #define cfgBIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST_DEFAULT 0x00000000 |
670 | #define cfgBIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W_DEFAULT 0x00000000 |
671 | #define cfgBIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST_DEFAULT 0x00000000 |
672 | #define cfgBIF_CFG_DEV0_EPF1_0_PMI_CAP_DEFAULT 0x00000000 |
673 | #define cfgBIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL_DEFAULT 0x00000000 |
674 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST_DEFAULT 0x0000a000 |
675 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CAP_DEFAULT 0x00000002 |
676 | #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CAP_DEFAULT 0x10000000 |
677 | #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CNTL_DEFAULT 0x00002810 |
678 | #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_STATUS_DEFAULT 0x00000000 |
679 | #define cfgBIF_CFG_DEV0_EPF1_0_LINK_CAP_DEFAULT 0x00011c03 |
680 | #define cfgBIF_CFG_DEV0_EPF1_0_LINK_CNTL_DEFAULT 0x00000000 |
681 | #define cfgBIF_CFG_DEV0_EPF1_0_LINK_STATUS_DEFAULT 0x00000001 |
682 | #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CAP2_DEFAULT 0x00000000 |
683 | #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2_DEFAULT 0x00000000 |
684 | #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2_DEFAULT 0x00000000 |
685 | #define cfgBIF_CFG_DEV0_EPF1_0_LINK_CAP2_DEFAULT 0x0000000e |
686 | #define cfgBIF_CFG_DEV0_EPF1_0_LINK_CNTL2_DEFAULT 0x00000003 |
687 | #define cfgBIF_CFG_DEV0_EPF1_0_LINK_STATUS2_DEFAULT 0x00000000 |
688 | #define cfgBIF_CFG_DEV0_EPF1_0_SLOT_CAP2_DEFAULT 0x00000000 |
689 | #define cfgBIF_CFG_DEV0_EPF1_0_SLOT_CNTL2_DEFAULT 0x00000000 |
690 | #define cfgBIF_CFG_DEV0_EPF1_0_SLOT_STATUS2_DEFAULT 0x00000000 |
691 | #define cfgBIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST_DEFAULT 0x0000c000 |
692 | #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL_DEFAULT 0x00000080 |
693 | #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 |
694 | #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 |
695 | #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_DEFAULT 0x00000000 |
696 | #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MASK_DEFAULT 0x00000000 |
697 | #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64_DEFAULT 0x00000000 |
698 | #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MASK_64_DEFAULT 0x00000000 |
699 | #define cfgBIF_CFG_DEV0_EPF1_0_MSI_PENDING_DEFAULT 0x00000000 |
700 | #define cfgBIF_CFG_DEV0_EPF1_0_MSI_PENDING_64_DEFAULT 0x00000000 |
701 | #define cfgBIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST_DEFAULT 0x00000000 |
702 | #define cfgBIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL_DEFAULT 0x00000000 |
703 | #define cfgBIF_CFG_DEV0_EPF1_0_MSIX_TABLE_DEFAULT 0x00000000 |
704 | #define cfgBIF_CFG_DEV0_EPF1_0_MSIX_PBA_DEFAULT 0x00000000 |
705 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 |
706 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 |
707 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 |
708 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 |
709 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000 |
710 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000 |
711 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000 |
712 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000 |
713 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000 |
714 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000 |
715 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe |
716 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000000 |
717 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000 |
718 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000 |
719 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000000 |
720 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000 |
721 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000 |
722 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000 |
723 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 |
724 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 |
725 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 |
726 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 |
727 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 |
728 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000 |
729 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 |
730 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0_DEFAULT 0x00000000 |
731 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1_DEFAULT 0x00000000 |
732 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2_DEFAULT 0x00000000 |
733 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3_DEFAULT 0x00000000 |
734 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 |
735 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 |
736 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 |
737 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 |
738 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000 |
739 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP_DEFAULT 0x00000000 |
740 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL_DEFAULT 0x00000020 |
741 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP_DEFAULT 0x00000000 |
742 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL_DEFAULT 0x00000000 |
743 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP_DEFAULT 0x00000000 |
744 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL_DEFAULT 0x00000000 |
745 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP_DEFAULT 0x00000000 |
746 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL_DEFAULT 0x00000000 |
747 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP_DEFAULT 0x00000000 |
748 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL_DEFAULT 0x00000000 |
749 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP_DEFAULT 0x00000000 |
750 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL_DEFAULT 0x00000000 |
751 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000 |
752 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000 |
753 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000 |
754 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000 |
755 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000 |
756 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP_DEFAULT 0x00000000 |
757 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000 |
758 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS_DEFAULT 0x00000100 |
759 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL_DEFAULT 0x00000000 |
760 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000 |
761 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000 |
762 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000 |
763 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000 |
764 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000 |
765 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000 |
766 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000 |
767 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000 |
768 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a010019 |
769 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3_DEFAULT 0x00000000 |
770 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000 |
771 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
772 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
773 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
774 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
775 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
776 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
777 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
778 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
779 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
780 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
781 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
782 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
783 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
784 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
785 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
786 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
787 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000 |
788 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP_DEFAULT 0x00000000 |
789 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL_DEFAULT 0x00000000 |
790 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 |
791 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP_DEFAULT 0x00000000 |
792 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ATS_CNTL_DEFAULT 0x00000000 |
793 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST_DEFAULT 0x2d000000 |
794 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_CNTL_DEFAULT 0x00000000 |
795 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS_DEFAULT 0x00000000 |
796 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY_DEFAULT 0x00000000 |
797 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC_DEFAULT 0x00000000 |
798 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST_DEFAULT 0x2e000000 |
799 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP_DEFAULT 0x00000000 |
800 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL_DEFAULT 0x00000000 |
801 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST_DEFAULT 0x2f000000 |
802 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP_DEFAULT 0x00000000 |
803 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CNTL_DEFAULT 0x00000000 |
804 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST_DEFAULT 0x32000000 |
805 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP_DEFAULT 0x00000000 |
806 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL_DEFAULT 0x00000000 |
807 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0_DEFAULT 0x00000000 |
808 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR1_DEFAULT 0x00000000 |
809 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV0_DEFAULT 0x00000000 |
810 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV1_DEFAULT 0x00000000 |
811 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL0_DEFAULT 0x00000000 |
812 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL1_DEFAULT 0x00000000 |
813 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_0_DEFAULT 0x00000000 |
814 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_1_DEFAULT 0x00000000 |
815 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST_DEFAULT 0x32800000 |
816 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP_DEFAULT 0x00000000 |
817 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000 |
818 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP_DEFAULT 0x00000000 |
819 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL_DEFAULT 0x00000000 |
820 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST_DEFAULT 0x00000000 |
821 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP_DEFAULT 0x00000000 |
822 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL_DEFAULT 0x00000000 |
823 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_STATUS_DEFAULT 0x00000000 |
824 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_INITIAL_VFS_DEFAULT 0x00000000 |
825 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_TOTAL_VFS_DEFAULT 0x00000000 |
826 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_NUM_VFS_DEFAULT 0x00000000 |
827 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FUNC_DEP_LINK_DEFAULT 0x00000000 |
828 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FIRST_VF_OFFSET_DEFAULT 0x00000000 |
829 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_STRIDE_DEFAULT 0x00000000 |
830 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_DEVICE_ID_DEFAULT 0x00000000 |
831 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE_DEFAULT 0x00000000 |
832 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE_DEFAULT 0x00000001 |
833 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_0_DEFAULT 0x00000000 |
834 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_1_DEFAULT 0x00000000 |
835 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_2_DEFAULT 0x00000000 |
836 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_3_DEFAULT 0x00000000 |
837 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_4_DEFAULT 0x00000000 |
838 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_5_DEFAULT 0x00000000 |
839 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_DEFAULT 0x00000000 |
840 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_DEFAULT 0x00000000 |
841 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_DEFAULT 0x00000000 |
842 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW_DEFAULT 0x00000000 |
843 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_DEFAULT 0x00000000 |
844 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_DEFAULT 0x00000000 |
845 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_DEFAULT 0x00000000 |
846 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0_DEFAULT 0x00000000 |
847 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_DEFAULT 0x00000000 |
848 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2_DEFAULT 0x00000000 |
849 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT_DEFAULT 0x00000000 |
850 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB_DEFAULT 0x00000000 |
851 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS_DEFAULT 0x00000000 |
852 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB_DEFAULT 0x00000000 |
853 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB_DEFAULT 0x00000000 |
854 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB_DEFAULT 0x00000000 |
855 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB_DEFAULT 0x00000000 |
856 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB_DEFAULT 0x00000000 |
857 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB_DEFAULT 0x00000000 |
858 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB_DEFAULT 0x00000000 |
859 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB_DEFAULT 0x00000000 |
860 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB_DEFAULT 0x00000000 |
861 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB_DEFAULT 0x00000000 |
862 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB_DEFAULT 0x00000000 |
863 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB_DEFAULT 0x00000000 |
864 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB_DEFAULT 0x00000000 |
865 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB_DEFAULT 0x00000000 |
866 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB_DEFAULT 0x00000000 |
867 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB_DEFAULT 0x00000000 |
868 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0_DEFAULT 0x00000000 |
869 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1_DEFAULT 0x00000000 |
870 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2_DEFAULT 0x00000000 |
871 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3_DEFAULT 0x00000000 |
872 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4_DEFAULT 0x00000000 |
873 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5_DEFAULT 0x00000000 |
874 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6_DEFAULT 0x00000000 |
875 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7_DEFAULT 0x00000000 |
876 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8_DEFAULT 0x00000000 |
877 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0_DEFAULT 0x00000000 |
878 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1_DEFAULT 0x00000000 |
879 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2_DEFAULT 0x00000000 |
880 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3_DEFAULT 0x00000000 |
881 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4_DEFAULT 0x00000000 |
882 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5_DEFAULT 0x00000000 |
883 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6_DEFAULT 0x00000000 |
884 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7_DEFAULT 0x00000000 |
885 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8_DEFAULT 0x00000000 |
886 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0_DEFAULT 0x00000000 |
887 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1_DEFAULT 0x00000000 |
888 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2_DEFAULT 0x00000000 |
889 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3_DEFAULT 0x00000000 |
890 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4_DEFAULT 0x00000000 |
891 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5_DEFAULT 0x00000000 |
892 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6_DEFAULT 0x00000000 |
893 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7_DEFAULT 0x00000000 |
894 | #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8_DEFAULT 0x00000000 |
895 | |
896 | |
897 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf2_bifcfgdecp |
898 | #define cfgBIF_CFG_DEV0_EPF2_0_VENDOR_ID_DEFAULT 0x00000000 |
899 | #define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_ID_DEFAULT 0x00000000 |
900 | #define cfgBIF_CFG_DEV0_EPF2_0_COMMAND_DEFAULT 0x00000000 |
901 | #define cfgBIF_CFG_DEV0_EPF2_0_STATUS_DEFAULT 0x00000000 |
902 | #define cfgBIF_CFG_DEV0_EPF2_0_REVISION_ID_DEFAULT 0x00000000 |
903 | #define cfgBIF_CFG_DEV0_EPF2_0_PROG_INTERFACE_DEFAULT 0x00000000 |
904 | #define cfgBIF_CFG_DEV0_EPF2_0_SUB_CLASS_DEFAULT 0x00000000 |
905 | #define cfgBIF_CFG_DEV0_EPF2_0_BASE_CLASS_DEFAULT 0x00000000 |
906 | #define cfgBIF_CFG_DEV0_EPF2_0_CACHE_LINE_DEFAULT 0x00000000 |
907 | #define cfgBIF_CFG_DEV0_EPF2_0_LATENCY_DEFAULT 0x00000000 |
908 | #define 0x00000000 |
909 | #define cfgBIF_CFG_DEV0_EPF2_0_BIST_DEFAULT 0x00000000 |
910 | #define cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_1_DEFAULT 0x00000000 |
911 | #define cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_2_DEFAULT 0x00000000 |
912 | #define cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_3_DEFAULT 0x00000000 |
913 | #define cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_4_DEFAULT 0x00000000 |
914 | #define cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_5_DEFAULT 0x00000000 |
915 | #define cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_6_DEFAULT 0x00000000 |
916 | #define cfgBIF_CFG_DEV0_EPF2_0_ADAPTER_ID_DEFAULT 0x00000000 |
917 | #define cfgBIF_CFG_DEV0_EPF2_0_ROM_BASE_ADDR_DEFAULT 0x00000000 |
918 | #define cfgBIF_CFG_DEV0_EPF2_0_CAP_PTR_DEFAULT 0x00000000 |
919 | #define cfgBIF_CFG_DEV0_EPF2_0_INTERRUPT_LINE_DEFAULT 0x00000000 |
920 | #define cfgBIF_CFG_DEV0_EPF2_0_INTERRUPT_PIN_DEFAULT 0x00000000 |
921 | #define cfgBIF_CFG_DEV0_EPF2_0_MIN_GRANT_DEFAULT 0x00000000 |
922 | #define cfgBIF_CFG_DEV0_EPF2_0_MAX_LATENCY_DEFAULT 0x00000000 |
923 | #define cfgBIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST_DEFAULT 0x00000000 |
924 | #define cfgBIF_CFG_DEV0_EPF2_0_ADAPTER_ID_W_DEFAULT 0x00000000 |
925 | #define cfgBIF_CFG_DEV0_EPF2_0_PMI_CAP_LIST_DEFAULT 0x00000000 |
926 | #define cfgBIF_CFG_DEV0_EPF2_0_PMI_CAP_DEFAULT 0x00000000 |
927 | #define cfgBIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL_DEFAULT 0x00000000 |
928 | #define cfgBIF_CFG_DEV0_EPF2_0_SBRN_DEFAULT 0x00000000 |
929 | #define cfgBIF_CFG_DEV0_EPF2_0_FLADJ_DEFAULT 0x00000020 |
930 | #define cfgBIF_CFG_DEV0_EPF2_0_DBESL_DBESLD_DEFAULT 0x00000000 |
931 | #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_CAP_LIST_DEFAULT 0x0000a000 |
932 | #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_CAP_DEFAULT 0x00000002 |
933 | #define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_CAP_DEFAULT 0x10000000 |
934 | #define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_CNTL_DEFAULT 0x00002810 |
935 | #define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_STATUS_DEFAULT 0x00000000 |
936 | #define cfgBIF_CFG_DEV0_EPF2_0_LINK_CAP_DEFAULT 0x00011c03 |
937 | #define cfgBIF_CFG_DEV0_EPF2_0_LINK_CNTL_DEFAULT 0x00000000 |
938 | #define cfgBIF_CFG_DEV0_EPF2_0_LINK_STATUS_DEFAULT 0x00000001 |
939 | #define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_CAP2_DEFAULT 0x00000000 |
940 | #define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2_DEFAULT 0x00000000 |
941 | #define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_STATUS2_DEFAULT 0x00000000 |
942 | #define cfgBIF_CFG_DEV0_EPF2_0_LINK_CAP2_DEFAULT 0x0000000e |
943 | #define cfgBIF_CFG_DEV0_EPF2_0_LINK_CNTL2_DEFAULT 0x00000003 |
944 | #define cfgBIF_CFG_DEV0_EPF2_0_LINK_STATUS2_DEFAULT 0x00000000 |
945 | #define cfgBIF_CFG_DEV0_EPF2_0_SLOT_CAP2_DEFAULT 0x00000000 |
946 | #define cfgBIF_CFG_DEV0_EPF2_0_SLOT_CNTL2_DEFAULT 0x00000000 |
947 | #define cfgBIF_CFG_DEV0_EPF2_0_SLOT_STATUS2_DEFAULT 0x00000000 |
948 | #define cfgBIF_CFG_DEV0_EPF2_0_MSI_CAP_LIST_DEFAULT 0x0000c000 |
949 | #define cfgBIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL_DEFAULT 0x00000080 |
950 | #define cfgBIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 |
951 | #define cfgBIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 |
952 | #define cfgBIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA_DEFAULT 0x00000000 |
953 | #define cfgBIF_CFG_DEV0_EPF2_0_MSI_MASK_DEFAULT 0x00000000 |
954 | #define cfgBIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA_64_DEFAULT 0x00000000 |
955 | #define cfgBIF_CFG_DEV0_EPF2_0_MSI_MASK_64_DEFAULT 0x00000000 |
956 | #define cfgBIF_CFG_DEV0_EPF2_0_MSI_PENDING_DEFAULT 0x00000000 |
957 | #define cfgBIF_CFG_DEV0_EPF2_0_MSI_PENDING_64_DEFAULT 0x00000000 |
958 | #define cfgBIF_CFG_DEV0_EPF2_0_MSIX_CAP_LIST_DEFAULT 0x00000000 |
959 | #define cfgBIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL_DEFAULT 0x00000000 |
960 | #define cfgBIF_CFG_DEV0_EPF2_0_MSIX_TABLE_DEFAULT 0x00000000 |
961 | #define cfgBIF_CFG_DEV0_EPF2_0_MSIX_PBA_DEFAULT 0x00000000 |
962 | #define cfgBIF_CFG_DEV0_EPF2_0_SATA_CAP_0_DEFAULT 0x00000000 |
963 | #define cfgBIF_CFG_DEV0_EPF2_0_SATA_CAP_1_DEFAULT 0x00000000 |
964 | #define cfgBIF_CFG_DEV0_EPF2_0_SATA_IDP_INDEX_DEFAULT 0x00000000 |
965 | #define cfgBIF_CFG_DEV0_EPF2_0_SATA_IDP_DATA_DEFAULT 0x00000000 |
966 | #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 |
967 | #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 |
968 | #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 |
969 | #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 |
970 | #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 |
971 | #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 |
972 | #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 |
973 | #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 |
974 | #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 |
975 | #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000 |
976 | #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 |
977 | #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG0_DEFAULT 0x00000000 |
978 | #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG1_DEFAULT 0x00000000 |
979 | #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG2_DEFAULT 0x00000000 |
980 | #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG3_DEFAULT 0x00000000 |
981 | #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 |
982 | #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 |
983 | #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 |
984 | #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 |
985 | #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000 |
986 | #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CAP_DEFAULT 0x00000000 |
987 | #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL_DEFAULT 0x00000020 |
988 | #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CAP_DEFAULT 0x00000000 |
989 | #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL_DEFAULT 0x00000000 |
990 | #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CAP_DEFAULT 0x00000000 |
991 | #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL_DEFAULT 0x00000000 |
992 | #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CAP_DEFAULT 0x00000000 |
993 | #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL_DEFAULT 0x00000000 |
994 | #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CAP_DEFAULT 0x00000000 |
995 | #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL_DEFAULT 0x00000000 |
996 | #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CAP_DEFAULT 0x00000000 |
997 | #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL_DEFAULT 0x00000000 |
998 | #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000 |
999 | #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000 |
1000 | #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000 |
1001 | #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000 |
1002 | #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000 |
1003 | #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP_DEFAULT 0x00000000 |
1004 | #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000 |
1005 | #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_STATUS_DEFAULT 0x00000100 |
1006 | #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_CNTL_DEFAULT 0x00000000 |
1007 | #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000 |
1008 | #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000 |
1009 | #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000 |
1010 | #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000 |
1011 | #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000 |
1012 | #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000 |
1013 | #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000 |
1014 | #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000 |
1015 | #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000 |
1016 | #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP_DEFAULT 0x00000000 |
1017 | #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL_DEFAULT 0x00000000 |
1018 | #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000 |
1019 | #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP_DEFAULT 0x00000000 |
1020 | #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL_DEFAULT 0x00000000 |
1021 | |
1022 | |
1023 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf3_bifcfgdecp |
1024 | #define cfgBIF_CFG_DEV0_EPF3_0_VENDOR_ID_DEFAULT 0x00000000 |
1025 | #define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_ID_DEFAULT 0x00000000 |
1026 | #define cfgBIF_CFG_DEV0_EPF3_0_COMMAND_DEFAULT 0x00000000 |
1027 | #define cfgBIF_CFG_DEV0_EPF3_0_STATUS_DEFAULT 0x00000000 |
1028 | #define cfgBIF_CFG_DEV0_EPF3_0_REVISION_ID_DEFAULT 0x00000000 |
1029 | #define cfgBIF_CFG_DEV0_EPF3_0_PROG_INTERFACE_DEFAULT 0x00000000 |
1030 | #define cfgBIF_CFG_DEV0_EPF3_0_SUB_CLASS_DEFAULT 0x00000000 |
1031 | #define cfgBIF_CFG_DEV0_EPF3_0_BASE_CLASS_DEFAULT 0x00000000 |
1032 | #define cfgBIF_CFG_DEV0_EPF3_0_CACHE_LINE_DEFAULT 0x00000000 |
1033 | #define cfgBIF_CFG_DEV0_EPF3_0_LATENCY_DEFAULT 0x00000000 |
1034 | #define 0x00000000 |
1035 | #define cfgBIF_CFG_DEV0_EPF3_0_BIST_DEFAULT 0x00000000 |
1036 | #define cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_1_DEFAULT 0x00000000 |
1037 | #define cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_2_DEFAULT 0x00000000 |
1038 | #define cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_3_DEFAULT 0x00000000 |
1039 | #define cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_4_DEFAULT 0x00000000 |
1040 | #define cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_5_DEFAULT 0x00000000 |
1041 | #define cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_6_DEFAULT 0x00000000 |
1042 | #define cfgBIF_CFG_DEV0_EPF3_0_ADAPTER_ID_DEFAULT 0x00000000 |
1043 | #define cfgBIF_CFG_DEV0_EPF3_0_ROM_BASE_ADDR_DEFAULT 0x00000000 |
1044 | #define cfgBIF_CFG_DEV0_EPF3_0_CAP_PTR_DEFAULT 0x00000000 |
1045 | #define cfgBIF_CFG_DEV0_EPF3_0_INTERRUPT_LINE_DEFAULT 0x00000000 |
1046 | #define cfgBIF_CFG_DEV0_EPF3_0_INTERRUPT_PIN_DEFAULT 0x00000000 |
1047 | #define cfgBIF_CFG_DEV0_EPF3_0_MIN_GRANT_DEFAULT 0x00000000 |
1048 | #define cfgBIF_CFG_DEV0_EPF3_0_MAX_LATENCY_DEFAULT 0x00000000 |
1049 | #define cfgBIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST_DEFAULT 0x00000000 |
1050 | #define cfgBIF_CFG_DEV0_EPF3_0_ADAPTER_ID_W_DEFAULT 0x00000000 |
1051 | #define cfgBIF_CFG_DEV0_EPF3_0_PMI_CAP_LIST_DEFAULT 0x00000000 |
1052 | #define cfgBIF_CFG_DEV0_EPF3_0_PMI_CAP_DEFAULT 0x00000000 |
1053 | #define cfgBIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL_DEFAULT 0x00000000 |
1054 | #define cfgBIF_CFG_DEV0_EPF3_0_SBRN_DEFAULT 0x00000000 |
1055 | #define cfgBIF_CFG_DEV0_EPF3_0_FLADJ_DEFAULT 0x00000020 |
1056 | #define cfgBIF_CFG_DEV0_EPF3_0_DBESL_DBESLD_DEFAULT 0x00000000 |
1057 | #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_CAP_LIST_DEFAULT 0x0000a000 |
1058 | #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_CAP_DEFAULT 0x00000002 |
1059 | #define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_CAP_DEFAULT 0x10000000 |
1060 | #define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_CNTL_DEFAULT 0x00002810 |
1061 | #define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_STATUS_DEFAULT 0x00000000 |
1062 | #define cfgBIF_CFG_DEV0_EPF3_0_LINK_CAP_DEFAULT 0x00011c03 |
1063 | #define cfgBIF_CFG_DEV0_EPF3_0_LINK_CNTL_DEFAULT 0x00000000 |
1064 | #define cfgBIF_CFG_DEV0_EPF3_0_LINK_STATUS_DEFAULT 0x00000001 |
1065 | #define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_CAP2_DEFAULT 0x00000000 |
1066 | #define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2_DEFAULT 0x00000000 |
1067 | #define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_STATUS2_DEFAULT 0x00000000 |
1068 | #define cfgBIF_CFG_DEV0_EPF3_0_LINK_CAP2_DEFAULT 0x0000000e |
1069 | #define cfgBIF_CFG_DEV0_EPF3_0_LINK_CNTL2_DEFAULT 0x00000003 |
1070 | #define cfgBIF_CFG_DEV0_EPF3_0_LINK_STATUS2_DEFAULT 0x00000000 |
1071 | #define cfgBIF_CFG_DEV0_EPF3_0_SLOT_CAP2_DEFAULT 0x00000000 |
1072 | #define cfgBIF_CFG_DEV0_EPF3_0_SLOT_CNTL2_DEFAULT 0x00000000 |
1073 | #define cfgBIF_CFG_DEV0_EPF3_0_SLOT_STATUS2_DEFAULT 0x00000000 |
1074 | #define cfgBIF_CFG_DEV0_EPF3_0_MSI_CAP_LIST_DEFAULT 0x0000c000 |
1075 | #define cfgBIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL_DEFAULT 0x00000080 |
1076 | #define cfgBIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 |
1077 | #define cfgBIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 |
1078 | #define cfgBIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA_DEFAULT 0x00000000 |
1079 | #define cfgBIF_CFG_DEV0_EPF3_0_MSI_MASK_DEFAULT 0x00000000 |
1080 | #define cfgBIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA_64_DEFAULT 0x00000000 |
1081 | #define cfgBIF_CFG_DEV0_EPF3_0_MSI_MASK_64_DEFAULT 0x00000000 |
1082 | #define cfgBIF_CFG_DEV0_EPF3_0_MSI_PENDING_DEFAULT 0x00000000 |
1083 | #define cfgBIF_CFG_DEV0_EPF3_0_MSI_PENDING_64_DEFAULT 0x00000000 |
1084 | #define cfgBIF_CFG_DEV0_EPF3_0_MSIX_CAP_LIST_DEFAULT 0x00000000 |
1085 | #define cfgBIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL_DEFAULT 0x00000000 |
1086 | #define cfgBIF_CFG_DEV0_EPF3_0_MSIX_TABLE_DEFAULT 0x00000000 |
1087 | #define cfgBIF_CFG_DEV0_EPF3_0_MSIX_PBA_DEFAULT 0x00000000 |
1088 | #define cfgBIF_CFG_DEV0_EPF3_0_SATA_CAP_0_DEFAULT 0x00000000 |
1089 | #define cfgBIF_CFG_DEV0_EPF3_0_SATA_CAP_1_DEFAULT 0x00000000 |
1090 | #define cfgBIF_CFG_DEV0_EPF3_0_SATA_IDP_INDEX_DEFAULT 0x00000000 |
1091 | #define cfgBIF_CFG_DEV0_EPF3_0_SATA_IDP_DATA_DEFAULT 0x00000000 |
1092 | #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 |
1093 | #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 |
1094 | #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 |
1095 | #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 |
1096 | #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 |
1097 | #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 |
1098 | #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 |
1099 | #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 |
1100 | #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 |
1101 | #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000 |
1102 | #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 |
1103 | #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG0_DEFAULT 0x00000000 |
1104 | #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG1_DEFAULT 0x00000000 |
1105 | #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG2_DEFAULT 0x00000000 |
1106 | #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG3_DEFAULT 0x00000000 |
1107 | #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 |
1108 | #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 |
1109 | #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 |
1110 | #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 |
1111 | #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000 |
1112 | #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CAP_DEFAULT 0x00000000 |
1113 | #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL_DEFAULT 0x00000020 |
1114 | #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CAP_DEFAULT 0x00000000 |
1115 | #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL_DEFAULT 0x00000000 |
1116 | #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CAP_DEFAULT 0x00000000 |
1117 | #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL_DEFAULT 0x00000000 |
1118 | #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CAP_DEFAULT 0x00000000 |
1119 | #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL_DEFAULT 0x00000000 |
1120 | #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CAP_DEFAULT 0x00000000 |
1121 | #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL_DEFAULT 0x00000000 |
1122 | #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CAP_DEFAULT 0x00000000 |
1123 | #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL_DEFAULT 0x00000000 |
1124 | #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000 |
1125 | #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000 |
1126 | #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000 |
1127 | #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000 |
1128 | #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000 |
1129 | #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP_DEFAULT 0x00000000 |
1130 | #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000 |
1131 | #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_STATUS_DEFAULT 0x00000100 |
1132 | #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_CNTL_DEFAULT 0x00000000 |
1133 | #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000 |
1134 | #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000 |
1135 | #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000 |
1136 | #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000 |
1137 | #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000 |
1138 | #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000 |
1139 | #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000 |
1140 | #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000 |
1141 | #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000 |
1142 | #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP_DEFAULT 0x00000000 |
1143 | #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL_DEFAULT 0x00000000 |
1144 | #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000 |
1145 | #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP_DEFAULT 0x00000000 |
1146 | #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL_DEFAULT 0x00000000 |
1147 | |
1148 | |
1149 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf4_bifcfgdecp |
1150 | #define cfgBIF_CFG_DEV0_EPF4_0_VENDOR_ID_DEFAULT 0x00000000 |
1151 | #define cfgBIF_CFG_DEV0_EPF4_0_DEVICE_ID_DEFAULT 0x00000000 |
1152 | #define cfgBIF_CFG_DEV0_EPF4_0_COMMAND_DEFAULT 0x00000000 |
1153 | #define cfgBIF_CFG_DEV0_EPF4_0_STATUS_DEFAULT 0x00000000 |
1154 | #define cfgBIF_CFG_DEV0_EPF4_0_REVISION_ID_DEFAULT 0x00000000 |
1155 | #define cfgBIF_CFG_DEV0_EPF4_0_PROG_INTERFACE_DEFAULT 0x00000000 |
1156 | #define cfgBIF_CFG_DEV0_EPF4_0_SUB_CLASS_DEFAULT 0x00000000 |
1157 | #define cfgBIF_CFG_DEV0_EPF4_0_BASE_CLASS_DEFAULT 0x00000000 |
1158 | #define cfgBIF_CFG_DEV0_EPF4_0_CACHE_LINE_DEFAULT 0x00000000 |
1159 | #define cfgBIF_CFG_DEV0_EPF4_0_LATENCY_DEFAULT 0x00000000 |
1160 | #define 0x00000000 |
1161 | #define cfgBIF_CFG_DEV0_EPF4_0_BIST_DEFAULT 0x00000000 |
1162 | #define cfgBIF_CFG_DEV0_EPF4_0_BASE_ADDR_1_DEFAULT 0x00000000 |
1163 | #define cfgBIF_CFG_DEV0_EPF4_0_BASE_ADDR_2_DEFAULT 0x00000000 |
1164 | #define cfgBIF_CFG_DEV0_EPF4_0_BASE_ADDR_3_DEFAULT 0x00000000 |
1165 | #define cfgBIF_CFG_DEV0_EPF4_0_BASE_ADDR_4_DEFAULT 0x00000000 |
1166 | #define cfgBIF_CFG_DEV0_EPF4_0_BASE_ADDR_5_DEFAULT 0x00000000 |
1167 | #define cfgBIF_CFG_DEV0_EPF4_0_BASE_ADDR_6_DEFAULT 0x00000000 |
1168 | #define cfgBIF_CFG_DEV0_EPF4_0_ADAPTER_ID_DEFAULT 0x00000000 |
1169 | #define cfgBIF_CFG_DEV0_EPF4_0_ROM_BASE_ADDR_DEFAULT 0x00000000 |
1170 | #define cfgBIF_CFG_DEV0_EPF4_0_CAP_PTR_DEFAULT 0x00000000 |
1171 | #define cfgBIF_CFG_DEV0_EPF4_0_INTERRUPT_LINE_DEFAULT 0x00000000 |
1172 | #define cfgBIF_CFG_DEV0_EPF4_0_INTERRUPT_PIN_DEFAULT 0x00000000 |
1173 | #define cfgBIF_CFG_DEV0_EPF4_0_MIN_GRANT_DEFAULT 0x00000000 |
1174 | #define cfgBIF_CFG_DEV0_EPF4_0_MAX_LATENCY_DEFAULT 0x00000000 |
1175 | #define cfgBIF_CFG_DEV0_EPF4_0_VENDOR_CAP_LIST_DEFAULT 0x00000000 |
1176 | #define cfgBIF_CFG_DEV0_EPF4_0_ADAPTER_ID_W_DEFAULT 0x00000000 |
1177 | #define cfgBIF_CFG_DEV0_EPF4_0_PMI_CAP_LIST_DEFAULT 0x00000000 |
1178 | #define cfgBIF_CFG_DEV0_EPF4_0_PMI_CAP_DEFAULT 0x00000000 |
1179 | #define cfgBIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL_DEFAULT 0x00000000 |
1180 | #define cfgBIF_CFG_DEV0_EPF4_0_SBRN_DEFAULT 0x00000000 |
1181 | #define cfgBIF_CFG_DEV0_EPF4_0_FLADJ_DEFAULT 0x00000020 |
1182 | #define cfgBIF_CFG_DEV0_EPF4_0_DBESL_DBESLD_DEFAULT 0x00000000 |
1183 | #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_CAP_LIST_DEFAULT 0x0000a000 |
1184 | #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_CAP_DEFAULT 0x00000002 |
1185 | #define cfgBIF_CFG_DEV0_EPF4_0_DEVICE_CAP_DEFAULT 0x10000000 |
1186 | #define cfgBIF_CFG_DEV0_EPF4_0_DEVICE_CNTL_DEFAULT 0x00002810 |
1187 | #define cfgBIF_CFG_DEV0_EPF4_0_DEVICE_STATUS_DEFAULT 0x00000000 |
1188 | #define cfgBIF_CFG_DEV0_EPF4_0_LINK_CAP_DEFAULT 0x00011c03 |
1189 | #define cfgBIF_CFG_DEV0_EPF4_0_LINK_CNTL_DEFAULT 0x00000000 |
1190 | #define cfgBIF_CFG_DEV0_EPF4_0_LINK_STATUS_DEFAULT 0x00000001 |
1191 | #define cfgBIF_CFG_DEV0_EPF4_0_DEVICE_CAP2_DEFAULT 0x00000000 |
1192 | #define cfgBIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2_DEFAULT 0x00000000 |
1193 | #define cfgBIF_CFG_DEV0_EPF4_0_DEVICE_STATUS2_DEFAULT 0x00000000 |
1194 | #define cfgBIF_CFG_DEV0_EPF4_0_LINK_CAP2_DEFAULT 0x0000000e |
1195 | #define cfgBIF_CFG_DEV0_EPF4_0_LINK_CNTL2_DEFAULT 0x00000003 |
1196 | #define cfgBIF_CFG_DEV0_EPF4_0_LINK_STATUS2_DEFAULT 0x00000000 |
1197 | #define cfgBIF_CFG_DEV0_EPF4_0_SLOT_CAP2_DEFAULT 0x00000000 |
1198 | #define cfgBIF_CFG_DEV0_EPF4_0_SLOT_CNTL2_DEFAULT 0x00000000 |
1199 | #define cfgBIF_CFG_DEV0_EPF4_0_SLOT_STATUS2_DEFAULT 0x00000000 |
1200 | #define cfgBIF_CFG_DEV0_EPF4_0_MSI_CAP_LIST_DEFAULT 0x0000c000 |
1201 | #define cfgBIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL_DEFAULT 0x00000080 |
1202 | #define cfgBIF_CFG_DEV0_EPF4_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 |
1203 | #define cfgBIF_CFG_DEV0_EPF4_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 |
1204 | #define cfgBIF_CFG_DEV0_EPF4_0_MSI_MSG_DATA_DEFAULT 0x00000000 |
1205 | #define cfgBIF_CFG_DEV0_EPF4_0_MSI_MASK_DEFAULT 0x00000000 |
1206 | #define cfgBIF_CFG_DEV0_EPF4_0_MSI_MSG_DATA_64_DEFAULT 0x00000000 |
1207 | #define cfgBIF_CFG_DEV0_EPF4_0_MSI_MASK_64_DEFAULT 0x00000000 |
1208 | #define cfgBIF_CFG_DEV0_EPF4_0_MSI_PENDING_DEFAULT 0x00000000 |
1209 | #define cfgBIF_CFG_DEV0_EPF4_0_MSI_PENDING_64_DEFAULT 0x00000000 |
1210 | #define cfgBIF_CFG_DEV0_EPF4_0_MSIX_CAP_LIST_DEFAULT 0x00000000 |
1211 | #define cfgBIF_CFG_DEV0_EPF4_0_MSIX_MSG_CNTL_DEFAULT 0x00000000 |
1212 | #define cfgBIF_CFG_DEV0_EPF4_0_MSIX_TABLE_DEFAULT 0x00000000 |
1213 | #define cfgBIF_CFG_DEV0_EPF4_0_MSIX_PBA_DEFAULT 0x00000000 |
1214 | #define cfgBIF_CFG_DEV0_EPF4_0_SATA_CAP_0_DEFAULT 0x00000000 |
1215 | #define cfgBIF_CFG_DEV0_EPF4_0_SATA_CAP_1_DEFAULT 0x00000000 |
1216 | #define cfgBIF_CFG_DEV0_EPF4_0_SATA_IDP_INDEX_DEFAULT 0x00000000 |
1217 | #define cfgBIF_CFG_DEV0_EPF4_0_SATA_IDP_DATA_DEFAULT 0x00000000 |
1218 | #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 |
1219 | #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 |
1220 | #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 |
1221 | #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 |
1222 | #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 |
1223 | #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 |
1224 | #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 |
1225 | #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 |
1226 | #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 |
1227 | #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000 |
1228 | #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 |
1229 | #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG0_DEFAULT 0x00000000 |
1230 | #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG1_DEFAULT 0x00000000 |
1231 | #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG2_DEFAULT 0x00000000 |
1232 | #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG3_DEFAULT 0x00000000 |
1233 | #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 |
1234 | #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 |
1235 | #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 |
1236 | #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 |
1237 | #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000 |
1238 | #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CAP_DEFAULT 0x00000000 |
1239 | #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CNTL_DEFAULT 0x00000020 |
1240 | #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CAP_DEFAULT 0x00000000 |
1241 | #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CNTL_DEFAULT 0x00000000 |
1242 | #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CAP_DEFAULT 0x00000000 |
1243 | #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CNTL_DEFAULT 0x00000000 |
1244 | #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CAP_DEFAULT 0x00000000 |
1245 | #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CNTL_DEFAULT 0x00000000 |
1246 | #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CAP_DEFAULT 0x00000000 |
1247 | #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CNTL_DEFAULT 0x00000000 |
1248 | #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CAP_DEFAULT 0x00000000 |
1249 | #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CNTL_DEFAULT 0x00000000 |
1250 | #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000 |
1251 | #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000 |
1252 | #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000 |
1253 | #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000 |
1254 | #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000 |
1255 | #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP_DEFAULT 0x00000000 |
1256 | #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000 |
1257 | #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_DPA_STATUS_DEFAULT 0x00000100 |
1258 | #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_DPA_CNTL_DEFAULT 0x00000000 |
1259 | #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000 |
1260 | #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000 |
1261 | #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000 |
1262 | #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000 |
1263 | #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000 |
1264 | #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000 |
1265 | #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000 |
1266 | #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000 |
1267 | #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000 |
1268 | #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP_DEFAULT 0x00000000 |
1269 | #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL_DEFAULT 0x00000000 |
1270 | #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000 |
1271 | #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_ARI_CAP_DEFAULT 0x00000000 |
1272 | #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_ARI_CNTL_DEFAULT 0x00000000 |
1273 | |
1274 | |
1275 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf5_bifcfgdecp |
1276 | #define cfgBIF_CFG_DEV0_EPF5_0_VENDOR_ID_DEFAULT 0x00000000 |
1277 | #define cfgBIF_CFG_DEV0_EPF5_0_DEVICE_ID_DEFAULT 0x00000000 |
1278 | #define cfgBIF_CFG_DEV0_EPF5_0_COMMAND_DEFAULT 0x00000000 |
1279 | #define cfgBIF_CFG_DEV0_EPF5_0_STATUS_DEFAULT 0x00000000 |
1280 | #define cfgBIF_CFG_DEV0_EPF5_0_REVISION_ID_DEFAULT 0x00000000 |
1281 | #define cfgBIF_CFG_DEV0_EPF5_0_PROG_INTERFACE_DEFAULT 0x00000000 |
1282 | #define cfgBIF_CFG_DEV0_EPF5_0_SUB_CLASS_DEFAULT 0x00000000 |
1283 | #define cfgBIF_CFG_DEV0_EPF5_0_BASE_CLASS_DEFAULT 0x00000000 |
1284 | #define cfgBIF_CFG_DEV0_EPF5_0_CACHE_LINE_DEFAULT 0x00000000 |
1285 | #define cfgBIF_CFG_DEV0_EPF5_0_LATENCY_DEFAULT 0x00000000 |
1286 | #define 0x00000000 |
1287 | #define cfgBIF_CFG_DEV0_EPF5_0_BIST_DEFAULT 0x00000000 |
1288 | #define cfgBIF_CFG_DEV0_EPF5_0_BASE_ADDR_1_DEFAULT 0x00000000 |
1289 | #define cfgBIF_CFG_DEV0_EPF5_0_BASE_ADDR_2_DEFAULT 0x00000000 |
1290 | #define cfgBIF_CFG_DEV0_EPF5_0_BASE_ADDR_3_DEFAULT 0x00000000 |
1291 | #define cfgBIF_CFG_DEV0_EPF5_0_BASE_ADDR_4_DEFAULT 0x00000000 |
1292 | #define cfgBIF_CFG_DEV0_EPF5_0_BASE_ADDR_5_DEFAULT 0x00000000 |
1293 | #define cfgBIF_CFG_DEV0_EPF5_0_BASE_ADDR_6_DEFAULT 0x00000000 |
1294 | #define cfgBIF_CFG_DEV0_EPF5_0_ADAPTER_ID_DEFAULT 0x00000000 |
1295 | #define cfgBIF_CFG_DEV0_EPF5_0_ROM_BASE_ADDR_DEFAULT 0x00000000 |
1296 | #define cfgBIF_CFG_DEV0_EPF5_0_CAP_PTR_DEFAULT 0x00000000 |
1297 | #define cfgBIF_CFG_DEV0_EPF5_0_INTERRUPT_LINE_DEFAULT 0x00000000 |
1298 | #define cfgBIF_CFG_DEV0_EPF5_0_INTERRUPT_PIN_DEFAULT 0x00000000 |
1299 | #define cfgBIF_CFG_DEV0_EPF5_0_MIN_GRANT_DEFAULT 0x00000000 |
1300 | #define cfgBIF_CFG_DEV0_EPF5_0_MAX_LATENCY_DEFAULT 0x00000000 |
1301 | #define cfgBIF_CFG_DEV0_EPF5_0_VENDOR_CAP_LIST_DEFAULT 0x00000000 |
1302 | #define cfgBIF_CFG_DEV0_EPF5_0_ADAPTER_ID_W_DEFAULT 0x00000000 |
1303 | #define cfgBIF_CFG_DEV0_EPF5_0_PMI_CAP_LIST_DEFAULT 0x00000000 |
1304 | #define cfgBIF_CFG_DEV0_EPF5_0_PMI_CAP_DEFAULT 0x00000000 |
1305 | #define cfgBIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL_DEFAULT 0x00000000 |
1306 | #define cfgBIF_CFG_DEV0_EPF5_0_SBRN_DEFAULT 0x00000000 |
1307 | #define cfgBIF_CFG_DEV0_EPF5_0_FLADJ_DEFAULT 0x00000020 |
1308 | #define cfgBIF_CFG_DEV0_EPF5_0_DBESL_DBESLD_DEFAULT 0x00000000 |
1309 | #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_CAP_LIST_DEFAULT 0x0000a000 |
1310 | #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_CAP_DEFAULT 0x00000002 |
1311 | #define cfgBIF_CFG_DEV0_EPF5_0_DEVICE_CAP_DEFAULT 0x10000000 |
1312 | #define cfgBIF_CFG_DEV0_EPF5_0_DEVICE_CNTL_DEFAULT 0x00002810 |
1313 | #define cfgBIF_CFG_DEV0_EPF5_0_DEVICE_STATUS_DEFAULT 0x00000000 |
1314 | #define cfgBIF_CFG_DEV0_EPF5_0_LINK_CAP_DEFAULT 0x00011c03 |
1315 | #define cfgBIF_CFG_DEV0_EPF5_0_LINK_CNTL_DEFAULT 0x00000000 |
1316 | #define cfgBIF_CFG_DEV0_EPF5_0_LINK_STATUS_DEFAULT 0x00000001 |
1317 | #define cfgBIF_CFG_DEV0_EPF5_0_DEVICE_CAP2_DEFAULT 0x00000000 |
1318 | #define cfgBIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2_DEFAULT 0x00000000 |
1319 | #define cfgBIF_CFG_DEV0_EPF5_0_DEVICE_STATUS2_DEFAULT 0x00000000 |
1320 | #define cfgBIF_CFG_DEV0_EPF5_0_LINK_CAP2_DEFAULT 0x0000000e |
1321 | #define cfgBIF_CFG_DEV0_EPF5_0_LINK_CNTL2_DEFAULT 0x00000003 |
1322 | #define cfgBIF_CFG_DEV0_EPF5_0_LINK_STATUS2_DEFAULT 0x00000000 |
1323 | #define cfgBIF_CFG_DEV0_EPF5_0_SLOT_CAP2_DEFAULT 0x00000000 |
1324 | #define cfgBIF_CFG_DEV0_EPF5_0_SLOT_CNTL2_DEFAULT 0x00000000 |
1325 | #define cfgBIF_CFG_DEV0_EPF5_0_SLOT_STATUS2_DEFAULT 0x00000000 |
1326 | #define cfgBIF_CFG_DEV0_EPF5_0_MSI_CAP_LIST_DEFAULT 0x0000c000 |
1327 | #define cfgBIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL_DEFAULT 0x00000080 |
1328 | #define cfgBIF_CFG_DEV0_EPF5_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 |
1329 | #define cfgBIF_CFG_DEV0_EPF5_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 |
1330 | #define cfgBIF_CFG_DEV0_EPF5_0_MSI_MSG_DATA_DEFAULT 0x00000000 |
1331 | #define cfgBIF_CFG_DEV0_EPF5_0_MSI_MASK_DEFAULT 0x00000000 |
1332 | #define cfgBIF_CFG_DEV0_EPF5_0_MSI_MSG_DATA_64_DEFAULT 0x00000000 |
1333 | #define cfgBIF_CFG_DEV0_EPF5_0_MSI_MASK_64_DEFAULT 0x00000000 |
1334 | #define cfgBIF_CFG_DEV0_EPF5_0_MSI_PENDING_DEFAULT 0x00000000 |
1335 | #define cfgBIF_CFG_DEV0_EPF5_0_MSI_PENDING_64_DEFAULT 0x00000000 |
1336 | #define cfgBIF_CFG_DEV0_EPF5_0_MSIX_CAP_LIST_DEFAULT 0x00000000 |
1337 | #define cfgBIF_CFG_DEV0_EPF5_0_MSIX_MSG_CNTL_DEFAULT 0x00000000 |
1338 | #define cfgBIF_CFG_DEV0_EPF5_0_MSIX_TABLE_DEFAULT 0x00000000 |
1339 | #define cfgBIF_CFG_DEV0_EPF5_0_MSIX_PBA_DEFAULT 0x00000000 |
1340 | #define cfgBIF_CFG_DEV0_EPF5_0_SATA_CAP_0_DEFAULT 0x00000000 |
1341 | #define cfgBIF_CFG_DEV0_EPF5_0_SATA_CAP_1_DEFAULT 0x00000000 |
1342 | #define cfgBIF_CFG_DEV0_EPF5_0_SATA_IDP_INDEX_DEFAULT 0x00000000 |
1343 | #define cfgBIF_CFG_DEV0_EPF5_0_SATA_IDP_DATA_DEFAULT 0x00000000 |
1344 | #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 |
1345 | #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 |
1346 | #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 |
1347 | #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 |
1348 | #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 |
1349 | #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 |
1350 | #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 |
1351 | #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 |
1352 | #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 |
1353 | #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000 |
1354 | #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 |
1355 | #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG0_DEFAULT 0x00000000 |
1356 | #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG1_DEFAULT 0x00000000 |
1357 | #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG2_DEFAULT 0x00000000 |
1358 | #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG3_DEFAULT 0x00000000 |
1359 | #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 |
1360 | #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 |
1361 | #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 |
1362 | #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 |
1363 | #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000 |
1364 | #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CAP_DEFAULT 0x00000000 |
1365 | #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CNTL_DEFAULT 0x00000020 |
1366 | #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CAP_DEFAULT 0x00000000 |
1367 | #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CNTL_DEFAULT 0x00000000 |
1368 | #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CAP_DEFAULT 0x00000000 |
1369 | #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CNTL_DEFAULT 0x00000000 |
1370 | #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CAP_DEFAULT 0x00000000 |
1371 | #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CNTL_DEFAULT 0x00000000 |
1372 | #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CAP_DEFAULT 0x00000000 |
1373 | #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CNTL_DEFAULT 0x00000000 |
1374 | #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CAP_DEFAULT 0x00000000 |
1375 | #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CNTL_DEFAULT 0x00000000 |
1376 | #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000 |
1377 | #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000 |
1378 | #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000 |
1379 | #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000 |
1380 | #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000 |
1381 | #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP_DEFAULT 0x00000000 |
1382 | #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000 |
1383 | #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_DPA_STATUS_DEFAULT 0x00000100 |
1384 | #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_DPA_CNTL_DEFAULT 0x00000000 |
1385 | #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000 |
1386 | #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000 |
1387 | #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000 |
1388 | #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000 |
1389 | #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000 |
1390 | #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000 |
1391 | #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000 |
1392 | #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000 |
1393 | #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000 |
1394 | #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP_DEFAULT 0x00000000 |
1395 | #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL_DEFAULT 0x00000000 |
1396 | #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000 |
1397 | #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_ARI_CAP_DEFAULT 0x00000000 |
1398 | #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_ARI_CNTL_DEFAULT 0x00000000 |
1399 | |
1400 | |
1401 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf6_bifcfgdecp |
1402 | #define cfgBIF_CFG_DEV0_EPF6_0_VENDOR_ID_DEFAULT 0x00000000 |
1403 | #define cfgBIF_CFG_DEV0_EPF6_0_DEVICE_ID_DEFAULT 0x00000000 |
1404 | #define cfgBIF_CFG_DEV0_EPF6_0_COMMAND_DEFAULT 0x00000000 |
1405 | #define cfgBIF_CFG_DEV0_EPF6_0_STATUS_DEFAULT 0x00000000 |
1406 | #define cfgBIF_CFG_DEV0_EPF6_0_REVISION_ID_DEFAULT 0x00000000 |
1407 | #define cfgBIF_CFG_DEV0_EPF6_0_PROG_INTERFACE_DEFAULT 0x00000000 |
1408 | #define cfgBIF_CFG_DEV0_EPF6_0_SUB_CLASS_DEFAULT 0x00000000 |
1409 | #define cfgBIF_CFG_DEV0_EPF6_0_BASE_CLASS_DEFAULT 0x00000000 |
1410 | #define cfgBIF_CFG_DEV0_EPF6_0_CACHE_LINE_DEFAULT 0x00000000 |
1411 | #define cfgBIF_CFG_DEV0_EPF6_0_LATENCY_DEFAULT 0x00000000 |
1412 | #define 0x00000000 |
1413 | #define cfgBIF_CFG_DEV0_EPF6_0_BIST_DEFAULT 0x00000000 |
1414 | #define cfgBIF_CFG_DEV0_EPF6_0_BASE_ADDR_1_DEFAULT 0x00000000 |
1415 | #define cfgBIF_CFG_DEV0_EPF6_0_BASE_ADDR_2_DEFAULT 0x00000000 |
1416 | #define cfgBIF_CFG_DEV0_EPF6_0_BASE_ADDR_3_DEFAULT 0x00000000 |
1417 | #define cfgBIF_CFG_DEV0_EPF6_0_BASE_ADDR_4_DEFAULT 0x00000000 |
1418 | #define cfgBIF_CFG_DEV0_EPF6_0_BASE_ADDR_5_DEFAULT 0x00000000 |
1419 | #define cfgBIF_CFG_DEV0_EPF6_0_BASE_ADDR_6_DEFAULT 0x00000000 |
1420 | #define cfgBIF_CFG_DEV0_EPF6_0_ADAPTER_ID_DEFAULT 0x00000000 |
1421 | #define cfgBIF_CFG_DEV0_EPF6_0_ROM_BASE_ADDR_DEFAULT 0x00000000 |
1422 | #define cfgBIF_CFG_DEV0_EPF6_0_CAP_PTR_DEFAULT 0x00000000 |
1423 | #define cfgBIF_CFG_DEV0_EPF6_0_INTERRUPT_LINE_DEFAULT 0x00000000 |
1424 | #define cfgBIF_CFG_DEV0_EPF6_0_INTERRUPT_PIN_DEFAULT 0x00000000 |
1425 | #define cfgBIF_CFG_DEV0_EPF6_0_MIN_GRANT_DEFAULT 0x00000000 |
1426 | #define cfgBIF_CFG_DEV0_EPF6_0_MAX_LATENCY_DEFAULT 0x00000000 |
1427 | #define cfgBIF_CFG_DEV0_EPF6_0_VENDOR_CAP_LIST_DEFAULT 0x00000000 |
1428 | #define cfgBIF_CFG_DEV0_EPF6_0_ADAPTER_ID_W_DEFAULT 0x00000000 |
1429 | #define cfgBIF_CFG_DEV0_EPF6_0_PMI_CAP_LIST_DEFAULT 0x00000000 |
1430 | #define cfgBIF_CFG_DEV0_EPF6_0_PMI_CAP_DEFAULT 0x00000000 |
1431 | #define cfgBIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL_DEFAULT 0x00000000 |
1432 | #define cfgBIF_CFG_DEV0_EPF6_0_SBRN_DEFAULT 0x00000000 |
1433 | #define cfgBIF_CFG_DEV0_EPF6_0_FLADJ_DEFAULT 0x00000020 |
1434 | #define cfgBIF_CFG_DEV0_EPF6_0_DBESL_DBESLD_DEFAULT 0x00000000 |
1435 | #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_CAP_LIST_DEFAULT 0x0000a000 |
1436 | #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_CAP_DEFAULT 0x00000002 |
1437 | #define cfgBIF_CFG_DEV0_EPF6_0_DEVICE_CAP_DEFAULT 0x10000000 |
1438 | #define cfgBIF_CFG_DEV0_EPF6_0_DEVICE_CNTL_DEFAULT 0x00002810 |
1439 | #define cfgBIF_CFG_DEV0_EPF6_0_DEVICE_STATUS_DEFAULT 0x00000000 |
1440 | #define cfgBIF_CFG_DEV0_EPF6_0_LINK_CAP_DEFAULT 0x00011c03 |
1441 | #define cfgBIF_CFG_DEV0_EPF6_0_LINK_CNTL_DEFAULT 0x00000000 |
1442 | #define cfgBIF_CFG_DEV0_EPF6_0_LINK_STATUS_DEFAULT 0x00000001 |
1443 | #define cfgBIF_CFG_DEV0_EPF6_0_DEVICE_CAP2_DEFAULT 0x00000000 |
1444 | #define cfgBIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2_DEFAULT 0x00000000 |
1445 | #define cfgBIF_CFG_DEV0_EPF6_0_DEVICE_STATUS2_DEFAULT 0x00000000 |
1446 | #define cfgBIF_CFG_DEV0_EPF6_0_LINK_CAP2_DEFAULT 0x0000000e |
1447 | #define cfgBIF_CFG_DEV0_EPF6_0_LINK_CNTL2_DEFAULT 0x00000003 |
1448 | #define cfgBIF_CFG_DEV0_EPF6_0_LINK_STATUS2_DEFAULT 0x00000000 |
1449 | #define cfgBIF_CFG_DEV0_EPF6_0_SLOT_CAP2_DEFAULT 0x00000000 |
1450 | #define cfgBIF_CFG_DEV0_EPF6_0_SLOT_CNTL2_DEFAULT 0x00000000 |
1451 | #define cfgBIF_CFG_DEV0_EPF6_0_SLOT_STATUS2_DEFAULT 0x00000000 |
1452 | #define cfgBIF_CFG_DEV0_EPF6_0_MSI_CAP_LIST_DEFAULT 0x0000c000 |
1453 | #define cfgBIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL_DEFAULT 0x00000080 |
1454 | #define cfgBIF_CFG_DEV0_EPF6_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 |
1455 | #define cfgBIF_CFG_DEV0_EPF6_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 |
1456 | #define cfgBIF_CFG_DEV0_EPF6_0_MSI_MSG_DATA_DEFAULT 0x00000000 |
1457 | #define cfgBIF_CFG_DEV0_EPF6_0_MSI_MASK_DEFAULT 0x00000000 |
1458 | #define cfgBIF_CFG_DEV0_EPF6_0_MSI_MSG_DATA_64_DEFAULT 0x00000000 |
1459 | #define cfgBIF_CFG_DEV0_EPF6_0_MSI_MASK_64_DEFAULT 0x00000000 |
1460 | #define cfgBIF_CFG_DEV0_EPF6_0_MSI_PENDING_DEFAULT 0x00000000 |
1461 | #define cfgBIF_CFG_DEV0_EPF6_0_MSI_PENDING_64_DEFAULT 0x00000000 |
1462 | #define cfgBIF_CFG_DEV0_EPF6_0_MSIX_CAP_LIST_DEFAULT 0x00000000 |
1463 | #define cfgBIF_CFG_DEV0_EPF6_0_MSIX_MSG_CNTL_DEFAULT 0x00000000 |
1464 | #define cfgBIF_CFG_DEV0_EPF6_0_MSIX_TABLE_DEFAULT 0x00000000 |
1465 | #define cfgBIF_CFG_DEV0_EPF6_0_MSIX_PBA_DEFAULT 0x00000000 |
1466 | #define cfgBIF_CFG_DEV0_EPF6_0_SATA_CAP_0_DEFAULT 0x00000000 |
1467 | #define cfgBIF_CFG_DEV0_EPF6_0_SATA_CAP_1_DEFAULT 0x00000000 |
1468 | #define cfgBIF_CFG_DEV0_EPF6_0_SATA_IDP_INDEX_DEFAULT 0x00000000 |
1469 | #define cfgBIF_CFG_DEV0_EPF6_0_SATA_IDP_DATA_DEFAULT 0x00000000 |
1470 | #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 |
1471 | #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 |
1472 | #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 |
1473 | #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 |
1474 | #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 |
1475 | #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 |
1476 | #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 |
1477 | #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 |
1478 | #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 |
1479 | #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000 |
1480 | #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 |
1481 | #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG0_DEFAULT 0x00000000 |
1482 | #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG1_DEFAULT 0x00000000 |
1483 | #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG2_DEFAULT 0x00000000 |
1484 | #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG3_DEFAULT 0x00000000 |
1485 | #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 |
1486 | #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 |
1487 | #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 |
1488 | #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 |
1489 | #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000 |
1490 | #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CAP_DEFAULT 0x00000000 |
1491 | #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CNTL_DEFAULT 0x00000020 |
1492 | #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CAP_DEFAULT 0x00000000 |
1493 | #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CNTL_DEFAULT 0x00000000 |
1494 | #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CAP_DEFAULT 0x00000000 |
1495 | #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CNTL_DEFAULT 0x00000000 |
1496 | #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CAP_DEFAULT 0x00000000 |
1497 | #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CNTL_DEFAULT 0x00000000 |
1498 | #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CAP_DEFAULT 0x00000000 |
1499 | #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CNTL_DEFAULT 0x00000000 |
1500 | #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CAP_DEFAULT 0x00000000 |
1501 | #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CNTL_DEFAULT 0x00000000 |
1502 | #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000 |
1503 | #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000 |
1504 | #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000 |
1505 | #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000 |
1506 | #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000 |
1507 | #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP_DEFAULT 0x00000000 |
1508 | #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000 |
1509 | #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_DPA_STATUS_DEFAULT 0x00000100 |
1510 | #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_DPA_CNTL_DEFAULT 0x00000000 |
1511 | #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000 |
1512 | #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000 |
1513 | #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000 |
1514 | #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000 |
1515 | #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000 |
1516 | #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000 |
1517 | #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000 |
1518 | #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000 |
1519 | #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000 |
1520 | #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP_DEFAULT 0x00000000 |
1521 | #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL_DEFAULT 0x00000000 |
1522 | #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000 |
1523 | #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_ARI_CAP_DEFAULT 0x00000000 |
1524 | #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_ARI_CNTL_DEFAULT 0x00000000 |
1525 | |
1526 | |
1527 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf7_bifcfgdecp |
1528 | #define cfgBIF_CFG_DEV0_EPF7_0_VENDOR_ID_DEFAULT 0x00000000 |
1529 | #define cfgBIF_CFG_DEV0_EPF7_0_DEVICE_ID_DEFAULT 0x00000000 |
1530 | #define cfgBIF_CFG_DEV0_EPF7_0_COMMAND_DEFAULT 0x00000000 |
1531 | #define cfgBIF_CFG_DEV0_EPF7_0_STATUS_DEFAULT 0x00000000 |
1532 | #define cfgBIF_CFG_DEV0_EPF7_0_REVISION_ID_DEFAULT 0x00000000 |
1533 | #define cfgBIF_CFG_DEV0_EPF7_0_PROG_INTERFACE_DEFAULT 0x00000000 |
1534 | #define cfgBIF_CFG_DEV0_EPF7_0_SUB_CLASS_DEFAULT 0x00000000 |
1535 | #define cfgBIF_CFG_DEV0_EPF7_0_BASE_CLASS_DEFAULT 0x00000000 |
1536 | #define cfgBIF_CFG_DEV0_EPF7_0_CACHE_LINE_DEFAULT 0x00000000 |
1537 | #define cfgBIF_CFG_DEV0_EPF7_0_LATENCY_DEFAULT 0x00000000 |
1538 | #define 0x00000000 |
1539 | #define cfgBIF_CFG_DEV0_EPF7_0_BIST_DEFAULT 0x00000000 |
1540 | #define cfgBIF_CFG_DEV0_EPF7_0_BASE_ADDR_1_DEFAULT 0x00000000 |
1541 | #define cfgBIF_CFG_DEV0_EPF7_0_BASE_ADDR_2_DEFAULT 0x00000000 |
1542 | #define cfgBIF_CFG_DEV0_EPF7_0_BASE_ADDR_3_DEFAULT 0x00000000 |
1543 | #define cfgBIF_CFG_DEV0_EPF7_0_BASE_ADDR_4_DEFAULT 0x00000000 |
1544 | #define cfgBIF_CFG_DEV0_EPF7_0_BASE_ADDR_5_DEFAULT 0x00000000 |
1545 | #define cfgBIF_CFG_DEV0_EPF7_0_BASE_ADDR_6_DEFAULT 0x00000000 |
1546 | #define cfgBIF_CFG_DEV0_EPF7_0_ADAPTER_ID_DEFAULT 0x00000000 |
1547 | #define cfgBIF_CFG_DEV0_EPF7_0_ROM_BASE_ADDR_DEFAULT 0x00000000 |
1548 | #define cfgBIF_CFG_DEV0_EPF7_0_CAP_PTR_DEFAULT 0x00000000 |
1549 | #define cfgBIF_CFG_DEV0_EPF7_0_INTERRUPT_LINE_DEFAULT 0x00000000 |
1550 | #define cfgBIF_CFG_DEV0_EPF7_0_INTERRUPT_PIN_DEFAULT 0x00000000 |
1551 | #define cfgBIF_CFG_DEV0_EPF7_0_MIN_GRANT_DEFAULT 0x00000000 |
1552 | #define cfgBIF_CFG_DEV0_EPF7_0_MAX_LATENCY_DEFAULT 0x00000000 |
1553 | #define cfgBIF_CFG_DEV0_EPF7_0_VENDOR_CAP_LIST_DEFAULT 0x00000000 |
1554 | #define cfgBIF_CFG_DEV0_EPF7_0_ADAPTER_ID_W_DEFAULT 0x00000000 |
1555 | #define cfgBIF_CFG_DEV0_EPF7_0_PMI_CAP_LIST_DEFAULT 0x00000000 |
1556 | #define cfgBIF_CFG_DEV0_EPF7_0_PMI_CAP_DEFAULT 0x00000000 |
1557 | #define cfgBIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL_DEFAULT 0x00000000 |
1558 | #define cfgBIF_CFG_DEV0_EPF7_0_SBRN_DEFAULT 0x00000000 |
1559 | #define cfgBIF_CFG_DEV0_EPF7_0_FLADJ_DEFAULT 0x00000020 |
1560 | #define cfgBIF_CFG_DEV0_EPF7_0_DBESL_DBESLD_DEFAULT 0x00000000 |
1561 | #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_CAP_LIST_DEFAULT 0x0000a000 |
1562 | #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_CAP_DEFAULT 0x00000002 |
1563 | #define cfgBIF_CFG_DEV0_EPF7_0_DEVICE_CAP_DEFAULT 0x10000000 |
1564 | #define cfgBIF_CFG_DEV0_EPF7_0_DEVICE_CNTL_DEFAULT 0x00002810 |
1565 | #define cfgBIF_CFG_DEV0_EPF7_0_DEVICE_STATUS_DEFAULT 0x00000000 |
1566 | #define cfgBIF_CFG_DEV0_EPF7_0_LINK_CAP_DEFAULT 0x00011c03 |
1567 | #define cfgBIF_CFG_DEV0_EPF7_0_LINK_CNTL_DEFAULT 0x00000000 |
1568 | #define cfgBIF_CFG_DEV0_EPF7_0_LINK_STATUS_DEFAULT 0x00000001 |
1569 | #define cfgBIF_CFG_DEV0_EPF7_0_DEVICE_CAP2_DEFAULT 0x00000000 |
1570 | #define cfgBIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2_DEFAULT 0x00000000 |
1571 | #define cfgBIF_CFG_DEV0_EPF7_0_DEVICE_STATUS2_DEFAULT 0x00000000 |
1572 | #define cfgBIF_CFG_DEV0_EPF7_0_LINK_CAP2_DEFAULT 0x0000000e |
1573 | #define cfgBIF_CFG_DEV0_EPF7_0_LINK_CNTL2_DEFAULT 0x00000003 |
1574 | #define cfgBIF_CFG_DEV0_EPF7_0_LINK_STATUS2_DEFAULT 0x00000000 |
1575 | #define cfgBIF_CFG_DEV0_EPF7_0_SLOT_CAP2_DEFAULT 0x00000000 |
1576 | #define cfgBIF_CFG_DEV0_EPF7_0_SLOT_CNTL2_DEFAULT 0x00000000 |
1577 | #define cfgBIF_CFG_DEV0_EPF7_0_SLOT_STATUS2_DEFAULT 0x00000000 |
1578 | #define cfgBIF_CFG_DEV0_EPF7_0_MSI_CAP_LIST_DEFAULT 0x0000c000 |
1579 | #define cfgBIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL_DEFAULT 0x00000080 |
1580 | #define cfgBIF_CFG_DEV0_EPF7_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 |
1581 | #define cfgBIF_CFG_DEV0_EPF7_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 |
1582 | #define cfgBIF_CFG_DEV0_EPF7_0_MSI_MSG_DATA_DEFAULT 0x00000000 |
1583 | #define cfgBIF_CFG_DEV0_EPF7_0_MSI_MASK_DEFAULT 0x00000000 |
1584 | #define cfgBIF_CFG_DEV0_EPF7_0_MSI_MSG_DATA_64_DEFAULT 0x00000000 |
1585 | #define cfgBIF_CFG_DEV0_EPF7_0_MSI_MASK_64_DEFAULT 0x00000000 |
1586 | #define cfgBIF_CFG_DEV0_EPF7_0_MSI_PENDING_DEFAULT 0x00000000 |
1587 | #define cfgBIF_CFG_DEV0_EPF7_0_MSI_PENDING_64_DEFAULT 0x00000000 |
1588 | #define cfgBIF_CFG_DEV0_EPF7_0_MSIX_CAP_LIST_DEFAULT 0x00000000 |
1589 | #define cfgBIF_CFG_DEV0_EPF7_0_MSIX_MSG_CNTL_DEFAULT 0x00000000 |
1590 | #define cfgBIF_CFG_DEV0_EPF7_0_MSIX_TABLE_DEFAULT 0x00000000 |
1591 | #define cfgBIF_CFG_DEV0_EPF7_0_MSIX_PBA_DEFAULT 0x00000000 |
1592 | #define cfgBIF_CFG_DEV0_EPF7_0_SATA_CAP_0_DEFAULT 0x00000000 |
1593 | #define cfgBIF_CFG_DEV0_EPF7_0_SATA_CAP_1_DEFAULT 0x00000000 |
1594 | #define cfgBIF_CFG_DEV0_EPF7_0_SATA_IDP_INDEX_DEFAULT 0x00000000 |
1595 | #define cfgBIF_CFG_DEV0_EPF7_0_SATA_IDP_DATA_DEFAULT 0x00000000 |
1596 | #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 |
1597 | #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 |
1598 | #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 |
1599 | #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 |
1600 | #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 |
1601 | #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 |
1602 | #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 |
1603 | #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 |
1604 | #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 |
1605 | #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000 |
1606 | #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 |
1607 | #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG0_DEFAULT 0x00000000 |
1608 | #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG1_DEFAULT 0x00000000 |
1609 | #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG2_DEFAULT 0x00000000 |
1610 | #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG3_DEFAULT 0x00000000 |
1611 | #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 |
1612 | #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 |
1613 | #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 |
1614 | #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 |
1615 | #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000 |
1616 | #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CAP_DEFAULT 0x00000000 |
1617 | #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CNTL_DEFAULT 0x00000020 |
1618 | #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CAP_DEFAULT 0x00000000 |
1619 | #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CNTL_DEFAULT 0x00000000 |
1620 | #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CAP_DEFAULT 0x00000000 |
1621 | #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CNTL_DEFAULT 0x00000000 |
1622 | #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CAP_DEFAULT 0x00000000 |
1623 | #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CNTL_DEFAULT 0x00000000 |
1624 | #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CAP_DEFAULT 0x00000000 |
1625 | #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CNTL_DEFAULT 0x00000000 |
1626 | #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CAP_DEFAULT 0x00000000 |
1627 | #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CNTL_DEFAULT 0x00000000 |
1628 | #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000 |
1629 | #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000 |
1630 | #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000 |
1631 | #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000 |
1632 | #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000 |
1633 | #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP_DEFAULT 0x00000000 |
1634 | #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000 |
1635 | #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_DPA_STATUS_DEFAULT 0x00000100 |
1636 | #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_DPA_CNTL_DEFAULT 0x00000000 |
1637 | #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000 |
1638 | #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000 |
1639 | #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000 |
1640 | #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000 |
1641 | #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000 |
1642 | #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000 |
1643 | #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000 |
1644 | #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000 |
1645 | #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000 |
1646 | #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP_DEFAULT 0x00000000 |
1647 | #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL_DEFAULT 0x00000000 |
1648 | #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000 |
1649 | #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_ARI_CAP_DEFAULT 0x00000000 |
1650 | #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_ARI_CNTL_DEFAULT 0x00000000 |
1651 | |
1652 | |
1653 | // addressBlock: nbio_nbif0_bif_cfg_dev1_epf0_bifcfgdecp |
1654 | #define cfgBIF_CFG_DEV1_EPF0_0_VENDOR_ID_DEFAULT 0x00000000 |
1655 | #define cfgBIF_CFG_DEV1_EPF0_0_DEVICE_ID_DEFAULT 0x00000000 |
1656 | #define cfgBIF_CFG_DEV1_EPF0_0_COMMAND_DEFAULT 0x00000000 |
1657 | #define cfgBIF_CFG_DEV1_EPF0_0_STATUS_DEFAULT 0x00000000 |
1658 | #define cfgBIF_CFG_DEV1_EPF0_0_REVISION_ID_DEFAULT 0x00000000 |
1659 | #define cfgBIF_CFG_DEV1_EPF0_0_PROG_INTERFACE_DEFAULT 0x00000000 |
1660 | #define cfgBIF_CFG_DEV1_EPF0_0_SUB_CLASS_DEFAULT 0x00000000 |
1661 | #define cfgBIF_CFG_DEV1_EPF0_0_BASE_CLASS_DEFAULT 0x00000000 |
1662 | #define cfgBIF_CFG_DEV1_EPF0_0_CACHE_LINE_DEFAULT 0x00000000 |
1663 | #define cfgBIF_CFG_DEV1_EPF0_0_LATENCY_DEFAULT 0x00000000 |
1664 | #define 0x00000000 |
1665 | #define cfgBIF_CFG_DEV1_EPF0_0_BIST_DEFAULT 0x00000000 |
1666 | #define cfgBIF_CFG_DEV1_EPF0_0_BASE_ADDR_1_DEFAULT 0x00000000 |
1667 | #define cfgBIF_CFG_DEV1_EPF0_0_BASE_ADDR_2_DEFAULT 0x00000000 |
1668 | #define cfgBIF_CFG_DEV1_EPF0_0_BASE_ADDR_3_DEFAULT 0x00000000 |
1669 | #define cfgBIF_CFG_DEV1_EPF0_0_BASE_ADDR_4_DEFAULT 0x00000000 |
1670 | #define cfgBIF_CFG_DEV1_EPF0_0_BASE_ADDR_5_DEFAULT 0x00000000 |
1671 | #define cfgBIF_CFG_DEV1_EPF0_0_BASE_ADDR_6_DEFAULT 0x00000000 |
1672 | #define cfgBIF_CFG_DEV1_EPF0_0_ADAPTER_ID_DEFAULT 0x00000000 |
1673 | #define cfgBIF_CFG_DEV1_EPF0_0_ROM_BASE_ADDR_DEFAULT 0x00000000 |
1674 | #define cfgBIF_CFG_DEV1_EPF0_0_CAP_PTR_DEFAULT 0x00000000 |
1675 | #define cfgBIF_CFG_DEV1_EPF0_0_INTERRUPT_LINE_DEFAULT 0x00000000 |
1676 | #define cfgBIF_CFG_DEV1_EPF0_0_INTERRUPT_PIN_DEFAULT 0x00000000 |
1677 | #define cfgBIF_CFG_DEV1_EPF0_0_MIN_GRANT_DEFAULT 0x00000000 |
1678 | #define cfgBIF_CFG_DEV1_EPF0_0_MAX_LATENCY_DEFAULT 0x00000000 |
1679 | #define cfgBIF_CFG_DEV1_EPF0_0_VENDOR_CAP_LIST_DEFAULT 0x00000000 |
1680 | #define cfgBIF_CFG_DEV1_EPF0_0_ADAPTER_ID_W_DEFAULT 0x00000000 |
1681 | #define cfgBIF_CFG_DEV1_EPF0_0_PMI_CAP_LIST_DEFAULT 0x00000000 |
1682 | #define cfgBIF_CFG_DEV1_EPF0_0_PMI_CAP_DEFAULT 0x00000000 |
1683 | #define cfgBIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL_DEFAULT 0x00000000 |
1684 | #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_CAP_LIST_DEFAULT 0x0000a000 |
1685 | #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_CAP_DEFAULT 0x00000002 |
1686 | #define cfgBIF_CFG_DEV1_EPF0_0_DEVICE_CAP_DEFAULT 0x10000000 |
1687 | #define cfgBIF_CFG_DEV1_EPF0_0_DEVICE_CNTL_DEFAULT 0x00002810 |
1688 | #define cfgBIF_CFG_DEV1_EPF0_0_DEVICE_STATUS_DEFAULT 0x00000000 |
1689 | #define cfgBIF_CFG_DEV1_EPF0_0_LINK_CAP_DEFAULT 0x00011c03 |
1690 | #define cfgBIF_CFG_DEV1_EPF0_0_LINK_CNTL_DEFAULT 0x00000000 |
1691 | #define cfgBIF_CFG_DEV1_EPF0_0_LINK_STATUS_DEFAULT 0x00000001 |
1692 | #define cfgBIF_CFG_DEV1_EPF0_0_DEVICE_CAP2_DEFAULT 0x00000000 |
1693 | #define cfgBIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2_DEFAULT 0x00000000 |
1694 | #define cfgBIF_CFG_DEV1_EPF0_0_DEVICE_STATUS2_DEFAULT 0x00000000 |
1695 | #define cfgBIF_CFG_DEV1_EPF0_0_LINK_CAP2_DEFAULT 0x0000000e |
1696 | #define cfgBIF_CFG_DEV1_EPF0_0_LINK_CNTL2_DEFAULT 0x00000003 |
1697 | #define cfgBIF_CFG_DEV1_EPF0_0_LINK_STATUS2_DEFAULT 0x00000000 |
1698 | #define cfgBIF_CFG_DEV1_EPF0_0_SLOT_CAP2_DEFAULT 0x00000000 |
1699 | #define cfgBIF_CFG_DEV1_EPF0_0_SLOT_CNTL2_DEFAULT 0x00000000 |
1700 | #define cfgBIF_CFG_DEV1_EPF0_0_SLOT_STATUS2_DEFAULT 0x00000000 |
1701 | #define cfgBIF_CFG_DEV1_EPF0_0_MSI_CAP_LIST_DEFAULT 0x0000c000 |
1702 | #define cfgBIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL_DEFAULT 0x00000080 |
1703 | #define cfgBIF_CFG_DEV1_EPF0_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 |
1704 | #define cfgBIF_CFG_DEV1_EPF0_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 |
1705 | #define cfgBIF_CFG_DEV1_EPF0_0_MSI_MSG_DATA_DEFAULT 0x00000000 |
1706 | #define cfgBIF_CFG_DEV1_EPF0_0_MSI_MASK_DEFAULT 0x00000000 |
1707 | #define cfgBIF_CFG_DEV1_EPF0_0_MSI_MSG_DATA_64_DEFAULT 0x00000000 |
1708 | #define cfgBIF_CFG_DEV1_EPF0_0_MSI_MASK_64_DEFAULT 0x00000000 |
1709 | #define cfgBIF_CFG_DEV1_EPF0_0_MSI_PENDING_DEFAULT 0x00000000 |
1710 | #define cfgBIF_CFG_DEV1_EPF0_0_MSI_PENDING_64_DEFAULT 0x00000000 |
1711 | #define cfgBIF_CFG_DEV1_EPF0_0_MSIX_CAP_LIST_DEFAULT 0x00000000 |
1712 | #define cfgBIF_CFG_DEV1_EPF0_0_MSIX_MSG_CNTL_DEFAULT 0x00000000 |
1713 | #define cfgBIF_CFG_DEV1_EPF0_0_MSIX_TABLE_DEFAULT 0x00000000 |
1714 | #define cfgBIF_CFG_DEV1_EPF0_0_MSIX_PBA_DEFAULT 0x00000000 |
1715 | #define cfgBIF_CFG_DEV1_EPF0_0_SATA_CAP_0_DEFAULT 0x00000000 |
1716 | #define cfgBIF_CFG_DEV1_EPF0_0_SATA_CAP_1_DEFAULT 0x00000000 |
1717 | #define cfgBIF_CFG_DEV1_EPF0_0_SATA_IDP_INDEX_DEFAULT 0x00000000 |
1718 | #define cfgBIF_CFG_DEV1_EPF0_0_SATA_IDP_DATA_DEFAULT 0x00000000 |
1719 | #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 |
1720 | #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 |
1721 | #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 |
1722 | #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 |
1723 | #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000 |
1724 | #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000 |
1725 | #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000 |
1726 | #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000 |
1727 | #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000 |
1728 | #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000 |
1729 | #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe |
1730 | #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000000 |
1731 | #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000 |
1732 | #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000 |
1733 | #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000000 |
1734 | #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 |
1735 | #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 |
1736 | #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 |
1737 | #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 |
1738 | #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 |
1739 | #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000 |
1740 | #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 |
1741 | #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG0_DEFAULT 0x00000000 |
1742 | #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG1_DEFAULT 0x00000000 |
1743 | #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG2_DEFAULT 0x00000000 |
1744 | #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG3_DEFAULT 0x00000000 |
1745 | #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 |
1746 | #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 |
1747 | #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 |
1748 | #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 |
1749 | #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000 |
1750 | #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CAP_DEFAULT 0x00000000 |
1751 | #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CNTL_DEFAULT 0x00000020 |
1752 | #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CAP_DEFAULT 0x00000000 |
1753 | #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CNTL_DEFAULT 0x00000000 |
1754 | #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CAP_DEFAULT 0x00000000 |
1755 | #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CNTL_DEFAULT 0x00000000 |
1756 | #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CAP_DEFAULT 0x00000000 |
1757 | #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CNTL_DEFAULT 0x00000000 |
1758 | #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CAP_DEFAULT 0x00000000 |
1759 | #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CNTL_DEFAULT 0x00000000 |
1760 | #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CAP_DEFAULT 0x00000000 |
1761 | #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CNTL_DEFAULT 0x00000000 |
1762 | #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000 |
1763 | #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000 |
1764 | #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000 |
1765 | #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000 |
1766 | #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000 |
1767 | #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP_DEFAULT 0x00000000 |
1768 | #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000 |
1769 | #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_DPA_STATUS_DEFAULT 0x00000100 |
1770 | #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_DPA_CNTL_DEFAULT 0x00000000 |
1771 | #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000 |
1772 | #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000 |
1773 | #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000 |
1774 | #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000 |
1775 | #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000 |
1776 | #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000 |
1777 | #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000 |
1778 | #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000 |
1779 | #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a010019 |
1780 | #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LINK_CNTL3_DEFAULT 0x00000000 |
1781 | #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000 |
1782 | #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
1783 | #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
1784 | #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
1785 | #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
1786 | #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
1787 | #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
1788 | #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
1789 | #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
1790 | #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
1791 | #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
1792 | #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
1793 | #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
1794 | #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
1795 | #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
1796 | #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
1797 | #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
1798 | #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000 |
1799 | #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP_DEFAULT 0x00000000 |
1800 | #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL_DEFAULT 0x00000000 |
1801 | #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LTR_ENH_CAP_LIST_DEFAULT 0x32800000 |
1802 | #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LTR_CAP_DEFAULT 0x00000000 |
1803 | #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000 |
1804 | #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_ARI_CAP_DEFAULT 0x00000000 |
1805 | #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_ARI_CNTL_DEFAULT 0x00000000 |
1806 | |
1807 | |
1808 | // addressBlock: nbio_nbif0_bif_cfg_dev1_epf1_bifcfgdecp |
1809 | #define cfgBIF_CFG_DEV1_EPF1_0_VENDOR_ID_DEFAULT 0x00000000 |
1810 | #define cfgBIF_CFG_DEV1_EPF1_0_DEVICE_ID_DEFAULT 0x00000000 |
1811 | #define cfgBIF_CFG_DEV1_EPF1_0_COMMAND_DEFAULT 0x00000000 |
1812 | #define cfgBIF_CFG_DEV1_EPF1_0_STATUS_DEFAULT 0x00000000 |
1813 | #define cfgBIF_CFG_DEV1_EPF1_0_REVISION_ID_DEFAULT 0x00000000 |
1814 | #define cfgBIF_CFG_DEV1_EPF1_0_PROG_INTERFACE_DEFAULT 0x00000000 |
1815 | #define cfgBIF_CFG_DEV1_EPF1_0_SUB_CLASS_DEFAULT 0x00000000 |
1816 | #define cfgBIF_CFG_DEV1_EPF1_0_BASE_CLASS_DEFAULT 0x00000000 |
1817 | #define cfgBIF_CFG_DEV1_EPF1_0_CACHE_LINE_DEFAULT 0x00000000 |
1818 | #define cfgBIF_CFG_DEV1_EPF1_0_LATENCY_DEFAULT 0x00000000 |
1819 | #define 0x00000000 |
1820 | #define cfgBIF_CFG_DEV1_EPF1_0_BIST_DEFAULT 0x00000000 |
1821 | #define cfgBIF_CFG_DEV1_EPF1_0_BASE_ADDR_1_DEFAULT 0x00000000 |
1822 | #define cfgBIF_CFG_DEV1_EPF1_0_BASE_ADDR_2_DEFAULT 0x00000000 |
1823 | #define cfgBIF_CFG_DEV1_EPF1_0_BASE_ADDR_3_DEFAULT 0x00000000 |
1824 | #define cfgBIF_CFG_DEV1_EPF1_0_BASE_ADDR_4_DEFAULT 0x00000000 |
1825 | #define cfgBIF_CFG_DEV1_EPF1_0_BASE_ADDR_5_DEFAULT 0x00000000 |
1826 | #define cfgBIF_CFG_DEV1_EPF1_0_BASE_ADDR_6_DEFAULT 0x00000000 |
1827 | #define cfgBIF_CFG_DEV1_EPF1_0_ADAPTER_ID_DEFAULT 0x00000000 |
1828 | #define cfgBIF_CFG_DEV1_EPF1_0_ROM_BASE_ADDR_DEFAULT 0x00000000 |
1829 | #define cfgBIF_CFG_DEV1_EPF1_0_CAP_PTR_DEFAULT 0x00000000 |
1830 | #define cfgBIF_CFG_DEV1_EPF1_0_INTERRUPT_LINE_DEFAULT 0x00000000 |
1831 | #define cfgBIF_CFG_DEV1_EPF1_0_INTERRUPT_PIN_DEFAULT 0x00000000 |
1832 | #define cfgBIF_CFG_DEV1_EPF1_0_MIN_GRANT_DEFAULT 0x00000000 |
1833 | #define cfgBIF_CFG_DEV1_EPF1_0_MAX_LATENCY_DEFAULT 0x00000000 |
1834 | #define cfgBIF_CFG_DEV1_EPF1_0_VENDOR_CAP_LIST_DEFAULT 0x00000000 |
1835 | #define cfgBIF_CFG_DEV1_EPF1_0_ADAPTER_ID_W_DEFAULT 0x00000000 |
1836 | #define cfgBIF_CFG_DEV1_EPF1_0_PMI_CAP_LIST_DEFAULT 0x00000000 |
1837 | #define cfgBIF_CFG_DEV1_EPF1_0_PMI_CAP_DEFAULT 0x00000000 |
1838 | #define cfgBIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL_DEFAULT 0x00000000 |
1839 | #define cfgBIF_CFG_DEV1_EPF1_0_SBRN_DEFAULT 0x00000000 |
1840 | #define cfgBIF_CFG_DEV1_EPF1_0_FLADJ_DEFAULT 0x00000020 |
1841 | #define cfgBIF_CFG_DEV1_EPF1_0_DBESL_DBESLD_DEFAULT 0x00000000 |
1842 | #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_CAP_LIST_DEFAULT 0x0000a000 |
1843 | #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_CAP_DEFAULT 0x00000002 |
1844 | #define cfgBIF_CFG_DEV1_EPF1_0_DEVICE_CAP_DEFAULT 0x10000000 |
1845 | #define cfgBIF_CFG_DEV1_EPF1_0_DEVICE_CNTL_DEFAULT 0x00002810 |
1846 | #define cfgBIF_CFG_DEV1_EPF1_0_DEVICE_STATUS_DEFAULT 0x00000000 |
1847 | #define cfgBIF_CFG_DEV1_EPF1_0_LINK_CAP_DEFAULT 0x00011c03 |
1848 | #define cfgBIF_CFG_DEV1_EPF1_0_LINK_CNTL_DEFAULT 0x00000000 |
1849 | #define cfgBIF_CFG_DEV1_EPF1_0_LINK_STATUS_DEFAULT 0x00000001 |
1850 | #define cfgBIF_CFG_DEV1_EPF1_0_DEVICE_CAP2_DEFAULT 0x00000000 |
1851 | #define cfgBIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2_DEFAULT 0x00000000 |
1852 | #define cfgBIF_CFG_DEV1_EPF1_0_DEVICE_STATUS2_DEFAULT 0x00000000 |
1853 | #define cfgBIF_CFG_DEV1_EPF1_0_LINK_CAP2_DEFAULT 0x0000000e |
1854 | #define cfgBIF_CFG_DEV1_EPF1_0_LINK_CNTL2_DEFAULT 0x00000003 |
1855 | #define cfgBIF_CFG_DEV1_EPF1_0_LINK_STATUS2_DEFAULT 0x00000000 |
1856 | #define cfgBIF_CFG_DEV1_EPF1_0_SLOT_CAP2_DEFAULT 0x00000000 |
1857 | #define cfgBIF_CFG_DEV1_EPF1_0_SLOT_CNTL2_DEFAULT 0x00000000 |
1858 | #define cfgBIF_CFG_DEV1_EPF1_0_SLOT_STATUS2_DEFAULT 0x00000000 |
1859 | #define cfgBIF_CFG_DEV1_EPF1_0_MSI_CAP_LIST_DEFAULT 0x0000c000 |
1860 | #define cfgBIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL_DEFAULT 0x00000080 |
1861 | #define cfgBIF_CFG_DEV1_EPF1_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 |
1862 | #define cfgBIF_CFG_DEV1_EPF1_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 |
1863 | #define cfgBIF_CFG_DEV1_EPF1_0_MSI_MSG_DATA_DEFAULT 0x00000000 |
1864 | #define cfgBIF_CFG_DEV1_EPF1_0_MSI_MASK_DEFAULT 0x00000000 |
1865 | #define cfgBIF_CFG_DEV1_EPF1_0_MSI_MSG_DATA_64_DEFAULT 0x00000000 |
1866 | #define cfgBIF_CFG_DEV1_EPF1_0_MSI_MASK_64_DEFAULT 0x00000000 |
1867 | #define cfgBIF_CFG_DEV1_EPF1_0_MSI_PENDING_DEFAULT 0x00000000 |
1868 | #define cfgBIF_CFG_DEV1_EPF1_0_MSI_PENDING_64_DEFAULT 0x00000000 |
1869 | #define cfgBIF_CFG_DEV1_EPF1_0_MSIX_CAP_LIST_DEFAULT 0x00000000 |
1870 | #define cfgBIF_CFG_DEV1_EPF1_0_MSIX_MSG_CNTL_DEFAULT 0x00000000 |
1871 | #define cfgBIF_CFG_DEV1_EPF1_0_MSIX_TABLE_DEFAULT 0x00000000 |
1872 | #define cfgBIF_CFG_DEV1_EPF1_0_MSIX_PBA_DEFAULT 0x00000000 |
1873 | #define cfgBIF_CFG_DEV1_EPF1_0_SATA_CAP_0_DEFAULT 0x00000000 |
1874 | #define cfgBIF_CFG_DEV1_EPF1_0_SATA_CAP_1_DEFAULT 0x00000000 |
1875 | #define cfgBIF_CFG_DEV1_EPF1_0_SATA_IDP_INDEX_DEFAULT 0x00000000 |
1876 | #define cfgBIF_CFG_DEV1_EPF1_0_SATA_IDP_DATA_DEFAULT 0x00000000 |
1877 | #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 |
1878 | #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 |
1879 | #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 |
1880 | #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 |
1881 | #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 |
1882 | #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 |
1883 | #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 |
1884 | #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 |
1885 | #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 |
1886 | #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000 |
1887 | #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 |
1888 | #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG0_DEFAULT 0x00000000 |
1889 | #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG1_DEFAULT 0x00000000 |
1890 | #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG2_DEFAULT 0x00000000 |
1891 | #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG3_DEFAULT 0x00000000 |
1892 | #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 |
1893 | #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 |
1894 | #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 |
1895 | #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 |
1896 | #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000 |
1897 | #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CAP_DEFAULT 0x00000000 |
1898 | #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CNTL_DEFAULT 0x00000020 |
1899 | #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CAP_DEFAULT 0x00000000 |
1900 | #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CNTL_DEFAULT 0x00000000 |
1901 | #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CAP_DEFAULT 0x00000000 |
1902 | #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CNTL_DEFAULT 0x00000000 |
1903 | #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CAP_DEFAULT 0x00000000 |
1904 | #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CNTL_DEFAULT 0x00000000 |
1905 | #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CAP_DEFAULT 0x00000000 |
1906 | #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CNTL_DEFAULT 0x00000000 |
1907 | #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CAP_DEFAULT 0x00000000 |
1908 | #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CNTL_DEFAULT 0x00000000 |
1909 | #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000 |
1910 | #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000 |
1911 | #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000 |
1912 | #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000 |
1913 | #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000 |
1914 | #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP_DEFAULT 0x00000000 |
1915 | #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000 |
1916 | #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_DPA_STATUS_DEFAULT 0x00000100 |
1917 | #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_DPA_CNTL_DEFAULT 0x00000000 |
1918 | #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000 |
1919 | #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000 |
1920 | #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000 |
1921 | #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000 |
1922 | #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000 |
1923 | #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000 |
1924 | #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000 |
1925 | #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000 |
1926 | #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000 |
1927 | #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP_DEFAULT 0x00000000 |
1928 | #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL_DEFAULT 0x00000000 |
1929 | #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000 |
1930 | #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_ARI_CAP_DEFAULT 0x00000000 |
1931 | #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_ARI_CNTL_DEFAULT 0x00000000 |
1932 | |
1933 | |
1934 | // addressBlock: nbio_nbif0_bif_cfg_dev1_epf2_bifcfgdecp |
1935 | #define cfgBIF_CFG_DEV1_EPF2_0_VENDOR_ID_DEFAULT 0x00000000 |
1936 | #define cfgBIF_CFG_DEV1_EPF2_0_DEVICE_ID_DEFAULT 0x00000000 |
1937 | #define cfgBIF_CFG_DEV1_EPF2_0_COMMAND_DEFAULT 0x00000000 |
1938 | #define cfgBIF_CFG_DEV1_EPF2_0_STATUS_DEFAULT 0x00000000 |
1939 | #define cfgBIF_CFG_DEV1_EPF2_0_REVISION_ID_DEFAULT 0x00000000 |
1940 | #define cfgBIF_CFG_DEV1_EPF2_0_PROG_INTERFACE_DEFAULT 0x00000000 |
1941 | #define cfgBIF_CFG_DEV1_EPF2_0_SUB_CLASS_DEFAULT 0x00000000 |
1942 | #define cfgBIF_CFG_DEV1_EPF2_0_BASE_CLASS_DEFAULT 0x00000000 |
1943 | #define cfgBIF_CFG_DEV1_EPF2_0_CACHE_LINE_DEFAULT 0x00000000 |
1944 | #define cfgBIF_CFG_DEV1_EPF2_0_LATENCY_DEFAULT 0x00000000 |
1945 | #define 0x00000000 |
1946 | #define cfgBIF_CFG_DEV1_EPF2_0_BIST_DEFAULT 0x00000000 |
1947 | #define cfgBIF_CFG_DEV1_EPF2_0_BASE_ADDR_1_DEFAULT 0x00000000 |
1948 | #define cfgBIF_CFG_DEV1_EPF2_0_BASE_ADDR_2_DEFAULT 0x00000000 |
1949 | #define cfgBIF_CFG_DEV1_EPF2_0_BASE_ADDR_3_DEFAULT 0x00000000 |
1950 | #define cfgBIF_CFG_DEV1_EPF2_0_BASE_ADDR_4_DEFAULT 0x00000000 |
1951 | #define cfgBIF_CFG_DEV1_EPF2_0_BASE_ADDR_5_DEFAULT 0x00000000 |
1952 | #define cfgBIF_CFG_DEV1_EPF2_0_BASE_ADDR_6_DEFAULT 0x00000000 |
1953 | #define cfgBIF_CFG_DEV1_EPF2_0_ADAPTER_ID_DEFAULT 0x00000000 |
1954 | #define cfgBIF_CFG_DEV1_EPF2_0_ROM_BASE_ADDR_DEFAULT 0x00000000 |
1955 | #define cfgBIF_CFG_DEV1_EPF2_0_CAP_PTR_DEFAULT 0x00000000 |
1956 | #define cfgBIF_CFG_DEV1_EPF2_0_INTERRUPT_LINE_DEFAULT 0x00000000 |
1957 | #define cfgBIF_CFG_DEV1_EPF2_0_INTERRUPT_PIN_DEFAULT 0x00000000 |
1958 | #define cfgBIF_CFG_DEV1_EPF2_0_MIN_GRANT_DEFAULT 0x00000000 |
1959 | #define cfgBIF_CFG_DEV1_EPF2_0_MAX_LATENCY_DEFAULT 0x00000000 |
1960 | #define cfgBIF_CFG_DEV1_EPF2_0_VENDOR_CAP_LIST_DEFAULT 0x00000000 |
1961 | #define cfgBIF_CFG_DEV1_EPF2_0_ADAPTER_ID_W_DEFAULT 0x00000000 |
1962 | #define cfgBIF_CFG_DEV1_EPF2_0_PMI_CAP_LIST_DEFAULT 0x00000000 |
1963 | #define cfgBIF_CFG_DEV1_EPF2_0_PMI_CAP_DEFAULT 0x00000000 |
1964 | #define cfgBIF_CFG_DEV1_EPF2_0_PMI_STATUS_CNTL_DEFAULT 0x00000000 |
1965 | #define cfgBIF_CFG_DEV1_EPF2_0_SBRN_DEFAULT 0x00000000 |
1966 | #define cfgBIF_CFG_DEV1_EPF2_0_FLADJ_DEFAULT 0x00000020 |
1967 | #define cfgBIF_CFG_DEV1_EPF2_0_DBESL_DBESLD_DEFAULT 0x00000000 |
1968 | #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_CAP_LIST_DEFAULT 0x0000a000 |
1969 | #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_CAP_DEFAULT 0x00000002 |
1970 | #define cfgBIF_CFG_DEV1_EPF2_0_DEVICE_CAP_DEFAULT 0x10000000 |
1971 | #define cfgBIF_CFG_DEV1_EPF2_0_DEVICE_CNTL_DEFAULT 0x00002810 |
1972 | #define cfgBIF_CFG_DEV1_EPF2_0_DEVICE_STATUS_DEFAULT 0x00000000 |
1973 | #define cfgBIF_CFG_DEV1_EPF2_0_LINK_CAP_DEFAULT 0x00011c03 |
1974 | #define cfgBIF_CFG_DEV1_EPF2_0_LINK_CNTL_DEFAULT 0x00000000 |
1975 | #define cfgBIF_CFG_DEV1_EPF2_0_LINK_STATUS_DEFAULT 0x00000001 |
1976 | #define cfgBIF_CFG_DEV1_EPF2_0_DEVICE_CAP2_DEFAULT 0x00000000 |
1977 | #define cfgBIF_CFG_DEV1_EPF2_0_DEVICE_CNTL2_DEFAULT 0x00000000 |
1978 | #define cfgBIF_CFG_DEV1_EPF2_0_DEVICE_STATUS2_DEFAULT 0x00000000 |
1979 | #define cfgBIF_CFG_DEV1_EPF2_0_LINK_CAP2_DEFAULT 0x0000000e |
1980 | #define cfgBIF_CFG_DEV1_EPF2_0_LINK_CNTL2_DEFAULT 0x00000003 |
1981 | #define cfgBIF_CFG_DEV1_EPF2_0_LINK_STATUS2_DEFAULT 0x00000000 |
1982 | #define cfgBIF_CFG_DEV1_EPF2_0_SLOT_CAP2_DEFAULT 0x00000000 |
1983 | #define cfgBIF_CFG_DEV1_EPF2_0_SLOT_CNTL2_DEFAULT 0x00000000 |
1984 | #define cfgBIF_CFG_DEV1_EPF2_0_SLOT_STATUS2_DEFAULT 0x00000000 |
1985 | #define cfgBIF_CFG_DEV1_EPF2_0_MSI_CAP_LIST_DEFAULT 0x0000c000 |
1986 | #define cfgBIF_CFG_DEV1_EPF2_0_MSI_MSG_CNTL_DEFAULT 0x00000080 |
1987 | #define cfgBIF_CFG_DEV1_EPF2_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 |
1988 | #define cfgBIF_CFG_DEV1_EPF2_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 |
1989 | #define cfgBIF_CFG_DEV1_EPF2_0_MSI_MSG_DATA_DEFAULT 0x00000000 |
1990 | #define cfgBIF_CFG_DEV1_EPF2_0_MSI_MASK_DEFAULT 0x00000000 |
1991 | #define cfgBIF_CFG_DEV1_EPF2_0_MSI_MSG_DATA_64_DEFAULT 0x00000000 |
1992 | #define cfgBIF_CFG_DEV1_EPF2_0_MSI_MASK_64_DEFAULT 0x00000000 |
1993 | #define cfgBIF_CFG_DEV1_EPF2_0_MSI_PENDING_DEFAULT 0x00000000 |
1994 | #define cfgBIF_CFG_DEV1_EPF2_0_MSI_PENDING_64_DEFAULT 0x00000000 |
1995 | #define cfgBIF_CFG_DEV1_EPF2_0_MSIX_CAP_LIST_DEFAULT 0x00000000 |
1996 | #define cfgBIF_CFG_DEV1_EPF2_0_MSIX_MSG_CNTL_DEFAULT 0x00000000 |
1997 | #define cfgBIF_CFG_DEV1_EPF2_0_MSIX_TABLE_DEFAULT 0x00000000 |
1998 | #define cfgBIF_CFG_DEV1_EPF2_0_MSIX_PBA_DEFAULT 0x00000000 |
1999 | #define cfgBIF_CFG_DEV1_EPF2_0_SATA_CAP_0_DEFAULT 0x00000000 |
2000 | #define cfgBIF_CFG_DEV1_EPF2_0_SATA_CAP_1_DEFAULT 0x00000000 |
2001 | #define cfgBIF_CFG_DEV1_EPF2_0_SATA_IDP_INDEX_DEFAULT 0x00000000 |
2002 | #define cfgBIF_CFG_DEV1_EPF2_0_SATA_IDP_DATA_DEFAULT 0x00000000 |
2003 | #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 |
2004 | #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 |
2005 | #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 |
2006 | #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 |
2007 | #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 |
2008 | #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 |
2009 | #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 |
2010 | #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 |
2011 | #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 |
2012 | #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000 |
2013 | #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 |
2014 | #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_HDR_LOG0_DEFAULT 0x00000000 |
2015 | #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_HDR_LOG1_DEFAULT 0x00000000 |
2016 | #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_HDR_LOG2_DEFAULT 0x00000000 |
2017 | #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_HDR_LOG3_DEFAULT 0x00000000 |
2018 | #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 |
2019 | #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 |
2020 | #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 |
2021 | #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 |
2022 | #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000 |
2023 | #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_BAR1_CAP_DEFAULT 0x00000000 |
2024 | #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_BAR1_CNTL_DEFAULT 0x00000020 |
2025 | #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_BAR2_CAP_DEFAULT 0x00000000 |
2026 | #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_BAR2_CNTL_DEFAULT 0x00000000 |
2027 | #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_BAR3_CAP_DEFAULT 0x00000000 |
2028 | #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_BAR3_CNTL_DEFAULT 0x00000000 |
2029 | #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_BAR4_CAP_DEFAULT 0x00000000 |
2030 | #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_BAR4_CNTL_DEFAULT 0x00000000 |
2031 | #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_BAR5_CAP_DEFAULT 0x00000000 |
2032 | #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_BAR5_CNTL_DEFAULT 0x00000000 |
2033 | #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_BAR6_CAP_DEFAULT 0x00000000 |
2034 | #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_BAR6_CNTL_DEFAULT 0x00000000 |
2035 | #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000 |
2036 | #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000 |
2037 | #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000 |
2038 | #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000 |
2039 | #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000 |
2040 | #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_DPA_CAP_DEFAULT 0x00000000 |
2041 | #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000 |
2042 | #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_DPA_STATUS_DEFAULT 0x00000100 |
2043 | #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_DPA_CNTL_DEFAULT 0x00000000 |
2044 | #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000 |
2045 | #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000 |
2046 | #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000 |
2047 | #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000 |
2048 | #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000 |
2049 | #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000 |
2050 | #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000 |
2051 | #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000 |
2052 | #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000 |
2053 | #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_ACS_CAP_DEFAULT 0x00000000 |
2054 | #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_ACS_CNTL_DEFAULT 0x00000000 |
2055 | #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000 |
2056 | #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_ARI_CAP_DEFAULT 0x00000000 |
2057 | #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_ARI_CNTL_DEFAULT 0x00000000 |
2058 | |
2059 | |
2060 | // addressBlock: nbio_pcie0_bifplr0_cfgdecp |
2061 | #define cfgBIFPLR0_0_VENDOR_ID_DEFAULT 0x00000000 |
2062 | #define cfgBIFPLR0_0_DEVICE_ID_DEFAULT 0x00000000 |
2063 | #define cfgBIFPLR0_0_COMMAND_DEFAULT 0x00000000 |
2064 | #define cfgBIFPLR0_0_STATUS_DEFAULT 0x00000000 |
2065 | #define cfgBIFPLR0_0_REVISION_ID_DEFAULT 0x00000000 |
2066 | #define cfgBIFPLR0_0_PROG_INTERFACE_DEFAULT 0x00000000 |
2067 | #define cfgBIFPLR0_0_SUB_CLASS_DEFAULT 0x00000000 |
2068 | #define cfgBIFPLR0_0_BASE_CLASS_DEFAULT 0x00000000 |
2069 | #define cfgBIFPLR0_0_CACHE_LINE_DEFAULT 0x00000000 |
2070 | #define cfgBIFPLR0_0_LATENCY_DEFAULT 0x00000000 |
2071 | #define 0x00000000 |
2072 | #define cfgBIFPLR0_0_BIST_DEFAULT 0x00000000 |
2073 | #define cfgBIFPLR0_0_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 |
2074 | #define cfgBIFPLR0_0_IO_BASE_LIMIT_DEFAULT 0x00000000 |
2075 | #define cfgBIFPLR0_0_SECONDARY_STATUS_DEFAULT 0x00000000 |
2076 | #define cfgBIFPLR0_0_MEM_BASE_LIMIT_DEFAULT 0x00000000 |
2077 | #define cfgBIFPLR0_0_PREF_BASE_LIMIT_DEFAULT 0x00000000 |
2078 | #define cfgBIFPLR0_0_PREF_BASE_UPPER_DEFAULT 0x00000000 |
2079 | #define cfgBIFPLR0_0_PREF_LIMIT_UPPER_DEFAULT 0x00000000 |
2080 | #define cfgBIFPLR0_0_IO_BASE_LIMIT_HI_DEFAULT 0x00000000 |
2081 | #define cfgBIFPLR0_0_CAP_PTR_DEFAULT 0x00000000 |
2082 | #define cfgBIFPLR0_0_INTERRUPT_LINE_DEFAULT 0x000000ff |
2083 | #define cfgBIFPLR0_0_INTERRUPT_PIN_DEFAULT 0x00000000 |
2084 | #define cfgBIFPLR0_0_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000 |
2085 | #define cfgBIFPLR0_0_EXT_BRIDGE_CNTL_DEFAULT 0x00000000 |
2086 | #define cfgBIFPLR0_0_PMI_CAP_LIST_DEFAULT 0x00000000 |
2087 | #define cfgBIFPLR0_0_PMI_CAP_DEFAULT 0x00000000 |
2088 | #define cfgBIFPLR0_0_PMI_STATUS_CNTL_DEFAULT 0x00000000 |
2089 | #define cfgBIFPLR0_0_PCIE_CAP_LIST_DEFAULT 0x0000a000 |
2090 | #define cfgBIFPLR0_0_PCIE_CAP_DEFAULT 0x00000002 |
2091 | #define cfgBIFPLR0_0_DEVICE_CAP_DEFAULT 0x00000000 |
2092 | #define cfgBIFPLR0_0_DEVICE_CNTL_DEFAULT 0x00002810 |
2093 | #define cfgBIFPLR0_0_DEVICE_STATUS_DEFAULT 0x00000000 |
2094 | #define cfgBIFPLR0_0_LINK_CAP_DEFAULT 0x00011c03 |
2095 | #define cfgBIFPLR0_0_LINK_CNTL_DEFAULT 0x00000000 |
2096 | #define cfgBIFPLR0_0_LINK_STATUS_DEFAULT 0x00000001 |
2097 | #define cfgBIFPLR0_0_SLOT_CAP_DEFAULT 0x00000000 |
2098 | #define cfgBIFPLR0_0_SLOT_CNTL_DEFAULT 0x00000000 |
2099 | #define cfgBIFPLR0_0_SLOT_STATUS_DEFAULT 0x00000000 |
2100 | #define cfgBIFPLR0_0_ROOT_CNTL_DEFAULT 0x00000000 |
2101 | #define cfgBIFPLR0_0_ROOT_CAP_DEFAULT 0x00000000 |
2102 | #define cfgBIFPLR0_0_ROOT_STATUS_DEFAULT 0x00000000 |
2103 | #define cfgBIFPLR0_0_DEVICE_CAP2_DEFAULT 0x00000000 |
2104 | #define cfgBIFPLR0_0_DEVICE_CNTL2_DEFAULT 0x00000000 |
2105 | #define cfgBIFPLR0_0_DEVICE_STATUS2_DEFAULT 0x00000000 |
2106 | #define cfgBIFPLR0_0_LINK_CAP2_DEFAULT 0x0000000e |
2107 | #define cfgBIFPLR0_0_LINK_CNTL2_DEFAULT 0x00000003 |
2108 | #define cfgBIFPLR0_0_LINK_STATUS2_DEFAULT 0x00000000 |
2109 | #define cfgBIFPLR0_0_SLOT_CAP2_DEFAULT 0x00000000 |
2110 | #define cfgBIFPLR0_0_SLOT_CNTL2_DEFAULT 0x00000000 |
2111 | #define cfgBIFPLR0_0_SLOT_STATUS2_DEFAULT 0x00000000 |
2112 | #define cfgBIFPLR0_0_MSI_CAP_LIST_DEFAULT 0x0000c000 |
2113 | #define cfgBIFPLR0_0_MSI_MSG_CNTL_DEFAULT 0x00000000 |
2114 | #define cfgBIFPLR0_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 |
2115 | #define cfgBIFPLR0_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 |
2116 | #define cfgBIFPLR0_0_MSI_MSG_DATA_DEFAULT 0x00000000 |
2117 | #define cfgBIFPLR0_0_MSI_MSG_DATA_64_DEFAULT 0x00000000 |
2118 | #define cfgBIFPLR0_0_SSID_CAP_LIST_DEFAULT 0x0000c800 |
2119 | #define cfgBIFPLR0_0_SSID_CAP_DEFAULT 0x00000000 |
2120 | #define cfgBIFPLR0_0_MSI_MAP_CAP_LIST_DEFAULT 0x00000000 |
2121 | #define cfgBIFPLR0_0_MSI_MAP_CAP_DEFAULT 0x00000000 |
2122 | #define cfgBIFPLR0_0_MSI_MAP_ADDR_LO_DEFAULT 0x00000000 |
2123 | #define cfgBIFPLR0_0_MSI_MAP_ADDR_HI_DEFAULT 0x00000000 |
2124 | #define cfgBIFPLR0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 |
2125 | #define cfgBIFPLR0_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 |
2126 | #define cfgBIFPLR0_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 |
2127 | #define cfgBIFPLR0_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 |
2128 | #define cfgBIFPLR0_0_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000 |
2129 | #define cfgBIFPLR0_0_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000 |
2130 | #define cfgBIFPLR0_0_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000 |
2131 | #define cfgBIFPLR0_0_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000 |
2132 | #define cfgBIFPLR0_0_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000 |
2133 | #define cfgBIFPLR0_0_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000 |
2134 | #define cfgBIFPLR0_0_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe |
2135 | #define cfgBIFPLR0_0_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000002 |
2136 | #define cfgBIFPLR0_0_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000 |
2137 | #define cfgBIFPLR0_0_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000 |
2138 | #define cfgBIFPLR0_0_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000002 |
2139 | #define cfgBIFPLR0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000 |
2140 | #define cfgBIFPLR0_0_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000 |
2141 | #define cfgBIFPLR0_0_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000 |
2142 | #define cfgBIFPLR0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x27020000 |
2143 | #define cfgBIFPLR0_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 |
2144 | #define cfgBIFPLR0_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00400000 |
2145 | #define cfgBIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 |
2146 | #define cfgBIFPLR0_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 |
2147 | #define cfgBIFPLR0_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00006000 |
2148 | #define cfgBIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 |
2149 | #define cfgBIFPLR0_0_PCIE_HDR_LOG0_DEFAULT 0x00000000 |
2150 | #define cfgBIFPLR0_0_PCIE_HDR_LOG1_DEFAULT 0x00000000 |
2151 | #define cfgBIFPLR0_0_PCIE_HDR_LOG2_DEFAULT 0x00000000 |
2152 | #define cfgBIFPLR0_0_PCIE_HDR_LOG3_DEFAULT 0x00000000 |
2153 | #define cfgBIFPLR0_0_PCIE_ROOT_ERR_CMD_DEFAULT 0x00000000 |
2154 | #define cfgBIFPLR0_0_PCIE_ROOT_ERR_STATUS_DEFAULT 0x00000000 |
2155 | #define cfgBIFPLR0_0_PCIE_ERR_SRC_ID_DEFAULT 0x00000000 |
2156 | #define cfgBIFPLR0_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 |
2157 | #define cfgBIFPLR0_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 |
2158 | #define cfgBIFPLR0_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 |
2159 | #define cfgBIFPLR0_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 |
2160 | #define cfgBIFPLR0_0_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a000000 |
2161 | #define cfgBIFPLR0_0_PCIE_LINK_CNTL3_DEFAULT 0x00000000 |
2162 | #define cfgBIFPLR0_0_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000 |
2163 | #define cfgBIFPLR0_0_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
2164 | #define cfgBIFPLR0_0_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
2165 | #define cfgBIFPLR0_0_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
2166 | #define cfgBIFPLR0_0_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
2167 | #define cfgBIFPLR0_0_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
2168 | #define cfgBIFPLR0_0_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
2169 | #define cfgBIFPLR0_0_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
2170 | #define cfgBIFPLR0_0_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
2171 | #define cfgBIFPLR0_0_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
2172 | #define cfgBIFPLR0_0_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
2173 | #define cfgBIFPLR0_0_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
2174 | #define cfgBIFPLR0_0_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
2175 | #define cfgBIFPLR0_0_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
2176 | #define cfgBIFPLR0_0_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
2177 | #define cfgBIFPLR0_0_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
2178 | #define cfgBIFPLR0_0_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
2179 | #define cfgBIFPLR0_0_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2f000000 |
2180 | #define cfgBIFPLR0_0_PCIE_ACS_CAP_DEFAULT 0x00000000 |
2181 | #define cfgBIFPLR0_0_PCIE_ACS_CNTL_DEFAULT 0x00000000 |
2182 | #define cfgBIFPLR0_0_PCIE_MC_ENH_CAP_LIST_DEFAULT 0x32000000 |
2183 | #define cfgBIFPLR0_0_PCIE_MC_CAP_DEFAULT 0x00000000 |
2184 | #define cfgBIFPLR0_0_PCIE_MC_CNTL_DEFAULT 0x00000000 |
2185 | #define cfgBIFPLR0_0_PCIE_MC_ADDR0_DEFAULT 0x00000000 |
2186 | #define cfgBIFPLR0_0_PCIE_MC_ADDR1_DEFAULT 0x00000000 |
2187 | #define cfgBIFPLR0_0_PCIE_MC_RCV0_DEFAULT 0x00000000 |
2188 | #define cfgBIFPLR0_0_PCIE_MC_RCV1_DEFAULT 0x00000000 |
2189 | #define cfgBIFPLR0_0_PCIE_MC_BLOCK_ALL0_DEFAULT 0x00000000 |
2190 | #define cfgBIFPLR0_0_PCIE_MC_BLOCK_ALL1_DEFAULT 0x00000000 |
2191 | #define cfgBIFPLR0_0_PCIE_MC_BLOCK_UNTRANSLATED_0_DEFAULT 0x00000000 |
2192 | #define cfgBIFPLR0_0_PCIE_MC_BLOCK_UNTRANSLATED_1_DEFAULT 0x00000000 |
2193 | #define cfgBIFPLR0_0_PCIE_MC_OVERLAY_BAR0_DEFAULT 0x00000000 |
2194 | #define cfgBIFPLR0_0_PCIE_MC_OVERLAY_BAR1_DEFAULT 0x00000000 |
2195 | #define cfgBIFPLR0_0_PCIE_L1_PM_SUB_CAP_LIST_DEFAULT 0x00000000 |
2196 | #define cfgBIFPLR0_0_PCIE_L1_PM_SUB_CAP_DEFAULT 0x00000000 |
2197 | #define cfgBIFPLR0_0_PCIE_L1_PM_SUB_CNTL_DEFAULT 0x00000000 |
2198 | #define cfgBIFPLR0_0_PCIE_L1_PM_SUB_CNTL2_DEFAULT 0x00000028 |
2199 | #define cfgBIFPLR0_0_PCIE_DPC_ENH_CAP_LIST_DEFAULT 0x00000000 |
2200 | #define cfgBIFPLR0_0_PCIE_DPC_CAP_LIST_DEFAULT 0x00000000 |
2201 | #define cfgBIFPLR0_0_PCIE_DPC_CNTL_DEFAULT 0x00000000 |
2202 | #define cfgBIFPLR0_0_PCIE_DPC_STATUS_DEFAULT 0x00000000 |
2203 | #define cfgBIFPLR0_0_PCIE_DPC_ERROR_SOURCE_ID_DEFAULT 0x00000000 |
2204 | #define cfgBIFPLR0_0_PCIE_RP_PIO_STATUS_DEFAULT 0x00000000 |
2205 | #define cfgBIFPLR0_0_PCIE_RP_PIO_MASK_DEFAULT 0x00070707 |
2206 | #define cfgBIFPLR0_0_PCIE_RP_PIO_SEVERITY_DEFAULT 0x00000000 |
2207 | #define cfgBIFPLR0_0_PCIE_RP_PIO_SYSERROR_DEFAULT 0x00000000 |
2208 | #define cfgBIFPLR0_0_PCIE_RP_PIO_EXCEPTION_DEFAULT 0x00000000 |
2209 | #define cfgBIFPLR0_0_PCIE_RP_PIO_HDR_LOG0_DEFAULT 0x00000000 |
2210 | #define cfgBIFPLR0_0_PCIE_RP_PIO_HDR_LOG1_DEFAULT 0x00000000 |
2211 | #define cfgBIFPLR0_0_PCIE_RP_PIO_HDR_LOG2_DEFAULT 0x00000000 |
2212 | #define cfgBIFPLR0_0_PCIE_RP_PIO_HDR_LOG3_DEFAULT 0x00000000 |
2213 | #define cfgBIFPLR0_0_PCIE_RP_PIO_IMPSPEC_LOG_DEFAULT 0x00000000 |
2214 | #define cfgBIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG0_DEFAULT 0x00000000 |
2215 | #define cfgBIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG1_DEFAULT 0x00000000 |
2216 | #define cfgBIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG2_DEFAULT 0x00000000 |
2217 | #define cfgBIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG3_DEFAULT 0x00000000 |
2218 | #define cfgBIFPLR0_0_PCIE_ESM_CAP_LIST_DEFAULT 0x00000000 |
2219 | #define 0x00000000 |
2220 | #define 0x00000000 |
2221 | #define cfgBIFPLR0_0_PCIE_ESM_STATUS_DEFAULT 0x00000000 |
2222 | #define cfgBIFPLR0_0_PCIE_ESM_CTRL_DEFAULT 0x00000000 |
2223 | #define cfgBIFPLR0_0_PCIE_ESM_CAP_1_DEFAULT 0x00000000 |
2224 | #define cfgBIFPLR0_0_PCIE_ESM_CAP_2_DEFAULT 0x00000000 |
2225 | #define cfgBIFPLR0_0_PCIE_ESM_CAP_3_DEFAULT 0x00000000 |
2226 | #define cfgBIFPLR0_0_PCIE_ESM_CAP_4_DEFAULT 0x00000000 |
2227 | #define cfgBIFPLR0_0_PCIE_ESM_CAP_5_DEFAULT 0x00000000 |
2228 | #define cfgBIFPLR0_0_PCIE_ESM_CAP_6_DEFAULT 0x00000000 |
2229 | #define cfgBIFPLR0_0_PCIE_ESM_CAP_7_DEFAULT 0x00000000 |
2230 | |
2231 | |
2232 | // addressBlock: nbio_pcie0_bifplr1_cfgdecp |
2233 | #define cfgBIFPLR1_0_VENDOR_ID_DEFAULT 0x00000000 |
2234 | #define cfgBIFPLR1_0_DEVICE_ID_DEFAULT 0x00000000 |
2235 | #define cfgBIFPLR1_0_COMMAND_DEFAULT 0x00000000 |
2236 | #define cfgBIFPLR1_0_STATUS_DEFAULT 0x00000000 |
2237 | #define cfgBIFPLR1_0_REVISION_ID_DEFAULT 0x00000000 |
2238 | #define cfgBIFPLR1_0_PROG_INTERFACE_DEFAULT 0x00000000 |
2239 | #define cfgBIFPLR1_0_SUB_CLASS_DEFAULT 0x00000000 |
2240 | #define cfgBIFPLR1_0_BASE_CLASS_DEFAULT 0x00000000 |
2241 | #define cfgBIFPLR1_0_CACHE_LINE_DEFAULT 0x00000000 |
2242 | #define cfgBIFPLR1_0_LATENCY_DEFAULT 0x00000000 |
2243 | #define 0x00000000 |
2244 | #define cfgBIFPLR1_0_BIST_DEFAULT 0x00000000 |
2245 | #define cfgBIFPLR1_0_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 |
2246 | #define cfgBIFPLR1_0_IO_BASE_LIMIT_DEFAULT 0x00000000 |
2247 | #define cfgBIFPLR1_0_SECONDARY_STATUS_DEFAULT 0x00000000 |
2248 | #define cfgBIFPLR1_0_MEM_BASE_LIMIT_DEFAULT 0x00000000 |
2249 | #define cfgBIFPLR1_0_PREF_BASE_LIMIT_DEFAULT 0x00000000 |
2250 | #define cfgBIFPLR1_0_PREF_BASE_UPPER_DEFAULT 0x00000000 |
2251 | #define cfgBIFPLR1_0_PREF_LIMIT_UPPER_DEFAULT 0x00000000 |
2252 | #define cfgBIFPLR1_0_IO_BASE_LIMIT_HI_DEFAULT 0x00000000 |
2253 | #define cfgBIFPLR1_0_CAP_PTR_DEFAULT 0x00000000 |
2254 | #define cfgBIFPLR1_0_INTERRUPT_LINE_DEFAULT 0x000000ff |
2255 | #define cfgBIFPLR1_0_INTERRUPT_PIN_DEFAULT 0x00000000 |
2256 | #define cfgBIFPLR1_0_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000 |
2257 | #define cfgBIFPLR1_0_EXT_BRIDGE_CNTL_DEFAULT 0x00000000 |
2258 | #define cfgBIFPLR1_0_PMI_CAP_LIST_DEFAULT 0x00000000 |
2259 | #define cfgBIFPLR1_0_PMI_CAP_DEFAULT 0x00000000 |
2260 | #define cfgBIFPLR1_0_PMI_STATUS_CNTL_DEFAULT 0x00000000 |
2261 | #define cfgBIFPLR1_0_PCIE_CAP_LIST_DEFAULT 0x0000a000 |
2262 | #define cfgBIFPLR1_0_PCIE_CAP_DEFAULT 0x00000002 |
2263 | #define cfgBIFPLR1_0_DEVICE_CAP_DEFAULT 0x00000000 |
2264 | #define cfgBIFPLR1_0_DEVICE_CNTL_DEFAULT 0x00002810 |
2265 | #define cfgBIFPLR1_0_DEVICE_STATUS_DEFAULT 0x00000000 |
2266 | #define cfgBIFPLR1_0_LINK_CAP_DEFAULT 0x00011c03 |
2267 | #define cfgBIFPLR1_0_LINK_CNTL_DEFAULT 0x00000000 |
2268 | #define cfgBIFPLR1_0_LINK_STATUS_DEFAULT 0x00000001 |
2269 | #define cfgBIFPLR1_0_SLOT_CAP_DEFAULT 0x00000000 |
2270 | #define cfgBIFPLR1_0_SLOT_CNTL_DEFAULT 0x00000000 |
2271 | #define cfgBIFPLR1_0_SLOT_STATUS_DEFAULT 0x00000000 |
2272 | #define cfgBIFPLR1_0_ROOT_CNTL_DEFAULT 0x00000000 |
2273 | #define cfgBIFPLR1_0_ROOT_CAP_DEFAULT 0x00000000 |
2274 | #define cfgBIFPLR1_0_ROOT_STATUS_DEFAULT 0x00000000 |
2275 | #define cfgBIFPLR1_0_DEVICE_CAP2_DEFAULT 0x00000000 |
2276 | #define cfgBIFPLR1_0_DEVICE_CNTL2_DEFAULT 0x00000000 |
2277 | #define cfgBIFPLR1_0_DEVICE_STATUS2_DEFAULT 0x00000000 |
2278 | #define cfgBIFPLR1_0_LINK_CAP2_DEFAULT 0x0000000e |
2279 | #define cfgBIFPLR1_0_LINK_CNTL2_DEFAULT 0x00000003 |
2280 | #define cfgBIFPLR1_0_LINK_STATUS2_DEFAULT 0x00000000 |
2281 | #define cfgBIFPLR1_0_SLOT_CAP2_DEFAULT 0x00000000 |
2282 | #define cfgBIFPLR1_0_SLOT_CNTL2_DEFAULT 0x00000000 |
2283 | #define cfgBIFPLR1_0_SLOT_STATUS2_DEFAULT 0x00000000 |
2284 | #define cfgBIFPLR1_0_MSI_CAP_LIST_DEFAULT 0x0000c000 |
2285 | #define cfgBIFPLR1_0_MSI_MSG_CNTL_DEFAULT 0x00000000 |
2286 | #define cfgBIFPLR1_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 |
2287 | #define cfgBIFPLR1_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 |
2288 | #define cfgBIFPLR1_0_MSI_MSG_DATA_DEFAULT 0x00000000 |
2289 | #define cfgBIFPLR1_0_MSI_MSG_DATA_64_DEFAULT 0x00000000 |
2290 | #define cfgBIFPLR1_0_SSID_CAP_LIST_DEFAULT 0x0000c800 |
2291 | #define cfgBIFPLR1_0_SSID_CAP_DEFAULT 0x00000000 |
2292 | #define cfgBIFPLR1_0_MSI_MAP_CAP_LIST_DEFAULT 0x00000000 |
2293 | #define cfgBIFPLR1_0_MSI_MAP_CAP_DEFAULT 0x00000000 |
2294 | #define cfgBIFPLR1_0_MSI_MAP_ADDR_LO_DEFAULT 0x00000000 |
2295 | #define cfgBIFPLR1_0_MSI_MAP_ADDR_HI_DEFAULT 0x00000000 |
2296 | #define cfgBIFPLR1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 |
2297 | #define cfgBIFPLR1_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 |
2298 | #define cfgBIFPLR1_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 |
2299 | #define cfgBIFPLR1_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 |
2300 | #define cfgBIFPLR1_0_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000 |
2301 | #define cfgBIFPLR1_0_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000 |
2302 | #define cfgBIFPLR1_0_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000 |
2303 | #define cfgBIFPLR1_0_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000 |
2304 | #define cfgBIFPLR1_0_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000 |
2305 | #define cfgBIFPLR1_0_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000 |
2306 | #define cfgBIFPLR1_0_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe |
2307 | #define cfgBIFPLR1_0_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000002 |
2308 | #define cfgBIFPLR1_0_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000 |
2309 | #define cfgBIFPLR1_0_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000 |
2310 | #define cfgBIFPLR1_0_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000002 |
2311 | #define cfgBIFPLR1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000 |
2312 | #define cfgBIFPLR1_0_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000 |
2313 | #define cfgBIFPLR1_0_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000 |
2314 | #define cfgBIFPLR1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x27020000 |
2315 | #define cfgBIFPLR1_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 |
2316 | #define cfgBIFPLR1_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00400000 |
2317 | #define cfgBIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 |
2318 | #define cfgBIFPLR1_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 |
2319 | #define cfgBIFPLR1_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00006000 |
2320 | #define cfgBIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 |
2321 | #define cfgBIFPLR1_0_PCIE_HDR_LOG0_DEFAULT 0x00000000 |
2322 | #define cfgBIFPLR1_0_PCIE_HDR_LOG1_DEFAULT 0x00000000 |
2323 | #define cfgBIFPLR1_0_PCIE_HDR_LOG2_DEFAULT 0x00000000 |
2324 | #define cfgBIFPLR1_0_PCIE_HDR_LOG3_DEFAULT 0x00000000 |
2325 | #define cfgBIFPLR1_0_PCIE_ROOT_ERR_CMD_DEFAULT 0x00000000 |
2326 | #define cfgBIFPLR1_0_PCIE_ROOT_ERR_STATUS_DEFAULT 0x00000000 |
2327 | #define cfgBIFPLR1_0_PCIE_ERR_SRC_ID_DEFAULT 0x00000000 |
2328 | #define cfgBIFPLR1_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 |
2329 | #define cfgBIFPLR1_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 |
2330 | #define cfgBIFPLR1_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 |
2331 | #define cfgBIFPLR1_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 |
2332 | #define cfgBIFPLR1_0_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a000000 |
2333 | #define cfgBIFPLR1_0_PCIE_LINK_CNTL3_DEFAULT 0x00000000 |
2334 | #define cfgBIFPLR1_0_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000 |
2335 | #define cfgBIFPLR1_0_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
2336 | #define cfgBIFPLR1_0_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
2337 | #define cfgBIFPLR1_0_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
2338 | #define cfgBIFPLR1_0_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
2339 | #define cfgBIFPLR1_0_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
2340 | #define cfgBIFPLR1_0_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
2341 | #define cfgBIFPLR1_0_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
2342 | #define cfgBIFPLR1_0_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
2343 | #define cfgBIFPLR1_0_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
2344 | #define cfgBIFPLR1_0_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
2345 | #define cfgBIFPLR1_0_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
2346 | #define cfgBIFPLR1_0_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
2347 | #define cfgBIFPLR1_0_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
2348 | #define cfgBIFPLR1_0_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
2349 | #define cfgBIFPLR1_0_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
2350 | #define cfgBIFPLR1_0_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
2351 | #define cfgBIFPLR1_0_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2f000000 |
2352 | #define cfgBIFPLR1_0_PCIE_ACS_CAP_DEFAULT 0x00000000 |
2353 | #define cfgBIFPLR1_0_PCIE_ACS_CNTL_DEFAULT 0x00000000 |
2354 | #define cfgBIFPLR1_0_PCIE_MC_ENH_CAP_LIST_DEFAULT 0x32000000 |
2355 | #define cfgBIFPLR1_0_PCIE_MC_CAP_DEFAULT 0x00000000 |
2356 | #define cfgBIFPLR1_0_PCIE_MC_CNTL_DEFAULT 0x00000000 |
2357 | #define cfgBIFPLR1_0_PCIE_MC_ADDR0_DEFAULT 0x00000000 |
2358 | #define cfgBIFPLR1_0_PCIE_MC_ADDR1_DEFAULT 0x00000000 |
2359 | #define cfgBIFPLR1_0_PCIE_MC_RCV0_DEFAULT 0x00000000 |
2360 | #define cfgBIFPLR1_0_PCIE_MC_RCV1_DEFAULT 0x00000000 |
2361 | #define cfgBIFPLR1_0_PCIE_MC_BLOCK_ALL0_DEFAULT 0x00000000 |
2362 | #define cfgBIFPLR1_0_PCIE_MC_BLOCK_ALL1_DEFAULT 0x00000000 |
2363 | #define cfgBIFPLR1_0_PCIE_MC_BLOCK_UNTRANSLATED_0_DEFAULT 0x00000000 |
2364 | #define cfgBIFPLR1_0_PCIE_MC_BLOCK_UNTRANSLATED_1_DEFAULT 0x00000000 |
2365 | #define cfgBIFPLR1_0_PCIE_MC_OVERLAY_BAR0_DEFAULT 0x00000000 |
2366 | #define cfgBIFPLR1_0_PCIE_MC_OVERLAY_BAR1_DEFAULT 0x00000000 |
2367 | #define cfgBIFPLR1_0_PCIE_L1_PM_SUB_CAP_LIST_DEFAULT 0x00000000 |
2368 | #define cfgBIFPLR1_0_PCIE_L1_PM_SUB_CAP_DEFAULT 0x00000000 |
2369 | #define cfgBIFPLR1_0_PCIE_L1_PM_SUB_CNTL_DEFAULT 0x00000000 |
2370 | #define cfgBIFPLR1_0_PCIE_L1_PM_SUB_CNTL2_DEFAULT 0x00000028 |
2371 | #define cfgBIFPLR1_0_PCIE_DPC_ENH_CAP_LIST_DEFAULT 0x00000000 |
2372 | #define cfgBIFPLR1_0_PCIE_DPC_CAP_LIST_DEFAULT 0x00000000 |
2373 | #define cfgBIFPLR1_0_PCIE_DPC_CNTL_DEFAULT 0x00000000 |
2374 | #define cfgBIFPLR1_0_PCIE_DPC_STATUS_DEFAULT 0x00000000 |
2375 | #define cfgBIFPLR1_0_PCIE_DPC_ERROR_SOURCE_ID_DEFAULT 0x00000000 |
2376 | #define cfgBIFPLR1_0_PCIE_RP_PIO_STATUS_DEFAULT 0x00000000 |
2377 | #define cfgBIFPLR1_0_PCIE_RP_PIO_MASK_DEFAULT 0x00070707 |
2378 | #define cfgBIFPLR1_0_PCIE_RP_PIO_SEVERITY_DEFAULT 0x00000000 |
2379 | #define cfgBIFPLR1_0_PCIE_RP_PIO_SYSERROR_DEFAULT 0x00000000 |
2380 | #define cfgBIFPLR1_0_PCIE_RP_PIO_EXCEPTION_DEFAULT 0x00000000 |
2381 | #define cfgBIFPLR1_0_PCIE_RP_PIO_HDR_LOG0_DEFAULT 0x00000000 |
2382 | #define cfgBIFPLR1_0_PCIE_RP_PIO_HDR_LOG1_DEFAULT 0x00000000 |
2383 | #define cfgBIFPLR1_0_PCIE_RP_PIO_HDR_LOG2_DEFAULT 0x00000000 |
2384 | #define cfgBIFPLR1_0_PCIE_RP_PIO_HDR_LOG3_DEFAULT 0x00000000 |
2385 | #define cfgBIFPLR1_0_PCIE_RP_PIO_IMPSPEC_LOG_DEFAULT 0x00000000 |
2386 | #define cfgBIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG0_DEFAULT 0x00000000 |
2387 | #define cfgBIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG1_DEFAULT 0x00000000 |
2388 | #define cfgBIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG2_DEFAULT 0x00000000 |
2389 | #define cfgBIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG3_DEFAULT 0x00000000 |
2390 | #define cfgBIFPLR1_0_PCIE_ESM_CAP_LIST_DEFAULT 0x00000000 |
2391 | #define 0x00000000 |
2392 | #define 0x00000000 |
2393 | #define cfgBIFPLR1_0_PCIE_ESM_STATUS_DEFAULT 0x00000000 |
2394 | #define cfgBIFPLR1_0_PCIE_ESM_CTRL_DEFAULT 0x00000000 |
2395 | #define cfgBIFPLR1_0_PCIE_ESM_CAP_1_DEFAULT 0x00000000 |
2396 | #define cfgBIFPLR1_0_PCIE_ESM_CAP_2_DEFAULT 0x00000000 |
2397 | #define cfgBIFPLR1_0_PCIE_ESM_CAP_3_DEFAULT 0x00000000 |
2398 | #define cfgBIFPLR1_0_PCIE_ESM_CAP_4_DEFAULT 0x00000000 |
2399 | #define cfgBIFPLR1_0_PCIE_ESM_CAP_5_DEFAULT 0x00000000 |
2400 | #define cfgBIFPLR1_0_PCIE_ESM_CAP_6_DEFAULT 0x00000000 |
2401 | #define cfgBIFPLR1_0_PCIE_ESM_CAP_7_DEFAULT 0x00000000 |
2402 | |
2403 | |
2404 | // addressBlock: nbio_pcie0_bifplr2_cfgdecp |
2405 | #define cfgBIFPLR2_0_VENDOR_ID_DEFAULT 0x00000000 |
2406 | #define cfgBIFPLR2_0_DEVICE_ID_DEFAULT 0x00000000 |
2407 | #define cfgBIFPLR2_0_COMMAND_DEFAULT 0x00000000 |
2408 | #define cfgBIFPLR2_0_STATUS_DEFAULT 0x00000000 |
2409 | #define cfgBIFPLR2_0_REVISION_ID_DEFAULT 0x00000000 |
2410 | #define cfgBIFPLR2_0_PROG_INTERFACE_DEFAULT 0x00000000 |
2411 | #define cfgBIFPLR2_0_SUB_CLASS_DEFAULT 0x00000000 |
2412 | #define cfgBIFPLR2_0_BASE_CLASS_DEFAULT 0x00000000 |
2413 | #define cfgBIFPLR2_0_CACHE_LINE_DEFAULT 0x00000000 |
2414 | #define cfgBIFPLR2_0_LATENCY_DEFAULT 0x00000000 |
2415 | #define 0x00000000 |
2416 | #define cfgBIFPLR2_0_BIST_DEFAULT 0x00000000 |
2417 | #define cfgBIFPLR2_0_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 |
2418 | #define cfgBIFPLR2_0_IO_BASE_LIMIT_DEFAULT 0x00000000 |
2419 | #define cfgBIFPLR2_0_SECONDARY_STATUS_DEFAULT 0x00000000 |
2420 | #define cfgBIFPLR2_0_MEM_BASE_LIMIT_DEFAULT 0x00000000 |
2421 | #define cfgBIFPLR2_0_PREF_BASE_LIMIT_DEFAULT 0x00000000 |
2422 | #define cfgBIFPLR2_0_PREF_BASE_UPPER_DEFAULT 0x00000000 |
2423 | #define cfgBIFPLR2_0_PREF_LIMIT_UPPER_DEFAULT 0x00000000 |
2424 | #define cfgBIFPLR2_0_IO_BASE_LIMIT_HI_DEFAULT 0x00000000 |
2425 | #define cfgBIFPLR2_0_CAP_PTR_DEFAULT 0x00000000 |
2426 | #define cfgBIFPLR2_0_INTERRUPT_LINE_DEFAULT 0x000000ff |
2427 | #define cfgBIFPLR2_0_INTERRUPT_PIN_DEFAULT 0x00000000 |
2428 | #define cfgBIFPLR2_0_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000 |
2429 | #define cfgBIFPLR2_0_EXT_BRIDGE_CNTL_DEFAULT 0x00000000 |
2430 | #define cfgBIFPLR2_0_PMI_CAP_LIST_DEFAULT 0x00000000 |
2431 | #define cfgBIFPLR2_0_PMI_CAP_DEFAULT 0x00000000 |
2432 | #define cfgBIFPLR2_0_PMI_STATUS_CNTL_DEFAULT 0x00000000 |
2433 | #define cfgBIFPLR2_0_PCIE_CAP_LIST_DEFAULT 0x0000a000 |
2434 | #define cfgBIFPLR2_0_PCIE_CAP_DEFAULT 0x00000002 |
2435 | #define cfgBIFPLR2_0_DEVICE_CAP_DEFAULT 0x00000000 |
2436 | #define cfgBIFPLR2_0_DEVICE_CNTL_DEFAULT 0x00002810 |
2437 | #define cfgBIFPLR2_0_DEVICE_STATUS_DEFAULT 0x00000000 |
2438 | #define cfgBIFPLR2_0_LINK_CAP_DEFAULT 0x00011c03 |
2439 | #define cfgBIFPLR2_0_LINK_CNTL_DEFAULT 0x00000000 |
2440 | #define cfgBIFPLR2_0_LINK_STATUS_DEFAULT 0x00000001 |
2441 | #define cfgBIFPLR2_0_SLOT_CAP_DEFAULT 0x00000000 |
2442 | #define cfgBIFPLR2_0_SLOT_CNTL_DEFAULT 0x00000000 |
2443 | #define cfgBIFPLR2_0_SLOT_STATUS_DEFAULT 0x00000000 |
2444 | #define cfgBIFPLR2_0_ROOT_CNTL_DEFAULT 0x00000000 |
2445 | #define cfgBIFPLR2_0_ROOT_CAP_DEFAULT 0x00000000 |
2446 | #define cfgBIFPLR2_0_ROOT_STATUS_DEFAULT 0x00000000 |
2447 | #define cfgBIFPLR2_0_DEVICE_CAP2_DEFAULT 0x00000000 |
2448 | #define cfgBIFPLR2_0_DEVICE_CNTL2_DEFAULT 0x00000000 |
2449 | #define cfgBIFPLR2_0_DEVICE_STATUS2_DEFAULT 0x00000000 |
2450 | #define cfgBIFPLR2_0_LINK_CAP2_DEFAULT 0x0000000e |
2451 | #define cfgBIFPLR2_0_LINK_CNTL2_DEFAULT 0x00000003 |
2452 | #define cfgBIFPLR2_0_LINK_STATUS2_DEFAULT 0x00000000 |
2453 | #define cfgBIFPLR2_0_SLOT_CAP2_DEFAULT 0x00000000 |
2454 | #define cfgBIFPLR2_0_SLOT_CNTL2_DEFAULT 0x00000000 |
2455 | #define cfgBIFPLR2_0_SLOT_STATUS2_DEFAULT 0x00000000 |
2456 | #define cfgBIFPLR2_0_MSI_CAP_LIST_DEFAULT 0x0000c000 |
2457 | #define cfgBIFPLR2_0_MSI_MSG_CNTL_DEFAULT 0x00000000 |
2458 | #define cfgBIFPLR2_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 |
2459 | #define cfgBIFPLR2_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 |
2460 | #define cfgBIFPLR2_0_MSI_MSG_DATA_DEFAULT 0x00000000 |
2461 | #define cfgBIFPLR2_0_MSI_MSG_DATA_64_DEFAULT 0x00000000 |
2462 | #define cfgBIFPLR2_0_SSID_CAP_LIST_DEFAULT 0x0000c800 |
2463 | #define cfgBIFPLR2_0_SSID_CAP_DEFAULT 0x00000000 |
2464 | #define cfgBIFPLR2_0_MSI_MAP_CAP_LIST_DEFAULT 0x00000000 |
2465 | #define cfgBIFPLR2_0_MSI_MAP_CAP_DEFAULT 0x00000000 |
2466 | #define cfgBIFPLR2_0_MSI_MAP_ADDR_LO_DEFAULT 0x00000000 |
2467 | #define cfgBIFPLR2_0_MSI_MAP_ADDR_HI_DEFAULT 0x00000000 |
2468 | #define cfgBIFPLR2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 |
2469 | #define cfgBIFPLR2_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 |
2470 | #define cfgBIFPLR2_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 |
2471 | #define cfgBIFPLR2_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 |
2472 | #define cfgBIFPLR2_0_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000 |
2473 | #define cfgBIFPLR2_0_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000 |
2474 | #define cfgBIFPLR2_0_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000 |
2475 | #define cfgBIFPLR2_0_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000 |
2476 | #define cfgBIFPLR2_0_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000 |
2477 | #define cfgBIFPLR2_0_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000 |
2478 | #define cfgBIFPLR2_0_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe |
2479 | #define cfgBIFPLR2_0_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000002 |
2480 | #define cfgBIFPLR2_0_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000 |
2481 | #define cfgBIFPLR2_0_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000 |
2482 | #define cfgBIFPLR2_0_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000002 |
2483 | #define cfgBIFPLR2_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000 |
2484 | #define cfgBIFPLR2_0_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000 |
2485 | #define cfgBIFPLR2_0_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000 |
2486 | #define cfgBIFPLR2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x27020000 |
2487 | #define cfgBIFPLR2_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 |
2488 | #define cfgBIFPLR2_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00400000 |
2489 | #define cfgBIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 |
2490 | #define cfgBIFPLR2_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 |
2491 | #define cfgBIFPLR2_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00006000 |
2492 | #define cfgBIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 |
2493 | #define cfgBIFPLR2_0_PCIE_HDR_LOG0_DEFAULT 0x00000000 |
2494 | #define cfgBIFPLR2_0_PCIE_HDR_LOG1_DEFAULT 0x00000000 |
2495 | #define cfgBIFPLR2_0_PCIE_HDR_LOG2_DEFAULT 0x00000000 |
2496 | #define cfgBIFPLR2_0_PCIE_HDR_LOG3_DEFAULT 0x00000000 |
2497 | #define cfgBIFPLR2_0_PCIE_ROOT_ERR_CMD_DEFAULT 0x00000000 |
2498 | #define cfgBIFPLR2_0_PCIE_ROOT_ERR_STATUS_DEFAULT 0x00000000 |
2499 | #define cfgBIFPLR2_0_PCIE_ERR_SRC_ID_DEFAULT 0x00000000 |
2500 | #define cfgBIFPLR2_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 |
2501 | #define cfgBIFPLR2_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 |
2502 | #define cfgBIFPLR2_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 |
2503 | #define cfgBIFPLR2_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 |
2504 | #define cfgBIFPLR2_0_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a000000 |
2505 | #define cfgBIFPLR2_0_PCIE_LINK_CNTL3_DEFAULT 0x00000000 |
2506 | #define cfgBIFPLR2_0_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000 |
2507 | #define cfgBIFPLR2_0_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
2508 | #define cfgBIFPLR2_0_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
2509 | #define cfgBIFPLR2_0_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
2510 | #define cfgBIFPLR2_0_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
2511 | #define cfgBIFPLR2_0_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
2512 | #define cfgBIFPLR2_0_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
2513 | #define cfgBIFPLR2_0_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
2514 | #define cfgBIFPLR2_0_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
2515 | #define cfgBIFPLR2_0_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
2516 | #define cfgBIFPLR2_0_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
2517 | #define cfgBIFPLR2_0_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
2518 | #define cfgBIFPLR2_0_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
2519 | #define cfgBIFPLR2_0_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
2520 | #define cfgBIFPLR2_0_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
2521 | #define cfgBIFPLR2_0_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
2522 | #define cfgBIFPLR2_0_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
2523 | #define cfgBIFPLR2_0_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2f000000 |
2524 | #define cfgBIFPLR2_0_PCIE_ACS_CAP_DEFAULT 0x00000000 |
2525 | #define cfgBIFPLR2_0_PCIE_ACS_CNTL_DEFAULT 0x00000000 |
2526 | #define cfgBIFPLR2_0_PCIE_MC_ENH_CAP_LIST_DEFAULT 0x32000000 |
2527 | #define cfgBIFPLR2_0_PCIE_MC_CAP_DEFAULT 0x00000000 |
2528 | #define cfgBIFPLR2_0_PCIE_MC_CNTL_DEFAULT 0x00000000 |
2529 | #define cfgBIFPLR2_0_PCIE_MC_ADDR0_DEFAULT 0x00000000 |
2530 | #define cfgBIFPLR2_0_PCIE_MC_ADDR1_DEFAULT 0x00000000 |
2531 | #define cfgBIFPLR2_0_PCIE_MC_RCV0_DEFAULT 0x00000000 |
2532 | #define cfgBIFPLR2_0_PCIE_MC_RCV1_DEFAULT 0x00000000 |
2533 | #define cfgBIFPLR2_0_PCIE_MC_BLOCK_ALL0_DEFAULT 0x00000000 |
2534 | #define cfgBIFPLR2_0_PCIE_MC_BLOCK_ALL1_DEFAULT 0x00000000 |
2535 | #define cfgBIFPLR2_0_PCIE_MC_BLOCK_UNTRANSLATED_0_DEFAULT 0x00000000 |
2536 | #define cfgBIFPLR2_0_PCIE_MC_BLOCK_UNTRANSLATED_1_DEFAULT 0x00000000 |
2537 | #define cfgBIFPLR2_0_PCIE_MC_OVERLAY_BAR0_DEFAULT 0x00000000 |
2538 | #define cfgBIFPLR2_0_PCIE_MC_OVERLAY_BAR1_DEFAULT 0x00000000 |
2539 | #define cfgBIFPLR2_0_PCIE_L1_PM_SUB_CAP_LIST_DEFAULT 0x00000000 |
2540 | #define cfgBIFPLR2_0_PCIE_L1_PM_SUB_CAP_DEFAULT 0x00000000 |
2541 | #define cfgBIFPLR2_0_PCIE_L1_PM_SUB_CNTL_DEFAULT 0x00000000 |
2542 | #define cfgBIFPLR2_0_PCIE_L1_PM_SUB_CNTL2_DEFAULT 0x00000028 |
2543 | #define cfgBIFPLR2_0_PCIE_DPC_ENH_CAP_LIST_DEFAULT 0x00000000 |
2544 | #define cfgBIFPLR2_0_PCIE_DPC_CAP_LIST_DEFAULT 0x00000000 |
2545 | #define cfgBIFPLR2_0_PCIE_DPC_CNTL_DEFAULT 0x00000000 |
2546 | #define cfgBIFPLR2_0_PCIE_DPC_STATUS_DEFAULT 0x00000000 |
2547 | #define cfgBIFPLR2_0_PCIE_DPC_ERROR_SOURCE_ID_DEFAULT 0x00000000 |
2548 | #define cfgBIFPLR2_0_PCIE_RP_PIO_STATUS_DEFAULT 0x00000000 |
2549 | #define cfgBIFPLR2_0_PCIE_RP_PIO_MASK_DEFAULT 0x00070707 |
2550 | #define cfgBIFPLR2_0_PCIE_RP_PIO_SEVERITY_DEFAULT 0x00000000 |
2551 | #define cfgBIFPLR2_0_PCIE_RP_PIO_SYSERROR_DEFAULT 0x00000000 |
2552 | #define cfgBIFPLR2_0_PCIE_RP_PIO_EXCEPTION_DEFAULT 0x00000000 |
2553 | #define cfgBIFPLR2_0_PCIE_RP_PIO_HDR_LOG0_DEFAULT 0x00000000 |
2554 | #define cfgBIFPLR2_0_PCIE_RP_PIO_HDR_LOG1_DEFAULT 0x00000000 |
2555 | #define cfgBIFPLR2_0_PCIE_RP_PIO_HDR_LOG2_DEFAULT 0x00000000 |
2556 | #define cfgBIFPLR2_0_PCIE_RP_PIO_HDR_LOG3_DEFAULT 0x00000000 |
2557 | #define cfgBIFPLR2_0_PCIE_RP_PIO_IMPSPEC_LOG_DEFAULT 0x00000000 |
2558 | #define cfgBIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG0_DEFAULT 0x00000000 |
2559 | #define cfgBIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG1_DEFAULT 0x00000000 |
2560 | #define cfgBIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG2_DEFAULT 0x00000000 |
2561 | #define cfgBIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG3_DEFAULT 0x00000000 |
2562 | #define cfgBIFPLR2_0_PCIE_ESM_CAP_LIST_DEFAULT 0x00000000 |
2563 | #define 0x00000000 |
2564 | #define 0x00000000 |
2565 | #define cfgBIFPLR2_0_PCIE_ESM_STATUS_DEFAULT 0x00000000 |
2566 | #define cfgBIFPLR2_0_PCIE_ESM_CTRL_DEFAULT 0x00000000 |
2567 | #define cfgBIFPLR2_0_PCIE_ESM_CAP_1_DEFAULT 0x00000000 |
2568 | #define cfgBIFPLR2_0_PCIE_ESM_CAP_2_DEFAULT 0x00000000 |
2569 | #define cfgBIFPLR2_0_PCIE_ESM_CAP_3_DEFAULT 0x00000000 |
2570 | #define cfgBIFPLR2_0_PCIE_ESM_CAP_4_DEFAULT 0x00000000 |
2571 | #define cfgBIFPLR2_0_PCIE_ESM_CAP_5_DEFAULT 0x00000000 |
2572 | #define cfgBIFPLR2_0_PCIE_ESM_CAP_6_DEFAULT 0x00000000 |
2573 | #define cfgBIFPLR2_0_PCIE_ESM_CAP_7_DEFAULT 0x00000000 |
2574 | |
2575 | |
2576 | // addressBlock: nbio_pcie0_bifplr3_cfgdecp |
2577 | #define cfgBIFPLR3_0_VENDOR_ID_DEFAULT 0x00000000 |
2578 | #define cfgBIFPLR3_0_DEVICE_ID_DEFAULT 0x00000000 |
2579 | #define cfgBIFPLR3_0_COMMAND_DEFAULT 0x00000000 |
2580 | #define cfgBIFPLR3_0_STATUS_DEFAULT 0x00000000 |
2581 | #define cfgBIFPLR3_0_REVISION_ID_DEFAULT 0x00000000 |
2582 | #define cfgBIFPLR3_0_PROG_INTERFACE_DEFAULT 0x00000000 |
2583 | #define cfgBIFPLR3_0_SUB_CLASS_DEFAULT 0x00000000 |
2584 | #define cfgBIFPLR3_0_BASE_CLASS_DEFAULT 0x00000000 |
2585 | #define cfgBIFPLR3_0_CACHE_LINE_DEFAULT 0x00000000 |
2586 | #define cfgBIFPLR3_0_LATENCY_DEFAULT 0x00000000 |
2587 | #define 0x00000000 |
2588 | #define cfgBIFPLR3_0_BIST_DEFAULT 0x00000000 |
2589 | #define cfgBIFPLR3_0_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 |
2590 | #define cfgBIFPLR3_0_IO_BASE_LIMIT_DEFAULT 0x00000000 |
2591 | #define cfgBIFPLR3_0_SECONDARY_STATUS_DEFAULT 0x00000000 |
2592 | #define cfgBIFPLR3_0_MEM_BASE_LIMIT_DEFAULT 0x00000000 |
2593 | #define cfgBIFPLR3_0_PREF_BASE_LIMIT_DEFAULT 0x00000000 |
2594 | #define cfgBIFPLR3_0_PREF_BASE_UPPER_DEFAULT 0x00000000 |
2595 | #define cfgBIFPLR3_0_PREF_LIMIT_UPPER_DEFAULT 0x00000000 |
2596 | #define cfgBIFPLR3_0_IO_BASE_LIMIT_HI_DEFAULT 0x00000000 |
2597 | #define cfgBIFPLR3_0_CAP_PTR_DEFAULT 0x00000000 |
2598 | #define cfgBIFPLR3_0_INTERRUPT_LINE_DEFAULT 0x000000ff |
2599 | #define cfgBIFPLR3_0_INTERRUPT_PIN_DEFAULT 0x00000000 |
2600 | #define cfgBIFPLR3_0_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000 |
2601 | #define cfgBIFPLR3_0_EXT_BRIDGE_CNTL_DEFAULT 0x00000000 |
2602 | #define cfgBIFPLR3_0_PMI_CAP_LIST_DEFAULT 0x00000000 |
2603 | #define cfgBIFPLR3_0_PMI_CAP_DEFAULT 0x00000000 |
2604 | #define cfgBIFPLR3_0_PMI_STATUS_CNTL_DEFAULT 0x00000000 |
2605 | #define cfgBIFPLR3_0_PCIE_CAP_LIST_DEFAULT 0x0000a000 |
2606 | #define cfgBIFPLR3_0_PCIE_CAP_DEFAULT 0x00000002 |
2607 | #define cfgBIFPLR3_0_DEVICE_CAP_DEFAULT 0x00000000 |
2608 | #define cfgBIFPLR3_0_DEVICE_CNTL_DEFAULT 0x00002810 |
2609 | #define cfgBIFPLR3_0_DEVICE_STATUS_DEFAULT 0x00000000 |
2610 | #define cfgBIFPLR3_0_LINK_CAP_DEFAULT 0x00011c03 |
2611 | #define cfgBIFPLR3_0_LINK_CNTL_DEFAULT 0x00000000 |
2612 | #define cfgBIFPLR3_0_LINK_STATUS_DEFAULT 0x00000001 |
2613 | #define cfgBIFPLR3_0_SLOT_CAP_DEFAULT 0x00000000 |
2614 | #define cfgBIFPLR3_0_SLOT_CNTL_DEFAULT 0x00000000 |
2615 | #define cfgBIFPLR3_0_SLOT_STATUS_DEFAULT 0x00000000 |
2616 | #define cfgBIFPLR3_0_ROOT_CNTL_DEFAULT 0x00000000 |
2617 | #define cfgBIFPLR3_0_ROOT_CAP_DEFAULT 0x00000000 |
2618 | #define cfgBIFPLR3_0_ROOT_STATUS_DEFAULT 0x00000000 |
2619 | #define cfgBIFPLR3_0_DEVICE_CAP2_DEFAULT 0x00000000 |
2620 | #define cfgBIFPLR3_0_DEVICE_CNTL2_DEFAULT 0x00000000 |
2621 | #define cfgBIFPLR3_0_DEVICE_STATUS2_DEFAULT 0x00000000 |
2622 | #define cfgBIFPLR3_0_LINK_CAP2_DEFAULT 0x0000000e |
2623 | #define cfgBIFPLR3_0_LINK_CNTL2_DEFAULT 0x00000003 |
2624 | #define cfgBIFPLR3_0_LINK_STATUS2_DEFAULT 0x00000000 |
2625 | #define cfgBIFPLR3_0_SLOT_CAP2_DEFAULT 0x00000000 |
2626 | #define cfgBIFPLR3_0_SLOT_CNTL2_DEFAULT 0x00000000 |
2627 | #define cfgBIFPLR3_0_SLOT_STATUS2_DEFAULT 0x00000000 |
2628 | #define cfgBIFPLR3_0_MSI_CAP_LIST_DEFAULT 0x0000c000 |
2629 | #define cfgBIFPLR3_0_MSI_MSG_CNTL_DEFAULT 0x00000000 |
2630 | #define cfgBIFPLR3_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 |
2631 | #define cfgBIFPLR3_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 |
2632 | #define cfgBIFPLR3_0_MSI_MSG_DATA_DEFAULT 0x00000000 |
2633 | #define cfgBIFPLR3_0_MSI_MSG_DATA_64_DEFAULT 0x00000000 |
2634 | #define cfgBIFPLR3_0_SSID_CAP_LIST_DEFAULT 0x0000c800 |
2635 | #define cfgBIFPLR3_0_SSID_CAP_DEFAULT 0x00000000 |
2636 | #define cfgBIFPLR3_0_MSI_MAP_CAP_LIST_DEFAULT 0x00000000 |
2637 | #define cfgBIFPLR3_0_MSI_MAP_CAP_DEFAULT 0x00000000 |
2638 | #define cfgBIFPLR3_0_MSI_MAP_ADDR_LO_DEFAULT 0x00000000 |
2639 | #define cfgBIFPLR3_0_MSI_MAP_ADDR_HI_DEFAULT 0x00000000 |
2640 | #define cfgBIFPLR3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 |
2641 | #define cfgBIFPLR3_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 |
2642 | #define cfgBIFPLR3_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 |
2643 | #define cfgBIFPLR3_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 |
2644 | #define cfgBIFPLR3_0_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000 |
2645 | #define cfgBIFPLR3_0_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000 |
2646 | #define cfgBIFPLR3_0_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000 |
2647 | #define cfgBIFPLR3_0_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000 |
2648 | #define cfgBIFPLR3_0_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000 |
2649 | #define cfgBIFPLR3_0_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000 |
2650 | #define cfgBIFPLR3_0_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe |
2651 | #define cfgBIFPLR3_0_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000002 |
2652 | #define cfgBIFPLR3_0_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000 |
2653 | #define cfgBIFPLR3_0_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000 |
2654 | #define cfgBIFPLR3_0_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000002 |
2655 | #define cfgBIFPLR3_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000 |
2656 | #define cfgBIFPLR3_0_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000 |
2657 | #define cfgBIFPLR3_0_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000 |
2658 | #define cfgBIFPLR3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x27020000 |
2659 | #define cfgBIFPLR3_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 |
2660 | #define cfgBIFPLR3_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00400000 |
2661 | #define cfgBIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 |
2662 | #define cfgBIFPLR3_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 |
2663 | #define cfgBIFPLR3_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00006000 |
2664 | #define cfgBIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 |
2665 | #define cfgBIFPLR3_0_PCIE_HDR_LOG0_DEFAULT 0x00000000 |
2666 | #define cfgBIFPLR3_0_PCIE_HDR_LOG1_DEFAULT 0x00000000 |
2667 | #define cfgBIFPLR3_0_PCIE_HDR_LOG2_DEFAULT 0x00000000 |
2668 | #define cfgBIFPLR3_0_PCIE_HDR_LOG3_DEFAULT 0x00000000 |
2669 | #define cfgBIFPLR3_0_PCIE_ROOT_ERR_CMD_DEFAULT 0x00000000 |
2670 | #define cfgBIFPLR3_0_PCIE_ROOT_ERR_STATUS_DEFAULT 0x00000000 |
2671 | #define cfgBIFPLR3_0_PCIE_ERR_SRC_ID_DEFAULT 0x00000000 |
2672 | #define cfgBIFPLR3_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 |
2673 | #define cfgBIFPLR3_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 |
2674 | #define cfgBIFPLR3_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 |
2675 | #define cfgBIFPLR3_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 |
2676 | #define cfgBIFPLR3_0_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a000000 |
2677 | #define cfgBIFPLR3_0_PCIE_LINK_CNTL3_DEFAULT 0x00000000 |
2678 | #define cfgBIFPLR3_0_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000 |
2679 | #define cfgBIFPLR3_0_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
2680 | #define cfgBIFPLR3_0_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
2681 | #define cfgBIFPLR3_0_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
2682 | #define cfgBIFPLR3_0_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
2683 | #define cfgBIFPLR3_0_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
2684 | #define cfgBIFPLR3_0_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
2685 | #define cfgBIFPLR3_0_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
2686 | #define cfgBIFPLR3_0_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
2687 | #define cfgBIFPLR3_0_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
2688 | #define cfgBIFPLR3_0_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
2689 | #define cfgBIFPLR3_0_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
2690 | #define cfgBIFPLR3_0_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
2691 | #define cfgBIFPLR3_0_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
2692 | #define cfgBIFPLR3_0_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
2693 | #define cfgBIFPLR3_0_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
2694 | #define cfgBIFPLR3_0_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
2695 | #define cfgBIFPLR3_0_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2f000000 |
2696 | #define cfgBIFPLR3_0_PCIE_ACS_CAP_DEFAULT 0x00000000 |
2697 | #define cfgBIFPLR3_0_PCIE_ACS_CNTL_DEFAULT 0x00000000 |
2698 | #define cfgBIFPLR3_0_PCIE_MC_ENH_CAP_LIST_DEFAULT 0x32000000 |
2699 | #define cfgBIFPLR3_0_PCIE_MC_CAP_DEFAULT 0x00000000 |
2700 | #define cfgBIFPLR3_0_PCIE_MC_CNTL_DEFAULT 0x00000000 |
2701 | #define cfgBIFPLR3_0_PCIE_MC_ADDR0_DEFAULT 0x00000000 |
2702 | #define cfgBIFPLR3_0_PCIE_MC_ADDR1_DEFAULT 0x00000000 |
2703 | #define cfgBIFPLR3_0_PCIE_MC_RCV0_DEFAULT 0x00000000 |
2704 | #define cfgBIFPLR3_0_PCIE_MC_RCV1_DEFAULT 0x00000000 |
2705 | #define cfgBIFPLR3_0_PCIE_MC_BLOCK_ALL0_DEFAULT 0x00000000 |
2706 | #define cfgBIFPLR3_0_PCIE_MC_BLOCK_ALL1_DEFAULT 0x00000000 |
2707 | #define cfgBIFPLR3_0_PCIE_MC_BLOCK_UNTRANSLATED_0_DEFAULT 0x00000000 |
2708 | #define cfgBIFPLR3_0_PCIE_MC_BLOCK_UNTRANSLATED_1_DEFAULT 0x00000000 |
2709 | #define cfgBIFPLR3_0_PCIE_MC_OVERLAY_BAR0_DEFAULT 0x00000000 |
2710 | #define cfgBIFPLR3_0_PCIE_MC_OVERLAY_BAR1_DEFAULT 0x00000000 |
2711 | #define cfgBIFPLR3_0_PCIE_L1_PM_SUB_CAP_LIST_DEFAULT 0x00000000 |
2712 | #define cfgBIFPLR3_0_PCIE_L1_PM_SUB_CAP_DEFAULT 0x00000000 |
2713 | #define cfgBIFPLR3_0_PCIE_L1_PM_SUB_CNTL_DEFAULT 0x00000000 |
2714 | #define cfgBIFPLR3_0_PCIE_L1_PM_SUB_CNTL2_DEFAULT 0x00000028 |
2715 | #define cfgBIFPLR3_0_PCIE_DPC_ENH_CAP_LIST_DEFAULT 0x00000000 |
2716 | #define cfgBIFPLR3_0_PCIE_DPC_CAP_LIST_DEFAULT 0x00000000 |
2717 | #define cfgBIFPLR3_0_PCIE_DPC_CNTL_DEFAULT 0x00000000 |
2718 | #define cfgBIFPLR3_0_PCIE_DPC_STATUS_DEFAULT 0x00000000 |
2719 | #define cfgBIFPLR3_0_PCIE_DPC_ERROR_SOURCE_ID_DEFAULT 0x00000000 |
2720 | #define cfgBIFPLR3_0_PCIE_RP_PIO_STATUS_DEFAULT 0x00000000 |
2721 | #define cfgBIFPLR3_0_PCIE_RP_PIO_MASK_DEFAULT 0x00070707 |
2722 | #define cfgBIFPLR3_0_PCIE_RP_PIO_SEVERITY_DEFAULT 0x00000000 |
2723 | #define cfgBIFPLR3_0_PCIE_RP_PIO_SYSERROR_DEFAULT 0x00000000 |
2724 | #define cfgBIFPLR3_0_PCIE_RP_PIO_EXCEPTION_DEFAULT 0x00000000 |
2725 | #define cfgBIFPLR3_0_PCIE_RP_PIO_HDR_LOG0_DEFAULT 0x00000000 |
2726 | #define cfgBIFPLR3_0_PCIE_RP_PIO_HDR_LOG1_DEFAULT 0x00000000 |
2727 | #define cfgBIFPLR3_0_PCIE_RP_PIO_HDR_LOG2_DEFAULT 0x00000000 |
2728 | #define cfgBIFPLR3_0_PCIE_RP_PIO_HDR_LOG3_DEFAULT 0x00000000 |
2729 | #define cfgBIFPLR3_0_PCIE_RP_PIO_IMPSPEC_LOG_DEFAULT 0x00000000 |
2730 | #define cfgBIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG0_DEFAULT 0x00000000 |
2731 | #define cfgBIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG1_DEFAULT 0x00000000 |
2732 | #define cfgBIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG2_DEFAULT 0x00000000 |
2733 | #define cfgBIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG3_DEFAULT 0x00000000 |
2734 | #define cfgBIFPLR3_0_PCIE_ESM_CAP_LIST_DEFAULT 0x00000000 |
2735 | #define 0x00000000 |
2736 | #define 0x00000000 |
2737 | #define cfgBIFPLR3_0_PCIE_ESM_STATUS_DEFAULT 0x00000000 |
2738 | #define cfgBIFPLR3_0_PCIE_ESM_CTRL_DEFAULT 0x00000000 |
2739 | #define cfgBIFPLR3_0_PCIE_ESM_CAP_1_DEFAULT 0x00000000 |
2740 | #define cfgBIFPLR3_0_PCIE_ESM_CAP_2_DEFAULT 0x00000000 |
2741 | #define cfgBIFPLR3_0_PCIE_ESM_CAP_3_DEFAULT 0x00000000 |
2742 | #define cfgBIFPLR3_0_PCIE_ESM_CAP_4_DEFAULT 0x00000000 |
2743 | #define cfgBIFPLR3_0_PCIE_ESM_CAP_5_DEFAULT 0x00000000 |
2744 | #define cfgBIFPLR3_0_PCIE_ESM_CAP_6_DEFAULT 0x00000000 |
2745 | #define cfgBIFPLR3_0_PCIE_ESM_CAP_7_DEFAULT 0x00000000 |
2746 | |
2747 | |
2748 | // addressBlock: nbio_pcie0_bifplr4_cfgdecp |
2749 | #define cfgBIFPLR4_0_VENDOR_ID_DEFAULT 0x00000000 |
2750 | #define cfgBIFPLR4_0_DEVICE_ID_DEFAULT 0x00000000 |
2751 | #define cfgBIFPLR4_0_COMMAND_DEFAULT 0x00000000 |
2752 | #define cfgBIFPLR4_0_STATUS_DEFAULT 0x00000000 |
2753 | #define cfgBIFPLR4_0_REVISION_ID_DEFAULT 0x00000000 |
2754 | #define cfgBIFPLR4_0_PROG_INTERFACE_DEFAULT 0x00000000 |
2755 | #define cfgBIFPLR4_0_SUB_CLASS_DEFAULT 0x00000000 |
2756 | #define cfgBIFPLR4_0_BASE_CLASS_DEFAULT 0x00000000 |
2757 | #define cfgBIFPLR4_0_CACHE_LINE_DEFAULT 0x00000000 |
2758 | #define cfgBIFPLR4_0_LATENCY_DEFAULT 0x00000000 |
2759 | #define 0x00000000 |
2760 | #define cfgBIFPLR4_0_BIST_DEFAULT 0x00000000 |
2761 | #define cfgBIFPLR4_0_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 |
2762 | #define cfgBIFPLR4_0_IO_BASE_LIMIT_DEFAULT 0x00000000 |
2763 | #define cfgBIFPLR4_0_SECONDARY_STATUS_DEFAULT 0x00000000 |
2764 | #define cfgBIFPLR4_0_MEM_BASE_LIMIT_DEFAULT 0x00000000 |
2765 | #define cfgBIFPLR4_0_PREF_BASE_LIMIT_DEFAULT 0x00000000 |
2766 | #define cfgBIFPLR4_0_PREF_BASE_UPPER_DEFAULT 0x00000000 |
2767 | #define cfgBIFPLR4_0_PREF_LIMIT_UPPER_DEFAULT 0x00000000 |
2768 | #define cfgBIFPLR4_0_IO_BASE_LIMIT_HI_DEFAULT 0x00000000 |
2769 | #define cfgBIFPLR4_0_CAP_PTR_DEFAULT 0x00000000 |
2770 | #define cfgBIFPLR4_0_INTERRUPT_LINE_DEFAULT 0x000000ff |
2771 | #define cfgBIFPLR4_0_INTERRUPT_PIN_DEFAULT 0x00000000 |
2772 | #define cfgBIFPLR4_0_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000 |
2773 | #define cfgBIFPLR4_0_EXT_BRIDGE_CNTL_DEFAULT 0x00000000 |
2774 | #define cfgBIFPLR4_0_PMI_CAP_LIST_DEFAULT 0x00000000 |
2775 | #define cfgBIFPLR4_0_PMI_CAP_DEFAULT 0x00000000 |
2776 | #define cfgBIFPLR4_0_PMI_STATUS_CNTL_DEFAULT 0x00000000 |
2777 | #define cfgBIFPLR4_0_PCIE_CAP_LIST_DEFAULT 0x0000a000 |
2778 | #define cfgBIFPLR4_0_PCIE_CAP_DEFAULT 0x00000002 |
2779 | #define cfgBIFPLR4_0_DEVICE_CAP_DEFAULT 0x00000000 |
2780 | #define cfgBIFPLR4_0_DEVICE_CNTL_DEFAULT 0x00002810 |
2781 | #define cfgBIFPLR4_0_DEVICE_STATUS_DEFAULT 0x00000000 |
2782 | #define cfgBIFPLR4_0_LINK_CAP_DEFAULT 0x00011c03 |
2783 | #define cfgBIFPLR4_0_LINK_CNTL_DEFAULT 0x00000000 |
2784 | #define cfgBIFPLR4_0_LINK_STATUS_DEFAULT 0x00000001 |
2785 | #define cfgBIFPLR4_0_SLOT_CAP_DEFAULT 0x00000000 |
2786 | #define cfgBIFPLR4_0_SLOT_CNTL_DEFAULT 0x00000000 |
2787 | #define cfgBIFPLR4_0_SLOT_STATUS_DEFAULT 0x00000000 |
2788 | #define cfgBIFPLR4_0_ROOT_CNTL_DEFAULT 0x00000000 |
2789 | #define cfgBIFPLR4_0_ROOT_CAP_DEFAULT 0x00000000 |
2790 | #define cfgBIFPLR4_0_ROOT_STATUS_DEFAULT 0x00000000 |
2791 | #define cfgBIFPLR4_0_DEVICE_CAP2_DEFAULT 0x00000000 |
2792 | #define cfgBIFPLR4_0_DEVICE_CNTL2_DEFAULT 0x00000000 |
2793 | #define cfgBIFPLR4_0_DEVICE_STATUS2_DEFAULT 0x00000000 |
2794 | #define cfgBIFPLR4_0_LINK_CAP2_DEFAULT 0x0000000e |
2795 | #define cfgBIFPLR4_0_LINK_CNTL2_DEFAULT 0x00000003 |
2796 | #define cfgBIFPLR4_0_LINK_STATUS2_DEFAULT 0x00000000 |
2797 | #define cfgBIFPLR4_0_SLOT_CAP2_DEFAULT 0x00000000 |
2798 | #define cfgBIFPLR4_0_SLOT_CNTL2_DEFAULT 0x00000000 |
2799 | #define cfgBIFPLR4_0_SLOT_STATUS2_DEFAULT 0x00000000 |
2800 | #define cfgBIFPLR4_0_MSI_CAP_LIST_DEFAULT 0x0000c000 |
2801 | #define cfgBIFPLR4_0_MSI_MSG_CNTL_DEFAULT 0x00000000 |
2802 | #define cfgBIFPLR4_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 |
2803 | #define cfgBIFPLR4_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 |
2804 | #define cfgBIFPLR4_0_MSI_MSG_DATA_DEFAULT 0x00000000 |
2805 | #define cfgBIFPLR4_0_MSI_MSG_DATA_64_DEFAULT 0x00000000 |
2806 | #define cfgBIFPLR4_0_SSID_CAP_LIST_DEFAULT 0x0000c800 |
2807 | #define cfgBIFPLR4_0_SSID_CAP_DEFAULT 0x00000000 |
2808 | #define cfgBIFPLR4_0_MSI_MAP_CAP_LIST_DEFAULT 0x00000000 |
2809 | #define cfgBIFPLR4_0_MSI_MAP_CAP_DEFAULT 0x00000000 |
2810 | #define cfgBIFPLR4_0_MSI_MAP_ADDR_LO_DEFAULT 0x00000000 |
2811 | #define cfgBIFPLR4_0_MSI_MAP_ADDR_HI_DEFAULT 0x00000000 |
2812 | #define cfgBIFPLR4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 |
2813 | #define cfgBIFPLR4_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 |
2814 | #define cfgBIFPLR4_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 |
2815 | #define cfgBIFPLR4_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 |
2816 | #define cfgBIFPLR4_0_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000 |
2817 | #define cfgBIFPLR4_0_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000 |
2818 | #define cfgBIFPLR4_0_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000 |
2819 | #define cfgBIFPLR4_0_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000 |
2820 | #define cfgBIFPLR4_0_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000 |
2821 | #define cfgBIFPLR4_0_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000 |
2822 | #define cfgBIFPLR4_0_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe |
2823 | #define cfgBIFPLR4_0_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000002 |
2824 | #define cfgBIFPLR4_0_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000 |
2825 | #define cfgBIFPLR4_0_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000 |
2826 | #define cfgBIFPLR4_0_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000002 |
2827 | #define cfgBIFPLR4_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000 |
2828 | #define cfgBIFPLR4_0_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000 |
2829 | #define cfgBIFPLR4_0_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000 |
2830 | #define cfgBIFPLR4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x27020000 |
2831 | #define cfgBIFPLR4_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 |
2832 | #define cfgBIFPLR4_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00400000 |
2833 | #define cfgBIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 |
2834 | #define cfgBIFPLR4_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 |
2835 | #define cfgBIFPLR4_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00006000 |
2836 | #define cfgBIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 |
2837 | #define cfgBIFPLR4_0_PCIE_HDR_LOG0_DEFAULT 0x00000000 |
2838 | #define cfgBIFPLR4_0_PCIE_HDR_LOG1_DEFAULT 0x00000000 |
2839 | #define cfgBIFPLR4_0_PCIE_HDR_LOG2_DEFAULT 0x00000000 |
2840 | #define cfgBIFPLR4_0_PCIE_HDR_LOG3_DEFAULT 0x00000000 |
2841 | #define cfgBIFPLR4_0_PCIE_ROOT_ERR_CMD_DEFAULT 0x00000000 |
2842 | #define cfgBIFPLR4_0_PCIE_ROOT_ERR_STATUS_DEFAULT 0x00000000 |
2843 | #define cfgBIFPLR4_0_PCIE_ERR_SRC_ID_DEFAULT 0x00000000 |
2844 | #define cfgBIFPLR4_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 |
2845 | #define cfgBIFPLR4_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 |
2846 | #define cfgBIFPLR4_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 |
2847 | #define cfgBIFPLR4_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 |
2848 | #define cfgBIFPLR4_0_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a000000 |
2849 | #define cfgBIFPLR4_0_PCIE_LINK_CNTL3_DEFAULT 0x00000000 |
2850 | #define cfgBIFPLR4_0_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000 |
2851 | #define cfgBIFPLR4_0_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
2852 | #define cfgBIFPLR4_0_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
2853 | #define cfgBIFPLR4_0_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
2854 | #define cfgBIFPLR4_0_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
2855 | #define cfgBIFPLR4_0_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
2856 | #define cfgBIFPLR4_0_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
2857 | #define cfgBIFPLR4_0_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
2858 | #define cfgBIFPLR4_0_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
2859 | #define cfgBIFPLR4_0_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
2860 | #define cfgBIFPLR4_0_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
2861 | #define cfgBIFPLR4_0_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
2862 | #define cfgBIFPLR4_0_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
2863 | #define cfgBIFPLR4_0_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
2864 | #define cfgBIFPLR4_0_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
2865 | #define cfgBIFPLR4_0_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
2866 | #define cfgBIFPLR4_0_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
2867 | #define cfgBIFPLR4_0_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2f000000 |
2868 | #define cfgBIFPLR4_0_PCIE_ACS_CAP_DEFAULT 0x00000000 |
2869 | #define cfgBIFPLR4_0_PCIE_ACS_CNTL_DEFAULT 0x00000000 |
2870 | #define cfgBIFPLR4_0_PCIE_MC_ENH_CAP_LIST_DEFAULT 0x32000000 |
2871 | #define cfgBIFPLR4_0_PCIE_MC_CAP_DEFAULT 0x00000000 |
2872 | #define cfgBIFPLR4_0_PCIE_MC_CNTL_DEFAULT 0x00000000 |
2873 | #define cfgBIFPLR4_0_PCIE_MC_ADDR0_DEFAULT 0x00000000 |
2874 | #define cfgBIFPLR4_0_PCIE_MC_ADDR1_DEFAULT 0x00000000 |
2875 | #define cfgBIFPLR4_0_PCIE_MC_RCV0_DEFAULT 0x00000000 |
2876 | #define cfgBIFPLR4_0_PCIE_MC_RCV1_DEFAULT 0x00000000 |
2877 | #define cfgBIFPLR4_0_PCIE_MC_BLOCK_ALL0_DEFAULT 0x00000000 |
2878 | #define cfgBIFPLR4_0_PCIE_MC_BLOCK_ALL1_DEFAULT 0x00000000 |
2879 | #define cfgBIFPLR4_0_PCIE_MC_BLOCK_UNTRANSLATED_0_DEFAULT 0x00000000 |
2880 | #define cfgBIFPLR4_0_PCIE_MC_BLOCK_UNTRANSLATED_1_DEFAULT 0x00000000 |
2881 | #define cfgBIFPLR4_0_PCIE_MC_OVERLAY_BAR0_DEFAULT 0x00000000 |
2882 | #define cfgBIFPLR4_0_PCIE_MC_OVERLAY_BAR1_DEFAULT 0x00000000 |
2883 | #define cfgBIFPLR4_0_PCIE_L1_PM_SUB_CAP_LIST_DEFAULT 0x00000000 |
2884 | #define cfgBIFPLR4_0_PCIE_L1_PM_SUB_CAP_DEFAULT 0x00000000 |
2885 | #define cfgBIFPLR4_0_PCIE_L1_PM_SUB_CNTL_DEFAULT 0x00000000 |
2886 | #define cfgBIFPLR4_0_PCIE_L1_PM_SUB_CNTL2_DEFAULT 0x00000028 |
2887 | #define cfgBIFPLR4_0_PCIE_DPC_ENH_CAP_LIST_DEFAULT 0x00000000 |
2888 | #define cfgBIFPLR4_0_PCIE_DPC_CAP_LIST_DEFAULT 0x00000000 |
2889 | #define cfgBIFPLR4_0_PCIE_DPC_CNTL_DEFAULT 0x00000000 |
2890 | #define cfgBIFPLR4_0_PCIE_DPC_STATUS_DEFAULT 0x00000000 |
2891 | #define cfgBIFPLR4_0_PCIE_DPC_ERROR_SOURCE_ID_DEFAULT 0x00000000 |
2892 | #define cfgBIFPLR4_0_PCIE_RP_PIO_STATUS_DEFAULT 0x00000000 |
2893 | #define cfgBIFPLR4_0_PCIE_RP_PIO_MASK_DEFAULT 0x00070707 |
2894 | #define cfgBIFPLR4_0_PCIE_RP_PIO_SEVERITY_DEFAULT 0x00000000 |
2895 | #define cfgBIFPLR4_0_PCIE_RP_PIO_SYSERROR_DEFAULT 0x00000000 |
2896 | #define cfgBIFPLR4_0_PCIE_RP_PIO_EXCEPTION_DEFAULT 0x00000000 |
2897 | #define cfgBIFPLR4_0_PCIE_RP_PIO_HDR_LOG0_DEFAULT 0x00000000 |
2898 | #define cfgBIFPLR4_0_PCIE_RP_PIO_HDR_LOG1_DEFAULT 0x00000000 |
2899 | #define cfgBIFPLR4_0_PCIE_RP_PIO_HDR_LOG2_DEFAULT 0x00000000 |
2900 | #define cfgBIFPLR4_0_PCIE_RP_PIO_HDR_LOG3_DEFAULT 0x00000000 |
2901 | #define cfgBIFPLR4_0_PCIE_RP_PIO_IMPSPEC_LOG_DEFAULT 0x00000000 |
2902 | #define cfgBIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG0_DEFAULT 0x00000000 |
2903 | #define cfgBIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG1_DEFAULT 0x00000000 |
2904 | #define cfgBIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG2_DEFAULT 0x00000000 |
2905 | #define cfgBIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG3_DEFAULT 0x00000000 |
2906 | #define cfgBIFPLR4_0_PCIE_ESM_CAP_LIST_DEFAULT 0x00000000 |
2907 | #define 0x00000000 |
2908 | #define 0x00000000 |
2909 | #define cfgBIFPLR4_0_PCIE_ESM_STATUS_DEFAULT 0x00000000 |
2910 | #define cfgBIFPLR4_0_PCIE_ESM_CTRL_DEFAULT 0x00000000 |
2911 | #define cfgBIFPLR4_0_PCIE_ESM_CAP_1_DEFAULT 0x00000000 |
2912 | #define cfgBIFPLR4_0_PCIE_ESM_CAP_2_DEFAULT 0x00000000 |
2913 | #define cfgBIFPLR4_0_PCIE_ESM_CAP_3_DEFAULT 0x00000000 |
2914 | #define cfgBIFPLR4_0_PCIE_ESM_CAP_4_DEFAULT 0x00000000 |
2915 | #define cfgBIFPLR4_0_PCIE_ESM_CAP_5_DEFAULT 0x00000000 |
2916 | #define cfgBIFPLR4_0_PCIE_ESM_CAP_6_DEFAULT 0x00000000 |
2917 | #define cfgBIFPLR4_0_PCIE_ESM_CAP_7_DEFAULT 0x00000000 |
2918 | |
2919 | |
2920 | // addressBlock: nbio_pcie0_bifplr5_cfgdecp |
2921 | #define cfgBIFPLR5_0_VENDOR_ID_DEFAULT 0x00000000 |
2922 | #define cfgBIFPLR5_0_DEVICE_ID_DEFAULT 0x00000000 |
2923 | #define cfgBIFPLR5_0_COMMAND_DEFAULT 0x00000000 |
2924 | #define cfgBIFPLR5_0_STATUS_DEFAULT 0x00000000 |
2925 | #define cfgBIFPLR5_0_REVISION_ID_DEFAULT 0x00000000 |
2926 | #define cfgBIFPLR5_0_PROG_INTERFACE_DEFAULT 0x00000000 |
2927 | #define cfgBIFPLR5_0_SUB_CLASS_DEFAULT 0x00000000 |
2928 | #define cfgBIFPLR5_0_BASE_CLASS_DEFAULT 0x00000000 |
2929 | #define cfgBIFPLR5_0_CACHE_LINE_DEFAULT 0x00000000 |
2930 | #define cfgBIFPLR5_0_LATENCY_DEFAULT 0x00000000 |
2931 | #define 0x00000000 |
2932 | #define cfgBIFPLR5_0_BIST_DEFAULT 0x00000000 |
2933 | #define cfgBIFPLR5_0_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 |
2934 | #define cfgBIFPLR5_0_IO_BASE_LIMIT_DEFAULT 0x00000000 |
2935 | #define cfgBIFPLR5_0_SECONDARY_STATUS_DEFAULT 0x00000000 |
2936 | #define cfgBIFPLR5_0_MEM_BASE_LIMIT_DEFAULT 0x00000000 |
2937 | #define cfgBIFPLR5_0_PREF_BASE_LIMIT_DEFAULT 0x00000000 |
2938 | #define cfgBIFPLR5_0_PREF_BASE_UPPER_DEFAULT 0x00000000 |
2939 | #define cfgBIFPLR5_0_PREF_LIMIT_UPPER_DEFAULT 0x00000000 |
2940 | #define cfgBIFPLR5_0_IO_BASE_LIMIT_HI_DEFAULT 0x00000000 |
2941 | #define cfgBIFPLR5_0_CAP_PTR_DEFAULT 0x00000000 |
2942 | #define cfgBIFPLR5_0_INTERRUPT_LINE_DEFAULT 0x000000ff |
2943 | #define cfgBIFPLR5_0_INTERRUPT_PIN_DEFAULT 0x00000000 |
2944 | #define cfgBIFPLR5_0_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000 |
2945 | #define cfgBIFPLR5_0_EXT_BRIDGE_CNTL_DEFAULT 0x00000000 |
2946 | #define cfgBIFPLR5_0_PMI_CAP_LIST_DEFAULT 0x00000000 |
2947 | #define cfgBIFPLR5_0_PMI_CAP_DEFAULT 0x00000000 |
2948 | #define cfgBIFPLR5_0_PMI_STATUS_CNTL_DEFAULT 0x00000000 |
2949 | #define cfgBIFPLR5_0_PCIE_CAP_LIST_DEFAULT 0x0000a000 |
2950 | #define cfgBIFPLR5_0_PCIE_CAP_DEFAULT 0x00000002 |
2951 | #define cfgBIFPLR5_0_DEVICE_CAP_DEFAULT 0x00000000 |
2952 | #define cfgBIFPLR5_0_DEVICE_CNTL_DEFAULT 0x00002810 |
2953 | #define cfgBIFPLR5_0_DEVICE_STATUS_DEFAULT 0x00000000 |
2954 | #define cfgBIFPLR5_0_LINK_CAP_DEFAULT 0x00011c03 |
2955 | #define cfgBIFPLR5_0_LINK_CNTL_DEFAULT 0x00000000 |
2956 | #define cfgBIFPLR5_0_LINK_STATUS_DEFAULT 0x00000001 |
2957 | #define cfgBIFPLR5_0_SLOT_CAP_DEFAULT 0x00000000 |
2958 | #define cfgBIFPLR5_0_SLOT_CNTL_DEFAULT 0x00000000 |
2959 | #define cfgBIFPLR5_0_SLOT_STATUS_DEFAULT 0x00000000 |
2960 | #define cfgBIFPLR5_0_ROOT_CNTL_DEFAULT 0x00000000 |
2961 | #define cfgBIFPLR5_0_ROOT_CAP_DEFAULT 0x00000000 |
2962 | #define cfgBIFPLR5_0_ROOT_STATUS_DEFAULT 0x00000000 |
2963 | #define cfgBIFPLR5_0_DEVICE_CAP2_DEFAULT 0x00000000 |
2964 | #define cfgBIFPLR5_0_DEVICE_CNTL2_DEFAULT 0x00000000 |
2965 | #define cfgBIFPLR5_0_DEVICE_STATUS2_DEFAULT 0x00000000 |
2966 | #define cfgBIFPLR5_0_LINK_CAP2_DEFAULT 0x0000000e |
2967 | #define cfgBIFPLR5_0_LINK_CNTL2_DEFAULT 0x00000003 |
2968 | #define cfgBIFPLR5_0_LINK_STATUS2_DEFAULT 0x00000000 |
2969 | #define cfgBIFPLR5_0_SLOT_CAP2_DEFAULT 0x00000000 |
2970 | #define cfgBIFPLR5_0_SLOT_CNTL2_DEFAULT 0x00000000 |
2971 | #define cfgBIFPLR5_0_SLOT_STATUS2_DEFAULT 0x00000000 |
2972 | #define cfgBIFPLR5_0_MSI_CAP_LIST_DEFAULT 0x0000c000 |
2973 | #define cfgBIFPLR5_0_MSI_MSG_CNTL_DEFAULT 0x00000000 |
2974 | #define cfgBIFPLR5_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 |
2975 | #define cfgBIFPLR5_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 |
2976 | #define cfgBIFPLR5_0_MSI_MSG_DATA_DEFAULT 0x00000000 |
2977 | #define cfgBIFPLR5_0_MSI_MSG_DATA_64_DEFAULT 0x00000000 |
2978 | #define cfgBIFPLR5_0_SSID_CAP_LIST_DEFAULT 0x0000c800 |
2979 | #define cfgBIFPLR5_0_SSID_CAP_DEFAULT 0x00000000 |
2980 | #define cfgBIFPLR5_0_MSI_MAP_CAP_LIST_DEFAULT 0x00000000 |
2981 | #define cfgBIFPLR5_0_MSI_MAP_CAP_DEFAULT 0x00000000 |
2982 | #define cfgBIFPLR5_0_MSI_MAP_ADDR_LO_DEFAULT 0x00000000 |
2983 | #define cfgBIFPLR5_0_MSI_MAP_ADDR_HI_DEFAULT 0x00000000 |
2984 | #define cfgBIFPLR5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 |
2985 | #define cfgBIFPLR5_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 |
2986 | #define cfgBIFPLR5_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 |
2987 | #define cfgBIFPLR5_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 |
2988 | #define cfgBIFPLR5_0_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000 |
2989 | #define cfgBIFPLR5_0_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000 |
2990 | #define cfgBIFPLR5_0_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000 |
2991 | #define cfgBIFPLR5_0_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000 |
2992 | #define cfgBIFPLR5_0_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000 |
2993 | #define cfgBIFPLR5_0_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000 |
2994 | #define cfgBIFPLR5_0_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe |
2995 | #define cfgBIFPLR5_0_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000002 |
2996 | #define cfgBIFPLR5_0_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000 |
2997 | #define cfgBIFPLR5_0_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000 |
2998 | #define cfgBIFPLR5_0_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000002 |
2999 | #define cfgBIFPLR5_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000 |
3000 | #define cfgBIFPLR5_0_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000 |
3001 | #define cfgBIFPLR5_0_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000 |
3002 | #define cfgBIFPLR5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x27020000 |
3003 | #define cfgBIFPLR5_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 |
3004 | #define cfgBIFPLR5_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00400000 |
3005 | #define cfgBIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 |
3006 | #define cfgBIFPLR5_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 |
3007 | #define cfgBIFPLR5_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00006000 |
3008 | #define cfgBIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 |
3009 | #define cfgBIFPLR5_0_PCIE_HDR_LOG0_DEFAULT 0x00000000 |
3010 | #define cfgBIFPLR5_0_PCIE_HDR_LOG1_DEFAULT 0x00000000 |
3011 | #define cfgBIFPLR5_0_PCIE_HDR_LOG2_DEFAULT 0x00000000 |
3012 | #define cfgBIFPLR5_0_PCIE_HDR_LOG3_DEFAULT 0x00000000 |
3013 | #define cfgBIFPLR5_0_PCIE_ROOT_ERR_CMD_DEFAULT 0x00000000 |
3014 | #define cfgBIFPLR5_0_PCIE_ROOT_ERR_STATUS_DEFAULT 0x00000000 |
3015 | #define cfgBIFPLR5_0_PCIE_ERR_SRC_ID_DEFAULT 0x00000000 |
3016 | #define cfgBIFPLR5_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 |
3017 | #define cfgBIFPLR5_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 |
3018 | #define cfgBIFPLR5_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 |
3019 | #define cfgBIFPLR5_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 |
3020 | #define cfgBIFPLR5_0_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a000000 |
3021 | #define cfgBIFPLR5_0_PCIE_LINK_CNTL3_DEFAULT 0x00000000 |
3022 | #define cfgBIFPLR5_0_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000 |
3023 | #define cfgBIFPLR5_0_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
3024 | #define cfgBIFPLR5_0_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
3025 | #define cfgBIFPLR5_0_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
3026 | #define cfgBIFPLR5_0_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
3027 | #define cfgBIFPLR5_0_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
3028 | #define cfgBIFPLR5_0_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
3029 | #define cfgBIFPLR5_0_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
3030 | #define cfgBIFPLR5_0_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
3031 | #define cfgBIFPLR5_0_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
3032 | #define cfgBIFPLR5_0_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
3033 | #define cfgBIFPLR5_0_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
3034 | #define cfgBIFPLR5_0_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
3035 | #define cfgBIFPLR5_0_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
3036 | #define cfgBIFPLR5_0_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
3037 | #define cfgBIFPLR5_0_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
3038 | #define cfgBIFPLR5_0_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
3039 | #define cfgBIFPLR5_0_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2f000000 |
3040 | #define cfgBIFPLR5_0_PCIE_ACS_CAP_DEFAULT 0x00000000 |
3041 | #define cfgBIFPLR5_0_PCIE_ACS_CNTL_DEFAULT 0x00000000 |
3042 | #define cfgBIFPLR5_0_PCIE_MC_ENH_CAP_LIST_DEFAULT 0x32000000 |
3043 | #define cfgBIFPLR5_0_PCIE_MC_CAP_DEFAULT 0x00000000 |
3044 | #define cfgBIFPLR5_0_PCIE_MC_CNTL_DEFAULT 0x00000000 |
3045 | #define cfgBIFPLR5_0_PCIE_MC_ADDR0_DEFAULT 0x00000000 |
3046 | #define cfgBIFPLR5_0_PCIE_MC_ADDR1_DEFAULT 0x00000000 |
3047 | #define cfgBIFPLR5_0_PCIE_MC_RCV0_DEFAULT 0x00000000 |
3048 | #define cfgBIFPLR5_0_PCIE_MC_RCV1_DEFAULT 0x00000000 |
3049 | #define cfgBIFPLR5_0_PCIE_MC_BLOCK_ALL0_DEFAULT 0x00000000 |
3050 | #define cfgBIFPLR5_0_PCIE_MC_BLOCK_ALL1_DEFAULT 0x00000000 |
3051 | #define cfgBIFPLR5_0_PCIE_MC_BLOCK_UNTRANSLATED_0_DEFAULT 0x00000000 |
3052 | #define cfgBIFPLR5_0_PCIE_MC_BLOCK_UNTRANSLATED_1_DEFAULT 0x00000000 |
3053 | #define cfgBIFPLR5_0_PCIE_MC_OVERLAY_BAR0_DEFAULT 0x00000000 |
3054 | #define cfgBIFPLR5_0_PCIE_MC_OVERLAY_BAR1_DEFAULT 0x00000000 |
3055 | #define cfgBIFPLR5_0_PCIE_L1_PM_SUB_CAP_LIST_DEFAULT 0x00000000 |
3056 | #define cfgBIFPLR5_0_PCIE_L1_PM_SUB_CAP_DEFAULT 0x00000000 |
3057 | #define cfgBIFPLR5_0_PCIE_L1_PM_SUB_CNTL_DEFAULT 0x00000000 |
3058 | #define cfgBIFPLR5_0_PCIE_L1_PM_SUB_CNTL2_DEFAULT 0x00000028 |
3059 | #define cfgBIFPLR5_0_PCIE_DPC_ENH_CAP_LIST_DEFAULT 0x00000000 |
3060 | #define cfgBIFPLR5_0_PCIE_DPC_CAP_LIST_DEFAULT 0x00000000 |
3061 | #define cfgBIFPLR5_0_PCIE_DPC_CNTL_DEFAULT 0x00000000 |
3062 | #define cfgBIFPLR5_0_PCIE_DPC_STATUS_DEFAULT 0x00000000 |
3063 | #define cfgBIFPLR5_0_PCIE_DPC_ERROR_SOURCE_ID_DEFAULT 0x00000000 |
3064 | #define cfgBIFPLR5_0_PCIE_RP_PIO_STATUS_DEFAULT 0x00000000 |
3065 | #define cfgBIFPLR5_0_PCIE_RP_PIO_MASK_DEFAULT 0x00070707 |
3066 | #define cfgBIFPLR5_0_PCIE_RP_PIO_SEVERITY_DEFAULT 0x00000000 |
3067 | #define cfgBIFPLR5_0_PCIE_RP_PIO_SYSERROR_DEFAULT 0x00000000 |
3068 | #define cfgBIFPLR5_0_PCIE_RP_PIO_EXCEPTION_DEFAULT 0x00000000 |
3069 | #define cfgBIFPLR5_0_PCIE_RP_PIO_HDR_LOG0_DEFAULT 0x00000000 |
3070 | #define cfgBIFPLR5_0_PCIE_RP_PIO_HDR_LOG1_DEFAULT 0x00000000 |
3071 | #define cfgBIFPLR5_0_PCIE_RP_PIO_HDR_LOG2_DEFAULT 0x00000000 |
3072 | #define cfgBIFPLR5_0_PCIE_RP_PIO_HDR_LOG3_DEFAULT 0x00000000 |
3073 | #define cfgBIFPLR5_0_PCIE_RP_PIO_IMPSPEC_LOG_DEFAULT 0x00000000 |
3074 | #define cfgBIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG0_DEFAULT 0x00000000 |
3075 | #define cfgBIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG1_DEFAULT 0x00000000 |
3076 | #define cfgBIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG2_DEFAULT 0x00000000 |
3077 | #define cfgBIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG3_DEFAULT 0x00000000 |
3078 | #define cfgBIFPLR5_0_PCIE_ESM_CAP_LIST_DEFAULT 0x00000000 |
3079 | #define 0x00000000 |
3080 | #define 0x00000000 |
3081 | #define cfgBIFPLR5_0_PCIE_ESM_STATUS_DEFAULT 0x00000000 |
3082 | #define cfgBIFPLR5_0_PCIE_ESM_CTRL_DEFAULT 0x00000000 |
3083 | #define cfgBIFPLR5_0_PCIE_ESM_CAP_1_DEFAULT 0x00000000 |
3084 | #define cfgBIFPLR5_0_PCIE_ESM_CAP_2_DEFAULT 0x00000000 |
3085 | #define cfgBIFPLR5_0_PCIE_ESM_CAP_3_DEFAULT 0x00000000 |
3086 | #define cfgBIFPLR5_0_PCIE_ESM_CAP_4_DEFAULT 0x00000000 |
3087 | #define cfgBIFPLR5_0_PCIE_ESM_CAP_5_DEFAULT 0x00000000 |
3088 | #define cfgBIFPLR5_0_PCIE_ESM_CAP_6_DEFAULT 0x00000000 |
3089 | #define cfgBIFPLR5_0_PCIE_ESM_CAP_7_DEFAULT 0x00000000 |
3090 | |
3091 | |
3092 | // addressBlock: nbio_pcie0_bifplr6_cfgdecp |
3093 | #define cfgBIFPLR6_0_VENDOR_ID_DEFAULT 0x00000000 |
3094 | #define cfgBIFPLR6_0_DEVICE_ID_DEFAULT 0x00000000 |
3095 | #define cfgBIFPLR6_0_COMMAND_DEFAULT 0x00000000 |
3096 | #define cfgBIFPLR6_0_STATUS_DEFAULT 0x00000000 |
3097 | #define cfgBIFPLR6_0_REVISION_ID_DEFAULT 0x00000000 |
3098 | #define cfgBIFPLR6_0_PROG_INTERFACE_DEFAULT 0x00000000 |
3099 | #define cfgBIFPLR6_0_SUB_CLASS_DEFAULT 0x00000000 |
3100 | #define cfgBIFPLR6_0_BASE_CLASS_DEFAULT 0x00000000 |
3101 | #define cfgBIFPLR6_0_CACHE_LINE_DEFAULT 0x00000000 |
3102 | #define cfgBIFPLR6_0_LATENCY_DEFAULT 0x00000000 |
3103 | #define 0x00000000 |
3104 | #define cfgBIFPLR6_0_BIST_DEFAULT 0x00000000 |
3105 | #define cfgBIFPLR6_0_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 |
3106 | #define cfgBIFPLR6_0_IO_BASE_LIMIT_DEFAULT 0x00000000 |
3107 | #define cfgBIFPLR6_0_SECONDARY_STATUS_DEFAULT 0x00000000 |
3108 | #define cfgBIFPLR6_0_MEM_BASE_LIMIT_DEFAULT 0x00000000 |
3109 | #define cfgBIFPLR6_0_PREF_BASE_LIMIT_DEFAULT 0x00000000 |
3110 | #define cfgBIFPLR6_0_PREF_BASE_UPPER_DEFAULT 0x00000000 |
3111 | #define cfgBIFPLR6_0_PREF_LIMIT_UPPER_DEFAULT 0x00000000 |
3112 | #define cfgBIFPLR6_0_IO_BASE_LIMIT_HI_DEFAULT 0x00000000 |
3113 | #define cfgBIFPLR6_0_CAP_PTR_DEFAULT 0x00000000 |
3114 | #define cfgBIFPLR6_0_INTERRUPT_LINE_DEFAULT 0x000000ff |
3115 | #define cfgBIFPLR6_0_INTERRUPT_PIN_DEFAULT 0x00000000 |
3116 | #define cfgBIFPLR6_0_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000 |
3117 | #define cfgBIFPLR6_0_EXT_BRIDGE_CNTL_DEFAULT 0x00000000 |
3118 | #define cfgBIFPLR6_0_PMI_CAP_LIST_DEFAULT 0x00000000 |
3119 | #define cfgBIFPLR6_0_PMI_CAP_DEFAULT 0x00000000 |
3120 | #define cfgBIFPLR6_0_PMI_STATUS_CNTL_DEFAULT 0x00000000 |
3121 | #define cfgBIFPLR6_0_PCIE_CAP_LIST_DEFAULT 0x0000a000 |
3122 | #define cfgBIFPLR6_0_PCIE_CAP_DEFAULT 0x00000002 |
3123 | #define cfgBIFPLR6_0_DEVICE_CAP_DEFAULT 0x00000000 |
3124 | #define cfgBIFPLR6_0_DEVICE_CNTL_DEFAULT 0x00002810 |
3125 | #define cfgBIFPLR6_0_DEVICE_STATUS_DEFAULT 0x00000000 |
3126 | #define cfgBIFPLR6_0_LINK_CAP_DEFAULT 0x00011c03 |
3127 | #define cfgBIFPLR6_0_LINK_CNTL_DEFAULT 0x00000000 |
3128 | #define cfgBIFPLR6_0_LINK_STATUS_DEFAULT 0x00000001 |
3129 | #define cfgBIFPLR6_0_SLOT_CAP_DEFAULT 0x00000000 |
3130 | #define cfgBIFPLR6_0_SLOT_CNTL_DEFAULT 0x00000000 |
3131 | #define cfgBIFPLR6_0_SLOT_STATUS_DEFAULT 0x00000000 |
3132 | #define cfgBIFPLR6_0_ROOT_CNTL_DEFAULT 0x00000000 |
3133 | #define cfgBIFPLR6_0_ROOT_CAP_DEFAULT 0x00000000 |
3134 | #define cfgBIFPLR6_0_ROOT_STATUS_DEFAULT 0x00000000 |
3135 | #define cfgBIFPLR6_0_DEVICE_CAP2_DEFAULT 0x00000000 |
3136 | #define cfgBIFPLR6_0_DEVICE_CNTL2_DEFAULT 0x00000000 |
3137 | #define cfgBIFPLR6_0_DEVICE_STATUS2_DEFAULT 0x00000000 |
3138 | #define cfgBIFPLR6_0_LINK_CAP2_DEFAULT 0x0000000e |
3139 | #define cfgBIFPLR6_0_LINK_CNTL2_DEFAULT 0x00000003 |
3140 | #define cfgBIFPLR6_0_LINK_STATUS2_DEFAULT 0x00000000 |
3141 | #define cfgBIFPLR6_0_SLOT_CAP2_DEFAULT 0x00000000 |
3142 | #define cfgBIFPLR6_0_SLOT_CNTL2_DEFAULT 0x00000000 |
3143 | #define cfgBIFPLR6_0_SLOT_STATUS2_DEFAULT 0x00000000 |
3144 | #define cfgBIFPLR6_0_MSI_CAP_LIST_DEFAULT 0x0000c000 |
3145 | #define cfgBIFPLR6_0_MSI_MSG_CNTL_DEFAULT 0x00000000 |
3146 | #define cfgBIFPLR6_0_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 |
3147 | #define cfgBIFPLR6_0_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 |
3148 | #define cfgBIFPLR6_0_MSI_MSG_DATA_DEFAULT 0x00000000 |
3149 | #define cfgBIFPLR6_0_MSI_MSG_DATA_64_DEFAULT 0x00000000 |
3150 | #define cfgBIFPLR6_0_SSID_CAP_LIST_DEFAULT 0x0000c800 |
3151 | #define cfgBIFPLR6_0_SSID_CAP_DEFAULT 0x00000000 |
3152 | #define cfgBIFPLR6_0_MSI_MAP_CAP_LIST_DEFAULT 0x00000000 |
3153 | #define cfgBIFPLR6_0_MSI_MAP_CAP_DEFAULT 0x00000000 |
3154 | #define cfgBIFPLR6_0_MSI_MAP_ADDR_LO_DEFAULT 0x00000000 |
3155 | #define cfgBIFPLR6_0_MSI_MAP_ADDR_HI_DEFAULT 0x00000000 |
3156 | #define cfgBIFPLR6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 |
3157 | #define cfgBIFPLR6_0_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 |
3158 | #define cfgBIFPLR6_0_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 |
3159 | #define cfgBIFPLR6_0_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 |
3160 | #define cfgBIFPLR6_0_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000 |
3161 | #define cfgBIFPLR6_0_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000 |
3162 | #define cfgBIFPLR6_0_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000 |
3163 | #define cfgBIFPLR6_0_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000 |
3164 | #define cfgBIFPLR6_0_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000 |
3165 | #define cfgBIFPLR6_0_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000 |
3166 | #define cfgBIFPLR6_0_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe |
3167 | #define cfgBIFPLR6_0_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000002 |
3168 | #define cfgBIFPLR6_0_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000 |
3169 | #define cfgBIFPLR6_0_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000 |
3170 | #define cfgBIFPLR6_0_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000002 |
3171 | #define cfgBIFPLR6_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000 |
3172 | #define cfgBIFPLR6_0_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000 |
3173 | #define cfgBIFPLR6_0_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000 |
3174 | #define cfgBIFPLR6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x27020000 |
3175 | #define cfgBIFPLR6_0_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 |
3176 | #define cfgBIFPLR6_0_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00400000 |
3177 | #define cfgBIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 |
3178 | #define cfgBIFPLR6_0_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 |
3179 | #define cfgBIFPLR6_0_PCIE_CORR_ERR_MASK_DEFAULT 0x00006000 |
3180 | #define cfgBIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 |
3181 | #define cfgBIFPLR6_0_PCIE_HDR_LOG0_DEFAULT 0x00000000 |
3182 | #define cfgBIFPLR6_0_PCIE_HDR_LOG1_DEFAULT 0x00000000 |
3183 | #define cfgBIFPLR6_0_PCIE_HDR_LOG2_DEFAULT 0x00000000 |
3184 | #define cfgBIFPLR6_0_PCIE_HDR_LOG3_DEFAULT 0x00000000 |
3185 | #define cfgBIFPLR6_0_PCIE_ROOT_ERR_CMD_DEFAULT 0x00000000 |
3186 | #define cfgBIFPLR6_0_PCIE_ROOT_ERR_STATUS_DEFAULT 0x00000000 |
3187 | #define cfgBIFPLR6_0_PCIE_ERR_SRC_ID_DEFAULT 0x00000000 |
3188 | #define cfgBIFPLR6_0_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 |
3189 | #define cfgBIFPLR6_0_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 |
3190 | #define cfgBIFPLR6_0_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 |
3191 | #define cfgBIFPLR6_0_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 |
3192 | #define cfgBIFPLR6_0_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a000000 |
3193 | #define cfgBIFPLR6_0_PCIE_LINK_CNTL3_DEFAULT 0x00000000 |
3194 | #define cfgBIFPLR6_0_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000 |
3195 | #define cfgBIFPLR6_0_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
3196 | #define cfgBIFPLR6_0_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
3197 | #define cfgBIFPLR6_0_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
3198 | #define cfgBIFPLR6_0_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
3199 | #define cfgBIFPLR6_0_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
3200 | #define cfgBIFPLR6_0_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
3201 | #define cfgBIFPLR6_0_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
3202 | #define cfgBIFPLR6_0_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
3203 | #define cfgBIFPLR6_0_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
3204 | #define cfgBIFPLR6_0_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
3205 | #define cfgBIFPLR6_0_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
3206 | #define cfgBIFPLR6_0_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
3207 | #define cfgBIFPLR6_0_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
3208 | #define cfgBIFPLR6_0_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
3209 | #define cfgBIFPLR6_0_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
3210 | #define cfgBIFPLR6_0_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
3211 | #define cfgBIFPLR6_0_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2f000000 |
3212 | #define cfgBIFPLR6_0_PCIE_ACS_CAP_DEFAULT 0x00000000 |
3213 | #define cfgBIFPLR6_0_PCIE_ACS_CNTL_DEFAULT 0x00000000 |
3214 | #define cfgBIFPLR6_0_PCIE_MC_ENH_CAP_LIST_DEFAULT 0x32000000 |
3215 | #define cfgBIFPLR6_0_PCIE_MC_CAP_DEFAULT 0x00000000 |
3216 | #define cfgBIFPLR6_0_PCIE_MC_CNTL_DEFAULT 0x00000000 |
3217 | #define cfgBIFPLR6_0_PCIE_MC_ADDR0_DEFAULT 0x00000000 |
3218 | #define cfgBIFPLR6_0_PCIE_MC_ADDR1_DEFAULT 0x00000000 |
3219 | #define cfgBIFPLR6_0_PCIE_MC_RCV0_DEFAULT 0x00000000 |
3220 | #define cfgBIFPLR6_0_PCIE_MC_RCV1_DEFAULT 0x00000000 |
3221 | #define cfgBIFPLR6_0_PCIE_MC_BLOCK_ALL0_DEFAULT 0x00000000 |
3222 | #define cfgBIFPLR6_0_PCIE_MC_BLOCK_ALL1_DEFAULT 0x00000000 |
3223 | #define cfgBIFPLR6_0_PCIE_MC_BLOCK_UNTRANSLATED_0_DEFAULT 0x00000000 |
3224 | #define cfgBIFPLR6_0_PCIE_MC_BLOCK_UNTRANSLATED_1_DEFAULT 0x00000000 |
3225 | #define cfgBIFPLR6_0_PCIE_MC_OVERLAY_BAR0_DEFAULT 0x00000000 |
3226 | #define cfgBIFPLR6_0_PCIE_MC_OVERLAY_BAR1_DEFAULT 0x00000000 |
3227 | #define cfgBIFPLR6_0_PCIE_L1_PM_SUB_CAP_LIST_DEFAULT 0x00000000 |
3228 | #define cfgBIFPLR6_0_PCIE_L1_PM_SUB_CAP_DEFAULT 0x00000000 |
3229 | #define cfgBIFPLR6_0_PCIE_L1_PM_SUB_CNTL_DEFAULT 0x00000000 |
3230 | #define cfgBIFPLR6_0_PCIE_L1_PM_SUB_CNTL2_DEFAULT 0x00000028 |
3231 | #define cfgBIFPLR6_0_PCIE_DPC_ENH_CAP_LIST_DEFAULT 0x00000000 |
3232 | #define cfgBIFPLR6_0_PCIE_DPC_CAP_LIST_DEFAULT 0x00000000 |
3233 | #define cfgBIFPLR6_0_PCIE_DPC_CNTL_DEFAULT 0x00000000 |
3234 | #define cfgBIFPLR6_0_PCIE_DPC_STATUS_DEFAULT 0x00000000 |
3235 | #define cfgBIFPLR6_0_PCIE_DPC_ERROR_SOURCE_ID_DEFAULT 0x00000000 |
3236 | #define cfgBIFPLR6_0_PCIE_RP_PIO_STATUS_DEFAULT 0x00000000 |
3237 | #define cfgBIFPLR6_0_PCIE_RP_PIO_MASK_DEFAULT 0x00070707 |
3238 | #define cfgBIFPLR6_0_PCIE_RP_PIO_SEVERITY_DEFAULT 0x00000000 |
3239 | #define cfgBIFPLR6_0_PCIE_RP_PIO_SYSERROR_DEFAULT 0x00000000 |
3240 | #define cfgBIFPLR6_0_PCIE_RP_PIO_EXCEPTION_DEFAULT 0x00000000 |
3241 | #define cfgBIFPLR6_0_PCIE_RP_PIO_HDR_LOG0_DEFAULT 0x00000000 |
3242 | #define cfgBIFPLR6_0_PCIE_RP_PIO_HDR_LOG1_DEFAULT 0x00000000 |
3243 | #define cfgBIFPLR6_0_PCIE_RP_PIO_HDR_LOG2_DEFAULT 0x00000000 |
3244 | #define cfgBIFPLR6_0_PCIE_RP_PIO_HDR_LOG3_DEFAULT 0x00000000 |
3245 | #define cfgBIFPLR6_0_PCIE_RP_PIO_IMPSPEC_LOG_DEFAULT 0x00000000 |
3246 | #define cfgBIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG0_DEFAULT 0x00000000 |
3247 | #define cfgBIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG1_DEFAULT 0x00000000 |
3248 | #define cfgBIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG2_DEFAULT 0x00000000 |
3249 | #define cfgBIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG3_DEFAULT 0x00000000 |
3250 | #define cfgBIFPLR6_0_PCIE_ESM_CAP_LIST_DEFAULT 0x00000000 |
3251 | #define 0x00000000 |
3252 | #define 0x00000000 |
3253 | #define cfgBIFPLR6_0_PCIE_ESM_STATUS_DEFAULT 0x00000000 |
3254 | #define cfgBIFPLR6_0_PCIE_ESM_CTRL_DEFAULT 0x00000000 |
3255 | #define cfgBIFPLR6_0_PCIE_ESM_CAP_1_DEFAULT 0x00000000 |
3256 | #define cfgBIFPLR6_0_PCIE_ESM_CAP_2_DEFAULT 0x00000000 |
3257 | #define cfgBIFPLR6_0_PCIE_ESM_CAP_3_DEFAULT 0x00000000 |
3258 | #define cfgBIFPLR6_0_PCIE_ESM_CAP_4_DEFAULT 0x00000000 |
3259 | #define cfgBIFPLR6_0_PCIE_ESM_CAP_5_DEFAULT 0x00000000 |
3260 | #define cfgBIFPLR6_0_PCIE_ESM_CAP_6_DEFAULT 0x00000000 |
3261 | #define cfgBIFPLR6_0_PCIE_ESM_CAP_7_DEFAULT 0x00000000 |
3262 | |
3263 | |
3264 | // addressBlock: nbio_dbgu0_dbgudec |
3265 | #define mmport_a_addr_DEFAULT 0x00000000 |
3266 | #define mmport_a_data_lo_DEFAULT 0x00000000 |
3267 | #define mmport_a_data_hi_DEFAULT 0x00000000 |
3268 | #define mmport_b_addr_DEFAULT 0x00000000 |
3269 | #define mmport_b_data_lo_DEFAULT 0x00000000 |
3270 | #define mmport_b_data_hi_DEFAULT 0x00000000 |
3271 | #define mmport_c_addr_DEFAULT 0x00000000 |
3272 | #define mmport_c_data_lo_DEFAULT 0x00000000 |
3273 | #define mmport_c_data_hi_DEFAULT 0x00000000 |
3274 | #define mmport_d_addr_DEFAULT 0x00000000 |
3275 | #define mmport_d_data_lo_DEFAULT 0x00000000 |
3276 | #define mmport_d_data_hi_DEFAULT 0x00000000 |
3277 | |
3278 | |
3279 | // addressBlock: nbio_nbif0_gdc_GDCDEC |
3280 | #define smnGDC0_NGDC_SDP_PORT_CTRL_DEFAULT 0x0000000f |
3281 | #define smnGDC0_SHUB_REGS_IF_CTL_DEFAULT 0x00000000 |
3282 | #define smnGDC0_NGDC_RESERVED_0_DEFAULT 0x00000000 |
3283 | #define smnGDC0_NGDC_RESERVED_1_DEFAULT 0x00000000 |
3284 | #define smnGDC0_NGDC_SDP_PORT_CTRL_SOCCLK_DEFAULT 0x0000000f |
3285 | #define smnGDC0_BIF_SDMA0_DOORBELL_RANGE_DEFAULT 0x00000000 |
3286 | #define smnGDC0_BIF_SDMA1_DOORBELL_RANGE_DEFAULT 0x00000000 |
3287 | #define smnGDC0_BIF_IH_DOORBELL_RANGE_DEFAULT 0x00000000 |
3288 | #define smnGDC0_BIF_MMSCH0_DOORBELL_RANGE_DEFAULT 0x00000000 |
3289 | #define smnGDC0_ATDMA_MISC_CNTL_DEFAULT 0x04040001 |
3290 | #define smnGDC0_BIF_DOORBELL_FENCE_CNTL_DEFAULT 0x00000000 |
3291 | #define smnGDC0_S2A_MISC_CNTL_DEFAULT 0x00000000 |
3292 | #define smnGDC0_GDC_PG_MISC_CNTL_DEFAULT 0x00000000 |
3293 | |
3294 | |
3295 | // addressBlock: nbio_nbif0_syshub_mmreg_direct_syshubdirect |
3296 | #define smnSYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SOCCLK_DEFAULT 0x00000000 |
3297 | #define smnSYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL2_SOCCLK_DEFAULT 0x00000100 |
3298 | #define smnSYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK_DEFAULT 0x00000000 |
3299 | #define smnSYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK_DEFAULT 0x00000000 |
3300 | #define smnSYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_SYSHUB_QOS_CNTL_DEFAULT 0x0000001e |
3301 | #define smnSYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_SYSHUB_QOS_CNTL_DEFAULT 0x0000001e |
3302 | #define smnSYSHUB_MMREG_DIRECT_DMA_CLK0_SW2_SYSHUB_QOS_CNTL_DEFAULT 0x0000001e |
3303 | #define smnSYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL0_CNTL_DEFAULT 0x20200000 |
3304 | #define smnSYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL1_CNTL_DEFAULT 0x20200000 |
3305 | #define smnSYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL2_CNTL_DEFAULT 0x20200000 |
3306 | #define smnSYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL3_CNTL_DEFAULT 0x20200000 |
3307 | #define smnSYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL4_CNTL_DEFAULT 0x20200000 |
3308 | #define smnSYSHUB_MMREG_DIRECT_DMA_CLK0_SW0_CL5_CNTL_DEFAULT 0x20200000 |
3309 | #define smnSYSHUB_MMREG_DIRECT_DMA_CLK0_SW1_CL0_CNTL_DEFAULT 0x20200000 |
3310 | #define smnSYSHUB_MMREG_DIRECT_DMA_CLK0_SW2_CL0_CNTL_DEFAULT 0x20200000 |
3311 | #define smnSYSHUB_MMREG_DIRECT_HST_CLK0_SW0_CL0_CNTL_DEFAULT 0x00000000 |
3312 | #define smnSYSHUB_MMREG_DIRECT_HST_CLK0_SW0_CL1_CNTL_DEFAULT 0x00000000 |
3313 | #define smnSYSHUB_MMREG_DIRECT_HST_CLK0_SW0_CL2_CNTL_DEFAULT 0x00000000 |
3314 | #define smnSYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL0_CNTL_DEFAULT 0x00000000 |
3315 | #define smnSYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL1_CNTL_DEFAULT 0x00000000 |
3316 | #define smnSYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL2_CNTL_DEFAULT 0x00000000 |
3317 | #define smnSYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL3_CNTL_DEFAULT 0x00000000 |
3318 | #define smnSYSHUB_MMREG_DIRECT_HST_CLK0_SW1_CL4_CNTL_DEFAULT 0x00000000 |
3319 | #define smnSYSHUB_MMREG_DIRECT_SYSHUB_CG_CNTL_DEFAULT 0x00082000 |
3320 | #define smnSYSHUB_MMREG_DIRECT_SYSHUB_TRANS_IDLE_DEFAULT 0x00000000 |
3321 | #define smnSYSHUB_MMREG_DIRECT_SYSHUB_HP_TIMER_DEFAULT 0x00000100 |
3322 | #define smnSYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK_DEFAULT 0x00000080 |
3323 | #define smnSYSHUB_MMREG_DIRECT_SYSUB_CPF_DOORBELL_RS_RESET_DEFAULT 0x00000000 |
3324 | #define smnSYSHUB_MMREG_DIRECT_SYSHUB_SCRATCH_DEFAULT 0x00000040 |
3325 | #define smnSYSHUB_MMREG_DIRECT_SYSHUB_CL_MASK_DEFAULT 0x00000000 |
3326 | #define smnSYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL_SHUBCLK_DEFAULT 0x00000000 |
3327 | #define smnSYSHUB_MMREG_DIRECT_SYSHUB_DS_CTRL2_SHUBCLK_DEFAULT 0x00000100 |
3328 | #define smnSYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK_DEFAULT 0x00000000 |
3329 | #define smnSYSHUB_MMREG_DIRECT_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK_DEFAULT 0x00000000 |
3330 | #define smnSYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_SYSHUB_QOS_CNTL_DEFAULT 0x0000001e |
3331 | #define smnSYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_SYSHUB_QOS_CNTL_DEFAULT 0x0000001e |
3332 | #define smnSYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL0_CNTL_DEFAULT 0x20200000 |
3333 | #define smnSYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL1_CNTL_DEFAULT 0x20200000 |
3334 | #define smnSYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL2_CNTL_DEFAULT 0x20200000 |
3335 | #define smnSYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL3_CNTL_DEFAULT 0x20200000 |
3336 | #define smnSYSHUB_MMREG_DIRECT_DMA_CLK1_SW0_CL4_CNTL_DEFAULT 0x20200000 |
3337 | #define smnSYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL0_CNTL_DEFAULT 0x20200000 |
3338 | #define smnSYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL1_CNTL_DEFAULT 0x20200000 |
3339 | #define smnSYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL2_CNTL_DEFAULT 0x20200000 |
3340 | #define smnSYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL3_CNTL_DEFAULT 0x20200000 |
3341 | #define smnSYSHUB_MMREG_DIRECT_DMA_CLK1_SW1_CL4_CNTL_DEFAULT 0x20200000 |
3342 | #define smnSYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK_DEFAULT 0x00000080 |
3343 | #define smnSYSHUB_MMREG_DIRECT_NIC400_0_ASIB_0_FN_MOD_DEFAULT 0x00000000 |
3344 | #define smnSYSHUB_MMREG_DIRECT_NIC400_0_AMIB_0_FN_MOD_BM_ISS_DEFAULT 0x00000000 |
3345 | #define smnSYSHUB_MMREG_DIRECT_NIC400_0_AMIB_1_FN_MOD_BM_ISS_DEFAULT 0x00000000 |
3346 | #define smnSYSHUB_MMREG_DIRECT_NIC400_1_ASIB_0_FN_MOD_DEFAULT 0x00000000 |
3347 | #define smnSYSHUB_MMREG_DIRECT_NIC400_1_AMIB_0_FN_MOD_DEFAULT 0x00000000 |
3348 | #define smnSYSHUB_MMREG_DIRECT_NIC400_1_AMIB_1_FN_MOD_DEFAULT 0x00000000 |
3349 | #define smnSYSHUB_MMREG_DIRECT_NIC400_1_AMIB_2_FN_MOD_DEFAULT 0x00000000 |
3350 | #define smnSYSHUB_MMREG_DIRECT_NIC400_2_ASIB_0_FN_MOD_DEFAULT 0x00000000 |
3351 | #define smnSYSHUB_MMREG_DIRECT_NIC400_2_ASIB_1_FN_MOD_DEFAULT 0x00000000 |
3352 | #define smnSYSHUB_MMREG_DIRECT_NIC400_2_ASIB_2_FN_MOD_DEFAULT 0x00000000 |
3353 | #define smnSYSHUB_MMREG_DIRECT_NIC400_2_ASIB_3_FN_MOD_DEFAULT 0x00000000 |
3354 | #define smnSYSHUB_MMREG_DIRECT_NIC400_2_ASIB_4_FN_MOD_DEFAULT 0x00000000 |
3355 | #define smnSYSHUB_MMREG_DIRECT_NIC400_2_AMIB_0_FN_MOD_BM_ISS_DEFAULT 0x00000000 |
3356 | #define smnSYSHUB_MMREG_DIRECT_NIC400_5_ASIB_0_FN_MOD_DEFAULT 0x00000000 |
3357 | #define smnSYSHUB_MMREG_DIRECT_NIC400_5_ASIB_1_FN_MOD_DEFAULT 0x00000000 |
3358 | #define smnSYSHUB_MMREG_DIRECT_NIC400_5_ASIB_2_FN_MOD_DEFAULT 0x00000000 |
3359 | #define smnSYSHUB_MMREG_DIRECT_NIC400_5_ASIB_3_FN_MOD_DEFAULT 0x00000000 |
3360 | #define smnSYSHUB_MMREG_DIRECT_NIC400_5_ASIB_4_FN_MOD_DEFAULT 0x00000000 |
3361 | #define smnSYSHUB_MMREG_DIRECT_NIC400_5_AMIB_0_FN_MOD_DEFAULT 0x00000000 |
3362 | #define smnSYSHUB_MMREG_DIRECT_NIC400_4_ASIB_0_FN_MOD_DEFAULT 0x00000000 |
3363 | #define smnSYSHUB_MMREG_DIRECT_NIC400_4_ASIB_1_FN_MOD_DEFAULT 0x00000000 |
3364 | #define smnSYSHUB_MMREG_DIRECT_NIC400_4_AMIB_0_FN_MOD_DEFAULT 0x00000000 |
3365 | |
3366 | |
3367 | // addressBlock: nbio_nbif0_nbif_sion_SIONDEC |
3368 | #define smnSION_CL0_RdRsp_BurstTarget_REG0_DEFAULT 0x00000000 |
3369 | #define smnSION_CL0_RdRsp_BurstTarget_REG1_DEFAULT 0x00000000 |
3370 | #define smnSION_CL0_RdRsp_TimeSlot_REG0_DEFAULT 0x00000000 |
3371 | #define smnSION_CL0_RdRsp_TimeSlot_REG1_DEFAULT 0x00000000 |
3372 | #define smnSION_CL0_WrRsp_BurstTarget_REG0_DEFAULT 0x00000000 |
3373 | #define smnSION_CL0_WrRsp_BurstTarget_REG1_DEFAULT 0x00000000 |
3374 | #define smnSION_CL0_WrRsp_TimeSlot_REG0_DEFAULT 0x00000000 |
3375 | #define smnSION_CL0_WrRsp_TimeSlot_REG1_DEFAULT 0x00000000 |
3376 | #define smnSION_CL0_Req_BurstTarget_REG0_DEFAULT 0x00000000 |
3377 | #define smnSION_CL0_Req_BurstTarget_REG1_DEFAULT 0x00000000 |
3378 | #define smnSION_CL0_Req_TimeSlot_REG0_DEFAULT 0x00000000 |
3379 | #define smnSION_CL0_Req_TimeSlot_REG1_DEFAULT 0x00000000 |
3380 | #define smnSION_CL0_ReqPoolCredit_Alloc_REG0_DEFAULT 0x00000000 |
3381 | #define smnSION_CL0_ReqPoolCredit_Alloc_REG1_DEFAULT 0x00000000 |
3382 | #define smnSION_CL0_DataPoolCredit_Alloc_REG0_DEFAULT 0x00000000 |
3383 | #define smnSION_CL0_DataPoolCredit_Alloc_REG1_DEFAULT 0x00000000 |
3384 | #define smnSION_CL0_RdRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000 |
3385 | #define smnSION_CL0_RdRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000 |
3386 | #define smnSION_CL0_WrRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000 |
3387 | #define smnSION_CL0_WrRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000 |
3388 | #define smnSION_CL1_RdRsp_BurstTarget_REG0_DEFAULT 0x00000000 |
3389 | #define smnSION_CL1_RdRsp_BurstTarget_REG1_DEFAULT 0x00000000 |
3390 | #define smnSION_CL1_RdRsp_TimeSlot_REG0_DEFAULT 0x00000000 |
3391 | #define smnSION_CL1_RdRsp_TimeSlot_REG1_DEFAULT 0x00000000 |
3392 | #define smnSION_CL1_WrRsp_BurstTarget_REG0_DEFAULT 0x00000000 |
3393 | #define smnSION_CL1_WrRsp_BurstTarget_REG1_DEFAULT 0x00000000 |
3394 | #define smnSION_CL1_WrRsp_TimeSlot_REG0_DEFAULT 0x00000000 |
3395 | #define smnSION_CL1_WrRsp_TimeSlot_REG1_DEFAULT 0x00000000 |
3396 | #define smnSION_CL1_Req_BurstTarget_REG0_DEFAULT 0x00000000 |
3397 | #define smnSION_CL1_Req_BurstTarget_REG1_DEFAULT 0x00000000 |
3398 | #define smnSION_CL1_Req_TimeSlot_REG0_DEFAULT 0x00000000 |
3399 | #define smnSION_CL1_Req_TimeSlot_REG1_DEFAULT 0x00000000 |
3400 | #define smnSION_CL1_ReqPoolCredit_Alloc_REG0_DEFAULT 0x00000000 |
3401 | #define smnSION_CL1_ReqPoolCredit_Alloc_REG1_DEFAULT 0x00000000 |
3402 | #define smnSION_CL1_DataPoolCredit_Alloc_REG0_DEFAULT 0x00000000 |
3403 | #define smnSION_CL1_DataPoolCredit_Alloc_REG1_DEFAULT 0x00000000 |
3404 | #define smnSION_CL1_RdRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000 |
3405 | #define smnSION_CL1_RdRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000 |
3406 | #define smnSION_CL1_WrRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000 |
3407 | #define smnSION_CL1_WrRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000 |
3408 | #define smnSION_CL2_RdRsp_BurstTarget_REG0_DEFAULT 0x00000000 |
3409 | #define smnSION_CL2_RdRsp_BurstTarget_REG1_DEFAULT 0x00000000 |
3410 | #define smnSION_CL2_RdRsp_TimeSlot_REG0_DEFAULT 0x00000000 |
3411 | #define smnSION_CL2_RdRsp_TimeSlot_REG1_DEFAULT 0x00000000 |
3412 | #define smnSION_CL2_WrRsp_BurstTarget_REG0_DEFAULT 0x00000000 |
3413 | #define smnSION_CL2_WrRsp_BurstTarget_REG1_DEFAULT 0x00000000 |
3414 | #define smnSION_CL2_WrRsp_TimeSlot_REG0_DEFAULT 0x00000000 |
3415 | #define smnSION_CL2_WrRsp_TimeSlot_REG1_DEFAULT 0x00000000 |
3416 | #define smnSION_CL2_Req_BurstTarget_REG0_DEFAULT 0x00000000 |
3417 | #define smnSION_CL2_Req_BurstTarget_REG1_DEFAULT 0x00000000 |
3418 | #define smnSION_CL2_Req_TimeSlot_REG0_DEFAULT 0x00000000 |
3419 | #define smnSION_CL2_Req_TimeSlot_REG1_DEFAULT 0x00000000 |
3420 | #define smnSION_CL2_ReqPoolCredit_Alloc_REG0_DEFAULT 0x00000000 |
3421 | #define smnSION_CL2_ReqPoolCredit_Alloc_REG1_DEFAULT 0x00000000 |
3422 | #define smnSION_CL2_DataPoolCredit_Alloc_REG0_DEFAULT 0x00000000 |
3423 | #define smnSION_CL2_DataPoolCredit_Alloc_REG1_DEFAULT 0x00000000 |
3424 | #define smnSION_CL2_RdRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000 |
3425 | #define smnSION_CL2_RdRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000 |
3426 | #define smnSION_CL2_WrRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000 |
3427 | #define smnSION_CL2_WrRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000 |
3428 | #define smnSION_CL3_RdRsp_BurstTarget_REG0_DEFAULT 0x00000000 |
3429 | #define smnSION_CL3_RdRsp_BurstTarget_REG1_DEFAULT 0x00000000 |
3430 | #define smnSION_CL3_RdRsp_TimeSlot_REG0_DEFAULT 0x00000000 |
3431 | #define smnSION_CL3_RdRsp_TimeSlot_REG1_DEFAULT 0x00000000 |
3432 | #define smnSION_CL3_WrRsp_BurstTarget_REG0_DEFAULT 0x00000000 |
3433 | #define smnSION_CL3_WrRsp_BurstTarget_REG1_DEFAULT 0x00000000 |
3434 | #define smnSION_CL3_WrRsp_TimeSlot_REG0_DEFAULT 0x00000000 |
3435 | #define smnSION_CL3_WrRsp_TimeSlot_REG1_DEFAULT 0x00000000 |
3436 | #define smnSION_CL3_Req_BurstTarget_REG0_DEFAULT 0x00000000 |
3437 | #define smnSION_CL3_Req_BurstTarget_REG1_DEFAULT 0x00000000 |
3438 | #define smnSION_CL3_Req_TimeSlot_REG0_DEFAULT 0x00000000 |
3439 | #define smnSION_CL3_Req_TimeSlot_REG1_DEFAULT 0x00000000 |
3440 | #define smnSION_CL3_ReqPoolCredit_Alloc_REG0_DEFAULT 0x00000000 |
3441 | #define smnSION_CL3_ReqPoolCredit_Alloc_REG1_DEFAULT 0x00000000 |
3442 | #define smnSION_CL3_DataPoolCredit_Alloc_REG0_DEFAULT 0x00000000 |
3443 | #define smnSION_CL3_DataPoolCredit_Alloc_REG1_DEFAULT 0x00000000 |
3444 | #define smnSION_CL3_RdRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000 |
3445 | #define smnSION_CL3_RdRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000 |
3446 | #define smnSION_CL3_WrRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000 |
3447 | #define smnSION_CL3_WrRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000 |
3448 | #define smnSION_CNTL_REG0_DEFAULT 0x00000000 |
3449 | #define smnSION_CNTL_REG1_DEFAULT 0x00000000 |
3450 | |
3451 | |
3452 | // addressBlock: nbio_nbif0_gdc_rst_GDCRST_DEC |
3453 | #define smnSHUB_PF_FLR_RST_DEFAULT 0x00000000 |
3454 | #define smnSHUB_GFX_DRV_VPU_RST_DEFAULT 0x00000000 |
3455 | #define smnSHUB_LINK_RESET_DEFAULT 0x00000000 |
3456 | #define smnSHUB_PF0_VF_FLR_RST_DEFAULT 0x00000000 |
3457 | #define smnSHUB_HARD_RST_CTRL_DEFAULT 0x0000001b |
3458 | #define smnSHUB_SOFT_RST_CTRL_DEFAULT 0x00000009 |
3459 | #define smnSHUB_SDP_PORT_RST_DEFAULT 0x00000000 |
3460 | #define smnSHUB_RST_MISC_TRL_DEFAULT 0x00100001 |
3461 | |
3462 | |
3463 | // addressBlock: nbio_nbif0_gdc_ras_gdc_ras_regblk |
3464 | #define smnGDC_RAS_LEAF0_CTRL_DEFAULT 0x00000080 |
3465 | #define smnGDC_RAS_LEAF1_CTRL_DEFAULT 0x00000080 |
3466 | #define smnGDC_RAS_LEAF2_CTRL_DEFAULT 0x00000080 |
3467 | #define smnGDC_RAS_LEAF3_CTRL_DEFAULT 0x00000080 |
3468 | #define smnGDC_RAS_LEAF4_CTRL_DEFAULT 0x00000080 |
3469 | #define smnGDC_RAS_LEAF5_CTRL_DEFAULT 0x00000080 |
3470 | |
3471 | |
3472 | // addressBlock: nbio_iohub_iommu_l2mmio_l2mmiocfg |
3473 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_BASE_0_DEFAULT 0x00000000 |
3474 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_BASE_1_DEFAULT 0x00000000 |
3475 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_CMD_BASE_0_DEFAULT 0x00000000 |
3476 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_CMD_BASE_1_DEFAULT 0x08000000 |
3477 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BASE_0_DEFAULT 0x00000000 |
3478 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BASE_1_DEFAULT 0x08000000 |
3479 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_0_DEFAULT 0x00000400 |
3480 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_CNTRL_1_DEFAULT 0x00002200 |
3481 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_EXCL_BASE_0_DEFAULT 0x00000000 |
3482 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_EXCL_BASE_1_DEFAULT 0x00000000 |
3483 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_EXCL_LIM_0_DEFAULT 0x00000000 |
3484 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_EXCL_LIM_1_DEFAULT 0x00000000 |
3485 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_EFR_0_DEFAULT 0x00000000 |
3486 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_EFR_1_DEFAULT 0x00000000 |
3487 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_PPR_BASE_0_DEFAULT 0x00000000 |
3488 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_PPR_BASE_1_DEFAULT 0x08000000 |
3489 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_UPPER_0_DEFAULT 0x00000000 |
3490 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_UPPER_1_DEFAULT 0x00000000 |
3491 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_LOWER_0_DEFAULT 0x00000000 |
3492 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_LOWER_1_DEFAULT 0x00000000 |
3493 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_STATUS_0_DEFAULT 0x00000000 |
3494 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_HW_ERR_STATUS_1_DEFAULT 0x00000000 |
3495 | #define smnIOMMU_L2MMIO0_SMI_FILTER_REGISTER_0_0_DEFAULT 0x00000000 |
3496 | #define smnIOMMU_L2MMIO0_SMI_FILTER_REGISTER_0_1_DEFAULT 0x00000000 |
3497 | #define smnIOMMU_L2MMIO0_SMI_FILTER_REGISTER_1_0_DEFAULT 0x00000000 |
3498 | #define smnIOMMU_L2MMIO0_SMI_FILTER_REGISTER_1_1_DEFAULT 0x00000000 |
3499 | #define smnIOMMU_L2MMIO0_SMI_FILTER_REGISTER_2_0_DEFAULT 0x00000000 |
3500 | #define smnIOMMU_L2MMIO0_SMI_FILTER_REGISTER_2_1_DEFAULT 0x00000000 |
3501 | #define smnIOMMU_L2MMIO0_SMI_FILTER_REGISTER_3_0_DEFAULT 0x00000000 |
3502 | #define smnIOMMU_L2MMIO0_SMI_FILTER_REGISTER_3_1_DEFAULT 0x00000000 |
3503 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_GA_LOG_BASE_0_DEFAULT 0x00000000 |
3504 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_GA_LOG_BASE_1_DEFAULT 0x08000000 |
3505 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_GA_LOG_TAILPTR_ADDR_0_DEFAULT 0x00000000 |
3506 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_GA_LOG_TAILPTR_ADDR_1_DEFAULT 0x00000000 |
3507 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BASE_0_DEFAULT 0x00000000 |
3508 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BASE_1_DEFAULT 0x08000000 |
3509 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BASE_0_DEFAULT 0x00000000 |
3510 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BASE_1_DEFAULT 0x08000000 |
3511 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_1_BASE_0_DEFAULT 0x00000000 |
3512 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_1_BASE_1_DEFAULT 0x00000000 |
3513 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_2_BASE_0_DEFAULT 0x00000000 |
3514 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_2_BASE_1_DEFAULT 0x00000000 |
3515 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_3_BASE_0_DEFAULT 0x00000000 |
3516 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_3_BASE_1_DEFAULT 0x00000000 |
3517 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_4_BASE_0_DEFAULT 0x00000000 |
3518 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_4_BASE_1_DEFAULT 0x00000000 |
3519 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_5_BASE_0_DEFAULT 0x00000000 |
3520 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_5_BASE_1_DEFAULT 0x00000000 |
3521 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_6_BASE_0_DEFAULT 0x00000000 |
3522 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_6_BASE_1_DEFAULT 0x00000000 |
3523 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_7_BASE_0_DEFAULT 0x00000000 |
3524 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_DEVTBL_7_BASE_1_DEFAULT 0x00000000 |
3525 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_DSFX_DEFAULT 0x00000000 |
3526 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_DSCX_DEFAULT 0x00000000 |
3527 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_DSSX_DEFAULT 0x00000000 |
3528 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_CAP_MISC_DEFAULT 0x00000000 |
3529 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_CAP_MISC_1_DEFAULT 0x00000000 |
3530 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_MSI_CAP_DEFAULT 0x00000000 |
3531 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_MSI_ADDR_LO_DEFAULT 0x00000000 |
3532 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_MSI_ADDR_HI_DEFAULT 0x00000000 |
3533 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_MSI_DATA_DEFAULT 0x00000000 |
3534 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_MSI_MAPPING_CAP_DEFAULT 0x00000000 |
3535 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_CONTROL_W_DEFAULT 0x00000000 |
3536 | #define smnIOMMU_L2MMIO0_IOMMU_MARC_BASE_LO_0_DEFAULT 0x00000000 |
3537 | #define smnIOMMU_L2MMIO0_IOMMU_MARC_BASE_HI_0_DEFAULT 0x00000000 |
3538 | #define smnIOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_0_DEFAULT 0x00000000 |
3539 | #define smnIOMMU_L2MMIO0_IOMMU_MARC_RELOC_HI_0_DEFAULT 0x00000000 |
3540 | #define smnIOMMU_L2MMIO0_IOMMU_MARC_LEN_LO_0_DEFAULT 0x00000000 |
3541 | #define smnIOMMU_L2MMIO0_IOMMU_MARC_LEN_HI_0_DEFAULT 0x00000000 |
3542 | #define smnIOMMU_L2MMIO0_IOMMU_MARC_BASE_LO_1_DEFAULT 0x00000000 |
3543 | #define smnIOMMU_L2MMIO0_IOMMU_MARC_BASE_HI_1_DEFAULT 0x00000000 |
3544 | #define smnIOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_1_DEFAULT 0x00000000 |
3545 | #define smnIOMMU_L2MMIO0_IOMMU_MARC_RELOC_HI_1_DEFAULT 0x00000000 |
3546 | #define smnIOMMU_L2MMIO0_IOMMU_MARC_LEN_LO_1_DEFAULT 0x00000000 |
3547 | #define smnIOMMU_L2MMIO0_IOMMU_MARC_LEN_HI_1_DEFAULT 0x00000000 |
3548 | #define smnIOMMU_L2MMIO0_IOMMU_MARC_BASE_LO_2_DEFAULT 0x00000000 |
3549 | #define smnIOMMU_L2MMIO0_IOMMU_MARC_BASE_HI_2_DEFAULT 0x00000000 |
3550 | #define smnIOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_2_DEFAULT 0x00000000 |
3551 | #define smnIOMMU_L2MMIO0_IOMMU_MARC_RELOC_HI_2_DEFAULT 0x00000000 |
3552 | #define smnIOMMU_L2MMIO0_IOMMU_MARC_LEN_LO_2_DEFAULT 0x00000000 |
3553 | #define smnIOMMU_L2MMIO0_IOMMU_MARC_LEN_HI_2_DEFAULT 0x00000000 |
3554 | #define smnIOMMU_L2MMIO0_IOMMU_MARC_BASE_LO_3_DEFAULT 0x00000000 |
3555 | #define smnIOMMU_L2MMIO0_IOMMU_MARC_BASE_HI_3_DEFAULT 0x00000000 |
3556 | #define smnIOMMU_L2MMIO0_IOMMU_MARC_RELOC_LO_3_DEFAULT 0x00000000 |
3557 | #define smnIOMMU_L2MMIO0_IOMMU_MARC_RELOC_HI_3_DEFAULT 0x00000000 |
3558 | #define smnIOMMU_L2MMIO0_IOMMU_MARC_LEN_LO_3_DEFAULT 0x00000000 |
3559 | #define smnIOMMU_L2MMIO0_IOMMU_MARC_LEN_HI_3_DEFAULT 0x00000000 |
3560 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_CMD_BUF_HDPTR_0_DEFAULT 0x00000000 |
3561 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_CMD_BUF_HDPTR_1_DEFAULT 0x00000000 |
3562 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_CMD_BUF_TAILPTR_0_DEFAULT 0x00000000 |
3563 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_CMD_BUF_TAILPTR_1_DEFAULT 0x00000000 |
3564 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BUF_HDPTR_0_DEFAULT 0x00000000 |
3565 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BUF_HDPTR_1_DEFAULT 0x00000000 |
3566 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BUF_TAILPTR_0_DEFAULT 0x00000000 |
3567 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_EVENT_BUF_TAILPTR_1_DEFAULT 0x00000000 |
3568 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_STATUS_0_DEFAULT 0x00000000 |
3569 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_STATUS_1_DEFAULT 0x00000000 |
3570 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_PPR_BUF_HDPTR_0_DEFAULT 0x00000000 |
3571 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_PPR_BUF_HDPTR_1_DEFAULT 0x00000000 |
3572 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_PPR_BUF_TAILPTR_0_DEFAULT 0x00000000 |
3573 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_PPR_BUF_TAILPTR_1_DEFAULT 0x00000000 |
3574 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_GA_BUF_HDPTR_0_DEFAULT 0x00000000 |
3575 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_GA_BUF_HDPTR_1_DEFAULT 0x00000000 |
3576 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_GA_BUF_TAILPTR_0_DEFAULT 0x00000000 |
3577 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_GA_BUF_TAILPTR_1_DEFAULT 0x00000000 |
3578 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BUF_HDPTR_0_DEFAULT 0x00000000 |
3579 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BUF_HDPTR_1_DEFAULT 0x00000000 |
3580 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BUF_TAILPTR_0_DEFAULT 0x00000000 |
3581 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_BUF_TAILPTR_1_DEFAULT 0x00000000 |
3582 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BUF_HDPTR_0_DEFAULT 0x00000000 |
3583 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BUF_HDPTR_1_DEFAULT 0x00000000 |
3584 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BUF_TAILPTR_0_DEFAULT 0x00000000 |
3585 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_EVENT_B_BUF_TAILPTR_1_DEFAULT 0x00000000 |
3586 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_PPR_AUTORESP_0_DEFAULT 0x00000000 |
3587 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_PPR_OVERFLOW_EARLY_0_DEFAULT 0x00000000 |
3588 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_PPR_B_OVERFLOW_EARLY_0_DEFAULT 0x00000000 |
3589 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_CONFIG_0_DEFAULT 0x00000000 |
3590 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_CONFIG_1_DEFAULT 0x00000000 |
3591 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_0_DEFAULT 0x00000000 |
3592 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_1_DEFAULT 0x00000000 |
3593 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_0_DEFAULT 0x00000000 |
3594 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_1_DEFAULT 0x00000000 |
3595 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_0_DEFAULT 0x00000000 |
3596 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_1_DEFAULT 0x00000000 |
3597 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_0_0_DEFAULT 0x00000000 |
3598 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_0_1_DEFAULT 0x00000000 |
3599 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0_DEFAULT 0x00000000 |
3600 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_1_DEFAULT 0x00000000 |
3601 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0_DEFAULT 0x00000000 |
3602 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_1_DEFAULT 0x00000000 |
3603 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0_DEFAULT 0x00000000 |
3604 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_1_DEFAULT 0x00000000 |
3605 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0_DEFAULT 0x00000000 |
3606 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_1_DEFAULT 0x00000000 |
3607 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_0_DEFAULT 0x00000000 |
3608 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_1_DEFAULT 0x00000000 |
3609 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_1_0_DEFAULT 0x00000000 |
3610 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_1_1_DEFAULT 0x00000000 |
3611 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0_DEFAULT 0x00000000 |
3612 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_1_DEFAULT 0x00000000 |
3613 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0_DEFAULT 0x00000000 |
3614 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_1_DEFAULT 0x00000000 |
3615 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0_DEFAULT 0x00000000 |
3616 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_1_DEFAULT 0x00000000 |
3617 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0_DEFAULT 0x00000000 |
3618 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_1_DEFAULT 0x00000000 |
3619 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_0_DEFAULT 0x00000000 |
3620 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_1_DEFAULT 0x00000000 |
3621 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_2_0_DEFAULT 0x00000000 |
3622 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_2_1_DEFAULT 0x00000000 |
3623 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0_DEFAULT 0x00000000 |
3624 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_1_DEFAULT 0x00000000 |
3625 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0_DEFAULT 0x00000000 |
3626 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_1_DEFAULT 0x00000000 |
3627 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0_DEFAULT 0x00000000 |
3628 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_1_DEFAULT 0x00000000 |
3629 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0_DEFAULT 0x00000000 |
3630 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_1_DEFAULT 0x00000000 |
3631 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_0_DEFAULT 0x00000000 |
3632 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_1_DEFAULT 0x00000000 |
3633 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_3_0_DEFAULT 0x00000000 |
3634 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_0_CNT_3_1_DEFAULT 0x00000000 |
3635 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0_DEFAULT 0x00000000 |
3636 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_1_DEFAULT 0x00000000 |
3637 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0_DEFAULT 0x00000000 |
3638 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_1_DEFAULT 0x00000000 |
3639 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0_DEFAULT 0x00000000 |
3640 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_1_DEFAULT 0x00000000 |
3641 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0_DEFAULT 0x00000000 |
3642 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_1_DEFAULT 0x00000000 |
3643 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_0_DEFAULT 0x00000000 |
3644 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_1_DEFAULT 0x00000000 |
3645 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_0_0_DEFAULT 0x00000000 |
3646 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_0_1_DEFAULT 0x00000000 |
3647 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0_DEFAULT 0x00000000 |
3648 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_1_DEFAULT 0x00000000 |
3649 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0_DEFAULT 0x00000000 |
3650 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_1_DEFAULT 0x00000000 |
3651 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0_DEFAULT 0x00000000 |
3652 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_1_DEFAULT 0x00000000 |
3653 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0_DEFAULT 0x00000000 |
3654 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_1_DEFAULT 0x00000000 |
3655 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_0_DEFAULT 0x00000000 |
3656 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_1_DEFAULT 0x00000000 |
3657 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_1_0_DEFAULT 0x00000000 |
3658 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_1_1_DEFAULT 0x00000000 |
3659 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0_DEFAULT 0x00000000 |
3660 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_1_DEFAULT 0x00000000 |
3661 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0_DEFAULT 0x00000000 |
3662 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_1_DEFAULT 0x00000000 |
3663 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0_DEFAULT 0x00000000 |
3664 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_1_DEFAULT 0x00000000 |
3665 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0_DEFAULT 0x00000000 |
3666 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_1_DEFAULT 0x00000000 |
3667 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_0_DEFAULT 0x00000000 |
3668 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_1_DEFAULT 0x00000000 |
3669 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_2_0_DEFAULT 0x00000000 |
3670 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_2_1_DEFAULT 0x00000000 |
3671 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0_DEFAULT 0x00000000 |
3672 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_1_DEFAULT 0x00000000 |
3673 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0_DEFAULT 0x00000000 |
3674 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_1_DEFAULT 0x00000000 |
3675 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0_DEFAULT 0x00000000 |
3676 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_1_DEFAULT 0x00000000 |
3677 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0_DEFAULT 0x00000000 |
3678 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_1_DEFAULT 0x00000000 |
3679 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_0_DEFAULT 0x00000000 |
3680 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_1_DEFAULT 0x00000000 |
3681 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_3_0_DEFAULT 0x00000000 |
3682 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_BANK_1_CNT_3_1_DEFAULT 0x00000000 |
3683 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0_DEFAULT 0x00000000 |
3684 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_1_DEFAULT 0x00000000 |
3685 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0_DEFAULT 0x00000000 |
3686 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_1_DEFAULT 0x00000000 |
3687 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0_DEFAULT 0x00000000 |
3688 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_1_DEFAULT 0x00000000 |
3689 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0_DEFAULT 0x00000000 |
3690 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_1_DEFAULT 0x00000000 |
3691 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_0_DEFAULT 0x00000000 |
3692 | #define smnIOMMU_L2MMIO0_IOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_1_DEFAULT 0x00000000 |
3693 | |
3694 | |
3695 | // addressBlock: nbio_iohub_nb_ioapicmio_ioapic_miodec |
3696 | #define smnIOAPICMIO_INDEX_DEFAULT 0x00000000 |
3697 | #define smnIOAPICMIO_DATA_DEFAULT 0x00000000 |
3698 | #define smnIRQ_PIN_ASSERTION_REGISTER_DEFAULT 0x00000000 |
3699 | #define smnEOI_REGISTER_DEFAULT 0x00000000 |
3700 | |
3701 | |
3702 | // addressBlock: nbio_iohub_nb_ioapicmioindex_ioapic_mioindexdec |
3703 | #define smnIOAPIC_ID_REGISTER_DEFAULT 0x00000000 |
3704 | #define smnIOAPIC_VERSION_REGISTER_DEFAULT 0x00000000 |
3705 | #define smnIOAPIC_ARBITRATION_REGISTER_DEFAULT 0x00000000 |
3706 | #define smnREDIRECTION_TABLE_ENTRY_LOW_0_DEFAULT 0x00010000 |
3707 | #define smnREDIRECTION_TABLE_ENTRY_HIGH_0_DEFAULT 0x00000000 |
3708 | #define smnREDIRECTION_TABLE_ENTRY_LOW_1_DEFAULT 0x00010000 |
3709 | #define smnREDIRECTION_TABLE_ENTRY_HIGH_1_DEFAULT 0x00000000 |
3710 | #define smnREDIRECTION_TABLE_ENTRY_LOW_2_DEFAULT 0x00010000 |
3711 | #define smnREDIRECTION_TABLE_ENTRY_HIGH_2_DEFAULT 0x00000000 |
3712 | #define smnREDIRECTION_TABLE_ENTRY_LOW_3_DEFAULT 0x00010000 |
3713 | #define smnREDIRECTION_TABLE_ENTRY_HIGH_3_DEFAULT 0x00000000 |
3714 | #define smnREDIRECTION_TABLE_ENTRY_LOW_4_DEFAULT 0x00010000 |
3715 | #define smnREDIRECTION_TABLE_ENTRY_HIGH_4_DEFAULT 0x00000000 |
3716 | #define smnREDIRECTION_TABLE_ENTRY_LOW_5_DEFAULT 0x00010000 |
3717 | #define smnREDIRECTION_TABLE_ENTRY_HIGH_5_DEFAULT 0x00000000 |
3718 | #define smnREDIRECTION_TABLE_ENTRY_LOW_6_DEFAULT 0x00010000 |
3719 | #define smnREDIRECTION_TABLE_ENTRY_HIGH_6_DEFAULT 0x00000000 |
3720 | #define smnREDIRECTION_TABLE_ENTRY_LOW_7_DEFAULT 0x00010000 |
3721 | #define smnREDIRECTION_TABLE_ENTRY_HIGH_7_DEFAULT 0x00000000 |
3722 | #define smnREDIRECTION_TABLE_ENTRY_LOW_8_DEFAULT 0x00010000 |
3723 | #define smnREDIRECTION_TABLE_ENTRY_HIGH_8_DEFAULT 0x00000000 |
3724 | #define smnREDIRECTION_TABLE_ENTRY_LOW_9_DEFAULT 0x00010000 |
3725 | #define smnREDIRECTION_TABLE_ENTRY_HIGH_9_DEFAULT 0x00000000 |
3726 | #define smnREDIRECTION_TABLE_ENTRY_LOW_10_DEFAULT 0x00010000 |
3727 | #define smnREDIRECTION_TABLE_ENTRY_HIGH_10_DEFAULT 0x00000000 |
3728 | #define smnREDIRECTION_TABLE_ENTRY_LOW_11_DEFAULT 0x00010000 |
3729 | #define smnREDIRECTION_TABLE_ENTRY_HIGH_11_DEFAULT 0x00000000 |
3730 | #define smnREDIRECTION_TABLE_ENTRY_LOW_12_DEFAULT 0x00010000 |
3731 | #define smnREDIRECTION_TABLE_ENTRY_HIGH_12_DEFAULT 0x00000000 |
3732 | #define smnREDIRECTION_TABLE_ENTRY_LOW_13_DEFAULT 0x00010000 |
3733 | #define smnREDIRECTION_TABLE_ENTRY_HIGH_13_DEFAULT 0x00000000 |
3734 | #define smnREDIRECTION_TABLE_ENTRY_LOW_14_DEFAULT 0x00010000 |
3735 | #define smnREDIRECTION_TABLE_ENTRY_HIGH_14_DEFAULT 0x00000000 |
3736 | #define smnREDIRECTION_TABLE_ENTRY_LOW_15_DEFAULT 0x00010000 |
3737 | #define smnREDIRECTION_TABLE_ENTRY_HIGH_15_DEFAULT 0x00000000 |
3738 | #define smnREDIRECTION_TABLE_ENTRY_LOW_16_DEFAULT 0x00010000 |
3739 | #define smnREDIRECTION_TABLE_ENTRY_HIGH_16_DEFAULT 0x00000000 |
3740 | #define smnREDIRECTION_TABLE_ENTRY_LOW_17_DEFAULT 0x00010000 |
3741 | #define smnREDIRECTION_TABLE_ENTRY_HIGH_17_DEFAULT 0x00000000 |
3742 | #define smnREDIRECTION_TABLE_ENTRY_LOW_18_DEFAULT 0x00010000 |
3743 | #define smnREDIRECTION_TABLE_ENTRY_HIGH_18_DEFAULT 0x00000000 |
3744 | #define smnREDIRECTION_TABLE_ENTRY_LOW_19_DEFAULT 0x00010000 |
3745 | #define smnREDIRECTION_TABLE_ENTRY_HIGH_19_DEFAULT 0x00000000 |
3746 | #define smnREDIRECTION_TABLE_ENTRY_LOW_20_DEFAULT 0x00010000 |
3747 | #define smnREDIRECTION_TABLE_ENTRY_HIGH_20_DEFAULT 0x00000000 |
3748 | #define smnREDIRECTION_TABLE_ENTRY_LOW_21_DEFAULT 0x00010000 |
3749 | #define smnREDIRECTION_TABLE_ENTRY_HIGH_21_DEFAULT 0x00000000 |
3750 | #define smnREDIRECTION_TABLE_ENTRY_LOW_22_DEFAULT 0x00010000 |
3751 | #define smnREDIRECTION_TABLE_ENTRY_HIGH_22_DEFAULT 0x00000000 |
3752 | #define smnREDIRECTION_TABLE_ENTRY_LOW_23_DEFAULT 0x00010000 |
3753 | #define smnREDIRECTION_TABLE_ENTRY_HIGH_23_DEFAULT 0x00000000 |
3754 | #define smnREDIRECTION_TABLE_ENTRY_LOW_24_DEFAULT 0x00010000 |
3755 | #define smnREDIRECTION_TABLE_ENTRY_HIGH_24_DEFAULT 0x00000000 |
3756 | #define smnREDIRECTION_TABLE_ENTRY_LOW_25_DEFAULT 0x00010000 |
3757 | #define smnREDIRECTION_TABLE_ENTRY_HIGH_25_DEFAULT 0x00000000 |
3758 | #define smnREDIRECTION_TABLE_ENTRY_LOW_26_DEFAULT 0x00010000 |
3759 | #define smnREDIRECTION_TABLE_ENTRY_HIGH_26_DEFAULT 0x00000000 |
3760 | #define smnREDIRECTION_TABLE_ENTRY_LOW_27_DEFAULT 0x00010000 |
3761 | #define smnREDIRECTION_TABLE_ENTRY_HIGH_27_DEFAULT 0x00000000 |
3762 | #define smnREDIRECTION_TABLE_ENTRY_LOW_28_DEFAULT 0x00010000 |
3763 | #define smnREDIRECTION_TABLE_ENTRY_HIGH_28_DEFAULT 0x00000000 |
3764 | #define smnREDIRECTION_TABLE_ENTRY_LOW_29_DEFAULT 0x00010000 |
3765 | #define smnREDIRECTION_TABLE_ENTRY_HIGH_29_DEFAULT 0x00000000 |
3766 | #define smnREDIRECTION_TABLE_ENTRY_LOW_30_DEFAULT 0x00010000 |
3767 | #define smnREDIRECTION_TABLE_ENTRY_HIGH_30_DEFAULT 0x00000000 |
3768 | #define smnREDIRECTION_TABLE_ENTRY_LOW_31_DEFAULT 0x00010000 |
3769 | #define smnREDIRECTION_TABLE_ENTRY_HIGH_31_DEFAULT 0x00000000 |
3770 | |
3771 | |
3772 | // addressBlock: nbio_nbif0_bif_cfg_dev0_rc_bifcfgdecp |
3773 | #define smnBIF_CFG_DEV0_RC1_VENDOR_ID_DEFAULT 0x00000000 |
3774 | #define smnBIF_CFG_DEV0_RC1_DEVICE_ID_DEFAULT 0x00000000 |
3775 | #define smnBIF_CFG_DEV0_RC1_COMMAND_DEFAULT 0x00000000 |
3776 | #define smnBIF_CFG_DEV0_RC1_STATUS_DEFAULT 0x00000000 |
3777 | #define smnBIF_CFG_DEV0_RC1_REVISION_ID_DEFAULT 0x00000000 |
3778 | #define smnBIF_CFG_DEV0_RC1_PROG_INTERFACE_DEFAULT 0x00000000 |
3779 | #define smnBIF_CFG_DEV0_RC1_SUB_CLASS_DEFAULT 0x00000000 |
3780 | #define smnBIF_CFG_DEV0_RC1_BASE_CLASS_DEFAULT 0x00000000 |
3781 | #define smnBIF_CFG_DEV0_RC1_CACHE_LINE_DEFAULT 0x00000000 |
3782 | #define smnBIF_CFG_DEV0_RC1_LATENCY_DEFAULT 0x00000000 |
3783 | #define 0x00000000 |
3784 | #define smnBIF_CFG_DEV0_RC1_BIST_DEFAULT 0x00000000 |
3785 | #define smnBIF_CFG_DEV0_RC1_BASE_ADDR_1_DEFAULT 0x00000000 |
3786 | #define smnBIF_CFG_DEV0_RC1_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 |
3787 | #define smnBIF_CFG_DEV0_RC1_IO_BASE_LIMIT_DEFAULT 0x00000000 |
3788 | #define smnBIF_CFG_DEV0_RC1_SECONDARY_STATUS_DEFAULT 0x00000000 |
3789 | #define smnBIF_CFG_DEV0_RC1_MEM_BASE_LIMIT_DEFAULT 0x00000000 |
3790 | #define smnBIF_CFG_DEV0_RC1_PREF_BASE_LIMIT_DEFAULT 0x00000000 |
3791 | #define smnBIF_CFG_DEV0_RC1_PREF_BASE_UPPER_DEFAULT 0x00000000 |
3792 | #define smnBIF_CFG_DEV0_RC1_PREF_LIMIT_UPPER_DEFAULT 0x00000000 |
3793 | #define smnBIF_CFG_DEV0_RC1_IO_BASE_LIMIT_HI_DEFAULT 0x00000000 |
3794 | #define smnBIF_CFG_DEV0_RC1_CAP_PTR_DEFAULT 0x00000000 |
3795 | #define smnBIF_CFG_DEV0_RC1_INTERRUPT_LINE_DEFAULT 0x000000ff |
3796 | #define smnBIF_CFG_DEV0_RC1_INTERRUPT_PIN_DEFAULT 0x00000001 |
3797 | #define smnBIF_CFG_DEV0_RC1_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000 |
3798 | #define smnBIF_CFG_DEV0_RC1_EXT_BRIDGE_CNTL_DEFAULT 0x00000000 |
3799 | #define smnBIF_CFG_DEV0_RC1_PMI_CAP_LIST_DEFAULT 0x00000000 |
3800 | #define smnBIF_CFG_DEV0_RC1_PMI_CAP_DEFAULT 0x00000000 |
3801 | #define smnBIF_CFG_DEV0_RC1_PMI_STATUS_CNTL_DEFAULT 0x00000000 |
3802 | #define smnBIF_CFG_DEV0_RC1_PCIE_CAP_LIST_DEFAULT 0x0000a000 |
3803 | #define smnBIF_CFG_DEV0_RC1_PCIE_CAP_DEFAULT 0x00000042 |
3804 | #define smnBIF_CFG_DEV0_RC1_DEVICE_CAP_DEFAULT 0x00000000 |
3805 | #define smnBIF_CFG_DEV0_RC1_DEVICE_CNTL_DEFAULT 0x00002810 |
3806 | #define smnBIF_CFG_DEV0_RC1_DEVICE_STATUS_DEFAULT 0x00000000 |
3807 | #define smnBIF_CFG_DEV0_RC1_LINK_CAP_DEFAULT 0x00011c03 |
3808 | #define smnBIF_CFG_DEV0_RC1_LINK_CNTL_DEFAULT 0x00000000 |
3809 | #define smnBIF_CFG_DEV0_RC1_LINK_STATUS_DEFAULT 0x00002001 |
3810 | #define smnBIF_CFG_DEV0_RC1_SLOT_CAP_DEFAULT 0x00000000 |
3811 | #define smnBIF_CFG_DEV0_RC1_SLOT_CNTL_DEFAULT 0x00000000 |
3812 | #define smnBIF_CFG_DEV0_RC1_SLOT_STATUS_DEFAULT 0x00000000 |
3813 | #define smnBIF_CFG_DEV0_RC1_ROOT_CNTL_DEFAULT 0x00000000 |
3814 | #define smnBIF_CFG_DEV0_RC1_ROOT_CAP_DEFAULT 0x00000000 |
3815 | #define smnBIF_CFG_DEV0_RC1_ROOT_STATUS_DEFAULT 0x00000000 |
3816 | #define smnBIF_CFG_DEV0_RC1_DEVICE_CAP2_DEFAULT 0x00000000 |
3817 | #define smnBIF_CFG_DEV0_RC1_DEVICE_CNTL2_DEFAULT 0x00000000 |
3818 | #define smnBIF_CFG_DEV0_RC1_DEVICE_STATUS2_DEFAULT 0x00000000 |
3819 | #define smnBIF_CFG_DEV0_RC1_LINK_CAP2_DEFAULT 0x0000000e |
3820 | #define smnBIF_CFG_DEV0_RC1_LINK_CNTL2_DEFAULT 0x00000003 |
3821 | #define smnBIF_CFG_DEV0_RC1_LINK_STATUS2_DEFAULT 0x00000000 |
3822 | #define smnBIF_CFG_DEV0_RC1_SLOT_CAP2_DEFAULT 0x00000000 |
3823 | #define smnBIF_CFG_DEV0_RC1_SLOT_CNTL2_DEFAULT 0x00000000 |
3824 | #define smnBIF_CFG_DEV0_RC1_SLOT_STATUS2_DEFAULT 0x00000000 |
3825 | #define smnBIF_CFG_DEV0_RC1_MSI_CAP_LIST_DEFAULT 0x0000c000 |
3826 | #define smnBIF_CFG_DEV0_RC1_MSI_MSG_CNTL_DEFAULT 0x00000080 |
3827 | #define smnBIF_CFG_DEV0_RC1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 |
3828 | #define smnBIF_CFG_DEV0_RC1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 |
3829 | #define smnBIF_CFG_DEV0_RC1_MSI_MSG_DATA_DEFAULT 0x00000000 |
3830 | #define smnBIF_CFG_DEV0_RC1_MSI_MSG_DATA_64_DEFAULT 0x00000000 |
3831 | #define smnBIF_CFG_DEV0_RC1_SSID_CAP_LIST_DEFAULT 0x00000000 |
3832 | #define smnBIF_CFG_DEV0_RC1_SSID_CAP_DEFAULT 0x00000000 |
3833 | #define smnBIF_CFG_DEV0_RC1_MSI_MAP_CAP_LIST_DEFAULT 0x00000000 |
3834 | #define smnBIF_CFG_DEV0_RC1_MSI_MAP_CAP_DEFAULT 0x00000000 |
3835 | #define smnBIF_CFG_DEV0_RC1_MSI_MAP_ADDR_LO_DEFAULT 0x00000000 |
3836 | #define smnBIF_CFG_DEV0_RC1_MSI_MAP_ADDR_HI_DEFAULT 0x00000000 |
3837 | #define smnBIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 |
3838 | #define smnBIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 |
3839 | #define smnBIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 |
3840 | #define smnBIF_CFG_DEV0_RC1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 |
3841 | #define smnBIF_CFG_DEV0_RC1_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000 |
3842 | #define smnBIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000 |
3843 | #define smnBIF_CFG_DEV0_RC1_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000 |
3844 | #define smnBIF_CFG_DEV0_RC1_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000 |
3845 | #define smnBIF_CFG_DEV0_RC1_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000 |
3846 | #define smnBIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000 |
3847 | #define smnBIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe |
3848 | #define smnBIF_CFG_DEV0_RC1_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000000 |
3849 | #define smnBIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000 |
3850 | #define smnBIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000 |
3851 | #define smnBIF_CFG_DEV0_RC1_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000000 |
3852 | #define smnBIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000 |
3853 | #define smnBIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000 |
3854 | #define smnBIF_CFG_DEV0_RC1_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000 |
3855 | #define smnBIF_CFG_DEV0_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 |
3856 | #define smnBIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 |
3857 | #define smnBIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 |
3858 | #define smnBIF_CFG_DEV0_RC1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 |
3859 | #define smnBIF_CFG_DEV0_RC1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 |
3860 | #define smnBIF_CFG_DEV0_RC1_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000 |
3861 | #define smnBIF_CFG_DEV0_RC1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 |
3862 | #define smnBIF_CFG_DEV0_RC1_PCIE_HDR_LOG0_DEFAULT 0x00000000 |
3863 | #define smnBIF_CFG_DEV0_RC1_PCIE_HDR_LOG1_DEFAULT 0x00000000 |
3864 | #define smnBIF_CFG_DEV0_RC1_PCIE_HDR_LOG2_DEFAULT 0x00000000 |
3865 | #define smnBIF_CFG_DEV0_RC1_PCIE_HDR_LOG3_DEFAULT 0x00000000 |
3866 | #define smnBIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_CMD_DEFAULT 0x00000000 |
3867 | #define smnBIF_CFG_DEV0_RC1_PCIE_ROOT_ERR_STATUS_DEFAULT 0x00000000 |
3868 | #define smnBIF_CFG_DEV0_RC1_PCIE_ERR_SRC_ID_DEFAULT 0x00000000 |
3869 | #define smnBIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 |
3870 | #define smnBIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 |
3871 | #define smnBIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 |
3872 | #define smnBIF_CFG_DEV0_RC1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 |
3873 | #define smnBIF_CFG_DEV0_RC1_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a000000 |
3874 | #define smnBIF_CFG_DEV0_RC1_PCIE_LINK_CNTL3_DEFAULT 0x00000000 |
3875 | #define smnBIF_CFG_DEV0_RC1_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000 |
3876 | #define smnBIF_CFG_DEV0_RC1_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
3877 | #define smnBIF_CFG_DEV0_RC1_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
3878 | #define smnBIF_CFG_DEV0_RC1_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
3879 | #define smnBIF_CFG_DEV0_RC1_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
3880 | #define smnBIF_CFG_DEV0_RC1_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
3881 | #define smnBIF_CFG_DEV0_RC1_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
3882 | #define smnBIF_CFG_DEV0_RC1_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
3883 | #define smnBIF_CFG_DEV0_RC1_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
3884 | #define smnBIF_CFG_DEV0_RC1_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
3885 | #define smnBIF_CFG_DEV0_RC1_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
3886 | #define smnBIF_CFG_DEV0_RC1_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
3887 | #define smnBIF_CFG_DEV0_RC1_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
3888 | #define smnBIF_CFG_DEV0_RC1_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
3889 | #define smnBIF_CFG_DEV0_RC1_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
3890 | #define smnBIF_CFG_DEV0_RC1_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
3891 | #define smnBIF_CFG_DEV0_RC1_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
3892 | #define smnBIF_CFG_DEV0_RC1_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2f000000 |
3893 | #define smnBIF_CFG_DEV0_RC1_PCIE_ACS_CAP_DEFAULT 0x00000000 |
3894 | #define smnBIF_CFG_DEV0_RC1_PCIE_ACS_CNTL_DEFAULT 0x00000000 |
3895 | |
3896 | |
3897 | // addressBlock: nbio_nbif0_bif_cfg_dev1_rc_bifcfgdecp |
3898 | #define smnBIF_CFG_DEV1_RC1_VENDOR_ID_DEFAULT 0x00000000 |
3899 | #define smnBIF_CFG_DEV1_RC1_DEVICE_ID_DEFAULT 0x00000000 |
3900 | #define smnBIF_CFG_DEV1_RC1_COMMAND_DEFAULT 0x00000000 |
3901 | #define smnBIF_CFG_DEV1_RC1_STATUS_DEFAULT 0x00000000 |
3902 | #define smnBIF_CFG_DEV1_RC1_REVISION_ID_DEFAULT 0x00000000 |
3903 | #define smnBIF_CFG_DEV1_RC1_PROG_INTERFACE_DEFAULT 0x00000000 |
3904 | #define smnBIF_CFG_DEV1_RC1_SUB_CLASS_DEFAULT 0x00000000 |
3905 | #define smnBIF_CFG_DEV1_RC1_BASE_CLASS_DEFAULT 0x00000000 |
3906 | #define smnBIF_CFG_DEV1_RC1_CACHE_LINE_DEFAULT 0x00000000 |
3907 | #define smnBIF_CFG_DEV1_RC1_LATENCY_DEFAULT 0x00000000 |
3908 | #define 0x00000000 |
3909 | #define smnBIF_CFG_DEV1_RC1_BIST_DEFAULT 0x00000000 |
3910 | #define smnBIF_CFG_DEV1_RC1_BASE_ADDR_1_DEFAULT 0x00000000 |
3911 | #define smnBIF_CFG_DEV1_RC1_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 |
3912 | #define smnBIF_CFG_DEV1_RC1_IO_BASE_LIMIT_DEFAULT 0x00000000 |
3913 | #define smnBIF_CFG_DEV1_RC1_SECONDARY_STATUS_DEFAULT 0x00000000 |
3914 | #define smnBIF_CFG_DEV1_RC1_MEM_BASE_LIMIT_DEFAULT 0x00000000 |
3915 | #define smnBIF_CFG_DEV1_RC1_PREF_BASE_LIMIT_DEFAULT 0x00000000 |
3916 | #define smnBIF_CFG_DEV1_RC1_PREF_BASE_UPPER_DEFAULT 0x00000000 |
3917 | #define smnBIF_CFG_DEV1_RC1_PREF_LIMIT_UPPER_DEFAULT 0x00000000 |
3918 | #define smnBIF_CFG_DEV1_RC1_IO_BASE_LIMIT_HI_DEFAULT 0x00000000 |
3919 | #define smnBIF_CFG_DEV1_RC1_CAP_PTR_DEFAULT 0x00000000 |
3920 | #define smnBIF_CFG_DEV1_RC1_INTERRUPT_LINE_DEFAULT 0x000000ff |
3921 | #define smnBIF_CFG_DEV1_RC1_INTERRUPT_PIN_DEFAULT 0x00000001 |
3922 | #define smnBIF_CFG_DEV1_RC1_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000 |
3923 | #define smnBIF_CFG_DEV1_RC1_EXT_BRIDGE_CNTL_DEFAULT 0x00000000 |
3924 | #define smnBIF_CFG_DEV1_RC1_PMI_CAP_LIST_DEFAULT 0x00000000 |
3925 | #define smnBIF_CFG_DEV1_RC1_PMI_CAP_DEFAULT 0x00000000 |
3926 | #define smnBIF_CFG_DEV1_RC1_PMI_STATUS_CNTL_DEFAULT 0x00000000 |
3927 | #define smnBIF_CFG_DEV1_RC1_PCIE_CAP_LIST_DEFAULT 0x0000a000 |
3928 | #define smnBIF_CFG_DEV1_RC1_PCIE_CAP_DEFAULT 0x00000042 |
3929 | #define smnBIF_CFG_DEV1_RC1_DEVICE_CAP_DEFAULT 0x00000000 |
3930 | #define smnBIF_CFG_DEV1_RC1_DEVICE_CNTL_DEFAULT 0x00002810 |
3931 | #define smnBIF_CFG_DEV1_RC1_DEVICE_STATUS_DEFAULT 0x00000000 |
3932 | #define smnBIF_CFG_DEV1_RC1_LINK_CAP_DEFAULT 0x00011c03 |
3933 | #define smnBIF_CFG_DEV1_RC1_LINK_CNTL_DEFAULT 0x00000000 |
3934 | #define smnBIF_CFG_DEV1_RC1_LINK_STATUS_DEFAULT 0x00002001 |
3935 | #define smnBIF_CFG_DEV1_RC1_SLOT_CAP_DEFAULT 0x00000000 |
3936 | #define smnBIF_CFG_DEV1_RC1_SLOT_CNTL_DEFAULT 0x00000000 |
3937 | #define smnBIF_CFG_DEV1_RC1_SLOT_STATUS_DEFAULT 0x00000000 |
3938 | #define smnBIF_CFG_DEV1_RC1_ROOT_CNTL_DEFAULT 0x00000000 |
3939 | #define smnBIF_CFG_DEV1_RC1_ROOT_CAP_DEFAULT 0x00000000 |
3940 | #define smnBIF_CFG_DEV1_RC1_ROOT_STATUS_DEFAULT 0x00000000 |
3941 | #define smnBIF_CFG_DEV1_RC1_DEVICE_CAP2_DEFAULT 0x00000000 |
3942 | #define smnBIF_CFG_DEV1_RC1_DEVICE_CNTL2_DEFAULT 0x00000000 |
3943 | #define smnBIF_CFG_DEV1_RC1_DEVICE_STATUS2_DEFAULT 0x00000000 |
3944 | #define smnBIF_CFG_DEV1_RC1_LINK_CAP2_DEFAULT 0x0000000e |
3945 | #define smnBIF_CFG_DEV1_RC1_LINK_CNTL2_DEFAULT 0x00000003 |
3946 | #define smnBIF_CFG_DEV1_RC1_LINK_STATUS2_DEFAULT 0x00000000 |
3947 | #define smnBIF_CFG_DEV1_RC1_SLOT_CAP2_DEFAULT 0x00000000 |
3948 | #define smnBIF_CFG_DEV1_RC1_SLOT_CNTL2_DEFAULT 0x00000000 |
3949 | #define smnBIF_CFG_DEV1_RC1_SLOT_STATUS2_DEFAULT 0x00000000 |
3950 | #define smnBIF_CFG_DEV1_RC1_MSI_CAP_LIST_DEFAULT 0x0000c000 |
3951 | #define smnBIF_CFG_DEV1_RC1_MSI_MSG_CNTL_DEFAULT 0x00000080 |
3952 | #define smnBIF_CFG_DEV1_RC1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 |
3953 | #define smnBIF_CFG_DEV1_RC1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 |
3954 | #define smnBIF_CFG_DEV1_RC1_MSI_MSG_DATA_DEFAULT 0x00000000 |
3955 | #define smnBIF_CFG_DEV1_RC1_MSI_MSG_DATA_64_DEFAULT 0x00000000 |
3956 | #define smnBIF_CFG_DEV1_RC1_SSID_CAP_LIST_DEFAULT 0x00000000 |
3957 | #define smnBIF_CFG_DEV1_RC1_SSID_CAP_DEFAULT 0x00000000 |
3958 | #define smnBIF_CFG_DEV1_RC1_MSI_MAP_CAP_LIST_DEFAULT 0x00000000 |
3959 | #define smnBIF_CFG_DEV1_RC1_MSI_MAP_CAP_DEFAULT 0x00000000 |
3960 | #define smnBIF_CFG_DEV1_RC1_MSI_MAP_ADDR_LO_DEFAULT 0x00000000 |
3961 | #define smnBIF_CFG_DEV1_RC1_MSI_MAP_ADDR_HI_DEFAULT 0x00000000 |
3962 | #define smnBIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 |
3963 | #define smnBIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 |
3964 | #define smnBIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 |
3965 | #define smnBIF_CFG_DEV1_RC1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 |
3966 | #define smnBIF_CFG_DEV1_RC1_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000 |
3967 | #define smnBIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000 |
3968 | #define smnBIF_CFG_DEV1_RC1_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000 |
3969 | #define smnBIF_CFG_DEV1_RC1_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000 |
3970 | #define smnBIF_CFG_DEV1_RC1_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000 |
3971 | #define smnBIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000 |
3972 | #define smnBIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe |
3973 | #define smnBIF_CFG_DEV1_RC1_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000000 |
3974 | #define smnBIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000 |
3975 | #define smnBIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000 |
3976 | #define smnBIF_CFG_DEV1_RC1_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000000 |
3977 | #define smnBIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000 |
3978 | #define smnBIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000 |
3979 | #define smnBIF_CFG_DEV1_RC1_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000 |
3980 | #define smnBIF_CFG_DEV1_RC1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 |
3981 | #define smnBIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 |
3982 | #define smnBIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 |
3983 | #define smnBIF_CFG_DEV1_RC1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 |
3984 | #define smnBIF_CFG_DEV1_RC1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 |
3985 | #define smnBIF_CFG_DEV1_RC1_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000 |
3986 | #define smnBIF_CFG_DEV1_RC1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 |
3987 | #define smnBIF_CFG_DEV1_RC1_PCIE_HDR_LOG0_DEFAULT 0x00000000 |
3988 | #define smnBIF_CFG_DEV1_RC1_PCIE_HDR_LOG1_DEFAULT 0x00000000 |
3989 | #define smnBIF_CFG_DEV1_RC1_PCIE_HDR_LOG2_DEFAULT 0x00000000 |
3990 | #define smnBIF_CFG_DEV1_RC1_PCIE_HDR_LOG3_DEFAULT 0x00000000 |
3991 | #define smnBIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_CMD_DEFAULT 0x00000000 |
3992 | #define smnBIF_CFG_DEV1_RC1_PCIE_ROOT_ERR_STATUS_DEFAULT 0x00000000 |
3993 | #define smnBIF_CFG_DEV1_RC1_PCIE_ERR_SRC_ID_DEFAULT 0x00000000 |
3994 | #define smnBIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 |
3995 | #define smnBIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 |
3996 | #define smnBIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 |
3997 | #define smnBIF_CFG_DEV1_RC1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 |
3998 | #define smnBIF_CFG_DEV1_RC1_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a000000 |
3999 | #define smnBIF_CFG_DEV1_RC1_PCIE_LINK_CNTL3_DEFAULT 0x00000000 |
4000 | #define smnBIF_CFG_DEV1_RC1_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000 |
4001 | #define smnBIF_CFG_DEV1_RC1_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
4002 | #define smnBIF_CFG_DEV1_RC1_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
4003 | #define smnBIF_CFG_DEV1_RC1_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
4004 | #define smnBIF_CFG_DEV1_RC1_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
4005 | #define smnBIF_CFG_DEV1_RC1_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
4006 | #define smnBIF_CFG_DEV1_RC1_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
4007 | #define smnBIF_CFG_DEV1_RC1_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
4008 | #define smnBIF_CFG_DEV1_RC1_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
4009 | #define smnBIF_CFG_DEV1_RC1_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
4010 | #define smnBIF_CFG_DEV1_RC1_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
4011 | #define smnBIF_CFG_DEV1_RC1_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
4012 | #define smnBIF_CFG_DEV1_RC1_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
4013 | #define smnBIF_CFG_DEV1_RC1_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
4014 | #define smnBIF_CFG_DEV1_RC1_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
4015 | #define smnBIF_CFG_DEV1_RC1_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
4016 | #define smnBIF_CFG_DEV1_RC1_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
4017 | #define smnBIF_CFG_DEV1_RC1_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2f000000 |
4018 | #define smnBIF_CFG_DEV1_RC1_PCIE_ACS_CAP_DEFAULT 0x00000000 |
4019 | #define smnBIF_CFG_DEV1_RC1_PCIE_ACS_CNTL_DEFAULT 0x00000000 |
4020 | |
4021 | |
4022 | // addressBlock: nbio_nbif0_bif_bx_pf_SYSPFVFDEC |
4023 | #define smnBIF_BX_PF0_MM_INDEX_DEFAULT 0x00000000 |
4024 | #define smnBIF_BX_PF0_MM_DATA_DEFAULT 0x00000000 |
4025 | #define smnBIF_BX_PF0_MM_INDEX_HI_DEFAULT 0x00000000 |
4026 | |
4027 | |
4028 | // addressBlock: nbio_nbif0_bif_bx_pf_SYSDEC |
4029 | #define smnBIF_BX_PF0_SYSHUB_INDEX_OVLP_DEFAULT 0x00000000 |
4030 | #define smnBIF_BX_PF0_SYSHUB_DATA_OVLP_DEFAULT 0x00000000 |
4031 | #define smnBIF_BX_PF0_PCIE_INDEX_DEFAULT 0x00000000 |
4032 | #define smnBIF_BX_PF0_PCIE_DATA_DEFAULT 0x00000000 |
4033 | #define smnBIF_BX_PF0_PCIE_INDEX2_DEFAULT 0x00000000 |
4034 | #define smnBIF_BX_PF0_PCIE_DATA2_DEFAULT 0x00000000 |
4035 | #define smnBIF_BX_PF0_SBIOS_SCRATCH_0_DEFAULT 0x00000000 |
4036 | #define smnBIF_BX_PF0_SBIOS_SCRATCH_1_DEFAULT 0x00000000 |
4037 | #define smnBIF_BX_PF0_SBIOS_SCRATCH_2_DEFAULT 0x00000000 |
4038 | #define smnBIF_BX_PF0_SBIOS_SCRATCH_3_DEFAULT 0x00000000 |
4039 | #define smnBIF_BX_PF0_BIOS_SCRATCH_0_DEFAULT 0x00000000 |
4040 | #define smnBIF_BX_PF0_BIOS_SCRATCH_1_DEFAULT 0x00000000 |
4041 | #define smnBIF_BX_PF0_BIOS_SCRATCH_2_DEFAULT 0x00000000 |
4042 | #define smnBIF_BX_PF0_BIOS_SCRATCH_3_DEFAULT 0x00000000 |
4043 | #define smnBIF_BX_PF0_BIOS_SCRATCH_4_DEFAULT 0x00000000 |
4044 | #define smnBIF_BX_PF0_BIOS_SCRATCH_5_DEFAULT 0x00000000 |
4045 | #define smnBIF_BX_PF0_BIOS_SCRATCH_6_DEFAULT 0x00000000 |
4046 | #define smnBIF_BX_PF0_BIOS_SCRATCH_7_DEFAULT 0x00000000 |
4047 | #define smnBIF_BX_PF0_BIOS_SCRATCH_8_DEFAULT 0x00000000 |
4048 | #define smnBIF_BX_PF0_BIOS_SCRATCH_9_DEFAULT 0x00000000 |
4049 | #define smnBIF_BX_PF0_BIOS_SCRATCH_10_DEFAULT 0x00000000 |
4050 | #define smnBIF_BX_PF0_BIOS_SCRATCH_11_DEFAULT 0x00000000 |
4051 | #define smnBIF_BX_PF0_BIOS_SCRATCH_12_DEFAULT 0x00000000 |
4052 | #define smnBIF_BX_PF0_BIOS_SCRATCH_13_DEFAULT 0x00000000 |
4053 | #define smnBIF_BX_PF0_BIOS_SCRATCH_14_DEFAULT 0x00000000 |
4054 | #define smnBIF_BX_PF0_BIOS_SCRATCH_15_DEFAULT 0x00000000 |
4055 | #define smnBIF_BX_PF0_BIF_RLC_INTR_CNTL_DEFAULT 0x00000000 |
4056 | #define smnBIF_BX_PF0_BIF_VCE_INTR_CNTL_DEFAULT 0x00000000 |
4057 | #define smnBIF_BX_PF0_BIF_UVD_INTR_CNTL_DEFAULT 0x00000000 |
4058 | #define smnBIF_BX_PF0_GFX_MMIOREG_CAM_ADDR0_DEFAULT 0x00000000 |
4059 | #define smnBIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR0_DEFAULT 0x00000000 |
4060 | #define smnBIF_BX_PF0_GFX_MMIOREG_CAM_ADDR1_DEFAULT 0x00000000 |
4061 | #define smnBIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR1_DEFAULT 0x00000000 |
4062 | #define smnBIF_BX_PF0_GFX_MMIOREG_CAM_ADDR2_DEFAULT 0x00000000 |
4063 | #define smnBIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR2_DEFAULT 0x00000000 |
4064 | #define smnBIF_BX_PF0_GFX_MMIOREG_CAM_ADDR3_DEFAULT 0x00000000 |
4065 | #define smnBIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR3_DEFAULT 0x00000000 |
4066 | #define smnBIF_BX_PF0_GFX_MMIOREG_CAM_ADDR4_DEFAULT 0x00000000 |
4067 | #define smnBIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR4_DEFAULT 0x00000000 |
4068 | #define smnBIF_BX_PF0_GFX_MMIOREG_CAM_ADDR5_DEFAULT 0x00000000 |
4069 | #define smnBIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR5_DEFAULT 0x00000000 |
4070 | #define smnBIF_BX_PF0_GFX_MMIOREG_CAM_ADDR6_DEFAULT 0x00000000 |
4071 | #define smnBIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR6_DEFAULT 0x00000000 |
4072 | #define smnBIF_BX_PF0_GFX_MMIOREG_CAM_ADDR7_DEFAULT 0x00000000 |
4073 | #define smnBIF_BX_PF0_GFX_MMIOREG_CAM_REMAP_ADDR7_DEFAULT 0x00000000 |
4074 | #define smnBIF_BX_PF0_GFX_MMIOREG_CAM_CNTL_DEFAULT 0x00000000 |
4075 | #define smnBIF_BX_PF0_GFX_MMIOREG_CAM_ZERO_CPL_DEFAULT 0x00000000 |
4076 | #define smnBIF_BX_PF0_GFX_MMIOREG_CAM_ONE_CPL_DEFAULT 0x00000000 |
4077 | #define smnBIF_BX_PF0_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL_DEFAULT 0x00000000 |
4078 | |
4079 | |
4080 | // addressBlock: nbio_nbif0_rcc_strap_BIFDEC1 |
4081 | #define smnRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_DEFAULT 0x300015dd |
4082 | |
4083 | |
4084 | // addressBlock: nbio_nbif0_rcc_ep_dev0_BIFDEC1 |
4085 | #define smnRCC_EP_DEV0_0_EP_PCIE_SCRATCH_DEFAULT 0x00000000 |
4086 | #define smnRCC_EP_DEV0_0_EP_PCIE_CNTL_DEFAULT 0x00000100 |
4087 | #define smnRCC_EP_DEV0_0_EP_PCIE_INT_CNTL_DEFAULT 0x00000000 |
4088 | #define smnRCC_EP_DEV0_0_EP_PCIE_INT_STATUS_DEFAULT 0x00000000 |
4089 | #define smnRCC_EP_DEV0_0_EP_PCIE_RX_CNTL2_DEFAULT 0x00000000 |
4090 | #define smnRCC_EP_DEV0_0_EP_PCIE_BUS_CNTL_DEFAULT 0x00000080 |
4091 | #define smnRCC_EP_DEV0_0_EP_PCIE_CFG_CNTL_DEFAULT 0x00000000 |
4092 | #define smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL_DEFAULT 0x00007468 |
4093 | #define smnRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x000000fa |
4094 | #define smnRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x000000c8 |
4095 | #define smnRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000096 |
4096 | #define smnRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000064 |
4097 | #define smnRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x0000004b |
4098 | #define smnRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000032 |
4099 | #define smnRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000019 |
4100 | #define smnRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x0000000a |
4101 | #define smnRCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP_DEFAULT 0x190a1000 |
4102 | #define smnRCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR_DEFAULT 0x000000f0 |
4103 | #define smnRCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL_DEFAULT 0x00000100 |
4104 | #define smnRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x000000fa |
4105 | #define smnRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x000000c8 |
4106 | #define smnRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000096 |
4107 | #define smnRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000064 |
4108 | #define smnRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x0000004b |
4109 | #define smnRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000032 |
4110 | #define smnRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000019 |
4111 | #define smnRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x0000000a |
4112 | #define smnRCC_EP_DEV0_0_EP_PCIE_PME_CONTROL_DEFAULT 0x00000000 |
4113 | #define smnRCC_EP_DEV0_0_EP_PCIEP_RESERVED_DEFAULT 0x00000000 |
4114 | #define smnRCC_EP_DEV0_0_EP_PCIE_TX_CNTL_DEFAULT 0x00000000 |
4115 | #define smnRCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID_DEFAULT 0x00000000 |
4116 | #define smnRCC_EP_DEV0_0_EP_PCIE_ERR_CNTL_DEFAULT 0x00000500 |
4117 | #define smnRCC_EP_DEV0_0_EP_PCIE_RX_CNTL_DEFAULT 0x01000000 |
4118 | #define smnRCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL_DEFAULT 0x00000000 |
4119 | |
4120 | |
4121 | // addressBlock: nbio_nbif0_rcc_dwn_dev0_BIFDEC1 |
4122 | #define smnRCC_DWN_DEV0_0_DN_PCIE_RESERVED_DEFAULT 0x00000000 |
4123 | #define smnRCC_DWN_DEV0_0_DN_PCIE_SCRATCH_DEFAULT 0x00000000 |
4124 | #define smnRCC_DWN_DEV0_0_DN_PCIE_CNTL_DEFAULT 0x00000000 |
4125 | #define smnRCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL_DEFAULT 0x00000000 |
4126 | #define smnRCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2_DEFAULT 0x00000000 |
4127 | #define smnRCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL_DEFAULT 0x00000080 |
4128 | #define smnRCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL_DEFAULT 0x00000000 |
4129 | |
4130 | |
4131 | // addressBlock: nbio_nbif0_rcc_dwnp_dev0_BIFDEC1 |
4132 | #define smnRCC_DWNP_DEV0_0_PCIE_ERR_CNTL_DEFAULT 0x00000500 |
4133 | #define smnRCC_DWNP_DEV0_0_PCIE_RX_CNTL_DEFAULT 0x00000000 |
4134 | #define smnRCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL_DEFAULT 0x00000000 |
4135 | #define smnRCC_DWNP_DEV0_0_PCIE_LC_CNTL2_DEFAULT 0x00000000 |
4136 | #define smnRCC_DWNP_DEV0_0_PCIEP_STRAP_MISC_DEFAULT 0x00000000 |
4137 | #define smnRCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP_DEFAULT 0x00000000 |
4138 | |
4139 | |
4140 | // addressBlock: nbio_nbif0_bif_bx_pf_BIFDEC1 |
4141 | #define smnBIF_BX_PF0_BIF_MM_INDACCESS_CNTL_DEFAULT 0x00000000 |
4142 | #define smnBIF_BX_PF0_BUS_CNTL_DEFAULT 0x00000000 |
4143 | #define smnBIF_BX_PF0_BIF_SCRATCH0_DEFAULT 0x00000000 |
4144 | #define smnBIF_BX_PF0_BIF_SCRATCH1_DEFAULT 0x00000000 |
4145 | #define smnBIF_BX_PF0_BX_RESET_EN_DEFAULT 0x00010003 |
4146 | #define smnBIF_BX_PF0_MM_CFGREGS_CNTL_DEFAULT 0x00000000 |
4147 | #define smnBIF_BX_PF0_BX_RESET_CNTL_DEFAULT 0x00000000 |
4148 | #define smnBIF_BX_PF0_INTERRUPT_CNTL_DEFAULT 0x00000000 |
4149 | #define smnBIF_BX_PF0_INTERRUPT_CNTL2_DEFAULT 0x00000000 |
4150 | #define smnBIF_BX_PF0_CLKREQB_PAD_CNTL_DEFAULT 0x000008e0 |
4151 | #define smnBIF_BX_PF0_BIF_FEATURES_CONTROL_MISC_DEFAULT 0x00000000 |
4152 | #define smnBIF_BX_PF0_BIF_DOORBELL_CNTL_DEFAULT 0x00000000 |
4153 | #define smnBIF_BX_PF0_BIF_DOORBELL_INT_CNTL_DEFAULT 0x00000000 |
4154 | #define smnBIF_BX_PF0_BIF_FB_EN_DEFAULT 0x00000000 |
4155 | #define smnBIF_BX_PF0_BIF_BUSY_DELAY_CNTR_DEFAULT 0x0000003f |
4156 | #define smnBIF_BX_PF0_BIF_MST_TRANS_PENDING_VF_DEFAULT 0x00000000 |
4157 | #define smnBIF_BX_PF0_BIF_SLV_TRANS_PENDING_VF_DEFAULT 0x00000000 |
4158 | #define smnBIF_BX_PF0_BACO_CNTL_DEFAULT 0x00000000 |
4159 | #define smnBIF_BX_PF0_BIF_BACO_EXIT_TIME0_DEFAULT 0x00000100 |
4160 | #define smnBIF_BX_PF0_BIF_BACO_EXIT_TIMER1_DEFAULT 0x00000200 |
4161 | #define smnBIF_BX_PF0_BIF_BACO_EXIT_TIMER2_DEFAULT 0x00000300 |
4162 | #define smnBIF_BX_PF0_BIF_BACO_EXIT_TIMER3_DEFAULT 0x00000500 |
4163 | #define smnBIF_BX_PF0_BIF_BACO_EXIT_TIMER4_DEFAULT 0x00000400 |
4164 | #define smnBIF_BX_PF0_MEM_TYPE_CNTL_DEFAULT 0x00000000 |
4165 | #define smnBIF_BX_PF0_SMU_BIF_VDDGFX_PWR_STATUS_DEFAULT 0x00000000 |
4166 | #define smnBIF_BX_PF0_BIF_VDDGFX_GFX0_LOWER_DEFAULT 0xc0008000 |
4167 | #define smnBIF_BX_PF0_BIF_VDDGFX_GFX0_UPPER_DEFAULT 0x0000cffc |
4168 | #define smnBIF_BX_PF0_BIF_VDDGFX_GFX1_LOWER_DEFAULT 0xc0028000 |
4169 | #define smnBIF_BX_PF0_BIF_VDDGFX_GFX1_UPPER_DEFAULT 0x00031ffc |
4170 | #define smnBIF_BX_PF0_BIF_VDDGFX_GFX2_LOWER_DEFAULT 0xc0034000 |
4171 | #define smnBIF_BX_PF0_BIF_VDDGFX_GFX2_UPPER_DEFAULT 0x00037ffc |
4172 | #define smnBIF_BX_PF0_BIF_VDDGFX_GFX3_LOWER_DEFAULT 0xc003c000 |
4173 | #define smnBIF_BX_PF0_BIF_VDDGFX_GFX3_UPPER_DEFAULT 0x0003e1fc |
4174 | #define smnBIF_BX_PF0_BIF_VDDGFX_GFX4_LOWER_DEFAULT 0xc003ec00 |
4175 | #define smnBIF_BX_PF0_BIF_VDDGFX_GFX4_UPPER_DEFAULT 0x0003f1fc |
4176 | #define smnBIF_BX_PF0_BIF_VDDGFX_GFX5_LOWER_DEFAULT 0xc003fc00 |
4177 | #define smnBIF_BX_PF0_BIF_VDDGFX_GFX5_UPPER_DEFAULT 0x0003fffc |
4178 | #define smnBIF_BX_PF0_BIF_VDDGFX_RSV1_LOWER_DEFAULT 0x00000000 |
4179 | #define smnBIF_BX_PF0_BIF_VDDGFX_RSV1_UPPER_DEFAULT 0x00000000 |
4180 | #define smnBIF_BX_PF0_BIF_VDDGFX_RSV2_LOWER_DEFAULT 0x00000000 |
4181 | #define smnBIF_BX_PF0_BIF_VDDGFX_RSV2_UPPER_DEFAULT 0x00000000 |
4182 | #define smnBIF_BX_PF0_BIF_VDDGFX_RSV3_LOWER_DEFAULT 0x00000000 |
4183 | #define smnBIF_BX_PF0_BIF_VDDGFX_RSV3_UPPER_DEFAULT 0x00000000 |
4184 | #define smnBIF_BX_PF0_BIF_VDDGFX_RSV4_LOWER_DEFAULT 0x00000000 |
4185 | #define smnBIF_BX_PF0_BIF_VDDGFX_RSV4_UPPER_DEFAULT 0x00000000 |
4186 | #define smnBIF_BX_PF0_BIF_VDDGFX_FB_CMP_DEFAULT 0x00000000 |
4187 | #define smnBIF_BX_PF0_BIF_DOORBELL_GBLAPER1_LOWER_DEFAULT 0x80000780 |
4188 | #define smnBIF_BX_PF0_BIF_DOORBELL_GBLAPER1_UPPER_DEFAULT 0x000007fc |
4189 | #define smnBIF_BX_PF0_BIF_DOORBELL_GBLAPER2_LOWER_DEFAULT 0x80000800 |
4190 | #define smnBIF_BX_PF0_BIF_DOORBELL_GBLAPER2_UPPER_DEFAULT 0x0000087c |
4191 | #define smnBIF_BX_PF0_REMAP_HDP_MEM_FLUSH_CNTL_DEFAULT 0x0000385c |
4192 | #define smnBIF_BX_PF0_REMAP_HDP_REG_FLUSH_CNTL_DEFAULT 0x00003858 |
4193 | #define smnBIF_BX_PF0_BIF_RB_CNTL_DEFAULT 0x00000000 |
4194 | #define smnBIF_BX_PF0_BIF_RB_BASE_DEFAULT 0x00000000 |
4195 | #define smnBIF_BX_PF0_BIF_RB_RPTR_DEFAULT 0x00000000 |
4196 | #define smnBIF_BX_PF0_BIF_RB_WPTR_DEFAULT 0x00000000 |
4197 | #define smnBIF_BX_PF0_BIF_RB_WPTR_ADDR_HI_DEFAULT 0x00000000 |
4198 | #define smnBIF_BX_PF0_BIF_RB_WPTR_ADDR_LO_DEFAULT 0x00000000 |
4199 | #define smnBIF_BX_PF0_MAILBOX_INDEX_DEFAULT 0x00000000 |
4200 | #define smnBIF_BX_PF0_BIF_UVD_GPUIOV_CFG_SIZE_DEFAULT 0x00000008 |
4201 | #define smnBIF_BX_PF0_BIF_VCE_GPUIOV_CFG_SIZE_DEFAULT 0x00000008 |
4202 | #define smnBIF_BX_PF0_BIF_GFX_SDMA_GPUIOV_CFG_SIZE_DEFAULT 0x00000008 |
4203 | #define smnBIF_BX_PF0_BIF_PERSTB_PAD_CNTL_DEFAULT 0x000000c0 |
4204 | #define smnBIF_BX_PF0_BIF_PX_EN_PAD_CNTL_DEFAULT 0x00000031 |
4205 | #define smnBIF_BX_PF0_BIF_REFPADKIN_PAD_CNTL_DEFAULT 0x00000007 |
4206 | #define smnBIF_BX_PF0_BIF_CLKREQB_PAD_CNTL_DEFAULT 0x00600100 |
4207 | |
4208 | |
4209 | // addressBlock: nbio_nbif0_bif_bx_pf_BIFPFVFDEC1 |
4210 | #define smnBIF_BX_PF0_BIF_BME_STATUS_DEFAULT 0x00000000 |
4211 | #define smnBIF_BX_PF0_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000 |
4212 | #define smnBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000 |
4213 | #define smnBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000 |
4214 | #define smnBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100 |
4215 | #define smnBIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 |
4216 | #define smnBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 |
4217 | #define smnBIF_BX_PF0_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000 |
4218 | #define smnBIF_BX_PF0_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000 |
4219 | #define smnBIF_BX_PF0_BIF_TRANS_PENDING_DEFAULT 0x00000000 |
4220 | #define smnBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000 |
4221 | #define smnBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000 |
4222 | #define smnBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000 |
4223 | #define smnBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000 |
4224 | #define smnBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000 |
4225 | #define smnBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000 |
4226 | #define smnBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000 |
4227 | #define smnBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000 |
4228 | #define smnBIF_BX_PF0_MAILBOX_CONTROL_DEFAULT 0x00000000 |
4229 | #define smnBIF_BX_PF0_MAILBOX_INT_CNTL_DEFAULT 0x00000000 |
4230 | #define smnBIF_BX_PF0_BIF_VMHV_MAILBOX_DEFAULT 0x00000000 |
4231 | |
4232 | |
4233 | // addressBlock: nbio_nbif0_rcc_shadow_reg_shadowdec |
4234 | #define smnSHADOW_COMMAND_DEFAULT 0x00000000 |
4235 | #define smnSHADOW_BASE_ADDR_1_DEFAULT 0x00000000 |
4236 | #define smnSHADOW_BASE_ADDR_2_DEFAULT 0x00000000 |
4237 | #define smnSHADOW_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 |
4238 | #define smnSHADOW_IO_BASE_LIMIT_DEFAULT 0x00000000 |
4239 | #define smnSHADOW_MEM_BASE_LIMIT_DEFAULT 0x00000000 |
4240 | #define smnSHADOW_PREF_BASE_LIMIT_DEFAULT 0x00000000 |
4241 | #define smnSHADOW_PREF_BASE_UPPER_DEFAULT 0x00000000 |
4242 | #define smnSHADOW_PREF_LIMIT_UPPER_DEFAULT 0x00000000 |
4243 | #define smnSHADOW_IO_BASE_LIMIT_HI_DEFAULT 0x00000000 |
4244 | #define smnSHADOW_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000 |
4245 | #define smnSUC_INDEX_DEFAULT 0x00000000 |
4246 | #define smnSUC_DATA_DEFAULT 0x00000000 |
4247 | |
4248 | |
4249 | // addressBlock: nbio_nbif0_rcc_ep_dev0_RCCPORTDEC |
4250 | #define smnRCC_EP_DEV0_1_EP_PCIE_SCRATCH_DEFAULT 0x00000000 |
4251 | #define smnRCC_EP_DEV0_1_EP_PCIE_CNTL_DEFAULT 0x00000100 |
4252 | #define smnRCC_EP_DEV0_1_EP_PCIE_INT_CNTL_DEFAULT 0x00000000 |
4253 | #define smnRCC_EP_DEV0_1_EP_PCIE_INT_STATUS_DEFAULT 0x00000000 |
4254 | #define smnRCC_EP_DEV0_1_EP_PCIE_RX_CNTL2_DEFAULT 0x00000000 |
4255 | #define smnRCC_EP_DEV0_1_EP_PCIE_BUS_CNTL_DEFAULT 0x00000080 |
4256 | #define smnRCC_EP_DEV0_1_EP_PCIE_CFG_CNTL_DEFAULT 0x00000000 |
4257 | #define smnRCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL_DEFAULT 0x00007468 |
4258 | #define smnRCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP_DEFAULT 0x190a1000 |
4259 | #define smnRCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR_DEFAULT 0x000000f0 |
4260 | #define smnRCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL_DEFAULT 0x00000100 |
4261 | #define smnRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x000000fa |
4262 | #define smnRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x000000c8 |
4263 | #define smnRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000096 |
4264 | #define smnRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000064 |
4265 | #define smnRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x0000004b |
4266 | #define smnRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000032 |
4267 | #define smnRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000019 |
4268 | #define smnRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x0000000a |
4269 | #define smnRCC_EP_DEV0_1_EP_PCIE_PME_CONTROL_DEFAULT 0x00000000 |
4270 | #define smnRCC_EP_DEV0_1_EP_PCIEP_RESERVED_DEFAULT 0x00000000 |
4271 | #define smnRCC_EP_DEV0_1_EP_PCIE_TX_CNTL_DEFAULT 0x00000000 |
4272 | #define smnRCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID_DEFAULT 0x00000000 |
4273 | #define smnRCC_EP_DEV0_1_EP_PCIE_ERR_CNTL_DEFAULT 0x00000500 |
4274 | #define smnRCC_EP_DEV0_1_EP_PCIE_RX_CNTL_DEFAULT 0x01000000 |
4275 | #define smnRCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL_DEFAULT 0x00000000 |
4276 | |
4277 | |
4278 | // addressBlock: nbio_nbif0_rcc_dwn_dev0_RCCPORTDEC |
4279 | #define smnRCC_DWN_DEV0_1_DN_PCIE_RESERVED_DEFAULT 0x00000000 |
4280 | #define smnRCC_DWN_DEV0_1_DN_PCIE_SCRATCH_DEFAULT 0x00000000 |
4281 | #define smnRCC_DWN_DEV0_1_DN_PCIE_CNTL_DEFAULT 0x00000000 |
4282 | #define smnRCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL_DEFAULT 0x00000000 |
4283 | #define smnRCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2_DEFAULT 0x00000000 |
4284 | #define smnRCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL_DEFAULT 0x00000080 |
4285 | #define smnRCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL_DEFAULT 0x00000000 |
4286 | |
4287 | |
4288 | // addressBlock: nbio_nbif0_rcc_dwnp_dev0_RCCPORTDEC |
4289 | #define smnRCC_DWNP_DEV0_1_PCIE_ERR_CNTL_DEFAULT 0x00000500 |
4290 | #define smnRCC_DWNP_DEV0_1_PCIE_RX_CNTL_DEFAULT 0x00000000 |
4291 | #define smnRCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL_DEFAULT 0x00000000 |
4292 | #define smnRCC_DWNP_DEV0_1_PCIE_LC_CNTL2_DEFAULT 0x00000000 |
4293 | #define smnRCC_DWNP_DEV0_1_PCIEP_STRAP_MISC_DEFAULT 0x00000000 |
4294 | #define smnRCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP_DEFAULT 0x00000000 |
4295 | |
4296 | |
4297 | // addressBlock: nbio_nbif0_rcc_ep_dev1_RCCPORTDEC |
4298 | #define smnRCC_EP_DEV1_EP_PCIE_SCRATCH_DEFAULT 0x00000000 |
4299 | #define smnRCC_EP_DEV1_EP_PCIE_CNTL_DEFAULT 0x00000100 |
4300 | #define smnRCC_EP_DEV1_EP_PCIE_INT_CNTL_DEFAULT 0x00000000 |
4301 | #define smnRCC_EP_DEV1_EP_PCIE_INT_STATUS_DEFAULT 0x00000000 |
4302 | #define smnRCC_EP_DEV1_EP_PCIE_RX_CNTL2_DEFAULT 0x00000000 |
4303 | #define smnRCC_EP_DEV1_EP_PCIE_BUS_CNTL_DEFAULT 0x00000080 |
4304 | #define smnRCC_EP_DEV1_EP_PCIE_CFG_CNTL_DEFAULT 0x00000000 |
4305 | #define smnRCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL_DEFAULT 0x00007468 |
4306 | #define smnRCC_EP_DEV1_EP_PCIE_F0_DPA_CAP_DEFAULT 0x190a1000 |
4307 | #define smnRCC_EP_DEV1_EP_PCIE_F0_DPA_LATENCY_INDICATOR_DEFAULT 0x000000f0 |
4308 | #define smnRCC_EP_DEV1_EP_PCIE_F0_DPA_CNTL_DEFAULT 0x00000100 |
4309 | #define smnRCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x000000fa |
4310 | #define smnRCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x000000c8 |
4311 | #define smnRCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000096 |
4312 | #define smnRCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000064 |
4313 | #define smnRCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x0000004b |
4314 | #define smnRCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000032 |
4315 | #define smnRCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000019 |
4316 | #define smnRCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x0000000a |
4317 | #define smnRCC_EP_DEV1_EP_PCIE_PME_CONTROL_DEFAULT 0x00000000 |
4318 | #define smnRCC_EP_DEV1_EP_PCIEP_RESERVED_DEFAULT 0x00000000 |
4319 | #define smnRCC_EP_DEV1_EP_PCIE_TX_CNTL_DEFAULT 0x00000000 |
4320 | #define smnRCC_EP_DEV1_EP_PCIE_TX_REQUESTER_ID_DEFAULT 0x00000000 |
4321 | #define smnRCC_EP_DEV1_EP_PCIE_ERR_CNTL_DEFAULT 0x00000500 |
4322 | #define smnRCC_EP_DEV1_EP_PCIE_RX_CNTL_DEFAULT 0x01000000 |
4323 | #define smnRCC_EP_DEV1_EP_PCIE_LC_SPEED_CNTL_DEFAULT 0x00000000 |
4324 | |
4325 | |
4326 | // addressBlock: nbio_nbif0_rcc_dwn_dev1_RCCPORTDEC |
4327 | #define smnRCC_DWN_DEV1_DN_PCIE_RESERVED_DEFAULT 0x00000000 |
4328 | #define smnRCC_DWN_DEV1_DN_PCIE_SCRATCH_DEFAULT 0x00000000 |
4329 | #define smnRCC_DWN_DEV1_DN_PCIE_CNTL_DEFAULT 0x00000000 |
4330 | #define smnRCC_DWN_DEV1_DN_PCIE_CONFIG_CNTL_DEFAULT 0x00000000 |
4331 | #define smnRCC_DWN_DEV1_DN_PCIE_RX_CNTL2_DEFAULT 0x00000000 |
4332 | #define smnRCC_DWN_DEV1_DN_PCIE_BUS_CNTL_DEFAULT 0x00000080 |
4333 | #define smnRCC_DWN_DEV1_DN_PCIE_CFG_CNTL_DEFAULT 0x00000000 |
4334 | |
4335 | |
4336 | // addressBlock: nbio_nbif0_rcc_dwnp_dev1_RCCPORTDEC |
4337 | #define smnRCC_DWNP_DEV1_PCIE_ERR_CNTL_DEFAULT 0x00000500 |
4338 | #define smnRCC_DWNP_DEV1_PCIE_RX_CNTL_DEFAULT 0x00000000 |
4339 | #define smnRCC_DWNP_DEV1_PCIE_LC_SPEED_CNTL_DEFAULT 0x00000000 |
4340 | #define smnRCC_DWNP_DEV1_PCIE_LC_CNTL2_DEFAULT 0x00000000 |
4341 | #define smnRCC_DWNP_DEV1_PCIEP_STRAP_MISC_DEFAULT 0x00000000 |
4342 | #define smnRCC_DWNP_DEV1_LTR_MSG_INFO_FROM_EP_DEFAULT 0x00000000 |
4343 | |
4344 | |
4345 | // addressBlock: nbio_nbif0_rcc_strap_rcc_strap_internal |
4346 | #define smnRCC_STRAP1_RCC_DEV0_EPF0_STRAP0_DEFAULT 0x300015dd |
4347 | |
4348 | |
4349 | // addressBlock: nbio_nbif0_bif_bx_pf_SUMDEC |
4350 | #define smnSUM_INDEX_DEFAULT 0x00000000 |
4351 | #define smnSUM_DATA_DEFAULT 0x00000000 |
4352 | |
4353 | |
4354 | // addressBlock: nbio_nbif0_bif_misc_bif_misc_regblk |
4355 | #define smnMISC_SCRATCH_DEFAULT 0x00000000 |
4356 | #define smnINTR_LINE_POLARITY_DEFAULT 0x00000000 |
4357 | #define smnINTR_LINE_ENABLE_DEFAULT 0x00000000 |
4358 | #define smnOUTSTANDING_VC_ALLOC_DEFAULT 0x6f06c0cf |
4359 | #define smnBIFC_MISC_CTRL0_DEFAULT 0x08000004 |
4360 | #define smnBIFC_MISC_CTRL1_DEFAULT 0xa0108c04 |
4361 | #define smnBIFC_BME_ERR_LOG_DEFAULT 0x00000000 |
4362 | #define smnBIFC_RCCBIH_BME_ERR_LOG_DEFAULT 0x00000000 |
4363 | #define smnBIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1_DEFAULT 0x00000000 |
4364 | #define smnBIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3_DEFAULT 0x00000000 |
4365 | #define smnBIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5_DEFAULT 0x00000000 |
4366 | #define smnBIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7_DEFAULT 0x00000000 |
4367 | #define smnBIFC_DMA_ATTR_OVERRIDE_DEV1_F0_F1_DEFAULT 0x00000000 |
4368 | #define smnBIFC_DMA_ATTR_OVERRIDE_DEV1_F2_F3_DEFAULT 0x00000000 |
4369 | #define smnBIFC_DMA_ATTR_OVERRIDE_DEV1_F4_F5_DEFAULT 0x00000000 |
4370 | #define smnBIFC_DMA_ATTR_OVERRIDE_DEV1_F6_F7_DEFAULT 0x00000000 |
4371 | #define smnNBIF_VWIRE_CTRL_DEFAULT 0x00000000 |
4372 | #define smnNBIF_SMN_VWR_VCHG_DIS_CTRL_DEFAULT 0x00000000 |
4373 | #define smnNBIF_SMN_VWR_VCHG_RST_CTRL0_DEFAULT 0x00000000 |
4374 | #define smnNBIF_SMN_VWR_VCHG_TRIG_DEFAULT 0x00000000 |
4375 | #define smnNBIF_SMN_VWR_WTRIG_CNTL_DEFAULT 0x00000000 |
4376 | #define smnNBIF_SMN_VWR_VCHG_DIS_CTRL_1_DEFAULT 0x00000000 |
4377 | #define smnNBIF_MGCG_CTRL_LCLK_DEFAULT 0x00000080 |
4378 | #define smnNBIF_DS_CTRL_LCLK_DEFAULT 0x01000000 |
4379 | #define smnSMN_MST_CNTL0_DEFAULT 0x00000001 |
4380 | #define smnSMN_MST_EP_CNTL1_DEFAULT 0x00000000 |
4381 | #define smnSMN_MST_EP_CNTL2_DEFAULT 0x00000000 |
4382 | #define smnNBIF_SDP_VWR_VCHG_DIS_CTRL_DEFAULT 0x00000000 |
4383 | #define smnNBIF_SDP_VWR_VCHG_RST_CTRL0_DEFAULT 0x00000000 |
4384 | #define smnNBIF_SDP_VWR_VCHG_RST_CTRL1_DEFAULT 0x00000000 |
4385 | #define smnNBIF_SDP_VWR_VCHG_TRIG_DEFAULT 0x00000000 |
4386 | #define smnBME_DUMMY_CNTL_0_DEFAULT 0xaaaaaaaa |
4387 | #define smnBIFC_THT_CNTL_DEFAULT 0x00000222 |
4388 | #define smnBIFC_HSTARB_CNTL_DEFAULT 0x00000000 |
4389 | #define smnBIFC_GSI_CNTL_DEFAULT 0x000017c0 |
4390 | #define smnBIFC_PCIEFUNC_CNTL_DEFAULT 0x00000000 |
4391 | #define smnBIFC_SDP_CNTL_0_DEFAULT 0x3f3f3f3f |
4392 | #define smnBIFC_SDP_CNTL_1_DEFAULT 0x00000000 |
4393 | #define smnBIFC_PERF_CNTL_0_DEFAULT 0x00000000 |
4394 | #define smnBIFC_PERF_CNTL_1_DEFAULT 0x00000000 |
4395 | #define smnBIFC_PERF_CNT_MMIO_RD_DEFAULT 0x00000000 |
4396 | #define smnBIFC_PERF_CNT_MMIO_WR_DEFAULT 0x00000000 |
4397 | #define smnBIFC_PERF_CNT_DMA_RD_DEFAULT 0x00000000 |
4398 | #define smnBIFC_PERF_CNT_DMA_WR_DEFAULT 0x00000000 |
4399 | #define smnNBIF_REGIF_ERRSET_CTRL_DEFAULT 0x00000000 |
4400 | #define smnNBIF_PGMST_CTRL_DEFAULT 0x00000000 |
4401 | #define smnNBIF_PGSLV_CTRL_DEFAULT 0x00000004 |
4402 | #define smnNBIF_PG_MISC_CTRL_DEFAULT 0x14006084 |
4403 | #define smnSMN_MST_EP_CNTL3_DEFAULT 0x00000000 |
4404 | #define smnSMN_MST_EP_CNTL4_DEFAULT 0x00000000 |
4405 | #define smnSMN_MST_CNTL1_DEFAULT 0x00000000 |
4406 | #define smnSMN_MST_EP_CNTL5_DEFAULT 0x00000000 |
4407 | #define smnBIF_SELFRING_BUFFER_VID_DEFAULT 0x0000605f |
4408 | #define smnBIF_SELFRING_VECTOR_CNTL_DEFAULT 0x00000000 |
4409 | #define smnBIF_GMI_WRR_WEIGHT_DEFAULT 0x00040404 |
4410 | #define smnBIF_GMI_CPLBUF_WR_CTRL_DEFAULT 0x00008884 |
4411 | #define smnBIF_GMI_CPLBUF_RD_CTRL_DEFAULT 0x00008008 |
4412 | |
4413 | |
4414 | // addressBlock: nbio_nbif0_rcc_pfc_amdgfx_RCCPFCDEC |
4415 | #define smnRCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL_DEFAULT 0x00000000 |
4416 | #define smnRCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE_DEFAULT 0x00000000 |
4417 | #define smnRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0_DEFAULT 0x00000000 |
4418 | #define smnRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_1_DEFAULT 0x00000000 |
4419 | #define smnRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_2_DEFAULT 0x00000000 |
4420 | #define smnRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_3_DEFAULT 0x00000000 |
4421 | #define smnRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_4_DEFAULT 0x00000000 |
4422 | #define smnRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_5_DEFAULT 0x00000000 |
4423 | #define smnRCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL_DEFAULT 0x00000000 |
4424 | |
4425 | |
4426 | // addressBlock: nbio_nbif0_rcc_pfc_amdgfxaz_RCCPFCDEC |
4427 | #define smnRCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL_DEFAULT 0x00000000 |
4428 | #define smnRCC_PFC_AMDGFXAZ_RCC_PFC_PME_RESTORE_DEFAULT 0x00000000 |
4429 | #define smnRCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0_DEFAULT 0x00000000 |
4430 | #define smnRCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_1_DEFAULT 0x00000000 |
4431 | #define smnRCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_2_DEFAULT 0x00000000 |
4432 | #define smnRCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_3_DEFAULT 0x00000000 |
4433 | #define smnRCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_4_DEFAULT 0x00000000 |
4434 | #define smnRCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_5_DEFAULT 0x00000000 |
4435 | #define smnRCC_PFC_AMDGFXAZ_RCC_PFC_AUXPWR_CNTL_DEFAULT 0x00000000 |
4436 | |
4437 | |
4438 | // addressBlock: nbio_nbif0_rcc_pfc_psp_RCCPFCDEC |
4439 | #define smnRCC_PFC_PSP_RCC_PFC_LTR_CNTL_DEFAULT 0x00000000 |
4440 | #define smnRCC_PFC_PSP_RCC_PFC_PME_RESTORE_DEFAULT 0x00000000 |
4441 | #define smnRCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_0_DEFAULT 0x00000000 |
4442 | #define smnRCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_1_DEFAULT 0x00000000 |
4443 | #define smnRCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_2_DEFAULT 0x00000000 |
4444 | #define smnRCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_3_DEFAULT 0x00000000 |
4445 | #define smnRCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_4_DEFAULT 0x00000000 |
4446 | #define smnRCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_5_DEFAULT 0x00000000 |
4447 | #define smnRCC_PFC_PSP_RCC_PFC_AUXPWR_CNTL_DEFAULT 0x00000000 |
4448 | |
4449 | |
4450 | // addressBlock: nbio_nbif0_rcc_pfc_usb3_0_RCCPFCDEC |
4451 | #define smnRCC_PFC_USB3_0_RCC_PFC_LTR_CNTL_DEFAULT 0x00000000 |
4452 | #define smnRCC_PFC_USB3_0_RCC_PFC_PME_RESTORE_DEFAULT 0x00000000 |
4453 | #define smnRCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_0_DEFAULT 0x00000000 |
4454 | #define smnRCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_1_DEFAULT 0x00000000 |
4455 | #define smnRCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_2_DEFAULT 0x00000000 |
4456 | #define smnRCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_3_DEFAULT 0x00000000 |
4457 | #define smnRCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_4_DEFAULT 0x00000000 |
4458 | #define smnRCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_5_DEFAULT 0x00000000 |
4459 | #define smnRCC_PFC_USB3_0_RCC_PFC_AUXPWR_CNTL_DEFAULT 0x00000000 |
4460 | |
4461 | |
4462 | // addressBlock: nbio_nbif0_rcc_pfc_usb3_1_RCCPFCDEC |
4463 | #define smnRCC_PFC_USB3_1_RCC_PFC_LTR_CNTL_DEFAULT 0x00000000 |
4464 | #define smnRCC_PFC_USB3_1_RCC_PFC_PME_RESTORE_DEFAULT 0x00000000 |
4465 | #define smnRCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_0_DEFAULT 0x00000000 |
4466 | #define smnRCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_1_DEFAULT 0x00000000 |
4467 | #define smnRCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_2_DEFAULT 0x00000000 |
4468 | #define smnRCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_3_DEFAULT 0x00000000 |
4469 | #define smnRCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_4_DEFAULT 0x00000000 |
4470 | #define smnRCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_5_DEFAULT 0x00000000 |
4471 | #define smnRCC_PFC_USB3_1_RCC_PFC_AUXPWR_CNTL_DEFAULT 0x00000000 |
4472 | |
4473 | |
4474 | // addressBlock: nbio_nbif0_rcc_pfc_acp_RCCPFCDEC |
4475 | #define smnRCC_PFC_ACP_RCC_PFC_LTR_CNTL_DEFAULT 0x00000000 |
4476 | #define smnRCC_PFC_ACP_RCC_PFC_PME_RESTORE_DEFAULT 0x00000000 |
4477 | #define smnRCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_0_DEFAULT 0x00000000 |
4478 | #define smnRCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_1_DEFAULT 0x00000000 |
4479 | #define smnRCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_2_DEFAULT 0x00000000 |
4480 | #define smnRCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_3_DEFAULT 0x00000000 |
4481 | #define smnRCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_4_DEFAULT 0x00000000 |
4482 | #define smnRCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_5_DEFAULT 0x00000000 |
4483 | #define smnRCC_PFC_ACP_RCC_PFC_AUXPWR_CNTL_DEFAULT 0x00000000 |
4484 | |
4485 | |
4486 | // addressBlock: nbio_nbif0_rcc_pfc_az_RCCPFCDEC |
4487 | #define smnRCC_PFC_AZ_RCC_PFC_LTR_CNTL_DEFAULT 0x00000000 |
4488 | #define smnRCC_PFC_AZ_RCC_PFC_PME_RESTORE_DEFAULT 0x00000000 |
4489 | #define smnRCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_0_DEFAULT 0x00000000 |
4490 | #define smnRCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_1_DEFAULT 0x00000000 |
4491 | #define smnRCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_2_DEFAULT 0x00000000 |
4492 | #define smnRCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_3_DEFAULT 0x00000000 |
4493 | #define smnRCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_4_DEFAULT 0x00000000 |
4494 | #define smnRCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_5_DEFAULT 0x00000000 |
4495 | #define smnRCC_PFC_AZ_RCC_PFC_AUXPWR_CNTL_DEFAULT 0x00000000 |
4496 | |
4497 | |
4498 | // addressBlock: nbio_nbif0_rcc_pfc_mp2_RCCPFCDEC |
4499 | #define smnRCC_PFC_MP2_RCC_PFC_LTR_CNTL_DEFAULT 0x00000000 |
4500 | #define smnRCC_PFC_MP2_RCC_PFC_PME_RESTORE_DEFAULT 0x00000000 |
4501 | #define smnRCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_0_DEFAULT 0x00000000 |
4502 | #define smnRCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_1_DEFAULT 0x00000000 |
4503 | #define smnRCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_2_DEFAULT 0x00000000 |
4504 | #define smnRCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_3_DEFAULT 0x00000000 |
4505 | #define smnRCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_4_DEFAULT 0x00000000 |
4506 | #define smnRCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_5_DEFAULT 0x00000000 |
4507 | #define smnRCC_PFC_MP2_RCC_PFC_AUXPWR_CNTL_DEFAULT 0x00000000 |
4508 | |
4509 | |
4510 | // addressBlock: nbio_nbif0_rcc_pfc_sata_RCCPFCDEC |
4511 | #define smnRCC_PFC_SATA_RCC_PFC_LTR_CNTL_DEFAULT 0x00000000 |
4512 | #define smnRCC_PFC_SATA_RCC_PFC_PME_RESTORE_DEFAULT 0x00000000 |
4513 | #define smnRCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_0_DEFAULT 0x00000000 |
4514 | #define smnRCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_1_DEFAULT 0x00000000 |
4515 | #define smnRCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_2_DEFAULT 0x00000000 |
4516 | #define smnRCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_3_DEFAULT 0x00000000 |
4517 | #define smnRCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_4_DEFAULT 0x00000000 |
4518 | #define smnRCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_5_DEFAULT 0x00000000 |
4519 | #define smnRCC_PFC_SATA_RCC_PFC_AUXPWR_CNTL_DEFAULT 0x00000000 |
4520 | |
4521 | |
4522 | // addressBlock: nbio_nbif0_rcc_pfc_gbe0_RCCPFCDEC |
4523 | #define smnRCC_PFC_GBE0_RCC_PFC_LTR_CNTL_DEFAULT 0x00000000 |
4524 | #define smnRCC_PFC_GBE0_RCC_PFC_PME_RESTORE_DEFAULT 0x00000000 |
4525 | #define smnRCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_0_DEFAULT 0x00000000 |
4526 | #define smnRCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_1_DEFAULT 0x00000000 |
4527 | #define smnRCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_2_DEFAULT 0x00000000 |
4528 | #define smnRCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_3_DEFAULT 0x00000000 |
4529 | #define smnRCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_4_DEFAULT 0x00000000 |
4530 | #define smnRCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_5_DEFAULT 0x00000000 |
4531 | #define smnRCC_PFC_GBE0_RCC_PFC_AUXPWR_CNTL_DEFAULT 0x00000000 |
4532 | |
4533 | |
4534 | // addressBlock: nbio_nbif0_rcc_pfc_gbe1_RCCPFCDEC |
4535 | #define smnRCC_PFC_GBE1_RCC_PFC_LTR_CNTL_DEFAULT 0x00000000 |
4536 | #define smnRCC_PFC_GBE1_RCC_PFC_PME_RESTORE_DEFAULT 0x00000000 |
4537 | #define smnRCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_0_DEFAULT 0x00000000 |
4538 | #define smnRCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_1_DEFAULT 0x00000000 |
4539 | #define smnRCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_2_DEFAULT 0x00000000 |
4540 | #define smnRCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_3_DEFAULT 0x00000000 |
4541 | #define smnRCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_4_DEFAULT 0x00000000 |
4542 | #define smnRCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_5_DEFAULT 0x00000000 |
4543 | #define smnRCC_PFC_GBE1_RCC_PFC_AUXPWR_CNTL_DEFAULT 0x00000000 |
4544 | |
4545 | |
4546 | // addressBlock: nbio_nbif0_bif_rst_bif_rst_regblk |
4547 | #define smnHARD_RST_CTRL_DEFAULT 0xb0000055 |
4548 | #define smnRSMU_SOFT_RST_CTRL_DEFAULT 0x90000000 |
4549 | #define smnSELF_SOFT_RST_DEFAULT 0x00000000 |
4550 | #define smnBIF_GFX_DRV_VPU_RST_DEFAULT 0x00000000 |
4551 | #define smnBIF_RST_MISC_CTRL_DEFAULT 0x000e0648 |
4552 | #define smnBIF_RST_MISC_CTRL2_DEFAULT 0x00000000 |
4553 | #define smnBIF_RST_MISC_CTRL3_DEFAULT 0x00104900 |
4554 | #define smnDEV0_PF0_FLR_RST_CTRL_DEFAULT 0x8206a0a9 |
4555 | #define smnDEV0_PF1_FLR_RST_CTRL_DEFAULT 0x02060009 |
4556 | #define smnDEV0_PF2_FLR_RST_CTRL_DEFAULT 0x02060009 |
4557 | #define smnDEV0_PF3_FLR_RST_CTRL_DEFAULT 0x02060009 |
4558 | #define smnDEV0_PF4_FLR_RST_CTRL_DEFAULT 0x02060009 |
4559 | #define smnDEV0_PF5_FLR_RST_CTRL_DEFAULT 0x02060009 |
4560 | #define smnDEV0_PF6_FLR_RST_CTRL_DEFAULT 0x02060009 |
4561 | #define smnDEV0_PF7_FLR_RST_CTRL_DEFAULT 0x02060009 |
4562 | #define smnBIF_INST_RESET_INTR_STS_DEFAULT 0x00000000 |
4563 | #define smnBIF_PF_FLR_INTR_STS_DEFAULT 0x00000000 |
4564 | #define smnBIF_D3HOTD0_INTR_STS_DEFAULT 0x00000000 |
4565 | #define smnBIF_POWER_INTR_STS_DEFAULT 0x00000000 |
4566 | #define smnBIF_PF_DSTATE_INTR_STS_DEFAULT 0x00000000 |
4567 | #define smnBIF_INST_RESET_INTR_MASK_DEFAULT 0x00000000 |
4568 | #define smnBIF_PF_FLR_INTR_MASK_DEFAULT 0x00000000 |
4569 | #define smnBIF_D3HOTD0_INTR_MASK_DEFAULT 0x0000ffff |
4570 | #define smnBIF_POWER_INTR_MASK_DEFAULT 0x00000000 |
4571 | #define smnBIF_PF_DSTATE_INTR_MASK_DEFAULT 0x00000000 |
4572 | #define smnBIF_PF_FLR_RST_DEFAULT 0x00000000 |
4573 | #define smnBIF_DEV0_PF0_DSTATE_VALUE_DEFAULT 0x00000000 |
4574 | #define smnBIF_DEV0_PF1_DSTATE_VALUE_DEFAULT 0x00000000 |
4575 | #define smnBIF_DEV0_PF2_DSTATE_VALUE_DEFAULT 0x00000000 |
4576 | #define smnBIF_DEV0_PF3_DSTATE_VALUE_DEFAULT 0x00000000 |
4577 | #define smnBIF_DEV0_PF4_DSTATE_VALUE_DEFAULT 0x00000000 |
4578 | #define smnBIF_DEV0_PF5_DSTATE_VALUE_DEFAULT 0x00000000 |
4579 | #define smnBIF_DEV0_PF6_DSTATE_VALUE_DEFAULT 0x00000000 |
4580 | #define smnBIF_DEV0_PF7_DSTATE_VALUE_DEFAULT 0x00000000 |
4581 | #define smnDEV0_PF0_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b |
4582 | #define smnDEV0_PF1_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b |
4583 | #define smnDEV0_PF2_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b |
4584 | #define smnDEV0_PF3_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b |
4585 | #define smnDEV0_PF4_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b |
4586 | #define smnDEV0_PF5_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b |
4587 | #define smnDEV0_PF6_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b |
4588 | #define smnDEV0_PF7_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b |
4589 | #define smnDEV1_PF0_FLR_RST_CTRL_DEFAULT 0x02060009 |
4590 | #define smnDEV1_PF1_FLR_RST_CTRL_DEFAULT 0x02060009 |
4591 | #define smnDEV1_PF2_FLR_RST_CTRL_DEFAULT 0x02060009 |
4592 | #define smnDEV1_PF3_FLR_RST_CTRL_DEFAULT 0x02060009 |
4593 | #define smnDEV1_PF4_FLR_RST_CTRL_DEFAULT 0x02060009 |
4594 | #define smnDEV1_PF5_FLR_RST_CTRL_DEFAULT 0x02060009 |
4595 | #define smnDEV1_PF6_FLR_RST_CTRL_DEFAULT 0x02060009 |
4596 | #define smnDEV1_PF7_FLR_RST_CTRL_DEFAULT 0x02060009 |
4597 | #define smnBIF_DEV1_PF0_DSTATE_VALUE_DEFAULT 0x00000000 |
4598 | #define smnBIF_DEV1_PF1_DSTATE_VALUE_DEFAULT 0x00000000 |
4599 | #define smnBIF_DEV1_PF2_DSTATE_VALUE_DEFAULT 0x00000000 |
4600 | #define smnBIF_DEV1_PF3_DSTATE_VALUE_DEFAULT 0x00000000 |
4601 | #define smnBIF_DEV1_PF4_DSTATE_VALUE_DEFAULT 0x00000000 |
4602 | #define smnBIF_DEV1_PF5_DSTATE_VALUE_DEFAULT 0x00000000 |
4603 | #define smnBIF_DEV1_PF6_DSTATE_VALUE_DEFAULT 0x00000000 |
4604 | #define smnBIF_DEV1_PF7_DSTATE_VALUE_DEFAULT 0x00000000 |
4605 | #define smnDEV1_PF0_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b |
4606 | #define smnDEV1_PF1_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b |
4607 | #define smnDEV1_PF2_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b |
4608 | #define smnDEV1_PF3_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b |
4609 | #define smnDEV1_PF4_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b |
4610 | #define smnDEV1_PF5_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b |
4611 | #define smnDEV1_PF6_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b |
4612 | #define smnDEV1_PF7_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b |
4613 | #define smnBIF_PORT0_DSTATE_VALUE_DEFAULT 0x00000000 |
4614 | #define smnBIF_PORT1_DSTATE_VALUE_DEFAULT 0x00000000 |
4615 | |
4616 | |
4617 | // addressBlock: nbio_nbif0_bif_ras_bif_ras_regblk |
4618 | #define smnBIF_RAS_LEAF0_CTRL_DEFAULT 0x00000080 |
4619 | #define smnBIF_RAS_LEAF1_CTRL_DEFAULT 0x00000080 |
4620 | #define smnBIF_RAS_LEAF2_CTRL_DEFAULT 0x00000080 |
4621 | #define smnBIF_RAS_MISC_CTRL_DEFAULT 0x00000000 |
4622 | #define smnBIF_IOHUB_RAS_IH_CNTL_DEFAULT 0x00000000 |
4623 | #define smnBIF_RAS_VWR_FROM_IOHUB_DEFAULT 0x00000000 |
4624 | |
4625 | |
4626 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_bifcfgdecp |
4627 | #define smnBIF_CFG_DEV0_EPF0_2_VENDOR_ID_DEFAULT 0x00000000 |
4628 | #define smnBIF_CFG_DEV0_EPF0_2_DEVICE_ID_DEFAULT 0x00000000 |
4629 | #define smnBIF_CFG_DEV0_EPF0_2_COMMAND_DEFAULT 0x00000000 |
4630 | #define smnBIF_CFG_DEV0_EPF0_2_STATUS_DEFAULT 0x00000000 |
4631 | #define smnBIF_CFG_DEV0_EPF0_2_REVISION_ID_DEFAULT 0x00000000 |
4632 | #define smnBIF_CFG_DEV0_EPF0_2_PROG_INTERFACE_DEFAULT 0x00000000 |
4633 | #define smnBIF_CFG_DEV0_EPF0_2_SUB_CLASS_DEFAULT 0x00000000 |
4634 | #define smnBIF_CFG_DEV0_EPF0_2_BASE_CLASS_DEFAULT 0x00000000 |
4635 | #define smnBIF_CFG_DEV0_EPF0_2_CACHE_LINE_DEFAULT 0x00000000 |
4636 | #define smnBIF_CFG_DEV0_EPF0_2_LATENCY_DEFAULT 0x00000000 |
4637 | #define 0x00000000 |
4638 | #define smnBIF_CFG_DEV0_EPF0_2_BIST_DEFAULT 0x00000000 |
4639 | #define smnBIF_CFG_DEV0_EPF0_2_BASE_ADDR_1_DEFAULT 0x00000000 |
4640 | #define smnBIF_CFG_DEV0_EPF0_2_BASE_ADDR_2_DEFAULT 0x00000000 |
4641 | #define smnBIF_CFG_DEV0_EPF0_2_BASE_ADDR_3_DEFAULT 0x00000000 |
4642 | #define smnBIF_CFG_DEV0_EPF0_2_BASE_ADDR_4_DEFAULT 0x00000000 |
4643 | #define smnBIF_CFG_DEV0_EPF0_2_BASE_ADDR_5_DEFAULT 0x00000000 |
4644 | #define smnBIF_CFG_DEV0_EPF0_2_BASE_ADDR_6_DEFAULT 0x00000000 |
4645 | #define smnBIF_CFG_DEV0_EPF0_2_ADAPTER_ID_DEFAULT 0x00000000 |
4646 | #define smnBIF_CFG_DEV0_EPF0_2_ROM_BASE_ADDR_DEFAULT 0x00000000 |
4647 | #define smnBIF_CFG_DEV0_EPF0_2_CAP_PTR_DEFAULT 0x00000000 |
4648 | #define smnBIF_CFG_DEV0_EPF0_2_INTERRUPT_LINE_DEFAULT 0x000000ff |
4649 | #define smnBIF_CFG_DEV0_EPF0_2_INTERRUPT_PIN_DEFAULT 0x00000000 |
4650 | #define smnBIF_CFG_DEV0_EPF0_2_MIN_GRANT_DEFAULT 0x00000000 |
4651 | #define smnBIF_CFG_DEV0_EPF0_2_MAX_LATENCY_DEFAULT 0x00000000 |
4652 | #define smnBIF_CFG_DEV0_EPF0_2_VENDOR_CAP_LIST_DEFAULT 0x00000000 |
4653 | #define smnBIF_CFG_DEV0_EPF0_2_ADAPTER_ID_W_DEFAULT 0x00000000 |
4654 | #define smnBIF_CFG_DEV0_EPF0_2_PMI_CAP_LIST_DEFAULT 0x00000000 |
4655 | #define smnBIF_CFG_DEV0_EPF0_2_PMI_CAP_DEFAULT 0x00000000 |
4656 | #define smnBIF_CFG_DEV0_EPF0_2_PMI_STATUS_CNTL_DEFAULT 0x00000000 |
4657 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_CAP_LIST_DEFAULT 0x0000a000 |
4658 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_CAP_DEFAULT 0x00000002 |
4659 | #define smnBIF_CFG_DEV0_EPF0_2_DEVICE_CAP_DEFAULT 0x10000000 |
4660 | #define smnBIF_CFG_DEV0_EPF0_2_DEVICE_CNTL_DEFAULT 0x00002810 |
4661 | #define smnBIF_CFG_DEV0_EPF0_2_DEVICE_STATUS_DEFAULT 0x00000000 |
4662 | #define smnBIF_CFG_DEV0_EPF0_2_LINK_CAP_DEFAULT 0x00011c03 |
4663 | #define smnBIF_CFG_DEV0_EPF0_2_LINK_CNTL_DEFAULT 0x00000000 |
4664 | #define smnBIF_CFG_DEV0_EPF0_2_LINK_STATUS_DEFAULT 0x00000001 |
4665 | #define smnBIF_CFG_DEV0_EPF0_2_DEVICE_CAP2_DEFAULT 0x00000000 |
4666 | #define smnBIF_CFG_DEV0_EPF0_2_DEVICE_CNTL2_DEFAULT 0x00000000 |
4667 | #define smnBIF_CFG_DEV0_EPF0_2_DEVICE_STATUS2_DEFAULT 0x00000000 |
4668 | #define smnBIF_CFG_DEV0_EPF0_2_LINK_CAP2_DEFAULT 0x0000000e |
4669 | #define smnBIF_CFG_DEV0_EPF0_2_LINK_CNTL2_DEFAULT 0x00000003 |
4670 | #define smnBIF_CFG_DEV0_EPF0_2_LINK_STATUS2_DEFAULT 0x00000000 |
4671 | #define smnBIF_CFG_DEV0_EPF0_2_SLOT_CAP2_DEFAULT 0x00000000 |
4672 | #define smnBIF_CFG_DEV0_EPF0_2_SLOT_CNTL2_DEFAULT 0x00000000 |
4673 | #define smnBIF_CFG_DEV0_EPF0_2_SLOT_STATUS2_DEFAULT 0x00000000 |
4674 | #define smnBIF_CFG_DEV0_EPF0_2_MSI_CAP_LIST_DEFAULT 0x0000c000 |
4675 | #define smnBIF_CFG_DEV0_EPF0_2_MSI_MSG_CNTL_DEFAULT 0x00000080 |
4676 | #define smnBIF_CFG_DEV0_EPF0_2_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 |
4677 | #define smnBIF_CFG_DEV0_EPF0_2_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 |
4678 | #define smnBIF_CFG_DEV0_EPF0_2_MSI_MSG_DATA_DEFAULT 0x00000000 |
4679 | #define smnBIF_CFG_DEV0_EPF0_2_MSI_MASK_DEFAULT 0x00000000 |
4680 | #define smnBIF_CFG_DEV0_EPF0_2_MSI_MSG_DATA_64_DEFAULT 0x00000000 |
4681 | #define smnBIF_CFG_DEV0_EPF0_2_MSI_MASK_64_DEFAULT 0x00000000 |
4682 | #define smnBIF_CFG_DEV0_EPF0_2_MSI_PENDING_DEFAULT 0x00000000 |
4683 | #define smnBIF_CFG_DEV0_EPF0_2_MSI_PENDING_64_DEFAULT 0x00000000 |
4684 | #define smnBIF_CFG_DEV0_EPF0_2_MSIX_CAP_LIST_DEFAULT 0x00000000 |
4685 | #define smnBIF_CFG_DEV0_EPF0_2_MSIX_MSG_CNTL_DEFAULT 0x00000000 |
4686 | #define smnBIF_CFG_DEV0_EPF0_2_MSIX_TABLE_DEFAULT 0x00000000 |
4687 | #define smnBIF_CFG_DEV0_EPF0_2_MSIX_PBA_DEFAULT 0x00000000 |
4688 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 |
4689 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 |
4690 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 |
4691 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 |
4692 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000 |
4693 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000 |
4694 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000 |
4695 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000 |
4696 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000 |
4697 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000 |
4698 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe |
4699 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000000 |
4700 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000 |
4701 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000 |
4702 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000000 |
4703 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000 |
4704 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000 |
4705 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000 |
4706 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 |
4707 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 |
4708 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 |
4709 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 |
4710 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 |
4711 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000 |
4712 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 |
4713 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_HDR_LOG0_DEFAULT 0x00000000 |
4714 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_HDR_LOG1_DEFAULT 0x00000000 |
4715 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_HDR_LOG2_DEFAULT 0x00000000 |
4716 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_HDR_LOG3_DEFAULT 0x00000000 |
4717 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 |
4718 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 |
4719 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 |
4720 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 |
4721 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000 |
4722 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_BAR1_CAP_DEFAULT 0x00000000 |
4723 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_BAR1_CNTL_DEFAULT 0x00000020 |
4724 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_BAR2_CAP_DEFAULT 0x00000000 |
4725 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_BAR2_CNTL_DEFAULT 0x00000000 |
4726 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_BAR3_CAP_DEFAULT 0x00000000 |
4727 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_BAR3_CNTL_DEFAULT 0x00000000 |
4728 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_BAR4_CAP_DEFAULT 0x00000000 |
4729 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_BAR4_CNTL_DEFAULT 0x00000000 |
4730 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_BAR5_CAP_DEFAULT 0x00000000 |
4731 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_BAR5_CNTL_DEFAULT 0x00000000 |
4732 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_BAR6_CAP_DEFAULT 0x00000000 |
4733 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_BAR6_CNTL_DEFAULT 0x00000000 |
4734 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000 |
4735 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000 |
4736 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000 |
4737 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000 |
4738 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000 |
4739 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_DPA_CAP_DEFAULT 0x00000000 |
4740 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000 |
4741 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_DPA_STATUS_DEFAULT 0x00000100 |
4742 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_DPA_CNTL_DEFAULT 0x00000000 |
4743 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000 |
4744 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000 |
4745 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000 |
4746 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000 |
4747 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000 |
4748 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000 |
4749 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000 |
4750 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000 |
4751 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a010019 |
4752 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_LINK_CNTL3_DEFAULT 0x00000000 |
4753 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000 |
4754 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
4755 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
4756 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
4757 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
4758 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
4759 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
4760 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
4761 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
4762 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
4763 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
4764 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
4765 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
4766 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
4767 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
4768 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
4769 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
4770 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000 |
4771 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_ACS_CAP_DEFAULT 0x00000000 |
4772 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_ACS_CNTL_DEFAULT 0x00000000 |
4773 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 |
4774 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_ATS_CAP_DEFAULT 0x00000000 |
4775 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_ATS_CNTL_DEFAULT 0x00000000 |
4776 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_PAGE_REQ_ENH_CAP_LIST_DEFAULT 0x2d000000 |
4777 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_PAGE_REQ_CNTL_DEFAULT 0x00000000 |
4778 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_PAGE_REQ_STATUS_DEFAULT 0x00000000 |
4779 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_OUTSTAND_PAGE_REQ_CAPACITY_DEFAULT 0x00000000 |
4780 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_OUTSTAND_PAGE_REQ_ALLOC_DEFAULT 0x00000000 |
4781 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_PASID_ENH_CAP_LIST_DEFAULT 0x2e000000 |
4782 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_PASID_CAP_DEFAULT 0x00000000 |
4783 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_PASID_CNTL_DEFAULT 0x00000000 |
4784 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_ENH_CAP_LIST_DEFAULT 0x2f000000 |
4785 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_CAP_DEFAULT 0x00000000 |
4786 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_TPH_REQR_CNTL_DEFAULT 0x00000000 |
4787 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_MC_ENH_CAP_LIST_DEFAULT 0x32000000 |
4788 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_MC_CAP_DEFAULT 0x00000000 |
4789 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_MC_CNTL_DEFAULT 0x00000000 |
4790 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_MC_ADDR0_DEFAULT 0x00000000 |
4791 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_MC_ADDR1_DEFAULT 0x00000000 |
4792 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_MC_RCV0_DEFAULT 0x00000000 |
4793 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_MC_RCV1_DEFAULT 0x00000000 |
4794 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_MC_BLOCK_ALL0_DEFAULT 0x00000000 |
4795 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_MC_BLOCK_ALL1_DEFAULT 0x00000000 |
4796 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_MC_BLOCK_UNTRANSLATED_0_DEFAULT 0x00000000 |
4797 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_MC_BLOCK_UNTRANSLATED_1_DEFAULT 0x00000000 |
4798 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_LTR_ENH_CAP_LIST_DEFAULT 0x32800000 |
4799 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_LTR_CAP_DEFAULT 0x00000000 |
4800 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000 |
4801 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_ARI_CAP_DEFAULT 0x00000000 |
4802 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_ARI_CNTL_DEFAULT 0x00000000 |
4803 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_ENH_CAP_LIST_DEFAULT 0x00000000 |
4804 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_CAP_DEFAULT 0x00000000 |
4805 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_CONTROL_DEFAULT 0x00000000 |
4806 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_STATUS_DEFAULT 0x00000000 |
4807 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_INITIAL_VFS_DEFAULT 0x00000000 |
4808 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_TOTAL_VFS_DEFAULT 0x00000000 |
4809 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_NUM_VFS_DEFAULT 0x00000000 |
4810 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_FUNC_DEP_LINK_DEFAULT 0x00000000 |
4811 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_FIRST_VF_OFFSET_DEFAULT 0x00000000 |
4812 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_STRIDE_DEFAULT 0x00000000 |
4813 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_DEVICE_ID_DEFAULT 0x00000000 |
4814 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_SUPPORTED_PAGE_SIZE_DEFAULT 0x00000000 |
4815 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_SYSTEM_PAGE_SIZE_DEFAULT 0x00000001 |
4816 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_BASE_ADDR_0_DEFAULT 0x00000000 |
4817 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_BASE_ADDR_1_DEFAULT 0x00000000 |
4818 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_BASE_ADDR_2_DEFAULT 0x00000000 |
4819 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_BASE_ADDR_3_DEFAULT 0x00000000 |
4820 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_BASE_ADDR_4_DEFAULT 0x00000000 |
4821 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_BASE_ADDR_5_DEFAULT 0x00000000 |
4822 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_DEFAULT 0x00000000 |
4823 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_DEFAULT 0x00000000 |
4824 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_DEFAULT 0x00000000 |
4825 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW_DEFAULT 0x00000000 |
4826 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_DEFAULT 0x00000000 |
4827 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_DEFAULT 0x00000000 |
4828 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_DEFAULT 0x00000000 |
4829 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0_DEFAULT 0x00000000 |
4830 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_DEFAULT 0x00000000 |
4831 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2_DEFAULT 0x00000000 |
4832 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT_DEFAULT 0x00000000 |
4833 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB_DEFAULT 0x00000000 |
4834 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS_DEFAULT 0x00000000 |
4835 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB_DEFAULT 0x00000000 |
4836 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB_DEFAULT 0x00000000 |
4837 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB_DEFAULT 0x00000000 |
4838 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB_DEFAULT 0x00000000 |
4839 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB_DEFAULT 0x00000000 |
4840 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB_DEFAULT 0x00000000 |
4841 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB_DEFAULT 0x00000000 |
4842 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB_DEFAULT 0x00000000 |
4843 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB_DEFAULT 0x00000000 |
4844 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB_DEFAULT 0x00000000 |
4845 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB_DEFAULT 0x00000000 |
4846 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB_DEFAULT 0x00000000 |
4847 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB_DEFAULT 0x00000000 |
4848 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB_DEFAULT 0x00000000 |
4849 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB_DEFAULT 0x00000000 |
4850 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB_DEFAULT 0x00000000 |
4851 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0_DEFAULT 0x00000000 |
4852 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1_DEFAULT 0x00000000 |
4853 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2_DEFAULT 0x00000000 |
4854 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3_DEFAULT 0x00000000 |
4855 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4_DEFAULT 0x00000000 |
4856 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5_DEFAULT 0x00000000 |
4857 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6_DEFAULT 0x00000000 |
4858 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7_DEFAULT 0x00000000 |
4859 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8_DEFAULT 0x00000000 |
4860 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0_DEFAULT 0x00000000 |
4861 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1_DEFAULT 0x00000000 |
4862 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2_DEFAULT 0x00000000 |
4863 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3_DEFAULT 0x00000000 |
4864 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4_DEFAULT 0x00000000 |
4865 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5_DEFAULT 0x00000000 |
4866 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6_DEFAULT 0x00000000 |
4867 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7_DEFAULT 0x00000000 |
4868 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8_DEFAULT 0x00000000 |
4869 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0_DEFAULT 0x00000000 |
4870 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1_DEFAULT 0x00000000 |
4871 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2_DEFAULT 0x00000000 |
4872 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3_DEFAULT 0x00000000 |
4873 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4_DEFAULT 0x00000000 |
4874 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5_DEFAULT 0x00000000 |
4875 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6_DEFAULT 0x00000000 |
4876 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7_DEFAULT 0x00000000 |
4877 | #define smnBIF_CFG_DEV0_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8_DEFAULT 0x00000000 |
4878 | |
4879 | |
4880 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf1_bifcfgdecp |
4881 | #define smnBIF_CFG_DEV0_EPF1_1_VENDOR_ID_DEFAULT 0x00000000 |
4882 | #define smnBIF_CFG_DEV0_EPF1_1_DEVICE_ID_DEFAULT 0x00000000 |
4883 | #define smnBIF_CFG_DEV0_EPF1_1_COMMAND_DEFAULT 0x00000000 |
4884 | #define smnBIF_CFG_DEV0_EPF1_1_STATUS_DEFAULT 0x00000000 |
4885 | #define smnBIF_CFG_DEV0_EPF1_1_REVISION_ID_DEFAULT 0x00000000 |
4886 | #define smnBIF_CFG_DEV0_EPF1_1_PROG_INTERFACE_DEFAULT 0x00000000 |
4887 | #define smnBIF_CFG_DEV0_EPF1_1_SUB_CLASS_DEFAULT 0x00000000 |
4888 | #define smnBIF_CFG_DEV0_EPF1_1_BASE_CLASS_DEFAULT 0x00000000 |
4889 | #define smnBIF_CFG_DEV0_EPF1_1_CACHE_LINE_DEFAULT 0x00000000 |
4890 | #define smnBIF_CFG_DEV0_EPF1_1_LATENCY_DEFAULT 0x00000000 |
4891 | #define 0x00000000 |
4892 | #define smnBIF_CFG_DEV0_EPF1_1_BIST_DEFAULT 0x00000000 |
4893 | #define smnBIF_CFG_DEV0_EPF1_1_BASE_ADDR_1_DEFAULT 0x00000000 |
4894 | #define smnBIF_CFG_DEV0_EPF1_1_BASE_ADDR_2_DEFAULT 0x00000000 |
4895 | #define smnBIF_CFG_DEV0_EPF1_1_BASE_ADDR_3_DEFAULT 0x00000000 |
4896 | #define smnBIF_CFG_DEV0_EPF1_1_BASE_ADDR_4_DEFAULT 0x00000000 |
4897 | #define smnBIF_CFG_DEV0_EPF1_1_BASE_ADDR_5_DEFAULT 0x00000000 |
4898 | #define smnBIF_CFG_DEV0_EPF1_1_BASE_ADDR_6_DEFAULT 0x00000000 |
4899 | #define smnBIF_CFG_DEV0_EPF1_1_ADAPTER_ID_DEFAULT 0x00000000 |
4900 | #define smnBIF_CFG_DEV0_EPF1_1_ROM_BASE_ADDR_DEFAULT 0x00000000 |
4901 | #define smnBIF_CFG_DEV0_EPF1_1_CAP_PTR_DEFAULT 0x00000000 |
4902 | #define smnBIF_CFG_DEV0_EPF1_1_INTERRUPT_LINE_DEFAULT 0x000000ff |
4903 | #define smnBIF_CFG_DEV0_EPF1_1_INTERRUPT_PIN_DEFAULT 0x00000000 |
4904 | #define smnBIF_CFG_DEV0_EPF1_1_MIN_GRANT_DEFAULT 0x00000000 |
4905 | #define smnBIF_CFG_DEV0_EPF1_1_MAX_LATENCY_DEFAULT 0x00000000 |
4906 | #define smnBIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST_DEFAULT 0x00000000 |
4907 | #define smnBIF_CFG_DEV0_EPF1_1_ADAPTER_ID_W_DEFAULT 0x00000000 |
4908 | #define smnBIF_CFG_DEV0_EPF1_1_PMI_CAP_LIST_DEFAULT 0x00000000 |
4909 | #define smnBIF_CFG_DEV0_EPF1_1_PMI_CAP_DEFAULT 0x00000000 |
4910 | #define smnBIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL_DEFAULT 0x00000000 |
4911 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_CAP_LIST_DEFAULT 0x0000a000 |
4912 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_CAP_DEFAULT 0x00000002 |
4913 | #define smnBIF_CFG_DEV0_EPF1_1_DEVICE_CAP_DEFAULT 0x10000000 |
4914 | #define smnBIF_CFG_DEV0_EPF1_1_DEVICE_CNTL_DEFAULT 0x00002810 |
4915 | #define smnBIF_CFG_DEV0_EPF1_1_DEVICE_STATUS_DEFAULT 0x00000000 |
4916 | #define smnBIF_CFG_DEV0_EPF1_1_LINK_CAP_DEFAULT 0x00011c03 |
4917 | #define smnBIF_CFG_DEV0_EPF1_1_LINK_CNTL_DEFAULT 0x00000000 |
4918 | #define smnBIF_CFG_DEV0_EPF1_1_LINK_STATUS_DEFAULT 0x00000001 |
4919 | #define smnBIF_CFG_DEV0_EPF1_1_DEVICE_CAP2_DEFAULT 0x00000000 |
4920 | #define smnBIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2_DEFAULT 0x00000000 |
4921 | #define smnBIF_CFG_DEV0_EPF1_1_DEVICE_STATUS2_DEFAULT 0x00000000 |
4922 | #define smnBIF_CFG_DEV0_EPF1_1_LINK_CAP2_DEFAULT 0x0000000e |
4923 | #define smnBIF_CFG_DEV0_EPF1_1_LINK_CNTL2_DEFAULT 0x00000003 |
4924 | #define smnBIF_CFG_DEV0_EPF1_1_LINK_STATUS2_DEFAULT 0x00000000 |
4925 | #define smnBIF_CFG_DEV0_EPF1_1_SLOT_CAP2_DEFAULT 0x00000000 |
4926 | #define smnBIF_CFG_DEV0_EPF1_1_SLOT_CNTL2_DEFAULT 0x00000000 |
4927 | #define smnBIF_CFG_DEV0_EPF1_1_SLOT_STATUS2_DEFAULT 0x00000000 |
4928 | #define smnBIF_CFG_DEV0_EPF1_1_MSI_CAP_LIST_DEFAULT 0x0000c000 |
4929 | #define smnBIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL_DEFAULT 0x00000080 |
4930 | #define smnBIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 |
4931 | #define smnBIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 |
4932 | #define smnBIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA_DEFAULT 0x00000000 |
4933 | #define smnBIF_CFG_DEV0_EPF1_1_MSI_MASK_DEFAULT 0x00000000 |
4934 | #define smnBIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA_64_DEFAULT 0x00000000 |
4935 | #define smnBIF_CFG_DEV0_EPF1_1_MSI_MASK_64_DEFAULT 0x00000000 |
4936 | #define smnBIF_CFG_DEV0_EPF1_1_MSI_PENDING_DEFAULT 0x00000000 |
4937 | #define smnBIF_CFG_DEV0_EPF1_1_MSI_PENDING_64_DEFAULT 0x00000000 |
4938 | #define smnBIF_CFG_DEV0_EPF1_1_MSIX_CAP_LIST_DEFAULT 0x00000000 |
4939 | #define smnBIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL_DEFAULT 0x00000000 |
4940 | #define smnBIF_CFG_DEV0_EPF1_1_MSIX_TABLE_DEFAULT 0x00000000 |
4941 | #define smnBIF_CFG_DEV0_EPF1_1_MSIX_PBA_DEFAULT 0x00000000 |
4942 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 |
4943 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 |
4944 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 |
4945 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 |
4946 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000 |
4947 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000 |
4948 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000 |
4949 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000 |
4950 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000 |
4951 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000 |
4952 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe |
4953 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000000 |
4954 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000 |
4955 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000 |
4956 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000000 |
4957 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000 |
4958 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000 |
4959 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000 |
4960 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 |
4961 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 |
4962 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 |
4963 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 |
4964 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 |
4965 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000 |
4966 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 |
4967 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG0_DEFAULT 0x00000000 |
4968 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG1_DEFAULT 0x00000000 |
4969 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG2_DEFAULT 0x00000000 |
4970 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG3_DEFAULT 0x00000000 |
4971 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 |
4972 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 |
4973 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 |
4974 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 |
4975 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000 |
4976 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CAP_DEFAULT 0x00000000 |
4977 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL_DEFAULT 0x00000020 |
4978 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CAP_DEFAULT 0x00000000 |
4979 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL_DEFAULT 0x00000000 |
4980 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CAP_DEFAULT 0x00000000 |
4981 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL_DEFAULT 0x00000000 |
4982 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CAP_DEFAULT 0x00000000 |
4983 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL_DEFAULT 0x00000000 |
4984 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CAP_DEFAULT 0x00000000 |
4985 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL_DEFAULT 0x00000000 |
4986 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CAP_DEFAULT 0x00000000 |
4987 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL_DEFAULT 0x00000000 |
4988 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000 |
4989 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000 |
4990 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000 |
4991 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000 |
4992 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000 |
4993 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP_DEFAULT 0x00000000 |
4994 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000 |
4995 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_DPA_STATUS_DEFAULT 0x00000100 |
4996 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_DPA_CNTL_DEFAULT 0x00000000 |
4997 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000 |
4998 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000 |
4999 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000 |
5000 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000 |
5001 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000 |
5002 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000 |
5003 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000 |
5004 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000 |
5005 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a010019 |
5006 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3_DEFAULT 0x00000000 |
5007 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000 |
5008 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
5009 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
5010 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
5011 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
5012 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
5013 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
5014 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
5015 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
5016 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
5017 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
5018 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
5019 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
5020 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
5021 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
5022 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
5023 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
5024 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000 |
5025 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP_DEFAULT 0x00000000 |
5026 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL_DEFAULT 0x00000000 |
5027 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 |
5028 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_ATS_CAP_DEFAULT 0x00000000 |
5029 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_ATS_CNTL_DEFAULT 0x00000000 |
5030 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_ENH_CAP_LIST_DEFAULT 0x2d000000 |
5031 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_CNTL_DEFAULT 0x00000000 |
5032 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS_DEFAULT 0x00000000 |
5033 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY_DEFAULT 0x00000000 |
5034 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_OUTSTAND_PAGE_REQ_ALLOC_DEFAULT 0x00000000 |
5035 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST_DEFAULT 0x2e000000 |
5036 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP_DEFAULT 0x00000000 |
5037 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL_DEFAULT 0x00000000 |
5038 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST_DEFAULT 0x2f000000 |
5039 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP_DEFAULT 0x00000000 |
5040 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CNTL_DEFAULT 0x00000000 |
5041 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST_DEFAULT 0x32000000 |
5042 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP_DEFAULT 0x00000000 |
5043 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_MC_CNTL_DEFAULT 0x00000000 |
5044 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR0_DEFAULT 0x00000000 |
5045 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR1_DEFAULT 0x00000000 |
5046 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV0_DEFAULT 0x00000000 |
5047 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV1_DEFAULT 0x00000000 |
5048 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL0_DEFAULT 0x00000000 |
5049 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL1_DEFAULT 0x00000000 |
5050 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_0_DEFAULT 0x00000000 |
5051 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_1_DEFAULT 0x00000000 |
5052 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST_DEFAULT 0x32800000 |
5053 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP_DEFAULT 0x00000000 |
5054 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000 |
5055 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP_DEFAULT 0x00000000 |
5056 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL_DEFAULT 0x00000000 |
5057 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST_DEFAULT 0x00000000 |
5058 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP_DEFAULT 0x00000000 |
5059 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL_DEFAULT 0x00000000 |
5060 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_STATUS_DEFAULT 0x00000000 |
5061 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_INITIAL_VFS_DEFAULT 0x00000000 |
5062 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_TOTAL_VFS_DEFAULT 0x00000000 |
5063 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_NUM_VFS_DEFAULT 0x00000000 |
5064 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FUNC_DEP_LINK_DEFAULT 0x00000000 |
5065 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FIRST_VF_OFFSET_DEFAULT 0x00000000 |
5066 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_STRIDE_DEFAULT 0x00000000 |
5067 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_DEVICE_ID_DEFAULT 0x00000000 |
5068 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE_DEFAULT 0x00000000 |
5069 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE_DEFAULT 0x00000001 |
5070 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_0_DEFAULT 0x00000000 |
5071 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_1_DEFAULT 0x00000000 |
5072 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_2_DEFAULT 0x00000000 |
5073 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_3_DEFAULT 0x00000000 |
5074 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_4_DEFAULT 0x00000000 |
5075 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_5_DEFAULT 0x00000000 |
5076 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_DEFAULT 0x00000000 |
5077 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_DEFAULT 0x00000000 |
5078 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_DEFAULT 0x00000000 |
5079 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW_DEFAULT 0x00000000 |
5080 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_DEFAULT 0x00000000 |
5081 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_DEFAULT 0x00000000 |
5082 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_DEFAULT 0x00000000 |
5083 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0_DEFAULT 0x00000000 |
5084 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_DEFAULT 0x00000000 |
5085 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2_DEFAULT 0x00000000 |
5086 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT_DEFAULT 0x00000000 |
5087 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB_DEFAULT 0x00000000 |
5088 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS_DEFAULT 0x00000000 |
5089 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB_DEFAULT 0x00000000 |
5090 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB_DEFAULT 0x00000000 |
5091 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB_DEFAULT 0x00000000 |
5092 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB_DEFAULT 0x00000000 |
5093 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB_DEFAULT 0x00000000 |
5094 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB_DEFAULT 0x00000000 |
5095 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB_DEFAULT 0x00000000 |
5096 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB_DEFAULT 0x00000000 |
5097 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB_DEFAULT 0x00000000 |
5098 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB_DEFAULT 0x00000000 |
5099 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB_DEFAULT 0x00000000 |
5100 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB_DEFAULT 0x00000000 |
5101 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB_DEFAULT 0x00000000 |
5102 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB_DEFAULT 0x00000000 |
5103 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB_DEFAULT 0x00000000 |
5104 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB_DEFAULT 0x00000000 |
5105 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0_DEFAULT 0x00000000 |
5106 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1_DEFAULT 0x00000000 |
5107 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2_DEFAULT 0x00000000 |
5108 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3_DEFAULT 0x00000000 |
5109 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4_DEFAULT 0x00000000 |
5110 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5_DEFAULT 0x00000000 |
5111 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6_DEFAULT 0x00000000 |
5112 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7_DEFAULT 0x00000000 |
5113 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8_DEFAULT 0x00000000 |
5114 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0_DEFAULT 0x00000000 |
5115 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1_DEFAULT 0x00000000 |
5116 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2_DEFAULT 0x00000000 |
5117 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3_DEFAULT 0x00000000 |
5118 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4_DEFAULT 0x00000000 |
5119 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5_DEFAULT 0x00000000 |
5120 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6_DEFAULT 0x00000000 |
5121 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7_DEFAULT 0x00000000 |
5122 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8_DEFAULT 0x00000000 |
5123 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0_DEFAULT 0x00000000 |
5124 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1_DEFAULT 0x00000000 |
5125 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2_DEFAULT 0x00000000 |
5126 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3_DEFAULT 0x00000000 |
5127 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4_DEFAULT 0x00000000 |
5128 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5_DEFAULT 0x00000000 |
5129 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6_DEFAULT 0x00000000 |
5130 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7_DEFAULT 0x00000000 |
5131 | #define smnBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8_DEFAULT 0x00000000 |
5132 | |
5133 | |
5134 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf2_bifcfgdecp |
5135 | #define smnBIF_CFG_DEV0_EPF2_1_VENDOR_ID_DEFAULT 0x00000000 |
5136 | #define smnBIF_CFG_DEV0_EPF2_1_DEVICE_ID_DEFAULT 0x00000000 |
5137 | #define smnBIF_CFG_DEV0_EPF2_1_COMMAND_DEFAULT 0x00000000 |
5138 | #define smnBIF_CFG_DEV0_EPF2_1_STATUS_DEFAULT 0x00000000 |
5139 | #define smnBIF_CFG_DEV0_EPF2_1_REVISION_ID_DEFAULT 0x00000000 |
5140 | #define smnBIF_CFG_DEV0_EPF2_1_PROG_INTERFACE_DEFAULT 0x00000000 |
5141 | #define smnBIF_CFG_DEV0_EPF2_1_SUB_CLASS_DEFAULT 0x00000000 |
5142 | #define smnBIF_CFG_DEV0_EPF2_1_BASE_CLASS_DEFAULT 0x00000000 |
5143 | #define smnBIF_CFG_DEV0_EPF2_1_CACHE_LINE_DEFAULT 0x00000000 |
5144 | #define smnBIF_CFG_DEV0_EPF2_1_LATENCY_DEFAULT 0x00000000 |
5145 | #define 0x00000000 |
5146 | #define smnBIF_CFG_DEV0_EPF2_1_BIST_DEFAULT 0x00000000 |
5147 | #define smnBIF_CFG_DEV0_EPF2_1_BASE_ADDR_1_DEFAULT 0x00000000 |
5148 | #define smnBIF_CFG_DEV0_EPF2_1_BASE_ADDR_2_DEFAULT 0x00000000 |
5149 | #define smnBIF_CFG_DEV0_EPF2_1_BASE_ADDR_3_DEFAULT 0x00000000 |
5150 | #define smnBIF_CFG_DEV0_EPF2_1_BASE_ADDR_4_DEFAULT 0x00000000 |
5151 | #define smnBIF_CFG_DEV0_EPF2_1_BASE_ADDR_5_DEFAULT 0x00000000 |
5152 | #define smnBIF_CFG_DEV0_EPF2_1_BASE_ADDR_6_DEFAULT 0x00000000 |
5153 | #define smnBIF_CFG_DEV0_EPF2_1_ADAPTER_ID_DEFAULT 0x00000000 |
5154 | #define smnBIF_CFG_DEV0_EPF2_1_ROM_BASE_ADDR_DEFAULT 0x00000000 |
5155 | #define smnBIF_CFG_DEV0_EPF2_1_CAP_PTR_DEFAULT 0x00000000 |
5156 | #define smnBIF_CFG_DEV0_EPF2_1_INTERRUPT_LINE_DEFAULT 0x00000000 |
5157 | #define smnBIF_CFG_DEV0_EPF2_1_INTERRUPT_PIN_DEFAULT 0x00000000 |
5158 | #define smnBIF_CFG_DEV0_EPF2_1_MIN_GRANT_DEFAULT 0x00000000 |
5159 | #define smnBIF_CFG_DEV0_EPF2_1_MAX_LATENCY_DEFAULT 0x00000000 |
5160 | #define smnBIF_CFG_DEV0_EPF2_1_VENDOR_CAP_LIST_DEFAULT 0x00000000 |
5161 | #define smnBIF_CFG_DEV0_EPF2_1_ADAPTER_ID_W_DEFAULT 0x00000000 |
5162 | #define smnBIF_CFG_DEV0_EPF2_1_PMI_CAP_LIST_DEFAULT 0x00000000 |
5163 | #define smnBIF_CFG_DEV0_EPF2_1_PMI_CAP_DEFAULT 0x00000000 |
5164 | #define smnBIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL_DEFAULT 0x00000000 |
5165 | #define smnBIF_CFG_DEV0_EPF2_1_SBRN_DEFAULT 0x00000000 |
5166 | #define smnBIF_CFG_DEV0_EPF2_1_FLADJ_DEFAULT 0x00000020 |
5167 | #define smnBIF_CFG_DEV0_EPF2_1_DBESL_DBESLD_DEFAULT 0x00000000 |
5168 | #define smnBIF_CFG_DEV0_EPF2_1_PCIE_CAP_LIST_DEFAULT 0x0000a000 |
5169 | #define smnBIF_CFG_DEV0_EPF2_1_PCIE_CAP_DEFAULT 0x00000002 |
5170 | #define smnBIF_CFG_DEV0_EPF2_1_DEVICE_CAP_DEFAULT 0x10000000 |
5171 | #define smnBIF_CFG_DEV0_EPF2_1_DEVICE_CNTL_DEFAULT 0x00002810 |
5172 | #define smnBIF_CFG_DEV0_EPF2_1_DEVICE_STATUS_DEFAULT 0x00000000 |
5173 | #define smnBIF_CFG_DEV0_EPF2_1_LINK_CAP_DEFAULT 0x00011c03 |
5174 | #define smnBIF_CFG_DEV0_EPF2_1_LINK_CNTL_DEFAULT 0x00000000 |
5175 | #define smnBIF_CFG_DEV0_EPF2_1_LINK_STATUS_DEFAULT 0x00000001 |
5176 | #define smnBIF_CFG_DEV0_EPF2_1_DEVICE_CAP2_DEFAULT 0x00000000 |
5177 | #define smnBIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2_DEFAULT 0x00000000 |
5178 | #define smnBIF_CFG_DEV0_EPF2_1_DEVICE_STATUS2_DEFAULT 0x00000000 |
5179 | #define smnBIF_CFG_DEV0_EPF2_1_LINK_CAP2_DEFAULT 0x0000000e |
5180 | #define smnBIF_CFG_DEV0_EPF2_1_LINK_CNTL2_DEFAULT 0x00000003 |
5181 | #define smnBIF_CFG_DEV0_EPF2_1_LINK_STATUS2_DEFAULT 0x00000000 |
5182 | #define smnBIF_CFG_DEV0_EPF2_1_SLOT_CAP2_DEFAULT 0x00000000 |
5183 | #define smnBIF_CFG_DEV0_EPF2_1_SLOT_CNTL2_DEFAULT 0x00000000 |
5184 | #define smnBIF_CFG_DEV0_EPF2_1_SLOT_STATUS2_DEFAULT 0x00000000 |
5185 | #define smnBIF_CFG_DEV0_EPF2_1_MSI_CAP_LIST_DEFAULT 0x0000c000 |
5186 | #define smnBIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL_DEFAULT 0x00000080 |
5187 | #define smnBIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 |
5188 | #define smnBIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 |
5189 | #define smnBIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA_DEFAULT 0x00000000 |
5190 | #define smnBIF_CFG_DEV0_EPF2_1_MSI_MASK_DEFAULT 0x00000000 |
5191 | #define smnBIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA_64_DEFAULT 0x00000000 |
5192 | #define smnBIF_CFG_DEV0_EPF2_1_MSI_MASK_64_DEFAULT 0x00000000 |
5193 | #define smnBIF_CFG_DEV0_EPF2_1_MSI_PENDING_DEFAULT 0x00000000 |
5194 | #define smnBIF_CFG_DEV0_EPF2_1_MSI_PENDING_64_DEFAULT 0x00000000 |
5195 | #define smnBIF_CFG_DEV0_EPF2_1_MSIX_CAP_LIST_DEFAULT 0x00000000 |
5196 | #define smnBIF_CFG_DEV0_EPF2_1_MSIX_MSG_CNTL_DEFAULT 0x00000000 |
5197 | #define smnBIF_CFG_DEV0_EPF2_1_MSIX_TABLE_DEFAULT 0x00000000 |
5198 | #define smnBIF_CFG_DEV0_EPF2_1_MSIX_PBA_DEFAULT 0x00000000 |
5199 | #define smnBIF_CFG_DEV0_EPF2_1_SATA_CAP_0_DEFAULT 0x00000000 |
5200 | #define smnBIF_CFG_DEV0_EPF2_1_SATA_CAP_1_DEFAULT 0x00000000 |
5201 | #define smnBIF_CFG_DEV0_EPF2_1_SATA_IDP_INDEX_DEFAULT 0x00000000 |
5202 | #define smnBIF_CFG_DEV0_EPF2_1_SATA_IDP_DATA_DEFAULT 0x00000000 |
5203 | #define smnBIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 |
5204 | #define smnBIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 |
5205 | #define smnBIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 |
5206 | #define smnBIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 |
5207 | #define smnBIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 |
5208 | #define smnBIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 |
5209 | #define smnBIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 |
5210 | #define smnBIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 |
5211 | #define smnBIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 |
5212 | #define smnBIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000 |
5213 | #define smnBIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 |
5214 | #define smnBIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG0_DEFAULT 0x00000000 |
5215 | #define smnBIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG1_DEFAULT 0x00000000 |
5216 | #define smnBIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG2_DEFAULT 0x00000000 |
5217 | #define smnBIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG3_DEFAULT 0x00000000 |
5218 | #define smnBIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 |
5219 | #define smnBIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 |
5220 | #define smnBIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 |
5221 | #define smnBIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 |
5222 | #define smnBIF_CFG_DEV0_EPF2_1_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000 |
5223 | #define smnBIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CAP_DEFAULT 0x00000000 |
5224 | #define smnBIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL_DEFAULT 0x00000020 |
5225 | #define smnBIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CAP_DEFAULT 0x00000000 |
5226 | #define smnBIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL_DEFAULT 0x00000000 |
5227 | #define smnBIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CAP_DEFAULT 0x00000000 |
5228 | #define smnBIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL_DEFAULT 0x00000000 |
5229 | #define smnBIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CAP_DEFAULT 0x00000000 |
5230 | #define smnBIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL_DEFAULT 0x00000000 |
5231 | #define smnBIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CAP_DEFAULT 0x00000000 |
5232 | #define smnBIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL_DEFAULT 0x00000000 |
5233 | #define smnBIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CAP_DEFAULT 0x00000000 |
5234 | #define smnBIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL_DEFAULT 0x00000000 |
5235 | #define smnBIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000 |
5236 | #define smnBIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000 |
5237 | #define smnBIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000 |
5238 | #define smnBIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000 |
5239 | #define smnBIF_CFG_DEV0_EPF2_1_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000 |
5240 | #define smnBIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP_DEFAULT 0x00000000 |
5241 | #define smnBIF_CFG_DEV0_EPF2_1_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000 |
5242 | #define smnBIF_CFG_DEV0_EPF2_1_PCIE_DPA_STATUS_DEFAULT 0x00000100 |
5243 | #define smnBIF_CFG_DEV0_EPF2_1_PCIE_DPA_CNTL_DEFAULT 0x00000000 |
5244 | #define smnBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000 |
5245 | #define smnBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000 |
5246 | #define smnBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000 |
5247 | #define smnBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000 |
5248 | #define smnBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000 |
5249 | #define smnBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000 |
5250 | #define smnBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000 |
5251 | #define smnBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000 |
5252 | #define smnBIF_CFG_DEV0_EPF2_1_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000 |
5253 | #define smnBIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP_DEFAULT 0x00000000 |
5254 | #define smnBIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL_DEFAULT 0x00000000 |
5255 | #define smnBIF_CFG_DEV0_EPF2_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000 |
5256 | #define smnBIF_CFG_DEV0_EPF2_1_PCIE_ARI_CAP_DEFAULT 0x00000000 |
5257 | #define smnBIF_CFG_DEV0_EPF2_1_PCIE_ARI_CNTL_DEFAULT 0x00000000 |
5258 | |
5259 | |
5260 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf3_bifcfgdecp |
5261 | #define smnBIF_CFG_DEV0_EPF3_1_VENDOR_ID_DEFAULT 0x00000000 |
5262 | #define smnBIF_CFG_DEV0_EPF3_1_DEVICE_ID_DEFAULT 0x00000000 |
5263 | #define smnBIF_CFG_DEV0_EPF3_1_COMMAND_DEFAULT 0x00000000 |
5264 | #define smnBIF_CFG_DEV0_EPF3_1_STATUS_DEFAULT 0x00000000 |
5265 | #define smnBIF_CFG_DEV0_EPF3_1_REVISION_ID_DEFAULT 0x00000000 |
5266 | #define smnBIF_CFG_DEV0_EPF3_1_PROG_INTERFACE_DEFAULT 0x00000000 |
5267 | #define smnBIF_CFG_DEV0_EPF3_1_SUB_CLASS_DEFAULT 0x00000000 |
5268 | #define smnBIF_CFG_DEV0_EPF3_1_BASE_CLASS_DEFAULT 0x00000000 |
5269 | #define smnBIF_CFG_DEV0_EPF3_1_CACHE_LINE_DEFAULT 0x00000000 |
5270 | #define smnBIF_CFG_DEV0_EPF3_1_LATENCY_DEFAULT 0x00000000 |
5271 | #define 0x00000000 |
5272 | #define smnBIF_CFG_DEV0_EPF3_1_BIST_DEFAULT 0x00000000 |
5273 | #define smnBIF_CFG_DEV0_EPF3_1_BASE_ADDR_1_DEFAULT 0x00000000 |
5274 | #define smnBIF_CFG_DEV0_EPF3_1_BASE_ADDR_2_DEFAULT 0x00000000 |
5275 | #define smnBIF_CFG_DEV0_EPF3_1_BASE_ADDR_3_DEFAULT 0x00000000 |
5276 | #define smnBIF_CFG_DEV0_EPF3_1_BASE_ADDR_4_DEFAULT 0x00000000 |
5277 | #define smnBIF_CFG_DEV0_EPF3_1_BASE_ADDR_5_DEFAULT 0x00000000 |
5278 | #define smnBIF_CFG_DEV0_EPF3_1_BASE_ADDR_6_DEFAULT 0x00000000 |
5279 | #define smnBIF_CFG_DEV0_EPF3_1_ADAPTER_ID_DEFAULT 0x00000000 |
5280 | #define smnBIF_CFG_DEV0_EPF3_1_ROM_BASE_ADDR_DEFAULT 0x00000000 |
5281 | #define smnBIF_CFG_DEV0_EPF3_1_CAP_PTR_DEFAULT 0x00000000 |
5282 | #define smnBIF_CFG_DEV0_EPF3_1_INTERRUPT_LINE_DEFAULT 0x00000000 |
5283 | #define smnBIF_CFG_DEV0_EPF3_1_INTERRUPT_PIN_DEFAULT 0x00000000 |
5284 | #define smnBIF_CFG_DEV0_EPF3_1_MIN_GRANT_DEFAULT 0x00000000 |
5285 | #define smnBIF_CFG_DEV0_EPF3_1_MAX_LATENCY_DEFAULT 0x00000000 |
5286 | #define smnBIF_CFG_DEV0_EPF3_1_VENDOR_CAP_LIST_DEFAULT 0x00000000 |
5287 | #define smnBIF_CFG_DEV0_EPF3_1_ADAPTER_ID_W_DEFAULT 0x00000000 |
5288 | #define smnBIF_CFG_DEV0_EPF3_1_PMI_CAP_LIST_DEFAULT 0x00000000 |
5289 | #define smnBIF_CFG_DEV0_EPF3_1_PMI_CAP_DEFAULT 0x00000000 |
5290 | #define smnBIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL_DEFAULT 0x00000000 |
5291 | #define smnBIF_CFG_DEV0_EPF3_1_SBRN_DEFAULT 0x00000000 |
5292 | #define smnBIF_CFG_DEV0_EPF3_1_FLADJ_DEFAULT 0x00000020 |
5293 | #define smnBIF_CFG_DEV0_EPF3_1_DBESL_DBESLD_DEFAULT 0x00000000 |
5294 | #define smnBIF_CFG_DEV0_EPF3_1_PCIE_CAP_LIST_DEFAULT 0x0000a000 |
5295 | #define smnBIF_CFG_DEV0_EPF3_1_PCIE_CAP_DEFAULT 0x00000002 |
5296 | #define smnBIF_CFG_DEV0_EPF3_1_DEVICE_CAP_DEFAULT 0x10000000 |
5297 | #define smnBIF_CFG_DEV0_EPF3_1_DEVICE_CNTL_DEFAULT 0x00002810 |
5298 | #define smnBIF_CFG_DEV0_EPF3_1_DEVICE_STATUS_DEFAULT 0x00000000 |
5299 | #define smnBIF_CFG_DEV0_EPF3_1_LINK_CAP_DEFAULT 0x00011c03 |
5300 | #define smnBIF_CFG_DEV0_EPF3_1_LINK_CNTL_DEFAULT 0x00000000 |
5301 | #define smnBIF_CFG_DEV0_EPF3_1_LINK_STATUS_DEFAULT 0x00000001 |
5302 | #define smnBIF_CFG_DEV0_EPF3_1_DEVICE_CAP2_DEFAULT 0x00000000 |
5303 | #define smnBIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2_DEFAULT 0x00000000 |
5304 | #define smnBIF_CFG_DEV0_EPF3_1_DEVICE_STATUS2_DEFAULT 0x00000000 |
5305 | #define smnBIF_CFG_DEV0_EPF3_1_LINK_CAP2_DEFAULT 0x0000000e |
5306 | #define smnBIF_CFG_DEV0_EPF3_1_LINK_CNTL2_DEFAULT 0x00000003 |
5307 | #define smnBIF_CFG_DEV0_EPF3_1_LINK_STATUS2_DEFAULT 0x00000000 |
5308 | #define smnBIF_CFG_DEV0_EPF3_1_SLOT_CAP2_DEFAULT 0x00000000 |
5309 | #define smnBIF_CFG_DEV0_EPF3_1_SLOT_CNTL2_DEFAULT 0x00000000 |
5310 | #define smnBIF_CFG_DEV0_EPF3_1_SLOT_STATUS2_DEFAULT 0x00000000 |
5311 | #define smnBIF_CFG_DEV0_EPF3_1_MSI_CAP_LIST_DEFAULT 0x0000c000 |
5312 | #define smnBIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL_DEFAULT 0x00000080 |
5313 | #define smnBIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 |
5314 | #define smnBIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 |
5315 | #define smnBIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA_DEFAULT 0x00000000 |
5316 | #define smnBIF_CFG_DEV0_EPF3_1_MSI_MASK_DEFAULT 0x00000000 |
5317 | #define smnBIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA_64_DEFAULT 0x00000000 |
5318 | #define smnBIF_CFG_DEV0_EPF3_1_MSI_MASK_64_DEFAULT 0x00000000 |
5319 | #define smnBIF_CFG_DEV0_EPF3_1_MSI_PENDING_DEFAULT 0x00000000 |
5320 | #define smnBIF_CFG_DEV0_EPF3_1_MSI_PENDING_64_DEFAULT 0x00000000 |
5321 | #define smnBIF_CFG_DEV0_EPF3_1_MSIX_CAP_LIST_DEFAULT 0x00000000 |
5322 | #define smnBIF_CFG_DEV0_EPF3_1_MSIX_MSG_CNTL_DEFAULT 0x00000000 |
5323 | #define smnBIF_CFG_DEV0_EPF3_1_MSIX_TABLE_DEFAULT 0x00000000 |
5324 | #define smnBIF_CFG_DEV0_EPF3_1_MSIX_PBA_DEFAULT 0x00000000 |
5325 | #define smnBIF_CFG_DEV0_EPF3_1_SATA_CAP_0_DEFAULT 0x00000000 |
5326 | #define smnBIF_CFG_DEV0_EPF3_1_SATA_CAP_1_DEFAULT 0x00000000 |
5327 | #define smnBIF_CFG_DEV0_EPF3_1_SATA_IDP_INDEX_DEFAULT 0x00000000 |
5328 | #define smnBIF_CFG_DEV0_EPF3_1_SATA_IDP_DATA_DEFAULT 0x00000000 |
5329 | #define smnBIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 |
5330 | #define smnBIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 |
5331 | #define smnBIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 |
5332 | #define smnBIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 |
5333 | #define smnBIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 |
5334 | #define smnBIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 |
5335 | #define smnBIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 |
5336 | #define smnBIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 |
5337 | #define smnBIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 |
5338 | #define smnBIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000 |
5339 | #define smnBIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 |
5340 | #define smnBIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG0_DEFAULT 0x00000000 |
5341 | #define smnBIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG1_DEFAULT 0x00000000 |
5342 | #define smnBIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG2_DEFAULT 0x00000000 |
5343 | #define smnBIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG3_DEFAULT 0x00000000 |
5344 | #define smnBIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 |
5345 | #define smnBIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 |
5346 | #define smnBIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 |
5347 | #define smnBIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 |
5348 | #define smnBIF_CFG_DEV0_EPF3_1_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000 |
5349 | #define smnBIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CAP_DEFAULT 0x00000000 |
5350 | #define smnBIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL_DEFAULT 0x00000020 |
5351 | #define smnBIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CAP_DEFAULT 0x00000000 |
5352 | #define smnBIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL_DEFAULT 0x00000000 |
5353 | #define smnBIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CAP_DEFAULT 0x00000000 |
5354 | #define smnBIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL_DEFAULT 0x00000000 |
5355 | #define smnBIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CAP_DEFAULT 0x00000000 |
5356 | #define smnBIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL_DEFAULT 0x00000000 |
5357 | #define smnBIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CAP_DEFAULT 0x00000000 |
5358 | #define smnBIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL_DEFAULT 0x00000000 |
5359 | #define smnBIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CAP_DEFAULT 0x00000000 |
5360 | #define smnBIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL_DEFAULT 0x00000000 |
5361 | #define smnBIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000 |
5362 | #define smnBIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000 |
5363 | #define smnBIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000 |
5364 | #define smnBIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000 |
5365 | #define smnBIF_CFG_DEV0_EPF3_1_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000 |
5366 | #define smnBIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP_DEFAULT 0x00000000 |
5367 | #define smnBIF_CFG_DEV0_EPF3_1_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000 |
5368 | #define smnBIF_CFG_DEV0_EPF3_1_PCIE_DPA_STATUS_DEFAULT 0x00000100 |
5369 | #define smnBIF_CFG_DEV0_EPF3_1_PCIE_DPA_CNTL_DEFAULT 0x00000000 |
5370 | #define smnBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000 |
5371 | #define smnBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000 |
5372 | #define smnBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000 |
5373 | #define smnBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000 |
5374 | #define smnBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000 |
5375 | #define smnBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000 |
5376 | #define smnBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000 |
5377 | #define smnBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000 |
5378 | #define smnBIF_CFG_DEV0_EPF3_1_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000 |
5379 | #define smnBIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP_DEFAULT 0x00000000 |
5380 | #define smnBIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL_DEFAULT 0x00000000 |
5381 | #define smnBIF_CFG_DEV0_EPF3_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000 |
5382 | #define smnBIF_CFG_DEV0_EPF3_1_PCIE_ARI_CAP_DEFAULT 0x00000000 |
5383 | #define smnBIF_CFG_DEV0_EPF3_1_PCIE_ARI_CNTL_DEFAULT 0x00000000 |
5384 | |
5385 | |
5386 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf4_bifcfgdecp |
5387 | #define smnBIF_CFG_DEV0_EPF4_1_VENDOR_ID_DEFAULT 0x00000000 |
5388 | #define smnBIF_CFG_DEV0_EPF4_1_DEVICE_ID_DEFAULT 0x00000000 |
5389 | #define smnBIF_CFG_DEV0_EPF4_1_COMMAND_DEFAULT 0x00000000 |
5390 | #define smnBIF_CFG_DEV0_EPF4_1_STATUS_DEFAULT 0x00000000 |
5391 | #define smnBIF_CFG_DEV0_EPF4_1_REVISION_ID_DEFAULT 0x00000000 |
5392 | #define smnBIF_CFG_DEV0_EPF4_1_PROG_INTERFACE_DEFAULT 0x00000000 |
5393 | #define smnBIF_CFG_DEV0_EPF4_1_SUB_CLASS_DEFAULT 0x00000000 |
5394 | #define smnBIF_CFG_DEV0_EPF4_1_BASE_CLASS_DEFAULT 0x00000000 |
5395 | #define smnBIF_CFG_DEV0_EPF4_1_CACHE_LINE_DEFAULT 0x00000000 |
5396 | #define smnBIF_CFG_DEV0_EPF4_1_LATENCY_DEFAULT 0x00000000 |
5397 | #define 0x00000000 |
5398 | #define smnBIF_CFG_DEV0_EPF4_1_BIST_DEFAULT 0x00000000 |
5399 | #define smnBIF_CFG_DEV0_EPF4_1_BASE_ADDR_1_DEFAULT 0x00000000 |
5400 | #define smnBIF_CFG_DEV0_EPF4_1_BASE_ADDR_2_DEFAULT 0x00000000 |
5401 | #define smnBIF_CFG_DEV0_EPF4_1_BASE_ADDR_3_DEFAULT 0x00000000 |
5402 | #define smnBIF_CFG_DEV0_EPF4_1_BASE_ADDR_4_DEFAULT 0x00000000 |
5403 | #define smnBIF_CFG_DEV0_EPF4_1_BASE_ADDR_5_DEFAULT 0x00000000 |
5404 | #define smnBIF_CFG_DEV0_EPF4_1_BASE_ADDR_6_DEFAULT 0x00000000 |
5405 | #define smnBIF_CFG_DEV0_EPF4_1_ADAPTER_ID_DEFAULT 0x00000000 |
5406 | #define smnBIF_CFG_DEV0_EPF4_1_ROM_BASE_ADDR_DEFAULT 0x00000000 |
5407 | #define smnBIF_CFG_DEV0_EPF4_1_CAP_PTR_DEFAULT 0x00000000 |
5408 | #define smnBIF_CFG_DEV0_EPF4_1_INTERRUPT_LINE_DEFAULT 0x00000000 |
5409 | #define smnBIF_CFG_DEV0_EPF4_1_INTERRUPT_PIN_DEFAULT 0x00000000 |
5410 | #define smnBIF_CFG_DEV0_EPF4_1_MIN_GRANT_DEFAULT 0x00000000 |
5411 | #define smnBIF_CFG_DEV0_EPF4_1_MAX_LATENCY_DEFAULT 0x00000000 |
5412 | #define smnBIF_CFG_DEV0_EPF4_1_VENDOR_CAP_LIST_DEFAULT 0x00000000 |
5413 | #define smnBIF_CFG_DEV0_EPF4_1_ADAPTER_ID_W_DEFAULT 0x00000000 |
5414 | #define smnBIF_CFG_DEV0_EPF4_1_PMI_CAP_LIST_DEFAULT 0x00000000 |
5415 | #define smnBIF_CFG_DEV0_EPF4_1_PMI_CAP_DEFAULT 0x00000000 |
5416 | #define smnBIF_CFG_DEV0_EPF4_1_PMI_STATUS_CNTL_DEFAULT 0x00000000 |
5417 | #define smnBIF_CFG_DEV0_EPF4_1_SBRN_DEFAULT 0x00000000 |
5418 | #define smnBIF_CFG_DEV0_EPF4_1_FLADJ_DEFAULT 0x00000020 |
5419 | #define smnBIF_CFG_DEV0_EPF4_1_DBESL_DBESLD_DEFAULT 0x00000000 |
5420 | #define smnBIF_CFG_DEV0_EPF4_1_PCIE_CAP_LIST_DEFAULT 0x0000a000 |
5421 | #define smnBIF_CFG_DEV0_EPF4_1_PCIE_CAP_DEFAULT 0x00000002 |
5422 | #define smnBIF_CFG_DEV0_EPF4_1_DEVICE_CAP_DEFAULT 0x10000000 |
5423 | #define smnBIF_CFG_DEV0_EPF4_1_DEVICE_CNTL_DEFAULT 0x00002810 |
5424 | #define smnBIF_CFG_DEV0_EPF4_1_DEVICE_STATUS_DEFAULT 0x00000000 |
5425 | #define smnBIF_CFG_DEV0_EPF4_1_LINK_CAP_DEFAULT 0x00011c03 |
5426 | #define smnBIF_CFG_DEV0_EPF4_1_LINK_CNTL_DEFAULT 0x00000000 |
5427 | #define smnBIF_CFG_DEV0_EPF4_1_LINK_STATUS_DEFAULT 0x00000001 |
5428 | #define smnBIF_CFG_DEV0_EPF4_1_DEVICE_CAP2_DEFAULT 0x00000000 |
5429 | #define smnBIF_CFG_DEV0_EPF4_1_DEVICE_CNTL2_DEFAULT 0x00000000 |
5430 | #define smnBIF_CFG_DEV0_EPF4_1_DEVICE_STATUS2_DEFAULT 0x00000000 |
5431 | #define smnBIF_CFG_DEV0_EPF4_1_LINK_CAP2_DEFAULT 0x0000000e |
5432 | #define smnBIF_CFG_DEV0_EPF4_1_LINK_CNTL2_DEFAULT 0x00000003 |
5433 | #define smnBIF_CFG_DEV0_EPF4_1_LINK_STATUS2_DEFAULT 0x00000000 |
5434 | #define smnBIF_CFG_DEV0_EPF4_1_SLOT_CAP2_DEFAULT 0x00000000 |
5435 | #define smnBIF_CFG_DEV0_EPF4_1_SLOT_CNTL2_DEFAULT 0x00000000 |
5436 | #define smnBIF_CFG_DEV0_EPF4_1_SLOT_STATUS2_DEFAULT 0x00000000 |
5437 | #define smnBIF_CFG_DEV0_EPF4_1_MSI_CAP_LIST_DEFAULT 0x0000c000 |
5438 | #define smnBIF_CFG_DEV0_EPF4_1_MSI_MSG_CNTL_DEFAULT 0x00000080 |
5439 | #define smnBIF_CFG_DEV0_EPF4_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 |
5440 | #define smnBIF_CFG_DEV0_EPF4_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 |
5441 | #define smnBIF_CFG_DEV0_EPF4_1_MSI_MSG_DATA_DEFAULT 0x00000000 |
5442 | #define smnBIF_CFG_DEV0_EPF4_1_MSI_MASK_DEFAULT 0x00000000 |
5443 | #define smnBIF_CFG_DEV0_EPF4_1_MSI_MSG_DATA_64_DEFAULT 0x00000000 |
5444 | #define smnBIF_CFG_DEV0_EPF4_1_MSI_MASK_64_DEFAULT 0x00000000 |
5445 | #define smnBIF_CFG_DEV0_EPF4_1_MSI_PENDING_DEFAULT 0x00000000 |
5446 | #define smnBIF_CFG_DEV0_EPF4_1_MSI_PENDING_64_DEFAULT 0x00000000 |
5447 | #define smnBIF_CFG_DEV0_EPF4_1_MSIX_CAP_LIST_DEFAULT 0x00000000 |
5448 | #define smnBIF_CFG_DEV0_EPF4_1_MSIX_MSG_CNTL_DEFAULT 0x00000000 |
5449 | #define smnBIF_CFG_DEV0_EPF4_1_MSIX_TABLE_DEFAULT 0x00000000 |
5450 | #define smnBIF_CFG_DEV0_EPF4_1_MSIX_PBA_DEFAULT 0x00000000 |
5451 | #define smnBIF_CFG_DEV0_EPF4_1_SATA_CAP_0_DEFAULT 0x00000000 |
5452 | #define smnBIF_CFG_DEV0_EPF4_1_SATA_CAP_1_DEFAULT 0x00000000 |
5453 | #define smnBIF_CFG_DEV0_EPF4_1_SATA_IDP_INDEX_DEFAULT 0x00000000 |
5454 | #define smnBIF_CFG_DEV0_EPF4_1_SATA_IDP_DATA_DEFAULT 0x00000000 |
5455 | #define smnBIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 |
5456 | #define smnBIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 |
5457 | #define smnBIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 |
5458 | #define smnBIF_CFG_DEV0_EPF4_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 |
5459 | #define smnBIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 |
5460 | #define smnBIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 |
5461 | #define smnBIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 |
5462 | #define smnBIF_CFG_DEV0_EPF4_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 |
5463 | #define smnBIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 |
5464 | #define smnBIF_CFG_DEV0_EPF4_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000 |
5465 | #define smnBIF_CFG_DEV0_EPF4_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 |
5466 | #define smnBIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG0_DEFAULT 0x00000000 |
5467 | #define smnBIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG1_DEFAULT 0x00000000 |
5468 | #define smnBIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG2_DEFAULT 0x00000000 |
5469 | #define smnBIF_CFG_DEV0_EPF4_1_PCIE_HDR_LOG3_DEFAULT 0x00000000 |
5470 | #define smnBIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 |
5471 | #define smnBIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 |
5472 | #define smnBIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 |
5473 | #define smnBIF_CFG_DEV0_EPF4_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 |
5474 | #define smnBIF_CFG_DEV0_EPF4_1_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000 |
5475 | #define smnBIF_CFG_DEV0_EPF4_1_PCIE_BAR1_CAP_DEFAULT 0x00000000 |
5476 | #define smnBIF_CFG_DEV0_EPF4_1_PCIE_BAR1_CNTL_DEFAULT 0x00000020 |
5477 | #define smnBIF_CFG_DEV0_EPF4_1_PCIE_BAR2_CAP_DEFAULT 0x00000000 |
5478 | #define smnBIF_CFG_DEV0_EPF4_1_PCIE_BAR2_CNTL_DEFAULT 0x00000000 |
5479 | #define smnBIF_CFG_DEV0_EPF4_1_PCIE_BAR3_CAP_DEFAULT 0x00000000 |
5480 | #define smnBIF_CFG_DEV0_EPF4_1_PCIE_BAR3_CNTL_DEFAULT 0x00000000 |
5481 | #define smnBIF_CFG_DEV0_EPF4_1_PCIE_BAR4_CAP_DEFAULT 0x00000000 |
5482 | #define smnBIF_CFG_DEV0_EPF4_1_PCIE_BAR4_CNTL_DEFAULT 0x00000000 |
5483 | #define smnBIF_CFG_DEV0_EPF4_1_PCIE_BAR5_CAP_DEFAULT 0x00000000 |
5484 | #define smnBIF_CFG_DEV0_EPF4_1_PCIE_BAR5_CNTL_DEFAULT 0x00000000 |
5485 | #define smnBIF_CFG_DEV0_EPF4_1_PCIE_BAR6_CAP_DEFAULT 0x00000000 |
5486 | #define smnBIF_CFG_DEV0_EPF4_1_PCIE_BAR6_CNTL_DEFAULT 0x00000000 |
5487 | #define smnBIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000 |
5488 | #define smnBIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000 |
5489 | #define smnBIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000 |
5490 | #define smnBIF_CFG_DEV0_EPF4_1_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000 |
5491 | #define smnBIF_CFG_DEV0_EPF4_1_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000 |
5492 | #define smnBIF_CFG_DEV0_EPF4_1_PCIE_DPA_CAP_DEFAULT 0x00000000 |
5493 | #define smnBIF_CFG_DEV0_EPF4_1_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000 |
5494 | #define smnBIF_CFG_DEV0_EPF4_1_PCIE_DPA_STATUS_DEFAULT 0x00000100 |
5495 | #define smnBIF_CFG_DEV0_EPF4_1_PCIE_DPA_CNTL_DEFAULT 0x00000000 |
5496 | #define smnBIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000 |
5497 | #define smnBIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000 |
5498 | #define smnBIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000 |
5499 | #define smnBIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000 |
5500 | #define smnBIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000 |
5501 | #define smnBIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000 |
5502 | #define smnBIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000 |
5503 | #define smnBIF_CFG_DEV0_EPF4_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000 |
5504 | #define smnBIF_CFG_DEV0_EPF4_1_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000 |
5505 | #define smnBIF_CFG_DEV0_EPF4_1_PCIE_ACS_CAP_DEFAULT 0x00000000 |
5506 | #define smnBIF_CFG_DEV0_EPF4_1_PCIE_ACS_CNTL_DEFAULT 0x00000000 |
5507 | #define smnBIF_CFG_DEV0_EPF4_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000 |
5508 | #define smnBIF_CFG_DEV0_EPF4_1_PCIE_ARI_CAP_DEFAULT 0x00000000 |
5509 | #define smnBIF_CFG_DEV0_EPF4_1_PCIE_ARI_CNTL_DEFAULT 0x00000000 |
5510 | |
5511 | |
5512 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf5_bifcfgdecp |
5513 | #define smnBIF_CFG_DEV0_EPF5_1_VENDOR_ID_DEFAULT 0x00000000 |
5514 | #define smnBIF_CFG_DEV0_EPF5_1_DEVICE_ID_DEFAULT 0x00000000 |
5515 | #define smnBIF_CFG_DEV0_EPF5_1_COMMAND_DEFAULT 0x00000000 |
5516 | #define smnBIF_CFG_DEV0_EPF5_1_STATUS_DEFAULT 0x00000000 |
5517 | #define smnBIF_CFG_DEV0_EPF5_1_REVISION_ID_DEFAULT 0x00000000 |
5518 | #define smnBIF_CFG_DEV0_EPF5_1_PROG_INTERFACE_DEFAULT 0x00000000 |
5519 | #define smnBIF_CFG_DEV0_EPF5_1_SUB_CLASS_DEFAULT 0x00000000 |
5520 | #define smnBIF_CFG_DEV0_EPF5_1_BASE_CLASS_DEFAULT 0x00000000 |
5521 | #define smnBIF_CFG_DEV0_EPF5_1_CACHE_LINE_DEFAULT 0x00000000 |
5522 | #define smnBIF_CFG_DEV0_EPF5_1_LATENCY_DEFAULT 0x00000000 |
5523 | #define 0x00000000 |
5524 | #define smnBIF_CFG_DEV0_EPF5_1_BIST_DEFAULT 0x00000000 |
5525 | #define smnBIF_CFG_DEV0_EPF5_1_BASE_ADDR_1_DEFAULT 0x00000000 |
5526 | #define smnBIF_CFG_DEV0_EPF5_1_BASE_ADDR_2_DEFAULT 0x00000000 |
5527 | #define smnBIF_CFG_DEV0_EPF5_1_BASE_ADDR_3_DEFAULT 0x00000000 |
5528 | #define smnBIF_CFG_DEV0_EPF5_1_BASE_ADDR_4_DEFAULT 0x00000000 |
5529 | #define smnBIF_CFG_DEV0_EPF5_1_BASE_ADDR_5_DEFAULT 0x00000000 |
5530 | #define smnBIF_CFG_DEV0_EPF5_1_BASE_ADDR_6_DEFAULT 0x00000000 |
5531 | #define smnBIF_CFG_DEV0_EPF5_1_ADAPTER_ID_DEFAULT 0x00000000 |
5532 | #define smnBIF_CFG_DEV0_EPF5_1_ROM_BASE_ADDR_DEFAULT 0x00000000 |
5533 | #define smnBIF_CFG_DEV0_EPF5_1_CAP_PTR_DEFAULT 0x00000000 |
5534 | #define smnBIF_CFG_DEV0_EPF5_1_INTERRUPT_LINE_DEFAULT 0x00000000 |
5535 | #define smnBIF_CFG_DEV0_EPF5_1_INTERRUPT_PIN_DEFAULT 0x00000000 |
5536 | #define smnBIF_CFG_DEV0_EPF5_1_MIN_GRANT_DEFAULT 0x00000000 |
5537 | #define smnBIF_CFG_DEV0_EPF5_1_MAX_LATENCY_DEFAULT 0x00000000 |
5538 | #define smnBIF_CFG_DEV0_EPF5_1_VENDOR_CAP_LIST_DEFAULT 0x00000000 |
5539 | #define smnBIF_CFG_DEV0_EPF5_1_ADAPTER_ID_W_DEFAULT 0x00000000 |
5540 | #define smnBIF_CFG_DEV0_EPF5_1_PMI_CAP_LIST_DEFAULT 0x00000000 |
5541 | #define smnBIF_CFG_DEV0_EPF5_1_PMI_CAP_DEFAULT 0x00000000 |
5542 | #define smnBIF_CFG_DEV0_EPF5_1_PMI_STATUS_CNTL_DEFAULT 0x00000000 |
5543 | #define smnBIF_CFG_DEV0_EPF5_1_SBRN_DEFAULT 0x00000000 |
5544 | #define smnBIF_CFG_DEV0_EPF5_1_FLADJ_DEFAULT 0x00000020 |
5545 | #define smnBIF_CFG_DEV0_EPF5_1_DBESL_DBESLD_DEFAULT 0x00000000 |
5546 | #define smnBIF_CFG_DEV0_EPF5_1_PCIE_CAP_LIST_DEFAULT 0x0000a000 |
5547 | #define smnBIF_CFG_DEV0_EPF5_1_PCIE_CAP_DEFAULT 0x00000002 |
5548 | #define smnBIF_CFG_DEV0_EPF5_1_DEVICE_CAP_DEFAULT 0x10000000 |
5549 | #define smnBIF_CFG_DEV0_EPF5_1_DEVICE_CNTL_DEFAULT 0x00002810 |
5550 | #define smnBIF_CFG_DEV0_EPF5_1_DEVICE_STATUS_DEFAULT 0x00000000 |
5551 | #define smnBIF_CFG_DEV0_EPF5_1_LINK_CAP_DEFAULT 0x00011c03 |
5552 | #define smnBIF_CFG_DEV0_EPF5_1_LINK_CNTL_DEFAULT 0x00000000 |
5553 | #define smnBIF_CFG_DEV0_EPF5_1_LINK_STATUS_DEFAULT 0x00000001 |
5554 | #define smnBIF_CFG_DEV0_EPF5_1_DEVICE_CAP2_DEFAULT 0x00000000 |
5555 | #define smnBIF_CFG_DEV0_EPF5_1_DEVICE_CNTL2_DEFAULT 0x00000000 |
5556 | #define smnBIF_CFG_DEV0_EPF5_1_DEVICE_STATUS2_DEFAULT 0x00000000 |
5557 | #define smnBIF_CFG_DEV0_EPF5_1_LINK_CAP2_DEFAULT 0x0000000e |
5558 | #define smnBIF_CFG_DEV0_EPF5_1_LINK_CNTL2_DEFAULT 0x00000003 |
5559 | #define smnBIF_CFG_DEV0_EPF5_1_LINK_STATUS2_DEFAULT 0x00000000 |
5560 | #define smnBIF_CFG_DEV0_EPF5_1_SLOT_CAP2_DEFAULT 0x00000000 |
5561 | #define smnBIF_CFG_DEV0_EPF5_1_SLOT_CNTL2_DEFAULT 0x00000000 |
5562 | #define smnBIF_CFG_DEV0_EPF5_1_SLOT_STATUS2_DEFAULT 0x00000000 |
5563 | #define smnBIF_CFG_DEV0_EPF5_1_MSI_CAP_LIST_DEFAULT 0x0000c000 |
5564 | #define smnBIF_CFG_DEV0_EPF5_1_MSI_MSG_CNTL_DEFAULT 0x00000080 |
5565 | #define smnBIF_CFG_DEV0_EPF5_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 |
5566 | #define smnBIF_CFG_DEV0_EPF5_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 |
5567 | #define smnBIF_CFG_DEV0_EPF5_1_MSI_MSG_DATA_DEFAULT 0x00000000 |
5568 | #define smnBIF_CFG_DEV0_EPF5_1_MSI_MASK_DEFAULT 0x00000000 |
5569 | #define smnBIF_CFG_DEV0_EPF5_1_MSI_MSG_DATA_64_DEFAULT 0x00000000 |
5570 | #define smnBIF_CFG_DEV0_EPF5_1_MSI_MASK_64_DEFAULT 0x00000000 |
5571 | #define smnBIF_CFG_DEV0_EPF5_1_MSI_PENDING_DEFAULT 0x00000000 |
5572 | #define smnBIF_CFG_DEV0_EPF5_1_MSI_PENDING_64_DEFAULT 0x00000000 |
5573 | #define smnBIF_CFG_DEV0_EPF5_1_MSIX_CAP_LIST_DEFAULT 0x00000000 |
5574 | #define smnBIF_CFG_DEV0_EPF5_1_MSIX_MSG_CNTL_DEFAULT 0x00000000 |
5575 | #define smnBIF_CFG_DEV0_EPF5_1_MSIX_TABLE_DEFAULT 0x00000000 |
5576 | #define smnBIF_CFG_DEV0_EPF5_1_MSIX_PBA_DEFAULT 0x00000000 |
5577 | #define smnBIF_CFG_DEV0_EPF5_1_SATA_CAP_0_DEFAULT 0x00000000 |
5578 | #define smnBIF_CFG_DEV0_EPF5_1_SATA_CAP_1_DEFAULT 0x00000000 |
5579 | #define smnBIF_CFG_DEV0_EPF5_1_SATA_IDP_INDEX_DEFAULT 0x00000000 |
5580 | #define smnBIF_CFG_DEV0_EPF5_1_SATA_IDP_DATA_DEFAULT 0x00000000 |
5581 | #define smnBIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 |
5582 | #define smnBIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 |
5583 | #define smnBIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 |
5584 | #define smnBIF_CFG_DEV0_EPF5_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 |
5585 | #define smnBIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 |
5586 | #define smnBIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 |
5587 | #define smnBIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 |
5588 | #define smnBIF_CFG_DEV0_EPF5_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 |
5589 | #define smnBIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 |
5590 | #define smnBIF_CFG_DEV0_EPF5_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000 |
5591 | #define smnBIF_CFG_DEV0_EPF5_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 |
5592 | #define smnBIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG0_DEFAULT 0x00000000 |
5593 | #define smnBIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG1_DEFAULT 0x00000000 |
5594 | #define smnBIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG2_DEFAULT 0x00000000 |
5595 | #define smnBIF_CFG_DEV0_EPF5_1_PCIE_HDR_LOG3_DEFAULT 0x00000000 |
5596 | #define smnBIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 |
5597 | #define smnBIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 |
5598 | #define smnBIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 |
5599 | #define smnBIF_CFG_DEV0_EPF5_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 |
5600 | #define smnBIF_CFG_DEV0_EPF5_1_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000 |
5601 | #define smnBIF_CFG_DEV0_EPF5_1_PCIE_BAR1_CAP_DEFAULT 0x00000000 |
5602 | #define smnBIF_CFG_DEV0_EPF5_1_PCIE_BAR1_CNTL_DEFAULT 0x00000020 |
5603 | #define smnBIF_CFG_DEV0_EPF5_1_PCIE_BAR2_CAP_DEFAULT 0x00000000 |
5604 | #define smnBIF_CFG_DEV0_EPF5_1_PCIE_BAR2_CNTL_DEFAULT 0x00000000 |
5605 | #define smnBIF_CFG_DEV0_EPF5_1_PCIE_BAR3_CAP_DEFAULT 0x00000000 |
5606 | #define smnBIF_CFG_DEV0_EPF5_1_PCIE_BAR3_CNTL_DEFAULT 0x00000000 |
5607 | #define smnBIF_CFG_DEV0_EPF5_1_PCIE_BAR4_CAP_DEFAULT 0x00000000 |
5608 | #define smnBIF_CFG_DEV0_EPF5_1_PCIE_BAR4_CNTL_DEFAULT 0x00000000 |
5609 | #define smnBIF_CFG_DEV0_EPF5_1_PCIE_BAR5_CAP_DEFAULT 0x00000000 |
5610 | #define smnBIF_CFG_DEV0_EPF5_1_PCIE_BAR5_CNTL_DEFAULT 0x00000000 |
5611 | #define smnBIF_CFG_DEV0_EPF5_1_PCIE_BAR6_CAP_DEFAULT 0x00000000 |
5612 | #define smnBIF_CFG_DEV0_EPF5_1_PCIE_BAR6_CNTL_DEFAULT 0x00000000 |
5613 | #define smnBIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000 |
5614 | #define smnBIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000 |
5615 | #define smnBIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000 |
5616 | #define smnBIF_CFG_DEV0_EPF5_1_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000 |
5617 | #define smnBIF_CFG_DEV0_EPF5_1_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000 |
5618 | #define smnBIF_CFG_DEV0_EPF5_1_PCIE_DPA_CAP_DEFAULT 0x00000000 |
5619 | #define smnBIF_CFG_DEV0_EPF5_1_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000 |
5620 | #define smnBIF_CFG_DEV0_EPF5_1_PCIE_DPA_STATUS_DEFAULT 0x00000100 |
5621 | #define smnBIF_CFG_DEV0_EPF5_1_PCIE_DPA_CNTL_DEFAULT 0x00000000 |
5622 | #define smnBIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000 |
5623 | #define smnBIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000 |
5624 | #define smnBIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000 |
5625 | #define smnBIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000 |
5626 | #define smnBIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000 |
5627 | #define smnBIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000 |
5628 | #define smnBIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000 |
5629 | #define smnBIF_CFG_DEV0_EPF5_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000 |
5630 | #define smnBIF_CFG_DEV0_EPF5_1_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000 |
5631 | #define smnBIF_CFG_DEV0_EPF5_1_PCIE_ACS_CAP_DEFAULT 0x00000000 |
5632 | #define smnBIF_CFG_DEV0_EPF5_1_PCIE_ACS_CNTL_DEFAULT 0x00000000 |
5633 | #define smnBIF_CFG_DEV0_EPF5_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000 |
5634 | #define smnBIF_CFG_DEV0_EPF5_1_PCIE_ARI_CAP_DEFAULT 0x00000000 |
5635 | #define smnBIF_CFG_DEV0_EPF5_1_PCIE_ARI_CNTL_DEFAULT 0x00000000 |
5636 | |
5637 | |
5638 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf6_bifcfgdecp |
5639 | #define smnBIF_CFG_DEV0_EPF6_1_VENDOR_ID_DEFAULT 0x00000000 |
5640 | #define smnBIF_CFG_DEV0_EPF6_1_DEVICE_ID_DEFAULT 0x00000000 |
5641 | #define smnBIF_CFG_DEV0_EPF6_1_COMMAND_DEFAULT 0x00000000 |
5642 | #define smnBIF_CFG_DEV0_EPF6_1_STATUS_DEFAULT 0x00000000 |
5643 | #define smnBIF_CFG_DEV0_EPF6_1_REVISION_ID_DEFAULT 0x00000000 |
5644 | #define smnBIF_CFG_DEV0_EPF6_1_PROG_INTERFACE_DEFAULT 0x00000000 |
5645 | #define smnBIF_CFG_DEV0_EPF6_1_SUB_CLASS_DEFAULT 0x00000000 |
5646 | #define smnBIF_CFG_DEV0_EPF6_1_BASE_CLASS_DEFAULT 0x00000000 |
5647 | #define smnBIF_CFG_DEV0_EPF6_1_CACHE_LINE_DEFAULT 0x00000000 |
5648 | #define smnBIF_CFG_DEV0_EPF6_1_LATENCY_DEFAULT 0x00000000 |
5649 | #define 0x00000000 |
5650 | #define smnBIF_CFG_DEV0_EPF6_1_BIST_DEFAULT 0x00000000 |
5651 | #define smnBIF_CFG_DEV0_EPF6_1_BASE_ADDR_1_DEFAULT 0x00000000 |
5652 | #define smnBIF_CFG_DEV0_EPF6_1_BASE_ADDR_2_DEFAULT 0x00000000 |
5653 | #define smnBIF_CFG_DEV0_EPF6_1_BASE_ADDR_3_DEFAULT 0x00000000 |
5654 | #define smnBIF_CFG_DEV0_EPF6_1_BASE_ADDR_4_DEFAULT 0x00000000 |
5655 | #define smnBIF_CFG_DEV0_EPF6_1_BASE_ADDR_5_DEFAULT 0x00000000 |
5656 | #define smnBIF_CFG_DEV0_EPF6_1_BASE_ADDR_6_DEFAULT 0x00000000 |
5657 | #define smnBIF_CFG_DEV0_EPF6_1_ADAPTER_ID_DEFAULT 0x00000000 |
5658 | #define smnBIF_CFG_DEV0_EPF6_1_ROM_BASE_ADDR_DEFAULT 0x00000000 |
5659 | #define smnBIF_CFG_DEV0_EPF6_1_CAP_PTR_DEFAULT 0x00000000 |
5660 | #define smnBIF_CFG_DEV0_EPF6_1_INTERRUPT_LINE_DEFAULT 0x00000000 |
5661 | #define smnBIF_CFG_DEV0_EPF6_1_INTERRUPT_PIN_DEFAULT 0x00000000 |
5662 | #define smnBIF_CFG_DEV0_EPF6_1_MIN_GRANT_DEFAULT 0x00000000 |
5663 | #define smnBIF_CFG_DEV0_EPF6_1_MAX_LATENCY_DEFAULT 0x00000000 |
5664 | #define smnBIF_CFG_DEV0_EPF6_1_VENDOR_CAP_LIST_DEFAULT 0x00000000 |
5665 | #define smnBIF_CFG_DEV0_EPF6_1_ADAPTER_ID_W_DEFAULT 0x00000000 |
5666 | #define smnBIF_CFG_DEV0_EPF6_1_PMI_CAP_LIST_DEFAULT 0x00000000 |
5667 | #define smnBIF_CFG_DEV0_EPF6_1_PMI_CAP_DEFAULT 0x00000000 |
5668 | #define smnBIF_CFG_DEV0_EPF6_1_PMI_STATUS_CNTL_DEFAULT 0x00000000 |
5669 | #define smnBIF_CFG_DEV0_EPF6_1_SBRN_DEFAULT 0x00000000 |
5670 | #define smnBIF_CFG_DEV0_EPF6_1_FLADJ_DEFAULT 0x00000020 |
5671 | #define smnBIF_CFG_DEV0_EPF6_1_DBESL_DBESLD_DEFAULT 0x00000000 |
5672 | #define smnBIF_CFG_DEV0_EPF6_1_PCIE_CAP_LIST_DEFAULT 0x0000a000 |
5673 | #define smnBIF_CFG_DEV0_EPF6_1_PCIE_CAP_DEFAULT 0x00000002 |
5674 | #define smnBIF_CFG_DEV0_EPF6_1_DEVICE_CAP_DEFAULT 0x10000000 |
5675 | #define smnBIF_CFG_DEV0_EPF6_1_DEVICE_CNTL_DEFAULT 0x00002810 |
5676 | #define smnBIF_CFG_DEV0_EPF6_1_DEVICE_STATUS_DEFAULT 0x00000000 |
5677 | #define smnBIF_CFG_DEV0_EPF6_1_LINK_CAP_DEFAULT 0x00011c03 |
5678 | #define smnBIF_CFG_DEV0_EPF6_1_LINK_CNTL_DEFAULT 0x00000000 |
5679 | #define smnBIF_CFG_DEV0_EPF6_1_LINK_STATUS_DEFAULT 0x00000001 |
5680 | #define smnBIF_CFG_DEV0_EPF6_1_DEVICE_CAP2_DEFAULT 0x00000000 |
5681 | #define smnBIF_CFG_DEV0_EPF6_1_DEVICE_CNTL2_DEFAULT 0x00000000 |
5682 | #define smnBIF_CFG_DEV0_EPF6_1_DEVICE_STATUS2_DEFAULT 0x00000000 |
5683 | #define smnBIF_CFG_DEV0_EPF6_1_LINK_CAP2_DEFAULT 0x0000000e |
5684 | #define smnBIF_CFG_DEV0_EPF6_1_LINK_CNTL2_DEFAULT 0x00000003 |
5685 | #define smnBIF_CFG_DEV0_EPF6_1_LINK_STATUS2_DEFAULT 0x00000000 |
5686 | #define smnBIF_CFG_DEV0_EPF6_1_SLOT_CAP2_DEFAULT 0x00000000 |
5687 | #define smnBIF_CFG_DEV0_EPF6_1_SLOT_CNTL2_DEFAULT 0x00000000 |
5688 | #define smnBIF_CFG_DEV0_EPF6_1_SLOT_STATUS2_DEFAULT 0x00000000 |
5689 | #define smnBIF_CFG_DEV0_EPF6_1_MSI_CAP_LIST_DEFAULT 0x0000c000 |
5690 | #define smnBIF_CFG_DEV0_EPF6_1_MSI_MSG_CNTL_DEFAULT 0x00000080 |
5691 | #define smnBIF_CFG_DEV0_EPF6_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 |
5692 | #define smnBIF_CFG_DEV0_EPF6_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 |
5693 | #define smnBIF_CFG_DEV0_EPF6_1_MSI_MSG_DATA_DEFAULT 0x00000000 |
5694 | #define smnBIF_CFG_DEV0_EPF6_1_MSI_MASK_DEFAULT 0x00000000 |
5695 | #define smnBIF_CFG_DEV0_EPF6_1_MSI_MSG_DATA_64_DEFAULT 0x00000000 |
5696 | #define smnBIF_CFG_DEV0_EPF6_1_MSI_MASK_64_DEFAULT 0x00000000 |
5697 | #define smnBIF_CFG_DEV0_EPF6_1_MSI_PENDING_DEFAULT 0x00000000 |
5698 | #define smnBIF_CFG_DEV0_EPF6_1_MSI_PENDING_64_DEFAULT 0x00000000 |
5699 | #define smnBIF_CFG_DEV0_EPF6_1_MSIX_CAP_LIST_DEFAULT 0x00000000 |
5700 | #define smnBIF_CFG_DEV0_EPF6_1_MSIX_MSG_CNTL_DEFAULT 0x00000000 |
5701 | #define smnBIF_CFG_DEV0_EPF6_1_MSIX_TABLE_DEFAULT 0x00000000 |
5702 | #define smnBIF_CFG_DEV0_EPF6_1_MSIX_PBA_DEFAULT 0x00000000 |
5703 | #define smnBIF_CFG_DEV0_EPF6_1_SATA_CAP_0_DEFAULT 0x00000000 |
5704 | #define smnBIF_CFG_DEV0_EPF6_1_SATA_CAP_1_DEFAULT 0x00000000 |
5705 | #define smnBIF_CFG_DEV0_EPF6_1_SATA_IDP_INDEX_DEFAULT 0x00000000 |
5706 | #define smnBIF_CFG_DEV0_EPF6_1_SATA_IDP_DATA_DEFAULT 0x00000000 |
5707 | #define smnBIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 |
5708 | #define smnBIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 |
5709 | #define smnBIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 |
5710 | #define smnBIF_CFG_DEV0_EPF6_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 |
5711 | #define smnBIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 |
5712 | #define smnBIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 |
5713 | #define smnBIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 |
5714 | #define smnBIF_CFG_DEV0_EPF6_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 |
5715 | #define smnBIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 |
5716 | #define smnBIF_CFG_DEV0_EPF6_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000 |
5717 | #define smnBIF_CFG_DEV0_EPF6_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 |
5718 | #define smnBIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG0_DEFAULT 0x00000000 |
5719 | #define smnBIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG1_DEFAULT 0x00000000 |
5720 | #define smnBIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG2_DEFAULT 0x00000000 |
5721 | #define smnBIF_CFG_DEV0_EPF6_1_PCIE_HDR_LOG3_DEFAULT 0x00000000 |
5722 | #define smnBIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 |
5723 | #define smnBIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 |
5724 | #define smnBIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 |
5725 | #define smnBIF_CFG_DEV0_EPF6_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 |
5726 | #define smnBIF_CFG_DEV0_EPF6_1_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000 |
5727 | #define smnBIF_CFG_DEV0_EPF6_1_PCIE_BAR1_CAP_DEFAULT 0x00000000 |
5728 | #define smnBIF_CFG_DEV0_EPF6_1_PCIE_BAR1_CNTL_DEFAULT 0x00000020 |
5729 | #define smnBIF_CFG_DEV0_EPF6_1_PCIE_BAR2_CAP_DEFAULT 0x00000000 |
5730 | #define smnBIF_CFG_DEV0_EPF6_1_PCIE_BAR2_CNTL_DEFAULT 0x00000000 |
5731 | #define smnBIF_CFG_DEV0_EPF6_1_PCIE_BAR3_CAP_DEFAULT 0x00000000 |
5732 | #define smnBIF_CFG_DEV0_EPF6_1_PCIE_BAR3_CNTL_DEFAULT 0x00000000 |
5733 | #define smnBIF_CFG_DEV0_EPF6_1_PCIE_BAR4_CAP_DEFAULT 0x00000000 |
5734 | #define smnBIF_CFG_DEV0_EPF6_1_PCIE_BAR4_CNTL_DEFAULT 0x00000000 |
5735 | #define smnBIF_CFG_DEV0_EPF6_1_PCIE_BAR5_CAP_DEFAULT 0x00000000 |
5736 | #define smnBIF_CFG_DEV0_EPF6_1_PCIE_BAR5_CNTL_DEFAULT 0x00000000 |
5737 | #define smnBIF_CFG_DEV0_EPF6_1_PCIE_BAR6_CAP_DEFAULT 0x00000000 |
5738 | #define smnBIF_CFG_DEV0_EPF6_1_PCIE_BAR6_CNTL_DEFAULT 0x00000000 |
5739 | #define smnBIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000 |
5740 | #define smnBIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000 |
5741 | #define smnBIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000 |
5742 | #define smnBIF_CFG_DEV0_EPF6_1_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000 |
5743 | #define smnBIF_CFG_DEV0_EPF6_1_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000 |
5744 | #define smnBIF_CFG_DEV0_EPF6_1_PCIE_DPA_CAP_DEFAULT 0x00000000 |
5745 | #define smnBIF_CFG_DEV0_EPF6_1_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000 |
5746 | #define smnBIF_CFG_DEV0_EPF6_1_PCIE_DPA_STATUS_DEFAULT 0x00000100 |
5747 | #define smnBIF_CFG_DEV0_EPF6_1_PCIE_DPA_CNTL_DEFAULT 0x00000000 |
5748 | #define smnBIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000 |
5749 | #define smnBIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000 |
5750 | #define smnBIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000 |
5751 | #define smnBIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000 |
5752 | #define smnBIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000 |
5753 | #define smnBIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000 |
5754 | #define smnBIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000 |
5755 | #define smnBIF_CFG_DEV0_EPF6_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000 |
5756 | #define smnBIF_CFG_DEV0_EPF6_1_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000 |
5757 | #define smnBIF_CFG_DEV0_EPF6_1_PCIE_ACS_CAP_DEFAULT 0x00000000 |
5758 | #define smnBIF_CFG_DEV0_EPF6_1_PCIE_ACS_CNTL_DEFAULT 0x00000000 |
5759 | #define smnBIF_CFG_DEV0_EPF6_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000 |
5760 | #define smnBIF_CFG_DEV0_EPF6_1_PCIE_ARI_CAP_DEFAULT 0x00000000 |
5761 | #define smnBIF_CFG_DEV0_EPF6_1_PCIE_ARI_CNTL_DEFAULT 0x00000000 |
5762 | |
5763 | |
5764 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf7_bifcfgdecp |
5765 | #define smnBIF_CFG_DEV0_EPF7_1_VENDOR_ID_DEFAULT 0x00000000 |
5766 | #define smnBIF_CFG_DEV0_EPF7_1_DEVICE_ID_DEFAULT 0x00000000 |
5767 | #define smnBIF_CFG_DEV0_EPF7_1_COMMAND_DEFAULT 0x00000000 |
5768 | #define smnBIF_CFG_DEV0_EPF7_1_STATUS_DEFAULT 0x00000000 |
5769 | #define smnBIF_CFG_DEV0_EPF7_1_REVISION_ID_DEFAULT 0x00000000 |
5770 | #define smnBIF_CFG_DEV0_EPF7_1_PROG_INTERFACE_DEFAULT 0x00000000 |
5771 | #define smnBIF_CFG_DEV0_EPF7_1_SUB_CLASS_DEFAULT 0x00000000 |
5772 | #define smnBIF_CFG_DEV0_EPF7_1_BASE_CLASS_DEFAULT 0x00000000 |
5773 | #define smnBIF_CFG_DEV0_EPF7_1_CACHE_LINE_DEFAULT 0x00000000 |
5774 | #define smnBIF_CFG_DEV0_EPF7_1_LATENCY_DEFAULT 0x00000000 |
5775 | #define 0x00000000 |
5776 | #define smnBIF_CFG_DEV0_EPF7_1_BIST_DEFAULT 0x00000000 |
5777 | #define smnBIF_CFG_DEV0_EPF7_1_BASE_ADDR_1_DEFAULT 0x00000000 |
5778 | #define smnBIF_CFG_DEV0_EPF7_1_BASE_ADDR_2_DEFAULT 0x00000000 |
5779 | #define smnBIF_CFG_DEV0_EPF7_1_BASE_ADDR_3_DEFAULT 0x00000000 |
5780 | #define smnBIF_CFG_DEV0_EPF7_1_BASE_ADDR_4_DEFAULT 0x00000000 |
5781 | #define smnBIF_CFG_DEV0_EPF7_1_BASE_ADDR_5_DEFAULT 0x00000000 |
5782 | #define smnBIF_CFG_DEV0_EPF7_1_BASE_ADDR_6_DEFAULT 0x00000000 |
5783 | #define smnBIF_CFG_DEV0_EPF7_1_ADAPTER_ID_DEFAULT 0x00000000 |
5784 | #define smnBIF_CFG_DEV0_EPF7_1_ROM_BASE_ADDR_DEFAULT 0x00000000 |
5785 | #define smnBIF_CFG_DEV0_EPF7_1_CAP_PTR_DEFAULT 0x00000000 |
5786 | #define smnBIF_CFG_DEV0_EPF7_1_INTERRUPT_LINE_DEFAULT 0x00000000 |
5787 | #define smnBIF_CFG_DEV0_EPF7_1_INTERRUPT_PIN_DEFAULT 0x00000000 |
5788 | #define smnBIF_CFG_DEV0_EPF7_1_MIN_GRANT_DEFAULT 0x00000000 |
5789 | #define smnBIF_CFG_DEV0_EPF7_1_MAX_LATENCY_DEFAULT 0x00000000 |
5790 | #define smnBIF_CFG_DEV0_EPF7_1_VENDOR_CAP_LIST_DEFAULT 0x00000000 |
5791 | #define smnBIF_CFG_DEV0_EPF7_1_ADAPTER_ID_W_DEFAULT 0x00000000 |
5792 | #define smnBIF_CFG_DEV0_EPF7_1_PMI_CAP_LIST_DEFAULT 0x00000000 |
5793 | #define smnBIF_CFG_DEV0_EPF7_1_PMI_CAP_DEFAULT 0x00000000 |
5794 | #define smnBIF_CFG_DEV0_EPF7_1_PMI_STATUS_CNTL_DEFAULT 0x00000000 |
5795 | #define smnBIF_CFG_DEV0_EPF7_1_SBRN_DEFAULT 0x00000000 |
5796 | #define smnBIF_CFG_DEV0_EPF7_1_FLADJ_DEFAULT 0x00000020 |
5797 | #define smnBIF_CFG_DEV0_EPF7_1_DBESL_DBESLD_DEFAULT 0x00000000 |
5798 | #define smnBIF_CFG_DEV0_EPF7_1_PCIE_CAP_LIST_DEFAULT 0x0000a000 |
5799 | #define smnBIF_CFG_DEV0_EPF7_1_PCIE_CAP_DEFAULT 0x00000002 |
5800 | #define smnBIF_CFG_DEV0_EPF7_1_DEVICE_CAP_DEFAULT 0x10000000 |
5801 | #define smnBIF_CFG_DEV0_EPF7_1_DEVICE_CNTL_DEFAULT 0x00002810 |
5802 | #define smnBIF_CFG_DEV0_EPF7_1_DEVICE_STATUS_DEFAULT 0x00000000 |
5803 | #define smnBIF_CFG_DEV0_EPF7_1_LINK_CAP_DEFAULT 0x00011c03 |
5804 | #define smnBIF_CFG_DEV0_EPF7_1_LINK_CNTL_DEFAULT 0x00000000 |
5805 | #define smnBIF_CFG_DEV0_EPF7_1_LINK_STATUS_DEFAULT 0x00000001 |
5806 | #define smnBIF_CFG_DEV0_EPF7_1_DEVICE_CAP2_DEFAULT 0x00000000 |
5807 | #define smnBIF_CFG_DEV0_EPF7_1_DEVICE_CNTL2_DEFAULT 0x00000000 |
5808 | #define smnBIF_CFG_DEV0_EPF7_1_DEVICE_STATUS2_DEFAULT 0x00000000 |
5809 | #define smnBIF_CFG_DEV0_EPF7_1_LINK_CAP2_DEFAULT 0x0000000e |
5810 | #define smnBIF_CFG_DEV0_EPF7_1_LINK_CNTL2_DEFAULT 0x00000003 |
5811 | #define smnBIF_CFG_DEV0_EPF7_1_LINK_STATUS2_DEFAULT 0x00000000 |
5812 | #define smnBIF_CFG_DEV0_EPF7_1_SLOT_CAP2_DEFAULT 0x00000000 |
5813 | #define smnBIF_CFG_DEV0_EPF7_1_SLOT_CNTL2_DEFAULT 0x00000000 |
5814 | #define smnBIF_CFG_DEV0_EPF7_1_SLOT_STATUS2_DEFAULT 0x00000000 |
5815 | #define smnBIF_CFG_DEV0_EPF7_1_MSI_CAP_LIST_DEFAULT 0x0000c000 |
5816 | #define smnBIF_CFG_DEV0_EPF7_1_MSI_MSG_CNTL_DEFAULT 0x00000080 |
5817 | #define smnBIF_CFG_DEV0_EPF7_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 |
5818 | #define smnBIF_CFG_DEV0_EPF7_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 |
5819 | #define smnBIF_CFG_DEV0_EPF7_1_MSI_MSG_DATA_DEFAULT 0x00000000 |
5820 | #define smnBIF_CFG_DEV0_EPF7_1_MSI_MASK_DEFAULT 0x00000000 |
5821 | #define smnBIF_CFG_DEV0_EPF7_1_MSI_MSG_DATA_64_DEFAULT 0x00000000 |
5822 | #define smnBIF_CFG_DEV0_EPF7_1_MSI_MASK_64_DEFAULT 0x00000000 |
5823 | #define smnBIF_CFG_DEV0_EPF7_1_MSI_PENDING_DEFAULT 0x00000000 |
5824 | #define smnBIF_CFG_DEV0_EPF7_1_MSI_PENDING_64_DEFAULT 0x00000000 |
5825 | #define smnBIF_CFG_DEV0_EPF7_1_MSIX_CAP_LIST_DEFAULT 0x00000000 |
5826 | #define smnBIF_CFG_DEV0_EPF7_1_MSIX_MSG_CNTL_DEFAULT 0x00000000 |
5827 | #define smnBIF_CFG_DEV0_EPF7_1_MSIX_TABLE_DEFAULT 0x00000000 |
5828 | #define smnBIF_CFG_DEV0_EPF7_1_MSIX_PBA_DEFAULT 0x00000000 |
5829 | #define smnBIF_CFG_DEV0_EPF7_1_SATA_CAP_0_DEFAULT 0x00000000 |
5830 | #define smnBIF_CFG_DEV0_EPF7_1_SATA_CAP_1_DEFAULT 0x00000000 |
5831 | #define smnBIF_CFG_DEV0_EPF7_1_SATA_IDP_INDEX_DEFAULT 0x00000000 |
5832 | #define smnBIF_CFG_DEV0_EPF7_1_SATA_IDP_DATA_DEFAULT 0x00000000 |
5833 | #define smnBIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 |
5834 | #define smnBIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 |
5835 | #define smnBIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 |
5836 | #define smnBIF_CFG_DEV0_EPF7_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 |
5837 | #define smnBIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 |
5838 | #define smnBIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 |
5839 | #define smnBIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 |
5840 | #define smnBIF_CFG_DEV0_EPF7_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 |
5841 | #define smnBIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 |
5842 | #define smnBIF_CFG_DEV0_EPF7_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000 |
5843 | #define smnBIF_CFG_DEV0_EPF7_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 |
5844 | #define smnBIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG0_DEFAULT 0x00000000 |
5845 | #define smnBIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG1_DEFAULT 0x00000000 |
5846 | #define smnBIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG2_DEFAULT 0x00000000 |
5847 | #define smnBIF_CFG_DEV0_EPF7_1_PCIE_HDR_LOG3_DEFAULT 0x00000000 |
5848 | #define smnBIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 |
5849 | #define smnBIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 |
5850 | #define smnBIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 |
5851 | #define smnBIF_CFG_DEV0_EPF7_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 |
5852 | #define smnBIF_CFG_DEV0_EPF7_1_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000 |
5853 | #define smnBIF_CFG_DEV0_EPF7_1_PCIE_BAR1_CAP_DEFAULT 0x00000000 |
5854 | #define smnBIF_CFG_DEV0_EPF7_1_PCIE_BAR1_CNTL_DEFAULT 0x00000020 |
5855 | #define smnBIF_CFG_DEV0_EPF7_1_PCIE_BAR2_CAP_DEFAULT 0x00000000 |
5856 | #define smnBIF_CFG_DEV0_EPF7_1_PCIE_BAR2_CNTL_DEFAULT 0x00000000 |
5857 | #define smnBIF_CFG_DEV0_EPF7_1_PCIE_BAR3_CAP_DEFAULT 0x00000000 |
5858 | #define smnBIF_CFG_DEV0_EPF7_1_PCIE_BAR3_CNTL_DEFAULT 0x00000000 |
5859 | #define smnBIF_CFG_DEV0_EPF7_1_PCIE_BAR4_CAP_DEFAULT 0x00000000 |
5860 | #define smnBIF_CFG_DEV0_EPF7_1_PCIE_BAR4_CNTL_DEFAULT 0x00000000 |
5861 | #define smnBIF_CFG_DEV0_EPF7_1_PCIE_BAR5_CAP_DEFAULT 0x00000000 |
5862 | #define smnBIF_CFG_DEV0_EPF7_1_PCIE_BAR5_CNTL_DEFAULT 0x00000000 |
5863 | #define smnBIF_CFG_DEV0_EPF7_1_PCIE_BAR6_CAP_DEFAULT 0x00000000 |
5864 | #define smnBIF_CFG_DEV0_EPF7_1_PCIE_BAR6_CNTL_DEFAULT 0x00000000 |
5865 | #define smnBIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000 |
5866 | #define smnBIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000 |
5867 | #define smnBIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000 |
5868 | #define smnBIF_CFG_DEV0_EPF7_1_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000 |
5869 | #define smnBIF_CFG_DEV0_EPF7_1_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000 |
5870 | #define smnBIF_CFG_DEV0_EPF7_1_PCIE_DPA_CAP_DEFAULT 0x00000000 |
5871 | #define smnBIF_CFG_DEV0_EPF7_1_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000 |
5872 | #define smnBIF_CFG_DEV0_EPF7_1_PCIE_DPA_STATUS_DEFAULT 0x00000100 |
5873 | #define smnBIF_CFG_DEV0_EPF7_1_PCIE_DPA_CNTL_DEFAULT 0x00000000 |
5874 | #define smnBIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000 |
5875 | #define smnBIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000 |
5876 | #define smnBIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000 |
5877 | #define smnBIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000 |
5878 | #define smnBIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000 |
5879 | #define smnBIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000 |
5880 | #define smnBIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000 |
5881 | #define smnBIF_CFG_DEV0_EPF7_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000 |
5882 | #define smnBIF_CFG_DEV0_EPF7_1_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000 |
5883 | #define smnBIF_CFG_DEV0_EPF7_1_PCIE_ACS_CAP_DEFAULT 0x00000000 |
5884 | #define smnBIF_CFG_DEV0_EPF7_1_PCIE_ACS_CNTL_DEFAULT 0x00000000 |
5885 | #define smnBIF_CFG_DEV0_EPF7_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000 |
5886 | #define smnBIF_CFG_DEV0_EPF7_1_PCIE_ARI_CAP_DEFAULT 0x00000000 |
5887 | #define smnBIF_CFG_DEV0_EPF7_1_PCIE_ARI_CNTL_DEFAULT 0x00000000 |
5888 | |
5889 | |
5890 | // addressBlock: nbio_nbif0_bif_cfg_dev1_epf0_bifcfgdecp |
5891 | #define smnBIF_CFG_DEV1_EPF0_1_VENDOR_ID_DEFAULT 0x00000000 |
5892 | #define smnBIF_CFG_DEV1_EPF0_1_DEVICE_ID_DEFAULT 0x00000000 |
5893 | #define smnBIF_CFG_DEV1_EPF0_1_COMMAND_DEFAULT 0x00000000 |
5894 | #define smnBIF_CFG_DEV1_EPF0_1_STATUS_DEFAULT 0x00000000 |
5895 | #define smnBIF_CFG_DEV1_EPF0_1_REVISION_ID_DEFAULT 0x00000000 |
5896 | #define smnBIF_CFG_DEV1_EPF0_1_PROG_INTERFACE_DEFAULT 0x00000000 |
5897 | #define smnBIF_CFG_DEV1_EPF0_1_SUB_CLASS_DEFAULT 0x00000000 |
5898 | #define smnBIF_CFG_DEV1_EPF0_1_BASE_CLASS_DEFAULT 0x00000000 |
5899 | #define smnBIF_CFG_DEV1_EPF0_1_CACHE_LINE_DEFAULT 0x00000000 |
5900 | #define smnBIF_CFG_DEV1_EPF0_1_LATENCY_DEFAULT 0x00000000 |
5901 | #define 0x00000000 |
5902 | #define smnBIF_CFG_DEV1_EPF0_1_BIST_DEFAULT 0x00000000 |
5903 | #define smnBIF_CFG_DEV1_EPF0_1_BASE_ADDR_1_DEFAULT 0x00000000 |
5904 | #define smnBIF_CFG_DEV1_EPF0_1_BASE_ADDR_2_DEFAULT 0x00000000 |
5905 | #define smnBIF_CFG_DEV1_EPF0_1_BASE_ADDR_3_DEFAULT 0x00000000 |
5906 | #define smnBIF_CFG_DEV1_EPF0_1_BASE_ADDR_4_DEFAULT 0x00000000 |
5907 | #define smnBIF_CFG_DEV1_EPF0_1_BASE_ADDR_5_DEFAULT 0x00000000 |
5908 | #define smnBIF_CFG_DEV1_EPF0_1_BASE_ADDR_6_DEFAULT 0x00000000 |
5909 | #define smnBIF_CFG_DEV1_EPF0_1_ADAPTER_ID_DEFAULT 0x00000000 |
5910 | #define smnBIF_CFG_DEV1_EPF0_1_ROM_BASE_ADDR_DEFAULT 0x00000000 |
5911 | #define smnBIF_CFG_DEV1_EPF0_1_CAP_PTR_DEFAULT 0x00000000 |
5912 | #define smnBIF_CFG_DEV1_EPF0_1_INTERRUPT_LINE_DEFAULT 0x00000000 |
5913 | #define smnBIF_CFG_DEV1_EPF0_1_INTERRUPT_PIN_DEFAULT 0x00000000 |
5914 | #define smnBIF_CFG_DEV1_EPF0_1_MIN_GRANT_DEFAULT 0x00000000 |
5915 | #define smnBIF_CFG_DEV1_EPF0_1_MAX_LATENCY_DEFAULT 0x00000000 |
5916 | #define smnBIF_CFG_DEV1_EPF0_1_VENDOR_CAP_LIST_DEFAULT 0x00000000 |
5917 | #define smnBIF_CFG_DEV1_EPF0_1_ADAPTER_ID_W_DEFAULT 0x00000000 |
5918 | #define smnBIF_CFG_DEV1_EPF0_1_PMI_CAP_LIST_DEFAULT 0x00000000 |
5919 | #define smnBIF_CFG_DEV1_EPF0_1_PMI_CAP_DEFAULT 0x00000000 |
5920 | #define smnBIF_CFG_DEV1_EPF0_1_PMI_STATUS_CNTL_DEFAULT 0x00000000 |
5921 | #define smnBIF_CFG_DEV1_EPF0_1_PCIE_CAP_LIST_DEFAULT 0x0000a000 |
5922 | #define smnBIF_CFG_DEV1_EPF0_1_PCIE_CAP_DEFAULT 0x00000002 |
5923 | #define smnBIF_CFG_DEV1_EPF0_1_DEVICE_CAP_DEFAULT 0x10000000 |
5924 | #define smnBIF_CFG_DEV1_EPF0_1_DEVICE_CNTL_DEFAULT 0x00002810 |
5925 | #define smnBIF_CFG_DEV1_EPF0_1_DEVICE_STATUS_DEFAULT 0x00000000 |
5926 | #define smnBIF_CFG_DEV1_EPF0_1_LINK_CAP_DEFAULT 0x00011c03 |
5927 | #define smnBIF_CFG_DEV1_EPF0_1_LINK_CNTL_DEFAULT 0x00000000 |
5928 | #define smnBIF_CFG_DEV1_EPF0_1_LINK_STATUS_DEFAULT 0x00000001 |
5929 | #define smnBIF_CFG_DEV1_EPF0_1_DEVICE_CAP2_DEFAULT 0x00000000 |
5930 | #define smnBIF_CFG_DEV1_EPF0_1_DEVICE_CNTL2_DEFAULT 0x00000000 |
5931 | #define smnBIF_CFG_DEV1_EPF0_1_DEVICE_STATUS2_DEFAULT 0x00000000 |
5932 | #define smnBIF_CFG_DEV1_EPF0_1_LINK_CAP2_DEFAULT 0x0000000e |
5933 | #define smnBIF_CFG_DEV1_EPF0_1_LINK_CNTL2_DEFAULT 0x00000003 |
5934 | #define smnBIF_CFG_DEV1_EPF0_1_LINK_STATUS2_DEFAULT 0x00000000 |
5935 | #define smnBIF_CFG_DEV1_EPF0_1_SLOT_CAP2_DEFAULT 0x00000000 |
5936 | #define smnBIF_CFG_DEV1_EPF0_1_SLOT_CNTL2_DEFAULT 0x00000000 |
5937 | #define smnBIF_CFG_DEV1_EPF0_1_SLOT_STATUS2_DEFAULT 0x00000000 |
5938 | #define smnBIF_CFG_DEV1_EPF0_1_MSI_CAP_LIST_DEFAULT 0x0000c000 |
5939 | #define smnBIF_CFG_DEV1_EPF0_1_MSI_MSG_CNTL_DEFAULT 0x00000080 |
5940 | #define smnBIF_CFG_DEV1_EPF0_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 |
5941 | #define smnBIF_CFG_DEV1_EPF0_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 |
5942 | #define smnBIF_CFG_DEV1_EPF0_1_MSI_MSG_DATA_DEFAULT 0x00000000 |
5943 | #define smnBIF_CFG_DEV1_EPF0_1_MSI_MASK_DEFAULT 0x00000000 |
5944 | #define smnBIF_CFG_DEV1_EPF0_1_MSI_MSG_DATA_64_DEFAULT 0x00000000 |
5945 | #define smnBIF_CFG_DEV1_EPF0_1_MSI_MASK_64_DEFAULT 0x00000000 |
5946 | #define smnBIF_CFG_DEV1_EPF0_1_MSI_PENDING_DEFAULT 0x00000000 |
5947 | #define smnBIF_CFG_DEV1_EPF0_1_MSI_PENDING_64_DEFAULT 0x00000000 |
5948 | #define smnBIF_CFG_DEV1_EPF0_1_MSIX_CAP_LIST_DEFAULT 0x00000000 |
5949 | #define smnBIF_CFG_DEV1_EPF0_1_MSIX_MSG_CNTL_DEFAULT 0x00000000 |
5950 | #define smnBIF_CFG_DEV1_EPF0_1_MSIX_TABLE_DEFAULT 0x00000000 |
5951 | #define smnBIF_CFG_DEV1_EPF0_1_MSIX_PBA_DEFAULT 0x00000000 |
5952 | #define smnBIF_CFG_DEV1_EPF0_1_SATA_CAP_0_DEFAULT 0x00000000 |
5953 | #define smnBIF_CFG_DEV1_EPF0_1_SATA_CAP_1_DEFAULT 0x00000000 |
5954 | #define smnBIF_CFG_DEV1_EPF0_1_SATA_IDP_INDEX_DEFAULT 0x00000000 |
5955 | #define smnBIF_CFG_DEV1_EPF0_1_SATA_IDP_DATA_DEFAULT 0x00000000 |
5956 | #define smnBIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 |
5957 | #define smnBIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 |
5958 | #define smnBIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 |
5959 | #define smnBIF_CFG_DEV1_EPF0_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 |
5960 | #define smnBIF_CFG_DEV1_EPF0_1_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000 |
5961 | #define smnBIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000 |
5962 | #define smnBIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000 |
5963 | #define smnBIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000 |
5964 | #define smnBIF_CFG_DEV1_EPF0_1_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000 |
5965 | #define smnBIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000 |
5966 | #define smnBIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe |
5967 | #define smnBIF_CFG_DEV1_EPF0_1_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000000 |
5968 | #define smnBIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000 |
5969 | #define smnBIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000 |
5970 | #define smnBIF_CFG_DEV1_EPF0_1_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000000 |
5971 | #define smnBIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 |
5972 | #define smnBIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 |
5973 | #define smnBIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 |
5974 | #define smnBIF_CFG_DEV1_EPF0_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 |
5975 | #define smnBIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 |
5976 | #define smnBIF_CFG_DEV1_EPF0_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000 |
5977 | #define smnBIF_CFG_DEV1_EPF0_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 |
5978 | #define smnBIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG0_DEFAULT 0x00000000 |
5979 | #define smnBIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG1_DEFAULT 0x00000000 |
5980 | #define smnBIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG2_DEFAULT 0x00000000 |
5981 | #define smnBIF_CFG_DEV1_EPF0_1_PCIE_HDR_LOG3_DEFAULT 0x00000000 |
5982 | #define smnBIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 |
5983 | #define smnBIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 |
5984 | #define smnBIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 |
5985 | #define smnBIF_CFG_DEV1_EPF0_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 |
5986 | #define smnBIF_CFG_DEV1_EPF0_1_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000 |
5987 | #define smnBIF_CFG_DEV1_EPF0_1_PCIE_BAR1_CAP_DEFAULT 0x00000000 |
5988 | #define smnBIF_CFG_DEV1_EPF0_1_PCIE_BAR1_CNTL_DEFAULT 0x00000020 |
5989 | #define smnBIF_CFG_DEV1_EPF0_1_PCIE_BAR2_CAP_DEFAULT 0x00000000 |
5990 | #define smnBIF_CFG_DEV1_EPF0_1_PCIE_BAR2_CNTL_DEFAULT 0x00000000 |
5991 | #define smnBIF_CFG_DEV1_EPF0_1_PCIE_BAR3_CAP_DEFAULT 0x00000000 |
5992 | #define smnBIF_CFG_DEV1_EPF0_1_PCIE_BAR3_CNTL_DEFAULT 0x00000000 |
5993 | #define smnBIF_CFG_DEV1_EPF0_1_PCIE_BAR4_CAP_DEFAULT 0x00000000 |
5994 | #define smnBIF_CFG_DEV1_EPF0_1_PCIE_BAR4_CNTL_DEFAULT 0x00000000 |
5995 | #define smnBIF_CFG_DEV1_EPF0_1_PCIE_BAR5_CAP_DEFAULT 0x00000000 |
5996 | #define smnBIF_CFG_DEV1_EPF0_1_PCIE_BAR5_CNTL_DEFAULT 0x00000000 |
5997 | #define smnBIF_CFG_DEV1_EPF0_1_PCIE_BAR6_CAP_DEFAULT 0x00000000 |
5998 | #define smnBIF_CFG_DEV1_EPF0_1_PCIE_BAR6_CNTL_DEFAULT 0x00000000 |
5999 | #define smnBIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000 |
6000 | #define smnBIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000 |
6001 | #define smnBIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000 |
6002 | #define smnBIF_CFG_DEV1_EPF0_1_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000 |
6003 | #define smnBIF_CFG_DEV1_EPF0_1_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000 |
6004 | #define smnBIF_CFG_DEV1_EPF0_1_PCIE_DPA_CAP_DEFAULT 0x00000000 |
6005 | #define smnBIF_CFG_DEV1_EPF0_1_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000 |
6006 | #define smnBIF_CFG_DEV1_EPF0_1_PCIE_DPA_STATUS_DEFAULT 0x00000100 |
6007 | #define smnBIF_CFG_DEV1_EPF0_1_PCIE_DPA_CNTL_DEFAULT 0x00000000 |
6008 | #define smnBIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000 |
6009 | #define smnBIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000 |
6010 | #define smnBIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000 |
6011 | #define smnBIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000 |
6012 | #define smnBIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000 |
6013 | #define smnBIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000 |
6014 | #define smnBIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000 |
6015 | #define smnBIF_CFG_DEV1_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000 |
6016 | #define smnBIF_CFG_DEV1_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a010019 |
6017 | #define smnBIF_CFG_DEV1_EPF0_1_PCIE_LINK_CNTL3_DEFAULT 0x00000000 |
6018 | #define smnBIF_CFG_DEV1_EPF0_1_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000 |
6019 | #define smnBIF_CFG_DEV1_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
6020 | #define smnBIF_CFG_DEV1_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
6021 | #define smnBIF_CFG_DEV1_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
6022 | #define smnBIF_CFG_DEV1_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
6023 | #define smnBIF_CFG_DEV1_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
6024 | #define smnBIF_CFG_DEV1_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
6025 | #define smnBIF_CFG_DEV1_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
6026 | #define smnBIF_CFG_DEV1_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
6027 | #define smnBIF_CFG_DEV1_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
6028 | #define smnBIF_CFG_DEV1_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
6029 | #define smnBIF_CFG_DEV1_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
6030 | #define smnBIF_CFG_DEV1_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
6031 | #define smnBIF_CFG_DEV1_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
6032 | #define smnBIF_CFG_DEV1_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
6033 | #define smnBIF_CFG_DEV1_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
6034 | #define smnBIF_CFG_DEV1_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
6035 | #define smnBIF_CFG_DEV1_EPF0_1_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000 |
6036 | #define smnBIF_CFG_DEV1_EPF0_1_PCIE_ACS_CAP_DEFAULT 0x00000000 |
6037 | #define smnBIF_CFG_DEV1_EPF0_1_PCIE_ACS_CNTL_DEFAULT 0x00000000 |
6038 | #define smnBIF_CFG_DEV1_EPF0_1_PCIE_LTR_ENH_CAP_LIST_DEFAULT 0x32800000 |
6039 | #define smnBIF_CFG_DEV1_EPF0_1_PCIE_LTR_CAP_DEFAULT 0x00000000 |
6040 | #define smnBIF_CFG_DEV1_EPF0_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000 |
6041 | #define smnBIF_CFG_DEV1_EPF0_1_PCIE_ARI_CAP_DEFAULT 0x00000000 |
6042 | #define smnBIF_CFG_DEV1_EPF0_1_PCIE_ARI_CNTL_DEFAULT 0x00000000 |
6043 | |
6044 | |
6045 | // addressBlock: nbio_nbif0_bif_cfg_dev1_epf1_bifcfgdecp |
6046 | #define smnBIF_CFG_DEV1_EPF1_1_VENDOR_ID_DEFAULT 0x00000000 |
6047 | #define smnBIF_CFG_DEV1_EPF1_1_DEVICE_ID_DEFAULT 0x00000000 |
6048 | #define smnBIF_CFG_DEV1_EPF1_1_COMMAND_DEFAULT 0x00000000 |
6049 | #define smnBIF_CFG_DEV1_EPF1_1_STATUS_DEFAULT 0x00000000 |
6050 | #define smnBIF_CFG_DEV1_EPF1_1_REVISION_ID_DEFAULT 0x00000000 |
6051 | #define smnBIF_CFG_DEV1_EPF1_1_PROG_INTERFACE_DEFAULT 0x00000000 |
6052 | #define smnBIF_CFG_DEV1_EPF1_1_SUB_CLASS_DEFAULT 0x00000000 |
6053 | #define smnBIF_CFG_DEV1_EPF1_1_BASE_CLASS_DEFAULT 0x00000000 |
6054 | #define smnBIF_CFG_DEV1_EPF1_1_CACHE_LINE_DEFAULT 0x00000000 |
6055 | #define smnBIF_CFG_DEV1_EPF1_1_LATENCY_DEFAULT 0x00000000 |
6056 | #define 0x00000000 |
6057 | #define smnBIF_CFG_DEV1_EPF1_1_BIST_DEFAULT 0x00000000 |
6058 | #define smnBIF_CFG_DEV1_EPF1_1_BASE_ADDR_1_DEFAULT 0x00000000 |
6059 | #define smnBIF_CFG_DEV1_EPF1_1_BASE_ADDR_2_DEFAULT 0x00000000 |
6060 | #define smnBIF_CFG_DEV1_EPF1_1_BASE_ADDR_3_DEFAULT 0x00000000 |
6061 | #define smnBIF_CFG_DEV1_EPF1_1_BASE_ADDR_4_DEFAULT 0x00000000 |
6062 | #define smnBIF_CFG_DEV1_EPF1_1_BASE_ADDR_5_DEFAULT 0x00000000 |
6063 | #define smnBIF_CFG_DEV1_EPF1_1_BASE_ADDR_6_DEFAULT 0x00000000 |
6064 | #define smnBIF_CFG_DEV1_EPF1_1_ADAPTER_ID_DEFAULT 0x00000000 |
6065 | #define smnBIF_CFG_DEV1_EPF1_1_ROM_BASE_ADDR_DEFAULT 0x00000000 |
6066 | #define smnBIF_CFG_DEV1_EPF1_1_CAP_PTR_DEFAULT 0x00000000 |
6067 | #define smnBIF_CFG_DEV1_EPF1_1_INTERRUPT_LINE_DEFAULT 0x00000000 |
6068 | #define smnBIF_CFG_DEV1_EPF1_1_INTERRUPT_PIN_DEFAULT 0x00000000 |
6069 | #define smnBIF_CFG_DEV1_EPF1_1_MIN_GRANT_DEFAULT 0x00000000 |
6070 | #define smnBIF_CFG_DEV1_EPF1_1_MAX_LATENCY_DEFAULT 0x00000000 |
6071 | #define smnBIF_CFG_DEV1_EPF1_1_VENDOR_CAP_LIST_DEFAULT 0x00000000 |
6072 | #define smnBIF_CFG_DEV1_EPF1_1_ADAPTER_ID_W_DEFAULT 0x00000000 |
6073 | #define smnBIF_CFG_DEV1_EPF1_1_PMI_CAP_LIST_DEFAULT 0x00000000 |
6074 | #define smnBIF_CFG_DEV1_EPF1_1_PMI_CAP_DEFAULT 0x00000000 |
6075 | #define smnBIF_CFG_DEV1_EPF1_1_PMI_STATUS_CNTL_DEFAULT 0x00000000 |
6076 | #define smnBIF_CFG_DEV1_EPF1_1_SBRN_DEFAULT 0x00000000 |
6077 | #define smnBIF_CFG_DEV1_EPF1_1_FLADJ_DEFAULT 0x00000020 |
6078 | #define smnBIF_CFG_DEV1_EPF1_1_DBESL_DBESLD_DEFAULT 0x00000000 |
6079 | #define smnBIF_CFG_DEV1_EPF1_1_PCIE_CAP_LIST_DEFAULT 0x0000a000 |
6080 | #define smnBIF_CFG_DEV1_EPF1_1_PCIE_CAP_DEFAULT 0x00000002 |
6081 | #define smnBIF_CFG_DEV1_EPF1_1_DEVICE_CAP_DEFAULT 0x10000000 |
6082 | #define smnBIF_CFG_DEV1_EPF1_1_DEVICE_CNTL_DEFAULT 0x00002810 |
6083 | #define smnBIF_CFG_DEV1_EPF1_1_DEVICE_STATUS_DEFAULT 0x00000000 |
6084 | #define smnBIF_CFG_DEV1_EPF1_1_LINK_CAP_DEFAULT 0x00011c03 |
6085 | #define smnBIF_CFG_DEV1_EPF1_1_LINK_CNTL_DEFAULT 0x00000000 |
6086 | #define smnBIF_CFG_DEV1_EPF1_1_LINK_STATUS_DEFAULT 0x00000001 |
6087 | #define smnBIF_CFG_DEV1_EPF1_1_DEVICE_CAP2_DEFAULT 0x00000000 |
6088 | #define smnBIF_CFG_DEV1_EPF1_1_DEVICE_CNTL2_DEFAULT 0x00000000 |
6089 | #define smnBIF_CFG_DEV1_EPF1_1_DEVICE_STATUS2_DEFAULT 0x00000000 |
6090 | #define smnBIF_CFG_DEV1_EPF1_1_LINK_CAP2_DEFAULT 0x0000000e |
6091 | #define smnBIF_CFG_DEV1_EPF1_1_LINK_CNTL2_DEFAULT 0x00000003 |
6092 | #define smnBIF_CFG_DEV1_EPF1_1_LINK_STATUS2_DEFAULT 0x00000000 |
6093 | #define smnBIF_CFG_DEV1_EPF1_1_SLOT_CAP2_DEFAULT 0x00000000 |
6094 | #define smnBIF_CFG_DEV1_EPF1_1_SLOT_CNTL2_DEFAULT 0x00000000 |
6095 | #define smnBIF_CFG_DEV1_EPF1_1_SLOT_STATUS2_DEFAULT 0x00000000 |
6096 | #define smnBIF_CFG_DEV1_EPF1_1_MSI_CAP_LIST_DEFAULT 0x0000c000 |
6097 | #define smnBIF_CFG_DEV1_EPF1_1_MSI_MSG_CNTL_DEFAULT 0x00000080 |
6098 | #define smnBIF_CFG_DEV1_EPF1_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 |
6099 | #define smnBIF_CFG_DEV1_EPF1_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 |
6100 | #define smnBIF_CFG_DEV1_EPF1_1_MSI_MSG_DATA_DEFAULT 0x00000000 |
6101 | #define smnBIF_CFG_DEV1_EPF1_1_MSI_MASK_DEFAULT 0x00000000 |
6102 | #define smnBIF_CFG_DEV1_EPF1_1_MSI_MSG_DATA_64_DEFAULT 0x00000000 |
6103 | #define smnBIF_CFG_DEV1_EPF1_1_MSI_MASK_64_DEFAULT 0x00000000 |
6104 | #define smnBIF_CFG_DEV1_EPF1_1_MSI_PENDING_DEFAULT 0x00000000 |
6105 | #define smnBIF_CFG_DEV1_EPF1_1_MSI_PENDING_64_DEFAULT 0x00000000 |
6106 | #define smnBIF_CFG_DEV1_EPF1_1_MSIX_CAP_LIST_DEFAULT 0x00000000 |
6107 | #define smnBIF_CFG_DEV1_EPF1_1_MSIX_MSG_CNTL_DEFAULT 0x00000000 |
6108 | #define smnBIF_CFG_DEV1_EPF1_1_MSIX_TABLE_DEFAULT 0x00000000 |
6109 | #define smnBIF_CFG_DEV1_EPF1_1_MSIX_PBA_DEFAULT 0x00000000 |
6110 | #define smnBIF_CFG_DEV1_EPF1_1_SATA_CAP_0_DEFAULT 0x00000000 |
6111 | #define smnBIF_CFG_DEV1_EPF1_1_SATA_CAP_1_DEFAULT 0x00000000 |
6112 | #define smnBIF_CFG_DEV1_EPF1_1_SATA_IDP_INDEX_DEFAULT 0x00000000 |
6113 | #define smnBIF_CFG_DEV1_EPF1_1_SATA_IDP_DATA_DEFAULT 0x00000000 |
6114 | #define smnBIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 |
6115 | #define smnBIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 |
6116 | #define smnBIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 |
6117 | #define smnBIF_CFG_DEV1_EPF1_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 |
6118 | #define smnBIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 |
6119 | #define smnBIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 |
6120 | #define smnBIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 |
6121 | #define smnBIF_CFG_DEV1_EPF1_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 |
6122 | #define smnBIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 |
6123 | #define smnBIF_CFG_DEV1_EPF1_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000 |
6124 | #define smnBIF_CFG_DEV1_EPF1_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 |
6125 | #define smnBIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG0_DEFAULT 0x00000000 |
6126 | #define smnBIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG1_DEFAULT 0x00000000 |
6127 | #define smnBIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG2_DEFAULT 0x00000000 |
6128 | #define smnBIF_CFG_DEV1_EPF1_1_PCIE_HDR_LOG3_DEFAULT 0x00000000 |
6129 | #define smnBIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 |
6130 | #define smnBIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 |
6131 | #define smnBIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 |
6132 | #define smnBIF_CFG_DEV1_EPF1_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 |
6133 | #define smnBIF_CFG_DEV1_EPF1_1_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000 |
6134 | #define smnBIF_CFG_DEV1_EPF1_1_PCIE_BAR1_CAP_DEFAULT 0x00000000 |
6135 | #define smnBIF_CFG_DEV1_EPF1_1_PCIE_BAR1_CNTL_DEFAULT 0x00000020 |
6136 | #define smnBIF_CFG_DEV1_EPF1_1_PCIE_BAR2_CAP_DEFAULT 0x00000000 |
6137 | #define smnBIF_CFG_DEV1_EPF1_1_PCIE_BAR2_CNTL_DEFAULT 0x00000000 |
6138 | #define smnBIF_CFG_DEV1_EPF1_1_PCIE_BAR3_CAP_DEFAULT 0x00000000 |
6139 | #define smnBIF_CFG_DEV1_EPF1_1_PCIE_BAR3_CNTL_DEFAULT 0x00000000 |
6140 | #define smnBIF_CFG_DEV1_EPF1_1_PCIE_BAR4_CAP_DEFAULT 0x00000000 |
6141 | #define smnBIF_CFG_DEV1_EPF1_1_PCIE_BAR4_CNTL_DEFAULT 0x00000000 |
6142 | #define smnBIF_CFG_DEV1_EPF1_1_PCIE_BAR5_CAP_DEFAULT 0x00000000 |
6143 | #define smnBIF_CFG_DEV1_EPF1_1_PCIE_BAR5_CNTL_DEFAULT 0x00000000 |
6144 | #define smnBIF_CFG_DEV1_EPF1_1_PCIE_BAR6_CAP_DEFAULT 0x00000000 |
6145 | #define smnBIF_CFG_DEV1_EPF1_1_PCIE_BAR6_CNTL_DEFAULT 0x00000000 |
6146 | #define smnBIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000 |
6147 | #define smnBIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000 |
6148 | #define smnBIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000 |
6149 | #define smnBIF_CFG_DEV1_EPF1_1_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000 |
6150 | #define smnBIF_CFG_DEV1_EPF1_1_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000 |
6151 | #define smnBIF_CFG_DEV1_EPF1_1_PCIE_DPA_CAP_DEFAULT 0x00000000 |
6152 | #define smnBIF_CFG_DEV1_EPF1_1_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000 |
6153 | #define smnBIF_CFG_DEV1_EPF1_1_PCIE_DPA_STATUS_DEFAULT 0x00000100 |
6154 | #define smnBIF_CFG_DEV1_EPF1_1_PCIE_DPA_CNTL_DEFAULT 0x00000000 |
6155 | #define smnBIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000 |
6156 | #define smnBIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000 |
6157 | #define smnBIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000 |
6158 | #define smnBIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000 |
6159 | #define smnBIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000 |
6160 | #define smnBIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000 |
6161 | #define smnBIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000 |
6162 | #define smnBIF_CFG_DEV1_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000 |
6163 | #define smnBIF_CFG_DEV1_EPF1_1_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000 |
6164 | #define smnBIF_CFG_DEV1_EPF1_1_PCIE_ACS_CAP_DEFAULT 0x00000000 |
6165 | #define smnBIF_CFG_DEV1_EPF1_1_PCIE_ACS_CNTL_DEFAULT 0x00000000 |
6166 | #define smnBIF_CFG_DEV1_EPF1_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000 |
6167 | #define smnBIF_CFG_DEV1_EPF1_1_PCIE_ARI_CAP_DEFAULT 0x00000000 |
6168 | #define smnBIF_CFG_DEV1_EPF1_1_PCIE_ARI_CNTL_DEFAULT 0x00000000 |
6169 | |
6170 | |
6171 | // addressBlock: nbio_nbif0_bif_cfg_dev1_epf2_bifcfgdecp |
6172 | #define smnBIF_CFG_DEV1_EPF2_1_VENDOR_ID_DEFAULT 0x00000000 |
6173 | #define smnBIF_CFG_DEV1_EPF2_1_DEVICE_ID_DEFAULT 0x00000000 |
6174 | #define smnBIF_CFG_DEV1_EPF2_1_COMMAND_DEFAULT 0x00000000 |
6175 | #define smnBIF_CFG_DEV1_EPF2_1_STATUS_DEFAULT 0x00000000 |
6176 | #define smnBIF_CFG_DEV1_EPF2_1_REVISION_ID_DEFAULT 0x00000000 |
6177 | #define smnBIF_CFG_DEV1_EPF2_1_PROG_INTERFACE_DEFAULT 0x00000000 |
6178 | #define smnBIF_CFG_DEV1_EPF2_1_SUB_CLASS_DEFAULT 0x00000000 |
6179 | #define smnBIF_CFG_DEV1_EPF2_1_BASE_CLASS_DEFAULT 0x00000000 |
6180 | #define smnBIF_CFG_DEV1_EPF2_1_CACHE_LINE_DEFAULT 0x00000000 |
6181 | #define smnBIF_CFG_DEV1_EPF2_1_LATENCY_DEFAULT 0x00000000 |
6182 | #define 0x00000000 |
6183 | #define smnBIF_CFG_DEV1_EPF2_1_BIST_DEFAULT 0x00000000 |
6184 | #define smnBIF_CFG_DEV1_EPF2_1_BASE_ADDR_1_DEFAULT 0x00000000 |
6185 | #define smnBIF_CFG_DEV1_EPF2_1_BASE_ADDR_2_DEFAULT 0x00000000 |
6186 | #define smnBIF_CFG_DEV1_EPF2_1_BASE_ADDR_3_DEFAULT 0x00000000 |
6187 | #define smnBIF_CFG_DEV1_EPF2_1_BASE_ADDR_4_DEFAULT 0x00000000 |
6188 | #define smnBIF_CFG_DEV1_EPF2_1_BASE_ADDR_5_DEFAULT 0x00000000 |
6189 | #define smnBIF_CFG_DEV1_EPF2_1_BASE_ADDR_6_DEFAULT 0x00000000 |
6190 | #define smnBIF_CFG_DEV1_EPF2_1_ADAPTER_ID_DEFAULT 0x00000000 |
6191 | #define smnBIF_CFG_DEV1_EPF2_1_ROM_BASE_ADDR_DEFAULT 0x00000000 |
6192 | #define smnBIF_CFG_DEV1_EPF2_1_CAP_PTR_DEFAULT 0x00000000 |
6193 | #define smnBIF_CFG_DEV1_EPF2_1_INTERRUPT_LINE_DEFAULT 0x00000000 |
6194 | #define smnBIF_CFG_DEV1_EPF2_1_INTERRUPT_PIN_DEFAULT 0x00000000 |
6195 | #define smnBIF_CFG_DEV1_EPF2_1_MIN_GRANT_DEFAULT 0x00000000 |
6196 | #define smnBIF_CFG_DEV1_EPF2_1_MAX_LATENCY_DEFAULT 0x00000000 |
6197 | #define smnBIF_CFG_DEV1_EPF2_1_VENDOR_CAP_LIST_DEFAULT 0x00000000 |
6198 | #define smnBIF_CFG_DEV1_EPF2_1_ADAPTER_ID_W_DEFAULT 0x00000000 |
6199 | #define smnBIF_CFG_DEV1_EPF2_1_PMI_CAP_LIST_DEFAULT 0x00000000 |
6200 | #define smnBIF_CFG_DEV1_EPF2_1_PMI_CAP_DEFAULT 0x00000000 |
6201 | #define smnBIF_CFG_DEV1_EPF2_1_PMI_STATUS_CNTL_DEFAULT 0x00000000 |
6202 | #define smnBIF_CFG_DEV1_EPF2_1_SBRN_DEFAULT 0x00000000 |
6203 | #define smnBIF_CFG_DEV1_EPF2_1_FLADJ_DEFAULT 0x00000020 |
6204 | #define smnBIF_CFG_DEV1_EPF2_1_DBESL_DBESLD_DEFAULT 0x00000000 |
6205 | #define smnBIF_CFG_DEV1_EPF2_1_PCIE_CAP_LIST_DEFAULT 0x0000a000 |
6206 | #define smnBIF_CFG_DEV1_EPF2_1_PCIE_CAP_DEFAULT 0x00000002 |
6207 | #define smnBIF_CFG_DEV1_EPF2_1_DEVICE_CAP_DEFAULT 0x10000000 |
6208 | #define smnBIF_CFG_DEV1_EPF2_1_DEVICE_CNTL_DEFAULT 0x00002810 |
6209 | #define smnBIF_CFG_DEV1_EPF2_1_DEVICE_STATUS_DEFAULT 0x00000000 |
6210 | #define smnBIF_CFG_DEV1_EPF2_1_LINK_CAP_DEFAULT 0x00011c03 |
6211 | #define smnBIF_CFG_DEV1_EPF2_1_LINK_CNTL_DEFAULT 0x00000000 |
6212 | #define smnBIF_CFG_DEV1_EPF2_1_LINK_STATUS_DEFAULT 0x00000001 |
6213 | #define smnBIF_CFG_DEV1_EPF2_1_DEVICE_CAP2_DEFAULT 0x00000000 |
6214 | #define smnBIF_CFG_DEV1_EPF2_1_DEVICE_CNTL2_DEFAULT 0x00000000 |
6215 | #define smnBIF_CFG_DEV1_EPF2_1_DEVICE_STATUS2_DEFAULT 0x00000000 |
6216 | #define smnBIF_CFG_DEV1_EPF2_1_LINK_CAP2_DEFAULT 0x0000000e |
6217 | #define smnBIF_CFG_DEV1_EPF2_1_LINK_CNTL2_DEFAULT 0x00000003 |
6218 | #define smnBIF_CFG_DEV1_EPF2_1_LINK_STATUS2_DEFAULT 0x00000000 |
6219 | #define smnBIF_CFG_DEV1_EPF2_1_SLOT_CAP2_DEFAULT 0x00000000 |
6220 | #define smnBIF_CFG_DEV1_EPF2_1_SLOT_CNTL2_DEFAULT 0x00000000 |
6221 | #define smnBIF_CFG_DEV1_EPF2_1_SLOT_STATUS2_DEFAULT 0x00000000 |
6222 | #define smnBIF_CFG_DEV1_EPF2_1_MSI_CAP_LIST_DEFAULT 0x0000c000 |
6223 | #define smnBIF_CFG_DEV1_EPF2_1_MSI_MSG_CNTL_DEFAULT 0x00000080 |
6224 | #define smnBIF_CFG_DEV1_EPF2_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 |
6225 | #define smnBIF_CFG_DEV1_EPF2_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 |
6226 | #define smnBIF_CFG_DEV1_EPF2_1_MSI_MSG_DATA_DEFAULT 0x00000000 |
6227 | #define smnBIF_CFG_DEV1_EPF2_1_MSI_MASK_DEFAULT 0x00000000 |
6228 | #define smnBIF_CFG_DEV1_EPF2_1_MSI_MSG_DATA_64_DEFAULT 0x00000000 |
6229 | #define smnBIF_CFG_DEV1_EPF2_1_MSI_MASK_64_DEFAULT 0x00000000 |
6230 | #define smnBIF_CFG_DEV1_EPF2_1_MSI_PENDING_DEFAULT 0x00000000 |
6231 | #define smnBIF_CFG_DEV1_EPF2_1_MSI_PENDING_64_DEFAULT 0x00000000 |
6232 | #define smnBIF_CFG_DEV1_EPF2_1_MSIX_CAP_LIST_DEFAULT 0x00000000 |
6233 | #define smnBIF_CFG_DEV1_EPF2_1_MSIX_MSG_CNTL_DEFAULT 0x00000000 |
6234 | #define smnBIF_CFG_DEV1_EPF2_1_MSIX_TABLE_DEFAULT 0x00000000 |
6235 | #define smnBIF_CFG_DEV1_EPF2_1_MSIX_PBA_DEFAULT 0x00000000 |
6236 | #define smnBIF_CFG_DEV1_EPF2_1_SATA_CAP_0_DEFAULT 0x00000000 |
6237 | #define smnBIF_CFG_DEV1_EPF2_1_SATA_CAP_1_DEFAULT 0x00000000 |
6238 | #define smnBIF_CFG_DEV1_EPF2_1_SATA_IDP_INDEX_DEFAULT 0x00000000 |
6239 | #define smnBIF_CFG_DEV1_EPF2_1_SATA_IDP_DATA_DEFAULT 0x00000000 |
6240 | #define smnBIF_CFG_DEV1_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 |
6241 | #define smnBIF_CFG_DEV1_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 |
6242 | #define smnBIF_CFG_DEV1_EPF2_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 |
6243 | #define smnBIF_CFG_DEV1_EPF2_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 |
6244 | #define smnBIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 |
6245 | #define smnBIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 |
6246 | #define smnBIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 |
6247 | #define smnBIF_CFG_DEV1_EPF2_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 |
6248 | #define smnBIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 |
6249 | #define smnBIF_CFG_DEV1_EPF2_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000 |
6250 | #define smnBIF_CFG_DEV1_EPF2_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 |
6251 | #define smnBIF_CFG_DEV1_EPF2_1_PCIE_HDR_LOG0_DEFAULT 0x00000000 |
6252 | #define smnBIF_CFG_DEV1_EPF2_1_PCIE_HDR_LOG1_DEFAULT 0x00000000 |
6253 | #define smnBIF_CFG_DEV1_EPF2_1_PCIE_HDR_LOG2_DEFAULT 0x00000000 |
6254 | #define smnBIF_CFG_DEV1_EPF2_1_PCIE_HDR_LOG3_DEFAULT 0x00000000 |
6255 | #define smnBIF_CFG_DEV1_EPF2_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 |
6256 | #define smnBIF_CFG_DEV1_EPF2_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 |
6257 | #define smnBIF_CFG_DEV1_EPF2_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 |
6258 | #define smnBIF_CFG_DEV1_EPF2_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 |
6259 | #define smnBIF_CFG_DEV1_EPF2_1_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000 |
6260 | #define smnBIF_CFG_DEV1_EPF2_1_PCIE_BAR1_CAP_DEFAULT 0x00000000 |
6261 | #define smnBIF_CFG_DEV1_EPF2_1_PCIE_BAR1_CNTL_DEFAULT 0x00000020 |
6262 | #define smnBIF_CFG_DEV1_EPF2_1_PCIE_BAR2_CAP_DEFAULT 0x00000000 |
6263 | #define smnBIF_CFG_DEV1_EPF2_1_PCIE_BAR2_CNTL_DEFAULT 0x00000000 |
6264 | #define smnBIF_CFG_DEV1_EPF2_1_PCIE_BAR3_CAP_DEFAULT 0x00000000 |
6265 | #define smnBIF_CFG_DEV1_EPF2_1_PCIE_BAR3_CNTL_DEFAULT 0x00000000 |
6266 | #define smnBIF_CFG_DEV1_EPF2_1_PCIE_BAR4_CAP_DEFAULT 0x00000000 |
6267 | #define smnBIF_CFG_DEV1_EPF2_1_PCIE_BAR4_CNTL_DEFAULT 0x00000000 |
6268 | #define smnBIF_CFG_DEV1_EPF2_1_PCIE_BAR5_CAP_DEFAULT 0x00000000 |
6269 | #define smnBIF_CFG_DEV1_EPF2_1_PCIE_BAR5_CNTL_DEFAULT 0x00000000 |
6270 | #define smnBIF_CFG_DEV1_EPF2_1_PCIE_BAR6_CAP_DEFAULT 0x00000000 |
6271 | #define smnBIF_CFG_DEV1_EPF2_1_PCIE_BAR6_CNTL_DEFAULT 0x00000000 |
6272 | #define smnBIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000 |
6273 | #define smnBIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000 |
6274 | #define smnBIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000 |
6275 | #define smnBIF_CFG_DEV1_EPF2_1_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000 |
6276 | #define smnBIF_CFG_DEV1_EPF2_1_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000 |
6277 | #define smnBIF_CFG_DEV1_EPF2_1_PCIE_DPA_CAP_DEFAULT 0x00000000 |
6278 | #define smnBIF_CFG_DEV1_EPF2_1_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000 |
6279 | #define smnBIF_CFG_DEV1_EPF2_1_PCIE_DPA_STATUS_DEFAULT 0x00000100 |
6280 | #define smnBIF_CFG_DEV1_EPF2_1_PCIE_DPA_CNTL_DEFAULT 0x00000000 |
6281 | #define smnBIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000 |
6282 | #define smnBIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000 |
6283 | #define smnBIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000 |
6284 | #define smnBIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000 |
6285 | #define smnBIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000 |
6286 | #define smnBIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000 |
6287 | #define smnBIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000 |
6288 | #define smnBIF_CFG_DEV1_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000 |
6289 | #define smnBIF_CFG_DEV1_EPF2_1_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000 |
6290 | #define smnBIF_CFG_DEV1_EPF2_1_PCIE_ACS_CAP_DEFAULT 0x00000000 |
6291 | #define smnBIF_CFG_DEV1_EPF2_1_PCIE_ACS_CNTL_DEFAULT 0x00000000 |
6292 | #define smnBIF_CFG_DEV1_EPF2_1_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000 |
6293 | #define smnBIF_CFG_DEV1_EPF2_1_PCIE_ARI_CAP_DEFAULT 0x00000000 |
6294 | #define smnBIF_CFG_DEV1_EPF2_1_PCIE_ARI_CNTL_DEFAULT 0x00000000 |
6295 | |
6296 | |
6297 | // addressBlock: nbio_nbif0_pciemsix_amdgfx_MSIXTDEC |
6298 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000 |
6299 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000 |
6300 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000 |
6301 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT0_CONTROL_DEFAULT 0x00000000 |
6302 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000 |
6303 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000 |
6304 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000 |
6305 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT1_CONTROL_DEFAULT 0x00000000 |
6306 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000 |
6307 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000 |
6308 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000 |
6309 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT2_CONTROL_DEFAULT 0x00000000 |
6310 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000 |
6311 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000 |
6312 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000 |
6313 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT3_CONTROL_DEFAULT 0x00000000 |
6314 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT4_ADDR_LO_DEFAULT 0x00000000 |
6315 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT4_ADDR_HI_DEFAULT 0x00000000 |
6316 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT4_MSG_DATA_DEFAULT 0x00000000 |
6317 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT4_CONTROL_DEFAULT 0x00000000 |
6318 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT5_ADDR_LO_DEFAULT 0x00000000 |
6319 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT5_ADDR_HI_DEFAULT 0x00000000 |
6320 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT5_MSG_DATA_DEFAULT 0x00000000 |
6321 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT5_CONTROL_DEFAULT 0x00000000 |
6322 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT6_ADDR_LO_DEFAULT 0x00000000 |
6323 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT6_ADDR_HI_DEFAULT 0x00000000 |
6324 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT6_MSG_DATA_DEFAULT 0x00000000 |
6325 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT6_CONTROL_DEFAULT 0x00000000 |
6326 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT7_ADDR_LO_DEFAULT 0x00000000 |
6327 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT7_ADDR_HI_DEFAULT 0x00000000 |
6328 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT7_MSG_DATA_DEFAULT 0x00000000 |
6329 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT7_CONTROL_DEFAULT 0x00000000 |
6330 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT8_ADDR_LO_DEFAULT 0x00000000 |
6331 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT8_ADDR_HI_DEFAULT 0x00000000 |
6332 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT8_MSG_DATA_DEFAULT 0x00000000 |
6333 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT8_CONTROL_DEFAULT 0x00000000 |
6334 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT9_ADDR_LO_DEFAULT 0x00000000 |
6335 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT9_ADDR_HI_DEFAULT 0x00000000 |
6336 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT9_MSG_DATA_DEFAULT 0x00000000 |
6337 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT9_CONTROL_DEFAULT 0x00000000 |
6338 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT10_ADDR_LO_DEFAULT 0x00000000 |
6339 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT10_ADDR_HI_DEFAULT 0x00000000 |
6340 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT10_MSG_DATA_DEFAULT 0x00000000 |
6341 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT10_CONTROL_DEFAULT 0x00000000 |
6342 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT11_ADDR_LO_DEFAULT 0x00000000 |
6343 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT11_ADDR_HI_DEFAULT 0x00000000 |
6344 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT11_MSG_DATA_DEFAULT 0x00000000 |
6345 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT11_CONTROL_DEFAULT 0x00000000 |
6346 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT12_ADDR_LO_DEFAULT 0x00000000 |
6347 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT12_ADDR_HI_DEFAULT 0x00000000 |
6348 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT12_MSG_DATA_DEFAULT 0x00000000 |
6349 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT12_CONTROL_DEFAULT 0x00000000 |
6350 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT13_ADDR_LO_DEFAULT 0x00000000 |
6351 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT13_ADDR_HI_DEFAULT 0x00000000 |
6352 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT13_MSG_DATA_DEFAULT 0x00000000 |
6353 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT13_CONTROL_DEFAULT 0x00000000 |
6354 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT14_ADDR_LO_DEFAULT 0x00000000 |
6355 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT14_ADDR_HI_DEFAULT 0x00000000 |
6356 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT14_MSG_DATA_DEFAULT 0x00000000 |
6357 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT14_CONTROL_DEFAULT 0x00000000 |
6358 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT15_ADDR_LO_DEFAULT 0x00000000 |
6359 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT15_ADDR_HI_DEFAULT 0x00000000 |
6360 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT15_MSG_DATA_DEFAULT 0x00000000 |
6361 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT15_CONTROL_DEFAULT 0x00000000 |
6362 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT16_ADDR_LO_DEFAULT 0x00000000 |
6363 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT16_ADDR_HI_DEFAULT 0x00000000 |
6364 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT16_MSG_DATA_DEFAULT 0x00000000 |
6365 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT16_CONTROL_DEFAULT 0x00000000 |
6366 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT17_ADDR_LO_DEFAULT 0x00000000 |
6367 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT17_ADDR_HI_DEFAULT 0x00000000 |
6368 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT17_MSG_DATA_DEFAULT 0x00000000 |
6369 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT17_CONTROL_DEFAULT 0x00000000 |
6370 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT18_ADDR_LO_DEFAULT 0x00000000 |
6371 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT18_ADDR_HI_DEFAULT 0x00000000 |
6372 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT18_MSG_DATA_DEFAULT 0x00000000 |
6373 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT18_CONTROL_DEFAULT 0x00000000 |
6374 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT19_ADDR_LO_DEFAULT 0x00000000 |
6375 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT19_ADDR_HI_DEFAULT 0x00000000 |
6376 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT19_MSG_DATA_DEFAULT 0x00000000 |
6377 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT19_CONTROL_DEFAULT 0x00000000 |
6378 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT20_ADDR_LO_DEFAULT 0x00000000 |
6379 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT20_ADDR_HI_DEFAULT 0x00000000 |
6380 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT20_MSG_DATA_DEFAULT 0x00000000 |
6381 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT20_CONTROL_DEFAULT 0x00000000 |
6382 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT21_ADDR_LO_DEFAULT 0x00000000 |
6383 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT21_ADDR_HI_DEFAULT 0x00000000 |
6384 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT21_MSG_DATA_DEFAULT 0x00000000 |
6385 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT21_CONTROL_DEFAULT 0x00000000 |
6386 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT22_ADDR_LO_DEFAULT 0x00000000 |
6387 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT22_ADDR_HI_DEFAULT 0x00000000 |
6388 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT22_MSG_DATA_DEFAULT 0x00000000 |
6389 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT22_CONTROL_DEFAULT 0x00000000 |
6390 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT23_ADDR_LO_DEFAULT 0x00000000 |
6391 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT23_ADDR_HI_DEFAULT 0x00000000 |
6392 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT23_MSG_DATA_DEFAULT 0x00000000 |
6393 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT23_CONTROL_DEFAULT 0x00000000 |
6394 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT24_ADDR_LO_DEFAULT 0x00000000 |
6395 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT24_ADDR_HI_DEFAULT 0x00000000 |
6396 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT24_MSG_DATA_DEFAULT 0x00000000 |
6397 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT24_CONTROL_DEFAULT 0x00000000 |
6398 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT25_ADDR_LO_DEFAULT 0x00000000 |
6399 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT25_ADDR_HI_DEFAULT 0x00000000 |
6400 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT25_MSG_DATA_DEFAULT 0x00000000 |
6401 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT25_CONTROL_DEFAULT 0x00000000 |
6402 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT26_ADDR_LO_DEFAULT 0x00000000 |
6403 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT26_ADDR_HI_DEFAULT 0x00000000 |
6404 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT26_MSG_DATA_DEFAULT 0x00000000 |
6405 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT26_CONTROL_DEFAULT 0x00000000 |
6406 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT27_ADDR_LO_DEFAULT 0x00000000 |
6407 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT27_ADDR_HI_DEFAULT 0x00000000 |
6408 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT27_MSG_DATA_DEFAULT 0x00000000 |
6409 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT27_CONTROL_DEFAULT 0x00000000 |
6410 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT28_ADDR_LO_DEFAULT 0x00000000 |
6411 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT28_ADDR_HI_DEFAULT 0x00000000 |
6412 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT28_MSG_DATA_DEFAULT 0x00000000 |
6413 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT28_CONTROL_DEFAULT 0x00000000 |
6414 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT29_ADDR_LO_DEFAULT 0x00000000 |
6415 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT29_ADDR_HI_DEFAULT 0x00000000 |
6416 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT29_MSG_DATA_DEFAULT 0x00000000 |
6417 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT29_CONTROL_DEFAULT 0x00000000 |
6418 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT30_ADDR_LO_DEFAULT 0x00000000 |
6419 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT30_ADDR_HI_DEFAULT 0x00000000 |
6420 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT30_MSG_DATA_DEFAULT 0x00000000 |
6421 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT30_CONTROL_DEFAULT 0x00000000 |
6422 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT31_ADDR_LO_DEFAULT 0x00000000 |
6423 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT31_ADDR_HI_DEFAULT 0x00000000 |
6424 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT31_MSG_DATA_DEFAULT 0x00000000 |
6425 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_VECT31_CONTROL_DEFAULT 0x00000000 |
6426 | |
6427 | |
6428 | // addressBlock: nbio_nbif0_pciemsix_psp_MSIXTDEC |
6429 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000 |
6430 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000 |
6431 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000 |
6432 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT0_CONTROL_DEFAULT 0x00000000 |
6433 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000 |
6434 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000 |
6435 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000 |
6436 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT1_CONTROL_DEFAULT 0x00000000 |
6437 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000 |
6438 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000 |
6439 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000 |
6440 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT2_CONTROL_DEFAULT 0x00000000 |
6441 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000 |
6442 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000 |
6443 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000 |
6444 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT3_CONTROL_DEFAULT 0x00000000 |
6445 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT4_ADDR_LO_DEFAULT 0x00000000 |
6446 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT4_ADDR_HI_DEFAULT 0x00000000 |
6447 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT4_MSG_DATA_DEFAULT 0x00000000 |
6448 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT4_CONTROL_DEFAULT 0x00000000 |
6449 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT5_ADDR_LO_DEFAULT 0x00000000 |
6450 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT5_ADDR_HI_DEFAULT 0x00000000 |
6451 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT5_MSG_DATA_DEFAULT 0x00000000 |
6452 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT5_CONTROL_DEFAULT 0x00000000 |
6453 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT6_ADDR_LO_DEFAULT 0x00000000 |
6454 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT6_ADDR_HI_DEFAULT 0x00000000 |
6455 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT6_MSG_DATA_DEFAULT 0x00000000 |
6456 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT6_CONTROL_DEFAULT 0x00000000 |
6457 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT7_ADDR_LO_DEFAULT 0x00000000 |
6458 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT7_ADDR_HI_DEFAULT 0x00000000 |
6459 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT7_MSG_DATA_DEFAULT 0x00000000 |
6460 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT7_CONTROL_DEFAULT 0x00000000 |
6461 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT8_ADDR_LO_DEFAULT 0x00000000 |
6462 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT8_ADDR_HI_DEFAULT 0x00000000 |
6463 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT8_MSG_DATA_DEFAULT 0x00000000 |
6464 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT8_CONTROL_DEFAULT 0x00000000 |
6465 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT9_ADDR_LO_DEFAULT 0x00000000 |
6466 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT9_ADDR_HI_DEFAULT 0x00000000 |
6467 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT9_MSG_DATA_DEFAULT 0x00000000 |
6468 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT9_CONTROL_DEFAULT 0x00000000 |
6469 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT10_ADDR_LO_DEFAULT 0x00000000 |
6470 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT10_ADDR_HI_DEFAULT 0x00000000 |
6471 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT10_MSG_DATA_DEFAULT 0x00000000 |
6472 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT10_CONTROL_DEFAULT 0x00000000 |
6473 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT11_ADDR_LO_DEFAULT 0x00000000 |
6474 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT11_ADDR_HI_DEFAULT 0x00000000 |
6475 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT11_MSG_DATA_DEFAULT 0x00000000 |
6476 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT11_CONTROL_DEFAULT 0x00000000 |
6477 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT12_ADDR_LO_DEFAULT 0x00000000 |
6478 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT12_ADDR_HI_DEFAULT 0x00000000 |
6479 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT12_MSG_DATA_DEFAULT 0x00000000 |
6480 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT12_CONTROL_DEFAULT 0x00000000 |
6481 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT13_ADDR_LO_DEFAULT 0x00000000 |
6482 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT13_ADDR_HI_DEFAULT 0x00000000 |
6483 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT13_MSG_DATA_DEFAULT 0x00000000 |
6484 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT13_CONTROL_DEFAULT 0x00000000 |
6485 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT14_ADDR_LO_DEFAULT 0x00000000 |
6486 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT14_ADDR_HI_DEFAULT 0x00000000 |
6487 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT14_MSG_DATA_DEFAULT 0x00000000 |
6488 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT14_CONTROL_DEFAULT 0x00000000 |
6489 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT15_ADDR_LO_DEFAULT 0x00000000 |
6490 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT15_ADDR_HI_DEFAULT 0x00000000 |
6491 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT15_MSG_DATA_DEFAULT 0x00000000 |
6492 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT15_CONTROL_DEFAULT 0x00000000 |
6493 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT16_ADDR_LO_DEFAULT 0x00000000 |
6494 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT16_ADDR_HI_DEFAULT 0x00000000 |
6495 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT16_MSG_DATA_DEFAULT 0x00000000 |
6496 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT16_CONTROL_DEFAULT 0x00000000 |
6497 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT17_ADDR_LO_DEFAULT 0x00000000 |
6498 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT17_ADDR_HI_DEFAULT 0x00000000 |
6499 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT17_MSG_DATA_DEFAULT 0x00000000 |
6500 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT17_CONTROL_DEFAULT 0x00000000 |
6501 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT18_ADDR_LO_DEFAULT 0x00000000 |
6502 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT18_ADDR_HI_DEFAULT 0x00000000 |
6503 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT18_MSG_DATA_DEFAULT 0x00000000 |
6504 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT18_CONTROL_DEFAULT 0x00000000 |
6505 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT19_ADDR_LO_DEFAULT 0x00000000 |
6506 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT19_ADDR_HI_DEFAULT 0x00000000 |
6507 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT19_MSG_DATA_DEFAULT 0x00000000 |
6508 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT19_CONTROL_DEFAULT 0x00000000 |
6509 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT20_ADDR_LO_DEFAULT 0x00000000 |
6510 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT20_ADDR_HI_DEFAULT 0x00000000 |
6511 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT20_MSG_DATA_DEFAULT 0x00000000 |
6512 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT20_CONTROL_DEFAULT 0x00000000 |
6513 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT21_ADDR_LO_DEFAULT 0x00000000 |
6514 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT21_ADDR_HI_DEFAULT 0x00000000 |
6515 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT21_MSG_DATA_DEFAULT 0x00000000 |
6516 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT21_CONTROL_DEFAULT 0x00000000 |
6517 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT22_ADDR_LO_DEFAULT 0x00000000 |
6518 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT22_ADDR_HI_DEFAULT 0x00000000 |
6519 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT22_MSG_DATA_DEFAULT 0x00000000 |
6520 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT22_CONTROL_DEFAULT 0x00000000 |
6521 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT23_ADDR_LO_DEFAULT 0x00000000 |
6522 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT23_ADDR_HI_DEFAULT 0x00000000 |
6523 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT23_MSG_DATA_DEFAULT 0x00000000 |
6524 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT23_CONTROL_DEFAULT 0x00000000 |
6525 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT24_ADDR_LO_DEFAULT 0x00000000 |
6526 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT24_ADDR_HI_DEFAULT 0x00000000 |
6527 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT24_MSG_DATA_DEFAULT 0x00000000 |
6528 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT24_CONTROL_DEFAULT 0x00000000 |
6529 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT25_ADDR_LO_DEFAULT 0x00000000 |
6530 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT25_ADDR_HI_DEFAULT 0x00000000 |
6531 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT25_MSG_DATA_DEFAULT 0x00000000 |
6532 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT25_CONTROL_DEFAULT 0x00000000 |
6533 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT26_ADDR_LO_DEFAULT 0x00000000 |
6534 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT26_ADDR_HI_DEFAULT 0x00000000 |
6535 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT26_MSG_DATA_DEFAULT 0x00000000 |
6536 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT26_CONTROL_DEFAULT 0x00000000 |
6537 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT27_ADDR_LO_DEFAULT 0x00000000 |
6538 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT27_ADDR_HI_DEFAULT 0x00000000 |
6539 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT27_MSG_DATA_DEFAULT 0x00000000 |
6540 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT27_CONTROL_DEFAULT 0x00000000 |
6541 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT28_ADDR_LO_DEFAULT 0x00000000 |
6542 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT28_ADDR_HI_DEFAULT 0x00000000 |
6543 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT28_MSG_DATA_DEFAULT 0x00000000 |
6544 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT28_CONTROL_DEFAULT 0x00000000 |
6545 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT29_ADDR_LO_DEFAULT 0x00000000 |
6546 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT29_ADDR_HI_DEFAULT 0x00000000 |
6547 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT29_MSG_DATA_DEFAULT 0x00000000 |
6548 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT29_CONTROL_DEFAULT 0x00000000 |
6549 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT30_ADDR_LO_DEFAULT 0x00000000 |
6550 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT30_ADDR_HI_DEFAULT 0x00000000 |
6551 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT30_MSG_DATA_DEFAULT 0x00000000 |
6552 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT30_CONTROL_DEFAULT 0x00000000 |
6553 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT31_ADDR_LO_DEFAULT 0x00000000 |
6554 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT31_ADDR_HI_DEFAULT 0x00000000 |
6555 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT31_MSG_DATA_DEFAULT 0x00000000 |
6556 | #define smnPCIEMSIX_PSP_PCIEMSIX_VECT31_CONTROL_DEFAULT 0x00000000 |
6557 | |
6558 | |
6559 | // addressBlock: nbio_nbif0_pciemsix_usb3_0_MSIXTDEC |
6560 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000 |
6561 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000 |
6562 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000 |
6563 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT0_CONTROL_DEFAULT 0x00000000 |
6564 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000 |
6565 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000 |
6566 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000 |
6567 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT1_CONTROL_DEFAULT 0x00000000 |
6568 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000 |
6569 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000 |
6570 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000 |
6571 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT2_CONTROL_DEFAULT 0x00000000 |
6572 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000 |
6573 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000 |
6574 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000 |
6575 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT3_CONTROL_DEFAULT 0x00000000 |
6576 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT4_ADDR_LO_DEFAULT 0x00000000 |
6577 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT4_ADDR_HI_DEFAULT 0x00000000 |
6578 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT4_MSG_DATA_DEFAULT 0x00000000 |
6579 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT4_CONTROL_DEFAULT 0x00000000 |
6580 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT5_ADDR_LO_DEFAULT 0x00000000 |
6581 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT5_ADDR_HI_DEFAULT 0x00000000 |
6582 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT5_MSG_DATA_DEFAULT 0x00000000 |
6583 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT5_CONTROL_DEFAULT 0x00000000 |
6584 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT6_ADDR_LO_DEFAULT 0x00000000 |
6585 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT6_ADDR_HI_DEFAULT 0x00000000 |
6586 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT6_MSG_DATA_DEFAULT 0x00000000 |
6587 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT6_CONTROL_DEFAULT 0x00000000 |
6588 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT7_ADDR_LO_DEFAULT 0x00000000 |
6589 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT7_ADDR_HI_DEFAULT 0x00000000 |
6590 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT7_MSG_DATA_DEFAULT 0x00000000 |
6591 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT7_CONTROL_DEFAULT 0x00000000 |
6592 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT8_ADDR_LO_DEFAULT 0x00000000 |
6593 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT8_ADDR_HI_DEFAULT 0x00000000 |
6594 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT8_MSG_DATA_DEFAULT 0x00000000 |
6595 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT8_CONTROL_DEFAULT 0x00000000 |
6596 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT9_ADDR_LO_DEFAULT 0x00000000 |
6597 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT9_ADDR_HI_DEFAULT 0x00000000 |
6598 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT9_MSG_DATA_DEFAULT 0x00000000 |
6599 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT9_CONTROL_DEFAULT 0x00000000 |
6600 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT10_ADDR_LO_DEFAULT 0x00000000 |
6601 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT10_ADDR_HI_DEFAULT 0x00000000 |
6602 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT10_MSG_DATA_DEFAULT 0x00000000 |
6603 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT10_CONTROL_DEFAULT 0x00000000 |
6604 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT11_ADDR_LO_DEFAULT 0x00000000 |
6605 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT11_ADDR_HI_DEFAULT 0x00000000 |
6606 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT11_MSG_DATA_DEFAULT 0x00000000 |
6607 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT11_CONTROL_DEFAULT 0x00000000 |
6608 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT12_ADDR_LO_DEFAULT 0x00000000 |
6609 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT12_ADDR_HI_DEFAULT 0x00000000 |
6610 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT12_MSG_DATA_DEFAULT 0x00000000 |
6611 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT12_CONTROL_DEFAULT 0x00000000 |
6612 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT13_ADDR_LO_DEFAULT 0x00000000 |
6613 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT13_ADDR_HI_DEFAULT 0x00000000 |
6614 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT13_MSG_DATA_DEFAULT 0x00000000 |
6615 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT13_CONTROL_DEFAULT 0x00000000 |
6616 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT14_ADDR_LO_DEFAULT 0x00000000 |
6617 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT14_ADDR_HI_DEFAULT 0x00000000 |
6618 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT14_MSG_DATA_DEFAULT 0x00000000 |
6619 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT14_CONTROL_DEFAULT 0x00000000 |
6620 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT15_ADDR_LO_DEFAULT 0x00000000 |
6621 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT15_ADDR_HI_DEFAULT 0x00000000 |
6622 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT15_MSG_DATA_DEFAULT 0x00000000 |
6623 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT15_CONTROL_DEFAULT 0x00000000 |
6624 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT16_ADDR_LO_DEFAULT 0x00000000 |
6625 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT16_ADDR_HI_DEFAULT 0x00000000 |
6626 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT16_MSG_DATA_DEFAULT 0x00000000 |
6627 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT16_CONTROL_DEFAULT 0x00000000 |
6628 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT17_ADDR_LO_DEFAULT 0x00000000 |
6629 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT17_ADDR_HI_DEFAULT 0x00000000 |
6630 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT17_MSG_DATA_DEFAULT 0x00000000 |
6631 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT17_CONTROL_DEFAULT 0x00000000 |
6632 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT18_ADDR_LO_DEFAULT 0x00000000 |
6633 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT18_ADDR_HI_DEFAULT 0x00000000 |
6634 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT18_MSG_DATA_DEFAULT 0x00000000 |
6635 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT18_CONTROL_DEFAULT 0x00000000 |
6636 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT19_ADDR_LO_DEFAULT 0x00000000 |
6637 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT19_ADDR_HI_DEFAULT 0x00000000 |
6638 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT19_MSG_DATA_DEFAULT 0x00000000 |
6639 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT19_CONTROL_DEFAULT 0x00000000 |
6640 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT20_ADDR_LO_DEFAULT 0x00000000 |
6641 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT20_ADDR_HI_DEFAULT 0x00000000 |
6642 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT20_MSG_DATA_DEFAULT 0x00000000 |
6643 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT20_CONTROL_DEFAULT 0x00000000 |
6644 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT21_ADDR_LO_DEFAULT 0x00000000 |
6645 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT21_ADDR_HI_DEFAULT 0x00000000 |
6646 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT21_MSG_DATA_DEFAULT 0x00000000 |
6647 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT21_CONTROL_DEFAULT 0x00000000 |
6648 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT22_ADDR_LO_DEFAULT 0x00000000 |
6649 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT22_ADDR_HI_DEFAULT 0x00000000 |
6650 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT22_MSG_DATA_DEFAULT 0x00000000 |
6651 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT22_CONTROL_DEFAULT 0x00000000 |
6652 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT23_ADDR_LO_DEFAULT 0x00000000 |
6653 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT23_ADDR_HI_DEFAULT 0x00000000 |
6654 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT23_MSG_DATA_DEFAULT 0x00000000 |
6655 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT23_CONTROL_DEFAULT 0x00000000 |
6656 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT24_ADDR_LO_DEFAULT 0x00000000 |
6657 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT24_ADDR_HI_DEFAULT 0x00000000 |
6658 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT24_MSG_DATA_DEFAULT 0x00000000 |
6659 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT24_CONTROL_DEFAULT 0x00000000 |
6660 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT25_ADDR_LO_DEFAULT 0x00000000 |
6661 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT25_ADDR_HI_DEFAULT 0x00000000 |
6662 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT25_MSG_DATA_DEFAULT 0x00000000 |
6663 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT25_CONTROL_DEFAULT 0x00000000 |
6664 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT26_ADDR_LO_DEFAULT 0x00000000 |
6665 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT26_ADDR_HI_DEFAULT 0x00000000 |
6666 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT26_MSG_DATA_DEFAULT 0x00000000 |
6667 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT26_CONTROL_DEFAULT 0x00000000 |
6668 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT27_ADDR_LO_DEFAULT 0x00000000 |
6669 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT27_ADDR_HI_DEFAULT 0x00000000 |
6670 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT27_MSG_DATA_DEFAULT 0x00000000 |
6671 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT27_CONTROL_DEFAULT 0x00000000 |
6672 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT28_ADDR_LO_DEFAULT 0x00000000 |
6673 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT28_ADDR_HI_DEFAULT 0x00000000 |
6674 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT28_MSG_DATA_DEFAULT 0x00000000 |
6675 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT28_CONTROL_DEFAULT 0x00000000 |
6676 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT29_ADDR_LO_DEFAULT 0x00000000 |
6677 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT29_ADDR_HI_DEFAULT 0x00000000 |
6678 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT29_MSG_DATA_DEFAULT 0x00000000 |
6679 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT29_CONTROL_DEFAULT 0x00000000 |
6680 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT30_ADDR_LO_DEFAULT 0x00000000 |
6681 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT30_ADDR_HI_DEFAULT 0x00000000 |
6682 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT30_MSG_DATA_DEFAULT 0x00000000 |
6683 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT30_CONTROL_DEFAULT 0x00000000 |
6684 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT31_ADDR_LO_DEFAULT 0x00000000 |
6685 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT31_ADDR_HI_DEFAULT 0x00000000 |
6686 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT31_MSG_DATA_DEFAULT 0x00000000 |
6687 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_VECT31_CONTROL_DEFAULT 0x00000000 |
6688 | |
6689 | |
6690 | // addressBlock: nbio_nbif0_pciemsix_usb3_1_MSIXTDEC |
6691 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000 |
6692 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000 |
6693 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000 |
6694 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT0_CONTROL_DEFAULT 0x00000000 |
6695 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000 |
6696 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000 |
6697 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000 |
6698 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT1_CONTROL_DEFAULT 0x00000000 |
6699 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000 |
6700 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000 |
6701 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000 |
6702 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT2_CONTROL_DEFAULT 0x00000000 |
6703 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000 |
6704 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000 |
6705 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000 |
6706 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT3_CONTROL_DEFAULT 0x00000000 |
6707 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT4_ADDR_LO_DEFAULT 0x00000000 |
6708 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT4_ADDR_HI_DEFAULT 0x00000000 |
6709 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT4_MSG_DATA_DEFAULT 0x00000000 |
6710 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT4_CONTROL_DEFAULT 0x00000000 |
6711 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT5_ADDR_LO_DEFAULT 0x00000000 |
6712 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT5_ADDR_HI_DEFAULT 0x00000000 |
6713 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT5_MSG_DATA_DEFAULT 0x00000000 |
6714 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT5_CONTROL_DEFAULT 0x00000000 |
6715 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT6_ADDR_LO_DEFAULT 0x00000000 |
6716 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT6_ADDR_HI_DEFAULT 0x00000000 |
6717 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT6_MSG_DATA_DEFAULT 0x00000000 |
6718 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT6_CONTROL_DEFAULT 0x00000000 |
6719 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT7_ADDR_LO_DEFAULT 0x00000000 |
6720 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT7_ADDR_HI_DEFAULT 0x00000000 |
6721 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT7_MSG_DATA_DEFAULT 0x00000000 |
6722 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT7_CONTROL_DEFAULT 0x00000000 |
6723 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT8_ADDR_LO_DEFAULT 0x00000000 |
6724 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT8_ADDR_HI_DEFAULT 0x00000000 |
6725 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT8_MSG_DATA_DEFAULT 0x00000000 |
6726 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT8_CONTROL_DEFAULT 0x00000000 |
6727 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT9_ADDR_LO_DEFAULT 0x00000000 |
6728 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT9_ADDR_HI_DEFAULT 0x00000000 |
6729 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT9_MSG_DATA_DEFAULT 0x00000000 |
6730 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT9_CONTROL_DEFAULT 0x00000000 |
6731 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT10_ADDR_LO_DEFAULT 0x00000000 |
6732 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT10_ADDR_HI_DEFAULT 0x00000000 |
6733 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT10_MSG_DATA_DEFAULT 0x00000000 |
6734 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT10_CONTROL_DEFAULT 0x00000000 |
6735 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT11_ADDR_LO_DEFAULT 0x00000000 |
6736 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT11_ADDR_HI_DEFAULT 0x00000000 |
6737 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT11_MSG_DATA_DEFAULT 0x00000000 |
6738 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT11_CONTROL_DEFAULT 0x00000000 |
6739 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT12_ADDR_LO_DEFAULT 0x00000000 |
6740 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT12_ADDR_HI_DEFAULT 0x00000000 |
6741 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT12_MSG_DATA_DEFAULT 0x00000000 |
6742 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT12_CONTROL_DEFAULT 0x00000000 |
6743 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT13_ADDR_LO_DEFAULT 0x00000000 |
6744 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT13_ADDR_HI_DEFAULT 0x00000000 |
6745 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT13_MSG_DATA_DEFAULT 0x00000000 |
6746 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT13_CONTROL_DEFAULT 0x00000000 |
6747 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT14_ADDR_LO_DEFAULT 0x00000000 |
6748 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT14_ADDR_HI_DEFAULT 0x00000000 |
6749 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT14_MSG_DATA_DEFAULT 0x00000000 |
6750 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT14_CONTROL_DEFAULT 0x00000000 |
6751 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT15_ADDR_LO_DEFAULT 0x00000000 |
6752 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT15_ADDR_HI_DEFAULT 0x00000000 |
6753 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT15_MSG_DATA_DEFAULT 0x00000000 |
6754 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT15_CONTROL_DEFAULT 0x00000000 |
6755 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT16_ADDR_LO_DEFAULT 0x00000000 |
6756 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT16_ADDR_HI_DEFAULT 0x00000000 |
6757 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT16_MSG_DATA_DEFAULT 0x00000000 |
6758 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT16_CONTROL_DEFAULT 0x00000000 |
6759 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT17_ADDR_LO_DEFAULT 0x00000000 |
6760 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT17_ADDR_HI_DEFAULT 0x00000000 |
6761 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT17_MSG_DATA_DEFAULT 0x00000000 |
6762 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT17_CONTROL_DEFAULT 0x00000000 |
6763 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT18_ADDR_LO_DEFAULT 0x00000000 |
6764 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT18_ADDR_HI_DEFAULT 0x00000000 |
6765 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT18_MSG_DATA_DEFAULT 0x00000000 |
6766 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT18_CONTROL_DEFAULT 0x00000000 |
6767 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT19_ADDR_LO_DEFAULT 0x00000000 |
6768 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT19_ADDR_HI_DEFAULT 0x00000000 |
6769 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT19_MSG_DATA_DEFAULT 0x00000000 |
6770 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT19_CONTROL_DEFAULT 0x00000000 |
6771 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT20_ADDR_LO_DEFAULT 0x00000000 |
6772 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT20_ADDR_HI_DEFAULT 0x00000000 |
6773 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT20_MSG_DATA_DEFAULT 0x00000000 |
6774 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT20_CONTROL_DEFAULT 0x00000000 |
6775 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT21_ADDR_LO_DEFAULT 0x00000000 |
6776 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT21_ADDR_HI_DEFAULT 0x00000000 |
6777 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT21_MSG_DATA_DEFAULT 0x00000000 |
6778 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT21_CONTROL_DEFAULT 0x00000000 |
6779 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT22_ADDR_LO_DEFAULT 0x00000000 |
6780 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT22_ADDR_HI_DEFAULT 0x00000000 |
6781 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT22_MSG_DATA_DEFAULT 0x00000000 |
6782 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT22_CONTROL_DEFAULT 0x00000000 |
6783 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT23_ADDR_LO_DEFAULT 0x00000000 |
6784 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT23_ADDR_HI_DEFAULT 0x00000000 |
6785 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT23_MSG_DATA_DEFAULT 0x00000000 |
6786 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT23_CONTROL_DEFAULT 0x00000000 |
6787 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT24_ADDR_LO_DEFAULT 0x00000000 |
6788 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT24_ADDR_HI_DEFAULT 0x00000000 |
6789 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT24_MSG_DATA_DEFAULT 0x00000000 |
6790 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT24_CONTROL_DEFAULT 0x00000000 |
6791 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT25_ADDR_LO_DEFAULT 0x00000000 |
6792 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT25_ADDR_HI_DEFAULT 0x00000000 |
6793 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT25_MSG_DATA_DEFAULT 0x00000000 |
6794 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT25_CONTROL_DEFAULT 0x00000000 |
6795 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT26_ADDR_LO_DEFAULT 0x00000000 |
6796 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT26_ADDR_HI_DEFAULT 0x00000000 |
6797 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT26_MSG_DATA_DEFAULT 0x00000000 |
6798 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT26_CONTROL_DEFAULT 0x00000000 |
6799 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT27_ADDR_LO_DEFAULT 0x00000000 |
6800 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT27_ADDR_HI_DEFAULT 0x00000000 |
6801 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT27_MSG_DATA_DEFAULT 0x00000000 |
6802 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT27_CONTROL_DEFAULT 0x00000000 |
6803 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT28_ADDR_LO_DEFAULT 0x00000000 |
6804 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT28_ADDR_HI_DEFAULT 0x00000000 |
6805 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT28_MSG_DATA_DEFAULT 0x00000000 |
6806 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT28_CONTROL_DEFAULT 0x00000000 |
6807 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT29_ADDR_LO_DEFAULT 0x00000000 |
6808 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT29_ADDR_HI_DEFAULT 0x00000000 |
6809 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT29_MSG_DATA_DEFAULT 0x00000000 |
6810 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT29_CONTROL_DEFAULT 0x00000000 |
6811 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT30_ADDR_LO_DEFAULT 0x00000000 |
6812 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT30_ADDR_HI_DEFAULT 0x00000000 |
6813 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT30_MSG_DATA_DEFAULT 0x00000000 |
6814 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT30_CONTROL_DEFAULT 0x00000000 |
6815 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT31_ADDR_LO_DEFAULT 0x00000000 |
6816 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT31_ADDR_HI_DEFAULT 0x00000000 |
6817 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT31_MSG_DATA_DEFAULT 0x00000000 |
6818 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_VECT31_CONTROL_DEFAULT 0x00000000 |
6819 | |
6820 | |
6821 | // addressBlock: nbio_nbif0_pciemsix_mp2_MSIXTDEC |
6822 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000 |
6823 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000 |
6824 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000 |
6825 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT0_CONTROL_DEFAULT 0x00000000 |
6826 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000 |
6827 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000 |
6828 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000 |
6829 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT1_CONTROL_DEFAULT 0x00000000 |
6830 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000 |
6831 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000 |
6832 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000 |
6833 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT2_CONTROL_DEFAULT 0x00000000 |
6834 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000 |
6835 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000 |
6836 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000 |
6837 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT3_CONTROL_DEFAULT 0x00000000 |
6838 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT4_ADDR_LO_DEFAULT 0x00000000 |
6839 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT4_ADDR_HI_DEFAULT 0x00000000 |
6840 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT4_MSG_DATA_DEFAULT 0x00000000 |
6841 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT4_CONTROL_DEFAULT 0x00000000 |
6842 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT5_ADDR_LO_DEFAULT 0x00000000 |
6843 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT5_ADDR_HI_DEFAULT 0x00000000 |
6844 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT5_MSG_DATA_DEFAULT 0x00000000 |
6845 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT5_CONTROL_DEFAULT 0x00000000 |
6846 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT6_ADDR_LO_DEFAULT 0x00000000 |
6847 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT6_ADDR_HI_DEFAULT 0x00000000 |
6848 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT6_MSG_DATA_DEFAULT 0x00000000 |
6849 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT6_CONTROL_DEFAULT 0x00000000 |
6850 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT7_ADDR_LO_DEFAULT 0x00000000 |
6851 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT7_ADDR_HI_DEFAULT 0x00000000 |
6852 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT7_MSG_DATA_DEFAULT 0x00000000 |
6853 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT7_CONTROL_DEFAULT 0x00000000 |
6854 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT8_ADDR_LO_DEFAULT 0x00000000 |
6855 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT8_ADDR_HI_DEFAULT 0x00000000 |
6856 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT8_MSG_DATA_DEFAULT 0x00000000 |
6857 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT8_CONTROL_DEFAULT 0x00000000 |
6858 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT9_ADDR_LO_DEFAULT 0x00000000 |
6859 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT9_ADDR_HI_DEFAULT 0x00000000 |
6860 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT9_MSG_DATA_DEFAULT 0x00000000 |
6861 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT9_CONTROL_DEFAULT 0x00000000 |
6862 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT10_ADDR_LO_DEFAULT 0x00000000 |
6863 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT10_ADDR_HI_DEFAULT 0x00000000 |
6864 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT10_MSG_DATA_DEFAULT 0x00000000 |
6865 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT10_CONTROL_DEFAULT 0x00000000 |
6866 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT11_ADDR_LO_DEFAULT 0x00000000 |
6867 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT11_ADDR_HI_DEFAULT 0x00000000 |
6868 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT11_MSG_DATA_DEFAULT 0x00000000 |
6869 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT11_CONTROL_DEFAULT 0x00000000 |
6870 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT12_ADDR_LO_DEFAULT 0x00000000 |
6871 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT12_ADDR_HI_DEFAULT 0x00000000 |
6872 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT12_MSG_DATA_DEFAULT 0x00000000 |
6873 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT12_CONTROL_DEFAULT 0x00000000 |
6874 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT13_ADDR_LO_DEFAULT 0x00000000 |
6875 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT13_ADDR_HI_DEFAULT 0x00000000 |
6876 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT13_MSG_DATA_DEFAULT 0x00000000 |
6877 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT13_CONTROL_DEFAULT 0x00000000 |
6878 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT14_ADDR_LO_DEFAULT 0x00000000 |
6879 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT14_ADDR_HI_DEFAULT 0x00000000 |
6880 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT14_MSG_DATA_DEFAULT 0x00000000 |
6881 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT14_CONTROL_DEFAULT 0x00000000 |
6882 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT15_ADDR_LO_DEFAULT 0x00000000 |
6883 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT15_ADDR_HI_DEFAULT 0x00000000 |
6884 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT15_MSG_DATA_DEFAULT 0x00000000 |
6885 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT15_CONTROL_DEFAULT 0x00000000 |
6886 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT16_ADDR_LO_DEFAULT 0x00000000 |
6887 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT16_ADDR_HI_DEFAULT 0x00000000 |
6888 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT16_MSG_DATA_DEFAULT 0x00000000 |
6889 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT16_CONTROL_DEFAULT 0x00000000 |
6890 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT17_ADDR_LO_DEFAULT 0x00000000 |
6891 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT17_ADDR_HI_DEFAULT 0x00000000 |
6892 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT17_MSG_DATA_DEFAULT 0x00000000 |
6893 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT17_CONTROL_DEFAULT 0x00000000 |
6894 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT18_ADDR_LO_DEFAULT 0x00000000 |
6895 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT18_ADDR_HI_DEFAULT 0x00000000 |
6896 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT18_MSG_DATA_DEFAULT 0x00000000 |
6897 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT18_CONTROL_DEFAULT 0x00000000 |
6898 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT19_ADDR_LO_DEFAULT 0x00000000 |
6899 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT19_ADDR_HI_DEFAULT 0x00000000 |
6900 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT19_MSG_DATA_DEFAULT 0x00000000 |
6901 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT19_CONTROL_DEFAULT 0x00000000 |
6902 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT20_ADDR_LO_DEFAULT 0x00000000 |
6903 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT20_ADDR_HI_DEFAULT 0x00000000 |
6904 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT20_MSG_DATA_DEFAULT 0x00000000 |
6905 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT20_CONTROL_DEFAULT 0x00000000 |
6906 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT21_ADDR_LO_DEFAULT 0x00000000 |
6907 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT21_ADDR_HI_DEFAULT 0x00000000 |
6908 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT21_MSG_DATA_DEFAULT 0x00000000 |
6909 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT21_CONTROL_DEFAULT 0x00000000 |
6910 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT22_ADDR_LO_DEFAULT 0x00000000 |
6911 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT22_ADDR_HI_DEFAULT 0x00000000 |
6912 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT22_MSG_DATA_DEFAULT 0x00000000 |
6913 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT22_CONTROL_DEFAULT 0x00000000 |
6914 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT23_ADDR_LO_DEFAULT 0x00000000 |
6915 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT23_ADDR_HI_DEFAULT 0x00000000 |
6916 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT23_MSG_DATA_DEFAULT 0x00000000 |
6917 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT23_CONTROL_DEFAULT 0x00000000 |
6918 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT24_ADDR_LO_DEFAULT 0x00000000 |
6919 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT24_ADDR_HI_DEFAULT 0x00000000 |
6920 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT24_MSG_DATA_DEFAULT 0x00000000 |
6921 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT24_CONTROL_DEFAULT 0x00000000 |
6922 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT25_ADDR_LO_DEFAULT 0x00000000 |
6923 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT25_ADDR_HI_DEFAULT 0x00000000 |
6924 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT25_MSG_DATA_DEFAULT 0x00000000 |
6925 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT25_CONTROL_DEFAULT 0x00000000 |
6926 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT26_ADDR_LO_DEFAULT 0x00000000 |
6927 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT26_ADDR_HI_DEFAULT 0x00000000 |
6928 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT26_MSG_DATA_DEFAULT 0x00000000 |
6929 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT26_CONTROL_DEFAULT 0x00000000 |
6930 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT27_ADDR_LO_DEFAULT 0x00000000 |
6931 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT27_ADDR_HI_DEFAULT 0x00000000 |
6932 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT27_MSG_DATA_DEFAULT 0x00000000 |
6933 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT27_CONTROL_DEFAULT 0x00000000 |
6934 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT28_ADDR_LO_DEFAULT 0x00000000 |
6935 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT28_ADDR_HI_DEFAULT 0x00000000 |
6936 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT28_MSG_DATA_DEFAULT 0x00000000 |
6937 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT28_CONTROL_DEFAULT 0x00000000 |
6938 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT29_ADDR_LO_DEFAULT 0x00000000 |
6939 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT29_ADDR_HI_DEFAULT 0x00000000 |
6940 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT29_MSG_DATA_DEFAULT 0x00000000 |
6941 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT29_CONTROL_DEFAULT 0x00000000 |
6942 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT30_ADDR_LO_DEFAULT 0x00000000 |
6943 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT30_ADDR_HI_DEFAULT 0x00000000 |
6944 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT30_MSG_DATA_DEFAULT 0x00000000 |
6945 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT30_CONTROL_DEFAULT 0x00000000 |
6946 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT31_ADDR_LO_DEFAULT 0x00000000 |
6947 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT31_ADDR_HI_DEFAULT 0x00000000 |
6948 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT31_MSG_DATA_DEFAULT 0x00000000 |
6949 | #define smnPCIEMSIX_MP2_PCIEMSIX_VECT31_CONTROL_DEFAULT 0x00000000 |
6950 | |
6951 | |
6952 | // addressBlock: nbio_nbif0_pciemsix_gbe0_MSIXTDEC |
6953 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000 |
6954 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000 |
6955 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000 |
6956 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT0_CONTROL_DEFAULT 0x00000000 |
6957 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000 |
6958 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000 |
6959 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000 |
6960 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT1_CONTROL_DEFAULT 0x00000000 |
6961 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000 |
6962 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000 |
6963 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000 |
6964 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT2_CONTROL_DEFAULT 0x00000000 |
6965 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000 |
6966 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000 |
6967 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000 |
6968 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT3_CONTROL_DEFAULT 0x00000000 |
6969 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT4_ADDR_LO_DEFAULT 0x00000000 |
6970 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT4_ADDR_HI_DEFAULT 0x00000000 |
6971 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT4_MSG_DATA_DEFAULT 0x00000000 |
6972 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT4_CONTROL_DEFAULT 0x00000000 |
6973 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT5_ADDR_LO_DEFAULT 0x00000000 |
6974 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT5_ADDR_HI_DEFAULT 0x00000000 |
6975 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT5_MSG_DATA_DEFAULT 0x00000000 |
6976 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT5_CONTROL_DEFAULT 0x00000000 |
6977 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT6_ADDR_LO_DEFAULT 0x00000000 |
6978 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT6_ADDR_HI_DEFAULT 0x00000000 |
6979 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT6_MSG_DATA_DEFAULT 0x00000000 |
6980 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT6_CONTROL_DEFAULT 0x00000000 |
6981 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT7_ADDR_LO_DEFAULT 0x00000000 |
6982 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT7_ADDR_HI_DEFAULT 0x00000000 |
6983 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT7_MSG_DATA_DEFAULT 0x00000000 |
6984 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT7_CONTROL_DEFAULT 0x00000000 |
6985 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT8_ADDR_LO_DEFAULT 0x00000000 |
6986 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT8_ADDR_HI_DEFAULT 0x00000000 |
6987 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT8_MSG_DATA_DEFAULT 0x00000000 |
6988 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT8_CONTROL_DEFAULT 0x00000000 |
6989 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT9_ADDR_LO_DEFAULT 0x00000000 |
6990 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT9_ADDR_HI_DEFAULT 0x00000000 |
6991 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT9_MSG_DATA_DEFAULT 0x00000000 |
6992 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT9_CONTROL_DEFAULT 0x00000000 |
6993 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT10_ADDR_LO_DEFAULT 0x00000000 |
6994 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT10_ADDR_HI_DEFAULT 0x00000000 |
6995 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT10_MSG_DATA_DEFAULT 0x00000000 |
6996 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT10_CONTROL_DEFAULT 0x00000000 |
6997 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT11_ADDR_LO_DEFAULT 0x00000000 |
6998 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT11_ADDR_HI_DEFAULT 0x00000000 |
6999 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT11_MSG_DATA_DEFAULT 0x00000000 |
7000 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT11_CONTROL_DEFAULT 0x00000000 |
7001 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT12_ADDR_LO_DEFAULT 0x00000000 |
7002 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT12_ADDR_HI_DEFAULT 0x00000000 |
7003 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT12_MSG_DATA_DEFAULT 0x00000000 |
7004 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT12_CONTROL_DEFAULT 0x00000000 |
7005 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT13_ADDR_LO_DEFAULT 0x00000000 |
7006 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT13_ADDR_HI_DEFAULT 0x00000000 |
7007 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT13_MSG_DATA_DEFAULT 0x00000000 |
7008 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT13_CONTROL_DEFAULT 0x00000000 |
7009 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT14_ADDR_LO_DEFAULT 0x00000000 |
7010 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT14_ADDR_HI_DEFAULT 0x00000000 |
7011 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT14_MSG_DATA_DEFAULT 0x00000000 |
7012 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT14_CONTROL_DEFAULT 0x00000000 |
7013 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT15_ADDR_LO_DEFAULT 0x00000000 |
7014 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT15_ADDR_HI_DEFAULT 0x00000000 |
7015 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT15_MSG_DATA_DEFAULT 0x00000000 |
7016 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT15_CONTROL_DEFAULT 0x00000000 |
7017 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT16_ADDR_LO_DEFAULT 0x00000000 |
7018 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT16_ADDR_HI_DEFAULT 0x00000000 |
7019 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT16_MSG_DATA_DEFAULT 0x00000000 |
7020 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT16_CONTROL_DEFAULT 0x00000000 |
7021 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT17_ADDR_LO_DEFAULT 0x00000000 |
7022 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT17_ADDR_HI_DEFAULT 0x00000000 |
7023 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT17_MSG_DATA_DEFAULT 0x00000000 |
7024 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT17_CONTROL_DEFAULT 0x00000000 |
7025 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT18_ADDR_LO_DEFAULT 0x00000000 |
7026 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT18_ADDR_HI_DEFAULT 0x00000000 |
7027 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT18_MSG_DATA_DEFAULT 0x00000000 |
7028 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT18_CONTROL_DEFAULT 0x00000000 |
7029 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT19_ADDR_LO_DEFAULT 0x00000000 |
7030 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT19_ADDR_HI_DEFAULT 0x00000000 |
7031 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT19_MSG_DATA_DEFAULT 0x00000000 |
7032 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT19_CONTROL_DEFAULT 0x00000000 |
7033 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT20_ADDR_LO_DEFAULT 0x00000000 |
7034 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT20_ADDR_HI_DEFAULT 0x00000000 |
7035 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT20_MSG_DATA_DEFAULT 0x00000000 |
7036 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT20_CONTROL_DEFAULT 0x00000000 |
7037 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT21_ADDR_LO_DEFAULT 0x00000000 |
7038 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT21_ADDR_HI_DEFAULT 0x00000000 |
7039 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT21_MSG_DATA_DEFAULT 0x00000000 |
7040 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT21_CONTROL_DEFAULT 0x00000000 |
7041 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT22_ADDR_LO_DEFAULT 0x00000000 |
7042 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT22_ADDR_HI_DEFAULT 0x00000000 |
7043 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT22_MSG_DATA_DEFAULT 0x00000000 |
7044 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT22_CONTROL_DEFAULT 0x00000000 |
7045 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT23_ADDR_LO_DEFAULT 0x00000000 |
7046 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT23_ADDR_HI_DEFAULT 0x00000000 |
7047 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT23_MSG_DATA_DEFAULT 0x00000000 |
7048 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT23_CONTROL_DEFAULT 0x00000000 |
7049 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT24_ADDR_LO_DEFAULT 0x00000000 |
7050 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT24_ADDR_HI_DEFAULT 0x00000000 |
7051 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT24_MSG_DATA_DEFAULT 0x00000000 |
7052 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT24_CONTROL_DEFAULT 0x00000000 |
7053 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT25_ADDR_LO_DEFAULT 0x00000000 |
7054 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT25_ADDR_HI_DEFAULT 0x00000000 |
7055 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT25_MSG_DATA_DEFAULT 0x00000000 |
7056 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT25_CONTROL_DEFAULT 0x00000000 |
7057 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT26_ADDR_LO_DEFAULT 0x00000000 |
7058 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT26_ADDR_HI_DEFAULT 0x00000000 |
7059 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT26_MSG_DATA_DEFAULT 0x00000000 |
7060 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT26_CONTROL_DEFAULT 0x00000000 |
7061 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT27_ADDR_LO_DEFAULT 0x00000000 |
7062 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT27_ADDR_HI_DEFAULT 0x00000000 |
7063 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT27_MSG_DATA_DEFAULT 0x00000000 |
7064 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT27_CONTROL_DEFAULT 0x00000000 |
7065 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT28_ADDR_LO_DEFAULT 0x00000000 |
7066 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT28_ADDR_HI_DEFAULT 0x00000000 |
7067 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT28_MSG_DATA_DEFAULT 0x00000000 |
7068 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT28_CONTROL_DEFAULT 0x00000000 |
7069 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT29_ADDR_LO_DEFAULT 0x00000000 |
7070 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT29_ADDR_HI_DEFAULT 0x00000000 |
7071 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT29_MSG_DATA_DEFAULT 0x00000000 |
7072 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT29_CONTROL_DEFAULT 0x00000000 |
7073 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT30_ADDR_LO_DEFAULT 0x00000000 |
7074 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT30_ADDR_HI_DEFAULT 0x00000000 |
7075 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT30_MSG_DATA_DEFAULT 0x00000000 |
7076 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT30_CONTROL_DEFAULT 0x00000000 |
7077 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT31_ADDR_LO_DEFAULT 0x00000000 |
7078 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT31_ADDR_HI_DEFAULT 0x00000000 |
7079 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT31_MSG_DATA_DEFAULT 0x00000000 |
7080 | #define smnPCIEMSIX_GBE0_PCIEMSIX_VECT31_CONTROL_DEFAULT 0x00000000 |
7081 | |
7082 | |
7083 | // addressBlock: nbio_nbif0_pciemsix_gbe1_MSIXTDEC |
7084 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000 |
7085 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000 |
7086 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000 |
7087 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT0_CONTROL_DEFAULT 0x00000000 |
7088 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000 |
7089 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000 |
7090 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000 |
7091 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT1_CONTROL_DEFAULT 0x00000000 |
7092 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000 |
7093 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000 |
7094 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000 |
7095 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT2_CONTROL_DEFAULT 0x00000000 |
7096 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000 |
7097 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000 |
7098 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000 |
7099 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT3_CONTROL_DEFAULT 0x00000000 |
7100 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT4_ADDR_LO_DEFAULT 0x00000000 |
7101 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT4_ADDR_HI_DEFAULT 0x00000000 |
7102 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT4_MSG_DATA_DEFAULT 0x00000000 |
7103 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT4_CONTROL_DEFAULT 0x00000000 |
7104 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT5_ADDR_LO_DEFAULT 0x00000000 |
7105 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT5_ADDR_HI_DEFAULT 0x00000000 |
7106 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT5_MSG_DATA_DEFAULT 0x00000000 |
7107 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT5_CONTROL_DEFAULT 0x00000000 |
7108 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT6_ADDR_LO_DEFAULT 0x00000000 |
7109 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT6_ADDR_HI_DEFAULT 0x00000000 |
7110 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT6_MSG_DATA_DEFAULT 0x00000000 |
7111 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT6_CONTROL_DEFAULT 0x00000000 |
7112 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT7_ADDR_LO_DEFAULT 0x00000000 |
7113 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT7_ADDR_HI_DEFAULT 0x00000000 |
7114 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT7_MSG_DATA_DEFAULT 0x00000000 |
7115 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT7_CONTROL_DEFAULT 0x00000000 |
7116 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT8_ADDR_LO_DEFAULT 0x00000000 |
7117 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT8_ADDR_HI_DEFAULT 0x00000000 |
7118 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT8_MSG_DATA_DEFAULT 0x00000000 |
7119 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT8_CONTROL_DEFAULT 0x00000000 |
7120 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT9_ADDR_LO_DEFAULT 0x00000000 |
7121 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT9_ADDR_HI_DEFAULT 0x00000000 |
7122 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT9_MSG_DATA_DEFAULT 0x00000000 |
7123 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT9_CONTROL_DEFAULT 0x00000000 |
7124 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT10_ADDR_LO_DEFAULT 0x00000000 |
7125 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT10_ADDR_HI_DEFAULT 0x00000000 |
7126 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT10_MSG_DATA_DEFAULT 0x00000000 |
7127 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT10_CONTROL_DEFAULT 0x00000000 |
7128 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT11_ADDR_LO_DEFAULT 0x00000000 |
7129 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT11_ADDR_HI_DEFAULT 0x00000000 |
7130 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT11_MSG_DATA_DEFAULT 0x00000000 |
7131 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT11_CONTROL_DEFAULT 0x00000000 |
7132 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT12_ADDR_LO_DEFAULT 0x00000000 |
7133 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT12_ADDR_HI_DEFAULT 0x00000000 |
7134 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT12_MSG_DATA_DEFAULT 0x00000000 |
7135 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT12_CONTROL_DEFAULT 0x00000000 |
7136 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT13_ADDR_LO_DEFAULT 0x00000000 |
7137 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT13_ADDR_HI_DEFAULT 0x00000000 |
7138 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT13_MSG_DATA_DEFAULT 0x00000000 |
7139 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT13_CONTROL_DEFAULT 0x00000000 |
7140 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT14_ADDR_LO_DEFAULT 0x00000000 |
7141 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT14_ADDR_HI_DEFAULT 0x00000000 |
7142 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT14_MSG_DATA_DEFAULT 0x00000000 |
7143 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT14_CONTROL_DEFAULT 0x00000000 |
7144 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT15_ADDR_LO_DEFAULT 0x00000000 |
7145 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT15_ADDR_HI_DEFAULT 0x00000000 |
7146 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT15_MSG_DATA_DEFAULT 0x00000000 |
7147 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT15_CONTROL_DEFAULT 0x00000000 |
7148 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT16_ADDR_LO_DEFAULT 0x00000000 |
7149 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT16_ADDR_HI_DEFAULT 0x00000000 |
7150 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT16_MSG_DATA_DEFAULT 0x00000000 |
7151 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT16_CONTROL_DEFAULT 0x00000000 |
7152 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT17_ADDR_LO_DEFAULT 0x00000000 |
7153 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT17_ADDR_HI_DEFAULT 0x00000000 |
7154 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT17_MSG_DATA_DEFAULT 0x00000000 |
7155 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT17_CONTROL_DEFAULT 0x00000000 |
7156 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT18_ADDR_LO_DEFAULT 0x00000000 |
7157 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT18_ADDR_HI_DEFAULT 0x00000000 |
7158 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT18_MSG_DATA_DEFAULT 0x00000000 |
7159 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT18_CONTROL_DEFAULT 0x00000000 |
7160 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT19_ADDR_LO_DEFAULT 0x00000000 |
7161 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT19_ADDR_HI_DEFAULT 0x00000000 |
7162 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT19_MSG_DATA_DEFAULT 0x00000000 |
7163 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT19_CONTROL_DEFAULT 0x00000000 |
7164 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT20_ADDR_LO_DEFAULT 0x00000000 |
7165 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT20_ADDR_HI_DEFAULT 0x00000000 |
7166 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT20_MSG_DATA_DEFAULT 0x00000000 |
7167 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT20_CONTROL_DEFAULT 0x00000000 |
7168 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT21_ADDR_LO_DEFAULT 0x00000000 |
7169 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT21_ADDR_HI_DEFAULT 0x00000000 |
7170 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT21_MSG_DATA_DEFAULT 0x00000000 |
7171 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT21_CONTROL_DEFAULT 0x00000000 |
7172 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT22_ADDR_LO_DEFAULT 0x00000000 |
7173 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT22_ADDR_HI_DEFAULT 0x00000000 |
7174 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT22_MSG_DATA_DEFAULT 0x00000000 |
7175 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT22_CONTROL_DEFAULT 0x00000000 |
7176 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT23_ADDR_LO_DEFAULT 0x00000000 |
7177 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT23_ADDR_HI_DEFAULT 0x00000000 |
7178 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT23_MSG_DATA_DEFAULT 0x00000000 |
7179 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT23_CONTROL_DEFAULT 0x00000000 |
7180 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT24_ADDR_LO_DEFAULT 0x00000000 |
7181 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT24_ADDR_HI_DEFAULT 0x00000000 |
7182 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT24_MSG_DATA_DEFAULT 0x00000000 |
7183 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT24_CONTROL_DEFAULT 0x00000000 |
7184 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT25_ADDR_LO_DEFAULT 0x00000000 |
7185 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT25_ADDR_HI_DEFAULT 0x00000000 |
7186 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT25_MSG_DATA_DEFAULT 0x00000000 |
7187 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT25_CONTROL_DEFAULT 0x00000000 |
7188 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT26_ADDR_LO_DEFAULT 0x00000000 |
7189 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT26_ADDR_HI_DEFAULT 0x00000000 |
7190 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT26_MSG_DATA_DEFAULT 0x00000000 |
7191 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT26_CONTROL_DEFAULT 0x00000000 |
7192 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT27_ADDR_LO_DEFAULT 0x00000000 |
7193 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT27_ADDR_HI_DEFAULT 0x00000000 |
7194 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT27_MSG_DATA_DEFAULT 0x00000000 |
7195 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT27_CONTROL_DEFAULT 0x00000000 |
7196 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT28_ADDR_LO_DEFAULT 0x00000000 |
7197 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT28_ADDR_HI_DEFAULT 0x00000000 |
7198 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT28_MSG_DATA_DEFAULT 0x00000000 |
7199 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT28_CONTROL_DEFAULT 0x00000000 |
7200 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT29_ADDR_LO_DEFAULT 0x00000000 |
7201 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT29_ADDR_HI_DEFAULT 0x00000000 |
7202 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT29_MSG_DATA_DEFAULT 0x00000000 |
7203 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT29_CONTROL_DEFAULT 0x00000000 |
7204 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT30_ADDR_LO_DEFAULT 0x00000000 |
7205 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT30_ADDR_HI_DEFAULT 0x00000000 |
7206 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT30_MSG_DATA_DEFAULT 0x00000000 |
7207 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT30_CONTROL_DEFAULT 0x00000000 |
7208 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT31_ADDR_LO_DEFAULT 0x00000000 |
7209 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT31_ADDR_HI_DEFAULT 0x00000000 |
7210 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT31_MSG_DATA_DEFAULT 0x00000000 |
7211 | #define smnPCIEMSIX_GBE1_PCIEMSIX_VECT31_CONTROL_DEFAULT 0x00000000 |
7212 | |
7213 | |
7214 | // addressBlock: nbio_nbif0_pciemsix_amdgfx_MSIXPDEC |
7215 | #define smnPCIEMSIX_AMDGFX_PCIEMSIX_PBA_DEFAULT 0x00000000 |
7216 | |
7217 | |
7218 | // addressBlock: nbio_nbif0_pciemsix_psp_MSIXPDEC |
7219 | #define smnPCIEMSIX_PSP_PCIEMSIX_PBA_DEFAULT 0x00000000 |
7220 | |
7221 | |
7222 | // addressBlock: nbio_nbif0_pciemsix_usb3_0_MSIXPDEC |
7223 | #define smnPCIEMSIX_USB3_0_PCIEMSIX_PBA_DEFAULT 0x00000000 |
7224 | |
7225 | |
7226 | // addressBlock: nbio_nbif0_pciemsix_usb3_1_MSIXPDEC |
7227 | #define smnPCIEMSIX_USB3_1_PCIEMSIX_PBA_DEFAULT 0x00000000 |
7228 | |
7229 | |
7230 | // addressBlock: nbio_nbif0_pciemsix_mp2_MSIXPDEC |
7231 | #define smnPCIEMSIX_MP2_PCIEMSIX_PBA_DEFAULT 0x00000000 |
7232 | |
7233 | |
7234 | // addressBlock: nbio_nbif0_pciemsix_gbe0_MSIXPDEC |
7235 | #define smnPCIEMSIX_GBE0_PCIEMSIX_PBA_DEFAULT 0x00000000 |
7236 | |
7237 | |
7238 | // addressBlock: nbio_nbif0_pciemsix_gbe1_MSIXPDEC |
7239 | #define smnPCIEMSIX_GBE1_PCIEMSIX_PBA_DEFAULT 0x00000000 |
7240 | |
7241 | |
7242 | // addressBlock: nbio_pcie0_bifplr0_cfgdecp |
7243 | #define smnBIFPLR0_1_VENDOR_ID_DEFAULT 0x00000000 |
7244 | #define smnBIFPLR0_1_DEVICE_ID_DEFAULT 0x00000000 |
7245 | #define smnBIFPLR0_1_COMMAND_DEFAULT 0x00000000 |
7246 | #define smnBIFPLR0_1_STATUS_DEFAULT 0x00000000 |
7247 | #define smnBIFPLR0_1_REVISION_ID_DEFAULT 0x00000000 |
7248 | #define smnBIFPLR0_1_PROG_INTERFACE_DEFAULT 0x00000000 |
7249 | #define smnBIFPLR0_1_SUB_CLASS_DEFAULT 0x00000000 |
7250 | #define smnBIFPLR0_1_BASE_CLASS_DEFAULT 0x00000000 |
7251 | #define smnBIFPLR0_1_CACHE_LINE_DEFAULT 0x00000000 |
7252 | #define smnBIFPLR0_1_LATENCY_DEFAULT 0x00000000 |
7253 | #define 0x00000000 |
7254 | #define smnBIFPLR0_1_BIST_DEFAULT 0x00000000 |
7255 | #define smnBIFPLR0_1_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 |
7256 | #define smnBIFPLR0_1_IO_BASE_LIMIT_DEFAULT 0x00000000 |
7257 | #define smnBIFPLR0_1_SECONDARY_STATUS_DEFAULT 0x00000000 |
7258 | #define smnBIFPLR0_1_MEM_BASE_LIMIT_DEFAULT 0x00000000 |
7259 | #define smnBIFPLR0_1_PREF_BASE_LIMIT_DEFAULT 0x00000000 |
7260 | #define smnBIFPLR0_1_PREF_BASE_UPPER_DEFAULT 0x00000000 |
7261 | #define smnBIFPLR0_1_PREF_LIMIT_UPPER_DEFAULT 0x00000000 |
7262 | #define smnBIFPLR0_1_IO_BASE_LIMIT_HI_DEFAULT 0x00000000 |
7263 | #define smnBIFPLR0_1_CAP_PTR_DEFAULT 0x00000000 |
7264 | #define smnBIFPLR0_1_INTERRUPT_LINE_DEFAULT 0x000000ff |
7265 | #define smnBIFPLR0_1_INTERRUPT_PIN_DEFAULT 0x00000000 |
7266 | #define smnBIFPLR0_1_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000 |
7267 | #define smnBIFPLR0_1_EXT_BRIDGE_CNTL_DEFAULT 0x00000000 |
7268 | #define smnBIFPLR0_1_PMI_CAP_LIST_DEFAULT 0x00000000 |
7269 | #define smnBIFPLR0_1_PMI_CAP_DEFAULT 0x00000000 |
7270 | #define smnBIFPLR0_1_PMI_STATUS_CNTL_DEFAULT 0x00000000 |
7271 | #define smnBIFPLR0_1_PCIE_CAP_LIST_DEFAULT 0x0000a000 |
7272 | #define smnBIFPLR0_1_PCIE_CAP_DEFAULT 0x00000002 |
7273 | #define smnBIFPLR0_1_DEVICE_CAP_DEFAULT 0x00000000 |
7274 | #define smnBIFPLR0_1_DEVICE_CNTL_DEFAULT 0x00002810 |
7275 | #define smnBIFPLR0_1_DEVICE_STATUS_DEFAULT 0x00000000 |
7276 | #define smnBIFPLR0_1_LINK_CAP_DEFAULT 0x00011c03 |
7277 | #define smnBIFPLR0_1_LINK_CNTL_DEFAULT 0x00000000 |
7278 | #define smnBIFPLR0_1_LINK_STATUS_DEFAULT 0x00000001 |
7279 | #define smnBIFPLR0_1_SLOT_CAP_DEFAULT 0x00000000 |
7280 | #define smnBIFPLR0_1_SLOT_CNTL_DEFAULT 0x00000000 |
7281 | #define smnBIFPLR0_1_SLOT_STATUS_DEFAULT 0x00000000 |
7282 | #define smnBIFPLR0_1_ROOT_CNTL_DEFAULT 0x00000000 |
7283 | #define smnBIFPLR0_1_ROOT_CAP_DEFAULT 0x00000000 |
7284 | #define smnBIFPLR0_1_ROOT_STATUS_DEFAULT 0x00000000 |
7285 | #define smnBIFPLR0_1_DEVICE_CAP2_DEFAULT 0x00000000 |
7286 | #define smnBIFPLR0_1_DEVICE_CNTL2_DEFAULT 0x00000000 |
7287 | #define smnBIFPLR0_1_DEVICE_STATUS2_DEFAULT 0x00000000 |
7288 | #define smnBIFPLR0_1_LINK_CAP2_DEFAULT 0x0000000e |
7289 | #define smnBIFPLR0_1_LINK_CNTL2_DEFAULT 0x00000003 |
7290 | #define smnBIFPLR0_1_LINK_STATUS2_DEFAULT 0x00000000 |
7291 | #define smnBIFPLR0_1_SLOT_CAP2_DEFAULT 0x00000000 |
7292 | #define smnBIFPLR0_1_SLOT_CNTL2_DEFAULT 0x00000000 |
7293 | #define smnBIFPLR0_1_SLOT_STATUS2_DEFAULT 0x00000000 |
7294 | #define smnBIFPLR0_1_MSI_CAP_LIST_DEFAULT 0x0000c000 |
7295 | #define smnBIFPLR0_1_MSI_MSG_CNTL_DEFAULT 0x00000000 |
7296 | #define smnBIFPLR0_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 |
7297 | #define smnBIFPLR0_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 |
7298 | #define smnBIFPLR0_1_MSI_MSG_DATA_DEFAULT 0x00000000 |
7299 | #define smnBIFPLR0_1_MSI_MSG_DATA_64_DEFAULT 0x00000000 |
7300 | #define smnBIFPLR0_1_SSID_CAP_LIST_DEFAULT 0x0000c800 |
7301 | #define smnBIFPLR0_1_SSID_CAP_DEFAULT 0x00000000 |
7302 | #define smnBIFPLR0_1_MSI_MAP_CAP_LIST_DEFAULT 0x00000000 |
7303 | #define smnBIFPLR0_1_MSI_MAP_CAP_DEFAULT 0x00000000 |
7304 | #define smnBIFPLR0_1_MSI_MAP_ADDR_LO_DEFAULT 0x00000000 |
7305 | #define smnBIFPLR0_1_MSI_MAP_ADDR_HI_DEFAULT 0x00000000 |
7306 | #define smnBIFPLR0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 |
7307 | #define smnBIFPLR0_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 |
7308 | #define smnBIFPLR0_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 |
7309 | #define smnBIFPLR0_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 |
7310 | #define smnBIFPLR0_1_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000 |
7311 | #define smnBIFPLR0_1_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000 |
7312 | #define smnBIFPLR0_1_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000 |
7313 | #define smnBIFPLR0_1_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000 |
7314 | #define smnBIFPLR0_1_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000 |
7315 | #define smnBIFPLR0_1_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000 |
7316 | #define smnBIFPLR0_1_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe |
7317 | #define smnBIFPLR0_1_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000002 |
7318 | #define smnBIFPLR0_1_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000 |
7319 | #define smnBIFPLR0_1_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000 |
7320 | #define smnBIFPLR0_1_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000002 |
7321 | #define smnBIFPLR0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000 |
7322 | #define smnBIFPLR0_1_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000 |
7323 | #define smnBIFPLR0_1_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000 |
7324 | #define smnBIFPLR0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x27020000 |
7325 | #define smnBIFPLR0_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 |
7326 | #define smnBIFPLR0_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00400000 |
7327 | #define smnBIFPLR0_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 |
7328 | #define smnBIFPLR0_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 |
7329 | #define smnBIFPLR0_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00006000 |
7330 | #define smnBIFPLR0_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 |
7331 | #define smnBIFPLR0_1_PCIE_HDR_LOG0_DEFAULT 0x00000000 |
7332 | #define smnBIFPLR0_1_PCIE_HDR_LOG1_DEFAULT 0x00000000 |
7333 | #define smnBIFPLR0_1_PCIE_HDR_LOG2_DEFAULT 0x00000000 |
7334 | #define smnBIFPLR0_1_PCIE_HDR_LOG3_DEFAULT 0x00000000 |
7335 | #define smnBIFPLR0_1_PCIE_ROOT_ERR_CMD_DEFAULT 0x00000000 |
7336 | #define smnBIFPLR0_1_PCIE_ROOT_ERR_STATUS_DEFAULT 0x00000000 |
7337 | #define smnBIFPLR0_1_PCIE_ERR_SRC_ID_DEFAULT 0x00000000 |
7338 | #define smnBIFPLR0_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 |
7339 | #define smnBIFPLR0_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 |
7340 | #define smnBIFPLR0_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 |
7341 | #define smnBIFPLR0_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 |
7342 | #define smnBIFPLR0_1_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a000000 |
7343 | #define smnBIFPLR0_1_PCIE_LINK_CNTL3_DEFAULT 0x00000000 |
7344 | #define smnBIFPLR0_1_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000 |
7345 | #define smnBIFPLR0_1_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
7346 | #define smnBIFPLR0_1_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
7347 | #define smnBIFPLR0_1_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
7348 | #define smnBIFPLR0_1_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
7349 | #define smnBIFPLR0_1_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
7350 | #define smnBIFPLR0_1_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
7351 | #define smnBIFPLR0_1_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
7352 | #define smnBIFPLR0_1_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
7353 | #define smnBIFPLR0_1_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
7354 | #define smnBIFPLR0_1_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
7355 | #define smnBIFPLR0_1_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
7356 | #define smnBIFPLR0_1_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
7357 | #define smnBIFPLR0_1_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
7358 | #define smnBIFPLR0_1_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
7359 | #define smnBIFPLR0_1_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
7360 | #define smnBIFPLR0_1_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
7361 | #define smnBIFPLR0_1_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2f000000 |
7362 | #define smnBIFPLR0_1_PCIE_ACS_CAP_DEFAULT 0x00000000 |
7363 | #define smnBIFPLR0_1_PCIE_ACS_CNTL_DEFAULT 0x00000000 |
7364 | #define smnBIFPLR0_1_PCIE_MC_ENH_CAP_LIST_DEFAULT 0x32000000 |
7365 | #define smnBIFPLR0_1_PCIE_MC_CAP_DEFAULT 0x00000000 |
7366 | #define smnBIFPLR0_1_PCIE_MC_CNTL_DEFAULT 0x00000000 |
7367 | #define smnBIFPLR0_1_PCIE_MC_ADDR0_DEFAULT 0x00000000 |
7368 | #define smnBIFPLR0_1_PCIE_MC_ADDR1_DEFAULT 0x00000000 |
7369 | #define smnBIFPLR0_1_PCIE_MC_RCV0_DEFAULT 0x00000000 |
7370 | #define smnBIFPLR0_1_PCIE_MC_RCV1_DEFAULT 0x00000000 |
7371 | #define smnBIFPLR0_1_PCIE_MC_BLOCK_ALL0_DEFAULT 0x00000000 |
7372 | #define smnBIFPLR0_1_PCIE_MC_BLOCK_ALL1_DEFAULT 0x00000000 |
7373 | #define smnBIFPLR0_1_PCIE_MC_BLOCK_UNTRANSLATED_0_DEFAULT 0x00000000 |
7374 | #define smnBIFPLR0_1_PCIE_MC_BLOCK_UNTRANSLATED_1_DEFAULT 0x00000000 |
7375 | #define smnBIFPLR0_1_PCIE_MC_OVERLAY_BAR0_DEFAULT 0x00000000 |
7376 | #define smnBIFPLR0_1_PCIE_MC_OVERLAY_BAR1_DEFAULT 0x00000000 |
7377 | #define smnBIFPLR0_1_PCIE_L1_PM_SUB_CAP_LIST_DEFAULT 0x00000000 |
7378 | #define smnBIFPLR0_1_PCIE_L1_PM_SUB_CAP_DEFAULT 0x00000000 |
7379 | #define smnBIFPLR0_1_PCIE_L1_PM_SUB_CNTL_DEFAULT 0x00000000 |
7380 | #define smnBIFPLR0_1_PCIE_L1_PM_SUB_CNTL2_DEFAULT 0x00000028 |
7381 | #define smnBIFPLR0_1_PCIE_DPC_ENH_CAP_LIST_DEFAULT 0x00000000 |
7382 | #define smnBIFPLR0_1_PCIE_DPC_CAP_LIST_DEFAULT 0x00000000 |
7383 | #define smnBIFPLR0_1_PCIE_DPC_CNTL_DEFAULT 0x00000000 |
7384 | #define smnBIFPLR0_1_PCIE_DPC_STATUS_DEFAULT 0x00000000 |
7385 | #define smnBIFPLR0_1_PCIE_DPC_ERROR_SOURCE_ID_DEFAULT 0x00000000 |
7386 | #define smnBIFPLR0_1_PCIE_RP_PIO_STATUS_DEFAULT 0x00000000 |
7387 | #define smnBIFPLR0_1_PCIE_RP_PIO_MASK_DEFAULT 0x00070707 |
7388 | #define smnBIFPLR0_1_PCIE_RP_PIO_SEVERITY_DEFAULT 0x00000000 |
7389 | #define smnBIFPLR0_1_PCIE_RP_PIO_SYSERROR_DEFAULT 0x00000000 |
7390 | #define smnBIFPLR0_1_PCIE_RP_PIO_EXCEPTION_DEFAULT 0x00000000 |
7391 | #define smnBIFPLR0_1_PCIE_RP_PIO_HDR_LOG0_DEFAULT 0x00000000 |
7392 | #define smnBIFPLR0_1_PCIE_RP_PIO_HDR_LOG1_DEFAULT 0x00000000 |
7393 | #define smnBIFPLR0_1_PCIE_RP_PIO_HDR_LOG2_DEFAULT 0x00000000 |
7394 | #define smnBIFPLR0_1_PCIE_RP_PIO_HDR_LOG3_DEFAULT 0x00000000 |
7395 | #define smnBIFPLR0_1_PCIE_RP_PIO_IMPSPEC_LOG_DEFAULT 0x00000000 |
7396 | #define smnBIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG0_DEFAULT 0x00000000 |
7397 | #define smnBIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG1_DEFAULT 0x00000000 |
7398 | #define smnBIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG2_DEFAULT 0x00000000 |
7399 | #define smnBIFPLR0_1_PCIE_RP_PIO_PREFIX_LOG3_DEFAULT 0x00000000 |
7400 | #define smnBIFPLR0_1_PCIE_ESM_CAP_LIST_DEFAULT 0x00000000 |
7401 | #define 0x00000000 |
7402 | #define 0x00000000 |
7403 | #define smnBIFPLR0_1_PCIE_ESM_STATUS_DEFAULT 0x00000000 |
7404 | #define smnBIFPLR0_1_PCIE_ESM_CTRL_DEFAULT 0x00000000 |
7405 | #define smnBIFPLR0_1_PCIE_ESM_CAP_1_DEFAULT 0x00000000 |
7406 | #define smnBIFPLR0_1_PCIE_ESM_CAP_2_DEFAULT 0x00000000 |
7407 | #define smnBIFPLR0_1_PCIE_ESM_CAP_3_DEFAULT 0x00000000 |
7408 | #define smnBIFPLR0_1_PCIE_ESM_CAP_4_DEFAULT 0x00000000 |
7409 | #define smnBIFPLR0_1_PCIE_ESM_CAP_5_DEFAULT 0x00000000 |
7410 | #define smnBIFPLR0_1_PCIE_ESM_CAP_6_DEFAULT 0x00000000 |
7411 | #define smnBIFPLR0_1_PCIE_ESM_CAP_7_DEFAULT 0x00000000 |
7412 | |
7413 | |
7414 | // addressBlock: nbio_pcie0_bifplr1_cfgdecp |
7415 | #define smnBIFPLR1_1_VENDOR_ID_DEFAULT 0x00000000 |
7416 | #define smnBIFPLR1_1_DEVICE_ID_DEFAULT 0x00000000 |
7417 | #define smnBIFPLR1_1_COMMAND_DEFAULT 0x00000000 |
7418 | #define smnBIFPLR1_1_STATUS_DEFAULT 0x00000000 |
7419 | #define smnBIFPLR1_1_REVISION_ID_DEFAULT 0x00000000 |
7420 | #define smnBIFPLR1_1_PROG_INTERFACE_DEFAULT 0x00000000 |
7421 | #define smnBIFPLR1_1_SUB_CLASS_DEFAULT 0x00000000 |
7422 | #define smnBIFPLR1_1_BASE_CLASS_DEFAULT 0x00000000 |
7423 | #define smnBIFPLR1_1_CACHE_LINE_DEFAULT 0x00000000 |
7424 | #define smnBIFPLR1_1_LATENCY_DEFAULT 0x00000000 |
7425 | #define 0x00000000 |
7426 | #define smnBIFPLR1_1_BIST_DEFAULT 0x00000000 |
7427 | #define smnBIFPLR1_1_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 |
7428 | #define smnBIFPLR1_1_IO_BASE_LIMIT_DEFAULT 0x00000000 |
7429 | #define smnBIFPLR1_1_SECONDARY_STATUS_DEFAULT 0x00000000 |
7430 | #define smnBIFPLR1_1_MEM_BASE_LIMIT_DEFAULT 0x00000000 |
7431 | #define smnBIFPLR1_1_PREF_BASE_LIMIT_DEFAULT 0x00000000 |
7432 | #define smnBIFPLR1_1_PREF_BASE_UPPER_DEFAULT 0x00000000 |
7433 | #define smnBIFPLR1_1_PREF_LIMIT_UPPER_DEFAULT 0x00000000 |
7434 | #define smnBIFPLR1_1_IO_BASE_LIMIT_HI_DEFAULT 0x00000000 |
7435 | #define smnBIFPLR1_1_CAP_PTR_DEFAULT 0x00000000 |
7436 | #define smnBIFPLR1_1_INTERRUPT_LINE_DEFAULT 0x000000ff |
7437 | #define smnBIFPLR1_1_INTERRUPT_PIN_DEFAULT 0x00000000 |
7438 | #define smnBIFPLR1_1_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000 |
7439 | #define smnBIFPLR1_1_EXT_BRIDGE_CNTL_DEFAULT 0x00000000 |
7440 | #define smnBIFPLR1_1_PMI_CAP_LIST_DEFAULT 0x00000000 |
7441 | #define smnBIFPLR1_1_PMI_CAP_DEFAULT 0x00000000 |
7442 | #define smnBIFPLR1_1_PMI_STATUS_CNTL_DEFAULT 0x00000000 |
7443 | #define smnBIFPLR1_1_PCIE_CAP_LIST_DEFAULT 0x0000a000 |
7444 | #define smnBIFPLR1_1_PCIE_CAP_DEFAULT 0x00000002 |
7445 | #define smnBIFPLR1_1_DEVICE_CAP_DEFAULT 0x00000000 |
7446 | #define smnBIFPLR1_1_DEVICE_CNTL_DEFAULT 0x00002810 |
7447 | #define smnBIFPLR1_1_DEVICE_STATUS_DEFAULT 0x00000000 |
7448 | #define smnBIFPLR1_1_LINK_CAP_DEFAULT 0x00011c03 |
7449 | #define smnBIFPLR1_1_LINK_CNTL_DEFAULT 0x00000000 |
7450 | #define smnBIFPLR1_1_LINK_STATUS_DEFAULT 0x00000001 |
7451 | #define smnBIFPLR1_1_SLOT_CAP_DEFAULT 0x00000000 |
7452 | #define smnBIFPLR1_1_SLOT_CNTL_DEFAULT 0x00000000 |
7453 | #define smnBIFPLR1_1_SLOT_STATUS_DEFAULT 0x00000000 |
7454 | #define smnBIFPLR1_1_ROOT_CNTL_DEFAULT 0x00000000 |
7455 | #define smnBIFPLR1_1_ROOT_CAP_DEFAULT 0x00000000 |
7456 | #define smnBIFPLR1_1_ROOT_STATUS_DEFAULT 0x00000000 |
7457 | #define smnBIFPLR1_1_DEVICE_CAP2_DEFAULT 0x00000000 |
7458 | #define smnBIFPLR1_1_DEVICE_CNTL2_DEFAULT 0x00000000 |
7459 | #define smnBIFPLR1_1_DEVICE_STATUS2_DEFAULT 0x00000000 |
7460 | #define smnBIFPLR1_1_LINK_CAP2_DEFAULT 0x0000000e |
7461 | #define smnBIFPLR1_1_LINK_CNTL2_DEFAULT 0x00000003 |
7462 | #define smnBIFPLR1_1_LINK_STATUS2_DEFAULT 0x00000000 |
7463 | #define smnBIFPLR1_1_SLOT_CAP2_DEFAULT 0x00000000 |
7464 | #define smnBIFPLR1_1_SLOT_CNTL2_DEFAULT 0x00000000 |
7465 | #define smnBIFPLR1_1_SLOT_STATUS2_DEFAULT 0x00000000 |
7466 | #define smnBIFPLR1_1_MSI_CAP_LIST_DEFAULT 0x0000c000 |
7467 | #define smnBIFPLR1_1_MSI_MSG_CNTL_DEFAULT 0x00000000 |
7468 | #define smnBIFPLR1_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 |
7469 | #define smnBIFPLR1_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 |
7470 | #define smnBIFPLR1_1_MSI_MSG_DATA_DEFAULT 0x00000000 |
7471 | #define smnBIFPLR1_1_MSI_MSG_DATA_64_DEFAULT 0x00000000 |
7472 | #define smnBIFPLR1_1_SSID_CAP_LIST_DEFAULT 0x0000c800 |
7473 | #define smnBIFPLR1_1_SSID_CAP_DEFAULT 0x00000000 |
7474 | #define smnBIFPLR1_1_MSI_MAP_CAP_LIST_DEFAULT 0x00000000 |
7475 | #define smnBIFPLR1_1_MSI_MAP_CAP_DEFAULT 0x00000000 |
7476 | #define smnBIFPLR1_1_MSI_MAP_ADDR_LO_DEFAULT 0x00000000 |
7477 | #define smnBIFPLR1_1_MSI_MAP_ADDR_HI_DEFAULT 0x00000000 |
7478 | #define smnBIFPLR1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 |
7479 | #define smnBIFPLR1_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 |
7480 | #define smnBIFPLR1_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 |
7481 | #define smnBIFPLR1_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 |
7482 | #define smnBIFPLR1_1_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000 |
7483 | #define smnBIFPLR1_1_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000 |
7484 | #define smnBIFPLR1_1_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000 |
7485 | #define smnBIFPLR1_1_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000 |
7486 | #define smnBIFPLR1_1_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000 |
7487 | #define smnBIFPLR1_1_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000 |
7488 | #define smnBIFPLR1_1_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe |
7489 | #define smnBIFPLR1_1_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000002 |
7490 | #define smnBIFPLR1_1_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000 |
7491 | #define smnBIFPLR1_1_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000 |
7492 | #define smnBIFPLR1_1_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000002 |
7493 | #define smnBIFPLR1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000 |
7494 | #define smnBIFPLR1_1_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000 |
7495 | #define smnBIFPLR1_1_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000 |
7496 | #define smnBIFPLR1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x27020000 |
7497 | #define smnBIFPLR1_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 |
7498 | #define smnBIFPLR1_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00400000 |
7499 | #define smnBIFPLR1_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 |
7500 | #define smnBIFPLR1_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 |
7501 | #define smnBIFPLR1_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00006000 |
7502 | #define smnBIFPLR1_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 |
7503 | #define smnBIFPLR1_1_PCIE_HDR_LOG0_DEFAULT 0x00000000 |
7504 | #define smnBIFPLR1_1_PCIE_HDR_LOG1_DEFAULT 0x00000000 |
7505 | #define smnBIFPLR1_1_PCIE_HDR_LOG2_DEFAULT 0x00000000 |
7506 | #define smnBIFPLR1_1_PCIE_HDR_LOG3_DEFAULT 0x00000000 |
7507 | #define smnBIFPLR1_1_PCIE_ROOT_ERR_CMD_DEFAULT 0x00000000 |
7508 | #define smnBIFPLR1_1_PCIE_ROOT_ERR_STATUS_DEFAULT 0x00000000 |
7509 | #define smnBIFPLR1_1_PCIE_ERR_SRC_ID_DEFAULT 0x00000000 |
7510 | #define smnBIFPLR1_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 |
7511 | #define smnBIFPLR1_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 |
7512 | #define smnBIFPLR1_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 |
7513 | #define smnBIFPLR1_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 |
7514 | #define smnBIFPLR1_1_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a000000 |
7515 | #define smnBIFPLR1_1_PCIE_LINK_CNTL3_DEFAULT 0x00000000 |
7516 | #define smnBIFPLR1_1_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000 |
7517 | #define smnBIFPLR1_1_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
7518 | #define smnBIFPLR1_1_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
7519 | #define smnBIFPLR1_1_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
7520 | #define smnBIFPLR1_1_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
7521 | #define smnBIFPLR1_1_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
7522 | #define smnBIFPLR1_1_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
7523 | #define smnBIFPLR1_1_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
7524 | #define smnBIFPLR1_1_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
7525 | #define smnBIFPLR1_1_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
7526 | #define smnBIFPLR1_1_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
7527 | #define smnBIFPLR1_1_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
7528 | #define smnBIFPLR1_1_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
7529 | #define smnBIFPLR1_1_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
7530 | #define smnBIFPLR1_1_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
7531 | #define smnBIFPLR1_1_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
7532 | #define smnBIFPLR1_1_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
7533 | #define smnBIFPLR1_1_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2f000000 |
7534 | #define smnBIFPLR1_1_PCIE_ACS_CAP_DEFAULT 0x00000000 |
7535 | #define smnBIFPLR1_1_PCIE_ACS_CNTL_DEFAULT 0x00000000 |
7536 | #define smnBIFPLR1_1_PCIE_MC_ENH_CAP_LIST_DEFAULT 0x32000000 |
7537 | #define smnBIFPLR1_1_PCIE_MC_CAP_DEFAULT 0x00000000 |
7538 | #define smnBIFPLR1_1_PCIE_MC_CNTL_DEFAULT 0x00000000 |
7539 | #define smnBIFPLR1_1_PCIE_MC_ADDR0_DEFAULT 0x00000000 |
7540 | #define smnBIFPLR1_1_PCIE_MC_ADDR1_DEFAULT 0x00000000 |
7541 | #define smnBIFPLR1_1_PCIE_MC_RCV0_DEFAULT 0x00000000 |
7542 | #define smnBIFPLR1_1_PCIE_MC_RCV1_DEFAULT 0x00000000 |
7543 | #define smnBIFPLR1_1_PCIE_MC_BLOCK_ALL0_DEFAULT 0x00000000 |
7544 | #define smnBIFPLR1_1_PCIE_MC_BLOCK_ALL1_DEFAULT 0x00000000 |
7545 | #define smnBIFPLR1_1_PCIE_MC_BLOCK_UNTRANSLATED_0_DEFAULT 0x00000000 |
7546 | #define smnBIFPLR1_1_PCIE_MC_BLOCK_UNTRANSLATED_1_DEFAULT 0x00000000 |
7547 | #define smnBIFPLR1_1_PCIE_MC_OVERLAY_BAR0_DEFAULT 0x00000000 |
7548 | #define smnBIFPLR1_1_PCIE_MC_OVERLAY_BAR1_DEFAULT 0x00000000 |
7549 | #define smnBIFPLR1_1_PCIE_L1_PM_SUB_CAP_LIST_DEFAULT 0x00000000 |
7550 | #define smnBIFPLR1_1_PCIE_L1_PM_SUB_CAP_DEFAULT 0x00000000 |
7551 | #define smnBIFPLR1_1_PCIE_L1_PM_SUB_CNTL_DEFAULT 0x00000000 |
7552 | #define smnBIFPLR1_1_PCIE_L1_PM_SUB_CNTL2_DEFAULT 0x00000028 |
7553 | #define smnBIFPLR1_1_PCIE_DPC_ENH_CAP_LIST_DEFAULT 0x00000000 |
7554 | #define smnBIFPLR1_1_PCIE_DPC_CAP_LIST_DEFAULT 0x00000000 |
7555 | #define smnBIFPLR1_1_PCIE_DPC_CNTL_DEFAULT 0x00000000 |
7556 | #define smnBIFPLR1_1_PCIE_DPC_STATUS_DEFAULT 0x00000000 |
7557 | #define smnBIFPLR1_1_PCIE_DPC_ERROR_SOURCE_ID_DEFAULT 0x00000000 |
7558 | #define smnBIFPLR1_1_PCIE_RP_PIO_STATUS_DEFAULT 0x00000000 |
7559 | #define smnBIFPLR1_1_PCIE_RP_PIO_MASK_DEFAULT 0x00070707 |
7560 | #define smnBIFPLR1_1_PCIE_RP_PIO_SEVERITY_DEFAULT 0x00000000 |
7561 | #define smnBIFPLR1_1_PCIE_RP_PIO_SYSERROR_DEFAULT 0x00000000 |
7562 | #define smnBIFPLR1_1_PCIE_RP_PIO_EXCEPTION_DEFAULT 0x00000000 |
7563 | #define smnBIFPLR1_1_PCIE_RP_PIO_HDR_LOG0_DEFAULT 0x00000000 |
7564 | #define smnBIFPLR1_1_PCIE_RP_PIO_HDR_LOG1_DEFAULT 0x00000000 |
7565 | #define smnBIFPLR1_1_PCIE_RP_PIO_HDR_LOG2_DEFAULT 0x00000000 |
7566 | #define smnBIFPLR1_1_PCIE_RP_PIO_HDR_LOG3_DEFAULT 0x00000000 |
7567 | #define smnBIFPLR1_1_PCIE_RP_PIO_IMPSPEC_LOG_DEFAULT 0x00000000 |
7568 | #define smnBIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG0_DEFAULT 0x00000000 |
7569 | #define smnBIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG1_DEFAULT 0x00000000 |
7570 | #define smnBIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG2_DEFAULT 0x00000000 |
7571 | #define smnBIFPLR1_1_PCIE_RP_PIO_PREFIX_LOG3_DEFAULT 0x00000000 |
7572 | #define smnBIFPLR1_1_PCIE_ESM_CAP_LIST_DEFAULT 0x00000000 |
7573 | #define 0x00000000 |
7574 | #define 0x00000000 |
7575 | #define smnBIFPLR1_1_PCIE_ESM_STATUS_DEFAULT 0x00000000 |
7576 | #define smnBIFPLR1_1_PCIE_ESM_CTRL_DEFAULT 0x00000000 |
7577 | #define smnBIFPLR1_1_PCIE_ESM_CAP_1_DEFAULT 0x00000000 |
7578 | #define smnBIFPLR1_1_PCIE_ESM_CAP_2_DEFAULT 0x00000000 |
7579 | #define smnBIFPLR1_1_PCIE_ESM_CAP_3_DEFAULT 0x00000000 |
7580 | #define smnBIFPLR1_1_PCIE_ESM_CAP_4_DEFAULT 0x00000000 |
7581 | #define smnBIFPLR1_1_PCIE_ESM_CAP_5_DEFAULT 0x00000000 |
7582 | #define smnBIFPLR1_1_PCIE_ESM_CAP_6_DEFAULT 0x00000000 |
7583 | #define smnBIFPLR1_1_PCIE_ESM_CAP_7_DEFAULT 0x00000000 |
7584 | |
7585 | |
7586 | // addressBlock: nbio_pcie0_bifplr2_cfgdecp |
7587 | #define smnBIFPLR2_1_VENDOR_ID_DEFAULT 0x00000000 |
7588 | #define smnBIFPLR2_1_DEVICE_ID_DEFAULT 0x00000000 |
7589 | #define smnBIFPLR2_1_COMMAND_DEFAULT 0x00000000 |
7590 | #define smnBIFPLR2_1_STATUS_DEFAULT 0x00000000 |
7591 | #define smnBIFPLR2_1_REVISION_ID_DEFAULT 0x00000000 |
7592 | #define smnBIFPLR2_1_PROG_INTERFACE_DEFAULT 0x00000000 |
7593 | #define smnBIFPLR2_1_SUB_CLASS_DEFAULT 0x00000000 |
7594 | #define smnBIFPLR2_1_BASE_CLASS_DEFAULT 0x00000000 |
7595 | #define smnBIFPLR2_1_CACHE_LINE_DEFAULT 0x00000000 |
7596 | #define smnBIFPLR2_1_LATENCY_DEFAULT 0x00000000 |
7597 | #define 0x00000000 |
7598 | #define smnBIFPLR2_1_BIST_DEFAULT 0x00000000 |
7599 | #define smnBIFPLR2_1_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 |
7600 | #define smnBIFPLR2_1_IO_BASE_LIMIT_DEFAULT 0x00000000 |
7601 | #define smnBIFPLR2_1_SECONDARY_STATUS_DEFAULT 0x00000000 |
7602 | #define smnBIFPLR2_1_MEM_BASE_LIMIT_DEFAULT 0x00000000 |
7603 | #define smnBIFPLR2_1_PREF_BASE_LIMIT_DEFAULT 0x00000000 |
7604 | #define smnBIFPLR2_1_PREF_BASE_UPPER_DEFAULT 0x00000000 |
7605 | #define smnBIFPLR2_1_PREF_LIMIT_UPPER_DEFAULT 0x00000000 |
7606 | #define smnBIFPLR2_1_IO_BASE_LIMIT_HI_DEFAULT 0x00000000 |
7607 | #define smnBIFPLR2_1_CAP_PTR_DEFAULT 0x00000000 |
7608 | #define smnBIFPLR2_1_INTERRUPT_LINE_DEFAULT 0x000000ff |
7609 | #define smnBIFPLR2_1_INTERRUPT_PIN_DEFAULT 0x00000000 |
7610 | #define smnBIFPLR2_1_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000 |
7611 | #define smnBIFPLR2_1_EXT_BRIDGE_CNTL_DEFAULT 0x00000000 |
7612 | #define smnBIFPLR2_1_PMI_CAP_LIST_DEFAULT 0x00000000 |
7613 | #define smnBIFPLR2_1_PMI_CAP_DEFAULT 0x00000000 |
7614 | #define smnBIFPLR2_1_PMI_STATUS_CNTL_DEFAULT 0x00000000 |
7615 | #define smnBIFPLR2_1_PCIE_CAP_LIST_DEFAULT 0x0000a000 |
7616 | #define smnBIFPLR2_1_PCIE_CAP_DEFAULT 0x00000002 |
7617 | #define smnBIFPLR2_1_DEVICE_CAP_DEFAULT 0x00000000 |
7618 | #define smnBIFPLR2_1_DEVICE_CNTL_DEFAULT 0x00002810 |
7619 | #define smnBIFPLR2_1_DEVICE_STATUS_DEFAULT 0x00000000 |
7620 | #define smnBIFPLR2_1_LINK_CAP_DEFAULT 0x00011c03 |
7621 | #define smnBIFPLR2_1_LINK_CNTL_DEFAULT 0x00000000 |
7622 | #define smnBIFPLR2_1_LINK_STATUS_DEFAULT 0x00000001 |
7623 | #define smnBIFPLR2_1_SLOT_CAP_DEFAULT 0x00000000 |
7624 | #define smnBIFPLR2_1_SLOT_CNTL_DEFAULT 0x00000000 |
7625 | #define smnBIFPLR2_1_SLOT_STATUS_DEFAULT 0x00000000 |
7626 | #define smnBIFPLR2_1_ROOT_CNTL_DEFAULT 0x00000000 |
7627 | #define smnBIFPLR2_1_ROOT_CAP_DEFAULT 0x00000000 |
7628 | #define smnBIFPLR2_1_ROOT_STATUS_DEFAULT 0x00000000 |
7629 | #define smnBIFPLR2_1_DEVICE_CAP2_DEFAULT 0x00000000 |
7630 | #define smnBIFPLR2_1_DEVICE_CNTL2_DEFAULT 0x00000000 |
7631 | #define smnBIFPLR2_1_DEVICE_STATUS2_DEFAULT 0x00000000 |
7632 | #define smnBIFPLR2_1_LINK_CAP2_DEFAULT 0x0000000e |
7633 | #define smnBIFPLR2_1_LINK_CNTL2_DEFAULT 0x00000003 |
7634 | #define smnBIFPLR2_1_LINK_STATUS2_DEFAULT 0x00000000 |
7635 | #define smnBIFPLR2_1_SLOT_CAP2_DEFAULT 0x00000000 |
7636 | #define smnBIFPLR2_1_SLOT_CNTL2_DEFAULT 0x00000000 |
7637 | #define smnBIFPLR2_1_SLOT_STATUS2_DEFAULT 0x00000000 |
7638 | #define smnBIFPLR2_1_MSI_CAP_LIST_DEFAULT 0x0000c000 |
7639 | #define smnBIFPLR2_1_MSI_MSG_CNTL_DEFAULT 0x00000000 |
7640 | #define smnBIFPLR2_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 |
7641 | #define smnBIFPLR2_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 |
7642 | #define smnBIFPLR2_1_MSI_MSG_DATA_DEFAULT 0x00000000 |
7643 | #define smnBIFPLR2_1_MSI_MSG_DATA_64_DEFAULT 0x00000000 |
7644 | #define smnBIFPLR2_1_SSID_CAP_LIST_DEFAULT 0x0000c800 |
7645 | #define smnBIFPLR2_1_SSID_CAP_DEFAULT 0x00000000 |
7646 | #define smnBIFPLR2_1_MSI_MAP_CAP_LIST_DEFAULT 0x00000000 |
7647 | #define smnBIFPLR2_1_MSI_MAP_CAP_DEFAULT 0x00000000 |
7648 | #define smnBIFPLR2_1_MSI_MAP_ADDR_LO_DEFAULT 0x00000000 |
7649 | #define smnBIFPLR2_1_MSI_MAP_ADDR_HI_DEFAULT 0x00000000 |
7650 | #define smnBIFPLR2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 |
7651 | #define smnBIFPLR2_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 |
7652 | #define smnBIFPLR2_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 |
7653 | #define smnBIFPLR2_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 |
7654 | #define smnBIFPLR2_1_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000 |
7655 | #define smnBIFPLR2_1_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000 |
7656 | #define smnBIFPLR2_1_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000 |
7657 | #define smnBIFPLR2_1_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000 |
7658 | #define smnBIFPLR2_1_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000 |
7659 | #define smnBIFPLR2_1_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000 |
7660 | #define smnBIFPLR2_1_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe |
7661 | #define smnBIFPLR2_1_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000002 |
7662 | #define smnBIFPLR2_1_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000 |
7663 | #define smnBIFPLR2_1_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000 |
7664 | #define smnBIFPLR2_1_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000002 |
7665 | #define smnBIFPLR2_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000 |
7666 | #define smnBIFPLR2_1_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000 |
7667 | #define smnBIFPLR2_1_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000 |
7668 | #define smnBIFPLR2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x27020000 |
7669 | #define smnBIFPLR2_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 |
7670 | #define smnBIFPLR2_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00400000 |
7671 | #define smnBIFPLR2_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 |
7672 | #define smnBIFPLR2_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 |
7673 | #define smnBIFPLR2_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00006000 |
7674 | #define smnBIFPLR2_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 |
7675 | #define smnBIFPLR2_1_PCIE_HDR_LOG0_DEFAULT 0x00000000 |
7676 | #define smnBIFPLR2_1_PCIE_HDR_LOG1_DEFAULT 0x00000000 |
7677 | #define smnBIFPLR2_1_PCIE_HDR_LOG2_DEFAULT 0x00000000 |
7678 | #define smnBIFPLR2_1_PCIE_HDR_LOG3_DEFAULT 0x00000000 |
7679 | #define smnBIFPLR2_1_PCIE_ROOT_ERR_CMD_DEFAULT 0x00000000 |
7680 | #define smnBIFPLR2_1_PCIE_ROOT_ERR_STATUS_DEFAULT 0x00000000 |
7681 | #define smnBIFPLR2_1_PCIE_ERR_SRC_ID_DEFAULT 0x00000000 |
7682 | #define smnBIFPLR2_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 |
7683 | #define smnBIFPLR2_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 |
7684 | #define smnBIFPLR2_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 |
7685 | #define smnBIFPLR2_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 |
7686 | #define smnBIFPLR2_1_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a000000 |
7687 | #define smnBIFPLR2_1_PCIE_LINK_CNTL3_DEFAULT 0x00000000 |
7688 | #define smnBIFPLR2_1_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000 |
7689 | #define smnBIFPLR2_1_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
7690 | #define smnBIFPLR2_1_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
7691 | #define smnBIFPLR2_1_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
7692 | #define smnBIFPLR2_1_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
7693 | #define smnBIFPLR2_1_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
7694 | #define smnBIFPLR2_1_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
7695 | #define smnBIFPLR2_1_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
7696 | #define smnBIFPLR2_1_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
7697 | #define smnBIFPLR2_1_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
7698 | #define smnBIFPLR2_1_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
7699 | #define smnBIFPLR2_1_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
7700 | #define smnBIFPLR2_1_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
7701 | #define smnBIFPLR2_1_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
7702 | #define smnBIFPLR2_1_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
7703 | #define smnBIFPLR2_1_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
7704 | #define smnBIFPLR2_1_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
7705 | #define smnBIFPLR2_1_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2f000000 |
7706 | #define smnBIFPLR2_1_PCIE_ACS_CAP_DEFAULT 0x00000000 |
7707 | #define smnBIFPLR2_1_PCIE_ACS_CNTL_DEFAULT 0x00000000 |
7708 | #define smnBIFPLR2_1_PCIE_MC_ENH_CAP_LIST_DEFAULT 0x32000000 |
7709 | #define smnBIFPLR2_1_PCIE_MC_CAP_DEFAULT 0x00000000 |
7710 | #define smnBIFPLR2_1_PCIE_MC_CNTL_DEFAULT 0x00000000 |
7711 | #define smnBIFPLR2_1_PCIE_MC_ADDR0_DEFAULT 0x00000000 |
7712 | #define smnBIFPLR2_1_PCIE_MC_ADDR1_DEFAULT 0x00000000 |
7713 | #define smnBIFPLR2_1_PCIE_MC_RCV0_DEFAULT 0x00000000 |
7714 | #define smnBIFPLR2_1_PCIE_MC_RCV1_DEFAULT 0x00000000 |
7715 | #define smnBIFPLR2_1_PCIE_MC_BLOCK_ALL0_DEFAULT 0x00000000 |
7716 | #define smnBIFPLR2_1_PCIE_MC_BLOCK_ALL1_DEFAULT 0x00000000 |
7717 | #define smnBIFPLR2_1_PCIE_MC_BLOCK_UNTRANSLATED_0_DEFAULT 0x00000000 |
7718 | #define smnBIFPLR2_1_PCIE_MC_BLOCK_UNTRANSLATED_1_DEFAULT 0x00000000 |
7719 | #define smnBIFPLR2_1_PCIE_MC_OVERLAY_BAR0_DEFAULT 0x00000000 |
7720 | #define smnBIFPLR2_1_PCIE_MC_OVERLAY_BAR1_DEFAULT 0x00000000 |
7721 | #define smnBIFPLR2_1_PCIE_L1_PM_SUB_CAP_LIST_DEFAULT 0x00000000 |
7722 | #define smnBIFPLR2_1_PCIE_L1_PM_SUB_CAP_DEFAULT 0x00000000 |
7723 | #define smnBIFPLR2_1_PCIE_L1_PM_SUB_CNTL_DEFAULT 0x00000000 |
7724 | #define smnBIFPLR2_1_PCIE_L1_PM_SUB_CNTL2_DEFAULT 0x00000028 |
7725 | #define smnBIFPLR2_1_PCIE_DPC_ENH_CAP_LIST_DEFAULT 0x00000000 |
7726 | #define smnBIFPLR2_1_PCIE_DPC_CAP_LIST_DEFAULT 0x00000000 |
7727 | #define smnBIFPLR2_1_PCIE_DPC_CNTL_DEFAULT 0x00000000 |
7728 | #define smnBIFPLR2_1_PCIE_DPC_STATUS_DEFAULT 0x00000000 |
7729 | #define smnBIFPLR2_1_PCIE_DPC_ERROR_SOURCE_ID_DEFAULT 0x00000000 |
7730 | #define smnBIFPLR2_1_PCIE_RP_PIO_STATUS_DEFAULT 0x00000000 |
7731 | #define smnBIFPLR2_1_PCIE_RP_PIO_MASK_DEFAULT 0x00070707 |
7732 | #define smnBIFPLR2_1_PCIE_RP_PIO_SEVERITY_DEFAULT 0x00000000 |
7733 | #define smnBIFPLR2_1_PCIE_RP_PIO_SYSERROR_DEFAULT 0x00000000 |
7734 | #define smnBIFPLR2_1_PCIE_RP_PIO_EXCEPTION_DEFAULT 0x00000000 |
7735 | #define smnBIFPLR2_1_PCIE_RP_PIO_HDR_LOG0_DEFAULT 0x00000000 |
7736 | #define smnBIFPLR2_1_PCIE_RP_PIO_HDR_LOG1_DEFAULT 0x00000000 |
7737 | #define smnBIFPLR2_1_PCIE_RP_PIO_HDR_LOG2_DEFAULT 0x00000000 |
7738 | #define smnBIFPLR2_1_PCIE_RP_PIO_HDR_LOG3_DEFAULT 0x00000000 |
7739 | #define smnBIFPLR2_1_PCIE_RP_PIO_IMPSPEC_LOG_DEFAULT 0x00000000 |
7740 | #define smnBIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG0_DEFAULT 0x00000000 |
7741 | #define smnBIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG1_DEFAULT 0x00000000 |
7742 | #define smnBIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG2_DEFAULT 0x00000000 |
7743 | #define smnBIFPLR2_1_PCIE_RP_PIO_PREFIX_LOG3_DEFAULT 0x00000000 |
7744 | #define smnBIFPLR2_1_PCIE_ESM_CAP_LIST_DEFAULT 0x00000000 |
7745 | #define 0x00000000 |
7746 | #define 0x00000000 |
7747 | #define smnBIFPLR2_1_PCIE_ESM_STATUS_DEFAULT 0x00000000 |
7748 | #define smnBIFPLR2_1_PCIE_ESM_CTRL_DEFAULT 0x00000000 |
7749 | #define smnBIFPLR2_1_PCIE_ESM_CAP_1_DEFAULT 0x00000000 |
7750 | #define smnBIFPLR2_1_PCIE_ESM_CAP_2_DEFAULT 0x00000000 |
7751 | #define smnBIFPLR2_1_PCIE_ESM_CAP_3_DEFAULT 0x00000000 |
7752 | #define smnBIFPLR2_1_PCIE_ESM_CAP_4_DEFAULT 0x00000000 |
7753 | #define smnBIFPLR2_1_PCIE_ESM_CAP_5_DEFAULT 0x00000000 |
7754 | #define smnBIFPLR2_1_PCIE_ESM_CAP_6_DEFAULT 0x00000000 |
7755 | #define smnBIFPLR2_1_PCIE_ESM_CAP_7_DEFAULT 0x00000000 |
7756 | |
7757 | |
7758 | // addressBlock: nbio_pcie0_bifplr3_cfgdecp |
7759 | #define smnBIFPLR3_1_VENDOR_ID_DEFAULT 0x00000000 |
7760 | #define smnBIFPLR3_1_DEVICE_ID_DEFAULT 0x00000000 |
7761 | #define smnBIFPLR3_1_COMMAND_DEFAULT 0x00000000 |
7762 | #define smnBIFPLR3_1_STATUS_DEFAULT 0x00000000 |
7763 | #define smnBIFPLR3_1_REVISION_ID_DEFAULT 0x00000000 |
7764 | #define smnBIFPLR3_1_PROG_INTERFACE_DEFAULT 0x00000000 |
7765 | #define smnBIFPLR3_1_SUB_CLASS_DEFAULT 0x00000000 |
7766 | #define smnBIFPLR3_1_BASE_CLASS_DEFAULT 0x00000000 |
7767 | #define smnBIFPLR3_1_CACHE_LINE_DEFAULT 0x00000000 |
7768 | #define smnBIFPLR3_1_LATENCY_DEFAULT 0x00000000 |
7769 | #define 0x00000000 |
7770 | #define smnBIFPLR3_1_BIST_DEFAULT 0x00000000 |
7771 | #define smnBIFPLR3_1_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 |
7772 | #define smnBIFPLR3_1_IO_BASE_LIMIT_DEFAULT 0x00000000 |
7773 | #define smnBIFPLR3_1_SECONDARY_STATUS_DEFAULT 0x00000000 |
7774 | #define smnBIFPLR3_1_MEM_BASE_LIMIT_DEFAULT 0x00000000 |
7775 | #define smnBIFPLR3_1_PREF_BASE_LIMIT_DEFAULT 0x00000000 |
7776 | #define smnBIFPLR3_1_PREF_BASE_UPPER_DEFAULT 0x00000000 |
7777 | #define smnBIFPLR3_1_PREF_LIMIT_UPPER_DEFAULT 0x00000000 |
7778 | #define smnBIFPLR3_1_IO_BASE_LIMIT_HI_DEFAULT 0x00000000 |
7779 | #define smnBIFPLR3_1_CAP_PTR_DEFAULT 0x00000000 |
7780 | #define smnBIFPLR3_1_INTERRUPT_LINE_DEFAULT 0x000000ff |
7781 | #define smnBIFPLR3_1_INTERRUPT_PIN_DEFAULT 0x00000000 |
7782 | #define smnBIFPLR3_1_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000 |
7783 | #define smnBIFPLR3_1_EXT_BRIDGE_CNTL_DEFAULT 0x00000000 |
7784 | #define smnBIFPLR3_1_PMI_CAP_LIST_DEFAULT 0x00000000 |
7785 | #define smnBIFPLR3_1_PMI_CAP_DEFAULT 0x00000000 |
7786 | #define smnBIFPLR3_1_PMI_STATUS_CNTL_DEFAULT 0x00000000 |
7787 | #define smnBIFPLR3_1_PCIE_CAP_LIST_DEFAULT 0x0000a000 |
7788 | #define smnBIFPLR3_1_PCIE_CAP_DEFAULT 0x00000002 |
7789 | #define smnBIFPLR3_1_DEVICE_CAP_DEFAULT 0x00000000 |
7790 | #define smnBIFPLR3_1_DEVICE_CNTL_DEFAULT 0x00002810 |
7791 | #define smnBIFPLR3_1_DEVICE_STATUS_DEFAULT 0x00000000 |
7792 | #define smnBIFPLR3_1_LINK_CAP_DEFAULT 0x00011c03 |
7793 | #define smnBIFPLR3_1_LINK_CNTL_DEFAULT 0x00000000 |
7794 | #define smnBIFPLR3_1_LINK_STATUS_DEFAULT 0x00000001 |
7795 | #define smnBIFPLR3_1_SLOT_CAP_DEFAULT 0x00000000 |
7796 | #define smnBIFPLR3_1_SLOT_CNTL_DEFAULT 0x00000000 |
7797 | #define smnBIFPLR3_1_SLOT_STATUS_DEFAULT 0x00000000 |
7798 | #define smnBIFPLR3_1_ROOT_CNTL_DEFAULT 0x00000000 |
7799 | #define smnBIFPLR3_1_ROOT_CAP_DEFAULT 0x00000000 |
7800 | #define smnBIFPLR3_1_ROOT_STATUS_DEFAULT 0x00000000 |
7801 | #define smnBIFPLR3_1_DEVICE_CAP2_DEFAULT 0x00000000 |
7802 | #define smnBIFPLR3_1_DEVICE_CNTL2_DEFAULT 0x00000000 |
7803 | #define smnBIFPLR3_1_DEVICE_STATUS2_DEFAULT 0x00000000 |
7804 | #define smnBIFPLR3_1_LINK_CAP2_DEFAULT 0x0000000e |
7805 | #define smnBIFPLR3_1_LINK_CNTL2_DEFAULT 0x00000003 |
7806 | #define smnBIFPLR3_1_LINK_STATUS2_DEFAULT 0x00000000 |
7807 | #define smnBIFPLR3_1_SLOT_CAP2_DEFAULT 0x00000000 |
7808 | #define smnBIFPLR3_1_SLOT_CNTL2_DEFAULT 0x00000000 |
7809 | #define smnBIFPLR3_1_SLOT_STATUS2_DEFAULT 0x00000000 |
7810 | #define smnBIFPLR3_1_MSI_CAP_LIST_DEFAULT 0x0000c000 |
7811 | #define smnBIFPLR3_1_MSI_MSG_CNTL_DEFAULT 0x00000000 |
7812 | #define smnBIFPLR3_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 |
7813 | #define smnBIFPLR3_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 |
7814 | #define smnBIFPLR3_1_MSI_MSG_DATA_DEFAULT 0x00000000 |
7815 | #define smnBIFPLR3_1_MSI_MSG_DATA_64_DEFAULT 0x00000000 |
7816 | #define smnBIFPLR3_1_SSID_CAP_LIST_DEFAULT 0x0000c800 |
7817 | #define smnBIFPLR3_1_SSID_CAP_DEFAULT 0x00000000 |
7818 | #define smnBIFPLR3_1_MSI_MAP_CAP_LIST_DEFAULT 0x00000000 |
7819 | #define smnBIFPLR3_1_MSI_MAP_CAP_DEFAULT 0x00000000 |
7820 | #define smnBIFPLR3_1_MSI_MAP_ADDR_LO_DEFAULT 0x00000000 |
7821 | #define smnBIFPLR3_1_MSI_MAP_ADDR_HI_DEFAULT 0x00000000 |
7822 | #define smnBIFPLR3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 |
7823 | #define smnBIFPLR3_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 |
7824 | #define smnBIFPLR3_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 |
7825 | #define smnBIFPLR3_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 |
7826 | #define smnBIFPLR3_1_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000 |
7827 | #define smnBIFPLR3_1_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000 |
7828 | #define smnBIFPLR3_1_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000 |
7829 | #define smnBIFPLR3_1_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000 |
7830 | #define smnBIFPLR3_1_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000 |
7831 | #define smnBIFPLR3_1_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000 |
7832 | #define smnBIFPLR3_1_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe |
7833 | #define smnBIFPLR3_1_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000002 |
7834 | #define smnBIFPLR3_1_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000 |
7835 | #define smnBIFPLR3_1_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000 |
7836 | #define smnBIFPLR3_1_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000002 |
7837 | #define smnBIFPLR3_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000 |
7838 | #define smnBIFPLR3_1_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000 |
7839 | #define smnBIFPLR3_1_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000 |
7840 | #define smnBIFPLR3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x27020000 |
7841 | #define smnBIFPLR3_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 |
7842 | #define smnBIFPLR3_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00400000 |
7843 | #define smnBIFPLR3_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 |
7844 | #define smnBIFPLR3_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 |
7845 | #define smnBIFPLR3_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00006000 |
7846 | #define smnBIFPLR3_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 |
7847 | #define smnBIFPLR3_1_PCIE_HDR_LOG0_DEFAULT 0x00000000 |
7848 | #define smnBIFPLR3_1_PCIE_HDR_LOG1_DEFAULT 0x00000000 |
7849 | #define smnBIFPLR3_1_PCIE_HDR_LOG2_DEFAULT 0x00000000 |
7850 | #define smnBIFPLR3_1_PCIE_HDR_LOG3_DEFAULT 0x00000000 |
7851 | #define smnBIFPLR3_1_PCIE_ROOT_ERR_CMD_DEFAULT 0x00000000 |
7852 | #define smnBIFPLR3_1_PCIE_ROOT_ERR_STATUS_DEFAULT 0x00000000 |
7853 | #define smnBIFPLR3_1_PCIE_ERR_SRC_ID_DEFAULT 0x00000000 |
7854 | #define smnBIFPLR3_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 |
7855 | #define smnBIFPLR3_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 |
7856 | #define smnBIFPLR3_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 |
7857 | #define smnBIFPLR3_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 |
7858 | #define smnBIFPLR3_1_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a000000 |
7859 | #define smnBIFPLR3_1_PCIE_LINK_CNTL3_DEFAULT 0x00000000 |
7860 | #define smnBIFPLR3_1_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000 |
7861 | #define smnBIFPLR3_1_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
7862 | #define smnBIFPLR3_1_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
7863 | #define smnBIFPLR3_1_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
7864 | #define smnBIFPLR3_1_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
7865 | #define smnBIFPLR3_1_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
7866 | #define smnBIFPLR3_1_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
7867 | #define smnBIFPLR3_1_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
7868 | #define smnBIFPLR3_1_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
7869 | #define smnBIFPLR3_1_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
7870 | #define smnBIFPLR3_1_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
7871 | #define smnBIFPLR3_1_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
7872 | #define smnBIFPLR3_1_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
7873 | #define smnBIFPLR3_1_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
7874 | #define smnBIFPLR3_1_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
7875 | #define smnBIFPLR3_1_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
7876 | #define smnBIFPLR3_1_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
7877 | #define smnBIFPLR3_1_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2f000000 |
7878 | #define smnBIFPLR3_1_PCIE_ACS_CAP_DEFAULT 0x00000000 |
7879 | #define smnBIFPLR3_1_PCIE_ACS_CNTL_DEFAULT 0x00000000 |
7880 | #define smnBIFPLR3_1_PCIE_MC_ENH_CAP_LIST_DEFAULT 0x32000000 |
7881 | #define smnBIFPLR3_1_PCIE_MC_CAP_DEFAULT 0x00000000 |
7882 | #define smnBIFPLR3_1_PCIE_MC_CNTL_DEFAULT 0x00000000 |
7883 | #define smnBIFPLR3_1_PCIE_MC_ADDR0_DEFAULT 0x00000000 |
7884 | #define smnBIFPLR3_1_PCIE_MC_ADDR1_DEFAULT 0x00000000 |
7885 | #define smnBIFPLR3_1_PCIE_MC_RCV0_DEFAULT 0x00000000 |
7886 | #define smnBIFPLR3_1_PCIE_MC_RCV1_DEFAULT 0x00000000 |
7887 | #define smnBIFPLR3_1_PCIE_MC_BLOCK_ALL0_DEFAULT 0x00000000 |
7888 | #define smnBIFPLR3_1_PCIE_MC_BLOCK_ALL1_DEFAULT 0x00000000 |
7889 | #define smnBIFPLR3_1_PCIE_MC_BLOCK_UNTRANSLATED_0_DEFAULT 0x00000000 |
7890 | #define smnBIFPLR3_1_PCIE_MC_BLOCK_UNTRANSLATED_1_DEFAULT 0x00000000 |
7891 | #define smnBIFPLR3_1_PCIE_MC_OVERLAY_BAR0_DEFAULT 0x00000000 |
7892 | #define smnBIFPLR3_1_PCIE_MC_OVERLAY_BAR1_DEFAULT 0x00000000 |
7893 | #define smnBIFPLR3_1_PCIE_L1_PM_SUB_CAP_LIST_DEFAULT 0x00000000 |
7894 | #define smnBIFPLR3_1_PCIE_L1_PM_SUB_CAP_DEFAULT 0x00000000 |
7895 | #define smnBIFPLR3_1_PCIE_L1_PM_SUB_CNTL_DEFAULT 0x00000000 |
7896 | #define smnBIFPLR3_1_PCIE_L1_PM_SUB_CNTL2_DEFAULT 0x00000028 |
7897 | #define smnBIFPLR3_1_PCIE_DPC_ENH_CAP_LIST_DEFAULT 0x00000000 |
7898 | #define smnBIFPLR3_1_PCIE_DPC_CAP_LIST_DEFAULT 0x00000000 |
7899 | #define smnBIFPLR3_1_PCIE_DPC_CNTL_DEFAULT 0x00000000 |
7900 | #define smnBIFPLR3_1_PCIE_DPC_STATUS_DEFAULT 0x00000000 |
7901 | #define smnBIFPLR3_1_PCIE_DPC_ERROR_SOURCE_ID_DEFAULT 0x00000000 |
7902 | #define smnBIFPLR3_1_PCIE_RP_PIO_STATUS_DEFAULT 0x00000000 |
7903 | #define smnBIFPLR3_1_PCIE_RP_PIO_MASK_DEFAULT 0x00070707 |
7904 | #define smnBIFPLR3_1_PCIE_RP_PIO_SEVERITY_DEFAULT 0x00000000 |
7905 | #define smnBIFPLR3_1_PCIE_RP_PIO_SYSERROR_DEFAULT 0x00000000 |
7906 | #define smnBIFPLR3_1_PCIE_RP_PIO_EXCEPTION_DEFAULT 0x00000000 |
7907 | #define smnBIFPLR3_1_PCIE_RP_PIO_HDR_LOG0_DEFAULT 0x00000000 |
7908 | #define smnBIFPLR3_1_PCIE_RP_PIO_HDR_LOG1_DEFAULT 0x00000000 |
7909 | #define smnBIFPLR3_1_PCIE_RP_PIO_HDR_LOG2_DEFAULT 0x00000000 |
7910 | #define smnBIFPLR3_1_PCIE_RP_PIO_HDR_LOG3_DEFAULT 0x00000000 |
7911 | #define smnBIFPLR3_1_PCIE_RP_PIO_IMPSPEC_LOG_DEFAULT 0x00000000 |
7912 | #define smnBIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG0_DEFAULT 0x00000000 |
7913 | #define smnBIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG1_DEFAULT 0x00000000 |
7914 | #define smnBIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG2_DEFAULT 0x00000000 |
7915 | #define smnBIFPLR3_1_PCIE_RP_PIO_PREFIX_LOG3_DEFAULT 0x00000000 |
7916 | #define smnBIFPLR3_1_PCIE_ESM_CAP_LIST_DEFAULT 0x00000000 |
7917 | #define 0x00000000 |
7918 | #define 0x00000000 |
7919 | #define smnBIFPLR3_1_PCIE_ESM_STATUS_DEFAULT 0x00000000 |
7920 | #define smnBIFPLR3_1_PCIE_ESM_CTRL_DEFAULT 0x00000000 |
7921 | #define smnBIFPLR3_1_PCIE_ESM_CAP_1_DEFAULT 0x00000000 |
7922 | #define smnBIFPLR3_1_PCIE_ESM_CAP_2_DEFAULT 0x00000000 |
7923 | #define smnBIFPLR3_1_PCIE_ESM_CAP_3_DEFAULT 0x00000000 |
7924 | #define smnBIFPLR3_1_PCIE_ESM_CAP_4_DEFAULT 0x00000000 |
7925 | #define smnBIFPLR3_1_PCIE_ESM_CAP_5_DEFAULT 0x00000000 |
7926 | #define smnBIFPLR3_1_PCIE_ESM_CAP_6_DEFAULT 0x00000000 |
7927 | #define smnBIFPLR3_1_PCIE_ESM_CAP_7_DEFAULT 0x00000000 |
7928 | |
7929 | |
7930 | // addressBlock: nbio_pcie0_bifplr4_cfgdecp |
7931 | #define smnBIFPLR4_1_VENDOR_ID_DEFAULT 0x00000000 |
7932 | #define smnBIFPLR4_1_DEVICE_ID_DEFAULT 0x00000000 |
7933 | #define smnBIFPLR4_1_COMMAND_DEFAULT 0x00000000 |
7934 | #define smnBIFPLR4_1_STATUS_DEFAULT 0x00000000 |
7935 | #define smnBIFPLR4_1_REVISION_ID_DEFAULT 0x00000000 |
7936 | #define smnBIFPLR4_1_PROG_INTERFACE_DEFAULT 0x00000000 |
7937 | #define smnBIFPLR4_1_SUB_CLASS_DEFAULT 0x00000000 |
7938 | #define smnBIFPLR4_1_BASE_CLASS_DEFAULT 0x00000000 |
7939 | #define smnBIFPLR4_1_CACHE_LINE_DEFAULT 0x00000000 |
7940 | #define smnBIFPLR4_1_LATENCY_DEFAULT 0x00000000 |
7941 | #define 0x00000000 |
7942 | #define smnBIFPLR4_1_BIST_DEFAULT 0x00000000 |
7943 | #define smnBIFPLR4_1_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 |
7944 | #define smnBIFPLR4_1_IO_BASE_LIMIT_DEFAULT 0x00000000 |
7945 | #define smnBIFPLR4_1_SECONDARY_STATUS_DEFAULT 0x00000000 |
7946 | #define smnBIFPLR4_1_MEM_BASE_LIMIT_DEFAULT 0x00000000 |
7947 | #define smnBIFPLR4_1_PREF_BASE_LIMIT_DEFAULT 0x00000000 |
7948 | #define smnBIFPLR4_1_PREF_BASE_UPPER_DEFAULT 0x00000000 |
7949 | #define smnBIFPLR4_1_PREF_LIMIT_UPPER_DEFAULT 0x00000000 |
7950 | #define smnBIFPLR4_1_IO_BASE_LIMIT_HI_DEFAULT 0x00000000 |
7951 | #define smnBIFPLR4_1_CAP_PTR_DEFAULT 0x00000000 |
7952 | #define smnBIFPLR4_1_INTERRUPT_LINE_DEFAULT 0x000000ff |
7953 | #define smnBIFPLR4_1_INTERRUPT_PIN_DEFAULT 0x00000000 |
7954 | #define smnBIFPLR4_1_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000 |
7955 | #define smnBIFPLR4_1_EXT_BRIDGE_CNTL_DEFAULT 0x00000000 |
7956 | #define smnBIFPLR4_1_PMI_CAP_LIST_DEFAULT 0x00000000 |
7957 | #define smnBIFPLR4_1_PMI_CAP_DEFAULT 0x00000000 |
7958 | #define smnBIFPLR4_1_PMI_STATUS_CNTL_DEFAULT 0x00000000 |
7959 | #define smnBIFPLR4_1_PCIE_CAP_LIST_DEFAULT 0x0000a000 |
7960 | #define smnBIFPLR4_1_PCIE_CAP_DEFAULT 0x00000002 |
7961 | #define smnBIFPLR4_1_DEVICE_CAP_DEFAULT 0x00000000 |
7962 | #define smnBIFPLR4_1_DEVICE_CNTL_DEFAULT 0x00002810 |
7963 | #define smnBIFPLR4_1_DEVICE_STATUS_DEFAULT 0x00000000 |
7964 | #define smnBIFPLR4_1_LINK_CAP_DEFAULT 0x00011c03 |
7965 | #define smnBIFPLR4_1_LINK_CNTL_DEFAULT 0x00000000 |
7966 | #define smnBIFPLR4_1_LINK_STATUS_DEFAULT 0x00000001 |
7967 | #define smnBIFPLR4_1_SLOT_CAP_DEFAULT 0x00000000 |
7968 | #define smnBIFPLR4_1_SLOT_CNTL_DEFAULT 0x00000000 |
7969 | #define smnBIFPLR4_1_SLOT_STATUS_DEFAULT 0x00000000 |
7970 | #define smnBIFPLR4_1_ROOT_CNTL_DEFAULT 0x00000000 |
7971 | #define smnBIFPLR4_1_ROOT_CAP_DEFAULT 0x00000000 |
7972 | #define smnBIFPLR4_1_ROOT_STATUS_DEFAULT 0x00000000 |
7973 | #define smnBIFPLR4_1_DEVICE_CAP2_DEFAULT 0x00000000 |
7974 | #define smnBIFPLR4_1_DEVICE_CNTL2_DEFAULT 0x00000000 |
7975 | #define smnBIFPLR4_1_DEVICE_STATUS2_DEFAULT 0x00000000 |
7976 | #define smnBIFPLR4_1_LINK_CAP2_DEFAULT 0x0000000e |
7977 | #define smnBIFPLR4_1_LINK_CNTL2_DEFAULT 0x00000003 |
7978 | #define smnBIFPLR4_1_LINK_STATUS2_DEFAULT 0x00000000 |
7979 | #define smnBIFPLR4_1_SLOT_CAP2_DEFAULT 0x00000000 |
7980 | #define smnBIFPLR4_1_SLOT_CNTL2_DEFAULT 0x00000000 |
7981 | #define smnBIFPLR4_1_SLOT_STATUS2_DEFAULT 0x00000000 |
7982 | #define smnBIFPLR4_1_MSI_CAP_LIST_DEFAULT 0x0000c000 |
7983 | #define smnBIFPLR4_1_MSI_MSG_CNTL_DEFAULT 0x00000000 |
7984 | #define smnBIFPLR4_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 |
7985 | #define smnBIFPLR4_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 |
7986 | #define smnBIFPLR4_1_MSI_MSG_DATA_DEFAULT 0x00000000 |
7987 | #define smnBIFPLR4_1_MSI_MSG_DATA_64_DEFAULT 0x00000000 |
7988 | #define smnBIFPLR4_1_SSID_CAP_LIST_DEFAULT 0x0000c800 |
7989 | #define smnBIFPLR4_1_SSID_CAP_DEFAULT 0x00000000 |
7990 | #define smnBIFPLR4_1_MSI_MAP_CAP_LIST_DEFAULT 0x00000000 |
7991 | #define smnBIFPLR4_1_MSI_MAP_CAP_DEFAULT 0x00000000 |
7992 | #define smnBIFPLR4_1_MSI_MAP_ADDR_LO_DEFAULT 0x00000000 |
7993 | #define smnBIFPLR4_1_MSI_MAP_ADDR_HI_DEFAULT 0x00000000 |
7994 | #define smnBIFPLR4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 |
7995 | #define smnBIFPLR4_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 |
7996 | #define smnBIFPLR4_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 |
7997 | #define smnBIFPLR4_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 |
7998 | #define smnBIFPLR4_1_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000 |
7999 | #define smnBIFPLR4_1_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000 |
8000 | #define smnBIFPLR4_1_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000 |
8001 | #define smnBIFPLR4_1_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000 |
8002 | #define smnBIFPLR4_1_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000 |
8003 | #define smnBIFPLR4_1_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000 |
8004 | #define smnBIFPLR4_1_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe |
8005 | #define smnBIFPLR4_1_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000002 |
8006 | #define smnBIFPLR4_1_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000 |
8007 | #define smnBIFPLR4_1_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000 |
8008 | #define smnBIFPLR4_1_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000002 |
8009 | #define smnBIFPLR4_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000 |
8010 | #define smnBIFPLR4_1_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000 |
8011 | #define smnBIFPLR4_1_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000 |
8012 | #define smnBIFPLR4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x27020000 |
8013 | #define smnBIFPLR4_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 |
8014 | #define smnBIFPLR4_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00400000 |
8015 | #define smnBIFPLR4_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 |
8016 | #define smnBIFPLR4_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 |
8017 | #define smnBIFPLR4_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00006000 |
8018 | #define smnBIFPLR4_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 |
8019 | #define smnBIFPLR4_1_PCIE_HDR_LOG0_DEFAULT 0x00000000 |
8020 | #define smnBIFPLR4_1_PCIE_HDR_LOG1_DEFAULT 0x00000000 |
8021 | #define smnBIFPLR4_1_PCIE_HDR_LOG2_DEFAULT 0x00000000 |
8022 | #define smnBIFPLR4_1_PCIE_HDR_LOG3_DEFAULT 0x00000000 |
8023 | #define smnBIFPLR4_1_PCIE_ROOT_ERR_CMD_DEFAULT 0x00000000 |
8024 | #define smnBIFPLR4_1_PCIE_ROOT_ERR_STATUS_DEFAULT 0x00000000 |
8025 | #define smnBIFPLR4_1_PCIE_ERR_SRC_ID_DEFAULT 0x00000000 |
8026 | #define smnBIFPLR4_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 |
8027 | #define smnBIFPLR4_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 |
8028 | #define smnBIFPLR4_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 |
8029 | #define smnBIFPLR4_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 |
8030 | #define smnBIFPLR4_1_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a000000 |
8031 | #define smnBIFPLR4_1_PCIE_LINK_CNTL3_DEFAULT 0x00000000 |
8032 | #define smnBIFPLR4_1_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000 |
8033 | #define smnBIFPLR4_1_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
8034 | #define smnBIFPLR4_1_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
8035 | #define smnBIFPLR4_1_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
8036 | #define smnBIFPLR4_1_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
8037 | #define smnBIFPLR4_1_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
8038 | #define smnBIFPLR4_1_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
8039 | #define smnBIFPLR4_1_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
8040 | #define smnBIFPLR4_1_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
8041 | #define smnBIFPLR4_1_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
8042 | #define smnBIFPLR4_1_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
8043 | #define smnBIFPLR4_1_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
8044 | #define smnBIFPLR4_1_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
8045 | #define smnBIFPLR4_1_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
8046 | #define smnBIFPLR4_1_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
8047 | #define smnBIFPLR4_1_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
8048 | #define smnBIFPLR4_1_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
8049 | #define smnBIFPLR4_1_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2f000000 |
8050 | #define smnBIFPLR4_1_PCIE_ACS_CAP_DEFAULT 0x00000000 |
8051 | #define smnBIFPLR4_1_PCIE_ACS_CNTL_DEFAULT 0x00000000 |
8052 | #define smnBIFPLR4_1_PCIE_MC_ENH_CAP_LIST_DEFAULT 0x32000000 |
8053 | #define smnBIFPLR4_1_PCIE_MC_CAP_DEFAULT 0x00000000 |
8054 | #define smnBIFPLR4_1_PCIE_MC_CNTL_DEFAULT 0x00000000 |
8055 | #define smnBIFPLR4_1_PCIE_MC_ADDR0_DEFAULT 0x00000000 |
8056 | #define smnBIFPLR4_1_PCIE_MC_ADDR1_DEFAULT 0x00000000 |
8057 | #define smnBIFPLR4_1_PCIE_MC_RCV0_DEFAULT 0x00000000 |
8058 | #define smnBIFPLR4_1_PCIE_MC_RCV1_DEFAULT 0x00000000 |
8059 | #define smnBIFPLR4_1_PCIE_MC_BLOCK_ALL0_DEFAULT 0x00000000 |
8060 | #define smnBIFPLR4_1_PCIE_MC_BLOCK_ALL1_DEFAULT 0x00000000 |
8061 | #define smnBIFPLR4_1_PCIE_MC_BLOCK_UNTRANSLATED_0_DEFAULT 0x00000000 |
8062 | #define smnBIFPLR4_1_PCIE_MC_BLOCK_UNTRANSLATED_1_DEFAULT 0x00000000 |
8063 | #define smnBIFPLR4_1_PCIE_MC_OVERLAY_BAR0_DEFAULT 0x00000000 |
8064 | #define smnBIFPLR4_1_PCIE_MC_OVERLAY_BAR1_DEFAULT 0x00000000 |
8065 | #define smnBIFPLR4_1_PCIE_L1_PM_SUB_CAP_LIST_DEFAULT 0x00000000 |
8066 | #define smnBIFPLR4_1_PCIE_L1_PM_SUB_CAP_DEFAULT 0x00000000 |
8067 | #define smnBIFPLR4_1_PCIE_L1_PM_SUB_CNTL_DEFAULT 0x00000000 |
8068 | #define smnBIFPLR4_1_PCIE_L1_PM_SUB_CNTL2_DEFAULT 0x00000028 |
8069 | #define smnBIFPLR4_1_PCIE_DPC_ENH_CAP_LIST_DEFAULT 0x00000000 |
8070 | #define smnBIFPLR4_1_PCIE_DPC_CAP_LIST_DEFAULT 0x00000000 |
8071 | #define smnBIFPLR4_1_PCIE_DPC_CNTL_DEFAULT 0x00000000 |
8072 | #define smnBIFPLR4_1_PCIE_DPC_STATUS_DEFAULT 0x00000000 |
8073 | #define smnBIFPLR4_1_PCIE_DPC_ERROR_SOURCE_ID_DEFAULT 0x00000000 |
8074 | #define smnBIFPLR4_1_PCIE_RP_PIO_STATUS_DEFAULT 0x00000000 |
8075 | #define smnBIFPLR4_1_PCIE_RP_PIO_MASK_DEFAULT 0x00070707 |
8076 | #define smnBIFPLR4_1_PCIE_RP_PIO_SEVERITY_DEFAULT 0x00000000 |
8077 | #define smnBIFPLR4_1_PCIE_RP_PIO_SYSERROR_DEFAULT 0x00000000 |
8078 | #define smnBIFPLR4_1_PCIE_RP_PIO_EXCEPTION_DEFAULT 0x00000000 |
8079 | #define smnBIFPLR4_1_PCIE_RP_PIO_HDR_LOG0_DEFAULT 0x00000000 |
8080 | #define smnBIFPLR4_1_PCIE_RP_PIO_HDR_LOG1_DEFAULT 0x00000000 |
8081 | #define smnBIFPLR4_1_PCIE_RP_PIO_HDR_LOG2_DEFAULT 0x00000000 |
8082 | #define smnBIFPLR4_1_PCIE_RP_PIO_HDR_LOG3_DEFAULT 0x00000000 |
8083 | #define smnBIFPLR4_1_PCIE_RP_PIO_IMPSPEC_LOG_DEFAULT 0x00000000 |
8084 | #define smnBIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG0_DEFAULT 0x00000000 |
8085 | #define smnBIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG1_DEFAULT 0x00000000 |
8086 | #define smnBIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG2_DEFAULT 0x00000000 |
8087 | #define smnBIFPLR4_1_PCIE_RP_PIO_PREFIX_LOG3_DEFAULT 0x00000000 |
8088 | #define smnBIFPLR4_1_PCIE_ESM_CAP_LIST_DEFAULT 0x00000000 |
8089 | #define 0x00000000 |
8090 | #define 0x00000000 |
8091 | #define smnBIFPLR4_1_PCIE_ESM_STATUS_DEFAULT 0x00000000 |
8092 | #define smnBIFPLR4_1_PCIE_ESM_CTRL_DEFAULT 0x00000000 |
8093 | #define smnBIFPLR4_1_PCIE_ESM_CAP_1_DEFAULT 0x00000000 |
8094 | #define smnBIFPLR4_1_PCIE_ESM_CAP_2_DEFAULT 0x00000000 |
8095 | #define smnBIFPLR4_1_PCIE_ESM_CAP_3_DEFAULT 0x00000000 |
8096 | #define smnBIFPLR4_1_PCIE_ESM_CAP_4_DEFAULT 0x00000000 |
8097 | #define smnBIFPLR4_1_PCIE_ESM_CAP_5_DEFAULT 0x00000000 |
8098 | #define smnBIFPLR4_1_PCIE_ESM_CAP_6_DEFAULT 0x00000000 |
8099 | #define smnBIFPLR4_1_PCIE_ESM_CAP_7_DEFAULT 0x00000000 |
8100 | |
8101 | |
8102 | // addressBlock: nbio_pcie0_bifplr5_cfgdecp |
8103 | #define smnBIFPLR5_1_VENDOR_ID_DEFAULT 0x00000000 |
8104 | #define smnBIFPLR5_1_DEVICE_ID_DEFAULT 0x00000000 |
8105 | #define smnBIFPLR5_1_COMMAND_DEFAULT 0x00000000 |
8106 | #define smnBIFPLR5_1_STATUS_DEFAULT 0x00000000 |
8107 | #define smnBIFPLR5_1_REVISION_ID_DEFAULT 0x00000000 |
8108 | #define smnBIFPLR5_1_PROG_INTERFACE_DEFAULT 0x00000000 |
8109 | #define smnBIFPLR5_1_SUB_CLASS_DEFAULT 0x00000000 |
8110 | #define smnBIFPLR5_1_BASE_CLASS_DEFAULT 0x00000000 |
8111 | #define smnBIFPLR5_1_CACHE_LINE_DEFAULT 0x00000000 |
8112 | #define smnBIFPLR5_1_LATENCY_DEFAULT 0x00000000 |
8113 | #define 0x00000000 |
8114 | #define smnBIFPLR5_1_BIST_DEFAULT 0x00000000 |
8115 | #define smnBIFPLR5_1_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 |
8116 | #define smnBIFPLR5_1_IO_BASE_LIMIT_DEFAULT 0x00000000 |
8117 | #define smnBIFPLR5_1_SECONDARY_STATUS_DEFAULT 0x00000000 |
8118 | #define smnBIFPLR5_1_MEM_BASE_LIMIT_DEFAULT 0x00000000 |
8119 | #define smnBIFPLR5_1_PREF_BASE_LIMIT_DEFAULT 0x00000000 |
8120 | #define smnBIFPLR5_1_PREF_BASE_UPPER_DEFAULT 0x00000000 |
8121 | #define smnBIFPLR5_1_PREF_LIMIT_UPPER_DEFAULT 0x00000000 |
8122 | #define smnBIFPLR5_1_IO_BASE_LIMIT_HI_DEFAULT 0x00000000 |
8123 | #define smnBIFPLR5_1_CAP_PTR_DEFAULT 0x00000000 |
8124 | #define smnBIFPLR5_1_INTERRUPT_LINE_DEFAULT 0x000000ff |
8125 | #define smnBIFPLR5_1_INTERRUPT_PIN_DEFAULT 0x00000000 |
8126 | #define smnBIFPLR5_1_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000 |
8127 | #define smnBIFPLR5_1_EXT_BRIDGE_CNTL_DEFAULT 0x00000000 |
8128 | #define smnBIFPLR5_1_PMI_CAP_LIST_DEFAULT 0x00000000 |
8129 | #define smnBIFPLR5_1_PMI_CAP_DEFAULT 0x00000000 |
8130 | #define smnBIFPLR5_1_PMI_STATUS_CNTL_DEFAULT 0x00000000 |
8131 | #define smnBIFPLR5_1_PCIE_CAP_LIST_DEFAULT 0x0000a000 |
8132 | #define smnBIFPLR5_1_PCIE_CAP_DEFAULT 0x00000002 |
8133 | #define smnBIFPLR5_1_DEVICE_CAP_DEFAULT 0x00000000 |
8134 | #define smnBIFPLR5_1_DEVICE_CNTL_DEFAULT 0x00002810 |
8135 | #define smnBIFPLR5_1_DEVICE_STATUS_DEFAULT 0x00000000 |
8136 | #define smnBIFPLR5_1_LINK_CAP_DEFAULT 0x00011c03 |
8137 | #define smnBIFPLR5_1_LINK_CNTL_DEFAULT 0x00000000 |
8138 | #define smnBIFPLR5_1_LINK_STATUS_DEFAULT 0x00000001 |
8139 | #define smnBIFPLR5_1_SLOT_CAP_DEFAULT 0x00000000 |
8140 | #define smnBIFPLR5_1_SLOT_CNTL_DEFAULT 0x00000000 |
8141 | #define smnBIFPLR5_1_SLOT_STATUS_DEFAULT 0x00000000 |
8142 | #define smnBIFPLR5_1_ROOT_CNTL_DEFAULT 0x00000000 |
8143 | #define smnBIFPLR5_1_ROOT_CAP_DEFAULT 0x00000000 |
8144 | #define smnBIFPLR5_1_ROOT_STATUS_DEFAULT 0x00000000 |
8145 | #define smnBIFPLR5_1_DEVICE_CAP2_DEFAULT 0x00000000 |
8146 | #define smnBIFPLR5_1_DEVICE_CNTL2_DEFAULT 0x00000000 |
8147 | #define smnBIFPLR5_1_DEVICE_STATUS2_DEFAULT 0x00000000 |
8148 | #define smnBIFPLR5_1_LINK_CAP2_DEFAULT 0x0000000e |
8149 | #define smnBIFPLR5_1_LINK_CNTL2_DEFAULT 0x00000003 |
8150 | #define smnBIFPLR5_1_LINK_STATUS2_DEFAULT 0x00000000 |
8151 | #define smnBIFPLR5_1_SLOT_CAP2_DEFAULT 0x00000000 |
8152 | #define smnBIFPLR5_1_SLOT_CNTL2_DEFAULT 0x00000000 |
8153 | #define smnBIFPLR5_1_SLOT_STATUS2_DEFAULT 0x00000000 |
8154 | #define smnBIFPLR5_1_MSI_CAP_LIST_DEFAULT 0x0000c000 |
8155 | #define smnBIFPLR5_1_MSI_MSG_CNTL_DEFAULT 0x00000000 |
8156 | #define smnBIFPLR5_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 |
8157 | #define smnBIFPLR5_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 |
8158 | #define smnBIFPLR5_1_MSI_MSG_DATA_DEFAULT 0x00000000 |
8159 | #define smnBIFPLR5_1_MSI_MSG_DATA_64_DEFAULT 0x00000000 |
8160 | #define smnBIFPLR5_1_SSID_CAP_LIST_DEFAULT 0x0000c800 |
8161 | #define smnBIFPLR5_1_SSID_CAP_DEFAULT 0x00000000 |
8162 | #define smnBIFPLR5_1_MSI_MAP_CAP_LIST_DEFAULT 0x00000000 |
8163 | #define smnBIFPLR5_1_MSI_MAP_CAP_DEFAULT 0x00000000 |
8164 | #define smnBIFPLR5_1_MSI_MAP_ADDR_LO_DEFAULT 0x00000000 |
8165 | #define smnBIFPLR5_1_MSI_MAP_ADDR_HI_DEFAULT 0x00000000 |
8166 | #define smnBIFPLR5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 |
8167 | #define smnBIFPLR5_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 |
8168 | #define smnBIFPLR5_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 |
8169 | #define smnBIFPLR5_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 |
8170 | #define smnBIFPLR5_1_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000 |
8171 | #define smnBIFPLR5_1_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000 |
8172 | #define smnBIFPLR5_1_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000 |
8173 | #define smnBIFPLR5_1_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000 |
8174 | #define smnBIFPLR5_1_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000 |
8175 | #define smnBIFPLR5_1_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000 |
8176 | #define smnBIFPLR5_1_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe |
8177 | #define smnBIFPLR5_1_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000002 |
8178 | #define smnBIFPLR5_1_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000 |
8179 | #define smnBIFPLR5_1_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000 |
8180 | #define smnBIFPLR5_1_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000002 |
8181 | #define smnBIFPLR5_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000 |
8182 | #define smnBIFPLR5_1_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000 |
8183 | #define smnBIFPLR5_1_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000 |
8184 | #define smnBIFPLR5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x27020000 |
8185 | #define smnBIFPLR5_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 |
8186 | #define smnBIFPLR5_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00400000 |
8187 | #define smnBIFPLR5_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 |
8188 | #define smnBIFPLR5_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 |
8189 | #define smnBIFPLR5_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00006000 |
8190 | #define smnBIFPLR5_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 |
8191 | #define smnBIFPLR5_1_PCIE_HDR_LOG0_DEFAULT 0x00000000 |
8192 | #define smnBIFPLR5_1_PCIE_HDR_LOG1_DEFAULT 0x00000000 |
8193 | #define smnBIFPLR5_1_PCIE_HDR_LOG2_DEFAULT 0x00000000 |
8194 | #define smnBIFPLR5_1_PCIE_HDR_LOG3_DEFAULT 0x00000000 |
8195 | #define smnBIFPLR5_1_PCIE_ROOT_ERR_CMD_DEFAULT 0x00000000 |
8196 | #define smnBIFPLR5_1_PCIE_ROOT_ERR_STATUS_DEFAULT 0x00000000 |
8197 | #define smnBIFPLR5_1_PCIE_ERR_SRC_ID_DEFAULT 0x00000000 |
8198 | #define smnBIFPLR5_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 |
8199 | #define smnBIFPLR5_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 |
8200 | #define smnBIFPLR5_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 |
8201 | #define smnBIFPLR5_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 |
8202 | #define smnBIFPLR5_1_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a000000 |
8203 | #define smnBIFPLR5_1_PCIE_LINK_CNTL3_DEFAULT 0x00000000 |
8204 | #define smnBIFPLR5_1_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000 |
8205 | #define smnBIFPLR5_1_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
8206 | #define smnBIFPLR5_1_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
8207 | #define smnBIFPLR5_1_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
8208 | #define smnBIFPLR5_1_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
8209 | #define smnBIFPLR5_1_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
8210 | #define smnBIFPLR5_1_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
8211 | #define smnBIFPLR5_1_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
8212 | #define smnBIFPLR5_1_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
8213 | #define smnBIFPLR5_1_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
8214 | #define smnBIFPLR5_1_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
8215 | #define smnBIFPLR5_1_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
8216 | #define smnBIFPLR5_1_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
8217 | #define smnBIFPLR5_1_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
8218 | #define smnBIFPLR5_1_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
8219 | #define smnBIFPLR5_1_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
8220 | #define smnBIFPLR5_1_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
8221 | #define smnBIFPLR5_1_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2f000000 |
8222 | #define smnBIFPLR5_1_PCIE_ACS_CAP_DEFAULT 0x00000000 |
8223 | #define smnBIFPLR5_1_PCIE_ACS_CNTL_DEFAULT 0x00000000 |
8224 | #define smnBIFPLR5_1_PCIE_MC_ENH_CAP_LIST_DEFAULT 0x32000000 |
8225 | #define smnBIFPLR5_1_PCIE_MC_CAP_DEFAULT 0x00000000 |
8226 | #define smnBIFPLR5_1_PCIE_MC_CNTL_DEFAULT 0x00000000 |
8227 | #define smnBIFPLR5_1_PCIE_MC_ADDR0_DEFAULT 0x00000000 |
8228 | #define smnBIFPLR5_1_PCIE_MC_ADDR1_DEFAULT 0x00000000 |
8229 | #define smnBIFPLR5_1_PCIE_MC_RCV0_DEFAULT 0x00000000 |
8230 | #define smnBIFPLR5_1_PCIE_MC_RCV1_DEFAULT 0x00000000 |
8231 | #define smnBIFPLR5_1_PCIE_MC_BLOCK_ALL0_DEFAULT 0x00000000 |
8232 | #define smnBIFPLR5_1_PCIE_MC_BLOCK_ALL1_DEFAULT 0x00000000 |
8233 | #define smnBIFPLR5_1_PCIE_MC_BLOCK_UNTRANSLATED_0_DEFAULT 0x00000000 |
8234 | #define smnBIFPLR5_1_PCIE_MC_BLOCK_UNTRANSLATED_1_DEFAULT 0x00000000 |
8235 | #define smnBIFPLR5_1_PCIE_MC_OVERLAY_BAR0_DEFAULT 0x00000000 |
8236 | #define smnBIFPLR5_1_PCIE_MC_OVERLAY_BAR1_DEFAULT 0x00000000 |
8237 | #define smnBIFPLR5_1_PCIE_L1_PM_SUB_CAP_LIST_DEFAULT 0x00000000 |
8238 | #define smnBIFPLR5_1_PCIE_L1_PM_SUB_CAP_DEFAULT 0x00000000 |
8239 | #define smnBIFPLR5_1_PCIE_L1_PM_SUB_CNTL_DEFAULT 0x00000000 |
8240 | #define smnBIFPLR5_1_PCIE_L1_PM_SUB_CNTL2_DEFAULT 0x00000028 |
8241 | #define smnBIFPLR5_1_PCIE_DPC_ENH_CAP_LIST_DEFAULT 0x00000000 |
8242 | #define smnBIFPLR5_1_PCIE_DPC_CAP_LIST_DEFAULT 0x00000000 |
8243 | #define smnBIFPLR5_1_PCIE_DPC_CNTL_DEFAULT 0x00000000 |
8244 | #define smnBIFPLR5_1_PCIE_DPC_STATUS_DEFAULT 0x00000000 |
8245 | #define smnBIFPLR5_1_PCIE_DPC_ERROR_SOURCE_ID_DEFAULT 0x00000000 |
8246 | #define smnBIFPLR5_1_PCIE_RP_PIO_STATUS_DEFAULT 0x00000000 |
8247 | #define smnBIFPLR5_1_PCIE_RP_PIO_MASK_DEFAULT 0x00070707 |
8248 | #define smnBIFPLR5_1_PCIE_RP_PIO_SEVERITY_DEFAULT 0x00000000 |
8249 | #define smnBIFPLR5_1_PCIE_RP_PIO_SYSERROR_DEFAULT 0x00000000 |
8250 | #define smnBIFPLR5_1_PCIE_RP_PIO_EXCEPTION_DEFAULT 0x00000000 |
8251 | #define smnBIFPLR5_1_PCIE_RP_PIO_HDR_LOG0_DEFAULT 0x00000000 |
8252 | #define smnBIFPLR5_1_PCIE_RP_PIO_HDR_LOG1_DEFAULT 0x00000000 |
8253 | #define smnBIFPLR5_1_PCIE_RP_PIO_HDR_LOG2_DEFAULT 0x00000000 |
8254 | #define smnBIFPLR5_1_PCIE_RP_PIO_HDR_LOG3_DEFAULT 0x00000000 |
8255 | #define smnBIFPLR5_1_PCIE_RP_PIO_IMPSPEC_LOG_DEFAULT 0x00000000 |
8256 | #define smnBIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG0_DEFAULT 0x00000000 |
8257 | #define smnBIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG1_DEFAULT 0x00000000 |
8258 | #define smnBIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG2_DEFAULT 0x00000000 |
8259 | #define smnBIFPLR5_1_PCIE_RP_PIO_PREFIX_LOG3_DEFAULT 0x00000000 |
8260 | #define smnBIFPLR5_1_PCIE_ESM_CAP_LIST_DEFAULT 0x00000000 |
8261 | #define 0x00000000 |
8262 | #define 0x00000000 |
8263 | #define smnBIFPLR5_1_PCIE_ESM_STATUS_DEFAULT 0x00000000 |
8264 | #define smnBIFPLR5_1_PCIE_ESM_CTRL_DEFAULT 0x00000000 |
8265 | #define smnBIFPLR5_1_PCIE_ESM_CAP_1_DEFAULT 0x00000000 |
8266 | #define smnBIFPLR5_1_PCIE_ESM_CAP_2_DEFAULT 0x00000000 |
8267 | #define smnBIFPLR5_1_PCIE_ESM_CAP_3_DEFAULT 0x00000000 |
8268 | #define smnBIFPLR5_1_PCIE_ESM_CAP_4_DEFAULT 0x00000000 |
8269 | #define smnBIFPLR5_1_PCIE_ESM_CAP_5_DEFAULT 0x00000000 |
8270 | #define smnBIFPLR5_1_PCIE_ESM_CAP_6_DEFAULT 0x00000000 |
8271 | #define smnBIFPLR5_1_PCIE_ESM_CAP_7_DEFAULT 0x00000000 |
8272 | |
8273 | |
8274 | // addressBlock: nbio_pcie0_bifplr6_cfgdecp |
8275 | #define smnBIFPLR6_1_VENDOR_ID_DEFAULT 0x00000000 |
8276 | #define smnBIFPLR6_1_DEVICE_ID_DEFAULT 0x00000000 |
8277 | #define smnBIFPLR6_1_COMMAND_DEFAULT 0x00000000 |
8278 | #define smnBIFPLR6_1_STATUS_DEFAULT 0x00000000 |
8279 | #define smnBIFPLR6_1_REVISION_ID_DEFAULT 0x00000000 |
8280 | #define smnBIFPLR6_1_PROG_INTERFACE_DEFAULT 0x00000000 |
8281 | #define smnBIFPLR6_1_SUB_CLASS_DEFAULT 0x00000000 |
8282 | #define smnBIFPLR6_1_BASE_CLASS_DEFAULT 0x00000000 |
8283 | #define smnBIFPLR6_1_CACHE_LINE_DEFAULT 0x00000000 |
8284 | #define smnBIFPLR6_1_LATENCY_DEFAULT 0x00000000 |
8285 | #define 0x00000000 |
8286 | #define smnBIFPLR6_1_BIST_DEFAULT 0x00000000 |
8287 | #define smnBIFPLR6_1_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 |
8288 | #define smnBIFPLR6_1_IO_BASE_LIMIT_DEFAULT 0x00000000 |
8289 | #define smnBIFPLR6_1_SECONDARY_STATUS_DEFAULT 0x00000000 |
8290 | #define smnBIFPLR6_1_MEM_BASE_LIMIT_DEFAULT 0x00000000 |
8291 | #define smnBIFPLR6_1_PREF_BASE_LIMIT_DEFAULT 0x00000000 |
8292 | #define smnBIFPLR6_1_PREF_BASE_UPPER_DEFAULT 0x00000000 |
8293 | #define smnBIFPLR6_1_PREF_LIMIT_UPPER_DEFAULT 0x00000000 |
8294 | #define smnBIFPLR6_1_IO_BASE_LIMIT_HI_DEFAULT 0x00000000 |
8295 | #define smnBIFPLR6_1_CAP_PTR_DEFAULT 0x00000000 |
8296 | #define smnBIFPLR6_1_INTERRUPT_LINE_DEFAULT 0x000000ff |
8297 | #define smnBIFPLR6_1_INTERRUPT_PIN_DEFAULT 0x00000000 |
8298 | #define smnBIFPLR6_1_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000 |
8299 | #define smnBIFPLR6_1_EXT_BRIDGE_CNTL_DEFAULT 0x00000000 |
8300 | #define smnBIFPLR6_1_PMI_CAP_LIST_DEFAULT 0x00000000 |
8301 | #define smnBIFPLR6_1_PMI_CAP_DEFAULT 0x00000000 |
8302 | #define smnBIFPLR6_1_PMI_STATUS_CNTL_DEFAULT 0x00000000 |
8303 | #define smnBIFPLR6_1_PCIE_CAP_LIST_DEFAULT 0x0000a000 |
8304 | #define smnBIFPLR6_1_PCIE_CAP_DEFAULT 0x00000002 |
8305 | #define smnBIFPLR6_1_DEVICE_CAP_DEFAULT 0x00000000 |
8306 | #define smnBIFPLR6_1_DEVICE_CNTL_DEFAULT 0x00002810 |
8307 | #define smnBIFPLR6_1_DEVICE_STATUS_DEFAULT 0x00000000 |
8308 | #define smnBIFPLR6_1_LINK_CAP_DEFAULT 0x00011c03 |
8309 | #define smnBIFPLR6_1_LINK_CNTL_DEFAULT 0x00000000 |
8310 | #define smnBIFPLR6_1_LINK_STATUS_DEFAULT 0x00000001 |
8311 | #define smnBIFPLR6_1_SLOT_CAP_DEFAULT 0x00000000 |
8312 | #define smnBIFPLR6_1_SLOT_CNTL_DEFAULT 0x00000000 |
8313 | #define smnBIFPLR6_1_SLOT_STATUS_DEFAULT 0x00000000 |
8314 | #define smnBIFPLR6_1_ROOT_CNTL_DEFAULT 0x00000000 |
8315 | #define smnBIFPLR6_1_ROOT_CAP_DEFAULT 0x00000000 |
8316 | #define smnBIFPLR6_1_ROOT_STATUS_DEFAULT 0x00000000 |
8317 | #define smnBIFPLR6_1_DEVICE_CAP2_DEFAULT 0x00000000 |
8318 | #define smnBIFPLR6_1_DEVICE_CNTL2_DEFAULT 0x00000000 |
8319 | #define smnBIFPLR6_1_DEVICE_STATUS2_DEFAULT 0x00000000 |
8320 | #define smnBIFPLR6_1_LINK_CAP2_DEFAULT 0x0000000e |
8321 | #define smnBIFPLR6_1_LINK_CNTL2_DEFAULT 0x00000003 |
8322 | #define smnBIFPLR6_1_LINK_STATUS2_DEFAULT 0x00000000 |
8323 | #define smnBIFPLR6_1_SLOT_CAP2_DEFAULT 0x00000000 |
8324 | #define smnBIFPLR6_1_SLOT_CNTL2_DEFAULT 0x00000000 |
8325 | #define smnBIFPLR6_1_SLOT_STATUS2_DEFAULT 0x00000000 |
8326 | #define smnBIFPLR6_1_MSI_CAP_LIST_DEFAULT 0x0000c000 |
8327 | #define smnBIFPLR6_1_MSI_MSG_CNTL_DEFAULT 0x00000000 |
8328 | #define smnBIFPLR6_1_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 |
8329 | #define smnBIFPLR6_1_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 |
8330 | #define smnBIFPLR6_1_MSI_MSG_DATA_DEFAULT 0x00000000 |
8331 | #define smnBIFPLR6_1_MSI_MSG_DATA_64_DEFAULT 0x00000000 |
8332 | #define smnBIFPLR6_1_SSID_CAP_LIST_DEFAULT 0x0000c800 |
8333 | #define smnBIFPLR6_1_SSID_CAP_DEFAULT 0x00000000 |
8334 | #define smnBIFPLR6_1_MSI_MAP_CAP_LIST_DEFAULT 0x00000000 |
8335 | #define smnBIFPLR6_1_MSI_MAP_CAP_DEFAULT 0x00000000 |
8336 | #define smnBIFPLR6_1_MSI_MAP_ADDR_LO_DEFAULT 0x00000000 |
8337 | #define smnBIFPLR6_1_MSI_MAP_ADDR_HI_DEFAULT 0x00000000 |
8338 | #define smnBIFPLR6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 |
8339 | #define smnBIFPLR6_1_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 |
8340 | #define smnBIFPLR6_1_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 |
8341 | #define smnBIFPLR6_1_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 |
8342 | #define smnBIFPLR6_1_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000 |
8343 | #define smnBIFPLR6_1_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000 |
8344 | #define smnBIFPLR6_1_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000 |
8345 | #define smnBIFPLR6_1_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000 |
8346 | #define smnBIFPLR6_1_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000 |
8347 | #define smnBIFPLR6_1_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000 |
8348 | #define smnBIFPLR6_1_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe |
8349 | #define smnBIFPLR6_1_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000002 |
8350 | #define smnBIFPLR6_1_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000 |
8351 | #define smnBIFPLR6_1_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000 |
8352 | #define smnBIFPLR6_1_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000002 |
8353 | #define smnBIFPLR6_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000 |
8354 | #define smnBIFPLR6_1_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000 |
8355 | #define smnBIFPLR6_1_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000 |
8356 | #define smnBIFPLR6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x27020000 |
8357 | #define smnBIFPLR6_1_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 |
8358 | #define smnBIFPLR6_1_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00400000 |
8359 | #define smnBIFPLR6_1_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 |
8360 | #define smnBIFPLR6_1_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 |
8361 | #define smnBIFPLR6_1_PCIE_CORR_ERR_MASK_DEFAULT 0x00006000 |
8362 | #define smnBIFPLR6_1_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 |
8363 | #define smnBIFPLR6_1_PCIE_HDR_LOG0_DEFAULT 0x00000000 |
8364 | #define smnBIFPLR6_1_PCIE_HDR_LOG1_DEFAULT 0x00000000 |
8365 | #define smnBIFPLR6_1_PCIE_HDR_LOG2_DEFAULT 0x00000000 |
8366 | #define smnBIFPLR6_1_PCIE_HDR_LOG3_DEFAULT 0x00000000 |
8367 | #define smnBIFPLR6_1_PCIE_ROOT_ERR_CMD_DEFAULT 0x00000000 |
8368 | #define smnBIFPLR6_1_PCIE_ROOT_ERR_STATUS_DEFAULT 0x00000000 |
8369 | #define smnBIFPLR6_1_PCIE_ERR_SRC_ID_DEFAULT 0x00000000 |
8370 | #define smnBIFPLR6_1_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 |
8371 | #define smnBIFPLR6_1_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 |
8372 | #define smnBIFPLR6_1_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 |
8373 | #define smnBIFPLR6_1_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 |
8374 | #define smnBIFPLR6_1_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a000000 |
8375 | #define smnBIFPLR6_1_PCIE_LINK_CNTL3_DEFAULT 0x00000000 |
8376 | #define smnBIFPLR6_1_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000 |
8377 | #define smnBIFPLR6_1_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
8378 | #define smnBIFPLR6_1_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
8379 | #define smnBIFPLR6_1_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
8380 | #define smnBIFPLR6_1_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
8381 | #define smnBIFPLR6_1_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
8382 | #define smnBIFPLR6_1_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
8383 | #define smnBIFPLR6_1_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
8384 | #define smnBIFPLR6_1_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
8385 | #define smnBIFPLR6_1_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
8386 | #define smnBIFPLR6_1_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
8387 | #define smnBIFPLR6_1_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
8388 | #define smnBIFPLR6_1_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
8389 | #define smnBIFPLR6_1_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
8390 | #define smnBIFPLR6_1_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
8391 | #define smnBIFPLR6_1_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
8392 | #define smnBIFPLR6_1_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
8393 | #define smnBIFPLR6_1_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2f000000 |
8394 | #define smnBIFPLR6_1_PCIE_ACS_CAP_DEFAULT 0x00000000 |
8395 | #define smnBIFPLR6_1_PCIE_ACS_CNTL_DEFAULT 0x00000000 |
8396 | #define smnBIFPLR6_1_PCIE_MC_ENH_CAP_LIST_DEFAULT 0x32000000 |
8397 | #define smnBIFPLR6_1_PCIE_MC_CAP_DEFAULT 0x00000000 |
8398 | #define smnBIFPLR6_1_PCIE_MC_CNTL_DEFAULT 0x00000000 |
8399 | #define smnBIFPLR6_1_PCIE_MC_ADDR0_DEFAULT 0x00000000 |
8400 | #define smnBIFPLR6_1_PCIE_MC_ADDR1_DEFAULT 0x00000000 |
8401 | #define smnBIFPLR6_1_PCIE_MC_RCV0_DEFAULT 0x00000000 |
8402 | #define smnBIFPLR6_1_PCIE_MC_RCV1_DEFAULT 0x00000000 |
8403 | #define smnBIFPLR6_1_PCIE_MC_BLOCK_ALL0_DEFAULT 0x00000000 |
8404 | #define smnBIFPLR6_1_PCIE_MC_BLOCK_ALL1_DEFAULT 0x00000000 |
8405 | #define smnBIFPLR6_1_PCIE_MC_BLOCK_UNTRANSLATED_0_DEFAULT 0x00000000 |
8406 | #define smnBIFPLR6_1_PCIE_MC_BLOCK_UNTRANSLATED_1_DEFAULT 0x00000000 |
8407 | #define smnBIFPLR6_1_PCIE_MC_OVERLAY_BAR0_DEFAULT 0x00000000 |
8408 | #define smnBIFPLR6_1_PCIE_MC_OVERLAY_BAR1_DEFAULT 0x00000000 |
8409 | #define smnBIFPLR6_1_PCIE_L1_PM_SUB_CAP_LIST_DEFAULT 0x00000000 |
8410 | #define smnBIFPLR6_1_PCIE_L1_PM_SUB_CAP_DEFAULT 0x00000000 |
8411 | #define smnBIFPLR6_1_PCIE_L1_PM_SUB_CNTL_DEFAULT 0x00000000 |
8412 | #define smnBIFPLR6_1_PCIE_L1_PM_SUB_CNTL2_DEFAULT 0x00000028 |
8413 | #define smnBIFPLR6_1_PCIE_DPC_ENH_CAP_LIST_DEFAULT 0x00000000 |
8414 | #define smnBIFPLR6_1_PCIE_DPC_CAP_LIST_DEFAULT 0x00000000 |
8415 | #define smnBIFPLR6_1_PCIE_DPC_CNTL_DEFAULT 0x00000000 |
8416 | #define smnBIFPLR6_1_PCIE_DPC_STATUS_DEFAULT 0x00000000 |
8417 | #define smnBIFPLR6_1_PCIE_DPC_ERROR_SOURCE_ID_DEFAULT 0x00000000 |
8418 | #define smnBIFPLR6_1_PCIE_RP_PIO_STATUS_DEFAULT 0x00000000 |
8419 | #define smnBIFPLR6_1_PCIE_RP_PIO_MASK_DEFAULT 0x00070707 |
8420 | #define smnBIFPLR6_1_PCIE_RP_PIO_SEVERITY_DEFAULT 0x00000000 |
8421 | #define smnBIFPLR6_1_PCIE_RP_PIO_SYSERROR_DEFAULT 0x00000000 |
8422 | #define smnBIFPLR6_1_PCIE_RP_PIO_EXCEPTION_DEFAULT 0x00000000 |
8423 | #define smnBIFPLR6_1_PCIE_RP_PIO_HDR_LOG0_DEFAULT 0x00000000 |
8424 | #define smnBIFPLR6_1_PCIE_RP_PIO_HDR_LOG1_DEFAULT 0x00000000 |
8425 | #define smnBIFPLR6_1_PCIE_RP_PIO_HDR_LOG2_DEFAULT 0x00000000 |
8426 | #define smnBIFPLR6_1_PCIE_RP_PIO_HDR_LOG3_DEFAULT 0x00000000 |
8427 | #define smnBIFPLR6_1_PCIE_RP_PIO_IMPSPEC_LOG_DEFAULT 0x00000000 |
8428 | #define smnBIFPLR6_1_PCIE_RP_PIO_PREFIX_LOG0_DEFAULT 0x00000000 |
8429 | #define smnBIFPLR6_1_PCIE_RP_PIO_PREFIX_LOG1_DEFAULT 0x00000000 |
8430 | #define smnBIFPLR6_1_PCIE_RP_PIO_PREFIX_LOG2_DEFAULT 0x00000000 |
8431 | #define smnBIFPLR6_1_PCIE_RP_PIO_PREFIX_LOG3_DEFAULT 0x00000000 |
8432 | #define smnBIFPLR6_1_PCIE_ESM_CAP_LIST_DEFAULT 0x00000000 |
8433 | #define 0x00000000 |
8434 | #define 0x00000000 |
8435 | #define smnBIFPLR6_1_PCIE_ESM_STATUS_DEFAULT 0x00000000 |
8436 | #define smnBIFPLR6_1_PCIE_ESM_CTRL_DEFAULT 0x00000000 |
8437 | #define smnBIFPLR6_1_PCIE_ESM_CAP_1_DEFAULT 0x00000000 |
8438 | #define smnBIFPLR6_1_PCIE_ESM_CAP_2_DEFAULT 0x00000000 |
8439 | #define smnBIFPLR6_1_PCIE_ESM_CAP_3_DEFAULT 0x00000000 |
8440 | #define smnBIFPLR6_1_PCIE_ESM_CAP_4_DEFAULT 0x00000000 |
8441 | #define smnBIFPLR6_1_PCIE_ESM_CAP_5_DEFAULT 0x00000000 |
8442 | #define smnBIFPLR6_1_PCIE_ESM_CAP_6_DEFAULT 0x00000000 |
8443 | #define smnBIFPLR6_1_PCIE_ESM_CAP_7_DEFAULT 0x00000000 |
8444 | |
8445 | |
8446 | // addressBlock: nbio_pcie0_bifp0_pciedir_p |
8447 | #define smnBIFP0_PCIEP_RESERVED_DEFAULT 0x00000000 |
8448 | #define smnBIFP0_PCIEP_SCRATCH_DEFAULT 0x00000000 |
8449 | #define smnBIFP0_PCIEP_PORT_CNTL_DEFAULT 0x00010009 |
8450 | #define smnBIFP0_PCIE_TX_CNTL_DEFAULT 0x00508000 |
8451 | #define smnBIFP0_PCIE_TX_REQUESTER_ID_DEFAULT 0x00000000 |
8452 | #define smnBIFP0_PCIE_TX_VENDOR_SPECIFIC_DEFAULT 0x00000000 |
8453 | #define smnBIFP0_PCIE_TX_REQUEST_NUM_CNTL_DEFAULT 0x02000000 |
8454 | #define smnBIFP0_PCIE_TX_SEQ_DEFAULT 0x00000000 |
8455 | #define smnBIFP0_PCIE_TX_REPLAY_DEFAULT 0x00900003 |
8456 | #define smnBIFP0_PCIE_TX_ACK_LATENCY_LIMIT_DEFAULT 0x00000000 |
8457 | #define smnBIFP0_PCIE_TX_CREDITS_ADVT_P_DEFAULT 0x00000000 |
8458 | #define smnBIFP0_PCIE_TX_CREDITS_ADVT_NP_DEFAULT 0x00000000 |
8459 | #define smnBIFP0_PCIE_TX_CREDITS_ADVT_CPL_DEFAULT 0x00000000 |
8460 | #define smnBIFP0_PCIE_TX_CREDITS_INIT_P_DEFAULT 0x00000000 |
8461 | #define smnBIFP0_PCIE_TX_CREDITS_INIT_NP_DEFAULT 0x00000000 |
8462 | #define smnBIFP0_PCIE_TX_CREDITS_INIT_CPL_DEFAULT 0x00000000 |
8463 | #define smnBIFP0_PCIE_TX_CREDITS_STATUS_DEFAULT 0x00000000 |
8464 | #define smnBIFP0_PCIE_TX_CREDITS_FCU_THRESHOLD_DEFAULT 0x03330333 |
8465 | #define smnBIFP0_PCIE_P_PORT_LANE_STATUS_DEFAULT 0x00000000 |
8466 | #define smnBIFP0_PCIE_FC_P_DEFAULT 0x00000208 |
8467 | #define smnBIFP0_PCIE_FC_NP_DEFAULT 0x00000202 |
8468 | #define smnBIFP0_PCIE_FC_CPL_DEFAULT 0x00000000 |
8469 | #define smnBIFP0_PCIE_ERR_CNTL_DEFAULT 0x00000500 |
8470 | #define smnBIFP0_PCIE_RX_CNTL_DEFAULT 0x01084000 |
8471 | #define smnBIFP0_PCIE_RX_EXPECTED_SEQNUM_DEFAULT 0x00000000 |
8472 | #define smnBIFP0_PCIE_RX_VENDOR_SPECIFIC_DEFAULT 0x00000000 |
8473 | #define smnBIFP0_PCIE_RX_CNTL3_DEFAULT 0x00000000 |
8474 | #define smnBIFP0_PCIE_RX_CREDITS_ALLOCATED_P_DEFAULT 0x00000000 |
8475 | #define smnBIFP0_PCIE_RX_CREDITS_ALLOCATED_NP_DEFAULT 0x00000000 |
8476 | #define smnBIFP0_PCIE_RX_CREDITS_ALLOCATED_CPL_DEFAULT 0x00000000 |
8477 | #define smnBIFP0_PCIEP_ERROR_INJECT_PHYSICAL_DEFAULT 0x00000000 |
8478 | #define smnBIFP0_PCIEP_ERROR_INJECT_TRANSACTION_DEFAULT 0x00000000 |
8479 | #define smnBIFP0_PCIEP_NAK_COUNTER_DEFAULT 0x00000000 |
8480 | #define smnBIFP0_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS_DEFAULT 0x00000000 |
8481 | #define smnBIFP0_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES_DEFAULT 0x00000000 |
8482 | #define smnBIFP0_PCIE_LC_CNTL_DEFAULT 0x40010030 |
8483 | #define smnBIFP0_PCIE_LC_TRAINING_CNTL_DEFAULT 0x94009880 |
8484 | #define smnBIFP0_PCIE_LC_LINK_WIDTH_CNTL_DEFAULT 0xda800006 |
8485 | #define smnBIFP0_PCIE_LC_N_FTS_CNTL_DEFAULT 0x00ff820c |
8486 | #define smnBIFP0_PCIE_LC_SPEED_CNTL_DEFAULT 0x04400100 |
8487 | #define smnBIFP0_PCIE_LC_STATE0_DEFAULT 0x00000000 |
8488 | #define smnBIFP0_PCIE_LC_STATE1_DEFAULT 0x00000000 |
8489 | #define smnBIFP0_PCIE_LC_STATE2_DEFAULT 0x00000000 |
8490 | #define smnBIFP0_PCIE_LC_STATE3_DEFAULT 0x00000000 |
8491 | #define smnBIFP0_PCIE_LC_STATE4_DEFAULT 0x00000000 |
8492 | #define smnBIFP0_PCIE_LC_STATE5_DEFAULT 0x00000000 |
8493 | #define smnBIFP0_PCIE_LINK_MANAGEMENT_CNTL2_DEFAULT 0x00000000 |
8494 | #define smnBIFP0_PCIE_LC_CNTL2_DEFAULT 0x96180280 |
8495 | #define smnBIFP0_PCIE_LC_BW_CHANGE_CNTL_DEFAULT 0x00000000 |
8496 | #define smnBIFP0_PCIE_LC_CDR_CNTL_DEFAULT 0x01018060 |
8497 | #define smnBIFP0_PCIE_LC_LANE_CNTL_DEFAULT 0x00000000 |
8498 | #define smnBIFP0_PCIE_LC_CNTL3_DEFAULT 0x2850a020 |
8499 | #define smnBIFP0_PCIE_LC_CNTL4_DEFAULT 0x0340048c |
8500 | #define smnBIFP0_PCIE_LC_CNTL5_DEFAULT 0x40410b2c |
8501 | #define smnBIFP0_PCIE_LC_FORCE_COEFF_DEFAULT 0x00080000 |
8502 | #define smnBIFP0_PCIE_LC_BEST_EQ_SETTINGS_DEFAULT 0x00000000 |
8503 | #define smnBIFP0_PCIE_LC_FORCE_EQ_REQ_COEFF_DEFAULT 0x00000000 |
8504 | #define smnBIFP0_PCIE_LC_CNTL6_DEFAULT 0x8a000010 |
8505 | #define smnBIFP0_PCIE_LC_CNTL7_DEFAULT 0x8000026e |
8506 | #define smnBIFP0_PCIE_LINK_MANAGEMENT_STATUS_DEFAULT 0x00000000 |
8507 | #define smnBIFP0_PCIE_LINK_MANAGEMENT_MASK_DEFAULT 0x00003fff |
8508 | #define smnBIFP0_PCIE_LINK_MANAGEMENT_CNTL_DEFAULT 0x00000000 |
8509 | #define smnBIFP0_PCIEP_STRAP_LC_DEFAULT 0x00000000 |
8510 | #define smnBIFP0_PCIEP_STRAP_MISC_DEFAULT 0x00000000 |
8511 | #define smnBIFP0_PCIE_LC_L1_PM_SUBSTATE_DEFAULT 0x00540000 |
8512 | #define smnBIFP0_PCIE_LC_L1_PM_SUBSTATE2_DEFAULT 0x00000000 |
8513 | #define smnBIFP0_PCIE_LC_PORT_ORDER_DEFAULT 0x00000000 |
8514 | #define smnBIFP0_PCIEP_BCH_ECC_CNTL_DEFAULT 0x00000100 |
8515 | #define smnBIFP0_PCIEP_HPGI_PRIVATE_DEFAULT 0x00000000 |
8516 | #define smnBIFP0_PCIEP_HPGI_DEFAULT 0x00000000 |
8517 | #define smnBIFP0_PCIEP_HCNT_DESCRIPTOR_DEFAULT 0x00000000 |
8518 | #define smnBIFP0_PCIEP_PERF_CNTL_COUNT_TXCLK_DEFAULT 0x00000000 |
8519 | |
8520 | |
8521 | // addressBlock: nbio_pcie0_bifp1_pciedir_p |
8522 | #define smnBIFP1_PCIEP_RESERVED_DEFAULT 0x00000000 |
8523 | #define smnBIFP1_PCIEP_SCRATCH_DEFAULT 0x00000000 |
8524 | #define smnBIFP1_PCIEP_PORT_CNTL_DEFAULT 0x00010009 |
8525 | #define smnBIFP1_PCIE_TX_CNTL_DEFAULT 0x00508000 |
8526 | #define smnBIFP1_PCIE_TX_REQUESTER_ID_DEFAULT 0x00000000 |
8527 | #define smnBIFP1_PCIE_TX_VENDOR_SPECIFIC_DEFAULT 0x00000000 |
8528 | #define smnBIFP1_PCIE_TX_REQUEST_NUM_CNTL_DEFAULT 0x02000000 |
8529 | #define smnBIFP1_PCIE_TX_SEQ_DEFAULT 0x00000000 |
8530 | #define smnBIFP1_PCIE_TX_REPLAY_DEFAULT 0x00900003 |
8531 | #define smnBIFP1_PCIE_TX_ACK_LATENCY_LIMIT_DEFAULT 0x00000000 |
8532 | #define smnBIFP1_PCIE_TX_CREDITS_ADVT_P_DEFAULT 0x00000000 |
8533 | #define smnBIFP1_PCIE_TX_CREDITS_ADVT_NP_DEFAULT 0x00000000 |
8534 | #define smnBIFP1_PCIE_TX_CREDITS_ADVT_CPL_DEFAULT 0x00000000 |
8535 | #define smnBIFP1_PCIE_TX_CREDITS_INIT_P_DEFAULT 0x00000000 |
8536 | #define smnBIFP1_PCIE_TX_CREDITS_INIT_NP_DEFAULT 0x00000000 |
8537 | #define smnBIFP1_PCIE_TX_CREDITS_INIT_CPL_DEFAULT 0x00000000 |
8538 | #define smnBIFP1_PCIE_TX_CREDITS_STATUS_DEFAULT 0x00000000 |
8539 | #define smnBIFP1_PCIE_TX_CREDITS_FCU_THRESHOLD_DEFAULT 0x03330333 |
8540 | #define smnBIFP1_PCIE_P_PORT_LANE_STATUS_DEFAULT 0x00000000 |
8541 | #define smnBIFP1_PCIE_FC_P_DEFAULT 0x00000208 |
8542 | #define smnBIFP1_PCIE_FC_NP_DEFAULT 0x00000202 |
8543 | #define smnBIFP1_PCIE_FC_CPL_DEFAULT 0x00000000 |
8544 | #define smnBIFP1_PCIE_ERR_CNTL_DEFAULT 0x00000500 |
8545 | #define smnBIFP1_PCIE_RX_CNTL_DEFAULT 0x01084000 |
8546 | #define smnBIFP1_PCIE_RX_EXPECTED_SEQNUM_DEFAULT 0x00000000 |
8547 | #define smnBIFP1_PCIE_RX_VENDOR_SPECIFIC_DEFAULT 0x00000000 |
8548 | #define smnBIFP1_PCIE_RX_CNTL3_DEFAULT 0x00000000 |
8549 | #define smnBIFP1_PCIE_RX_CREDITS_ALLOCATED_P_DEFAULT 0x00000000 |
8550 | #define smnBIFP1_PCIE_RX_CREDITS_ALLOCATED_NP_DEFAULT 0x00000000 |
8551 | #define smnBIFP1_PCIE_RX_CREDITS_ALLOCATED_CPL_DEFAULT 0x00000000 |
8552 | #define smnBIFP1_PCIEP_ERROR_INJECT_PHYSICAL_DEFAULT 0x00000000 |
8553 | #define smnBIFP1_PCIEP_ERROR_INJECT_TRANSACTION_DEFAULT 0x00000000 |
8554 | #define smnBIFP1_PCIEP_NAK_COUNTER_DEFAULT 0x00000000 |
8555 | #define smnBIFP1_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS_DEFAULT 0x00000000 |
8556 | #define smnBIFP1_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES_DEFAULT 0x00000000 |
8557 | #define smnBIFP1_PCIE_LC_CNTL_DEFAULT 0x40010030 |
8558 | #define smnBIFP1_PCIE_LC_TRAINING_CNTL_DEFAULT 0x94009880 |
8559 | #define smnBIFP1_PCIE_LC_LINK_WIDTH_CNTL_DEFAULT 0xda800006 |
8560 | #define smnBIFP1_PCIE_LC_N_FTS_CNTL_DEFAULT 0x00ff820c |
8561 | #define smnBIFP1_PCIE_LC_SPEED_CNTL_DEFAULT 0x04400100 |
8562 | #define smnBIFP1_PCIE_LC_STATE0_DEFAULT 0x00000000 |
8563 | #define smnBIFP1_PCIE_LC_STATE1_DEFAULT 0x00000000 |
8564 | #define smnBIFP1_PCIE_LC_STATE2_DEFAULT 0x00000000 |
8565 | #define smnBIFP1_PCIE_LC_STATE3_DEFAULT 0x00000000 |
8566 | #define smnBIFP1_PCIE_LC_STATE4_DEFAULT 0x00000000 |
8567 | #define smnBIFP1_PCIE_LC_STATE5_DEFAULT 0x00000000 |
8568 | #define smnBIFP1_PCIE_LINK_MANAGEMENT_CNTL2_DEFAULT 0x00000000 |
8569 | #define smnBIFP1_PCIE_LC_CNTL2_DEFAULT 0x96180280 |
8570 | #define smnBIFP1_PCIE_LC_BW_CHANGE_CNTL_DEFAULT 0x00000000 |
8571 | #define smnBIFP1_PCIE_LC_CDR_CNTL_DEFAULT 0x01018060 |
8572 | #define smnBIFP1_PCIE_LC_LANE_CNTL_DEFAULT 0x00000000 |
8573 | #define smnBIFP1_PCIE_LC_CNTL3_DEFAULT 0x2850a020 |
8574 | #define smnBIFP1_PCIE_LC_CNTL4_DEFAULT 0x0340048c |
8575 | #define smnBIFP1_PCIE_LC_CNTL5_DEFAULT 0x40410b2c |
8576 | #define smnBIFP1_PCIE_LC_FORCE_COEFF_DEFAULT 0x00080000 |
8577 | #define smnBIFP1_PCIE_LC_BEST_EQ_SETTINGS_DEFAULT 0x00000000 |
8578 | #define smnBIFP1_PCIE_LC_FORCE_EQ_REQ_COEFF_DEFAULT 0x00000000 |
8579 | #define smnBIFP1_PCIE_LC_CNTL6_DEFAULT 0x8a000010 |
8580 | #define smnBIFP1_PCIE_LC_CNTL7_DEFAULT 0x8000026e |
8581 | #define smnBIFP1_PCIE_LINK_MANAGEMENT_STATUS_DEFAULT 0x00000000 |
8582 | #define smnBIFP1_PCIE_LINK_MANAGEMENT_MASK_DEFAULT 0x00003fff |
8583 | #define smnBIFP1_PCIE_LINK_MANAGEMENT_CNTL_DEFAULT 0x00000000 |
8584 | #define smnBIFP1_PCIEP_STRAP_LC_DEFAULT 0x00000000 |
8585 | #define smnBIFP1_PCIEP_STRAP_MISC_DEFAULT 0x00000000 |
8586 | #define smnBIFP1_PCIE_LC_L1_PM_SUBSTATE_DEFAULT 0x00540000 |
8587 | #define smnBIFP1_PCIE_LC_L1_PM_SUBSTATE2_DEFAULT 0x00000000 |
8588 | #define smnBIFP1_PCIE_LC_PORT_ORDER_DEFAULT 0x00000000 |
8589 | #define smnBIFP1_PCIEP_BCH_ECC_CNTL_DEFAULT 0x00000100 |
8590 | #define smnBIFP1_PCIEP_HPGI_PRIVATE_DEFAULT 0x00000000 |
8591 | #define smnBIFP1_PCIEP_HPGI_DEFAULT 0x00000000 |
8592 | #define smnBIFP1_PCIEP_HCNT_DESCRIPTOR_DEFAULT 0x00000000 |
8593 | #define smnBIFP1_PCIEP_PERF_CNTL_COUNT_TXCLK_DEFAULT 0x00000000 |
8594 | |
8595 | |
8596 | // addressBlock: nbio_pcie0_bifp2_pciedir_p |
8597 | #define smnBIFP2_PCIEP_RESERVED_DEFAULT 0x00000000 |
8598 | #define smnBIFP2_PCIEP_SCRATCH_DEFAULT 0x00000000 |
8599 | #define smnBIFP2_PCIEP_PORT_CNTL_DEFAULT 0x00010009 |
8600 | #define smnBIFP2_PCIE_TX_CNTL_DEFAULT 0x00508000 |
8601 | #define smnBIFP2_PCIE_TX_REQUESTER_ID_DEFAULT 0x00000000 |
8602 | #define smnBIFP2_PCIE_TX_VENDOR_SPECIFIC_DEFAULT 0x00000000 |
8603 | #define smnBIFP2_PCIE_TX_REQUEST_NUM_CNTL_DEFAULT 0x02000000 |
8604 | #define smnBIFP2_PCIE_TX_SEQ_DEFAULT 0x00000000 |
8605 | #define smnBIFP2_PCIE_TX_REPLAY_DEFAULT 0x00900003 |
8606 | #define smnBIFP2_PCIE_TX_ACK_LATENCY_LIMIT_DEFAULT 0x00000000 |
8607 | #define smnBIFP2_PCIE_TX_CREDITS_ADVT_P_DEFAULT 0x00000000 |
8608 | #define smnBIFP2_PCIE_TX_CREDITS_ADVT_NP_DEFAULT 0x00000000 |
8609 | #define smnBIFP2_PCIE_TX_CREDITS_ADVT_CPL_DEFAULT 0x00000000 |
8610 | #define smnBIFP2_PCIE_TX_CREDITS_INIT_P_DEFAULT 0x00000000 |
8611 | #define smnBIFP2_PCIE_TX_CREDITS_INIT_NP_DEFAULT 0x00000000 |
8612 | #define smnBIFP2_PCIE_TX_CREDITS_INIT_CPL_DEFAULT 0x00000000 |
8613 | #define smnBIFP2_PCIE_TX_CREDITS_STATUS_DEFAULT 0x00000000 |
8614 | #define smnBIFP2_PCIE_TX_CREDITS_FCU_THRESHOLD_DEFAULT 0x03330333 |
8615 | #define smnBIFP2_PCIE_P_PORT_LANE_STATUS_DEFAULT 0x00000000 |
8616 | #define smnBIFP2_PCIE_FC_P_DEFAULT 0x00000208 |
8617 | #define smnBIFP2_PCIE_FC_NP_DEFAULT 0x00000202 |
8618 | #define smnBIFP2_PCIE_FC_CPL_DEFAULT 0x00000000 |
8619 | #define smnBIFP2_PCIE_ERR_CNTL_DEFAULT 0x00000500 |
8620 | #define smnBIFP2_PCIE_RX_CNTL_DEFAULT 0x01084000 |
8621 | #define smnBIFP2_PCIE_RX_EXPECTED_SEQNUM_DEFAULT 0x00000000 |
8622 | #define smnBIFP2_PCIE_RX_VENDOR_SPECIFIC_DEFAULT 0x00000000 |
8623 | #define smnBIFP2_PCIE_RX_CNTL3_DEFAULT 0x00000000 |
8624 | #define smnBIFP2_PCIE_RX_CREDITS_ALLOCATED_P_DEFAULT 0x00000000 |
8625 | #define smnBIFP2_PCIE_RX_CREDITS_ALLOCATED_NP_DEFAULT 0x00000000 |
8626 | #define smnBIFP2_PCIE_RX_CREDITS_ALLOCATED_CPL_DEFAULT 0x00000000 |
8627 | #define smnBIFP2_PCIEP_ERROR_INJECT_PHYSICAL_DEFAULT 0x00000000 |
8628 | #define smnBIFP2_PCIEP_ERROR_INJECT_TRANSACTION_DEFAULT 0x00000000 |
8629 | #define smnBIFP2_PCIEP_NAK_COUNTER_DEFAULT 0x00000000 |
8630 | #define smnBIFP2_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS_DEFAULT 0x00000000 |
8631 | #define smnBIFP2_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES_DEFAULT 0x00000000 |
8632 | #define smnBIFP2_PCIE_LC_CNTL_DEFAULT 0x40010030 |
8633 | #define smnBIFP2_PCIE_LC_TRAINING_CNTL_DEFAULT 0x94009880 |
8634 | #define smnBIFP2_PCIE_LC_LINK_WIDTH_CNTL_DEFAULT 0xda800006 |
8635 | #define smnBIFP2_PCIE_LC_N_FTS_CNTL_DEFAULT 0x00ff820c |
8636 | #define smnBIFP2_PCIE_LC_SPEED_CNTL_DEFAULT 0x04400100 |
8637 | #define smnBIFP2_PCIE_LC_STATE0_DEFAULT 0x00000000 |
8638 | #define smnBIFP2_PCIE_LC_STATE1_DEFAULT 0x00000000 |
8639 | #define smnBIFP2_PCIE_LC_STATE2_DEFAULT 0x00000000 |
8640 | #define smnBIFP2_PCIE_LC_STATE3_DEFAULT 0x00000000 |
8641 | #define smnBIFP2_PCIE_LC_STATE4_DEFAULT 0x00000000 |
8642 | #define smnBIFP2_PCIE_LC_STATE5_DEFAULT 0x00000000 |
8643 | #define smnBIFP2_PCIE_LINK_MANAGEMENT_CNTL2_DEFAULT 0x00000000 |
8644 | #define smnBIFP2_PCIE_LC_CNTL2_DEFAULT 0x96180280 |
8645 | #define smnBIFP2_PCIE_LC_BW_CHANGE_CNTL_DEFAULT 0x00000000 |
8646 | #define smnBIFP2_PCIE_LC_CDR_CNTL_DEFAULT 0x01018060 |
8647 | #define smnBIFP2_PCIE_LC_LANE_CNTL_DEFAULT 0x00000000 |
8648 | #define smnBIFP2_PCIE_LC_CNTL3_DEFAULT 0x2850a020 |
8649 | #define smnBIFP2_PCIE_LC_CNTL4_DEFAULT 0x0340048c |
8650 | #define smnBIFP2_PCIE_LC_CNTL5_DEFAULT 0x40410b2c |
8651 | #define smnBIFP2_PCIE_LC_FORCE_COEFF_DEFAULT 0x00080000 |
8652 | #define smnBIFP2_PCIE_LC_BEST_EQ_SETTINGS_DEFAULT 0x00000000 |
8653 | #define smnBIFP2_PCIE_LC_FORCE_EQ_REQ_COEFF_DEFAULT 0x00000000 |
8654 | #define smnBIFP2_PCIE_LC_CNTL6_DEFAULT 0x8a000010 |
8655 | #define smnBIFP2_PCIE_LC_CNTL7_DEFAULT 0x8000026e |
8656 | #define smnBIFP2_PCIE_LINK_MANAGEMENT_STATUS_DEFAULT 0x00000000 |
8657 | #define smnBIFP2_PCIE_LINK_MANAGEMENT_MASK_DEFAULT 0x00003fff |
8658 | #define smnBIFP2_PCIE_LINK_MANAGEMENT_CNTL_DEFAULT 0x00000000 |
8659 | #define smnBIFP2_PCIEP_STRAP_LC_DEFAULT 0x00000000 |
8660 | #define smnBIFP2_PCIEP_STRAP_MISC_DEFAULT 0x00000000 |
8661 | #define smnBIFP2_PCIE_LC_L1_PM_SUBSTATE_DEFAULT 0x00540000 |
8662 | #define smnBIFP2_PCIE_LC_L1_PM_SUBSTATE2_DEFAULT 0x00000000 |
8663 | #define smnBIFP2_PCIE_LC_PORT_ORDER_DEFAULT 0x00000000 |
8664 | #define smnBIFP2_PCIEP_BCH_ECC_CNTL_DEFAULT 0x00000100 |
8665 | #define smnBIFP2_PCIEP_HPGI_PRIVATE_DEFAULT 0x00000000 |
8666 | #define smnBIFP2_PCIEP_HPGI_DEFAULT 0x00000000 |
8667 | #define smnBIFP2_PCIEP_HCNT_DESCRIPTOR_DEFAULT 0x00000000 |
8668 | #define smnBIFP2_PCIEP_PERF_CNTL_COUNT_TXCLK_DEFAULT 0x00000000 |
8669 | |
8670 | |
8671 | // addressBlock: nbio_pcie0_bifp3_pciedir_p |
8672 | #define smnBIFP3_PCIEP_RESERVED_DEFAULT 0x00000000 |
8673 | #define smnBIFP3_PCIEP_SCRATCH_DEFAULT 0x00000000 |
8674 | #define smnBIFP3_PCIEP_PORT_CNTL_DEFAULT 0x00010009 |
8675 | #define smnBIFP3_PCIE_TX_CNTL_DEFAULT 0x00508000 |
8676 | #define smnBIFP3_PCIE_TX_REQUESTER_ID_DEFAULT 0x00000000 |
8677 | #define smnBIFP3_PCIE_TX_VENDOR_SPECIFIC_DEFAULT 0x00000000 |
8678 | #define smnBIFP3_PCIE_TX_REQUEST_NUM_CNTL_DEFAULT 0x02000000 |
8679 | #define smnBIFP3_PCIE_TX_SEQ_DEFAULT 0x00000000 |
8680 | #define smnBIFP3_PCIE_TX_REPLAY_DEFAULT 0x00900003 |
8681 | #define smnBIFP3_PCIE_TX_ACK_LATENCY_LIMIT_DEFAULT 0x00000000 |
8682 | #define smnBIFP3_PCIE_TX_CREDITS_ADVT_P_DEFAULT 0x00000000 |
8683 | #define smnBIFP3_PCIE_TX_CREDITS_ADVT_NP_DEFAULT 0x00000000 |
8684 | #define smnBIFP3_PCIE_TX_CREDITS_ADVT_CPL_DEFAULT 0x00000000 |
8685 | #define smnBIFP3_PCIE_TX_CREDITS_INIT_P_DEFAULT 0x00000000 |
8686 | #define smnBIFP3_PCIE_TX_CREDITS_INIT_NP_DEFAULT 0x00000000 |
8687 | #define smnBIFP3_PCIE_TX_CREDITS_INIT_CPL_DEFAULT 0x00000000 |
8688 | #define smnBIFP3_PCIE_TX_CREDITS_STATUS_DEFAULT 0x00000000 |
8689 | #define smnBIFP3_PCIE_TX_CREDITS_FCU_THRESHOLD_DEFAULT 0x03330333 |
8690 | #define smnBIFP3_PCIE_P_PORT_LANE_STATUS_DEFAULT 0x00000000 |
8691 | #define smnBIFP3_PCIE_FC_P_DEFAULT 0x00000208 |
8692 | #define smnBIFP3_PCIE_FC_NP_DEFAULT 0x00000202 |
8693 | #define smnBIFP3_PCIE_FC_CPL_DEFAULT 0x00000000 |
8694 | #define smnBIFP3_PCIE_ERR_CNTL_DEFAULT 0x00000500 |
8695 | #define smnBIFP3_PCIE_RX_CNTL_DEFAULT 0x01084000 |
8696 | #define smnBIFP3_PCIE_RX_EXPECTED_SEQNUM_DEFAULT 0x00000000 |
8697 | #define smnBIFP3_PCIE_RX_VENDOR_SPECIFIC_DEFAULT 0x00000000 |
8698 | #define smnBIFP3_PCIE_RX_CNTL3_DEFAULT 0x00000000 |
8699 | #define smnBIFP3_PCIE_RX_CREDITS_ALLOCATED_P_DEFAULT 0x00000000 |
8700 | #define smnBIFP3_PCIE_RX_CREDITS_ALLOCATED_NP_DEFAULT 0x00000000 |
8701 | #define smnBIFP3_PCIE_RX_CREDITS_ALLOCATED_CPL_DEFAULT 0x00000000 |
8702 | #define smnBIFP3_PCIEP_ERROR_INJECT_PHYSICAL_DEFAULT 0x00000000 |
8703 | #define smnBIFP3_PCIEP_ERROR_INJECT_TRANSACTION_DEFAULT 0x00000000 |
8704 | #define smnBIFP3_PCIEP_NAK_COUNTER_DEFAULT 0x00000000 |
8705 | #define smnBIFP3_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS_DEFAULT 0x00000000 |
8706 | #define smnBIFP3_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES_DEFAULT 0x00000000 |
8707 | #define smnBIFP3_PCIE_LC_CNTL_DEFAULT 0x40010030 |
8708 | #define smnBIFP3_PCIE_LC_TRAINING_CNTL_DEFAULT 0x94009880 |
8709 | #define smnBIFP3_PCIE_LC_LINK_WIDTH_CNTL_DEFAULT 0xda800006 |
8710 | #define smnBIFP3_PCIE_LC_N_FTS_CNTL_DEFAULT 0x00ff820c |
8711 | #define smnBIFP3_PCIE_LC_SPEED_CNTL_DEFAULT 0x04400100 |
8712 | #define smnBIFP3_PCIE_LC_STATE0_DEFAULT 0x00000000 |
8713 | #define smnBIFP3_PCIE_LC_STATE1_DEFAULT 0x00000000 |
8714 | #define smnBIFP3_PCIE_LC_STATE2_DEFAULT 0x00000000 |
8715 | #define smnBIFP3_PCIE_LC_STATE3_DEFAULT 0x00000000 |
8716 | #define smnBIFP3_PCIE_LC_STATE4_DEFAULT 0x00000000 |
8717 | #define smnBIFP3_PCIE_LC_STATE5_DEFAULT 0x00000000 |
8718 | #define smnBIFP3_PCIE_LINK_MANAGEMENT_CNTL2_DEFAULT 0x00000000 |
8719 | #define smnBIFP3_PCIE_LC_CNTL2_DEFAULT 0x96180280 |
8720 | #define smnBIFP3_PCIE_LC_BW_CHANGE_CNTL_DEFAULT 0x00000000 |
8721 | #define smnBIFP3_PCIE_LC_CDR_CNTL_DEFAULT 0x01018060 |
8722 | #define smnBIFP3_PCIE_LC_LANE_CNTL_DEFAULT 0x00000000 |
8723 | #define smnBIFP3_PCIE_LC_CNTL3_DEFAULT 0x2850a020 |
8724 | #define smnBIFP3_PCIE_LC_CNTL4_DEFAULT 0x0340048c |
8725 | #define smnBIFP3_PCIE_LC_CNTL5_DEFAULT 0x40410b2c |
8726 | #define smnBIFP3_PCIE_LC_FORCE_COEFF_DEFAULT 0x00080000 |
8727 | #define smnBIFP3_PCIE_LC_BEST_EQ_SETTINGS_DEFAULT 0x00000000 |
8728 | #define smnBIFP3_PCIE_LC_FORCE_EQ_REQ_COEFF_DEFAULT 0x00000000 |
8729 | #define smnBIFP3_PCIE_LC_CNTL6_DEFAULT 0x8a000010 |
8730 | #define smnBIFP3_PCIE_LC_CNTL7_DEFAULT 0x8000026e |
8731 | #define smnBIFP3_PCIE_LINK_MANAGEMENT_STATUS_DEFAULT 0x00000000 |
8732 | #define smnBIFP3_PCIE_LINK_MANAGEMENT_MASK_DEFAULT 0x00003fff |
8733 | #define smnBIFP3_PCIE_LINK_MANAGEMENT_CNTL_DEFAULT 0x00000000 |
8734 | #define smnBIFP3_PCIEP_STRAP_LC_DEFAULT 0x00000000 |
8735 | #define smnBIFP3_PCIEP_STRAP_MISC_DEFAULT 0x00000000 |
8736 | #define smnBIFP3_PCIE_LC_L1_PM_SUBSTATE_DEFAULT 0x00540000 |
8737 | #define smnBIFP3_PCIE_LC_L1_PM_SUBSTATE2_DEFAULT 0x00000000 |
8738 | #define smnBIFP3_PCIE_LC_PORT_ORDER_DEFAULT 0x00000000 |
8739 | #define smnBIFP3_PCIEP_BCH_ECC_CNTL_DEFAULT 0x00000100 |
8740 | #define smnBIFP3_PCIEP_HPGI_PRIVATE_DEFAULT 0x00000000 |
8741 | #define smnBIFP3_PCIEP_HPGI_DEFAULT 0x00000000 |
8742 | #define smnBIFP3_PCIEP_HCNT_DESCRIPTOR_DEFAULT 0x00000000 |
8743 | #define smnBIFP3_PCIEP_PERF_CNTL_COUNT_TXCLK_DEFAULT 0x00000000 |
8744 | |
8745 | |
8746 | // addressBlock: nbio_pcie0_bifp4_pciedir_p |
8747 | #define smnBIFP4_PCIEP_RESERVED_DEFAULT 0x00000000 |
8748 | #define smnBIFP4_PCIEP_SCRATCH_DEFAULT 0x00000000 |
8749 | #define smnBIFP4_PCIEP_PORT_CNTL_DEFAULT 0x00010009 |
8750 | #define smnBIFP4_PCIE_TX_CNTL_DEFAULT 0x00508000 |
8751 | #define smnBIFP4_PCIE_TX_REQUESTER_ID_DEFAULT 0x00000000 |
8752 | #define smnBIFP4_PCIE_TX_VENDOR_SPECIFIC_DEFAULT 0x00000000 |
8753 | #define smnBIFP4_PCIE_TX_REQUEST_NUM_CNTL_DEFAULT 0x02000000 |
8754 | #define smnBIFP4_PCIE_TX_SEQ_DEFAULT 0x00000000 |
8755 | #define smnBIFP4_PCIE_TX_REPLAY_DEFAULT 0x00900003 |
8756 | #define smnBIFP4_PCIE_TX_ACK_LATENCY_LIMIT_DEFAULT 0x00000000 |
8757 | #define smnBIFP4_PCIE_TX_CREDITS_ADVT_P_DEFAULT 0x00000000 |
8758 | #define smnBIFP4_PCIE_TX_CREDITS_ADVT_NP_DEFAULT 0x00000000 |
8759 | #define smnBIFP4_PCIE_TX_CREDITS_ADVT_CPL_DEFAULT 0x00000000 |
8760 | #define smnBIFP4_PCIE_TX_CREDITS_INIT_P_DEFAULT 0x00000000 |
8761 | #define smnBIFP4_PCIE_TX_CREDITS_INIT_NP_DEFAULT 0x00000000 |
8762 | #define smnBIFP4_PCIE_TX_CREDITS_INIT_CPL_DEFAULT 0x00000000 |
8763 | #define smnBIFP4_PCIE_TX_CREDITS_STATUS_DEFAULT 0x00000000 |
8764 | #define smnBIFP4_PCIE_TX_CREDITS_FCU_THRESHOLD_DEFAULT 0x03330333 |
8765 | #define smnBIFP4_PCIE_P_PORT_LANE_STATUS_DEFAULT 0x00000000 |
8766 | #define smnBIFP4_PCIE_FC_P_DEFAULT 0x00000208 |
8767 | #define smnBIFP4_PCIE_FC_NP_DEFAULT 0x00000202 |
8768 | #define smnBIFP4_PCIE_FC_CPL_DEFAULT 0x00000000 |
8769 | #define smnBIFP4_PCIE_ERR_CNTL_DEFAULT 0x00000500 |
8770 | #define smnBIFP4_PCIE_RX_CNTL_DEFAULT 0x01084000 |
8771 | #define smnBIFP4_PCIE_RX_EXPECTED_SEQNUM_DEFAULT 0x00000000 |
8772 | #define smnBIFP4_PCIE_RX_VENDOR_SPECIFIC_DEFAULT 0x00000000 |
8773 | #define smnBIFP4_PCIE_RX_CNTL3_DEFAULT 0x00000000 |
8774 | #define smnBIFP4_PCIE_RX_CREDITS_ALLOCATED_P_DEFAULT 0x00000000 |
8775 | #define smnBIFP4_PCIE_RX_CREDITS_ALLOCATED_NP_DEFAULT 0x00000000 |
8776 | #define smnBIFP4_PCIE_RX_CREDITS_ALLOCATED_CPL_DEFAULT 0x00000000 |
8777 | #define smnBIFP4_PCIEP_ERROR_INJECT_PHYSICAL_DEFAULT 0x00000000 |
8778 | #define smnBIFP4_PCIEP_ERROR_INJECT_TRANSACTION_DEFAULT 0x00000000 |
8779 | #define smnBIFP4_PCIEP_NAK_COUNTER_DEFAULT 0x00000000 |
8780 | #define smnBIFP4_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS_DEFAULT 0x00000000 |
8781 | #define smnBIFP4_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES_DEFAULT 0x00000000 |
8782 | #define smnBIFP4_PCIE_LC_CNTL_DEFAULT 0x40010030 |
8783 | #define smnBIFP4_PCIE_LC_TRAINING_CNTL_DEFAULT 0x94009880 |
8784 | #define smnBIFP4_PCIE_LC_LINK_WIDTH_CNTL_DEFAULT 0xda800006 |
8785 | #define smnBIFP4_PCIE_LC_N_FTS_CNTL_DEFAULT 0x00ff820c |
8786 | #define smnBIFP4_PCIE_LC_SPEED_CNTL_DEFAULT 0x04400100 |
8787 | #define smnBIFP4_PCIE_LC_STATE0_DEFAULT 0x00000000 |
8788 | #define smnBIFP4_PCIE_LC_STATE1_DEFAULT 0x00000000 |
8789 | #define smnBIFP4_PCIE_LC_STATE2_DEFAULT 0x00000000 |
8790 | #define smnBIFP4_PCIE_LC_STATE3_DEFAULT 0x00000000 |
8791 | #define smnBIFP4_PCIE_LC_STATE4_DEFAULT 0x00000000 |
8792 | #define smnBIFP4_PCIE_LC_STATE5_DEFAULT 0x00000000 |
8793 | #define smnBIFP4_PCIE_LINK_MANAGEMENT_CNTL2_DEFAULT 0x00000000 |
8794 | #define smnBIFP4_PCIE_LC_CNTL2_DEFAULT 0x96180280 |
8795 | #define smnBIFP4_PCIE_LC_BW_CHANGE_CNTL_DEFAULT 0x00000000 |
8796 | #define smnBIFP4_PCIE_LC_CDR_CNTL_DEFAULT 0x01018060 |
8797 | #define smnBIFP4_PCIE_LC_LANE_CNTL_DEFAULT 0x00000000 |
8798 | #define smnBIFP4_PCIE_LC_CNTL3_DEFAULT 0x2850a020 |
8799 | #define smnBIFP4_PCIE_LC_CNTL4_DEFAULT 0x0340048c |
8800 | #define smnBIFP4_PCIE_LC_CNTL5_DEFAULT 0x40410b2c |
8801 | #define smnBIFP4_PCIE_LC_FORCE_COEFF_DEFAULT 0x00080000 |
8802 | #define smnBIFP4_PCIE_LC_BEST_EQ_SETTINGS_DEFAULT 0x00000000 |
8803 | #define smnBIFP4_PCIE_LC_FORCE_EQ_REQ_COEFF_DEFAULT 0x00000000 |
8804 | #define smnBIFP4_PCIE_LC_CNTL6_DEFAULT 0x8a000010 |
8805 | #define smnBIFP4_PCIE_LC_CNTL7_DEFAULT 0x8000026e |
8806 | #define smnBIFP4_PCIE_LINK_MANAGEMENT_STATUS_DEFAULT 0x00000000 |
8807 | #define smnBIFP4_PCIE_LINK_MANAGEMENT_MASK_DEFAULT 0x00003fff |
8808 | #define smnBIFP4_PCIE_LINK_MANAGEMENT_CNTL_DEFAULT 0x00000000 |
8809 | #define smnBIFP4_PCIEP_STRAP_LC_DEFAULT 0x00000000 |
8810 | #define smnBIFP4_PCIEP_STRAP_MISC_DEFAULT 0x00000000 |
8811 | #define smnBIFP4_PCIE_LC_L1_PM_SUBSTATE_DEFAULT 0x00540000 |
8812 | #define smnBIFP4_PCIE_LC_L1_PM_SUBSTATE2_DEFAULT 0x00000000 |
8813 | #define smnBIFP4_PCIE_LC_PORT_ORDER_DEFAULT 0x00000000 |
8814 | #define smnBIFP4_PCIEP_BCH_ECC_CNTL_DEFAULT 0x00000100 |
8815 | #define smnBIFP4_PCIEP_HPGI_PRIVATE_DEFAULT 0x00000000 |
8816 | #define smnBIFP4_PCIEP_HPGI_DEFAULT 0x00000000 |
8817 | #define smnBIFP4_PCIEP_HCNT_DESCRIPTOR_DEFAULT 0x00000000 |
8818 | #define smnBIFP4_PCIEP_PERF_CNTL_COUNT_TXCLK_DEFAULT 0x00000000 |
8819 | |
8820 | |
8821 | // addressBlock: nbio_pcie0_bifp5_pciedir_p |
8822 | #define smnBIFP5_PCIEP_RESERVED_DEFAULT 0x00000000 |
8823 | #define smnBIFP5_PCIEP_SCRATCH_DEFAULT 0x00000000 |
8824 | #define smnBIFP5_PCIEP_PORT_CNTL_DEFAULT 0x00010009 |
8825 | #define smnBIFP5_PCIE_TX_CNTL_DEFAULT 0x00508000 |
8826 | #define smnBIFP5_PCIE_TX_REQUESTER_ID_DEFAULT 0x00000000 |
8827 | #define smnBIFP5_PCIE_TX_VENDOR_SPECIFIC_DEFAULT 0x00000000 |
8828 | #define smnBIFP5_PCIE_TX_REQUEST_NUM_CNTL_DEFAULT 0x02000000 |
8829 | #define smnBIFP5_PCIE_TX_SEQ_DEFAULT 0x00000000 |
8830 | #define smnBIFP5_PCIE_TX_REPLAY_DEFAULT 0x00900003 |
8831 | #define smnBIFP5_PCIE_TX_ACK_LATENCY_LIMIT_DEFAULT 0x00000000 |
8832 | #define smnBIFP5_PCIE_TX_CREDITS_ADVT_P_DEFAULT 0x00000000 |
8833 | #define smnBIFP5_PCIE_TX_CREDITS_ADVT_NP_DEFAULT 0x00000000 |
8834 | #define smnBIFP5_PCIE_TX_CREDITS_ADVT_CPL_DEFAULT 0x00000000 |
8835 | #define smnBIFP5_PCIE_TX_CREDITS_INIT_P_DEFAULT 0x00000000 |
8836 | #define smnBIFP5_PCIE_TX_CREDITS_INIT_NP_DEFAULT 0x00000000 |
8837 | #define smnBIFP5_PCIE_TX_CREDITS_INIT_CPL_DEFAULT 0x00000000 |
8838 | #define smnBIFP5_PCIE_TX_CREDITS_STATUS_DEFAULT 0x00000000 |
8839 | #define smnBIFP5_PCIE_TX_CREDITS_FCU_THRESHOLD_DEFAULT 0x03330333 |
8840 | #define smnBIFP5_PCIE_P_PORT_LANE_STATUS_DEFAULT 0x00000000 |
8841 | #define smnBIFP5_PCIE_FC_P_DEFAULT 0x00000208 |
8842 | #define smnBIFP5_PCIE_FC_NP_DEFAULT 0x00000202 |
8843 | #define smnBIFP5_PCIE_FC_CPL_DEFAULT 0x00000000 |
8844 | #define smnBIFP5_PCIE_ERR_CNTL_DEFAULT 0x00000500 |
8845 | #define smnBIFP5_PCIE_RX_CNTL_DEFAULT 0x01084000 |
8846 | #define smnBIFP5_PCIE_RX_EXPECTED_SEQNUM_DEFAULT 0x00000000 |
8847 | #define smnBIFP5_PCIE_RX_VENDOR_SPECIFIC_DEFAULT 0x00000000 |
8848 | #define smnBIFP5_PCIE_RX_CNTL3_DEFAULT 0x00000000 |
8849 | #define smnBIFP5_PCIE_RX_CREDITS_ALLOCATED_P_DEFAULT 0x00000000 |
8850 | #define smnBIFP5_PCIE_RX_CREDITS_ALLOCATED_NP_DEFAULT 0x00000000 |
8851 | #define smnBIFP5_PCIE_RX_CREDITS_ALLOCATED_CPL_DEFAULT 0x00000000 |
8852 | #define smnBIFP5_PCIEP_ERROR_INJECT_PHYSICAL_DEFAULT 0x00000000 |
8853 | #define smnBIFP5_PCIEP_ERROR_INJECT_TRANSACTION_DEFAULT 0x00000000 |
8854 | #define smnBIFP5_PCIEP_NAK_COUNTER_DEFAULT 0x00000000 |
8855 | #define smnBIFP5_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS_DEFAULT 0x00000000 |
8856 | #define smnBIFP5_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES_DEFAULT 0x00000000 |
8857 | #define smnBIFP5_PCIE_LC_CNTL_DEFAULT 0x40010030 |
8858 | #define smnBIFP5_PCIE_LC_TRAINING_CNTL_DEFAULT 0x94009880 |
8859 | #define smnBIFP5_PCIE_LC_LINK_WIDTH_CNTL_DEFAULT 0xda800006 |
8860 | #define smnBIFP5_PCIE_LC_N_FTS_CNTL_DEFAULT 0x00ff820c |
8861 | #define smnBIFP5_PCIE_LC_SPEED_CNTL_DEFAULT 0x04400100 |
8862 | #define smnBIFP5_PCIE_LC_STATE0_DEFAULT 0x00000000 |
8863 | #define smnBIFP5_PCIE_LC_STATE1_DEFAULT 0x00000000 |
8864 | #define smnBIFP5_PCIE_LC_STATE2_DEFAULT 0x00000000 |
8865 | #define smnBIFP5_PCIE_LC_STATE3_DEFAULT 0x00000000 |
8866 | #define smnBIFP5_PCIE_LC_STATE4_DEFAULT 0x00000000 |
8867 | #define smnBIFP5_PCIE_LC_STATE5_DEFAULT 0x00000000 |
8868 | #define smnBIFP5_PCIE_LINK_MANAGEMENT_CNTL2_DEFAULT 0x00000000 |
8869 | #define smnBIFP5_PCIE_LC_CNTL2_DEFAULT 0x96180280 |
8870 | #define smnBIFP5_PCIE_LC_BW_CHANGE_CNTL_DEFAULT 0x00000000 |
8871 | #define smnBIFP5_PCIE_LC_CDR_CNTL_DEFAULT 0x01018060 |
8872 | #define smnBIFP5_PCIE_LC_LANE_CNTL_DEFAULT 0x00000000 |
8873 | #define smnBIFP5_PCIE_LC_CNTL3_DEFAULT 0x2850a020 |
8874 | #define smnBIFP5_PCIE_LC_CNTL4_DEFAULT 0x0340048c |
8875 | #define smnBIFP5_PCIE_LC_CNTL5_DEFAULT 0x40410b2c |
8876 | #define smnBIFP5_PCIE_LC_FORCE_COEFF_DEFAULT 0x00080000 |
8877 | #define smnBIFP5_PCIE_LC_BEST_EQ_SETTINGS_DEFAULT 0x00000000 |
8878 | #define smnBIFP5_PCIE_LC_FORCE_EQ_REQ_COEFF_DEFAULT 0x00000000 |
8879 | #define smnBIFP5_PCIE_LC_CNTL6_DEFAULT 0x8a000010 |
8880 | #define smnBIFP5_PCIE_LC_CNTL7_DEFAULT 0x8000026e |
8881 | #define smnBIFP5_PCIE_LINK_MANAGEMENT_STATUS_DEFAULT 0x00000000 |
8882 | #define smnBIFP5_PCIE_LINK_MANAGEMENT_MASK_DEFAULT 0x00003fff |
8883 | #define smnBIFP5_PCIE_LINK_MANAGEMENT_CNTL_DEFAULT 0x00000000 |
8884 | #define smnBIFP5_PCIEP_STRAP_LC_DEFAULT 0x00000000 |
8885 | #define smnBIFP5_PCIEP_STRAP_MISC_DEFAULT 0x00000000 |
8886 | #define smnBIFP5_PCIE_LC_L1_PM_SUBSTATE_DEFAULT 0x00540000 |
8887 | #define smnBIFP5_PCIE_LC_L1_PM_SUBSTATE2_DEFAULT 0x00000000 |
8888 | #define smnBIFP5_PCIE_LC_PORT_ORDER_DEFAULT 0x00000000 |
8889 | #define smnBIFP5_PCIEP_BCH_ECC_CNTL_DEFAULT 0x00000100 |
8890 | #define smnBIFP5_PCIEP_HPGI_PRIVATE_DEFAULT 0x00000000 |
8891 | #define smnBIFP5_PCIEP_HPGI_DEFAULT 0x00000000 |
8892 | #define smnBIFP5_PCIEP_HCNT_DESCRIPTOR_DEFAULT 0x00000000 |
8893 | #define smnBIFP5_PCIEP_PERF_CNTL_COUNT_TXCLK_DEFAULT 0x00000000 |
8894 | |
8895 | |
8896 | // addressBlock: nbio_pcie0_bifp6_pciedir_p |
8897 | #define smnBIFP6_PCIEP_RESERVED_DEFAULT 0x00000000 |
8898 | #define smnBIFP6_PCIEP_SCRATCH_DEFAULT 0x00000000 |
8899 | #define smnBIFP6_PCIEP_PORT_CNTL_DEFAULT 0x00010009 |
8900 | #define smnBIFP6_PCIE_TX_CNTL_DEFAULT 0x00508000 |
8901 | #define smnBIFP6_PCIE_TX_REQUESTER_ID_DEFAULT 0x00000000 |
8902 | #define smnBIFP6_PCIE_TX_VENDOR_SPECIFIC_DEFAULT 0x00000000 |
8903 | #define smnBIFP6_PCIE_TX_REQUEST_NUM_CNTL_DEFAULT 0x02000000 |
8904 | #define smnBIFP6_PCIE_TX_SEQ_DEFAULT 0x00000000 |
8905 | #define smnBIFP6_PCIE_TX_REPLAY_DEFAULT 0x00900003 |
8906 | #define smnBIFP6_PCIE_TX_ACK_LATENCY_LIMIT_DEFAULT 0x00000000 |
8907 | #define smnBIFP6_PCIE_TX_CREDITS_ADVT_P_DEFAULT 0x00000000 |
8908 | #define smnBIFP6_PCIE_TX_CREDITS_ADVT_NP_DEFAULT 0x00000000 |
8909 | #define smnBIFP6_PCIE_TX_CREDITS_ADVT_CPL_DEFAULT 0x00000000 |
8910 | #define smnBIFP6_PCIE_TX_CREDITS_INIT_P_DEFAULT 0x00000000 |
8911 | #define smnBIFP6_PCIE_TX_CREDITS_INIT_NP_DEFAULT 0x00000000 |
8912 | #define smnBIFP6_PCIE_TX_CREDITS_INIT_CPL_DEFAULT 0x00000000 |
8913 | #define smnBIFP6_PCIE_TX_CREDITS_STATUS_DEFAULT 0x00000000 |
8914 | #define smnBIFP6_PCIE_TX_CREDITS_FCU_THRESHOLD_DEFAULT 0x03330333 |
8915 | #define smnBIFP6_PCIE_P_PORT_LANE_STATUS_DEFAULT 0x00000000 |
8916 | #define smnBIFP6_PCIE_FC_P_DEFAULT 0x00000208 |
8917 | #define smnBIFP6_PCIE_FC_NP_DEFAULT 0x00000202 |
8918 | #define smnBIFP6_PCIE_FC_CPL_DEFAULT 0x00000000 |
8919 | #define smnBIFP6_PCIE_ERR_CNTL_DEFAULT 0x00000500 |
8920 | #define smnBIFP6_PCIE_RX_CNTL_DEFAULT 0x01084000 |
8921 | #define smnBIFP6_PCIE_RX_EXPECTED_SEQNUM_DEFAULT 0x00000000 |
8922 | #define smnBIFP6_PCIE_RX_VENDOR_SPECIFIC_DEFAULT 0x00000000 |
8923 | #define smnBIFP6_PCIE_RX_CNTL3_DEFAULT 0x00000000 |
8924 | #define smnBIFP6_PCIE_RX_CREDITS_ALLOCATED_P_DEFAULT 0x00000000 |
8925 | #define smnBIFP6_PCIE_RX_CREDITS_ALLOCATED_NP_DEFAULT 0x00000000 |
8926 | #define smnBIFP6_PCIE_RX_CREDITS_ALLOCATED_CPL_DEFAULT 0x00000000 |
8927 | #define smnBIFP6_PCIEP_ERROR_INJECT_PHYSICAL_DEFAULT 0x00000000 |
8928 | #define smnBIFP6_PCIEP_ERROR_INJECT_TRANSACTION_DEFAULT 0x00000000 |
8929 | #define smnBIFP6_PCIEP_NAK_COUNTER_DEFAULT 0x00000000 |
8930 | #define smnBIFP6_PCIEP_RX_CAPTURED_LTR_CTRL_STATUS_DEFAULT 0x00000000 |
8931 | #define smnBIFP6_PCIEP_RX_CAPTURED_LTR_THRESHOLD_VALUES_DEFAULT 0x00000000 |
8932 | #define smnBIFP6_PCIE_LC_CNTL_DEFAULT 0x40010030 |
8933 | #define smnBIFP6_PCIE_LC_TRAINING_CNTL_DEFAULT 0x94009880 |
8934 | #define smnBIFP6_PCIE_LC_LINK_WIDTH_CNTL_DEFAULT 0xda800006 |
8935 | #define smnBIFP6_PCIE_LC_N_FTS_CNTL_DEFAULT 0x00ff820c |
8936 | #define smnBIFP6_PCIE_LC_SPEED_CNTL_DEFAULT 0x04400100 |
8937 | #define smnBIFP6_PCIE_LC_STATE0_DEFAULT 0x00000000 |
8938 | #define smnBIFP6_PCIE_LC_STATE1_DEFAULT 0x00000000 |
8939 | #define smnBIFP6_PCIE_LC_STATE2_DEFAULT 0x00000000 |
8940 | #define smnBIFP6_PCIE_LC_STATE3_DEFAULT 0x00000000 |
8941 | #define smnBIFP6_PCIE_LC_STATE4_DEFAULT 0x00000000 |
8942 | #define smnBIFP6_PCIE_LC_STATE5_DEFAULT 0x00000000 |
8943 | #define smnBIFP6_PCIE_LINK_MANAGEMENT_CNTL2_DEFAULT 0x00000000 |
8944 | #define smnBIFP6_PCIE_LC_CNTL2_DEFAULT 0x96180280 |
8945 | #define smnBIFP6_PCIE_LC_BW_CHANGE_CNTL_DEFAULT 0x00000000 |
8946 | #define smnBIFP6_PCIE_LC_CDR_CNTL_DEFAULT 0x01018060 |
8947 | #define smnBIFP6_PCIE_LC_LANE_CNTL_DEFAULT 0x00000000 |
8948 | #define smnBIFP6_PCIE_LC_CNTL3_DEFAULT 0x2850a020 |
8949 | #define smnBIFP6_PCIE_LC_CNTL4_DEFAULT 0x0340048c |
8950 | #define smnBIFP6_PCIE_LC_CNTL5_DEFAULT 0x40410b2c |
8951 | #define smnBIFP6_PCIE_LC_FORCE_COEFF_DEFAULT 0x00080000 |
8952 | #define smnBIFP6_PCIE_LC_BEST_EQ_SETTINGS_DEFAULT 0x00000000 |
8953 | #define smnBIFP6_PCIE_LC_FORCE_EQ_REQ_COEFF_DEFAULT 0x00000000 |
8954 | #define smnBIFP6_PCIE_LC_CNTL6_DEFAULT 0x8a000010 |
8955 | #define smnBIFP6_PCIE_LC_CNTL7_DEFAULT 0x8000026e |
8956 | #define smnBIFP6_PCIE_LINK_MANAGEMENT_STATUS_DEFAULT 0x00000000 |
8957 | #define smnBIFP6_PCIE_LINK_MANAGEMENT_MASK_DEFAULT 0x00003fff |
8958 | #define smnBIFP6_PCIE_LINK_MANAGEMENT_CNTL_DEFAULT 0x00000000 |
8959 | #define smnBIFP6_PCIEP_STRAP_LC_DEFAULT 0x00000000 |
8960 | #define smnBIFP6_PCIEP_STRAP_MISC_DEFAULT 0x00000000 |
8961 | #define smnBIFP6_PCIE_LC_L1_PM_SUBSTATE_DEFAULT 0x00540000 |
8962 | #define smnBIFP6_PCIE_LC_L1_PM_SUBSTATE2_DEFAULT 0x00000000 |
8963 | #define smnBIFP6_PCIE_LC_PORT_ORDER_DEFAULT 0x00000000 |
8964 | #define smnBIFP6_PCIEP_BCH_ECC_CNTL_DEFAULT 0x00000100 |
8965 | #define smnBIFP6_PCIEP_HPGI_PRIVATE_DEFAULT 0x00000000 |
8966 | #define smnBIFP6_PCIEP_HPGI_DEFAULT 0x00000000 |
8967 | #define smnBIFP6_PCIEP_HCNT_DESCRIPTOR_DEFAULT 0x00000000 |
8968 | #define smnBIFP6_PCIEP_PERF_CNTL_COUNT_TXCLK_DEFAULT 0x00000000 |
8969 | |
8970 | |
8971 | // addressBlock: nbio_pcie0_pciedir |
8972 | #define smnPCIE_RESERVED_DEFAULT 0x00000000 |
8973 | #define smnPCIE_SCRATCH_DEFAULT 0x00000000 |
8974 | #define smnPCIE_RX_NUM_NAK_DEFAULT 0x00000000 |
8975 | #define smnPCIE_RX_NUM_NAK_GENERATED_DEFAULT 0x00000000 |
8976 | #define smnPCIE_CNTL_DEFAULT 0x80e31000 |
8977 | #define smnPCIE_CONFIG_CNTL_DEFAULT 0x0800010f |
8978 | #define smnPCIE_TX_TRACKING_ADDR_LO_DEFAULT 0x00000000 |
8979 | #define smnPCIE_TX_TRACKING_ADDR_HI_DEFAULT 0x00000000 |
8980 | #define smnPCIE_TX_TRACKING_CTRL_STATUS_DEFAULT 0x00000000 |
8981 | #define smnPCIE_BW_BY_UNITID_DEFAULT 0x00000000 |
8982 | #define smnPCIE_CNTL2_DEFAULT 0x0e000109 |
8983 | #define smnPCIE_RX_CNTL2_DEFAULT 0x00000000 |
8984 | #define smnPCIE_TX_F0_ATTR_CNTL_DEFAULT 0x00000000 |
8985 | #define smnPCIE_TX_SWUS_ATTR_CNTL_DEFAULT 0x00000000 |
8986 | #define smnPCIE_CI_CNTL_DEFAULT 0x00000010 |
8987 | #define smnPCIE_BUS_CNTL_DEFAULT 0x00000000 |
8988 | #define smnPCIE_LC_STATE6_DEFAULT 0x00000000 |
8989 | #define smnPCIE_LC_STATE7_DEFAULT 0x00000000 |
8990 | #define smnPCIE_LC_STATE8_DEFAULT 0x00000000 |
8991 | #define smnPCIE_LC_STATE9_DEFAULT 0x00000000 |
8992 | #define smnPCIE_LC_STATE10_DEFAULT 0x00000000 |
8993 | #define smnPCIE_LC_STATE11_DEFAULT 0x00000000 |
8994 | #define smnPCIE_LC_STATUS1_DEFAULT 0x00000000 |
8995 | #define smnPCIE_LC_STATUS2_DEFAULT 0x00000000 |
8996 | #define smnPCIE_WPR_CNTL_DEFAULT 0x00000005 |
8997 | #define smnPCIE_RX_LAST_TLP0_DEFAULT 0x00000000 |
8998 | #define smnPCIE_RX_LAST_TLP1_DEFAULT 0x00000000 |
8999 | #define smnPCIE_RX_LAST_TLP2_DEFAULT 0x00000000 |
9000 | #define smnPCIE_RX_LAST_TLP3_DEFAULT 0x00000000 |
9001 | #define smnPCIE_TX_LAST_TLP0_DEFAULT 0x00000000 |
9002 | #define smnPCIE_TX_LAST_TLP1_DEFAULT 0x00000000 |
9003 | #define smnPCIE_TX_LAST_TLP2_DEFAULT 0x00000000 |
9004 | #define smnPCIE_TX_LAST_TLP3_DEFAULT 0x00000000 |
9005 | #define smnPCIE_I2C_REG_ADDR_EXPAND_DEFAULT 0x00000000 |
9006 | #define smnPCIE_I2C_REG_DATA_DEFAULT 0x00000000 |
9007 | #define smnPCIE_CFG_CNTL_DEFAULT 0x00000000 |
9008 | #define smnPCIE_LC_PM_CNTL_DEFAULT 0x76543210 |
9009 | #define smnPCIE_LC_PORT_ORDER_CNTL_DEFAULT 0x00000000 |
9010 | #define smnPCIE_P_CNTL_DEFAULT 0x00010000 |
9011 | #define smnPCIE_P_BUF_STATUS_DEFAULT 0x00000000 |
9012 | #define smnPCIE_P_DECODER_STATUS_DEFAULT 0x00000000 |
9013 | #define smnPCIE_P_MISC_STATUS_DEFAULT 0x00000000 |
9014 | #define smnPCIE_P_RCV_L0S_FTS_DET_DEFAULT 0x000000ff |
9015 | #define smnPCIE_RX_AD_DEFAULT 0x00000002 |
9016 | #define smnPCIE_SDP_CTRL_DEFAULT 0x00000002 |
9017 | #define smnNBIO_CLKREQb_MAP_CNTL_DEFAULT 0x00000000 |
9018 | #define smnPCIE_SDP_SWUS_SLV_ATTR_CTRL_DEFAULT 0x00000000 |
9019 | #define smnPCIE_SDP_RC_SLV_ATTR_CTRL_DEFAULT 0x00000000 |
9020 | #define smnPCIE_PERF_COUNT_CNTL_DEFAULT 0x00000000 |
9021 | #define smnPCIE_PERF_CNTL_TXCLK_DEFAULT 0x00000000 |
9022 | #define smnPCIE_PERF_COUNT0_TXCLK_DEFAULT 0x00000000 |
9023 | #define smnPCIE_PERF_COUNT1_TXCLK_DEFAULT 0x00000000 |
9024 | #define smnPCIE_PERF_CNTL_MST_R_CLK_DEFAULT 0x00000000 |
9025 | #define smnPCIE_PERF_COUNT0_MST_R_CLK_DEFAULT 0x00000000 |
9026 | #define smnPCIE_PERF_COUNT1_MST_R_CLK_DEFAULT 0x00000000 |
9027 | #define smnPCIE_PERF_CNTL_MST_C_CLK_DEFAULT 0x00000000 |
9028 | #define smnPCIE_PERF_COUNT0_MST_C_CLK_DEFAULT 0x00000000 |
9029 | #define smnPCIE_PERF_COUNT1_MST_C_CLK_DEFAULT 0x00000000 |
9030 | #define smnPCIE_PERF_CNTL_SLV_R_CLK_DEFAULT 0x00000000 |
9031 | #define smnPCIE_PERF_COUNT0_SLV_R_CLK_DEFAULT 0x00000000 |
9032 | #define smnPCIE_PERF_COUNT1_SLV_R_CLK_DEFAULT 0x00000000 |
9033 | #define smnPCIE_PERF_CNTL_SLV_S_C_CLK_DEFAULT 0x00000000 |
9034 | #define smnPCIE_PERF_COUNT0_SLV_S_C_CLK_DEFAULT 0x00000000 |
9035 | #define smnPCIE_PERF_COUNT1_SLV_S_C_CLK_DEFAULT 0x00000000 |
9036 | #define smnPCIE_PERF_CNTL_SLV_NS_C_CLK_DEFAULT 0x00000000 |
9037 | #define smnPCIE_PERF_COUNT0_SLV_NS_C_CLK_DEFAULT 0x00000000 |
9038 | #define smnPCIE_PERF_COUNT1_SLV_NS_C_CLK_DEFAULT 0x00000000 |
9039 | #define smnPCIE_PERF_CNTL_EVENT0_PORT_SEL_DEFAULT 0x00000000 |
9040 | #define smnPCIE_PERF_CNTL_EVENT1_PORT_SEL_DEFAULT 0x00000000 |
9041 | #define smnPCIE_PERF_CNTL_TXCLK2_DEFAULT 0x00000000 |
9042 | #define smnPCIE_PERF_COUNT0_TXCLK2_DEFAULT 0x00000000 |
9043 | #define smnPCIE_PERF_COUNT1_TXCLK2_DEFAULT 0x00000000 |
9044 | #define smnPCIE_PRBS_CLR_DEFAULT 0x00000000 |
9045 | #define smnPCIE_PRBS_STATUS1_DEFAULT 0x00000000 |
9046 | #define smnPCIE_PRBS_STATUS2_DEFAULT 0x00000000 |
9047 | #define smnPCIE_PRBS_FREERUN_DEFAULT 0x00000000 |
9048 | #define smnPCIE_PRBS_MISC_DEFAULT 0x00000000 |
9049 | #define smnPCIE_PRBS_USER_PATTERN_DEFAULT 0x00000000 |
9050 | #define smnPCIE_PRBS_LO_BITCNT_DEFAULT 0x00000000 |
9051 | #define smnPCIE_PRBS_HI_BITCNT_DEFAULT 0x00000000 |
9052 | #define smnPCIE_PRBS_ERRCNT_0_DEFAULT 0x00000000 |
9053 | #define smnPCIE_PRBS_ERRCNT_1_DEFAULT 0x00000000 |
9054 | #define smnPCIE_PRBS_ERRCNT_2_DEFAULT 0x00000000 |
9055 | #define smnPCIE_PRBS_ERRCNT_3_DEFAULT 0x00000000 |
9056 | #define smnPCIE_PRBS_ERRCNT_4_DEFAULT 0x00000000 |
9057 | #define smnPCIE_PRBS_ERRCNT_5_DEFAULT 0x00000000 |
9058 | #define smnPCIE_PRBS_ERRCNT_6_DEFAULT 0x00000000 |
9059 | #define smnPCIE_PRBS_ERRCNT_7_DEFAULT 0x00000000 |
9060 | #define smnPCIE_PRBS_ERRCNT_8_DEFAULT 0x00000000 |
9061 | #define smnPCIE_PRBS_ERRCNT_9_DEFAULT 0x00000000 |
9062 | #define smnPCIE_PRBS_ERRCNT_10_DEFAULT 0x00000000 |
9063 | #define smnPCIE_PRBS_ERRCNT_11_DEFAULT 0x00000000 |
9064 | #define smnPCIE_PRBS_ERRCNT_12_DEFAULT 0x00000000 |
9065 | #define smnPCIE_PRBS_ERRCNT_13_DEFAULT 0x00000000 |
9066 | #define smnPCIE_PRBS_ERRCNT_14_DEFAULT 0x00000000 |
9067 | #define smnPCIE_PRBS_ERRCNT_15_DEFAULT 0x00000000 |
9068 | #define smnSWRST_COMMAND_STATUS_DEFAULT 0x00000000 |
9069 | #define smnSWRST_GENERAL_CONTROL_DEFAULT 0x02001002 |
9070 | #define smnSWRST_COMMAND_0_DEFAULT 0x00000000 |
9071 | #define smnSWRST_COMMAND_1_DEFAULT 0x04000000 |
9072 | #define smnSWRST_CONTROL_0_DEFAULT 0x5600ff00 |
9073 | #define smnSWRST_CONTROL_1_DEFAULT 0xc220ffff |
9074 | #define smnSWRST_CONTROL_2_DEFAULT 0x00000000 |
9075 | #define smnSWRST_CONTROL_3_DEFAULT 0x00000000 |
9076 | #define smnSWRST_CONTROL_4_DEFAULT 0x5c00ff01 |
9077 | #define smnSWRST_CONTROL_5_DEFAULT 0xfe20ffff |
9078 | #define smnSWRST_CONTROL_6_DEFAULT 0x000007ff |
9079 | #define smnSWRST_EP_COMMAND_0_DEFAULT 0x00000000 |
9080 | #define smnSWRST_EP_CONTROL_0_DEFAULT 0x00000500 |
9081 | #define smnCPM_CONTROL_DEFAULT 0x0080da00 |
9082 | #define smnSMN_APERTURE_ID_A_DEFAULT 0x00000000 |
9083 | #define smnSMN_APERTURE_ID_B_DEFAULT 0x00000000 |
9084 | #define smnRSMU_MASTER_CONTROL_DEFAULT 0x00000000 |
9085 | #define smnRSMU_SLAVE_CONTROL_DEFAULT 0x00000001 |
9086 | #define smnRSMU_POWER_GATING_CONTROL_DEFAULT 0x00000000 |
9087 | #define smnRSMU_BIOS_TIMER_CMD_DEFAULT 0x00000000 |
9088 | #define smnRSMU_BIOS_TIMER_CNTL_DEFAULT 0x00000064 |
9089 | #define smnLNCNT_CONTROL_DEFAULT 0x00000000 |
9090 | #define smnCFG_LNC_WINDOW_REGISTER_DEFAULT 0x00000000 |
9091 | #define smnLNCNT_QUAN_THRD_DEFAULT 0x00000000 |
9092 | #define smnLNCNT_WEIGHT_DEFAULT 0x00000000 |
9093 | #define smnLNC_TOTAL_WACC_REGISTER_DEFAULT 0x00000000 |
9094 | #define smnLNC_BW_WACC_REGISTER_DEFAULT 0x00000000 |
9095 | #define smnLNC_CMN_WACC_REGISTER_DEFAULT 0x00000000 |
9096 | #define smnSMU_HP_STATUS_UPDATE_DEFAULT 0x00000000 |
9097 | #define smnHP_SMU_COMMAND_UPDATE_DEFAULT 0x00000000 |
9098 | #define smnSMU_HP_END_OF_INTERRUPT_DEFAULT 0x00000000 |
9099 | #define smnSMU_INT_PIN_SHARING_PORT_INDICATOR_DEFAULT 0x00000000 |
9100 | #define smnPCIE_PGMST_CNTL_DEFAULT 0x00000000 |
9101 | #define smnPCIE_PGSLV_CNTL_DEFAULT 0x00000004 |
9102 | #define smnSMU_PCIE_FENCED1_REG_DEFAULT 0x00000000 |
9103 | #define smnSMU_PCIE_FENCED2_REG_DEFAULT 0x00000000 |
9104 | |
9105 | |
9106 | // addressBlock: nbio_iohub_nb_nbcfg_nb_cfgdec |
9107 | #define smnNB_NBCFG1_NB_VENDOR_ID_DEFAULT 0x00000000 |
9108 | #define smnNB_NBCFG1_NB_DEVICE_ID_DEFAULT 0x00000000 |
9109 | #define smnNB_NBCFG1_NB_COMMAND_DEFAULT 0x00000000 |
9110 | #define smnNB_NBCFG1_NB_STATUS_DEFAULT 0x00000000 |
9111 | #define smnNB_NBCFG1_NB_REVISION_ID_DEFAULT 0x00000000 |
9112 | #define smnNB_NBCFG1_NB_REGPROG_INF_DEFAULT 0x00000000 |
9113 | #define smnNB_NBCFG1_NB_SUB_CLASS_DEFAULT 0x00000000 |
9114 | #define smnNB_NBCFG1_NB_BASE_CODE_DEFAULT 0x00000000 |
9115 | #define smnNB_NBCFG1_NB_CACHE_LINE_DEFAULT 0x00000000 |
9116 | #define smnNB_NBCFG1_NB_LATENCY_DEFAULT 0x00000000 |
9117 | #define 0x00000080 |
9118 | #define smnNB_NBCFG1_NB_ADAPTER_ID_DEFAULT 0x15d01022 |
9119 | #define smnNB_NBCFG1_NB_CAPABILITIES_PTR_DEFAULT 0x00000000 |
9120 | #define 0x00000080 |
9121 | #define smnNB_NBCFG1_NB_PCI_CTRL_DEFAULT 0x00000000 |
9122 | #define smnNB_NBCFG1_NB_ADAPTER_ID_W_DEFAULT 0x15d01022 |
9123 | #define smnNB_NBCFG1_NB_SMN_INDEX_EXTENSION_0_DEFAULT 0x00000000 |
9124 | #define smnNB_NBCFG1_NB_SMN_INDEX_0_DEFAULT 0x00000000 |
9125 | #define smnNB_NBCFG1_NB_SMN_DATA_0_DEFAULT 0x00000000 |
9126 | #define smnNB_NBCFG1_NBCFG_SCRATCH_0_DEFAULT 0x00000000 |
9127 | #define smnNB_NBCFG1_NBCFG_SCRATCH_1_DEFAULT 0x00000000 |
9128 | #define smnNB_NBCFG1_NBCFG_SCRATCH_2_DEFAULT 0x00000000 |
9129 | #define smnNB_NBCFG1_NBCFG_SCRATCH_3_DEFAULT 0x00000000 |
9130 | #define smnNB_NBCFG1_NBCFG_SCRATCH_4_DEFAULT 0x00000000 |
9131 | #define smnNB_NBCFG1_NB_PCI_ARB_DEFAULT 0x00000108 |
9132 | #define smnNB_NBCFG1_NB_DRAM_SLOT1_BASE_DEFAULT 0x00000000 |
9133 | #define smnNB_NBCFG1_NB_TOP_OF_DRAM_SLOT1_DEFAULT 0x00000000 |
9134 | #define smnNB_NBCFG1_NB_SMN_INDEX_EXTENSION_1_DEFAULT 0x00000000 |
9135 | #define smnNB_NBCFG1_NB_SMN_INDEX_1_DEFAULT 0x00000000 |
9136 | #define smnNB_NBCFG1_NB_SMN_DATA_1_DEFAULT 0x00000000 |
9137 | #define smnNB_NBCFG1_NB_INDEX_DATA_MUTEX0_DEFAULT 0x00000000 |
9138 | #define smnNB_NBCFG1_NB_INDEX_DATA_MUTEX1_DEFAULT 0x00000000 |
9139 | #define smnNB_NBCFG1_NB_SMN_INDEX_EXTENSION_2_DEFAULT 0x00000000 |
9140 | #define smnNB_NBCFG1_NB_SMN_INDEX_2_DEFAULT 0x00000000 |
9141 | #define smnNB_NBCFG1_NB_SMN_DATA_2_DEFAULT 0x00000000 |
9142 | #define smnNB_NBCFG1_NB_SMN_INDEX_EXTENSION_3_DEFAULT 0x00000000 |
9143 | #define smnNB_NBCFG1_NB_SMN_INDEX_3_DEFAULT 0x00000000 |
9144 | #define smnNB_NBCFG1_NB_SMN_DATA_3_DEFAULT 0x00000000 |
9145 | #define smnNB_NBCFG1_NB_SMN_INDEX_EXTENSION_4_DEFAULT 0x00000000 |
9146 | #define smnNB_NBCFG1_NB_SMN_INDEX_4_DEFAULT 0x00000000 |
9147 | #define smnNB_NBCFG1_NB_SMN_DATA_4_DEFAULT 0x00000000 |
9148 | #define smnNB_NBCFG1_NB_SMN_INDEX_EXTENSION_5_DEFAULT 0x00000000 |
9149 | #define smnNB_NBCFG1_NB_SMN_INDEX_5_DEFAULT 0x00000000 |
9150 | #define smnNB_NBCFG1_NB_SMN_DATA_5_DEFAULT 0x00000000 |
9151 | #define smnNB_NBCFG1_NB_PERF_CNT_CTRL_DEFAULT 0x00808000 |
9152 | #define smnNB_NBCFG1_NB_SMN_INDEX_6_DEFAULT 0x00000000 |
9153 | #define smnNB_NBCFG1_NB_SMN_DATA_6_DEFAULT 0x00000000 |
9154 | |
9155 | |
9156 | // addressBlock: nbio_iohub_nb_iommushadow_iommushadow_cfgdecp |
9157 | #define smnSHADOW_IOMMU_MMIO_CNTRL_0_DEFAULT 0x00000000 |
9158 | #define smnSHADOW_IOMMU_CAP_BASE_LO_DEFAULT 0x00000000 |
9159 | #define smnSHADOW_IOMMU_CAP_BASE_HI_DEFAULT 0x00000000 |
9160 | |
9161 | |
9162 | // addressBlock: nbio_iohub_nb_PCIE0shadow0_pcieshadow_cfgdecp |
9163 | #define smnNB_PCIE0SHADOW0_COMMAND_DEFAULT 0x00000000 |
9164 | #define smnNB_PCIE0SHADOW0_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 |
9165 | #define smnNB_PCIE0SHADOW0_IO_BASE_LIMIT_DEFAULT 0x00000000 |
9166 | #define smnNB_PCIE0SHADOW0_MEM_BASE_LIMIT_DEFAULT 0x00000000 |
9167 | #define smnNB_PCIE0SHADOW0_PREF_BASE_LIMIT_DEFAULT 0x00000000 |
9168 | #define smnNB_PCIE0SHADOW0_PREF_BASE_UPPER_DEFAULT 0x00000000 |
9169 | #define smnNB_PCIE0SHADOW0_PREF_LIMIT_UPPER_DEFAULT 0x00000000 |
9170 | #define smnNB_PCIE0SHADOW0_IO_BASE_LIMIT_HI_DEFAULT 0x00000000 |
9171 | #define smnNB_PCIE0SHADOW0_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000 |
9172 | #define smnNB_PCIE0SHADOW0_EXT_BRIDGE_CNTL_DEFAULT 0x00000000 |
9173 | #define smnNB_PCIE0SHADOW0_PMI_STATUS_CNTL_DEFAULT 0x00000000 |
9174 | #define smnNB_PCIE0SHADOW0_SLOT_CAP_DEFAULT 0x00000000 |
9175 | #define smnNB_PCIE0SHADOW0_ROOT_CNTL_DEFAULT 0x00000000 |
9176 | #define smnNB_PCIE0SHADOW0_DEVICE_CNTL2_DEFAULT 0x00000000 |
9177 | |
9178 | |
9179 | // addressBlock: nbio_iohub_nb_PCIE0shadow1_pcieshadow_cfgdecp |
9180 | #define smnNB_PCIE0SHADOW1_COMMAND_DEFAULT 0x00000000 |
9181 | #define smnNB_PCIE0SHADOW1_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 |
9182 | #define smnNB_PCIE0SHADOW1_IO_BASE_LIMIT_DEFAULT 0x00000000 |
9183 | #define smnNB_PCIE0SHADOW1_MEM_BASE_LIMIT_DEFAULT 0x00000000 |
9184 | #define smnNB_PCIE0SHADOW1_PREF_BASE_LIMIT_DEFAULT 0x00000000 |
9185 | #define smnNB_PCIE0SHADOW1_PREF_BASE_UPPER_DEFAULT 0x00000000 |
9186 | #define smnNB_PCIE0SHADOW1_PREF_LIMIT_UPPER_DEFAULT 0x00000000 |
9187 | #define smnNB_PCIE0SHADOW1_IO_BASE_LIMIT_HI_DEFAULT 0x00000000 |
9188 | #define smnNB_PCIE0SHADOW1_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000 |
9189 | #define smnNB_PCIE0SHADOW1_EXT_BRIDGE_CNTL_DEFAULT 0x00000000 |
9190 | #define smnNB_PCIE0SHADOW1_PMI_STATUS_CNTL_DEFAULT 0x00000000 |
9191 | #define smnNB_PCIE0SHADOW1_SLOT_CAP_DEFAULT 0x00000000 |
9192 | #define smnNB_PCIE0SHADOW1_ROOT_CNTL_DEFAULT 0x00000000 |
9193 | #define smnNB_PCIE0SHADOW1_DEVICE_CNTL2_DEFAULT 0x00000000 |
9194 | |
9195 | |
9196 | // addressBlock: nbio_iohub_nb_PCIE0shadow2_pcieshadow_cfgdecp |
9197 | #define smnNB_PCIE0SHADOW2_COMMAND_DEFAULT 0x00000000 |
9198 | #define smnNB_PCIE0SHADOW2_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 |
9199 | #define smnNB_PCIE0SHADOW2_IO_BASE_LIMIT_DEFAULT 0x00000000 |
9200 | #define smnNB_PCIE0SHADOW2_MEM_BASE_LIMIT_DEFAULT 0x00000000 |
9201 | #define smnNB_PCIE0SHADOW2_PREF_BASE_LIMIT_DEFAULT 0x00000000 |
9202 | #define smnNB_PCIE0SHADOW2_PREF_BASE_UPPER_DEFAULT 0x00000000 |
9203 | #define smnNB_PCIE0SHADOW2_PREF_LIMIT_UPPER_DEFAULT 0x00000000 |
9204 | #define smnNB_PCIE0SHADOW2_IO_BASE_LIMIT_HI_DEFAULT 0x00000000 |
9205 | #define smnNB_PCIE0SHADOW2_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000 |
9206 | #define smnNB_PCIE0SHADOW2_EXT_BRIDGE_CNTL_DEFAULT 0x00000000 |
9207 | #define smnNB_PCIE0SHADOW2_PMI_STATUS_CNTL_DEFAULT 0x00000000 |
9208 | #define smnNB_PCIE0SHADOW2_SLOT_CAP_DEFAULT 0x00000000 |
9209 | #define smnNB_PCIE0SHADOW2_ROOT_CNTL_DEFAULT 0x00000000 |
9210 | #define smnNB_PCIE0SHADOW2_DEVICE_CNTL2_DEFAULT 0x00000000 |
9211 | |
9212 | |
9213 | // addressBlock: nbio_iohub_nb_PCIE0shadow3_pcieshadow_cfgdecp |
9214 | #define smnNB_PCIE0SHADOW3_COMMAND_DEFAULT 0x00000000 |
9215 | #define smnNB_PCIE0SHADOW3_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 |
9216 | #define smnNB_PCIE0SHADOW3_IO_BASE_LIMIT_DEFAULT 0x00000000 |
9217 | #define smnNB_PCIE0SHADOW3_MEM_BASE_LIMIT_DEFAULT 0x00000000 |
9218 | #define smnNB_PCIE0SHADOW3_PREF_BASE_LIMIT_DEFAULT 0x00000000 |
9219 | #define smnNB_PCIE0SHADOW3_PREF_BASE_UPPER_DEFAULT 0x00000000 |
9220 | #define smnNB_PCIE0SHADOW3_PREF_LIMIT_UPPER_DEFAULT 0x00000000 |
9221 | #define smnNB_PCIE0SHADOW3_IO_BASE_LIMIT_HI_DEFAULT 0x00000000 |
9222 | #define smnNB_PCIE0SHADOW3_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000 |
9223 | #define smnNB_PCIE0SHADOW3_EXT_BRIDGE_CNTL_DEFAULT 0x00000000 |
9224 | #define smnNB_PCIE0SHADOW3_PMI_STATUS_CNTL_DEFAULT 0x00000000 |
9225 | #define smnNB_PCIE0SHADOW3_SLOT_CAP_DEFAULT 0x00000000 |
9226 | #define smnNB_PCIE0SHADOW3_ROOT_CNTL_DEFAULT 0x00000000 |
9227 | #define smnNB_PCIE0SHADOW3_DEVICE_CNTL2_DEFAULT 0x00000000 |
9228 | |
9229 | |
9230 | // addressBlock: nbio_iohub_nb_PCIE0shadow4_pcieshadow_cfgdecp |
9231 | #define smnNB_PCIE0SHADOW4_COMMAND_DEFAULT 0x00000000 |
9232 | #define smnNB_PCIE0SHADOW4_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 |
9233 | #define smnNB_PCIE0SHADOW4_IO_BASE_LIMIT_DEFAULT 0x00000000 |
9234 | #define smnNB_PCIE0SHADOW4_MEM_BASE_LIMIT_DEFAULT 0x00000000 |
9235 | #define smnNB_PCIE0SHADOW4_PREF_BASE_LIMIT_DEFAULT 0x00000000 |
9236 | #define smnNB_PCIE0SHADOW4_PREF_BASE_UPPER_DEFAULT 0x00000000 |
9237 | #define smnNB_PCIE0SHADOW4_PREF_LIMIT_UPPER_DEFAULT 0x00000000 |
9238 | #define smnNB_PCIE0SHADOW4_IO_BASE_LIMIT_HI_DEFAULT 0x00000000 |
9239 | #define smnNB_PCIE0SHADOW4_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000 |
9240 | #define smnNB_PCIE0SHADOW4_EXT_BRIDGE_CNTL_DEFAULT 0x00000000 |
9241 | #define smnNB_PCIE0SHADOW4_PMI_STATUS_CNTL_DEFAULT 0x00000000 |
9242 | #define smnNB_PCIE0SHADOW4_SLOT_CAP_DEFAULT 0x00000000 |
9243 | #define smnNB_PCIE0SHADOW4_ROOT_CNTL_DEFAULT 0x00000000 |
9244 | #define smnNB_PCIE0SHADOW4_DEVICE_CNTL2_DEFAULT 0x00000000 |
9245 | |
9246 | |
9247 | // addressBlock: nbio_iohub_nb_PCIE0shadow5_pcieshadow_cfgdecp |
9248 | #define smnNB_PCIE0SHADOW5_COMMAND_DEFAULT 0x00000000 |
9249 | #define smnNB_PCIE0SHADOW5_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 |
9250 | #define smnNB_PCIE0SHADOW5_IO_BASE_LIMIT_DEFAULT 0x00000000 |
9251 | #define smnNB_PCIE0SHADOW5_MEM_BASE_LIMIT_DEFAULT 0x00000000 |
9252 | #define smnNB_PCIE0SHADOW5_PREF_BASE_LIMIT_DEFAULT 0x00000000 |
9253 | #define smnNB_PCIE0SHADOW5_PREF_BASE_UPPER_DEFAULT 0x00000000 |
9254 | #define smnNB_PCIE0SHADOW5_PREF_LIMIT_UPPER_DEFAULT 0x00000000 |
9255 | #define smnNB_PCIE0SHADOW5_IO_BASE_LIMIT_HI_DEFAULT 0x00000000 |
9256 | #define smnNB_PCIE0SHADOW5_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000 |
9257 | #define smnNB_PCIE0SHADOW5_EXT_BRIDGE_CNTL_DEFAULT 0x00000000 |
9258 | #define smnNB_PCIE0SHADOW5_PMI_STATUS_CNTL_DEFAULT 0x00000000 |
9259 | #define smnNB_PCIE0SHADOW5_SLOT_CAP_DEFAULT 0x00000000 |
9260 | #define smnNB_PCIE0SHADOW5_ROOT_CNTL_DEFAULT 0x00000000 |
9261 | #define smnNB_PCIE0SHADOW5_DEVICE_CNTL2_DEFAULT 0x00000000 |
9262 | |
9263 | |
9264 | // addressBlock: nbio_iohub_nb_PCIE0shadow6_pcieshadow_cfgdecp |
9265 | #define smnNB_PCIE0SHADOW6_COMMAND_DEFAULT 0x00000000 |
9266 | #define smnNB_PCIE0SHADOW6_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 |
9267 | #define smnNB_PCIE0SHADOW6_IO_BASE_LIMIT_DEFAULT 0x00000000 |
9268 | #define smnNB_PCIE0SHADOW6_MEM_BASE_LIMIT_DEFAULT 0x00000000 |
9269 | #define smnNB_PCIE0SHADOW6_PREF_BASE_LIMIT_DEFAULT 0x00000000 |
9270 | #define smnNB_PCIE0SHADOW6_PREF_BASE_UPPER_DEFAULT 0x00000000 |
9271 | #define smnNB_PCIE0SHADOW6_PREF_LIMIT_UPPER_DEFAULT 0x00000000 |
9272 | #define smnNB_PCIE0SHADOW6_IO_BASE_LIMIT_HI_DEFAULT 0x00000000 |
9273 | #define smnNB_PCIE0SHADOW6_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000 |
9274 | #define smnNB_PCIE0SHADOW6_EXT_BRIDGE_CNTL_DEFAULT 0x00000000 |
9275 | #define smnNB_PCIE0SHADOW6_PMI_STATUS_CNTL_DEFAULT 0x00000000 |
9276 | #define smnNB_PCIE0SHADOW6_SLOT_CAP_DEFAULT 0x00000000 |
9277 | #define smnNB_PCIE0SHADOW6_ROOT_CNTL_DEFAULT 0x00000000 |
9278 | #define smnNB_PCIE0SHADOW6_DEVICE_CNTL2_DEFAULT 0x00000000 |
9279 | |
9280 | |
9281 | // addressBlock: nbio_iohub_nb_NBIF1shadow0_pcieshadow_cfgdecp |
9282 | #define smnNB_NBIF1SHADOW0_COMMAND_DEFAULT 0x00000000 |
9283 | #define smnNB_NBIF1SHADOW0_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 |
9284 | #define smnNB_NBIF1SHADOW0_IO_BASE_LIMIT_DEFAULT 0x00000000 |
9285 | #define smnNB_NBIF1SHADOW0_MEM_BASE_LIMIT_DEFAULT 0x00000000 |
9286 | #define smnNB_NBIF1SHADOW0_PREF_BASE_LIMIT_DEFAULT 0x00000000 |
9287 | #define smnNB_NBIF1SHADOW0_PREF_BASE_UPPER_DEFAULT 0x00000000 |
9288 | #define smnNB_NBIF1SHADOW0_PREF_LIMIT_UPPER_DEFAULT 0x00000000 |
9289 | #define smnNB_NBIF1SHADOW0_IO_BASE_LIMIT_HI_DEFAULT 0x00000000 |
9290 | #define smnNB_NBIF1SHADOW0_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000 |
9291 | #define smnNB_NBIF1SHADOW0_EXT_BRIDGE_CNTL_DEFAULT 0x00000000 |
9292 | #define smnNB_NBIF1SHADOW0_PMI_STATUS_CNTL_DEFAULT 0x00000000 |
9293 | #define smnNB_NBIF1SHADOW0_SLOT_CAP_DEFAULT 0x00000000 |
9294 | #define smnNB_NBIF1SHADOW0_ROOT_CNTL_DEFAULT 0x00000000 |
9295 | #define smnNB_NBIF1SHADOW0_DEVICE_CNTL2_DEFAULT 0x00000000 |
9296 | |
9297 | |
9298 | // addressBlock: nbio_iohub_nb_NBIF1shadow1_pcieshadow_cfgdecp |
9299 | #define smnNB_NBIF1SHADOW1_COMMAND_DEFAULT 0x00000000 |
9300 | #define smnNB_NBIF1SHADOW1_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 |
9301 | #define smnNB_NBIF1SHADOW1_IO_BASE_LIMIT_DEFAULT 0x00000000 |
9302 | #define smnNB_NBIF1SHADOW1_MEM_BASE_LIMIT_DEFAULT 0x00000000 |
9303 | #define smnNB_NBIF1SHADOW1_PREF_BASE_LIMIT_DEFAULT 0x00000000 |
9304 | #define smnNB_NBIF1SHADOW1_PREF_BASE_UPPER_DEFAULT 0x00000000 |
9305 | #define smnNB_NBIF1SHADOW1_PREF_LIMIT_UPPER_DEFAULT 0x00000000 |
9306 | #define smnNB_NBIF1SHADOW1_IO_BASE_LIMIT_HI_DEFAULT 0x00000000 |
9307 | #define smnNB_NBIF1SHADOW1_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000 |
9308 | #define smnNB_NBIF1SHADOW1_EXT_BRIDGE_CNTL_DEFAULT 0x00000000 |
9309 | #define smnNB_NBIF1SHADOW1_PMI_STATUS_CNTL_DEFAULT 0x00000000 |
9310 | #define smnNB_NBIF1SHADOW1_SLOT_CAP_DEFAULT 0x00000000 |
9311 | #define smnNB_NBIF1SHADOW1_ROOT_CNTL_DEFAULT 0x00000000 |
9312 | #define smnNB_NBIF1SHADOW1_DEVICE_CNTL2_DEFAULT 0x00000000 |
9313 | |
9314 | |
9315 | // addressBlock: nbio_iohub_nb_fastreg_fastreg_cfgdec |
9316 | #define smnFASTREG_APERTURE_DEFAULT 0x00000000 |
9317 | |
9318 | |
9319 | // addressBlock: nbio_iohub_nb_misc_misc_cfgdec |
9320 | #define smnNB_CNTL_DEFAULT 0x00000000 |
9321 | #define smnNB_SPARE1_DEFAULT 0x00000000 |
9322 | #define smnNB_SPARE2_DEFAULT 0x00000000 |
9323 | #define smnNB_REVID_DEFAULT 0x00000000 |
9324 | #define smnIOHC_REFCLK_MODE_DEFAULT 0x00000002 |
9325 | #define smnIOHC_PCIE_CRS_Count_DEFAULT 0x00000000 |
9326 | #define smnIOHC_P2P_CNTL_DEFAULT 0x00000000 |
9327 | #define smnCFG_IOHC_PCI_DEFAULT 0x00000001 |
9328 | #define smnNB_BUS_NUM_CNTL_DEFAULT 0x00000000 |
9329 | #define smnIOHC_AER_CNTL_DEFAULT 0x00000000 |
9330 | #define smnNB_MMIOBASE_DEFAULT 0x00000000 |
9331 | #define smnNB_MMIOLIMIT_DEFAULT 0x00000000 |
9332 | #define smnNB_LOWER_TOP_OF_DRAM2_DEFAULT 0x00000000 |
9333 | #define smnNB_UPPER_TOP_OF_DRAM2_DEFAULT 0x00000000 |
9334 | #define smnNB_LOWER_DRAM2_BASE_DEFAULT 0x00000000 |
9335 | #define smnNB_UPPER_DRAM2_BASE_DEFAULT 0x00000001 |
9336 | #define smnSB_LOCATION_DEFAULT 0x00020001 |
9337 | #define smnIOHC_GLUE_CG_LCLK_CTRL_0_DEFAULT 0xffc00100 |
9338 | #define smnIOHC_GLUE_CG_LCLK_CTRL_1_DEFAULT 0xffc00000 |
9339 | #define smnIOHC_GLUE_CG_LCLK_CTRL_2_DEFAULT 0xffc00000 |
9340 | #define smnIOHC_PERF_CNTL_DEFAULT 0x00000000 |
9341 | #define smnIOHC_PERF_COUNT0_DEFAULT 0x00000000 |
9342 | #define smnIOHC_PERF_COUNT0_UPPER_DEFAULT 0x00000000 |
9343 | #define smnIOHC_PERF_COUNT1_DEFAULT 0x00000000 |
9344 | #define smnIOHC_PERF_COUNT1_UPPER_DEFAULT 0x00000000 |
9345 | #define smnIOHC_PERF_COUNT2_DEFAULT 0x00000000 |
9346 | #define smnIOHC_PERF_COUNT2_UPPER_DEFAULT 0x00000000 |
9347 | #define smnIOHC_PERF_COUNT3_DEFAULT 0x00000000 |
9348 | #define smnIOHC_PERF_COUNT3_UPPER_DEFAULT 0x00000000 |
9349 | #define smnNB_PROG_DEVICE_REMAP_PBr0_DEFAULT 0x00000009 |
9350 | #define smnNB_PROG_DEVICE_REMAP_PBr1_DEFAULT 0x0000000a |
9351 | #define smnNB_PROG_DEVICE_REMAP_PBr2_DEFAULT 0x0000000b |
9352 | #define smnNB_PROG_DEVICE_REMAP_PBr3_DEFAULT 0x0000000c |
9353 | #define smnNB_PROG_DEVICE_REMAP_PBr4_DEFAULT 0x0000000d |
9354 | #define smnNB_PROG_DEVICE_REMAP_PBr5_DEFAULT 0x0000000e |
9355 | #define smnNB_PROG_DEVICE_REMAP_PBr6_DEFAULT 0x0000000f |
9356 | #define smnNB_PROG_DEVICE_REMAP_PBr7_DEFAULT 0x00000041 |
9357 | #define smnNB_PROG_DEVICE_REMAP_PBr8_DEFAULT 0x00000042 |
9358 | #define smnSW_NMI_CNTL_DEFAULT 0x00000000 |
9359 | #define smnSW_SMI_CNTL_DEFAULT 0x00000000 |
9360 | #define smnSW_SCI_CNTL_DEFAULT 0x00000000 |
9361 | #define smnAPML_SW_STATUS_DEFAULT 0x00000000 |
9362 | #define smnIOHC_FEATURE_CNTL_DEFAULT 0x00000003 |
9363 | #define smnSW_GIC_SPI_CNTL_DEFAULT 0x00000000 |
9364 | #define smnIOHC_INTERRUPT_EOI_DEFAULT 0x00000000 |
9365 | #define smnSW_SYNCFLOOD_CNTL_DEFAULT 0x00000000 |
9366 | #define smnIOHC_PIN_CNTL_DEFAULT 0x00000000 |
9367 | #define smnIOHC_INTR_CNTL_DEFAULT 0x0000ff00 |
9368 | #define smnIOHC_FEATURE_CNTL2_DEFAULT 0x00000000 |
9369 | #define smnNB_TOP_OF_DRAM3_DEFAULT 0x00000000 |
9370 | #define smnCAM_CONTROL_DEFAULT 0x00000000 |
9371 | #define smnCAM_TARGET_INDEX_ADDR_BOTTOM_DEFAULT 0x00000000 |
9372 | #define smnCAM_TARGET_INDEX_ADDR_TOP_DEFAULT 0x00000000 |
9373 | #define smnCAM_TARGET_INDEX_DATA_DEFAULT 0x00000000 |
9374 | #define smnCAM_TARGET_INDEX_DATA_MASK_DEFAULT 0x00000000 |
9375 | #define smnCAM_TARGET_DATA_ADDR_BOTTOM_DEFAULT 0x00000000 |
9376 | #define smnCAM_TARGET_DATA_ADDR_TOP_DEFAULT 0x00000000 |
9377 | #define smnCAM_TARGET_DATA_DEFAULT 0x00000000 |
9378 | #define smnCAM_TARGET_DATA_MASK_DEFAULT 0x00000000 |
9379 | #define smnP_DMA_DROPPED_LOG_LOWER_DEFAULT 0x00000000 |
9380 | #define smnP_DMA_DROPPED_LOG_UPPER_DEFAULT 0x00000000 |
9381 | #define smnNP_DMA_DROPPED_LOG_LOWER_DEFAULT 0x00000000 |
9382 | #define smnNP_DMA_DROPPED_LOG_UPPER_DEFAULT 0x00000000 |
9383 | #define smnPCIE_VDM_NODE0_CTRL4_DEFAULT 0x00000000 |
9384 | #define smnPCIE_VDM_CNTL2_DEFAULT 0x00000000 |
9385 | #define smnPCIE_VDM_CNTL3_DEFAULT 0x00000000 |
9386 | #define smnSTALL_CONTROL_XBARPORT0_0_DEFAULT 0x00000000 |
9387 | #define smnSTALL_CONTROL_XBARPORT0_1_DEFAULT 0x00000000 |
9388 | #define smnSTALL_CONTROL_XBARPORT1_0_DEFAULT 0x00000000 |
9389 | #define smnSTALL_CONTROL_XBARPORT1_1_DEFAULT 0x00000000 |
9390 | #define smnSTALL_CONTROL_XBARPORT2_0_DEFAULT 0x00000000 |
9391 | #define smnSTALL_CONTROL_XBARPORT2_1_DEFAULT 0x00000000 |
9392 | #define smnSTALL_CONTROL_XBARPORT3_0_DEFAULT 0x00000000 |
9393 | #define smnSTALL_CONTROL_XBARPORT3_1_DEFAULT 0x00000000 |
9394 | #define smnSTALL_CONTROL_XBARPORT4_0_DEFAULT 0x00000000 |
9395 | #define smnSTALL_CONTROL_XBARPORT4_1_DEFAULT 0x00000000 |
9396 | #define smnNB_DRAM3_BASE_DEFAULT 0x00040000 |
9397 | #define smnPSP_BASE_ADDR_LO_DEFAULT 0x00000000 |
9398 | #define smnPSP_BASE_ADDR_HI_DEFAULT 0x00000000 |
9399 | #define smnSMU_BASE_ADDR_LO_DEFAULT 0x00000000 |
9400 | #define smnSMU_BASE_ADDR_HI_DEFAULT 0x00000000 |
9401 | #define smnIOAPIC_BASE_ADDR_LO_DEFAULT 0xfec00000 |
9402 | #define smnIOAPIC_BASE_ADDR_HI_DEFAULT 0x00000000 |
9403 | #define smnFASTREG_BASE_ADDR_LO_DEFAULT 0x00000000 |
9404 | #define smnFASTREG_BASE_ADDR_HI_DEFAULT 0x00000000 |
9405 | #define smnFASTREGCNTL_BASE_ADDR_LO_DEFAULT 0x00000000 |
9406 | #define smnFASTREGCNTL_BASE_ADDR_HI_DEFAULT 0x00000000 |
9407 | #define smnSMMU_BASE_ADDR_LO_DEFAULT 0x00000000 |
9408 | #define smnSMMU_BASE_ADDR_HI_DEFAULT 0x00000000 |
9409 | #define smnIOHC_PGMST_CNTL_DEFAULT 0x0000000f |
9410 | #define smnIOHC_SDP_PORT_CONTROL_DEFAULT 0x00000c8f |
9411 | #define smnIOHC_SDP_PARITY_CONTROL_DEFAULT 0x00000000 |
9412 | #define smnIOHC_PGSLV_CNTL_DEFAULT 0x00000004 |
9413 | #define smnSCRATCH_4_DEFAULT 0x00000000 |
9414 | #define smnSCRATCH_5_DEFAULT 0x00000000 |
9415 | #define smnSMU_BLOCK_CPU_DEFAULT 0x00000000 |
9416 | #define smnSMU_BLOCK_CPU_STATUS_DEFAULT 0x00000000 |
9417 | #define smnTRAP_STATUS_DEFAULT 0x00000000 |
9418 | #define smnTRAP_REQUEST0_DEFAULT 0x00000000 |
9419 | #define smnTRAP_REQUEST1_DEFAULT 0x00000000 |
9420 | #define smnTRAP_REQUEST2_DEFAULT 0x00000000 |
9421 | #define smnTRAP_REQUEST3_DEFAULT 0x00000000 |
9422 | #define smnTRAP_REQUEST4_DEFAULT 0x00000000 |
9423 | #define smnTRAP_REQUEST5_DEFAULT 0x00000000 |
9424 | #define smnTRAP_REQUEST_DATASTRB0_DEFAULT 0x00000000 |
9425 | #define smnTRAP_REQUEST_DATASTRB1_DEFAULT 0x00000000 |
9426 | #define smnTRAP_REQUEST_DATA0_DEFAULT 0x00000000 |
9427 | #define smnTRAP_REQUEST_DATA1_DEFAULT 0x00000000 |
9428 | #define smnTRAP_REQUEST_DATA2_DEFAULT 0x00000000 |
9429 | #define smnTRAP_REQUEST_DATA3_DEFAULT 0x00000000 |
9430 | #define smnTRAP_REQUEST_DATA4_DEFAULT 0x00000000 |
9431 | #define smnTRAP_REQUEST_DATA5_DEFAULT 0x00000000 |
9432 | #define smnTRAP_REQUEST_DATA6_DEFAULT 0x00000000 |
9433 | #define smnTRAP_REQUEST_DATA7_DEFAULT 0x00000000 |
9434 | #define smnTRAP_REQUEST_DATA8_DEFAULT 0x00000000 |
9435 | #define smnTRAP_REQUEST_DATA9_DEFAULT 0x00000000 |
9436 | #define smnTRAP_REQUEST_DATA10_DEFAULT 0x00000000 |
9437 | #define smnTRAP_REQUEST_DATA11_DEFAULT 0x00000000 |
9438 | #define smnTRAP_REQUEST_DATA12_DEFAULT 0x00000000 |
9439 | #define smnTRAP_REQUEST_DATA13_DEFAULT 0x00000000 |
9440 | #define smnTRAP_REQUEST_DATA14_DEFAULT 0x00000000 |
9441 | #define smnTRAP_REQUEST_DATA15_DEFAULT 0x00000000 |
9442 | #define smnTRAP_RESPONSE_CONTROL_DEFAULT 0x00000000 |
9443 | #define smnTRAP_RESPONSE0_DEFAULT 0x00000000 |
9444 | #define smnTRAP_RESPONSE_DATA0_DEFAULT 0x00000000 |
9445 | #define smnTRAP_RESPONSE_DATA1_DEFAULT 0x00000000 |
9446 | #define smnTRAP_RESPONSE_DATA2_DEFAULT 0x00000000 |
9447 | #define smnTRAP_RESPONSE_DATA3_DEFAULT 0x00000000 |
9448 | #define smnTRAP_RESPONSE_DATA4_DEFAULT 0x00000000 |
9449 | #define smnTRAP_RESPONSE_DATA5_DEFAULT 0x00000000 |
9450 | #define smnTRAP_RESPONSE_DATA6_DEFAULT 0x00000000 |
9451 | #define smnTRAP_RESPONSE_DATA7_DEFAULT 0x00000000 |
9452 | #define smnTRAP_RESPONSE_DATA8_DEFAULT 0x00000000 |
9453 | #define smnTRAP_RESPONSE_DATA9_DEFAULT 0x00000000 |
9454 | #define smnTRAP_RESPONSE_DATA10_DEFAULT 0x00000000 |
9455 | #define smnTRAP_RESPONSE_DATA11_DEFAULT 0x00000000 |
9456 | #define smnTRAP_RESPONSE_DATA12_DEFAULT 0x00000000 |
9457 | #define smnTRAP_RESPONSE_DATA13_DEFAULT 0x00000000 |
9458 | #define smnTRAP_RESPONSE_DATA14_DEFAULT 0x00000000 |
9459 | #define smnTRAP_RESPONSE_DATA15_DEFAULT 0x00000000 |
9460 | #define smnTRAP0_CONTROL0_DEFAULT 0x00000000 |
9461 | #define smnTRAP0_ADDRESS_LO_DEFAULT 0x00000000 |
9462 | #define smnTRAP0_ADDRESS_HI_DEFAULT 0x00000000 |
9463 | #define smnTRAP0_COMMAND_DEFAULT 0x00000000 |
9464 | #define smnTRAP0_ADDRESS_LO_MASK_DEFAULT 0x00000000 |
9465 | #define smnTRAP0_ADDRESS_HI_MASK_DEFAULT 0x00000000 |
9466 | #define smnTRAP0_COMMAND_MASK_DEFAULT 0x00000000 |
9467 | #define smnTRAP1_CONTROL0_DEFAULT 0x00000000 |
9468 | #define smnTRAP1_ADDRESS_LO_DEFAULT 0x00000000 |
9469 | #define smnTRAP1_ADDRESS_HI_DEFAULT 0x00000000 |
9470 | #define smnTRAP1_COMMAND_DEFAULT 0x00000000 |
9471 | #define smnTRAP1_ADDRESS_LO_MASK_DEFAULT 0x00000000 |
9472 | #define smnTRAP1_ADDRESS_HI_MASK_DEFAULT 0x00000000 |
9473 | #define smnTRAP1_COMMAND_MASK_DEFAULT 0x00000000 |
9474 | #define smnTRAP2_CONTROL0_DEFAULT 0x00000000 |
9475 | #define smnTRAP2_ADDRESS_LO_DEFAULT 0x00000000 |
9476 | #define smnTRAP2_ADDRESS_HI_DEFAULT 0x00000000 |
9477 | #define smnTRAP2_COMMAND_DEFAULT 0x00000000 |
9478 | #define smnTRAP2_ADDRESS_LO_MASK_DEFAULT 0x00000000 |
9479 | #define smnTRAP2_ADDRESS_HI_MASK_DEFAULT 0x00000000 |
9480 | #define smnTRAP2_COMMAND_MASK_DEFAULT 0x00000000 |
9481 | #define smnTRAP3_CONTROL0_DEFAULT 0x00000000 |
9482 | #define smnTRAP3_ADDRESS_LO_DEFAULT 0x00000000 |
9483 | #define smnTRAP3_ADDRESS_HI_DEFAULT 0x00000000 |
9484 | #define smnTRAP3_COMMAND_DEFAULT 0x00000000 |
9485 | #define smnTRAP3_ADDRESS_LO_MASK_DEFAULT 0x00000000 |
9486 | #define smnTRAP3_ADDRESS_HI_MASK_DEFAULT 0x00000000 |
9487 | #define smnTRAP3_COMMAND_MASK_DEFAULT 0x00000000 |
9488 | #define smnTRAP4_CONTROL0_DEFAULT 0x00000000 |
9489 | #define smnTRAP4_ADDRESS_LO_DEFAULT 0x00000000 |
9490 | #define smnTRAP4_ADDRESS_HI_DEFAULT 0x00000000 |
9491 | #define smnTRAP4_COMMAND_DEFAULT 0x00000000 |
9492 | #define smnTRAP4_ADDRESS_LO_MASK_DEFAULT 0x00000000 |
9493 | #define smnTRAP4_ADDRESS_HI_MASK_DEFAULT 0x00000000 |
9494 | #define smnTRAP4_COMMAND_MASK_DEFAULT 0x00000000 |
9495 | #define smnTRAP5_CONTROL0_DEFAULT 0x00000000 |
9496 | #define smnTRAP5_ADDRESS_LO_DEFAULT 0x00000000 |
9497 | #define smnTRAP5_ADDRESS_HI_DEFAULT 0x00000000 |
9498 | #define smnTRAP5_COMMAND_DEFAULT 0x00000000 |
9499 | #define smnTRAP5_ADDRESS_LO_MASK_DEFAULT 0x00000000 |
9500 | #define smnTRAP5_ADDRESS_HI_MASK_DEFAULT 0x00000000 |
9501 | #define smnTRAP5_COMMAND_MASK_DEFAULT 0x00000000 |
9502 | #define smnTRAP6_CONTROL0_DEFAULT 0x00000000 |
9503 | #define smnTRAP6_ADDRESS_LO_DEFAULT 0x00000000 |
9504 | #define smnTRAP6_ADDRESS_HI_DEFAULT 0x00000000 |
9505 | #define smnTRAP6_COMMAND_DEFAULT 0x00000000 |
9506 | #define smnTRAP6_ADDRESS_LO_MASK_DEFAULT 0x00000000 |
9507 | #define smnTRAP6_ADDRESS_HI_MASK_DEFAULT 0x00000000 |
9508 | #define smnTRAP6_COMMAND_MASK_DEFAULT 0x00000000 |
9509 | #define smnTRAP7_CONTROL0_DEFAULT 0x00000000 |
9510 | #define smnTRAP7_ADDRESS_LO_DEFAULT 0x00000000 |
9511 | #define smnTRAP7_ADDRESS_HI_DEFAULT 0x00000000 |
9512 | #define smnTRAP7_COMMAND_DEFAULT 0x00000000 |
9513 | #define smnTRAP7_ADDRESS_LO_MASK_DEFAULT 0x00000000 |
9514 | #define smnTRAP7_ADDRESS_HI_MASK_DEFAULT 0x00000000 |
9515 | #define smnTRAP7_COMMAND_MASK_DEFAULT 0x00000000 |
9516 | #define smnTRAP8_CONTROL0_DEFAULT 0x00000000 |
9517 | #define smnTRAP8_ADDRESS_LO_DEFAULT 0x00000000 |
9518 | #define smnTRAP8_ADDRESS_HI_DEFAULT 0x00000000 |
9519 | #define smnTRAP8_COMMAND_DEFAULT 0x00000000 |
9520 | #define smnTRAP8_ADDRESS_LO_MASK_DEFAULT 0x00000000 |
9521 | #define smnTRAP8_ADDRESS_HI_MASK_DEFAULT 0x00000000 |
9522 | #define smnTRAP8_COMMAND_MASK_DEFAULT 0x00000000 |
9523 | #define smnTRAP9_CONTROL0_DEFAULT 0x00000000 |
9524 | #define smnTRAP9_ADDRESS_LO_DEFAULT 0x00000000 |
9525 | #define smnTRAP9_ADDRESS_HI_DEFAULT 0x00000000 |
9526 | #define smnTRAP9_COMMAND_DEFAULT 0x00000000 |
9527 | #define smnTRAP9_ADDRESS_LO_MASK_DEFAULT 0x00000000 |
9528 | #define smnTRAP9_ADDRESS_HI_MASK_DEFAULT 0x00000000 |
9529 | #define smnTRAP9_COMMAND_MASK_DEFAULT 0x00000000 |
9530 | #define smnTRAP10_CONTROL0_DEFAULT 0x00000000 |
9531 | #define smnTRAP10_ADDRESS_LO_DEFAULT 0x00000000 |
9532 | #define smnTRAP10_ADDRESS_HI_DEFAULT 0x00000000 |
9533 | #define smnTRAP10_COMMAND_DEFAULT 0x00000000 |
9534 | #define smnTRAP10_ADDRESS_LO_MASK_DEFAULT 0x00000000 |
9535 | #define smnTRAP10_ADDRESS_HI_MASK_DEFAULT 0x00000000 |
9536 | #define smnTRAP10_COMMAND_MASK_DEFAULT 0x00000000 |
9537 | #define smnTRAP11_CONTROL0_DEFAULT 0x00000000 |
9538 | #define smnTRAP11_ADDRESS_LO_DEFAULT 0x00000000 |
9539 | #define smnTRAP11_ADDRESS_HI_DEFAULT 0x00000000 |
9540 | #define smnTRAP11_COMMAND_DEFAULT 0x00000000 |
9541 | #define smnTRAP11_ADDRESS_LO_MASK_DEFAULT 0x00000000 |
9542 | #define smnTRAP11_ADDRESS_HI_MASK_DEFAULT 0x00000000 |
9543 | #define smnTRAP11_COMMAND_MASK_DEFAULT 0x00000000 |
9544 | #define smnTRAP12_CONTROL0_DEFAULT 0x00000000 |
9545 | #define smnTRAP12_ADDRESS_LO_DEFAULT 0x00000000 |
9546 | #define smnTRAP12_ADDRESS_HI_DEFAULT 0x00000000 |
9547 | #define smnTRAP12_COMMAND_DEFAULT 0x00000000 |
9548 | #define smnTRAP12_ADDRESS_LO_MASK_DEFAULT 0x00000000 |
9549 | #define smnTRAP12_ADDRESS_HI_MASK_DEFAULT 0x00000000 |
9550 | #define smnTRAP12_COMMAND_MASK_DEFAULT 0x00000000 |
9551 | #define smnTRAP13_CONTROL0_DEFAULT 0x00000000 |
9552 | #define smnTRAP13_ADDRESS_LO_DEFAULT 0x00000000 |
9553 | #define smnTRAP13_ADDRESS_HI_DEFAULT 0x00000000 |
9554 | #define smnTRAP13_COMMAND_DEFAULT 0x00000000 |
9555 | #define smnTRAP13_ADDRESS_LO_MASK_DEFAULT 0x00000000 |
9556 | #define smnTRAP13_ADDRESS_HI_MASK_DEFAULT 0x00000000 |
9557 | #define smnTRAP13_COMMAND_MASK_DEFAULT 0x00000000 |
9558 | #define smnTRAP14_CONTROL0_DEFAULT 0x00000000 |
9559 | #define smnTRAP14_ADDRESS_LO_DEFAULT 0x00000000 |
9560 | #define smnTRAP14_ADDRESS_HI_DEFAULT 0x00000000 |
9561 | #define smnTRAP14_COMMAND_DEFAULT 0x00000000 |
9562 | #define smnTRAP14_ADDRESS_LO_MASK_DEFAULT 0x00000000 |
9563 | #define smnTRAP14_ADDRESS_HI_MASK_DEFAULT 0x00000000 |
9564 | #define smnTRAP14_COMMAND_MASK_DEFAULT 0x00000000 |
9565 | #define smnTRAP15_CONTROL0_DEFAULT 0x00000000 |
9566 | #define smnTRAP15_ADDRESS_LO_DEFAULT 0x00000000 |
9567 | #define smnTRAP15_ADDRESS_HI_DEFAULT 0x00000000 |
9568 | #define smnTRAP15_COMMAND_DEFAULT 0x00000000 |
9569 | #define smnTRAP15_ADDRESS_LO_MASK_DEFAULT 0x00000000 |
9570 | #define smnTRAP15_ADDRESS_HI_MASK_DEFAULT 0x00000000 |
9571 | #define smnTRAP15_COMMAND_MASK_DEFAULT 0x00000000 |
9572 | #define smnIOHC_REQDECODE_OVERRIDE_DEFAULT 0x00000000 |
9573 | #define smnIOHC_RSPDECODE_OVERRIDE_DEFAULT 0x00000000 |
9574 | #define smnIOHC_RSPPASSPW_OVERRIDE_DEFAULT 0x00000000 |
9575 | #define smnIOHC_USERBIT_BYPASS_DEFAULT 0x00000000 |
9576 | #define smnIOHC_SMN_MASTER_CNTL_DEFAULT 0x00000000 |
9577 | #define smnIOHC_SMN_MASTER_STATUS_DEFAULT 0x00000000 |
9578 | #define smnSB_COMMAND_DEFAULT 0x00000000 |
9579 | #define smnSB_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 |
9580 | #define smnSB_IO_BASE_LIMIT_DEFAULT 0x00000000 |
9581 | #define smnSB_MEM_BASE_LIMIT_DEFAULT 0x00000000 |
9582 | #define smnSB_PREF_BASE_LIMIT_DEFAULT 0x00000000 |
9583 | #define smnSB_PREF_BASE_UPPER_DEFAULT 0x00000000 |
9584 | #define smnSB_PREF_LIMIT_UPPER_DEFAULT 0x00000000 |
9585 | #define smnSB_IO_BASE_LIMIT_HI_DEFAULT 0x00000000 |
9586 | #define smnSB_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000 |
9587 | #define smnSB_EXT_BRIDGE_CNTL_DEFAULT 0x00000000 |
9588 | #define smnSB_PMI_STATUS_CNTL_DEFAULT 0x00000000 |
9589 | #define smnSB_SLOT_CAP_DEFAULT 0x00000000 |
9590 | #define smnSB_ROOT_CNTL_DEFAULT 0x00000000 |
9591 | #define smnSB_DEVICE_CNTL2_DEFAULT 0x00000000 |
9592 | #define smnIOHC_QOS_CONTROL_DEFAULT 0x00000000 |
9593 | #define smnUSB_QoS_CNTL_DEFAULT 0x00000000 |
9594 | #define smnIOHC_SION_S0_Client0_Req_BurstTarget_Lower_DEFAULT 0x00000000 |
9595 | #define smnIOHC_SION_S0_Client0_Req_BurstTarget_Upper_DEFAULT 0x00000000 |
9596 | #define smnIOHC_SION_S0_Client0_Req_TimeSlot_Lower_DEFAULT 0x00000000 |
9597 | #define smnIOHC_SION_S0_Client0_Req_TimeSlot_Upper_DEFAULT 0x00000000 |
9598 | #define smnIOHC_SION_S0_Client0_RdRsp_BurstTarget_Lower_DEFAULT 0x02020202 |
9599 | #define smnIOHC_SION_S0_Client0_RdRsp_BurstTarget_Upper_DEFAULT 0x02020202 |
9600 | #define smnIOHC_SION_S0_Client0_RdRsp_TimeSlot_Lower_DEFAULT 0x00000000 |
9601 | #define smnIOHC_SION_S0_Client0_RdRsp_TimeSlot_Upper_DEFAULT 0x00000000 |
9602 | #define smnIOHC_SION_S0_Client0_WrRsp_BurstTarget_Lower_DEFAULT 0x00000000 |
9603 | #define smnIOHC_SION_S0_Client0_WrRsp_BurstTarget_Upper_DEFAULT 0x00000000 |
9604 | #define smnIOHC_SION_S0_Client0_WrRsp_TimeSlot_Lower_DEFAULT 0x00000000 |
9605 | #define smnIOHC_SION_S0_Client0_WrRsp_TimeSlot_Upper_DEFAULT 0x00000000 |
9606 | #define smnIOHC_SION_S1_Client0_Req_BurstTarget_Lower_DEFAULT 0x00000000 |
9607 | #define smnIOHC_SION_S1_Client0_Req_BurstTarget_Upper_DEFAULT 0x00000000 |
9608 | #define smnIOHC_SION_S1_Client0_Req_TimeSlot_Lower_DEFAULT 0x00000000 |
9609 | #define smnIOHC_SION_S1_Client0_Req_TimeSlot_Upper_DEFAULT 0x00000000 |
9610 | #define smnIOHC_SION_S1_Client0_RdRsp_BurstTarget_Lower_DEFAULT 0x02020202 |
9611 | #define smnIOHC_SION_S1_Client0_RdRsp_BurstTarget_Upper_DEFAULT 0x02020202 |
9612 | #define smnIOHC_SION_S1_Client0_RdRsp_TimeSlot_Lower_DEFAULT 0x00000000 |
9613 | #define smnIOHC_SION_S1_Client0_RdRsp_TimeSlot_Upper_DEFAULT 0x00000000 |
9614 | #define smnIOHC_SION_S1_Client0_WrRsp_BurstTarget_Lower_DEFAULT 0x00000000 |
9615 | #define smnIOHC_SION_S1_Client0_WrRsp_BurstTarget_Upper_DEFAULT 0x00000000 |
9616 | #define smnIOHC_SION_S1_Client0_WrRsp_TimeSlot_Lower_DEFAULT 0x00000000 |
9617 | #define smnIOHC_SION_S1_Client0_WrRsp_TimeSlot_Upper_DEFAULT 0x00000000 |
9618 | #define smnIOHC_SION_Client0_ReqPoolCredit_Alloc_Lower_DEFAULT 0x01000101 |
9619 | #define smnIOHC_SION_Client0_ReqPoolCredit_Alloc_Upper_DEFAULT 0x01000001 |
9620 | #define smnIOHC_SION_Client0_DataPoolCredit_Alloc_Lower_DEFAULT 0x01000101 |
9621 | #define smnIOHC_SION_Client0_DataPoolCredit_Alloc_Upper_DEFAULT 0x01000001 |
9622 | #define smnIOHC_SION_Client0_RdRspPoolCredit_Alloc_Lower_DEFAULT 0x00000001 |
9623 | #define smnIOHC_SION_Client0_RdRspPoolCredit_Alloc_Upper_DEFAULT 0x00000000 |
9624 | #define smnIOHC_SION_Client0_WrRspPoolCredit_Alloc_Lower_DEFAULT 0x00010101 |
9625 | #define smnIOHC_SION_Client0_WrRspPoolCredit_Alloc_Upper_DEFAULT 0x00000000 |
9626 | #define smnIOHC_SION_S0_Client1_Req_BurstTarget_Lower_DEFAULT 0x00000000 |
9627 | #define smnIOHC_SION_S0_Client1_Req_BurstTarget_Upper_DEFAULT 0x00000000 |
9628 | #define smnIOHC_SION_S0_Client1_Req_TimeSlot_Lower_DEFAULT 0x00000000 |
9629 | #define smnIOHC_SION_S0_Client1_Req_TimeSlot_Upper_DEFAULT 0x00000000 |
9630 | #define smnIOHC_SION_S0_Client1_RdRsp_BurstTarget_Lower_DEFAULT 0x02020202 |
9631 | #define smnIOHC_SION_S0_Client1_RdRsp_BurstTarget_Upper_DEFAULT 0x02020202 |
9632 | #define smnIOHC_SION_S0_Client1_RdRsp_TimeSlot_Lower_DEFAULT 0x00000000 |
9633 | #define smnIOHC_SION_S0_Client1_RdRsp_TimeSlot_Upper_DEFAULT 0x00000000 |
9634 | #define smnIOHC_SION_S0_Client1_WrRsp_BurstTarget_Lower_DEFAULT 0x00000000 |
9635 | #define smnIOHC_SION_S0_Client1_WrRsp_BurstTarget_Upper_DEFAULT 0x00000000 |
9636 | #define smnIOHC_SION_S0_Client1_WrRsp_TimeSlot_Lower_DEFAULT 0x00000000 |
9637 | #define smnIOHC_SION_S0_Client1_WrRsp_TimeSlot_Upper_DEFAULT 0x00000000 |
9638 | #define smnIOHC_SION_S1_Client1_Req_BurstTarget_Lower_DEFAULT 0x00000000 |
9639 | #define smnIOHC_SION_S1_Client1_Req_BurstTarget_Upper_DEFAULT 0x00000000 |
9640 | #define smnIOHC_SION_S1_Client1_Req_TimeSlot_Lower_DEFAULT 0x00000000 |
9641 | #define smnIOHC_SION_S1_Client1_Req_TimeSlot_Upper_DEFAULT 0x00000000 |
9642 | #define smnIOHC_SION_S1_Client1_RdRsp_BurstTarget_Lower_DEFAULT 0x02020202 |
9643 | #define smnIOHC_SION_S1_Client1_RdRsp_BurstTarget_Upper_DEFAULT 0x02020202 |
9644 | #define smnIOHC_SION_S1_Client1_RdRsp_TimeSlot_Lower_DEFAULT 0x00000000 |
9645 | #define smnIOHC_SION_S1_Client1_RdRsp_TimeSlot_Upper_DEFAULT 0x00000000 |
9646 | #define smnIOHC_SION_S1_Client1_WrRsp_BurstTarget_Lower_DEFAULT 0x00000000 |
9647 | #define smnIOHC_SION_S1_Client1_WrRsp_BurstTarget_Upper_DEFAULT 0x00000000 |
9648 | #define smnIOHC_SION_S1_Client1_WrRsp_TimeSlot_Lower_DEFAULT 0x00000000 |
9649 | #define smnIOHC_SION_S1_Client1_WrRsp_TimeSlot_Upper_DEFAULT 0x00000000 |
9650 | #define smnIOHC_SION_Client1_ReqPoolCredit_Alloc_Lower_DEFAULT 0x01010101 |
9651 | #define smnIOHC_SION_Client1_ReqPoolCredit_Alloc_Upper_DEFAULT 0x01010101 |
9652 | #define smnIOHC_SION_Client1_DataPoolCredit_Alloc_Lower_DEFAULT 0x02020202 |
9653 | #define smnIOHC_SION_Client1_DataPoolCredit_Alloc_Upper_DEFAULT 0x02020202 |
9654 | #define smnIOHC_SION_Client1_RdRspPoolCredit_Alloc_Lower_DEFAULT 0x00000001 |
9655 | #define smnIOHC_SION_Client1_RdRspPoolCredit_Alloc_Upper_DEFAULT 0x01010101 |
9656 | #define smnIOHC_SION_Client1_WrRspPoolCredit_Alloc_Lower_DEFAULT 0x01010101 |
9657 | #define smnIOHC_SION_Client1_WrRspPoolCredit_Alloc_Upper_DEFAULT 0x01010101 |
9658 | #define smnIOHC_SION_S0_Client2_Req_BurstTarget_Lower_DEFAULT 0x00000000 |
9659 | #define smnIOHC_SION_S0_Client2_Req_BurstTarget_Upper_DEFAULT 0x00000000 |
9660 | #define smnIOHC_SION_S0_Client2_Req_TimeSlot_Lower_DEFAULT 0x00000000 |
9661 | #define smnIOHC_SION_S0_Client2_Req_TimeSlot_Upper_DEFAULT 0x00000000 |
9662 | #define smnIOHC_SION_S0_Client2_RdRsp_BurstTarget_Lower_DEFAULT 0x02020202 |
9663 | #define smnIOHC_SION_S0_Client2_RdRsp_BurstTarget_Upper_DEFAULT 0x02020202 |
9664 | #define smnIOHC_SION_S0_Client2_RdRsp_TimeSlot_Lower_DEFAULT 0x00000000 |
9665 | #define smnIOHC_SION_S0_Client2_RdRsp_TimeSlot_Upper_DEFAULT 0x00000000 |
9666 | #define smnIOHC_SION_S0_Client2_WrRsp_BurstTarget_Lower_DEFAULT 0x00000000 |
9667 | #define smnIOHC_SION_S0_Client2_WrRsp_BurstTarget_Upper_DEFAULT 0x00000000 |
9668 | #define smnIOHC_SION_S0_Client2_WrRsp_TimeSlot_Lower_DEFAULT 0x00000000 |
9669 | #define smnIOHC_SION_S0_Client2_WrRsp_TimeSlot_Upper_DEFAULT 0x00000000 |
9670 | #define smnIOHC_SION_S1_Client2_Req_BurstTarget_Lower_DEFAULT 0x00000000 |
9671 | #define smnIOHC_SION_S1_Client2_Req_BurstTarget_Upper_DEFAULT 0x00000000 |
9672 | #define smnIOHC_SION_S1_Client2_Req_TimeSlot_Lower_DEFAULT 0x00000000 |
9673 | #define smnIOHC_SION_S1_Client2_Req_TimeSlot_Upper_DEFAULT 0x00000000 |
9674 | #define smnIOHC_SION_S1_Client2_RdRsp_BurstTarget_Lower_DEFAULT 0x02020202 |
9675 | #define smnIOHC_SION_S1_Client2_RdRsp_BurstTarget_Upper_DEFAULT 0x02020202 |
9676 | #define smnIOHC_SION_S1_Client2_RdRsp_TimeSlot_Lower_DEFAULT 0x00000000 |
9677 | #define smnIOHC_SION_S1_Client2_RdRsp_TimeSlot_Upper_DEFAULT 0x00000000 |
9678 | #define smnIOHC_SION_S1_Client2_WrRsp_BurstTarget_Lower_DEFAULT 0x00000000 |
9679 | #define smnIOHC_SION_S1_Client2_WrRsp_BurstTarget_Upper_DEFAULT 0x00000000 |
9680 | #define smnIOHC_SION_S1_Client2_WrRsp_TimeSlot_Lower_DEFAULT 0x00000000 |
9681 | #define smnIOHC_SION_S1_Client2_WrRsp_TimeSlot_Upper_DEFAULT 0x00000000 |
9682 | #define smnIOHC_SION_Client2_ReqPoolCredit_Alloc_Lower_DEFAULT 0x01010101 |
9683 | #define smnIOHC_SION_Client2_ReqPoolCredit_Alloc_Upper_DEFAULT 0x01010101 |
9684 | #define smnIOHC_SION_Client2_DataPoolCredit_Alloc_Lower_DEFAULT 0x02020202 |
9685 | #define smnIOHC_SION_Client2_DataPoolCredit_Alloc_Upper_DEFAULT 0x02020202 |
9686 | #define smnIOHC_SION_Client2_RdRspPoolCredit_Alloc_Lower_DEFAULT 0x00000001 |
9687 | #define smnIOHC_SION_Client2_RdRspPoolCredit_Alloc_Upper_DEFAULT 0x01010101 |
9688 | #define smnIOHC_SION_Client2_WrRspPoolCredit_Alloc_Lower_DEFAULT 0x01010101 |
9689 | #define smnIOHC_SION_Client2_WrRspPoolCredit_Alloc_Upper_DEFAULT 0x01010101 |
9690 | #define smnIOHC_SION_S0_Client3_Req_BurstTarget_Lower_DEFAULT 0x00000000 |
9691 | #define smnIOHC_SION_S0_Client3_Req_BurstTarget_Upper_DEFAULT 0x00000000 |
9692 | #define smnIOHC_SION_S0_Client3_Req_TimeSlot_Lower_DEFAULT 0x00000000 |
9693 | #define smnIOHC_SION_S0_Client3_Req_TimeSlot_Upper_DEFAULT 0x00000000 |
9694 | #define smnIOHC_SION_S0_Client3_RdRsp_BurstTarget_Lower_DEFAULT 0x02020202 |
9695 | #define smnIOHC_SION_S0_Client3_RdRsp_BurstTarget_Upper_DEFAULT 0x02020202 |
9696 | #define smnIOHC_SION_S0_Client3_RdRsp_TimeSlot_Lower_DEFAULT 0x00000000 |
9697 | #define smnIOHC_SION_S0_Client3_RdRsp_TimeSlot_Upper_DEFAULT 0x00000000 |
9698 | #define smnIOHC_SION_S0_Client3_WrRsp_BurstTarget_Lower_DEFAULT 0x00000000 |
9699 | #define smnIOHC_SION_S0_Client3_WrRsp_BurstTarget_Upper_DEFAULT 0x00000000 |
9700 | #define smnIOHC_SION_S0_Client3_WrRsp_TimeSlot_Lower_DEFAULT 0x00000000 |
9701 | #define smnIOHC_SION_S0_Client3_WrRsp_TimeSlot_Upper_DEFAULT 0x00000000 |
9702 | #define smnIOHC_SION_S1_Client3_Req_BurstTarget_Lower_DEFAULT 0x00000000 |
9703 | #define smnIOHC_SION_S1_Client3_Req_BurstTarget_Upper_DEFAULT 0x00000000 |
9704 | #define smnIOHC_SION_S1_Client3_Req_TimeSlot_Lower_DEFAULT 0x00000000 |
9705 | #define smnIOHC_SION_S1_Client3_Req_TimeSlot_Upper_DEFAULT 0x00000000 |
9706 | #define smnIOHC_SION_S1_Client3_RdRsp_BurstTarget_Lower_DEFAULT 0x02020202 |
9707 | #define smnIOHC_SION_S1_Client3_RdRsp_BurstTarget_Upper_DEFAULT 0x02020202 |
9708 | #define smnIOHC_SION_S1_Client3_RdRsp_TimeSlot_Lower_DEFAULT 0x00000000 |
9709 | #define smnIOHC_SION_S1_Client3_RdRsp_TimeSlot_Upper_DEFAULT 0x00000000 |
9710 | #define smnIOHC_SION_S1_Client3_WrRsp_BurstTarget_Lower_DEFAULT 0x00000000 |
9711 | #define smnIOHC_SION_S1_Client3_WrRsp_BurstTarget_Upper_DEFAULT 0x00000000 |
9712 | #define smnIOHC_SION_S1_Client3_WrRsp_TimeSlot_Lower_DEFAULT 0x00000000 |
9713 | #define smnIOHC_SION_S1_Client3_WrRsp_TimeSlot_Upper_DEFAULT 0x00000000 |
9714 | #define smnIOHC_SION_Client3_ReqPoolCredit_Alloc_Lower_DEFAULT 0x01010101 |
9715 | #define smnIOHC_SION_Client3_ReqPoolCredit_Alloc_Upper_DEFAULT 0x01010101 |
9716 | #define smnIOHC_SION_Client3_DataPoolCredit_Alloc_Lower_DEFAULT 0x02020202 |
9717 | #define smnIOHC_SION_Client3_DataPoolCredit_Alloc_Upper_DEFAULT 0x02020202 |
9718 | #define smnIOHC_SION_Client3_RdRspPoolCredit_Alloc_Lower_DEFAULT 0x00000001 |
9719 | #define smnIOHC_SION_Client3_RdRspPoolCredit_Alloc_Upper_DEFAULT 0x01010101 |
9720 | #define smnIOHC_SION_Client3_WrRspPoolCredit_Alloc_Lower_DEFAULT 0x01010101 |
9721 | #define smnIOHC_SION_Client3_WrRspPoolCredit_Alloc_Upper_DEFAULT 0x01010101 |
9722 | #define smnIOHC_SION_S0_Client4_Req_BurstTarget_Lower_DEFAULT 0x00000000 |
9723 | #define smnIOHC_SION_S0_Client4_Req_BurstTarget_Upper_DEFAULT 0x00000000 |
9724 | #define smnIOHC_SION_S0_Client4_Req_TimeSlot_Lower_DEFAULT 0x00000000 |
9725 | #define smnIOHC_SION_S0_Client4_Req_TimeSlot_Upper_DEFAULT 0x00000000 |
9726 | #define smnIOHC_SION_S0_Client4_RdRsp_BurstTarget_Lower_DEFAULT 0x02020202 |
9727 | #define smnIOHC_SION_S0_Client4_RdRsp_BurstTarget_Upper_DEFAULT 0x02020202 |
9728 | #define smnIOHC_SION_S0_Client4_RdRsp_TimeSlot_Lower_DEFAULT 0x00000000 |
9729 | #define smnIOHC_SION_S0_Client4_RdRsp_TimeSlot_Upper_DEFAULT 0x00000000 |
9730 | #define smnIOHC_SION_S0_Client4_WrRsp_BurstTarget_Lower_DEFAULT 0x00000000 |
9731 | #define smnIOHC_SION_S0_Client4_WrRsp_BurstTarget_Upper_DEFAULT 0x00000000 |
9732 | #define smnIOHC_SION_S0_Client4_WrRsp_TimeSlot_Lower_DEFAULT 0x00000000 |
9733 | #define smnIOHC_SION_S0_Client4_WrRsp_TimeSlot_Upper_DEFAULT 0x00000000 |
9734 | #define smnIOHC_SION_S1_Client4_Req_BurstTarget_Lower_DEFAULT 0x00000000 |
9735 | #define smnIOHC_SION_S1_Client4_Req_BurstTarget_Upper_DEFAULT 0x00000000 |
9736 | #define smnIOHC_SION_S1_Client4_Req_TimeSlot_Lower_DEFAULT 0x00000000 |
9737 | #define smnIOHC_SION_S1_Client4_Req_TimeSlot_Upper_DEFAULT 0x00000000 |
9738 | #define smnIOHC_SION_S1_Client4_RdRsp_BurstTarget_Lower_DEFAULT 0x02020202 |
9739 | #define smnIOHC_SION_S1_Client4_RdRsp_BurstTarget_Upper_DEFAULT 0x02020202 |
9740 | #define smnIOHC_SION_S1_Client4_RdRsp_TimeSlot_Lower_DEFAULT 0x00000000 |
9741 | #define smnIOHC_SION_S1_Client4_RdRsp_TimeSlot_Upper_DEFAULT 0x00000000 |
9742 | #define smnIOHC_SION_S1_Client4_WrRsp_BurstTarget_Lower_DEFAULT 0x00000000 |
9743 | #define smnIOHC_SION_S1_Client4_WrRsp_BurstTarget_Upper_DEFAULT 0x00000000 |
9744 | #define smnIOHC_SION_S1_Client4_WrRsp_TimeSlot_Lower_DEFAULT 0x00000000 |
9745 | #define smnIOHC_SION_S1_Client4_WrRsp_TimeSlot_Upper_DEFAULT 0x00000000 |
9746 | #define smnIOHC_SION_Client4_ReqPoolCredit_Alloc_Lower_DEFAULT 0x01010101 |
9747 | #define smnIOHC_SION_Client4_ReqPoolCredit_Alloc_Upper_DEFAULT 0x01010101 |
9748 | #define smnIOHC_SION_Client4_DataPoolCredit_Alloc_Lower_DEFAULT 0x02020202 |
9749 | #define smnIOHC_SION_Client4_DataPoolCredit_Alloc_Upper_DEFAULT 0x02020202 |
9750 | #define smnIOHC_SION_Client4_RdRspPoolCredit_Alloc_Lower_DEFAULT 0x00000001 |
9751 | #define smnIOHC_SION_Client4_RdRspPoolCredit_Alloc_Upper_DEFAULT 0x01010101 |
9752 | #define smnIOHC_SION_Client4_WrRspPoolCredit_Alloc_Lower_DEFAULT 0x01010101 |
9753 | #define smnIOHC_SION_Client4_WrRspPoolCredit_Alloc_Upper_DEFAULT 0x01010101 |
9754 | #define smnIOHC_SION_LiveLock_WatchDog_Threshold_DEFAULT 0x00000014 |
9755 | |
9756 | |
9757 | // addressBlock: nbio_iohub_nb_rascfg_ras_cfgdec |
9758 | #define smnPARITY_CONTROL_0_DEFAULT 0x00010001 |
9759 | #define smnPARITY_CONTROL_1_DEFAULT 0x80000000 |
9760 | #define smnPARITY_SEVERITY_CONTROL_UNCORR_0_DEFAULT 0x00000000 |
9761 | #define smnPARITY_SEVERITY_CONTROL_CORR_0_DEFAULT 0x00000000 |
9762 | #define smnPARITY_SEVERITY_CONTROL_UCP_0_DEFAULT 0x00000000 |
9763 | #define smnRAS_GLOBAL_STATUS_LO_DEFAULT 0x00000000 |
9764 | #define smnRAS_GLOBAL_STATUS_HI_DEFAULT 0x00000000 |
9765 | #define smnPARITY_ERROR_STATUS_UNCORR_GRP0_DEFAULT 0x00000000 |
9766 | #define smnPARITY_ERROR_STATUS_UNCORR_GRP1_DEFAULT 0x00000000 |
9767 | #define smnPARITY_ERROR_STATUS_UNCORR_GRP2_DEFAULT 0x00000000 |
9768 | #define smnPARITY_ERROR_STATUS_UNCORR_GRP3_DEFAULT 0x00000000 |
9769 | #define smnPARITY_ERROR_STATUS_UNCORR_GRP4_DEFAULT 0x00000000 |
9770 | #define smnPARITY_ERROR_STATUS_CORR_GRP0_DEFAULT 0x00000000 |
9771 | #define smnPARITY_ERROR_STATUS_CORR_GRP1_DEFAULT 0x00000000 |
9772 | #define smnPARITY_ERROR_STATUS_CORR_GRP2_DEFAULT 0x00000000 |
9773 | #define smnPARITY_ERROR_STATUS_CORR_GRP3_DEFAULT 0x00000000 |
9774 | #define smnPARITY_ERROR_STATUS_CORR_GRP4_DEFAULT 0x00000000 |
9775 | #define smnPARITY_COUNTER_CORR_GRP0_DEFAULT 0x00000000 |
9776 | #define smnPARITY_COUNTER_CORR_GRP1_DEFAULT 0x00000000 |
9777 | #define smnPARITY_COUNTER_CORR_GRP2_DEFAULT 0x00000000 |
9778 | #define smnPARITY_COUNTER_CORR_GRP3_DEFAULT 0x00000000 |
9779 | #define smnPARITY_COUNTER_CORR_GRP4_DEFAULT 0x00000000 |
9780 | #define smnPARITY_ERROR_STATUS_UCP_GRP0_DEFAULT 0x00000000 |
9781 | #define smnPARITY_ERROR_STATUS_UCP_GRP1_DEFAULT 0x00000000 |
9782 | #define smnPARITY_ERROR_STATUS_UCP_GRP2_DEFAULT 0x00000000 |
9783 | #define smnPARITY_ERROR_STATUS_UCP_GRP3_DEFAULT 0x00000000 |
9784 | #define smnPARITY_ERROR_STATUS_UCP_GRP4_DEFAULT 0x00000000 |
9785 | #define smnPARITY_COUNTER_UCP_GRP0_DEFAULT 0x00000000 |
9786 | #define smnPARITY_COUNTER_UCP_GRP1_DEFAULT 0x00000000 |
9787 | #define smnPARITY_COUNTER_UCP_GRP2_DEFAULT 0x00000000 |
9788 | #define smnPARITY_COUNTER_UCP_GRP3_DEFAULT 0x00000000 |
9789 | #define smnPARITY_COUNTER_UCP_GRP4_DEFAULT 0x00000000 |
9790 | #define smnMISC_SEVERITY_CONTROL_DEFAULT 0x00000000 |
9791 | #define smnMISC_RAS_CONTROL_DEFAULT 0x00000008 |
9792 | #define smnRAS_SCRATCH_0_DEFAULT 0x00000000 |
9793 | #define smnRAS_SCRATCH_1_DEFAULT 0x00000000 |
9794 | #define smnErrEvent_ACTION_CONTROL_DEFAULT 0x00000000 |
9795 | #define smnParitySerr_ACTION_CONTROL_DEFAULT 0x00000000 |
9796 | #define smnParityFatal_ACTION_CONTROL_DEFAULT 0x00000000 |
9797 | #define smnParityNonFatal_ACTION_CONTROL_DEFAULT 0x00000000 |
9798 | #define smnParityCorr_ACTION_CONTROL_DEFAULT 0x00000000 |
9799 | #define smnPCIE0PortASerr_ACTION_CONTROL_DEFAULT 0x00000000 |
9800 | #define smnPCIE0PortAIntFatal_ACTION_CONTROL_DEFAULT 0x00000000 |
9801 | #define smnPCIE0PortAIntNonFatal_ACTION_CONTROL_DEFAULT 0x00000000 |
9802 | #define smnPCIE0PortAIntCorr_ACTION_CONTROL_DEFAULT 0x00000000 |
9803 | #define smnPCIE0PortAExtFatal_ACTION_CONTROL_DEFAULT 0x00000000 |
9804 | #define smnPCIE0PortAExtNonFatal_ACTION_CONTROL_DEFAULT 0x00000000 |
9805 | #define smnPCIE0PortAExtCorr_ACTION_CONTROL_DEFAULT 0x00000000 |
9806 | #define smnPCIE0PortAParityErr_ACTION_CONTROL_DEFAULT 0x00000000 |
9807 | #define smnPCIE0PortBSerr_ACTION_CONTROL_DEFAULT 0x00000000 |
9808 | #define smnPCIE0PortBIntFatal_ACTION_CONTROL_DEFAULT 0x00000000 |
9809 | #define smnPCIE0PortBIntNonFatal_ACTION_CONTROL_DEFAULT 0x00000000 |
9810 | #define smnPCIE0PortBIntCorr_ACTION_CONTROL_DEFAULT 0x00000000 |
9811 | #define smnPCIE0PortBExtFatal_ACTION_CONTROL_DEFAULT 0x00000000 |
9812 | #define smnPCIE0PortBExtNonFatal_ACTION_CONTROL_DEFAULT 0x00000000 |
9813 | #define smnPCIE0PortBExtCorr_ACTION_CONTROL_DEFAULT 0x00000000 |
9814 | #define smnPCIE0PortBParityErr_ACTION_CONTROL_DEFAULT 0x00000000 |
9815 | #define smnPCIE0PortCSerr_ACTION_CONTROL_DEFAULT 0x00000000 |
9816 | #define smnPCIE0PortCIntFatal_ACTION_CONTROL_DEFAULT 0x00000000 |
9817 | #define smnPCIE0PortCIntNonFatal_ACTION_CONTROL_DEFAULT 0x00000000 |
9818 | #define smnPCIE0PortCIntCorr_ACTION_CONTROL_DEFAULT 0x00000000 |
9819 | #define smnPCIE0PortCExtFatal_ACTION_CONTROL_DEFAULT 0x00000000 |
9820 | #define smnPCIE0PortCExtNonFatal_ACTION_CONTROL_DEFAULT 0x00000000 |
9821 | #define smnPCIE0PortCExtCorr_ACTION_CONTROL_DEFAULT 0x00000000 |
9822 | #define smnPCIE0PortCParityErr_ACTION_CONTROL_DEFAULT 0x00000000 |
9823 | #define smnPCIE0PortDSerr_ACTION_CONTROL_DEFAULT 0x00000000 |
9824 | #define smnPCIE0PortDIntFatal_ACTION_CONTROL_DEFAULT 0x00000000 |
9825 | #define smnPCIE0PortDIntNonFatal_ACTION_CONTROL_DEFAULT 0x00000000 |
9826 | #define smnPCIE0PortDIntCorr_ACTION_CONTROL_DEFAULT 0x00000000 |
9827 | #define smnPCIE0PortDExtFatal_ACTION_CONTROL_DEFAULT 0x00000000 |
9828 | #define smnPCIE0PortDExtNonFatal_ACTION_CONTROL_DEFAULT 0x00000000 |
9829 | #define smnPCIE0PortDExtCorr_ACTION_CONTROL_DEFAULT 0x00000000 |
9830 | #define smnPCIE0PortDParityErr_ACTION_CONTROL_DEFAULT 0x00000000 |
9831 | #define smnPCIE0PortESerr_ACTION_CONTROL_DEFAULT 0x00000000 |
9832 | #define smnPCIE0PortEIntFatal_ACTION_CONTROL_DEFAULT 0x00000000 |
9833 | #define smnPCIE0PortEIntNonFatal_ACTION_CONTROL_DEFAULT 0x00000000 |
9834 | #define smnPCIE0PortEIntCorr_ACTION_CONTROL_DEFAULT 0x00000000 |
9835 | #define smnPCIE0PortEExtFatal_ACTION_CONTROL_DEFAULT 0x00000000 |
9836 | #define smnPCIE0PortEExtNonFatal_ACTION_CONTROL_DEFAULT 0x00000000 |
9837 | #define smnPCIE0PortEExtCorr_ACTION_CONTROL_DEFAULT 0x00000000 |
9838 | #define smnPCIE0PortEParityErr_ACTION_CONTROL_DEFAULT 0x00000000 |
9839 | #define smnPCIE0PortFSerr_ACTION_CONTROL_DEFAULT 0x00000000 |
9840 | #define smnPCIE0PortFIntFatal_ACTION_CONTROL_DEFAULT 0x00000000 |
9841 | #define smnPCIE0PortFIntNonFatal_ACTION_CONTROL_DEFAULT 0x00000000 |
9842 | #define smnPCIE0PortFIntCorr_ACTION_CONTROL_DEFAULT 0x00000000 |
9843 | #define smnPCIE0PortFExtFatal_ACTION_CONTROL_DEFAULT 0x00000000 |
9844 | #define smnPCIE0PortFExtNonFatal_ACTION_CONTROL_DEFAULT 0x00000000 |
9845 | #define smnPCIE0PortFExtCorr_ACTION_CONTROL_DEFAULT 0x00000000 |
9846 | #define smnPCIE0PortFParityErr_ACTION_CONTROL_DEFAULT 0x00000000 |
9847 | #define smnPCIE0PortGSerr_ACTION_CONTROL_DEFAULT 0x00000000 |
9848 | #define smnPCIE0PortGIntFatal_ACTION_CONTROL_DEFAULT 0x00000000 |
9849 | #define smnPCIE0PortGIntNonFatal_ACTION_CONTROL_DEFAULT 0x00000000 |
9850 | #define smnPCIE0PortGIntCorr_ACTION_CONTROL_DEFAULT 0x00000000 |
9851 | #define smnPCIE0PortGExtFatal_ACTION_CONTROL_DEFAULT 0x00000000 |
9852 | #define smnPCIE0PortGExtNonFatal_ACTION_CONTROL_DEFAULT 0x00000000 |
9853 | #define smnPCIE0PortGExtCorr_ACTION_CONTROL_DEFAULT 0x00000000 |
9854 | #define smnPCIE0PortGParityErr_ACTION_CONTROL_DEFAULT 0x00000000 |
9855 | #define smnNBIF1PortASerr_ACTION_CONTROL_DEFAULT 0x00000000 |
9856 | #define smnNBIF1PortAIntFatal_ACTION_CONTROL_DEFAULT 0x00000000 |
9857 | #define smnNBIF1PortAIntNonFatal_ACTION_CONTROL_DEFAULT 0x00000000 |
9858 | #define smnNBIF1PortAIntCorr_ACTION_CONTROL_DEFAULT 0x00000000 |
9859 | #define smnNBIF1PortAExtFatal_ACTION_CONTROL_DEFAULT 0x00000000 |
9860 | #define smnNBIF1PortAExtNonFatal_ACTION_CONTROL_DEFAULT 0x00000000 |
9861 | #define smnNBIF1PortAExtCorr_ACTION_CONTROL_DEFAULT 0x00000000 |
9862 | #define smnNBIF1PortAParityErr_ACTION_CONTROL_DEFAULT 0x00000000 |
9863 | #define smnNBIF1PortBSerr_ACTION_CONTROL_DEFAULT 0x00000000 |
9864 | #define smnNBIF1PortBIntFatal_ACTION_CONTROL_DEFAULT 0x00000000 |
9865 | #define smnNBIF1PortBIntNonFatal_ACTION_CONTROL_DEFAULT 0x00000000 |
9866 | #define smnNBIF1PortBIntCorr_ACTION_CONTROL_DEFAULT 0x00000000 |
9867 | #define smnNBIF1PortBExtFatal_ACTION_CONTROL_DEFAULT 0x00000000 |
9868 | #define smnNBIF1PortBExtNonFatal_ACTION_CONTROL_DEFAULT 0x00000000 |
9869 | #define smnNBIF1PortBExtCorr_ACTION_CONTROL_DEFAULT 0x00000000 |
9870 | #define smnNBIF1PortBParityErr_ACTION_CONTROL_DEFAULT 0x00000000 |
9871 | #define smnSYNCFLOOD_STATUS_DEFAULT 0x00000000 |
9872 | #define smnNMI_STATUS_DEFAULT 0x00000000 |
9873 | #define smnPOISON_ACTION_CONTROL_DEFAULT 0x00000000 |
9874 | #define smnINTERNAL_POISON_STATUS_DEFAULT 0x00000000 |
9875 | #define smnINTERNAL_POISON_MASK_DEFAULT 0x00000000 |
9876 | #define smnEGRESS_POISON_STATUS_LO_DEFAULT 0x00000000 |
9877 | #define smnEGRESS_POISON_STATUS_HI_DEFAULT 0x00000000 |
9878 | #define smnEGRESS_POISON_MASK_LO_DEFAULT 0x00000000 |
9879 | #define smnEGRESS_POISON_MASK_HI_DEFAULT 0x00000000 |
9880 | #define smnEGRESS_POISON_SEVERITY_DOWN_DEFAULT 0x00000000 |
9881 | #define smnEGRESS_POISON_SEVERITY_UPPER_DEFAULT 0x00000000 |
9882 | #define smnAPML_STATUS_DEFAULT 0x00000000 |
9883 | #define smnAPML_CONTROL_DEFAULT 0x00000100 |
9884 | #define smnAPML_TRIGGER_DEFAULT 0x00000000 |
9885 | |
9886 | |
9887 | // addressBlock: nbio_iohub_nb_psprascfg_pspras_cfgdec |
9888 | #define smnPSP_SYNCFLOOD_STATUS_DEFAULT 0x00000000 |
9889 | #define smnPSP_INTERNAL_POISON_STATUS_DEFAULT 0x00000000 |
9890 | #define smnPSP_EGRESS_POISON_STATUS_LO_DEFAULT 0x00000000 |
9891 | #define smnPSP_EGRESS_POISON_STATUS_HI_DEFAULT 0x00000000 |
9892 | #define smnPSP_PARITY_CONTROL_0_DEFAULT 0x00010001 |
9893 | #define smnPSP_PARITY_STATUS_DEFAULT 0x00000000 |
9894 | #define smnPSP_PARITY_ERROR_STATUS_UNCORR_GRP0_DEFAULT 0x00000000 |
9895 | #define smnPSP_PARITY_ERROR_STATUS_UNCORR_GRP1_DEFAULT 0x00000000 |
9896 | #define smnPSP_PARITY_ERROR_STATUS_UNCORR_GRP2_DEFAULT 0x00000000 |
9897 | #define smnPSP_PARITY_ERROR_STATUS_UNCORR_GRP3_DEFAULT 0x00000000 |
9898 | #define smnPSP_PARITY_ERROR_STATUS_UNCORR_GRP4_DEFAULT 0x00000000 |
9899 | #define smnPSP_PARITY_ERROR_STATUS_UCP_GRP0_DEFAULT 0x00000000 |
9900 | #define smnPSP_PARITY_ERROR_STATUS_UCP_GRP1_DEFAULT 0x00000000 |
9901 | #define smnPSP_PARITY_ERROR_STATUS_UCP_GRP2_DEFAULT 0x00000000 |
9902 | #define smnPSP_PARITY_ERROR_STATUS_UCP_GRP3_DEFAULT 0x00000000 |
9903 | #define smnPSP_PARITY_ERROR_STATUS_UCP_GRP4_DEFAULT 0x00000000 |
9904 | #define smnPSP_PARITY_COUNTER_UCP_GRP0_DEFAULT 0x00000000 |
9905 | #define smnPSP_PARITY_COUNTER_UCP_GRP1_DEFAULT 0x00000000 |
9906 | #define smnPSP_PARITY_COUNTER_UCP_GRP2_DEFAULT 0x00000000 |
9907 | #define smnPSP_PARITY_COUNTER_UCP_GRP3_DEFAULT 0x00000000 |
9908 | #define smnPSP_PARITY_COUNTER_UCP_GRP4_DEFAULT 0x00000000 |
9909 | #define smnPSP_PARITY_ERROR_STATUS_CORR_GRP0_DEFAULT 0x00000000 |
9910 | #define smnPSP_PARITY_ERROR_STATUS_CORR_GRP1_DEFAULT 0x00000000 |
9911 | #define smnPSP_PARITY_ERROR_STATUS_CORR_GRP2_DEFAULT 0x00000000 |
9912 | #define smnPSP_PARITY_ERROR_STATUS_CORR_GRP3_DEFAULT 0x00000000 |
9913 | #define smnPSP_PARITY_ERROR_STATUS_CORR_GRP4_DEFAULT 0x00000000 |
9914 | #define smnPSP_PARITY_COUNTER_CORR_GRP0_DEFAULT 0x00000000 |
9915 | #define smnPSP_PARITY_COUNTER_CORR_GRP1_DEFAULT 0x00000000 |
9916 | #define smnPSP_PARITY_COUNTER_CORR_GRP2_DEFAULT 0x00000000 |
9917 | #define smnPSP_PARITY_COUNTER_CORR_GRP3_DEFAULT 0x00000000 |
9918 | #define smnPSP_PARITY_COUNTER_CORR_GRP4_DEFAULT 0x00000000 |
9919 | #define smnPSP_ParitySerr_ACTION_CONTROL_DEFAULT 0x00000000 |
9920 | #define smnPSP_ParityFatal_ACTION_CONTROL_DEFAULT 0x00000000 |
9921 | #define smnPSP_ParityNonFatal_ACTION_CONTROL_DEFAULT 0x00000000 |
9922 | #define smnPSP_ParityCorr_ACTION_CONTROL_DEFAULT 0x00000000 |
9923 | |
9924 | |
9925 | // addressBlock: nbio_iohub_nb_PCIE0devindcfg0_devind_cfgdecp |
9926 | #define smnNB_PCIE0DEVINDCFG0_IOHC_Bridge_CNTL_DEFAULT 0x00000000 |
9927 | #define smnNB_PCIE0DEVINDCFG0_IOHC_Bridge_STATUS_DEFAULT 0x00000000 |
9928 | #define smnNB_PCIE0DEVINDCFG0_STEERING_CNTL_DEFAULT 0x00000000 |
9929 | #define smnNB_PCIE0DEVINDCFG0_IOHC_Bridge_SCRATCH_0_DEFAULT 0x00000000 |
9930 | #define smnNB_PCIE0DEVINDCFG0_IOHC_Bridge_SCRATCH_1_DEFAULT 0x00000000 |
9931 | |
9932 | |
9933 | // addressBlock: nbio_iohub_nb_PCIE0devindcfg1_devind_cfgdecp |
9934 | #define smnNB_PCIE0DEVINDCFG1_IOHC_Bridge_CNTL_DEFAULT 0x00000000 |
9935 | #define smnNB_PCIE0DEVINDCFG1_IOHC_Bridge_STATUS_DEFAULT 0x00000000 |
9936 | #define smnNB_PCIE0DEVINDCFG1_STEERING_CNTL_DEFAULT 0x00000000 |
9937 | #define smnNB_PCIE0DEVINDCFG1_IOHC_Bridge_SCRATCH_0_DEFAULT 0x00000000 |
9938 | #define smnNB_PCIE0DEVINDCFG1_IOHC_Bridge_SCRATCH_1_DEFAULT 0x00000000 |
9939 | |
9940 | |
9941 | // addressBlock: nbio_iohub_nb_PCIE0devindcfg2_devind_cfgdecp |
9942 | #define smnNB_PCIE0DEVINDCFG2_IOHC_Bridge_CNTL_DEFAULT 0x00000000 |
9943 | #define smnNB_PCIE0DEVINDCFG2_IOHC_Bridge_STATUS_DEFAULT 0x00000000 |
9944 | #define smnNB_PCIE0DEVINDCFG2_STEERING_CNTL_DEFAULT 0x00000000 |
9945 | #define smnNB_PCIE0DEVINDCFG2_IOHC_Bridge_SCRATCH_0_DEFAULT 0x00000000 |
9946 | #define smnNB_PCIE0DEVINDCFG2_IOHC_Bridge_SCRATCH_1_DEFAULT 0x00000000 |
9947 | |
9948 | |
9949 | // addressBlock: nbio_iohub_nb_PCIE0devindcfg3_devind_cfgdecp |
9950 | #define smnNB_PCIE0DEVINDCFG3_IOHC_Bridge_CNTL_DEFAULT 0x00000000 |
9951 | #define smnNB_PCIE0DEVINDCFG3_IOHC_Bridge_STATUS_DEFAULT 0x00000000 |
9952 | #define smnNB_PCIE0DEVINDCFG3_STEERING_CNTL_DEFAULT 0x00000000 |
9953 | #define smnNB_PCIE0DEVINDCFG3_IOHC_Bridge_SCRATCH_0_DEFAULT 0x00000000 |
9954 | #define smnNB_PCIE0DEVINDCFG3_IOHC_Bridge_SCRATCH_1_DEFAULT 0x00000000 |
9955 | |
9956 | |
9957 | // addressBlock: nbio_iohub_nb_PCIE0devindcfg4_devind_cfgdecp |
9958 | #define smnNB_PCIE0DEVINDCFG4_IOHC_Bridge_CNTL_DEFAULT 0x00000000 |
9959 | #define smnNB_PCIE0DEVINDCFG4_IOHC_Bridge_STATUS_DEFAULT 0x00000000 |
9960 | #define smnNB_PCIE0DEVINDCFG4_STEERING_CNTL_DEFAULT 0x00000000 |
9961 | #define smnNB_PCIE0DEVINDCFG4_IOHC_Bridge_SCRATCH_0_DEFAULT 0x00000000 |
9962 | #define smnNB_PCIE0DEVINDCFG4_IOHC_Bridge_SCRATCH_1_DEFAULT 0x00000000 |
9963 | |
9964 | |
9965 | // addressBlock: nbio_iohub_nb_PCIE0devindcfg5_devind_cfgdecp |
9966 | #define smnNB_PCIE0DEVINDCFG5_IOHC_Bridge_CNTL_DEFAULT 0x00000000 |
9967 | #define smnNB_PCIE0DEVINDCFG5_IOHC_Bridge_STATUS_DEFAULT 0x00000000 |
9968 | #define smnNB_PCIE0DEVINDCFG5_STEERING_CNTL_DEFAULT 0x00000000 |
9969 | #define smnNB_PCIE0DEVINDCFG5_IOHC_Bridge_SCRATCH_0_DEFAULT 0x00000000 |
9970 | #define smnNB_PCIE0DEVINDCFG5_IOHC_Bridge_SCRATCH_1_DEFAULT 0x00000000 |
9971 | |
9972 | |
9973 | // addressBlock: nbio_iohub_nb_PCIE0devindcfg6_devind_cfgdecp |
9974 | #define smnNB_PCIE0DEVINDCFG6_IOHC_Bridge_CNTL_DEFAULT 0x00000000 |
9975 | #define smnNB_PCIE0DEVINDCFG6_IOHC_Bridge_STATUS_DEFAULT 0x00000000 |
9976 | #define smnNB_PCIE0DEVINDCFG6_STEERING_CNTL_DEFAULT 0x00000000 |
9977 | #define smnNB_PCIE0DEVINDCFG6_IOHC_Bridge_SCRATCH_0_DEFAULT 0x00000000 |
9978 | #define smnNB_PCIE0DEVINDCFG6_IOHC_Bridge_SCRATCH_1_DEFAULT 0x00000000 |
9979 | |
9980 | |
9981 | // addressBlock: nbio_iohub_nb_NBIF1devindcfg0_devind_cfgdecp |
9982 | #define smnNB_NBIF1DEVINDCFG0_IOHC_Bridge_CNTL_DEFAULT 0x00000000 |
9983 | #define smnNB_NBIF1DEVINDCFG0_IOHC_Bridge_STATUS_DEFAULT 0x00000000 |
9984 | #define smnNB_NBIF1DEVINDCFG0_STEERING_CNTL_DEFAULT 0x00000000 |
9985 | #define smnNB_NBIF1DEVINDCFG0_IOHC_Bridge_SCRATCH_0_DEFAULT 0x00000000 |
9986 | #define smnNB_NBIF1DEVINDCFG0_IOHC_Bridge_SCRATCH_1_DEFAULT 0x00000000 |
9987 | |
9988 | |
9989 | // addressBlock: nbio_iohub_nb_NBIF1devindcfg1_devind_cfgdecp |
9990 | #define smnNB_NBIF1DEVINDCFG1_IOHC_Bridge_CNTL_DEFAULT 0x00000000 |
9991 | #define smnNB_NBIF1DEVINDCFG1_IOHC_Bridge_STATUS_DEFAULT 0x00000000 |
9992 | #define smnNB_NBIF1DEVINDCFG1_STEERING_CNTL_DEFAULT 0x00000000 |
9993 | #define smnNB_NBIF1DEVINDCFG1_IOHC_Bridge_SCRATCH_0_DEFAULT 0x00000000 |
9994 | #define smnNB_NBIF1DEVINDCFG1_IOHC_Bridge_SCRATCH_1_DEFAULT 0x00000000 |
9995 | |
9996 | |
9997 | // addressBlock: nbio_iohub_nb_intSBdevindcfg0_devind_cfgdecp |
9998 | #define smnNB_INTSBDEVINDCFG0_IOHC_Bridge_CNTL_DEFAULT 0x00000000 |
9999 | #define smnNB_INTSBDEVINDCFG0_IOHC_Bridge_STATUS_DEFAULT 0x00000000 |
10000 | #define smnNB_INTSBDEVINDCFG0_STEERING_CNTL_DEFAULT 0x00000000 |
10001 | #define smnNB_INTSBDEVINDCFG0_IOHC_Bridge_SCRATCH_0_DEFAULT 0x00000000 |
10002 | #define smnNB_INTSBDEVINDCFG0_IOHC_Bridge_SCRATCH_1_DEFAULT 0x00000000 |
10003 | |
10004 | |
10005 | // addressBlock: nbio_iohub_nb_pciedummy0_pciedummy_cfgdec |
10006 | #define smnNB_PCIEDUMMY0_1_DEVICE_VENDOR_ID_DEFAULT 0x00000000 |
10007 | #define smnNB_PCIEDUMMY0_1_STATUS_COMMAND_DEFAULT 0x00000000 |
10008 | #define smnNB_PCIEDUMMY0_1_CLASS_CODE_REVID_DEFAULT 0x00000000 |
10009 | #define 0x00800000 |
10010 | #define 0x00000080 |
10011 | |
10012 | |
10013 | // addressBlock: nbio_iohub_nb_pciedummy1_pciedummy_cfgdec |
10014 | #define smnNB_PCIEDUMMY1_1_DEVICE_VENDOR_ID_DEFAULT 0x00000000 |
10015 | #define smnNB_PCIEDUMMY1_1_STATUS_COMMAND_DEFAULT 0x00000000 |
10016 | #define smnNB_PCIEDUMMY1_1_CLASS_CODE_REVID_DEFAULT 0x00000000 |
10017 | #define 0x00800000 |
10018 | #define 0x00000080 |
10019 | |
10020 | |
10021 | // addressBlock: nbio_iohub_iommu_indcfg_iommuind_cfgdec |
10022 | #define smnIOMMU_SMN_INDEX_0_DEFAULT 0x00000000 |
10023 | #define smnIOMMU_SMN_DATA_0_DEFAULT 0x00000000 |
10024 | #define smnIOMMU_SMN_INDEX_1_DEFAULT 0x00000000 |
10025 | #define smnIOMMU_SMN_DATA_1_DEFAULT 0x00000000 |
10026 | |
10027 | |
10028 | // addressBlock: nbio_iohub_ioapic_indcfg_ioapicind_cfgdec |
10029 | #define smnIOAPIC_MIO_INDEX_DEFAULT 0x00000000 |
10030 | #define smnIOAPIC_MIO_DATA_DEFAULT 0x00000000 |
10031 | |
10032 | |
10033 | // addressBlock: nbio_iohub_nb_PCIE0rcbdg_indcfg0_pciercbdgind_cfgdec |
10034 | #define smnNB_PCIE0RCBDG_INDCFG0_RC_SMN_INDEX_DEFAULT 0x00000000 |
10035 | #define smnNB_PCIE0RCBDG_INDCFG0_RC_SMN_DATA_DEFAULT 0x00000000 |
10036 | |
10037 | |
10038 | // addressBlock: nbio_iohub_nb_PCIE0rcbdg_indcfg1_pciercbdgind_cfgdec |
10039 | #define smnNB_PCIE0RCBDG_INDCFG1_RC_SMN_INDEX_DEFAULT 0x00000000 |
10040 | #define smnNB_PCIE0RCBDG_INDCFG1_RC_SMN_DATA_DEFAULT 0x00000000 |
10041 | |
10042 | |
10043 | // addressBlock: nbio_iohub_nb_PCIE0rcbdg_indcfg2_pciercbdgind_cfgdec |
10044 | #define smnNB_PCIE0RCBDG_INDCFG2_RC_SMN_INDEX_DEFAULT 0x00000000 |
10045 | #define smnNB_PCIE0RCBDG_INDCFG2_RC_SMN_DATA_DEFAULT 0x00000000 |
10046 | |
10047 | |
10048 | // addressBlock: nbio_iohub_nb_PCIE0rcbdg_indcfg3_pciercbdgind_cfgdec |
10049 | #define smnNB_PCIE0RCBDG_INDCFG3_RC_SMN_INDEX_DEFAULT 0x00000000 |
10050 | #define smnNB_PCIE0RCBDG_INDCFG3_RC_SMN_DATA_DEFAULT 0x00000000 |
10051 | |
10052 | |
10053 | // addressBlock: nbio_iohub_nb_PCIE0rcbdg_indcfg4_pciercbdgind_cfgdec |
10054 | #define smnNB_PCIE0RCBDG_INDCFG4_RC_SMN_INDEX_DEFAULT 0x00000000 |
10055 | #define smnNB_PCIE0RCBDG_INDCFG4_RC_SMN_DATA_DEFAULT 0x00000000 |
10056 | |
10057 | |
10058 | // addressBlock: nbio_iohub_nb_PCIE0rcbdg_indcfg5_pciercbdgind_cfgdec |
10059 | #define smnNB_PCIE0RCBDG_INDCFG5_RC_SMN_INDEX_DEFAULT 0x00000000 |
10060 | #define smnNB_PCIE0RCBDG_INDCFG5_RC_SMN_DATA_DEFAULT 0x00000000 |
10061 | |
10062 | |
10063 | // addressBlock: nbio_iohub_nb_PCIE0rcbdg_indcfg6_pciercbdgind_cfgdec |
10064 | #define smnNB_PCIE0RCBDG_INDCFG6_RC_SMN_INDEX_DEFAULT 0x00000000 |
10065 | #define smnNB_PCIE0RCBDG_INDCFG6_RC_SMN_DATA_DEFAULT 0x00000000 |
10066 | |
10067 | |
10068 | // addressBlock: nbio_iohub_nb_NBIF1rcbdg_indcfg0_pciercbdgind_cfgdec |
10069 | #define smnNB_NBIF1RCBDG_INDCFG0_RC_SMN_INDEX_DEFAULT 0x00000000 |
10070 | #define smnNB_NBIF1RCBDG_INDCFG0_RC_SMN_DATA_DEFAULT 0x00000000 |
10071 | |
10072 | |
10073 | // addressBlock: nbio_iohub_nb_NBIF1rcbdg_indcfg1_pciercbdgind_cfgdec |
10074 | #define smnNB_NBIF1RCBDG_INDCFG1_RC_SMN_INDEX_DEFAULT 0x00000000 |
10075 | #define smnNB_NBIF1RCBDG_INDCFG1_RC_SMN_DATA_DEFAULT 0x00000000 |
10076 | |
10077 | |
10078 | // addressBlock: nbio_iohub_iommu_l2_iommul2cfg |
10079 | #define smnIOMMU_L2_1_IOMMU_VENDOR_ID_DEFAULT 0x00001022 |
10080 | #define smnIOMMU_L2_1_IOMMU_DEVICE_ID_DEFAULT 0x000015d1 |
10081 | #define smnIOMMU_L2_1_IOMMU_COMMAND_DEFAULT 0x00000000 |
10082 | #define smnIOMMU_L2_1_IOMMU_STATUS_DEFAULT 0x00000000 |
10083 | #define smnIOMMU_L2_1_IOMMU_REVISION_ID_DEFAULT 0x00000000 |
10084 | #define smnIOMMU_L2_1_IOMMU_REGPROG_INF_DEFAULT 0x00000000 |
10085 | #define smnIOMMU_L2_1_IOMMU_SUB_CLASS_DEFAULT 0x00000000 |
10086 | #define smnIOMMU_L2_1_IOMMU_BASE_CODE_DEFAULT 0x00000000 |
10087 | #define smnIOMMU_L2_1_IOMMU_CACHE_LINE_DEFAULT 0x00000000 |
10088 | #define smnIOMMU_L2_1_IOMMU_LATENCY_DEFAULT 0x00000000 |
10089 | #define 0x00000000 |
10090 | #define smnIOMMU_L2_1_IOMMU_BIST_DEFAULT 0x00000000 |
10091 | #define smnIOMMU_L2_1_IOMMU_ADAPTER_ID_DEFAULT 0x00000000 |
10092 | #define smnIOMMU_L2_1_IOMMU_CAPABILITIES_PTR_DEFAULT 0x00000000 |
10093 | #define smnIOMMU_L2_1_IOMMU_INTERRUPT_LINE_DEFAULT 0x00000000 |
10094 | #define smnIOMMU_L2_1_IOMMU_INTERRUPT_PIN_DEFAULT 0x00000001 |
10095 | #define 0x00000000 |
10096 | #define smnIOMMU_L2_1_IOMMU_CAP_BASE_LO_DEFAULT 0x00000000 |
10097 | #define smnIOMMU_L2_1_IOMMU_CAP_BASE_HI_DEFAULT 0x00000000 |
10098 | #define smnIOMMU_L2_1_IOMMU_CAP_RANGE_DEFAULT 0x00000000 |
10099 | #define smnIOMMU_L2_1_IOMMU_CAP_MISC_DEFAULT 0x00003000 |
10100 | #define smnIOMMU_L2_1_IOMMU_CAP_MISC_1_DEFAULT 0x00000080 |
10101 | #define smnIOMMU_L2_1_IOMMU_MSI_CAP_DEFAULT 0x00000000 |
10102 | #define smnIOMMU_L2_1_IOMMU_MSI_ADDR_LO_DEFAULT 0x00000000 |
10103 | #define smnIOMMU_L2_1_IOMMU_MSI_ADDR_HI_DEFAULT 0x00000000 |
10104 | #define smnIOMMU_L2_1_IOMMU_MSI_DATA_DEFAULT 0x00000000 |
10105 | #define smnIOMMU_L2_1_IOMMU_MSI_MAPPING_CAP_DEFAULT 0x00000000 |
10106 | #define smnIOMMU_L2_1_IOMMU_ADAPTER_ID_W_DEFAULT 0x00000000 |
10107 | #define smnIOMMU_L2_1_IOMMU_CONTROL_W_DEFAULT 0x00002b01 |
10108 | #define smnIOMMU_L2_1_IOMMU_MMIO_CONTROL0_W_DEFAULT 0x62201ada |
10109 | #define smnIOMMU_L2_1_IOMMU_MMIO_CONTROL1_W_DEFAULT 0x0003cfcf |
10110 | #define smnIOMMU_L2_1_IOMMU_RANGE_W_DEFAULT 0x00000000 |
10111 | #define smnIOMMU_L2_1_IOMMU_DSFX_CONTROL_DEFAULT 0x00000000 |
10112 | #define smnIOMMU_L2_1_IOMMU_DSSX_DUMMY_0_DEFAULT 0x00000000 |
10113 | #define smnIOMMU_L2_1_IOMMU_DSCX_DUMMY_0_DEFAULT 0x00000000 |
10114 | #define smnIOMMU_L2_1_L2B_POISON_DVM_CNTRL_DEFAULT 0x00000002 |
10115 | #define smnIOMMU_L2_1_L2_IOHC_DmaReq_Stall_Control_DEFAULT 0x00000000 |
10116 | #define smnIOMMU_L2_1_IOHC_L2_HostRsp_Stall_Control_DEFAULT 0x00000000 |
10117 | #define smnIOMMU_L2_1_SMMU_MMIO_IDR0_W_DEFAULT 0x2d4f7fbf |
10118 | #define smnIOMMU_L2_1_SMMU_MMIO_IDR1_W_DEFAULT 0x0e739c10 |
10119 | #define smnIOMMU_L2_1_SMMU_MMIO_IDR2_W_DEFAULT 0x00000000 |
10120 | #define smnIOMMU_L2_1_SMMU_MMIO_IDR3_W_DEFAULT 0x00000000 |
10121 | #define smnIOMMU_L2_1_SMMU_MMIO_IDR5_W_DEFAULT 0x00000075 |
10122 | #define smnIOMMU_L2_1_SMMU_MMIO_IIDR_W_DEFAULT 0x00000000 |
10123 | #define smnIOMMU_L2_1_SMMU_AIDR_W_DEFAULT 0x00000000 |
10124 | |
10125 | |
10126 | // addressBlock: nbio_iohub_iommu_l2indx_l2indxcfg |
10127 | #define smnL2_STATUS_1_DEFAULT 0x00000000 |
10128 | #define smnL2_SB_LOCATION_DEFAULT 0x00000000 |
10129 | #define smnL2_CONTROL_5_DEFAULT 0x01001001 |
10130 | #define smnL2_CONTROL_6_DEFAULT 0x00010808 |
10131 | #define smnL2_PDC_CONTROL_DEFAULT 0x00000200 |
10132 | #define smnL2_PDC_HASH_CONTROL_DEFAULT 0x00000000 |
10133 | #define smnL2_PDC_WAY_CONTROL_DEFAULT 0x00000000 |
10134 | #define smnL2B_UPDATE_FILTER_CNTL_DEFAULT 0x00000007 |
10135 | #define smnL2_TW_CONTROL_DEFAULT 0x00501000 |
10136 | #define smnL2_CP_CONTROL_DEFAULT 0x00000004 |
10137 | #define smnL2_CP_CONTROL_1_DEFAULT 0x00000000 |
10138 | #define smnIOMMU_L2_GUEST_ADDR_CNTRL_DEFAULT 0x00000000 |
10139 | #define smnL2_TW_CONTROL_1_DEFAULT 0x00000000 |
10140 | #define smnL2_TW_CONTROL_2_DEFAULT 0x00000000 |
10141 | #define smnL2_TW_CONTROL_3_DEFAULT 0x00000000 |
10142 | #define smnL2_CREDIT_CONTROL_0_DEFAULT 0x40000000 |
10143 | #define smnL2_CREDIT_CONTROL_1_DEFAULT 0x00440404 |
10144 | #define smnL2_ERR_RULE_CONTROL_0_DEFAULT 0x00000000 |
10145 | #define smnL2_ERR_RULE_CONTROL_1_DEFAULT 0x00000000 |
10146 | #define smnL2_ERR_RULE_CONTROL_2_DEFAULT 0x00000000 |
10147 | #define smnL2_L2B_CK_GATE_CONTROL_DEFAULT 0x00000057 |
10148 | #define smnPPR_CONTROL_DEFAULT 0x00000000 |
10149 | #define smnL2_L2B_PGSIZE_CONTROL_DEFAULT 0x00000101 |
10150 | #define smnL2_L2B_MEMPWR_GATE_1_DEFAULT 0x00000000 |
10151 | #define smnL2_L2B_MEMPWR_GATE_2_DEFAULT 0x00000064 |
10152 | #define smnL2_L2B_MEMPWR_GATE_3_DEFAULT 0x00000064 |
10153 | #define smnL2_L2B_MEMPWR_GATE_4_DEFAULT 0x0000044c |
10154 | #define smnL2_PERF_CNTL_2_DEFAULT 0x00000000 |
10155 | #define smnL2_PERF_COUNT_4_DEFAULT 0x00000000 |
10156 | #define smnL2_PERF_COUNT_5_DEFAULT 0x00000000 |
10157 | #define smnL2_PERF_CNTL_3_DEFAULT 0x00000000 |
10158 | #define smnL2_PERF_COUNT_6_DEFAULT 0x00000000 |
10159 | #define smnL2_PERF_COUNT_7_DEFAULT 0x00000000 |
10160 | #define smnL2_L2B_DVM_CTRL_0_DEFAULT 0x00000008 |
10161 | #define smnL2_L2B_DVM_CTRL_1_DEFAULT 0x00000000 |
10162 | #define smnL2B_SDP_MAXCRED_DEFAULT 0x08888888 |
10163 | #define smnL2B_SDP_PARITY_ERROR_EN_DEFAULT 0x00000000 |
10164 | #define smnL2_ECO_CNTRL_1_DEFAULT 0x00000000 |
10165 | #define smnL2_L2B_MEMPWR_GATE_5_DEFAULT 0x00000001 |
10166 | #define smnL2_L2B_MEMPWR_GATE_6_DEFAULT 0x00000001 |
10167 | #define smnL2_L2B_MEMPWR_GATE_7_DEFAULT 0x00000001 |
10168 | #define smnL2_L2B_MEMPWR_GATE_8_DEFAULT 0x00000006 |
10169 | #define smnL2_L2B_MEMPWR_GATE_9_DEFAULT 0x00000001 |
10170 | #define smnL2_L2B_MEMPWR_GATE_10_DEFAULT 0x00000006 |
10171 | |
10172 | |
10173 | // addressBlock: nbio_iohub_iommu_l2bshdw_l2bshdw |
10174 | #define smnSHDW_PCIE0_Port0_NBIO_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 |
10175 | #define smnSHDW_PCIE0_Port1_NBIO_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 |
10176 | #define smnSHDW_PCIE0_Port2_NBIO_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 |
10177 | #define smnSHDW_PCIE0_Port3_NBIO_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 |
10178 | #define smnSHDW_PCIE0_Port4_NBIO_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 |
10179 | #define smnSHDW_PCIE0_Port5_NBIO_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 |
10180 | #define smnSHDW_PCIE0_Port6_NBIO_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 |
10181 | #define smnSHDW_PCIE0_Port7_NBIO_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 |
10182 | #define smnSHDW_NBIF1_Port0_NBIO_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 |
10183 | #define smnSHDW_NBIF1_Port1_NBIO_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 |
10184 | |
10185 | |
10186 | // addressBlock: nbio_iohub_iommu_l2bpsp_l2bpsp |
10187 | #define smnL2BPSP_ERR_REP_ENABLE_DEFAULT 0x00000000 |
10188 | #define smnL2BPSP_HW_ERR_STATUS_0_DEFAULT 0x00000000 |
10189 | #define smnL2BPSP_HW_ERR_STATUS_1_DEFAULT 0x00000000 |
10190 | #define smnL2BPSP_HW_ERR_LOWER_0_DEFAULT 0x00000000 |
10191 | #define smnL2BPSP_HW_ERR_LOWER_1_DEFAULT 0x00000000 |
10192 | #define smnL2BPSP_HW_ERR_UPPER_0_DEFAULT 0x00000000 |
10193 | #define smnL2BPSP_HW_ERR_UPPER_1_DEFAULT 0x00000000 |
10194 | |
10195 | |
10196 | // addressBlock: nbio_iohub_nb_ioapiccfg_ioapic_cfgdec |
10197 | #define smnFEATURES_ENABLE_DEFAULT 0x00000204 |
10198 | #define smnIOAPIC_BR0_INTERRUPT_ROUTING_DEFAULT 0x00000000 |
10199 | #define smnIOAPIC_BR1_INTERRUPT_ROUTING_DEFAULT 0x00000000 |
10200 | #define smnIOAPIC_BR2_INTERRUPT_ROUTING_DEFAULT 0x00000000 |
10201 | #define smnIOAPIC_BR3_INTERRUPT_ROUTING_DEFAULT 0x00000000 |
10202 | #define smnIOAPIC_BR4_INTERRUPT_ROUTING_DEFAULT 0x00000000 |
10203 | #define smnIOAPIC_BR5_INTERRUPT_ROUTING_DEFAULT 0x00000000 |
10204 | #define smnIOAPIC_BR6_INTERRUPT_ROUTING_DEFAULT 0x00000000 |
10205 | #define smnIOAPIC_BR7_INTERRUPT_ROUTING_DEFAULT 0x00000000 |
10206 | #define smnIOAPIC_BR8_INTERRUPT_ROUTING_DEFAULT 0x00000000 |
10207 | #define smnIOAPIC_SERIAL_IRQ_STATUS_DEFAULT 0x00000000 |
10208 | #define smnIOAPIC_SCRATCH_0_DEFAULT 0x00000000 |
10209 | #define smnIOAPIC_SCRATCH_1_DEFAULT 0x00000000 |
10210 | #define smnIOAPIC_GLUE_CG_LCLK_CTRL_0_DEFAULT 0xffc00100 |
10211 | #define smnIOAPIC_SDP_PORT_CONTROL_DEFAULT 0x0000000f |
10212 | #define smnIOAPIC_PERF_CNTL_DEFAULT 0x00000000 |
10213 | #define smnIOAPIC_PERF_COUNT0_DEFAULT 0x00000000 |
10214 | #define smnIOAPIC_PERF_COUNT0_UPPER_DEFAULT 0x00000000 |
10215 | #define smnIOAPIC_PERF_COUNT1_DEFAULT 0x00000000 |
10216 | #define smnIOAPIC_PERF_COUNT1_UPPER_DEFAULT 0x00000000 |
10217 | #define smnIOAPIC_PERF_COUNT2_DEFAULT 0x00000000 |
10218 | #define smnIOAPIC_PERF_COUNT2_UPPER_DEFAULT 0x00000000 |
10219 | #define smnIOAPIC_PERF_COUNT3_DEFAULT 0x00000000 |
10220 | #define smnIOAPIC_PERF_COUNT3_UPPER_DEFAULT 0x00000000 |
10221 | #define smnIOAPIC_PGSLV_CONTROL_DEFAULT 0x00000004 |
10222 | |
10223 | |
10224 | // addressBlock: nbio_iohub_nb_ioapicshdw_ioapic_shdwdec |
10225 | #define smnIOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr0_DEFAULT 0x00000009 |
10226 | #define smnIOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr1_DEFAULT 0x0000000a |
10227 | #define smnIOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr2_DEFAULT 0x0000000b |
10228 | #define smnIOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr3_DEFAULT 0x0000000c |
10229 | #define smnIOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr4_DEFAULT 0x0000000d |
10230 | #define smnIOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr5_DEFAULT 0x0000000e |
10231 | #define smnIOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr6_DEFAULT 0x0000000f |
10232 | #define smnIOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr7_DEFAULT 0x00000041 |
10233 | #define smnIOAPICSHDW_NB_PROG_DEVICE_REMAP_PBr8_DEFAULT 0x00000042 |
10234 | |
10235 | |
10236 | // addressBlock: nbio_iohub_iommu_l1_PCIE0_iommul1cfg |
10237 | #define smnIOMMU_L1_PCIE0_L1_PERF_CNTL_DEFAULT 0x00000000 |
10238 | #define smnIOMMU_L1_PCIE0_L1_PERF_COUNT_0_DEFAULT 0x00000000 |
10239 | #define smnIOMMU_L1_PCIE0_L1_PERF_COUNT_1_DEFAULT 0x00000000 |
10240 | #define smnIOMMU_L1_PCIE0_L1_PERF_CNTL_B_DEFAULT 0x00000000 |
10241 | #define smnIOMMU_L1_PCIE0_L1_PERF_COUNT_B0_DEFAULT 0x00000000 |
10242 | #define smnIOMMU_L1_PCIE0_L1_PERF_COUNT_B1_DEFAULT 0x00000000 |
10243 | #define smnIOMMU_L1_PCIE0_L1_SB_LOCATION_DEFAULT 0x00000000 |
10244 | #define smnIOMMU_L1_PCIE0_L1_CNTRL_0_DEFAULT 0x00100a0c |
10245 | #define smnIOMMU_L1_PCIE0_L1_CNTRL_1_DEFAULT 0x00000400 |
10246 | #define smnIOMMU_L1_PCIE0_L1_CNTRL_2_DEFAULT 0x32000008 |
10247 | #define smnIOMMU_L1_PCIE0_L1_CNTRL_3_DEFAULT 0x0000c350 |
10248 | #define smnIOMMU_L1_PCIE0_L1_BANK_SEL_0_DEFAULT 0x00000001 |
10249 | #define smnIOMMU_L1_PCIE0_L1_BANK_DISABLE_0_DEFAULT 0x00000000 |
10250 | #define smnIOMMU_L1_PCIE0_L1_WQ_STATUS_0_DEFAULT 0x00000000 |
10251 | #define smnIOMMU_L1_PCIE0_L1_WQ_STATUS_1_DEFAULT 0x00000000 |
10252 | #define smnIOMMU_L1_PCIE0_L1_WQ_STATUS_2_DEFAULT 0x00000000 |
10253 | #define smnIOMMU_L1_PCIE0_L1_WQ_STATUS_3_DEFAULT 0x00000000 |
10254 | #define smnIOMMU_L1_PCIE0_L1_FEATURE_CNTRL_DEFAULT 0x00000000 |
10255 | #define smnIOMMU_L1_PCIE0_L1_PGMEM_CTRL_5_DEFAULT 0x00000001 |
10256 | #define smnIOMMU_L1_PCIE0_L1_PGMEM_CTRL_6_DEFAULT 0x00000001 |
10257 | #define smnIOMMU_L1_PCIE0_L1_PGMEM_CTRL_7_DEFAULT 0x00000001 |
10258 | #define smnIOMMU_L1_PCIE0_L1_PGMEM_CTRL_8_DEFAULT 0x00000006 |
10259 | #define smnIOMMU_L1_PCIE0_L1_PGMEM_CTRL_9_DEFAULT 0x00000001 |
10260 | #define smnIOMMU_L1_PCIE0_L1_PGMEM_CTRL_10_DEFAULT 0x00000006 |
10261 | #define smnIOMMU_L1_PCIE0_L1_CNTRL_4_DEFAULT 0x24000000 |
10262 | #define smnIOMMU_L1_PCIE0_L1_CLKCNTRL_0_DEFAULT 0x00020000 |
10263 | #define smnIOMMU_L1_PCIE0_L1_SDP_CLKREQ_CNTRL_DEFAULT 0x00000000 |
10264 | #define smnIOMMU_L1_PCIE0_L1_GUEST_ADDR_CNTRL_DEFAULT 0x00000000 |
10265 | #define smnIOMMU_L1_PCIE0_L1_FEATURE_SUP_CNTRL_DEFAULT 0x0000001f |
10266 | #define smnIOMMU_L1_PCIE0_L1_CNTRL_5_DEFAULT 0x00000000 |
10267 | #define smnIOMMU_L1_PCIE0_L1_PGMEM_CTRL_1_DEFAULT 0x00000000 |
10268 | #define smnIOMMU_L1_PCIE0_L1_PGMEM_CTRL_2_DEFAULT 0x00000000 |
10269 | #define smnIOMMU_L1_PCIE0_L1_PGMEM_CTRL_3_DEFAULT 0x00000000 |
10270 | #define smnIOMMU_L1_PCIE0_L1_PGMEM_CTRL_4_DEFAULT 0x00000000 |
10271 | #define smnIOMMU_L1_PCIE0_IOMMU_PGSLV_CONTROL_DEFAULT 0x0000000b |
10272 | #define smnIOMMU_L1_PCIE0_L1_ATS_RESP_CTRL_0_DEFAULT 0x00000000 |
10273 | #define smnIOMMU_L1_PCIE0_L1_IOHC_DmaReq_Stall_Control_DEFAULT 0x00000000 |
10274 | #define smnIOMMU_L1_PCIE0_CLIENT_L1_DmaRsp_Stall_Control_DEFAULT 0x00000000 |
10275 | #define smnIOMMU_L1_PCIE0_L1_CLIENT_HostReq_Stall_Control_DEFAULT 0x00000000 |
10276 | #define smnIOMMU_L1_PCIE0_IOHC_L1_HostRsp_Stall_Control_DEFAULT 0x00000000 |
10277 | #define smnIOMMU_L1_PCIE0_L1_SDP_MAXCRED_0_DEFAULT 0x00000008 |
10278 | #define smnIOMMU_L1_PCIE0_L1_ECO_CNTRL_DEFAULT 0x00000000 |
10279 | |
10280 | |
10281 | // addressBlock: nbio_iohub_iommu_l1shdw_PCIE0_l1shdw |
10282 | #define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_BASE_0_DEFAULT 0x00000000 |
10283 | #define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_0_DEFAULT 0x00000400 |
10284 | #define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_CNTRL_1_DEFAULT 0x00000000 |
10285 | #define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_BASE_0_DEFAULT 0x00000000 |
10286 | #define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_BASE_1_DEFAULT 0x00000000 |
10287 | #define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_LIM_0_DEFAULT 0x00000000 |
10288 | #define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_EXCL_LIM_1_DEFAULT 0x00000000 |
10289 | #define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_1_BASE_0_DEFAULT 0x00000000 |
10290 | #define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_2_BASE_0_DEFAULT 0x00000000 |
10291 | #define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_3_BASE_0_DEFAULT 0x00000000 |
10292 | #define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_4_BASE_0_DEFAULT 0x00000000 |
10293 | #define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_5_BASE_0_DEFAULT 0x00000000 |
10294 | #define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_6_BASE_0_DEFAULT 0x00000000 |
10295 | #define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVTBL_7_BASE_0_DEFAULT 0x00000000 |
10296 | #define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_0_DEFAULT 0x00000000 |
10297 | #define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_1_DEFAULT 0x00000000 |
10298 | #define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_0_DEFAULT 0x00000000 |
10299 | #define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_1_DEFAULT 0x00000000 |
10300 | #define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_0_DEFAULT 0x00000000 |
10301 | #define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_1_DEFAULT 0x00000000 |
10302 | #define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0_DEFAULT 0x00000000 |
10303 | #define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0_DEFAULT 0x00000000 |
10304 | #define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_1_DEFAULT 0x00000000 |
10305 | #define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0_DEFAULT 0x00000000 |
10306 | #define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_1_DEFAULT 0x00000000 |
10307 | #define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0_DEFAULT 0x00000000 |
10308 | #define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_1_DEFAULT 0x00000000 |
10309 | #define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0_DEFAULT 0x00000000 |
10310 | #define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0_DEFAULT 0x00000000 |
10311 | #define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_1_DEFAULT 0x00000000 |
10312 | #define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0_DEFAULT 0x00000000 |
10313 | #define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_1_DEFAULT 0x00000000 |
10314 | #define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0_DEFAULT 0x00000000 |
10315 | #define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_1_DEFAULT 0x00000000 |
10316 | #define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0_DEFAULT 0x00000000 |
10317 | #define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0_DEFAULT 0x00000000 |
10318 | #define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_1_DEFAULT 0x00000000 |
10319 | #define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0_DEFAULT 0x00000000 |
10320 | #define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_1_DEFAULT 0x00000000 |
10321 | #define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0_DEFAULT 0x00000000 |
10322 | #define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_1_DEFAULT 0x00000000 |
10323 | #define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0_DEFAULT 0x00000000 |
10324 | #define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0_DEFAULT 0x00000000 |
10325 | #define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_1_DEFAULT 0x00000000 |
10326 | #define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0_DEFAULT 0x00000000 |
10327 | #define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_1_DEFAULT 0x00000000 |
10328 | #define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0_DEFAULT 0x00000000 |
10329 | #define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_1_DEFAULT 0x00000000 |
10330 | #define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0_DEFAULT 0x00000000 |
10331 | #define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0_DEFAULT 0x00000000 |
10332 | #define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_1_DEFAULT 0x00000000 |
10333 | #define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0_DEFAULT 0x00000000 |
10334 | #define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_1_DEFAULT 0x00000000 |
10335 | #define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0_DEFAULT 0x00000000 |
10336 | #define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_1_DEFAULT 0x00000000 |
10337 | #define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0_DEFAULT 0x00000000 |
10338 | #define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0_DEFAULT 0x00000000 |
10339 | #define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_1_DEFAULT 0x00000000 |
10340 | #define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0_DEFAULT 0x00000000 |
10341 | #define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_1_DEFAULT 0x00000000 |
10342 | #define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0_DEFAULT 0x00000000 |
10343 | #define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_1_DEFAULT 0x00000000 |
10344 | #define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0_DEFAULT 0x00000000 |
10345 | #define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0_DEFAULT 0x00000000 |
10346 | #define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_1_DEFAULT 0x00000000 |
10347 | #define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0_DEFAULT 0x00000000 |
10348 | #define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_1_DEFAULT 0x00000000 |
10349 | #define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0_DEFAULT 0x00000000 |
10350 | #define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_1_DEFAULT 0x00000000 |
10351 | #define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0_DEFAULT 0x00000000 |
10352 | #define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0_DEFAULT 0x00000000 |
10353 | #define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_1_DEFAULT 0x00000000 |
10354 | #define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0_DEFAULT 0x00000000 |
10355 | #define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_1_DEFAULT 0x00000000 |
10356 | #define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0_DEFAULT 0x00000000 |
10357 | #define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_1_DEFAULT 0x00000000 |
10358 | #define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_CAP_BASE_LO_DEFAULT 0x00000000 |
10359 | #define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_CAP_MISC_DEFAULT 0x00000000 |
10360 | #define smnIOMMU_L1SHDW_PCIE0_SHDWL1_IOMMU_CAP_MISC_1_DEFAULT 0x00000080 |
10361 | |
10362 | |
10363 | // addressBlock: nbio_iohub_iommu_l1psp_PCIE0_l1psp |
10364 | #define smnIOMMU_L1PSP_PCIE0_L1PSP_ERR_REP_CNTRL_DEFAULT 0x00000000 |
10365 | #define smnIOMMU_L1PSP_PCIE0_L1PSP_CPD_STATUS_0_DEFAULT 0x00000000 |
10366 | #define smnIOMMU_L1PSP_PCIE0_L1PSP_CPD_STATUS_1_DEFAULT 0x00000000 |
10367 | #define smnIOMMU_L1PSP_PCIE0_L1PSP_CPD_REQADDR_0_DEFAULT 0x00000000 |
10368 | #define smnIOMMU_L1PSP_PCIE0_L1PSP_CPD_REQADDR_1_DEFAULT 0x00000000 |
10369 | #define smnIOMMU_L1PSP_PCIE0_L1PSP_REQ_CNTRL_DEFAULT 0x00000000 |
10370 | |
10371 | |
10372 | // addressBlock: nbio_iohub_iommu_l1_IOAGR_iommul1cfg |
10373 | #define smnIOMMU_L1_IOAGR_L1_PERF_CNTL_DEFAULT 0x00000000 |
10374 | #define smnIOMMU_L1_IOAGR_L1_PERF_COUNT_0_DEFAULT 0x00000000 |
10375 | #define smnIOMMU_L1_IOAGR_L1_PERF_COUNT_1_DEFAULT 0x00000000 |
10376 | #define smnIOMMU_L1_IOAGR_L1_PERF_CNTL_B_DEFAULT 0x00000000 |
10377 | #define smnIOMMU_L1_IOAGR_L1_PERF_COUNT_B0_DEFAULT 0x00000000 |
10378 | #define smnIOMMU_L1_IOAGR_L1_PERF_COUNT_B1_DEFAULT 0x00000000 |
10379 | #define smnIOMMU_L1_IOAGR_L1_SB_LOCATION_DEFAULT 0x00000000 |
10380 | #define smnIOMMU_L1_IOAGR_L1_CNTRL_0_DEFAULT 0x00100a0c |
10381 | #define smnIOMMU_L1_IOAGR_L1_CNTRL_1_DEFAULT 0x00000400 |
10382 | #define smnIOMMU_L1_IOAGR_L1_CNTRL_2_DEFAULT 0x32000008 |
10383 | #define smnIOMMU_L1_IOAGR_L1_CNTRL_3_DEFAULT 0x0000c350 |
10384 | #define smnIOMMU_L1_IOAGR_L1_BANK_SEL_0_DEFAULT 0x00000001 |
10385 | #define smnIOMMU_L1_IOAGR_L1_BANK_DISABLE_0_DEFAULT 0x00000000 |
10386 | #define smnIOMMU_L1_IOAGR_L1_WQ_STATUS_0_DEFAULT 0x00000000 |
10387 | #define smnIOMMU_L1_IOAGR_L1_WQ_STATUS_1_DEFAULT 0x00000000 |
10388 | #define smnIOMMU_L1_IOAGR_L1_WQ_STATUS_2_DEFAULT 0x00000000 |
10389 | #define smnIOMMU_L1_IOAGR_L1_WQ_STATUS_3_DEFAULT 0x00000000 |
10390 | #define smnIOMMU_L1_IOAGR_L1_FEATURE_CNTRL_DEFAULT 0x00000000 |
10391 | #define smnIOMMU_L1_IOAGR_L1_PGMEM_CTRL_5_DEFAULT 0x00000001 |
10392 | #define smnIOMMU_L1_IOAGR_L1_PGMEM_CTRL_6_DEFAULT 0x00000001 |
10393 | #define smnIOMMU_L1_IOAGR_L1_PGMEM_CTRL_7_DEFAULT 0x00000001 |
10394 | #define smnIOMMU_L1_IOAGR_L1_PGMEM_CTRL_8_DEFAULT 0x00000006 |
10395 | #define smnIOMMU_L1_IOAGR_L1_PGMEM_CTRL_9_DEFAULT 0x00000001 |
10396 | #define smnIOMMU_L1_IOAGR_L1_PGMEM_CTRL_10_DEFAULT 0x00000006 |
10397 | #define smnIOMMU_L1_IOAGR_L1_CNTRL_4_DEFAULT 0x24000000 |
10398 | #define smnIOMMU_L1_IOAGR_L1_CLKCNTRL_0_DEFAULT 0x00020000 |
10399 | #define smnIOMMU_L1_IOAGR_L1_SDP_CLKREQ_CNTRL_DEFAULT 0x00000000 |
10400 | #define smnIOMMU_L1_IOAGR_L1_GUEST_ADDR_CNTRL_DEFAULT 0x00000000 |
10401 | #define smnIOMMU_L1_IOAGR_L1_FEATURE_SUP_CNTRL_DEFAULT 0x0000001f |
10402 | #define smnIOMMU_L1_IOAGR_L1_CNTRL_5_DEFAULT 0x00000000 |
10403 | #define smnIOMMU_L1_IOAGR_L1_PGMEM_CTRL_1_DEFAULT 0x00000000 |
10404 | #define smnIOMMU_L1_IOAGR_L1_PGMEM_CTRL_2_DEFAULT 0x00000000 |
10405 | #define smnIOMMU_L1_IOAGR_L1_PGMEM_CTRL_3_DEFAULT 0x00000000 |
10406 | #define smnIOMMU_L1_IOAGR_L1_PGMEM_CTRL_4_DEFAULT 0x00000000 |
10407 | #define smnIOMMU_L1_IOAGR_IOMMU_PGSLV_CONTROL_DEFAULT 0x0000000b |
10408 | #define smnIOMMU_L1_IOAGR_L1_ATS_RESP_CTRL_0_DEFAULT 0x00000000 |
10409 | #define smnIOMMU_L1_IOAGR_L1_IOHC_DmaReq_Stall_Control_DEFAULT 0x00000000 |
10410 | #define smnIOMMU_L1_IOAGR_CLIENT_L1_DmaRsp_Stall_Control_DEFAULT 0x00000000 |
10411 | #define smnIOMMU_L1_IOAGR_L1_CLIENT_HostReq_Stall_Control_DEFAULT 0x00000000 |
10412 | #define smnIOMMU_L1_IOAGR_IOHC_L1_HostRsp_Stall_Control_DEFAULT 0x00000000 |
10413 | #define smnIOMMU_L1_IOAGR_L1_SDP_MAXCRED_0_DEFAULT 0x00000008 |
10414 | #define smnIOMMU_L1_IOAGR_L1_ECO_CNTRL_DEFAULT 0x00000000 |
10415 | |
10416 | |
10417 | // addressBlock: nbio_iohub_iommu_l1shdw_IOAGR_l1shdw |
10418 | #define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_BASE_0_DEFAULT 0x00000000 |
10419 | #define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_0_DEFAULT 0x00000400 |
10420 | #define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_CNTRL_1_DEFAULT 0x00000000 |
10421 | #define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_BASE_0_DEFAULT 0x00000000 |
10422 | #define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_BASE_1_DEFAULT 0x00000000 |
10423 | #define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_LIM_0_DEFAULT 0x00000000 |
10424 | #define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_EXCL_LIM_1_DEFAULT 0x00000000 |
10425 | #define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_1_BASE_0_DEFAULT 0x00000000 |
10426 | #define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_2_BASE_0_DEFAULT 0x00000000 |
10427 | #define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_3_BASE_0_DEFAULT 0x00000000 |
10428 | #define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_4_BASE_0_DEFAULT 0x00000000 |
10429 | #define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_5_BASE_0_DEFAULT 0x00000000 |
10430 | #define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_6_BASE_0_DEFAULT 0x00000000 |
10431 | #define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVTBL_7_BASE_0_DEFAULT 0x00000000 |
10432 | #define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_0_DEFAULT 0x00000000 |
10433 | #define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_PASID_BANK_LOCK_1_DEFAULT 0x00000000 |
10434 | #define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_0_DEFAULT 0x00000000 |
10435 | #define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_1_DEFAULT 0x00000000 |
10436 | #define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_0_DEFAULT 0x00000000 |
10437 | #define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_1_DEFAULT 0x00000000 |
10438 | #define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0_DEFAULT 0x00000000 |
10439 | #define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0_DEFAULT 0x00000000 |
10440 | #define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_1_DEFAULT 0x00000000 |
10441 | #define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0_DEFAULT 0x00000000 |
10442 | #define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_1_DEFAULT 0x00000000 |
10443 | #define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0_DEFAULT 0x00000000 |
10444 | #define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_1_DEFAULT 0x00000000 |
10445 | #define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0_DEFAULT 0x00000000 |
10446 | #define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0_DEFAULT 0x00000000 |
10447 | #define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_1_DEFAULT 0x00000000 |
10448 | #define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0_DEFAULT 0x00000000 |
10449 | #define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_1_DEFAULT 0x00000000 |
10450 | #define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0_DEFAULT 0x00000000 |
10451 | #define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_1_DEFAULT 0x00000000 |
10452 | #define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0_DEFAULT 0x00000000 |
10453 | #define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0_DEFAULT 0x00000000 |
10454 | #define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_1_DEFAULT 0x00000000 |
10455 | #define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0_DEFAULT 0x00000000 |
10456 | #define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_1_DEFAULT 0x00000000 |
10457 | #define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0_DEFAULT 0x00000000 |
10458 | #define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_1_DEFAULT 0x00000000 |
10459 | #define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0_DEFAULT 0x00000000 |
10460 | #define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0_DEFAULT 0x00000000 |
10461 | #define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_1_DEFAULT 0x00000000 |
10462 | #define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0_DEFAULT 0x00000000 |
10463 | #define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_1_DEFAULT 0x00000000 |
10464 | #define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0_DEFAULT 0x00000000 |
10465 | #define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_1_DEFAULT 0x00000000 |
10466 | #define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0_DEFAULT 0x00000000 |
10467 | #define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0_DEFAULT 0x00000000 |
10468 | #define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_1_DEFAULT 0x00000000 |
10469 | #define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0_DEFAULT 0x00000000 |
10470 | #define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_1_DEFAULT 0x00000000 |
10471 | #define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0_DEFAULT 0x00000000 |
10472 | #define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_1_DEFAULT 0x00000000 |
10473 | #define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0_DEFAULT 0x00000000 |
10474 | #define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0_DEFAULT 0x00000000 |
10475 | #define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_1_DEFAULT 0x00000000 |
10476 | #define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0_DEFAULT 0x00000000 |
10477 | #define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_1_DEFAULT 0x00000000 |
10478 | #define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0_DEFAULT 0x00000000 |
10479 | #define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_1_DEFAULT 0x00000000 |
10480 | #define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0_DEFAULT 0x00000000 |
10481 | #define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0_DEFAULT 0x00000000 |
10482 | #define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_1_DEFAULT 0x00000000 |
10483 | #define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0_DEFAULT 0x00000000 |
10484 | #define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_1_DEFAULT 0x00000000 |
10485 | #define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0_DEFAULT 0x00000000 |
10486 | #define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_1_DEFAULT 0x00000000 |
10487 | #define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0_DEFAULT 0x00000000 |
10488 | #define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0_DEFAULT 0x00000000 |
10489 | #define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_1_DEFAULT 0x00000000 |
10490 | #define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0_DEFAULT 0x00000000 |
10491 | #define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_1_DEFAULT 0x00000000 |
10492 | #define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0_DEFAULT 0x00000000 |
10493 | #define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_1_DEFAULT 0x00000000 |
10494 | #define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_CAP_BASE_LO_DEFAULT 0x00000000 |
10495 | #define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_CAP_MISC_DEFAULT 0x00000000 |
10496 | #define smnIOMMU_L1SHDW_IOAGR_SHDWL1_IOMMU_CAP_MISC_1_DEFAULT 0x00000080 |
10497 | |
10498 | |
10499 | // addressBlock: nbio_iohub_iommu_l1psp_IOAGR_l1psp |
10500 | #define smnIOMMU_L1PSP_IOAGR_L1PSP_ERR_REP_CNTRL_DEFAULT 0x00000000 |
10501 | #define smnIOMMU_L1PSP_IOAGR_L1PSP_CPD_STATUS_0_DEFAULT 0x00000000 |
10502 | #define smnIOMMU_L1PSP_IOAGR_L1PSP_CPD_STATUS_1_DEFAULT 0x00000000 |
10503 | #define smnIOMMU_L1PSP_IOAGR_L1PSP_CPD_REQADDR_0_DEFAULT 0x00000000 |
10504 | #define smnIOMMU_L1PSP_IOAGR_L1PSP_CPD_REQADDR_1_DEFAULT 0x00000000 |
10505 | #define smnIOMMU_L1PSP_IOAGR_L1PSP_REQ_CNTRL_DEFAULT 0x00000000 |
10506 | |
10507 | |
10508 | // addressBlock: nbio_iohub_iommu_l2a_l2acfg |
10509 | #define smnL2_PERF_CNTL_0_DEFAULT 0x00000000 |
10510 | #define smnL2_PERF_COUNT_0_DEFAULT 0x00000000 |
10511 | #define smnL2_PERF_COUNT_1_DEFAULT 0x00000000 |
10512 | #define smnL2_PERF_CNTL_1_DEFAULT 0x00000000 |
10513 | #define smnL2_PERF_COUNT_2_DEFAULT 0x00000000 |
10514 | #define smnL2_PERF_COUNT_3_DEFAULT 0x00000000 |
10515 | #define smnL2_STATUS_0_DEFAULT 0x00000000 |
10516 | #define smnL2_CONTROL_0_DEFAULT 0x00100000 |
10517 | #define smnL2_CONTROL_1_DEFAULT 0x00010808 |
10518 | #define smnL2_DTC_CONTROL_DEFAULT 0x00000200 |
10519 | #define smnL2_DTC_HASH_CONTROL_DEFAULT 0x00000000 |
10520 | #define smnL2_DTC_WAY_CONTROL_DEFAULT 0x00000000 |
10521 | #define smnL2_ITC_CONTROL_DEFAULT 0x00000200 |
10522 | #define smnL2_ITC_HASH_CONTROL_DEFAULT 0x00000000 |
10523 | #define smnL2_ITC_WAY_CONTROL_DEFAULT 0x00000000 |
10524 | #define smnL2_PTC_A_CONTROL_DEFAULT 0x00000200 |
10525 | #define smnL2_PTC_A_HASH_CONTROL_DEFAULT 0x00000000 |
10526 | #define smnL2_PTC_A_WAY_CONTROL_DEFAULT 0x00000000 |
10527 | #define smnL2_CREDIT_CONTROL_2_DEFAULT 0x04000000 |
10528 | #define smnL2A_UPDATE_FILTER_CNTL_DEFAULT 0x00000007 |
10529 | #define smnL2_ERR_RULE_CONTROL_3_DEFAULT 0x00000000 |
10530 | #define smnL2_ERR_RULE_CONTROL_4_DEFAULT 0x00000000 |
10531 | #define smnL2_ERR_RULE_CONTROL_5_DEFAULT 0x00000000 |
10532 | #define smnL2_L2A_CK_GATE_CONTROL_DEFAULT 0x00000057 |
10533 | #define smnL2_L2A_PGSIZE_CONTROL_DEFAULT 0x00000101 |
10534 | #define smnL2_L2A_MEMPWR_GATE_1_DEFAULT 0x00000000 |
10535 | #define smnL2_L2A_MEMPWR_GATE_2_DEFAULT 0x00000064 |
10536 | #define smnL2_L2A_MEMPWR_GATE_3_DEFAULT 0x00000064 |
10537 | #define smnL2_L2A_MEMPWR_GATE_4_DEFAULT 0x0000044c |
10538 | #define smnL2_L2A_MEMPWR_GATE_5_DEFAULT 0x00000001 |
10539 | #define smnL2_L2A_MEMPWR_GATE_6_DEFAULT 0x00000001 |
10540 | #define smnL2_L2A_MEMPWR_GATE_7_DEFAULT 0x00000001 |
10541 | #define smnL2_L2A_MEMPWR_GATE_8_DEFAULT 0x00000006 |
10542 | #define smnL2_L2A_MEMPWR_GATE_9_DEFAULT 0x00000001 |
10543 | #define smnL2_PWRGATE_CNTRL_REG_0_DEFAULT 0x000003e8 |
10544 | #define smnL2_L2A_MEMPWR_GATE_10_DEFAULT 0x00000006 |
10545 | #define smnL2_PWRGATE_CNTRL_REG_3_DEFAULT 0x00000000 |
10546 | #define smnL2_ECO_CNTRL_0_DEFAULT 0x00000000 |
10547 | |
10548 | |
10549 | // addressBlock: nbio_iohub_iommu_l2ashdw_l2ashdw |
10550 | #define smnSHDWL2A_IOMMU_MMIO_DEVTBL_BASE_0_DEFAULT 0x00000000 |
10551 | #define smnSHDWL2A_IOMMU_MMIO_CNTRL_0_DEFAULT 0x00000000 |
10552 | #define smnSHDWL2A_IOMMU_MMIO_CNTRL_1_DEFAULT 0x00000000 |
10553 | #define smnSHDWL2A_IOMMU_MMIO_EXCL_BASE_0_DEFAULT 0x00000000 |
10554 | #define smnSHDWL2A_IOMMU_MMIO_EXCL_BASE_1_DEFAULT 0x00000000 |
10555 | #define smnSHDWL2A_IOMMU_MMIO_EXCL_LIM_0_DEFAULT 0x00000000 |
10556 | #define smnSHDWL2A_IOMMU_MMIO_EXCL_LIM_1_DEFAULT 0x00000000 |
10557 | #define smnSHDWL2A_SMI_FILTER_REGISTER_0_0_DEFAULT 0x00000000 |
10558 | #define smnSHDWL2A_SMI_FILTER_REGISTER_1_0_DEFAULT 0x00000000 |
10559 | #define smnSHDWL2A_SMI_FILTER_REGISTER_2_0_DEFAULT 0x00000000 |
10560 | #define smnSHDWL2A_SMI_FILTER_REGISTER_3_0_DEFAULT 0x00000000 |
10561 | #define smnSHDWL2A_IOMMU_MMIO_DEVTBL_1_BASE_0_DEFAULT 0x00000000 |
10562 | #define smnSHDWL2A_IOMMU_MMIO_DEVTBL_2_BASE_0_DEFAULT 0x00000000 |
10563 | #define smnSHDWL2A_IOMMU_MMIO_DEVTBL_3_BASE_0_DEFAULT 0x00000000 |
10564 | #define smnSHDWL2A_IOMMU_MMIO_DEVTBL_4_BASE_0_DEFAULT 0x00000000 |
10565 | #define smnSHDWL2A_IOMMU_MMIO_DEVTBL_5_BASE_0_DEFAULT 0x00000000 |
10566 | #define smnSHDWL2A_IOMMU_MMIO_DEVTBL_6_BASE_0_DEFAULT 0x00000000 |
10567 | #define smnSHDWL2A_IOMMU_MMIO_DEVTBL_7_BASE_0_DEFAULT 0x00000000 |
10568 | #define smnSHDWL2A_IOMMU_CAP_BASE_LO_DEFAULT 0x00000000 |
10569 | #define smnSHDWL2A_IOMMU_CAP_MISC_DEFAULT 0x00000000 |
10570 | #define smnSHDWL2A_IOMMU_CAP_MISC_1_DEFAULT 0x00000080 |
10571 | #define smnSHDWL2A_IOMMU_CONTROL_W_DEFAULT 0x00000300 |
10572 | #define smnSHDWL2A_IOMMU_MMIO_CONTROL0_W_DEFAULT 0x00001a1a |
10573 | #define smnSHDWL2A_IOMMU_MMIO_CONTROL1_W_DEFAULT 0x000100cf |
10574 | |
10575 | |
10576 | // addressBlock: nbio_iohub_smmu_mmio_smmummiocfg |
10577 | #define smnSMMU_IDR0_DEFAULT 0x00000000 |
10578 | #define smnSMMU_IDR1_DEFAULT 0x00000000 |
10579 | #define smnSMMU_IDR2_DEFAULT 0x00000000 |
10580 | #define smnSMMU_IDR3_DEFAULT 0x00000000 |
10581 | #define smnSMMU_IDR4_DEFAULT 0x00000000 |
10582 | #define smnSMMU_IDR5_DEFAULT 0x00000072 |
10583 | #define smnSMMU_IIDR_DEFAULT 0x0000043b |
10584 | #define smnSMMU_AIDR_DEFAULT 0x00000000 |
10585 | #define smnSMMU_CR0_DEFAULT 0x00000000 |
10586 | #define smnSMMU_CR0ACK_DEFAULT 0x00000000 |
10587 | #define smnSMMU_CR2_DEFAULT 0x00000000 |
10588 | #define smnSMMU_GBPA_DEFAULT 0x00000000 |
10589 | #define smnSMMU_STRTAB_BASE_HI_DEFAULT 0x00000000 |
10590 | #define smnSMMU_STRTAB_BASE_LO_DEFAULT 0x00000000 |
10591 | #define smnSMMU_STRTAB_BASE_CFG_DEFAULT 0x00000000 |
10592 | |
10593 | |
10594 | // addressBlock: nbio_iohub_nb_ioagrcfg_ioagr_cfgdec |
10595 | #define smnIOAGR_GLUE_CG_LCLK_CTRL_0_DEFAULT 0xffc00100 |
10596 | #define smnIOAGR_GLUE_CG_LCLK_CTRL_1_DEFAULT 0xffc00000 |
10597 | #define smnIOAGR_REQDECODE_OVERRIDE_DEFAULT 0x00000000 |
10598 | #define smnIOAGR_RSPDECODE_OVERRIDE_DEFAULT 0x00000000 |
10599 | #define smnIOAGR_USERBIT_BYPASS_DEFAULT 0x00000000 |
10600 | #define smnIOAGR_SDP_PORT_CONTROL_DEFAULT 0x0000000f |
10601 | #define smnIOAGR_PERF_CNTL_DEFAULT 0x00000000 |
10602 | #define smnIOAGR_PERF_COUNT0_DEFAULT 0x00000000 |
10603 | #define smnIOAGR_PERF_COUNT0_UPPER_DEFAULT 0x00000000 |
10604 | #define smnIOAGR_PERF_COUNT1_DEFAULT 0x00000000 |
10605 | #define smnIOAGR_PERF_COUNT1_UPPER_DEFAULT 0x00000000 |
10606 | #define smnIOAGR_PERF_COUNT2_DEFAULT 0x00000000 |
10607 | #define smnIOAGR_PERF_COUNT2_UPPER_DEFAULT 0x00000000 |
10608 | #define smnIOAGR_PERF_COUNT3_DEFAULT 0x00000000 |
10609 | #define smnIOAGR_PERF_COUNT3_UPPER_DEFAULT 0x00000000 |
10610 | #define smnIOAGR_PGMST_CNTL_DEFAULT 0x0000000f |
10611 | #define smnIOAGR_PGSLV_CNTL_DEFAULT 0x00000004 |
10612 | #define smnIOAGR_SION_S0_Client0_Req_BurstTarget_Lower_DEFAULT 0x00000000 |
10613 | #define smnIOAGR_SION_S0_Client0_Req_BurstTarget_Upper_DEFAULT 0x00000000 |
10614 | #define smnIOAGR_SION_S0_Client0_Req_TimeSlot_Lower_DEFAULT 0x00000000 |
10615 | #define smnIOAGR_SION_S0_Client0_Req_TimeSlot_Upper_DEFAULT 0x00000000 |
10616 | #define smnIOAGR_SION_S0_Client0_RdRsp_BurstTarget_Lower_DEFAULT 0x02020202 |
10617 | #define smnIOAGR_SION_S0_Client0_RdRsp_BurstTarget_Upper_DEFAULT 0x02020202 |
10618 | #define smnIOAGR_SION_S0_Client0_RdRsp_TimeSlot_Lower_DEFAULT 0x00000000 |
10619 | #define smnIOAGR_SION_S0_Client0_RdRsp_TimeSlot_Upper_DEFAULT 0x00000000 |
10620 | #define smnIOAGR_SION_S0_Client0_WrRsp_BurstTarget_Lower_DEFAULT 0x00000000 |
10621 | #define smnIOAGR_SION_S0_Client0_WrRsp_BurstTarget_Upper_DEFAULT 0x00000000 |
10622 | #define smnIOAGR_SION_S0_Client0_WrRsp_TimeSlot_Lower_DEFAULT 0x00000000 |
10623 | #define smnIOAGR_SION_S0_Client0_WrRsp_TimeSlot_Upper_DEFAULT 0x00000000 |
10624 | #define smnIOAGR_SION_S1_Client0_Req_BurstTarget_Lower_DEFAULT 0x00000000 |
10625 | #define smnIOAGR_SION_S1_Client0_Req_BurstTarget_Upper_DEFAULT 0x00000000 |
10626 | #define smnIOAGR_SION_S1_Client0_Req_TimeSlot_Lower_DEFAULT 0x00000000 |
10627 | #define smnIOAGR_SION_S1_Client0_Req_TimeSlot_Upper_DEFAULT 0x00000000 |
10628 | #define smnIOAGR_SION_S1_Client0_RdRsp_BurstTarget_Lower_DEFAULT 0x02020202 |
10629 | #define smnIOAGR_SION_S1_Client0_RdRsp_BurstTarget_Upper_DEFAULT 0x02020202 |
10630 | #define smnIOAGR_SION_S1_Client0_RdRsp_TimeSlot_Lower_DEFAULT 0x00000000 |
10631 | #define smnIOAGR_SION_S1_Client0_RdRsp_TimeSlot_Upper_DEFAULT 0x00000000 |
10632 | #define smnIOAGR_SION_S1_Client0_WrRsp_BurstTarget_Lower_DEFAULT 0x00000000 |
10633 | #define smnIOAGR_SION_S1_Client0_WrRsp_BurstTarget_Upper_DEFAULT 0x00000000 |
10634 | #define smnIOAGR_SION_S1_Client0_WrRsp_TimeSlot_Lower_DEFAULT 0x00000000 |
10635 | #define smnIOAGR_SION_S1_Client0_WrRsp_TimeSlot_Upper_DEFAULT 0x00000000 |
10636 | #define smnIOAGR_SION_Client0_ReqPoolCredit_Alloc_Lower_DEFAULT 0x01010401 |
10637 | #define smnIOAGR_SION_Client0_ReqPoolCredit_Alloc_Upper_DEFAULT 0x01010101 |
10638 | #define smnIOAGR_SION_Client0_DataPoolCredit_Alloc_Lower_DEFAULT 0x02020902 |
10639 | #define smnIOAGR_SION_Client0_DataPoolCredit_Alloc_Upper_DEFAULT 0x02020202 |
10640 | #define smnIOAGR_SION_Client0_RdRspPoolCredit_Alloc_Lower_DEFAULT 0x00000001 |
10641 | #define smnIOAGR_SION_Client0_RdRspPoolCredit_Alloc_Upper_DEFAULT 0x01010101 |
10642 | #define smnIOAGR_SION_Client0_WrRspPoolCredit_Alloc_Lower_DEFAULT 0x01010101 |
10643 | #define smnIOAGR_SION_Client0_WrRspPoolCredit_Alloc_Upper_DEFAULT 0x01010101 |
10644 | #define smnIOAGR_SION_S0_Client1_Req_BurstTarget_Lower_DEFAULT 0x00000000 |
10645 | #define smnIOAGR_SION_S0_Client1_Req_BurstTarget_Upper_DEFAULT 0x00000000 |
10646 | #define smnIOAGR_SION_S0_Client1_Req_TimeSlot_Lower_DEFAULT 0x00000000 |
10647 | #define smnIOAGR_SION_S0_Client1_Req_TimeSlot_Upper_DEFAULT 0x00000000 |
10648 | #define smnIOAGR_SION_S0_Client1_RdRsp_BurstTarget_Lower_DEFAULT 0x02020202 |
10649 | #define smnIOAGR_SION_S0_Client1_RdRsp_BurstTarget_Upper_DEFAULT 0x02020202 |
10650 | #define smnIOAGR_SION_S0_Client1_RdRsp_TimeSlot_Lower_DEFAULT 0x00000000 |
10651 | #define smnIOAGR_SION_S0_Client1_RdRsp_TimeSlot_Upper_DEFAULT 0x00000000 |
10652 | #define smnIOAGR_SION_S0_Client1_WrRsp_BurstTarget_Lower_DEFAULT 0x00000000 |
10653 | #define smnIOAGR_SION_S0_Client1_WrRsp_BurstTarget_Upper_DEFAULT 0x00000000 |
10654 | #define smnIOAGR_SION_S0_Client1_WrRsp_TimeSlot_Lower_DEFAULT 0x00000000 |
10655 | #define smnIOAGR_SION_S0_Client1_WrRsp_TimeSlot_Upper_DEFAULT 0x00000000 |
10656 | #define smnIOAGR_SION_S1_Client1_Req_BurstTarget_Lower_DEFAULT 0x00000000 |
10657 | #define smnIOAGR_SION_S1_Client1_Req_BurstTarget_Upper_DEFAULT 0x00000000 |
10658 | #define smnIOAGR_SION_S1_Client1_Req_TimeSlot_Lower_DEFAULT 0x00000000 |
10659 | #define smnIOAGR_SION_S1_Client1_Req_TimeSlot_Upper_DEFAULT 0x00000000 |
10660 | #define smnIOAGR_SION_S1_Client1_RdRsp_BurstTarget_Lower_DEFAULT 0x02020202 |
10661 | #define smnIOAGR_SION_S1_Client1_RdRsp_BurstTarget_Upper_DEFAULT 0x02020202 |
10662 | #define smnIOAGR_SION_S1_Client1_RdRsp_TimeSlot_Lower_DEFAULT 0x00000000 |
10663 | #define smnIOAGR_SION_S1_Client1_RdRsp_TimeSlot_Upper_DEFAULT 0x00000000 |
10664 | #define smnIOAGR_SION_S1_Client1_WrRsp_BurstTarget_Lower_DEFAULT 0x00000000 |
10665 | #define smnIOAGR_SION_S1_Client1_WrRsp_BurstTarget_Upper_DEFAULT 0x00000000 |
10666 | #define smnIOAGR_SION_S1_Client1_WrRsp_TimeSlot_Lower_DEFAULT 0x00000000 |
10667 | #define smnIOAGR_SION_S1_Client1_WrRsp_TimeSlot_Upper_DEFAULT 0x00000000 |
10668 | #define smnIOAGR_SION_Client1_ReqPoolCredit_Alloc_Lower_DEFAULT 0x01010101 |
10669 | #define smnIOAGR_SION_Client1_ReqPoolCredit_Alloc_Upper_DEFAULT 0x01010101 |
10670 | #define smnIOAGR_SION_Client1_DataPoolCredit_Alloc_Lower_DEFAULT 0x02020202 |
10671 | #define smnIOAGR_SION_Client1_DataPoolCredit_Alloc_Upper_DEFAULT 0x02020202 |
10672 | #define smnIOAGR_SION_Client1_RdRspPoolCredit_Alloc_Lower_DEFAULT 0x00000001 |
10673 | #define smnIOAGR_SION_Client1_RdRspPoolCredit_Alloc_Upper_DEFAULT 0x01010101 |
10674 | #define smnIOAGR_SION_Client1_WrRspPoolCredit_Alloc_Lower_DEFAULT 0x01010101 |
10675 | #define smnIOAGR_SION_Client1_WrRspPoolCredit_Alloc_Upper_DEFAULT 0x01010101 |
10676 | #define smnIOAGR_SION_S0_Client2_Req_BurstTarget_Lower_DEFAULT 0x00000000 |
10677 | #define smnIOAGR_SION_S0_Client2_Req_BurstTarget_Upper_DEFAULT 0x00000000 |
10678 | #define smnIOAGR_SION_S0_Client2_Req_TimeSlot_Lower_DEFAULT 0x00000000 |
10679 | #define smnIOAGR_SION_S0_Client2_Req_TimeSlot_Upper_DEFAULT 0x00000000 |
10680 | #define smnIOAGR_SION_S0_Client2_RdRsp_BurstTarget_Lower_DEFAULT 0x02020202 |
10681 | #define smnIOAGR_SION_S0_Client2_RdRsp_BurstTarget_Upper_DEFAULT 0x02020202 |
10682 | #define smnIOAGR_SION_S0_Client2_RdRsp_TimeSlot_Lower_DEFAULT 0x00000000 |
10683 | #define smnIOAGR_SION_S0_Client2_RdRsp_TimeSlot_Upper_DEFAULT 0x00000000 |
10684 | #define smnIOAGR_SION_S0_Client2_WrRsp_BurstTarget_Lower_DEFAULT 0x00000000 |
10685 | #define smnIOAGR_SION_S0_Client2_WrRsp_BurstTarget_Upper_DEFAULT 0x00000000 |
10686 | #define smnIOAGR_SION_S0_Client2_WrRsp_TimeSlot_Lower_DEFAULT 0x00000000 |
10687 | #define smnIOAGR_SION_S0_Client2_WrRsp_TimeSlot_Upper_DEFAULT 0x00000000 |
10688 | #define smnIOAGR_SION_S1_Client2_Req_BurstTarget_Lower_DEFAULT 0x00000000 |
10689 | #define smnIOAGR_SION_S1_Client2_Req_BurstTarget_Upper_DEFAULT 0x00000000 |
10690 | #define smnIOAGR_SION_S1_Client2_Req_TimeSlot_Lower_DEFAULT 0x00000000 |
10691 | #define smnIOAGR_SION_S1_Client2_Req_TimeSlot_Upper_DEFAULT 0x00000000 |
10692 | #define smnIOAGR_SION_S1_Client2_RdRsp_BurstTarget_Lower_DEFAULT 0x02020202 |
10693 | #define smnIOAGR_SION_S1_Client2_RdRsp_BurstTarget_Upper_DEFAULT 0x02020202 |
10694 | #define smnIOAGR_SION_S1_Client2_RdRsp_TimeSlot_Lower_DEFAULT 0x00000000 |
10695 | #define smnIOAGR_SION_S1_Client2_RdRsp_TimeSlot_Upper_DEFAULT 0x00000000 |
10696 | #define smnIOAGR_SION_S1_Client2_WrRsp_BurstTarget_Lower_DEFAULT 0x00000000 |
10697 | #define smnIOAGR_SION_S1_Client2_WrRsp_BurstTarget_Upper_DEFAULT 0x00000000 |
10698 | #define smnIOAGR_SION_S1_Client2_WrRsp_TimeSlot_Lower_DEFAULT 0x00000000 |
10699 | #define smnIOAGR_SION_S1_Client2_WrRsp_TimeSlot_Upper_DEFAULT 0x00000000 |
10700 | #define smnIOAGR_SION_Client2_ReqPoolCredit_Alloc_Lower_DEFAULT 0x01010101 |
10701 | #define smnIOAGR_SION_Client2_ReqPoolCredit_Alloc_Upper_DEFAULT 0x01010101 |
10702 | #define smnIOAGR_SION_Client2_DataPoolCredit_Alloc_Lower_DEFAULT 0x02020202 |
10703 | #define smnIOAGR_SION_Client2_DataPoolCredit_Alloc_Upper_DEFAULT 0x02020202 |
10704 | #define smnIOAGR_SION_Client2_RdRspPoolCredit_Alloc_Lower_DEFAULT 0x00000001 |
10705 | #define smnIOAGR_SION_Client2_RdRspPoolCredit_Alloc_Upper_DEFAULT 0x01010101 |
10706 | #define smnIOAGR_SION_Client2_WrRspPoolCredit_Alloc_Lower_DEFAULT 0x01010101 |
10707 | #define smnIOAGR_SION_Client2_WrRspPoolCredit_Alloc_Upper_DEFAULT 0x01010101 |
10708 | #define smnIOAGR_SION_S0_Client3_Req_BurstTarget_Lower_DEFAULT 0x00000000 |
10709 | #define smnIOAGR_SION_S0_Client3_Req_BurstTarget_Upper_DEFAULT 0x00000000 |
10710 | #define smnIOAGR_SION_S0_Client3_Req_TimeSlot_Lower_DEFAULT 0x00000000 |
10711 | #define smnIOAGR_SION_S0_Client3_Req_TimeSlot_Upper_DEFAULT 0x00000000 |
10712 | #define smnIOAGR_SION_S0_Client3_RdRsp_BurstTarget_Lower_DEFAULT 0x02020202 |
10713 | #define smnIOAGR_SION_S0_Client3_RdRsp_BurstTarget_Upper_DEFAULT 0x02020202 |
10714 | #define smnIOAGR_SION_S0_Client3_RdRsp_TimeSlot_Lower_DEFAULT 0x00000000 |
10715 | #define smnIOAGR_SION_S0_Client3_RdRsp_TimeSlot_Upper_DEFAULT 0x00000000 |
10716 | #define smnIOAGR_SION_S0_Client3_WrRsp_BurstTarget_Lower_DEFAULT 0x00000000 |
10717 | #define smnIOAGR_SION_S0_Client3_WrRsp_BurstTarget_Upper_DEFAULT 0x00000000 |
10718 | #define smnIOAGR_SION_S0_Client3_WrRsp_TimeSlot_Lower_DEFAULT 0x00000000 |
10719 | #define smnIOAGR_SION_S0_Client3_WrRsp_TimeSlot_Upper_DEFAULT 0x00000000 |
10720 | #define smnIOAGR_SION_S1_Client3_Req_BurstTarget_Lower_DEFAULT 0x00000000 |
10721 | #define smnIOAGR_SION_S1_Client3_Req_BurstTarget_Upper_DEFAULT 0x00000000 |
10722 | #define smnIOAGR_SION_S1_Client3_Req_TimeSlot_Lower_DEFAULT 0x00000000 |
10723 | #define smnIOAGR_SION_S1_Client3_Req_TimeSlot_Upper_DEFAULT 0x00000000 |
10724 | #define smnIOAGR_SION_S1_Client3_RdRsp_BurstTarget_Lower_DEFAULT 0x02020202 |
10725 | #define smnIOAGR_SION_S1_Client3_RdRsp_BurstTarget_Upper_DEFAULT 0x02020202 |
10726 | #define smnIOAGR_SION_S1_Client3_RdRsp_TimeSlot_Lower_DEFAULT 0x00000000 |
10727 | #define smnIOAGR_SION_S1_Client3_RdRsp_TimeSlot_Upper_DEFAULT 0x00000000 |
10728 | #define smnIOAGR_SION_S1_Client3_WrRsp_BurstTarget_Lower_DEFAULT 0x00000000 |
10729 | #define smnIOAGR_SION_S1_Client3_WrRsp_BurstTarget_Upper_DEFAULT 0x00000000 |
10730 | #define smnIOAGR_SION_S1_Client3_WrRsp_TimeSlot_Lower_DEFAULT 0x00000000 |
10731 | #define smnIOAGR_SION_S1_Client3_WrRsp_TimeSlot_Upper_DEFAULT 0x00000000 |
10732 | #define smnIOAGR_SION_Client3_ReqPoolCredit_Alloc_Lower_DEFAULT 0x01010101 |
10733 | #define smnIOAGR_SION_Client3_ReqPoolCredit_Alloc_Upper_DEFAULT 0x01010101 |
10734 | #define smnIOAGR_SION_Client3_DataPoolCredit_Alloc_Lower_DEFAULT 0x02020202 |
10735 | #define smnIOAGR_SION_Client3_DataPoolCredit_Alloc_Upper_DEFAULT 0x02020202 |
10736 | #define smnIOAGR_SION_Client3_RdRspPoolCredit_Alloc_Lower_DEFAULT 0x00000001 |
10737 | #define smnIOAGR_SION_Client3_RdRspPoolCredit_Alloc_Upper_DEFAULT 0x01010101 |
10738 | #define smnIOAGR_SION_Client3_WrRspPoolCredit_Alloc_Lower_DEFAULT 0x01010101 |
10739 | #define smnIOAGR_SION_Client3_WrRspPoolCredit_Alloc_Upper_DEFAULT 0x01010101 |
10740 | #define smnIOAGR_SION_LiveLock_WatchDog_Threshold_DEFAULT 0x00000014 |
10741 | |
10742 | |
10743 | // addressBlock: nbio_sst0_sst_core_sstcorecfg |
10744 | #define smnSST_CORE0_SST_CLOCK_CTRL_DEFAULT 0x00014001 |
10745 | #define smnSST_CORE0_SST_ENABLE_CTRL_DEFAULT 0x00000000 |
10746 | #define smnSST_CORE0_SST_RSMU_HCID_DEFAULT 0x00002000 |
10747 | #define smnSST_CORE0_SST_RSMU_SIID_DEFAULT 0x00002000 |
10748 | #define smnSST_CORE0_SST_STATISTIC_0_DEFAULT 0x00000000 |
10749 | #define smnSST_CORE0_SION_CFG_S0_REQ_BURSTTARGET_LO_DEFAULT 0x00000000 |
10750 | #define smnSST_CORE0_SION_CFG_S0_REQ_BURSTTARGET_HI_DEFAULT 0x00000000 |
10751 | #define smnSST_CORE0_SION_CFG_S0_RDRSP_BURSTTARGET_LO_DEFAULT 0x00000000 |
10752 | #define smnSST_CORE0_SION_CFG_S0_RDRSP_BURSTTARGET_HI_DEFAULT 0x00000000 |
10753 | #define smnSST_CORE0_SION_CFG_S0_WRRSP_BURSTTARGET_LO_DEFAULT 0x00000000 |
10754 | #define smnSST_CORE0_SION_CFG_S0_WRRSP_BURSTTARGET_HI_DEFAULT 0x00000000 |
10755 | #define smnSST_CORE0_SION_CFG_S0_REQ_TIMESLOT_LO_DEFAULT 0x00000000 |
10756 | #define smnSST_CORE0_SION_CFG_S0_REQ_TIMESLOT_HI_DEFAULT 0x00000000 |
10757 | #define smnSST_CORE0_SION_CFG_S0_RDRSP_TIMESLOT_LO_DEFAULT 0x00000000 |
10758 | #define smnSST_CORE0_SION_CFG_S0_RDRSP_TIMESLOT_HI_DEFAULT 0x00000000 |
10759 | #define smnSST_CORE0_SION_CFG_S0_WRRSP_TIMESLOT_LO_DEFAULT 0x00000000 |
10760 | #define smnSST_CORE0_SION_CFG_S0_WRRSP_TIMESLOT_HI_DEFAULT 0x00000000 |
10761 | #define smnSST_CORE0_SION_WRAPPER_CFG_CG_OFF_HYSTERESIS_DEFAULT 0x000000ff |
10762 | #define smnSST_CORE0_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK_DEFAULT 0x00000000 |
10763 | #define smnSST_CORE0_CFG_SST_ReqPoolCredit_Alloc_LO_DEFAULT 0x00000000 |
10764 | #define smnSST_CORE0_CFG_SST_ReqPoolCredit_Alloc_HI_DEFAULT 0x00000000 |
10765 | #define smnSST_CORE0_CFG_SST_DataPoolCredit_Alloc_LO_DEFAULT 0x00000000 |
10766 | #define smnSST_CORE0_CFG_SST_DataPoolCredit_Alloc_HI_DEFAULT 0x00000000 |
10767 | #define smnSST_CORE0_CFG_SST_RdRspPoolCredit_Alloc_LO_DEFAULT 0x00000000 |
10768 | #define smnSST_CORE0_CFG_SST_RdRspPoolCredit_Alloc_HI_DEFAULT 0x00000000 |
10769 | #define smnSST_CORE0_CFG_SST_WrRspPoolCredit_Alloc_LO_DEFAULT 0x00000000 |
10770 | #define smnSST_CORE0_CFG_SST_WrRspPoolCredit_Alloc_HI_DEFAULT 0x00000000 |
10771 | #define smnSST_CORE0_SST_BACKDOOR0_DEFAULT 0x00000000 |
10772 | #define smnSST_CORE0_SST_BACKDOOR1_DEFAULT 0x00000000 |
10773 | #define smnSST_CORE0_SST_BACKDOOR2_DEFAULT 0x00000000 |
10774 | |
10775 | |
10776 | // addressBlock: nbio_sst1_sst_core_sstcorecfg |
10777 | #define smnSST_CORE1_SST_CLOCK_CTRL_DEFAULT 0x00014001 |
10778 | #define smnSST_CORE1_SST_ENABLE_CTRL_DEFAULT 0x00000000 |
10779 | #define smnSST_CORE1_SST_RSMU_HCID_DEFAULT 0x00002000 |
10780 | #define smnSST_CORE1_SST_RSMU_SIID_DEFAULT 0x00002000 |
10781 | #define smnSST_CORE1_SST_STATISTIC_0_DEFAULT 0x00000000 |
10782 | #define smnSST_CORE1_SION_CFG_S0_REQ_BURSTTARGET_LO_DEFAULT 0x00000000 |
10783 | #define smnSST_CORE1_SION_CFG_S0_REQ_BURSTTARGET_HI_DEFAULT 0x00000000 |
10784 | #define smnSST_CORE1_SION_CFG_S0_RDRSP_BURSTTARGET_LO_DEFAULT 0x00000000 |
10785 | #define smnSST_CORE1_SION_CFG_S0_RDRSP_BURSTTARGET_HI_DEFAULT 0x00000000 |
10786 | #define smnSST_CORE1_SION_CFG_S0_WRRSP_BURSTTARGET_LO_DEFAULT 0x00000000 |
10787 | #define smnSST_CORE1_SION_CFG_S0_WRRSP_BURSTTARGET_HI_DEFAULT 0x00000000 |
10788 | #define smnSST_CORE1_SION_CFG_S0_REQ_TIMESLOT_LO_DEFAULT 0x00000000 |
10789 | #define smnSST_CORE1_SION_CFG_S0_REQ_TIMESLOT_HI_DEFAULT 0x00000000 |
10790 | #define smnSST_CORE1_SION_CFG_S0_RDRSP_TIMESLOT_LO_DEFAULT 0x00000000 |
10791 | #define smnSST_CORE1_SION_CFG_S0_RDRSP_TIMESLOT_HI_DEFAULT 0x00000000 |
10792 | #define smnSST_CORE1_SION_CFG_S0_WRRSP_TIMESLOT_LO_DEFAULT 0x00000000 |
10793 | #define smnSST_CORE1_SION_CFG_S0_WRRSP_TIMESLOT_HI_DEFAULT 0x00000000 |
10794 | #define smnSST_CORE1_SION_WRAPPER_CFG_CG_OFF_HYSTERESIS_DEFAULT 0x000000ff |
10795 | #define smnSST_CORE1_SION_WRAPPER_CFG_SSTSION_GLUE_CG_LCLK_CTRL_SOFT_OVERRIDE_CLK_DEFAULT 0x00000000 |
10796 | #define smnSST_CORE1_CFG_SST_ReqPoolCredit_Alloc_LO_DEFAULT 0x00000000 |
10797 | #define smnSST_CORE1_CFG_SST_ReqPoolCredit_Alloc_HI_DEFAULT 0x00000000 |
10798 | #define smnSST_CORE1_CFG_SST_DataPoolCredit_Alloc_LO_DEFAULT 0x00000000 |
10799 | #define smnSST_CORE1_CFG_SST_DataPoolCredit_Alloc_HI_DEFAULT 0x00000000 |
10800 | #define smnSST_CORE1_CFG_SST_RdRspPoolCredit_Alloc_LO_DEFAULT 0x00000000 |
10801 | #define smnSST_CORE1_CFG_SST_RdRspPoolCredit_Alloc_HI_DEFAULT 0x00000000 |
10802 | #define smnSST_CORE1_CFG_SST_WrRspPoolCredit_Alloc_LO_DEFAULT 0x00000000 |
10803 | #define smnSST_CORE1_CFG_SST_WrRspPoolCredit_Alloc_HI_DEFAULT 0x00000000 |
10804 | #define smnSST_CORE1_SST_BACKDOOR0_DEFAULT 0x00000000 |
10805 | #define smnSST_CORE1_SST_BACKDOOR1_DEFAULT 0x00000000 |
10806 | #define smnSST_CORE1_SST_BACKDOOR2_DEFAULT 0x00000000 |
10807 | |
10808 | |
10809 | // addressBlock: nbio_iohub_iommu_l2mmio_l2mmiocfg |
10810 | #define mmIOMMU_MMIO_DEVTBL_BASE_0_DEFAULT 0x00000000 |
10811 | #define mmIOMMU_MMIO_DEVTBL_BASE_1_DEFAULT 0x00000000 |
10812 | #define mmIOMMU_MMIO_CMD_BASE_0_DEFAULT 0x00000000 |
10813 | #define mmIOMMU_MMIO_CMD_BASE_1_DEFAULT 0x08000000 |
10814 | #define mmIOMMU_MMIO_EVENT_BASE_0_DEFAULT 0x00000000 |
10815 | #define mmIOMMU_MMIO_EVENT_BASE_1_DEFAULT 0x08000000 |
10816 | #define mmIOMMU_MMIO_CNTRL_0_DEFAULT 0x00000400 |
10817 | #define mmIOMMU_MMIO_CNTRL_1_DEFAULT 0x00002200 |
10818 | #define mmIOMMU_MMIO_EXCL_BASE_0_DEFAULT 0x00000000 |
10819 | #define mmIOMMU_MMIO_EXCL_BASE_1_DEFAULT 0x00000000 |
10820 | #define mmIOMMU_MMIO_EXCL_LIM_0_DEFAULT 0x00000000 |
10821 | #define mmIOMMU_MMIO_EXCL_LIM_1_DEFAULT 0x00000000 |
10822 | #define mmIOMMU_MMIO_EFR_0_DEFAULT 0x00000000 |
10823 | #define mmIOMMU_MMIO_EFR_1_DEFAULT 0x00000000 |
10824 | #define mmIOMMU_MMIO_PPR_BASE_0_DEFAULT 0x00000000 |
10825 | #define mmIOMMU_MMIO_PPR_BASE_1_DEFAULT 0x08000000 |
10826 | #define mmIOMMU_MMIO_HW_ERR_UPPER_0_DEFAULT 0x00000000 |
10827 | #define mmIOMMU_MMIO_HW_ERR_UPPER_1_DEFAULT 0x00000000 |
10828 | #define mmIOMMU_MMIO_HW_ERR_LOWER_0_DEFAULT 0x00000000 |
10829 | #define mmIOMMU_MMIO_HW_ERR_LOWER_1_DEFAULT 0x00000000 |
10830 | #define mmIOMMU_MMIO_HW_ERR_STATUS_0_DEFAULT 0x00000000 |
10831 | #define mmIOMMU_MMIO_HW_ERR_STATUS_1_DEFAULT 0x00000000 |
10832 | #define mmSMI_FILTER_REGISTER_0_0_DEFAULT 0x00000000 |
10833 | #define mmSMI_FILTER_REGISTER_0_1_DEFAULT 0x00000000 |
10834 | #define mmSMI_FILTER_REGISTER_1_0_DEFAULT 0x00000000 |
10835 | #define mmSMI_FILTER_REGISTER_1_1_DEFAULT 0x00000000 |
10836 | #define mmSMI_FILTER_REGISTER_2_0_DEFAULT 0x00000000 |
10837 | #define mmSMI_FILTER_REGISTER_2_1_DEFAULT 0x00000000 |
10838 | #define mmSMI_FILTER_REGISTER_3_0_DEFAULT 0x00000000 |
10839 | #define mmSMI_FILTER_REGISTER_3_1_DEFAULT 0x00000000 |
10840 | #define mmIOMMU_MMIO_GA_LOG_BASE_0_DEFAULT 0x00000000 |
10841 | #define mmIOMMU_MMIO_GA_LOG_BASE_1_DEFAULT 0x08000000 |
10842 | #define mmIOMMU_MMIO_GA_LOG_TAILPTR_ADDR_0_DEFAULT 0x00000000 |
10843 | #define mmIOMMU_MMIO_GA_LOG_TAILPTR_ADDR_1_DEFAULT 0x00000000 |
10844 | #define mmIOMMU_MMIO_PPR_B_BASE_0_DEFAULT 0x00000000 |
10845 | #define mmIOMMU_MMIO_PPR_B_BASE_1_DEFAULT 0x08000000 |
10846 | #define mmIOMMU_MMIO_EVENT_B_BASE_0_DEFAULT 0x00000000 |
10847 | #define mmIOMMU_MMIO_EVENT_B_BASE_1_DEFAULT 0x08000000 |
10848 | #define mmIOMMU_MMIO_DEVTBL_1_BASE_0_DEFAULT 0x00000000 |
10849 | #define mmIOMMU_MMIO_DEVTBL_1_BASE_1_DEFAULT 0x00000000 |
10850 | #define mmIOMMU_MMIO_DEVTBL_2_BASE_0_DEFAULT 0x00000000 |
10851 | #define mmIOMMU_MMIO_DEVTBL_2_BASE_1_DEFAULT 0x00000000 |
10852 | #define mmIOMMU_MMIO_DEVTBL_3_BASE_0_DEFAULT 0x00000000 |
10853 | #define mmIOMMU_MMIO_DEVTBL_3_BASE_1_DEFAULT 0x00000000 |
10854 | #define mmIOMMU_MMIO_DEVTBL_4_BASE_0_DEFAULT 0x00000000 |
10855 | #define mmIOMMU_MMIO_DEVTBL_4_BASE_1_DEFAULT 0x00000000 |
10856 | #define mmIOMMU_MMIO_DEVTBL_5_BASE_0_DEFAULT 0x00000000 |
10857 | #define mmIOMMU_MMIO_DEVTBL_5_BASE_1_DEFAULT 0x00000000 |
10858 | #define mmIOMMU_MMIO_DEVTBL_6_BASE_0_DEFAULT 0x00000000 |
10859 | #define mmIOMMU_MMIO_DEVTBL_6_BASE_1_DEFAULT 0x00000000 |
10860 | #define mmIOMMU_MMIO_DEVTBL_7_BASE_0_DEFAULT 0x00000000 |
10861 | #define mmIOMMU_MMIO_DEVTBL_7_BASE_1_DEFAULT 0x00000000 |
10862 | #define mmIOMMU_MMIO_DSFX_DEFAULT 0x00000000 |
10863 | #define mmIOMMU_MMIO_DSCX_DEFAULT 0x00000000 |
10864 | #define mmIOMMU_MMIO_DSSX_DEFAULT 0x00000000 |
10865 | #define mmIOMMU_MMIO_CAP_MISC_DEFAULT 0x00000000 |
10866 | #define mmIOMMU_MMIO_CAP_MISC_1_DEFAULT 0x00000000 |
10867 | #define mmIOMMU_MMIO_MSI_CAP_DEFAULT 0x00000000 |
10868 | #define mmIOMMU_MMIO_MSI_ADDR_LO_DEFAULT 0x00000000 |
10869 | #define mmIOMMU_MMIO_MSI_ADDR_HI_DEFAULT 0x00000000 |
10870 | #define mmIOMMU_MMIO_MSI_DATA_DEFAULT 0x00000000 |
10871 | #define mmIOMMU_MMIO_MSI_MAPPING_CAP_DEFAULT 0x00000000 |
10872 | #define mmIOMMU_MMIO_CONTROL_W_DEFAULT 0x00000000 |
10873 | #define mmIOMMU_MARC_BASE_LO_0_DEFAULT 0x00000000 |
10874 | #define mmIOMMU_MARC_BASE_HI_0_DEFAULT 0x00000000 |
10875 | #define mmIOMMU_MARC_RELOC_LO_0_DEFAULT 0x00000000 |
10876 | #define mmIOMMU_MARC_RELOC_HI_0_DEFAULT 0x00000000 |
10877 | #define mmIOMMU_MARC_LEN_LO_0_DEFAULT 0x00000000 |
10878 | #define mmIOMMU_MARC_LEN_HI_0_DEFAULT 0x00000000 |
10879 | #define mmIOMMU_MARC_BASE_LO_1_DEFAULT 0x00000000 |
10880 | #define mmIOMMU_MARC_BASE_HI_1_DEFAULT 0x00000000 |
10881 | #define mmIOMMU_MARC_RELOC_LO_1_DEFAULT 0x00000000 |
10882 | #define mmIOMMU_MARC_RELOC_HI_1_DEFAULT 0x00000000 |
10883 | #define mmIOMMU_MARC_LEN_LO_1_DEFAULT 0x00000000 |
10884 | #define mmIOMMU_MARC_LEN_HI_1_DEFAULT 0x00000000 |
10885 | #define mmIOMMU_MARC_BASE_LO_2_DEFAULT 0x00000000 |
10886 | #define mmIOMMU_MARC_BASE_HI_2_DEFAULT 0x00000000 |
10887 | #define mmIOMMU_MARC_RELOC_LO_2_DEFAULT 0x00000000 |
10888 | #define mmIOMMU_MARC_RELOC_HI_2_DEFAULT 0x00000000 |
10889 | #define mmIOMMU_MARC_LEN_LO_2_DEFAULT 0x00000000 |
10890 | #define mmIOMMU_MARC_LEN_HI_2_DEFAULT 0x00000000 |
10891 | #define mmIOMMU_MARC_BASE_LO_3_DEFAULT 0x00000000 |
10892 | #define mmIOMMU_MARC_BASE_HI_3_DEFAULT 0x00000000 |
10893 | #define mmIOMMU_MARC_RELOC_LO_3_DEFAULT 0x00000000 |
10894 | #define mmIOMMU_MARC_RELOC_HI_3_DEFAULT 0x00000000 |
10895 | #define mmIOMMU_MARC_LEN_LO_3_DEFAULT 0x00000000 |
10896 | #define mmIOMMU_MARC_LEN_HI_3_DEFAULT 0x00000000 |
10897 | #define mmIOMMU_MMIO_CMD_BUF_HDPTR_0_DEFAULT 0x00000000 |
10898 | #define mmIOMMU_MMIO_CMD_BUF_HDPTR_1_DEFAULT 0x00000000 |
10899 | #define mmIOMMU_MMIO_CMD_BUF_TAILPTR_0_DEFAULT 0x00000000 |
10900 | #define mmIOMMU_MMIO_CMD_BUF_TAILPTR_1_DEFAULT 0x00000000 |
10901 | #define mmIOMMU_MMIO_EVENT_BUF_HDPTR_0_DEFAULT 0x00000000 |
10902 | #define mmIOMMU_MMIO_EVENT_BUF_HDPTR_1_DEFAULT 0x00000000 |
10903 | #define mmIOMMU_MMIO_EVENT_BUF_TAILPTR_0_DEFAULT 0x00000000 |
10904 | #define mmIOMMU_MMIO_EVENT_BUF_TAILPTR_1_DEFAULT 0x00000000 |
10905 | #define mmIOMMU_MMIO_STATUS_0_DEFAULT 0x00000000 |
10906 | #define mmIOMMU_MMIO_STATUS_1_DEFAULT 0x00000000 |
10907 | #define mmIOMMU_MMIO_PPR_BUF_HDPTR_0_DEFAULT 0x00000000 |
10908 | #define mmIOMMU_MMIO_PPR_BUF_HDPTR_1_DEFAULT 0x00000000 |
10909 | #define mmIOMMU_MMIO_PPR_BUF_TAILPTR_0_DEFAULT 0x00000000 |
10910 | #define mmIOMMU_MMIO_PPR_BUF_TAILPTR_1_DEFAULT 0x00000000 |
10911 | #define mmIOMMU_MMIO_GA_BUF_HDPTR_0_DEFAULT 0x00000000 |
10912 | #define mmIOMMU_MMIO_GA_BUF_HDPTR_1_DEFAULT 0x00000000 |
10913 | #define mmIOMMU_MMIO_GA_BUF_TAILPTR_0_DEFAULT 0x00000000 |
10914 | #define mmIOMMU_MMIO_GA_BUF_TAILPTR_1_DEFAULT 0x00000000 |
10915 | #define mmIOMMU_MMIO_PPR_B_BUF_HDPTR_0_DEFAULT 0x00000000 |
10916 | #define mmIOMMU_MMIO_PPR_B_BUF_HDPTR_1_DEFAULT 0x00000000 |
10917 | #define mmIOMMU_MMIO_PPR_B_BUF_TAILPTR_0_DEFAULT 0x00000000 |
10918 | #define mmIOMMU_MMIO_PPR_B_BUF_TAILPTR_1_DEFAULT 0x00000000 |
10919 | #define mmIOMMU_MMIO_EVENT_B_BUF_HDPTR_0_DEFAULT 0x00000000 |
10920 | #define mmIOMMU_MMIO_EVENT_B_BUF_HDPTR_1_DEFAULT 0x00000000 |
10921 | #define mmIOMMU_MMIO_EVENT_B_BUF_TAILPTR_0_DEFAULT 0x00000000 |
10922 | #define mmIOMMU_MMIO_EVENT_B_BUF_TAILPTR_1_DEFAULT 0x00000000 |
10923 | #define mmIOMMU_MMIO_PPR_AUTORESP_0_DEFAULT 0x00000000 |
10924 | #define mmIOMMU_MMIO_PPR_OVERFLOW_EARLY_0_DEFAULT 0x00000000 |
10925 | #define mmIOMMU_MMIO_PPR_B_OVERFLOW_EARLY_0_DEFAULT 0x00000000 |
10926 | #define mmIOMMU_MMIO_COUNTER_CONFIG_0_DEFAULT 0x00000000 |
10927 | #define mmIOMMU_MMIO_COUNTER_CONFIG_1_DEFAULT 0x00000000 |
10928 | #define mmIOMMU_MMIO_COUNTER_PASID_BANK_LOCK_0_DEFAULT 0x00000000 |
10929 | #define mmIOMMU_MMIO_COUNTER_PASID_BANK_LOCK_1_DEFAULT 0x00000000 |
10930 | #define mmIOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_0_DEFAULT 0x00000000 |
10931 | #define mmIOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_1_DEFAULT 0x00000000 |
10932 | #define mmIOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_0_DEFAULT 0x00000000 |
10933 | #define mmIOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_1_DEFAULT 0x00000000 |
10934 | #define mmIOMMU_MMIO_COUNTER_BANK_0_CNT_0_0_DEFAULT 0x00000000 |
10935 | #define mmIOMMU_MMIO_COUNTER_BANK_0_CNT_0_1_DEFAULT 0x00000000 |
10936 | #define mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0_DEFAULT 0x00000000 |
10937 | #define mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_1_DEFAULT 0x00000000 |
10938 | #define mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0_DEFAULT 0x00000000 |
10939 | #define mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_1_DEFAULT 0x00000000 |
10940 | #define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0_DEFAULT 0x00000000 |
10941 | #define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_1_DEFAULT 0x00000000 |
10942 | #define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0_DEFAULT 0x00000000 |
10943 | #define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_1_DEFAULT 0x00000000 |
10944 | #define mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_0_DEFAULT 0x00000000 |
10945 | #define mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_1_DEFAULT 0x00000000 |
10946 | #define mmIOMMU_MMIO_COUNTER_BANK_0_CNT_1_0_DEFAULT 0x00000000 |
10947 | #define mmIOMMU_MMIO_COUNTER_BANK_0_CNT_1_1_DEFAULT 0x00000000 |
10948 | #define mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0_DEFAULT 0x00000000 |
10949 | #define mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_1_DEFAULT 0x00000000 |
10950 | #define mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0_DEFAULT 0x00000000 |
10951 | #define mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_1_DEFAULT 0x00000000 |
10952 | #define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0_DEFAULT 0x00000000 |
10953 | #define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_1_DEFAULT 0x00000000 |
10954 | #define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0_DEFAULT 0x00000000 |
10955 | #define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_1_DEFAULT 0x00000000 |
10956 | #define mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_0_DEFAULT 0x00000000 |
10957 | #define mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_1_DEFAULT 0x00000000 |
10958 | #define mmIOMMU_MMIO_COUNTER_BANK_0_CNT_2_0_DEFAULT 0x00000000 |
10959 | #define mmIOMMU_MMIO_COUNTER_BANK_0_CNT_2_1_DEFAULT 0x00000000 |
10960 | #define mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0_DEFAULT 0x00000000 |
10961 | #define mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_1_DEFAULT 0x00000000 |
10962 | #define mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0_DEFAULT 0x00000000 |
10963 | #define mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_1_DEFAULT 0x00000000 |
10964 | #define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0_DEFAULT 0x00000000 |
10965 | #define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_1_DEFAULT 0x00000000 |
10966 | #define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0_DEFAULT 0x00000000 |
10967 | #define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_1_DEFAULT 0x00000000 |
10968 | #define mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_0_DEFAULT 0x00000000 |
10969 | #define mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_1_DEFAULT 0x00000000 |
10970 | #define mmIOMMU_MMIO_COUNTER_BANK_0_CNT_3_0_DEFAULT 0x00000000 |
10971 | #define mmIOMMU_MMIO_COUNTER_BANK_0_CNT_3_1_DEFAULT 0x00000000 |
10972 | #define mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0_DEFAULT 0x00000000 |
10973 | #define mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_1_DEFAULT 0x00000000 |
10974 | #define mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0_DEFAULT 0x00000000 |
10975 | #define mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_1_DEFAULT 0x00000000 |
10976 | #define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0_DEFAULT 0x00000000 |
10977 | #define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_1_DEFAULT 0x00000000 |
10978 | #define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0_DEFAULT 0x00000000 |
10979 | #define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_1_DEFAULT 0x00000000 |
10980 | #define mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_0_DEFAULT 0x00000000 |
10981 | #define mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_1_DEFAULT 0x00000000 |
10982 | #define mmIOMMU_MMIO_COUNTER_BANK_1_CNT_0_0_DEFAULT 0x00000000 |
10983 | #define mmIOMMU_MMIO_COUNTER_BANK_1_CNT_0_1_DEFAULT 0x00000000 |
10984 | #define mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0_DEFAULT 0x00000000 |
10985 | #define mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_1_DEFAULT 0x00000000 |
10986 | #define mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0_DEFAULT 0x00000000 |
10987 | #define mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_1_DEFAULT 0x00000000 |
10988 | #define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0_DEFAULT 0x00000000 |
10989 | #define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_1_DEFAULT 0x00000000 |
10990 | #define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0_DEFAULT 0x00000000 |
10991 | #define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_1_DEFAULT 0x00000000 |
10992 | #define mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_0_DEFAULT 0x00000000 |
10993 | #define mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_1_DEFAULT 0x00000000 |
10994 | #define mmIOMMU_MMIO_COUNTER_BANK_1_CNT_1_0_DEFAULT 0x00000000 |
10995 | #define mmIOMMU_MMIO_COUNTER_BANK_1_CNT_1_1_DEFAULT 0x00000000 |
10996 | #define mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0_DEFAULT 0x00000000 |
10997 | #define mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_1_DEFAULT 0x00000000 |
10998 | #define mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0_DEFAULT 0x00000000 |
10999 | #define mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_1_DEFAULT 0x00000000 |
11000 | #define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0_DEFAULT 0x00000000 |
11001 | #define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_1_DEFAULT 0x00000000 |
11002 | #define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0_DEFAULT 0x00000000 |
11003 | #define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_1_DEFAULT 0x00000000 |
11004 | #define mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_0_DEFAULT 0x00000000 |
11005 | #define mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_1_DEFAULT 0x00000000 |
11006 | #define mmIOMMU_MMIO_COUNTER_BANK_1_CNT_2_0_DEFAULT 0x00000000 |
11007 | #define mmIOMMU_MMIO_COUNTER_BANK_1_CNT_2_1_DEFAULT 0x00000000 |
11008 | #define mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0_DEFAULT 0x00000000 |
11009 | #define mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_1_DEFAULT 0x00000000 |
11010 | #define mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0_DEFAULT 0x00000000 |
11011 | #define mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_1_DEFAULT 0x00000000 |
11012 | #define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0_DEFAULT 0x00000000 |
11013 | #define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_1_DEFAULT 0x00000000 |
11014 | #define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0_DEFAULT 0x00000000 |
11015 | #define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_1_DEFAULT 0x00000000 |
11016 | #define mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_0_DEFAULT 0x00000000 |
11017 | #define mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_1_DEFAULT 0x00000000 |
11018 | #define mmIOMMU_MMIO_COUNTER_BANK_1_CNT_3_0_DEFAULT 0x00000000 |
11019 | #define mmIOMMU_MMIO_COUNTER_BANK_1_CNT_3_1_DEFAULT 0x00000000 |
11020 | #define mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0_DEFAULT 0x00000000 |
11021 | #define mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_1_DEFAULT 0x00000000 |
11022 | #define mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0_DEFAULT 0x00000000 |
11023 | #define mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_1_DEFAULT 0x00000000 |
11024 | #define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0_DEFAULT 0x00000000 |
11025 | #define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_1_DEFAULT 0x00000000 |
11026 | #define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0_DEFAULT 0x00000000 |
11027 | #define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_1_DEFAULT 0x00000000 |
11028 | #define mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_0_DEFAULT 0x00000000 |
11029 | #define mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_1_DEFAULT 0x00000000 |
11030 | |
11031 | |
11032 | // addressBlock: nbio_iohub_nb_nbcfg_nb_cfgdec |
11033 | #define smnNB_NBCFG2_NB_VENDOR_ID_DEFAULT 0x00000000 |
11034 | #define smnNB_NBCFG2_NB_DEVICE_ID_DEFAULT 0x00000000 |
11035 | #define smnNB_NBCFG2_NB_COMMAND_DEFAULT 0x00000000 |
11036 | #define smnNB_NBCFG2_NB_STATUS_DEFAULT 0x00000000 |
11037 | #define smnNB_NBCFG2_NB_REVISION_ID_DEFAULT 0x00000000 |
11038 | #define smnNB_NBCFG2_NB_REGPROG_INF_DEFAULT 0x00000000 |
11039 | #define smnNB_NBCFG2_NB_SUB_CLASS_DEFAULT 0x00000000 |
11040 | #define smnNB_NBCFG2_NB_BASE_CODE_DEFAULT 0x00000000 |
11041 | #define smnNB_NBCFG2_NB_CACHE_LINE_DEFAULT 0x00000000 |
11042 | #define smnNB_NBCFG2_NB_LATENCY_DEFAULT 0x00000000 |
11043 | #define 0x00000080 |
11044 | #define smnNB_NBCFG2_NB_ADAPTER_ID_DEFAULT 0x15d01022 |
11045 | #define smnNB_NBCFG2_NB_CAPABILITIES_PTR_DEFAULT 0x00000000 |
11046 | #define 0x00000080 |
11047 | #define smnNB_NBCFG2_NB_PCI_CTRL_DEFAULT 0x00000000 |
11048 | #define smnNB_NBCFG2_NB_ADAPTER_ID_W_DEFAULT 0x15d01022 |
11049 | #define smnNB_NBCFG2_NB_SMN_INDEX_EXTENSION_0_DEFAULT 0x00000000 |
11050 | #define smnNB_NBCFG2_NB_SMN_INDEX_0_DEFAULT 0x00000000 |
11051 | #define smnNB_NBCFG2_NB_SMN_DATA_0_DEFAULT 0x00000000 |
11052 | #define smnNB_NBCFG2_NBCFG_SCRATCH_0_DEFAULT 0x00000000 |
11053 | #define smnNB_NBCFG2_NBCFG_SCRATCH_1_DEFAULT 0x00000000 |
11054 | #define smnNB_NBCFG2_NBCFG_SCRATCH_2_DEFAULT 0x00000000 |
11055 | #define smnNB_NBCFG2_NBCFG_SCRATCH_3_DEFAULT 0x00000000 |
11056 | #define smnNB_NBCFG2_NBCFG_SCRATCH_4_DEFAULT 0x00000000 |
11057 | #define smnNB_NBCFG2_NB_PCI_ARB_DEFAULT 0x00000108 |
11058 | #define smnNB_NBCFG2_NB_DRAM_SLOT1_BASE_DEFAULT 0x00000000 |
11059 | #define smnNB_NBCFG2_NB_TOP_OF_DRAM_SLOT1_DEFAULT 0x00000000 |
11060 | #define smnNB_NBCFG2_NB_SMN_INDEX_EXTENSION_1_DEFAULT 0x00000000 |
11061 | #define smnNB_NBCFG2_NB_SMN_INDEX_1_DEFAULT 0x00000000 |
11062 | #define smnNB_NBCFG2_NB_SMN_DATA_1_DEFAULT 0x00000000 |
11063 | #define smnNB_NBCFG2_NB_INDEX_DATA_MUTEX0_DEFAULT 0x00000000 |
11064 | #define smnNB_NBCFG2_NB_INDEX_DATA_MUTEX1_DEFAULT 0x00000000 |
11065 | #define smnNB_NBCFG2_NB_SMN_INDEX_EXTENSION_2_DEFAULT 0x00000000 |
11066 | #define smnNB_NBCFG2_NB_SMN_INDEX_2_DEFAULT 0x00000000 |
11067 | #define smnNB_NBCFG2_NB_SMN_DATA_2_DEFAULT 0x00000000 |
11068 | #define smnNB_NBCFG2_NB_SMN_INDEX_EXTENSION_3_DEFAULT 0x00000000 |
11069 | #define smnNB_NBCFG2_NB_SMN_INDEX_3_DEFAULT 0x00000000 |
11070 | #define smnNB_NBCFG2_NB_SMN_DATA_3_DEFAULT 0x00000000 |
11071 | #define smnNB_NBCFG2_NB_SMN_INDEX_EXTENSION_4_DEFAULT 0x00000000 |
11072 | #define smnNB_NBCFG2_NB_SMN_INDEX_4_DEFAULT 0x00000000 |
11073 | #define smnNB_NBCFG2_NB_SMN_DATA_4_DEFAULT 0x00000000 |
11074 | #define smnNB_NBCFG2_NB_SMN_INDEX_EXTENSION_5_DEFAULT 0x00000000 |
11075 | #define smnNB_NBCFG2_NB_SMN_INDEX_5_DEFAULT 0x00000000 |
11076 | #define smnNB_NBCFG2_NB_SMN_DATA_5_DEFAULT 0x00000000 |
11077 | #define smnNB_NBCFG2_NB_PERF_CNT_CTRL_DEFAULT 0x00808000 |
11078 | #define smnNB_NBCFG2_NB_SMN_INDEX_6_DEFAULT 0x00000000 |
11079 | #define smnNB_NBCFG2_NB_SMN_DATA_6_DEFAULT 0x00000000 |
11080 | |
11081 | |
11082 | // addressBlock: nbio_iohub_iommu_l2_iommul2cfg |
11083 | #define smnIOMMU_L2_2_IOMMU_VENDOR_ID_DEFAULT 0x00001022 |
11084 | #define smnIOMMU_L2_2_IOMMU_DEVICE_ID_DEFAULT 0x000015d1 |
11085 | #define smnIOMMU_L2_2_IOMMU_COMMAND_DEFAULT 0x00000000 |
11086 | #define smnIOMMU_L2_2_IOMMU_STATUS_DEFAULT 0x00000000 |
11087 | #define smnIOMMU_L2_2_IOMMU_REVISION_ID_DEFAULT 0x00000000 |
11088 | #define smnIOMMU_L2_2_IOMMU_REGPROG_INF_DEFAULT 0x00000000 |
11089 | #define smnIOMMU_L2_2_IOMMU_SUB_CLASS_DEFAULT 0x00000000 |
11090 | #define smnIOMMU_L2_2_IOMMU_BASE_CODE_DEFAULT 0x00000000 |
11091 | #define smnIOMMU_L2_2_IOMMU_CACHE_LINE_DEFAULT 0x00000000 |
11092 | #define smnIOMMU_L2_2_IOMMU_LATENCY_DEFAULT 0x00000000 |
11093 | #define 0x00000000 |
11094 | #define smnIOMMU_L2_2_IOMMU_BIST_DEFAULT 0x00000000 |
11095 | #define smnIOMMU_L2_2_IOMMU_ADAPTER_ID_DEFAULT 0x00000000 |
11096 | #define smnIOMMU_L2_2_IOMMU_CAPABILITIES_PTR_DEFAULT 0x00000000 |
11097 | #define smnIOMMU_L2_2_IOMMU_INTERRUPT_LINE_DEFAULT 0x00000000 |
11098 | #define smnIOMMU_L2_2_IOMMU_INTERRUPT_PIN_DEFAULT 0x00000001 |
11099 | #define 0x00000000 |
11100 | #define smnIOMMU_L2_2_IOMMU_CAP_BASE_LO_DEFAULT 0x00000000 |
11101 | #define smnIOMMU_L2_2_IOMMU_CAP_BASE_HI_DEFAULT 0x00000000 |
11102 | #define smnIOMMU_L2_2_IOMMU_CAP_RANGE_DEFAULT 0x00000000 |
11103 | #define smnIOMMU_L2_2_IOMMU_CAP_MISC_DEFAULT 0x00003000 |
11104 | #define smnIOMMU_L2_2_IOMMU_CAP_MISC_1_DEFAULT 0x00000080 |
11105 | #define smnIOMMU_L2_2_IOMMU_MSI_CAP_DEFAULT 0x00000000 |
11106 | #define smnIOMMU_L2_2_IOMMU_MSI_ADDR_LO_DEFAULT 0x00000000 |
11107 | #define smnIOMMU_L2_2_IOMMU_MSI_ADDR_HI_DEFAULT 0x00000000 |
11108 | #define smnIOMMU_L2_2_IOMMU_MSI_DATA_DEFAULT 0x00000000 |
11109 | #define smnIOMMU_L2_2_IOMMU_MSI_MAPPING_CAP_DEFAULT 0x00000000 |
11110 | #define smnIOMMU_L2_2_IOMMU_ADAPTER_ID_W_DEFAULT 0x00000000 |
11111 | #define smnIOMMU_L2_2_IOMMU_CONTROL_W_DEFAULT 0x00002b01 |
11112 | #define smnIOMMU_L2_2_IOMMU_MMIO_CONTROL0_W_DEFAULT 0x62201ada |
11113 | #define smnIOMMU_L2_2_IOMMU_MMIO_CONTROL1_W_DEFAULT 0x0003cfcf |
11114 | #define smnIOMMU_L2_2_IOMMU_RANGE_W_DEFAULT 0x00000000 |
11115 | #define smnIOMMU_L2_2_IOMMU_DSFX_CONTROL_DEFAULT 0x00000000 |
11116 | #define smnIOMMU_L2_2_IOMMU_DSSX_DUMMY_0_DEFAULT 0x00000000 |
11117 | #define smnIOMMU_L2_2_IOMMU_DSCX_DUMMY_0_DEFAULT 0x00000000 |
11118 | #define smnIOMMU_L2_2_L2B_POISON_DVM_CNTRL_DEFAULT 0x00000002 |
11119 | #define smnIOMMU_L2_2_L2_IOHC_DmaReq_Stall_Control_DEFAULT 0x00000000 |
11120 | #define smnIOMMU_L2_2_IOHC_L2_HostRsp_Stall_Control_DEFAULT 0x00000000 |
11121 | #define smnIOMMU_L2_2_SMMU_MMIO_IDR0_W_DEFAULT 0x2d4f7fbf |
11122 | #define smnIOMMU_L2_2_SMMU_MMIO_IDR1_W_DEFAULT 0x0e739c10 |
11123 | #define smnIOMMU_L2_2_SMMU_MMIO_IDR2_W_DEFAULT 0x00000000 |
11124 | #define smnIOMMU_L2_2_SMMU_MMIO_IDR3_W_DEFAULT 0x00000000 |
11125 | #define smnIOMMU_L2_2_SMMU_MMIO_IDR5_W_DEFAULT 0x00000075 |
11126 | #define smnIOMMU_L2_2_SMMU_MMIO_IIDR_W_DEFAULT 0x00000000 |
11127 | #define smnIOMMU_L2_2_SMMU_AIDR_W_DEFAULT 0x00000000 |
11128 | |
11129 | |
11130 | // addressBlock: nbio_iohub_nb_pciedummy0_pciedummy_cfgdec |
11131 | #define smnNB_PCIEDUMMY0_2_DEVICE_VENDOR_ID_DEFAULT 0x00000000 |
11132 | #define smnNB_PCIEDUMMY0_2_STATUS_COMMAND_DEFAULT 0x00000000 |
11133 | #define smnNB_PCIEDUMMY0_2_CLASS_CODE_REVID_DEFAULT 0x00000000 |
11134 | #define 0x00800000 |
11135 | #define 0x00000080 |
11136 | |
11137 | |
11138 | // addressBlock: nbio_pcie0_bifplr0_cfgdecp |
11139 | #define smnBIFPLR0_2_VENDOR_ID_DEFAULT 0x00000000 |
11140 | #define smnBIFPLR0_2_DEVICE_ID_DEFAULT 0x00000000 |
11141 | #define smnBIFPLR0_2_COMMAND_DEFAULT 0x00000000 |
11142 | #define smnBIFPLR0_2_STATUS_DEFAULT 0x00000000 |
11143 | #define smnBIFPLR0_2_REVISION_ID_DEFAULT 0x00000000 |
11144 | #define smnBIFPLR0_2_PROG_INTERFACE_DEFAULT 0x00000000 |
11145 | #define smnBIFPLR0_2_SUB_CLASS_DEFAULT 0x00000000 |
11146 | #define smnBIFPLR0_2_BASE_CLASS_DEFAULT 0x00000000 |
11147 | #define smnBIFPLR0_2_CACHE_LINE_DEFAULT 0x00000000 |
11148 | #define smnBIFPLR0_2_LATENCY_DEFAULT 0x00000000 |
11149 | #define 0x00000000 |
11150 | #define smnBIFPLR0_2_BIST_DEFAULT 0x00000000 |
11151 | #define smnBIFPLR0_2_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 |
11152 | #define smnBIFPLR0_2_IO_BASE_LIMIT_DEFAULT 0x00000000 |
11153 | #define smnBIFPLR0_2_SECONDARY_STATUS_DEFAULT 0x00000000 |
11154 | #define smnBIFPLR0_2_MEM_BASE_LIMIT_DEFAULT 0x00000000 |
11155 | #define smnBIFPLR0_2_PREF_BASE_LIMIT_DEFAULT 0x00000000 |
11156 | #define smnBIFPLR0_2_PREF_BASE_UPPER_DEFAULT 0x00000000 |
11157 | #define smnBIFPLR0_2_PREF_LIMIT_UPPER_DEFAULT 0x00000000 |
11158 | #define smnBIFPLR0_2_IO_BASE_LIMIT_HI_DEFAULT 0x00000000 |
11159 | #define smnBIFPLR0_2_CAP_PTR_DEFAULT 0x00000000 |
11160 | #define smnBIFPLR0_2_INTERRUPT_LINE_DEFAULT 0x000000ff |
11161 | #define smnBIFPLR0_2_INTERRUPT_PIN_DEFAULT 0x00000000 |
11162 | #define smnBIFPLR0_2_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000 |
11163 | #define smnBIFPLR0_2_EXT_BRIDGE_CNTL_DEFAULT 0x00000000 |
11164 | #define smnBIFPLR0_2_PMI_CAP_LIST_DEFAULT 0x00000000 |
11165 | #define smnBIFPLR0_2_PMI_CAP_DEFAULT 0x00000000 |
11166 | #define smnBIFPLR0_2_PMI_STATUS_CNTL_DEFAULT 0x00000000 |
11167 | #define smnBIFPLR0_2_PCIE_CAP_LIST_DEFAULT 0x0000a000 |
11168 | #define smnBIFPLR0_2_PCIE_CAP_DEFAULT 0x00000002 |
11169 | #define smnBIFPLR0_2_DEVICE_CAP_DEFAULT 0x00000000 |
11170 | #define smnBIFPLR0_2_DEVICE_CNTL_DEFAULT 0x00002810 |
11171 | #define smnBIFPLR0_2_DEVICE_STATUS_DEFAULT 0x00000000 |
11172 | #define smnBIFPLR0_2_LINK_CAP_DEFAULT 0x00011c03 |
11173 | #define smnBIFPLR0_2_LINK_CNTL_DEFAULT 0x00000000 |
11174 | #define smnBIFPLR0_2_LINK_STATUS_DEFAULT 0x00000001 |
11175 | #define smnBIFPLR0_2_SLOT_CAP_DEFAULT 0x00000000 |
11176 | #define smnBIFPLR0_2_SLOT_CNTL_DEFAULT 0x00000000 |
11177 | #define smnBIFPLR0_2_SLOT_STATUS_DEFAULT 0x00000000 |
11178 | #define smnBIFPLR0_2_ROOT_CNTL_DEFAULT 0x00000000 |
11179 | #define smnBIFPLR0_2_ROOT_CAP_DEFAULT 0x00000000 |
11180 | #define smnBIFPLR0_2_ROOT_STATUS_DEFAULT 0x00000000 |
11181 | #define smnBIFPLR0_2_DEVICE_CAP2_DEFAULT 0x00000000 |
11182 | #define smnBIFPLR0_2_DEVICE_CNTL2_DEFAULT 0x00000000 |
11183 | #define smnBIFPLR0_2_DEVICE_STATUS2_DEFAULT 0x00000000 |
11184 | #define smnBIFPLR0_2_LINK_CAP2_DEFAULT 0x0000000e |
11185 | #define smnBIFPLR0_2_LINK_CNTL2_DEFAULT 0x00000003 |
11186 | #define smnBIFPLR0_2_LINK_STATUS2_DEFAULT 0x00000000 |
11187 | #define smnBIFPLR0_2_SLOT_CAP2_DEFAULT 0x00000000 |
11188 | #define smnBIFPLR0_2_SLOT_CNTL2_DEFAULT 0x00000000 |
11189 | #define smnBIFPLR0_2_SLOT_STATUS2_DEFAULT 0x00000000 |
11190 | #define smnBIFPLR0_2_MSI_CAP_LIST_DEFAULT 0x0000c000 |
11191 | #define smnBIFPLR0_2_MSI_MSG_CNTL_DEFAULT 0x00000000 |
11192 | #define smnBIFPLR0_2_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 |
11193 | #define smnBIFPLR0_2_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 |
11194 | #define smnBIFPLR0_2_MSI_MSG_DATA_DEFAULT 0x00000000 |
11195 | #define smnBIFPLR0_2_MSI_MSG_DATA_64_DEFAULT 0x00000000 |
11196 | #define smnBIFPLR0_2_SSID_CAP_LIST_DEFAULT 0x0000c800 |
11197 | #define smnBIFPLR0_2_SSID_CAP_DEFAULT 0x00000000 |
11198 | #define smnBIFPLR0_2_MSI_MAP_CAP_LIST_DEFAULT 0x00000000 |
11199 | #define smnBIFPLR0_2_MSI_MAP_CAP_DEFAULT 0x00000000 |
11200 | #define smnBIFPLR0_2_MSI_MAP_ADDR_LO_DEFAULT 0x00000000 |
11201 | #define smnBIFPLR0_2_MSI_MAP_ADDR_HI_DEFAULT 0x00000000 |
11202 | #define smnBIFPLR0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 |
11203 | #define smnBIFPLR0_2_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 |
11204 | #define smnBIFPLR0_2_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 |
11205 | #define smnBIFPLR0_2_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 |
11206 | #define smnBIFPLR0_2_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000 |
11207 | #define smnBIFPLR0_2_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000 |
11208 | #define smnBIFPLR0_2_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000 |
11209 | #define smnBIFPLR0_2_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000 |
11210 | #define smnBIFPLR0_2_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000 |
11211 | #define smnBIFPLR0_2_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000 |
11212 | #define smnBIFPLR0_2_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe |
11213 | #define smnBIFPLR0_2_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000002 |
11214 | #define smnBIFPLR0_2_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000 |
11215 | #define smnBIFPLR0_2_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000 |
11216 | #define smnBIFPLR0_2_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000002 |
11217 | #define smnBIFPLR0_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000 |
11218 | #define smnBIFPLR0_2_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000 |
11219 | #define smnBIFPLR0_2_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000 |
11220 | #define smnBIFPLR0_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x27020000 |
11221 | #define smnBIFPLR0_2_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 |
11222 | #define smnBIFPLR0_2_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00400000 |
11223 | #define smnBIFPLR0_2_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 |
11224 | #define smnBIFPLR0_2_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 |
11225 | #define smnBIFPLR0_2_PCIE_CORR_ERR_MASK_DEFAULT 0x00006000 |
11226 | #define smnBIFPLR0_2_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 |
11227 | #define smnBIFPLR0_2_PCIE_HDR_LOG0_DEFAULT 0x00000000 |
11228 | #define smnBIFPLR0_2_PCIE_HDR_LOG1_DEFAULT 0x00000000 |
11229 | #define smnBIFPLR0_2_PCIE_HDR_LOG2_DEFAULT 0x00000000 |
11230 | #define smnBIFPLR0_2_PCIE_HDR_LOG3_DEFAULT 0x00000000 |
11231 | #define smnBIFPLR0_2_PCIE_ROOT_ERR_CMD_DEFAULT 0x00000000 |
11232 | #define smnBIFPLR0_2_PCIE_ROOT_ERR_STATUS_DEFAULT 0x00000000 |
11233 | #define smnBIFPLR0_2_PCIE_ERR_SRC_ID_DEFAULT 0x00000000 |
11234 | #define smnBIFPLR0_2_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 |
11235 | #define smnBIFPLR0_2_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 |
11236 | #define smnBIFPLR0_2_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 |
11237 | #define smnBIFPLR0_2_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 |
11238 | #define smnBIFPLR0_2_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a000000 |
11239 | #define smnBIFPLR0_2_PCIE_LINK_CNTL3_DEFAULT 0x00000000 |
11240 | #define smnBIFPLR0_2_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000 |
11241 | #define smnBIFPLR0_2_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
11242 | #define smnBIFPLR0_2_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
11243 | #define smnBIFPLR0_2_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
11244 | #define smnBIFPLR0_2_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
11245 | #define smnBIFPLR0_2_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
11246 | #define smnBIFPLR0_2_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
11247 | #define smnBIFPLR0_2_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
11248 | #define smnBIFPLR0_2_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
11249 | #define smnBIFPLR0_2_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
11250 | #define smnBIFPLR0_2_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
11251 | #define smnBIFPLR0_2_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
11252 | #define smnBIFPLR0_2_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
11253 | #define smnBIFPLR0_2_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
11254 | #define smnBIFPLR0_2_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
11255 | #define smnBIFPLR0_2_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
11256 | #define smnBIFPLR0_2_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
11257 | #define smnBIFPLR0_2_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2f000000 |
11258 | #define smnBIFPLR0_2_PCIE_ACS_CAP_DEFAULT 0x00000000 |
11259 | #define smnBIFPLR0_2_PCIE_ACS_CNTL_DEFAULT 0x00000000 |
11260 | #define smnBIFPLR0_2_PCIE_MC_ENH_CAP_LIST_DEFAULT 0x32000000 |
11261 | #define smnBIFPLR0_2_PCIE_MC_CAP_DEFAULT 0x00000000 |
11262 | #define smnBIFPLR0_2_PCIE_MC_CNTL_DEFAULT 0x00000000 |
11263 | #define smnBIFPLR0_2_PCIE_MC_ADDR0_DEFAULT 0x00000000 |
11264 | #define smnBIFPLR0_2_PCIE_MC_ADDR1_DEFAULT 0x00000000 |
11265 | #define smnBIFPLR0_2_PCIE_MC_RCV0_DEFAULT 0x00000000 |
11266 | #define smnBIFPLR0_2_PCIE_MC_RCV1_DEFAULT 0x00000000 |
11267 | #define smnBIFPLR0_2_PCIE_MC_BLOCK_ALL0_DEFAULT 0x00000000 |
11268 | #define smnBIFPLR0_2_PCIE_MC_BLOCK_ALL1_DEFAULT 0x00000000 |
11269 | #define smnBIFPLR0_2_PCIE_MC_BLOCK_UNTRANSLATED_0_DEFAULT 0x00000000 |
11270 | #define smnBIFPLR0_2_PCIE_MC_BLOCK_UNTRANSLATED_1_DEFAULT 0x00000000 |
11271 | #define smnBIFPLR0_2_PCIE_MC_OVERLAY_BAR0_DEFAULT 0x00000000 |
11272 | #define smnBIFPLR0_2_PCIE_MC_OVERLAY_BAR1_DEFAULT 0x00000000 |
11273 | #define smnBIFPLR0_2_PCIE_L1_PM_SUB_CAP_LIST_DEFAULT 0x00000000 |
11274 | #define smnBIFPLR0_2_PCIE_L1_PM_SUB_CAP_DEFAULT 0x00000000 |
11275 | #define smnBIFPLR0_2_PCIE_L1_PM_SUB_CNTL_DEFAULT 0x00000000 |
11276 | #define smnBIFPLR0_2_PCIE_L1_PM_SUB_CNTL2_DEFAULT 0x00000028 |
11277 | #define smnBIFPLR0_2_PCIE_DPC_ENH_CAP_LIST_DEFAULT 0x00000000 |
11278 | #define smnBIFPLR0_2_PCIE_DPC_CAP_LIST_DEFAULT 0x00000000 |
11279 | #define smnBIFPLR0_2_PCIE_DPC_CNTL_DEFAULT 0x00000000 |
11280 | #define smnBIFPLR0_2_PCIE_DPC_STATUS_DEFAULT 0x00000000 |
11281 | #define smnBIFPLR0_2_PCIE_DPC_ERROR_SOURCE_ID_DEFAULT 0x00000000 |
11282 | #define smnBIFPLR0_2_PCIE_RP_PIO_STATUS_DEFAULT 0x00000000 |
11283 | #define smnBIFPLR0_2_PCIE_RP_PIO_MASK_DEFAULT 0x00070707 |
11284 | #define smnBIFPLR0_2_PCIE_RP_PIO_SEVERITY_DEFAULT 0x00000000 |
11285 | #define smnBIFPLR0_2_PCIE_RP_PIO_SYSERROR_DEFAULT 0x00000000 |
11286 | #define smnBIFPLR0_2_PCIE_RP_PIO_EXCEPTION_DEFAULT 0x00000000 |
11287 | #define smnBIFPLR0_2_PCIE_RP_PIO_HDR_LOG0_DEFAULT 0x00000000 |
11288 | #define smnBIFPLR0_2_PCIE_RP_PIO_HDR_LOG1_DEFAULT 0x00000000 |
11289 | #define smnBIFPLR0_2_PCIE_RP_PIO_HDR_LOG2_DEFAULT 0x00000000 |
11290 | #define smnBIFPLR0_2_PCIE_RP_PIO_HDR_LOG3_DEFAULT 0x00000000 |
11291 | #define smnBIFPLR0_2_PCIE_RP_PIO_IMPSPEC_LOG_DEFAULT 0x00000000 |
11292 | #define smnBIFPLR0_2_PCIE_RP_PIO_PREFIX_LOG0_DEFAULT 0x00000000 |
11293 | #define smnBIFPLR0_2_PCIE_RP_PIO_PREFIX_LOG1_DEFAULT 0x00000000 |
11294 | #define smnBIFPLR0_2_PCIE_RP_PIO_PREFIX_LOG2_DEFAULT 0x00000000 |
11295 | #define smnBIFPLR0_2_PCIE_RP_PIO_PREFIX_LOG3_DEFAULT 0x00000000 |
11296 | #define smnBIFPLR0_2_PCIE_ESM_CAP_LIST_DEFAULT 0x00000000 |
11297 | #define 0x00000000 |
11298 | #define 0x00000000 |
11299 | #define smnBIFPLR0_2_PCIE_ESM_STATUS_DEFAULT 0x00000000 |
11300 | #define smnBIFPLR0_2_PCIE_ESM_CTRL_DEFAULT 0x00000000 |
11301 | #define smnBIFPLR0_2_PCIE_ESM_CAP_1_DEFAULT 0x00000000 |
11302 | #define smnBIFPLR0_2_PCIE_ESM_CAP_2_DEFAULT 0x00000000 |
11303 | #define smnBIFPLR0_2_PCIE_ESM_CAP_3_DEFAULT 0x00000000 |
11304 | #define smnBIFPLR0_2_PCIE_ESM_CAP_4_DEFAULT 0x00000000 |
11305 | #define smnBIFPLR0_2_PCIE_ESM_CAP_5_DEFAULT 0x00000000 |
11306 | #define smnBIFPLR0_2_PCIE_ESM_CAP_6_DEFAULT 0x00000000 |
11307 | #define smnBIFPLR0_2_PCIE_ESM_CAP_7_DEFAULT 0x00000000 |
11308 | |
11309 | |
11310 | // addressBlock: nbio_pcie0_bifplr1_cfgdecp |
11311 | #define smnBIFPLR1_2_VENDOR_ID_DEFAULT 0x00000000 |
11312 | #define smnBIFPLR1_2_DEVICE_ID_DEFAULT 0x00000000 |
11313 | #define smnBIFPLR1_2_COMMAND_DEFAULT 0x00000000 |
11314 | #define smnBIFPLR1_2_STATUS_DEFAULT 0x00000000 |
11315 | #define smnBIFPLR1_2_REVISION_ID_DEFAULT 0x00000000 |
11316 | #define smnBIFPLR1_2_PROG_INTERFACE_DEFAULT 0x00000000 |
11317 | #define smnBIFPLR1_2_SUB_CLASS_DEFAULT 0x00000000 |
11318 | #define smnBIFPLR1_2_BASE_CLASS_DEFAULT 0x00000000 |
11319 | #define smnBIFPLR1_2_CACHE_LINE_DEFAULT 0x00000000 |
11320 | #define smnBIFPLR1_2_LATENCY_DEFAULT 0x00000000 |
11321 | #define 0x00000000 |
11322 | #define smnBIFPLR1_2_BIST_DEFAULT 0x00000000 |
11323 | #define smnBIFPLR1_2_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 |
11324 | #define smnBIFPLR1_2_IO_BASE_LIMIT_DEFAULT 0x00000000 |
11325 | #define smnBIFPLR1_2_SECONDARY_STATUS_DEFAULT 0x00000000 |
11326 | #define smnBIFPLR1_2_MEM_BASE_LIMIT_DEFAULT 0x00000000 |
11327 | #define smnBIFPLR1_2_PREF_BASE_LIMIT_DEFAULT 0x00000000 |
11328 | #define smnBIFPLR1_2_PREF_BASE_UPPER_DEFAULT 0x00000000 |
11329 | #define smnBIFPLR1_2_PREF_LIMIT_UPPER_DEFAULT 0x00000000 |
11330 | #define smnBIFPLR1_2_IO_BASE_LIMIT_HI_DEFAULT 0x00000000 |
11331 | #define smnBIFPLR1_2_CAP_PTR_DEFAULT 0x00000000 |
11332 | #define smnBIFPLR1_2_INTERRUPT_LINE_DEFAULT 0x000000ff |
11333 | #define smnBIFPLR1_2_INTERRUPT_PIN_DEFAULT 0x00000000 |
11334 | #define smnBIFPLR1_2_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000 |
11335 | #define smnBIFPLR1_2_EXT_BRIDGE_CNTL_DEFAULT 0x00000000 |
11336 | #define smnBIFPLR1_2_PMI_CAP_LIST_DEFAULT 0x00000000 |
11337 | #define smnBIFPLR1_2_PMI_CAP_DEFAULT 0x00000000 |
11338 | #define smnBIFPLR1_2_PMI_STATUS_CNTL_DEFAULT 0x00000000 |
11339 | #define smnBIFPLR1_2_PCIE_CAP_LIST_DEFAULT 0x0000a000 |
11340 | #define smnBIFPLR1_2_PCIE_CAP_DEFAULT 0x00000002 |
11341 | #define smnBIFPLR1_2_DEVICE_CAP_DEFAULT 0x00000000 |
11342 | #define smnBIFPLR1_2_DEVICE_CNTL_DEFAULT 0x00002810 |
11343 | #define smnBIFPLR1_2_DEVICE_STATUS_DEFAULT 0x00000000 |
11344 | #define smnBIFPLR1_2_LINK_CAP_DEFAULT 0x00011c03 |
11345 | #define smnBIFPLR1_2_LINK_CNTL_DEFAULT 0x00000000 |
11346 | #define smnBIFPLR1_2_LINK_STATUS_DEFAULT 0x00000001 |
11347 | #define smnBIFPLR1_2_SLOT_CAP_DEFAULT 0x00000000 |
11348 | #define smnBIFPLR1_2_SLOT_CNTL_DEFAULT 0x00000000 |
11349 | #define smnBIFPLR1_2_SLOT_STATUS_DEFAULT 0x00000000 |
11350 | #define smnBIFPLR1_2_ROOT_CNTL_DEFAULT 0x00000000 |
11351 | #define smnBIFPLR1_2_ROOT_CAP_DEFAULT 0x00000000 |
11352 | #define smnBIFPLR1_2_ROOT_STATUS_DEFAULT 0x00000000 |
11353 | #define smnBIFPLR1_2_DEVICE_CAP2_DEFAULT 0x00000000 |
11354 | #define smnBIFPLR1_2_DEVICE_CNTL2_DEFAULT 0x00000000 |
11355 | #define smnBIFPLR1_2_DEVICE_STATUS2_DEFAULT 0x00000000 |
11356 | #define smnBIFPLR1_2_LINK_CAP2_DEFAULT 0x0000000e |
11357 | #define smnBIFPLR1_2_LINK_CNTL2_DEFAULT 0x00000003 |
11358 | #define smnBIFPLR1_2_LINK_STATUS2_DEFAULT 0x00000000 |
11359 | #define smnBIFPLR1_2_SLOT_CAP2_DEFAULT 0x00000000 |
11360 | #define smnBIFPLR1_2_SLOT_CNTL2_DEFAULT 0x00000000 |
11361 | #define smnBIFPLR1_2_SLOT_STATUS2_DEFAULT 0x00000000 |
11362 | #define smnBIFPLR1_2_MSI_CAP_LIST_DEFAULT 0x0000c000 |
11363 | #define smnBIFPLR1_2_MSI_MSG_CNTL_DEFAULT 0x00000000 |
11364 | #define smnBIFPLR1_2_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 |
11365 | #define smnBIFPLR1_2_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 |
11366 | #define smnBIFPLR1_2_MSI_MSG_DATA_DEFAULT 0x00000000 |
11367 | #define smnBIFPLR1_2_MSI_MSG_DATA_64_DEFAULT 0x00000000 |
11368 | #define smnBIFPLR1_2_SSID_CAP_LIST_DEFAULT 0x0000c800 |
11369 | #define smnBIFPLR1_2_SSID_CAP_DEFAULT 0x00000000 |
11370 | #define smnBIFPLR1_2_MSI_MAP_CAP_LIST_DEFAULT 0x00000000 |
11371 | #define smnBIFPLR1_2_MSI_MAP_CAP_DEFAULT 0x00000000 |
11372 | #define smnBIFPLR1_2_MSI_MAP_ADDR_LO_DEFAULT 0x00000000 |
11373 | #define smnBIFPLR1_2_MSI_MAP_ADDR_HI_DEFAULT 0x00000000 |
11374 | #define smnBIFPLR1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 |
11375 | #define smnBIFPLR1_2_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 |
11376 | #define smnBIFPLR1_2_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 |
11377 | #define smnBIFPLR1_2_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 |
11378 | #define smnBIFPLR1_2_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000 |
11379 | #define smnBIFPLR1_2_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000 |
11380 | #define smnBIFPLR1_2_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000 |
11381 | #define smnBIFPLR1_2_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000 |
11382 | #define smnBIFPLR1_2_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000 |
11383 | #define smnBIFPLR1_2_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000 |
11384 | #define smnBIFPLR1_2_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe |
11385 | #define smnBIFPLR1_2_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000002 |
11386 | #define smnBIFPLR1_2_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000 |
11387 | #define smnBIFPLR1_2_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000 |
11388 | #define smnBIFPLR1_2_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000002 |
11389 | #define smnBIFPLR1_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000 |
11390 | #define smnBIFPLR1_2_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000 |
11391 | #define smnBIFPLR1_2_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000 |
11392 | #define smnBIFPLR1_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x27020000 |
11393 | #define smnBIFPLR1_2_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 |
11394 | #define smnBIFPLR1_2_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00400000 |
11395 | #define smnBIFPLR1_2_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 |
11396 | #define smnBIFPLR1_2_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 |
11397 | #define smnBIFPLR1_2_PCIE_CORR_ERR_MASK_DEFAULT 0x00006000 |
11398 | #define smnBIFPLR1_2_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 |
11399 | #define smnBIFPLR1_2_PCIE_HDR_LOG0_DEFAULT 0x00000000 |
11400 | #define smnBIFPLR1_2_PCIE_HDR_LOG1_DEFAULT 0x00000000 |
11401 | #define smnBIFPLR1_2_PCIE_HDR_LOG2_DEFAULT 0x00000000 |
11402 | #define smnBIFPLR1_2_PCIE_HDR_LOG3_DEFAULT 0x00000000 |
11403 | #define smnBIFPLR1_2_PCIE_ROOT_ERR_CMD_DEFAULT 0x00000000 |
11404 | #define smnBIFPLR1_2_PCIE_ROOT_ERR_STATUS_DEFAULT 0x00000000 |
11405 | #define smnBIFPLR1_2_PCIE_ERR_SRC_ID_DEFAULT 0x00000000 |
11406 | #define smnBIFPLR1_2_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 |
11407 | #define smnBIFPLR1_2_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 |
11408 | #define smnBIFPLR1_2_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 |
11409 | #define smnBIFPLR1_2_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 |
11410 | #define smnBIFPLR1_2_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a000000 |
11411 | #define smnBIFPLR1_2_PCIE_LINK_CNTL3_DEFAULT 0x00000000 |
11412 | #define smnBIFPLR1_2_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000 |
11413 | #define smnBIFPLR1_2_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
11414 | #define smnBIFPLR1_2_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
11415 | #define smnBIFPLR1_2_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
11416 | #define smnBIFPLR1_2_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
11417 | #define smnBIFPLR1_2_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
11418 | #define smnBIFPLR1_2_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
11419 | #define smnBIFPLR1_2_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
11420 | #define smnBIFPLR1_2_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
11421 | #define smnBIFPLR1_2_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
11422 | #define smnBIFPLR1_2_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
11423 | #define smnBIFPLR1_2_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
11424 | #define smnBIFPLR1_2_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
11425 | #define smnBIFPLR1_2_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
11426 | #define smnBIFPLR1_2_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
11427 | #define smnBIFPLR1_2_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
11428 | #define smnBIFPLR1_2_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
11429 | #define smnBIFPLR1_2_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2f000000 |
11430 | #define smnBIFPLR1_2_PCIE_ACS_CAP_DEFAULT 0x00000000 |
11431 | #define smnBIFPLR1_2_PCIE_ACS_CNTL_DEFAULT 0x00000000 |
11432 | #define smnBIFPLR1_2_PCIE_MC_ENH_CAP_LIST_DEFAULT 0x32000000 |
11433 | #define smnBIFPLR1_2_PCIE_MC_CAP_DEFAULT 0x00000000 |
11434 | #define smnBIFPLR1_2_PCIE_MC_CNTL_DEFAULT 0x00000000 |
11435 | #define smnBIFPLR1_2_PCIE_MC_ADDR0_DEFAULT 0x00000000 |
11436 | #define smnBIFPLR1_2_PCIE_MC_ADDR1_DEFAULT 0x00000000 |
11437 | #define smnBIFPLR1_2_PCIE_MC_RCV0_DEFAULT 0x00000000 |
11438 | #define smnBIFPLR1_2_PCIE_MC_RCV1_DEFAULT 0x00000000 |
11439 | #define smnBIFPLR1_2_PCIE_MC_BLOCK_ALL0_DEFAULT 0x00000000 |
11440 | #define smnBIFPLR1_2_PCIE_MC_BLOCK_ALL1_DEFAULT 0x00000000 |
11441 | #define smnBIFPLR1_2_PCIE_MC_BLOCK_UNTRANSLATED_0_DEFAULT 0x00000000 |
11442 | #define smnBIFPLR1_2_PCIE_MC_BLOCK_UNTRANSLATED_1_DEFAULT 0x00000000 |
11443 | #define smnBIFPLR1_2_PCIE_MC_OVERLAY_BAR0_DEFAULT 0x00000000 |
11444 | #define smnBIFPLR1_2_PCIE_MC_OVERLAY_BAR1_DEFAULT 0x00000000 |
11445 | #define smnBIFPLR1_2_PCIE_L1_PM_SUB_CAP_LIST_DEFAULT 0x00000000 |
11446 | #define smnBIFPLR1_2_PCIE_L1_PM_SUB_CAP_DEFAULT 0x00000000 |
11447 | #define smnBIFPLR1_2_PCIE_L1_PM_SUB_CNTL_DEFAULT 0x00000000 |
11448 | #define smnBIFPLR1_2_PCIE_L1_PM_SUB_CNTL2_DEFAULT 0x00000028 |
11449 | #define smnBIFPLR1_2_PCIE_DPC_ENH_CAP_LIST_DEFAULT 0x00000000 |
11450 | #define smnBIFPLR1_2_PCIE_DPC_CAP_LIST_DEFAULT 0x00000000 |
11451 | #define smnBIFPLR1_2_PCIE_DPC_CNTL_DEFAULT 0x00000000 |
11452 | #define smnBIFPLR1_2_PCIE_DPC_STATUS_DEFAULT 0x00000000 |
11453 | #define smnBIFPLR1_2_PCIE_DPC_ERROR_SOURCE_ID_DEFAULT 0x00000000 |
11454 | #define smnBIFPLR1_2_PCIE_RP_PIO_STATUS_DEFAULT 0x00000000 |
11455 | #define smnBIFPLR1_2_PCIE_RP_PIO_MASK_DEFAULT 0x00070707 |
11456 | #define smnBIFPLR1_2_PCIE_RP_PIO_SEVERITY_DEFAULT 0x00000000 |
11457 | #define smnBIFPLR1_2_PCIE_RP_PIO_SYSERROR_DEFAULT 0x00000000 |
11458 | #define smnBIFPLR1_2_PCIE_RP_PIO_EXCEPTION_DEFAULT 0x00000000 |
11459 | #define smnBIFPLR1_2_PCIE_RP_PIO_HDR_LOG0_DEFAULT 0x00000000 |
11460 | #define smnBIFPLR1_2_PCIE_RP_PIO_HDR_LOG1_DEFAULT 0x00000000 |
11461 | #define smnBIFPLR1_2_PCIE_RP_PIO_HDR_LOG2_DEFAULT 0x00000000 |
11462 | #define smnBIFPLR1_2_PCIE_RP_PIO_HDR_LOG3_DEFAULT 0x00000000 |
11463 | #define smnBIFPLR1_2_PCIE_RP_PIO_IMPSPEC_LOG_DEFAULT 0x00000000 |
11464 | #define smnBIFPLR1_2_PCIE_RP_PIO_PREFIX_LOG0_DEFAULT 0x00000000 |
11465 | #define smnBIFPLR1_2_PCIE_RP_PIO_PREFIX_LOG1_DEFAULT 0x00000000 |
11466 | #define smnBIFPLR1_2_PCIE_RP_PIO_PREFIX_LOG2_DEFAULT 0x00000000 |
11467 | #define smnBIFPLR1_2_PCIE_RP_PIO_PREFIX_LOG3_DEFAULT 0x00000000 |
11468 | #define smnBIFPLR1_2_PCIE_ESM_CAP_LIST_DEFAULT 0x00000000 |
11469 | #define 0x00000000 |
11470 | #define 0x00000000 |
11471 | #define smnBIFPLR1_2_PCIE_ESM_STATUS_DEFAULT 0x00000000 |
11472 | #define smnBIFPLR1_2_PCIE_ESM_CTRL_DEFAULT 0x00000000 |
11473 | #define smnBIFPLR1_2_PCIE_ESM_CAP_1_DEFAULT 0x00000000 |
11474 | #define smnBIFPLR1_2_PCIE_ESM_CAP_2_DEFAULT 0x00000000 |
11475 | #define smnBIFPLR1_2_PCIE_ESM_CAP_3_DEFAULT 0x00000000 |
11476 | #define smnBIFPLR1_2_PCIE_ESM_CAP_4_DEFAULT 0x00000000 |
11477 | #define smnBIFPLR1_2_PCIE_ESM_CAP_5_DEFAULT 0x00000000 |
11478 | #define smnBIFPLR1_2_PCIE_ESM_CAP_6_DEFAULT 0x00000000 |
11479 | #define smnBIFPLR1_2_PCIE_ESM_CAP_7_DEFAULT 0x00000000 |
11480 | |
11481 | |
11482 | // addressBlock: nbio_pcie0_bifplr2_cfgdecp |
11483 | #define smnBIFPLR2_2_VENDOR_ID_DEFAULT 0x00000000 |
11484 | #define smnBIFPLR2_2_DEVICE_ID_DEFAULT 0x00000000 |
11485 | #define smnBIFPLR2_2_COMMAND_DEFAULT 0x00000000 |
11486 | #define smnBIFPLR2_2_STATUS_DEFAULT 0x00000000 |
11487 | #define smnBIFPLR2_2_REVISION_ID_DEFAULT 0x00000000 |
11488 | #define smnBIFPLR2_2_PROG_INTERFACE_DEFAULT 0x00000000 |
11489 | #define smnBIFPLR2_2_SUB_CLASS_DEFAULT 0x00000000 |
11490 | #define smnBIFPLR2_2_BASE_CLASS_DEFAULT 0x00000000 |
11491 | #define smnBIFPLR2_2_CACHE_LINE_DEFAULT 0x00000000 |
11492 | #define smnBIFPLR2_2_LATENCY_DEFAULT 0x00000000 |
11493 | #define 0x00000000 |
11494 | #define smnBIFPLR2_2_BIST_DEFAULT 0x00000000 |
11495 | #define smnBIFPLR2_2_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 |
11496 | #define smnBIFPLR2_2_IO_BASE_LIMIT_DEFAULT 0x00000000 |
11497 | #define smnBIFPLR2_2_SECONDARY_STATUS_DEFAULT 0x00000000 |
11498 | #define smnBIFPLR2_2_MEM_BASE_LIMIT_DEFAULT 0x00000000 |
11499 | #define smnBIFPLR2_2_PREF_BASE_LIMIT_DEFAULT 0x00000000 |
11500 | #define smnBIFPLR2_2_PREF_BASE_UPPER_DEFAULT 0x00000000 |
11501 | #define smnBIFPLR2_2_PREF_LIMIT_UPPER_DEFAULT 0x00000000 |
11502 | #define smnBIFPLR2_2_IO_BASE_LIMIT_HI_DEFAULT 0x00000000 |
11503 | #define smnBIFPLR2_2_CAP_PTR_DEFAULT 0x00000000 |
11504 | #define smnBIFPLR2_2_INTERRUPT_LINE_DEFAULT 0x000000ff |
11505 | #define smnBIFPLR2_2_INTERRUPT_PIN_DEFAULT 0x00000000 |
11506 | #define smnBIFPLR2_2_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000 |
11507 | #define smnBIFPLR2_2_EXT_BRIDGE_CNTL_DEFAULT 0x00000000 |
11508 | #define smnBIFPLR2_2_PMI_CAP_LIST_DEFAULT 0x00000000 |
11509 | #define smnBIFPLR2_2_PMI_CAP_DEFAULT 0x00000000 |
11510 | #define smnBIFPLR2_2_PMI_STATUS_CNTL_DEFAULT 0x00000000 |
11511 | #define smnBIFPLR2_2_PCIE_CAP_LIST_DEFAULT 0x0000a000 |
11512 | #define smnBIFPLR2_2_PCIE_CAP_DEFAULT 0x00000002 |
11513 | #define smnBIFPLR2_2_DEVICE_CAP_DEFAULT 0x00000000 |
11514 | #define smnBIFPLR2_2_DEVICE_CNTL_DEFAULT 0x00002810 |
11515 | #define smnBIFPLR2_2_DEVICE_STATUS_DEFAULT 0x00000000 |
11516 | #define smnBIFPLR2_2_LINK_CAP_DEFAULT 0x00011c03 |
11517 | #define smnBIFPLR2_2_LINK_CNTL_DEFAULT 0x00000000 |
11518 | #define smnBIFPLR2_2_LINK_STATUS_DEFAULT 0x00000001 |
11519 | #define smnBIFPLR2_2_SLOT_CAP_DEFAULT 0x00000000 |
11520 | #define smnBIFPLR2_2_SLOT_CNTL_DEFAULT 0x00000000 |
11521 | #define smnBIFPLR2_2_SLOT_STATUS_DEFAULT 0x00000000 |
11522 | #define smnBIFPLR2_2_ROOT_CNTL_DEFAULT 0x00000000 |
11523 | #define smnBIFPLR2_2_ROOT_CAP_DEFAULT 0x00000000 |
11524 | #define smnBIFPLR2_2_ROOT_STATUS_DEFAULT 0x00000000 |
11525 | #define smnBIFPLR2_2_DEVICE_CAP2_DEFAULT 0x00000000 |
11526 | #define smnBIFPLR2_2_DEVICE_CNTL2_DEFAULT 0x00000000 |
11527 | #define smnBIFPLR2_2_DEVICE_STATUS2_DEFAULT 0x00000000 |
11528 | #define smnBIFPLR2_2_LINK_CAP2_DEFAULT 0x0000000e |
11529 | #define smnBIFPLR2_2_LINK_CNTL2_DEFAULT 0x00000003 |
11530 | #define smnBIFPLR2_2_LINK_STATUS2_DEFAULT 0x00000000 |
11531 | #define smnBIFPLR2_2_SLOT_CAP2_DEFAULT 0x00000000 |
11532 | #define smnBIFPLR2_2_SLOT_CNTL2_DEFAULT 0x00000000 |
11533 | #define smnBIFPLR2_2_SLOT_STATUS2_DEFAULT 0x00000000 |
11534 | #define smnBIFPLR2_2_MSI_CAP_LIST_DEFAULT 0x0000c000 |
11535 | #define smnBIFPLR2_2_MSI_MSG_CNTL_DEFAULT 0x00000000 |
11536 | #define smnBIFPLR2_2_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 |
11537 | #define smnBIFPLR2_2_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 |
11538 | #define smnBIFPLR2_2_MSI_MSG_DATA_DEFAULT 0x00000000 |
11539 | #define smnBIFPLR2_2_MSI_MSG_DATA_64_DEFAULT 0x00000000 |
11540 | #define smnBIFPLR2_2_SSID_CAP_LIST_DEFAULT 0x0000c800 |
11541 | #define smnBIFPLR2_2_SSID_CAP_DEFAULT 0x00000000 |
11542 | #define smnBIFPLR2_2_MSI_MAP_CAP_LIST_DEFAULT 0x00000000 |
11543 | #define smnBIFPLR2_2_MSI_MAP_CAP_DEFAULT 0x00000000 |
11544 | #define smnBIFPLR2_2_MSI_MAP_ADDR_LO_DEFAULT 0x00000000 |
11545 | #define smnBIFPLR2_2_MSI_MAP_ADDR_HI_DEFAULT 0x00000000 |
11546 | #define smnBIFPLR2_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 |
11547 | #define smnBIFPLR2_2_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 |
11548 | #define smnBIFPLR2_2_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 |
11549 | #define smnBIFPLR2_2_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 |
11550 | #define smnBIFPLR2_2_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000 |
11551 | #define smnBIFPLR2_2_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000 |
11552 | #define smnBIFPLR2_2_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000 |
11553 | #define smnBIFPLR2_2_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000 |
11554 | #define smnBIFPLR2_2_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000 |
11555 | #define smnBIFPLR2_2_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000 |
11556 | #define smnBIFPLR2_2_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe |
11557 | #define smnBIFPLR2_2_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000002 |
11558 | #define smnBIFPLR2_2_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000 |
11559 | #define smnBIFPLR2_2_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000 |
11560 | #define smnBIFPLR2_2_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000002 |
11561 | #define smnBIFPLR2_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000 |
11562 | #define smnBIFPLR2_2_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000 |
11563 | #define smnBIFPLR2_2_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000 |
11564 | #define smnBIFPLR2_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x27020000 |
11565 | #define smnBIFPLR2_2_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 |
11566 | #define smnBIFPLR2_2_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00400000 |
11567 | #define smnBIFPLR2_2_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 |
11568 | #define smnBIFPLR2_2_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 |
11569 | #define smnBIFPLR2_2_PCIE_CORR_ERR_MASK_DEFAULT 0x00006000 |
11570 | #define smnBIFPLR2_2_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 |
11571 | #define smnBIFPLR2_2_PCIE_HDR_LOG0_DEFAULT 0x00000000 |
11572 | #define smnBIFPLR2_2_PCIE_HDR_LOG1_DEFAULT 0x00000000 |
11573 | #define smnBIFPLR2_2_PCIE_HDR_LOG2_DEFAULT 0x00000000 |
11574 | #define smnBIFPLR2_2_PCIE_HDR_LOG3_DEFAULT 0x00000000 |
11575 | #define smnBIFPLR2_2_PCIE_ROOT_ERR_CMD_DEFAULT 0x00000000 |
11576 | #define smnBIFPLR2_2_PCIE_ROOT_ERR_STATUS_DEFAULT 0x00000000 |
11577 | #define smnBIFPLR2_2_PCIE_ERR_SRC_ID_DEFAULT 0x00000000 |
11578 | #define smnBIFPLR2_2_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 |
11579 | #define smnBIFPLR2_2_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 |
11580 | #define smnBIFPLR2_2_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 |
11581 | #define smnBIFPLR2_2_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 |
11582 | #define smnBIFPLR2_2_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a000000 |
11583 | #define smnBIFPLR2_2_PCIE_LINK_CNTL3_DEFAULT 0x00000000 |
11584 | #define smnBIFPLR2_2_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000 |
11585 | #define smnBIFPLR2_2_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
11586 | #define smnBIFPLR2_2_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
11587 | #define smnBIFPLR2_2_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
11588 | #define smnBIFPLR2_2_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
11589 | #define smnBIFPLR2_2_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
11590 | #define smnBIFPLR2_2_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
11591 | #define smnBIFPLR2_2_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
11592 | #define smnBIFPLR2_2_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
11593 | #define smnBIFPLR2_2_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
11594 | #define smnBIFPLR2_2_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
11595 | #define smnBIFPLR2_2_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
11596 | #define smnBIFPLR2_2_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
11597 | #define smnBIFPLR2_2_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
11598 | #define smnBIFPLR2_2_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
11599 | #define smnBIFPLR2_2_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
11600 | #define smnBIFPLR2_2_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
11601 | #define smnBIFPLR2_2_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2f000000 |
11602 | #define smnBIFPLR2_2_PCIE_ACS_CAP_DEFAULT 0x00000000 |
11603 | #define smnBIFPLR2_2_PCIE_ACS_CNTL_DEFAULT 0x00000000 |
11604 | #define smnBIFPLR2_2_PCIE_MC_ENH_CAP_LIST_DEFAULT 0x32000000 |
11605 | #define smnBIFPLR2_2_PCIE_MC_CAP_DEFAULT 0x00000000 |
11606 | #define smnBIFPLR2_2_PCIE_MC_CNTL_DEFAULT 0x00000000 |
11607 | #define smnBIFPLR2_2_PCIE_MC_ADDR0_DEFAULT 0x00000000 |
11608 | #define smnBIFPLR2_2_PCIE_MC_ADDR1_DEFAULT 0x00000000 |
11609 | #define smnBIFPLR2_2_PCIE_MC_RCV0_DEFAULT 0x00000000 |
11610 | #define smnBIFPLR2_2_PCIE_MC_RCV1_DEFAULT 0x00000000 |
11611 | #define smnBIFPLR2_2_PCIE_MC_BLOCK_ALL0_DEFAULT 0x00000000 |
11612 | #define smnBIFPLR2_2_PCIE_MC_BLOCK_ALL1_DEFAULT 0x00000000 |
11613 | #define smnBIFPLR2_2_PCIE_MC_BLOCK_UNTRANSLATED_0_DEFAULT 0x00000000 |
11614 | #define smnBIFPLR2_2_PCIE_MC_BLOCK_UNTRANSLATED_1_DEFAULT 0x00000000 |
11615 | #define smnBIFPLR2_2_PCIE_MC_OVERLAY_BAR0_DEFAULT 0x00000000 |
11616 | #define smnBIFPLR2_2_PCIE_MC_OVERLAY_BAR1_DEFAULT 0x00000000 |
11617 | #define smnBIFPLR2_2_PCIE_L1_PM_SUB_CAP_LIST_DEFAULT 0x00000000 |
11618 | #define smnBIFPLR2_2_PCIE_L1_PM_SUB_CAP_DEFAULT 0x00000000 |
11619 | #define smnBIFPLR2_2_PCIE_L1_PM_SUB_CNTL_DEFAULT 0x00000000 |
11620 | #define smnBIFPLR2_2_PCIE_L1_PM_SUB_CNTL2_DEFAULT 0x00000028 |
11621 | #define smnBIFPLR2_2_PCIE_DPC_ENH_CAP_LIST_DEFAULT 0x00000000 |
11622 | #define smnBIFPLR2_2_PCIE_DPC_CAP_LIST_DEFAULT 0x00000000 |
11623 | #define smnBIFPLR2_2_PCIE_DPC_CNTL_DEFAULT 0x00000000 |
11624 | #define smnBIFPLR2_2_PCIE_DPC_STATUS_DEFAULT 0x00000000 |
11625 | #define smnBIFPLR2_2_PCIE_DPC_ERROR_SOURCE_ID_DEFAULT 0x00000000 |
11626 | #define smnBIFPLR2_2_PCIE_RP_PIO_STATUS_DEFAULT 0x00000000 |
11627 | #define smnBIFPLR2_2_PCIE_RP_PIO_MASK_DEFAULT 0x00070707 |
11628 | #define smnBIFPLR2_2_PCIE_RP_PIO_SEVERITY_DEFAULT 0x00000000 |
11629 | #define smnBIFPLR2_2_PCIE_RP_PIO_SYSERROR_DEFAULT 0x00000000 |
11630 | #define smnBIFPLR2_2_PCIE_RP_PIO_EXCEPTION_DEFAULT 0x00000000 |
11631 | #define smnBIFPLR2_2_PCIE_RP_PIO_HDR_LOG0_DEFAULT 0x00000000 |
11632 | #define smnBIFPLR2_2_PCIE_RP_PIO_HDR_LOG1_DEFAULT 0x00000000 |
11633 | #define smnBIFPLR2_2_PCIE_RP_PIO_HDR_LOG2_DEFAULT 0x00000000 |
11634 | #define smnBIFPLR2_2_PCIE_RP_PIO_HDR_LOG3_DEFAULT 0x00000000 |
11635 | #define smnBIFPLR2_2_PCIE_RP_PIO_IMPSPEC_LOG_DEFAULT 0x00000000 |
11636 | #define smnBIFPLR2_2_PCIE_RP_PIO_PREFIX_LOG0_DEFAULT 0x00000000 |
11637 | #define smnBIFPLR2_2_PCIE_RP_PIO_PREFIX_LOG1_DEFAULT 0x00000000 |
11638 | #define smnBIFPLR2_2_PCIE_RP_PIO_PREFIX_LOG2_DEFAULT 0x00000000 |
11639 | #define smnBIFPLR2_2_PCIE_RP_PIO_PREFIX_LOG3_DEFAULT 0x00000000 |
11640 | #define smnBIFPLR2_2_PCIE_ESM_CAP_LIST_DEFAULT 0x00000000 |
11641 | #define 0x00000000 |
11642 | #define 0x00000000 |
11643 | #define smnBIFPLR2_2_PCIE_ESM_STATUS_DEFAULT 0x00000000 |
11644 | #define smnBIFPLR2_2_PCIE_ESM_CTRL_DEFAULT 0x00000000 |
11645 | #define smnBIFPLR2_2_PCIE_ESM_CAP_1_DEFAULT 0x00000000 |
11646 | #define smnBIFPLR2_2_PCIE_ESM_CAP_2_DEFAULT 0x00000000 |
11647 | #define smnBIFPLR2_2_PCIE_ESM_CAP_3_DEFAULT 0x00000000 |
11648 | #define smnBIFPLR2_2_PCIE_ESM_CAP_4_DEFAULT 0x00000000 |
11649 | #define smnBIFPLR2_2_PCIE_ESM_CAP_5_DEFAULT 0x00000000 |
11650 | #define smnBIFPLR2_2_PCIE_ESM_CAP_6_DEFAULT 0x00000000 |
11651 | #define smnBIFPLR2_2_PCIE_ESM_CAP_7_DEFAULT 0x00000000 |
11652 | |
11653 | |
11654 | // addressBlock: nbio_pcie0_bifplr3_cfgdecp |
11655 | #define smnBIFPLR3_2_VENDOR_ID_DEFAULT 0x00000000 |
11656 | #define smnBIFPLR3_2_DEVICE_ID_DEFAULT 0x00000000 |
11657 | #define smnBIFPLR3_2_COMMAND_DEFAULT 0x00000000 |
11658 | #define smnBIFPLR3_2_STATUS_DEFAULT 0x00000000 |
11659 | #define smnBIFPLR3_2_REVISION_ID_DEFAULT 0x00000000 |
11660 | #define smnBIFPLR3_2_PROG_INTERFACE_DEFAULT 0x00000000 |
11661 | #define smnBIFPLR3_2_SUB_CLASS_DEFAULT 0x00000000 |
11662 | #define smnBIFPLR3_2_BASE_CLASS_DEFAULT 0x00000000 |
11663 | #define smnBIFPLR3_2_CACHE_LINE_DEFAULT 0x00000000 |
11664 | #define smnBIFPLR3_2_LATENCY_DEFAULT 0x00000000 |
11665 | #define 0x00000000 |
11666 | #define smnBIFPLR3_2_BIST_DEFAULT 0x00000000 |
11667 | #define smnBIFPLR3_2_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 |
11668 | #define smnBIFPLR3_2_IO_BASE_LIMIT_DEFAULT 0x00000000 |
11669 | #define smnBIFPLR3_2_SECONDARY_STATUS_DEFAULT 0x00000000 |
11670 | #define smnBIFPLR3_2_MEM_BASE_LIMIT_DEFAULT 0x00000000 |
11671 | #define smnBIFPLR3_2_PREF_BASE_LIMIT_DEFAULT 0x00000000 |
11672 | #define smnBIFPLR3_2_PREF_BASE_UPPER_DEFAULT 0x00000000 |
11673 | #define smnBIFPLR3_2_PREF_LIMIT_UPPER_DEFAULT 0x00000000 |
11674 | #define smnBIFPLR3_2_IO_BASE_LIMIT_HI_DEFAULT 0x00000000 |
11675 | #define smnBIFPLR3_2_CAP_PTR_DEFAULT 0x00000000 |
11676 | #define smnBIFPLR3_2_INTERRUPT_LINE_DEFAULT 0x000000ff |
11677 | #define smnBIFPLR3_2_INTERRUPT_PIN_DEFAULT 0x00000000 |
11678 | #define smnBIFPLR3_2_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000 |
11679 | #define smnBIFPLR3_2_EXT_BRIDGE_CNTL_DEFAULT 0x00000000 |
11680 | #define smnBIFPLR3_2_PMI_CAP_LIST_DEFAULT 0x00000000 |
11681 | #define smnBIFPLR3_2_PMI_CAP_DEFAULT 0x00000000 |
11682 | #define smnBIFPLR3_2_PMI_STATUS_CNTL_DEFAULT 0x00000000 |
11683 | #define smnBIFPLR3_2_PCIE_CAP_LIST_DEFAULT 0x0000a000 |
11684 | #define smnBIFPLR3_2_PCIE_CAP_DEFAULT 0x00000002 |
11685 | #define smnBIFPLR3_2_DEVICE_CAP_DEFAULT 0x00000000 |
11686 | #define smnBIFPLR3_2_DEVICE_CNTL_DEFAULT 0x00002810 |
11687 | #define smnBIFPLR3_2_DEVICE_STATUS_DEFAULT 0x00000000 |
11688 | #define smnBIFPLR3_2_LINK_CAP_DEFAULT 0x00011c03 |
11689 | #define smnBIFPLR3_2_LINK_CNTL_DEFAULT 0x00000000 |
11690 | #define smnBIFPLR3_2_LINK_STATUS_DEFAULT 0x00000001 |
11691 | #define smnBIFPLR3_2_SLOT_CAP_DEFAULT 0x00000000 |
11692 | #define smnBIFPLR3_2_SLOT_CNTL_DEFAULT 0x00000000 |
11693 | #define smnBIFPLR3_2_SLOT_STATUS_DEFAULT 0x00000000 |
11694 | #define smnBIFPLR3_2_ROOT_CNTL_DEFAULT 0x00000000 |
11695 | #define smnBIFPLR3_2_ROOT_CAP_DEFAULT 0x00000000 |
11696 | #define smnBIFPLR3_2_ROOT_STATUS_DEFAULT 0x00000000 |
11697 | #define smnBIFPLR3_2_DEVICE_CAP2_DEFAULT 0x00000000 |
11698 | #define smnBIFPLR3_2_DEVICE_CNTL2_DEFAULT 0x00000000 |
11699 | #define smnBIFPLR3_2_DEVICE_STATUS2_DEFAULT 0x00000000 |
11700 | #define smnBIFPLR3_2_LINK_CAP2_DEFAULT 0x0000000e |
11701 | #define smnBIFPLR3_2_LINK_CNTL2_DEFAULT 0x00000003 |
11702 | #define smnBIFPLR3_2_LINK_STATUS2_DEFAULT 0x00000000 |
11703 | #define smnBIFPLR3_2_SLOT_CAP2_DEFAULT 0x00000000 |
11704 | #define smnBIFPLR3_2_SLOT_CNTL2_DEFAULT 0x00000000 |
11705 | #define smnBIFPLR3_2_SLOT_STATUS2_DEFAULT 0x00000000 |
11706 | #define smnBIFPLR3_2_MSI_CAP_LIST_DEFAULT 0x0000c000 |
11707 | #define smnBIFPLR3_2_MSI_MSG_CNTL_DEFAULT 0x00000000 |
11708 | #define smnBIFPLR3_2_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 |
11709 | #define smnBIFPLR3_2_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 |
11710 | #define smnBIFPLR3_2_MSI_MSG_DATA_DEFAULT 0x00000000 |
11711 | #define smnBIFPLR3_2_MSI_MSG_DATA_64_DEFAULT 0x00000000 |
11712 | #define smnBIFPLR3_2_SSID_CAP_LIST_DEFAULT 0x0000c800 |
11713 | #define smnBIFPLR3_2_SSID_CAP_DEFAULT 0x00000000 |
11714 | #define smnBIFPLR3_2_MSI_MAP_CAP_LIST_DEFAULT 0x00000000 |
11715 | #define smnBIFPLR3_2_MSI_MAP_CAP_DEFAULT 0x00000000 |
11716 | #define smnBIFPLR3_2_MSI_MAP_ADDR_LO_DEFAULT 0x00000000 |
11717 | #define smnBIFPLR3_2_MSI_MAP_ADDR_HI_DEFAULT 0x00000000 |
11718 | #define smnBIFPLR3_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 |
11719 | #define smnBIFPLR3_2_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 |
11720 | #define smnBIFPLR3_2_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 |
11721 | #define smnBIFPLR3_2_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 |
11722 | #define smnBIFPLR3_2_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000 |
11723 | #define smnBIFPLR3_2_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000 |
11724 | #define smnBIFPLR3_2_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000 |
11725 | #define smnBIFPLR3_2_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000 |
11726 | #define smnBIFPLR3_2_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000 |
11727 | #define smnBIFPLR3_2_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000 |
11728 | #define smnBIFPLR3_2_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe |
11729 | #define smnBIFPLR3_2_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000002 |
11730 | #define smnBIFPLR3_2_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000 |
11731 | #define smnBIFPLR3_2_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000 |
11732 | #define smnBIFPLR3_2_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000002 |
11733 | #define smnBIFPLR3_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000 |
11734 | #define smnBIFPLR3_2_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000 |
11735 | #define smnBIFPLR3_2_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000 |
11736 | #define smnBIFPLR3_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x27020000 |
11737 | #define smnBIFPLR3_2_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 |
11738 | #define smnBIFPLR3_2_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00400000 |
11739 | #define smnBIFPLR3_2_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 |
11740 | #define smnBIFPLR3_2_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 |
11741 | #define smnBIFPLR3_2_PCIE_CORR_ERR_MASK_DEFAULT 0x00006000 |
11742 | #define smnBIFPLR3_2_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 |
11743 | #define smnBIFPLR3_2_PCIE_HDR_LOG0_DEFAULT 0x00000000 |
11744 | #define smnBIFPLR3_2_PCIE_HDR_LOG1_DEFAULT 0x00000000 |
11745 | #define smnBIFPLR3_2_PCIE_HDR_LOG2_DEFAULT 0x00000000 |
11746 | #define smnBIFPLR3_2_PCIE_HDR_LOG3_DEFAULT 0x00000000 |
11747 | #define smnBIFPLR3_2_PCIE_ROOT_ERR_CMD_DEFAULT 0x00000000 |
11748 | #define smnBIFPLR3_2_PCIE_ROOT_ERR_STATUS_DEFAULT 0x00000000 |
11749 | #define smnBIFPLR3_2_PCIE_ERR_SRC_ID_DEFAULT 0x00000000 |
11750 | #define smnBIFPLR3_2_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 |
11751 | #define smnBIFPLR3_2_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 |
11752 | #define smnBIFPLR3_2_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 |
11753 | #define smnBIFPLR3_2_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 |
11754 | #define smnBIFPLR3_2_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a000000 |
11755 | #define smnBIFPLR3_2_PCIE_LINK_CNTL3_DEFAULT 0x00000000 |
11756 | #define smnBIFPLR3_2_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000 |
11757 | #define smnBIFPLR3_2_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
11758 | #define smnBIFPLR3_2_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
11759 | #define smnBIFPLR3_2_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
11760 | #define smnBIFPLR3_2_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
11761 | #define smnBIFPLR3_2_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
11762 | #define smnBIFPLR3_2_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
11763 | #define smnBIFPLR3_2_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
11764 | #define smnBIFPLR3_2_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
11765 | #define smnBIFPLR3_2_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
11766 | #define smnBIFPLR3_2_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
11767 | #define smnBIFPLR3_2_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
11768 | #define smnBIFPLR3_2_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
11769 | #define smnBIFPLR3_2_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
11770 | #define smnBIFPLR3_2_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
11771 | #define smnBIFPLR3_2_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
11772 | #define smnBIFPLR3_2_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
11773 | #define smnBIFPLR3_2_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2f000000 |
11774 | #define smnBIFPLR3_2_PCIE_ACS_CAP_DEFAULT 0x00000000 |
11775 | #define smnBIFPLR3_2_PCIE_ACS_CNTL_DEFAULT 0x00000000 |
11776 | #define smnBIFPLR3_2_PCIE_MC_ENH_CAP_LIST_DEFAULT 0x32000000 |
11777 | #define smnBIFPLR3_2_PCIE_MC_CAP_DEFAULT 0x00000000 |
11778 | #define smnBIFPLR3_2_PCIE_MC_CNTL_DEFAULT 0x00000000 |
11779 | #define smnBIFPLR3_2_PCIE_MC_ADDR0_DEFAULT 0x00000000 |
11780 | #define smnBIFPLR3_2_PCIE_MC_ADDR1_DEFAULT 0x00000000 |
11781 | #define smnBIFPLR3_2_PCIE_MC_RCV0_DEFAULT 0x00000000 |
11782 | #define smnBIFPLR3_2_PCIE_MC_RCV1_DEFAULT 0x00000000 |
11783 | #define smnBIFPLR3_2_PCIE_MC_BLOCK_ALL0_DEFAULT 0x00000000 |
11784 | #define smnBIFPLR3_2_PCIE_MC_BLOCK_ALL1_DEFAULT 0x00000000 |
11785 | #define smnBIFPLR3_2_PCIE_MC_BLOCK_UNTRANSLATED_0_DEFAULT 0x00000000 |
11786 | #define smnBIFPLR3_2_PCIE_MC_BLOCK_UNTRANSLATED_1_DEFAULT 0x00000000 |
11787 | #define smnBIFPLR3_2_PCIE_MC_OVERLAY_BAR0_DEFAULT 0x00000000 |
11788 | #define smnBIFPLR3_2_PCIE_MC_OVERLAY_BAR1_DEFAULT 0x00000000 |
11789 | #define smnBIFPLR3_2_PCIE_L1_PM_SUB_CAP_LIST_DEFAULT 0x00000000 |
11790 | #define smnBIFPLR3_2_PCIE_L1_PM_SUB_CAP_DEFAULT 0x00000000 |
11791 | #define smnBIFPLR3_2_PCIE_L1_PM_SUB_CNTL_DEFAULT 0x00000000 |
11792 | #define smnBIFPLR3_2_PCIE_L1_PM_SUB_CNTL2_DEFAULT 0x00000028 |
11793 | #define smnBIFPLR3_2_PCIE_DPC_ENH_CAP_LIST_DEFAULT 0x00000000 |
11794 | #define smnBIFPLR3_2_PCIE_DPC_CAP_LIST_DEFAULT 0x00000000 |
11795 | #define smnBIFPLR3_2_PCIE_DPC_CNTL_DEFAULT 0x00000000 |
11796 | #define smnBIFPLR3_2_PCIE_DPC_STATUS_DEFAULT 0x00000000 |
11797 | #define smnBIFPLR3_2_PCIE_DPC_ERROR_SOURCE_ID_DEFAULT 0x00000000 |
11798 | #define smnBIFPLR3_2_PCIE_RP_PIO_STATUS_DEFAULT 0x00000000 |
11799 | #define smnBIFPLR3_2_PCIE_RP_PIO_MASK_DEFAULT 0x00070707 |
11800 | #define smnBIFPLR3_2_PCIE_RP_PIO_SEVERITY_DEFAULT 0x00000000 |
11801 | #define smnBIFPLR3_2_PCIE_RP_PIO_SYSERROR_DEFAULT 0x00000000 |
11802 | #define smnBIFPLR3_2_PCIE_RP_PIO_EXCEPTION_DEFAULT 0x00000000 |
11803 | #define smnBIFPLR3_2_PCIE_RP_PIO_HDR_LOG0_DEFAULT 0x00000000 |
11804 | #define smnBIFPLR3_2_PCIE_RP_PIO_HDR_LOG1_DEFAULT 0x00000000 |
11805 | #define smnBIFPLR3_2_PCIE_RP_PIO_HDR_LOG2_DEFAULT 0x00000000 |
11806 | #define smnBIFPLR3_2_PCIE_RP_PIO_HDR_LOG3_DEFAULT 0x00000000 |
11807 | #define smnBIFPLR3_2_PCIE_RP_PIO_IMPSPEC_LOG_DEFAULT 0x00000000 |
11808 | #define smnBIFPLR3_2_PCIE_RP_PIO_PREFIX_LOG0_DEFAULT 0x00000000 |
11809 | #define smnBIFPLR3_2_PCIE_RP_PIO_PREFIX_LOG1_DEFAULT 0x00000000 |
11810 | #define smnBIFPLR3_2_PCIE_RP_PIO_PREFIX_LOG2_DEFAULT 0x00000000 |
11811 | #define smnBIFPLR3_2_PCIE_RP_PIO_PREFIX_LOG3_DEFAULT 0x00000000 |
11812 | #define smnBIFPLR3_2_PCIE_ESM_CAP_LIST_DEFAULT 0x00000000 |
11813 | #define 0x00000000 |
11814 | #define 0x00000000 |
11815 | #define smnBIFPLR3_2_PCIE_ESM_STATUS_DEFAULT 0x00000000 |
11816 | #define smnBIFPLR3_2_PCIE_ESM_CTRL_DEFAULT 0x00000000 |
11817 | #define smnBIFPLR3_2_PCIE_ESM_CAP_1_DEFAULT 0x00000000 |
11818 | #define smnBIFPLR3_2_PCIE_ESM_CAP_2_DEFAULT 0x00000000 |
11819 | #define smnBIFPLR3_2_PCIE_ESM_CAP_3_DEFAULT 0x00000000 |
11820 | #define smnBIFPLR3_2_PCIE_ESM_CAP_4_DEFAULT 0x00000000 |
11821 | #define smnBIFPLR3_2_PCIE_ESM_CAP_5_DEFAULT 0x00000000 |
11822 | #define smnBIFPLR3_2_PCIE_ESM_CAP_6_DEFAULT 0x00000000 |
11823 | #define smnBIFPLR3_2_PCIE_ESM_CAP_7_DEFAULT 0x00000000 |
11824 | |
11825 | |
11826 | // addressBlock: nbio_pcie0_bifplr4_cfgdecp |
11827 | #define smnBIFPLR4_2_VENDOR_ID_DEFAULT 0x00000000 |
11828 | #define smnBIFPLR4_2_DEVICE_ID_DEFAULT 0x00000000 |
11829 | #define smnBIFPLR4_2_COMMAND_DEFAULT 0x00000000 |
11830 | #define smnBIFPLR4_2_STATUS_DEFAULT 0x00000000 |
11831 | #define smnBIFPLR4_2_REVISION_ID_DEFAULT 0x00000000 |
11832 | #define smnBIFPLR4_2_PROG_INTERFACE_DEFAULT 0x00000000 |
11833 | #define smnBIFPLR4_2_SUB_CLASS_DEFAULT 0x00000000 |
11834 | #define smnBIFPLR4_2_BASE_CLASS_DEFAULT 0x00000000 |
11835 | #define smnBIFPLR4_2_CACHE_LINE_DEFAULT 0x00000000 |
11836 | #define smnBIFPLR4_2_LATENCY_DEFAULT 0x00000000 |
11837 | #define 0x00000000 |
11838 | #define smnBIFPLR4_2_BIST_DEFAULT 0x00000000 |
11839 | #define smnBIFPLR4_2_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 |
11840 | #define smnBIFPLR4_2_IO_BASE_LIMIT_DEFAULT 0x00000000 |
11841 | #define smnBIFPLR4_2_SECONDARY_STATUS_DEFAULT 0x00000000 |
11842 | #define smnBIFPLR4_2_MEM_BASE_LIMIT_DEFAULT 0x00000000 |
11843 | #define smnBIFPLR4_2_PREF_BASE_LIMIT_DEFAULT 0x00000000 |
11844 | #define smnBIFPLR4_2_PREF_BASE_UPPER_DEFAULT 0x00000000 |
11845 | #define smnBIFPLR4_2_PREF_LIMIT_UPPER_DEFAULT 0x00000000 |
11846 | #define smnBIFPLR4_2_IO_BASE_LIMIT_HI_DEFAULT 0x00000000 |
11847 | #define smnBIFPLR4_2_CAP_PTR_DEFAULT 0x00000000 |
11848 | #define smnBIFPLR4_2_INTERRUPT_LINE_DEFAULT 0x000000ff |
11849 | #define smnBIFPLR4_2_INTERRUPT_PIN_DEFAULT 0x00000000 |
11850 | #define smnBIFPLR4_2_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000 |
11851 | #define smnBIFPLR4_2_EXT_BRIDGE_CNTL_DEFAULT 0x00000000 |
11852 | #define smnBIFPLR4_2_PMI_CAP_LIST_DEFAULT 0x00000000 |
11853 | #define smnBIFPLR4_2_PMI_CAP_DEFAULT 0x00000000 |
11854 | #define smnBIFPLR4_2_PMI_STATUS_CNTL_DEFAULT 0x00000000 |
11855 | #define smnBIFPLR4_2_PCIE_CAP_LIST_DEFAULT 0x0000a000 |
11856 | #define smnBIFPLR4_2_PCIE_CAP_DEFAULT 0x00000002 |
11857 | #define smnBIFPLR4_2_DEVICE_CAP_DEFAULT 0x00000000 |
11858 | #define smnBIFPLR4_2_DEVICE_CNTL_DEFAULT 0x00002810 |
11859 | #define smnBIFPLR4_2_DEVICE_STATUS_DEFAULT 0x00000000 |
11860 | #define smnBIFPLR4_2_LINK_CAP_DEFAULT 0x00011c03 |
11861 | #define smnBIFPLR4_2_LINK_CNTL_DEFAULT 0x00000000 |
11862 | #define smnBIFPLR4_2_LINK_STATUS_DEFAULT 0x00000001 |
11863 | #define smnBIFPLR4_2_SLOT_CAP_DEFAULT 0x00000000 |
11864 | #define smnBIFPLR4_2_SLOT_CNTL_DEFAULT 0x00000000 |
11865 | #define smnBIFPLR4_2_SLOT_STATUS_DEFAULT 0x00000000 |
11866 | #define smnBIFPLR4_2_ROOT_CNTL_DEFAULT 0x00000000 |
11867 | #define smnBIFPLR4_2_ROOT_CAP_DEFAULT 0x00000000 |
11868 | #define smnBIFPLR4_2_ROOT_STATUS_DEFAULT 0x00000000 |
11869 | #define smnBIFPLR4_2_DEVICE_CAP2_DEFAULT 0x00000000 |
11870 | #define smnBIFPLR4_2_DEVICE_CNTL2_DEFAULT 0x00000000 |
11871 | #define smnBIFPLR4_2_DEVICE_STATUS2_DEFAULT 0x00000000 |
11872 | #define smnBIFPLR4_2_LINK_CAP2_DEFAULT 0x0000000e |
11873 | #define smnBIFPLR4_2_LINK_CNTL2_DEFAULT 0x00000003 |
11874 | #define smnBIFPLR4_2_LINK_STATUS2_DEFAULT 0x00000000 |
11875 | #define smnBIFPLR4_2_SLOT_CAP2_DEFAULT 0x00000000 |
11876 | #define smnBIFPLR4_2_SLOT_CNTL2_DEFAULT 0x00000000 |
11877 | #define smnBIFPLR4_2_SLOT_STATUS2_DEFAULT 0x00000000 |
11878 | #define smnBIFPLR4_2_MSI_CAP_LIST_DEFAULT 0x0000c000 |
11879 | #define smnBIFPLR4_2_MSI_MSG_CNTL_DEFAULT 0x00000000 |
11880 | #define smnBIFPLR4_2_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 |
11881 | #define smnBIFPLR4_2_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 |
11882 | #define smnBIFPLR4_2_MSI_MSG_DATA_DEFAULT 0x00000000 |
11883 | #define smnBIFPLR4_2_MSI_MSG_DATA_64_DEFAULT 0x00000000 |
11884 | #define smnBIFPLR4_2_SSID_CAP_LIST_DEFAULT 0x0000c800 |
11885 | #define smnBIFPLR4_2_SSID_CAP_DEFAULT 0x00000000 |
11886 | #define smnBIFPLR4_2_MSI_MAP_CAP_LIST_DEFAULT 0x00000000 |
11887 | #define smnBIFPLR4_2_MSI_MAP_CAP_DEFAULT 0x00000000 |
11888 | #define smnBIFPLR4_2_MSI_MAP_ADDR_LO_DEFAULT 0x00000000 |
11889 | #define smnBIFPLR4_2_MSI_MAP_ADDR_HI_DEFAULT 0x00000000 |
11890 | #define smnBIFPLR4_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 |
11891 | #define smnBIFPLR4_2_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 |
11892 | #define smnBIFPLR4_2_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 |
11893 | #define smnBIFPLR4_2_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 |
11894 | #define smnBIFPLR4_2_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000 |
11895 | #define smnBIFPLR4_2_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000 |
11896 | #define smnBIFPLR4_2_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000 |
11897 | #define smnBIFPLR4_2_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000 |
11898 | #define smnBIFPLR4_2_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000 |
11899 | #define smnBIFPLR4_2_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000 |
11900 | #define smnBIFPLR4_2_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe |
11901 | #define smnBIFPLR4_2_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000002 |
11902 | #define smnBIFPLR4_2_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000 |
11903 | #define smnBIFPLR4_2_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000 |
11904 | #define smnBIFPLR4_2_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000002 |
11905 | #define smnBIFPLR4_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000 |
11906 | #define smnBIFPLR4_2_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000 |
11907 | #define smnBIFPLR4_2_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000 |
11908 | #define smnBIFPLR4_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x27020000 |
11909 | #define smnBIFPLR4_2_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 |
11910 | #define smnBIFPLR4_2_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00400000 |
11911 | #define smnBIFPLR4_2_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 |
11912 | #define smnBIFPLR4_2_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 |
11913 | #define smnBIFPLR4_2_PCIE_CORR_ERR_MASK_DEFAULT 0x00006000 |
11914 | #define smnBIFPLR4_2_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 |
11915 | #define smnBIFPLR4_2_PCIE_HDR_LOG0_DEFAULT 0x00000000 |
11916 | #define smnBIFPLR4_2_PCIE_HDR_LOG1_DEFAULT 0x00000000 |
11917 | #define smnBIFPLR4_2_PCIE_HDR_LOG2_DEFAULT 0x00000000 |
11918 | #define smnBIFPLR4_2_PCIE_HDR_LOG3_DEFAULT 0x00000000 |
11919 | #define smnBIFPLR4_2_PCIE_ROOT_ERR_CMD_DEFAULT 0x00000000 |
11920 | #define smnBIFPLR4_2_PCIE_ROOT_ERR_STATUS_DEFAULT 0x00000000 |
11921 | #define smnBIFPLR4_2_PCIE_ERR_SRC_ID_DEFAULT 0x00000000 |
11922 | #define smnBIFPLR4_2_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 |
11923 | #define smnBIFPLR4_2_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 |
11924 | #define smnBIFPLR4_2_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 |
11925 | #define smnBIFPLR4_2_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 |
11926 | #define smnBIFPLR4_2_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a000000 |
11927 | #define smnBIFPLR4_2_PCIE_LINK_CNTL3_DEFAULT 0x00000000 |
11928 | #define smnBIFPLR4_2_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000 |
11929 | #define smnBIFPLR4_2_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
11930 | #define smnBIFPLR4_2_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
11931 | #define smnBIFPLR4_2_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
11932 | #define smnBIFPLR4_2_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
11933 | #define smnBIFPLR4_2_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
11934 | #define smnBIFPLR4_2_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
11935 | #define smnBIFPLR4_2_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
11936 | #define smnBIFPLR4_2_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
11937 | #define smnBIFPLR4_2_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
11938 | #define smnBIFPLR4_2_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
11939 | #define smnBIFPLR4_2_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
11940 | #define smnBIFPLR4_2_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
11941 | #define smnBIFPLR4_2_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
11942 | #define smnBIFPLR4_2_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
11943 | #define smnBIFPLR4_2_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
11944 | #define smnBIFPLR4_2_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
11945 | #define smnBIFPLR4_2_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2f000000 |
11946 | #define smnBIFPLR4_2_PCIE_ACS_CAP_DEFAULT 0x00000000 |
11947 | #define smnBIFPLR4_2_PCIE_ACS_CNTL_DEFAULT 0x00000000 |
11948 | #define smnBIFPLR4_2_PCIE_MC_ENH_CAP_LIST_DEFAULT 0x32000000 |
11949 | #define smnBIFPLR4_2_PCIE_MC_CAP_DEFAULT 0x00000000 |
11950 | #define smnBIFPLR4_2_PCIE_MC_CNTL_DEFAULT 0x00000000 |
11951 | #define smnBIFPLR4_2_PCIE_MC_ADDR0_DEFAULT 0x00000000 |
11952 | #define smnBIFPLR4_2_PCIE_MC_ADDR1_DEFAULT 0x00000000 |
11953 | #define smnBIFPLR4_2_PCIE_MC_RCV0_DEFAULT 0x00000000 |
11954 | #define smnBIFPLR4_2_PCIE_MC_RCV1_DEFAULT 0x00000000 |
11955 | #define smnBIFPLR4_2_PCIE_MC_BLOCK_ALL0_DEFAULT 0x00000000 |
11956 | #define smnBIFPLR4_2_PCIE_MC_BLOCK_ALL1_DEFAULT 0x00000000 |
11957 | #define smnBIFPLR4_2_PCIE_MC_BLOCK_UNTRANSLATED_0_DEFAULT 0x00000000 |
11958 | #define smnBIFPLR4_2_PCIE_MC_BLOCK_UNTRANSLATED_1_DEFAULT 0x00000000 |
11959 | #define smnBIFPLR4_2_PCIE_MC_OVERLAY_BAR0_DEFAULT 0x00000000 |
11960 | #define smnBIFPLR4_2_PCIE_MC_OVERLAY_BAR1_DEFAULT 0x00000000 |
11961 | #define smnBIFPLR4_2_PCIE_L1_PM_SUB_CAP_LIST_DEFAULT 0x00000000 |
11962 | #define smnBIFPLR4_2_PCIE_L1_PM_SUB_CAP_DEFAULT 0x00000000 |
11963 | #define smnBIFPLR4_2_PCIE_L1_PM_SUB_CNTL_DEFAULT 0x00000000 |
11964 | #define smnBIFPLR4_2_PCIE_L1_PM_SUB_CNTL2_DEFAULT 0x00000028 |
11965 | #define smnBIFPLR4_2_PCIE_DPC_ENH_CAP_LIST_DEFAULT 0x00000000 |
11966 | #define smnBIFPLR4_2_PCIE_DPC_CAP_LIST_DEFAULT 0x00000000 |
11967 | #define smnBIFPLR4_2_PCIE_DPC_CNTL_DEFAULT 0x00000000 |
11968 | #define smnBIFPLR4_2_PCIE_DPC_STATUS_DEFAULT 0x00000000 |
11969 | #define smnBIFPLR4_2_PCIE_DPC_ERROR_SOURCE_ID_DEFAULT 0x00000000 |
11970 | #define smnBIFPLR4_2_PCIE_RP_PIO_STATUS_DEFAULT 0x00000000 |
11971 | #define smnBIFPLR4_2_PCIE_RP_PIO_MASK_DEFAULT 0x00070707 |
11972 | #define smnBIFPLR4_2_PCIE_RP_PIO_SEVERITY_DEFAULT 0x00000000 |
11973 | #define smnBIFPLR4_2_PCIE_RP_PIO_SYSERROR_DEFAULT 0x00000000 |
11974 | #define smnBIFPLR4_2_PCIE_RP_PIO_EXCEPTION_DEFAULT 0x00000000 |
11975 | #define smnBIFPLR4_2_PCIE_RP_PIO_HDR_LOG0_DEFAULT 0x00000000 |
11976 | #define smnBIFPLR4_2_PCIE_RP_PIO_HDR_LOG1_DEFAULT 0x00000000 |
11977 | #define smnBIFPLR4_2_PCIE_RP_PIO_HDR_LOG2_DEFAULT 0x00000000 |
11978 | #define smnBIFPLR4_2_PCIE_RP_PIO_HDR_LOG3_DEFAULT 0x00000000 |
11979 | #define smnBIFPLR4_2_PCIE_RP_PIO_IMPSPEC_LOG_DEFAULT 0x00000000 |
11980 | #define smnBIFPLR4_2_PCIE_RP_PIO_PREFIX_LOG0_DEFAULT 0x00000000 |
11981 | #define smnBIFPLR4_2_PCIE_RP_PIO_PREFIX_LOG1_DEFAULT 0x00000000 |
11982 | #define smnBIFPLR4_2_PCIE_RP_PIO_PREFIX_LOG2_DEFAULT 0x00000000 |
11983 | #define smnBIFPLR4_2_PCIE_RP_PIO_PREFIX_LOG3_DEFAULT 0x00000000 |
11984 | #define smnBIFPLR4_2_PCIE_ESM_CAP_LIST_DEFAULT 0x00000000 |
11985 | #define 0x00000000 |
11986 | #define 0x00000000 |
11987 | #define smnBIFPLR4_2_PCIE_ESM_STATUS_DEFAULT 0x00000000 |
11988 | #define smnBIFPLR4_2_PCIE_ESM_CTRL_DEFAULT 0x00000000 |
11989 | #define smnBIFPLR4_2_PCIE_ESM_CAP_1_DEFAULT 0x00000000 |
11990 | #define smnBIFPLR4_2_PCIE_ESM_CAP_2_DEFAULT 0x00000000 |
11991 | #define smnBIFPLR4_2_PCIE_ESM_CAP_3_DEFAULT 0x00000000 |
11992 | #define smnBIFPLR4_2_PCIE_ESM_CAP_4_DEFAULT 0x00000000 |
11993 | #define smnBIFPLR4_2_PCIE_ESM_CAP_5_DEFAULT 0x00000000 |
11994 | #define smnBIFPLR4_2_PCIE_ESM_CAP_6_DEFAULT 0x00000000 |
11995 | #define smnBIFPLR4_2_PCIE_ESM_CAP_7_DEFAULT 0x00000000 |
11996 | |
11997 | |
11998 | // addressBlock: nbio_pcie0_bifplr5_cfgdecp |
11999 | #define smnBIFPLR5_2_VENDOR_ID_DEFAULT 0x00000000 |
12000 | #define smnBIFPLR5_2_DEVICE_ID_DEFAULT 0x00000000 |
12001 | #define smnBIFPLR5_2_COMMAND_DEFAULT 0x00000000 |
12002 | #define smnBIFPLR5_2_STATUS_DEFAULT 0x00000000 |
12003 | #define smnBIFPLR5_2_REVISION_ID_DEFAULT 0x00000000 |
12004 | #define smnBIFPLR5_2_PROG_INTERFACE_DEFAULT 0x00000000 |
12005 | #define smnBIFPLR5_2_SUB_CLASS_DEFAULT 0x00000000 |
12006 | #define smnBIFPLR5_2_BASE_CLASS_DEFAULT 0x00000000 |
12007 | #define smnBIFPLR5_2_CACHE_LINE_DEFAULT 0x00000000 |
12008 | #define smnBIFPLR5_2_LATENCY_DEFAULT 0x00000000 |
12009 | #define 0x00000000 |
12010 | #define smnBIFPLR5_2_BIST_DEFAULT 0x00000000 |
12011 | #define smnBIFPLR5_2_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 |
12012 | #define smnBIFPLR5_2_IO_BASE_LIMIT_DEFAULT 0x00000000 |
12013 | #define smnBIFPLR5_2_SECONDARY_STATUS_DEFAULT 0x00000000 |
12014 | #define smnBIFPLR5_2_MEM_BASE_LIMIT_DEFAULT 0x00000000 |
12015 | #define smnBIFPLR5_2_PREF_BASE_LIMIT_DEFAULT 0x00000000 |
12016 | #define smnBIFPLR5_2_PREF_BASE_UPPER_DEFAULT 0x00000000 |
12017 | #define smnBIFPLR5_2_PREF_LIMIT_UPPER_DEFAULT 0x00000000 |
12018 | #define smnBIFPLR5_2_IO_BASE_LIMIT_HI_DEFAULT 0x00000000 |
12019 | #define smnBIFPLR5_2_CAP_PTR_DEFAULT 0x00000000 |
12020 | #define smnBIFPLR5_2_INTERRUPT_LINE_DEFAULT 0x000000ff |
12021 | #define smnBIFPLR5_2_INTERRUPT_PIN_DEFAULT 0x00000000 |
12022 | #define smnBIFPLR5_2_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000 |
12023 | #define smnBIFPLR5_2_EXT_BRIDGE_CNTL_DEFAULT 0x00000000 |
12024 | #define smnBIFPLR5_2_PMI_CAP_LIST_DEFAULT 0x00000000 |
12025 | #define smnBIFPLR5_2_PMI_CAP_DEFAULT 0x00000000 |
12026 | #define smnBIFPLR5_2_PMI_STATUS_CNTL_DEFAULT 0x00000000 |
12027 | #define smnBIFPLR5_2_PCIE_CAP_LIST_DEFAULT 0x0000a000 |
12028 | #define smnBIFPLR5_2_PCIE_CAP_DEFAULT 0x00000002 |
12029 | #define smnBIFPLR5_2_DEVICE_CAP_DEFAULT 0x00000000 |
12030 | #define smnBIFPLR5_2_DEVICE_CNTL_DEFAULT 0x00002810 |
12031 | #define smnBIFPLR5_2_DEVICE_STATUS_DEFAULT 0x00000000 |
12032 | #define smnBIFPLR5_2_LINK_CAP_DEFAULT 0x00011c03 |
12033 | #define smnBIFPLR5_2_LINK_CNTL_DEFAULT 0x00000000 |
12034 | #define smnBIFPLR5_2_LINK_STATUS_DEFAULT 0x00000001 |
12035 | #define smnBIFPLR5_2_SLOT_CAP_DEFAULT 0x00000000 |
12036 | #define smnBIFPLR5_2_SLOT_CNTL_DEFAULT 0x00000000 |
12037 | #define smnBIFPLR5_2_SLOT_STATUS_DEFAULT 0x00000000 |
12038 | #define smnBIFPLR5_2_ROOT_CNTL_DEFAULT 0x00000000 |
12039 | #define smnBIFPLR5_2_ROOT_CAP_DEFAULT 0x00000000 |
12040 | #define smnBIFPLR5_2_ROOT_STATUS_DEFAULT 0x00000000 |
12041 | #define smnBIFPLR5_2_DEVICE_CAP2_DEFAULT 0x00000000 |
12042 | #define smnBIFPLR5_2_DEVICE_CNTL2_DEFAULT 0x00000000 |
12043 | #define smnBIFPLR5_2_DEVICE_STATUS2_DEFAULT 0x00000000 |
12044 | #define smnBIFPLR5_2_LINK_CAP2_DEFAULT 0x0000000e |
12045 | #define smnBIFPLR5_2_LINK_CNTL2_DEFAULT 0x00000003 |
12046 | #define smnBIFPLR5_2_LINK_STATUS2_DEFAULT 0x00000000 |
12047 | #define smnBIFPLR5_2_SLOT_CAP2_DEFAULT 0x00000000 |
12048 | #define smnBIFPLR5_2_SLOT_CNTL2_DEFAULT 0x00000000 |
12049 | #define smnBIFPLR5_2_SLOT_STATUS2_DEFAULT 0x00000000 |
12050 | #define smnBIFPLR5_2_MSI_CAP_LIST_DEFAULT 0x0000c000 |
12051 | #define smnBIFPLR5_2_MSI_MSG_CNTL_DEFAULT 0x00000000 |
12052 | #define smnBIFPLR5_2_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 |
12053 | #define smnBIFPLR5_2_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 |
12054 | #define smnBIFPLR5_2_MSI_MSG_DATA_DEFAULT 0x00000000 |
12055 | #define smnBIFPLR5_2_MSI_MSG_DATA_64_DEFAULT 0x00000000 |
12056 | #define smnBIFPLR5_2_SSID_CAP_LIST_DEFAULT 0x0000c800 |
12057 | #define smnBIFPLR5_2_SSID_CAP_DEFAULT 0x00000000 |
12058 | #define smnBIFPLR5_2_MSI_MAP_CAP_LIST_DEFAULT 0x00000000 |
12059 | #define smnBIFPLR5_2_MSI_MAP_CAP_DEFAULT 0x00000000 |
12060 | #define smnBIFPLR5_2_MSI_MAP_ADDR_LO_DEFAULT 0x00000000 |
12061 | #define smnBIFPLR5_2_MSI_MAP_ADDR_HI_DEFAULT 0x00000000 |
12062 | #define smnBIFPLR5_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 |
12063 | #define smnBIFPLR5_2_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 |
12064 | #define smnBIFPLR5_2_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 |
12065 | #define smnBIFPLR5_2_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 |
12066 | #define smnBIFPLR5_2_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000 |
12067 | #define smnBIFPLR5_2_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000 |
12068 | #define smnBIFPLR5_2_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000 |
12069 | #define smnBIFPLR5_2_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000 |
12070 | #define smnBIFPLR5_2_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000 |
12071 | #define smnBIFPLR5_2_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000 |
12072 | #define smnBIFPLR5_2_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe |
12073 | #define smnBIFPLR5_2_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000002 |
12074 | #define smnBIFPLR5_2_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000 |
12075 | #define smnBIFPLR5_2_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000 |
12076 | #define smnBIFPLR5_2_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000002 |
12077 | #define smnBIFPLR5_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000 |
12078 | #define smnBIFPLR5_2_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000 |
12079 | #define smnBIFPLR5_2_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000 |
12080 | #define smnBIFPLR5_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x27020000 |
12081 | #define smnBIFPLR5_2_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 |
12082 | #define smnBIFPLR5_2_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00400000 |
12083 | #define smnBIFPLR5_2_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 |
12084 | #define smnBIFPLR5_2_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 |
12085 | #define smnBIFPLR5_2_PCIE_CORR_ERR_MASK_DEFAULT 0x00006000 |
12086 | #define smnBIFPLR5_2_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 |
12087 | #define smnBIFPLR5_2_PCIE_HDR_LOG0_DEFAULT 0x00000000 |
12088 | #define smnBIFPLR5_2_PCIE_HDR_LOG1_DEFAULT 0x00000000 |
12089 | #define smnBIFPLR5_2_PCIE_HDR_LOG2_DEFAULT 0x00000000 |
12090 | #define smnBIFPLR5_2_PCIE_HDR_LOG3_DEFAULT 0x00000000 |
12091 | #define smnBIFPLR5_2_PCIE_ROOT_ERR_CMD_DEFAULT 0x00000000 |
12092 | #define smnBIFPLR5_2_PCIE_ROOT_ERR_STATUS_DEFAULT 0x00000000 |
12093 | #define smnBIFPLR5_2_PCIE_ERR_SRC_ID_DEFAULT 0x00000000 |
12094 | #define smnBIFPLR5_2_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 |
12095 | #define smnBIFPLR5_2_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 |
12096 | #define smnBIFPLR5_2_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 |
12097 | #define smnBIFPLR5_2_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 |
12098 | #define smnBIFPLR5_2_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a000000 |
12099 | #define smnBIFPLR5_2_PCIE_LINK_CNTL3_DEFAULT 0x00000000 |
12100 | #define smnBIFPLR5_2_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000 |
12101 | #define smnBIFPLR5_2_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
12102 | #define smnBIFPLR5_2_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
12103 | #define smnBIFPLR5_2_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
12104 | #define smnBIFPLR5_2_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
12105 | #define smnBIFPLR5_2_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
12106 | #define smnBIFPLR5_2_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
12107 | #define smnBIFPLR5_2_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
12108 | #define smnBIFPLR5_2_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
12109 | #define smnBIFPLR5_2_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
12110 | #define smnBIFPLR5_2_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
12111 | #define smnBIFPLR5_2_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
12112 | #define smnBIFPLR5_2_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
12113 | #define smnBIFPLR5_2_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
12114 | #define smnBIFPLR5_2_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
12115 | #define smnBIFPLR5_2_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
12116 | #define smnBIFPLR5_2_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
12117 | #define smnBIFPLR5_2_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2f000000 |
12118 | #define smnBIFPLR5_2_PCIE_ACS_CAP_DEFAULT 0x00000000 |
12119 | #define smnBIFPLR5_2_PCIE_ACS_CNTL_DEFAULT 0x00000000 |
12120 | #define smnBIFPLR5_2_PCIE_MC_ENH_CAP_LIST_DEFAULT 0x32000000 |
12121 | #define smnBIFPLR5_2_PCIE_MC_CAP_DEFAULT 0x00000000 |
12122 | #define smnBIFPLR5_2_PCIE_MC_CNTL_DEFAULT 0x00000000 |
12123 | #define smnBIFPLR5_2_PCIE_MC_ADDR0_DEFAULT 0x00000000 |
12124 | #define smnBIFPLR5_2_PCIE_MC_ADDR1_DEFAULT 0x00000000 |
12125 | #define smnBIFPLR5_2_PCIE_MC_RCV0_DEFAULT 0x00000000 |
12126 | #define smnBIFPLR5_2_PCIE_MC_RCV1_DEFAULT 0x00000000 |
12127 | #define smnBIFPLR5_2_PCIE_MC_BLOCK_ALL0_DEFAULT 0x00000000 |
12128 | #define smnBIFPLR5_2_PCIE_MC_BLOCK_ALL1_DEFAULT 0x00000000 |
12129 | #define smnBIFPLR5_2_PCIE_MC_BLOCK_UNTRANSLATED_0_DEFAULT 0x00000000 |
12130 | #define smnBIFPLR5_2_PCIE_MC_BLOCK_UNTRANSLATED_1_DEFAULT 0x00000000 |
12131 | #define smnBIFPLR5_2_PCIE_MC_OVERLAY_BAR0_DEFAULT 0x00000000 |
12132 | #define smnBIFPLR5_2_PCIE_MC_OVERLAY_BAR1_DEFAULT 0x00000000 |
12133 | #define smnBIFPLR5_2_PCIE_L1_PM_SUB_CAP_LIST_DEFAULT 0x00000000 |
12134 | #define smnBIFPLR5_2_PCIE_L1_PM_SUB_CAP_DEFAULT 0x00000000 |
12135 | #define smnBIFPLR5_2_PCIE_L1_PM_SUB_CNTL_DEFAULT 0x00000000 |
12136 | #define smnBIFPLR5_2_PCIE_L1_PM_SUB_CNTL2_DEFAULT 0x00000028 |
12137 | #define smnBIFPLR5_2_PCIE_DPC_ENH_CAP_LIST_DEFAULT 0x00000000 |
12138 | #define smnBIFPLR5_2_PCIE_DPC_CAP_LIST_DEFAULT 0x00000000 |
12139 | #define smnBIFPLR5_2_PCIE_DPC_CNTL_DEFAULT 0x00000000 |
12140 | #define smnBIFPLR5_2_PCIE_DPC_STATUS_DEFAULT 0x00000000 |
12141 | #define smnBIFPLR5_2_PCIE_DPC_ERROR_SOURCE_ID_DEFAULT 0x00000000 |
12142 | #define smnBIFPLR5_2_PCIE_RP_PIO_STATUS_DEFAULT 0x00000000 |
12143 | #define smnBIFPLR5_2_PCIE_RP_PIO_MASK_DEFAULT 0x00070707 |
12144 | #define smnBIFPLR5_2_PCIE_RP_PIO_SEVERITY_DEFAULT 0x00000000 |
12145 | #define smnBIFPLR5_2_PCIE_RP_PIO_SYSERROR_DEFAULT 0x00000000 |
12146 | #define smnBIFPLR5_2_PCIE_RP_PIO_EXCEPTION_DEFAULT 0x00000000 |
12147 | #define smnBIFPLR5_2_PCIE_RP_PIO_HDR_LOG0_DEFAULT 0x00000000 |
12148 | #define smnBIFPLR5_2_PCIE_RP_PIO_HDR_LOG1_DEFAULT 0x00000000 |
12149 | #define smnBIFPLR5_2_PCIE_RP_PIO_HDR_LOG2_DEFAULT 0x00000000 |
12150 | #define smnBIFPLR5_2_PCIE_RP_PIO_HDR_LOG3_DEFAULT 0x00000000 |
12151 | #define smnBIFPLR5_2_PCIE_RP_PIO_IMPSPEC_LOG_DEFAULT 0x00000000 |
12152 | #define smnBIFPLR5_2_PCIE_RP_PIO_PREFIX_LOG0_DEFAULT 0x00000000 |
12153 | #define smnBIFPLR5_2_PCIE_RP_PIO_PREFIX_LOG1_DEFAULT 0x00000000 |
12154 | #define smnBIFPLR5_2_PCIE_RP_PIO_PREFIX_LOG2_DEFAULT 0x00000000 |
12155 | #define smnBIFPLR5_2_PCIE_RP_PIO_PREFIX_LOG3_DEFAULT 0x00000000 |
12156 | #define smnBIFPLR5_2_PCIE_ESM_CAP_LIST_DEFAULT 0x00000000 |
12157 | #define 0x00000000 |
12158 | #define 0x00000000 |
12159 | #define smnBIFPLR5_2_PCIE_ESM_STATUS_DEFAULT 0x00000000 |
12160 | #define smnBIFPLR5_2_PCIE_ESM_CTRL_DEFAULT 0x00000000 |
12161 | #define smnBIFPLR5_2_PCIE_ESM_CAP_1_DEFAULT 0x00000000 |
12162 | #define smnBIFPLR5_2_PCIE_ESM_CAP_2_DEFAULT 0x00000000 |
12163 | #define smnBIFPLR5_2_PCIE_ESM_CAP_3_DEFAULT 0x00000000 |
12164 | #define smnBIFPLR5_2_PCIE_ESM_CAP_4_DEFAULT 0x00000000 |
12165 | #define smnBIFPLR5_2_PCIE_ESM_CAP_5_DEFAULT 0x00000000 |
12166 | #define smnBIFPLR5_2_PCIE_ESM_CAP_6_DEFAULT 0x00000000 |
12167 | #define smnBIFPLR5_2_PCIE_ESM_CAP_7_DEFAULT 0x00000000 |
12168 | |
12169 | |
12170 | // addressBlock: nbio_pcie0_bifplr6_cfgdecp |
12171 | #define smnBIFPLR6_2_VENDOR_ID_DEFAULT 0x00000000 |
12172 | #define smnBIFPLR6_2_DEVICE_ID_DEFAULT 0x00000000 |
12173 | #define smnBIFPLR6_2_COMMAND_DEFAULT 0x00000000 |
12174 | #define smnBIFPLR6_2_STATUS_DEFAULT 0x00000000 |
12175 | #define smnBIFPLR6_2_REVISION_ID_DEFAULT 0x00000000 |
12176 | #define smnBIFPLR6_2_PROG_INTERFACE_DEFAULT 0x00000000 |
12177 | #define smnBIFPLR6_2_SUB_CLASS_DEFAULT 0x00000000 |
12178 | #define smnBIFPLR6_2_BASE_CLASS_DEFAULT 0x00000000 |
12179 | #define smnBIFPLR6_2_CACHE_LINE_DEFAULT 0x00000000 |
12180 | #define smnBIFPLR6_2_LATENCY_DEFAULT 0x00000000 |
12181 | #define 0x00000000 |
12182 | #define smnBIFPLR6_2_BIST_DEFAULT 0x00000000 |
12183 | #define smnBIFPLR6_2_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 |
12184 | #define smnBIFPLR6_2_IO_BASE_LIMIT_DEFAULT 0x00000000 |
12185 | #define smnBIFPLR6_2_SECONDARY_STATUS_DEFAULT 0x00000000 |
12186 | #define smnBIFPLR6_2_MEM_BASE_LIMIT_DEFAULT 0x00000000 |
12187 | #define smnBIFPLR6_2_PREF_BASE_LIMIT_DEFAULT 0x00000000 |
12188 | #define smnBIFPLR6_2_PREF_BASE_UPPER_DEFAULT 0x00000000 |
12189 | #define smnBIFPLR6_2_PREF_LIMIT_UPPER_DEFAULT 0x00000000 |
12190 | #define smnBIFPLR6_2_IO_BASE_LIMIT_HI_DEFAULT 0x00000000 |
12191 | #define smnBIFPLR6_2_CAP_PTR_DEFAULT 0x00000000 |
12192 | #define smnBIFPLR6_2_INTERRUPT_LINE_DEFAULT 0x000000ff |
12193 | #define smnBIFPLR6_2_INTERRUPT_PIN_DEFAULT 0x00000000 |
12194 | #define smnBIFPLR6_2_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000 |
12195 | #define smnBIFPLR6_2_EXT_BRIDGE_CNTL_DEFAULT 0x00000000 |
12196 | #define smnBIFPLR6_2_PMI_CAP_LIST_DEFAULT 0x00000000 |
12197 | #define smnBIFPLR6_2_PMI_CAP_DEFAULT 0x00000000 |
12198 | #define smnBIFPLR6_2_PMI_STATUS_CNTL_DEFAULT 0x00000000 |
12199 | #define smnBIFPLR6_2_PCIE_CAP_LIST_DEFAULT 0x0000a000 |
12200 | #define smnBIFPLR6_2_PCIE_CAP_DEFAULT 0x00000002 |
12201 | #define smnBIFPLR6_2_DEVICE_CAP_DEFAULT 0x00000000 |
12202 | #define smnBIFPLR6_2_DEVICE_CNTL_DEFAULT 0x00002810 |
12203 | #define smnBIFPLR6_2_DEVICE_STATUS_DEFAULT 0x00000000 |
12204 | #define smnBIFPLR6_2_LINK_CAP_DEFAULT 0x00011c03 |
12205 | #define smnBIFPLR6_2_LINK_CNTL_DEFAULT 0x00000000 |
12206 | #define smnBIFPLR6_2_LINK_STATUS_DEFAULT 0x00000001 |
12207 | #define smnBIFPLR6_2_SLOT_CAP_DEFAULT 0x00000000 |
12208 | #define smnBIFPLR6_2_SLOT_CNTL_DEFAULT 0x00000000 |
12209 | #define smnBIFPLR6_2_SLOT_STATUS_DEFAULT 0x00000000 |
12210 | #define smnBIFPLR6_2_ROOT_CNTL_DEFAULT 0x00000000 |
12211 | #define smnBIFPLR6_2_ROOT_CAP_DEFAULT 0x00000000 |
12212 | #define smnBIFPLR6_2_ROOT_STATUS_DEFAULT 0x00000000 |
12213 | #define smnBIFPLR6_2_DEVICE_CAP2_DEFAULT 0x00000000 |
12214 | #define smnBIFPLR6_2_DEVICE_CNTL2_DEFAULT 0x00000000 |
12215 | #define smnBIFPLR6_2_DEVICE_STATUS2_DEFAULT 0x00000000 |
12216 | #define smnBIFPLR6_2_LINK_CAP2_DEFAULT 0x0000000e |
12217 | #define smnBIFPLR6_2_LINK_CNTL2_DEFAULT 0x00000003 |
12218 | #define smnBIFPLR6_2_LINK_STATUS2_DEFAULT 0x00000000 |
12219 | #define smnBIFPLR6_2_SLOT_CAP2_DEFAULT 0x00000000 |
12220 | #define smnBIFPLR6_2_SLOT_CNTL2_DEFAULT 0x00000000 |
12221 | #define smnBIFPLR6_2_SLOT_STATUS2_DEFAULT 0x00000000 |
12222 | #define smnBIFPLR6_2_MSI_CAP_LIST_DEFAULT 0x0000c000 |
12223 | #define smnBIFPLR6_2_MSI_MSG_CNTL_DEFAULT 0x00000000 |
12224 | #define smnBIFPLR6_2_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 |
12225 | #define smnBIFPLR6_2_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 |
12226 | #define smnBIFPLR6_2_MSI_MSG_DATA_DEFAULT 0x00000000 |
12227 | #define smnBIFPLR6_2_MSI_MSG_DATA_64_DEFAULT 0x00000000 |
12228 | #define smnBIFPLR6_2_SSID_CAP_LIST_DEFAULT 0x0000c800 |
12229 | #define smnBIFPLR6_2_SSID_CAP_DEFAULT 0x00000000 |
12230 | #define smnBIFPLR6_2_MSI_MAP_CAP_LIST_DEFAULT 0x00000000 |
12231 | #define smnBIFPLR6_2_MSI_MAP_CAP_DEFAULT 0x00000000 |
12232 | #define smnBIFPLR6_2_MSI_MAP_ADDR_LO_DEFAULT 0x00000000 |
12233 | #define smnBIFPLR6_2_MSI_MAP_ADDR_HI_DEFAULT 0x00000000 |
12234 | #define smnBIFPLR6_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 |
12235 | #define smnBIFPLR6_2_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 |
12236 | #define smnBIFPLR6_2_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 |
12237 | #define smnBIFPLR6_2_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 |
12238 | #define smnBIFPLR6_2_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000 |
12239 | #define smnBIFPLR6_2_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000 |
12240 | #define smnBIFPLR6_2_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000 |
12241 | #define smnBIFPLR6_2_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000 |
12242 | #define smnBIFPLR6_2_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000 |
12243 | #define smnBIFPLR6_2_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000 |
12244 | #define smnBIFPLR6_2_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe |
12245 | #define smnBIFPLR6_2_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000002 |
12246 | #define smnBIFPLR6_2_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000 |
12247 | #define smnBIFPLR6_2_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000 |
12248 | #define smnBIFPLR6_2_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000002 |
12249 | #define smnBIFPLR6_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000 |
12250 | #define smnBIFPLR6_2_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000 |
12251 | #define smnBIFPLR6_2_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000 |
12252 | #define smnBIFPLR6_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x27020000 |
12253 | #define smnBIFPLR6_2_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 |
12254 | #define smnBIFPLR6_2_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00400000 |
12255 | #define smnBIFPLR6_2_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 |
12256 | #define smnBIFPLR6_2_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 |
12257 | #define smnBIFPLR6_2_PCIE_CORR_ERR_MASK_DEFAULT 0x00006000 |
12258 | #define smnBIFPLR6_2_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 |
12259 | #define smnBIFPLR6_2_PCIE_HDR_LOG0_DEFAULT 0x00000000 |
12260 | #define smnBIFPLR6_2_PCIE_HDR_LOG1_DEFAULT 0x00000000 |
12261 | #define smnBIFPLR6_2_PCIE_HDR_LOG2_DEFAULT 0x00000000 |
12262 | #define smnBIFPLR6_2_PCIE_HDR_LOG3_DEFAULT 0x00000000 |
12263 | #define smnBIFPLR6_2_PCIE_ROOT_ERR_CMD_DEFAULT 0x00000000 |
12264 | #define smnBIFPLR6_2_PCIE_ROOT_ERR_STATUS_DEFAULT 0x00000000 |
12265 | #define smnBIFPLR6_2_PCIE_ERR_SRC_ID_DEFAULT 0x00000000 |
12266 | #define smnBIFPLR6_2_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 |
12267 | #define smnBIFPLR6_2_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 |
12268 | #define smnBIFPLR6_2_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 |
12269 | #define smnBIFPLR6_2_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 |
12270 | #define smnBIFPLR6_2_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a000000 |
12271 | #define smnBIFPLR6_2_PCIE_LINK_CNTL3_DEFAULT 0x00000000 |
12272 | #define smnBIFPLR6_2_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000 |
12273 | #define smnBIFPLR6_2_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
12274 | #define smnBIFPLR6_2_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
12275 | #define smnBIFPLR6_2_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
12276 | #define smnBIFPLR6_2_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
12277 | #define smnBIFPLR6_2_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
12278 | #define smnBIFPLR6_2_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
12279 | #define smnBIFPLR6_2_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
12280 | #define smnBIFPLR6_2_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
12281 | #define smnBIFPLR6_2_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
12282 | #define smnBIFPLR6_2_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
12283 | #define smnBIFPLR6_2_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
12284 | #define smnBIFPLR6_2_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
12285 | #define smnBIFPLR6_2_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
12286 | #define smnBIFPLR6_2_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
12287 | #define smnBIFPLR6_2_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
12288 | #define smnBIFPLR6_2_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f7f |
12289 | #define smnBIFPLR6_2_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2f000000 |
12290 | #define smnBIFPLR6_2_PCIE_ACS_CAP_DEFAULT 0x00000000 |
12291 | #define smnBIFPLR6_2_PCIE_ACS_CNTL_DEFAULT 0x00000000 |
12292 | #define smnBIFPLR6_2_PCIE_MC_ENH_CAP_LIST_DEFAULT 0x32000000 |
12293 | #define smnBIFPLR6_2_PCIE_MC_CAP_DEFAULT 0x00000000 |
12294 | #define smnBIFPLR6_2_PCIE_MC_CNTL_DEFAULT 0x00000000 |
12295 | #define smnBIFPLR6_2_PCIE_MC_ADDR0_DEFAULT 0x00000000 |
12296 | #define smnBIFPLR6_2_PCIE_MC_ADDR1_DEFAULT 0x00000000 |
12297 | #define smnBIFPLR6_2_PCIE_MC_RCV0_DEFAULT 0x00000000 |
12298 | #define smnBIFPLR6_2_PCIE_MC_RCV1_DEFAULT 0x00000000 |
12299 | #define smnBIFPLR6_2_PCIE_MC_BLOCK_ALL0_DEFAULT 0x00000000 |
12300 | #define smnBIFPLR6_2_PCIE_MC_BLOCK_ALL1_DEFAULT 0x00000000 |
12301 | #define smnBIFPLR6_2_PCIE_MC_BLOCK_UNTRANSLATED_0_DEFAULT 0x00000000 |
12302 | #define smnBIFPLR6_2_PCIE_MC_BLOCK_UNTRANSLATED_1_DEFAULT 0x00000000 |
12303 | #define smnBIFPLR6_2_PCIE_MC_OVERLAY_BAR0_DEFAULT 0x00000000 |
12304 | #define smnBIFPLR6_2_PCIE_MC_OVERLAY_BAR1_DEFAULT 0x00000000 |
12305 | #define smnBIFPLR6_2_PCIE_L1_PM_SUB_CAP_LIST_DEFAULT 0x00000000 |
12306 | #define smnBIFPLR6_2_PCIE_L1_PM_SUB_CAP_DEFAULT 0x00000000 |
12307 | #define smnBIFPLR6_2_PCIE_L1_PM_SUB_CNTL_DEFAULT 0x00000000 |
12308 | #define smnBIFPLR6_2_PCIE_L1_PM_SUB_CNTL2_DEFAULT 0x00000028 |
12309 | #define smnBIFPLR6_2_PCIE_DPC_ENH_CAP_LIST_DEFAULT 0x00000000 |
12310 | #define smnBIFPLR6_2_PCIE_DPC_CAP_LIST_DEFAULT 0x00000000 |
12311 | #define smnBIFPLR6_2_PCIE_DPC_CNTL_DEFAULT 0x00000000 |
12312 | #define smnBIFPLR6_2_PCIE_DPC_STATUS_DEFAULT 0x00000000 |
12313 | #define smnBIFPLR6_2_PCIE_DPC_ERROR_SOURCE_ID_DEFAULT 0x00000000 |
12314 | #define smnBIFPLR6_2_PCIE_RP_PIO_STATUS_DEFAULT 0x00000000 |
12315 | #define smnBIFPLR6_2_PCIE_RP_PIO_MASK_DEFAULT 0x00070707 |
12316 | #define smnBIFPLR6_2_PCIE_RP_PIO_SEVERITY_DEFAULT 0x00000000 |
12317 | #define smnBIFPLR6_2_PCIE_RP_PIO_SYSERROR_DEFAULT 0x00000000 |
12318 | #define smnBIFPLR6_2_PCIE_RP_PIO_EXCEPTION_DEFAULT 0x00000000 |
12319 | #define smnBIFPLR6_2_PCIE_RP_PIO_HDR_LOG0_DEFAULT 0x00000000 |
12320 | #define smnBIFPLR6_2_PCIE_RP_PIO_HDR_LOG1_DEFAULT 0x00000000 |
12321 | #define smnBIFPLR6_2_PCIE_RP_PIO_HDR_LOG2_DEFAULT 0x00000000 |
12322 | #define smnBIFPLR6_2_PCIE_RP_PIO_HDR_LOG3_DEFAULT 0x00000000 |
12323 | #define smnBIFPLR6_2_PCIE_RP_PIO_IMPSPEC_LOG_DEFAULT 0x00000000 |
12324 | #define smnBIFPLR6_2_PCIE_RP_PIO_PREFIX_LOG0_DEFAULT 0x00000000 |
12325 | #define smnBIFPLR6_2_PCIE_RP_PIO_PREFIX_LOG1_DEFAULT 0x00000000 |
12326 | #define smnBIFPLR6_2_PCIE_RP_PIO_PREFIX_LOG2_DEFAULT 0x00000000 |
12327 | #define smnBIFPLR6_2_PCIE_RP_PIO_PREFIX_LOG3_DEFAULT 0x00000000 |
12328 | #define smnBIFPLR6_2_PCIE_ESM_CAP_LIST_DEFAULT 0x00000000 |
12329 | #define 0x00000000 |
12330 | #define 0x00000000 |
12331 | #define smnBIFPLR6_2_PCIE_ESM_STATUS_DEFAULT 0x00000000 |
12332 | #define smnBIFPLR6_2_PCIE_ESM_CTRL_DEFAULT 0x00000000 |
12333 | #define smnBIFPLR6_2_PCIE_ESM_CAP_1_DEFAULT 0x00000000 |
12334 | #define smnBIFPLR6_2_PCIE_ESM_CAP_2_DEFAULT 0x00000000 |
12335 | #define smnBIFPLR6_2_PCIE_ESM_CAP_3_DEFAULT 0x00000000 |
12336 | #define smnBIFPLR6_2_PCIE_ESM_CAP_4_DEFAULT 0x00000000 |
12337 | #define smnBIFPLR6_2_PCIE_ESM_CAP_5_DEFAULT 0x00000000 |
12338 | #define smnBIFPLR6_2_PCIE_ESM_CAP_6_DEFAULT 0x00000000 |
12339 | #define smnBIFPLR6_2_PCIE_ESM_CAP_7_DEFAULT 0x00000000 |
12340 | |
12341 | |
12342 | // addressBlock: nbio_iohub_nb_pciedummy1_pciedummy_cfgdec |
12343 | #define smnNB_PCIEDUMMY1_2_DEVICE_VENDOR_ID_DEFAULT 0x00000000 |
12344 | #define smnNB_PCIEDUMMY1_2_STATUS_COMMAND_DEFAULT 0x00000000 |
12345 | #define smnNB_PCIEDUMMY1_2_CLASS_CODE_REVID_DEFAULT 0x00000000 |
12346 | #define 0x00800000 |
12347 | #define 0x00000080 |
12348 | |
12349 | |
12350 | // addressBlock: nbio_nbif0_bif_cfg_dev0_rc_bifcfgdecp |
12351 | #define smnBIF_CFG_DEV0_RC2_VENDOR_ID_DEFAULT 0x00000000 |
12352 | #define smnBIF_CFG_DEV0_RC2_DEVICE_ID_DEFAULT 0x00000000 |
12353 | #define smnBIF_CFG_DEV0_RC2_COMMAND_DEFAULT 0x00000000 |
12354 | #define smnBIF_CFG_DEV0_RC2_STATUS_DEFAULT 0x00000000 |
12355 | #define smnBIF_CFG_DEV0_RC2_REVISION_ID_DEFAULT 0x00000000 |
12356 | #define smnBIF_CFG_DEV0_RC2_PROG_INTERFACE_DEFAULT 0x00000000 |
12357 | #define smnBIF_CFG_DEV0_RC2_SUB_CLASS_DEFAULT 0x00000000 |
12358 | #define smnBIF_CFG_DEV0_RC2_BASE_CLASS_DEFAULT 0x00000000 |
12359 | #define smnBIF_CFG_DEV0_RC2_CACHE_LINE_DEFAULT 0x00000000 |
12360 | #define smnBIF_CFG_DEV0_RC2_LATENCY_DEFAULT 0x00000000 |
12361 | #define 0x00000000 |
12362 | #define smnBIF_CFG_DEV0_RC2_BIST_DEFAULT 0x00000000 |
12363 | #define smnBIF_CFG_DEV0_RC2_BASE_ADDR_1_DEFAULT 0x00000000 |
12364 | #define smnBIF_CFG_DEV0_RC2_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 |
12365 | #define smnBIF_CFG_DEV0_RC2_IO_BASE_LIMIT_DEFAULT 0x00000000 |
12366 | #define smnBIF_CFG_DEV0_RC2_SECONDARY_STATUS_DEFAULT 0x00000000 |
12367 | #define smnBIF_CFG_DEV0_RC2_MEM_BASE_LIMIT_DEFAULT 0x00000000 |
12368 | #define smnBIF_CFG_DEV0_RC2_PREF_BASE_LIMIT_DEFAULT 0x00000000 |
12369 | #define smnBIF_CFG_DEV0_RC2_PREF_BASE_UPPER_DEFAULT 0x00000000 |
12370 | #define smnBIF_CFG_DEV0_RC2_PREF_LIMIT_UPPER_DEFAULT 0x00000000 |
12371 | #define smnBIF_CFG_DEV0_RC2_IO_BASE_LIMIT_HI_DEFAULT 0x00000000 |
12372 | #define smnBIF_CFG_DEV0_RC2_CAP_PTR_DEFAULT 0x00000000 |
12373 | #define smnBIF_CFG_DEV0_RC2_INTERRUPT_LINE_DEFAULT 0x000000ff |
12374 | #define smnBIF_CFG_DEV0_RC2_INTERRUPT_PIN_DEFAULT 0x00000001 |
12375 | #define smnBIF_CFG_DEV0_RC2_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000 |
12376 | #define smnBIF_CFG_DEV0_RC2_EXT_BRIDGE_CNTL_DEFAULT 0x00000000 |
12377 | #define smnBIF_CFG_DEV0_RC2_PMI_CAP_LIST_DEFAULT 0x00000000 |
12378 | #define smnBIF_CFG_DEV0_RC2_PMI_CAP_DEFAULT 0x00000000 |
12379 | #define smnBIF_CFG_DEV0_RC2_PMI_STATUS_CNTL_DEFAULT 0x00000000 |
12380 | #define smnBIF_CFG_DEV0_RC2_PCIE_CAP_LIST_DEFAULT 0x0000a000 |
12381 | #define smnBIF_CFG_DEV0_RC2_PCIE_CAP_DEFAULT 0x00000042 |
12382 | #define smnBIF_CFG_DEV0_RC2_DEVICE_CAP_DEFAULT 0x00000000 |
12383 | #define smnBIF_CFG_DEV0_RC2_DEVICE_CNTL_DEFAULT 0x00002810 |
12384 | #define smnBIF_CFG_DEV0_RC2_DEVICE_STATUS_DEFAULT 0x00000000 |
12385 | #define smnBIF_CFG_DEV0_RC2_LINK_CAP_DEFAULT 0x00011c03 |
12386 | #define smnBIF_CFG_DEV0_RC2_LINK_CNTL_DEFAULT 0x00000000 |
12387 | #define smnBIF_CFG_DEV0_RC2_LINK_STATUS_DEFAULT 0x00002001 |
12388 | #define smnBIF_CFG_DEV0_RC2_SLOT_CAP_DEFAULT 0x00000000 |
12389 | #define smnBIF_CFG_DEV0_RC2_SLOT_CNTL_DEFAULT 0x00000000 |
12390 | #define smnBIF_CFG_DEV0_RC2_SLOT_STATUS_DEFAULT 0x00000000 |
12391 | #define smnBIF_CFG_DEV0_RC2_ROOT_CNTL_DEFAULT 0x00000000 |
12392 | #define smnBIF_CFG_DEV0_RC2_ROOT_CAP_DEFAULT 0x00000000 |
12393 | #define smnBIF_CFG_DEV0_RC2_ROOT_STATUS_DEFAULT 0x00000000 |
12394 | #define smnBIF_CFG_DEV0_RC2_DEVICE_CAP2_DEFAULT 0x00000000 |
12395 | #define smnBIF_CFG_DEV0_RC2_DEVICE_CNTL2_DEFAULT 0x00000000 |
12396 | #define smnBIF_CFG_DEV0_RC2_DEVICE_STATUS2_DEFAULT 0x00000000 |
12397 | #define smnBIF_CFG_DEV0_RC2_LINK_CAP2_DEFAULT 0x0000000e |
12398 | #define smnBIF_CFG_DEV0_RC2_LINK_CNTL2_DEFAULT 0x00000003 |
12399 | #define smnBIF_CFG_DEV0_RC2_LINK_STATUS2_DEFAULT 0x00000000 |
12400 | #define smnBIF_CFG_DEV0_RC2_SLOT_CAP2_DEFAULT 0x00000000 |
12401 | #define smnBIF_CFG_DEV0_RC2_SLOT_CNTL2_DEFAULT 0x00000000 |
12402 | #define smnBIF_CFG_DEV0_RC2_SLOT_STATUS2_DEFAULT 0x00000000 |
12403 | #define smnBIF_CFG_DEV0_RC2_MSI_CAP_LIST_DEFAULT 0x0000c000 |
12404 | #define smnBIF_CFG_DEV0_RC2_MSI_MSG_CNTL_DEFAULT 0x00000080 |
12405 | #define smnBIF_CFG_DEV0_RC2_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 |
12406 | #define smnBIF_CFG_DEV0_RC2_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 |
12407 | #define smnBIF_CFG_DEV0_RC2_MSI_MSG_DATA_DEFAULT 0x00000000 |
12408 | #define smnBIF_CFG_DEV0_RC2_MSI_MSG_DATA_64_DEFAULT 0x00000000 |
12409 | #define smnBIF_CFG_DEV0_RC2_SSID_CAP_LIST_DEFAULT 0x00000000 |
12410 | #define smnBIF_CFG_DEV0_RC2_SSID_CAP_DEFAULT 0x00000000 |
12411 | #define smnBIF_CFG_DEV0_RC2_MSI_MAP_CAP_LIST_DEFAULT 0x00000000 |
12412 | #define smnBIF_CFG_DEV0_RC2_MSI_MAP_CAP_DEFAULT 0x00000000 |
12413 | #define smnBIF_CFG_DEV0_RC2_MSI_MAP_ADDR_LO_DEFAULT 0x00000000 |
12414 | #define smnBIF_CFG_DEV0_RC2_MSI_MAP_ADDR_HI_DEFAULT 0x00000000 |
12415 | #define smnBIF_CFG_DEV0_RC2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 |
12416 | #define smnBIF_CFG_DEV0_RC2_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 |
12417 | #define smnBIF_CFG_DEV0_RC2_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 |
12418 | #define smnBIF_CFG_DEV0_RC2_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 |
12419 | #define smnBIF_CFG_DEV0_RC2_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000 |
12420 | #define smnBIF_CFG_DEV0_RC2_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000 |
12421 | #define smnBIF_CFG_DEV0_RC2_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000 |
12422 | #define smnBIF_CFG_DEV0_RC2_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000 |
12423 | #define smnBIF_CFG_DEV0_RC2_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000 |
12424 | #define smnBIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000 |
12425 | #define smnBIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe |
12426 | #define smnBIF_CFG_DEV0_RC2_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000000 |
12427 | #define smnBIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000 |
12428 | #define smnBIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000 |
12429 | #define smnBIF_CFG_DEV0_RC2_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000000 |
12430 | #define smnBIF_CFG_DEV0_RC2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000 |
12431 | #define smnBIF_CFG_DEV0_RC2_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000 |
12432 | #define smnBIF_CFG_DEV0_RC2_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000 |
12433 | #define smnBIF_CFG_DEV0_RC2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 |
12434 | #define smnBIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 |
12435 | #define smnBIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 |
12436 | #define smnBIF_CFG_DEV0_RC2_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 |
12437 | #define smnBIF_CFG_DEV0_RC2_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 |
12438 | #define smnBIF_CFG_DEV0_RC2_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000 |
12439 | #define smnBIF_CFG_DEV0_RC2_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 |
12440 | #define smnBIF_CFG_DEV0_RC2_PCIE_HDR_LOG0_DEFAULT 0x00000000 |
12441 | #define smnBIF_CFG_DEV0_RC2_PCIE_HDR_LOG1_DEFAULT 0x00000000 |
12442 | #define smnBIF_CFG_DEV0_RC2_PCIE_HDR_LOG2_DEFAULT 0x00000000 |
12443 | #define smnBIF_CFG_DEV0_RC2_PCIE_HDR_LOG3_DEFAULT 0x00000000 |
12444 | #define smnBIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_CMD_DEFAULT 0x00000000 |
12445 | #define smnBIF_CFG_DEV0_RC2_PCIE_ROOT_ERR_STATUS_DEFAULT 0x00000000 |
12446 | #define smnBIF_CFG_DEV0_RC2_PCIE_ERR_SRC_ID_DEFAULT 0x00000000 |
12447 | #define smnBIF_CFG_DEV0_RC2_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 |
12448 | #define smnBIF_CFG_DEV0_RC2_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 |
12449 | #define smnBIF_CFG_DEV0_RC2_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 |
12450 | #define smnBIF_CFG_DEV0_RC2_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 |
12451 | #define smnBIF_CFG_DEV0_RC2_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a000000 |
12452 | #define smnBIF_CFG_DEV0_RC2_PCIE_LINK_CNTL3_DEFAULT 0x00000000 |
12453 | #define smnBIF_CFG_DEV0_RC2_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000 |
12454 | #define smnBIF_CFG_DEV0_RC2_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
12455 | #define smnBIF_CFG_DEV0_RC2_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
12456 | #define smnBIF_CFG_DEV0_RC2_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
12457 | #define smnBIF_CFG_DEV0_RC2_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
12458 | #define smnBIF_CFG_DEV0_RC2_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
12459 | #define smnBIF_CFG_DEV0_RC2_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
12460 | #define smnBIF_CFG_DEV0_RC2_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
12461 | #define smnBIF_CFG_DEV0_RC2_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
12462 | #define smnBIF_CFG_DEV0_RC2_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
12463 | #define smnBIF_CFG_DEV0_RC2_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
12464 | #define smnBIF_CFG_DEV0_RC2_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
12465 | #define smnBIF_CFG_DEV0_RC2_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
12466 | #define smnBIF_CFG_DEV0_RC2_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
12467 | #define smnBIF_CFG_DEV0_RC2_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
12468 | #define smnBIF_CFG_DEV0_RC2_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
12469 | #define smnBIF_CFG_DEV0_RC2_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
12470 | #define smnBIF_CFG_DEV0_RC2_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2f000000 |
12471 | #define smnBIF_CFG_DEV0_RC2_PCIE_ACS_CAP_DEFAULT 0x00000000 |
12472 | #define smnBIF_CFG_DEV0_RC2_PCIE_ACS_CNTL_DEFAULT 0x00000000 |
12473 | |
12474 | |
12475 | // addressBlock: nbio_nbif0_bif_cfg_dev1_rc_bifcfgdecp |
12476 | #define smnBIF_CFG_DEV1_RC2_VENDOR_ID_DEFAULT 0x00000000 |
12477 | #define smnBIF_CFG_DEV1_RC2_DEVICE_ID_DEFAULT 0x00000000 |
12478 | #define smnBIF_CFG_DEV1_RC2_COMMAND_DEFAULT 0x00000000 |
12479 | #define smnBIF_CFG_DEV1_RC2_STATUS_DEFAULT 0x00000000 |
12480 | #define smnBIF_CFG_DEV1_RC2_REVISION_ID_DEFAULT 0x00000000 |
12481 | #define smnBIF_CFG_DEV1_RC2_PROG_INTERFACE_DEFAULT 0x00000000 |
12482 | #define smnBIF_CFG_DEV1_RC2_SUB_CLASS_DEFAULT 0x00000000 |
12483 | #define smnBIF_CFG_DEV1_RC2_BASE_CLASS_DEFAULT 0x00000000 |
12484 | #define smnBIF_CFG_DEV1_RC2_CACHE_LINE_DEFAULT 0x00000000 |
12485 | #define smnBIF_CFG_DEV1_RC2_LATENCY_DEFAULT 0x00000000 |
12486 | #define 0x00000000 |
12487 | #define smnBIF_CFG_DEV1_RC2_BIST_DEFAULT 0x00000000 |
12488 | #define smnBIF_CFG_DEV1_RC2_BASE_ADDR_1_DEFAULT 0x00000000 |
12489 | #define smnBIF_CFG_DEV1_RC2_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 |
12490 | #define smnBIF_CFG_DEV1_RC2_IO_BASE_LIMIT_DEFAULT 0x00000000 |
12491 | #define smnBIF_CFG_DEV1_RC2_SECONDARY_STATUS_DEFAULT 0x00000000 |
12492 | #define smnBIF_CFG_DEV1_RC2_MEM_BASE_LIMIT_DEFAULT 0x00000000 |
12493 | #define smnBIF_CFG_DEV1_RC2_PREF_BASE_LIMIT_DEFAULT 0x00000000 |
12494 | #define smnBIF_CFG_DEV1_RC2_PREF_BASE_UPPER_DEFAULT 0x00000000 |
12495 | #define smnBIF_CFG_DEV1_RC2_PREF_LIMIT_UPPER_DEFAULT 0x00000000 |
12496 | #define smnBIF_CFG_DEV1_RC2_IO_BASE_LIMIT_HI_DEFAULT 0x00000000 |
12497 | #define smnBIF_CFG_DEV1_RC2_CAP_PTR_DEFAULT 0x00000000 |
12498 | #define smnBIF_CFG_DEV1_RC2_INTERRUPT_LINE_DEFAULT 0x000000ff |
12499 | #define smnBIF_CFG_DEV1_RC2_INTERRUPT_PIN_DEFAULT 0x00000001 |
12500 | #define smnBIF_CFG_DEV1_RC2_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000 |
12501 | #define smnBIF_CFG_DEV1_RC2_EXT_BRIDGE_CNTL_DEFAULT 0x00000000 |
12502 | #define smnBIF_CFG_DEV1_RC2_PMI_CAP_LIST_DEFAULT 0x00000000 |
12503 | #define smnBIF_CFG_DEV1_RC2_PMI_CAP_DEFAULT 0x00000000 |
12504 | #define smnBIF_CFG_DEV1_RC2_PMI_STATUS_CNTL_DEFAULT 0x00000000 |
12505 | #define smnBIF_CFG_DEV1_RC2_PCIE_CAP_LIST_DEFAULT 0x0000a000 |
12506 | #define smnBIF_CFG_DEV1_RC2_PCIE_CAP_DEFAULT 0x00000042 |
12507 | #define smnBIF_CFG_DEV1_RC2_DEVICE_CAP_DEFAULT 0x00000000 |
12508 | #define smnBIF_CFG_DEV1_RC2_DEVICE_CNTL_DEFAULT 0x00002810 |
12509 | #define smnBIF_CFG_DEV1_RC2_DEVICE_STATUS_DEFAULT 0x00000000 |
12510 | #define smnBIF_CFG_DEV1_RC2_LINK_CAP_DEFAULT 0x00011c03 |
12511 | #define smnBIF_CFG_DEV1_RC2_LINK_CNTL_DEFAULT 0x00000000 |
12512 | #define smnBIF_CFG_DEV1_RC2_LINK_STATUS_DEFAULT 0x00002001 |
12513 | #define smnBIF_CFG_DEV1_RC2_SLOT_CAP_DEFAULT 0x00000000 |
12514 | #define smnBIF_CFG_DEV1_RC2_SLOT_CNTL_DEFAULT 0x00000000 |
12515 | #define smnBIF_CFG_DEV1_RC2_SLOT_STATUS_DEFAULT 0x00000000 |
12516 | #define smnBIF_CFG_DEV1_RC2_ROOT_CNTL_DEFAULT 0x00000000 |
12517 | #define smnBIF_CFG_DEV1_RC2_ROOT_CAP_DEFAULT 0x00000000 |
12518 | #define smnBIF_CFG_DEV1_RC2_ROOT_STATUS_DEFAULT 0x00000000 |
12519 | #define smnBIF_CFG_DEV1_RC2_DEVICE_CAP2_DEFAULT 0x00000000 |
12520 | #define smnBIF_CFG_DEV1_RC2_DEVICE_CNTL2_DEFAULT 0x00000000 |
12521 | #define smnBIF_CFG_DEV1_RC2_DEVICE_STATUS2_DEFAULT 0x00000000 |
12522 | #define smnBIF_CFG_DEV1_RC2_LINK_CAP2_DEFAULT 0x0000000e |
12523 | #define smnBIF_CFG_DEV1_RC2_LINK_CNTL2_DEFAULT 0x00000003 |
12524 | #define smnBIF_CFG_DEV1_RC2_LINK_STATUS2_DEFAULT 0x00000000 |
12525 | #define smnBIF_CFG_DEV1_RC2_SLOT_CAP2_DEFAULT 0x00000000 |
12526 | #define smnBIF_CFG_DEV1_RC2_SLOT_CNTL2_DEFAULT 0x00000000 |
12527 | #define smnBIF_CFG_DEV1_RC2_SLOT_STATUS2_DEFAULT 0x00000000 |
12528 | #define smnBIF_CFG_DEV1_RC2_MSI_CAP_LIST_DEFAULT 0x0000c000 |
12529 | #define smnBIF_CFG_DEV1_RC2_MSI_MSG_CNTL_DEFAULT 0x00000080 |
12530 | #define smnBIF_CFG_DEV1_RC2_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 |
12531 | #define smnBIF_CFG_DEV1_RC2_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 |
12532 | #define smnBIF_CFG_DEV1_RC2_MSI_MSG_DATA_DEFAULT 0x00000000 |
12533 | #define smnBIF_CFG_DEV1_RC2_MSI_MSG_DATA_64_DEFAULT 0x00000000 |
12534 | #define smnBIF_CFG_DEV1_RC2_SSID_CAP_LIST_DEFAULT 0x00000000 |
12535 | #define smnBIF_CFG_DEV1_RC2_SSID_CAP_DEFAULT 0x00000000 |
12536 | #define smnBIF_CFG_DEV1_RC2_MSI_MAP_CAP_LIST_DEFAULT 0x00000000 |
12537 | #define smnBIF_CFG_DEV1_RC2_MSI_MAP_CAP_DEFAULT 0x00000000 |
12538 | #define smnBIF_CFG_DEV1_RC2_MSI_MAP_ADDR_LO_DEFAULT 0x00000000 |
12539 | #define smnBIF_CFG_DEV1_RC2_MSI_MAP_ADDR_HI_DEFAULT 0x00000000 |
12540 | #define smnBIF_CFG_DEV1_RC2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 |
12541 | #define smnBIF_CFG_DEV1_RC2_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 |
12542 | #define smnBIF_CFG_DEV1_RC2_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 |
12543 | #define smnBIF_CFG_DEV1_RC2_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 |
12544 | #define smnBIF_CFG_DEV1_RC2_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000 |
12545 | #define smnBIF_CFG_DEV1_RC2_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000 |
12546 | #define smnBIF_CFG_DEV1_RC2_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000 |
12547 | #define smnBIF_CFG_DEV1_RC2_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000 |
12548 | #define smnBIF_CFG_DEV1_RC2_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000 |
12549 | #define smnBIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000 |
12550 | #define smnBIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe |
12551 | #define smnBIF_CFG_DEV1_RC2_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000000 |
12552 | #define smnBIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000 |
12553 | #define smnBIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000 |
12554 | #define smnBIF_CFG_DEV1_RC2_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000000 |
12555 | #define smnBIF_CFG_DEV1_RC2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000 |
12556 | #define smnBIF_CFG_DEV1_RC2_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000 |
12557 | #define smnBIF_CFG_DEV1_RC2_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000 |
12558 | #define smnBIF_CFG_DEV1_RC2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 |
12559 | #define smnBIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 |
12560 | #define smnBIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 |
12561 | #define smnBIF_CFG_DEV1_RC2_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 |
12562 | #define smnBIF_CFG_DEV1_RC2_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 |
12563 | #define smnBIF_CFG_DEV1_RC2_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000 |
12564 | #define smnBIF_CFG_DEV1_RC2_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 |
12565 | #define smnBIF_CFG_DEV1_RC2_PCIE_HDR_LOG0_DEFAULT 0x00000000 |
12566 | #define smnBIF_CFG_DEV1_RC2_PCIE_HDR_LOG1_DEFAULT 0x00000000 |
12567 | #define smnBIF_CFG_DEV1_RC2_PCIE_HDR_LOG2_DEFAULT 0x00000000 |
12568 | #define smnBIF_CFG_DEV1_RC2_PCIE_HDR_LOG3_DEFAULT 0x00000000 |
12569 | #define smnBIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_CMD_DEFAULT 0x00000000 |
12570 | #define smnBIF_CFG_DEV1_RC2_PCIE_ROOT_ERR_STATUS_DEFAULT 0x00000000 |
12571 | #define smnBIF_CFG_DEV1_RC2_PCIE_ERR_SRC_ID_DEFAULT 0x00000000 |
12572 | #define smnBIF_CFG_DEV1_RC2_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 |
12573 | #define smnBIF_CFG_DEV1_RC2_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 |
12574 | #define smnBIF_CFG_DEV1_RC2_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 |
12575 | #define smnBIF_CFG_DEV1_RC2_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 |
12576 | #define smnBIF_CFG_DEV1_RC2_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a000000 |
12577 | #define smnBIF_CFG_DEV1_RC2_PCIE_LINK_CNTL3_DEFAULT 0x00000000 |
12578 | #define smnBIF_CFG_DEV1_RC2_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000 |
12579 | #define smnBIF_CFG_DEV1_RC2_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
12580 | #define smnBIF_CFG_DEV1_RC2_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
12581 | #define smnBIF_CFG_DEV1_RC2_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
12582 | #define smnBIF_CFG_DEV1_RC2_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
12583 | #define smnBIF_CFG_DEV1_RC2_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
12584 | #define smnBIF_CFG_DEV1_RC2_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
12585 | #define smnBIF_CFG_DEV1_RC2_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
12586 | #define smnBIF_CFG_DEV1_RC2_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
12587 | #define smnBIF_CFG_DEV1_RC2_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
12588 | #define smnBIF_CFG_DEV1_RC2_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
12589 | #define smnBIF_CFG_DEV1_RC2_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
12590 | #define smnBIF_CFG_DEV1_RC2_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
12591 | #define smnBIF_CFG_DEV1_RC2_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
12592 | #define smnBIF_CFG_DEV1_RC2_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
12593 | #define smnBIF_CFG_DEV1_RC2_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
12594 | #define smnBIF_CFG_DEV1_RC2_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f0f |
12595 | #define smnBIF_CFG_DEV1_RC2_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2f000000 |
12596 | #define smnBIF_CFG_DEV1_RC2_PCIE_ACS_CAP_DEFAULT 0x00000000 |
12597 | #define smnBIF_CFG_DEV1_RC2_PCIE_ACS_CNTL_DEFAULT 0x00000000 |
12598 | |
12599 | |
12600 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_bifcfgdecp |
12601 | #define smnBIF_CFG_DEV0_EPF0_3_VENDOR_ID_DEFAULT 0x00000000 |
12602 | #define smnBIF_CFG_DEV0_EPF0_3_DEVICE_ID_DEFAULT 0x00000000 |
12603 | #define smnBIF_CFG_DEV0_EPF0_3_COMMAND_DEFAULT 0x00000000 |
12604 | #define smnBIF_CFG_DEV0_EPF0_3_STATUS_DEFAULT 0x00000000 |
12605 | #define smnBIF_CFG_DEV0_EPF0_3_REVISION_ID_DEFAULT 0x00000000 |
12606 | #define smnBIF_CFG_DEV0_EPF0_3_PROG_INTERFACE_DEFAULT 0x00000000 |
12607 | #define smnBIF_CFG_DEV0_EPF0_3_SUB_CLASS_DEFAULT 0x00000000 |
12608 | #define smnBIF_CFG_DEV0_EPF0_3_BASE_CLASS_DEFAULT 0x00000000 |
12609 | #define smnBIF_CFG_DEV0_EPF0_3_CACHE_LINE_DEFAULT 0x00000000 |
12610 | #define smnBIF_CFG_DEV0_EPF0_3_LATENCY_DEFAULT 0x00000000 |
12611 | #define 0x00000000 |
12612 | #define smnBIF_CFG_DEV0_EPF0_3_BIST_DEFAULT 0x00000000 |
12613 | #define smnBIF_CFG_DEV0_EPF0_3_BASE_ADDR_1_DEFAULT 0x00000000 |
12614 | #define smnBIF_CFG_DEV0_EPF0_3_BASE_ADDR_2_DEFAULT 0x00000000 |
12615 | #define smnBIF_CFG_DEV0_EPF0_3_BASE_ADDR_3_DEFAULT 0x00000000 |
12616 | #define smnBIF_CFG_DEV0_EPF0_3_BASE_ADDR_4_DEFAULT 0x00000000 |
12617 | #define smnBIF_CFG_DEV0_EPF0_3_BASE_ADDR_5_DEFAULT 0x00000000 |
12618 | #define smnBIF_CFG_DEV0_EPF0_3_BASE_ADDR_6_DEFAULT 0x00000000 |
12619 | #define smnBIF_CFG_DEV0_EPF0_3_ADAPTER_ID_DEFAULT 0x00000000 |
12620 | #define smnBIF_CFG_DEV0_EPF0_3_ROM_BASE_ADDR_DEFAULT 0x00000000 |
12621 | #define smnBIF_CFG_DEV0_EPF0_3_CAP_PTR_DEFAULT 0x00000000 |
12622 | #define smnBIF_CFG_DEV0_EPF0_3_INTERRUPT_LINE_DEFAULT 0x000000ff |
12623 | #define smnBIF_CFG_DEV0_EPF0_3_INTERRUPT_PIN_DEFAULT 0x00000000 |
12624 | #define smnBIF_CFG_DEV0_EPF0_3_MIN_GRANT_DEFAULT 0x00000000 |
12625 | #define smnBIF_CFG_DEV0_EPF0_3_MAX_LATENCY_DEFAULT 0x00000000 |
12626 | #define smnBIF_CFG_DEV0_EPF0_3_VENDOR_CAP_LIST_DEFAULT 0x00000000 |
12627 | #define smnBIF_CFG_DEV0_EPF0_3_ADAPTER_ID_W_DEFAULT 0x00000000 |
12628 | #define smnBIF_CFG_DEV0_EPF0_3_PMI_CAP_LIST_DEFAULT 0x00000000 |
12629 | #define smnBIF_CFG_DEV0_EPF0_3_PMI_CAP_DEFAULT 0x00000000 |
12630 | #define smnBIF_CFG_DEV0_EPF0_3_PMI_STATUS_CNTL_DEFAULT 0x00000000 |
12631 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_CAP_LIST_DEFAULT 0x0000a000 |
12632 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_CAP_DEFAULT 0x00000002 |
12633 | #define smnBIF_CFG_DEV0_EPF0_3_DEVICE_CAP_DEFAULT 0x10000000 |
12634 | #define smnBIF_CFG_DEV0_EPF0_3_DEVICE_CNTL_DEFAULT 0x00002810 |
12635 | #define smnBIF_CFG_DEV0_EPF0_3_DEVICE_STATUS_DEFAULT 0x00000000 |
12636 | #define smnBIF_CFG_DEV0_EPF0_3_LINK_CAP_DEFAULT 0x00011c03 |
12637 | #define smnBIF_CFG_DEV0_EPF0_3_LINK_CNTL_DEFAULT 0x00000000 |
12638 | #define smnBIF_CFG_DEV0_EPF0_3_LINK_STATUS_DEFAULT 0x00000001 |
12639 | #define smnBIF_CFG_DEV0_EPF0_3_DEVICE_CAP2_DEFAULT 0x00000000 |
12640 | #define smnBIF_CFG_DEV0_EPF0_3_DEVICE_CNTL2_DEFAULT 0x00000000 |
12641 | #define smnBIF_CFG_DEV0_EPF0_3_DEVICE_STATUS2_DEFAULT 0x00000000 |
12642 | #define smnBIF_CFG_DEV0_EPF0_3_LINK_CAP2_DEFAULT 0x0000000e |
12643 | #define smnBIF_CFG_DEV0_EPF0_3_LINK_CNTL2_DEFAULT 0x00000003 |
12644 | #define smnBIF_CFG_DEV0_EPF0_3_LINK_STATUS2_DEFAULT 0x00000000 |
12645 | #define smnBIF_CFG_DEV0_EPF0_3_SLOT_CAP2_DEFAULT 0x00000000 |
12646 | #define smnBIF_CFG_DEV0_EPF0_3_SLOT_CNTL2_DEFAULT 0x00000000 |
12647 | #define smnBIF_CFG_DEV0_EPF0_3_SLOT_STATUS2_DEFAULT 0x00000000 |
12648 | #define smnBIF_CFG_DEV0_EPF0_3_MSI_CAP_LIST_DEFAULT 0x0000c000 |
12649 | #define smnBIF_CFG_DEV0_EPF0_3_MSI_MSG_CNTL_DEFAULT 0x00000080 |
12650 | #define smnBIF_CFG_DEV0_EPF0_3_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 |
12651 | #define smnBIF_CFG_DEV0_EPF0_3_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 |
12652 | #define smnBIF_CFG_DEV0_EPF0_3_MSI_MSG_DATA_DEFAULT 0x00000000 |
12653 | #define smnBIF_CFG_DEV0_EPF0_3_MSI_MASK_DEFAULT 0x00000000 |
12654 | #define smnBIF_CFG_DEV0_EPF0_3_MSI_MSG_DATA_64_DEFAULT 0x00000000 |
12655 | #define smnBIF_CFG_DEV0_EPF0_3_MSI_MASK_64_DEFAULT 0x00000000 |
12656 | #define smnBIF_CFG_DEV0_EPF0_3_MSI_PENDING_DEFAULT 0x00000000 |
12657 | #define smnBIF_CFG_DEV0_EPF0_3_MSI_PENDING_64_DEFAULT 0x00000000 |
12658 | #define smnBIF_CFG_DEV0_EPF0_3_MSIX_CAP_LIST_DEFAULT 0x00000000 |
12659 | #define smnBIF_CFG_DEV0_EPF0_3_MSIX_MSG_CNTL_DEFAULT 0x00000000 |
12660 | #define smnBIF_CFG_DEV0_EPF0_3_MSIX_TABLE_DEFAULT 0x00000000 |
12661 | #define smnBIF_CFG_DEV0_EPF0_3_MSIX_PBA_DEFAULT 0x00000000 |
12662 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 |
12663 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 |
12664 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 |
12665 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 |
12666 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000 |
12667 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000 |
12668 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000 |
12669 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000 |
12670 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000 |
12671 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000 |
12672 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe |
12673 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000000 |
12674 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000 |
12675 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000 |
12676 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000000 |
12677 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000 |
12678 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000 |
12679 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000 |
12680 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 |
12681 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 |
12682 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 |
12683 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 |
12684 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 |
12685 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000 |
12686 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 |
12687 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_HDR_LOG0_DEFAULT 0x00000000 |
12688 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_HDR_LOG1_DEFAULT 0x00000000 |
12689 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_HDR_LOG2_DEFAULT 0x00000000 |
12690 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_HDR_LOG3_DEFAULT 0x00000000 |
12691 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 |
12692 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 |
12693 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 |
12694 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 |
12695 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000 |
12696 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_BAR1_CAP_DEFAULT 0x00000000 |
12697 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_BAR1_CNTL_DEFAULT 0x00000020 |
12698 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_BAR2_CAP_DEFAULT 0x00000000 |
12699 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_BAR2_CNTL_DEFAULT 0x00000000 |
12700 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_BAR3_CAP_DEFAULT 0x00000000 |
12701 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_BAR3_CNTL_DEFAULT 0x00000000 |
12702 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_BAR4_CAP_DEFAULT 0x00000000 |
12703 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_BAR4_CNTL_DEFAULT 0x00000000 |
12704 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_BAR5_CAP_DEFAULT 0x00000000 |
12705 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_BAR5_CNTL_DEFAULT 0x00000000 |
12706 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_BAR6_CAP_DEFAULT 0x00000000 |
12707 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_BAR6_CNTL_DEFAULT 0x00000000 |
12708 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000 |
12709 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000 |
12710 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000 |
12711 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000 |
12712 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000 |
12713 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_DPA_CAP_DEFAULT 0x00000000 |
12714 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000 |
12715 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_DPA_STATUS_DEFAULT 0x00000100 |
12716 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_DPA_CNTL_DEFAULT 0x00000000 |
12717 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000 |
12718 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000 |
12719 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000 |
12720 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000 |
12721 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000 |
12722 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000 |
12723 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000 |
12724 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000 |
12725 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a010019 |
12726 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_LINK_CNTL3_DEFAULT 0x00000000 |
12727 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000 |
12728 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
12729 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
12730 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
12731 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
12732 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
12733 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
12734 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
12735 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
12736 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
12737 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
12738 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
12739 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
12740 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
12741 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
12742 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
12743 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
12744 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000 |
12745 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_ACS_CAP_DEFAULT 0x00000000 |
12746 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_ACS_CNTL_DEFAULT 0x00000000 |
12747 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 |
12748 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_ATS_CAP_DEFAULT 0x00000000 |
12749 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_ATS_CNTL_DEFAULT 0x00000000 |
12750 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_PAGE_REQ_ENH_CAP_LIST_DEFAULT 0x2d000000 |
12751 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_PAGE_REQ_CNTL_DEFAULT 0x00000000 |
12752 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_PAGE_REQ_STATUS_DEFAULT 0x00000000 |
12753 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_OUTSTAND_PAGE_REQ_CAPACITY_DEFAULT 0x00000000 |
12754 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_OUTSTAND_PAGE_REQ_ALLOC_DEFAULT 0x00000000 |
12755 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_PASID_ENH_CAP_LIST_DEFAULT 0x2e000000 |
12756 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_PASID_CAP_DEFAULT 0x00000000 |
12757 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_PASID_CNTL_DEFAULT 0x00000000 |
12758 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_ENH_CAP_LIST_DEFAULT 0x2f000000 |
12759 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_CAP_DEFAULT 0x00000000 |
12760 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_TPH_REQR_CNTL_DEFAULT 0x00000000 |
12761 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_MC_ENH_CAP_LIST_DEFAULT 0x32000000 |
12762 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_MC_CAP_DEFAULT 0x00000000 |
12763 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_MC_CNTL_DEFAULT 0x00000000 |
12764 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_MC_ADDR0_DEFAULT 0x00000000 |
12765 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_MC_ADDR1_DEFAULT 0x00000000 |
12766 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_MC_RCV0_DEFAULT 0x00000000 |
12767 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_MC_RCV1_DEFAULT 0x00000000 |
12768 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_MC_BLOCK_ALL0_DEFAULT 0x00000000 |
12769 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_MC_BLOCK_ALL1_DEFAULT 0x00000000 |
12770 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_MC_BLOCK_UNTRANSLATED_0_DEFAULT 0x00000000 |
12771 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_MC_BLOCK_UNTRANSLATED_1_DEFAULT 0x00000000 |
12772 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_LTR_ENH_CAP_LIST_DEFAULT 0x32800000 |
12773 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_LTR_CAP_DEFAULT 0x00000000 |
12774 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000 |
12775 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_ARI_CAP_DEFAULT 0x00000000 |
12776 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_ARI_CNTL_DEFAULT 0x00000000 |
12777 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_ENH_CAP_LIST_DEFAULT 0x00000000 |
12778 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_CAP_DEFAULT 0x00000000 |
12779 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_CONTROL_DEFAULT 0x00000000 |
12780 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_STATUS_DEFAULT 0x00000000 |
12781 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_INITIAL_VFS_DEFAULT 0x00000000 |
12782 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_TOTAL_VFS_DEFAULT 0x00000000 |
12783 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_NUM_VFS_DEFAULT 0x00000000 |
12784 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_FUNC_DEP_LINK_DEFAULT 0x00000000 |
12785 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_FIRST_VF_OFFSET_DEFAULT 0x00000000 |
12786 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_STRIDE_DEFAULT 0x00000000 |
12787 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_DEVICE_ID_DEFAULT 0x00000000 |
12788 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_SUPPORTED_PAGE_SIZE_DEFAULT 0x00000000 |
12789 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_SYSTEM_PAGE_SIZE_DEFAULT 0x00000001 |
12790 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_BASE_ADDR_0_DEFAULT 0x00000000 |
12791 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_BASE_ADDR_1_DEFAULT 0x00000000 |
12792 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_BASE_ADDR_2_DEFAULT 0x00000000 |
12793 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_BASE_ADDR_3_DEFAULT 0x00000000 |
12794 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_BASE_ADDR_4_DEFAULT 0x00000000 |
12795 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_BASE_ADDR_5_DEFAULT 0x00000000 |
12796 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_DEFAULT 0x00000000 |
12797 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_DEFAULT 0x00000000 |
12798 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_DEFAULT 0x00000000 |
12799 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW_DEFAULT 0x00000000 |
12800 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_DEFAULT 0x00000000 |
12801 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_DEFAULT 0x00000000 |
12802 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_DEFAULT 0x00000000 |
12803 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0_DEFAULT 0x00000000 |
12804 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_DEFAULT 0x00000000 |
12805 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2_DEFAULT 0x00000000 |
12806 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT_DEFAULT 0x00000000 |
12807 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB_DEFAULT 0x00000000 |
12808 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS_DEFAULT 0x00000000 |
12809 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB_DEFAULT 0x00000000 |
12810 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB_DEFAULT 0x00000000 |
12811 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB_DEFAULT 0x00000000 |
12812 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB_DEFAULT 0x00000000 |
12813 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB_DEFAULT 0x00000000 |
12814 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB_DEFAULT 0x00000000 |
12815 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB_DEFAULT 0x00000000 |
12816 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB_DEFAULT 0x00000000 |
12817 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB_DEFAULT 0x00000000 |
12818 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB_DEFAULT 0x00000000 |
12819 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB_DEFAULT 0x00000000 |
12820 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB_DEFAULT 0x00000000 |
12821 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB_DEFAULT 0x00000000 |
12822 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB_DEFAULT 0x00000000 |
12823 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB_DEFAULT 0x00000000 |
12824 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB_DEFAULT 0x00000000 |
12825 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0_DEFAULT 0x00000000 |
12826 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1_DEFAULT 0x00000000 |
12827 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2_DEFAULT 0x00000000 |
12828 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3_DEFAULT 0x00000000 |
12829 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4_DEFAULT 0x00000000 |
12830 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5_DEFAULT 0x00000000 |
12831 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6_DEFAULT 0x00000000 |
12832 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7_DEFAULT 0x00000000 |
12833 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8_DEFAULT 0x00000000 |
12834 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0_DEFAULT 0x00000000 |
12835 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1_DEFAULT 0x00000000 |
12836 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2_DEFAULT 0x00000000 |
12837 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3_DEFAULT 0x00000000 |
12838 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4_DEFAULT 0x00000000 |
12839 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5_DEFAULT 0x00000000 |
12840 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6_DEFAULT 0x00000000 |
12841 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7_DEFAULT 0x00000000 |
12842 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8_DEFAULT 0x00000000 |
12843 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0_DEFAULT 0x00000000 |
12844 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1_DEFAULT 0x00000000 |
12845 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2_DEFAULT 0x00000000 |
12846 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3_DEFAULT 0x00000000 |
12847 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4_DEFAULT 0x00000000 |
12848 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5_DEFAULT 0x00000000 |
12849 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6_DEFAULT 0x00000000 |
12850 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7_DEFAULT 0x00000000 |
12851 | #define smnBIF_CFG_DEV0_EPF0_3_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8_DEFAULT 0x00000000 |
12852 | |
12853 | |
12854 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf1_bifcfgdecp |
12855 | #define smnBIF_CFG_DEV0_EPF1_2_VENDOR_ID_DEFAULT 0x00000000 |
12856 | #define smnBIF_CFG_DEV0_EPF1_2_DEVICE_ID_DEFAULT 0x00000000 |
12857 | #define smnBIF_CFG_DEV0_EPF1_2_COMMAND_DEFAULT 0x00000000 |
12858 | #define smnBIF_CFG_DEV0_EPF1_2_STATUS_DEFAULT 0x00000000 |
12859 | #define smnBIF_CFG_DEV0_EPF1_2_REVISION_ID_DEFAULT 0x00000000 |
12860 | #define smnBIF_CFG_DEV0_EPF1_2_PROG_INTERFACE_DEFAULT 0x00000000 |
12861 | #define smnBIF_CFG_DEV0_EPF1_2_SUB_CLASS_DEFAULT 0x00000000 |
12862 | #define smnBIF_CFG_DEV0_EPF1_2_BASE_CLASS_DEFAULT 0x00000000 |
12863 | #define smnBIF_CFG_DEV0_EPF1_2_CACHE_LINE_DEFAULT 0x00000000 |
12864 | #define smnBIF_CFG_DEV0_EPF1_2_LATENCY_DEFAULT 0x00000000 |
12865 | #define 0x00000000 |
12866 | #define smnBIF_CFG_DEV0_EPF1_2_BIST_DEFAULT 0x00000000 |
12867 | #define smnBIF_CFG_DEV0_EPF1_2_BASE_ADDR_1_DEFAULT 0x00000000 |
12868 | #define smnBIF_CFG_DEV0_EPF1_2_BASE_ADDR_2_DEFAULT 0x00000000 |
12869 | #define smnBIF_CFG_DEV0_EPF1_2_BASE_ADDR_3_DEFAULT 0x00000000 |
12870 | #define smnBIF_CFG_DEV0_EPF1_2_BASE_ADDR_4_DEFAULT 0x00000000 |
12871 | #define smnBIF_CFG_DEV0_EPF1_2_BASE_ADDR_5_DEFAULT 0x00000000 |
12872 | #define smnBIF_CFG_DEV0_EPF1_2_BASE_ADDR_6_DEFAULT 0x00000000 |
12873 | #define smnBIF_CFG_DEV0_EPF1_2_ADAPTER_ID_DEFAULT 0x00000000 |
12874 | #define smnBIF_CFG_DEV0_EPF1_2_ROM_BASE_ADDR_DEFAULT 0x00000000 |
12875 | #define smnBIF_CFG_DEV0_EPF1_2_CAP_PTR_DEFAULT 0x00000000 |
12876 | #define smnBIF_CFG_DEV0_EPF1_2_INTERRUPT_LINE_DEFAULT 0x000000ff |
12877 | #define smnBIF_CFG_DEV0_EPF1_2_INTERRUPT_PIN_DEFAULT 0x00000000 |
12878 | #define smnBIF_CFG_DEV0_EPF1_2_MIN_GRANT_DEFAULT 0x00000000 |
12879 | #define smnBIF_CFG_DEV0_EPF1_2_MAX_LATENCY_DEFAULT 0x00000000 |
12880 | #define smnBIF_CFG_DEV0_EPF1_2_VENDOR_CAP_LIST_DEFAULT 0x00000000 |
12881 | #define smnBIF_CFG_DEV0_EPF1_2_ADAPTER_ID_W_DEFAULT 0x00000000 |
12882 | #define smnBIF_CFG_DEV0_EPF1_2_PMI_CAP_LIST_DEFAULT 0x00000000 |
12883 | #define smnBIF_CFG_DEV0_EPF1_2_PMI_CAP_DEFAULT 0x00000000 |
12884 | #define smnBIF_CFG_DEV0_EPF1_2_PMI_STATUS_CNTL_DEFAULT 0x00000000 |
12885 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_CAP_LIST_DEFAULT 0x0000a000 |
12886 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_CAP_DEFAULT 0x00000002 |
12887 | #define smnBIF_CFG_DEV0_EPF1_2_DEVICE_CAP_DEFAULT 0x10000000 |
12888 | #define smnBIF_CFG_DEV0_EPF1_2_DEVICE_CNTL_DEFAULT 0x00002810 |
12889 | #define smnBIF_CFG_DEV0_EPF1_2_DEVICE_STATUS_DEFAULT 0x00000000 |
12890 | #define smnBIF_CFG_DEV0_EPF1_2_LINK_CAP_DEFAULT 0x00011c03 |
12891 | #define smnBIF_CFG_DEV0_EPF1_2_LINK_CNTL_DEFAULT 0x00000000 |
12892 | #define smnBIF_CFG_DEV0_EPF1_2_LINK_STATUS_DEFAULT 0x00000001 |
12893 | #define smnBIF_CFG_DEV0_EPF1_2_DEVICE_CAP2_DEFAULT 0x00000000 |
12894 | #define smnBIF_CFG_DEV0_EPF1_2_DEVICE_CNTL2_DEFAULT 0x00000000 |
12895 | #define smnBIF_CFG_DEV0_EPF1_2_DEVICE_STATUS2_DEFAULT 0x00000000 |
12896 | #define smnBIF_CFG_DEV0_EPF1_2_LINK_CAP2_DEFAULT 0x0000000e |
12897 | #define smnBIF_CFG_DEV0_EPF1_2_LINK_CNTL2_DEFAULT 0x00000003 |
12898 | #define smnBIF_CFG_DEV0_EPF1_2_LINK_STATUS2_DEFAULT 0x00000000 |
12899 | #define smnBIF_CFG_DEV0_EPF1_2_SLOT_CAP2_DEFAULT 0x00000000 |
12900 | #define smnBIF_CFG_DEV0_EPF1_2_SLOT_CNTL2_DEFAULT 0x00000000 |
12901 | #define smnBIF_CFG_DEV0_EPF1_2_SLOT_STATUS2_DEFAULT 0x00000000 |
12902 | #define smnBIF_CFG_DEV0_EPF1_2_MSI_CAP_LIST_DEFAULT 0x0000c000 |
12903 | #define smnBIF_CFG_DEV0_EPF1_2_MSI_MSG_CNTL_DEFAULT 0x00000080 |
12904 | #define smnBIF_CFG_DEV0_EPF1_2_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 |
12905 | #define smnBIF_CFG_DEV0_EPF1_2_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 |
12906 | #define smnBIF_CFG_DEV0_EPF1_2_MSI_MSG_DATA_DEFAULT 0x00000000 |
12907 | #define smnBIF_CFG_DEV0_EPF1_2_MSI_MASK_DEFAULT 0x00000000 |
12908 | #define smnBIF_CFG_DEV0_EPF1_2_MSI_MSG_DATA_64_DEFAULT 0x00000000 |
12909 | #define smnBIF_CFG_DEV0_EPF1_2_MSI_MASK_64_DEFAULT 0x00000000 |
12910 | #define smnBIF_CFG_DEV0_EPF1_2_MSI_PENDING_DEFAULT 0x00000000 |
12911 | #define smnBIF_CFG_DEV0_EPF1_2_MSI_PENDING_64_DEFAULT 0x00000000 |
12912 | #define smnBIF_CFG_DEV0_EPF1_2_MSIX_CAP_LIST_DEFAULT 0x00000000 |
12913 | #define smnBIF_CFG_DEV0_EPF1_2_MSIX_MSG_CNTL_DEFAULT 0x00000000 |
12914 | #define smnBIF_CFG_DEV0_EPF1_2_MSIX_TABLE_DEFAULT 0x00000000 |
12915 | #define smnBIF_CFG_DEV0_EPF1_2_MSIX_PBA_DEFAULT 0x00000000 |
12916 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 |
12917 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 |
12918 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 |
12919 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 |
12920 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000 |
12921 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000 |
12922 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000 |
12923 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000 |
12924 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000 |
12925 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000 |
12926 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe |
12927 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000000 |
12928 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000 |
12929 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000 |
12930 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000000 |
12931 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000 |
12932 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000 |
12933 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000 |
12934 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 |
12935 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 |
12936 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 |
12937 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 |
12938 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 |
12939 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000 |
12940 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 |
12941 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_HDR_LOG0_DEFAULT 0x00000000 |
12942 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_HDR_LOG1_DEFAULT 0x00000000 |
12943 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_HDR_LOG2_DEFAULT 0x00000000 |
12944 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_HDR_LOG3_DEFAULT 0x00000000 |
12945 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 |
12946 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 |
12947 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 |
12948 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 |
12949 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000 |
12950 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_BAR1_CAP_DEFAULT 0x00000000 |
12951 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_BAR1_CNTL_DEFAULT 0x00000020 |
12952 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_BAR2_CAP_DEFAULT 0x00000000 |
12953 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_BAR2_CNTL_DEFAULT 0x00000000 |
12954 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_BAR3_CAP_DEFAULT 0x00000000 |
12955 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_BAR3_CNTL_DEFAULT 0x00000000 |
12956 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_BAR4_CAP_DEFAULT 0x00000000 |
12957 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_BAR4_CNTL_DEFAULT 0x00000000 |
12958 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_BAR5_CAP_DEFAULT 0x00000000 |
12959 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_BAR5_CNTL_DEFAULT 0x00000000 |
12960 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_BAR6_CAP_DEFAULT 0x00000000 |
12961 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_BAR6_CNTL_DEFAULT 0x00000000 |
12962 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000 |
12963 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000 |
12964 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000 |
12965 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000 |
12966 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000 |
12967 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_DPA_CAP_DEFAULT 0x00000000 |
12968 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000 |
12969 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_DPA_STATUS_DEFAULT 0x00000100 |
12970 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_DPA_CNTL_DEFAULT 0x00000000 |
12971 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000 |
12972 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000 |
12973 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000 |
12974 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000 |
12975 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000 |
12976 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000 |
12977 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000 |
12978 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000 |
12979 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a010019 |
12980 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_LINK_CNTL3_DEFAULT 0x00000000 |
12981 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000 |
12982 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
12983 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
12984 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
12985 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
12986 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
12987 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
12988 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
12989 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
12990 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
12991 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
12992 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
12993 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
12994 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
12995 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
12996 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
12997 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
12998 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000 |
12999 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_ACS_CAP_DEFAULT 0x00000000 |
13000 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_ACS_CNTL_DEFAULT 0x00000000 |
13001 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 |
13002 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_ATS_CAP_DEFAULT 0x00000000 |
13003 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_ATS_CNTL_DEFAULT 0x00000000 |
13004 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_PAGE_REQ_ENH_CAP_LIST_DEFAULT 0x2d000000 |
13005 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_PAGE_REQ_CNTL_DEFAULT 0x00000000 |
13006 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_PAGE_REQ_STATUS_DEFAULT 0x00000000 |
13007 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_OUTSTAND_PAGE_REQ_CAPACITY_DEFAULT 0x00000000 |
13008 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_OUTSTAND_PAGE_REQ_ALLOC_DEFAULT 0x00000000 |
13009 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_PASID_ENH_CAP_LIST_DEFAULT 0x2e000000 |
13010 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_PASID_CAP_DEFAULT 0x00000000 |
13011 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_PASID_CNTL_DEFAULT 0x00000000 |
13012 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_ENH_CAP_LIST_DEFAULT 0x2f000000 |
13013 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_CAP_DEFAULT 0x00000000 |
13014 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_TPH_REQR_CNTL_DEFAULT 0x00000000 |
13015 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_MC_ENH_CAP_LIST_DEFAULT 0x32000000 |
13016 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_MC_CAP_DEFAULT 0x00000000 |
13017 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_MC_CNTL_DEFAULT 0x00000000 |
13018 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_MC_ADDR0_DEFAULT 0x00000000 |
13019 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_MC_ADDR1_DEFAULT 0x00000000 |
13020 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_MC_RCV0_DEFAULT 0x00000000 |
13021 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_MC_RCV1_DEFAULT 0x00000000 |
13022 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_MC_BLOCK_ALL0_DEFAULT 0x00000000 |
13023 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_MC_BLOCK_ALL1_DEFAULT 0x00000000 |
13024 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_MC_BLOCK_UNTRANSLATED_0_DEFAULT 0x00000000 |
13025 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_MC_BLOCK_UNTRANSLATED_1_DEFAULT 0x00000000 |
13026 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_LTR_ENH_CAP_LIST_DEFAULT 0x32800000 |
13027 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_LTR_CAP_DEFAULT 0x00000000 |
13028 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000 |
13029 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_ARI_CAP_DEFAULT 0x00000000 |
13030 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_ARI_CNTL_DEFAULT 0x00000000 |
13031 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_ENH_CAP_LIST_DEFAULT 0x00000000 |
13032 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_CAP_DEFAULT 0x00000000 |
13033 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_CONTROL_DEFAULT 0x00000000 |
13034 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_STATUS_DEFAULT 0x00000000 |
13035 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_INITIAL_VFS_DEFAULT 0x00000000 |
13036 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_TOTAL_VFS_DEFAULT 0x00000000 |
13037 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_NUM_VFS_DEFAULT 0x00000000 |
13038 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_FUNC_DEP_LINK_DEFAULT 0x00000000 |
13039 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_FIRST_VF_OFFSET_DEFAULT 0x00000000 |
13040 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_STRIDE_DEFAULT 0x00000000 |
13041 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_DEVICE_ID_DEFAULT 0x00000000 |
13042 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_SUPPORTED_PAGE_SIZE_DEFAULT 0x00000000 |
13043 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_SYSTEM_PAGE_SIZE_DEFAULT 0x00000001 |
13044 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_BASE_ADDR_0_DEFAULT 0x00000000 |
13045 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_BASE_ADDR_1_DEFAULT 0x00000000 |
13046 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_BASE_ADDR_2_DEFAULT 0x00000000 |
13047 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_BASE_ADDR_3_DEFAULT 0x00000000 |
13048 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_BASE_ADDR_4_DEFAULT 0x00000000 |
13049 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_BASE_ADDR_5_DEFAULT 0x00000000 |
13050 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_DEFAULT 0x00000000 |
13051 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_DEFAULT 0x00000000 |
13052 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_DEFAULT 0x00000000 |
13053 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW_DEFAULT 0x00000000 |
13054 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_DEFAULT 0x00000000 |
13055 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_DEFAULT 0x00000000 |
13056 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_DEFAULT 0x00000000 |
13057 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0_DEFAULT 0x00000000 |
13058 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_DEFAULT 0x00000000 |
13059 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2_DEFAULT 0x00000000 |
13060 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT_DEFAULT 0x00000000 |
13061 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB_DEFAULT 0x00000000 |
13062 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS_DEFAULT 0x00000000 |
13063 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB_DEFAULT 0x00000000 |
13064 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB_DEFAULT 0x00000000 |
13065 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB_DEFAULT 0x00000000 |
13066 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB_DEFAULT 0x00000000 |
13067 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB_DEFAULT 0x00000000 |
13068 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB_DEFAULT 0x00000000 |
13069 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB_DEFAULT 0x00000000 |
13070 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB_DEFAULT 0x00000000 |
13071 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB_DEFAULT 0x00000000 |
13072 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB_DEFAULT 0x00000000 |
13073 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB_DEFAULT 0x00000000 |
13074 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB_DEFAULT 0x00000000 |
13075 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB_DEFAULT 0x00000000 |
13076 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB_DEFAULT 0x00000000 |
13077 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB_DEFAULT 0x00000000 |
13078 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB_DEFAULT 0x00000000 |
13079 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0_DEFAULT 0x00000000 |
13080 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1_DEFAULT 0x00000000 |
13081 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2_DEFAULT 0x00000000 |
13082 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3_DEFAULT 0x00000000 |
13083 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4_DEFAULT 0x00000000 |
13084 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5_DEFAULT 0x00000000 |
13085 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6_DEFAULT 0x00000000 |
13086 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7_DEFAULT 0x00000000 |
13087 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8_DEFAULT 0x00000000 |
13088 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0_DEFAULT 0x00000000 |
13089 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1_DEFAULT 0x00000000 |
13090 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2_DEFAULT 0x00000000 |
13091 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3_DEFAULT 0x00000000 |
13092 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4_DEFAULT 0x00000000 |
13093 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5_DEFAULT 0x00000000 |
13094 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6_DEFAULT 0x00000000 |
13095 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7_DEFAULT 0x00000000 |
13096 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8_DEFAULT 0x00000000 |
13097 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0_DEFAULT 0x00000000 |
13098 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1_DEFAULT 0x00000000 |
13099 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2_DEFAULT 0x00000000 |
13100 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3_DEFAULT 0x00000000 |
13101 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4_DEFAULT 0x00000000 |
13102 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5_DEFAULT 0x00000000 |
13103 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6_DEFAULT 0x00000000 |
13104 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7_DEFAULT 0x00000000 |
13105 | #define smnBIF_CFG_DEV0_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8_DEFAULT 0x00000000 |
13106 | |
13107 | |
13108 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf2_bifcfgdecp |
13109 | #define smnBIF_CFG_DEV0_EPF2_2_VENDOR_ID_DEFAULT 0x00000000 |
13110 | #define smnBIF_CFG_DEV0_EPF2_2_DEVICE_ID_DEFAULT 0x00000000 |
13111 | #define smnBIF_CFG_DEV0_EPF2_2_COMMAND_DEFAULT 0x00000000 |
13112 | #define smnBIF_CFG_DEV0_EPF2_2_STATUS_DEFAULT 0x00000000 |
13113 | #define smnBIF_CFG_DEV0_EPF2_2_REVISION_ID_DEFAULT 0x00000000 |
13114 | #define smnBIF_CFG_DEV0_EPF2_2_PROG_INTERFACE_DEFAULT 0x00000000 |
13115 | #define smnBIF_CFG_DEV0_EPF2_2_SUB_CLASS_DEFAULT 0x00000000 |
13116 | #define smnBIF_CFG_DEV0_EPF2_2_BASE_CLASS_DEFAULT 0x00000000 |
13117 | #define smnBIF_CFG_DEV0_EPF2_2_CACHE_LINE_DEFAULT 0x00000000 |
13118 | #define smnBIF_CFG_DEV0_EPF2_2_LATENCY_DEFAULT 0x00000000 |
13119 | #define 0x00000000 |
13120 | #define smnBIF_CFG_DEV0_EPF2_2_BIST_DEFAULT 0x00000000 |
13121 | #define smnBIF_CFG_DEV0_EPF2_2_BASE_ADDR_1_DEFAULT 0x00000000 |
13122 | #define smnBIF_CFG_DEV0_EPF2_2_BASE_ADDR_2_DEFAULT 0x00000000 |
13123 | #define smnBIF_CFG_DEV0_EPF2_2_BASE_ADDR_3_DEFAULT 0x00000000 |
13124 | #define smnBIF_CFG_DEV0_EPF2_2_BASE_ADDR_4_DEFAULT 0x00000000 |
13125 | #define smnBIF_CFG_DEV0_EPF2_2_BASE_ADDR_5_DEFAULT 0x00000000 |
13126 | #define smnBIF_CFG_DEV0_EPF2_2_BASE_ADDR_6_DEFAULT 0x00000000 |
13127 | #define smnBIF_CFG_DEV0_EPF2_2_ADAPTER_ID_DEFAULT 0x00000000 |
13128 | #define smnBIF_CFG_DEV0_EPF2_2_ROM_BASE_ADDR_DEFAULT 0x00000000 |
13129 | #define smnBIF_CFG_DEV0_EPF2_2_CAP_PTR_DEFAULT 0x00000000 |
13130 | #define smnBIF_CFG_DEV0_EPF2_2_INTERRUPT_LINE_DEFAULT 0x00000000 |
13131 | #define smnBIF_CFG_DEV0_EPF2_2_INTERRUPT_PIN_DEFAULT 0x00000000 |
13132 | #define smnBIF_CFG_DEV0_EPF2_2_MIN_GRANT_DEFAULT 0x00000000 |
13133 | #define smnBIF_CFG_DEV0_EPF2_2_MAX_LATENCY_DEFAULT 0x00000000 |
13134 | #define smnBIF_CFG_DEV0_EPF2_2_VENDOR_CAP_LIST_DEFAULT 0x00000000 |
13135 | #define smnBIF_CFG_DEV0_EPF2_2_ADAPTER_ID_W_DEFAULT 0x00000000 |
13136 | #define smnBIF_CFG_DEV0_EPF2_2_PMI_CAP_LIST_DEFAULT 0x00000000 |
13137 | #define smnBIF_CFG_DEV0_EPF2_2_PMI_CAP_DEFAULT 0x00000000 |
13138 | #define smnBIF_CFG_DEV0_EPF2_2_PMI_STATUS_CNTL_DEFAULT 0x00000000 |
13139 | #define smnBIF_CFG_DEV0_EPF2_2_SBRN_DEFAULT 0x00000000 |
13140 | #define smnBIF_CFG_DEV0_EPF2_2_FLADJ_DEFAULT 0x00000020 |
13141 | #define smnBIF_CFG_DEV0_EPF2_2_DBESL_DBESLD_DEFAULT 0x00000000 |
13142 | #define smnBIF_CFG_DEV0_EPF2_2_PCIE_CAP_LIST_DEFAULT 0x0000a000 |
13143 | #define smnBIF_CFG_DEV0_EPF2_2_PCIE_CAP_DEFAULT 0x00000002 |
13144 | #define smnBIF_CFG_DEV0_EPF2_2_DEVICE_CAP_DEFAULT 0x10000000 |
13145 | #define smnBIF_CFG_DEV0_EPF2_2_DEVICE_CNTL_DEFAULT 0x00002810 |
13146 | #define smnBIF_CFG_DEV0_EPF2_2_DEVICE_STATUS_DEFAULT 0x00000000 |
13147 | #define smnBIF_CFG_DEV0_EPF2_2_LINK_CAP_DEFAULT 0x00011c03 |
13148 | #define smnBIF_CFG_DEV0_EPF2_2_LINK_CNTL_DEFAULT 0x00000000 |
13149 | #define smnBIF_CFG_DEV0_EPF2_2_LINK_STATUS_DEFAULT 0x00000001 |
13150 | #define smnBIF_CFG_DEV0_EPF2_2_DEVICE_CAP2_DEFAULT 0x00000000 |
13151 | #define smnBIF_CFG_DEV0_EPF2_2_DEVICE_CNTL2_DEFAULT 0x00000000 |
13152 | #define smnBIF_CFG_DEV0_EPF2_2_DEVICE_STATUS2_DEFAULT 0x00000000 |
13153 | #define smnBIF_CFG_DEV0_EPF2_2_LINK_CAP2_DEFAULT 0x0000000e |
13154 | #define smnBIF_CFG_DEV0_EPF2_2_LINK_CNTL2_DEFAULT 0x00000003 |
13155 | #define smnBIF_CFG_DEV0_EPF2_2_LINK_STATUS2_DEFAULT 0x00000000 |
13156 | #define smnBIF_CFG_DEV0_EPF2_2_SLOT_CAP2_DEFAULT 0x00000000 |
13157 | #define smnBIF_CFG_DEV0_EPF2_2_SLOT_CNTL2_DEFAULT 0x00000000 |
13158 | #define smnBIF_CFG_DEV0_EPF2_2_SLOT_STATUS2_DEFAULT 0x00000000 |
13159 | #define smnBIF_CFG_DEV0_EPF2_2_MSI_CAP_LIST_DEFAULT 0x0000c000 |
13160 | #define smnBIF_CFG_DEV0_EPF2_2_MSI_MSG_CNTL_DEFAULT 0x00000080 |
13161 | #define smnBIF_CFG_DEV0_EPF2_2_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 |
13162 | #define smnBIF_CFG_DEV0_EPF2_2_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 |
13163 | #define smnBIF_CFG_DEV0_EPF2_2_MSI_MSG_DATA_DEFAULT 0x00000000 |
13164 | #define smnBIF_CFG_DEV0_EPF2_2_MSI_MASK_DEFAULT 0x00000000 |
13165 | #define smnBIF_CFG_DEV0_EPF2_2_MSI_MSG_DATA_64_DEFAULT 0x00000000 |
13166 | #define smnBIF_CFG_DEV0_EPF2_2_MSI_MASK_64_DEFAULT 0x00000000 |
13167 | #define smnBIF_CFG_DEV0_EPF2_2_MSI_PENDING_DEFAULT 0x00000000 |
13168 | #define smnBIF_CFG_DEV0_EPF2_2_MSI_PENDING_64_DEFAULT 0x00000000 |
13169 | #define smnBIF_CFG_DEV0_EPF2_2_MSIX_CAP_LIST_DEFAULT 0x00000000 |
13170 | #define smnBIF_CFG_DEV0_EPF2_2_MSIX_MSG_CNTL_DEFAULT 0x00000000 |
13171 | #define smnBIF_CFG_DEV0_EPF2_2_MSIX_TABLE_DEFAULT 0x00000000 |
13172 | #define smnBIF_CFG_DEV0_EPF2_2_MSIX_PBA_DEFAULT 0x00000000 |
13173 | #define smnBIF_CFG_DEV0_EPF2_2_SATA_CAP_0_DEFAULT 0x00000000 |
13174 | #define smnBIF_CFG_DEV0_EPF2_2_SATA_CAP_1_DEFAULT 0x00000000 |
13175 | #define smnBIF_CFG_DEV0_EPF2_2_SATA_IDP_INDEX_DEFAULT 0x00000000 |
13176 | #define smnBIF_CFG_DEV0_EPF2_2_SATA_IDP_DATA_DEFAULT 0x00000000 |
13177 | #define smnBIF_CFG_DEV0_EPF2_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 |
13178 | #define smnBIF_CFG_DEV0_EPF2_2_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 |
13179 | #define smnBIF_CFG_DEV0_EPF2_2_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 |
13180 | #define smnBIF_CFG_DEV0_EPF2_2_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 |
13181 | #define smnBIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 |
13182 | #define smnBIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 |
13183 | #define smnBIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 |
13184 | #define smnBIF_CFG_DEV0_EPF2_2_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 |
13185 | #define smnBIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 |
13186 | #define smnBIF_CFG_DEV0_EPF2_2_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000 |
13187 | #define smnBIF_CFG_DEV0_EPF2_2_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 |
13188 | #define smnBIF_CFG_DEV0_EPF2_2_PCIE_HDR_LOG0_DEFAULT 0x00000000 |
13189 | #define smnBIF_CFG_DEV0_EPF2_2_PCIE_HDR_LOG1_DEFAULT 0x00000000 |
13190 | #define smnBIF_CFG_DEV0_EPF2_2_PCIE_HDR_LOG2_DEFAULT 0x00000000 |
13191 | #define smnBIF_CFG_DEV0_EPF2_2_PCIE_HDR_LOG3_DEFAULT 0x00000000 |
13192 | #define smnBIF_CFG_DEV0_EPF2_2_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 |
13193 | #define smnBIF_CFG_DEV0_EPF2_2_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 |
13194 | #define smnBIF_CFG_DEV0_EPF2_2_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 |
13195 | #define smnBIF_CFG_DEV0_EPF2_2_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 |
13196 | #define smnBIF_CFG_DEV0_EPF2_2_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000 |
13197 | #define smnBIF_CFG_DEV0_EPF2_2_PCIE_BAR1_CAP_DEFAULT 0x00000000 |
13198 | #define smnBIF_CFG_DEV0_EPF2_2_PCIE_BAR1_CNTL_DEFAULT 0x00000020 |
13199 | #define smnBIF_CFG_DEV0_EPF2_2_PCIE_BAR2_CAP_DEFAULT 0x00000000 |
13200 | #define smnBIF_CFG_DEV0_EPF2_2_PCIE_BAR2_CNTL_DEFAULT 0x00000000 |
13201 | #define smnBIF_CFG_DEV0_EPF2_2_PCIE_BAR3_CAP_DEFAULT 0x00000000 |
13202 | #define smnBIF_CFG_DEV0_EPF2_2_PCIE_BAR3_CNTL_DEFAULT 0x00000000 |
13203 | #define smnBIF_CFG_DEV0_EPF2_2_PCIE_BAR4_CAP_DEFAULT 0x00000000 |
13204 | #define smnBIF_CFG_DEV0_EPF2_2_PCIE_BAR4_CNTL_DEFAULT 0x00000000 |
13205 | #define smnBIF_CFG_DEV0_EPF2_2_PCIE_BAR5_CAP_DEFAULT 0x00000000 |
13206 | #define smnBIF_CFG_DEV0_EPF2_2_PCIE_BAR5_CNTL_DEFAULT 0x00000000 |
13207 | #define smnBIF_CFG_DEV0_EPF2_2_PCIE_BAR6_CAP_DEFAULT 0x00000000 |
13208 | #define smnBIF_CFG_DEV0_EPF2_2_PCIE_BAR6_CNTL_DEFAULT 0x00000000 |
13209 | #define smnBIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000 |
13210 | #define smnBIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000 |
13211 | #define smnBIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000 |
13212 | #define smnBIF_CFG_DEV0_EPF2_2_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000 |
13213 | #define smnBIF_CFG_DEV0_EPF2_2_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000 |
13214 | #define smnBIF_CFG_DEV0_EPF2_2_PCIE_DPA_CAP_DEFAULT 0x00000000 |
13215 | #define smnBIF_CFG_DEV0_EPF2_2_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000 |
13216 | #define smnBIF_CFG_DEV0_EPF2_2_PCIE_DPA_STATUS_DEFAULT 0x00000100 |
13217 | #define smnBIF_CFG_DEV0_EPF2_2_PCIE_DPA_CNTL_DEFAULT 0x00000000 |
13218 | #define smnBIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000 |
13219 | #define smnBIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000 |
13220 | #define smnBIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000 |
13221 | #define smnBIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000 |
13222 | #define smnBIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000 |
13223 | #define smnBIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000 |
13224 | #define smnBIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000 |
13225 | #define smnBIF_CFG_DEV0_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000 |
13226 | #define smnBIF_CFG_DEV0_EPF2_2_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000 |
13227 | #define smnBIF_CFG_DEV0_EPF2_2_PCIE_ACS_CAP_DEFAULT 0x00000000 |
13228 | #define smnBIF_CFG_DEV0_EPF2_2_PCIE_ACS_CNTL_DEFAULT 0x00000000 |
13229 | #define smnBIF_CFG_DEV0_EPF2_2_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000 |
13230 | #define smnBIF_CFG_DEV0_EPF2_2_PCIE_ARI_CAP_DEFAULT 0x00000000 |
13231 | #define smnBIF_CFG_DEV0_EPF2_2_PCIE_ARI_CNTL_DEFAULT 0x00000000 |
13232 | |
13233 | |
13234 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf3_bifcfgdecp |
13235 | #define smnBIF_CFG_DEV0_EPF3_2_VENDOR_ID_DEFAULT 0x00000000 |
13236 | #define smnBIF_CFG_DEV0_EPF3_2_DEVICE_ID_DEFAULT 0x00000000 |
13237 | #define smnBIF_CFG_DEV0_EPF3_2_COMMAND_DEFAULT 0x00000000 |
13238 | #define smnBIF_CFG_DEV0_EPF3_2_STATUS_DEFAULT 0x00000000 |
13239 | #define smnBIF_CFG_DEV0_EPF3_2_REVISION_ID_DEFAULT 0x00000000 |
13240 | #define smnBIF_CFG_DEV0_EPF3_2_PROG_INTERFACE_DEFAULT 0x00000000 |
13241 | #define smnBIF_CFG_DEV0_EPF3_2_SUB_CLASS_DEFAULT 0x00000000 |
13242 | #define smnBIF_CFG_DEV0_EPF3_2_BASE_CLASS_DEFAULT 0x00000000 |
13243 | #define smnBIF_CFG_DEV0_EPF3_2_CACHE_LINE_DEFAULT 0x00000000 |
13244 | #define smnBIF_CFG_DEV0_EPF3_2_LATENCY_DEFAULT 0x00000000 |
13245 | #define 0x00000000 |
13246 | #define smnBIF_CFG_DEV0_EPF3_2_BIST_DEFAULT 0x00000000 |
13247 | #define smnBIF_CFG_DEV0_EPF3_2_BASE_ADDR_1_DEFAULT 0x00000000 |
13248 | #define smnBIF_CFG_DEV0_EPF3_2_BASE_ADDR_2_DEFAULT 0x00000000 |
13249 | #define smnBIF_CFG_DEV0_EPF3_2_BASE_ADDR_3_DEFAULT 0x00000000 |
13250 | #define smnBIF_CFG_DEV0_EPF3_2_BASE_ADDR_4_DEFAULT 0x00000000 |
13251 | #define smnBIF_CFG_DEV0_EPF3_2_BASE_ADDR_5_DEFAULT 0x00000000 |
13252 | #define smnBIF_CFG_DEV0_EPF3_2_BASE_ADDR_6_DEFAULT 0x00000000 |
13253 | #define smnBIF_CFG_DEV0_EPF3_2_ADAPTER_ID_DEFAULT 0x00000000 |
13254 | #define smnBIF_CFG_DEV0_EPF3_2_ROM_BASE_ADDR_DEFAULT 0x00000000 |
13255 | #define smnBIF_CFG_DEV0_EPF3_2_CAP_PTR_DEFAULT 0x00000000 |
13256 | #define smnBIF_CFG_DEV0_EPF3_2_INTERRUPT_LINE_DEFAULT 0x00000000 |
13257 | #define smnBIF_CFG_DEV0_EPF3_2_INTERRUPT_PIN_DEFAULT 0x00000000 |
13258 | #define smnBIF_CFG_DEV0_EPF3_2_MIN_GRANT_DEFAULT 0x00000000 |
13259 | #define smnBIF_CFG_DEV0_EPF3_2_MAX_LATENCY_DEFAULT 0x00000000 |
13260 | #define smnBIF_CFG_DEV0_EPF3_2_VENDOR_CAP_LIST_DEFAULT 0x00000000 |
13261 | #define smnBIF_CFG_DEV0_EPF3_2_ADAPTER_ID_W_DEFAULT 0x00000000 |
13262 | #define smnBIF_CFG_DEV0_EPF3_2_PMI_CAP_LIST_DEFAULT 0x00000000 |
13263 | #define smnBIF_CFG_DEV0_EPF3_2_PMI_CAP_DEFAULT 0x00000000 |
13264 | #define smnBIF_CFG_DEV0_EPF3_2_PMI_STATUS_CNTL_DEFAULT 0x00000000 |
13265 | #define smnBIF_CFG_DEV0_EPF3_2_SBRN_DEFAULT 0x00000000 |
13266 | #define smnBIF_CFG_DEV0_EPF3_2_FLADJ_DEFAULT 0x00000020 |
13267 | #define smnBIF_CFG_DEV0_EPF3_2_DBESL_DBESLD_DEFAULT 0x00000000 |
13268 | #define smnBIF_CFG_DEV0_EPF3_2_PCIE_CAP_LIST_DEFAULT 0x0000a000 |
13269 | #define smnBIF_CFG_DEV0_EPF3_2_PCIE_CAP_DEFAULT 0x00000002 |
13270 | #define smnBIF_CFG_DEV0_EPF3_2_DEVICE_CAP_DEFAULT 0x10000000 |
13271 | #define smnBIF_CFG_DEV0_EPF3_2_DEVICE_CNTL_DEFAULT 0x00002810 |
13272 | #define smnBIF_CFG_DEV0_EPF3_2_DEVICE_STATUS_DEFAULT 0x00000000 |
13273 | #define smnBIF_CFG_DEV0_EPF3_2_LINK_CAP_DEFAULT 0x00011c03 |
13274 | #define smnBIF_CFG_DEV0_EPF3_2_LINK_CNTL_DEFAULT 0x00000000 |
13275 | #define smnBIF_CFG_DEV0_EPF3_2_LINK_STATUS_DEFAULT 0x00000001 |
13276 | #define smnBIF_CFG_DEV0_EPF3_2_DEVICE_CAP2_DEFAULT 0x00000000 |
13277 | #define smnBIF_CFG_DEV0_EPF3_2_DEVICE_CNTL2_DEFAULT 0x00000000 |
13278 | #define smnBIF_CFG_DEV0_EPF3_2_DEVICE_STATUS2_DEFAULT 0x00000000 |
13279 | #define smnBIF_CFG_DEV0_EPF3_2_LINK_CAP2_DEFAULT 0x0000000e |
13280 | #define smnBIF_CFG_DEV0_EPF3_2_LINK_CNTL2_DEFAULT 0x00000003 |
13281 | #define smnBIF_CFG_DEV0_EPF3_2_LINK_STATUS2_DEFAULT 0x00000000 |
13282 | #define smnBIF_CFG_DEV0_EPF3_2_SLOT_CAP2_DEFAULT 0x00000000 |
13283 | #define smnBIF_CFG_DEV0_EPF3_2_SLOT_CNTL2_DEFAULT 0x00000000 |
13284 | #define smnBIF_CFG_DEV0_EPF3_2_SLOT_STATUS2_DEFAULT 0x00000000 |
13285 | #define smnBIF_CFG_DEV0_EPF3_2_MSI_CAP_LIST_DEFAULT 0x0000c000 |
13286 | #define smnBIF_CFG_DEV0_EPF3_2_MSI_MSG_CNTL_DEFAULT 0x00000080 |
13287 | #define smnBIF_CFG_DEV0_EPF3_2_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 |
13288 | #define smnBIF_CFG_DEV0_EPF3_2_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 |
13289 | #define smnBIF_CFG_DEV0_EPF3_2_MSI_MSG_DATA_DEFAULT 0x00000000 |
13290 | #define smnBIF_CFG_DEV0_EPF3_2_MSI_MASK_DEFAULT 0x00000000 |
13291 | #define smnBIF_CFG_DEV0_EPF3_2_MSI_MSG_DATA_64_DEFAULT 0x00000000 |
13292 | #define smnBIF_CFG_DEV0_EPF3_2_MSI_MASK_64_DEFAULT 0x00000000 |
13293 | #define smnBIF_CFG_DEV0_EPF3_2_MSI_PENDING_DEFAULT 0x00000000 |
13294 | #define smnBIF_CFG_DEV0_EPF3_2_MSI_PENDING_64_DEFAULT 0x00000000 |
13295 | #define smnBIF_CFG_DEV0_EPF3_2_MSIX_CAP_LIST_DEFAULT 0x00000000 |
13296 | #define smnBIF_CFG_DEV0_EPF3_2_MSIX_MSG_CNTL_DEFAULT 0x00000000 |
13297 | #define smnBIF_CFG_DEV0_EPF3_2_MSIX_TABLE_DEFAULT 0x00000000 |
13298 | #define smnBIF_CFG_DEV0_EPF3_2_MSIX_PBA_DEFAULT 0x00000000 |
13299 | #define smnBIF_CFG_DEV0_EPF3_2_SATA_CAP_0_DEFAULT 0x00000000 |
13300 | #define smnBIF_CFG_DEV0_EPF3_2_SATA_CAP_1_DEFAULT 0x00000000 |
13301 | #define smnBIF_CFG_DEV0_EPF3_2_SATA_IDP_INDEX_DEFAULT 0x00000000 |
13302 | #define smnBIF_CFG_DEV0_EPF3_2_SATA_IDP_DATA_DEFAULT 0x00000000 |
13303 | #define smnBIF_CFG_DEV0_EPF3_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 |
13304 | #define smnBIF_CFG_DEV0_EPF3_2_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 |
13305 | #define smnBIF_CFG_DEV0_EPF3_2_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 |
13306 | #define smnBIF_CFG_DEV0_EPF3_2_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 |
13307 | #define smnBIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 |
13308 | #define smnBIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 |
13309 | #define smnBIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 |
13310 | #define smnBIF_CFG_DEV0_EPF3_2_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 |
13311 | #define smnBIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 |
13312 | #define smnBIF_CFG_DEV0_EPF3_2_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000 |
13313 | #define smnBIF_CFG_DEV0_EPF3_2_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 |
13314 | #define smnBIF_CFG_DEV0_EPF3_2_PCIE_HDR_LOG0_DEFAULT 0x00000000 |
13315 | #define smnBIF_CFG_DEV0_EPF3_2_PCIE_HDR_LOG1_DEFAULT 0x00000000 |
13316 | #define smnBIF_CFG_DEV0_EPF3_2_PCIE_HDR_LOG2_DEFAULT 0x00000000 |
13317 | #define smnBIF_CFG_DEV0_EPF3_2_PCIE_HDR_LOG3_DEFAULT 0x00000000 |
13318 | #define smnBIF_CFG_DEV0_EPF3_2_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 |
13319 | #define smnBIF_CFG_DEV0_EPF3_2_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 |
13320 | #define smnBIF_CFG_DEV0_EPF3_2_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 |
13321 | #define smnBIF_CFG_DEV0_EPF3_2_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 |
13322 | #define smnBIF_CFG_DEV0_EPF3_2_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000 |
13323 | #define smnBIF_CFG_DEV0_EPF3_2_PCIE_BAR1_CAP_DEFAULT 0x00000000 |
13324 | #define smnBIF_CFG_DEV0_EPF3_2_PCIE_BAR1_CNTL_DEFAULT 0x00000020 |
13325 | #define smnBIF_CFG_DEV0_EPF3_2_PCIE_BAR2_CAP_DEFAULT 0x00000000 |
13326 | #define smnBIF_CFG_DEV0_EPF3_2_PCIE_BAR2_CNTL_DEFAULT 0x00000000 |
13327 | #define smnBIF_CFG_DEV0_EPF3_2_PCIE_BAR3_CAP_DEFAULT 0x00000000 |
13328 | #define smnBIF_CFG_DEV0_EPF3_2_PCIE_BAR3_CNTL_DEFAULT 0x00000000 |
13329 | #define smnBIF_CFG_DEV0_EPF3_2_PCIE_BAR4_CAP_DEFAULT 0x00000000 |
13330 | #define smnBIF_CFG_DEV0_EPF3_2_PCIE_BAR4_CNTL_DEFAULT 0x00000000 |
13331 | #define smnBIF_CFG_DEV0_EPF3_2_PCIE_BAR5_CAP_DEFAULT 0x00000000 |
13332 | #define smnBIF_CFG_DEV0_EPF3_2_PCIE_BAR5_CNTL_DEFAULT 0x00000000 |
13333 | #define smnBIF_CFG_DEV0_EPF3_2_PCIE_BAR6_CAP_DEFAULT 0x00000000 |
13334 | #define smnBIF_CFG_DEV0_EPF3_2_PCIE_BAR6_CNTL_DEFAULT 0x00000000 |
13335 | #define smnBIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000 |
13336 | #define smnBIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000 |
13337 | #define smnBIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000 |
13338 | #define smnBIF_CFG_DEV0_EPF3_2_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000 |
13339 | #define smnBIF_CFG_DEV0_EPF3_2_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000 |
13340 | #define smnBIF_CFG_DEV0_EPF3_2_PCIE_DPA_CAP_DEFAULT 0x00000000 |
13341 | #define smnBIF_CFG_DEV0_EPF3_2_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000 |
13342 | #define smnBIF_CFG_DEV0_EPF3_2_PCIE_DPA_STATUS_DEFAULT 0x00000100 |
13343 | #define smnBIF_CFG_DEV0_EPF3_2_PCIE_DPA_CNTL_DEFAULT 0x00000000 |
13344 | #define smnBIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000 |
13345 | #define smnBIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000 |
13346 | #define smnBIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000 |
13347 | #define smnBIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000 |
13348 | #define smnBIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000 |
13349 | #define smnBIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000 |
13350 | #define smnBIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000 |
13351 | #define smnBIF_CFG_DEV0_EPF3_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000 |
13352 | #define smnBIF_CFG_DEV0_EPF3_2_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000 |
13353 | #define smnBIF_CFG_DEV0_EPF3_2_PCIE_ACS_CAP_DEFAULT 0x00000000 |
13354 | #define smnBIF_CFG_DEV0_EPF3_2_PCIE_ACS_CNTL_DEFAULT 0x00000000 |
13355 | #define smnBIF_CFG_DEV0_EPF3_2_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000 |
13356 | #define smnBIF_CFG_DEV0_EPF3_2_PCIE_ARI_CAP_DEFAULT 0x00000000 |
13357 | #define smnBIF_CFG_DEV0_EPF3_2_PCIE_ARI_CNTL_DEFAULT 0x00000000 |
13358 | |
13359 | |
13360 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf4_bifcfgdecp |
13361 | #define smnBIF_CFG_DEV0_EPF4_2_VENDOR_ID_DEFAULT 0x00000000 |
13362 | #define smnBIF_CFG_DEV0_EPF4_2_DEVICE_ID_DEFAULT 0x00000000 |
13363 | #define smnBIF_CFG_DEV0_EPF4_2_COMMAND_DEFAULT 0x00000000 |
13364 | #define smnBIF_CFG_DEV0_EPF4_2_STATUS_DEFAULT 0x00000000 |
13365 | #define smnBIF_CFG_DEV0_EPF4_2_REVISION_ID_DEFAULT 0x00000000 |
13366 | #define smnBIF_CFG_DEV0_EPF4_2_PROG_INTERFACE_DEFAULT 0x00000000 |
13367 | #define smnBIF_CFG_DEV0_EPF4_2_SUB_CLASS_DEFAULT 0x00000000 |
13368 | #define smnBIF_CFG_DEV0_EPF4_2_BASE_CLASS_DEFAULT 0x00000000 |
13369 | #define smnBIF_CFG_DEV0_EPF4_2_CACHE_LINE_DEFAULT 0x00000000 |
13370 | #define smnBIF_CFG_DEV0_EPF4_2_LATENCY_DEFAULT 0x00000000 |
13371 | #define 0x00000000 |
13372 | #define smnBIF_CFG_DEV0_EPF4_2_BIST_DEFAULT 0x00000000 |
13373 | #define smnBIF_CFG_DEV0_EPF4_2_BASE_ADDR_1_DEFAULT 0x00000000 |
13374 | #define smnBIF_CFG_DEV0_EPF4_2_BASE_ADDR_2_DEFAULT 0x00000000 |
13375 | #define smnBIF_CFG_DEV0_EPF4_2_BASE_ADDR_3_DEFAULT 0x00000000 |
13376 | #define smnBIF_CFG_DEV0_EPF4_2_BASE_ADDR_4_DEFAULT 0x00000000 |
13377 | #define smnBIF_CFG_DEV0_EPF4_2_BASE_ADDR_5_DEFAULT 0x00000000 |
13378 | #define smnBIF_CFG_DEV0_EPF4_2_BASE_ADDR_6_DEFAULT 0x00000000 |
13379 | #define smnBIF_CFG_DEV0_EPF4_2_ADAPTER_ID_DEFAULT 0x00000000 |
13380 | #define smnBIF_CFG_DEV0_EPF4_2_ROM_BASE_ADDR_DEFAULT 0x00000000 |
13381 | #define smnBIF_CFG_DEV0_EPF4_2_CAP_PTR_DEFAULT 0x00000000 |
13382 | #define smnBIF_CFG_DEV0_EPF4_2_INTERRUPT_LINE_DEFAULT 0x00000000 |
13383 | #define smnBIF_CFG_DEV0_EPF4_2_INTERRUPT_PIN_DEFAULT 0x00000000 |
13384 | #define smnBIF_CFG_DEV0_EPF4_2_MIN_GRANT_DEFAULT 0x00000000 |
13385 | #define smnBIF_CFG_DEV0_EPF4_2_MAX_LATENCY_DEFAULT 0x00000000 |
13386 | #define smnBIF_CFG_DEV0_EPF4_2_VENDOR_CAP_LIST_DEFAULT 0x00000000 |
13387 | #define smnBIF_CFG_DEV0_EPF4_2_ADAPTER_ID_W_DEFAULT 0x00000000 |
13388 | #define smnBIF_CFG_DEV0_EPF4_2_PMI_CAP_LIST_DEFAULT 0x00000000 |
13389 | #define smnBIF_CFG_DEV0_EPF4_2_PMI_CAP_DEFAULT 0x00000000 |
13390 | #define smnBIF_CFG_DEV0_EPF4_2_PMI_STATUS_CNTL_DEFAULT 0x00000000 |
13391 | #define smnBIF_CFG_DEV0_EPF4_2_SBRN_DEFAULT 0x00000000 |
13392 | #define smnBIF_CFG_DEV0_EPF4_2_FLADJ_DEFAULT 0x00000020 |
13393 | #define smnBIF_CFG_DEV0_EPF4_2_DBESL_DBESLD_DEFAULT 0x00000000 |
13394 | #define smnBIF_CFG_DEV0_EPF4_2_PCIE_CAP_LIST_DEFAULT 0x0000a000 |
13395 | #define smnBIF_CFG_DEV0_EPF4_2_PCIE_CAP_DEFAULT 0x00000002 |
13396 | #define smnBIF_CFG_DEV0_EPF4_2_DEVICE_CAP_DEFAULT 0x10000000 |
13397 | #define smnBIF_CFG_DEV0_EPF4_2_DEVICE_CNTL_DEFAULT 0x00002810 |
13398 | #define smnBIF_CFG_DEV0_EPF4_2_DEVICE_STATUS_DEFAULT 0x00000000 |
13399 | #define smnBIF_CFG_DEV0_EPF4_2_LINK_CAP_DEFAULT 0x00011c03 |
13400 | #define smnBIF_CFG_DEV0_EPF4_2_LINK_CNTL_DEFAULT 0x00000000 |
13401 | #define smnBIF_CFG_DEV0_EPF4_2_LINK_STATUS_DEFAULT 0x00000001 |
13402 | #define smnBIF_CFG_DEV0_EPF4_2_DEVICE_CAP2_DEFAULT 0x00000000 |
13403 | #define smnBIF_CFG_DEV0_EPF4_2_DEVICE_CNTL2_DEFAULT 0x00000000 |
13404 | #define smnBIF_CFG_DEV0_EPF4_2_DEVICE_STATUS2_DEFAULT 0x00000000 |
13405 | #define smnBIF_CFG_DEV0_EPF4_2_LINK_CAP2_DEFAULT 0x0000000e |
13406 | #define smnBIF_CFG_DEV0_EPF4_2_LINK_CNTL2_DEFAULT 0x00000003 |
13407 | #define smnBIF_CFG_DEV0_EPF4_2_LINK_STATUS2_DEFAULT 0x00000000 |
13408 | #define smnBIF_CFG_DEV0_EPF4_2_SLOT_CAP2_DEFAULT 0x00000000 |
13409 | #define smnBIF_CFG_DEV0_EPF4_2_SLOT_CNTL2_DEFAULT 0x00000000 |
13410 | #define smnBIF_CFG_DEV0_EPF4_2_SLOT_STATUS2_DEFAULT 0x00000000 |
13411 | #define smnBIF_CFG_DEV0_EPF4_2_MSI_CAP_LIST_DEFAULT 0x0000c000 |
13412 | #define smnBIF_CFG_DEV0_EPF4_2_MSI_MSG_CNTL_DEFAULT 0x00000080 |
13413 | #define smnBIF_CFG_DEV0_EPF4_2_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 |
13414 | #define smnBIF_CFG_DEV0_EPF4_2_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 |
13415 | #define smnBIF_CFG_DEV0_EPF4_2_MSI_MSG_DATA_DEFAULT 0x00000000 |
13416 | #define smnBIF_CFG_DEV0_EPF4_2_MSI_MASK_DEFAULT 0x00000000 |
13417 | #define smnBIF_CFG_DEV0_EPF4_2_MSI_MSG_DATA_64_DEFAULT 0x00000000 |
13418 | #define smnBIF_CFG_DEV0_EPF4_2_MSI_MASK_64_DEFAULT 0x00000000 |
13419 | #define smnBIF_CFG_DEV0_EPF4_2_MSI_PENDING_DEFAULT 0x00000000 |
13420 | #define smnBIF_CFG_DEV0_EPF4_2_MSI_PENDING_64_DEFAULT 0x00000000 |
13421 | #define smnBIF_CFG_DEV0_EPF4_2_MSIX_CAP_LIST_DEFAULT 0x00000000 |
13422 | #define smnBIF_CFG_DEV0_EPF4_2_MSIX_MSG_CNTL_DEFAULT 0x00000000 |
13423 | #define smnBIF_CFG_DEV0_EPF4_2_MSIX_TABLE_DEFAULT 0x00000000 |
13424 | #define smnBIF_CFG_DEV0_EPF4_2_MSIX_PBA_DEFAULT 0x00000000 |
13425 | #define smnBIF_CFG_DEV0_EPF4_2_SATA_CAP_0_DEFAULT 0x00000000 |
13426 | #define smnBIF_CFG_DEV0_EPF4_2_SATA_CAP_1_DEFAULT 0x00000000 |
13427 | #define smnBIF_CFG_DEV0_EPF4_2_SATA_IDP_INDEX_DEFAULT 0x00000000 |
13428 | #define smnBIF_CFG_DEV0_EPF4_2_SATA_IDP_DATA_DEFAULT 0x00000000 |
13429 | #define smnBIF_CFG_DEV0_EPF4_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 |
13430 | #define smnBIF_CFG_DEV0_EPF4_2_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 |
13431 | #define smnBIF_CFG_DEV0_EPF4_2_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 |
13432 | #define smnBIF_CFG_DEV0_EPF4_2_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 |
13433 | #define smnBIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 |
13434 | #define smnBIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 |
13435 | #define smnBIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 |
13436 | #define smnBIF_CFG_DEV0_EPF4_2_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 |
13437 | #define smnBIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 |
13438 | #define smnBIF_CFG_DEV0_EPF4_2_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000 |
13439 | #define smnBIF_CFG_DEV0_EPF4_2_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 |
13440 | #define smnBIF_CFG_DEV0_EPF4_2_PCIE_HDR_LOG0_DEFAULT 0x00000000 |
13441 | #define smnBIF_CFG_DEV0_EPF4_2_PCIE_HDR_LOG1_DEFAULT 0x00000000 |
13442 | #define smnBIF_CFG_DEV0_EPF4_2_PCIE_HDR_LOG2_DEFAULT 0x00000000 |
13443 | #define smnBIF_CFG_DEV0_EPF4_2_PCIE_HDR_LOG3_DEFAULT 0x00000000 |
13444 | #define smnBIF_CFG_DEV0_EPF4_2_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 |
13445 | #define smnBIF_CFG_DEV0_EPF4_2_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 |
13446 | #define smnBIF_CFG_DEV0_EPF4_2_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 |
13447 | #define smnBIF_CFG_DEV0_EPF4_2_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 |
13448 | #define smnBIF_CFG_DEV0_EPF4_2_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000 |
13449 | #define smnBIF_CFG_DEV0_EPF4_2_PCIE_BAR1_CAP_DEFAULT 0x00000000 |
13450 | #define smnBIF_CFG_DEV0_EPF4_2_PCIE_BAR1_CNTL_DEFAULT 0x00000020 |
13451 | #define smnBIF_CFG_DEV0_EPF4_2_PCIE_BAR2_CAP_DEFAULT 0x00000000 |
13452 | #define smnBIF_CFG_DEV0_EPF4_2_PCIE_BAR2_CNTL_DEFAULT 0x00000000 |
13453 | #define smnBIF_CFG_DEV0_EPF4_2_PCIE_BAR3_CAP_DEFAULT 0x00000000 |
13454 | #define smnBIF_CFG_DEV0_EPF4_2_PCIE_BAR3_CNTL_DEFAULT 0x00000000 |
13455 | #define smnBIF_CFG_DEV0_EPF4_2_PCIE_BAR4_CAP_DEFAULT 0x00000000 |
13456 | #define smnBIF_CFG_DEV0_EPF4_2_PCIE_BAR4_CNTL_DEFAULT 0x00000000 |
13457 | #define smnBIF_CFG_DEV0_EPF4_2_PCIE_BAR5_CAP_DEFAULT 0x00000000 |
13458 | #define smnBIF_CFG_DEV0_EPF4_2_PCIE_BAR5_CNTL_DEFAULT 0x00000000 |
13459 | #define smnBIF_CFG_DEV0_EPF4_2_PCIE_BAR6_CAP_DEFAULT 0x00000000 |
13460 | #define smnBIF_CFG_DEV0_EPF4_2_PCIE_BAR6_CNTL_DEFAULT 0x00000000 |
13461 | #define smnBIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000 |
13462 | #define smnBIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000 |
13463 | #define smnBIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000 |
13464 | #define smnBIF_CFG_DEV0_EPF4_2_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000 |
13465 | #define smnBIF_CFG_DEV0_EPF4_2_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000 |
13466 | #define smnBIF_CFG_DEV0_EPF4_2_PCIE_DPA_CAP_DEFAULT 0x00000000 |
13467 | #define smnBIF_CFG_DEV0_EPF4_2_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000 |
13468 | #define smnBIF_CFG_DEV0_EPF4_2_PCIE_DPA_STATUS_DEFAULT 0x00000100 |
13469 | #define smnBIF_CFG_DEV0_EPF4_2_PCIE_DPA_CNTL_DEFAULT 0x00000000 |
13470 | #define smnBIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000 |
13471 | #define smnBIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000 |
13472 | #define smnBIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000 |
13473 | #define smnBIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000 |
13474 | #define smnBIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000 |
13475 | #define smnBIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000 |
13476 | #define smnBIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000 |
13477 | #define smnBIF_CFG_DEV0_EPF4_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000 |
13478 | #define smnBIF_CFG_DEV0_EPF4_2_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000 |
13479 | #define smnBIF_CFG_DEV0_EPF4_2_PCIE_ACS_CAP_DEFAULT 0x00000000 |
13480 | #define smnBIF_CFG_DEV0_EPF4_2_PCIE_ACS_CNTL_DEFAULT 0x00000000 |
13481 | #define smnBIF_CFG_DEV0_EPF4_2_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000 |
13482 | #define smnBIF_CFG_DEV0_EPF4_2_PCIE_ARI_CAP_DEFAULT 0x00000000 |
13483 | #define smnBIF_CFG_DEV0_EPF4_2_PCIE_ARI_CNTL_DEFAULT 0x00000000 |
13484 | |
13485 | |
13486 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf5_bifcfgdecp |
13487 | #define smnBIF_CFG_DEV0_EPF5_2_VENDOR_ID_DEFAULT 0x00000000 |
13488 | #define smnBIF_CFG_DEV0_EPF5_2_DEVICE_ID_DEFAULT 0x00000000 |
13489 | #define smnBIF_CFG_DEV0_EPF5_2_COMMAND_DEFAULT 0x00000000 |
13490 | #define smnBIF_CFG_DEV0_EPF5_2_STATUS_DEFAULT 0x00000000 |
13491 | #define smnBIF_CFG_DEV0_EPF5_2_REVISION_ID_DEFAULT 0x00000000 |
13492 | #define smnBIF_CFG_DEV0_EPF5_2_PROG_INTERFACE_DEFAULT 0x00000000 |
13493 | #define smnBIF_CFG_DEV0_EPF5_2_SUB_CLASS_DEFAULT 0x00000000 |
13494 | #define smnBIF_CFG_DEV0_EPF5_2_BASE_CLASS_DEFAULT 0x00000000 |
13495 | #define smnBIF_CFG_DEV0_EPF5_2_CACHE_LINE_DEFAULT 0x00000000 |
13496 | #define smnBIF_CFG_DEV0_EPF5_2_LATENCY_DEFAULT 0x00000000 |
13497 | #define 0x00000000 |
13498 | #define smnBIF_CFG_DEV0_EPF5_2_BIST_DEFAULT 0x00000000 |
13499 | #define smnBIF_CFG_DEV0_EPF5_2_BASE_ADDR_1_DEFAULT 0x00000000 |
13500 | #define smnBIF_CFG_DEV0_EPF5_2_BASE_ADDR_2_DEFAULT 0x00000000 |
13501 | #define smnBIF_CFG_DEV0_EPF5_2_BASE_ADDR_3_DEFAULT 0x00000000 |
13502 | #define smnBIF_CFG_DEV0_EPF5_2_BASE_ADDR_4_DEFAULT 0x00000000 |
13503 | #define smnBIF_CFG_DEV0_EPF5_2_BASE_ADDR_5_DEFAULT 0x00000000 |
13504 | #define smnBIF_CFG_DEV0_EPF5_2_BASE_ADDR_6_DEFAULT 0x00000000 |
13505 | #define smnBIF_CFG_DEV0_EPF5_2_ADAPTER_ID_DEFAULT 0x00000000 |
13506 | #define smnBIF_CFG_DEV0_EPF5_2_ROM_BASE_ADDR_DEFAULT 0x00000000 |
13507 | #define smnBIF_CFG_DEV0_EPF5_2_CAP_PTR_DEFAULT 0x00000000 |
13508 | #define smnBIF_CFG_DEV0_EPF5_2_INTERRUPT_LINE_DEFAULT 0x00000000 |
13509 | #define smnBIF_CFG_DEV0_EPF5_2_INTERRUPT_PIN_DEFAULT 0x00000000 |
13510 | #define smnBIF_CFG_DEV0_EPF5_2_MIN_GRANT_DEFAULT 0x00000000 |
13511 | #define smnBIF_CFG_DEV0_EPF5_2_MAX_LATENCY_DEFAULT 0x00000000 |
13512 | #define smnBIF_CFG_DEV0_EPF5_2_VENDOR_CAP_LIST_DEFAULT 0x00000000 |
13513 | #define smnBIF_CFG_DEV0_EPF5_2_ADAPTER_ID_W_DEFAULT 0x00000000 |
13514 | #define smnBIF_CFG_DEV0_EPF5_2_PMI_CAP_LIST_DEFAULT 0x00000000 |
13515 | #define smnBIF_CFG_DEV0_EPF5_2_PMI_CAP_DEFAULT 0x00000000 |
13516 | #define smnBIF_CFG_DEV0_EPF5_2_PMI_STATUS_CNTL_DEFAULT 0x00000000 |
13517 | #define smnBIF_CFG_DEV0_EPF5_2_SBRN_DEFAULT 0x00000000 |
13518 | #define smnBIF_CFG_DEV0_EPF5_2_FLADJ_DEFAULT 0x00000020 |
13519 | #define smnBIF_CFG_DEV0_EPF5_2_DBESL_DBESLD_DEFAULT 0x00000000 |
13520 | #define smnBIF_CFG_DEV0_EPF5_2_PCIE_CAP_LIST_DEFAULT 0x0000a000 |
13521 | #define smnBIF_CFG_DEV0_EPF5_2_PCIE_CAP_DEFAULT 0x00000002 |
13522 | #define smnBIF_CFG_DEV0_EPF5_2_DEVICE_CAP_DEFAULT 0x10000000 |
13523 | #define smnBIF_CFG_DEV0_EPF5_2_DEVICE_CNTL_DEFAULT 0x00002810 |
13524 | #define smnBIF_CFG_DEV0_EPF5_2_DEVICE_STATUS_DEFAULT 0x00000000 |
13525 | #define smnBIF_CFG_DEV0_EPF5_2_LINK_CAP_DEFAULT 0x00011c03 |
13526 | #define smnBIF_CFG_DEV0_EPF5_2_LINK_CNTL_DEFAULT 0x00000000 |
13527 | #define smnBIF_CFG_DEV0_EPF5_2_LINK_STATUS_DEFAULT 0x00000001 |
13528 | #define smnBIF_CFG_DEV0_EPF5_2_DEVICE_CAP2_DEFAULT 0x00000000 |
13529 | #define smnBIF_CFG_DEV0_EPF5_2_DEVICE_CNTL2_DEFAULT 0x00000000 |
13530 | #define smnBIF_CFG_DEV0_EPF5_2_DEVICE_STATUS2_DEFAULT 0x00000000 |
13531 | #define smnBIF_CFG_DEV0_EPF5_2_LINK_CAP2_DEFAULT 0x0000000e |
13532 | #define smnBIF_CFG_DEV0_EPF5_2_LINK_CNTL2_DEFAULT 0x00000003 |
13533 | #define smnBIF_CFG_DEV0_EPF5_2_LINK_STATUS2_DEFAULT 0x00000000 |
13534 | #define smnBIF_CFG_DEV0_EPF5_2_SLOT_CAP2_DEFAULT 0x00000000 |
13535 | #define smnBIF_CFG_DEV0_EPF5_2_SLOT_CNTL2_DEFAULT 0x00000000 |
13536 | #define smnBIF_CFG_DEV0_EPF5_2_SLOT_STATUS2_DEFAULT 0x00000000 |
13537 | #define smnBIF_CFG_DEV0_EPF5_2_MSI_CAP_LIST_DEFAULT 0x0000c000 |
13538 | #define smnBIF_CFG_DEV0_EPF5_2_MSI_MSG_CNTL_DEFAULT 0x00000080 |
13539 | #define smnBIF_CFG_DEV0_EPF5_2_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 |
13540 | #define smnBIF_CFG_DEV0_EPF5_2_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 |
13541 | #define smnBIF_CFG_DEV0_EPF5_2_MSI_MSG_DATA_DEFAULT 0x00000000 |
13542 | #define smnBIF_CFG_DEV0_EPF5_2_MSI_MASK_DEFAULT 0x00000000 |
13543 | #define smnBIF_CFG_DEV0_EPF5_2_MSI_MSG_DATA_64_DEFAULT 0x00000000 |
13544 | #define smnBIF_CFG_DEV0_EPF5_2_MSI_MASK_64_DEFAULT 0x00000000 |
13545 | #define smnBIF_CFG_DEV0_EPF5_2_MSI_PENDING_DEFAULT 0x00000000 |
13546 | #define smnBIF_CFG_DEV0_EPF5_2_MSI_PENDING_64_DEFAULT 0x00000000 |
13547 | #define smnBIF_CFG_DEV0_EPF5_2_MSIX_CAP_LIST_DEFAULT 0x00000000 |
13548 | #define smnBIF_CFG_DEV0_EPF5_2_MSIX_MSG_CNTL_DEFAULT 0x00000000 |
13549 | #define smnBIF_CFG_DEV0_EPF5_2_MSIX_TABLE_DEFAULT 0x00000000 |
13550 | #define smnBIF_CFG_DEV0_EPF5_2_MSIX_PBA_DEFAULT 0x00000000 |
13551 | #define smnBIF_CFG_DEV0_EPF5_2_SATA_CAP_0_DEFAULT 0x00000000 |
13552 | #define smnBIF_CFG_DEV0_EPF5_2_SATA_CAP_1_DEFAULT 0x00000000 |
13553 | #define smnBIF_CFG_DEV0_EPF5_2_SATA_IDP_INDEX_DEFAULT 0x00000000 |
13554 | #define smnBIF_CFG_DEV0_EPF5_2_SATA_IDP_DATA_DEFAULT 0x00000000 |
13555 | #define smnBIF_CFG_DEV0_EPF5_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 |
13556 | #define smnBIF_CFG_DEV0_EPF5_2_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 |
13557 | #define smnBIF_CFG_DEV0_EPF5_2_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 |
13558 | #define smnBIF_CFG_DEV0_EPF5_2_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 |
13559 | #define smnBIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 |
13560 | #define smnBIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 |
13561 | #define smnBIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 |
13562 | #define smnBIF_CFG_DEV0_EPF5_2_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 |
13563 | #define smnBIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 |
13564 | #define smnBIF_CFG_DEV0_EPF5_2_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000 |
13565 | #define smnBIF_CFG_DEV0_EPF5_2_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 |
13566 | #define smnBIF_CFG_DEV0_EPF5_2_PCIE_HDR_LOG0_DEFAULT 0x00000000 |
13567 | #define smnBIF_CFG_DEV0_EPF5_2_PCIE_HDR_LOG1_DEFAULT 0x00000000 |
13568 | #define smnBIF_CFG_DEV0_EPF5_2_PCIE_HDR_LOG2_DEFAULT 0x00000000 |
13569 | #define smnBIF_CFG_DEV0_EPF5_2_PCIE_HDR_LOG3_DEFAULT 0x00000000 |
13570 | #define smnBIF_CFG_DEV0_EPF5_2_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 |
13571 | #define smnBIF_CFG_DEV0_EPF5_2_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 |
13572 | #define smnBIF_CFG_DEV0_EPF5_2_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 |
13573 | #define smnBIF_CFG_DEV0_EPF5_2_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 |
13574 | #define smnBIF_CFG_DEV0_EPF5_2_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000 |
13575 | #define smnBIF_CFG_DEV0_EPF5_2_PCIE_BAR1_CAP_DEFAULT 0x00000000 |
13576 | #define smnBIF_CFG_DEV0_EPF5_2_PCIE_BAR1_CNTL_DEFAULT 0x00000020 |
13577 | #define smnBIF_CFG_DEV0_EPF5_2_PCIE_BAR2_CAP_DEFAULT 0x00000000 |
13578 | #define smnBIF_CFG_DEV0_EPF5_2_PCIE_BAR2_CNTL_DEFAULT 0x00000000 |
13579 | #define smnBIF_CFG_DEV0_EPF5_2_PCIE_BAR3_CAP_DEFAULT 0x00000000 |
13580 | #define smnBIF_CFG_DEV0_EPF5_2_PCIE_BAR3_CNTL_DEFAULT 0x00000000 |
13581 | #define smnBIF_CFG_DEV0_EPF5_2_PCIE_BAR4_CAP_DEFAULT 0x00000000 |
13582 | #define smnBIF_CFG_DEV0_EPF5_2_PCIE_BAR4_CNTL_DEFAULT 0x00000000 |
13583 | #define smnBIF_CFG_DEV0_EPF5_2_PCIE_BAR5_CAP_DEFAULT 0x00000000 |
13584 | #define smnBIF_CFG_DEV0_EPF5_2_PCIE_BAR5_CNTL_DEFAULT 0x00000000 |
13585 | #define smnBIF_CFG_DEV0_EPF5_2_PCIE_BAR6_CAP_DEFAULT 0x00000000 |
13586 | #define smnBIF_CFG_DEV0_EPF5_2_PCIE_BAR6_CNTL_DEFAULT 0x00000000 |
13587 | #define smnBIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000 |
13588 | #define smnBIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000 |
13589 | #define smnBIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000 |
13590 | #define smnBIF_CFG_DEV0_EPF5_2_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000 |
13591 | #define smnBIF_CFG_DEV0_EPF5_2_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000 |
13592 | #define smnBIF_CFG_DEV0_EPF5_2_PCIE_DPA_CAP_DEFAULT 0x00000000 |
13593 | #define smnBIF_CFG_DEV0_EPF5_2_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000 |
13594 | #define smnBIF_CFG_DEV0_EPF5_2_PCIE_DPA_STATUS_DEFAULT 0x00000100 |
13595 | #define smnBIF_CFG_DEV0_EPF5_2_PCIE_DPA_CNTL_DEFAULT 0x00000000 |
13596 | #define smnBIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000 |
13597 | #define smnBIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000 |
13598 | #define smnBIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000 |
13599 | #define smnBIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000 |
13600 | #define smnBIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000 |
13601 | #define smnBIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000 |
13602 | #define smnBIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000 |
13603 | #define smnBIF_CFG_DEV0_EPF5_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000 |
13604 | #define smnBIF_CFG_DEV0_EPF5_2_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000 |
13605 | #define smnBIF_CFG_DEV0_EPF5_2_PCIE_ACS_CAP_DEFAULT 0x00000000 |
13606 | #define smnBIF_CFG_DEV0_EPF5_2_PCIE_ACS_CNTL_DEFAULT 0x00000000 |
13607 | #define smnBIF_CFG_DEV0_EPF5_2_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000 |
13608 | #define smnBIF_CFG_DEV0_EPF5_2_PCIE_ARI_CAP_DEFAULT 0x00000000 |
13609 | #define smnBIF_CFG_DEV0_EPF5_2_PCIE_ARI_CNTL_DEFAULT 0x00000000 |
13610 | |
13611 | |
13612 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf6_bifcfgdecp |
13613 | #define smnBIF_CFG_DEV0_EPF6_2_VENDOR_ID_DEFAULT 0x00000000 |
13614 | #define smnBIF_CFG_DEV0_EPF6_2_DEVICE_ID_DEFAULT 0x00000000 |
13615 | #define smnBIF_CFG_DEV0_EPF6_2_COMMAND_DEFAULT 0x00000000 |
13616 | #define smnBIF_CFG_DEV0_EPF6_2_STATUS_DEFAULT 0x00000000 |
13617 | #define smnBIF_CFG_DEV0_EPF6_2_REVISION_ID_DEFAULT 0x00000000 |
13618 | #define smnBIF_CFG_DEV0_EPF6_2_PROG_INTERFACE_DEFAULT 0x00000000 |
13619 | #define smnBIF_CFG_DEV0_EPF6_2_SUB_CLASS_DEFAULT 0x00000000 |
13620 | #define smnBIF_CFG_DEV0_EPF6_2_BASE_CLASS_DEFAULT 0x00000000 |
13621 | #define smnBIF_CFG_DEV0_EPF6_2_CACHE_LINE_DEFAULT 0x00000000 |
13622 | #define smnBIF_CFG_DEV0_EPF6_2_LATENCY_DEFAULT 0x00000000 |
13623 | #define 0x00000000 |
13624 | #define smnBIF_CFG_DEV0_EPF6_2_BIST_DEFAULT 0x00000000 |
13625 | #define smnBIF_CFG_DEV0_EPF6_2_BASE_ADDR_1_DEFAULT 0x00000000 |
13626 | #define smnBIF_CFG_DEV0_EPF6_2_BASE_ADDR_2_DEFAULT 0x00000000 |
13627 | #define smnBIF_CFG_DEV0_EPF6_2_BASE_ADDR_3_DEFAULT 0x00000000 |
13628 | #define smnBIF_CFG_DEV0_EPF6_2_BASE_ADDR_4_DEFAULT 0x00000000 |
13629 | #define smnBIF_CFG_DEV0_EPF6_2_BASE_ADDR_5_DEFAULT 0x00000000 |
13630 | #define smnBIF_CFG_DEV0_EPF6_2_BASE_ADDR_6_DEFAULT 0x00000000 |
13631 | #define smnBIF_CFG_DEV0_EPF6_2_ADAPTER_ID_DEFAULT 0x00000000 |
13632 | #define smnBIF_CFG_DEV0_EPF6_2_ROM_BASE_ADDR_DEFAULT 0x00000000 |
13633 | #define smnBIF_CFG_DEV0_EPF6_2_CAP_PTR_DEFAULT 0x00000000 |
13634 | #define smnBIF_CFG_DEV0_EPF6_2_INTERRUPT_LINE_DEFAULT 0x00000000 |
13635 | #define smnBIF_CFG_DEV0_EPF6_2_INTERRUPT_PIN_DEFAULT 0x00000000 |
13636 | #define smnBIF_CFG_DEV0_EPF6_2_MIN_GRANT_DEFAULT 0x00000000 |
13637 | #define smnBIF_CFG_DEV0_EPF6_2_MAX_LATENCY_DEFAULT 0x00000000 |
13638 | #define smnBIF_CFG_DEV0_EPF6_2_VENDOR_CAP_LIST_DEFAULT 0x00000000 |
13639 | #define smnBIF_CFG_DEV0_EPF6_2_ADAPTER_ID_W_DEFAULT 0x00000000 |
13640 | #define smnBIF_CFG_DEV0_EPF6_2_PMI_CAP_LIST_DEFAULT 0x00000000 |
13641 | #define smnBIF_CFG_DEV0_EPF6_2_PMI_CAP_DEFAULT 0x00000000 |
13642 | #define smnBIF_CFG_DEV0_EPF6_2_PMI_STATUS_CNTL_DEFAULT 0x00000000 |
13643 | #define smnBIF_CFG_DEV0_EPF6_2_SBRN_DEFAULT 0x00000000 |
13644 | #define smnBIF_CFG_DEV0_EPF6_2_FLADJ_DEFAULT 0x00000020 |
13645 | #define smnBIF_CFG_DEV0_EPF6_2_DBESL_DBESLD_DEFAULT 0x00000000 |
13646 | #define smnBIF_CFG_DEV0_EPF6_2_PCIE_CAP_LIST_DEFAULT 0x0000a000 |
13647 | #define smnBIF_CFG_DEV0_EPF6_2_PCIE_CAP_DEFAULT 0x00000002 |
13648 | #define smnBIF_CFG_DEV0_EPF6_2_DEVICE_CAP_DEFAULT 0x10000000 |
13649 | #define smnBIF_CFG_DEV0_EPF6_2_DEVICE_CNTL_DEFAULT 0x00002810 |
13650 | #define smnBIF_CFG_DEV0_EPF6_2_DEVICE_STATUS_DEFAULT 0x00000000 |
13651 | #define smnBIF_CFG_DEV0_EPF6_2_LINK_CAP_DEFAULT 0x00011c03 |
13652 | #define smnBIF_CFG_DEV0_EPF6_2_LINK_CNTL_DEFAULT 0x00000000 |
13653 | #define smnBIF_CFG_DEV0_EPF6_2_LINK_STATUS_DEFAULT 0x00000001 |
13654 | #define smnBIF_CFG_DEV0_EPF6_2_DEVICE_CAP2_DEFAULT 0x00000000 |
13655 | #define smnBIF_CFG_DEV0_EPF6_2_DEVICE_CNTL2_DEFAULT 0x00000000 |
13656 | #define smnBIF_CFG_DEV0_EPF6_2_DEVICE_STATUS2_DEFAULT 0x00000000 |
13657 | #define smnBIF_CFG_DEV0_EPF6_2_LINK_CAP2_DEFAULT 0x0000000e |
13658 | #define smnBIF_CFG_DEV0_EPF6_2_LINK_CNTL2_DEFAULT 0x00000003 |
13659 | #define smnBIF_CFG_DEV0_EPF6_2_LINK_STATUS2_DEFAULT 0x00000000 |
13660 | #define smnBIF_CFG_DEV0_EPF6_2_SLOT_CAP2_DEFAULT 0x00000000 |
13661 | #define smnBIF_CFG_DEV0_EPF6_2_SLOT_CNTL2_DEFAULT 0x00000000 |
13662 | #define smnBIF_CFG_DEV0_EPF6_2_SLOT_STATUS2_DEFAULT 0x00000000 |
13663 | #define smnBIF_CFG_DEV0_EPF6_2_MSI_CAP_LIST_DEFAULT 0x0000c000 |
13664 | #define smnBIF_CFG_DEV0_EPF6_2_MSI_MSG_CNTL_DEFAULT 0x00000080 |
13665 | #define smnBIF_CFG_DEV0_EPF6_2_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 |
13666 | #define smnBIF_CFG_DEV0_EPF6_2_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 |
13667 | #define smnBIF_CFG_DEV0_EPF6_2_MSI_MSG_DATA_DEFAULT 0x00000000 |
13668 | #define smnBIF_CFG_DEV0_EPF6_2_MSI_MASK_DEFAULT 0x00000000 |
13669 | #define smnBIF_CFG_DEV0_EPF6_2_MSI_MSG_DATA_64_DEFAULT 0x00000000 |
13670 | #define smnBIF_CFG_DEV0_EPF6_2_MSI_MASK_64_DEFAULT 0x00000000 |
13671 | #define smnBIF_CFG_DEV0_EPF6_2_MSI_PENDING_DEFAULT 0x00000000 |
13672 | #define smnBIF_CFG_DEV0_EPF6_2_MSI_PENDING_64_DEFAULT 0x00000000 |
13673 | #define smnBIF_CFG_DEV0_EPF6_2_MSIX_CAP_LIST_DEFAULT 0x00000000 |
13674 | #define smnBIF_CFG_DEV0_EPF6_2_MSIX_MSG_CNTL_DEFAULT 0x00000000 |
13675 | #define smnBIF_CFG_DEV0_EPF6_2_MSIX_TABLE_DEFAULT 0x00000000 |
13676 | #define smnBIF_CFG_DEV0_EPF6_2_MSIX_PBA_DEFAULT 0x00000000 |
13677 | #define smnBIF_CFG_DEV0_EPF6_2_SATA_CAP_0_DEFAULT 0x00000000 |
13678 | #define smnBIF_CFG_DEV0_EPF6_2_SATA_CAP_1_DEFAULT 0x00000000 |
13679 | #define smnBIF_CFG_DEV0_EPF6_2_SATA_IDP_INDEX_DEFAULT 0x00000000 |
13680 | #define smnBIF_CFG_DEV0_EPF6_2_SATA_IDP_DATA_DEFAULT 0x00000000 |
13681 | #define smnBIF_CFG_DEV0_EPF6_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 |
13682 | #define smnBIF_CFG_DEV0_EPF6_2_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 |
13683 | #define smnBIF_CFG_DEV0_EPF6_2_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 |
13684 | #define smnBIF_CFG_DEV0_EPF6_2_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 |
13685 | #define smnBIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 |
13686 | #define smnBIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 |
13687 | #define smnBIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 |
13688 | #define smnBIF_CFG_DEV0_EPF6_2_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 |
13689 | #define smnBIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 |
13690 | #define smnBIF_CFG_DEV0_EPF6_2_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000 |
13691 | #define smnBIF_CFG_DEV0_EPF6_2_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 |
13692 | #define smnBIF_CFG_DEV0_EPF6_2_PCIE_HDR_LOG0_DEFAULT 0x00000000 |
13693 | #define smnBIF_CFG_DEV0_EPF6_2_PCIE_HDR_LOG1_DEFAULT 0x00000000 |
13694 | #define smnBIF_CFG_DEV0_EPF6_2_PCIE_HDR_LOG2_DEFAULT 0x00000000 |
13695 | #define smnBIF_CFG_DEV0_EPF6_2_PCIE_HDR_LOG3_DEFAULT 0x00000000 |
13696 | #define smnBIF_CFG_DEV0_EPF6_2_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 |
13697 | #define smnBIF_CFG_DEV0_EPF6_2_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 |
13698 | #define smnBIF_CFG_DEV0_EPF6_2_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 |
13699 | #define smnBIF_CFG_DEV0_EPF6_2_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 |
13700 | #define smnBIF_CFG_DEV0_EPF6_2_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000 |
13701 | #define smnBIF_CFG_DEV0_EPF6_2_PCIE_BAR1_CAP_DEFAULT 0x00000000 |
13702 | #define smnBIF_CFG_DEV0_EPF6_2_PCIE_BAR1_CNTL_DEFAULT 0x00000020 |
13703 | #define smnBIF_CFG_DEV0_EPF6_2_PCIE_BAR2_CAP_DEFAULT 0x00000000 |
13704 | #define smnBIF_CFG_DEV0_EPF6_2_PCIE_BAR2_CNTL_DEFAULT 0x00000000 |
13705 | #define smnBIF_CFG_DEV0_EPF6_2_PCIE_BAR3_CAP_DEFAULT 0x00000000 |
13706 | #define smnBIF_CFG_DEV0_EPF6_2_PCIE_BAR3_CNTL_DEFAULT 0x00000000 |
13707 | #define smnBIF_CFG_DEV0_EPF6_2_PCIE_BAR4_CAP_DEFAULT 0x00000000 |
13708 | #define smnBIF_CFG_DEV0_EPF6_2_PCIE_BAR4_CNTL_DEFAULT 0x00000000 |
13709 | #define smnBIF_CFG_DEV0_EPF6_2_PCIE_BAR5_CAP_DEFAULT 0x00000000 |
13710 | #define smnBIF_CFG_DEV0_EPF6_2_PCIE_BAR5_CNTL_DEFAULT 0x00000000 |
13711 | #define smnBIF_CFG_DEV0_EPF6_2_PCIE_BAR6_CAP_DEFAULT 0x00000000 |
13712 | #define smnBIF_CFG_DEV0_EPF6_2_PCIE_BAR6_CNTL_DEFAULT 0x00000000 |
13713 | #define smnBIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000 |
13714 | #define smnBIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000 |
13715 | #define smnBIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000 |
13716 | #define smnBIF_CFG_DEV0_EPF6_2_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000 |
13717 | #define smnBIF_CFG_DEV0_EPF6_2_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000 |
13718 | #define smnBIF_CFG_DEV0_EPF6_2_PCIE_DPA_CAP_DEFAULT 0x00000000 |
13719 | #define smnBIF_CFG_DEV0_EPF6_2_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000 |
13720 | #define smnBIF_CFG_DEV0_EPF6_2_PCIE_DPA_STATUS_DEFAULT 0x00000100 |
13721 | #define smnBIF_CFG_DEV0_EPF6_2_PCIE_DPA_CNTL_DEFAULT 0x00000000 |
13722 | #define smnBIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000 |
13723 | #define smnBIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000 |
13724 | #define smnBIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000 |
13725 | #define smnBIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000 |
13726 | #define smnBIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000 |
13727 | #define smnBIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000 |
13728 | #define smnBIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000 |
13729 | #define smnBIF_CFG_DEV0_EPF6_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000 |
13730 | #define smnBIF_CFG_DEV0_EPF6_2_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000 |
13731 | #define smnBIF_CFG_DEV0_EPF6_2_PCIE_ACS_CAP_DEFAULT 0x00000000 |
13732 | #define smnBIF_CFG_DEV0_EPF6_2_PCIE_ACS_CNTL_DEFAULT 0x00000000 |
13733 | #define smnBIF_CFG_DEV0_EPF6_2_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000 |
13734 | #define smnBIF_CFG_DEV0_EPF6_2_PCIE_ARI_CAP_DEFAULT 0x00000000 |
13735 | #define smnBIF_CFG_DEV0_EPF6_2_PCIE_ARI_CNTL_DEFAULT 0x00000000 |
13736 | |
13737 | |
13738 | // addressBlock: nbio_nbif0_bif_cfg_dev0_epf7_bifcfgdecp |
13739 | #define smnBIF_CFG_DEV0_EPF7_2_VENDOR_ID_DEFAULT 0x00000000 |
13740 | #define smnBIF_CFG_DEV0_EPF7_2_DEVICE_ID_DEFAULT 0x00000000 |
13741 | #define smnBIF_CFG_DEV0_EPF7_2_COMMAND_DEFAULT 0x00000000 |
13742 | #define smnBIF_CFG_DEV0_EPF7_2_STATUS_DEFAULT 0x00000000 |
13743 | #define smnBIF_CFG_DEV0_EPF7_2_REVISION_ID_DEFAULT 0x00000000 |
13744 | #define smnBIF_CFG_DEV0_EPF7_2_PROG_INTERFACE_DEFAULT 0x00000000 |
13745 | #define smnBIF_CFG_DEV0_EPF7_2_SUB_CLASS_DEFAULT 0x00000000 |
13746 | #define smnBIF_CFG_DEV0_EPF7_2_BASE_CLASS_DEFAULT 0x00000000 |
13747 | #define smnBIF_CFG_DEV0_EPF7_2_CACHE_LINE_DEFAULT 0x00000000 |
13748 | #define smnBIF_CFG_DEV0_EPF7_2_LATENCY_DEFAULT 0x00000000 |
13749 | #define 0x00000000 |
13750 | #define smnBIF_CFG_DEV0_EPF7_2_BIST_DEFAULT 0x00000000 |
13751 | #define smnBIF_CFG_DEV0_EPF7_2_BASE_ADDR_1_DEFAULT 0x00000000 |
13752 | #define smnBIF_CFG_DEV0_EPF7_2_BASE_ADDR_2_DEFAULT 0x00000000 |
13753 | #define smnBIF_CFG_DEV0_EPF7_2_BASE_ADDR_3_DEFAULT 0x00000000 |
13754 | #define smnBIF_CFG_DEV0_EPF7_2_BASE_ADDR_4_DEFAULT 0x00000000 |
13755 | #define smnBIF_CFG_DEV0_EPF7_2_BASE_ADDR_5_DEFAULT 0x00000000 |
13756 | #define smnBIF_CFG_DEV0_EPF7_2_BASE_ADDR_6_DEFAULT 0x00000000 |
13757 | #define smnBIF_CFG_DEV0_EPF7_2_ADAPTER_ID_DEFAULT 0x00000000 |
13758 | #define smnBIF_CFG_DEV0_EPF7_2_ROM_BASE_ADDR_DEFAULT 0x00000000 |
13759 | #define smnBIF_CFG_DEV0_EPF7_2_CAP_PTR_DEFAULT 0x00000000 |
13760 | #define smnBIF_CFG_DEV0_EPF7_2_INTERRUPT_LINE_DEFAULT 0x00000000 |
13761 | #define smnBIF_CFG_DEV0_EPF7_2_INTERRUPT_PIN_DEFAULT 0x00000000 |
13762 | #define smnBIF_CFG_DEV0_EPF7_2_MIN_GRANT_DEFAULT 0x00000000 |
13763 | #define smnBIF_CFG_DEV0_EPF7_2_MAX_LATENCY_DEFAULT 0x00000000 |
13764 | #define smnBIF_CFG_DEV0_EPF7_2_VENDOR_CAP_LIST_DEFAULT 0x00000000 |
13765 | #define smnBIF_CFG_DEV0_EPF7_2_ADAPTER_ID_W_DEFAULT 0x00000000 |
13766 | #define smnBIF_CFG_DEV0_EPF7_2_PMI_CAP_LIST_DEFAULT 0x00000000 |
13767 | #define smnBIF_CFG_DEV0_EPF7_2_PMI_CAP_DEFAULT 0x00000000 |
13768 | #define smnBIF_CFG_DEV0_EPF7_2_PMI_STATUS_CNTL_DEFAULT 0x00000000 |
13769 | #define smnBIF_CFG_DEV0_EPF7_2_SBRN_DEFAULT 0x00000000 |
13770 | #define smnBIF_CFG_DEV0_EPF7_2_FLADJ_DEFAULT 0x00000020 |
13771 | #define smnBIF_CFG_DEV0_EPF7_2_DBESL_DBESLD_DEFAULT 0x00000000 |
13772 | #define smnBIF_CFG_DEV0_EPF7_2_PCIE_CAP_LIST_DEFAULT 0x0000a000 |
13773 | #define smnBIF_CFG_DEV0_EPF7_2_PCIE_CAP_DEFAULT 0x00000002 |
13774 | #define smnBIF_CFG_DEV0_EPF7_2_DEVICE_CAP_DEFAULT 0x10000000 |
13775 | #define smnBIF_CFG_DEV0_EPF7_2_DEVICE_CNTL_DEFAULT 0x00002810 |
13776 | #define smnBIF_CFG_DEV0_EPF7_2_DEVICE_STATUS_DEFAULT 0x00000000 |
13777 | #define smnBIF_CFG_DEV0_EPF7_2_LINK_CAP_DEFAULT 0x00011c03 |
13778 | #define smnBIF_CFG_DEV0_EPF7_2_LINK_CNTL_DEFAULT 0x00000000 |
13779 | #define smnBIF_CFG_DEV0_EPF7_2_LINK_STATUS_DEFAULT 0x00000001 |
13780 | #define smnBIF_CFG_DEV0_EPF7_2_DEVICE_CAP2_DEFAULT 0x00000000 |
13781 | #define smnBIF_CFG_DEV0_EPF7_2_DEVICE_CNTL2_DEFAULT 0x00000000 |
13782 | #define smnBIF_CFG_DEV0_EPF7_2_DEVICE_STATUS2_DEFAULT 0x00000000 |
13783 | #define smnBIF_CFG_DEV0_EPF7_2_LINK_CAP2_DEFAULT 0x0000000e |
13784 | #define smnBIF_CFG_DEV0_EPF7_2_LINK_CNTL2_DEFAULT 0x00000003 |
13785 | #define smnBIF_CFG_DEV0_EPF7_2_LINK_STATUS2_DEFAULT 0x00000000 |
13786 | #define smnBIF_CFG_DEV0_EPF7_2_SLOT_CAP2_DEFAULT 0x00000000 |
13787 | #define smnBIF_CFG_DEV0_EPF7_2_SLOT_CNTL2_DEFAULT 0x00000000 |
13788 | #define smnBIF_CFG_DEV0_EPF7_2_SLOT_STATUS2_DEFAULT 0x00000000 |
13789 | #define smnBIF_CFG_DEV0_EPF7_2_MSI_CAP_LIST_DEFAULT 0x0000c000 |
13790 | #define smnBIF_CFG_DEV0_EPF7_2_MSI_MSG_CNTL_DEFAULT 0x00000080 |
13791 | #define smnBIF_CFG_DEV0_EPF7_2_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 |
13792 | #define smnBIF_CFG_DEV0_EPF7_2_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 |
13793 | #define smnBIF_CFG_DEV0_EPF7_2_MSI_MSG_DATA_DEFAULT 0x00000000 |
13794 | #define smnBIF_CFG_DEV0_EPF7_2_MSI_MASK_DEFAULT 0x00000000 |
13795 | #define smnBIF_CFG_DEV0_EPF7_2_MSI_MSG_DATA_64_DEFAULT 0x00000000 |
13796 | #define smnBIF_CFG_DEV0_EPF7_2_MSI_MASK_64_DEFAULT 0x00000000 |
13797 | #define smnBIF_CFG_DEV0_EPF7_2_MSI_PENDING_DEFAULT 0x00000000 |
13798 | #define smnBIF_CFG_DEV0_EPF7_2_MSI_PENDING_64_DEFAULT 0x00000000 |
13799 | #define smnBIF_CFG_DEV0_EPF7_2_MSIX_CAP_LIST_DEFAULT 0x00000000 |
13800 | #define smnBIF_CFG_DEV0_EPF7_2_MSIX_MSG_CNTL_DEFAULT 0x00000000 |
13801 | #define smnBIF_CFG_DEV0_EPF7_2_MSIX_TABLE_DEFAULT 0x00000000 |
13802 | #define smnBIF_CFG_DEV0_EPF7_2_MSIX_PBA_DEFAULT 0x00000000 |
13803 | #define smnBIF_CFG_DEV0_EPF7_2_SATA_CAP_0_DEFAULT 0x00000000 |
13804 | #define smnBIF_CFG_DEV0_EPF7_2_SATA_CAP_1_DEFAULT 0x00000000 |
13805 | #define smnBIF_CFG_DEV0_EPF7_2_SATA_IDP_INDEX_DEFAULT 0x00000000 |
13806 | #define smnBIF_CFG_DEV0_EPF7_2_SATA_IDP_DATA_DEFAULT 0x00000000 |
13807 | #define smnBIF_CFG_DEV0_EPF7_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 |
13808 | #define smnBIF_CFG_DEV0_EPF7_2_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 |
13809 | #define smnBIF_CFG_DEV0_EPF7_2_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 |
13810 | #define smnBIF_CFG_DEV0_EPF7_2_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 |
13811 | #define smnBIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 |
13812 | #define smnBIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 |
13813 | #define smnBIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 |
13814 | #define smnBIF_CFG_DEV0_EPF7_2_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 |
13815 | #define smnBIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 |
13816 | #define smnBIF_CFG_DEV0_EPF7_2_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000 |
13817 | #define smnBIF_CFG_DEV0_EPF7_2_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 |
13818 | #define smnBIF_CFG_DEV0_EPF7_2_PCIE_HDR_LOG0_DEFAULT 0x00000000 |
13819 | #define smnBIF_CFG_DEV0_EPF7_2_PCIE_HDR_LOG1_DEFAULT 0x00000000 |
13820 | #define smnBIF_CFG_DEV0_EPF7_2_PCIE_HDR_LOG2_DEFAULT 0x00000000 |
13821 | #define smnBIF_CFG_DEV0_EPF7_2_PCIE_HDR_LOG3_DEFAULT 0x00000000 |
13822 | #define smnBIF_CFG_DEV0_EPF7_2_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 |
13823 | #define smnBIF_CFG_DEV0_EPF7_2_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 |
13824 | #define smnBIF_CFG_DEV0_EPF7_2_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 |
13825 | #define smnBIF_CFG_DEV0_EPF7_2_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 |
13826 | #define smnBIF_CFG_DEV0_EPF7_2_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000 |
13827 | #define smnBIF_CFG_DEV0_EPF7_2_PCIE_BAR1_CAP_DEFAULT 0x00000000 |
13828 | #define smnBIF_CFG_DEV0_EPF7_2_PCIE_BAR1_CNTL_DEFAULT 0x00000020 |
13829 | #define smnBIF_CFG_DEV0_EPF7_2_PCIE_BAR2_CAP_DEFAULT 0x00000000 |
13830 | #define smnBIF_CFG_DEV0_EPF7_2_PCIE_BAR2_CNTL_DEFAULT 0x00000000 |
13831 | #define smnBIF_CFG_DEV0_EPF7_2_PCIE_BAR3_CAP_DEFAULT 0x00000000 |
13832 | #define smnBIF_CFG_DEV0_EPF7_2_PCIE_BAR3_CNTL_DEFAULT 0x00000000 |
13833 | #define smnBIF_CFG_DEV0_EPF7_2_PCIE_BAR4_CAP_DEFAULT 0x00000000 |
13834 | #define smnBIF_CFG_DEV0_EPF7_2_PCIE_BAR4_CNTL_DEFAULT 0x00000000 |
13835 | #define smnBIF_CFG_DEV0_EPF7_2_PCIE_BAR5_CAP_DEFAULT 0x00000000 |
13836 | #define smnBIF_CFG_DEV0_EPF7_2_PCIE_BAR5_CNTL_DEFAULT 0x00000000 |
13837 | #define smnBIF_CFG_DEV0_EPF7_2_PCIE_BAR6_CAP_DEFAULT 0x00000000 |
13838 | #define smnBIF_CFG_DEV0_EPF7_2_PCIE_BAR6_CNTL_DEFAULT 0x00000000 |
13839 | #define smnBIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000 |
13840 | #define smnBIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000 |
13841 | #define smnBIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000 |
13842 | #define smnBIF_CFG_DEV0_EPF7_2_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000 |
13843 | #define smnBIF_CFG_DEV0_EPF7_2_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000 |
13844 | #define smnBIF_CFG_DEV0_EPF7_2_PCIE_DPA_CAP_DEFAULT 0x00000000 |
13845 | #define smnBIF_CFG_DEV0_EPF7_2_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000 |
13846 | #define smnBIF_CFG_DEV0_EPF7_2_PCIE_DPA_STATUS_DEFAULT 0x00000100 |
13847 | #define smnBIF_CFG_DEV0_EPF7_2_PCIE_DPA_CNTL_DEFAULT 0x00000000 |
13848 | #define smnBIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000 |
13849 | #define smnBIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000 |
13850 | #define smnBIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000 |
13851 | #define smnBIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000 |
13852 | #define smnBIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000 |
13853 | #define smnBIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000 |
13854 | #define smnBIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000 |
13855 | #define smnBIF_CFG_DEV0_EPF7_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000 |
13856 | #define smnBIF_CFG_DEV0_EPF7_2_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000 |
13857 | #define smnBIF_CFG_DEV0_EPF7_2_PCIE_ACS_CAP_DEFAULT 0x00000000 |
13858 | #define smnBIF_CFG_DEV0_EPF7_2_PCIE_ACS_CNTL_DEFAULT 0x00000000 |
13859 | #define smnBIF_CFG_DEV0_EPF7_2_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000 |
13860 | #define smnBIF_CFG_DEV0_EPF7_2_PCIE_ARI_CAP_DEFAULT 0x00000000 |
13861 | #define smnBIF_CFG_DEV0_EPF7_2_PCIE_ARI_CNTL_DEFAULT 0x00000000 |
13862 | |
13863 | |
13864 | // addressBlock: nbio_nbif0_bif_cfg_dev1_epf0_bifcfgdecp |
13865 | #define smnBIF_CFG_DEV1_EPF0_2_VENDOR_ID_DEFAULT 0x00000000 |
13866 | #define smnBIF_CFG_DEV1_EPF0_2_DEVICE_ID_DEFAULT 0x00000000 |
13867 | #define smnBIF_CFG_DEV1_EPF0_2_COMMAND_DEFAULT 0x00000000 |
13868 | #define smnBIF_CFG_DEV1_EPF0_2_STATUS_DEFAULT 0x00000000 |
13869 | #define smnBIF_CFG_DEV1_EPF0_2_REVISION_ID_DEFAULT 0x00000000 |
13870 | #define smnBIF_CFG_DEV1_EPF0_2_PROG_INTERFACE_DEFAULT 0x00000000 |
13871 | #define smnBIF_CFG_DEV1_EPF0_2_SUB_CLASS_DEFAULT 0x00000000 |
13872 | #define smnBIF_CFG_DEV1_EPF0_2_BASE_CLASS_DEFAULT 0x00000000 |
13873 | #define smnBIF_CFG_DEV1_EPF0_2_CACHE_LINE_DEFAULT 0x00000000 |
13874 | #define smnBIF_CFG_DEV1_EPF0_2_LATENCY_DEFAULT 0x00000000 |
13875 | #define 0x00000000 |
13876 | #define smnBIF_CFG_DEV1_EPF0_2_BIST_DEFAULT 0x00000000 |
13877 | #define smnBIF_CFG_DEV1_EPF0_2_BASE_ADDR_1_DEFAULT 0x00000000 |
13878 | #define smnBIF_CFG_DEV1_EPF0_2_BASE_ADDR_2_DEFAULT 0x00000000 |
13879 | #define smnBIF_CFG_DEV1_EPF0_2_BASE_ADDR_3_DEFAULT 0x00000000 |
13880 | #define smnBIF_CFG_DEV1_EPF0_2_BASE_ADDR_4_DEFAULT 0x00000000 |
13881 | #define smnBIF_CFG_DEV1_EPF0_2_BASE_ADDR_5_DEFAULT 0x00000000 |
13882 | #define smnBIF_CFG_DEV1_EPF0_2_BASE_ADDR_6_DEFAULT 0x00000000 |
13883 | #define smnBIF_CFG_DEV1_EPF0_2_ADAPTER_ID_DEFAULT 0x00000000 |
13884 | #define smnBIF_CFG_DEV1_EPF0_2_ROM_BASE_ADDR_DEFAULT 0x00000000 |
13885 | #define smnBIF_CFG_DEV1_EPF0_2_CAP_PTR_DEFAULT 0x00000000 |
13886 | #define smnBIF_CFG_DEV1_EPF0_2_INTERRUPT_LINE_DEFAULT 0x00000000 |
13887 | #define smnBIF_CFG_DEV1_EPF0_2_INTERRUPT_PIN_DEFAULT 0x00000000 |
13888 | #define smnBIF_CFG_DEV1_EPF0_2_MIN_GRANT_DEFAULT 0x00000000 |
13889 | #define smnBIF_CFG_DEV1_EPF0_2_MAX_LATENCY_DEFAULT 0x00000000 |
13890 | #define smnBIF_CFG_DEV1_EPF0_2_VENDOR_CAP_LIST_DEFAULT 0x00000000 |
13891 | #define smnBIF_CFG_DEV1_EPF0_2_ADAPTER_ID_W_DEFAULT 0x00000000 |
13892 | #define smnBIF_CFG_DEV1_EPF0_2_PMI_CAP_LIST_DEFAULT 0x00000000 |
13893 | #define smnBIF_CFG_DEV1_EPF0_2_PMI_CAP_DEFAULT 0x00000000 |
13894 | #define smnBIF_CFG_DEV1_EPF0_2_PMI_STATUS_CNTL_DEFAULT 0x00000000 |
13895 | #define smnBIF_CFG_DEV1_EPF0_2_PCIE_CAP_LIST_DEFAULT 0x0000a000 |
13896 | #define smnBIF_CFG_DEV1_EPF0_2_PCIE_CAP_DEFAULT 0x00000002 |
13897 | #define smnBIF_CFG_DEV1_EPF0_2_DEVICE_CAP_DEFAULT 0x10000000 |
13898 | #define smnBIF_CFG_DEV1_EPF0_2_DEVICE_CNTL_DEFAULT 0x00002810 |
13899 | #define smnBIF_CFG_DEV1_EPF0_2_DEVICE_STATUS_DEFAULT 0x00000000 |
13900 | #define smnBIF_CFG_DEV1_EPF0_2_LINK_CAP_DEFAULT 0x00011c03 |
13901 | #define smnBIF_CFG_DEV1_EPF0_2_LINK_CNTL_DEFAULT 0x00000000 |
13902 | #define smnBIF_CFG_DEV1_EPF0_2_LINK_STATUS_DEFAULT 0x00000001 |
13903 | #define smnBIF_CFG_DEV1_EPF0_2_DEVICE_CAP2_DEFAULT 0x00000000 |
13904 | #define smnBIF_CFG_DEV1_EPF0_2_DEVICE_CNTL2_DEFAULT 0x00000000 |
13905 | #define smnBIF_CFG_DEV1_EPF0_2_DEVICE_STATUS2_DEFAULT 0x00000000 |
13906 | #define smnBIF_CFG_DEV1_EPF0_2_LINK_CAP2_DEFAULT 0x0000000e |
13907 | #define smnBIF_CFG_DEV1_EPF0_2_LINK_CNTL2_DEFAULT 0x00000003 |
13908 | #define smnBIF_CFG_DEV1_EPF0_2_LINK_STATUS2_DEFAULT 0x00000000 |
13909 | #define smnBIF_CFG_DEV1_EPF0_2_SLOT_CAP2_DEFAULT 0x00000000 |
13910 | #define smnBIF_CFG_DEV1_EPF0_2_SLOT_CNTL2_DEFAULT 0x00000000 |
13911 | #define smnBIF_CFG_DEV1_EPF0_2_SLOT_STATUS2_DEFAULT 0x00000000 |
13912 | #define smnBIF_CFG_DEV1_EPF0_2_MSI_CAP_LIST_DEFAULT 0x0000c000 |
13913 | #define smnBIF_CFG_DEV1_EPF0_2_MSI_MSG_CNTL_DEFAULT 0x00000080 |
13914 | #define smnBIF_CFG_DEV1_EPF0_2_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 |
13915 | #define smnBIF_CFG_DEV1_EPF0_2_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 |
13916 | #define smnBIF_CFG_DEV1_EPF0_2_MSI_MSG_DATA_DEFAULT 0x00000000 |
13917 | #define smnBIF_CFG_DEV1_EPF0_2_MSI_MASK_DEFAULT 0x00000000 |
13918 | #define smnBIF_CFG_DEV1_EPF0_2_MSI_MSG_DATA_64_DEFAULT 0x00000000 |
13919 | #define smnBIF_CFG_DEV1_EPF0_2_MSI_MASK_64_DEFAULT 0x00000000 |
13920 | #define smnBIF_CFG_DEV1_EPF0_2_MSI_PENDING_DEFAULT 0x00000000 |
13921 | #define smnBIF_CFG_DEV1_EPF0_2_MSI_PENDING_64_DEFAULT 0x00000000 |
13922 | #define smnBIF_CFG_DEV1_EPF0_2_MSIX_CAP_LIST_DEFAULT 0x00000000 |
13923 | #define smnBIF_CFG_DEV1_EPF0_2_MSIX_MSG_CNTL_DEFAULT 0x00000000 |
13924 | #define smnBIF_CFG_DEV1_EPF0_2_MSIX_TABLE_DEFAULT 0x00000000 |
13925 | #define smnBIF_CFG_DEV1_EPF0_2_MSIX_PBA_DEFAULT 0x00000000 |
13926 | #define smnBIF_CFG_DEV1_EPF0_2_SATA_CAP_0_DEFAULT 0x00000000 |
13927 | #define smnBIF_CFG_DEV1_EPF0_2_SATA_CAP_1_DEFAULT 0x00000000 |
13928 | #define smnBIF_CFG_DEV1_EPF0_2_SATA_IDP_INDEX_DEFAULT 0x00000000 |
13929 | #define smnBIF_CFG_DEV1_EPF0_2_SATA_IDP_DATA_DEFAULT 0x00000000 |
13930 | #define smnBIF_CFG_DEV1_EPF0_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 |
13931 | #define smnBIF_CFG_DEV1_EPF0_2_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 |
13932 | #define smnBIF_CFG_DEV1_EPF0_2_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 |
13933 | #define smnBIF_CFG_DEV1_EPF0_2_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 |
13934 | #define smnBIF_CFG_DEV1_EPF0_2_PCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000 |
13935 | #define smnBIF_CFG_DEV1_EPF0_2_PCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000 |
13936 | #define smnBIF_CFG_DEV1_EPF0_2_PCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000 |
13937 | #define smnBIF_CFG_DEV1_EPF0_2_PCIE_PORT_VC_CNTL_DEFAULT 0x00000000 |
13938 | #define smnBIF_CFG_DEV1_EPF0_2_PCIE_PORT_VC_STATUS_DEFAULT 0x00000000 |
13939 | #define smnBIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000 |
13940 | #define smnBIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe |
13941 | #define smnBIF_CFG_DEV1_EPF0_2_PCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000000 |
13942 | #define smnBIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000 |
13943 | #define smnBIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000 |
13944 | #define smnBIF_CFG_DEV1_EPF0_2_PCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000000 |
13945 | #define smnBIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 |
13946 | #define smnBIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 |
13947 | #define smnBIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 |
13948 | #define smnBIF_CFG_DEV1_EPF0_2_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 |
13949 | #define smnBIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 |
13950 | #define smnBIF_CFG_DEV1_EPF0_2_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000 |
13951 | #define smnBIF_CFG_DEV1_EPF0_2_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 |
13952 | #define smnBIF_CFG_DEV1_EPF0_2_PCIE_HDR_LOG0_DEFAULT 0x00000000 |
13953 | #define smnBIF_CFG_DEV1_EPF0_2_PCIE_HDR_LOG1_DEFAULT 0x00000000 |
13954 | #define smnBIF_CFG_DEV1_EPF0_2_PCIE_HDR_LOG2_DEFAULT 0x00000000 |
13955 | #define smnBIF_CFG_DEV1_EPF0_2_PCIE_HDR_LOG3_DEFAULT 0x00000000 |
13956 | #define smnBIF_CFG_DEV1_EPF0_2_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 |
13957 | #define smnBIF_CFG_DEV1_EPF0_2_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 |
13958 | #define smnBIF_CFG_DEV1_EPF0_2_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 |
13959 | #define smnBIF_CFG_DEV1_EPF0_2_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 |
13960 | #define smnBIF_CFG_DEV1_EPF0_2_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000 |
13961 | #define smnBIF_CFG_DEV1_EPF0_2_PCIE_BAR1_CAP_DEFAULT 0x00000000 |
13962 | #define smnBIF_CFG_DEV1_EPF0_2_PCIE_BAR1_CNTL_DEFAULT 0x00000020 |
13963 | #define smnBIF_CFG_DEV1_EPF0_2_PCIE_BAR2_CAP_DEFAULT 0x00000000 |
13964 | #define smnBIF_CFG_DEV1_EPF0_2_PCIE_BAR2_CNTL_DEFAULT 0x00000000 |
13965 | #define smnBIF_CFG_DEV1_EPF0_2_PCIE_BAR3_CAP_DEFAULT 0x00000000 |
13966 | #define smnBIF_CFG_DEV1_EPF0_2_PCIE_BAR3_CNTL_DEFAULT 0x00000000 |
13967 | #define smnBIF_CFG_DEV1_EPF0_2_PCIE_BAR4_CAP_DEFAULT 0x00000000 |
13968 | #define smnBIF_CFG_DEV1_EPF0_2_PCIE_BAR4_CNTL_DEFAULT 0x00000000 |
13969 | #define smnBIF_CFG_DEV1_EPF0_2_PCIE_BAR5_CAP_DEFAULT 0x00000000 |
13970 | #define smnBIF_CFG_DEV1_EPF0_2_PCIE_BAR5_CNTL_DEFAULT 0x00000000 |
13971 | #define smnBIF_CFG_DEV1_EPF0_2_PCIE_BAR6_CAP_DEFAULT 0x00000000 |
13972 | #define smnBIF_CFG_DEV1_EPF0_2_PCIE_BAR6_CNTL_DEFAULT 0x00000000 |
13973 | #define smnBIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000 |
13974 | #define smnBIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000 |
13975 | #define smnBIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000 |
13976 | #define smnBIF_CFG_DEV1_EPF0_2_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000 |
13977 | #define smnBIF_CFG_DEV1_EPF0_2_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000 |
13978 | #define smnBIF_CFG_DEV1_EPF0_2_PCIE_DPA_CAP_DEFAULT 0x00000000 |
13979 | #define smnBIF_CFG_DEV1_EPF0_2_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000 |
13980 | #define smnBIF_CFG_DEV1_EPF0_2_PCIE_DPA_STATUS_DEFAULT 0x00000100 |
13981 | #define smnBIF_CFG_DEV1_EPF0_2_PCIE_DPA_CNTL_DEFAULT 0x00000000 |
13982 | #define smnBIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000 |
13983 | #define smnBIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000 |
13984 | #define smnBIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000 |
13985 | #define smnBIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000 |
13986 | #define smnBIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000 |
13987 | #define smnBIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000 |
13988 | #define smnBIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000 |
13989 | #define smnBIF_CFG_DEV1_EPF0_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000 |
13990 | #define smnBIF_CFG_DEV1_EPF0_2_PCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a010019 |
13991 | #define smnBIF_CFG_DEV1_EPF0_2_PCIE_LINK_CNTL3_DEFAULT 0x00000000 |
13992 | #define smnBIF_CFG_DEV1_EPF0_2_PCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000 |
13993 | #define smnBIF_CFG_DEV1_EPF0_2_PCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
13994 | #define smnBIF_CFG_DEV1_EPF0_2_PCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
13995 | #define smnBIF_CFG_DEV1_EPF0_2_PCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
13996 | #define smnBIF_CFG_DEV1_EPF0_2_PCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
13997 | #define smnBIF_CFG_DEV1_EPF0_2_PCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
13998 | #define smnBIF_CFG_DEV1_EPF0_2_PCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
13999 | #define smnBIF_CFG_DEV1_EPF0_2_PCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
14000 | #define smnBIF_CFG_DEV1_EPF0_2_PCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
14001 | #define smnBIF_CFG_DEV1_EPF0_2_PCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
14002 | #define smnBIF_CFG_DEV1_EPF0_2_PCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
14003 | #define smnBIF_CFG_DEV1_EPF0_2_PCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
14004 | #define smnBIF_CFG_DEV1_EPF0_2_PCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
14005 | #define smnBIF_CFG_DEV1_EPF0_2_PCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
14006 | #define smnBIF_CFG_DEV1_EPF0_2_PCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
14007 | #define smnBIF_CFG_DEV1_EPF0_2_PCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
14008 | #define smnBIF_CFG_DEV1_EPF0_2_PCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f00 |
14009 | #define smnBIF_CFG_DEV1_EPF0_2_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000 |
14010 | #define smnBIF_CFG_DEV1_EPF0_2_PCIE_ACS_CAP_DEFAULT 0x00000000 |
14011 | #define smnBIF_CFG_DEV1_EPF0_2_PCIE_ACS_CNTL_DEFAULT 0x00000000 |
14012 | #define smnBIF_CFG_DEV1_EPF0_2_PCIE_LTR_ENH_CAP_LIST_DEFAULT 0x32800000 |
14013 | #define smnBIF_CFG_DEV1_EPF0_2_PCIE_LTR_CAP_DEFAULT 0x00000000 |
14014 | #define smnBIF_CFG_DEV1_EPF0_2_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000 |
14015 | #define smnBIF_CFG_DEV1_EPF0_2_PCIE_ARI_CAP_DEFAULT 0x00000000 |
14016 | #define smnBIF_CFG_DEV1_EPF0_2_PCIE_ARI_CNTL_DEFAULT 0x00000000 |
14017 | |
14018 | |
14019 | // addressBlock: nbio_nbif0_bif_cfg_dev1_epf1_bifcfgdecp |
14020 | #define smnBIF_CFG_DEV1_EPF1_2_VENDOR_ID_DEFAULT 0x00000000 |
14021 | #define smnBIF_CFG_DEV1_EPF1_2_DEVICE_ID_DEFAULT 0x00000000 |
14022 | #define smnBIF_CFG_DEV1_EPF1_2_COMMAND_DEFAULT 0x00000000 |
14023 | #define smnBIF_CFG_DEV1_EPF1_2_STATUS_DEFAULT 0x00000000 |
14024 | #define smnBIF_CFG_DEV1_EPF1_2_REVISION_ID_DEFAULT 0x00000000 |
14025 | #define smnBIF_CFG_DEV1_EPF1_2_PROG_INTERFACE_DEFAULT 0x00000000 |
14026 | #define smnBIF_CFG_DEV1_EPF1_2_SUB_CLASS_DEFAULT 0x00000000 |
14027 | #define smnBIF_CFG_DEV1_EPF1_2_BASE_CLASS_DEFAULT 0x00000000 |
14028 | #define smnBIF_CFG_DEV1_EPF1_2_CACHE_LINE_DEFAULT 0x00000000 |
14029 | #define smnBIF_CFG_DEV1_EPF1_2_LATENCY_DEFAULT 0x00000000 |
14030 | #define 0x00000000 |
14031 | #define smnBIF_CFG_DEV1_EPF1_2_BIST_DEFAULT 0x00000000 |
14032 | #define smnBIF_CFG_DEV1_EPF1_2_BASE_ADDR_1_DEFAULT 0x00000000 |
14033 | #define smnBIF_CFG_DEV1_EPF1_2_BASE_ADDR_2_DEFAULT 0x00000000 |
14034 | #define smnBIF_CFG_DEV1_EPF1_2_BASE_ADDR_3_DEFAULT 0x00000000 |
14035 | #define smnBIF_CFG_DEV1_EPF1_2_BASE_ADDR_4_DEFAULT 0x00000000 |
14036 | #define smnBIF_CFG_DEV1_EPF1_2_BASE_ADDR_5_DEFAULT 0x00000000 |
14037 | #define smnBIF_CFG_DEV1_EPF1_2_BASE_ADDR_6_DEFAULT 0x00000000 |
14038 | #define smnBIF_CFG_DEV1_EPF1_2_ADAPTER_ID_DEFAULT 0x00000000 |
14039 | #define smnBIF_CFG_DEV1_EPF1_2_ROM_BASE_ADDR_DEFAULT 0x00000000 |
14040 | #define smnBIF_CFG_DEV1_EPF1_2_CAP_PTR_DEFAULT 0x00000000 |
14041 | #define smnBIF_CFG_DEV1_EPF1_2_INTERRUPT_LINE_DEFAULT 0x00000000 |
14042 | #define smnBIF_CFG_DEV1_EPF1_2_INTERRUPT_PIN_DEFAULT 0x00000000 |
14043 | #define smnBIF_CFG_DEV1_EPF1_2_MIN_GRANT_DEFAULT 0x00000000 |
14044 | #define smnBIF_CFG_DEV1_EPF1_2_MAX_LATENCY_DEFAULT 0x00000000 |
14045 | #define smnBIF_CFG_DEV1_EPF1_2_VENDOR_CAP_LIST_DEFAULT 0x00000000 |
14046 | #define smnBIF_CFG_DEV1_EPF1_2_ADAPTER_ID_W_DEFAULT 0x00000000 |
14047 | #define smnBIF_CFG_DEV1_EPF1_2_PMI_CAP_LIST_DEFAULT 0x00000000 |
14048 | #define smnBIF_CFG_DEV1_EPF1_2_PMI_CAP_DEFAULT 0x00000000 |
14049 | #define smnBIF_CFG_DEV1_EPF1_2_PMI_STATUS_CNTL_DEFAULT 0x00000000 |
14050 | #define smnBIF_CFG_DEV1_EPF1_2_SBRN_DEFAULT 0x00000000 |
14051 | #define smnBIF_CFG_DEV1_EPF1_2_FLADJ_DEFAULT 0x00000020 |
14052 | #define smnBIF_CFG_DEV1_EPF1_2_DBESL_DBESLD_DEFAULT 0x00000000 |
14053 | #define smnBIF_CFG_DEV1_EPF1_2_PCIE_CAP_LIST_DEFAULT 0x0000a000 |
14054 | #define smnBIF_CFG_DEV1_EPF1_2_PCIE_CAP_DEFAULT 0x00000002 |
14055 | #define smnBIF_CFG_DEV1_EPF1_2_DEVICE_CAP_DEFAULT 0x10000000 |
14056 | #define smnBIF_CFG_DEV1_EPF1_2_DEVICE_CNTL_DEFAULT 0x00002810 |
14057 | #define smnBIF_CFG_DEV1_EPF1_2_DEVICE_STATUS_DEFAULT 0x00000000 |
14058 | #define smnBIF_CFG_DEV1_EPF1_2_LINK_CAP_DEFAULT 0x00011c03 |
14059 | #define smnBIF_CFG_DEV1_EPF1_2_LINK_CNTL_DEFAULT 0x00000000 |
14060 | #define smnBIF_CFG_DEV1_EPF1_2_LINK_STATUS_DEFAULT 0x00000001 |
14061 | #define smnBIF_CFG_DEV1_EPF1_2_DEVICE_CAP2_DEFAULT 0x00000000 |
14062 | #define smnBIF_CFG_DEV1_EPF1_2_DEVICE_CNTL2_DEFAULT 0x00000000 |
14063 | #define smnBIF_CFG_DEV1_EPF1_2_DEVICE_STATUS2_DEFAULT 0x00000000 |
14064 | #define smnBIF_CFG_DEV1_EPF1_2_LINK_CAP2_DEFAULT 0x0000000e |
14065 | #define smnBIF_CFG_DEV1_EPF1_2_LINK_CNTL2_DEFAULT 0x00000003 |
14066 | #define smnBIF_CFG_DEV1_EPF1_2_LINK_STATUS2_DEFAULT 0x00000000 |
14067 | #define smnBIF_CFG_DEV1_EPF1_2_SLOT_CAP2_DEFAULT 0x00000000 |
14068 | #define smnBIF_CFG_DEV1_EPF1_2_SLOT_CNTL2_DEFAULT 0x00000000 |
14069 | #define smnBIF_CFG_DEV1_EPF1_2_SLOT_STATUS2_DEFAULT 0x00000000 |
14070 | #define smnBIF_CFG_DEV1_EPF1_2_MSI_CAP_LIST_DEFAULT 0x0000c000 |
14071 | #define smnBIF_CFG_DEV1_EPF1_2_MSI_MSG_CNTL_DEFAULT 0x00000080 |
14072 | #define smnBIF_CFG_DEV1_EPF1_2_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 |
14073 | #define smnBIF_CFG_DEV1_EPF1_2_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 |
14074 | #define smnBIF_CFG_DEV1_EPF1_2_MSI_MSG_DATA_DEFAULT 0x00000000 |
14075 | #define smnBIF_CFG_DEV1_EPF1_2_MSI_MASK_DEFAULT 0x00000000 |
14076 | #define smnBIF_CFG_DEV1_EPF1_2_MSI_MSG_DATA_64_DEFAULT 0x00000000 |
14077 | #define smnBIF_CFG_DEV1_EPF1_2_MSI_MASK_64_DEFAULT 0x00000000 |
14078 | #define smnBIF_CFG_DEV1_EPF1_2_MSI_PENDING_DEFAULT 0x00000000 |
14079 | #define smnBIF_CFG_DEV1_EPF1_2_MSI_PENDING_64_DEFAULT 0x00000000 |
14080 | #define smnBIF_CFG_DEV1_EPF1_2_MSIX_CAP_LIST_DEFAULT 0x00000000 |
14081 | #define smnBIF_CFG_DEV1_EPF1_2_MSIX_MSG_CNTL_DEFAULT 0x00000000 |
14082 | #define smnBIF_CFG_DEV1_EPF1_2_MSIX_TABLE_DEFAULT 0x00000000 |
14083 | #define smnBIF_CFG_DEV1_EPF1_2_MSIX_PBA_DEFAULT 0x00000000 |
14084 | #define smnBIF_CFG_DEV1_EPF1_2_SATA_CAP_0_DEFAULT 0x00000000 |
14085 | #define smnBIF_CFG_DEV1_EPF1_2_SATA_CAP_1_DEFAULT 0x00000000 |
14086 | #define smnBIF_CFG_DEV1_EPF1_2_SATA_IDP_INDEX_DEFAULT 0x00000000 |
14087 | #define smnBIF_CFG_DEV1_EPF1_2_SATA_IDP_DATA_DEFAULT 0x00000000 |
14088 | #define smnBIF_CFG_DEV1_EPF1_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 |
14089 | #define smnBIF_CFG_DEV1_EPF1_2_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 |
14090 | #define smnBIF_CFG_DEV1_EPF1_2_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 |
14091 | #define smnBIF_CFG_DEV1_EPF1_2_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 |
14092 | #define smnBIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 |
14093 | #define smnBIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 |
14094 | #define smnBIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 |
14095 | #define smnBIF_CFG_DEV1_EPF1_2_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 |
14096 | #define smnBIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 |
14097 | #define smnBIF_CFG_DEV1_EPF1_2_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000 |
14098 | #define smnBIF_CFG_DEV1_EPF1_2_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 |
14099 | #define smnBIF_CFG_DEV1_EPF1_2_PCIE_HDR_LOG0_DEFAULT 0x00000000 |
14100 | #define smnBIF_CFG_DEV1_EPF1_2_PCIE_HDR_LOG1_DEFAULT 0x00000000 |
14101 | #define smnBIF_CFG_DEV1_EPF1_2_PCIE_HDR_LOG2_DEFAULT 0x00000000 |
14102 | #define smnBIF_CFG_DEV1_EPF1_2_PCIE_HDR_LOG3_DEFAULT 0x00000000 |
14103 | #define smnBIF_CFG_DEV1_EPF1_2_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 |
14104 | #define smnBIF_CFG_DEV1_EPF1_2_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 |
14105 | #define smnBIF_CFG_DEV1_EPF1_2_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 |
14106 | #define smnBIF_CFG_DEV1_EPF1_2_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 |
14107 | #define smnBIF_CFG_DEV1_EPF1_2_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000 |
14108 | #define smnBIF_CFG_DEV1_EPF1_2_PCIE_BAR1_CAP_DEFAULT 0x00000000 |
14109 | #define smnBIF_CFG_DEV1_EPF1_2_PCIE_BAR1_CNTL_DEFAULT 0x00000020 |
14110 | #define smnBIF_CFG_DEV1_EPF1_2_PCIE_BAR2_CAP_DEFAULT 0x00000000 |
14111 | #define smnBIF_CFG_DEV1_EPF1_2_PCIE_BAR2_CNTL_DEFAULT 0x00000000 |
14112 | #define smnBIF_CFG_DEV1_EPF1_2_PCIE_BAR3_CAP_DEFAULT 0x00000000 |
14113 | #define smnBIF_CFG_DEV1_EPF1_2_PCIE_BAR3_CNTL_DEFAULT 0x00000000 |
14114 | #define smnBIF_CFG_DEV1_EPF1_2_PCIE_BAR4_CAP_DEFAULT 0x00000000 |
14115 | #define smnBIF_CFG_DEV1_EPF1_2_PCIE_BAR4_CNTL_DEFAULT 0x00000000 |
14116 | #define smnBIF_CFG_DEV1_EPF1_2_PCIE_BAR5_CAP_DEFAULT 0x00000000 |
14117 | #define smnBIF_CFG_DEV1_EPF1_2_PCIE_BAR5_CNTL_DEFAULT 0x00000000 |
14118 | #define smnBIF_CFG_DEV1_EPF1_2_PCIE_BAR6_CAP_DEFAULT 0x00000000 |
14119 | #define smnBIF_CFG_DEV1_EPF1_2_PCIE_BAR6_CNTL_DEFAULT 0x00000000 |
14120 | #define smnBIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000 |
14121 | #define smnBIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000 |
14122 | #define smnBIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000 |
14123 | #define smnBIF_CFG_DEV1_EPF1_2_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000 |
14124 | #define smnBIF_CFG_DEV1_EPF1_2_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000 |
14125 | #define smnBIF_CFG_DEV1_EPF1_2_PCIE_DPA_CAP_DEFAULT 0x00000000 |
14126 | #define smnBIF_CFG_DEV1_EPF1_2_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000 |
14127 | #define smnBIF_CFG_DEV1_EPF1_2_PCIE_DPA_STATUS_DEFAULT 0x00000100 |
14128 | #define smnBIF_CFG_DEV1_EPF1_2_PCIE_DPA_CNTL_DEFAULT 0x00000000 |
14129 | #define smnBIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000 |
14130 | #define smnBIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000 |
14131 | #define smnBIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000 |
14132 | #define smnBIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000 |
14133 | #define smnBIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000 |
14134 | #define smnBIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000 |
14135 | #define smnBIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000 |
14136 | #define smnBIF_CFG_DEV1_EPF1_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000 |
14137 | #define smnBIF_CFG_DEV1_EPF1_2_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000 |
14138 | #define smnBIF_CFG_DEV1_EPF1_2_PCIE_ACS_CAP_DEFAULT 0x00000000 |
14139 | #define smnBIF_CFG_DEV1_EPF1_2_PCIE_ACS_CNTL_DEFAULT 0x00000000 |
14140 | #define smnBIF_CFG_DEV1_EPF1_2_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000 |
14141 | #define smnBIF_CFG_DEV1_EPF1_2_PCIE_ARI_CAP_DEFAULT 0x00000000 |
14142 | #define smnBIF_CFG_DEV1_EPF1_2_PCIE_ARI_CNTL_DEFAULT 0x00000000 |
14143 | |
14144 | |
14145 | // addressBlock: nbio_nbif0_bif_cfg_dev1_epf2_bifcfgdecp |
14146 | #define smnBIF_CFG_DEV1_EPF2_2_VENDOR_ID_DEFAULT 0x00000000 |
14147 | #define smnBIF_CFG_DEV1_EPF2_2_DEVICE_ID_DEFAULT 0x00000000 |
14148 | #define smnBIF_CFG_DEV1_EPF2_2_COMMAND_DEFAULT 0x00000000 |
14149 | #define smnBIF_CFG_DEV1_EPF2_2_STATUS_DEFAULT 0x00000000 |
14150 | #define smnBIF_CFG_DEV1_EPF2_2_REVISION_ID_DEFAULT 0x00000000 |
14151 | #define smnBIF_CFG_DEV1_EPF2_2_PROG_INTERFACE_DEFAULT 0x00000000 |
14152 | #define smnBIF_CFG_DEV1_EPF2_2_SUB_CLASS_DEFAULT 0x00000000 |
14153 | #define smnBIF_CFG_DEV1_EPF2_2_BASE_CLASS_DEFAULT 0x00000000 |
14154 | #define smnBIF_CFG_DEV1_EPF2_2_CACHE_LINE_DEFAULT 0x00000000 |
14155 | #define smnBIF_CFG_DEV1_EPF2_2_LATENCY_DEFAULT 0x00000000 |
14156 | #define 0x00000000 |
14157 | #define smnBIF_CFG_DEV1_EPF2_2_BIST_DEFAULT 0x00000000 |
14158 | #define smnBIF_CFG_DEV1_EPF2_2_BASE_ADDR_1_DEFAULT 0x00000000 |
14159 | #define smnBIF_CFG_DEV1_EPF2_2_BASE_ADDR_2_DEFAULT 0x00000000 |
14160 | #define smnBIF_CFG_DEV1_EPF2_2_BASE_ADDR_3_DEFAULT 0x00000000 |
14161 | #define smnBIF_CFG_DEV1_EPF2_2_BASE_ADDR_4_DEFAULT 0x00000000 |
14162 | #define smnBIF_CFG_DEV1_EPF2_2_BASE_ADDR_5_DEFAULT 0x00000000 |
14163 | #define smnBIF_CFG_DEV1_EPF2_2_BASE_ADDR_6_DEFAULT 0x00000000 |
14164 | #define smnBIF_CFG_DEV1_EPF2_2_ADAPTER_ID_DEFAULT 0x00000000 |
14165 | #define smnBIF_CFG_DEV1_EPF2_2_ROM_BASE_ADDR_DEFAULT 0x00000000 |
14166 | #define smnBIF_CFG_DEV1_EPF2_2_CAP_PTR_DEFAULT 0x00000000 |
14167 | #define smnBIF_CFG_DEV1_EPF2_2_INTERRUPT_LINE_DEFAULT 0x00000000 |
14168 | #define smnBIF_CFG_DEV1_EPF2_2_INTERRUPT_PIN_DEFAULT 0x00000000 |
14169 | #define smnBIF_CFG_DEV1_EPF2_2_MIN_GRANT_DEFAULT 0x00000000 |
14170 | #define smnBIF_CFG_DEV1_EPF2_2_MAX_LATENCY_DEFAULT 0x00000000 |
14171 | #define smnBIF_CFG_DEV1_EPF2_2_VENDOR_CAP_LIST_DEFAULT 0x00000000 |
14172 | #define smnBIF_CFG_DEV1_EPF2_2_ADAPTER_ID_W_DEFAULT 0x00000000 |
14173 | #define smnBIF_CFG_DEV1_EPF2_2_PMI_CAP_LIST_DEFAULT 0x00000000 |
14174 | #define smnBIF_CFG_DEV1_EPF2_2_PMI_CAP_DEFAULT 0x00000000 |
14175 | #define smnBIF_CFG_DEV1_EPF2_2_PMI_STATUS_CNTL_DEFAULT 0x00000000 |
14176 | #define smnBIF_CFG_DEV1_EPF2_2_SBRN_DEFAULT 0x00000000 |
14177 | #define smnBIF_CFG_DEV1_EPF2_2_FLADJ_DEFAULT 0x00000020 |
14178 | #define smnBIF_CFG_DEV1_EPF2_2_DBESL_DBESLD_DEFAULT 0x00000000 |
14179 | #define smnBIF_CFG_DEV1_EPF2_2_PCIE_CAP_LIST_DEFAULT 0x0000a000 |
14180 | #define smnBIF_CFG_DEV1_EPF2_2_PCIE_CAP_DEFAULT 0x00000002 |
14181 | #define smnBIF_CFG_DEV1_EPF2_2_DEVICE_CAP_DEFAULT 0x10000000 |
14182 | #define smnBIF_CFG_DEV1_EPF2_2_DEVICE_CNTL_DEFAULT 0x00002810 |
14183 | #define smnBIF_CFG_DEV1_EPF2_2_DEVICE_STATUS_DEFAULT 0x00000000 |
14184 | #define smnBIF_CFG_DEV1_EPF2_2_LINK_CAP_DEFAULT 0x00011c03 |
14185 | #define smnBIF_CFG_DEV1_EPF2_2_LINK_CNTL_DEFAULT 0x00000000 |
14186 | #define smnBIF_CFG_DEV1_EPF2_2_LINK_STATUS_DEFAULT 0x00000001 |
14187 | #define smnBIF_CFG_DEV1_EPF2_2_DEVICE_CAP2_DEFAULT 0x00000000 |
14188 | #define smnBIF_CFG_DEV1_EPF2_2_DEVICE_CNTL2_DEFAULT 0x00000000 |
14189 | #define smnBIF_CFG_DEV1_EPF2_2_DEVICE_STATUS2_DEFAULT 0x00000000 |
14190 | #define smnBIF_CFG_DEV1_EPF2_2_LINK_CAP2_DEFAULT 0x0000000e |
14191 | #define smnBIF_CFG_DEV1_EPF2_2_LINK_CNTL2_DEFAULT 0x00000003 |
14192 | #define smnBIF_CFG_DEV1_EPF2_2_LINK_STATUS2_DEFAULT 0x00000000 |
14193 | #define smnBIF_CFG_DEV1_EPF2_2_SLOT_CAP2_DEFAULT 0x00000000 |
14194 | #define smnBIF_CFG_DEV1_EPF2_2_SLOT_CNTL2_DEFAULT 0x00000000 |
14195 | #define smnBIF_CFG_DEV1_EPF2_2_SLOT_STATUS2_DEFAULT 0x00000000 |
14196 | #define smnBIF_CFG_DEV1_EPF2_2_MSI_CAP_LIST_DEFAULT 0x0000c000 |
14197 | #define smnBIF_CFG_DEV1_EPF2_2_MSI_MSG_CNTL_DEFAULT 0x00000080 |
14198 | #define smnBIF_CFG_DEV1_EPF2_2_MSI_MSG_ADDR_LO_DEFAULT 0x00000000 |
14199 | #define smnBIF_CFG_DEV1_EPF2_2_MSI_MSG_ADDR_HI_DEFAULT 0x00000000 |
14200 | #define smnBIF_CFG_DEV1_EPF2_2_MSI_MSG_DATA_DEFAULT 0x00000000 |
14201 | #define smnBIF_CFG_DEV1_EPF2_2_MSI_MASK_DEFAULT 0x00000000 |
14202 | #define smnBIF_CFG_DEV1_EPF2_2_MSI_MSG_DATA_64_DEFAULT 0x00000000 |
14203 | #define smnBIF_CFG_DEV1_EPF2_2_MSI_MASK_64_DEFAULT 0x00000000 |
14204 | #define smnBIF_CFG_DEV1_EPF2_2_MSI_PENDING_DEFAULT 0x00000000 |
14205 | #define smnBIF_CFG_DEV1_EPF2_2_MSI_PENDING_64_DEFAULT 0x00000000 |
14206 | #define smnBIF_CFG_DEV1_EPF2_2_MSIX_CAP_LIST_DEFAULT 0x00000000 |
14207 | #define smnBIF_CFG_DEV1_EPF2_2_MSIX_MSG_CNTL_DEFAULT 0x00000000 |
14208 | #define smnBIF_CFG_DEV1_EPF2_2_MSIX_TABLE_DEFAULT 0x00000000 |
14209 | #define smnBIF_CFG_DEV1_EPF2_2_MSIX_PBA_DEFAULT 0x00000000 |
14210 | #define smnBIF_CFG_DEV1_EPF2_2_SATA_CAP_0_DEFAULT 0x00000000 |
14211 | #define smnBIF_CFG_DEV1_EPF2_2_SATA_CAP_1_DEFAULT 0x00000000 |
14212 | #define smnBIF_CFG_DEV1_EPF2_2_SATA_IDP_INDEX_DEFAULT 0x00000000 |
14213 | #define smnBIF_CFG_DEV1_EPF2_2_SATA_IDP_DATA_DEFAULT 0x00000000 |
14214 | #define smnBIF_CFG_DEV1_EPF2_2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 |
14215 | #define smnBIF_CFG_DEV1_EPF2_2_PCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 |
14216 | #define smnBIF_CFG_DEV1_EPF2_2_PCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 |
14217 | #define smnBIF_CFG_DEV1_EPF2_2_PCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 |
14218 | #define smnBIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 |
14219 | #define smnBIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 |
14220 | #define smnBIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 |
14221 | #define smnBIF_CFG_DEV1_EPF2_2_PCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 |
14222 | #define smnBIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 |
14223 | #define smnBIF_CFG_DEV1_EPF2_2_PCIE_CORR_ERR_MASK_DEFAULT 0x00002000 |
14224 | #define smnBIF_CFG_DEV1_EPF2_2_PCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 |
14225 | #define smnBIF_CFG_DEV1_EPF2_2_PCIE_HDR_LOG0_DEFAULT 0x00000000 |
14226 | #define smnBIF_CFG_DEV1_EPF2_2_PCIE_HDR_LOG1_DEFAULT 0x00000000 |
14227 | #define smnBIF_CFG_DEV1_EPF2_2_PCIE_HDR_LOG2_DEFAULT 0x00000000 |
14228 | #define smnBIF_CFG_DEV1_EPF2_2_PCIE_HDR_LOG3_DEFAULT 0x00000000 |
14229 | #define smnBIF_CFG_DEV1_EPF2_2_PCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 |
14230 | #define smnBIF_CFG_DEV1_EPF2_2_PCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 |
14231 | #define smnBIF_CFG_DEV1_EPF2_2_PCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 |
14232 | #define smnBIF_CFG_DEV1_EPF2_2_PCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 |
14233 | #define smnBIF_CFG_DEV1_EPF2_2_PCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000 |
14234 | #define smnBIF_CFG_DEV1_EPF2_2_PCIE_BAR1_CAP_DEFAULT 0x00000000 |
14235 | #define smnBIF_CFG_DEV1_EPF2_2_PCIE_BAR1_CNTL_DEFAULT 0x00000020 |
14236 | #define smnBIF_CFG_DEV1_EPF2_2_PCIE_BAR2_CAP_DEFAULT 0x00000000 |
14237 | #define smnBIF_CFG_DEV1_EPF2_2_PCIE_BAR2_CNTL_DEFAULT 0x00000000 |
14238 | #define smnBIF_CFG_DEV1_EPF2_2_PCIE_BAR3_CAP_DEFAULT 0x00000000 |
14239 | #define smnBIF_CFG_DEV1_EPF2_2_PCIE_BAR3_CNTL_DEFAULT 0x00000000 |
14240 | #define smnBIF_CFG_DEV1_EPF2_2_PCIE_BAR4_CAP_DEFAULT 0x00000000 |
14241 | #define smnBIF_CFG_DEV1_EPF2_2_PCIE_BAR4_CNTL_DEFAULT 0x00000000 |
14242 | #define smnBIF_CFG_DEV1_EPF2_2_PCIE_BAR5_CAP_DEFAULT 0x00000000 |
14243 | #define smnBIF_CFG_DEV1_EPF2_2_PCIE_BAR5_CNTL_DEFAULT 0x00000000 |
14244 | #define smnBIF_CFG_DEV1_EPF2_2_PCIE_BAR6_CAP_DEFAULT 0x00000000 |
14245 | #define smnBIF_CFG_DEV1_EPF2_2_PCIE_BAR6_CNTL_DEFAULT 0x00000000 |
14246 | #define smnBIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000 |
14247 | #define smnBIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000 |
14248 | #define smnBIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000 |
14249 | #define smnBIF_CFG_DEV1_EPF2_2_PCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000 |
14250 | #define smnBIF_CFG_DEV1_EPF2_2_PCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000 |
14251 | #define smnBIF_CFG_DEV1_EPF2_2_PCIE_DPA_CAP_DEFAULT 0x00000000 |
14252 | #define smnBIF_CFG_DEV1_EPF2_2_PCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000 |
14253 | #define smnBIF_CFG_DEV1_EPF2_2_PCIE_DPA_STATUS_DEFAULT 0x00000100 |
14254 | #define smnBIF_CFG_DEV1_EPF2_2_PCIE_DPA_CNTL_DEFAULT 0x00000000 |
14255 | #define smnBIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000 |
14256 | #define smnBIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000 |
14257 | #define smnBIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000 |
14258 | #define smnBIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000 |
14259 | #define smnBIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000 |
14260 | #define smnBIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000 |
14261 | #define smnBIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000 |
14262 | #define smnBIF_CFG_DEV1_EPF2_2_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000 |
14263 | #define smnBIF_CFG_DEV1_EPF2_2_PCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000 |
14264 | #define smnBIF_CFG_DEV1_EPF2_2_PCIE_ACS_CAP_DEFAULT 0x00000000 |
14265 | #define smnBIF_CFG_DEV1_EPF2_2_PCIE_ACS_CNTL_DEFAULT 0x00000000 |
14266 | #define smnBIF_CFG_DEV1_EPF2_2_PCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000 |
14267 | #define smnBIF_CFG_DEV1_EPF2_2_PCIE_ARI_CAP_DEFAULT 0x00000000 |
14268 | #define smnBIF_CFG_DEV1_EPF2_2_PCIE_ARI_CNTL_DEFAULT 0x00000000 |
14269 | |
14270 | |
14271 | // addressBlock: nbio_nbif0_bif_bx_pf_SYSPFVFDEC |
14272 | #define smnBIF_BX_PF1_MM_INDEX_DEFAULT 0x00000000 |
14273 | #define smnBIF_BX_PF1_MM_DATA_DEFAULT 0x00000000 |
14274 | #define smnBIF_BX_PF1_MM_INDEX_HI_DEFAULT 0x00000000 |
14275 | |
14276 | |
14277 | // addressBlock: nbio_nbif0_bif_bx_pf_SYSDEC |
14278 | #define smnBIF_BX_PF1_SYSHUB_INDEX_OVLP_DEFAULT 0x00000000 |
14279 | #define smnBIF_BX_PF1_SYSHUB_DATA_OVLP_DEFAULT 0x00000000 |
14280 | #define smnBIF_BX_PF1_PCIE_INDEX_DEFAULT 0x00000000 |
14281 | #define smnBIF_BX_PF1_PCIE_DATA_DEFAULT 0x00000000 |
14282 | #define smnBIF_BX_PF1_PCIE_INDEX2_DEFAULT 0x00000000 |
14283 | #define smnBIF_BX_PF1_PCIE_DATA2_DEFAULT 0x00000000 |
14284 | #define smnBIF_BX_PF1_SBIOS_SCRATCH_0_DEFAULT 0x00000000 |
14285 | #define smnBIF_BX_PF1_SBIOS_SCRATCH_1_DEFAULT 0x00000000 |
14286 | #define smnBIF_BX_PF1_SBIOS_SCRATCH_2_DEFAULT 0x00000000 |
14287 | #define smnBIF_BX_PF1_SBIOS_SCRATCH_3_DEFAULT 0x00000000 |
14288 | #define smnBIF_BX_PF1_BIOS_SCRATCH_0_DEFAULT 0x00000000 |
14289 | #define smnBIF_BX_PF1_BIOS_SCRATCH_1_DEFAULT 0x00000000 |
14290 | #define smnBIF_BX_PF1_BIOS_SCRATCH_2_DEFAULT 0x00000000 |
14291 | #define smnBIF_BX_PF1_BIOS_SCRATCH_3_DEFAULT 0x00000000 |
14292 | #define smnBIF_BX_PF1_BIOS_SCRATCH_4_DEFAULT 0x00000000 |
14293 | #define smnBIF_BX_PF1_BIOS_SCRATCH_5_DEFAULT 0x00000000 |
14294 | #define smnBIF_BX_PF1_BIOS_SCRATCH_6_DEFAULT 0x00000000 |
14295 | #define smnBIF_BX_PF1_BIOS_SCRATCH_7_DEFAULT 0x00000000 |
14296 | #define smnBIF_BX_PF1_BIOS_SCRATCH_8_DEFAULT 0x00000000 |
14297 | #define smnBIF_BX_PF1_BIOS_SCRATCH_9_DEFAULT 0x00000000 |
14298 | #define smnBIF_BX_PF1_BIOS_SCRATCH_10_DEFAULT 0x00000000 |
14299 | #define smnBIF_BX_PF1_BIOS_SCRATCH_11_DEFAULT 0x00000000 |
14300 | #define smnBIF_BX_PF1_BIOS_SCRATCH_12_DEFAULT 0x00000000 |
14301 | #define smnBIF_BX_PF1_BIOS_SCRATCH_13_DEFAULT 0x00000000 |
14302 | #define smnBIF_BX_PF1_BIOS_SCRATCH_14_DEFAULT 0x00000000 |
14303 | #define smnBIF_BX_PF1_BIOS_SCRATCH_15_DEFAULT 0x00000000 |
14304 | #define smnBIF_BX_PF1_BIF_RLC_INTR_CNTL_DEFAULT 0x00000000 |
14305 | #define smnBIF_BX_PF1_BIF_VCE_INTR_CNTL_DEFAULT 0x00000000 |
14306 | #define smnBIF_BX_PF1_BIF_UVD_INTR_CNTL_DEFAULT 0x00000000 |
14307 | #define smnBIF_BX_PF1_GFX_MMIOREG_CAM_ADDR0_DEFAULT 0x00000000 |
14308 | #define smnBIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR0_DEFAULT 0x00000000 |
14309 | #define smnBIF_BX_PF1_GFX_MMIOREG_CAM_ADDR1_DEFAULT 0x00000000 |
14310 | #define smnBIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR1_DEFAULT 0x00000000 |
14311 | #define smnBIF_BX_PF1_GFX_MMIOREG_CAM_ADDR2_DEFAULT 0x00000000 |
14312 | #define smnBIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR2_DEFAULT 0x00000000 |
14313 | #define smnBIF_BX_PF1_GFX_MMIOREG_CAM_ADDR3_DEFAULT 0x00000000 |
14314 | #define smnBIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR3_DEFAULT 0x00000000 |
14315 | #define smnBIF_BX_PF1_GFX_MMIOREG_CAM_ADDR4_DEFAULT 0x00000000 |
14316 | #define smnBIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR4_DEFAULT 0x00000000 |
14317 | #define smnBIF_BX_PF1_GFX_MMIOREG_CAM_ADDR5_DEFAULT 0x00000000 |
14318 | #define smnBIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR5_DEFAULT 0x00000000 |
14319 | #define smnBIF_BX_PF1_GFX_MMIOREG_CAM_ADDR6_DEFAULT 0x00000000 |
14320 | #define smnBIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR6_DEFAULT 0x00000000 |
14321 | #define smnBIF_BX_PF1_GFX_MMIOREG_CAM_ADDR7_DEFAULT 0x00000000 |
14322 | #define smnBIF_BX_PF1_GFX_MMIOREG_CAM_REMAP_ADDR7_DEFAULT 0x00000000 |
14323 | #define smnBIF_BX_PF1_GFX_MMIOREG_CAM_CNTL_DEFAULT 0x00000000 |
14324 | #define smnBIF_BX_PF1_GFX_MMIOREG_CAM_ZERO_CPL_DEFAULT 0x00000000 |
14325 | #define smnBIF_BX_PF1_GFX_MMIOREG_CAM_ONE_CPL_DEFAULT 0x00000000 |
14326 | #define smnBIF_BX_PF1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL_DEFAULT 0x00000000 |
14327 | |
14328 | |
14329 | // addressBlock: nbio_nbif0_syshub_mmreg_ind_syshubdec |
14330 | #define smnSYSHUB_MMREG_IND0_SYSHUB_INDEX_DEFAULT 0x00000000 |
14331 | #define smnSYSHUB_MMREG_IND0_SYSHUB_DATA_DEFAULT 0x00000000 |
14332 | |
14333 | |
14334 | // addressBlock: nbio_nbif0_rcc_strap_BIFDEC1 |
14335 | #define smnRCC_STRAP2_RCC_DEV0_EPF0_STRAP0_DEFAULT 0x300015dd |
14336 | |
14337 | |
14338 | // addressBlock: nbio_nbif0_rcc_ep_dev0_BIFDEC1 |
14339 | #define smnRCC_EP_DEV0_2_EP_PCIE_SCRATCH_DEFAULT 0x00000000 |
14340 | #define smnRCC_EP_DEV0_2_EP_PCIE_CNTL_DEFAULT 0x00000100 |
14341 | #define smnRCC_EP_DEV0_2_EP_PCIE_INT_CNTL_DEFAULT 0x00000000 |
14342 | #define smnRCC_EP_DEV0_2_EP_PCIE_INT_STATUS_DEFAULT 0x00000000 |
14343 | #define smnRCC_EP_DEV0_2_EP_PCIE_RX_CNTL2_DEFAULT 0x00000000 |
14344 | #define smnRCC_EP_DEV0_2_EP_PCIE_BUS_CNTL_DEFAULT 0x00000080 |
14345 | #define smnRCC_EP_DEV0_2_EP_PCIE_CFG_CNTL_DEFAULT 0x00000000 |
14346 | #define smnRCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL_DEFAULT 0x00007468 |
14347 | #define smnRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x000000fa |
14348 | #define smnRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x000000c8 |
14349 | #define smnRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000096 |
14350 | #define smnRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000064 |
14351 | #define smnRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x0000004b |
14352 | #define smnRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000032 |
14353 | #define smnRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000019 |
14354 | #define smnRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x0000000a |
14355 | #define smnRCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP_DEFAULT 0x190a1000 |
14356 | #define smnRCC_EP_DEV0_2_EP_PCIE_F0_DPA_LATENCY_INDICATOR_DEFAULT 0x000000f0 |
14357 | #define smnRCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL_DEFAULT 0x00000100 |
14358 | #define smnRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x000000fa |
14359 | #define smnRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x000000c8 |
14360 | #define smnRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000096 |
14361 | #define smnRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000064 |
14362 | #define smnRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x0000004b |
14363 | #define smnRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000032 |
14364 | #define smnRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000019 |
14365 | #define smnRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x0000000a |
14366 | #define smnRCC_EP_DEV0_2_EP_PCIE_PME_CONTROL_DEFAULT 0x00000000 |
14367 | #define smnRCC_EP_DEV0_2_EP_PCIEP_RESERVED_DEFAULT 0x00000000 |
14368 | #define smnRCC_EP_DEV0_2_EP_PCIE_TX_CNTL_DEFAULT 0x00000000 |
14369 | #define smnRCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID_DEFAULT 0x00000000 |
14370 | #define smnRCC_EP_DEV0_2_EP_PCIE_ERR_CNTL_DEFAULT 0x00000500 |
14371 | #define smnRCC_EP_DEV0_2_EP_PCIE_RX_CNTL_DEFAULT 0x01000000 |
14372 | #define smnRCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL_DEFAULT 0x00000000 |
14373 | |
14374 | |
14375 | // addressBlock: nbio_nbif0_rcc_dwn_dev0_BIFDEC1 |
14376 | #define smnRCC_DWN_DEV0_2_DN_PCIE_RESERVED_DEFAULT 0x00000000 |
14377 | #define smnRCC_DWN_DEV0_2_DN_PCIE_SCRATCH_DEFAULT 0x00000000 |
14378 | #define smnRCC_DWN_DEV0_2_DN_PCIE_CNTL_DEFAULT 0x00000000 |
14379 | #define smnRCC_DWN_DEV0_2_DN_PCIE_CONFIG_CNTL_DEFAULT 0x00000000 |
14380 | #define smnRCC_DWN_DEV0_2_DN_PCIE_RX_CNTL2_DEFAULT 0x00000000 |
14381 | #define smnRCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL_DEFAULT 0x00000080 |
14382 | #define smnRCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL_DEFAULT 0x00000000 |
14383 | |
14384 | |
14385 | // addressBlock: nbio_nbif0_rcc_dwnp_dev0_BIFDEC1 |
14386 | #define smnRCC_DWNP_DEV0_2_PCIE_ERR_CNTL_DEFAULT 0x00000500 |
14387 | #define smnRCC_DWNP_DEV0_2_PCIE_RX_CNTL_DEFAULT 0x00000000 |
14388 | #define smnRCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL_DEFAULT 0x00000000 |
14389 | #define smnRCC_DWNP_DEV0_2_PCIE_LC_CNTL2_DEFAULT 0x00000000 |
14390 | #define smnRCC_DWNP_DEV0_2_PCIEP_STRAP_MISC_DEFAULT 0x00000000 |
14391 | #define smnRCC_DWNP_DEV0_2_LTR_MSG_INFO_FROM_EP_DEFAULT 0x00000000 |
14392 | |
14393 | |
14394 | // addressBlock: nbio_nbif0_bif_bx_pf_BIFDEC1 |
14395 | #define smnBIF_BX_PF1_BIF_MM_INDACCESS_CNTL_DEFAULT 0x00000000 |
14396 | #define smnBIF_BX_PF1_BUS_CNTL_DEFAULT 0x00000000 |
14397 | #define smnBIF_BX_PF1_BIF_SCRATCH0_DEFAULT 0x00000000 |
14398 | #define smnBIF_BX_PF1_BIF_SCRATCH1_DEFAULT 0x00000000 |
14399 | #define smnBIF_BX_PF1_BX_RESET_EN_DEFAULT 0x00010003 |
14400 | #define smnBIF_BX_PF1_MM_CFGREGS_CNTL_DEFAULT 0x00000000 |
14401 | #define smnBIF_BX_PF1_BX_RESET_CNTL_DEFAULT 0x00000000 |
14402 | #define smnBIF_BX_PF1_INTERRUPT_CNTL_DEFAULT 0x00000000 |
14403 | #define smnBIF_BX_PF1_INTERRUPT_CNTL2_DEFAULT 0x00000000 |
14404 | #define smnBIF_BX_PF1_CLKREQB_PAD_CNTL_DEFAULT 0x000008e0 |
14405 | #define smnBIF_BX_PF1_BIF_FEATURES_CONTROL_MISC_DEFAULT 0x00000000 |
14406 | #define smnBIF_BX_PF1_BIF_DOORBELL_CNTL_DEFAULT 0x00000000 |
14407 | #define smnBIF_BX_PF1_BIF_DOORBELL_INT_CNTL_DEFAULT 0x00000000 |
14408 | #define smnBIF_BX_PF1_BIF_FB_EN_DEFAULT 0x00000000 |
14409 | #define smnBIF_BX_PF1_BIF_BUSY_DELAY_CNTR_DEFAULT 0x0000003f |
14410 | #define smnBIF_BX_PF1_BIF_MST_TRANS_PENDING_VF_DEFAULT 0x00000000 |
14411 | #define smnBIF_BX_PF1_BIF_SLV_TRANS_PENDING_VF_DEFAULT 0x00000000 |
14412 | #define smnBIF_BX_PF1_BACO_CNTL_DEFAULT 0x00000000 |
14413 | #define smnBIF_BX_PF1_BIF_BACO_EXIT_TIME0_DEFAULT 0x00000100 |
14414 | #define smnBIF_BX_PF1_BIF_BACO_EXIT_TIMER1_DEFAULT 0x00000200 |
14415 | #define smnBIF_BX_PF1_BIF_BACO_EXIT_TIMER2_DEFAULT 0x00000300 |
14416 | #define smnBIF_BX_PF1_BIF_BACO_EXIT_TIMER3_DEFAULT 0x00000500 |
14417 | #define smnBIF_BX_PF1_BIF_BACO_EXIT_TIMER4_DEFAULT 0x00000400 |
14418 | #define smnBIF_BX_PF1_MEM_TYPE_CNTL_DEFAULT 0x00000000 |
14419 | #define smnBIF_BX_PF1_SMU_BIF_VDDGFX_PWR_STATUS_DEFAULT 0x00000000 |
14420 | #define smnBIF_BX_PF1_BIF_VDDGFX_GFX0_LOWER_DEFAULT 0xc0008000 |
14421 | #define smnBIF_BX_PF1_BIF_VDDGFX_GFX0_UPPER_DEFAULT 0x0000cffc |
14422 | #define smnBIF_BX_PF1_BIF_VDDGFX_GFX1_LOWER_DEFAULT 0xc0028000 |
14423 | #define smnBIF_BX_PF1_BIF_VDDGFX_GFX1_UPPER_DEFAULT 0x00031ffc |
14424 | #define smnBIF_BX_PF1_BIF_VDDGFX_GFX2_LOWER_DEFAULT 0xc0034000 |
14425 | #define smnBIF_BX_PF1_BIF_VDDGFX_GFX2_UPPER_DEFAULT 0x00037ffc |
14426 | #define smnBIF_BX_PF1_BIF_VDDGFX_GFX3_LOWER_DEFAULT 0xc003c000 |
14427 | #define smnBIF_BX_PF1_BIF_VDDGFX_GFX3_UPPER_DEFAULT 0x0003e1fc |
14428 | #define smnBIF_BX_PF1_BIF_VDDGFX_GFX4_LOWER_DEFAULT 0xc003ec00 |
14429 | #define smnBIF_BX_PF1_BIF_VDDGFX_GFX4_UPPER_DEFAULT 0x0003f1fc |
14430 | #define smnBIF_BX_PF1_BIF_VDDGFX_GFX5_LOWER_DEFAULT 0xc003fc00 |
14431 | #define smnBIF_BX_PF1_BIF_VDDGFX_GFX5_UPPER_DEFAULT 0x0003fffc |
14432 | #define smnBIF_BX_PF1_BIF_VDDGFX_RSV1_LOWER_DEFAULT 0x00000000 |
14433 | #define smnBIF_BX_PF1_BIF_VDDGFX_RSV1_UPPER_DEFAULT 0x00000000 |
14434 | #define smnBIF_BX_PF1_BIF_VDDGFX_RSV2_LOWER_DEFAULT 0x00000000 |
14435 | #define smnBIF_BX_PF1_BIF_VDDGFX_RSV2_UPPER_DEFAULT 0x00000000 |
14436 | #define smnBIF_BX_PF1_BIF_VDDGFX_RSV3_LOWER_DEFAULT 0x00000000 |
14437 | #define smnBIF_BX_PF1_BIF_VDDGFX_RSV3_UPPER_DEFAULT 0x00000000 |
14438 | #define smnBIF_BX_PF1_BIF_VDDGFX_RSV4_LOWER_DEFAULT 0x00000000 |
14439 | #define smnBIF_BX_PF1_BIF_VDDGFX_RSV4_UPPER_DEFAULT 0x00000000 |
14440 | #define smnBIF_BX_PF1_BIF_VDDGFX_FB_CMP_DEFAULT 0x00000000 |
14441 | #define smnBIF_BX_PF1_BIF_DOORBELL_GBLAPER1_LOWER_DEFAULT 0x80000780 |
14442 | #define smnBIF_BX_PF1_BIF_DOORBELL_GBLAPER1_UPPER_DEFAULT 0x000007fc |
14443 | #define smnBIF_BX_PF1_BIF_DOORBELL_GBLAPER2_LOWER_DEFAULT 0x80000800 |
14444 | #define smnBIF_BX_PF1_BIF_DOORBELL_GBLAPER2_UPPER_DEFAULT 0x0000087c |
14445 | #define smnBIF_BX_PF1_REMAP_HDP_MEM_FLUSH_CNTL_DEFAULT 0x0000385c |
14446 | #define smnBIF_BX_PF1_REMAP_HDP_REG_FLUSH_CNTL_DEFAULT 0x00003858 |
14447 | #define smnBIF_BX_PF1_BIF_RB_CNTL_DEFAULT 0x00000000 |
14448 | #define smnBIF_BX_PF1_BIF_RB_BASE_DEFAULT 0x00000000 |
14449 | #define smnBIF_BX_PF1_BIF_RB_RPTR_DEFAULT 0x00000000 |
14450 | #define smnBIF_BX_PF1_BIF_RB_WPTR_DEFAULT 0x00000000 |
14451 | #define smnBIF_BX_PF1_BIF_RB_WPTR_ADDR_HI_DEFAULT 0x00000000 |
14452 | #define smnBIF_BX_PF1_BIF_RB_WPTR_ADDR_LO_DEFAULT 0x00000000 |
14453 | #define smnBIF_BX_PF1_MAILBOX_INDEX_DEFAULT 0x00000000 |
14454 | #define smnBIF_BX_PF1_BIF_UVD_GPUIOV_CFG_SIZE_DEFAULT 0x00000008 |
14455 | #define smnBIF_BX_PF1_BIF_VCE_GPUIOV_CFG_SIZE_DEFAULT 0x00000008 |
14456 | #define smnBIF_BX_PF1_BIF_GFX_SDMA_GPUIOV_CFG_SIZE_DEFAULT 0x00000008 |
14457 | #define smnBIF_BX_PF1_BIF_PERSTB_PAD_CNTL_DEFAULT 0x000000c0 |
14458 | #define smnBIF_BX_PF1_BIF_PX_EN_PAD_CNTL_DEFAULT 0x00000031 |
14459 | #define smnBIF_BX_PF1_BIF_REFPADKIN_PAD_CNTL_DEFAULT 0x00000007 |
14460 | #define smnBIF_BX_PF1_BIF_CLKREQB_PAD_CNTL_DEFAULT 0x00600100 |
14461 | |
14462 | |
14463 | // addressBlock: nbio_nbif0_bif_bx_pf_BIFPFVFDEC1 |
14464 | #define smnBIF_BX_PF1_BIF_BME_STATUS_DEFAULT 0x00000000 |
14465 | #define smnBIF_BX_PF1_BIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000 |
14466 | #define smnBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000 |
14467 | #define smnBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000 |
14468 | #define smnBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100 |
14469 | #define smnBIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 |
14470 | #define smnBIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 |
14471 | #define smnBIF_BX_PF1_GPU_HDP_FLUSH_REQ_DEFAULT 0x00000000 |
14472 | #define smnBIF_BX_PF1_GPU_HDP_FLUSH_DONE_DEFAULT 0x00000000 |
14473 | #define smnBIF_BX_PF1_BIF_TRANS_PENDING_DEFAULT 0x00000000 |
14474 | #define smnBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000 |
14475 | #define smnBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000 |
14476 | #define smnBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000 |
14477 | #define smnBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000 |
14478 | #define smnBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000 |
14479 | #define smnBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000 |
14480 | #define smnBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000 |
14481 | #define smnBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000 |
14482 | #define smnBIF_BX_PF1_MAILBOX_CONTROL_DEFAULT 0x00000000 |
14483 | #define smnBIF_BX_PF1_MAILBOX_INT_CNTL_DEFAULT 0x00000000 |
14484 | #define smnBIF_BX_PF1_BIF_VMHV_MAILBOX_DEFAULT 0x00000000 |
14485 | |
14486 | |
14487 | // addressBlock: nbio_nbif0_gdc_GDCDEC |
14488 | #define smnGDC1_NGDC_SDP_PORT_CTRL_DEFAULT 0x0000000f |
14489 | #define smnGDC1_SHUB_REGS_IF_CTL_DEFAULT 0x00000000 |
14490 | #define smnGDC1_NGDC_RESERVED_0_DEFAULT 0x00000000 |
14491 | #define smnGDC1_NGDC_RESERVED_1_DEFAULT 0x00000000 |
14492 | #define smnGDC1_NGDC_SDP_PORT_CTRL_SOCCLK_DEFAULT 0x0000000f |
14493 | #define smnGDC1_BIF_SDMA0_DOORBELL_RANGE_DEFAULT 0x00000000 |
14494 | #define smnGDC1_BIF_SDMA1_DOORBELL_RANGE_DEFAULT 0x00000000 |
14495 | #define smnGDC1_BIF_IH_DOORBELL_RANGE_DEFAULT 0x00000000 |
14496 | #define smnGDC1_BIF_MMSCH0_DOORBELL_RANGE_DEFAULT 0x00000000 |
14497 | #define smnGDC1_ATDMA_MISC_CNTL_DEFAULT 0x04040001 |
14498 | #define smnGDC1_BIF_DOORBELL_FENCE_CNTL_DEFAULT 0x00000000 |
14499 | #define smnGDC1_S2A_MISC_CNTL_DEFAULT 0x00000000 |
14500 | #define smnGDC1_GDC_PG_MISC_CNTL_DEFAULT 0x00000000 |
14501 | |
14502 | |
14503 | // addressBlock: nbio_nbif0_bif_bx_pf_SYSPFVFDEC |
14504 | #define mmMM_INDEX_DEFAULT 0x00000000 |
14505 | #define mmMM_DATA_DEFAULT 0x00000000 |
14506 | #define mmMM_INDEX_HI_DEFAULT 0x00000000 |
14507 | |
14508 | |
14509 | // addressBlock: nbio_nbif0_bif_bx_pf_SYSDEC |
14510 | #define mmSYSHUB_INDEX_OVLP_DEFAULT 0x00000000 |
14511 | #define mmSYSHUB_DATA_OVLP_DEFAULT 0x00000000 |
14512 | #define mmPCIE_INDEX_DEFAULT 0x00000000 |
14513 | #define mmPCIE_DATA_DEFAULT 0x00000000 |
14514 | #define mmPCIE_INDEX2_DEFAULT 0x00000000 |
14515 | #define mmPCIE_DATA2_DEFAULT 0x00000000 |
14516 | #define mmSBIOS_SCRATCH_0_DEFAULT 0x00000000 |
14517 | #define mmSBIOS_SCRATCH_1_DEFAULT 0x00000000 |
14518 | #define mmSBIOS_SCRATCH_2_DEFAULT 0x00000000 |
14519 | #define mmSBIOS_SCRATCH_3_DEFAULT 0x00000000 |
14520 | #define mmBIOS_SCRATCH_0_DEFAULT 0x00000000 |
14521 | #define mmBIOS_SCRATCH_1_DEFAULT 0x00000000 |
14522 | #define mmBIOS_SCRATCH_2_DEFAULT 0x00000000 |
14523 | #define mmBIOS_SCRATCH_3_DEFAULT 0x00000000 |
14524 | #define mmBIOS_SCRATCH_4_DEFAULT 0x00000000 |
14525 | #define mmBIOS_SCRATCH_5_DEFAULT 0x00000000 |
14526 | #define mmBIOS_SCRATCH_6_DEFAULT 0x00000000 |
14527 | #define mmBIOS_SCRATCH_7_DEFAULT 0x00000000 |
14528 | #define mmBIOS_SCRATCH_8_DEFAULT 0x00000000 |
14529 | #define mmBIOS_SCRATCH_9_DEFAULT 0x00000000 |
14530 | #define mmBIOS_SCRATCH_10_DEFAULT 0x00000000 |
14531 | #define mmBIOS_SCRATCH_11_DEFAULT 0x00000000 |
14532 | #define mmBIOS_SCRATCH_12_DEFAULT 0x00000000 |
14533 | #define mmBIOS_SCRATCH_13_DEFAULT 0x00000000 |
14534 | #define mmBIOS_SCRATCH_14_DEFAULT 0x00000000 |
14535 | #define mmBIOS_SCRATCH_15_DEFAULT 0x00000000 |
14536 | #define mmBIF_RLC_INTR_CNTL_DEFAULT 0x00000000 |
14537 | #define mmBIF_VCE_INTR_CNTL_DEFAULT 0x00000000 |
14538 | #define mmBIF_UVD_INTR_CNTL_DEFAULT 0x00000000 |
14539 | #define mmGFX_MMIOREG_CAM_ADDR0_DEFAULT 0x00000000 |
14540 | #define mmGFX_MMIOREG_CAM_REMAP_ADDR0_DEFAULT 0x00000000 |
14541 | #define mmGFX_MMIOREG_CAM_ADDR1_DEFAULT 0x00000000 |
14542 | #define mmGFX_MMIOREG_CAM_REMAP_ADDR1_DEFAULT 0x00000000 |
14543 | #define mmGFX_MMIOREG_CAM_ADDR2_DEFAULT 0x00000000 |
14544 | #define mmGFX_MMIOREG_CAM_REMAP_ADDR2_DEFAULT 0x00000000 |
14545 | #define mmGFX_MMIOREG_CAM_ADDR3_DEFAULT 0x00000000 |
14546 | #define mmGFX_MMIOREG_CAM_REMAP_ADDR3_DEFAULT 0x00000000 |
14547 | #define mmGFX_MMIOREG_CAM_ADDR4_DEFAULT 0x00000000 |
14548 | #define mmGFX_MMIOREG_CAM_REMAP_ADDR4_DEFAULT 0x00000000 |
14549 | #define mmGFX_MMIOREG_CAM_ADDR5_DEFAULT 0x00000000 |
14550 | #define mmGFX_MMIOREG_CAM_REMAP_ADDR5_DEFAULT 0x00000000 |
14551 | #define mmGFX_MMIOREG_CAM_ADDR6_DEFAULT 0x00000000 |
14552 | #define mmGFX_MMIOREG_CAM_REMAP_ADDR6_DEFAULT 0x00000000 |
14553 | #define mmGFX_MMIOREG_CAM_ADDR7_DEFAULT 0x00000000 |
14554 | #define mmGFX_MMIOREG_CAM_REMAP_ADDR7_DEFAULT 0x00000000 |
14555 | #define mmGFX_MMIOREG_CAM_CNTL_DEFAULT 0x00000000 |
14556 | #define mmGFX_MMIOREG_CAM_ZERO_CPL_DEFAULT 0x00000000 |
14557 | #define mmGFX_MMIOREG_CAM_ONE_CPL_DEFAULT 0x00000000 |
14558 | #define mmGFX_MMIOREG_CAM_PROGRAMMABLE_CPL_DEFAULT 0x00000000 |
14559 | |
14560 | |
14561 | // addressBlock: nbio_nbif0_syshub_mmreg_ind_syshubdec |
14562 | #define mmSYSHUB_INDEX_DEFAULT 0x00000000 |
14563 | #define mmSYSHUB_DATA_DEFAULT 0x00000000 |
14564 | |
14565 | |
14566 | // addressBlock: nbio_nbif0_rcc_strap_BIFDEC1 |
14567 | #define mmRCC_DEV0_EPF0_STRAP0_DEFAULT 0x300015dd |
14568 | |
14569 | |
14570 | // addressBlock: nbio_nbif0_rcc_ep_dev0_BIFDEC1 |
14571 | #define mmEP_PCIE_SCRATCH_DEFAULT 0x00000000 |
14572 | #define mmEP_PCIE_CNTL_DEFAULT 0x00000100 |
14573 | #define mmEP_PCIE_INT_CNTL_DEFAULT 0x00000000 |
14574 | #define mmEP_PCIE_INT_STATUS_DEFAULT 0x00000000 |
14575 | #define mmEP_PCIE_RX_CNTL2_DEFAULT 0x00000000 |
14576 | #define mmEP_PCIE_BUS_CNTL_DEFAULT 0x00000080 |
14577 | #define mmEP_PCIE_CFG_CNTL_DEFAULT 0x00000000 |
14578 | #define mmEP_PCIE_TX_LTR_CNTL_DEFAULT 0x00007468 |
14579 | #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x000000fa |
14580 | #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x000000c8 |
14581 | #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000096 |
14582 | #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000064 |
14583 | #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x0000004b |
14584 | #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000032 |
14585 | #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000019 |
14586 | #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x0000000a |
14587 | #define mmEP_PCIE_F0_DPA_CAP_DEFAULT 0x190a1000 |
14588 | #define mmEP_PCIE_F0_DPA_LATENCY_INDICATOR_DEFAULT 0x000000f0 |
14589 | #define mmEP_PCIE_F0_DPA_CNTL_DEFAULT 0x00000100 |
14590 | #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x000000fa |
14591 | #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x000000c8 |
14592 | #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000096 |
14593 | #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000064 |
14594 | #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x0000004b |
14595 | #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000032 |
14596 | #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000019 |
14597 | #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x0000000a |
14598 | #define mmEP_PCIE_PME_CONTROL_DEFAULT 0x00000000 |
14599 | #define mmEP_PCIEP_RESERVED_DEFAULT 0x00000000 |
14600 | #define mmEP_PCIE_TX_CNTL_DEFAULT 0x00000000 |
14601 | #define mmEP_PCIE_TX_REQUESTER_ID_DEFAULT 0x00000000 |
14602 | #define mmEP_PCIE_ERR_CNTL_DEFAULT 0x00000500 |
14603 | #define mmEP_PCIE_RX_CNTL_DEFAULT 0x01000000 |
14604 | #define mmEP_PCIE_LC_SPEED_CNTL_DEFAULT 0x00000000 |
14605 | |
14606 | |
14607 | // addressBlock: nbio_nbif0_rcc_dwn_dev0_BIFDEC1 |
14608 | #define mmDN_PCIE_RESERVED_DEFAULT 0x00000000 |
14609 | #define mmDN_PCIE_SCRATCH_DEFAULT 0x00000000 |
14610 | #define mmDN_PCIE_CNTL_DEFAULT 0x00000000 |
14611 | #define mmDN_PCIE_CONFIG_CNTL_DEFAULT 0x00000000 |
14612 | #define mmDN_PCIE_RX_CNTL2_DEFAULT 0x00000000 |
14613 | #define mmDN_PCIE_BUS_CNTL_DEFAULT 0x00000080 |
14614 | #define mmDN_PCIE_CFG_CNTL_DEFAULT 0x00000000 |
14615 | |
14616 | |
14617 | // addressBlock: nbio_nbif0_rcc_dwnp_dev0_BIFDEC1 |
14618 | #define mmPCIE_ERR_CNTL_DEFAULT 0x00000500 |
14619 | #define mmPCIE_RX_CNTL_DEFAULT 0x00000000 |
14620 | #define mmPCIE_LC_SPEED_CNTL_DEFAULT 0x00000000 |
14621 | #define mmPCIE_LC_CNTL2_DEFAULT 0x00000000 |
14622 | #define mmPCIEP_STRAP_MISC_DEFAULT 0x00000000 |
14623 | #define mmLTR_MSG_INFO_FROM_EP_DEFAULT 0x00000000 |
14624 | |
14625 | |
14626 | // addressBlock: nbio_nbif0_rcc_dev0_BIFPFVFDEC1 |
14627 | #define mmRCC_ERR_LOG_DEFAULT 0x00000000 |
14628 | #define mmRCC_DOORBELL_APER_EN_DEFAULT 0x00000000 |
14629 | #define mmRCC_CONFIG_MEMSIZE_DEFAULT 0x00000000 |
14630 | #define mmRCC_CONFIG_RESERVED_DEFAULT 0x00000000 |
14631 | #define mmRCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000 |
14632 | |
14633 | |
14634 | // addressBlock: nbio_nbif0_rcc_dev0_BIFDEC1 |
14635 | #define mmRCC_ERR_INT_CNTL_DEFAULT 0x00000000 |
14636 | #define mmRCC_BACO_CNTL_MISC_DEFAULT 0x00000000 |
14637 | #define mmRCC_RESET_EN_DEFAULT 0x00008000 |
14638 | #define mmRCC_VDM_SUPPORT_DEFAULT 0x00000000 |
14639 | #define mmRCC_PEER_REG_RANGE0_DEFAULT 0xffff0000 |
14640 | #define mmRCC_PEER_REG_RANGE1_DEFAULT 0xffff0000 |
14641 | #define mmRCC_BUS_CNTL_DEFAULT 0x00000000 |
14642 | #define mmRCC_CONFIG_CNTL_DEFAULT 0x00000000 |
14643 | #define mmRCC_CONFIG_F0_BASE_DEFAULT 0x00000000 |
14644 | #define mmRCC_CONFIG_APER_SIZE_DEFAULT 0x00000000 |
14645 | #define mmRCC_CONFIG_REG_APER_SIZE_DEFAULT 0x00000000 |
14646 | #define mmRCC_XDMA_LO_DEFAULT 0x00000000 |
14647 | #define mmRCC_XDMA_HI_DEFAULT 0x00000000 |
14648 | #define mmRCC_FEATURES_CONTROL_MISC_DEFAULT 0x00000000 |
14649 | #define mmRCC_BUSNUM_CNTL1_DEFAULT 0x00000000 |
14650 | #define mmRCC_BUSNUM_LIST0_DEFAULT 0x00000000 |
14651 | #define mmRCC_BUSNUM_LIST1_DEFAULT 0x00000000 |
14652 | #define mmRCC_BUSNUM_CNTL2_DEFAULT 0x00000000 |
14653 | #define mmRCC_CAPTURE_HOST_BUSNUM_DEFAULT 0x00000000 |
14654 | #define mmRCC_HOST_BUSNUM_DEFAULT 0x00000000 |
14655 | #define mmRCC_PEER0_FB_OFFSET_HI_DEFAULT 0x00000000 |
14656 | #define mmRCC_PEER0_FB_OFFSET_LO_DEFAULT 0x00000000 |
14657 | #define mmRCC_PEER1_FB_OFFSET_HI_DEFAULT 0x00000000 |
14658 | #define mmRCC_PEER1_FB_OFFSET_LO_DEFAULT 0x00000000 |
14659 | #define mmRCC_PEER2_FB_OFFSET_HI_DEFAULT 0x00000000 |
14660 | #define mmRCC_PEER2_FB_OFFSET_LO_DEFAULT 0x00000000 |
14661 | #define mmRCC_PEER3_FB_OFFSET_HI_DEFAULT 0x00000000 |
14662 | #define mmRCC_PEER3_FB_OFFSET_LO_DEFAULT 0x00000000 |
14663 | #define mmRCC_CMN_LINK_CNTL_DEFAULT 0x00400000 |
14664 | #define mmRCC_EP_REQUESTERID_RESTORE_DEFAULT 0x00000000 |
14665 | #define mmRCC_LTR_LSWITCH_CNTL_DEFAULT 0x00000000 |
14666 | #define mmRCC_MH_ARB_CNTL_DEFAULT 0x00000000 |
14667 | |
14668 | |
14669 | // addressBlock: nbio_nbif0_bif_bx_pf_BIFDEC1 |
14670 | #define mmBIF_MM_INDACCESS_CNTL_DEFAULT 0x00000000 |
14671 | #define mmBUS_CNTL_DEFAULT 0x00000000 |
14672 | #define mmBIF_SCRATCH0_DEFAULT 0x00000000 |
14673 | #define mmBIF_SCRATCH1_DEFAULT 0x00000000 |
14674 | #define mmBX_RESET_EN_DEFAULT 0x00010003 |
14675 | #define mmMM_CFGREGS_CNTL_DEFAULT 0x00000000 |
14676 | #define mmBX_RESET_CNTL_DEFAULT 0x00000000 |
14677 | #define mmINTERRUPT_CNTL_DEFAULT 0x00000000 |
14678 | #define mmINTERRUPT_CNTL2_DEFAULT 0x00000000 |
14679 | #define mmCLKREQB_PAD_CNTL_DEFAULT 0x000008e0 |
14680 | #define mmBIF_FEATURES_CONTROL_MISC_DEFAULT 0x00000000 |
14681 | #define mmBIF_DOORBELL_CNTL_DEFAULT 0x00000000 |
14682 | #define mmBIF_DOORBELL_INT_CNTL_DEFAULT 0x00000000 |
14683 | #define mmBIF_FB_EN_DEFAULT 0x00000000 |
14684 | #define mmBIF_BUSY_DELAY_CNTR_DEFAULT 0x0000003f |
14685 | #define mmBIF_MST_TRANS_PENDING_VF_DEFAULT 0x00000000 |
14686 | #define mmBIF_SLV_TRANS_PENDING_VF_DEFAULT 0x00000000 |
14687 | #define mmBACO_CNTL_DEFAULT 0x00000000 |
14688 | #define mmBIF_BACO_EXIT_TIME0_DEFAULT 0x00000100 |
14689 | #define mmBIF_BACO_EXIT_TIMER1_DEFAULT 0x00000200 |
14690 | #define mmBIF_BACO_EXIT_TIMER2_DEFAULT 0x00000300 |
14691 | #define mmBIF_BACO_EXIT_TIMER3_DEFAULT 0x00000500 |
14692 | #define mmBIF_BACO_EXIT_TIMER4_DEFAULT 0x00000400 |
14693 | #define mmMEM_TYPE_CNTL_DEFAULT 0x00000000 |
14694 | #define mmSMU_BIF_VDDGFX_PWR_STATUS_DEFAULT 0x00000000 |
14695 | #define mmBIF_VDDGFX_GFX0_LOWER_DEFAULT 0xc0008000 |
14696 | #define mmBIF_VDDGFX_GFX0_UPPER_DEFAULT 0x0000cffc |
14697 | #define mmBIF_VDDGFX_GFX1_LOWER_DEFAULT 0xc0028000 |
14698 | #define mmBIF_VDDGFX_GFX1_UPPER_DEFAULT 0x00031ffc |
14699 | #define mmBIF_VDDGFX_GFX2_LOWER_DEFAULT 0xc0034000 |
14700 | #define mmBIF_VDDGFX_GFX2_UPPER_DEFAULT 0x00037ffc |
14701 | #define mmBIF_VDDGFX_GFX3_LOWER_DEFAULT 0xc003c000 |
14702 | #define mmBIF_VDDGFX_GFX3_UPPER_DEFAULT 0x0003e1fc |
14703 | #define mmBIF_VDDGFX_GFX4_LOWER_DEFAULT 0xc003ec00 |
14704 | #define mmBIF_VDDGFX_GFX4_UPPER_DEFAULT 0x0003f1fc |
14705 | #define mmBIF_VDDGFX_GFX5_LOWER_DEFAULT 0xc003fc00 |
14706 | #define mmBIF_VDDGFX_GFX5_UPPER_DEFAULT 0x0003fffc |
14707 | #define mmBIF_VDDGFX_RSV1_LOWER_DEFAULT 0x00000000 |
14708 | #define mmBIF_VDDGFX_RSV1_UPPER_DEFAULT 0x00000000 |
14709 | #define mmBIF_VDDGFX_RSV2_LOWER_DEFAULT 0x00000000 |
14710 | #define mmBIF_VDDGFX_RSV2_UPPER_DEFAULT 0x00000000 |
14711 | #define mmBIF_VDDGFX_RSV3_LOWER_DEFAULT 0x00000000 |
14712 | #define mmBIF_VDDGFX_RSV3_UPPER_DEFAULT 0x00000000 |
14713 | #define mmBIF_VDDGFX_RSV4_LOWER_DEFAULT 0x00000000 |
14714 | #define mmBIF_VDDGFX_RSV4_UPPER_DEFAULT 0x00000000 |
14715 | #define mmBIF_VDDGFX_FB_CMP_DEFAULT 0x00000000 |
14716 | #define mmBIF_DOORBELL_GBLAPER1_LOWER_DEFAULT 0x80000780 |
14717 | #define mmBIF_DOORBELL_GBLAPER1_UPPER_DEFAULT 0x000007fc |
14718 | #define mmBIF_DOORBELL_GBLAPER2_LOWER_DEFAULT 0x80000800 |
14719 | #define mmBIF_DOORBELL_GBLAPER2_UPPER_DEFAULT 0x0000087c |
14720 | #define mmREMAP_HDP_MEM_FLUSH_CNTL_DEFAULT 0x0000385c |
14721 | #define mmREMAP_HDP_REG_FLUSH_CNTL_DEFAULT 0x00003858 |
14722 | #define mmBIF_RB_CNTL_DEFAULT 0x00000000 |
14723 | #define mmBIF_RB_BASE_DEFAULT 0x00000000 |
14724 | #define mmBIF_RB_RPTR_DEFAULT 0x00000000 |
14725 | #define mmBIF_RB_WPTR_DEFAULT 0x00000000 |
14726 | #define mmBIF_RB_WPTR_ADDR_HI_DEFAULT 0x00000000 |
14727 | #define mmBIF_RB_WPTR_ADDR_LO_DEFAULT 0x00000000 |
14728 | #define mmMAILBOX_INDEX_DEFAULT 0x00000000 |
14729 | #define mmBIF_UVD_GPUIOV_CFG_SIZE_DEFAULT 0x00000008 |
14730 | #define mmBIF_VCE_GPUIOV_CFG_SIZE_DEFAULT 0x00000008 |
14731 | #define mmBIF_GFX_SDMA_GPUIOV_CFG_SIZE_DEFAULT 0x00000008 |
14732 | #define mmBIF_PERSTB_PAD_CNTL_DEFAULT 0x000000c0 |
14733 | #define mmBIF_PX_EN_PAD_CNTL_DEFAULT 0x00000031 |
14734 | #define mmBIF_REFPADKIN_PAD_CNTL_DEFAULT 0x00000007 |
14735 | #define mmBIF_CLKREQB_PAD_CNTL_DEFAULT 0x00600100 |
14736 | |
14737 | |
14738 | // addressBlock: nbio_nbif0_bif_bx_pf_BIFPFVFDEC1 |
14739 | #define mmBIF_BME_STATUS_DEFAULT 0x00000000 |
14740 | #define mmBIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000 |
14741 | #define mmDOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000 |
14742 | #define mmDOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000 |
14743 | #define mmDOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000100 |
14744 | #define mmHDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 |
14745 | #define mmHDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 |
14746 | #define mmGPU_HDP_FLUSH_REQ_DEFAULT 0x00000000 |
14747 | #define mmGPU_HDP_FLUSH_DONE_DEFAULT 0x00000000 |
14748 | #define mmBIF_TRANS_PENDING_DEFAULT 0x00000000 |
14749 | #define mmMAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000 |
14750 | #define mmMAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000 |
14751 | #define mmMAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000 |
14752 | #define mmMAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000 |
14753 | #define mmMAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000 |
14754 | #define mmMAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000 |
14755 | #define mmMAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000 |
14756 | #define mmMAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000 |
14757 | #define mmMAILBOX_CONTROL_DEFAULT 0x00000000 |
14758 | #define mmMAILBOX_INT_CNTL_DEFAULT 0x00000000 |
14759 | #define mmBIF_VMHV_MAILBOX_DEFAULT 0x00000000 |
14760 | |
14761 | |
14762 | // addressBlock: nbio_nbif0_gdc_GDCDEC |
14763 | #define mmNGDC_SDP_PORT_CTRL_DEFAULT 0x0000000f |
14764 | #define mmSHUB_REGS_IF_CTL_DEFAULT 0x00000000 |
14765 | #define mmNGDC_RESERVED_0_DEFAULT 0x00000000 |
14766 | #define mmNGDC_RESERVED_1_DEFAULT 0x00000000 |
14767 | #define mmNGDC_SDP_PORT_CTRL_SOCCLK_DEFAULT 0x0000000f |
14768 | #define mmBIF_SDMA0_DOORBELL_RANGE_DEFAULT 0x00000000 |
14769 | #define mmBIF_SDMA1_DOORBELL_RANGE_DEFAULT 0x00000000 |
14770 | #define mmBIF_IH_DOORBELL_RANGE_DEFAULT 0x00000000 |
14771 | #define mmBIF_MMSCH0_DOORBELL_RANGE_DEFAULT 0x00000000 |
14772 | #define mmATDMA_MISC_CNTL_DEFAULT 0x04040001 |
14773 | #define mmBIF_DOORBELL_FENCE_CNTL_DEFAULT 0x00000000 |
14774 | #define mmS2A_MISC_CNTL_DEFAULT 0x00000000 |
14775 | #define mmGDC_PG_MISC_CNTL_DEFAULT 0x00000000 |
14776 | |
14777 | |
14778 | // addressBlock: nbio_nbif0_rcc_dev0_BIFDEC2 |
14779 | #define mmGFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000 |
14780 | #define mmGFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000 |
14781 | #define mmGFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000 |
14782 | #define mmGFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001 |
14783 | #define mmGFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000 |
14784 | #define mmGFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000 |
14785 | #define mmGFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000 |
14786 | #define mmGFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001 |
14787 | #define mmGFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000 |
14788 | #define mmGFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000 |
14789 | #define mmGFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000 |
14790 | #define mmGFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001 |
14791 | #define mmGFXMSIX_PBA_DEFAULT 0x00000000 |
14792 | |
14793 | |
14794 | // addressBlock: syshub_mmreg_ind_syshubind |
14795 | #define ixSYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK_DEFAULT 0x00000000 |
14796 | #define ixSYSHUB_MMREG_IND_SYSHUB_DS_CTRL2_SOCCLK_DEFAULT 0x00000100 |
14797 | #define ixSYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK_DEFAULT 0x00000000 |
14798 | #define ixSYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK_DEFAULT 0x00000000 |
14799 | #define ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL_DEFAULT 0x0000001e |
14800 | #define ixSYSHUB_MMREG_IND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL_DEFAULT 0x0000001e |
14801 | #define ixSYSHUB_MMREG_IND_DMA_CLK0_SW2_SYSHUB_QOS_CNTL_DEFAULT 0x0000001e |
14802 | #define ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL0_CNTL_DEFAULT 0x20200000 |
14803 | #define ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL1_CNTL_DEFAULT 0x20200000 |
14804 | #define ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL2_CNTL_DEFAULT 0x20200000 |
14805 | #define ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL3_CNTL_DEFAULT 0x20200000 |
14806 | #define ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL4_CNTL_DEFAULT 0x20200000 |
14807 | #define ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL5_CNTL_DEFAULT 0x20200000 |
14808 | #define ixSYSHUB_MMREG_IND_DMA_CLK0_SW1_CL0_CNTL_DEFAULT 0x20200000 |
14809 | #define ixSYSHUB_MMREG_IND_DMA_CLK0_SW2_CL0_CNTL_DEFAULT 0x20200000 |
14810 | #define ixSYSHUB_MMREG_IND_HST_CLK0_SW0_CL0_CNTL_DEFAULT 0x00000000 |
14811 | #define ixSYSHUB_MMREG_IND_HST_CLK0_SW0_CL1_CNTL_DEFAULT 0x00000000 |
14812 | #define ixSYSHUB_MMREG_IND_HST_CLK0_SW0_CL2_CNTL_DEFAULT 0x00000000 |
14813 | #define ixSYSHUB_MMREG_IND_HST_CLK0_SW1_CL0_CNTL_DEFAULT 0x00000000 |
14814 | #define ixSYSHUB_MMREG_IND_HST_CLK0_SW1_CL1_CNTL_DEFAULT 0x00000000 |
14815 | #define ixSYSHUB_MMREG_IND_HST_CLK0_SW1_CL2_CNTL_DEFAULT 0x00000000 |
14816 | #define ixSYSHUB_MMREG_IND_HST_CLK0_SW1_CL3_CNTL_DEFAULT 0x00000000 |
14817 | #define ixSYSHUB_MMREG_IND_HST_CLK0_SW1_CL4_CNTL_DEFAULT 0x00000000 |
14818 | #define ixSYSHUB_MMREG_IND_SYSHUB_CG_CNTL_DEFAULT 0x00082000 |
14819 | #define ixSYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE_DEFAULT 0x00000000 |
14820 | #define ixSYSHUB_MMREG_IND_SYSHUB_HP_TIMER_DEFAULT 0x00000100 |
14821 | #define ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK_DEFAULT 0x00000080 |
14822 | #define ixSYSHUB_MMREG_IND_SYSUB_CPF_DOORBELL_RS_RESET_DEFAULT 0x00000000 |
14823 | #define ixSYSHUB_MMREG_IND_SYSHUB_SCRATCH_DEFAULT 0x00000040 |
14824 | #define ixSYSHUB_MMREG_IND_SYSHUB_CL_MASK_DEFAULT 0x00000000 |
14825 | #define ixSYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK_DEFAULT 0x00000000 |
14826 | #define ixSYSHUB_MMREG_IND_SYSHUB_DS_CTRL2_SHUBCLK_DEFAULT 0x00000100 |
14827 | #define ixSYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK_DEFAULT 0x00000000 |
14828 | #define ixSYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK_DEFAULT 0x00000000 |
14829 | #define ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL_DEFAULT 0x0000001e |
14830 | #define ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL_DEFAULT 0x0000001e |
14831 | #define ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_CL0_CNTL_DEFAULT 0x20200000 |
14832 | #define ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_CL1_CNTL_DEFAULT 0x20200000 |
14833 | #define ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_CL2_CNTL_DEFAULT 0x20200000 |
14834 | #define ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_CL3_CNTL_DEFAULT 0x20200000 |
14835 | #define ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_CL4_CNTL_DEFAULT 0x20200000 |
14836 | #define ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_CL0_CNTL_DEFAULT 0x20200000 |
14837 | #define ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_CL1_CNTL_DEFAULT 0x20200000 |
14838 | #define ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_CL2_CNTL_DEFAULT 0x20200000 |
14839 | #define ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_CL3_CNTL_DEFAULT 0x20200000 |
14840 | #define ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_CL4_CNTL_DEFAULT 0x20200000 |
14841 | #define ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK_DEFAULT 0x00000080 |
14842 | #define ixSYSHUB_MMREG_IND_NIC400_0_ASIB_0_FN_MOD_DEFAULT 0x00000000 |
14843 | #define ixSYSHUB_MMREG_IND_NIC400_0_AMIB_0_FN_MOD_BM_ISS_DEFAULT 0x00000000 |
14844 | #define ixSYSHUB_MMREG_IND_NIC400_0_AMIB_1_FN_MOD_BM_ISS_DEFAULT 0x00000000 |
14845 | #define ixSYSHUB_MMREG_IND_NIC400_1_ASIB_0_FN_MOD_DEFAULT 0x00000000 |
14846 | #define ixSYSHUB_MMREG_IND_NIC400_1_AMIB_0_FN_MOD_DEFAULT 0x00000000 |
14847 | #define ixSYSHUB_MMREG_IND_NIC400_1_AMIB_1_FN_MOD_DEFAULT 0x00000000 |
14848 | #define ixSYSHUB_MMREG_IND_NIC400_1_AMIB_2_FN_MOD_DEFAULT 0x00000000 |
14849 | #define ixSYSHUB_MMREG_IND_NIC400_2_ASIB_0_FN_MOD_DEFAULT 0x00000000 |
14850 | #define ixSYSHUB_MMREG_IND_NIC400_2_ASIB_1_FN_MOD_DEFAULT 0x00000000 |
14851 | #define ixSYSHUB_MMREG_IND_NIC400_2_ASIB_2_FN_MOD_DEFAULT 0x00000000 |
14852 | #define ixSYSHUB_MMREG_IND_NIC400_2_ASIB_3_FN_MOD_DEFAULT 0x00000000 |
14853 | #define ixSYSHUB_MMREG_IND_NIC400_2_ASIB_4_FN_MOD_DEFAULT 0x00000000 |
14854 | #define ixSYSHUB_MMREG_IND_NIC400_2_AMIB_0_FN_MOD_BM_ISS_DEFAULT 0x00000000 |
14855 | #define ixSYSHUB_MMREG_IND_NIC400_5_ASIB_0_FN_MOD_DEFAULT 0x00000000 |
14856 | #define ixSYSHUB_MMREG_IND_NIC400_5_ASIB_1_FN_MOD_DEFAULT 0x00000000 |
14857 | #define ixSYSHUB_MMREG_IND_NIC400_5_ASIB_2_FN_MOD_DEFAULT 0x00000000 |
14858 | #define ixSYSHUB_MMREG_IND_NIC400_5_ASIB_3_FN_MOD_DEFAULT 0x00000000 |
14859 | #define ixSYSHUB_MMREG_IND_NIC400_5_ASIB_4_FN_MOD_DEFAULT 0x00000000 |
14860 | #define ixSYSHUB_MMREG_IND_NIC400_5_AMIB_0_FN_MOD_DEFAULT 0x00000000 |
14861 | #define ixSYSHUB_MMREG_IND_NIC400_4_ASIB_0_FN_MOD_DEFAULT 0x00000000 |
14862 | #define ixSYSHUB_MMREG_IND_NIC400_4_ASIB_1_FN_MOD_DEFAULT 0x00000000 |
14863 | #define ixSYSHUB_MMREG_IND_NIC400_4_AMIB_0_FN_MOD_DEFAULT 0x00000000 |
14864 | |
14865 | #endif |
14866 | |